/*
 ***********************************************************************************************************************
 *
 *  Copyright (c) 2014-2021 Advanced Micro Devices, Inc. All Rights Reserved.
 *
 *  Permission is hereby granted, free of charge, to any person obtaining a copy
 *  of this software and associated documentation files (the "Software"), to deal
 *  in the Software without restriction, including without limitation the rights
 *  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 *  copies of the Software, and to permit persons to whom the Software is
 *  furnished to do so, subject to the following conditions:
 *
 *  The above copyright notice and this permission notice shall be included in all
 *  copies or substantial portions of the Software.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 *  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 *  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 *  SOFTWARE.
 *
 **********************************************************************************************************************/

#if !defined (__SI__CI__VI_MERGED_REG_HEADER)
#define __SI__CI__VI_MERGED_REG_HEADER

// Make sure the necessary endian defines are there.
#if defined(LITTLEENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif

namespace Pal
{
namespace Gfx6
{
inline namespace Chip
{

	union ABM_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int             ABM_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ABM_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int            ABM_TEST_DEBUG_INDEX : 8;
                unsigned int         ABM_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ACP_CONFIG__CI {
	struct {
		unsigned int                                 : 8;
		unsigned int                   ACP_RDREQ_URG : 4;
		unsigned int                                 : 4;
		unsigned int                    ACP_REQ_TRAN : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ADAPTER_ID {
	struct {
		unsigned int             SUBSYSTEM_VENDOR_ID : 16;
		unsigned int                    SUBSYSTEM_ID : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ADAPTER_ID_W {
	struct {
		unsigned int             SUBSYSTEM_VENDOR_ID : 16;
		unsigned int                    SUBSYSTEM_ID : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_60958_0__SI__VI {
	struct {
                unsigned int                 AFMT_60958_CS_A : 1;
                unsigned int                 AFMT_60958_CS_B : 1;
                unsigned int                 AFMT_60958_CS_C : 1;
                unsigned int                 AFMT_60958_CS_D : 3;
                unsigned int              AFMT_60958_CS_MODE : 2;
                unsigned int     AFMT_60958_CS_CATEGORY_CODE : 8;
                unsigned int     AFMT_60958_CS_SOURCE_NUMBER : 4;
                unsigned int  AFMT_60958_CS_CHANNEL_NUMBER_L : 4;
                unsigned int AFMT_60958_CS_SAMPLING_FREQUENCY : 4;
                unsigned int    AFMT_60958_CS_CLOCK_ACCURACY : 2;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_60958_1__SI__VI {
	struct {
                unsigned int       AFMT_60958_CS_WORD_LENGTH : 4;
                unsigned int AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY : 4;
                unsigned int                                 : 8;
                unsigned int              AFMT_60958_VALID_L : 1;
                unsigned int                                 : 1;
                unsigned int              AFMT_60958_VALID_R : 1;
                unsigned int                                 : 1;
                unsigned int  AFMT_60958_CS_CHANNEL_NUMBER_R : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_60958_2__SI__VI {
	struct {
                unsigned int  AFMT_60958_CS_CHANNEL_NUMBER_2 : 4;
                unsigned int  AFMT_60958_CS_CHANNEL_NUMBER_3 : 4;
                unsigned int  AFMT_60958_CS_CHANNEL_NUMBER_4 : 4;
                unsigned int  AFMT_60958_CS_CHANNEL_NUMBER_5 : 4;
                unsigned int  AFMT_60958_CS_CHANNEL_NUMBER_6 : 4;
                unsigned int  AFMT_60958_CS_CHANNEL_NUMBER_7 : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AUDIO_CRC_CONTROL__SI__VI {
	struct {
                unsigned int               AFMT_AUDIO_CRC_EN : 1;
                unsigned int                                 : 3;
                unsigned int             AFMT_AUDIO_CRC_CONT : 1;
                unsigned int                                 : 3;
                unsigned int           AFMT_AUDIO_CRC_SOURCE : 1;
                unsigned int                                 : 3;
                unsigned int           AFMT_AUDIO_CRC_CH_SEL : 4;
                unsigned int            AFMT_AUDIO_CRC_COUNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AUDIO_CRC_RESULT__SI__VI {
	struct {
                unsigned int             AFMT_AUDIO_CRC_DONE : 1;
                unsigned int                                 : 7;
                unsigned int                  AFMT_AUDIO_CRC : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AUDIO_INFO0__SI__VI {
	struct {
                unsigned int        AFMT_AUDIO_INFO_CHECKSUM : 8;
                unsigned int              AFMT_AUDIO_INFO_CC : 3;
                unsigned int              AFMT_AUDIO_INFO_CT : 4;
                unsigned int                                 : 1;
                unsigned int AFMT_AUDIO_INFO_CHECKSUM_OFFSET : 8;
                unsigned int             AFMT_AUDIO_INFO_CXT : 5;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AUDIO_INFO1__SI__VI {
	struct {
                unsigned int              AFMT_AUDIO_INFO_CA : 8;
                unsigned int                                 : 3;
                unsigned int             AFMT_AUDIO_INFO_LSV : 4;
                unsigned int          AFMT_AUDIO_INFO_DM_INH : 1;
                unsigned int          AFMT_AUDIO_INFO_LFEPBL : 2;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AUDIO_PACKET_CONTROL2__SI {
	struct {
		unsigned int          AFMT_AUDIO_LAYOUT_OVRD : 1;
		unsigned int        AFMT_AUDIO_LAYOUT_SELECT : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int       AFMT_AUDIO_CHANNEL_ENABLE : 8;
		unsigned int         AFMT_DP_AUDIO_STREAM_ID : 8;
		unsigned int            AFMT_HBR_ENABLE_OVRD : 1;
		unsigned int                                 : 3;
		unsigned int             AFMT_60958_OSF_OVRD : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AUDIO_PACKET_CONTROL2__VI {
	struct {
		unsigned int          AFMT_AUDIO_LAYOUT_OVRD : 1;
		unsigned int        AFMT_AUDIO_LAYOUT_SELECT : 1;
		unsigned int                                 : 6;
		unsigned int       AFMT_AUDIO_CHANNEL_ENABLE : 8;
		unsigned int         AFMT_DP_AUDIO_STREAM_ID : 8;
		unsigned int            AFMT_HBR_ENABLE_OVRD : 1;
		unsigned int                                 : 3;
		unsigned int             AFMT_60958_OSF_OVRD : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AUDIO_PACKET_CONTROL__SI {
	struct {
		unsigned int          AFMT_AUDIO_SAMPLE_SEND : 1;
		unsigned int                                 : 10;
		unsigned int  AFMT_RESET_FIFO_WHEN_AUDIO_DIS : 1;
		unsigned int              AFMT_AUDIO_TEST_EN : 1;
		unsigned int                                 : 1;
		unsigned int            AFMT_AUDIO_TEST_MODE : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int    AFMT_AUDIO_FIFO_OVERFLOW_ACK : 1;
		unsigned int         AFMT_AUDIO_CHANNEL_SWAP : 1;
		unsigned int                                 : 1;
		unsigned int            AFMT_60958_CS_UPDATE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int    AFMT_AZ_AUDIO_ENABLE_CHG_ACK : 1;
		unsigned int AFMT_BLANK_TEST_DATA_ON_ENC_ENB : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AUDIO_PACKET_CONTROL__VI {
	struct {
		unsigned int          AFMT_AUDIO_SAMPLE_SEND : 1;
		unsigned int                                 : 10;
		unsigned int  AFMT_RESET_FIFO_WHEN_AUDIO_DIS : 1;
		unsigned int              AFMT_AUDIO_TEST_EN : 1;
		unsigned int                                 : 1;
		unsigned int            AFMT_AUDIO_TEST_MODE : 1;
		unsigned int                                 : 8;
		unsigned int    AFMT_AUDIO_FIFO_OVERFLOW_ACK : 1;
		unsigned int         AFMT_AUDIO_CHANNEL_SWAP : 1;
		unsigned int                                 : 1;
		unsigned int            AFMT_60958_CS_UPDATE : 1;
		unsigned int                                 : 3;
		unsigned int    AFMT_AZ_AUDIO_ENABLE_CHG_ACK : 1;
		unsigned int AFMT_BLANK_TEST_DATA_ON_ENC_ENB : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AVI_INFO0__SI__VI {
	struct {
                unsigned int          AFMT_AVI_INFO_CHECKSUM : 8;
                unsigned int                 AFMT_AVI_INFO_S : 2;
                unsigned int                 AFMT_AVI_INFO_B : 2;
                unsigned int                 AFMT_AVI_INFO_A : 1;
                unsigned int                 AFMT_AVI_INFO_Y : 2;
                unsigned int          AFMT_AVI_INFO_PB1_RSVD : 1;
                unsigned int                 AFMT_AVI_INFO_R : 4;
                unsigned int                 AFMT_AVI_INFO_M : 2;
                unsigned int                 AFMT_AVI_INFO_C : 2;
                unsigned int                AFMT_AVI_INFO_SC : 2;
                unsigned int                 AFMT_AVI_INFO_Q : 2;
                unsigned int                AFMT_AVI_INFO_EC : 3;
                unsigned int               AFMT_AVI_INFO_ITC : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AVI_INFO1__SI__VI {
	struct {
                unsigned int               AFMT_AVI_INFO_VIC : 7;
                unsigned int          AFMT_AVI_INFO_PB4_RSVD : 1;
                unsigned int                AFMT_AVI_INFO_PR : 4;
                unsigned int                AFMT_AVI_INFO_CN : 2;
                unsigned int                AFMT_AVI_INFO_YQ : 2;
                unsigned int               AFMT_AVI_INFO_TOP : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AVI_INFO2__SI__VI {
	struct {
                unsigned int            AFMT_AVI_INFO_BOTTOM : 16;
                unsigned int              AFMT_AVI_INFO_LEFT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AVI_INFO3__SI__VI {
	struct {
                unsigned int             AFMT_AVI_INFO_RIGHT : 16;
                unsigned int                                 : 8;
                unsigned int           AFMT_AVI_INFO_VERSION : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_INFOFRAME_CONTROL0__SI__VI {
	struct {
                unsigned int                                 : 6;
                unsigned int          AFMT_AUDIO_INFO_SOURCE : 1;
                unsigned int          AFMT_AUDIO_INFO_UPDATE : 1;
                unsigned int                                 : 2;
                unsigned int           AFMT_MPEG_INFO_UPDATE : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_ISRC1_0__SI__VI {
	struct {
                unsigned int                AFMT_ISRC_STATUS : 3;
                unsigned int                                 : 3;
                unsigned int              AFMT_ISRC_CONTINUE : 1;
                unsigned int                 AFMT_ISRC_VALID : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_ISRC1_1__SI__VI {
	struct {
                unsigned int              AFMT_UPC_EAN_ISRC0 : 8;
                unsigned int              AFMT_UPC_EAN_ISRC1 : 8;
                unsigned int              AFMT_UPC_EAN_ISRC2 : 8;
                unsigned int              AFMT_UPC_EAN_ISRC3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_ISRC1_2__SI__VI {
	struct {
                unsigned int              AFMT_UPC_EAN_ISRC4 : 8;
                unsigned int              AFMT_UPC_EAN_ISRC5 : 8;
                unsigned int              AFMT_UPC_EAN_ISRC6 : 8;
                unsigned int              AFMT_UPC_EAN_ISRC7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_ISRC1_3__SI__VI {
	struct {
                unsigned int              AFMT_UPC_EAN_ISRC8 : 8;
                unsigned int              AFMT_UPC_EAN_ISRC9 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC10 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_ISRC1_4__SI__VI {
	struct {
                unsigned int             AFMT_UPC_EAN_ISRC12 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC13 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC14 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC15 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_ISRC2_0__SI__VI {
	struct {
                unsigned int             AFMT_UPC_EAN_ISRC16 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC17 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC18 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC19 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_ISRC2_1__SI__VI {
	struct {
                unsigned int             AFMT_UPC_EAN_ISRC20 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC21 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC22 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC23 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_ISRC2_2__SI__VI {
	struct {
                unsigned int             AFMT_UPC_EAN_ISRC24 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC25 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC26 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC27 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_ISRC2_3__SI__VI {
	struct {
                unsigned int             AFMT_UPC_EAN_ISRC28 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC29 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC30 : 8;
                unsigned int             AFMT_UPC_EAN_ISRC31 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_MPEG_INFO0__SI__VI {
	struct {
                unsigned int         AFMT_MPEG_INFO_CHECKSUM : 8;
                unsigned int              AFMT_MPEG_INFO_MB0 : 8;
                unsigned int              AFMT_MPEG_INFO_MB1 : 8;
                unsigned int              AFMT_MPEG_INFO_MB2 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_MPEG_INFO1__SI__VI {
	struct {
                unsigned int              AFMT_MPEG_INFO_MB3 : 8;
                unsigned int               AFMT_MPEG_INFO_MF : 2;
                unsigned int                                 : 2;
                unsigned int               AFMT_MPEG_INFO_FR : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_RAMP_CONTROL0__SI__VI {
	struct {
                unsigned int             AFMT_RAMP_MAX_COUNT : 24;
                unsigned int                                 : 7;
                unsigned int             AFMT_RAMP_DATA_SIGN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_RAMP_CONTROL1__SI__VI {
	struct {
                unsigned int             AFMT_RAMP_MIN_COUNT : 24;
                unsigned int      AFMT_AUDIO_TEST_CH_DISABLE : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_RAMP_CONTROL2__SI__VI {
	struct {
                unsigned int             AFMT_RAMP_INC_COUNT : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_RAMP_CONTROL3__SI__VI {
	struct {
                unsigned int             AFMT_RAMP_DEC_COUNT : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_STATUS__SI {
	struct {
		unsigned int                                 : 4;
		unsigned int               AFMT_AUDIO_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int              AFMT_AZ_HBR_ENABLE : 1;
		unsigned int                                 : 15;
		unsigned int        AFMT_AUDIO_FIFO_OVERFLOW : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int        AFMT_AZ_AUDIO_ENABLE_CHG : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_STATUS__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int               AFMT_AUDIO_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int              AFMT_AZ_HBR_ENABLE : 1;
		unsigned int                                 : 15;
		unsigned int        AFMT_AUDIO_FIFO_OVERFLOW : 1;
		unsigned int                                 : 5;
		unsigned int        AFMT_AZ_AUDIO_ENABLE_CHG : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_VBI_PACKET_CONTROL__SI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int            AFMT_GENERIC0_UPDATE : 1;
                unsigned int        AFMT_GENERIC2_UPDATE__VI : 1;
                unsigned int                                 : 9;
                unsigned int                                 : 1;
                unsigned int                                 : 16;
                unsigned int          AFMT_GENERIC_INDEX__VI : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_CNTL__CI__VI {
	struct {
                unsigned int                     DISABLE_ATC : 1;
                unsigned int                     DISABLE_PRI : 1;
                unsigned int                   DISABLE_PASID : 1;
                unsigned int                                 : 5;
                unsigned int                 CREDITS_ATS_RPB : 6;
                unsigned int                                 : 2;
                unsigned int                       DEBUG_ECO : 4;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_DEBUG__CI__VI {
	struct {
                unsigned int                  INVALIDATE_ALL : 1;
                unsigned int                    IDENT_RETURN : 1;
                unsigned int ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS : 1;
                unsigned int                                 : 2;
                unsigned int PAGE_REQUESTS_USE_RELAXED_ORDERING : 1;
                unsigned int                        PRIV_BIT : 1;
                unsigned int                         EXE_BIT : 1;
                unsigned int              PAGE_REQUEST_PERMS : 1;
                unsigned int UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE : 1;
                unsigned int             NUM_REQUESTS_AT_ERR : 4;
                unsigned int            DISALLOW_ERR_TO_DONE : 1;
                unsigned int                      IGNORE_FED : 1;
                unsigned int INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED : 1;
                unsigned int                DEBUG_BUS_SELECT : 1;
                unsigned int DISABLE_INVALIDATE_PER_DOMAIN__VI : 1;
                unsigned int DISABLE_VMID0_PASID_MAPPING__VI : 1;
                unsigned int DISABLE_INVALIDATION_ON_WORLD_SWITCH__VI : 1;
                unsigned int ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__VI : 1;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_DEFAULT_PAGE_CNTL__CI__VI {
	struct {
                unsigned int               SEND_DEFAULT_PAGE : 1;
                unsigned int                                 : 1;
                unsigned int               DEFAULT_PAGE_HIGH : 4;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_DEFAULT_PAGE_LOW__CI {
	struct {
		unsigned int                    DEFAULT_PAGE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_DEFAULT_PAGE_LOW__VI {
	struct {
		unsigned int                    DEFAULT_PAGE : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_FAULT_CNTL__CI__VI {
	struct {
                unsigned int              FAULT_REGISTER_LOG : 9;
                unsigned int                                 : 1;
                unsigned int           FAULT_INTERRUPT_TABLE : 9;
                unsigned int                                 : 1;
                unsigned int               FAULT_CRASH_TABLE : 9;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_FAULT_DEBUG__CI__VI {
	struct {
                unsigned int                  CREDITS_ATS_IH : 5;
                unsigned int                                 : 3;
                unsigned int ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES : 1;
                unsigned int                                 : 7;
                unsigned int         CLEAR_FAULT_STATUS_ADDR : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_FAULT_STATUS_ADDR__CI__VI {
	struct {
                unsigned int                       PAGE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_FAULT_STATUS_INFO__CI__VI {
	struct {
                unsigned int                      FAULT_TYPE : 9;
                unsigned int                                 : 1;
                unsigned int                            VMID : 5;
                unsigned int                      EXTRA_INFO : 1;
                unsigned int                     EXTRA_INFO2 : 1;
                unsigned int                    INVALIDATION : 1;
                unsigned int                    PAGE_REQUEST : 1;
                unsigned int                          STATUS : 5;
                unsigned int                  PAGE_ADDR_HIGH : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_STATUS__CI__VI {
	struct {
                unsigned int                            BUSY : 1;
                unsigned int                         CRASHED : 1;
                unsigned int              DEADLOCK_DETECTION : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L1RD_DEBUG_TLB__CI__VI {
	struct {
                unsigned int               DISABLE_FRAGMENTS : 1;
                unsigned int DISABLE_INVALIDATE_BY_ADDRESS_RANGE : 1;
                unsigned int                                 : 2;
                unsigned int              EFFECTIVE_CAM_SIZE : 4;
                unsigned int       EFFECTIVE_WORK_QUEUE_SIZE : 3;
                unsigned int                                 : 1;
                unsigned int                   CREDITS_L1_L2 : 6;
                unsigned int                                 : 2;
                unsigned int                  CREDITS_L1_RPB : 8;
                unsigned int                       DEBUG_ECO : 2;
                unsigned int                  INVALIDATE_ALL : 1;
                unsigned int   DISABLE_CACHING_FAULT_RETURNS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L1RD_STATUS__CI__VI {
	struct {
                unsigned int                            BUSY : 1;
                unsigned int              DEADLOCK_DETECTION : 1;
                unsigned int                                 : 6;
                unsigned int                    BAD_NEED_ATS : 1;
                unsigned int                                 : 3;
                unsigned int           CAM_PARITY_ERRORS__VI : 5;
                unsigned int                   CAM_INDEX__VI : 5;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L1WR_DEBUG_TLB__CI__VI {
	struct {
                unsigned int               DISABLE_FRAGMENTS : 1;
                unsigned int DISABLE_INVALIDATE_BY_ADDRESS_RANGE : 1;
                unsigned int                                 : 2;
                unsigned int              EFFECTIVE_CAM_SIZE : 4;
                unsigned int       EFFECTIVE_WORK_QUEUE_SIZE : 3;
                unsigned int                                 : 1;
                unsigned int                   CREDITS_L1_L2 : 6;
                unsigned int                                 : 2;
                unsigned int                  CREDITS_L1_RPB : 8;
                unsigned int                       DEBUG_ECO : 2;
                unsigned int                  INVALIDATE_ALL : 1;
                unsigned int   DISABLE_CACHING_FAULT_RETURNS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L1WR_STATUS__CI__VI {
	struct {
                unsigned int                            BUSY : 1;
                unsigned int              DEADLOCK_DETECTION : 1;
                unsigned int                                 : 6;
                unsigned int                    BAD_NEED_ATS : 1;
                unsigned int                                 : 3;
                unsigned int           CAM_PARITY_ERRORS__VI : 5;
                unsigned int                   CAM_INDEX__VI : 5;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L1_ADDRESS_OFFSET__CI__VI {
	struct {
                unsigned int                 LOGICAL_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L1_CNTL__CI__VI {
	struct {
                unsigned int          DONT_NEED_ATS_BEHAVIOR : 2;
                unsigned int               NEED_ATS_BEHAVIOR : 1;
                unsigned int                                 : 1;
                unsigned int          NEED_ATS_SNOOP_DEFAULT : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_CNTL2__CI__VI {
	struct {
                unsigned int                     BANK_SELECT : 6;
                unsigned int            L2_CACHE_UPDATE_MODE : 2;
                unsigned int ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE : 1;
                unsigned int    L2_CACHE_SWAP_TAG_INDEX_LSBS : 3;
                unsigned int              L2_CACHE_VMID_MODE : 3;
                unsigned int L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE : 6;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_CNTL__CI__VI {
	struct {
                unsigned int NUMBER_OF_TRANSLATION_READ_REQUESTS : 2;
                unsigned int                                 : 2;
                unsigned int NUMBER_OF_TRANSLATION_WRITE_REQUESTS : 2;
                unsigned int                                 : 2;
                unsigned int NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD : 1;
                unsigned int NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD : 1;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_DEBUG2__CI {
	struct {
		unsigned int            EFFECTIVE_CACHE_SIZE : 5;
		unsigned int       EFFECTIVE_WORK_QUEUE_SIZE : 3;
		unsigned int                FORCE_CACHE_MISS : 1;
		unsigned int                  INVALIDATE_ALL : 1;
		unsigned int   DISABLE_INVALIDATE_PER_DOMAIN : 1;
		unsigned int DISABLE_CACHING_SPECULATIVE_READ_RETURNS : 1;
		unsigned int DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS : 1;
		unsigned int                                 : 1;
		unsigned int   DISABLE_CACHING_FAULT_RETURNS : 1;
		unsigned int                DEBUG_BUS_SELECT : 2;
		unsigned int                       DEBUG_ECO : 2;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_DEBUG2__VI {
	struct {
		unsigned int            EFFECTIVE_CACHE_SIZE : 5;
		unsigned int       EFFECTIVE_WORK_QUEUE_SIZE : 3;
		unsigned int                FORCE_CACHE_MISS : 1;
		unsigned int                  INVALIDATE_ALL : 1;
		unsigned int                DISABLE_2M_CACHE : 1;
		unsigned int DISABLE_CACHING_SPECULATIVE_RETURNS : 1;
		unsigned int                                 : 2;
		unsigned int   DISABLE_CACHING_FAULT_RETURNS : 1;
		unsigned int                DEBUG_BUS_SELECT : 2;
		unsigned int                       DEBUG_ECO : 2;
		unsigned int         EFFECTIVE_2M_CACHE_SIZE : 4;
		unsigned int CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD : 8;
		unsigned int         CLEAR_PARITY_ERROR_INFO : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_DEBUG__CI__VI {
	struct {
                unsigned int                  CREDITS_L2_ATS : 6;
                unsigned int                                 : 1;
                unsigned int               L2_MEM_SELECT__VI : 1;
                unsigned int                 CACHE_INDEX__VI : 12;
                unsigned int                                 : 4;
                unsigned int                CACHE_SELECT__VI : 1;
                unsigned int           CACHE_BANK_SELECT__VI : 1;
                unsigned int                                 : 1;
                unsigned int            CACHE_WAY_SELECT__VI : 1;
                unsigned int                                 : 1;
                unsigned int                  CACHE_READ__VI : 1;
                unsigned int CACHE_INJECT_SOFT_PARITY_ERROR__VI : 1;
                unsigned int CACHE_INJECT_HARD_PARITY_ERROR__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_MISC_CG__CI__VI {
	struct {
                unsigned int                                 : 6;
                unsigned int                          OFFDLY : 6;
                unsigned int                                 : 6;
                unsigned int                          ENABLE : 1;
                unsigned int                   MEM_LS_ENABLE : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_PERFCOUNTER0_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_PERFCOUNTER1_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_PERFCOUNTER2_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_PERFCOUNTER3_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                      COUNTER_HI : 16;
                unsigned int                   COMPARE_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                      COUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_PERFCOUNTER_RSLT_CNTL__CI__VI {
	struct {
                unsigned int             PERF_COUNTER_SELECT : 4;
                unsigned int                                 : 4;
                unsigned int                   START_TRIGGER : 8;
                unsigned int                    STOP_TRIGGER : 8;
                unsigned int                      ENABLE_ANY : 1;
                unsigned int                       CLEAR_ALL : 1;
                unsigned int            STOP_ALL_ON_SATURATE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID0_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID10_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID11_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID12_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID13_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID14_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID15_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID1_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID2_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID3_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID4_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID5_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID6_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID7_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID8_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID9_PASID_MAPPING__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 14;
                unsigned int             NO_INVALIDATION__VI : 1;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VMID_PASID_MAPPING_UPDATE_STATUS__CI__VI {
	struct {
                unsigned int        VMID0_REMAPPING_FINISHED : 1;
                unsigned int        VMID1_REMAPPING_FINISHED : 1;
                unsigned int        VMID2_REMAPPING_FINISHED : 1;
                unsigned int        VMID3_REMAPPING_FINISHED : 1;
                unsigned int        VMID4_REMAPPING_FINISHED : 1;
                unsigned int        VMID5_REMAPPING_FINISHED : 1;
                unsigned int        VMID6_REMAPPING_FINISHED : 1;
                unsigned int        VMID7_REMAPPING_FINISHED : 1;
                unsigned int        VMID8_REMAPPING_FINISHED : 1;
                unsigned int        VMID9_REMAPPING_FINISHED : 1;
                unsigned int       VMID10_REMAPPING_FINISHED : 1;
                unsigned int       VMID11_REMAPPING_FINISHED : 1;
                unsigned int       VMID12_REMAPPING_FINISHED : 1;
                unsigned int       VMID13_REMAPPING_FINISHED : 1;
                unsigned int       VMID14_REMAPPING_FINISHED : 1;
                unsigned int       VMID15_REMAPPING_FINISHED : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VM_APERTURE0_CNTL2__CI__VI {
	struct {
                unsigned int               VMIDS_USING_RANGE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VM_APERTURE0_CNTL__CI__VI {
	struct {
                unsigned int                 ATS_ACCESS_MODE : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VM_APERTURE0_HIGH_ADDR__CI__VI {
	struct {
                unsigned int             VIRTUAL_PAGE_NUMBER : 28;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VM_APERTURE0_LOW_ADDR__CI__VI {
	struct {
                unsigned int             VIRTUAL_PAGE_NUMBER : 28;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VM_APERTURE1_CNTL2__CI__VI {
	struct {
                unsigned int               VMIDS_USING_RANGE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VM_APERTURE1_CNTL__CI__VI {
	struct {
                unsigned int                 ATS_ACCESS_MODE : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VM_APERTURE1_HIGH_ADDR__CI__VI {
	struct {
                unsigned int             VIRTUAL_PAGE_NUMBER : 28;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_VM_APERTURE1_LOW_ADDR__CI__VI {
	struct {
                unsigned int             VIRTUAL_PAGE_NUMBER : 28;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR00__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR01__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR02__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR03__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR04__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR05__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR06__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR07__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR08__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR09__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR0A__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR0B__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR0C__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR0D__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR0E__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR0F__SI__VI {
	struct {
                unsigned int                        ATTR_PAL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR10__SI__VI {
	struct {
                unsigned int                  ATTR_GRPH_MODE : 1;
                unsigned int                    ATTR_MONO_EN : 1;
                unsigned int                   ATTR_LGRPH_EN : 1;
                unsigned int                   ATTR_BLINK_EN : 1;
                unsigned int                                 : 1;
                unsigned int                 ATTR_PANTOPONLY : 1;
                unsigned int                    ATTR_PCLKBY2 : 1;
                unsigned int                    ATTR_CSEL_EN : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR11__SI__VI {
	struct {
                unsigned int                       ATTR_OVSC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR12__SI__VI {
	struct {
                unsigned int                     ATTR_MAP_EN : 4;
                unsigned int                      ATTR_VSMUX : 2;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR13__SI__VI {
	struct {
                unsigned int                       ATTR_PPAN : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTR14__SI__VI {
	struct {
                unsigned int                      ATTR_CSEL1 : 2;
                unsigned int                      ATTR_CSEL2 : 2;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTRDR__SI__VI {
	struct {
                unsigned int                       ATTR_DATA : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTRDW__SI__VI {
	struct {
                unsigned int                       ATTR_DATA : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATTRX__SI__VI {
	struct {
                unsigned int                        ATTR_IDX : 5;
                unsigned int                 ATTR_PAL_RW_ENB : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR0__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR10__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR11__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR12__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR13__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR1__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR2__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR3__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR4__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR5__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR6__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR7__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR8__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUDIO_DESCRIPTOR9__SI__VI {
	struct {
                unsigned int                    MAX_CHANNELS : 3;
                unsigned int                                 : 5;
                unsigned int           SUPPORTED_FREQUENCIES : 8;
                unsigned int               DESCRIPTOR_BYTE_2 : 8;
                unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUXN_IMPCAL__SI {
	struct {
		unsigned int              AUXN_IMPCAL_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int              AUXN_IMPCAL_CALOUT : 1;
		unsigned int               AUXN_CALOUT_ERROR : 1;
		unsigned int            AUXN_CALOUT_ERROR_AK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int               AUXN_IMPCAL_VALUE : 4;
		unsigned int          AUXN_IMPCAL_STEP_DELAY : 4;
		unsigned int            AUXN_IMPCAL_OVERRIDE : 4;
		unsigned int     AUXN_IMPCAL_OVERRIDE_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUXN_IMPCAL__VI {
	struct {
		unsigned int              AUXN_IMPCAL_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int              AUXN_IMPCAL_CALOUT : 1;
		unsigned int               AUXN_CALOUT_ERROR : 1;
		unsigned int            AUXN_CALOUT_ERROR_AK : 1;
		unsigned int                                 : 5;
		unsigned int               AUXN_IMPCAL_VALUE : 4;
		unsigned int          AUXN_IMPCAL_STEP_DELAY : 4;
		unsigned int            AUXN_IMPCAL_OVERRIDE : 4;
		unsigned int     AUXN_IMPCAL_OVERRIDE_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUXP_IMPCAL__SI {
	struct {
		unsigned int              AUXP_IMPCAL_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int              AUXP_IMPCAL_CALOUT : 1;
		unsigned int               AUXP_CALOUT_ERROR : 1;
		unsigned int            AUXP_CALOUT_ERROR_AK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int               AUXP_IMPCAL_VALUE : 4;
		unsigned int          AUXP_IMPCAL_STEP_DELAY : 4;
		unsigned int            AUXP_IMPCAL_OVERRIDE : 4;
		unsigned int     AUXP_IMPCAL_OVERRIDE_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUXP_IMPCAL__VI {
	struct {
		unsigned int              AUXP_IMPCAL_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int              AUXP_IMPCAL_CALOUT : 1;
		unsigned int               AUXP_CALOUT_ERROR : 1;
		unsigned int            AUXP_CALOUT_ERROR_AK : 1;
		unsigned int                                 : 5;
		unsigned int               AUXP_IMPCAL_VALUE : 4;
		unsigned int          AUXP_IMPCAL_STEP_DELAY : 4;
		unsigned int            AUXP_IMPCAL_OVERRIDE : 4;
		unsigned int     AUXP_IMPCAL_OVERRIDE_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_ARB_CONTROL__SI__VI {
	struct {
                unsigned int                AUX_ARB_PRIORITY : 2;
                unsigned int          AUX_REG_RW_CNTL_STATUS : 2;
                unsigned int                                 : 4;
                unsigned int             AUX_NO_QUEUED_SW_GO : 1;
                unsigned int                                 : 1;
                unsigned int             AUX_NO_QUEUED_LS_GO : 1;
                unsigned int                                 : 5;
                unsigned int          AUX_SW_USE_AUX_REG_REQ : 1;
                unsigned int       AUX_SW_DONE_USING_AUX_REG : 1;
                unsigned int                                 : 6;
                unsigned int        AUX_DMCU_USE_AUX_REG_REQ : 1;
                unsigned int     AUX_DMCU_DONE_USING_AUX_REG : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_CONTROL__SI__VI {
	struct {
                unsigned int                          AUX_EN : 1;
                unsigned int                                 : 7;
                unsigned int                  AUX_LS_READ_EN : 1;
                unsigned int                                 : 3;
                unsigned int           AUX_LS_UPDATE_DISABLE : 1;
                unsigned int                                 : 3;
                unsigned int           AUX_IGNORE_HPD_DISCON : 1;
                unsigned int                                 : 1;
                unsigned int                 AUX_MODE_DET_EN : 1;
                unsigned int                                 : 1;
                unsigned int                     AUX_HPD_SEL : 3;
                unsigned int                                 : 1;
                unsigned int               AUX_IMPCAL_REQ_EN : 1;
                unsigned int                                 : 3;
                unsigned int                   AUX_TEST_MODE : 1;
                unsigned int                 AUX_DEGLITCH_EN : 1;
                unsigned int                         SPARE_0 : 1;
                unsigned int                         SPARE_1 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_DPHY_RX_CONTROL0__SI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int             AUX_RX_START_WINDOW : 3;
                unsigned int                                 : 1;
                unsigned int           AUX_RX_RECEIVE_WINDOW : 3;
                unsigned int                                 : 1;
                unsigned int      AUX_RX_HALF_SYM_DETECT_LEN : 2;
                unsigned int                                 : 2;
                unsigned int     AUX_RX_TRANSITION_FILTER_EN : 1;
                unsigned int AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT : 1;
                unsigned int AUX_RX_ALLOW_BELOW_THRESHOLD_START : 1;
                unsigned int AUX_RX_ALLOW_BELOW_THRESHOLD_STOP : 1;
                unsigned int         AUX_RX_PHASE_DETECT_LEN : 2;
                unsigned int                                 : 2;
                unsigned int              AUX_RX_TIMEOUT_LEN : 3;
                unsigned int                                 : 1;
                unsigned int      AUX_RX_DETECTION_THRESHOLD : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_DPHY_RX_CONTROL1__SI__VI {
	struct {
                unsigned int           AUX_RX_PRECHARGE_SKIP : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_DPHY_RX_STATUS__SI__VI {
	struct {
                unsigned int                    AUX_RX_STATE : 3;
                unsigned int                                 : 5;
                unsigned int         AUX_RX_SYNC_VALID_COUNT : 5;
                unsigned int                                 : 3;
                unsigned int    AUX_RX_HALF_SYM_PERIOD_FRACT : 5;
                unsigned int          AUX_RX_HALF_SYM_PERIOD : 9;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_DPHY_TX_CONTROL__SI__VI {
	struct {
                unsigned int            AUX_TX_PRECHARGE_LEN : 3;
                unsigned int                                 : 5;
                unsigned int        AUX_TX_PRECHARGE_SYMBOLS : 6;
                unsigned int                                 : 2;
                unsigned int    AUX_MODE_DET_CHECK_DELAY__VI : 3;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_DPHY_TX_REF_CONTROL__SI__VI {
	struct {
                unsigned int                  AUX_TX_REF_SEL : 1;
                unsigned int                                 : 3;
                unsigned int                     AUX_TX_RATE : 2;
                unsigned int                                 : 10;
                unsigned int                  AUX_TX_REF_DIV : 9;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_DPHY_TX_STATUS__SI__VI {
	struct {
                unsigned int                   AUX_TX_ACTIVE : 1;
                unsigned int                                 : 3;
                unsigned int                    AUX_TX_STATE : 3;
                unsigned int                                 : 9;
                unsigned int          AUX_TX_HALF_SYM_PERIOD : 9;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_INTERRUPT_CONTROL__SI__VI {
	struct {
                unsigned int                 AUX_SW_DONE_INT : 1;
                unsigned int                 AUX_SW_DONE_ACK : 1;
                unsigned int                AUX_SW_DONE_MASK : 1;
                unsigned int                                 : 1;
                unsigned int                 AUX_LS_DONE_INT : 1;
                unsigned int                 AUX_LS_DONE_ACK : 1;
                unsigned int                AUX_LS_DONE_MASK : 1;
                unsigned int                                 : 1;
                unsigned int  AUX_GTC_SYNC_LOCK_DONE_INT__VI : 1;
                unsigned int  AUX_GTC_SYNC_LOCK_DONE_ACK__VI : 1;
                unsigned int AUX_GTC_SYNC_LOCK_DONE_INT_MASK__VI : 1;
                unsigned int                                 : 1;
                unsigned int      AUX_GTC_SYNC_ERROR_INT__VI : 1;
                unsigned int      AUX_GTC_SYNC_ERROR_ACK__VI : 1;
                unsigned int AUX_GTC_SYNC_ERROR_INT_MASK__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_LS_DATA__SI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int                     AUX_LS_DATA : 8;
                unsigned int                    AUX_LS_INDEX : 5;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_LS_STATUS__SI__VI {
	struct {
                unsigned int                     AUX_LS_DONE : 1;
                unsigned int                      AUX_LS_REQ : 1;
                unsigned int                                 : 2;
                unsigned int         AUX_LS_RX_TIMEOUT_STATE : 3;
                unsigned int               AUX_LS_RX_TIMEOUT : 1;
                unsigned int              AUX_LS_RX_OVERFLOW : 1;
                unsigned int               AUX_LS_HPD_DISCON : 1;
                unsigned int          AUX_LS_RX_PARTIAL_BYTE : 1;
                unsigned int             AUX_LS_NON_AUX_MODE : 1;
                unsigned int        AUX_LS_RX_MIN_COUNT_VIOL : 1;
                unsigned int                                 : 1;
                unsigned int          AUX_LS_RX_INVALID_STOP : 1;
                unsigned int                                 : 2;
                unsigned int        AUX_LS_RX_SYNC_INVALID_L : 1;
                unsigned int        AUX_LS_RX_SYNC_INVALID_H : 1;
                unsigned int         AUX_LS_RX_INVALID_START : 1;
                unsigned int           AUX_LS_RX_RECV_NO_DET : 1;
                unsigned int                                 : 1;
                unsigned int        AUX_LS_RX_RECV_INVALID_H : 1;
                unsigned int        AUX_LS_RX_RECV_INVALID_L : 1;
                unsigned int         AUX_LS_REPLY_BYTE_COUNT : 5;
                unsigned int                   AUX_LS_CP_IRQ : 1;
                unsigned int                  AUX_LS_UPDATED : 1;
                unsigned int              AUX_LS_UPDATED_ACK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_SW_CONTROL__SI__VI {
	struct {
                unsigned int                       AUX_SW_GO : 1;
                unsigned int                                 : 1;
                unsigned int                AUX_LS_READ_TRIG : 1;
                unsigned int                                 : 1;
                unsigned int              AUX_SW_START_DELAY : 4;
                unsigned int                                 : 8;
                unsigned int                 AUX_SW_WR_BYTES : 5;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_SW_DATA__SI__VI {
	struct {
                unsigned int                  AUX_SW_DATA_RW : 1;
                unsigned int                                 : 7;
                unsigned int                     AUX_SW_DATA : 8;
                unsigned int                    AUX_SW_INDEX : 5;
                unsigned int                                 : 10;
                unsigned int    AUX_SW_AUTOINCREMENT_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_SW_STATUS__SI__VI {
	struct {
                unsigned int                     AUX_SW_DONE : 1;
                unsigned int                      AUX_SW_REQ : 1;
                unsigned int                                 : 2;
                unsigned int         AUX_SW_RX_TIMEOUT_STATE : 3;
                unsigned int               AUX_SW_RX_TIMEOUT : 1;
                unsigned int              AUX_SW_RX_OVERFLOW : 1;
                unsigned int               AUX_SW_HPD_DISCON : 1;
                unsigned int          AUX_SW_RX_PARTIAL_BYTE : 1;
                unsigned int             AUX_SW_NON_AUX_MODE : 1;
                unsigned int        AUX_SW_RX_MIN_COUNT_VIOL : 1;
                unsigned int                                 : 1;
                unsigned int          AUX_SW_RX_INVALID_STOP : 1;
                unsigned int                                 : 2;
                unsigned int        AUX_SW_RX_SYNC_INVALID_L : 1;
                unsigned int        AUX_SW_RX_SYNC_INVALID_H : 1;
                unsigned int         AUX_SW_RX_INVALID_START : 1;
                unsigned int           AUX_SW_RX_RECV_NO_DET : 1;
                unsigned int                                 : 1;
                unsigned int        AUX_SW_RX_RECV_INVALID_H : 1;
                unsigned int        AUX_SW_RX_RECV_INVALID_L : 1;
                unsigned int         AUX_SW_REPLY_BYTE_COUNT : 5;
                unsigned int                                 : 1;
                unsigned int                  AUX_ARB_STATUS : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__SI__VI {
	struct {
                unsigned int APPLICATION_POSITION_IN_CYCLIC_BUFFER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_AUDIO_DTO_CONTROL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int          AZALIA_AUDIO_FORCE_DTO : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_AUDIO_DTO_CONTROL__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int          AZALIA_AUDIO_FORCE_DTO : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_AUDIO_DTO__SI__VI {
	struct {
                unsigned int          AZALIA_AUDIO_DTO_PHASE : 16;
                unsigned int         AZALIA_AUDIO_DTO_MODULE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_BDL_DMA_CONTROL__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_BDL_DMA_CONTROL__VI {
	struct {
		unsigned int               BDL_DMA_NON_SNOOP : 2;
		unsigned int         INPUT_BDL_DMA_NON_SNOOP : 2;
		unsigned int             BDL_DMA_ISOCHRONOUS : 2;
		unsigned int       INPUT_BDL_DMA_ISOCHRONOUS : 2;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CORB_DMA_CONTROL__SI__VI {
	struct {
                unsigned int              CORB_DMA_NON_SNOOP : 1;
                unsigned int                                 : 3;
                unsigned int            CORB_DMA_ISOCHRONOUS : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CUMULATIVE_LATENCY_COUNT__SI__VI {
	struct {
                unsigned int AZALIA_CUMULATIVE_LATENCY_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CUMULATIVE_REQUEST_COUNT__SI__VI {
	struct {
                unsigned int AZALIA_CUMULATIVE_REQUEST_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CYCLIC_BUFFER_SYNC__SI__VI {
	struct {
                unsigned int       CYCLIC_BUFFER_SYNC_ENABLE : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_DATA_DMA_CONTROL__SI__VI {
	struct {
                unsigned int              DATA_DMA_NON_SNOOP : 2;
                unsigned int    INPUT_DATA_DMA_NON_SNOOP__VI : 2;
                unsigned int            DATA_DMA_ISOCHRONOUS : 2;
                unsigned int  INPUT_DATA_DMA_ISOCHRONOUS__VI : 2;
                unsigned int                                 : 6;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int    AZALIA_IOC_GENERATION_METHOD : 1;
                unsigned int        AZALIA_UNDERFLOW_CONTROL : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_DEBUG__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__SI {
	struct {
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI {
	struct {
		unsigned int                      CHANNEL_ID : 4;
		unsigned int                       STREAM_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__SI__VI {
	struct {
                unsigned int                 POWER_STATE_SET : 4;
                unsigned int                 POWER_STATE_ACT : 4;
                unsigned int                                 : 1;
                unsigned int                   CLKSTOPOK__VI : 1;
                unsigned int  POWER_STATE_SETTINGS_RESET__VI : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__SI__VI {
	struct {
                unsigned int                     CODEC_RESET : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI__VI {
	struct {
                unsigned int              SUBSYSTEM_ID_BYTE0 : 8;
                unsigned int              SUBSYSTEM_ID_BYTE1 : 8;
                unsigned int              SUBSYSTEM_ID_BYTE2 : 8;
                unsigned int              SUBSYSTEM_ID_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI__VI {
	struct {
                unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI {
	struct {
		unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__VI {
	struct {
		unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES : 30;
		unsigned int                         CLKSTOP : 1;
		unsigned int                            EPSS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI__VI {
	struct {
                unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI__VI {
	struct {
                unsigned int         AUDIO_RATE_CAPABILITIES : 12;
                unsigned int                                 : 4;
                unsigned int          AUDIO_BIT_CAPABILITIES : 5;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__SI {
	struct {
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__VI {
	struct {
		unsigned int                             TAG : 6;
		unsigned int                                 : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__SI {
	struct {
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__VI {
	struct {
		unsigned int                                 : 6;
		unsigned int                      OUT_ENABLE : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__SI__VI {
	struct {
                unsigned int AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI__VI {
	struct {
                unsigned int AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__SI__VI {
	struct {
                unsigned int                 POWER_STATE_SET : 4;
                unsigned int                 POWER_STATE_ACT : 4;
                unsigned int                                 : 1;
                unsigned int                   CLKSTOPOK__VI : 1;
                unsigned int  POWER_STATE_SETTINGS_RESET__VI : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__SI__VI {
	struct {
                unsigned int                     CODEC_RESET : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SI__VI {
	struct {
                unsigned int              SUBSYSTEM_ID_BYTE1 : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SI__VI {
	struct {
                unsigned int              SUBSYSTEM_ID_BYTE2 : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SI__VI {
	struct {
                unsigned int              SUBSYSTEM_ID_BYTE3 : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI__VI {
	struct {
                unsigned int              SUBSYSTEM_ID_BYTE0 : 8;
                unsigned int              SUBSYSTEM_ID_BYTE1 : 8;
                unsigned int              SUBSYSTEM_ID_BYTE2 : 8;
                unsigned int              SUBSYSTEM_ID_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI__VI {
	struct {
                unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI {
	struct {
		unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__VI {
	struct {
		unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES : 30;
		unsigned int                         CLKSTOP : 1;
		unsigned int                            EPSS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI__VI {
	struct {
                unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SI__VI {
	struct {
                unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI__VI {
	struct {
                unsigned int         AUDIO_RATE_CAPABILITIES : 12;
                unsigned int                                 : 4;
                unsigned int          AUDIO_BIT_CAPABILITIES : 5;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__SI__VI {
	struct {
                unsigned int AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SI__VI {
	struct {
                unsigned int AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI__VI {
	struct {
                unsigned int AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_LATENCY_COUNTER_CONTROL__SI__VI {
	struct {
                unsigned int    AZALIA_LATENCY_COUNTER_RESET : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_RIRB_AND_DP_CONTROL__SI__VI {
	struct {
                unsigned int                  RIRB_NON_SNOOP : 1;
                unsigned int                                 : 3;
                unsigned int                DP_DMA_NON_SNOOP : 1;
                unsigned int      DP_UPDATE_FREQ_DIVIDER__VI : 4;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_UNDERFLOW_FILLER_SAMPLE__SI__VI {
	struct {
                unsigned int  AZALIA_UNDERFLOW_FILLER_SAMPLE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_WORSTCASE_LATENCY_COUNT__SI__VI {
	struct {
                unsigned int  AZALIA_WORSTCASE_LATENCY_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZ_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int              AZ_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZ_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int             AZ_TEST_DEBUG_INDEX : 8;
                unsigned int          AZ_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BACO_CNTL_MISC__CI__VI {
	struct {
                unsigned int                 BIF_ROM_REQ_DIS : 1;
                unsigned int                  BIF_AZ_REQ_DIS : 1;
                unsigned int         BACO_LINK_RST_WIDTH_SEL : 2;
                unsigned int             BACO_REFCLK_SEL__VI : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BACO_CNTL__CI__VI {
	struct {
                unsigned int                         BACO_EN : 1;
                unsigned int                   BACO_BCLK_OFF : 1;
                unsigned int                    BACO_ISO_DIS : 1;
                unsigned int                  BACO_POWER_OFF : 1;
                unsigned int                   BACO_RESET_EN : 1;
                unsigned int         BACO_HANG_PROTECTION_EN : 1;
                unsigned int                       BACO_MODE : 1;
                unsigned int                BACO_ANA_ISO_DIS : 1;
                unsigned int             RCU_BIF_CONFIG_DONE : 1;
                unsigned int                      PWRGOOD_BF : 1;
                unsigned int                    PWRGOOD_GPIO : 1;
                unsigned int                     PWRGOOD_MEM : 1;
                unsigned int                     PWRGOOD_DVO : 1;
                unsigned int                PWRGOOD_IDSC__VI : 1;
                unsigned int                                 : 2;
                unsigned int             BACO_POWER_OFF_DRAM : 1;
                unsigned int       BACO_BF_MEM_PHY_ISO_CNTRL : 1;
                unsigned int        BACO_BIF_SCLK_SWITCH__VI : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BASE_ADDR_1 {
	struct {
		unsigned int                       BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BASE_ADDR_2 {
	struct {
		unsigned int                       BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BASE_ADDR_3 {
	struct {
		unsigned int                       BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BASE_ADDR_4 {
	struct {
		unsigned int                       BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BASE_ADDR_5 {
	struct {
		unsigned int                       BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BASE_ADDR_6 {
	struct {
		unsigned int                       BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BASE_CLASS {
	struct {
		unsigned int                      BASE_CLASS : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BCI_DEBUG_READ {
	struct {
		unsigned int                            DATA : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_BACO_DEBUG_LATCH__CI__VI {
	struct {
                unsigned int              BIF_BACO_LATCH_FLG : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_BACO_DEBUG__CI__VI {
	struct {
                unsigned int           BIF_BACO_SCANDUMP_FLG : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_BACO_MSIC__CI {
	struct {
		unsigned int                  BIF_XTALIN_SEL : 1;
		unsigned int               BACO_LINK_RST_SEL : 2;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_BUSNUM_CNTL1 {
	struct {
		unsigned int                         ID_MASK : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_BUSNUM_CNTL2 {
	struct {
		unsigned int                  AUTOUPDATE_SEL : 8;
		unsigned int                   AUTOUPDATE_EN : 1;
		unsigned int                                 : 7;
		unsigned int                     HDPREG_CNTL : 1;
		unsigned int         ERROR_MULTIPLE_ID_MATCH : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_BUSNUM_LIST0 {
	struct {
		unsigned int                             ID0 : 8;
		unsigned int                             ID1 : 8;
		unsigned int                             ID2 : 8;
		unsigned int                             ID3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_BUSNUM_LIST1 {
	struct {
		unsigned int                             ID4 : 8;
		unsigned int                             ID5 : 8;
		unsigned int                             ID6 : 8;
		unsigned int                             ID7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_BUSY_DELAY_CNTR {
	struct {
		unsigned int                       DELAY_CNT : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_CC_RFE_IMP_OVERRIDECNTL__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int             STRAP_PLL_RX_IMPVAL : 4;
                unsigned int          STRAP_PLL_RX_IMPVAL_EN : 1;
                unsigned int          STRAP_PLL_TX_IMPVAL_PD : 4;
                unsigned int       STRAP_PLL_TX_IMPVAL_EN_PD : 1;
                unsigned int          STRAP_PLL_TX_IMPVAL_PU : 4;
                unsigned int       STRAP_PLL_TX_IMPVAL_EN_PU : 1;
                unsigned int     STRAP_PLL_IMP_DBG_ANALOG_EN : 1;
                unsigned int STRAP_PLL_IMP_IGNORE_QUICKSIM__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_CLK_PDWN_DELAY_TIMER__SI__CI {
	struct {
		unsigned int                           TIMER : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DEBUG_CNTL {
	struct {
		unsigned int                        DEBUG_EN : 1;
		unsigned int              DEBUG_MULTIBLOCKEN : 1;
		unsigned int                    DEBUG_OUT_EN : 1;
		unsigned int                   DEBUG_PAD_SEL : 1;
		unsigned int              DEBUG_BYTESEL_BLK1 : 1;
		unsigned int              DEBUG_BYTESEL_BLK2 : 1;
		unsigned int                   DEBUG_SYNC_EN : 1;
		unsigned int                      DEBUG_SWAP : 1;
		unsigned int                DEBUG_IDSEL_BLK1 : 5;
		unsigned int                                 : 3;
		unsigned int                DEBUG_IDSEL_BLK2 : 5;
		unsigned int                                 : 3;
		unsigned int                 DEBUG_IDSEL_XSP : 1;
		unsigned int                                 : 5;
		unsigned int               DEBUG_SYNC_CLKSEL : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DEBUG_MUX {
	struct {
		unsigned int                  DEBUG_MUX_BLK1 : 6;
		unsigned int                                 : 2;
		unsigned int                  DEBUG_MUX_BLK2 : 6;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DEBUG_OUT {
	struct {
		unsigned int                    DEBUG_OUTPUT : 17;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DEVFUNCNUM_LIST0__CI__VI {
	struct {
                unsigned int                     DEVFUNC_ID0 : 8;
                unsigned int                     DEVFUNC_ID1 : 8;
                unsigned int                     DEVFUNC_ID2 : 8;
                unsigned int                     DEVFUNC_ID3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DEVFUNCNUM_LIST1__CI__VI {
	struct {
                unsigned int                     DEVFUNC_ID4 : 8;
                unsigned int                     DEVFUNC_ID5 : 8;
                unsigned int                     DEVFUNC_ID6 : 8;
                unsigned int                     DEVFUNC_ID7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DOORBELL_CNTL__CI__VI {
	struct {
                unsigned int                   SELF_RING_DIS : 1;
                unsigned int                 TRANS_CHECK_DIS : 1;
                unsigned int                UNTRANS_LBACK_EN : 1;
                unsigned int     NON_CONSECUTIVE_BE_ZERO_DIS : 1;
                unsigned int         DOORBELL_MONITOR_EN__VI : 1;
                unsigned int   DOORBELL_INTERRUPT_STATUS__VI : 1;
                unsigned int                                 : 10;
                unsigned int    DOORBELL_INTERRUPT_CLEAR__VI : 1;
                unsigned int                                 : 7;
                unsigned int          DB_MNTR_INTGEN_DIS__VI : 1;
                unsigned int       DB_MNTR_INTGEN_MODE_0__VI : 1;
                unsigned int       DB_MNTR_INTGEN_MODE_1__VI : 1;
                unsigned int       DB_MNTR_INTGEN_MODE_2__VI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_FB_EN {
	struct {
		unsigned int                      FB_READ_EN : 1;
		unsigned int                     FB_WRITE_EN : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_FEATURES_CONTROL_MISC__CI__VI {
	struct {
                unsigned int              MST_BIF_REQ_EP_DIS : 1;
                unsigned int              SLV_BIF_CPL_EP_DIS : 1;
                unsigned int              BIF_SLV_REQ_EP_DIS : 1;
                unsigned int              BIF_MST_CPL_EP_DIS : 1;
                unsigned int    UR_PSN_PKT_REPORT_POISON_DIS : 1;
                unsigned int POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS : 1;
                unsigned int POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS : 1;
                unsigned int  PLL_SWITCH_IMPCTL_CAL_DONE_DIS : 1;
                unsigned int IGNORE_BE_CHECK_GASKET_COMB_DIS : 1;
                unsigned int   MC_BIF_REQ_ID_ROUTING_DIS__VI : 1;
                unsigned int   AZ_BIF_REQ_ID_ROUTING_DIS__VI : 1;
                unsigned int    ATC_PRG_RESP_PASID_UR_EN__VI : 1;
                unsigned int      BIF_RB_SET_OVERFLOW_EN__VI : 1;
                unsigned int          ATOMIC_ERR_INT_DIS__VI : 1;
                unsigned int                                 : 1;
                unsigned int           BME_HDL_NONVIR_EN__VI : 1;
                unsigned int      INIT_PFFLR_CRS_RET_DIS__VI : 1;
                unsigned int        FLR_MST_PEND_CHK_DIS__VI : 1;
                unsigned int        FLR_SLV_PEND_CHK_DIS__VI : 1;
                unsigned int       SOFT_PF_FLR_UR_CFG_EN__VI : 1;
                unsigned int             FLR_OSTD_UR_DIS__VI : 1;
                unsigned int            FLR_OSTD_HDL_DIS__VI : 1;
                unsigned int          FLR_NEWREQ_HDL_DIS__VI : 1;
                unsigned int             FLR_CRS_CFG_DIS__VI : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__CI__VI {
	struct {
                unsigned int                   UPDATE_PERIOD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_IMPCTL_RXCNTL__CI__VI {
	struct {
                unsigned int                       RX_ADJUST : 3;
                unsigned int                    RX_BIAS_HIGH : 1;
                unsigned int              CONT_AFTER_RX_DECT : 1;
                unsigned int                                 : 1;
                unsigned int                         SUSPEND : 1;
                unsigned int                       FORCE_RST : 1;
                unsigned int             LOWER_RX_ADJ_THRESH : 4;
                unsigned int                    LOWER_RX_ADJ : 1;
                unsigned int             UPPER_RX_ADJ_THRESH : 4;
                unsigned int                    UPPER_RX_ADJ : 1;
                unsigned int                   RX_IMP_LOCKED : 1;
                unsigned int             RX_IMP_READBACK_SEL : 1;
                unsigned int                 RX_IMP_READBACK : 4;
                unsigned int                                 : 4;
                unsigned int                    RX_CMP_AMBIG : 1;
                unsigned int                        CAL_DONE : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_IMPCTL_SMPLCNTL__CI__VI {
	struct {
                unsigned int                      FORCE_DONE : 1;
                unsigned int                          RxPDNB : 1;
                unsigned int                       TxPDNB_pd : 1;
                unsigned int                       TxPDNB_pu : 1;
                unsigned int                                 : 4;
                unsigned int                   SAMPLE_PERIOD : 5;
                unsigned int                  EXTEND_SAMPLES : 1;
                unsigned int                    FORCE_ENABLE : 1;
                unsigned int                      SETUP_TIME : 5;
                unsigned int             LOWER_SAMPLE_THRESH : 6;
                unsigned int             UPPER_SAMPLE_THRESH : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_IMPCTL_TXCNTL_pd__CI__VI {
	struct {
                unsigned int                    TX_ADJUST_pd : 3;
                unsigned int                 TX_BIAS_HIGH_pd : 1;
                unsigned int                                 : 4;
                unsigned int          LOWER_TX_ADJ_THRESH_pd : 4;
                unsigned int                 LOWER_TX_ADJ_pd : 1;
                unsigned int          UPPER_TX_ADJ_THRESH_pd : 4;
                unsigned int                 UPPER_TX_ADJ_pd : 1;
                unsigned int                TX_IMP_LOCKED_pd : 1;
                unsigned int          TX_IMP_READBACK_SEL_pd : 1;
                unsigned int              TX_IMP_READBACK_pd : 4;
                unsigned int                                 : 4;
                unsigned int                 TX_CMP_AMBIG_pd : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_IMPCTL_TXCNTL_pu__CI__VI {
	struct {
                unsigned int                    TX_ADJUST_pu : 3;
                unsigned int                 TX_BIAS_HIGH_pu : 1;
                unsigned int                                 : 4;
                unsigned int          LOWER_TX_ADJ_THRESH_pu : 4;
                unsigned int                 LOWER_TX_ADJ_pu : 1;
                unsigned int          UPPER_TX_ADJ_THRESH_pu : 4;
                unsigned int                 UPPER_TX_ADJ_pu : 1;
                unsigned int                TX_IMP_LOCKED_pu : 1;
                unsigned int          TX_IMP_READBACK_SEL_pu : 1;
                unsigned int              TX_IMP_READBACK_pu : 4;
                unsigned int                                 : 4;
                unsigned int                 TX_CMP_AMBIG_pu : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_LNCNT_RESET__CI {
	struct {
		unsigned int                  RESET_LNCNT_EN : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_PERFCOUNTER0_RESULT__CI__VI {
	struct {
                unsigned int              PERFCOUNTER_RESULT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_PERFCOUNTER1_RESULT__CI__VI {
	struct {
                unsigned int              PERFCOUNTER_RESULT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_PERFMON_CNTL__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_EN : 1;
                unsigned int              PERFCOUNTER_RESET0 : 1;
                unsigned int              PERFCOUNTER_RESET1 : 1;
                unsigned int                                 : 5;
                unsigned int                       PERF_SEL0 : 5;
                unsigned int                       PERF_SEL1 : 5;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_PIF_TXCLK_SWITCH_TIMER__CI {
	struct {
		unsigned int                  PLL0_ACK_TIMER : 3;
		unsigned int                  PLL1_ACK_TIMER : 3;
		unsigned int                PLL_SWITCH_TIMER : 4;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_PWDN_COMMAND__CI {
	struct {
		unsigned int                   REG_BU_pw_cmd : 1;
		unsigned int       REG_RWREG_RFEWDBIF_pw_cmd : 1;
		unsigned int                   REG_BX_pw_cmd : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_PWDN_COMMAND__VI {
	struct {
		unsigned int                   REG_BU_pw_cmd : 1;
		unsigned int       REG_RWREG_RFEWDBIF_pw_cmd : 1;
		unsigned int                REG_SMBUS_pw_cmd : 1;
		unsigned int                   REG_BX_pw_cmd : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_PWDN_STATUS__CI {
	struct {
		unsigned int                BU_REG_pw_status : 1;
		unsigned int    RWREG_RFEWDBIF_REG_pw_status : 1;
		unsigned int                BX_REG_pw_status : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_PWDN_STATUS__VI {
	struct {
		unsigned int                BU_REG_pw_status : 1;
		unsigned int    RWREG_RFEWDBIF_REG_pw_status : 1;
		unsigned int             SMBUS_REG_pw_status : 1;
		unsigned int                BX_REG_pw_status : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RESET_CNTL__CI {
	struct {
		unsigned int                        STRAP_EN : 1;
		unsigned int                        RST_DONE : 1;
		unsigned int                   LINK_TRAIN_EN : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RESET_EN__SI__CI {
	struct {
                unsigned int                                 : 1;
                unsigned int               SOFT_RST_MODE__CI : 1;
                unsigned int                    PHY_RESET_EN : 1;
                unsigned int                    COR_RESET_EN : 1;
                unsigned int                    REG_RESET_EN : 1;
                unsigned int                    STY_RESET_EN : 1;
                unsigned int                    CFG_RESET_EN : 1;
                unsigned int                    DRV_RESET_EN : 1;
                unsigned int            RESET_CFGREG_ONLY_EN : 1;
                unsigned int                    HOT_RESET_EN : 1;
                unsigned int           LINK_DISABLE_RESET_EN : 1;
                unsigned int              LINK_DOWN_RESET_EN : 1;
                unsigned int           CFG_RESET_PULSE_WIDTH : 6;
                unsigned int             DRV_RESET_DELAY_SEL : 2;
                unsigned int                 PIF_RSTB_EN__CI : 1;
                unsigned int       PIF_STRAP_ALLVALID_EN__CI : 1;
                unsigned int            BIF_COR_RESET_EN__CI : 1;
                unsigned int                FUNC0_FLR_EN__CI : 1;
                unsigned int                FUNC1_FLR_EN__CI : 1;
                unsigned int                FUNC2_FLR_EN__CI : 1;
                unsigned int       FUNC0_RESET_DELAY_SEL__CI : 2;
                unsigned int       FUNC1_RESET_DELAY_SEL__CI : 2;
                unsigned int       FUNC2_RESET_DELAY_SEL__CI : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_CLIENT_SOFTRST_TRIGGER__CI__VI {
	struct {
                unsigned int        CLIENT0_RFE_RFEWDBIF_rst : 1;
                unsigned int        CLIENT1_RFE_RFEWDBIF_rst : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_IMPRST_CNTL__CI__VI {
	struct {
                unsigned int                   REG_RST_impEn : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_MASTER_SOFTRST_TRIGGER__CI {
	struct {
		unsigned int                          BU_rst : 1;
		unsigned int              RWREG_RFEWDBIF_rst : 1;
		unsigned int                          BX_rst : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_MASTER_SOFTRST_TRIGGER__VI {
	struct {
		unsigned int                          BU_rst : 1;
		unsigned int              RWREG_RFEWDBIF_rst : 1;
		unsigned int                       SMBUS_rst : 1;
		unsigned int                          BX_rst : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_MMCFG_CNTL__CI__VI {
	struct {
                unsigned int CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN : 1;
                unsigned int CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL : 3;
                unsigned int CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN : 1;
                unsigned int CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL : 3;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_MST_BU_CMDSTATUS__CI__VI {
	struct {
                unsigned int            REG_BU_clkGate_timer : 8;
                unsigned int           REG_BU_clkSetup_timer : 4;
                unsigned int                                 : 4;
                unsigned int            REG_BU_timeout_timer : 8;
                unsigned int               BU_RFE_mstTimeout : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_MST_BX_CMDSTATUS__CI__VI {
	struct {
                unsigned int            REG_BX_clkGate_timer : 8;
                unsigned int           REG_BX_clkSetup_timer : 4;
                unsigned int                                 : 4;
                unsigned int            REG_BX_timeout_timer : 8;
                unsigned int               BX_RFE_mstTimeout : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__CI__VI {
	struct {
                unsigned int REG_RWREG_RFEWDBIF_clkGate_timer : 8;
                unsigned int REG_RWREG_RFEWDBIF_clkSetup_timer : 4;
                unsigned int                                 : 4;
                unsigned int REG_RWREG_RFEWDBIF_timeout_timer : 8;
                unsigned int   RWREG_RFEWDBIF_RFE_mstTimeout : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_MST_TMOUT_STATUS__CI__VI {
	struct {
                unsigned int                  MstTmoutStatus : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_SNOOP_REG__CI__VI {
	struct {
                unsigned int               REG_SNOOP_ARBITER : 1;
                unsigned int             REG_SNOOP_ALLMASTER : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_SOFTRST_CNTL__CI {
	struct {
		unsigned int                REG_RST_rstTimer : 16;
		unsigned int                                 : 13;
		unsigned int                                 : 1;
		unsigned int           REG_RST_softRstPropEn : 1;
		unsigned int                      SoftRstReg : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_SOFTRST_CNTL__VI {
	struct {
		unsigned int                REG_RST_rstTimer : 16;
		unsigned int                                 : 14;
		unsigned int           REG_RST_softRstPropEn : 1;
		unsigned int                      SoftRstReg : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SCRATCH0 {
	struct {
		unsigned int                    BIF_SCRATCH0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SCRATCH1 {
	struct {
		unsigned int                    BIF_SCRATCH1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SLVARB_MODE__CI__VI {
	struct {
                unsigned int                     SLVARB_MODE : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_DISP_LOWER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  SSA_DISP_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int             SSA_DISP_REG_CMP_EN : 1;
		unsigned int           SSA_DISP_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_DISP_UPPER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  SSA_DISP_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_GFX0_LOWER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  SSA_GFX0_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int             SSA_GFX0_REG_CMP_EN : 1;
		unsigned int           SSA_GFX0_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_GFX0_UPPER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  SSA_GFX0_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_GFX1_LOWER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  SSA_GFX1_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int             SSA_GFX1_REG_CMP_EN : 1;
		unsigned int           SSA_GFX1_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_GFX1_UPPER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  SSA_GFX1_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_GFX2_LOWER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  SSA_GFX2_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int             SSA_GFX2_REG_CMP_EN : 1;
		unsigned int           SSA_GFX2_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_GFX2_UPPER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  SSA_GFX2_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_GFX3_LOWER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  SSA_GFX3_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int             SSA_GFX3_REG_CMP_EN : 1;
		unsigned int           SSA_GFX3_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_GFX3_UPPER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  SSA_GFX3_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_MC_LOWER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                    SSA_MC_LOWER : 16;
		unsigned int                                 : 11;
		unsigned int              SSA_MC_FB_STALL_EN : 1;
		unsigned int               SSA_MC_REG_CMP_EN : 1;
		unsigned int             SSA_MC_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_MC_UPPER__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                    SSA_MC_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SSA_PWR_STATUS__CI {
	struct {
		unsigned int              SSA_GFX_PWR_STATUS : 1;
		unsigned int             SSA_DISP_PWR_STATUS : 1;
		unsigned int               SSA_MC_PWR_STATUS : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_XDMA_HI__CI__VI {
	struct {
                unsigned int            BIF_XDMA_UPPER_BOUND : 29;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_XDMA_LO__CI__VI {
	struct {
                unsigned int            BIF_XDMA_LOWER_BOUND : 29;
                unsigned int                                 : 2;
                unsigned int                BIF_XDMA_APER_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_0 {
	struct {
		unsigned int                  BIOS_SCRATCH_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_1 {
	struct {
		unsigned int                  BIOS_SCRATCH_1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_10 {
	struct {
		unsigned int                 BIOS_SCRATCH_10 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_11 {
	struct {
		unsigned int                 BIOS_SCRATCH_11 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_12 {
	struct {
		unsigned int                 BIOS_SCRATCH_12 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_13 {
	struct {
		unsigned int                 BIOS_SCRATCH_13 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_14 {
	struct {
		unsigned int                 BIOS_SCRATCH_14 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_15 {
	struct {
		unsigned int                 BIOS_SCRATCH_15 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_2 {
	struct {
		unsigned int                  BIOS_SCRATCH_2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_3 {
	struct {
		unsigned int                  BIOS_SCRATCH_3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_4 {
	struct {
		unsigned int                  BIOS_SCRATCH_4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_5 {
	struct {
		unsigned int                  BIOS_SCRATCH_5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_6 {
	struct {
		unsigned int                  BIOS_SCRATCH_6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_7 {
	struct {
		unsigned int                  BIOS_SCRATCH_7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_8 {
	struct {
		unsigned int                  BIOS_SCRATCH_8 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIOS_SCRATCH_9 {
	struct {
		unsigned int                  BIOS_SCRATCH_9 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIST {
	struct {
		unsigned int                       BIST_COMP : 4;
		unsigned int                                 : 2;
		unsigned int                       BIST_STRT : 1;
		unsigned int                        BIST_CAP : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL1_PWM_ABM_CNTL__SI__VI {
	struct {
                unsigned int              BL1_PWM_USE_ABM_EN : 1;
                unsigned int    BL1_PWM_USE_AMBIENT_LEVEL_EN : 1;
                unsigned int BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN : 1;
                unsigned int BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN : 1;
                unsigned int                                 : 12;
                unsigned int BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL1_PWM_AMBIENT_LIGHT_LEVEL__SI__VI {
	struct {
                unsigned int     BL1_PWM_AMBIENT_LIGHT_LEVEL : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL1_PWM_BL_UPDATE_SAMPLE_RATE__SI__VI {
	struct {
                unsigned int BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN : 1;
                unsigned int BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER : 1;
                unsigned int                                 : 6;
                unsigned int BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT : 8;
                unsigned int BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET : 8;
                unsigned int                                 : 7;
                unsigned int              ABM1_HGLS_REG_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL1_PWM_CURRENT_ABM_LEVEL__SI__VI {
	struct {
                unsigned int       BL1_PWM_CURRENT_ABM_LEVEL : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL1_PWM_FINAL_DUTY_CYCLE__SI__VI {
	struct {
                unsigned int        BL1_PWM_FINAL_DUTY_CYCLE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL1_PWM_GRP2_REG_LOCK__SI__VI {
	struct {
                unsigned int           BL1_PWM_GRP2_REG_LOCK : 1;
                unsigned int                                 : 7;
                unsigned int BL1_PWM_GRP2_REG_UPDATE_PENDING : 1;
                unsigned int                                 : 7;
                unsigned int BL1_PWM_GRP2_UPDATE_AT_FRAME_START : 1;
                unsigned int BL1_PWM_GRP2_FRAME_START_DISP_SEL : 3;
                unsigned int                                 : 4;
                unsigned int BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN : 1;
                unsigned int                                 : 6;
                unsigned int BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL1_PWM_MINIMUM_DUTY_CYCLE__SI__VI {
	struct {
                unsigned int      BL1_PWM_MINIMUM_DUTY_CYCLE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL1_PWM_TARGET_ABM_LEVEL__SI__VI {
	struct {
                unsigned int        BL1_PWM_TARGET_ABM_LEVEL : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL1_PWM_USER_LEVEL__SI__VI {
	struct {
                unsigned int              BL1_PWM_USER_LEVEL : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL_PWM_CNTL2__SI__VI {
	struct {
                unsigned int BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE : 16;
                unsigned int                                 : 12;
                unsigned int  DBG_BL_PWM_INPUT_REFCLK_SELECT : 2;
                unsigned int   BL_PWM_OVERRIDE_BL_OUT_ENABLE : 1;
                unsigned int BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL_PWM_CNTL__SI__VI {
	struct {
                unsigned int          BL_ACTIVE_INT_FRAC_CNT : 16;
                unsigned int                                 : 14;
                unsigned int            BL_PWM_FRACTIONAL_EN : 1;
                unsigned int                       BL_PWM_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL_PWM_GRP1_REG_LOCK__SI__VI {
	struct {
                unsigned int            BL_PWM_GRP1_REG_LOCK : 1;
                unsigned int                                 : 7;
                unsigned int  BL_PWM_GRP1_REG_UPDATE_PENDING : 1;
                unsigned int                                 : 7;
                unsigned int BL_PWM_GRP1_UPDATE_AT_FRAME_START : 1;
                unsigned int BL_PWM_GRP1_FRAME_START_DISP_SEL : 3;
                unsigned int                                 : 4;
                unsigned int BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN : 1;
                unsigned int                                 : 6;
                unsigned int BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BL_PWM_PERIOD_CNTL__SI__VI {
	struct {
                unsigned int                   BL_PWM_PERIOD : 16;
                unsigned int            BL_PWM_PERIOD_BITCNT : 4;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BUS_CNTL {
	struct {
                unsigned int                 BIOS_ROM_WRT_EN : 1;
                unsigned int                    BIOS_ROM_DIS : 1;
                unsigned int                      PMI_IO_DIS : 1;
                unsigned int                     PMI_MEM_DIS : 1;
                unsigned int                      PMI_BM_DIS : 1;
                unsigned int                     PMI_INT_DIS : 1;
                unsigned int           VGA_REG_COHERENCY_DIS : 1;
                unsigned int           VGA_MEM_COHERENCY_DIS : 1;
                unsigned int       BIF_ERR_RTR_BKPRESSURE_EN : 1;
                unsigned int                                 : 1;
                unsigned int                       SET_AZ_TC : 3;
                unsigned int                       SET_MC_TC : 3;
                unsigned int                   ZERO_BE_WR_EN : 1;
                unsigned int                   ZERO_BE_RD_EN : 1;
                unsigned int          RD_STALL_IO_WR__CI__VI : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BX_RESET_EN__CI__VI {
	struct {
                unsigned int                    COR_RESET_EN : 1;
                unsigned int                    REG_RESET_EN : 1;
                unsigned int                    STY_RESET_EN : 1;
                unsigned int                                 : 5;
                unsigned int                FLR_TWICE_EN__VI : 1;
                unsigned int               FLR_TIMER_SEL__VI : 2;
                unsigned int                                 : 4;
                unsigned int            DB_APER_RESET_EN__VI : 1;
                unsigned int    RESET_ON_VFENABLE_LOW_EN__VI : 1;
                unsigned int            PF_FLR_NEWHDL_EN__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CACHE_LINE {
	struct {
		unsigned int                 CACHE_LINE_SIZE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CAPTURE_HOST_BUSNUM {
	struct {
		unsigned int                        CHECK_EN : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CAP_PTR {
	struct {
		unsigned int                         CAP_PTR : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND0_CONTROL {
	struct {
		unsigned int                  COLOR_SRCBLEND : 5;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                 COLOR_DESTBLEND : 5;
		unsigned int                                 : 3;
		unsigned int                  ALPHA_SRCBLEND : 5;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                 ALPHA_DESTBLEND : 5;
		unsigned int            SEPARATE_ALPHA_BLEND : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                    DISABLE_ROP3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND1_CONTROL {
	struct {
		unsigned int                  COLOR_SRCBLEND : 5;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                 COLOR_DESTBLEND : 5;
		unsigned int                                 : 3;
		unsigned int                  ALPHA_SRCBLEND : 5;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                 ALPHA_DESTBLEND : 5;
		unsigned int            SEPARATE_ALPHA_BLEND : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                    DISABLE_ROP3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND2_CONTROL {
	struct {
		unsigned int                  COLOR_SRCBLEND : 5;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                 COLOR_DESTBLEND : 5;
		unsigned int                                 : 3;
		unsigned int                  ALPHA_SRCBLEND : 5;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                 ALPHA_DESTBLEND : 5;
		unsigned int            SEPARATE_ALPHA_BLEND : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                    DISABLE_ROP3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND3_CONTROL {
	struct {
		unsigned int                  COLOR_SRCBLEND : 5;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                 COLOR_DESTBLEND : 5;
		unsigned int                                 : 3;
		unsigned int                  ALPHA_SRCBLEND : 5;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                 ALPHA_DESTBLEND : 5;
		unsigned int            SEPARATE_ALPHA_BLEND : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                    DISABLE_ROP3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND4_CONTROL {
	struct {
		unsigned int                  COLOR_SRCBLEND : 5;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                 COLOR_DESTBLEND : 5;
		unsigned int                                 : 3;
		unsigned int                  ALPHA_SRCBLEND : 5;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                 ALPHA_DESTBLEND : 5;
		unsigned int            SEPARATE_ALPHA_BLEND : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                    DISABLE_ROP3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND5_CONTROL {
	struct {
		unsigned int                  COLOR_SRCBLEND : 5;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                 COLOR_DESTBLEND : 5;
		unsigned int                                 : 3;
		unsigned int                  ALPHA_SRCBLEND : 5;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                 ALPHA_DESTBLEND : 5;
		unsigned int            SEPARATE_ALPHA_BLEND : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                    DISABLE_ROP3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND6_CONTROL {
	struct {
		unsigned int                  COLOR_SRCBLEND : 5;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                 COLOR_DESTBLEND : 5;
		unsigned int                                 : 3;
		unsigned int                  ALPHA_SRCBLEND : 5;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                 ALPHA_DESTBLEND : 5;
		unsigned int            SEPARATE_ALPHA_BLEND : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                    DISABLE_ROP3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND7_CONTROL {
	struct {
		unsigned int                  COLOR_SRCBLEND : 5;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                 COLOR_DESTBLEND : 5;
		unsigned int                                 : 3;
		unsigned int                  ALPHA_SRCBLEND : 5;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                 ALPHA_DESTBLEND : 5;
		unsigned int            SEPARATE_ALPHA_BLEND : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                    DISABLE_ROP3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND_ALPHA {
	struct {
		unsigned int                     BLEND_ALPHA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND_BLUE {
	struct {
		unsigned int                      BLEND_BLUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND_GREEN {
	struct {
		unsigned int                     BLEND_GREEN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_BLEND_RED {
	struct {
		unsigned int                       BLEND_RED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_CGTT_SCLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_ATTRIB {
	struct {
		unsigned int                 TILE_MODE_INDEX : 5;
		unsigned int           FMASK_TILE_MODE_INDEX : 5;
		unsigned int               FMASK_BANK_HEIGHT : 2;
		unsigned int                     NUM_SAMPLES : 3;
		unsigned int                   NUM_FRAGMENTS : 2;
		unsigned int               FORCE_DST_ALPHA_1 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_CLEAR_WORD0 {
	struct {
		unsigned int                     CLEAR_WORD0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_CLEAR_WORD1 {
	struct {
		unsigned int                     CLEAR_WORD1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_CMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_CMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_FMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_FMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_INFO {
	struct {
                unsigned int                          ENDIAN : 2;
                unsigned int                          FORMAT : 5;
                unsigned int                  LINEAR_GENERAL : 1;
                unsigned int                     NUMBER_TYPE : 3;
                unsigned int                       COMP_SWAP : 2;
                unsigned int                      FAST_CLEAR : 1;
                unsigned int                     COMPRESSION : 1;
                unsigned int                     BLEND_CLAMP : 1;
                unsigned int                    BLEND_BYPASS : 1;
                unsigned int                    SIMPLE_FLOAT : 1;
                unsigned int                      ROUND_MODE : 1;
                unsigned int                 CMASK_IS_LINEAR : 1;
                unsigned int           BLEND_OPT_DONT_RD_DST : 3;
                unsigned int         BLEND_OPT_DISCARD_PIXEL : 3;
                unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1;
                unsigned int   FMASK_COMPRESS_1FRAG_ONLY__VI : 1;
                unsigned int                  DCC_ENABLE__VI : 1;
                unsigned int             CMASK_ADDR_TYPE__VI : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_PITCH {
	struct {
                unsigned int                        TILE_MAX : 11;
                unsigned int                                 : 9;
                unsigned int          FMASK_TILE_MAX__CI__VI : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_VIEW {
	struct {
		unsigned int                     SLICE_START : 11;
		unsigned int                                 : 2;
		unsigned int                       SLICE_MAX : 11;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_ATTRIB {
	struct {
		unsigned int                 TILE_MODE_INDEX : 5;
		unsigned int           FMASK_TILE_MODE_INDEX : 5;
		unsigned int               FMASK_BANK_HEIGHT : 2;
		unsigned int                     NUM_SAMPLES : 3;
		unsigned int                   NUM_FRAGMENTS : 2;
		unsigned int               FORCE_DST_ALPHA_1 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_CLEAR_WORD0 {
	struct {
		unsigned int                     CLEAR_WORD0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_CLEAR_WORD1 {
	struct {
		unsigned int                     CLEAR_WORD1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_CMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_CMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_FMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_FMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_INFO {
	struct {
                unsigned int                          ENDIAN : 2;
                unsigned int                          FORMAT : 5;
                unsigned int                  LINEAR_GENERAL : 1;
                unsigned int                     NUMBER_TYPE : 3;
                unsigned int                       COMP_SWAP : 2;
                unsigned int                      FAST_CLEAR : 1;
                unsigned int                     COMPRESSION : 1;
                unsigned int                     BLEND_CLAMP : 1;
                unsigned int                    BLEND_BYPASS : 1;
                unsigned int                    SIMPLE_FLOAT : 1;
                unsigned int                      ROUND_MODE : 1;
                unsigned int                 CMASK_IS_LINEAR : 1;
                unsigned int           BLEND_OPT_DONT_RD_DST : 3;
                unsigned int         BLEND_OPT_DISCARD_PIXEL : 3;
                unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1;
                unsigned int   FMASK_COMPRESS_1FRAG_ONLY__VI : 1;
                unsigned int                  DCC_ENABLE__VI : 1;
                unsigned int             CMASK_ADDR_TYPE__VI : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_PITCH {
	struct {
                unsigned int                        TILE_MAX : 11;
                unsigned int                                 : 9;
                unsigned int          FMASK_TILE_MAX__CI__VI : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_VIEW {
	struct {
		unsigned int                     SLICE_START : 11;
		unsigned int                                 : 2;
		unsigned int                       SLICE_MAX : 11;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_ATTRIB {
	struct {
		unsigned int                 TILE_MODE_INDEX : 5;
		unsigned int           FMASK_TILE_MODE_INDEX : 5;
		unsigned int               FMASK_BANK_HEIGHT : 2;
		unsigned int                     NUM_SAMPLES : 3;
		unsigned int                   NUM_FRAGMENTS : 2;
		unsigned int               FORCE_DST_ALPHA_1 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_CLEAR_WORD0 {
	struct {
		unsigned int                     CLEAR_WORD0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_CLEAR_WORD1 {
	struct {
		unsigned int                     CLEAR_WORD1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_CMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_CMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_FMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_FMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_INFO {
	struct {
                unsigned int                          ENDIAN : 2;
                unsigned int                          FORMAT : 5;
                unsigned int                  LINEAR_GENERAL : 1;
                unsigned int                     NUMBER_TYPE : 3;
                unsigned int                       COMP_SWAP : 2;
                unsigned int                      FAST_CLEAR : 1;
                unsigned int                     COMPRESSION : 1;
                unsigned int                     BLEND_CLAMP : 1;
                unsigned int                    BLEND_BYPASS : 1;
                unsigned int                    SIMPLE_FLOAT : 1;
                unsigned int                      ROUND_MODE : 1;
                unsigned int                 CMASK_IS_LINEAR : 1;
                unsigned int           BLEND_OPT_DONT_RD_DST : 3;
                unsigned int         BLEND_OPT_DISCARD_PIXEL : 3;
                unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1;
                unsigned int   FMASK_COMPRESS_1FRAG_ONLY__VI : 1;
                unsigned int                  DCC_ENABLE__VI : 1;
                unsigned int             CMASK_ADDR_TYPE__VI : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_PITCH {
	struct {
                unsigned int                        TILE_MAX : 11;
                unsigned int                                 : 9;
                unsigned int          FMASK_TILE_MAX__CI__VI : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_VIEW {
	struct {
		unsigned int                     SLICE_START : 11;
		unsigned int                                 : 2;
		unsigned int                       SLICE_MAX : 11;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_ATTRIB {
	struct {
		unsigned int                 TILE_MODE_INDEX : 5;
		unsigned int           FMASK_TILE_MODE_INDEX : 5;
		unsigned int               FMASK_BANK_HEIGHT : 2;
		unsigned int                     NUM_SAMPLES : 3;
		unsigned int                   NUM_FRAGMENTS : 2;
		unsigned int               FORCE_DST_ALPHA_1 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_CLEAR_WORD0 {
	struct {
		unsigned int                     CLEAR_WORD0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_CLEAR_WORD1 {
	struct {
		unsigned int                     CLEAR_WORD1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_CMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_CMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_FMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_FMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_INFO {
	struct {
                unsigned int                          ENDIAN : 2;
                unsigned int                          FORMAT : 5;
                unsigned int                  LINEAR_GENERAL : 1;
                unsigned int                     NUMBER_TYPE : 3;
                unsigned int                       COMP_SWAP : 2;
                unsigned int                      FAST_CLEAR : 1;
                unsigned int                     COMPRESSION : 1;
                unsigned int                     BLEND_CLAMP : 1;
                unsigned int                    BLEND_BYPASS : 1;
                unsigned int                    SIMPLE_FLOAT : 1;
                unsigned int                      ROUND_MODE : 1;
                unsigned int                 CMASK_IS_LINEAR : 1;
                unsigned int           BLEND_OPT_DONT_RD_DST : 3;
                unsigned int         BLEND_OPT_DISCARD_PIXEL : 3;
                unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1;
                unsigned int   FMASK_COMPRESS_1FRAG_ONLY__VI : 1;
                unsigned int                  DCC_ENABLE__VI : 1;
                unsigned int             CMASK_ADDR_TYPE__VI : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_PITCH {
	struct {
                unsigned int                        TILE_MAX : 11;
                unsigned int                                 : 9;
                unsigned int          FMASK_TILE_MAX__CI__VI : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_VIEW {
	struct {
		unsigned int                     SLICE_START : 11;
		unsigned int                                 : 2;
		unsigned int                       SLICE_MAX : 11;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_ATTRIB {
	struct {
		unsigned int                 TILE_MODE_INDEX : 5;
		unsigned int           FMASK_TILE_MODE_INDEX : 5;
		unsigned int               FMASK_BANK_HEIGHT : 2;
		unsigned int                     NUM_SAMPLES : 3;
		unsigned int                   NUM_FRAGMENTS : 2;
		unsigned int               FORCE_DST_ALPHA_1 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_CLEAR_WORD0 {
	struct {
		unsigned int                     CLEAR_WORD0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_CLEAR_WORD1 {
	struct {
		unsigned int                     CLEAR_WORD1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_CMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_CMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_FMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_FMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_INFO {
	struct {
                unsigned int                          ENDIAN : 2;
                unsigned int                          FORMAT : 5;
                unsigned int                  LINEAR_GENERAL : 1;
                unsigned int                     NUMBER_TYPE : 3;
                unsigned int                       COMP_SWAP : 2;
                unsigned int                      FAST_CLEAR : 1;
                unsigned int                     COMPRESSION : 1;
                unsigned int                     BLEND_CLAMP : 1;
                unsigned int                    BLEND_BYPASS : 1;
                unsigned int                    SIMPLE_FLOAT : 1;
                unsigned int                      ROUND_MODE : 1;
                unsigned int                 CMASK_IS_LINEAR : 1;
                unsigned int           BLEND_OPT_DONT_RD_DST : 3;
                unsigned int         BLEND_OPT_DISCARD_PIXEL : 3;
                unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1;
                unsigned int   FMASK_COMPRESS_1FRAG_ONLY__VI : 1;
                unsigned int                  DCC_ENABLE__VI : 1;
                unsigned int             CMASK_ADDR_TYPE__VI : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_PITCH {
	struct {
                unsigned int                        TILE_MAX : 11;
                unsigned int                                 : 9;
                unsigned int          FMASK_TILE_MAX__CI__VI : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_VIEW {
	struct {
		unsigned int                     SLICE_START : 11;
		unsigned int                                 : 2;
		unsigned int                       SLICE_MAX : 11;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_ATTRIB {
	struct {
		unsigned int                 TILE_MODE_INDEX : 5;
		unsigned int           FMASK_TILE_MODE_INDEX : 5;
		unsigned int               FMASK_BANK_HEIGHT : 2;
		unsigned int                     NUM_SAMPLES : 3;
		unsigned int                   NUM_FRAGMENTS : 2;
		unsigned int               FORCE_DST_ALPHA_1 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_CLEAR_WORD0 {
	struct {
		unsigned int                     CLEAR_WORD0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_CLEAR_WORD1 {
	struct {
		unsigned int                     CLEAR_WORD1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_CMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_CMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_FMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_FMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_INFO {
	struct {
                unsigned int                          ENDIAN : 2;
                unsigned int                          FORMAT : 5;
                unsigned int                  LINEAR_GENERAL : 1;
                unsigned int                     NUMBER_TYPE : 3;
                unsigned int                       COMP_SWAP : 2;
                unsigned int                      FAST_CLEAR : 1;
                unsigned int                     COMPRESSION : 1;
                unsigned int                     BLEND_CLAMP : 1;
                unsigned int                    BLEND_BYPASS : 1;
                unsigned int                    SIMPLE_FLOAT : 1;
                unsigned int                      ROUND_MODE : 1;
                unsigned int                 CMASK_IS_LINEAR : 1;
                unsigned int           BLEND_OPT_DONT_RD_DST : 3;
                unsigned int         BLEND_OPT_DISCARD_PIXEL : 3;
                unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1;
                unsigned int   FMASK_COMPRESS_1FRAG_ONLY__VI : 1;
                unsigned int                  DCC_ENABLE__VI : 1;
                unsigned int             CMASK_ADDR_TYPE__VI : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_PITCH {
	struct {
                unsigned int                        TILE_MAX : 11;
                unsigned int                                 : 9;
                unsigned int          FMASK_TILE_MAX__CI__VI : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_VIEW {
	struct {
		unsigned int                     SLICE_START : 11;
		unsigned int                                 : 2;
		unsigned int                       SLICE_MAX : 11;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_ATTRIB {
	struct {
		unsigned int                 TILE_MODE_INDEX : 5;
		unsigned int           FMASK_TILE_MODE_INDEX : 5;
		unsigned int               FMASK_BANK_HEIGHT : 2;
		unsigned int                     NUM_SAMPLES : 3;
		unsigned int                   NUM_FRAGMENTS : 2;
		unsigned int               FORCE_DST_ALPHA_1 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_CLEAR_WORD0 {
	struct {
		unsigned int                     CLEAR_WORD0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_CLEAR_WORD1 {
	struct {
		unsigned int                     CLEAR_WORD1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_CMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_CMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_FMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_FMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_INFO {
	struct {
                unsigned int                          ENDIAN : 2;
                unsigned int                          FORMAT : 5;
                unsigned int                  LINEAR_GENERAL : 1;
                unsigned int                     NUMBER_TYPE : 3;
                unsigned int                       COMP_SWAP : 2;
                unsigned int                      FAST_CLEAR : 1;
                unsigned int                     COMPRESSION : 1;
                unsigned int                     BLEND_CLAMP : 1;
                unsigned int                    BLEND_BYPASS : 1;
                unsigned int                    SIMPLE_FLOAT : 1;
                unsigned int                      ROUND_MODE : 1;
                unsigned int                 CMASK_IS_LINEAR : 1;
                unsigned int           BLEND_OPT_DONT_RD_DST : 3;
                unsigned int         BLEND_OPT_DISCARD_PIXEL : 3;
                unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1;
                unsigned int   FMASK_COMPRESS_1FRAG_ONLY__VI : 1;
                unsigned int                  DCC_ENABLE__VI : 1;
                unsigned int             CMASK_ADDR_TYPE__VI : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_PITCH {
	struct {
                unsigned int                        TILE_MAX : 11;
                unsigned int                                 : 9;
                unsigned int          FMASK_TILE_MAX__CI__VI : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_VIEW {
	struct {
		unsigned int                     SLICE_START : 11;
		unsigned int                                 : 2;
		unsigned int                       SLICE_MAX : 11;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_ATTRIB {
	struct {
		unsigned int                 TILE_MODE_INDEX : 5;
		unsigned int           FMASK_TILE_MODE_INDEX : 5;
		unsigned int               FMASK_BANK_HEIGHT : 2;
		unsigned int                     NUM_SAMPLES : 3;
		unsigned int                   NUM_FRAGMENTS : 2;
		unsigned int               FORCE_DST_ALPHA_1 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_CLEAR_WORD0 {
	struct {
		unsigned int                     CLEAR_WORD0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_CLEAR_WORD1 {
	struct {
		unsigned int                     CLEAR_WORD1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_CMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_CMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_FMASK {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_FMASK_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_INFO {
	struct {
                unsigned int                          ENDIAN : 2;
                unsigned int                          FORMAT : 5;
                unsigned int                  LINEAR_GENERAL : 1;
                unsigned int                     NUMBER_TYPE : 3;
                unsigned int                       COMP_SWAP : 2;
                unsigned int                      FAST_CLEAR : 1;
                unsigned int                     COMPRESSION : 1;
                unsigned int                     BLEND_CLAMP : 1;
                unsigned int                    BLEND_BYPASS : 1;
                unsigned int                    SIMPLE_FLOAT : 1;
                unsigned int                      ROUND_MODE : 1;
                unsigned int                 CMASK_IS_LINEAR : 1;
                unsigned int           BLEND_OPT_DONT_RD_DST : 3;
                unsigned int         BLEND_OPT_DISCARD_PIXEL : 3;
                unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1;
                unsigned int   FMASK_COMPRESS_1FRAG_ONLY__VI : 1;
                unsigned int                  DCC_ENABLE__VI : 1;
                unsigned int             CMASK_ADDR_TYPE__VI : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_PITCH {
	struct {
                unsigned int                        TILE_MAX : 11;
                unsigned int                                 : 9;
                unsigned int          FMASK_TILE_MAX__CI__VI : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_SLICE {
	struct {
		unsigned int                        TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_VIEW {
	struct {
		unsigned int                     SLICE_START : 11;
		unsigned int                                 : 2;
		unsigned int                       SLICE_MAX : 11;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR_CONTROL {
	struct {
                unsigned int           DISABLE_DUAL_QUAD__VI : 1;
                unsigned int                                 : 2;
                unsigned int                  DEGAMMA_ENABLE : 1;
                unsigned int                            MODE : 3;
                unsigned int                                 : 9;
                unsigned int                            ROP3 : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_1 {
	struct {
                unsigned int                     CB_BUSY__VI : 1;
                unsigned int      DB_CB_TILE_VALID_READY__VI : 1;
                unsigned int     DB_CB_TILE_VALID_READYB__VI : 1;
                unsigned int     DB_CB_TILE_VALIDB_READY__VI : 1;
                unsigned int    DB_CB_TILE_VALIDB_READYB__VI : 1;
                unsigned int     DB_CB_LQUAD_VALID_READY__VI : 1;
                unsigned int    DB_CB_LQUAD_VALID_READYB__VI : 1;
                unsigned int    DB_CB_LQUAD_VALIDB_READY__VI : 1;
                unsigned int   DB_CB_LQUAD_VALIDB_READYB__VI : 1;
                unsigned int    CB_TAP_WRREQ_VALID_READY__VI : 1;
                unsigned int   CB_TAP_WRREQ_VALID_READYB__VI : 1;
                unsigned int   CB_TAP_WRREQ_VALIDB_READY__VI : 1;
                unsigned int  CB_TAP_WRREQ_VALIDB_READYB__VI : 1;
                unsigned int    CB_TAP_RDREQ_VALID_READY__VI : 1;
                unsigned int   CB_TAP_RDREQ_VALID_READYB__VI : 1;
                unsigned int   CB_TAP_RDREQ_VALIDB_READY__VI : 1;
                unsigned int  CB_TAP_RDREQ_VALIDB_READYB__VI : 1;
                unsigned int      CM_FC_TILE_VALID_READY__VI : 1;
                unsigned int     CM_FC_TILE_VALID_READYB__VI : 1;
                unsigned int     CM_FC_TILE_VALIDB_READY__VI : 1;
                unsigned int    CM_FC_TILE_VALIDB_READYB__VI : 1;
                unsigned int   FC_CLEAR_QUAD_VALID_READY__VI : 1;
                unsigned int  FC_CLEAR_QUAD_VALID_READYB__VI : 1;
                unsigned int  FC_CLEAR_QUAD_VALIDB_READY__VI : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_13__SI__CI {
	struct {
		unsigned int                 TILE_INTFC_BUSY : 1;
		unsigned int                         MU_BUSY : 1;
		unsigned int                         TQ_BUSY : 1;
		unsigned int                         AC_BUSY : 1;
		unsigned int                        CRW_BUSY : 1;
		unsigned int                 CACHE_CTRL_BUSY : 1;
		unsigned int                   MC_WR_PENDING : 1;
		unsigned int                   FC_WR_PENDING : 1;
		unsigned int                   FC_RD_PENDING : 1;
		unsigned int                   EVICT_PENDING : 1;
		unsigned int              LAST_RD_ARB_WINNER : 1;
		unsigned int                        MU_STATE : 8;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_13__VI {
	struct {
                unsigned int  FC_PF_FC_KEYID_RDLAT_FIFO_FULL : 1;
                unsigned int           FC_DOC_QTILE_CAM_MISS : 1;
                unsigned int            FC_DOC_QTILE_CAM_HIT : 1;
                unsigned int           FC_DOC_CLINE_CAM_MISS : 1;
                unsigned int            FC_DOC_CLINE_CAM_HIT : 1;
                unsigned int       FC_DOC_OVERWROTE_1_SECTOR : 1;
                unsigned int      FC_DOC_OVERWROTE_2_SECTORS : 1;
                unsigned int      FC_DOC_OVERWROTE_3_SECTORS : 1;
                unsigned int      FC_DOC_OVERWROTE_4_SECTORS : 1;
                unsigned int             FC_PF_DCC_CACHE_HIT : 1;
                unsigned int        FC_PF_DCC_CACHE_TAG_MISS : 1;
                unsigned int     FC_PF_DCC_CACHE_SECTOR_MISS : 1;
                unsigned int FC_PF_DCC_CACHE_REEVICTION_STALL : 1;
                unsigned int FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL : 1;
                unsigned int FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL : 1;
                unsigned int FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL : 1;
                unsigned int FC_PF_DCC_CACHE_READ_OUTPUT_STALL : 1;
                unsigned int FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL : 1;
                unsigned int FC_PF_DCC_CACHE_ACK_OUTPUT_STALL : 1;
                unsigned int           FC_PF_DCC_CACHE_STALL : 1;
                unsigned int           FC_PF_DCC_CACHE_FLUSH : 1;
                unsigned int FC_PF_DCC_CACHE_SECTORS_FLUSHED : 1;
                unsigned int FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED : 1;
                unsigned int    FC_PF_DCC_CACHE_TAGS_FLUSHED : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_14__SI__CI {
	struct {
		unsigned int            TILE_RETIREMENT_BUSY : 1;
		unsigned int                        FOP_BUSY : 1;
		unsigned int                        LAT_BUSY : 1;
		unsigned int                  CACHE_CTL_BUSY : 1;
		unsigned int                       ADDR_BUSY : 1;
		unsigned int                      MERGE_BUSY : 1;
		unsigned int                       QUAD_BUSY : 1;
		unsigned int                       TILE_BUSY : 1;
		unsigned int                      CLEAR_BUSY : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_14__VI {
	struct {
                unsigned int FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT : 11;
                unsigned int FC_MC_DCC_READ_REQUESTS_IN_FLIGHT : 11;
                unsigned int     CC_PF_DCC_BEYOND_TILE_SPLIT : 1;
                unsigned int           CC_PF_DCC_RDREQ_STALL : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_15__SI__CI {
	struct {
		unsigned int                 SURF_SYNC_STATE : 2;
		unsigned int                 SURF_SYNC_START : 1;
		unsigned int                         SF_BUSY : 1;
		unsigned int                         CS_BUSY : 1;
		unsigned int                         RB_BUSY : 1;
		unsigned int                         DS_BUSY : 1;
		unsigned int                         TB_BUSY : 1;
		unsigned int                         IB_BUSY : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_15__VI {
	struct {
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_2TO1 : 3;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_4TO1 : 2;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_4TO2 : 2;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_4TO3 : 2;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_6TO1 : 2;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_6TO2 : 2;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_6TO3 : 2;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_6TO4 : 2;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_6TO5 : 2;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_16__SI__CI {
	struct {
		unsigned int                MC_RDREQ_CREDITS : 6;
		unsigned int               LAST_RD_GRANT_VEC : 4;
		unsigned int                MC_WRREQ_CREDITS : 6;
		unsigned int               LAST_WR_GRANT_VEC : 4;
		unsigned int             CC_WRREQ_FIFO_EMPTY : 1;
		unsigned int             FC_WRREQ_FIFO_EMPTY : 1;
		unsigned int             CM_WRREQ_FIFO_EMPTY : 1;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_16__VI {
	struct {
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_8TO1 : 1;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_8TO2 : 1;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_8TO3 : 1;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_8TO4 : 1;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_8TO5 : 1;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_8TO6 : 1;
                unsigned int   CC_PF_DCC_COMPRESS_RATIO_8TO7 : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_17__SI__CI {
	struct {
		unsigned int                         CM_BUSY : 1;
		unsigned int                         FC_BUSY : 1;
		unsigned int                         CC_BUSY : 1;
		unsigned int                         BB_BUSY : 1;
		unsigned int                         MA_BUSY : 1;
		unsigned int                   CORE_SCLK_VLD : 1;
		unsigned int                   REG_SCLK1_VLD : 1;
		unsigned int                   REG_SCLK0_VLD : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_17__VI {
	struct {
		unsigned int                 TILE_INTFC_BUSY : 1;
		unsigned int                         MU_BUSY : 1;
		unsigned int                         TQ_BUSY : 1;
		unsigned int                         AC_BUSY : 1;
		unsigned int                        CRW_BUSY : 1;
		unsigned int                 CACHE_CTRL_BUSY : 1;
		unsigned int                   MC_WR_PENDING : 1;
		unsigned int                   FC_WR_PENDING : 1;
		unsigned int                   FC_RD_PENDING : 1;
		unsigned int                   EVICT_PENDING : 1;
		unsigned int              LAST_RD_ARB_WINNER : 1;
		unsigned int                        MU_STATE : 8;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_18__SI__CI {
	struct {
		unsigned int                        NOT_USED : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_18__VI {
	struct {
		unsigned int            TILE_RETIREMENT_BUSY : 1;
		unsigned int                        FOP_BUSY : 1;
		unsigned int                      CLEAR_BUSY : 1;
		unsigned int                        LAT_BUSY : 1;
		unsigned int                  CACHE_CTL_BUSY : 1;
		unsigned int                       ADDR_BUSY : 1;
		unsigned int                      MERGE_BUSY : 1;
		unsigned int                       QUAD_BUSY : 1;
		unsigned int                       TILE_BUSY : 1;
		unsigned int                        DCC_BUSY : 1;
		unsigned int                        DOC_BUSY : 1;
		unsigned int                        DAG_BUSY : 1;
		unsigned int                       DOC_STALL : 1;
		unsigned int                 DOC_QT_CAM_FULL : 1;
		unsigned int                 DOC_CL_CAM_FULL : 1;
		unsigned int          DOC_QUAD_PTR_FIFO_FULL : 1;
		unsigned int       DOC_SECTOR_MASK_FIFO_FULL : 1;
		unsigned int            DCS_READ_WINNER_LAST : 1;
		unsigned int             DCS_READ_EV_PENDING : 1;
		unsigned int            DCS_WRITE_CC_PENDING : 1;
		unsigned int             DCS_READ_CC_PENDING : 1;
		unsigned int            DCS_WRITE_MC_PENDING : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_2 {
	struct {
                unsigned int FC_CLEAR_QUAD_VALIDB_READYB__VI : 1;
                unsigned int     FC_QUAD_RESIDENCY_STALL__VI : 1;
                unsigned int  FC_CC_QUADFRAG_VALID_READY__VI : 1;
                unsigned int FC_CC_QUADFRAG_VALID_READYB__VI : 1;
                unsigned int FC_CC_QUADFRAG_VALIDB_READY__VI : 1;
                unsigned int FC_CC_QUADFRAG_VALIDB_READYB__VI : 1;
                unsigned int          FOP_IN_VALID_READY__VI : 1;
                unsigned int         FOP_IN_VALID_READYB__VI : 1;
                unsigned int         FOP_IN_VALIDB_READY__VI : 1;
                unsigned int        FOP_IN_VALIDB_READYB__VI : 1;
                unsigned int         FOP_FMASK_RAW_STALL__VI : 1;
                unsigned int      FOP_FMASK_BYPASS_STALL__VI : 1;
                unsigned int   CC_IB_TB_FRAG_VALID_READY__VI : 1;
                unsigned int  CC_IB_TB_FRAG_VALID_READYB__VI : 1;
                unsigned int  CC_IB_TB_FRAG_VALIDB_READY__VI : 1;
                unsigned int CC_IB_TB_FRAG_VALIDB_READYB__VI : 1;
                unsigned int   CC_IB_SR_FRAG_VALID_READY__VI : 1;
                unsigned int  CC_IB_SR_FRAG_VALID_READYB__VI : 1;
                unsigned int  CC_IB_SR_FRAG_VALIDB_READY__VI : 1;
                unsigned int CC_IB_SR_FRAG_VALIDB_READYB__VI : 1;
                unsigned int CC_RB_BC_EVENFRAG_VALID_READY__VI : 1;
                unsigned int CC_RB_BC_EVENFRAG_VALID_READYB__VI : 1;
                unsigned int CC_RB_BC_EVENFRAG_VALIDB_READY__VI : 1;
                unsigned int CC_RB_BC_EVENFRAG_VALIDB_READYB__VI : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_HW_CONTROL {
	struct {
                unsigned int            CM_CACHE_EVICT_POINT : 4;
                unsigned int                                 : 2;
                unsigned int            FC_CACHE_EVICT_POINT : 4;
                unsigned int                                 : 2;
                unsigned int            CC_CACHE_EVICT_POINT : 4;
                unsigned int      ALLOW_MRT_WITH_DUAL_SOURCE : 1;
                unsigned int                                 : 1;
                unsigned int DISABLE_INTNORM_LE11BPC_CLAMPING__CI__VI : 1;
                unsigned int                 FORCE_NEEDS_DST : 1;
                unsigned int             FORCE_ALWAYS_TOGGLE : 1;
                unsigned int DISABLE_BLEND_OPT_RESULT_EQ_DEST__CI__VI : 1;
                unsigned int         DISABLE_FULL_WRITE_MASK : 1;
                unsigned int DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG : 1;
                unsigned int   DISABLE_BLEND_OPT_DONT_RD_DST : 1;
                unsigned int        DISABLE_BLEND_OPT_BYPASS : 1;
                unsigned int DISABLE_BLEND_OPT_DISCARD_PIXEL : 1;
                unsigned int DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED : 1;
                unsigned int PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT : 1;
                unsigned int PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT : 1;
                unsigned int DISABLE_CC_IB_SERIALIZER_STATE_OPT : 1;
                unsigned int DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_HW_CONTROL_1 {
	struct {
		unsigned int               CM_CACHE_NUM_TAGS : 5;
		unsigned int               FC_CACHE_NUM_TAGS : 6;
		unsigned int               CC_CACHE_NUM_TAGS : 6;
		unsigned int              CM_TILE_FIFO_DEPTH : 9;
		unsigned int                    CHICKEN_BITS : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_HW_CONTROL_2__CI {
	struct {
		unsigned int          CC_EVEN_ODD_FIFO_DEPTH : 8;
		unsigned int        FC_RDLAT_TILE_FIFO_DEPTH : 7;
		unsigned int        FC_RDLAT_QUAD_FIFO_DEPTH : 8;
		unsigned int                                 : 1;
		unsigned int                    CHICKEN_BITS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_HW_CONTROL_2__VI {
	struct {
		unsigned int          CC_EVEN_ODD_FIFO_DEPTH : 8;
		unsigned int        FC_RDLAT_TILE_FIFO_DEPTH : 7;
		unsigned int        FC_RDLAT_QUAD_FIFO_DEPTH : 8;
		unsigned int                                 : 1;
		unsigned int     DRR_ASSUMED_FIFO_DEPTH_DIV8 : 4;
		unsigned int                    CHICKEN_BITS : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_HW_CONTROL_2__SI {
	struct {
		unsigned int          CC_EVEN_ODD_FIFO_DEPTH : 8;
		unsigned int        FC_RDLAT_TILE_FIFO_DEPTH : 7;
		unsigned int        FC_RDLAT_QUAD_FIFO_DEPTH : 8;
		unsigned int                    CHICKEN_BITS : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_HW_CONTROL_3__CI__VI {
	struct {
                unsigned int DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL : 1;
                unsigned int RAM_ADDRESS_CONFLICTS_DISALLOWED__VI : 1;
                unsigned int DISABLE_FAST_CLEAR_FETCH_OPT__VI : 1;
                unsigned int DISABLE_QUAD_MARKER_DROP_STOP__VI : 1;
                unsigned int DISABLE_OVERWRITE_COMBINER_CAM_CLR__VI : 1;
                unsigned int DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__VI : 1;
                unsigned int DISABLE_CC_CACHE_OVWR_KEY_MOD__VI : 1;
                unsigned int DISABLE_CC_CACHE_PANIC_GATING__VI : 1;
                unsigned int DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__VI : 1;
                unsigned int SPLIT_ALL_FAST_MODE_TRANSFERS__VI : 1;
                unsigned int   DISABLE_SHADER_BLEND_OPTS__VI : 1;
                unsigned int DISABLE_CMASK_LAST_QUAD_INSERTION__VI : 1;
                unsigned int DISABLE_ROP3_FIXES_OF_BUG_511967__VI : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER0_SELECT0__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 9;
                unsigned int                                 : 1;
                unsigned int                       PERF_SEL3 : 9;
                unsigned int                                 : 5;
                unsigned int                      PERF_MODE3 : 4;
                unsigned int                      PERF_MODE2 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER0_SELECT1__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 1;
                unsigned int                       PERF_SEL1 : 9;
                unsigned int                                 : 1;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER1_SELECT0__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER1_SELECT1__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 19;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER2_SELECT0__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER2_SELECT1__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER2_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 19;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER3_SELECT0__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER3_SELECT1__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER3_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 19;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_PERFCOUNTER_FILTER__CI__VI {
	struct {
                unsigned int                OP_FILTER_ENABLE : 1;
                unsigned int                   OP_FILTER_SEL : 3;
                unsigned int            FORMAT_FILTER_ENABLE : 1;
                unsigned int               FORMAT_FILTER_SEL : 5;
                unsigned int             CLEAR_FILTER_ENABLE : 1;
                unsigned int                CLEAR_FILTER_SEL : 1;
                unsigned int               MRT_FILTER_ENABLE : 1;
                unsigned int                  MRT_FILTER_SEL : 3;
                unsigned int                                 : 1;
                unsigned int       NUM_SAMPLES_FILTER_ENABLE : 1;
                unsigned int          NUM_SAMPLES_FILTER_SEL : 3;
                unsigned int     NUM_FRAGMENTS_FILTER_ENABLE : 1;
                unsigned int        NUM_FRAGMENTS_FILTER_SEL : 2;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_SHADER_MASK {
	struct {
		unsigned int                  OUTPUT0_ENABLE : 4;
		unsigned int                  OUTPUT1_ENABLE : 4;
		unsigned int                  OUTPUT2_ENABLE : 4;
		unsigned int                  OUTPUT3_ENABLE : 4;
		unsigned int                  OUTPUT4_ENABLE : 4;
		unsigned int                  OUTPUT5_ENABLE : 4;
		unsigned int                  OUTPUT6_ENABLE : 4;
		unsigned int                  OUTPUT7_ENABLE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_TARGET_MASK {
	struct {
		unsigned int                  TARGET0_ENABLE : 4;
		unsigned int                  TARGET1_ENABLE : 4;
		unsigned int                  TARGET2_ENABLE : 4;
		unsigned int                  TARGET3_ENABLE : 4;
		unsigned int                  TARGET4_ENABLE : 4;
		unsigned int                  TARGET5_ENABLE : 4;
		unsigned int                  TARGET6_ENABLE : 4;
		unsigned int                  TARGET7_ENABLE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_DRM_ID_STRAPS {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                       DEVICE_ID : 16;
		unsigned int                    MAJOR_REV_ID : 4;
		unsigned int                    MINOR_REV_ID : 4;
		unsigned int                      ATI_REV_ID : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_GC_EDC_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                         DIS_EDC : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_GC_PRIM_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 15;
                unsigned int                     INACTIVE_IA : 2;
                unsigned int                                 : 6;
                unsigned int                 INACTIVE_VGT_PA : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_GC_SHADER_ARRAY_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int               DPFP_RATE__SI__CI : 2;
                unsigned int     SQC_BALANCE_DISABLE__SI__CI : 1;
                unsigned int                HALF_LDS__SI__CI : 1;
                unsigned int                                 : 11;
                unsigned int                    INACTIVE_CUS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_GC_SHADER_ARRAY_CONFIG__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 14;
		unsigned int                    INACTIVE_CUS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_GIO_IOCCFG_FUSES__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                       NB_REV_ID : 10;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_GIO_IOC_FUSES__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                       IOC_FUSES : 5;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_MC_MAX_CHANNEL {
	struct {
		unsigned int                                 : 1;
		unsigned int                        NOOFCHAN : 4;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_RB_BACKEND_DISABLE {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 15;
		unsigned int                 BACKEND_DISABLE : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_RB_DAISY_CHAIN {
	struct {
		unsigned int                            RB_0 : 4;
		unsigned int                            RB_1 : 4;
		unsigned int                            RB_2 : 4;
		unsigned int                            RB_3 : 4;
		unsigned int                            RB_4 : 4;
		unsigned int                            RB_5 : 4;
		unsigned int                            RB_6 : 4;
		unsigned int                            RB_7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_RB_REDUNDANCY__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 7;
                unsigned int                      FAILED_RB0 : 4;
                unsigned int                  EN_REDUNDANCY0 : 1;
                unsigned int                                 : 3;
                unsigned int                      FAILED_RB1 : 4;
                unsigned int                  EN_REDUNDANCY1 : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_RB_REDUNDANCY__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 15;
		unsigned int                       FAILED_RB : 3;
		unsigned int                                 : 12;
		unsigned int                   EN_REDUNDANCY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_RCU_FUSES__CI {
	struct {
		unsigned int                                 : 1;
		unsigned int                         GPU_DIS : 1;
		unsigned int                   DEBUG_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int                EFUSE_RD_DISABLE : 1;
		unsigned int              CG_RST_GLB_REQ_DIS : 1;
		unsigned int                    DRV_RST_MODE : 1;
		unsigned int                         ROM_DIS : 1;
		unsigned int                 JPC_REP_DISABLE : 1;
		unsigned int                RCU_BREAK_POINT1 : 1;
		unsigned int                RCU_BREAK_POINT2 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                  PHY_FUSE_VALID : 1;
		unsigned int             SMU_IOC_MST_DISABLE : 1;
		unsigned int              FCH_LOCKOUT_ENABLE : 1;
		unsigned int         FCH_XFIRE_FILTER_ENABLE : 1;
		unsigned int                   XFIRE_DISABLE : 1;
		unsigned int               SAMU_FUSE_DISABLE : 1;
		unsigned int         BIF_RST_POLLING_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int                  MEM_HARDREP_EN : 1;
		unsigned int               PCIE_INIT_DISABLE : 1;
		unsigned int                    DSMU_DISABLE : 1;
		unsigned int                       RCU_SPARE : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_RCU_FUSES__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                         GPU_DIS : 1;
		unsigned int                   DEBUG_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int                EFUSE_RD_DISABLE : 1;
		unsigned int              CG_RST_GLB_REQ_DIS : 1;
		unsigned int                    DRV_RST_MODE : 1;
		unsigned int                         ROM_DIS : 1;
		unsigned int                 JPC_REP_DISABLE : 1;
		unsigned int                RCU_BREAK_POINT1 : 1;
		unsigned int                RCU_BREAK_POINT2 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int             SMU_IOC_MST_DISABLE : 1;
		unsigned int              FCH_LOCKOUT_ENABLE : 1;
		unsigned int         FCH_XFIRE_FILTER_ENABLE : 1;
		unsigned int                   XFIRE_DISABLE : 1;
		unsigned int               SAMU_FUSE_DISABLE : 1;
		unsigned int         BIF_RST_POLLING_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int                  MEM_HARDREP_EN : 1;
		unsigned int               PCIE_INIT_DISABLE : 1;
		unsigned int                    DSMU_DISABLE : 1;
		unsigned int                  WRP_FUSE_VALID : 1;
		unsigned int                  PHY_FUSE_VALID : 1;
		unsigned int                       RCU_SPARE : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_SCLK_VID_FUSES__CI__VI {
	struct {
                unsigned int                        SClkVid0 : 8;
                unsigned int                        SClkVid1 : 8;
                unsigned int                        SClkVid2 : 8;
                unsigned int                        SClkVid3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_SMU_MISC_FUSES__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                IOMMU_V2_DISABLE : 1;
                unsigned int                      MinSClkDid : 7;
                unsigned int                      MISC_SPARE : 2;
                unsigned int              PostResetGnbClkDid : 7;
                unsigned int              L2IMU_tn2_dtc_half : 1;
                unsigned int              L2IMU_tn2_ptc_half : 1;
                unsigned int              L2IMU_tn2_itc_half : 1;
                unsigned int              L2IMU_tn2_pdc_half : 1;
                unsigned int               L2IMU_tn2_ptc_dis : 1;
                unsigned int               L2IMU_tn2_itc_dis : 1;
                unsigned int                                 : 3;
                unsigned int                     VCE_DISABLE : 1;
                unsigned int               IOC_IOMMU_DISABLE : 1;
                unsigned int                       GNB_SPARE : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_SMU_TST_EFUSE1_MISC__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                       RF_RM_6_2 : 5;
                unsigned int                             RME : 1;
                unsigned int                   MBIST_DISABLE : 1;
                unsigned int             HARD_REPAIR_DISABLE : 1;
                unsigned int             SOFT_REPAIR_DISABLE : 1;
                unsigned int                         GPU_DIS : 1;
                unsigned int              SMS_PWRDWN_DISABLE : 1;
                unsigned int                 CRBBMP1500_DISA : 1;
                unsigned int                 CRBBMP1500_DISB : 1;
                unsigned int                          RM_RF8 : 1;
                unsigned int                                 : 7;
                unsigned int                      DFT_SPARE1 : 1;
                unsigned int                      DFT_SPARE2 : 1;
                unsigned int                      DFT_SPARE3 : 1;
                unsigned int                     VCE_DISABLE : 1;
                unsigned int                DCE_SCAN_DISABLE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_SQC_BANK_DISABLE {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 15;
                unsigned int               SQC0_BANK_DISABLE : 4;
                unsigned int               SQC1_BANK_DISABLE : 4;
                unsigned int       SQC2_BANK_DISABLE__CI__VI : 4;
                unsigned int       SQC3_BANK_DISABLE__CI__VI : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_SYS_RB_BACKEND_DISABLE {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 15;
		unsigned int                 BACKEND_DISABLE : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_SYS_RB_REDUNDANCY__SI__CI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 15;
		unsigned int                       FAILED_RB : 3;
		unsigned int                                 : 12;
		unsigned int                   EN_REDUNDANCY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_SYS_RB_REDUNDANCY__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                      FAILED_RB0 : 4;
		unsigned int                  EN_REDUNDANCY0 : 1;
		unsigned int                                 : 3;
		unsigned int                      FAILED_RB1 : 4;
		unsigned int                  EN_REDUNDANCY1 : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_THM_STRAPS0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                     TMON0_BGADJ : 8;
                unsigned int                     TMON1_BGADJ : 8;
                unsigned int              TMON_CMON_FUSE_SEL : 1;
                unsigned int                         NUM_ACQ : 3;
                unsigned int                    TMON_CLK_SEL : 3;
                unsigned int              TMON_CONFIG_SOURCE : 1;
                unsigned int                     CTF_DISABLE : 1;
                unsigned int                   TMON0_DISABLE : 1;
                unsigned int                   TMON1_DISABLE : 1;
                unsigned int                   TMON2_DISABLE : 1;
                unsigned int                   TMON3_DISABLE : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_TST_ID_STRAPS__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 3;
                unsigned int                       DEVICE_ID : 16;
                unsigned int                    MAJOR_REV_ID : 4;
                unsigned int                    MINOR_REV_ID : 4;
                unsigned int                  ATI_REV_ID__VI : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU0_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU0_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU0_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU0_TA_SQC_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             SQC : 7;
                unsigned int                    SQC_OVERRIDE : 1;
                unsigned int               SQC_BUSY_OVERRIDE : 2;
                unsigned int                 SQC_LS_OVERRIDE : 1;
                unsigned int           SQC_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU0_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU10_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU10_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU10_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU10_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU10_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU11_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU11_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU11_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU11_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU11_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU12_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU12_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU12_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU12_TA_SQC_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             SQC : 7;
                unsigned int                    SQC_OVERRIDE : 1;
                unsigned int               SQC_BUSY_OVERRIDE : 2;
                unsigned int                 SQC_LS_OVERRIDE : 1;
                unsigned int           SQC_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU12_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU13_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU13_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU13_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU13_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU13_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU14_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU14_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU14_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU14_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU14_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU15_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU15_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU15_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU15_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU15_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU1_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU1_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU1_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU1_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU1_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU2_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU2_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU2_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU2_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU2_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU3_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU3_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU3_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU3_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU3_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU4_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU4_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU4_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU4_TA_SQC_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             SQC : 7;
                unsigned int                    SQC_OVERRIDE : 1;
                unsigned int               SQC_BUSY_OVERRIDE : 2;
                unsigned int                 SQC_LS_OVERRIDE : 1;
                unsigned int           SQC_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU4_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU5_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU5_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU5_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU5_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU5_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU6_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU6_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU6_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU6_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU6_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU7_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU7_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU7_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU7_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU7_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU8_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU8_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU8_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU8_TA_SQC_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             SQC : 7;
                unsigned int                    SQC_OVERRIDE : 1;
                unsigned int               SQC_BUSY_OVERRIDE : 2;
                unsigned int                 SQC_LS_OVERRIDE : 1;
                unsigned int           SQC_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU8_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU9_LDS_SQ_CTRL_REG__CI__VI {
	struct {
                unsigned int                             LDS : 7;
                unsigned int                    LDS_OVERRIDE : 1;
                unsigned int               LDS_BUSY_OVERRIDE : 2;
                unsigned int                 LDS_LS_OVERRIDE : 1;
                unsigned int           LDS_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                              SQ : 7;
                unsigned int                     SQ_OVERRIDE : 1;
                unsigned int                SQ_BUSY_OVERRIDE : 2;
                unsigned int                  SQ_LS_OVERRIDE : 1;
                unsigned int            SQ_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU9_SP0_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP00 : 7;
                unsigned int                   SP00_OVERRIDE : 1;
                unsigned int              SP00_BUSY_OVERRIDE : 2;
                unsigned int                SP00_LS_OVERRIDE : 1;
                unsigned int          SP00_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP01 : 7;
                unsigned int                   SP01_OVERRIDE : 1;
                unsigned int              SP01_BUSY_OVERRIDE : 2;
                unsigned int                SP01_LS_OVERRIDE : 1;
                unsigned int          SP01_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU9_SP1_CTRL_REG__CI__VI {
	struct {
                unsigned int                            SP10 : 7;
                unsigned int                   SP10_OVERRIDE : 1;
                unsigned int              SP10_BUSY_OVERRIDE : 2;
                unsigned int                SP10_LS_OVERRIDE : 1;
                unsigned int          SP10_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                            SP11 : 7;
                unsigned int                   SP11_OVERRIDE : 1;
                unsigned int              SP11_BUSY_OVERRIDE : 2;
                unsigned int                SP11_LS_OVERRIDE : 1;
                unsigned int          SP11_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU9_TA_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TA : 7;
                unsigned int                     TA_OVERRIDE : 1;
                unsigned int                TA_BUSY_OVERRIDE : 2;
                unsigned int                  TA_LS_OVERRIDE : 1;
                unsigned int            TA_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_CU9_TD_TCP_CTRL_REG__CI__VI {
	struct {
                unsigned int                              TD : 7;
                unsigned int                     TD_OVERRIDE : 1;
                unsigned int                TD_BUSY_OVERRIDE : 2;
                unsigned int                  TD_LS_OVERRIDE : 1;
                unsigned int            TD_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
                unsigned int                             TCP : 7;
                unsigned int                    TCP_OVERRIDE : 1;
                unsigned int               TCP_BUSY_OVERRIDE : 2;
                unsigned int                 TCP_LS_OVERRIDE : 1;
                unsigned int           TCP_SIMDBUSY_OVERRIDE : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_RD_CTRL_REG {
	struct {
		unsigned int                     ROW_MUX_SEL : 5;
		unsigned int                                 : 3;
		unsigned int                     REG_MUX_SEL : 5;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_RD_REG {
	struct {
		unsigned int                       READ_DATA : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_SM_CTRL_REG {
	struct {
		unsigned int                    ON_SEQ_DELAY : 4;
		unsigned int                   OFF_SEQ_DELAY : 8;
		unsigned int                    MGCG_ENABLED : 1;
		unsigned int                                 : 3;
		unsigned int                       BASE_MODE : 1;
		unsigned int                         SM_MODE : 3;
		unsigned int                  SM_MODE_ENABLE : 1;
		unsigned int                        OVERRIDE : 1;
		unsigned int                     LS_OVERRIDE : 1;
		unsigned int               ON_MONITOR_ADD_EN : 1;
		unsigned int                  ON_MONITOR_ADD : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_TCC_DISABLE {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 15;
		unsigned int                     TCC_DISABLE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTS_USER_TCC_DISABLE {
	struct {
		unsigned int                                 : 16;
		unsigned int                     TCC_DISABLE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_BCI_CLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                  CORE6_OVERRIDE : 1;
		unsigned int                  CORE5_OVERRIDE : 1;
		unsigned int                  CORE4_OVERRIDE : 1;
		unsigned int                  CORE3_OVERRIDE : 1;
		unsigned int                  CORE2_OVERRIDE : 1;
		unsigned int                  CORE1_OVERRIDE : 1;
		unsigned int                  CORE0_OVERRIDE : 1;
		unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_CPC_CLK_CTRL__CI__VI {
	struct {
                unsigned int                        ON_DELAY : 4;
                unsigned int                  OFF_HYSTERESIS : 8;
                unsigned int                                 : 17;
                unsigned int       SOFT_OVERRIDE_PERFMON__VI : 1;
                unsigned int               SOFT_OVERRIDE_DYN : 1;
                unsigned int               SOFT_OVERRIDE_REG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_CPF_CLK_CTRL__CI__VI {
	struct {
                unsigned int                        ON_DELAY : 4;
                unsigned int                  OFF_HYSTERESIS : 8;
                unsigned int                                 : 17;
                unsigned int       SOFT_OVERRIDE_PERFMON__VI : 1;
                unsigned int               SOFT_OVERRIDE_DYN : 1;
                unsigned int               SOFT_OVERRIDE_REG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_CP_CLK_CTRL {
	struct {
                unsigned int                        ON_DELAY : 4;
                unsigned int                  OFF_HYSTERESIS : 8;
                unsigned int                                 : 17;
                unsigned int       SOFT_OVERRIDE_PERFMON__VI : 1;
                unsigned int               SOFT_OVERRIDE_DYN : 1;
                unsigned int               SOFT_OVERRIDE_REG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_GDS_CLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_IA_CLK_CTRL__CI__VI {
	struct {
                unsigned int                        ON_DELAY : 4;
                unsigned int                  OFF_HYSTERESIS : 8;
                unsigned int                                 : 12;
                unsigned int                  SOFT_OVERRIDE7 : 1;
                unsigned int                     PERF_ENABLE : 1;
                unsigned int                      DBG_ENABLE : 1;
                unsigned int                  SOFT_OVERRIDE4 : 1;
                unsigned int                  SOFT_OVERRIDE3 : 1;
                unsigned int                  SOFT_OVERRIDE2 : 1;
                unsigned int                   CORE_OVERRIDE : 1;
                unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_IA_CLK_CTRL__SI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                     PERF_ENABLE : 1;
		unsigned int                      DBG_ENABLE : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                                 : 1;
		unsigned int                   CORE_OVERRIDE : 1;
		unsigned int                                 : 1;
		unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_PA_CLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                 SU_CLK_OVERRIDE : 1;
		unsigned int                 CL_CLK_OVERRIDE : 1;
		unsigned int                REG_CLK_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_PC_CLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 6;
		unsigned int                GRP5_CG_OFF_HYST : 6;
		unsigned int                GRP5_CG_OVERRIDE : 1;
		unsigned int            BACK_CLK_ON_OVERRIDE : 1;
		unsigned int           FRONT_CLK_ON_OVERRIDE : 1;
		unsigned int                  CORE3_OVERRIDE : 1;
		unsigned int                  CORE2_OVERRIDE : 1;
		unsigned int                  CORE1_OVERRIDE : 1;
		unsigned int                  CORE0_OVERRIDE : 1;
		unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_RLC_CLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 18;
		unsigned int               SOFT_OVERRIDE_DYN : 1;
		unsigned int               SOFT_OVERRIDE_REG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_ROM_CLK_CTRL0 {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 18;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SC_CLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SPI_CLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 6;
		unsigned int                GRP5_CG_OFF_HYST : 6;
		unsigned int                GRP5_CG_OVERRIDE : 1;
		unsigned int                                 : 1;
		unsigned int             ALL_CLK_ON_OVERRIDE : 1;
		unsigned int                   GRP3_OVERRIDE : 1;
		unsigned int                   GRP2_OVERRIDE : 1;
		unsigned int                   GRP1_OVERRIDE : 1;
		unsigned int                   GRP0_OVERRIDE : 1;
		unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SQG_CLK_CTRL {
	struct {
                unsigned int                        ON_DELAY : 4;
                unsigned int                  OFF_HYSTERESIS : 8;
                unsigned int                                 : 16;
                unsigned int             TTRACE_OVERRIDE__VI : 1;
                unsigned int            PERFMON_OVERRIDE__VI : 1;
                unsigned int                   CORE_OVERRIDE : 1;
                unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SQ_CLK_CTRL {
	struct {
                unsigned int                        ON_DELAY : 4;
                unsigned int                  OFF_HYSTERESIS : 8;
                unsigned int                                 : 17;
                unsigned int            PERFMON_OVERRIDE__VI : 1;
                unsigned int                   CORE_OVERRIDE : 1;
                unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SX_CLK_CTRL0 {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SX_CLK_CTRL1__SI__CI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SX_CLK_CTRL1__VI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                          DBG_EN : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SX_CLK_CTRL2__SI__CI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SX_CLK_CTRL2__VI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                          DBG_EN : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SX_CLK_CTRL3__SI__CI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SX_CLK_CTRL3__VI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                          DBG_EN : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SX_CLK_CTRL4__SI__CI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_SX_CLK_CTRL4__VI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                          DBG_EN : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_TCI_CLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_TCP_CLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_VGT_CLK_CTRL__SI__CI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                     PERF_ENABLE : 1;
		unsigned int                      DBG_ENABLE : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                     GS_OVERRIDE : 1;
		unsigned int                   CORE_OVERRIDE : 1;
		unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_VGT_CLK_CTRL__VI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                     PERF_ENABLE : 1;
		unsigned int                      DBG_ENABLE : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                   TESS_OVERRIDE : 1;
		unsigned int                     GS_OVERRIDE : 1;
		unsigned int                   CORE_OVERRIDE : 1;
		unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_WD_CLK_CTRL__CI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                     PERF_ENABLE : 1;
		unsigned int                      DBG_ENABLE : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                    ADC_OVERRIDE : 1;
		unsigned int                   CORE_OVERRIDE : 1;
		unsigned int             RBIU_INPUT_OVERRIDE : 1;
		unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CGTT_WD_CLK_CTRL__VI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                     PERF_ENABLE : 1;
		unsigned int                      DBG_ENABLE : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                   TESS_OVERRIDE : 1;
		unsigned int                   CORE_OVERRIDE : 1;
		unsigned int             RBIU_INPUT_OVERRIDE : 1;
		unsigned int                    REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_ACLK_CNTL__CI__VI {
	struct {
                unsigned int                    ACLK_DIVIDER : 7;
                unsigned int                                 : 1;
                unsigned int                ACLK_DIR_CNTL_EN : 1;
                unsigned int               ACLK_DIR_CNTL_TOG : 1;
                unsigned int           ACLK_DIR_CNTL_DIVIDER : 7;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_ACPI_CNTL__CI__VI {
	struct {
                unsigned int                   SCLK_ACPI_DIV : 7;
                unsigned int                SCLK_CHANGE_SKIP : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_CLKPIN_CNTL_2__CI__VI {
	struct {
                unsigned int                     ENABLE_XCLK : 1;
                unsigned int                                 : 2;
                unsigned int             FORCE_BIF_REFCLK_EN : 1;
                unsigned int                                 : 4;
                unsigned int                MUX_TCLK_TO_XCLK : 1;
                unsigned int                                 : 5;
                unsigned int                  XO_IN_OSCIN_EN : 1;
                unsigned int              XO_IN_ICORE_CLK_OE : 1;
                unsigned int                  XO_IN_CML_RXEN : 1;
                unsigned int              XO_IN_BIDIR_CML_OE : 1;
                unsigned int                 XO_IN2_OSCIN_EN : 1;
                unsigned int             XO_IN2_ICORE_CLK_OE : 1;
                unsigned int                 XO_IN2_CML_RXEN : 1;
                unsigned int             XO_IN2_BIDIR_CML_OE : 1;
                unsigned int                        CML_CTRL : 2;
                unsigned int                       CLK_SPARE : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_CLKPIN_CNTL__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                   XTALIN_DIVIDE : 1;
                unsigned int                    BCLK_AS_XCLK : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_CLKPIN_CNTL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                   XTALIN_DIVIDE : 1;
		unsigned int                                 : 3;
		unsigned int                    BCLK_AS_XCLK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_DCLK_CNTL__CI__VI {
	struct {
                unsigned int                    DCLK_DIVIDER : 7;
                unsigned int                                 : 1;
                unsigned int                DCLK_DIR_CNTL_EN : 1;
                unsigned int               DCLK_DIR_CNTL_TOG : 1;
                unsigned int           DCLK_DIR_CNTL_DIVIDER : 7;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_DCLK_STATUS__CI__VI {
	struct {
                unsigned int                     DCLK_STATUS : 1;
                unsigned int           DCLK_DIR_CNTL_DONETOG : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_DISPLAY_GAP_CNTL2__CI__VI {
	struct {
                unsigned int                  VBI_PREDICTION : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_DISPLAY_GAP_CNTL__CI__VI {
	struct {
                unsigned int                        DISP_GAP : 2;
                unsigned int                                 : 2;
                unsigned int                 VBI_TIMER_COUNT : 14;
                unsigned int                                 : 2;
                unsigned int                  VBI_TIMER_UNIT : 3;
                unsigned int                                 : 1;
                unsigned int                   DISP_GAP_MCHG : 2;
                unsigned int                                 : 2;
                unsigned int               VBI_TIMER_DISABLE : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_DISPLAY_GAP_CNTL__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                 VBI_TIMER_COUNT : 14;
		unsigned int                                 : 2;
		unsigned int                  VBI_TIMER_UNIT : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int               VBI_TIMER_DISABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_ECLK_CNTL__CI__VI {
	struct {
                unsigned int                    ECLK_DIVIDER : 7;
                unsigned int                                 : 1;
                unsigned int                ECLK_DIR_CNTL_EN : 1;
                unsigned int               ECLK_DIR_CNTL_TOG : 1;
                unsigned int           ECLK_DIR_CNTL_DIVIDER : 7;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_ECLK_STATUS__CI__VI {
	struct {
                unsigned int                     ECLK_STATUS : 1;
                unsigned int           ECLK_DIR_CNTL_DONETOG : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FDO_CTRL0 {
	struct {
		unsigned int                 FDO_STATIC_DUTY : 8;
		unsigned int                 FAN_SPINUP_DUTY : 8;
		unsigned int                  FDO_PWM_MANUAL : 1;
		unsigned int                  FDO_PWM_HYSTER : 6;
		unsigned int                 FDO_PWM_RAMP_EN : 1;
		unsigned int                    FDO_PWM_RAMP : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FDO_CTRL1 {
	struct {
		unsigned int                    FMAX_DUTY100 : 8;
		unsigned int                       FMIN_DUTY : 8;
		unsigned int                               M : 8;
		unsigned int                        RESERVED : 6;
		unsigned int                      FDO_PWRDNB : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FDO_CTRL2 {
	struct {
		unsigned int                            TMIN : 8;
		unsigned int                 FAN_SPINUP_TIME : 3;
		unsigned int                    FDO_PWM_MODE : 3;
		unsigned int                     TMIN_HYSTER : 3;
		unsigned int                            TMAX : 8;
		unsigned int              TACH_PWM_RESP_RATE : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FPS_CNT__CI {
	struct {
		unsigned int                         FPS_CNT : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FPS_CNT__VI {
	struct {
		unsigned int                         FPS_CNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FREQ_TRAN_VOTING_0__CI__VI {
	struct {
                unsigned int     BIF_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     HDP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ROM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  IH_SEM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    PDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     DRM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    IDCT_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ACP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    SDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     UVD_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     VCE_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int   DC_AZ_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     SAM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     AVP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_0_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_1_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_2_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_3_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_4_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_5_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_6_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_7_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_8_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_9_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     RLC_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FREQ_TRAN_VOTING_1__CI__VI {
	struct {
                unsigned int     BIF_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     HDP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ROM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  IH_SEM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    PDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     DRM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    IDCT_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ACP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    SDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     UVD_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     VCE_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int   DC_AZ_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     SAM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     AVP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_0_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_1_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_2_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_3_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_4_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_5_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_6_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_7_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_8_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_9_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     RLC_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FREQ_TRAN_VOTING_2__CI__VI {
	struct {
                unsigned int     BIF_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     HDP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ROM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  IH_SEM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    PDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     DRM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    IDCT_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ACP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    SDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     UVD_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     VCE_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int   DC_AZ_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     SAM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     AVP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_0_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_1_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_2_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_3_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_4_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_5_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_6_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_7_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_8_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_9_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     RLC_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FREQ_TRAN_VOTING_3__CI__VI {
	struct {
                unsigned int     BIF_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     HDP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ROM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  IH_SEM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    PDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     DRM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    IDCT_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ACP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    SDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     UVD_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     VCE_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int   DC_AZ_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     SAM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     AVP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_0_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_1_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_2_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_3_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_4_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_5_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_6_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_7_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_8_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_9_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     RLC_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FREQ_TRAN_VOTING_4__CI__VI {
	struct {
                unsigned int     BIF_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     HDP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ROM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  IH_SEM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    PDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     DRM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    IDCT_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ACP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    SDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     UVD_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     VCE_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int   DC_AZ_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     SAM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     AVP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_0_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_1_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_2_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_3_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_4_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_5_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_6_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_7_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_8_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_9_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     RLC_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FREQ_TRAN_VOTING_5__CI__VI {
	struct {
                unsigned int     BIF_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     HDP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ROM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  IH_SEM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    PDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     DRM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    IDCT_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ACP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    SDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     UVD_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     VCE_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int   DC_AZ_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     SAM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     AVP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_0_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_1_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_2_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_3_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_4_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_5_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_6_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_7_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_8_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_9_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     RLC_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FREQ_TRAN_VOTING_6__CI__VI {
	struct {
                unsigned int     BIF_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     HDP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ROM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  IH_SEM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    PDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     DRM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    IDCT_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ACP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    SDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     UVD_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     VCE_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int   DC_AZ_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     SAM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     AVP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_0_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_1_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_2_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_3_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_4_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_5_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_6_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_7_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_8_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_9_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     RLC_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FREQ_TRAN_VOTING_7__CI__VI {
	struct {
                unsigned int     BIF_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     HDP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ROM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  IH_SEM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    PDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     DRM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    IDCT_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     ACP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int    SDMA_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     UVD_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     VCE_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int   DC_AZ_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     SAM_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     AVP_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_0_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_1_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_2_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_3_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_4_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_5_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_6_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_7_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_8_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int  GRBM_9_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int     RLC_FREQ_THROTTLING_VOTE_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_FREQ_TRAN_VOTING__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_MULT_THERMAL_CTRL__SI__CI {
	struct {
                unsigned int                       TS_FILTER : 4;
                unsigned int                          UNUSED : 4;
                unsigned int                                 : 1;
                unsigned int               THERMAL_RANGE_RST : 1;
                unsigned int                                 : 10;
                unsigned int                        TEMP_SEL : 8;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_MULT_THERMAL_CTRL__VI {
	struct {
		unsigned int                       TS_FILTER : 4;
		unsigned int                          UNUSED : 5;
		unsigned int               THERMAL_RANGE_RST : 1;
		unsigned int                                 : 10;
		unsigned int                        TEMP_SEL : 8;
		unsigned int                 THM_READY_CLEAR : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_MULT_THERMAL_STATUS {
	struct {
		unsigned int                   ASIC_MAX_TEMP : 9;
		unsigned int                        CTF_TEMP : 9;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_FUNC_CNTL__SI__CI {
	struct {
		unsigned int                      SPLL_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                      SPLL_DIVEN : 1;
		unsigned int                  SPLL_BYPASS_EN : 1;
		unsigned int                    SPLL_REF_DIV : 6;
		unsigned int                                 : 10;
		unsigned int                     SPLL_PDIV_A : 7;
		unsigned int                                 : 1;
		unsigned int                      SPLL_BGADJ : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_FUNC_CNTL__VI {
	struct {
		unsigned int                      SPLL_RESET : 1;
		unsigned int                      SPLL_PWRON : 1;
		unsigned int                      SPLL_DIVEN : 1;
		unsigned int                  SPLL_BYPASS_EN : 1;
		unsigned int            SPLL_BYPASS_THRU_DFS : 1;
		unsigned int                    SPLL_REF_DIV : 6;
		unsigned int              SPLL_PDIV_A_UPDATE : 1;
		unsigned int                  SPLL_PDIV_A_EN : 1;
		unsigned int                   SPLL_BG_PWRON : 1;
		unsigned int                      SPLL_BGADJ : 4;
		unsigned int                     SPLL_PDIV_A : 7;
		unsigned int                   SPLL_REG_BIAS : 3;
		unsigned int              SPLL_OTEST_LOCK_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_FUNC_CNTL_2 {
	struct {
                unsigned int                    SCLK_MUX_SEL : 9;
                unsigned int                                 : 2;
                unsigned int                     SPLL_CTLREQ : 1;
                unsigned int                                 : 10;
                unsigned int             SPLL_BYPASS_CHG__VI : 1;
                unsigned int                 SPLL_CTLREQ_CHG : 1;
                unsigned int                  SPLL_RESET_CHG : 1;
                unsigned int              SPLL_BABY_STEP_CHG : 1;
                unsigned int                 SCLK_MUX_UPDATE : 1;
                unsigned int               SPLL_UNLOCK_CLEAR : 1;
                unsigned int                SPLL_CLKF_UPDATE : 1;
                unsigned int                                 : 1;
                unsigned int        SPLL_TEST_UNLOCK_CLR__VI : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_FUNC_CNTL_3 {
	struct {
		unsigned int                     SPLL_FB_DIV : 26;
		unsigned int                                 : 2;
		unsigned int                     SPLL_DITHEN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_FUNC_CNTL_4__SI__CI {
	struct {
		unsigned int              SPLL_SCLK_TEST_SEL : 3;
		unsigned int                                 : 1;
		unsigned int               SPLL_SCLK_EXT_SEL : 2;
		unsigned int                    SPLL_SCLK_EN : 2;
		unsigned int                      SPLL_SPARE : 10;
		unsigned int                                 : 3;
		unsigned int                TEST_FRAC_BYPASS : 1;
		unsigned int                                 : 1;
		unsigned int                      SPLL_ILOCK : 1;
		unsigned int                  SPLL_FBCLK_SEL : 1;
		unsigned int                SPLL_VCTRLADC_EN : 1;
		unsigned int                   SPLL_SCLK_EXT : 2;
		unsigned int                  SPLL_SPARE_EXT : 3;
		unsigned int             SPLL_VTOI_BIAS_CNTL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_FUNC_CNTL_4__VI {
	struct {
		unsigned int              SPLL_SCLK_TEST_SEL : 4;
		unsigned int                                 : 1;
		unsigned int               SPLL_SCLK_EXT_SEL : 2;
		unsigned int                    SPLL_SCLK_EN : 2;
		unsigned int                   SPLL_SSAMP_EN : 1;
		unsigned int                      SPLL_SPARE : 9;
		unsigned int                                 : 2;
		unsigned int                TEST_FRAC_BYPASS : 1;
		unsigned int                                 : 1;
		unsigned int                      SPLL_ILOCK : 1;
		unsigned int                  SPLL_FBCLK_SEL : 1;
		unsigned int                SPLL_VCTRLADC_EN : 1;
		unsigned int                   SPLL_SCLK_EXT : 2;
		unsigned int                  SPLL_SPARE_EXT : 3;
		unsigned int             SPLL_VTOI_BIAS_CNTL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_FUNC_CNTL_5__SI__CI {
	struct {
                unsigned int                FBDIV_SSC_BYPASS : 1;
                unsigned int                    RISEFBVCO_EN : 1;
                unsigned int                 PFD_RESET_CNTRL : 2;
                unsigned int                     RESET_TIMER : 2;
                unsigned int                 FAST_LOCK_CNTRL : 2;
                unsigned int                    FAST_LOCK_EN : 1;
                unsigned int                  RESET_ANTI_MUX : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_FUNC_CNTL_5__VI {
	struct {
                unsigned int                FBDIV_SSC_BYPASS : 1;
                unsigned int                    RISEFBVCO_EN : 1;
                unsigned int                 PFD_RESET_CNTRL : 2;
                unsigned int                     RESET_TIMER : 2;
                unsigned int                 FAST_LOCK_CNTRL : 2;
                unsigned int                    FAST_LOCK_EN : 1;
                unsigned int                  RESET_ANTI_MUX : 1;
                unsigned int                REFCLK_BYPASS_EN : 1;
                unsigned int                       PLLBYPASS : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_FUNC_CNTL_6__CI__VI {
	struct {
                unsigned int             SCLKMUX0_CLKOFF_CNT : 8;
                unsigned int             SCLKMUX1_CLKOFF_CNT : 8;
                unsigned int                SPLL_VCTL_EN__VI : 1;
                unsigned int          SPLL_VCTL_CNTRL_IN__VI : 4;
                unsigned int         SPLL_VCTL_CNTRL_OUT__VI : 4;
                unsigned int                SPLL_LF_CNTR__VI : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_SPREAD_SPECTRUM {
	struct {
                unsigned int                            SSEN : 2;
                unsigned int                                 : 2;
                unsigned int                            CLKS : 12;
                unsigned int                                 : 12;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_SPREAD_SPECTRUM_2 {
	struct {
		unsigned int                            CLKV : 26;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_STATIC_SCREEN_PARAMETER {
	struct {
		unsigned int         STATIC_SCREEN_THRESHOLD : 16;
		unsigned int    STATIC_SCREEN_THRESHOLD_UNIT : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_TACH_CTRL {
	struct {
		unsigned int                    EDGE_PER_REV : 3;
		unsigned int                   TARGET_PERIOD : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_TACH_STATUS {
	struct {
		unsigned int                     TACH_PERIOD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_THERMAL_CTRL {
	struct {
		unsigned int                   DPM_EVENT_SRC : 3;
		unsigned int                   THERM_INC_CLK : 1;
		unsigned int                           SPARE : 10;
		unsigned int                   DIG_THERM_DPM : 8;
		unsigned int                        RESERVED : 3;
		unsigned int                CTF_PAD_POLARITY : 1;
		unsigned int                      CTF_PAD_EN : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_THERMAL_INT {
	struct {
                unsigned int                   DIG_THERM_CTF : 8;
                unsigned int                  DIG_THERM_INTH : 8;
                unsigned int                  DIG_THERM_INTL : 8;
                unsigned int                  THERM_INT_MASK : 4;
                unsigned int                                 : 2;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_THERMAL_INT_CTRL__CI__VI {
	struct {
                unsigned int                  DIG_THERM_INTH : 8;
                unsigned int                  DIG_THERM_INTL : 8;
                unsigned int              GNB_TEMP_THRESHOLD : 8;
                unsigned int                 THERM_INTH_MASK : 1;
                unsigned int                 THERM_INTL_MASK : 1;
                unsigned int              THERM_TRIGGER_MASK : 1;
                unsigned int          THERM_TRIGGER_CNB_MASK : 1;
                unsigned int                THERM_GNB_HW_ENA : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_THERMAL_INT_ENA__CI__VI {
	struct {
                unsigned int                  THERM_INTH_SET : 1;
                unsigned int                  THERM_INTL_SET : 1;
                unsigned int               THERM_TRIGGER_SET : 1;
                unsigned int                  THERM_INTH_CLR : 1;
                unsigned int                  THERM_INTL_CLR : 1;
                unsigned int               THERM_TRIGGER_CLR : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_THERMAL_INT_STATUS__CI__VI {
	struct {
                unsigned int               THERM_INTH_DETECT : 1;
                unsigned int               THERM_INTL_DETECT : 1;
                unsigned int            THERM_TRIGGER_DETECT : 1;
                unsigned int        THERM_TRIGGER_CNB_DETECT : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_THERMAL_STATUS {
	struct {
		unsigned int                           SPARE : 9;
		unsigned int                    FDO_PWM_DUTY : 8;
		unsigned int                     THERM_ALERT : 1;
		unsigned int                      GEN_STATUS : 4;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_ULV_PARAMETER {
	struct {
		unsigned int                   ULV_THRESHOLD : 16;
		unsigned int              ULV_THRESHOLD_UNIT : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_VCLK_CNTL__CI__VI {
	struct {
                unsigned int                    VCLK_DIVIDER : 7;
                unsigned int                                 : 1;
                unsigned int                VCLK_DIR_CNTL_EN : 1;
                unsigned int               VCLK_DIR_CNTL_TOG : 1;
                unsigned int           VCLK_DIR_CNTL_DIVIDER : 7;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_VCLK_STATUS__CI__VI {
	struct {
                unsigned int                     VCLK_STATUS : 1;
                unsigned int           VCLK_DIR_CNTL_DONETOG : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CHUB_ATC_PERFCOUNTER0_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CHUB_ATC_PERFCOUNTER1_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CHUB_ATC_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                      COUNTER_HI : 16;
                unsigned int                   COMPARE_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CHUB_ATC_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                      COUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CI__VI {
	struct {
                unsigned int             PERF_COUNTER_SELECT : 4;
                unsigned int                                 : 4;
                unsigned int                   START_TRIGGER : 8;
                unsigned int                    STOP_TRIGGER : 8;
                unsigned int                      ENABLE_ANY : 1;
                unsigned int                       CLEAR_ALL : 1;
                unsigned int            STOP_ALL_ON_SATURATE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_BM {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_CD0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_CD1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_CD2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_CD3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_CK0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_CK1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_CK2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_CK3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_K0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_K1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_K2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_K3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_OFFSET {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_STATUS {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_BM {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_CD0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_CD1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_CD2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_CD3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_CK0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_CK1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_CK2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_CK3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_K0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_K1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_K2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_K3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_OFFSET {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_PORT_STATUS {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_BM {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_CD0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_CD1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_CD2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_CD3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_CK0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_CK1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_CK2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_CK3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_K0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_K1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_K2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_K3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_OFFSET {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_STATUS {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG00 {
	struct {
		unsigned int                     ALWAYS_ZERO : 8;
		unsigned int           clip_ga_bc_fifo_write : 1;
		unsigned int              su_clip_baryc_free : 2;
		unsigned int           clip_to_ga_fifo_write : 1;
		unsigned int            clip_to_ga_fifo_full : 1;
		unsigned int     primic_to_clprim_fifo_empty : 1;
		unsigned int      primic_to_clprim_fifo_full : 1;
		unsigned int        clip_to_outsm_fifo_empty : 1;
		unsigned int         clip_to_outsm_fifo_full : 1;
		unsigned int         vgt_to_clipp_fifo_empty : 1;
		unsigned int          vgt_to_clipp_fifo_full : 1;
		unsigned int         vgt_to_clips_fifo_empty : 1;
		unsigned int          vgt_to_clips_fifo_full : 1;
		unsigned int        clipcode_fifo_fifo_empty : 1;
		unsigned int              clipcode_fifo_full : 1;
		unsigned int    vte_out_clip_fifo_fifo_empty : 1;
		unsigned int     vte_out_clip_fifo_fifo_full : 1;
		unsigned int    vte_out_orig_fifo_fifo_empty : 1;
		unsigned int     vte_out_orig_fifo_fifo_full : 1;
		unsigned int      ccgen_to_clipcc_fifo_empty : 1;
		unsigned int       ccgen_to_clipcc_fifo_full : 1;
		unsigned int        clip_to_outsm_fifo_write : 1;
		unsigned int    vte_out_orig_fifo_fifo_write : 1;
		unsigned int         vgt_to_clipp_fifo_write : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG01 {
	struct {
		unsigned int                     ALWAYS_ZERO : 8;
		unsigned int             clip_extra_bc_valid : 3;
		unsigned int             clip_vert_vte_valid : 3;
		unsigned int clip_to_outsm_vertex_deallocate : 3;
		unsigned int   clip_to_outsm_deallocate_slot : 3;
		unsigned int    clip_to_outsm_null_primitive : 1;
		unsigned int vte_positions_vte_clip_vte_naninf_kill_2 : 1;
		unsigned int vte_positions_vte_clip_vte_naninf_kill_1 : 1;
		unsigned int vte_positions_vte_clip_vte_naninf_kill_0 : 1;
		unsigned int  vte_out_clip_rd_extra_bc_valid : 1;
		unsigned int vte_out_clip_rd_vte_naninf_kill : 1;
		unsigned int vte_out_clip_rd_vertex_store_indx : 2;
		unsigned int           clip_ga_bc_fifo_write : 1;
		unsigned int           clip_to_ga_fifo_write : 1;
		unsigned int vte_out_clip_fifo_fifo_advanceread : 1;
		unsigned int    vte_out_clip_fifo_fifo_empty : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG02 {
	struct {
		unsigned int             clip_extra_bc_valid : 3;
		unsigned int             clip_vert_vte_valid : 3;
		unsigned int     clip_to_outsm_clip_seq_indx : 2;
		unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
		unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
		unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
		unsigned int  clip_to_clipga_extra_bc_coords : 1;
		unsigned int  clip_to_clipga_vte_naninf_kill : 1;
		unsigned int     clip_to_outsm_end_of_packet : 1;
		unsigned int clip_to_outsm_first_prim_of_slot : 1;
		unsigned int      clip_to_outsm_clipped_prim : 1;
		unsigned int    clip_to_outsm_null_primitive : 1;
		unsigned int            clip_ga_bc_fifo_full : 1;
		unsigned int            clip_to_ga_fifo_full : 1;
		unsigned int           clip_ga_bc_fifo_write : 1;
		unsigned int           clip_to_ga_fifo_write : 1;
		unsigned int  clip_to_outsm_fifo_advanceread : 1;
		unsigned int        clip_to_outsm_fifo_empty : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG03 {
	struct {
		unsigned int clipsm0_clprim_to_clip_clip_code_or : 14;
		unsigned int clipsm0_clprim_to_clip_event_id : 6;
		unsigned int clipsm0_clprim_to_clip_state_var_indx : 3;
		unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
		unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
		unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
		unsigned int clipsm0_clprim_to_clip_end_of_packet : 1;
		unsigned int    clipsm0_clprim_to_clip_event : 1;
		unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
		unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG04 {
	struct {
		unsigned int                                 : 1;
		unsigned int clipsm0_clprim_to_clip_param_cache_indx_0 : 10;
		unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 6;
		unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 6;
		unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 6;
		unsigned int    clipsm0_clprim_to_clip_event : 1;
		unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
		unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG05 {
	struct {
		unsigned int clipsm1_clprim_to_clip_clip_code_or : 14;
		unsigned int clipsm1_clprim_to_clip_event_id : 6;
		unsigned int clipsm1_clprim_to_clip_state_var_indx : 3;
		unsigned int clipsm1_clprim_to_clip_clip_primitive : 1;
		unsigned int clipsm1_clprim_to_clip_deallocate_slot : 3;
		unsigned int clipsm1_clprim_to_clip_first_prim_of_slot : 1;
		unsigned int clipsm1_clprim_to_clip_end_of_packet : 1;
		unsigned int    clipsm1_clprim_to_clip_event : 1;
		unsigned int clipsm1_clprim_to_clip_null_primitive : 1;
		unsigned int clipsm1_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG06 {
	struct {
		unsigned int                                 : 1;
		unsigned int clipsm1_clprim_to_clip_param_cache_indx_0 : 10;
		unsigned int clipsm1_clprim_to_clip_vertex_store_indx_2 : 6;
		unsigned int clipsm1_clprim_to_clip_vertex_store_indx_1 : 6;
		unsigned int clipsm1_clprim_to_clip_vertex_store_indx_0 : 6;
		unsigned int    clipsm1_clprim_to_clip_event : 1;
		unsigned int clipsm1_clprim_to_clip_null_primitive : 1;
		unsigned int clipsm1_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG07 {
	struct {
		unsigned int clipsm2_clprim_to_clip_clip_code_or : 14;
		unsigned int clipsm2_clprim_to_clip_event_id : 6;
		unsigned int clipsm2_clprim_to_clip_state_var_indx : 3;
		unsigned int clipsm2_clprim_to_clip_clip_primitive : 1;
		unsigned int clipsm2_clprim_to_clip_deallocate_slot : 3;
		unsigned int clipsm2_clprim_to_clip_first_prim_of_slot : 1;
		unsigned int clipsm2_clprim_to_clip_end_of_packet : 1;
		unsigned int    clipsm2_clprim_to_clip_event : 1;
		unsigned int clipsm2_clprim_to_clip_null_primitive : 1;
		unsigned int clipsm2_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG08 {
	struct {
		unsigned int                                 : 1;
		unsigned int clipsm2_clprim_to_clip_param_cache_indx_0 : 10;
		unsigned int clipsm2_clprim_to_clip_vertex_store_indx_2 : 6;
		unsigned int clipsm2_clprim_to_clip_vertex_store_indx_1 : 6;
		unsigned int clipsm2_clprim_to_clip_vertex_store_indx_0 : 6;
		unsigned int    clipsm2_clprim_to_clip_event : 1;
		unsigned int clipsm2_clprim_to_clip_null_primitive : 1;
		unsigned int clipsm2_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG09 {
	struct {
		unsigned int clipsm3_clprim_to_clip_clip_code_or : 14;
		unsigned int clipsm3_clprim_to_clip_event_id : 6;
		unsigned int clipsm3_clprim_to_clip_state_var_indx : 3;
		unsigned int clipsm3_clprim_to_clip_clip_primitive : 1;
		unsigned int clipsm3_clprim_to_clip_deallocate_slot : 3;
		unsigned int clipsm3_clprim_to_clip_first_prim_of_slot : 1;
		unsigned int clipsm3_clprim_to_clip_end_of_packet : 1;
		unsigned int    clipsm3_clprim_to_clip_event : 1;
		unsigned int clipsm3_clprim_to_clip_null_primitive : 1;
		unsigned int clipsm3_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG10 {
	struct {
		unsigned int                                 : 1;
		unsigned int clipsm3_clprim_to_clip_param_cache_indx_0 : 10;
		unsigned int clipsm3_clprim_to_clip_vertex_store_indx_2 : 6;
		unsigned int clipsm3_clprim_to_clip_vertex_store_indx_1 : 6;
		unsigned int clipsm3_clprim_to_clip_vertex_store_indx_0 : 6;
		unsigned int    clipsm3_clprim_to_clip_event : 1;
		unsigned int clipsm3_clprim_to_clip_null_primitive : 1;
		unsigned int clipsm3_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG11 {
	struct {
		unsigned int    clipsm3_clip_to_clipga_event : 1;
		unsigned int    clipsm2_clip_to_clipga_event : 1;
		unsigned int    clipsm1_clip_to_clipga_event : 1;
		unsigned int    clipsm0_clip_to_clipga_event : 1;
		unsigned int clipsm3_clip_to_clipga_clip_primitive : 1;
		unsigned int clipsm2_clip_to_clipga_clip_primitive : 1;
		unsigned int clipsm1_clip_to_clipga_clip_primitive : 1;
		unsigned int clipsm0_clip_to_clipga_clip_primitive : 1;
		unsigned int clipsm3_clip_to_clipga_clip_to_outsm_cnt : 4;
		unsigned int clipsm2_clip_to_clipga_clip_to_outsm_cnt : 4;
		unsigned int clipsm1_clip_to_clipga_clip_to_outsm_cnt : 4;
		unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 4;
		unsigned int clipsm3_clip_to_clipga_prim_valid : 1;
		unsigned int clipsm2_clip_to_clipga_prim_valid : 1;
		unsigned int clipsm1_clip_to_clipga_prim_valid : 1;
		unsigned int clipsm0_clip_to_clipga_prim_valid : 1;
		unsigned int clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt : 1;
		unsigned int clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt : 1;
		unsigned int clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt : 1;
		unsigned int clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG12 {
	struct {
		unsigned int                     ALWAYS_ZERO : 8;
		unsigned int clip_priority_available_vte_out_clip : 5;
		unsigned int clip_priority_available_clip_verts : 5;
		unsigned int      clip_priority_seq_indx_out : 2;
		unsigned int     clip_priority_seq_indx_vert : 2;
		unsigned int     clip_priority_seq_indx_load : 2;
		unsigned int clipsm3_clprim_to_clip_clip_primitive : 1;
		unsigned int clipsm3_clprim_to_clip_prim_valid : 1;
		unsigned int clipsm2_clprim_to_clip_clip_primitive : 1;
		unsigned int clipsm2_clprim_to_clip_prim_valid : 1;
		unsigned int clipsm1_clprim_to_clip_clip_primitive : 1;
		unsigned int clipsm1_clprim_to_clip_prim_valid : 1;
		unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
		unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG13 {
	struct {
		unsigned int   clprim_in_back_state_var_indx : 3;
		unsigned int            point_clip_candidate : 1;
		unsigned int                   prim_nan_kill : 1;
		unsigned int           clprim_clip_primitive : 1;
		unsigned int           clprim_cull_primitive : 1;
		unsigned int                 prim_back_valid : 1;
		unsigned int vertval_bits_vertex_cc_next_valid : 4;
		unsigned int        clipcc_vertex_store_indx : 2;
		unsigned int    vte_out_orig_fifo_fifo_empty : 1;
		unsigned int        clipcode_fifo_fifo_empty : 1;
		unsigned int      ccgen_to_clipcc_fifo_empty : 1;
		unsigned int  clip_priority_seq_indx_out_cnt : 4;
		unsigned int      outsm_clr_rd_orig_vertices : 2;
		unsigned int        outsm_clr_rd_clipsm_wait : 1;
		unsigned int         outsm_clr_fifo_contents : 5;
		unsigned int             outsm_clr_fifo_full : 1;
		unsigned int      outsm_clr_fifo_advanceread : 1;
		unsigned int            outsm_clr_fifo_write : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG14 {
	struct {
		unsigned int clprim_in_back_vertex_store_indx_2 : 6;
		unsigned int clprim_in_back_vertex_store_indx_1 : 6;
		unsigned int clprim_in_back_vertex_store_indx_0 : 6;
		unsigned int outputclprimtoclip_null_primitive : 1;
		unsigned int    clprim_in_back_end_of_packet : 1;
		unsigned int clprim_in_back_first_prim_of_slot : 1;
		unsigned int  clprim_in_back_deallocate_slot : 3;
		unsigned int         clprim_in_back_event_id : 6;
		unsigned int            clprim_in_back_event : 1;
		unsigned int                 prim_back_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG15 {
	struct {
		unsigned int vertval_bits_vertex_vertex_store_msb : 16;
		unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 5;
		unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 5;
		unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 5;
		unsigned int          primic_to_clprim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG16 {
	struct {
		unsigned int              sm0_prim_end_state : 7;
		unsigned int                   sm0_ps_expand : 1;
		unsigned int               sm0_clip_vert_cnt : 5;
		unsigned int             sm0_vertex_clip_cnt : 5;
		unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
		unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
		unsigned int               sm0_current_state : 7;
		unsigned int sm0_clip_to_clipga_clip_to_outsm_cnt_eq0 : 1;
		unsigned int     sm0_clip_to_outsm_fifo_full : 1;
		unsigned int        sm0_highest_priority_seq : 1;
		unsigned int        sm0_outputcliptoclipga_0 : 1;
		unsigned int   sm0_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG17 {
	struct {
		unsigned int              sm1_prim_end_state : 7;
		unsigned int                   sm1_ps_expand : 1;
		unsigned int               sm1_clip_vert_cnt : 5;
		unsigned int             sm1_vertex_clip_cnt : 5;
		unsigned int    sm1_inv_to_clip_data_valid_1 : 1;
		unsigned int    sm1_inv_to_clip_data_valid_0 : 1;
		unsigned int               sm1_current_state : 7;
		unsigned int sm1_clip_to_clipga_clip_to_outsm_cnt_eq0 : 1;
		unsigned int     sm1_clip_to_outsm_fifo_full : 1;
		unsigned int        sm1_highest_priority_seq : 1;
		unsigned int        sm1_outputcliptoclipga_0 : 1;
		unsigned int   sm1_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG18 {
	struct {
		unsigned int              sm2_prim_end_state : 7;
		unsigned int                   sm2_ps_expand : 1;
		unsigned int               sm2_clip_vert_cnt : 5;
		unsigned int             sm2_vertex_clip_cnt : 5;
		unsigned int    sm2_inv_to_clip_data_valid_1 : 1;
		unsigned int    sm2_inv_to_clip_data_valid_0 : 1;
		unsigned int               sm2_current_state : 7;
		unsigned int sm2_clip_to_clipga_clip_to_outsm_cnt_eq0 : 1;
		unsigned int     sm2_clip_to_outsm_fifo_full : 1;
		unsigned int        sm2_highest_priority_seq : 1;
		unsigned int        sm2_outputcliptoclipga_0 : 1;
		unsigned int   sm2_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIPPER_DEBUG_REG19 {
	struct {
		unsigned int              sm3_prim_end_state : 7;
		unsigned int                   sm3_ps_expand : 1;
		unsigned int               sm3_clip_vert_cnt : 5;
		unsigned int             sm3_vertex_clip_cnt : 5;
		unsigned int    sm3_inv_to_clip_data_valid_1 : 1;
		unsigned int    sm3_inv_to_clip_data_valid_0 : 1;
		unsigned int               sm3_current_state : 7;
		unsigned int sm3_clip_to_clipga_clip_to_outsm_cnt_eq0 : 1;
		unsigned int     sm3_clip_to_outsm_fifo_full : 1;
		unsigned int        sm3_highest_priority_seq : 1;
		unsigned int        sm3_outputcliptoclipga_0 : 1;
		unsigned int   sm3_clprim_to_clip_prim_valid : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLKREQB_PAD_CNTL__CI__VI {
	struct {
                unsigned int                   CLKREQB_PAD_A : 1;
                unsigned int                 CLKREQB_PAD_SEL : 1;
                unsigned int                CLKREQB_PAD_MODE : 1;
                unsigned int               CLKREQB_PAD_SPARE : 2;
                unsigned int                 CLKREQB_PAD_SN0 : 1;
                unsigned int                 CLKREQB_PAD_SN1 : 1;
                unsigned int                 CLKREQB_PAD_SN2 : 1;
                unsigned int                 CLKREQB_PAD_SN3 : 1;
                unsigned int               CLKREQB_PAD_SLEWN : 1;
                unsigned int                CLKREQB_PAD_WAKE : 1;
                unsigned int              CLKREQB_PAD_SCHMEN : 1;
                unsigned int             CLKREQB_PAD_CNTL_EN : 1;
                unsigned int               CLKREQB_PAD_Y__VI : 1;
                unsigned int                                 : 10;
                unsigned int  CLKREQB_PERF_COUNTER_UPPER__VI : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CM_STAT__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNB_PWRMGT_CNTL__CI__VI {
	struct {
                unsigned int                   GNB_SLOW_MODE : 2;
                unsigned int                        GNB_SLOW : 1;
                unsigned int                    FORCE_NB_PS1 : 1;
                unsigned int                     DPM_ENABLED : 1;
                unsigned int                           SPARE : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COHER_DEST_BASE_0 {
	struct {
		unsigned int                  DEST_BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COHER_DEST_BASE_1 {
	struct {
		unsigned int                  DEST_BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COHER_DEST_BASE_2 {
	struct {
		unsigned int                  DEST_BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COHER_DEST_BASE_3 {
	struct {
		unsigned int                  DEST_BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COHER_DEST_BASE_HI_0__CI__VI {
	struct {
                unsigned int               DEST_BASE_HI_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COHER_DEST_BASE_HI_1__CI__VI {
	struct {
                unsigned int               DEST_BASE_HI_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COHER_DEST_BASE_HI_2__CI__VI {
	struct {
                unsigned int               DEST_BASE_HI_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COHER_DEST_BASE_HI_3__CI__VI {
	struct {
                unsigned int               DEST_BASE_HI_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMMAND {
	struct {
		unsigned int                    IO_ACCESS_EN : 1;
		unsigned int                   MEM_ACCESS_EN : 1;
		unsigned int                   BUS_MASTER_EN : 1;
		unsigned int                SPECIAL_CYCLE_EN : 1;
		unsigned int         MEM_WRITE_INVALIDATE_EN : 1;
		unsigned int                    PAL_SNOOP_EN : 1;
		unsigned int           PARITY_ERROR_RESPONSE : 1;
		unsigned int                     AD_STEPPING : 1;
		unsigned int                         SERR_EN : 1;
		unsigned int                     FAST_B2B_EN : 1;
		unsigned int                         INT_DIS : 1;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_DIM_X {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_DIM_Y {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_DIM_Z {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_DISPATCH_INITIATOR {
	struct {
                unsigned int               COMPUTE_SHADER_EN : 1;
                unsigned int                   PARTIAL_TG_EN : 1;
                unsigned int              FORCE_START_AT_000 : 1;
                unsigned int             ORDERED_APPEND_ENBL : 1;
                unsigned int     ORDERED_APPEND_MODE__CI__VI : 1;
                unsigned int   USE_THREAD_DIMENSIONS__CI__VI : 1;
                unsigned int              ORDER_MODE__CI__VI : 1;
                unsigned int     DISPATCH_CACHE_CNTL__CI__VI : 3;
                unsigned int       SCALAR_L1_INV_VOL__CI__VI : 1;
                unsigned int       VECTOR_L1_INV_VOL__CI__VI : 1;
                unsigned int                DATA_ATC__CI__VI : 1;
                unsigned int                                 : 1;
                unsigned int                 RESTORE__CI__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_MAX_WAVE_ID__SI {
	struct {
		unsigned int                                 : 12;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_MISC_RESERVED__CI__VI {
	struct {
                unsigned int                       SEND_SEID : 2;
                unsigned int                                 : 3;
                unsigned int                WAVE_ID_BASE__VI : 12;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_NUM_THREAD_X {
	struct {
		unsigned int                 NUM_THREAD_FULL : 16;
		unsigned int              NUM_THREAD_PARTIAL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_NUM_THREAD_Y {
	struct {
		unsigned int                 NUM_THREAD_FULL : 16;
		unsigned int              NUM_THREAD_PARTIAL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_NUM_THREAD_Z {
	struct {
		unsigned int                 NUM_THREAD_FULL : 16;
		unsigned int              NUM_THREAD_PARTIAL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_PERFCOUNT_ENABLE__CI__VI {
	struct {
                unsigned int                PERFCOUNT_ENABLE : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_PGM_HI {
	struct {
                unsigned int                            DATA : 8;
                unsigned int                INST_ATC__CI__VI : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_PGM_LO {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_PGM_RSRC1 {
	struct {
                unsigned int                           VGPRS : 6;
                unsigned int                           SGPRS : 4;
                unsigned int                        PRIORITY : 2;
                unsigned int                      FLOAT_MODE : 8;
                unsigned int                            PRIV : 1;
                unsigned int                      DX10_CLAMP : 1;
                unsigned int                      DEBUG_MODE : 1;
                unsigned int                       IEEE_MODE : 1;
                unsigned int                   BULKY__CI__VI : 1;
                unsigned int               CDBG_USER__CI__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_PGM_RSRC2 {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                       TGID_X_EN : 1;
                unsigned int                       TGID_Y_EN : 1;
                unsigned int                       TGID_Z_EN : 1;
                unsigned int                      TG_SIZE_EN : 1;
                unsigned int                  TIDIG_COMP_CNT : 2;
                unsigned int             EXCP_EN_MSB__CI__VI : 2;
                unsigned int                        LDS_SIZE : 9;
                unsigned int                         EXCP_EN : 7;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_PIPELINESTAT_ENABLE__CI__VI {
	struct {
                unsigned int             PIPELINESTAT_ENABLE : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_RESOURCE_LIMITS {
	struct {
                unsigned int                    WAVES_PER_SH : 10;
                unsigned int                                 : 2;
                unsigned int                       TG_PER_CU : 4;
                unsigned int                  LOCK_THRESHOLD : 6;
                unsigned int                  SIMD_DEST_CNTL : 1;
                unsigned int         FORCE_SIMD_DIST__CI__VI : 1;
                unsigned int          CU_GROUP_COUNT__CI__VI : 3;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_RESTART_X__CI__VI {
	struct {
                unsigned int                         RESTART : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_RESTART_Y__CI__VI {
	struct {
                unsigned int                         RESTART : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_RESTART_Z__CI__VI {
	struct {
                unsigned int                         RESTART : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_START_X {
	struct {
		unsigned int                           START : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_START_Y {
	struct {
		unsigned int                           START : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_START_Z {
	struct {
		unsigned int                           START : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_STATIC_THREAD_MGMT_SE0 {
	struct {
		unsigned int                       SH0_CU_EN : 16;
		unsigned int                       SH1_CU_EN : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_STATIC_THREAD_MGMT_SE1 {
	struct {
		unsigned int                       SH0_CU_EN : 16;
		unsigned int                       SH1_CU_EN : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI {
	struct {
                unsigned int                       SH0_CU_EN : 16;
                unsigned int                       SH1_CU_EN : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI {
	struct {
                unsigned int                       SH0_CU_EN : 16;
                unsigned int                       SH1_CU_EN : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_TBA_HI {
	struct {
		unsigned int                            DATA : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_TBA_LO {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_THREAD_TRACE_ENABLE__CI__VI {
	struct {
                unsigned int             THREAD_TRACE_ENABLE : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_TMA_HI {
	struct {
		unsigned int                            DATA : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_TMA_LO {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_TMPRING_SIZE {
	struct {
		unsigned int                           WAVES : 12;
		unsigned int                        WAVESIZE : 13;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_10 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_11 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_12 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_13 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_14 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_15 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_3 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_4 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_5 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_6 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_7 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_8 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_USER_DATA_9 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_VMID {
	struct {
		unsigned int                            DATA : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CONFIG_APER_SIZE {
	struct {
		unsigned int                       APER_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CONFIG_CNTL {
	struct {
		unsigned int                  CFG_VGA_RAM_EN : 1;
		unsigned int                         VGA_DIS : 1;
		unsigned int            GENMO_MONO_ADDRESS_B : 1;
		unsigned int                     GRPH_ADRSEL : 2;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CONFIG_F0_BASE {
	struct {
		unsigned int                         F0_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CONFIG_MEMSIZE {
	struct {
		unsigned int                  CONFIG_MEMSIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CONFIG_REG_APER_SIZE {
	struct {
		unsigned int                   REG_APER_SIZE : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CORB_CONTROL__SI__VI {
	struct {
                unsigned int CORB_MEMORY_ERROR_INTERRUPT_ENABLE : 1;
                unsigned int          ENABLE_CORB_DMA_ENGINE : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CORB_LOWER_BASE_ADDRESS__SI__VI {
	struct {
                unsigned int CORB_LOWER_BASE_UNIMPLEMENTED_BITS : 7;
                unsigned int         CORB_LOWER_BASE_ADDRESS : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CORB_READ_POINTER__SI__VI {
	struct {
                unsigned int               CORB_READ_POINTER : 8;
                unsigned int                                 : 7;
                unsigned int         CORB_READ_POINTER_RESET : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CORB_SIZE__SI__VI {
	struct {
                unsigned int                       CORB_SIZE : 2;
                unsigned int                                 : 2;
                unsigned int            CORB_SIZE_CAPABILITY : 4;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CORB_STATUS__SI__VI {
	struct {
                unsigned int    CORB_MEMORY_ERROR_INDICATION : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CORB_UPPER_BASE_ADDRESS__SI__VI {
	struct {
                unsigned int         CORB_UPPER_BASE_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CORB_WRITE_POINTER__SI__VI {
	struct {
                unsigned int              CORB_WRITE_POINTER : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC1_CONFIG__CI {
	struct {
		unsigned int                                 : 8;
		unsigned int                  CPC1_RDREQ_URG : 4;
		unsigned int                                 : 4;
		unsigned int                   CPC1_REQ_TRAN : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC2_CONFIG__CI {
	struct {
		unsigned int                                 : 8;
		unsigned int                  CPC2_RDREQ_URG : 4;
		unsigned int                                 : 4;
		unsigned int                   CPC2_REQ_TRAN : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC_INT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_ENABLE : 1;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int    SUA_VIOLATION_INT_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC_INT_CNTX_ID__CI__VI {
	struct {
                unsigned int                         CNTX_ID : 28;
                unsigned int                    QUEUE_ID__VI : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC_INT_STATUS__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_STATUS : 1;
                unsigned int         CP_ECC_ERROR_INT_STATUS : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_STATUS : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_STATUS : 1;
                unsigned int         OPCODE_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_STATUS : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_STATUS : 1;
                unsigned int             GENERIC1_INT_STATUS : 1;
                unsigned int             GENERIC0_INT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC_PERFCOUNTER0_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC_PERFCOUNTER0_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 6;
                unsigned int                                 : 4;
                unsigned int                       PERF_SEL3 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 6;
                unsigned int                                 : 4;
                unsigned int                       PERF_SEL1 : 6;
                unsigned int                                 : 4;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC_PERFCOUNTER1_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC_PERFCOUNTER1_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPC_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPF_PERFCOUNTER0_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPF_PERFCOUNTER0_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPF_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 6;
                unsigned int                                 : 4;
                unsigned int                       PERF_SEL3 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPF_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 6;
                unsigned int                                 : 4;
                unsigned int                       PERF_SEL1 : 6;
                unsigned int                                 : 4;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPF_PERFCOUNTER1_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPF_PERFCOUNTER1_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPF_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPG_CONFIG__CI {
	struct {
		unsigned int                                 : 8;
		unsigned int                   CPG_RDREQ_URG : 4;
		unsigned int                                 : 4;
		unsigned int                    CPG_REQ_TRAN : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPG_PERFCOUNTER0_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPG_PERFCOUNTER0_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPG_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 6;
                unsigned int                                 : 4;
                unsigned int                       PERF_SEL3 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPG_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 6;
                unsigned int                                 : 4;
                unsigned int                       PERF_SEL1 : 6;
                unsigned int                                 : 4;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPG_PERFCOUNTER1_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPG_PERFCOUNTER1_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPG_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_APPEND_ADDR_HI__SI__CI {
	struct {
                unsigned int                     MEM_ADDR_HI : 16;
                unsigned int                       CS_PS_SEL : 2;
                unsigned int                                 : 11;
                unsigned int                         COMMAND : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_APPEND_ADDR_HI__VI {
	struct {
		unsigned int                     MEM_ADDR_HI : 16;
		unsigned int                       CS_PS_SEL : 1;
		unsigned int                                 : 8;
		unsigned int                    CACHE_POLICY : 1;
		unsigned int                                 : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                         COMMAND : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_APPEND_ADDR_LO {
	struct {
		unsigned int                                 : 2;
		unsigned int                     MEM_ADDR_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_APPEND_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_APPEND_LAST_CS_FENCE {
	struct {
		unsigned int                      LAST_FENCE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_APPEND_LAST_PS_FENCE {
	struct {
		unsigned int                      LAST_FENCE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ATOMIC_PREOP_HI {
	struct {
		unsigned int                 ATOMIC_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ATOMIC_PREOP_LO {
	struct {
		unsigned int                 ATOMIC_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_BUSY_STAT {
	struct {
                unsigned int               REG_BUS_FIFO_BUSY : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int              COHER_CNT_NEQ_ZERO : 1;
                unsigned int             PFP_PARSING_PACKETS : 1;
                unsigned int              ME_PARSING_PACKETS : 1;
                unsigned int                   RCIU_PFP_BUSY : 1;
                unsigned int                    RCIU_ME_BUSY : 1;
                unsigned int                                 : 1;
                unsigned int           SEM_CMDFIFO_NOT_EMPTY : 1;
                unsigned int          SEM_FAILED_AND_HOLDING : 1;
                unsigned int            SEM_POLLING_FOR_PASS : 1;
                unsigned int                GFX_CONTEXT_BUSY : 1;
                unsigned int                                 : 1;
                unsigned int                  ME_PARSER_BUSY : 1;
                unsigned int                   EOP_DONE_BUSY : 1;
                unsigned int                   STRM_OUT_BUSY : 1;
                unsigned int                 PIPE_STATS_BUSY : 1;
                unsigned int                    RCIU_CE_BUSY : 1;
                unsigned int              CE_PARSING_PACKETS : 1;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CEQ1_AVAIL {
	struct {
		unsigned int                    CEQ_CNT_RING : 11;
		unsigned int                                 : 5;
		unsigned int                     CEQ_CNT_IB1 : 11;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CEQ2_AVAIL {
	struct {
		unsigned int                     CEQ_CNT_IB2 : 11;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_COMPARE_COUNT__CI__VI {
	struct {
                unsigned int                   COMPARE_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_COUNTER__CI__VI {
	struct {
                unsigned int              CONST_ENGINE_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_DE_COUNT__CI__VI {
	struct {
                unsigned int               DRAW_ENGINE_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_HEADER_DUMP {
	struct {
		unsigned int                  CE_HEADER_DUMP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_IB1_BASE_HI {
	struct {
                unsigned int                     IB1_BASE_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_IB1_BASE_LO {
	struct {
		unsigned int                                 : 2;
		unsigned int                     IB1_BASE_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_IB1_BUFSZ {
	struct {
		unsigned int                       IB1_BUFSZ : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_IB1_OFFSET__CI__VI {
	struct {
                unsigned int                      IB1_OFFSET : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_IB2_BASE_HI {
	struct {
                unsigned int                     IB2_BASE_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_IB2_BASE_LO {
	struct {
		unsigned int                                 : 2;
		unsigned int                     IB2_BASE_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_IB2_BUFSZ {
	struct {
		unsigned int                       IB2_BUFSZ : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_IB2_OFFSET__CI__VI {
	struct {
                unsigned int                      IB2_OFFSET : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_INIT_BASE_HI {
	struct {
                unsigned int                    INIT_BASE_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_INIT_BASE_LO {
	struct {
		unsigned int                                 : 5;
		unsigned int                    INIT_BASE_LO : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_INIT_BUFSZ {
	struct {
		unsigned int                      INIT_BUFSZ : 12;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_INTR_ROUTINE_START__CI__VI {
	struct {
                unsigned int                        IR_START : 11;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_PRGRM_CNTR_START__CI__VI {
	struct {
                unsigned int                        IP_START : 11;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_ROQ_IB1_STAT {
	struct {
		unsigned int              CEQ_RPTR_INDIRECT1 : 10;
		unsigned int                                 : 6;
		unsigned int              CEQ_WPTR_INDIRECT1 : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_ROQ_IB2_STAT {
	struct {
		unsigned int              CEQ_RPTR_INDIRECT2 : 10;
		unsigned int                                 : 6;
		unsigned int              CEQ_WPTR_INDIRECT2 : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_ROQ_RB_STAT {
	struct {
		unsigned int                CEQ_RPTR_PRIMARY : 10;
		unsigned int                                 : 6;
		unsigned int                CEQ_WPTR_PRIMARY : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_UCODE_ADDR {
	struct {
		unsigned int                      UCODE_ADDR : 12;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_UCODE_DATA {
	struct {
		unsigned int                      UCODE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CMD_DATA {
	struct {
		unsigned int                        CMD_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CMD_INDEX {
	struct {
                unsigned int                       CMD_INDEX : 11;
                unsigned int                                 : 1;
                unsigned int              CMD_ME_SEL__CI__VI : 2;
                unsigned int                                 : 2;
                unsigned int                   CMD_QUEUE_SEL : 3;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CNTL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CNTX_STAT__CI__VI {
	struct {
                unsigned int            ACTIVE_HP3D_CONTEXTS : 8;
                unsigned int            CURRENT_HP3D_CONTEXT : 3;
                unsigned int                                 : 9;
                unsigned int             ACTIVE_GFX_CONTEXTS : 8;
                unsigned int             CURRENT_GFX_CONTEXT : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CNTX_STAT__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
		unsigned int             ACTIVE_GFX_CONTEXTS : 8;
		unsigned int             CURRENT_GFX_CONTEXT : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_COHER_BASE {
	struct {
		unsigned int                 COHER_BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_COHER_BASE_HI__CI__VI {
	struct {
                unsigned int              COHER_BASE_HI_256B : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_COHER_CNTL {
	struct {
                unsigned int                 DEST_BASE_0_ENA : 1;
                unsigned int                 DEST_BASE_1_ENA : 1;
                unsigned int            TC_SD_ACTION_ENA__VI : 1;
                unsigned int            TC_NC_ACTION_ENA__VI : 1;
                unsigned int                                 : 2;
                unsigned int               CB0_DEST_BASE_ENA : 1;
                unsigned int               CB1_DEST_BASE_ENA : 1;
                unsigned int               CB2_DEST_BASE_ENA : 1;
                unsigned int               CB3_DEST_BASE_ENA : 1;
                unsigned int               CB4_DEST_BASE_ENA : 1;
                unsigned int               CB5_DEST_BASE_ENA : 1;
                unsigned int               CB6_DEST_BASE_ENA : 1;
                unsigned int               CB7_DEST_BASE_ENA : 1;
                unsigned int                DB_DEST_BASE_ENA : 1;
                unsigned int     TCL1_VOL_ACTION_ENA__CI__VI : 1;
                unsigned int           TC_VOL_ACTION_ENA__CI : 1;
                unsigned int                                 : 1;
                unsigned int        TC_WB_ACTION_ENA__CI__VI : 1;
                unsigned int                 DEST_BASE_2_ENA : 1;
                unsigned int                                 : 1;
                unsigned int                 DEST_BASE_3_ENA : 1;
                unsigned int                 TCL1_ACTION_ENA : 1;
                unsigned int                   TC_ACTION_ENA : 1;
                unsigned int                                 : 1;
                unsigned int                   CB_ACTION_ENA : 1;
                unsigned int                   DB_ACTION_ENA : 1;
                unsigned int            SH_KCACHE_ACTION_ENA : 1;
                unsigned int SH_KCACHE_VOL_ACTION_ENA__CI__VI : 1;
                unsigned int            SH_ICACHE_ACTION_ENA : 1;
                unsigned int     SH_KCACHE_WB_ACTION_ENA__VI : 1;
                unsigned int            SH_SD_ACTION_ENA__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_COHER_SIZE {
	struct {
		unsigned int                 COHER_SIZE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_COHER_SIZE_HI__CI__VI {
	struct {
                unsigned int              COHER_SIZE_HI_256B : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_COHER_START_DELAY {
	struct {
		unsigned int               START_DELAY_COUNT : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_COHER_STATUS {
	struct {
                unsigned int               MATCHING_GFX_CNTX : 8;
                unsigned int                                 : 16;
                unsigned int                    MEID__CI__VI : 2;
                unsigned int                                 : 4;
                unsigned int                   PHASE1_STATUS : 1;
                unsigned int                          STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CONFIG__SI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int                    CP_RDREQ_URG : 4;
                unsigned int                                 : 4;
                unsigned int                     CP_REQ_TRAN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CONTEXT_CNTL__CI__VI {
	struct {
                unsigned int            ME0PIPE0_MAX_WD_CNTX : 3;
                unsigned int                                 : 1;
                unsigned int          ME0PIPE0_MAX_PIPE_CNTX : 3;
                unsigned int                                 : 9;
                unsigned int            ME0PIPE1_MAX_WD_CNTX : 3;
                unsigned int                                 : 1;
                unsigned int          ME0PIPE1_MAX_PIPE_CNTX : 3;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_BUSY_STAT__CI__VI {
	struct {
                unsigned int                  MEC1_LOAD_BUSY : 1;
                unsigned int             MEC1_SEMAPOHRE_BUSY : 1;
                unsigned int                 MEC1_MUTEX_BUSY : 1;
                unsigned int               MEC1_MESSAGE_BUSY : 1;
                unsigned int             MEC1_EOP_QUEUE_BUSY : 1;
                unsigned int              MEC1_IQ_QUEUE_BUSY : 1;
                unsigned int              MEC1_IB_QUEUE_BUSY : 1;
                unsigned int                    MEC1_TC_BUSY : 1;
                unsigned int                   MEC1_DMA_BUSY : 1;
                unsigned int         MEC1_PARTIAL_FLUSH_BUSY : 1;
                unsigned int                 MEC1_PIPE0_BUSY : 1;
                unsigned int                 MEC1_PIPE1_BUSY : 1;
                unsigned int                 MEC1_PIPE2_BUSY : 1;
                unsigned int                 MEC1_PIPE3_BUSY : 1;
                unsigned int                                 : 2;
                unsigned int                  MEC2_LOAD_BUSY : 1;
                unsigned int             MEC2_SEMAPOHRE_BUSY : 1;
                unsigned int                 MEC2_MUTEX_BUSY : 1;
                unsigned int               MEC2_MESSAGE_BUSY : 1;
                unsigned int             MEC2_EOP_QUEUE_BUSY : 1;
                unsigned int              MEC2_IQ_QUEUE_BUSY : 1;
                unsigned int              MEC2_IB_QUEUE_BUSY : 1;
                unsigned int                    MEC2_TC_BUSY : 1;
                unsigned int                   MEC2_DMA_BUSY : 1;
                unsigned int         MEC2_PARTIAL_FLUSH_BUSY : 1;
                unsigned int                 MEC2_PIPE0_BUSY : 1;
                unsigned int                 MEC2_PIPE1_BUSY : 1;
                unsigned int                 MEC2_PIPE2_BUSY : 1;
                unsigned int                 MEC2_PIPE3_BUSY : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_GRBM_FREE_COUNT__CI__VI {
	struct {
                unsigned int                      FREE_COUNT : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_HALT_HYST_COUNT__CI__VI {
	struct {
                unsigned int                           COUNT : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_MC_CNTL__CI {
	struct {
		unsigned int                  PACK_DELAY_CNT : 5;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_SCRATCH_DATA__CI__VI {
	struct {
                unsigned int                    SCRATCH_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_SCRATCH_INDEX__CI__VI {
	struct {
                unsigned int                   SCRATCH_INDEX : 9;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_STALLED_STAT1__CI__VI {
	struct {
                unsigned int    MIU_RDREQ_FREE_STALL__SI__CI : 1;
                unsigned int    MIU_WRREQ_FREE_STALL__SI__CI : 1;
                unsigned int                                 : 1;
                unsigned int              RCIU_TX_FREE_STALL : 1;
                unsigned int             RCIU_PRIV_VIOLATION : 1;
                unsigned int                                 : 1;
                unsigned int              TCIU_TX_FREE_STALL : 1;
                unsigned int                                 : 1;
                unsigned int            MEC1_DECODING_PACKET : 1;
                unsigned int               MEC1_WAIT_ON_RCIU : 1;
                unsigned int          MEC1_WAIT_ON_RCIU_READ : 1;
                unsigned int    MEC1_WAIT_ON_MC_READ__SI__CI : 1;
                unsigned int  MEC1_WAIT_ON_MC_WR_ACK__SI__CI : 1;
                unsigned int           MEC1_WAIT_ON_ROQ_DATA : 1;
                unsigned int                                 : 2;
                unsigned int            MEC2_DECODING_PACKET : 1;
                unsigned int               MEC2_WAIT_ON_RCIU : 1;
                unsigned int          MEC2_WAIT_ON_RCIU_READ : 1;
                unsigned int    MEC2_WAIT_ON_MC_READ__SI__CI : 1;
                unsigned int  MEC2_WAIT_ON_MC_WR_ACK__SI__CI : 1;
                unsigned int           MEC2_WAIT_ON_ROQ_DATA : 1;
                unsigned int     ATCL2IU_WAITING_ON_FREE__VI : 1;
                unsigned int     ATCL2IU_WAITING_ON_TAGS__VI : 1;
                unsigned int      ATCL1_WAITING_ON_TRANS__VI : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_STATUS__CI__VI {
	struct {
                unsigned int                       MEC1_BUSY : 1;
                unsigned int                       MEC2_BUSY : 1;
                unsigned int                        DC0_BUSY : 1;
                unsigned int                        DC1_BUSY : 1;
                unsigned int                      RCIU1_BUSY : 1;
                unsigned int                      RCIU2_BUSY : 1;
                unsigned int                       ROQ1_BUSY : 1;
                unsigned int                       ROQ2_BUSY : 1;
                unsigned int          MIU_RDREQ_BUSY__SI__CI : 1;
                unsigned int          MIU_WRREQ_BUSY__SI__CI : 1;
                unsigned int                       TCIU_BUSY : 1;
                unsigned int                SCRATCH_RAM_BUSY : 1;
                unsigned int                         QU_BUSY : 1;
                unsigned int                ATCL2IU_BUSY__VI : 1;
                unsigned int                                 : 15;
                unsigned int                    CPG_CPC_BUSY : 1;
                unsigned int                    CPF_CPC_BUSY : 1;
                unsigned int                        CPC_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPF_BUSY_STAT__CI__VI {
	struct {
                unsigned int               REG_BUS_FIFO_BUSY : 1;
                unsigned int                   CSF_RING_BUSY : 1;
                unsigned int              CSF_INDIRECT1_BUSY : 1;
                unsigned int              CSF_INDIRECT2_BUSY : 1;
                unsigned int                  CSF_STATE_BUSY : 1;
                unsigned int               CSF_CE_INDR1_BUSY : 1;
                unsigned int               CSF_CE_INDR2_BUSY : 1;
                unsigned int                CSF_ARBITER_BUSY : 1;
                unsigned int                  CSF_INPUT_BUSY : 1;
                unsigned int           OUTSTANDING_READ_TAGS : 1;
                unsigned int                                 : 1;
                unsigned int         HPD_PROCESSING_EOP_BUSY : 1;
                unsigned int               HQD_DISPATCH_BUSY : 1;
                unsigned int               HQD_IQ_TIMER_BUSY : 1;
                unsigned int            HQD_DMA_OFFLOAD_BUSY : 1;
                unsigned int         HQD_WAIT_SEMAPHORE_BUSY : 1;
                unsigned int       HQD_SIGNAL_SEMAPHORE_BUSY : 1;
                unsigned int                HQD_MESSAGE_BUSY : 1;
                unsigned int             HQD_PQ_FETCHER_BUSY : 1;
                unsigned int             HQD_IB_FETCHER_BUSY : 1;
                unsigned int             HQD_IQ_FETCHER_BUSY : 1;
                unsigned int            HQD_EOP_FETCHER_BUSY : 1;
                unsigned int          HQD_CONSUMED_RPTR_BUSY : 1;
                unsigned int            HQD_FETCHER_ARB_BUSY : 1;
                unsigned int              HQD_ROQ_ALIGN_BUSY : 1;
                unsigned int                HQD_ROQ_EOP_BUSY : 1;
                unsigned int                 HQD_ROQ_IQ_BUSY : 1;
                unsigned int                 HQD_ROQ_PQ_BUSY : 1;
                unsigned int                 HQD_ROQ_IB_BUSY : 1;
                unsigned int              HQD_WPTR_POLL_BUSY : 1;
                unsigned int                     HQD_PQ_BUSY : 1;
                unsigned int                     HQD_IB_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPF_STALLED_STAT1__CI__VI {
	struct {
                unsigned int              RING_FETCHING_DATA : 1;
                unsigned int             INDR1_FETCHING_DATA : 1;
                unsigned int             INDR2_FETCHING_DATA : 1;
                unsigned int             STATE_FETCHING_DATA : 1;
                unsigned int MIU_WAITING_ON_RDREQ_FREE__SI__CI : 1;
                unsigned int            TCIU_WAITING_ON_FREE : 1;
                unsigned int            TCIU_WAITING_ON_TAGS : 1;
                unsigned int     ATCL2IU_WAITING_ON_FREE__VI : 1;
                unsigned int     ATCL2IU_WAITING_ON_TAGS__VI : 1;
                unsigned int      ATCL1_WAITING_ON_TRANS__VI : 1;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPF_STATUS__CI__VI {
	struct {
                unsigned int              POST_WPTR_GFX_BUSY : 1;
                unsigned int                        CSF_BUSY : 1;
                unsigned int          MIU_RDREQ_BUSY__SI__CI : 1;
                unsigned int          MIU_WRREQ_BUSY__SI__CI : 1;
                unsigned int                  ROQ_ALIGN_BUSY : 1;
                unsigned int                   ROQ_RING_BUSY : 1;
                unsigned int              ROQ_INDIRECT1_BUSY : 1;
                unsigned int              ROQ_INDIRECT2_BUSY : 1;
                unsigned int                  ROQ_STATE_BUSY : 1;
                unsigned int                ROQ_CE_RING_BUSY : 1;
                unsigned int           ROQ_CE_INDIRECT1_BUSY : 1;
                unsigned int           ROQ_CE_INDIRECT2_BUSY : 1;
                unsigned int                  SEMAPHORE_BUSY : 1;
                unsigned int                  INTERRUPT_BUSY : 1;
                unsigned int                       TCIU_BUSY : 1;
                unsigned int                        HQD_BUSY : 1;
                unsigned int                    PRT_BUSY__VI : 1;
                unsigned int                ATCL2IU_BUSY__VI : 1;
                unsigned int                                 : 8;
                unsigned int                CPF_GFX_BUSY__VI : 1;
                unsigned int                CPF_CMP_BUSY__VI : 1;
                unsigned int          GRBM_CPF_STAT_BUSY__VI : 2;
                unsigned int                    CPC_CPF_BUSY : 1;
                unsigned int                        CPF_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CSF_CNTL {
	struct {
		unsigned int              FETCH_BUFFER_DEPTH : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CSF_STAT {
	struct {
                unsigned int          BUFFER_SLOTS_ALLOCATED : 4;
                unsigned int                                 : 4;
                unsigned int            BUFFER_REQUEST_COUNT : 9;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DEBUG__CI__VI {
	struct {
                unsigned int                                 : 6;
                unsigned int                                 : 1;
                unsigned int                                 : 8;
                unsigned int                                 : 1;
                unsigned int                                 : 3;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DEBUG__SI {
	struct {
		unsigned int                                 : 6;
		unsigned int                                 : 9;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DEVICE_ID__CI__VI {
	struct {
                unsigned int                       DEVICE_ID : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DE_CE_COUNT__CI__VI {
	struct {
                unsigned int              CONST_ENGINE_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DE_DE_COUNT__CI__VI {
	struct {
                unsigned int               DRAW_ENGINE_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DE_LAST_INVAL_COUNT__CI__VI {
	struct {
                unsigned int                LAST_INVAL_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_ADDR_HI__CI__VI {
	struct {
                unsigned int                         ADDR_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 5;
                unsigned int                         ADDR_LO : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_CNTL__CI {
	struct {
		unsigned int                                 : 8;
		unsigned int                          POLICY : 2;
		unsigned int                             VOL : 1;
		unsigned int                             ATC : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_CNTL__VI {
	struct {
		unsigned int                          POLICY : 1;
		unsigned int                                 : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 23;
		unsigned int                                 : 1;
		unsigned int                      LFSR_RESET : 1;
		unsigned int                            MODE : 2;
		unsigned int                          ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_0__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_10__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_11__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_12__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_13__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_14__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_15__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_1__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_2__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_3__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_4__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_5__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_6__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_7__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_8__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_DATA_9__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_STAT__CI__VI {
	struct {
                unsigned int                     BURST_COUNT : 16;
                unsigned int                    TAGS_PENDING : 9;
                unsigned int                                 : 6;
                unsigned int                            BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_CNTL {
	struct {
		unsigned int                                 : 4;
		unsigned int                     MIN_AVAILSZ : 2;
		unsigned int                                 : 10;
		unsigned int                    BUFFER_DEPTH : 4;
		unsigned int                                 : 8;
		unsigned int                  PIO_FIFO_EMPTY : 1;
		unsigned int                   PIO_FIFO_FULL : 1;
		unsigned int                       PIO_COUNT : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_ME_COMMAND {
	struct {
		unsigned int                      BYTE_COUNT : 21;
		unsigned int                          DIS_WC : 1;
		unsigned int                        SRC_SWAP : 2;
		unsigned int                        DST_SWAP : 2;
		unsigned int                             SAS : 1;
		unsigned int                             DAS : 1;
		unsigned int                            SAIC : 1;
		unsigned int                            DAIC : 1;
		unsigned int                        RAW_WAIT : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_ME_CONTROL__CI {
	struct {
		unsigned int                                 : 12;
		unsigned int                         SRC_ATC : 1;
		unsigned int                SRC_CACHE_POLICY : 2;
		unsigned int                    SRC_VOLATILE : 1;
		unsigned int                                 : 4;
		unsigned int                      DST_SELECT : 2;
		unsigned int                                 : 2;
		unsigned int                         DST_ATC : 1;
		unsigned int                DST_CACHE_POLICY : 2;
		unsigned int                    DST_VOLATILE : 1;
		unsigned int                                 : 1;
		unsigned int                      SRC_SELECT : 2;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_ME_CONTROL__VI {
	struct {
		unsigned int                                 : 10;
		unsigned int                       SRC_MTYPE : 2;
		unsigned int                         SRC_ATC : 1;
		unsigned int                SRC_CACHE_POLICY : 1;
		unsigned int                                 : 6;
		unsigned int                      DST_SELECT : 2;
		unsigned int                       DST_MTYPE : 2;
		unsigned int                         DST_ATC : 1;
		unsigned int                DST_CACHE_POLICY : 1;
		unsigned int                                 : 3;
		unsigned int                      SRC_SELECT : 2;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_ME_DST_ADDR {
	struct {
		unsigned int                        DST_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_ME_DST_ADDR_HI {
	struct {
                unsigned int                     DST_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_ME_SRC_ADDR {
	struct {
		unsigned int                        SRC_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_ME_SRC_ADDR_HI {
	struct {
                unsigned int                     SRC_ADDR_HI : 16;
                unsigned int                                 : 4;
                unsigned int                                 : 2;
                unsigned int                                 : 7;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_PFP_COMMAND {
	struct {
		unsigned int                      BYTE_COUNT : 21;
		unsigned int                          DIS_WC : 1;
		unsigned int                        SRC_SWAP : 2;
		unsigned int                        DST_SWAP : 2;
		unsigned int                             SAS : 1;
		unsigned int                             DAS : 1;
		unsigned int                            SAIC : 1;
		unsigned int                            DAIC : 1;
		unsigned int                        RAW_WAIT : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_PFP_CONTROL__CI {
	struct {
		unsigned int                                 : 12;
		unsigned int                         SRC_ATC : 1;
		unsigned int                SRC_CACHE_POLICY : 2;
		unsigned int                    SRC_VOLATILE : 1;
		unsigned int                                 : 4;
		unsigned int                      DST_SELECT : 2;
		unsigned int                                 : 2;
		unsigned int                         DST_ATC : 1;
		unsigned int                DST_CACHE_POLICY : 2;
		unsigned int                    DST_VOLATILE : 1;
		unsigned int                                 : 1;
		unsigned int                      SRC_SELECT : 2;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_PFP_CONTROL__VI {
	struct {
		unsigned int                                 : 10;
		unsigned int                       SRC_MTYPE : 2;
		unsigned int                         SRC_ATC : 1;
		unsigned int                SRC_CACHE_POLICY : 1;
		unsigned int                                 : 6;
		unsigned int                      DST_SELECT : 2;
		unsigned int                       DST_MTYPE : 2;
		unsigned int                         DST_ATC : 1;
		unsigned int                DST_CACHE_POLICY : 1;
		unsigned int                                 : 3;
		unsigned int                      SRC_SELECT : 2;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_PFP_DST_ADDR {
	struct {
		unsigned int                        DST_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_PFP_DST_ADDR_HI {
	struct {
                unsigned int                     DST_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_PFP_SRC_ADDR {
	struct {
		unsigned int                        SRC_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_PFP_SRC_ADDR_HI {
	struct {
                unsigned int                     SRC_ADDR_HI : 16;
                unsigned int                                 : 4;
                unsigned int                                 : 2;
                unsigned int                                 : 7;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_PIO_COMMAND {
	struct {
		unsigned int                                 : 21;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DMA_READ_TAGS {
	struct {
		unsigned int                    DMA_READ_TAG : 26;
		unsigned int                                 : 2;
		unsigned int              DMA_READ_TAG_VALID : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ECC_FIRSTOCCURRENCE__SI__CI {
	struct {
		unsigned int                       INTERFACE : 2;
		unsigned int                                 : 2;
		unsigned int                  REQUEST_CLIENT : 4;
		unsigned int                                 : 2;
		unsigned int                         RING_ID : 4;
		unsigned int                                 : 2;
		unsigned int                            VMID : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ECC_FIRSTOCCURRENCE__VI {
	struct {
		unsigned int                       INTERFACE : 2;
		unsigned int                                 : 2;
		unsigned int                          CLIENT : 4;
		unsigned int                              ME : 2;
		unsigned int                            PIPE : 2;
		unsigned int                           QUEUE : 3;
		unsigned int                                 : 1;
		unsigned int                            VMID : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ECC_FIRSTOCCURRENCE_RING0__SI__CI {
	struct {
		unsigned int                       INTERFACE : 2;
		unsigned int                                 : 2;
		unsigned int                  REQUEST_CLIENT : 4;
		unsigned int                                 : 2;
		unsigned int                         RING_ID : 4;
		unsigned int                                 : 2;
		unsigned int                            VMID : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ECC_FIRSTOCCURRENCE_RING0__VI {
	struct {
		unsigned int                        OBSOLETE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ECC_FIRSTOCCURRENCE_RING1__SI__CI {
	struct {
		unsigned int                       INTERFACE : 2;
		unsigned int                                 : 2;
		unsigned int                  REQUEST_CLIENT : 4;
		unsigned int                                 : 2;
		unsigned int                         RING_ID : 4;
		unsigned int                                 : 2;
		unsigned int                            VMID : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ECC_FIRSTOCCURRENCE_RING1__VI {
	struct {
		unsigned int                        OBSOLETE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ECC_FIRSTOCCURRENCE_RING2__SI__CI {
	struct {
		unsigned int                       INTERFACE : 2;
		unsigned int                                 : 2;
		unsigned int                  REQUEST_CLIENT : 4;
		unsigned int                                 : 2;
		unsigned int                         RING_ID : 4;
		unsigned int                                 : 2;
		unsigned int                            VMID : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ECC_FIRSTOCCURRENCE_RING2__VI {
	struct {
		unsigned int                        OBSOLETE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ENDIAN_SWAP__CI__VI {
	struct {
                unsigned int                     ENDIAN_SWAP : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_ADDR_HI__CI__VI {
	struct {
                unsigned int                         ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_ADDR_HI__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 16;
		unsigned int                                 : 2;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_ADDR_LO__CI__VI {
	struct {
                unsigned int               ADDR_SWAP__SI__CI : 2;
                unsigned int                         ADDR_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_ADDR_LO__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_DATA_CNTL__CI__VI {
	struct {
                unsigned int                         CNTX_ID : 16;
                unsigned int                         DST_SEL : 2;
                unsigned int                                 : 6;
                unsigned int                         INT_SEL : 3;
                unsigned int                                 : 2;
                unsigned int                        DATA_SEL : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_DATA_HI__CI__VI {
	struct {
                unsigned int                         DATA_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_DATA_HI__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_DATA_LO__CI__VI {
	struct {
                unsigned int                         DATA_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_DATA_LO__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_EVENT_CNTL__CI {
	struct {
		unsigned int                     WBINV_TC_OP : 7;
		unsigned int                                 : 5;
		unsigned int                WBINV_ACTION_ENA : 6;
		unsigned int                                 : 7;
		unsigned int                   CACHE_CONTROL : 2;
		unsigned int                    EOP_VOLATILE : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_EVENT_CNTL__VI {
	struct {
		unsigned int                     WBINV_TC_OP : 7;
		unsigned int                                 : 5;
		unsigned int                WBINV_ACTION_ENA : 6;
		unsigned int                                 : 7;
		unsigned int                   CACHE_CONTROL : 1;
		unsigned int                                 : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_LAST_FENCE_HI {
	struct {
		unsigned int                   LAST_FENCE_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_LAST_FENCE_LO {
	struct {
		unsigned int                   LAST_FENCE_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_FETCHER_SOURCE__CI {
	struct {
		unsigned int                          ME_SRC : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_GDS_ATOMIC0_PREOP_HI {
	struct {
		unsigned int            GDS_ATOMIC0_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_GDS_ATOMIC0_PREOP_LO {
	struct {
		unsigned int            GDS_ATOMIC0_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_GDS_ATOMIC1_PREOP_HI {
	struct {
		unsigned int            GDS_ATOMIC1_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_GDS_ATOMIC1_PREOP_LO {
	struct {
		unsigned int            GDS_ATOMIC1_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_GRBM_FREE_COUNT {
	struct {
		unsigned int                      FREE_COUNT : 6;
		unsigned int                                 : 2;
		unsigned int                  FREE_COUNT_GDS : 6;
		unsigned int                                 : 2;
		unsigned int                  FREE_COUNT_PFP : 6;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HPD_EOP_BASE_ADDR_HI__CI {
	struct {
		unsigned int                    BASE_ADDR_HI : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HPD_EOP_BASE_ADDR__CI {
	struct {
		unsigned int                       BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HPD_EOP_CONTROL__CI {
	struct {
		unsigned int                        EOP_SIZE : 6;
		unsigned int                                 : 2;
		unsigned int                  PROCESSING_EOP : 1;
		unsigned int                  PROCESSING_QID : 3;
		unsigned int                  PROCESS_EOP_EN : 1;
		unsigned int                PROCESSING_EOPIB : 1;
		unsigned int                PROCESS_EOPIB_EN : 1;
		unsigned int                                 : 8;
		unsigned int                         EOP_ATC : 1;
		unsigned int                    CACHE_POLICY : 2;
		unsigned int                    EOP_VOLATILE : 1;
		unsigned int                                 : 1;
		unsigned int                      PEND_Q_SEM : 3;
		unsigned int                    PEND_SIG_SEM : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HPD_EOP_VMID__CI {
	struct {
		unsigned int                            VMID : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HPD_ROQ_OFFSETS__CI__VI {
	struct {
                unsigned int                       IQ_OFFSET : 3;
                unsigned int                                 : 5;
                unsigned int                       PQ_OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                       IB_OFFSET : 6;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_ACTIVE__CI__VI {
	struct {
                unsigned int                          ACTIVE : 1;
                unsigned int                   BUSY_GATE__VI : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_ATOMIC0_PREOP_HI__CI__VI {
	struct {
                unsigned int                ATOMIC0_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_ATOMIC0_PREOP_LO__CI__VI {
	struct {
                unsigned int                ATOMIC0_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_ATOMIC1_PREOP_HI__CI__VI {
	struct {
                unsigned int                ATOMIC1_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_ATOMIC1_PREOP_LO__CI__VI {
	struct {
                unsigned int                ATOMIC1_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_DEQUEUE_REQUEST__CI__VI {
	struct {
                unsigned int                     DEQUEUE_REQ : 3;
                unsigned int                                 : 1;
                unsigned int                     IQ_REQ_PEND : 1;
                unsigned int                                 : 3;
                unsigned int                     DEQUEUE_INT : 1;
                unsigned int              IQ_REQ_PEND_EN__VI : 1;
                unsigned int              DEQUEUE_REQ_EN__VI : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_DMA_OFFLOAD__CI__VI {
	struct {
                unsigned int                     DMA_OFFLOAD : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_HQ_SCHEDULER0__CI {
	struct {
		unsigned int                  DEQUEUE_STATUS : 2;
		unsigned int               DEQUEUE_RETRY_CNT : 2;
		unsigned int                                 : 3;
		unsigned int                SCRATCH_RAM_INIT : 1;
		unsigned int                      TCL2_DIRTY : 1;
		unsigned int                    PG_ACTIVATED : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_HQ_SCHEDULER0__VI {
	struct {
		unsigned int                       SCHEDULER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_HQ_SCHEDULER1__CI__VI {
	struct {
                unsigned int                       SCHEDULER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_IB_BASE_ADDR_HI__CI__VI {
	struct {
                unsigned int                 IB_BASE_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_IB_BASE_ADDR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                    IB_BASE_ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_IB_CONTROL__CI {
	struct {
		unsigned int                         IB_SIZE : 20;
		unsigned int               MIN_IB_AVAIL_SIZE : 2;
		unsigned int                                 : 1;
		unsigned int                          IB_ATC : 1;
		unsigned int                 IB_CACHE_POLICY : 2;
		unsigned int                     IB_VOLATILE : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                   PROCESSING_IB : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_IB_CONTROL__VI {
	struct {
		unsigned int                         IB_SIZE : 20;
		unsigned int               MIN_IB_AVAIL_SIZE : 2;
		unsigned int                                 : 1;
		unsigned int                          IB_ATC : 1;
		unsigned int                 IB_CACHE_POLICY : 1;
		unsigned int                                 : 2;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                   PROCESSING_IB : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_IB_RPTR__CI__VI {
	struct {
                unsigned int                 CONSUMED_OFFSET : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_IQ_RPTR__CI__VI {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_IQ_TIMER__CI {
	struct {
		unsigned int                       WAIT_TIME : 8;
		unsigned int                      RETRY_TYPE : 3;
		unsigned int                                 : 1;
		unsigned int                  INTERRUPT_TYPE : 2;
		unsigned int                                 : 2;
		unsigned int                  INTERRUPT_SIZE : 6;
		unsigned int                                 : 1;
		unsigned int                          IQ_ATC : 1;
		unsigned int                    CACHE_POLICY : 2;
		unsigned int                     IQ_VOLATILE : 1;
		unsigned int                                 : 2;
		unsigned int                   PROCESS_IQ_EN : 1;
		unsigned int                   PROCESSING_IQ : 1;
		unsigned int                          ACTIVE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_IQ_TIMER__VI {
	struct {
		unsigned int                       WAIT_TIME : 8;
		unsigned int                      RETRY_TYPE : 3;
		unsigned int                IMMEDIATE_EXPIRE : 1;
		unsigned int                  INTERRUPT_TYPE : 2;
		unsigned int                     CLOCK_COUNT : 2;
		unsigned int                  INTERRUPT_SIZE : 6;
		unsigned int                   QUANTUM_TIMER : 1;
		unsigned int                          IQ_ATC : 1;
		unsigned int                    CACHE_POLICY : 1;
		unsigned int                                 : 2;
		unsigned int                           MTYPE : 2;
		unsigned int                   PROCESS_IQ_EN : 1;
		unsigned int                   PROCESSING_IQ : 1;
		unsigned int                          ACTIVE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_MSG_TYPE__CI__VI {
	struct {
                unsigned int                          ACTION : 3;
                unsigned int                                 : 1;
                unsigned int                  SAVE_STATE__VI : 3;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PERSISTENT_STATE__CI__VI {
	struct {
                unsigned int                     PRELOAD_REQ : 1;
                unsigned int                                 : 7;
                unsigned int                    PRELOAD_SIZE : 10;
                unsigned int                                 : 10;
                unsigned int              RESTORE_ACTIVE__VI : 1;
                unsigned int              RELAUNCH_WAVES__VI : 1;
                unsigned int                QSWITCH_MODE__VI : 1;
                unsigned int                     DISP_ACTIVE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PIPE_PRIORITY__CI__VI {
	struct {
                unsigned int                   PIPE_PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_BASE_HI__CI__VI {
	struct {
                unsigned int                         ADDR_HI : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_BASE__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_CONTROL__CI {
	struct {
		unsigned int                      QUEUE_SIZE : 6;
		unsigned int                                 : 2;
		unsigned int                 RPTR_BLOCK_SIZE : 6;
		unsigned int                                 : 2;
		unsigned int                     ENDIAN_SWAP : 2;
		unsigned int                                 : 2;
		unsigned int                  MIN_AVAIL_SIZE : 2;
		unsigned int                                 : 1;
		unsigned int                          PQ_ATC : 1;
		unsigned int                    CACHE_POLICY : 2;
		unsigned int                     PQ_VOLATILE : 1;
		unsigned int                  NO_UPDATE_RPTR : 1;
		unsigned int                  UNORD_DISPATCH : 1;
		unsigned int                  ROQ_PQ_IB_FLIP : 1;
		unsigned int                      PRIV_STATE : 1;
		unsigned int                       KMD_QUEUE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_CONTROL__VI {
	struct {
		unsigned int                      QUEUE_SIZE : 6;
		unsigned int                                 : 2;
		unsigned int                 RPTR_BLOCK_SIZE : 6;
		unsigned int                                 : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                     ENDIAN_SWAP : 2;
		unsigned int                                 : 1;
		unsigned int                  MIN_AVAIL_SIZE : 2;
		unsigned int                                 : 1;
		unsigned int                          PQ_ATC : 1;
		unsigned int                    CACHE_POLICY : 1;
		unsigned int                 SLOT_BASED_WPTR : 2;
		unsigned int                  NO_UPDATE_RPTR : 1;
		unsigned int                  UNORD_DISPATCH : 1;
		unsigned int                  ROQ_PQ_IB_FLIP : 1;
		unsigned int                      PRIV_STATE : 1;
		unsigned int                       KMD_QUEUE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_DOORBELL_CONTROL__CI__VI {
	struct {
                unsigned int               DOORBELL_MODE__VI : 1;
                unsigned int           DOORBELL_BIF_DROP__VI : 1;
                unsigned int                 DOORBELL_OFFSET : 21;
                unsigned int         DOORBELL_CARRY_BITS__VI : 3;
                unsigned int                                 : 2;
                unsigned int                 DOORBELL_SOURCE : 1;
                unsigned int               DOORBELL_SCHD_HIT : 1;
                unsigned int                     DOORBELL_EN : 1;
                unsigned int                    DOORBELL_HIT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_RPTR_REPORT_ADDR_HI__CI__VI {
	struct {
                unsigned int             RPTR_REPORT_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_RPTR_REPORT_ADDR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                RPTR_REPORT_ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_RPTR__CI__VI {
	struct {
                unsigned int                 CONSUMED_OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_WPTR_POLL_ADDR_HI__CI__VI {
	struct {
                unsigned int                    WPTR_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_WPTR_POLL_ADDR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                       WPTR_ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_PQ_WPTR__CI__VI {
	struct {
                unsigned int                          OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_QUANTUM__CI__VI {
	struct {
                unsigned int                      QUANTUM_EN : 1;
                unsigned int                                 : 3;
                unsigned int                   QUANTUM_SCALE : 1;
                unsigned int                                 : 3;
                unsigned int                QUANTUM_DURATION : 6;
                unsigned int                                 : 17;
                unsigned int              QUANTUM_ACTIVE__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_QUEUE_PRIORITY__CI__VI {
	struct {
                unsigned int                  PRIORITY_LEVEL : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_SEMA_CMD__CI__VI {
	struct {
                unsigned int                           RETRY : 1;
                unsigned int                          RESULT : 2;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_VMID__CI__VI {
	struct {
                unsigned int                            VMID : 4;
                unsigned int                                 : 4;
                unsigned int                         IB_VMID : 4;
                unsigned int                                 : 4;
                unsigned int                            VQID : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB1_BASE_HI {
	struct {
                unsigned int                     IB1_BASE_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB1_BASE_LO {
	struct {
		unsigned int                                 : 2;
		unsigned int                     IB1_BASE_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB1_BUFSZ {
	struct {
		unsigned int                       IB1_BUFSZ : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB1_OFFSET {
	struct {
		unsigned int                      IB1_OFFSET : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB1_PREAMBLE_BEGIN {
	struct {
		unsigned int              IB1_PREAMBLE_BEGIN : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB1_PREAMBLE_END {
	struct {
		unsigned int                IB1_PREAMBLE_END : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB2_BASE_HI {
	struct {
                unsigned int                     IB2_BASE_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB2_BASE_LO {
	struct {
		unsigned int                                 : 2;
		unsigned int                     IB2_BASE_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB2_BUFSZ {
	struct {
		unsigned int                       IB2_BUFSZ : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB2_OFFSET {
	struct {
		unsigned int                      IB2_OFFSET : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB2_PREAMBLE_BEGIN {
	struct {
		unsigned int              IB2_PREAMBLE_BEGIN : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IB2_PREAMBLE_END {
	struct {
		unsigned int                IB2_PREAMBLE_END : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_CNTL_RING0__CI__VI {
	struct {
                unsigned int                                 : 11;
                unsigned int CP_VM_DOORBELL_WR_INT_ENABLE__VI : 1;
                unsigned int                                 : 2;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int         CMP_BUSY_INT_ENABLE__VI : 1;
                unsigned int            CNTX_BUSY_INT_ENABLE : 1;
                unsigned int           CNTX_EMPTY_INT_ENABLE : 1;
                unsigned int         GFX_IDLE_INT_ENABLE__VI : 1;
                unsigned int           PRIV_INSTR_INT_ENABLE : 1;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_CNTL_RING0__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int            CNTX_BUSY_INT_ENABLE : 1;
		unsigned int           CNTX_EMPTY_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int           PRIV_INSTR_INT_ENABLE : 1;
		unsigned int             PRIV_REG_INT_ENABLE : 1;
		unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int           TIME_STAMP_INT_ENABLE : 1;
		unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_CNTL_RING1__CI__VI {
	struct {
                unsigned int                                 : 11;
                unsigned int CP_VM_DOORBELL_WR_INT_ENABLE__VI : 1;
                unsigned int                                 : 2;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int         CMP_BUSY_INT_ENABLE__VI : 1;
                unsigned int            CNTX_BUSY_INT_ENABLE : 1;
                unsigned int           CNTX_EMPTY_INT_ENABLE : 1;
                unsigned int         GFX_IDLE_INT_ENABLE__VI : 1;
                unsigned int           PRIV_INSTR_INT_ENABLE : 1;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_CNTL_RING1__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int            CNTX_BUSY_INT_ENABLE : 1;
		unsigned int           CNTX_EMPTY_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int           PRIV_INSTR_INT_ENABLE : 1;
		unsigned int             PRIV_REG_INT_ENABLE : 1;
		unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int           TIME_STAMP_INT_ENABLE : 1;
		unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_CNTL_RING2__CI__VI {
	struct {
                unsigned int                                 : 11;
                unsigned int CP_VM_DOORBELL_WR_INT_ENABLE__VI : 1;
                unsigned int                                 : 2;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int         CMP_BUSY_INT_ENABLE__VI : 1;
                unsigned int            CNTX_BUSY_INT_ENABLE : 1;
                unsigned int           CNTX_EMPTY_INT_ENABLE : 1;
                unsigned int         GFX_IDLE_INT_ENABLE__VI : 1;
                unsigned int           PRIV_INSTR_INT_ENABLE : 1;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_CNTL_RING2__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int            CNTX_BUSY_INT_ENABLE : 1;
		unsigned int           CNTX_EMPTY_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int           PRIV_INSTR_INT_ENABLE : 1;
		unsigned int             PRIV_REG_INT_ENABLE : 1;
		unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int           TIME_STAMP_INT_ENABLE : 1;
		unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 11;
                unsigned int CP_VM_DOORBELL_WR_INT_ENABLE__VI : 1;
                unsigned int                                 : 2;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int         CMP_BUSY_INT_ENABLE__VI : 1;
                unsigned int            CNTX_BUSY_INT_ENABLE : 1;
                unsigned int           CNTX_EMPTY_INT_ENABLE : 1;
                unsigned int         GFX_IDLE_INT_ENABLE__VI : 1;
                unsigned int           PRIV_INSTR_INT_ENABLE : 1;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_CNTL__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int            CNTX_BUSY_INT_ENABLE : 1;
		unsigned int           CNTX_EMPTY_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int           PRIV_INSTR_INT_ENABLE : 1;
		unsigned int             PRIV_REG_INT_ENABLE : 1;
		unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int           TIME_STAMP_INT_ENABLE : 1;
		unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STATUS_RING0__CI {
	struct {
		unsigned int                                 : 14;
		unsigned int           CP_ECC_ERROR_INT_STAT : 1;
		unsigned int                                 : 2;
		unsigned int       WRM_POLL_TIMEOUT_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int              CNTX_BUSY_INT_STAT : 1;
		unsigned int             CNTX_EMPTY_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             PRIV_INSTR_INT_STAT : 1;
		unsigned int               PRIV_REG_INT_STAT : 1;
		unsigned int           OPCODE_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             TIME_STAMP_INT_STAT : 1;
		unsigned int     RESERVED_BIT_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int               GENERIC2_INT_STAT : 1;
		unsigned int               GENERIC1_INT_STAT : 1;
		unsigned int               GENERIC0_INT_STAT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STATUS_RING0__VI {
	struct {
		unsigned int                                 : 11;
		unsigned int      CP_VM_DOORBELL_WR_INT_STAT : 1;
		unsigned int                                 : 2;
		unsigned int           CP_ECC_ERROR_INT_STAT : 1;
		unsigned int                                 : 2;
		unsigned int       WRM_POLL_TIMEOUT_INT_STAT : 1;
		unsigned int               CMP_BUSY_INT_STAT : 1;
		unsigned int             GCNTX_BUSY_INT_STAT : 1;
		unsigned int             CNTX_EMPTY_INT_STAT : 1;
		unsigned int               GFX_IDLE_INT_STAT : 1;
		unsigned int             PRIV_INSTR_INT_STAT : 1;
		unsigned int               PRIV_REG_INT_STAT : 1;
		unsigned int           OPCODE_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             TIME_STAMP_INT_STAT : 1;
		unsigned int     RESERVED_BIT_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int               GENERIC2_INT_STAT : 1;
		unsigned int               GENERIC1_INT_STAT : 1;
		unsigned int               GENERIC0_INT_STAT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STATUS_RING0__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int           CP_ECC_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int       WRM_POLL_TIMEOUT_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int              CNTX_BUSY_INT_STAT : 1;
		unsigned int             CNTX_EMPTY_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             PRIV_INSTR_INT_STAT : 1;
		unsigned int               PRIV_REG_INT_STAT : 1;
		unsigned int           OPCODE_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             TIME_STAMP_INT_STAT : 1;
		unsigned int     RESERVED_BIT_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STATUS_RING1__CI__VI {
	struct {
                unsigned int                                 : 11;
                unsigned int  CP_VM_DOORBELL_WR_INT_STAT__VI : 1;
                unsigned int                                 : 2;
                unsigned int           CP_ECC_ERROR_INT_STAT : 1;
                unsigned int                                 : 2;
                unsigned int       WRM_POLL_TIMEOUT_INT_STAT : 1;
                unsigned int           CMP_BUSY_INT_STAT__VI : 1;
                unsigned int              CNTX_BUSY_INT_STAT : 1;
                unsigned int             CNTX_EMPTY_INT_STAT : 1;
                unsigned int           GFX_IDLE_INT_STAT__VI : 1;
                unsigned int             PRIV_INSTR_INT_STAT : 1;
                unsigned int               PRIV_REG_INT_STAT : 1;
                unsigned int           OPCODE_ERROR_INT_STAT : 1;
                unsigned int                                 : 1;
                unsigned int             TIME_STAMP_INT_STAT : 1;
                unsigned int     RESERVED_BIT_ERROR_INT_STAT : 1;
                unsigned int                                 : 1;
                unsigned int               GENERIC2_INT_STAT : 1;
                unsigned int               GENERIC1_INT_STAT : 1;
                unsigned int               GENERIC0_INT_STAT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STATUS_RING1__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int           CP_ECC_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int       WRM_POLL_TIMEOUT_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int              CNTX_BUSY_INT_STAT : 1;
		unsigned int             CNTX_EMPTY_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             PRIV_INSTR_INT_STAT : 1;
		unsigned int               PRIV_REG_INT_STAT : 1;
		unsigned int           OPCODE_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             TIME_STAMP_INT_STAT : 1;
		unsigned int     RESERVED_BIT_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STATUS_RING2__CI__VI {
	struct {
                unsigned int                                 : 11;
                unsigned int  CP_VM_DOORBELL_WR_INT_STAT__VI : 1;
                unsigned int                                 : 2;
                unsigned int           CP_ECC_ERROR_INT_STAT : 1;
                unsigned int                                 : 2;
                unsigned int       WRM_POLL_TIMEOUT_INT_STAT : 1;
                unsigned int           CMP_BUSY_INT_STAT__VI : 1;
                unsigned int              CNTX_BUSY_INT_STAT : 1;
                unsigned int             CNTX_EMPTY_INT_STAT : 1;
                unsigned int           GFX_IDLE_INT_STAT__VI : 1;
                unsigned int             PRIV_INSTR_INT_STAT : 1;
                unsigned int               PRIV_REG_INT_STAT : 1;
                unsigned int           OPCODE_ERROR_INT_STAT : 1;
                unsigned int                                 : 1;
                unsigned int             TIME_STAMP_INT_STAT : 1;
                unsigned int     RESERVED_BIT_ERROR_INT_STAT : 1;
                unsigned int                                 : 1;
                unsigned int               GENERIC2_INT_STAT : 1;
                unsigned int               GENERIC1_INT_STAT : 1;
                unsigned int               GENERIC0_INT_STAT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STATUS_RING2__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int           CP_ECC_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int       WRM_POLL_TIMEOUT_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int              CNTX_BUSY_INT_STAT : 1;
		unsigned int             CNTX_EMPTY_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             PRIV_INSTR_INT_STAT : 1;
		unsigned int               PRIV_REG_INT_STAT : 1;
		unsigned int           OPCODE_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             TIME_STAMP_INT_STAT : 1;
		unsigned int     RESERVED_BIT_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STATUS__CI__VI {
	struct {
                unsigned int                                 : 11;
                unsigned int  CP_VM_DOORBELL_WR_INT_STAT__VI : 1;
                unsigned int                                 : 2;
                unsigned int           CP_ECC_ERROR_INT_STAT : 1;
                unsigned int                                 : 2;
                unsigned int       WRM_POLL_TIMEOUT_INT_STAT : 1;
                unsigned int           CMP_BUSY_INT_STAT__VI : 1;
                unsigned int              CNTX_BUSY_INT_STAT : 1;
                unsigned int             CNTX_EMPTY_INT_STAT : 1;
                unsigned int           GFX_IDLE_INT_STAT__VI : 1;
                unsigned int             PRIV_INSTR_INT_STAT : 1;
                unsigned int               PRIV_REG_INT_STAT : 1;
                unsigned int           OPCODE_ERROR_INT_STAT : 1;
                unsigned int                                 : 1;
                unsigned int             TIME_STAMP_INT_STAT : 1;
                unsigned int     RESERVED_BIT_ERROR_INT_STAT : 1;
                unsigned int                                 : 1;
                unsigned int               GENERIC2_INT_STAT : 1;
                unsigned int               GENERIC1_INT_STAT : 1;
                unsigned int               GENERIC0_INT_STAT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STATUS__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int           CP_ECC_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int       WRM_POLL_TIMEOUT_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int              CNTX_BUSY_INT_STAT : 1;
		unsigned int             CNTX_EMPTY_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             PRIV_INSTR_INT_STAT : 1;
		unsigned int               PRIV_REG_INT_STAT : 1;
		unsigned int           OPCODE_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int             TIME_STAMP_INT_STAT : 1;
		unsigned int     RESERVED_BIT_ERROR_INT_STAT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STAT_DEBUG__CI__VI {
	struct {
                unsigned int                                 : 11;
                unsigned int CP_VM_DOORBELL_WR_INT_ASSERTED__VI : 1;
                unsigned int                                 : 2;
                unsigned int       CP_ECC_ERROR_INT_ASSERTED : 1;
                unsigned int                                 : 2;
                unsigned int   WRM_POLL_TIMEOUT_INT_ASSERTED : 1;
                unsigned int       CMP_BUSY_INT_ASSERTED__VI : 1;
                unsigned int          CNTX_BUSY_INT_ASSERTED : 1;
                unsigned int         CNTX_EMPTY_INT_ASSERTED : 1;
                unsigned int       GFX_IDLE_INT_ASSERTED__VI : 1;
                unsigned int         PRIV_INSTR_INT_ASSERTED : 1;
                unsigned int           PRIV_REG_INT_ASSERTED : 1;
                unsigned int       OPCODE_ERROR_INT_ASSERTED : 1;
                unsigned int                                 : 1;
                unsigned int         TIME_STAMP_INT_ASSERTED : 1;
                unsigned int RESERVED_BIT_ERROR_INT_ASSERTED : 1;
                unsigned int                                 : 1;
                unsigned int           GENERIC2_INT_ASSERTED : 1;
                unsigned int           GENERIC1_INT_ASSERTED : 1;
                unsigned int           GENERIC0_INT_ASSERTED : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INT_STAT_DEBUG__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int       CP_ECC_ERROR_INT_ASSERTED : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int   WRM_POLL_TIMEOUT_INT_ASSERTED : 1;
		unsigned int                                 : 1;
		unsigned int          CNTX_BUSY_INT_ASSERTED : 1;
		unsigned int         CNTX_EMPTY_INT_ASSERTED : 1;
		unsigned int                                 : 1;
		unsigned int         PRIV_INSTR_INT_ASSERTED : 1;
		unsigned int           PRIV_REG_INT_ASSERTED : 1;
		unsigned int       OPCODE_ERROR_INT_ASSERTED : 1;
		unsigned int                                 : 1;
		unsigned int         TIME_STAMP_INT_ASSERTED : 1;
		unsigned int RESERVED_BIT_ERROR_INT_ASSERTED : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IQ_WAIT_TIME1__CI__VI {
	struct {
                unsigned int                      IB_OFFLOAD : 8;
                unsigned int                  ATOMIC_OFFLOAD : 8;
                unsigned int                     WRM_OFFLOAD : 8;
                unsigned int                             GWS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_IQ_WAIT_TIME2__CI__VI {
	struct {
                unsigned int                       QUE_SLEEP : 8;
                unsigned int                        SCH_WAVE : 8;
                unsigned int                       SEM_REARM : 8;
                unsigned int                       DEQ_RETRY : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MAX_CONTEXT__CI__VI {
	struct {
                unsigned int                     MAX_CONTEXT : 3;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MC_PACK_DELAY_CNT__SI__CI {
	struct {
		unsigned int                  PACK_DELAY_CNT : 5;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MC_TAG_CNTL__CI {
	struct {
		unsigned int                   TAG_RAM_INDEX : 6;
		unsigned int                                 : 10;
		unsigned int                     TAG_RAM_SEL : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MC_TAG_DATA__CI {
	struct {
		unsigned int                    TAG_RAM_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME0_PIPE0_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME0_PIPE0_VMID__CI__VI {
	struct {
                unsigned int                            VMID : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME0_PIPE1_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME0_PIPE1_VMID__CI__VI {
	struct {
                unsigned int                            VMID : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME0_PIPE2_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME0_PIPE_PRIORITY_CNTS__CI__VI {
	struct {
                unsigned int                   PRIORITY1_CNT : 8;
                unsigned int                  PRIORITY2A_CNT : 8;
                unsigned int                  PRIORITY2B_CNT : 8;
                unsigned int                   PRIORITY3_CNT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_INT_STAT_DEBUG__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ASSERTED__VI : 1;
                unsigned int    DEQUEUE_REQUEST_INT_ASSERTED : 1;
                unsigned int       CP_ECC_ERROR_INT_ASSERTED : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int   WRM_POLL_TIMEOUT_INT_ASSERTED : 1;
                unsigned int                                 : 5;
                unsigned int           PRIV_REG_INT_ASSERTED : 1;
                unsigned int       OPCODE_ERROR_INT_ASSERTED : 1;
                unsigned int                                 : 1;
                unsigned int         TIME_STAMP_INT_ASSERTED : 1;
                unsigned int RESERVED_BIT_ERROR_INT_ASSERTED : 1;
                unsigned int                                 : 1;
                unsigned int           GENERIC2_INT_ASSERTED : 1;
                unsigned int           GENERIC1_INT_ASSERTED : 1;
                unsigned int           GENERIC0_INT_ASSERTED : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE0_INT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_ENABLE : 1;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int    SUA_VIOLATION_INT_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE0_INT_STATUS__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_STATUS : 1;
                unsigned int         CP_ECC_ERROR_INT_STATUS : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_STATUS : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_STATUS : 1;
                unsigned int         OPCODE_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_STATUS : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_STATUS : 1;
                unsigned int             GENERIC1_INT_STATUS : 1;
                unsigned int             GENERIC0_INT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE0_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE1_INT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_ENABLE : 1;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int    SUA_VIOLATION_INT_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE1_INT_STATUS__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_STATUS : 1;
                unsigned int         CP_ECC_ERROR_INT_STATUS : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_STATUS : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_STATUS : 1;
                unsigned int         OPCODE_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_STATUS : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_STATUS : 1;
                unsigned int             GENERIC1_INT_STATUS : 1;
                unsigned int             GENERIC0_INT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE1_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE2_INT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_ENABLE : 1;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int    SUA_VIOLATION_INT_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE2_INT_STATUS__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_STATUS : 1;
                unsigned int         CP_ECC_ERROR_INT_STATUS : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_STATUS : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_STATUS : 1;
                unsigned int         OPCODE_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_STATUS : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_STATUS : 1;
                unsigned int             GENERIC1_INT_STATUS : 1;
                unsigned int             GENERIC0_INT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE2_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE3_INT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_ENABLE : 1;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int    SUA_VIOLATION_INT_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE3_INT_STATUS__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_STATUS : 1;
                unsigned int         CP_ECC_ERROR_INT_STATUS : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_STATUS : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_STATUS : 1;
                unsigned int         OPCODE_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_STATUS : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_STATUS : 1;
                unsigned int             GENERIC1_INT_STATUS : 1;
                unsigned int             GENERIC0_INT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE3_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME1_PIPE_PRIORITY_CNTS__CI__VI {
	struct {
                unsigned int                   PRIORITY1_CNT : 8;
                unsigned int                  PRIORITY2A_CNT : 8;
                unsigned int                  PRIORITY2B_CNT : 8;
                unsigned int                   PRIORITY3_CNT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_INT_STAT_DEBUG__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ASSERTED__VI : 1;
                unsigned int    DEQUEUE_REQUEST_INT_ASSERTED : 1;
                unsigned int       CP_ECC_ERROR_INT_ASSERTED : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int   WRM_POLL_TIMEOUT_INT_ASSERTED : 1;
                unsigned int                                 : 5;
                unsigned int           PRIV_REG_INT_ASSERTED : 1;
                unsigned int       OPCODE_ERROR_INT_ASSERTED : 1;
                unsigned int                                 : 1;
                unsigned int         TIME_STAMP_INT_ASSERTED : 1;
                unsigned int RESERVED_BIT_ERROR_INT_ASSERTED : 1;
                unsigned int                                 : 1;
                unsigned int           GENERIC2_INT_ASSERTED : 1;
                unsigned int           GENERIC1_INT_ASSERTED : 1;
                unsigned int           GENERIC0_INT_ASSERTED : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE0_INT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_ENABLE : 1;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int    SUA_VIOLATION_INT_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE0_INT_STATUS__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_STATUS : 1;
                unsigned int         CP_ECC_ERROR_INT_STATUS : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_STATUS : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_STATUS : 1;
                unsigned int         OPCODE_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_STATUS : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_STATUS : 1;
                unsigned int             GENERIC1_INT_STATUS : 1;
                unsigned int             GENERIC0_INT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE0_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE1_INT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_ENABLE : 1;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int    SUA_VIOLATION_INT_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE1_INT_STATUS__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_STATUS : 1;
                unsigned int         CP_ECC_ERROR_INT_STATUS : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_STATUS : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_STATUS : 1;
                unsigned int         OPCODE_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_STATUS : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_STATUS : 1;
                unsigned int             GENERIC1_INT_STATUS : 1;
                unsigned int             GENERIC0_INT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE1_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE2_INT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_ENABLE : 1;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int    SUA_VIOLATION_INT_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE2_INT_STATUS__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_STATUS : 1;
                unsigned int         CP_ECC_ERROR_INT_STATUS : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_STATUS : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_STATUS : 1;
                unsigned int         OPCODE_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_STATUS : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_STATUS : 1;
                unsigned int             GENERIC1_INT_STATUS : 1;
                unsigned int             GENERIC0_INT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE2_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE3_INT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_ENABLE : 1;
                unsigned int         CP_ECC_ERROR_INT_ENABLE : 1;
                unsigned int    SUA_VIOLATION_INT_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_ENABLE : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_ENABLE : 1;
                unsigned int         OPCODE_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_ENABLE : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_ENABLE : 1;
                unsigned int             GENERIC1_INT_ENABLE : 1;
                unsigned int             GENERIC0_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE3_INT_STATUS__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1;
                unsigned int      DEQUEUE_REQUEST_INT_STATUS : 1;
                unsigned int         CP_ECC_ERROR_INT_STATUS : 1;
                unsigned int    SUA_VIOLATION_INT_STATUS__VI : 1;
                unsigned int                                 : 1;
                unsigned int     WRM_POLL_TIMEOUT_INT_STATUS : 1;
                unsigned int                                 : 5;
                unsigned int             PRIV_REG_INT_STATUS : 1;
                unsigned int         OPCODE_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int           TIME_STAMP_INT_STATUS : 1;
                unsigned int   RESERVED_BIT_ERROR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int             GENERIC2_INT_STATUS : 1;
                unsigned int             GENERIC1_INT_STATUS : 1;
                unsigned int             GENERIC0_INT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE3_PRIORITY__CI__VI {
	struct {
                unsigned int                        PRIORITY : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME2_PIPE_PRIORITY_CNTS__CI__VI {
	struct {
                unsigned int                   PRIORITY1_CNT : 8;
                unsigned int                  PRIORITY2A_CNT : 8;
                unsigned int                  PRIORITY2B_CNT : 8;
                unsigned int                   PRIORITY3_CNT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC1_F32_INTERRUPT__CI {
	struct {
		unsigned int                                 : 1;
		unsigned int                    PRIV_REG_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC1_F32_INTERRUPT__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                    PRIV_REG_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC1_INTR_ROUTINE_START__CI__VI {
	struct {
                unsigned int                        IR_START : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC1_PRGRM_CNTR_START__CI__VI {
	struct {
                unsigned int                        IP_START : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC2_F32_INTERRUPT__CI {
	struct {
		unsigned int                                 : 1;
		unsigned int                    PRIV_REG_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC2_F32_INTERRUPT__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                    PRIV_REG_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC2_INTR_ROUTINE_START__CI__VI {
	struct {
                unsigned int                        IR_START : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC2_PRGRM_CNTR_START__CI__VI {
	struct {
                unsigned int                        IP_START : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC_CNTL__CI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int           MEC_INVALIDATE_ICACHE : 1;
                unsigned int                                 : 11;
                unsigned int         MEC_ME1_PIPE0_RESET__VI : 1;
                unsigned int         MEC_ME1_PIPE1_RESET__VI : 1;
                unsigned int         MEC_ME1_PIPE2_RESET__VI : 1;
                unsigned int         MEC_ME1_PIPE3_RESET__VI : 1;
                unsigned int         MEC_ME2_PIPE0_RESET__VI : 1;
                unsigned int         MEC_ME2_PIPE1_RESET__VI : 1;
                unsigned int                                 : 6;
                unsigned int                    MEC_ME2_HALT : 1;
                unsigned int                    MEC_ME2_STEP : 1;
                unsigned int                    MEC_ME1_HALT : 1;
                unsigned int                    MEC_ME1_STEP : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC_ME1_HEADER_DUMP__CI__VI {
	struct {
                unsigned int                     HEADER_DUMP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC_ME1_UCODE_ADDR__CI__VI {
	struct {
                unsigned int                      UCODE_ADDR : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC_ME1_UCODE_DATA__CI__VI {
	struct {
                unsigned int                      UCODE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC_ME2_HEADER_DUMP__CI__VI {
	struct {
                unsigned int                     HEADER_DUMP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC_ME2_UCODE_ADDR__CI__VI {
	struct {
                unsigned int                      UCODE_ADDR : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC_ME2_UCODE_DATA__CI__VI {
	struct {
                unsigned int                      UCODE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEM_SLP_CNTL {
	struct {
                unsigned int                    CP_MEM_LS_EN : 1;
                unsigned int                    CP_MEM_DS_EN : 1;
                unsigned int                    RESERVED__VI : 5;
                unsigned int      CP_LS_DS_BUSY_OVERRIDE__VI : 1;
                unsigned int              CP_MEM_LS_ON_DELAY : 8;
                unsigned int             CP_MEM_LS_OFF_DELAY : 8;
                unsigned int                       RESERVED1 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEQ_AVAIL {
	struct {
		unsigned int                         MEQ_CNT : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEQ_STAT {
	struct {
		unsigned int                        MEQ_RPTR : 10;
		unsigned int                                 : 6;
		unsigned int                        MEQ_WPTR : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEQ_STQ_THRESHOLD__CI__VI {
	struct {
                unsigned int                       STQ_START : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEQ_THRESHOLDS {
	struct {
		unsigned int                      MEQ1_START : 8;
		unsigned int                      MEQ2_START : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_ATOMIC_PREOP_HI__CI__VI {
	struct {
                unsigned int                 ATOMIC_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_ATOMIC_PREOP_LO__CI__VI {
	struct {
                unsigned int                 ATOMIC_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_CNTL {
	struct {
                unsigned int                                 : 4;
                unsigned int    CE_INVALIDATE_ICACHE__CI__VI : 1;
                unsigned int                                 : 1;
                unsigned int   PFP_INVALIDATE_ICACHE__CI__VI : 1;
                unsigned int                                 : 1;
                unsigned int    ME_INVALIDATE_ICACHE__CI__VI : 1;
                unsigned int                                 : 7;
                unsigned int              CE_PIPE0_RESET__VI : 1;
                unsigned int                                 : 1;
                unsigned int             PFP_PIPE0_RESET__VI : 1;
                unsigned int                                 : 1;
                unsigned int              ME_PIPE0_RESET__VI : 1;
                unsigned int                                 : 3;
                unsigned int                         CE_HALT : 1;
                unsigned int                         CE_STEP : 1;
                unsigned int                        PFP_HALT : 1;
                unsigned int                        PFP_STEP : 1;
                unsigned int                         ME_HALT : 1;
                unsigned int                         ME_STEP : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_GDS_ATOMIC0_PREOP_HI__CI__VI {
	struct {
                unsigned int            GDS_ATOMIC0_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_GDS_ATOMIC0_PREOP_LO__CI__VI {
	struct {
                unsigned int            GDS_ATOMIC0_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_GDS_ATOMIC1_PREOP_HI__CI__VI {
	struct {
                unsigned int            GDS_ATOMIC1_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_GDS_ATOMIC1_PREOP_LO__CI__VI {
	struct {
                unsigned int            GDS_ATOMIC1_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_HEADER_DUMP {
	struct {
		unsigned int                  ME_HEADER_DUMP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_INTR_ROUTINE_START__CI__VI {
	struct {
                unsigned int                        IR_START : 12;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_MC_RADDR_HI {
	struct {
                unsigned int                  ME_MC_RADDR_HI : 16;
                unsigned int                                 : 4;
                unsigned int                       MTYPE__VI : 2;
                unsigned int                CACHE_POLICY__VI : 1;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_MC_RADDR_LO {
	struct {
		unsigned int                ME_MC_RADDR_SWAP : 2;
		unsigned int                  ME_MC_RADDR_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_MC_WADDR_HI {
	struct {
                unsigned int                  ME_MC_WADDR_HI : 16;
                unsigned int                                 : 4;
                unsigned int                       MTYPE__VI : 2;
                unsigned int                CACHE_POLICY__VI : 1;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_MC_WADDR_LO {
	struct {
		unsigned int                ME_MC_WADDR_SWAP : 2;
		unsigned int                  ME_MC_WADDR_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_MC_WDATA_HI {
	struct {
		unsigned int                  ME_MC_WDATA_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_MC_WDATA_LO {
	struct {
		unsigned int                  ME_MC_WDATA_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_PREEMPTION__SI__CI {
	struct {
		unsigned int            ME_CNTXSW_PREEMPTION : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_PREEMPTION__VI {
	struct {
		unsigned int                        OBSOLETE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_PRGRM_CNTR_START__CI__VI {
	struct {
                unsigned int                        IP_START : 12;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_RAM_DATA {
	struct {
		unsigned int                     ME_RAM_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_RAM_RADDR {
	struct {
                unsigned int                    ME_RAM_RADDR : 13;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ME_RAM_WADDR {
	struct {
                unsigned int                    ME_RAM_WADDR : 13;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MQD_BASE_ADDR_HI__CI__VI {
	struct {
                unsigned int                    BASE_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MQD_BASE_ADDR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                       BASE_ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MQD_CONTROL__CI {
	struct {
		unsigned int                            VMID : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 14;
		unsigned int                         MQD_ATC : 1;
		unsigned int                    CACHE_POLICY : 2;
		unsigned int                    MQD_VOLATILE : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MQD_CONTROL__VI {
	struct {
		unsigned int                            VMID : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                  PROCESSING_MQD : 1;
		unsigned int               PROCESSING_MQD_EN : 1;
		unsigned int                                 : 9;
		unsigned int                         MQD_ATC : 1;
		unsigned int                    CACHE_POLICY : 1;
		unsigned int                                 : 2;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_NEEDED_COUNT0_HI {
	struct {
		unsigned int         NUM_PRIM_NEEDED_CNT0_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_NEEDED_COUNT0_LO {
	struct {
		unsigned int         NUM_PRIM_NEEDED_CNT0_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_NEEDED_COUNT1_HI {
	struct {
		unsigned int         NUM_PRIM_NEEDED_CNT1_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_NEEDED_COUNT1_LO {
	struct {
		unsigned int         NUM_PRIM_NEEDED_CNT1_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_NEEDED_COUNT2_HI {
	struct {
		unsigned int         NUM_PRIM_NEEDED_CNT2_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_NEEDED_COUNT2_LO {
	struct {
		unsigned int         NUM_PRIM_NEEDED_CNT2_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_NEEDED_COUNT3_HI {
	struct {
		unsigned int         NUM_PRIM_NEEDED_CNT3_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_NEEDED_COUNT3_LO {
	struct {
		unsigned int         NUM_PRIM_NEEDED_CNT3_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_WRITTEN_COUNT0_HI {
	struct {
		unsigned int        NUM_PRIM_WRITTEN_CNT0_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_WRITTEN_COUNT0_LO {
	struct {
		unsigned int        NUM_PRIM_WRITTEN_CNT0_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_WRITTEN_COUNT1_HI {
	struct {
		unsigned int        NUM_PRIM_WRITTEN_CNT1_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_WRITTEN_COUNT1_LO {
	struct {
		unsigned int        NUM_PRIM_WRITTEN_CNT1_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_WRITTEN_COUNT2_HI {
	struct {
		unsigned int        NUM_PRIM_WRITTEN_CNT2_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_WRITTEN_COUNT2_LO {
	struct {
		unsigned int        NUM_PRIM_WRITTEN_CNT2_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_WRITTEN_COUNT3_HI {
	struct {
		unsigned int        NUM_PRIM_WRITTEN_CNT3_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_NUM_PRIM_WRITTEN_COUNT3_LO {
	struct {
		unsigned int        NUM_PRIM_WRITTEN_CNT3_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PA_CINVOC_COUNT_HI {
	struct {
		unsigned int                 CINVOC_COUNT_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PA_CINVOC_COUNT_LO {
	struct {
		unsigned int                 CINVOC_COUNT_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PA_CPRIM_COUNT_HI {
	struct {
		unsigned int                  CPRIM_COUNT_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PA_CPRIM_COUNT_LO {
	struct {
		unsigned int                  CPRIM_COUNT_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PERFCOUNTER_HI__SI {
	struct {
		unsigned int                                 : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PERFCOUNTER_LO__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PERFCOUNTER_SELECT__SI {
	struct {
		unsigned int                                 : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PERFMON_CNTL {
	struct {
                unsigned int                   PERFMON_STATE : 4;
                unsigned int       SPM_PERFMON_STATE__CI__VI : 4;
                unsigned int             PERFMON_ENABLE_MODE : 2;
                unsigned int           PERFMON_SAMPLE_ENABLE : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PERFMON_CNTX_CNTL {
	struct {
		unsigned int                                 : 31;
		unsigned int                  PERFMON_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_ATOMIC_PREOP_HI__CI__VI {
	struct {
                unsigned int                 ATOMIC_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_ATOMIC_PREOP_LO__CI__VI {
	struct {
                unsigned int                 ATOMIC_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_F32_INTERRUPT__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                    PRIV_REG_INT : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_GDS_ATOMIC0_PREOP_HI__CI__VI {
	struct {
                unsigned int            GDS_ATOMIC0_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_GDS_ATOMIC0_PREOP_LO__CI__VI {
	struct {
                unsigned int            GDS_ATOMIC0_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_GDS_ATOMIC1_PREOP_HI__CI__VI {
	struct {
                unsigned int            GDS_ATOMIC1_PREOP_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_GDS_ATOMIC1_PREOP_LO__CI__VI {
	struct {
                unsigned int            GDS_ATOMIC1_PREOP_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_HEADER_DUMP {
	struct {
		unsigned int                 PFP_HEADER_DUMP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_IB_CONTROL {
	struct {
                unsigned int                           IB_EN : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_INTR_ROUTINE_START__CI__VI {
	struct {
                unsigned int                        IR_START : 12;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_LOAD_CONTROL__SI__CI {
	struct {
                unsigned int                   CONFIG_REG_EN : 1;
                unsigned int                     CNTX_REG_EN : 1;
                unsigned int                                 : 13;
                unsigned int              UCONFIG_REG_EN__CI : 1;
                unsigned int                   SH_GFX_REG_EN : 1;
                unsigned int                                 : 7;
                unsigned int                    SH_CS_REG_EN : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_LOAD_CONTROL__VI {
	struct {
		unsigned int                   CONFIG_REG_EN : 1;
		unsigned int                     CNTX_REG_EN : 1;
		unsigned int                                 : 14;
		unsigned int                   SH_GFX_REG_EN : 1;
		unsigned int                                 : 7;
		unsigned int                    SH_CS_REG_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_PRGRM_CNTR_START__CI__VI {
	struct {
                unsigned int                        IP_START : 12;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_UCODE_ADDR {
	struct {
                unsigned int                      UCODE_ADDR : 13;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_UCODE_DATA {
	struct {
		unsigned int                      UCODE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PIPEID__CI__VI {
	struct {
                unsigned int                         PIPE_ID : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PIPE_STATS_ADDR_HI__CI__VI {
	struct {
                unsigned int              PIPE_STATS_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PIPE_STATS_ADDR_HI__SI {
	struct {
		unsigned int              PIPE_STATS_ADDR_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PIPE_STATS_ADDR_LO {
	struct {
                unsigned int    PIPE_STATS_ADDR_SWAP__SI__CI : 2;
                unsigned int              PIPE_STATS_ADDR_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PQ_WPTR_POLL_CNTL1__CI__VI {
	struct {
                unsigned int                      QUEUE_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PQ_WPTR_POLL_CNTL__CI__VI {
	struct {
                unsigned int                          PERIOD : 8;
                unsigned int                                 : 22;
                unsigned int                     POLL_ACTIVE : 1;
                unsigned int                              EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PRT_LOD_STATS_CNTL0__CI__VI {
	struct {
                unsigned int                         BU_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PRT_LOD_STATS_CNTL1__CI__VI {
	struct {
                unsigned int                         BASE_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PRT_LOD_STATS_CNTL2__CI__VI {
	struct {
                unsigned int                         BASE_HI : 2;
                unsigned int                        INTERVAL : 8;
                unsigned int                       RESET_CNT : 8;
                unsigned int                     RESET_FORCE : 1;
                unsigned int                REPORT_AND_RESET : 1;
                unsigned int          MC_ENDIAN_SWAP__SI__CI : 2;
                unsigned int                                 : 1;
                unsigned int                         MC_VMID : 4;
                unsigned int                                 : 1;
                unsigned int                CACHE_POLICY__VI : 1;
                unsigned int                                 : 1;
                unsigned int                       MTYPE__VI : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PWR_CNTL__CI {
	struct {
		unsigned int                    GFX_CLK_HALT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PWR_CNTL__VI {
	struct {
		unsigned int          GFX_CLK_HALT_ME0_PIPE0 : 1;
		unsigned int          GFX_CLK_HALT_ME0_PIPE1 : 1;
		unsigned int                                 : 6;
		unsigned int          CMP_CLK_HALT_ME1_PIPE0 : 1;
		unsigned int          CMP_CLK_HALT_ME1_PIPE1 : 1;
		unsigned int          CMP_CLK_HALT_ME1_PIPE2 : 1;
		unsigned int          CMP_CLK_HALT_ME1_PIPE3 : 1;
		unsigned int                                 : 4;
		unsigned int          CMP_CLK_HALT_ME2_PIPE0 : 1;
		unsigned int          CMP_CLK_HALT_ME2_PIPE1 : 1;
		unsigned int          CMP_CLK_HALT_ME2_PIPE2 : 1;
		unsigned int          CMP_CLK_HALT_ME2_PIPE3 : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PWR_CNTL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_QUEUE_THRESHOLDS {
	struct {
		unsigned int                   ROQ_IB1_START : 6;
		unsigned int                                 : 2;
		unsigned int                   ROQ_IB2_START : 6;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB0_BASE {
	struct {
		unsigned int                         RB_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB0_BASE_HI__CI__VI {
	struct {
                unsigned int                      RB_BASE_HI : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB0_CNTL__CI {
	struct {
		unsigned int                        RB_BUFSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        RB_BLKSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        BUF_SWAP : 2;
		unsigned int                                 : 2;
		unsigned int                     MIN_AVAILSZ : 2;
		unsigned int                  MIN_IB_AVAILSZ : 2;
		unsigned int                    CACHE_POLICY : 2;
		unsigned int                     RB_VOLATILE : 1;
		unsigned int                    RB_NO_UPDATE : 1;
		unsigned int                                 : 3;
		unsigned int                  RB_RPTR_WR_ENA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB0_CNTL__VI {
	struct {
		unsigned int                        RB_BUFSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        RB_BLKSZ : 6;
		unsigned int                                 : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                        BUF_SWAP : 2;
		unsigned int                                 : 1;
		unsigned int                     MIN_AVAILSZ : 2;
		unsigned int                  MIN_IB_AVAILSZ : 2;
		unsigned int                    CACHE_POLICY : 1;
		unsigned int                                 : 2;
		unsigned int                    RB_NO_UPDATE : 1;
		unsigned int                                 : 3;
		unsigned int                  RB_RPTR_WR_ENA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB0_CNTL__SI {
	struct {
		unsigned int                        RB_BUFSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        RB_BLKSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        BUF_SWAP : 2;
		unsigned int                                 : 2;
		unsigned int                     MIN_AVAILSZ : 2;
		unsigned int                  MIN_IB_AVAILSZ : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                    RB_NO_UPDATE : 1;
		unsigned int                                 : 3;
		unsigned int                  RB_RPTR_WR_ENA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB0_RPTR {
	struct {
		unsigned int                         RB_RPTR : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB0_RPTR_ADDR {
	struct {
		unsigned int                    RB_RPTR_SWAP : 2;
		unsigned int                    RB_RPTR_ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB0_RPTR_ADDR_HI {
	struct {
                unsigned int                 RB_RPTR_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB0_WPTR {
	struct {
		unsigned int                         RB_WPTR : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB1_BASE {
	struct {
		unsigned int                         RB_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB1_BASE_HI__CI__VI {
	struct {
                unsigned int                      RB_BASE_HI : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB1_CNTL__SI__CI {
	struct {
                unsigned int                        RB_BUFSZ : 6;
                unsigned int                                 : 2;
                unsigned int                        RB_BLKSZ : 6;
                unsigned int                                 : 6;
                unsigned int                     MIN_AVAILSZ : 2;
                unsigned int                  MIN_IB_AVAILSZ : 2;
                unsigned int                CACHE_POLICY__CI : 2;
                unsigned int                 RB_VOLATILE__CI : 1;
                unsigned int                    RB_NO_UPDATE : 1;
                unsigned int                                 : 3;
                unsigned int                  RB_RPTR_WR_ENA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB1_CNTL__VI {
	struct {
		unsigned int                        RB_BUFSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        RB_BLKSZ : 6;
		unsigned int                                 : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 3;
		unsigned int                     MIN_AVAILSZ : 2;
		unsigned int                  MIN_IB_AVAILSZ : 2;
		unsigned int                    CACHE_POLICY : 1;
		unsigned int                                 : 2;
		unsigned int                    RB_NO_UPDATE : 1;
		unsigned int                                 : 3;
		unsigned int                  RB_RPTR_WR_ENA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB1_RPTR {
	struct {
		unsigned int                         RB_RPTR : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB1_RPTR_ADDR {
	struct {
		unsigned int                    RB_RPTR_SWAP : 2;
		unsigned int                    RB_RPTR_ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB1_RPTR_ADDR_HI {
	struct {
                unsigned int                 RB_RPTR_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB1_WPTR {
	struct {
		unsigned int                         RB_WPTR : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB2_BASE {
	struct {
		unsigned int                         RB_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB2_CNTL__SI__CI {
	struct {
                unsigned int                        RB_BUFSZ : 6;
                unsigned int                                 : 2;
                unsigned int                        RB_BLKSZ : 6;
                unsigned int                                 : 6;
                unsigned int                     MIN_AVAILSZ : 2;
                unsigned int                  MIN_IB_AVAILSZ : 2;
                unsigned int                CACHE_POLICY__CI : 2;
                unsigned int                 RB_VOLATILE__CI : 1;
                unsigned int                    RB_NO_UPDATE : 1;
                unsigned int                                 : 3;
                unsigned int                  RB_RPTR_WR_ENA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB2_CNTL__VI {
	struct {
		unsigned int                        RB_BUFSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        RB_BLKSZ : 6;
		unsigned int                                 : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 3;
		unsigned int                     MIN_AVAILSZ : 2;
		unsigned int                  MIN_IB_AVAILSZ : 2;
		unsigned int                    CACHE_POLICY : 1;
		unsigned int                                 : 2;
		unsigned int                    RB_NO_UPDATE : 1;
		unsigned int                                 : 3;
		unsigned int                  RB_RPTR_WR_ENA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB2_RPTR {
	struct {
		unsigned int                         RB_RPTR : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB2_RPTR_ADDR {
	struct {
		unsigned int                    RB_RPTR_SWAP : 2;
		unsigned int                    RB_RPTR_ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB2_RPTR_ADDR_HI {
	struct {
                unsigned int                 RB_RPTR_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB2_WPTR {
	struct {
		unsigned int                         RB_WPTR : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_BASE {
	struct {
		unsigned int                         RB_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_CNTL__CI {
	struct {
		unsigned int                        RB_BUFSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        RB_BLKSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        BUF_SWAP : 2;
		unsigned int                                 : 2;
		unsigned int                     MIN_AVAILSZ : 2;
		unsigned int                  MIN_IB_AVAILSZ : 2;
		unsigned int                    CACHE_POLICY : 2;
		unsigned int                     RB_VOLATILE : 1;
		unsigned int                    RB_NO_UPDATE : 1;
		unsigned int                                 : 3;
		unsigned int                  RB_RPTR_WR_ENA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_CNTL__VI {
	struct {
		unsigned int                        RB_BUFSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        RB_BLKSZ : 6;
		unsigned int                                 : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                        BUF_SWAP : 2;
		unsigned int                                 : 1;
		unsigned int                     MIN_AVAILSZ : 2;
		unsigned int                  MIN_IB_AVAILSZ : 2;
		unsigned int                    CACHE_POLICY : 1;
		unsigned int                                 : 2;
		unsigned int                    RB_NO_UPDATE : 1;
		unsigned int                                 : 3;
		unsigned int                  RB_RPTR_WR_ENA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_CNTL__SI {
	struct {
		unsigned int                        RB_BUFSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        RB_BLKSZ : 6;
		unsigned int                                 : 2;
		unsigned int                        BUF_SWAP : 2;
		unsigned int                                 : 2;
		unsigned int                     MIN_AVAILSZ : 2;
		unsigned int                  MIN_IB_AVAILSZ : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                    RB_NO_UPDATE : 1;
		unsigned int                                 : 3;
		unsigned int                  RB_RPTR_WR_ENA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_OFFSET {
	struct {
		unsigned int                       RB_OFFSET : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_RPTR {
	struct {
		unsigned int                         RB_RPTR : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_RPTR_ADDR {
	struct {
		unsigned int                    RB_RPTR_SWAP : 2;
		unsigned int                    RB_RPTR_ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_RPTR_ADDR_HI {
	struct {
                unsigned int                 RB_RPTR_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_RPTR_WR {
	struct {
		unsigned int                      RB_RPTR_WR : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_VMID {
	struct {
		unsigned int                        RB0_VMID : 4;
		unsigned int                                 : 4;
		unsigned int                        RB1_VMID : 4;
		unsigned int                                 : 4;
		unsigned int                        RB2_VMID : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_WPTR {
	struct {
		unsigned int                         RB_WPTR : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_WPTR_DELAY {
	struct {
		unsigned int                 PRE_WRITE_TIMER : 28;
		unsigned int                 PRE_WRITE_LIMIT : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_WPTR_POLL_ADDR_HI__CI {
	struct {
		unsigned int                        OBSOLETE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_WPTR_POLL_ADDR_HI__VI {
	struct {
		unsigned int            RB_WPTR_POLL_ADDR_HI : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_WPTR_POLL_ADDR_HI__SI {
	struct {
		unsigned int            RB_WPTR_POLL_ADDR_HI : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_WPTR_POLL_ADDR_LO__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                        OBSOLETE : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_WPTR_POLL_ADDR_LO__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int            RB_WPTR_POLL_ADDR_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_WPTR_POLL_ADDR_LO__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int            RB_WPTR_POLL_ADDR_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_WPTR_POLL_CNTL {
	struct {
		unsigned int                  POLL_FREQUENCY : 16;
		unsigned int                 IDLE_POLL_COUNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RING0_PRIORITY {
	struct {
		unsigned int                        PRIORITY : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RING1_PRIORITY {
	struct {
		unsigned int                        PRIORITY : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RING2_PRIORITY {
	struct {
		unsigned int                        PRIORITY : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RINGID {
	struct {
		unsigned int                          RINGID : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RING_PRIORITY_CNTS {
	struct {
		unsigned int                   PRIORITY1_CNT : 8;
		unsigned int                  PRIORITY2A_CNT : 8;
		unsigned int                  PRIORITY2B_CNT : 8;
		unsigned int                   PRIORITY3_CNT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ROQ1_THRESHOLDS {
	struct {
		unsigned int                       RB1_START : 8;
		unsigned int                       RB2_START : 8;
		unsigned int                    R0_IB1_START : 8;
		unsigned int                    R1_IB1_START : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ROQ2_AVAIL {
	struct {
		unsigned int                     ROQ_CNT_IB2 : 11;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ROQ2_THRESHOLDS {
	struct {
		unsigned int                    R2_IB1_START : 8;
		unsigned int                    R0_IB2_START : 8;
		unsigned int                    R1_IB2_START : 8;
		unsigned int                    R2_IB2_START : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ROQ_AVAIL {
	struct {
		unsigned int                    ROQ_CNT_RING : 11;
		unsigned int                                 : 5;
		unsigned int                     ROQ_CNT_IB1 : 11;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ROQ_IB1_STAT {
	struct {
		unsigned int              ROQ_RPTR_INDIRECT1 : 10;
		unsigned int                                 : 6;
		unsigned int              ROQ_WPTR_INDIRECT1 : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ROQ_IB2_STAT {
	struct {
		unsigned int              ROQ_RPTR_INDIRECT2 : 10;
		unsigned int                                 : 6;
		unsigned int              ROQ_WPTR_INDIRECT2 : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ROQ_RB_STAT {
	struct {
		unsigned int                ROQ_RPTR_PRIMARY : 10;
		unsigned int                                 : 6;
		unsigned int                ROQ_WPTR_PRIMARY : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ROQ_THRESHOLDS__CI__VI {
	struct {
                unsigned int                       IB1_START : 8;
                unsigned int                       IB2_START : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SCRATCH_DATA {
	struct {
		unsigned int                    SCRATCH_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SCRATCH_INDEX {
	struct {
		unsigned int                   SCRATCH_INDEX : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SC_PSINVOC_COUNT0_HI {
	struct {
		unsigned int               PSINVOC_COUNT0_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SC_PSINVOC_COUNT0_LO {
	struct {
		unsigned int               PSINVOC_COUNT0_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SC_PSINVOC_COUNT1_HI__CI__VI {
	struct {
                unsigned int                        OBSOLETE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SC_PSINVOC_COUNT1_HI__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SC_PSINVOC_COUNT1_LO__CI__VI {
	struct {
                unsigned int                        OBSOLETE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SC_PSINVOC_COUNT1_LO__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SEM_WAIT_TIMER {
	struct {
		unsigned int                  SEM_WAIT_TIMER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SIG_SEM_ADDR_HI {
	struct {
                unsigned int                     SEM_ADDR_HI : 16;
                unsigned int                 SEM_USE_MAILBOX : 1;
                unsigned int                                 : 3;
                unsigned int                 SEM_SIGNAL_TYPE : 1;
                unsigned int                                 : 3;
                unsigned int                 SEM_CLIENT_CODE : 2;
                unsigned int                                 : 3;
                unsigned int                      SEM_SELECT : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SIG_SEM_ADDR_LO {
	struct {
		unsigned int                   SEM_ADDR_SWAP : 2;
		unsigned int                                 : 1;
		unsigned int                     SEM_ADDR_LO : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STALLED_STAT1__CI {
	struct {
		unsigned int      RBIU_TO_DMA_NOT_RDY_TO_RCV : 1;
		unsigned int                                 : 1;
		unsigned int      RBIU_TO_SEM_NOT_RDY_TO_RCV : 1;
		unsigned int                                 : 1;
		unsigned int    RBIU_TO_MEMWR_NOT_RDY_TO_RCV : 1;
		unsigned int                                 : 5;
		unsigned int    ME_HAS_ACTIVE_CE_BUFFER_FLAG : 1;
		unsigned int    ME_HAS_ACTIVE_DE_BUFFER_FLAG : 1;
		unsigned int     ME_STALLED_ON_TC_WR_CONFIRM : 1;
		unsigned int   ME_STALLED_ON_ATOMIC_RTN_DATA : 1;
		unsigned int      ME_WAITING_ON_MC_READ_DATA : 1;
		unsigned int     ME_WAITING_ON_REG_READ_DATA : 1;
		unsigned int       MIU_WAITING_ON_RDREQ_FREE : 1;
		unsigned int       MIU_WAITING_ON_WRREQ_FREE : 1;
		unsigned int                                 : 5;
		unsigned int        RCIU_WAITING_ON_GDS_FREE : 1;
		unsigned int       RCIU_WAITING_ON_GRBM_FREE : 1;
		unsigned int        RCIU_WAITING_ON_VGT_FREE : 1;
		unsigned int         RCIU_STALLED_ON_ME_READ : 1;
		unsigned int        RCIU_STALLED_ON_DMA_READ : 1;
		unsigned int     RCIU_STALLED_ON_APPEND_READ : 1;
		unsigned int    RCIU_HALTED_BY_REG_VIOLATION : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STALLED_STAT1__VI {
	struct {
		unsigned int      RBIU_TO_DMA_NOT_RDY_TO_RCV : 1;
		unsigned int                                 : 1;
		unsigned int      RBIU_TO_SEM_NOT_RDY_TO_RCV : 1;
		unsigned int                                 : 1;
		unsigned int    RBIU_TO_MEMWR_NOT_RDY_TO_RCV : 1;
		unsigned int                                 : 5;
		unsigned int    ME_HAS_ACTIVE_CE_BUFFER_FLAG : 1;
		unsigned int    ME_HAS_ACTIVE_DE_BUFFER_FLAG : 1;
		unsigned int     ME_STALLED_ON_TC_WR_CONFIRM : 1;
		unsigned int   ME_STALLED_ON_ATOMIC_RTN_DATA : 1;
		unsigned int      ME_WAITING_ON_TC_READ_DATA : 1;
		unsigned int     ME_WAITING_ON_REG_READ_DATA : 1;
		unsigned int                                 : 7;
		unsigned int        RCIU_WAITING_ON_GDS_FREE : 1;
		unsigned int       RCIU_WAITING_ON_GRBM_FREE : 1;
		unsigned int        RCIU_WAITING_ON_VGT_FREE : 1;
		unsigned int         RCIU_STALLED_ON_ME_READ : 1;
		unsigned int        RCIU_STALLED_ON_DMA_READ : 1;
		unsigned int     RCIU_STALLED_ON_APPEND_READ : 1;
		unsigned int    RCIU_HALTED_BY_REG_VIOLATION : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STALLED_STAT1__SI {
	struct {
		unsigned int      RBIU_TO_DMA_NOT_RDY_TO_RCV : 1;
		unsigned int                                 : 1;
		unsigned int      RBIU_TO_SEM_NOT_RDY_TO_RCV : 1;
		unsigned int                                 : 1;
		unsigned int    RBIU_TO_MEMWR_NOT_RDY_TO_RCV : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int    ME_HAS_ACTIVE_CE_BUFFER_FLAG : 1;
		unsigned int    ME_HAS_ACTIVE_DE_BUFFER_FLAG : 1;
		unsigned int     ME_STALLED_ON_TC_WR_CONFIRM : 1;
		unsigned int   ME_STALLED_ON_ATOMIC_RTN_DATA : 1;
		unsigned int      ME_WAITING_ON_MC_READ_DATA : 1;
		unsigned int     ME_WAITING_ON_REG_READ_DATA : 1;
		unsigned int       MIU_WAITING_ON_RDREQ_FREE : 1;
		unsigned int       MIU_WAITING_ON_WRREQ_FREE : 1;
		unsigned int                                 : 5;
		unsigned int        RCIU_WAITING_ON_GDS_FREE : 1;
		unsigned int       RCIU_WAITING_ON_GRBM_FREE : 1;
		unsigned int        RCIU_WAITING_ON_VGT_FREE : 1;
		unsigned int         RCIU_STALLED_ON_ME_READ : 1;
		unsigned int        RCIU_STALLED_ON_DMA_READ : 1;
		unsigned int    RCIU_HALTED_BY_REG_VIOLATION : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STALLED_STAT2 {
	struct {
                unsigned int       PFP_TO_CSF_NOT_RDY_TO_RCV : 1;
                unsigned int       PFP_TO_MEQ_NOT_RDY_TO_RCV : 1;
                unsigned int      PFP_TO_RCIU_NOT_RDY_TO_RCV : 1;
                unsigned int                                 : 1;
                unsigned int       PFP_TO_VGT_WRITES_PENDING : 1;
                unsigned int           PFP_RCIU_READ_PENDING : 1;
                unsigned int            PFP_MIU_READ_PENDING : 1;
                unsigned int PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV : 1;
                unsigned int      PFP_WAITING_ON_BUFFER_DATA : 1;
                unsigned int           ME_WAIT_ON_CE_COUNTER : 1;
                unsigned int         ME_WAIT_ON_AVAIL_BUFFER : 1;
                unsigned int        GFX_CNTX_NOT_AVAIL_TO_ME : 1;
                unsigned int          ME_RCIU_NOT_RDY_TO_RCV : 1;
                unsigned int      ME_TO_CONST_NOT_RDY_TO_RCV : 1;
                unsigned int        ME_WAITING_DATA_FROM_PFP : 1;
                unsigned int     ME_WAITING_ON_PARTIAL_FLUSH : 1;
                unsigned int        MEQ_TO_ME_NOT_RDY_TO_RCV : 1;
                unsigned int        STQ_TO_ME_NOT_RDY_TO_RCV : 1;
                unsigned int        ME_WAITING_DATA_FROM_STQ : 1;
                unsigned int PFP_STALLED_ON_TC_WR_CONFIRM__CI__VI : 1;
                unsigned int PFP_STALLED_ON_ATOMIC_RTN_DATA__CI__VI : 1;
                unsigned int     EOPD_FIFO_NEEDS_SC_EOP_DONE : 1;
                unsigned int      EOPD_FIFO_NEEDS_WR_CONFIRM : 1;
                unsigned int   STRMO_WR_OF_PRIM_DATA_PENDING : 1;
                unsigned int      PIPE_STATS_WR_DATA_PENDING : 1;
                unsigned int      APPEND_RDY_WAIT_ON_CS_DONE : 1;
                unsigned int      APPEND_RDY_WAIT_ON_PS_DONE : 1;
                unsigned int       APPEND_WAIT_ON_WR_CONFIRM : 1;
                unsigned int         APPEND_ACTIVE_PARTITION : 1;
                unsigned int APPEND_WAITING_TO_SEND_MEMWRITE : 1;
                unsigned int      SURF_SYNC_NEEDS_IDLE_CNTXS : 1;
                unsigned int       SURF_SYNC_NEEDS_ALL_CLEAN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STALLED_STAT3 {
	struct {
                unsigned int        CE_TO_CSF_NOT_RDY_TO_RCV : 1;
                unsigned int CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV : 1;
                unsigned int CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER : 1;
                unsigned int          CE_TO_RAM_INIT_NOT_RDY : 1;
                unsigned int          CE_TO_RAM_DUMP_NOT_RDY : 1;
                unsigned int         CE_TO_RAM_WRITE_NOT_RDY : 1;
                unsigned int   CE_TO_INC_FIFO_NOT_RDY_TO_RCV : 1;
                unsigned int    CE_TO_WR_FIFO_NOT_RDY_TO_RCV : 1;
                unsigned int CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SI__CI : 1;
                unsigned int                                 : 1;
                unsigned int       CE_WAITING_ON_BUFFER_DATA : 1;
                unsigned int    CE_WAITING_ON_CE_BUFFER_FLAG : 1;
                unsigned int        CE_WAITING_ON_DE_COUNTER : 1;
                unsigned int CE_WAITING_ON_DE_COUNTER_UNDERFLOW : 1;
                unsigned int            TCIU_WAITING_ON_FREE : 1;
                unsigned int            TCIU_WAITING_ON_TAGS : 1;
                unsigned int CE_STALLED_ON_TC_WR_CONFIRM__VI : 1;
                unsigned int CE_STALLED_ON_ATOMIC_RTN_DATA__VI : 1;
                unsigned int     ATCL2IU_WAITING_ON_FREE__VI : 1;
                unsigned int     ATCL2IU_WAITING_ON_TAGS__VI : 1;
                unsigned int      ATCL1_WAITING_ON_TRANS__VI : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STAT__CI {
	struct {
		unsigned int                                 : 7;
		unsigned int                  MIU_RDREQ_BUSY : 1;
		unsigned int                  MIU_WRREQ_BUSY : 1;
		unsigned int                   ROQ_RING_BUSY : 1;
		unsigned int              ROQ_INDIRECT1_BUSY : 1;
		unsigned int              ROQ_INDIRECT2_BUSY : 1;
		unsigned int                  ROQ_STATE_BUSY : 1;
		unsigned int                         DC_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                        PFP_BUSY : 1;
		unsigned int                        MEQ_BUSY : 1;
		unsigned int                         ME_BUSY : 1;
		unsigned int                      QUERY_BUSY : 1;
		unsigned int                  SEMAPHORE_BUSY : 1;
		unsigned int                  INTERRUPT_BUSY : 1;
		unsigned int               SURFACE_SYNC_BUSY : 1;
		unsigned int                        DMA_BUSY : 1;
		unsigned int                       RCIU_BUSY : 1;
		unsigned int                SCRATCH_RAM_BUSY : 1;
		unsigned int                    CPC_CPG_BUSY : 1;
		unsigned int                         CE_BUSY : 1;
		unsigned int                       TCIU_BUSY : 1;
		unsigned int                ROQ_CE_RING_BUSY : 1;
		unsigned int           ROQ_CE_INDIRECT1_BUSY : 1;
		unsigned int           ROQ_CE_INDIRECT2_BUSY : 1;
		unsigned int                         CP_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STAT__VI {
	struct {
		unsigned int                                 : 9;
		unsigned int                   ROQ_RING_BUSY : 1;
		unsigned int              ROQ_INDIRECT1_BUSY : 1;
		unsigned int              ROQ_INDIRECT2_BUSY : 1;
		unsigned int                  ROQ_STATE_BUSY : 1;
		unsigned int                         DC_BUSY : 1;
		unsigned int                    ATCL2IU_BUSY : 1;
		unsigned int                        PFP_BUSY : 1;
		unsigned int                        MEQ_BUSY : 1;
		unsigned int                         ME_BUSY : 1;
		unsigned int                      QUERY_BUSY : 1;
		unsigned int                  SEMAPHORE_BUSY : 1;
		unsigned int                  INTERRUPT_BUSY : 1;
		unsigned int               SURFACE_SYNC_BUSY : 1;
		unsigned int                        DMA_BUSY : 1;
		unsigned int                       RCIU_BUSY : 1;
		unsigned int                SCRATCH_RAM_BUSY : 1;
		unsigned int                    CPC_CPG_BUSY : 1;
		unsigned int                         CE_BUSY : 1;
		unsigned int                       TCIU_BUSY : 1;
		unsigned int                ROQ_CE_RING_BUSY : 1;
		unsigned int           ROQ_CE_INDIRECT1_BUSY : 1;
		unsigned int           ROQ_CE_INDIRECT2_BUSY : 1;
		unsigned int                         CP_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STAT__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                  MIU_RDREQ_BUSY : 1;
		unsigned int                  MIU_WRREQ_BUSY : 1;
		unsigned int                   ROQ_RING_BUSY : 1;
		unsigned int              ROQ_INDIRECT1_BUSY : 1;
		unsigned int              ROQ_INDIRECT2_BUSY : 1;
		unsigned int                  ROQ_STATE_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                        PFP_BUSY : 1;
		unsigned int                        MEQ_BUSY : 1;
		unsigned int                         ME_BUSY : 1;
		unsigned int                      QUERY_BUSY : 1;
		unsigned int                  SEMAPHORE_BUSY : 1;
		unsigned int                  INTERRUPT_BUSY : 1;
		unsigned int               SURFACE_SYNC_BUSY : 1;
		unsigned int                        DMA_BUSY : 1;
		unsigned int                       RCIU_BUSY : 1;
		unsigned int                SCRATCH_RAM_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                         CE_BUSY : 1;
		unsigned int                       TCIU_BUSY : 1;
		unsigned int                ROQ_CE_RING_BUSY : 1;
		unsigned int           ROQ_CE_INDIRECT1_BUSY : 1;
		unsigned int           ROQ_CE_INDIRECT2_BUSY : 1;
		unsigned int                         CP_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STQ_AVAIL {
	struct {
		unsigned int                         STQ_CNT : 9;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STQ_STAT {
	struct {
                unsigned int                        STQ_RPTR : 10;
                unsigned int                                 : 6;
                unsigned int                                 : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STQ_THRESHOLDS {
	struct {
		unsigned int                      STQ0_START : 8;
		unsigned int                      STQ1_START : 8;
		unsigned int                      STQ2_START : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STQ_WR_STAT__CI__VI {
	struct {
                unsigned int                        STQ_WPTR : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STREAM_OUT_ADDR_HI__CI__VI {
	struct {
                unsigned int              STREAM_OUT_ADDR_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STREAM_OUT_ADDR_HI__SI {
	struct {
		unsigned int              STREAM_OUT_ADDR_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STREAM_OUT_ADDR_LO {
	struct {
                unsigned int    STREAM_OUT_ADDR_SWAP__SI__CI : 2;
                unsigned int              STREAM_OUT_ADDR_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STRMOUT_CNTL {
	struct {
		unsigned int              OFFSET_UPDATE_DONE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ST_BASE_HI {
	struct {
                unsigned int                      ST_BASE_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ST_BASE_LO {
	struct {
		unsigned int                                 : 2;
		unsigned int                      ST_BASE_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_ST_BUFSZ {
	struct {
		unsigned int                        ST_BUFSZ : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_CSINVOC_COUNT_HI {
	struct {
		unsigned int                CSINVOC_COUNT_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_CSINVOC_COUNT_LO {
	struct {
		unsigned int                CSINVOC_COUNT_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_DSINVOC_COUNT_HI {
	struct {
		unsigned int                DSINVOC_COUNT_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_DSINVOC_COUNT_LO {
	struct {
		unsigned int                DSINVOC_COUNT_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_GSINVOC_COUNT_HI {
	struct {
		unsigned int                GSINVOC_COUNT_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_GSINVOC_COUNT_LO {
	struct {
		unsigned int                GSINVOC_COUNT_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_GSPRIM_COUNT_HI {
	struct {
		unsigned int                 GSPRIM_COUNT_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_GSPRIM_COUNT_LO {
	struct {
		unsigned int                 GSPRIM_COUNT_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_HSINVOC_COUNT_HI {
	struct {
		unsigned int                HSINVOC_COUNT_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_HSINVOC_COUNT_LO {
	struct {
		unsigned int                HSINVOC_COUNT_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_IAPRIM_COUNT_HI {
	struct {
		unsigned int                 IAPRIM_COUNT_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_IAPRIM_COUNT_LO {
	struct {
		unsigned int                 IAPRIM_COUNT_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_IAVERT_COUNT_HI {
	struct {
		unsigned int                 IAVERT_COUNT_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_IAVERT_COUNT_LO {
	struct {
		unsigned int                 IAVERT_COUNT_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_VSINVOC_COUNT_HI {
	struct {
		unsigned int                VSINVOC_COUNT_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VGT_VSINVOC_COUNT_LO {
	struct {
		unsigned int                VSINVOC_COUNT_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VMID {
	struct {
		unsigned int                            VMID : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VMID_PREEMPT__CI {
	struct {
		unsigned int                 PREEMPT_REQUEST : 16;
		unsigned int                  PREEMPT_STATUS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VMID_PREEMPT__VI {
	struct {
		unsigned int                 PREEMPT_REQUEST : 16;
		unsigned int                    VIRT_COMMAND : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VMID_RESET__CI__VI {
	struct {
                unsigned int                   RESET_REQUEST : 16;
                unsigned int                    RESET_STATUS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_WAIT_REG_MEM_TIMEOUT {
	struct {
		unsigned int            WAIT_REG_MEM_TIMEOUT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_WAIT_SEM_ADDR_HI {
	struct {
                unsigned int                     SEM_ADDR_HI : 16;
                unsigned int                 SEM_USE_MAILBOX : 1;
                unsigned int                                 : 3;
                unsigned int                 SEM_SIGNAL_TYPE : 1;
                unsigned int                                 : 3;
                unsigned int                 SEM_CLIENT_CODE : 2;
                unsigned int                                 : 3;
                unsigned int                      SEM_SELECT : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_WAIT_SEM_ADDR_LO {
	struct {
		unsigned int                   SEM_ADDR_SWAP : 2;
		unsigned int                                 : 1;
		unsigned int                     SEM_ADDR_LO : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT00__SI__VI {
	struct {
                unsigned int                         H_TOTAL : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT01__SI__VI {
	struct {
                unsigned int                      H_DISP_END : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT02__SI__VI {
	struct {
                unsigned int                   H_BLANK_START : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT03__SI__VI {
	struct {
                unsigned int                     H_BLANK_END : 5;
                unsigned int                       H_DE_SKEW : 2;
                unsigned int                CR10CR11_R_DIS_B : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT04__SI__VI {
	struct {
                unsigned int                    H_SYNC_START : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT05__SI__VI {
	struct {
                unsigned int                      H_SYNC_END : 5;
                unsigned int                     H_SYNC_SKEW : 2;
                unsigned int                  H_BLANK_END_B5 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT06__SI__VI {
	struct {
                unsigned int                         V_TOTAL : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT07__SI__VI {
	struct {
                unsigned int                      V_TOTAL_B8 : 1;
                unsigned int                   V_DISP_END_B8 : 1;
                unsigned int                 V_SYNC_START_B8 : 1;
                unsigned int                V_BLANK_START_B8 : 1;
                unsigned int                     LINE_CMP_B8 : 1;
                unsigned int                      V_TOTAL_B9 : 1;
                unsigned int                   V_DISP_END_B9 : 1;
                unsigned int                 V_SYNC_START_B9 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT08__SI__VI {
	struct {
                unsigned int                  ROW_SCAN_START : 5;
                unsigned int                        BYTE_PAN : 2;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT09__SI__VI {
	struct {
                unsigned int                    MAX_ROW_SCAN : 5;
                unsigned int                V_BLANK_START_B9 : 1;
                unsigned int                     LINE_CMP_B9 : 1;
                unsigned int              DOUBLE_CHAR_HEIGHT : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT0A__SI__VI {
	struct {
                unsigned int                    CURSOR_START : 5;
                unsigned int                  CURSOR_DISABLE : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT0B__SI__VI {
	struct {
                unsigned int                      CURSOR_END : 5;
                unsigned int                     CURSOR_SKEW : 2;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT0C__SI__VI {
	struct {
                unsigned int                      DISP_START : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT0D__SI__VI {
	struct {
                unsigned int                      DISP_START : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT0E__SI__VI {
	struct {
                unsigned int                   CURSOR_LOC_HI : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT0F__SI__VI {
	struct {
                unsigned int                   CURSOR_LOC_LO : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT10__SI__VI {
	struct {
                unsigned int                    V_SYNC_START : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT11__SI__VI {
	struct {
                unsigned int                      V_SYNC_END : 4;
                unsigned int                      V_INTR_CLR : 1;
                unsigned int                       V_INTR_EN : 1;
                unsigned int                SEL5_REFRESH_CYC : 1;
                unsigned int                    C0T7_WR_ONLY : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT12__SI__VI {
	struct {
                unsigned int                      V_DISP_END : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT13__SI__VI {
	struct {
                unsigned int                      DISP_PITCH : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT14__SI__VI {
	struct {
                unsigned int                      UNDRLN_LOC : 5;
                unsigned int                    ADDR_CNT_BY4 : 1;
                unsigned int                     DOUBLE_WORD : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT15__SI__VI {
	struct {
                unsigned int                   V_BLANK_START : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT16__SI__VI {
	struct {
                unsigned int                     V_BLANK_END : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT17__SI__VI {
	struct {
                unsigned int                     RA0_AS_A13B : 1;
                unsigned int                     RA1_AS_A14B : 1;
                unsigned int                      VCOUNT_BY2 : 1;
                unsigned int                    ADDR_CNT_BY2 : 1;
                unsigned int                                 : 1;
                unsigned int                    WRAP_A15TOA0 : 1;
                unsigned int                       BYTE_MODE : 1;
                unsigned int                    CRTC_SYNC_EN : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT18__SI__VI {
	struct {
                unsigned int                        LINE_CMP : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT1E__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                    GRPH_DEC_RD1 : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT1F__SI__VI {
	struct {
                unsigned int                    GRPH_DEC_RD0 : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRT22__SI__VI {
	struct {
                unsigned int                 GRPH_LATCH_DATA : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC0_PIXEL_RATE_CNTL__SI {
	struct {
		unsigned int         CRTC0_PIXEL_RATE_SOURCE : 1;
		unsigned int                  DP_DTO0_ENABLE : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC0_PIXEL_RATE_CNTL__VI {
	struct {
		unsigned int         CRTC0_PIXEL_RATE_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int                  DP_DTO0_ENABLE : 1;
		unsigned int              DP_DTO0_DS_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int                 CRTC0_ADD_PIXEL : 1;
		unsigned int                CRTC0_DROP_PIXEL : 1;
		unsigned int                                 : 4;
		unsigned int        CRTC0_DISPOUT_FIFO_ERROR : 2;
		unsigned int       CRTC0_DISPOUT_ERROR_COUNT : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC1_PIXEL_RATE_CNTL__SI {
	struct {
		unsigned int         CRTC1_PIXEL_RATE_SOURCE : 1;
		unsigned int                  DP_DTO1_ENABLE : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC1_PIXEL_RATE_CNTL__VI {
	struct {
		unsigned int         CRTC1_PIXEL_RATE_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int                  DP_DTO1_ENABLE : 1;
		unsigned int              DP_DTO1_DS_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int                 CRTC1_ADD_PIXEL : 1;
		unsigned int                CRTC1_DROP_PIXEL : 1;
		unsigned int                                 : 4;
		unsigned int        CRTC1_DISPOUT_FIFO_ERROR : 2;
		unsigned int       CRTC1_DISPOUT_ERROR_COUNT : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC2_PIXEL_RATE_CNTL__SI {
	struct {
		unsigned int         CRTC2_PIXEL_RATE_SOURCE : 1;
		unsigned int                  DP_DTO2_ENABLE : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC2_PIXEL_RATE_CNTL__VI {
	struct {
		unsigned int         CRTC2_PIXEL_RATE_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int                  DP_DTO2_ENABLE : 1;
		unsigned int              DP_DTO2_DS_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int                 CRTC2_ADD_PIXEL : 1;
		unsigned int                CRTC2_DROP_PIXEL : 1;
		unsigned int                                 : 4;
		unsigned int        CRTC2_DISPOUT_FIFO_ERROR : 2;
		unsigned int       CRTC2_DISPOUT_ERROR_COUNT : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC3_PIXEL_RATE_CNTL__SI {
	struct {
		unsigned int         CRTC3_PIXEL_RATE_SOURCE : 1;
		unsigned int                  DP_DTO3_ENABLE : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC3_PIXEL_RATE_CNTL__VI {
	struct {
		unsigned int         CRTC3_PIXEL_RATE_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int                  DP_DTO3_ENABLE : 1;
		unsigned int              DP_DTO3_DS_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int                 CRTC3_ADD_PIXEL : 1;
		unsigned int                CRTC3_DROP_PIXEL : 1;
		unsigned int                                 : 4;
		unsigned int        CRTC3_DISPOUT_FIFO_ERROR : 2;
		unsigned int       CRTC3_DISPOUT_ERROR_COUNT : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC4_PIXEL_RATE_CNTL__SI {
	struct {
		unsigned int         CRTC4_PIXEL_RATE_SOURCE : 1;
		unsigned int                  DP_DTO4_ENABLE : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC4_PIXEL_RATE_CNTL__VI {
	struct {
		unsigned int         CRTC4_PIXEL_RATE_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int                  DP_DTO4_ENABLE : 1;
		unsigned int              DP_DTO4_DS_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int                 CRTC4_ADD_PIXEL : 1;
		unsigned int                CRTC4_DROP_PIXEL : 1;
		unsigned int                                 : 4;
		unsigned int        CRTC4_DISPOUT_FIFO_ERROR : 2;
		unsigned int       CRTC4_DISPOUT_ERROR_COUNT : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC5_PIXEL_RATE_CNTL__SI {
	struct {
		unsigned int         CRTC5_PIXEL_RATE_SOURCE : 1;
		unsigned int                  DP_DTO5_ENABLE : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC5_PIXEL_RATE_CNTL__VI {
	struct {
		unsigned int         CRTC5_PIXEL_RATE_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int                  DP_DTO5_ENABLE : 1;
		unsigned int              DP_DTO5_DS_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int                 CRTC5_ADD_PIXEL : 1;
		unsigned int                CRTC5_DROP_PIXEL : 1;
		unsigned int                                 : 4;
		unsigned int        CRTC5_DISPOUT_FIFO_ERROR : 2;
		unsigned int       CRTC5_DISPOUT_ERROR_COUNT : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC8_DATA__SI__VI {
	struct {
                unsigned int                      VCRTC_DATA : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC8_IDX__SI__VI {
	struct {
                unsigned int                       VCRTC_IDX : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_ALLOW_STOP_OFF_V_CNT__SI__VI {
	struct {
                unsigned int       CRTC_ALLOW_STOP_OFF_V_CNT : 8;
                unsigned int                                 : 8;
                unsigned int CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_BLACK_COLOR__SI__VI {
	struct {
                unsigned int           CRTC_BLACK_COLOR_B_CB : 10;
                unsigned int            CRTC_BLACK_COLOR_G_Y : 10;
                unsigned int           CRTC_BLACK_COLOR_R_CR : 10;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_BLANK_CONTROL {
	struct {
		unsigned int        CRTC_CURRENT_BLANK_STATE : 1;
		unsigned int                                 : 7;
		unsigned int              CRTC_BLANK_DATA_EN : 1;
		unsigned int                                 : 7;
		unsigned int              CRTC_BLANK_DE_MODE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_BLANK_DATA_COLOR__SI__VI {
	struct {
                unsigned int   CRTC_BLANK_DATA_COLOR_BLUE_CB : 10;
                unsigned int   CRTC_BLANK_DATA_COLOR_GREEN_Y : 10;
                unsigned int    CRTC_BLANK_DATA_COLOR_RED_CR : 10;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CONTROL__SI {
	struct {
		unsigned int                  CRTC_MASTER_EN : 1;
		unsigned int                                 : 3;
		unsigned int             CRTC_SYNC_RESET_SEL : 1;
		unsigned int                                 : 3;
		unsigned int         CRTC_DISABLE_POINT_CNTL : 2;
		unsigned int                                 : 2;
		unsigned int           CRTC_START_POINT_CNTL : 1;
		unsigned int          CRTC_FIELD_NUMBER_CNTL : 1;
		unsigned int                                 : 2;
		unsigned int    CRTC_CURRENT_MASTER_EN_STATE : 1;
		unsigned int                                 : 3;
		unsigned int       CRTC_HBLANK_EARLY_CONTROL : 3;
		unsigned int                                 : 1;
		unsigned int  CRTC_DISP_READ_REQUEST_DISABLE : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                CRTC_SOF_PULL_EN : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CONTROL__VI {
	struct {
		unsigned int                  CRTC_MASTER_EN : 1;
		unsigned int                                 : 3;
		unsigned int             CRTC_SYNC_RESET_SEL : 1;
		unsigned int                                 : 3;
		unsigned int         CRTC_DISABLE_POINT_CNTL : 2;
		unsigned int                                 : 2;
		unsigned int           CRTC_START_POINT_CNTL : 1;
		unsigned int          CRTC_FIELD_NUMBER_CNTL : 1;
		unsigned int      CRTC_FIELD_NUMBER_POLARITY : 1;
		unsigned int                                 : 1;
		unsigned int    CRTC_CURRENT_MASTER_EN_STATE : 1;
		unsigned int                                 : 3;
		unsigned int       CRTC_HBLANK_EARLY_CONTROL : 3;
		unsigned int                                 : 1;
		unsigned int  CRTC_DISP_READ_REQUEST_DISABLE : 1;
		unsigned int                                 : 4;
		unsigned int                CRTC_SOF_PULL_EN : 1;
		unsigned int       CRTC_AVSYNC_LOCK_SNAPSHOT : 1;
		unsigned int  CRTC_AVSYNC_VSYNC_N_HSYNC_MODE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_COUNT_CONTROL__SI__VI {
	struct {
                unsigned int          CRTC_HORZ_COUNT_BY2_EN : 1;
                unsigned int      CRTC_HORZ_REPETITION_COUNT : 4;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_COUNT_RESET__SI__VI {
	struct {
                unsigned int          CRTC_RESET_FRAME_COUNT : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_DOUBLE_BUFFER_CONTROL__SI__VI {
	struct {
                unsigned int             CRTC_UPDATE_PENDING : 1;
                unsigned int                                 : 7;
                unsigned int           CRTC_UPDATE_INSTANTLY : 1;
                unsigned int                                 : 7;
                unsigned int CRTC_BLANK_DATA_DOUBLE_BUFFER_EN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_DTMTEST_CNTL__SI__VI {
	struct {
                unsigned int            CRTC_DTMTEST_CRTC_EN : 1;
                unsigned int            CRTC_DTMTEST_CLK_DIV : 4;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_DTMTEST_STATUS_POSITION__SI__VI {
	struct {
                unsigned int         CRTC_DTMTEST_VERT_COUNT : 14;
                unsigned int                                 : 2;
                unsigned int         CRTC_DTMTEST_HORZ_COUNT : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_FLOW_CONTROL__SI__VI {
	struct {
                unsigned int CRTC_FLOW_CONTROL_SOURCE_SELECT : 5;
                unsigned int                                 : 3;
                unsigned int      CRTC_FLOW_CONTROL_POLARITY : 1;
                unsigned int                                 : 7;
                unsigned int   CRTC_FLOW_CONTROL_GRANULARITY : 1;
                unsigned int                                 : 7;
                unsigned int  CRTC_FLOW_CONTROL_INPUT_STATUS : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_FORCE_COUNT_NOW_CNTL__SI__VI {
	struct {
                unsigned int       CRTC_FORCE_COUNT_NOW_MODE : 2;
                unsigned int                                 : 2;
                unsigned int  CRTC_FORCE_COUNT_NOW_CHECK__VI : 1;
                unsigned int                                 : 3;
                unsigned int   CRTC_FORCE_COUNT_NOW_TRIG_SEL : 1;
                unsigned int                                 : 7;
                unsigned int   CRTC_FORCE_COUNT_NOW_OCCURRED : 1;
                unsigned int                                 : 7;
                unsigned int      CRTC_FORCE_COUNT_NOW_CLEAR : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_H_BLANK_START_END__SI__VI {
	struct {
                unsigned int              CRTC_H_BLANK_START : 14;
                unsigned int                                 : 2;
                unsigned int                CRTC_H_BLANK_END : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_H_SYNC_A_CNTL__SI__VI {
	struct {
                unsigned int               CRTC_H_SYNC_A_POL : 1;
                unsigned int                                 : 15;
                unsigned int             CRTC_COMP_SYNC_A_EN : 1;
                unsigned int            CRTC_H_SYNC_A_CUTOFF : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_H_SYNC_A__SI__VI {
	struct {
                unsigned int             CRTC_H_SYNC_A_START : 14;
                unsigned int                                 : 2;
                unsigned int               CRTC_H_SYNC_A_END : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_H_SYNC_B_CNTL__SI__VI {
	struct {
                unsigned int               CRTC_H_SYNC_B_POL : 1;
                unsigned int                                 : 15;
                unsigned int             CRTC_COMP_SYNC_B_EN : 1;
                unsigned int            CRTC_H_SYNC_B_CUTOFF : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_H_SYNC_B__SI__VI {
	struct {
                unsigned int             CRTC_H_SYNC_B_START : 14;
                unsigned int                                 : 2;
                unsigned int               CRTC_H_SYNC_B_END : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_H_TOTAL__SI__VI {
	struct {
                unsigned int                    CRTC_H_TOTAL : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_INTERLACE_CONTROL__SI__VI {
	struct {
                unsigned int           CRTC_INTERLACE_ENABLE : 1;
                unsigned int                                 : 15;
                unsigned int CRTC_INTERLACE_FORCE_NEXT_FIELD : 2;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_INTERLACE_STATUS__SI__VI {
	struct {
                unsigned int    CRTC_INTERLACE_CURRENT_FIELD : 1;
                unsigned int       CRTC_INTERLACE_NEXT_FIELD : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_INTERRUPT_CONTROL__SI__VI {
	struct {
                unsigned int           CRTC_SNAPSHOT_INT_MSK : 1;
                unsigned int          CRTC_SNAPSHOT_INT_TYPE : 1;
                unsigned int                                 : 2;
                unsigned int           CRTC_V_UPDATE_INT_MSK : 1;
                unsigned int          CRTC_V_UPDATE_INT_TYPE : 1;
                unsigned int                                 : 2;
                unsigned int    CRTC_FORCE_COUNT_NOW_INT_MSK : 1;
                unsigned int   CRTC_FORCE_COUNT_NOW_INT_TYPE : 1;
                unsigned int                                 : 6;
                unsigned int CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK : 1;
                unsigned int CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE : 1;
                unsigned int                                 : 6;
                unsigned int              CRTC_TRIGA_INT_MSK : 1;
                unsigned int              CRTC_TRIGB_INT_MSK : 1;
                unsigned int             CRTC_TRIGA_INT_TYPE : 1;
                unsigned int             CRTC_TRIGB_INT_TYPE : 1;
                unsigned int          CRTC_VSYNC_NOM_INT_MSK : 1;
                unsigned int         CRTC_VSYNC_NOM_INT_TYPE : 1;
                unsigned int  CRTC_GSL_VSYNC_GAP_INT_MSK__VI : 1;
                unsigned int CRTC_GSL_VSYNC_GAP_INT_TYPE__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI__VI {
	struct {
                unsigned int CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_MASTER_EN__SI__VI {
	struct {
                unsigned int                  CRTC_MASTER_EN : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI__VI {
	struct {
                unsigned int CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_MVP_INBAND_CNTL_INSERT__SI__VI {
	struct {
                unsigned int        CRTC_MVP_INBAND_OUT_MODE : 2;
                unsigned int                                 : 6;
                unsigned int CRTC_MVP_INBAND_CNTL_CHAR_INSERT : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_MVP_STATUS__SI__VI {
	struct {
                unsigned int          CRTC_FLIP_NOW_OCCURRED : 1;
                unsigned int                                 : 3;
                unsigned int CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED : 1;
                unsigned int                                 : 11;
                unsigned int             CRTC_FLIP_NOW_CLEAR : 1;
                unsigned int                                 : 3;
                unsigned int CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_NOM_VERT_POSITION__SI__VI {
	struct {
                unsigned int             CRTC_VERT_COUNT_NOM : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_OVERSCAN_COLOR__SI__VI {
	struct {
                unsigned int        CRTC_OVERSCAN_COLOR_BLUE : 10;
                unsigned int       CRTC_OVERSCAN_COLOR_GREEN : 10;
                unsigned int         CRTC_OVERSCAN_COLOR_RED : 10;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_PIXEL_DATA_READBACK__SI {
	struct {
		unsigned int                                 : 10;
		unsigned int                                 : 10;
		unsigned int                                 : 10;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_SNAPSHOT_CONTROL__SI__VI {
	struct {
                unsigned int     CRTC_AUTO_SNAPSHOT_TRIG_SEL : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_SNAPSHOT_FRAME__SI__VI {
	struct {
                unsigned int       CRTC_SNAPSHOT_FRAME_COUNT : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_SNAPSHOT_POSITION__SI__VI {
	struct {
                unsigned int        CRTC_SNAPSHOT_VERT_COUNT : 14;
                unsigned int                                 : 2;
                unsigned int        CRTC_SNAPSHOT_HORZ_COUNT : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_SNAPSHOT_STATUS__SI__VI {
	struct {
                unsigned int          CRTC_SNAPSHOT_OCCURRED : 1;
                unsigned int             CRTC_SNAPSHOT_CLEAR : 1;
                unsigned int    CRTC_SNAPSHOT_MANUAL_TRIGGER : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_START_LINE_CONTROL__SI__VI {
	struct {
                unsigned int CRTC_PROGRESSIVE_START_LINE_EARLY : 1;
                unsigned int                                 : 7;
                unsigned int CRTC_INTERLACE_START_LINE_EARLY : 1;
                unsigned int                                 : 3;
                unsigned int CRTC_ADVANCED_START_LINE_POSITION__VI : 8;
                unsigned int    CRTC_LEGACY_REQUESTOR_EN__VI : 1;
                unsigned int                                 : 7;
                unsigned int            CRTC_PREFETCH_EN__VI : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_STATUS {
	struct {
                unsigned int                    CRTC_V_BLANK : 1;
                unsigned int              CRTC_V_ACTIVE_DISP : 1;
                unsigned int                   CRTC_V_SYNC_A : 1;
                unsigned int                   CRTC_V_UPDATE : 1;
                unsigned int               CRTC_V_START_LINE : 1;
                unsigned int   CRTC_V_BLANK_3D_STRUCTURE__VI : 1;
                unsigned int                                 : 10;
                unsigned int                    CRTC_H_BLANK : 1;
                unsigned int              CRTC_H_ACTIVE_DISP : 1;
                unsigned int                   CRTC_H_SYNC_A : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_STATUS_FRAME_COUNT__SI__VI {
	struct {
                unsigned int                CRTC_FRAME_COUNT : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_STATUS_HV_COUNT__SI__VI {
	struct {
                unsigned int                   CRTC_HV_COUNT : 30;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_STATUS_POSITION {
	struct {
                unsigned int                 CRTC_VERT_COUNT : 14;
                unsigned int                                 : 2;
                unsigned int                 CRTC_HORZ_COUNT : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_STATUS_VF_COUNT__SI__VI {
	struct {
                unsigned int                   CRTC_VF_COUNT : 30;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_STEREO_CONTROL__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int CRTC_STEREO_SYNC_OUTPUT_POLARITY : 1;
		unsigned int                                 : 7;
		unsigned int CRTC_STEREO_SYNC_SELECT_POLARITY : 1;
		unsigned int                                 : 7;
		unsigned int                  CRTC_STEREO_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_STEREO_CONTROL__VI {
	struct {
		unsigned int CRTC_STEREO_SYNC_OUTPUT_LINE_NUM : 14;
		unsigned int                                 : 1;
		unsigned int CRTC_STEREO_SYNC_OUTPUT_POLARITY : 1;
		unsigned int CRTC_STEREO_SYNC_SELECT_POLARITY : 1;
		unsigned int   CRTC_STEREO_EYE_FLAG_POLARITY : 1;
		unsigned int CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP : 1;
		unsigned int          CRTC_DISABLE_FIELD_NUM : 1;
		unsigned int CRTC_DISABLE_V_BLANK_FOR_DP_FIX : 1;
		unsigned int                                 : 3;
		unsigned int                  CRTC_STEREO_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_STEREO_FORCE_NEXT_EYE__SI__VI {
	struct {
                unsigned int      CRTC_STEREO_FORCE_NEXT_EYE : 2;
                unsigned int                                 : 6;
                unsigned int   CRTC_AVSYNC_FRAME_COUNTER__VI : 8;
                unsigned int    CRTC_AVSYNC_LINE_COUNTER__VI : 13;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_STEREO_STATUS__SI__VI {
	struct {
                unsigned int         CRTC_STEREO_CURRENT_EYE : 1;
                unsigned int                                 : 7;
                unsigned int         CRTC_STEREO_SYNC_OUTPUT : 1;
                unsigned int                                 : 7;
                unsigned int         CRTC_STEREO_SYNC_SELECT : 1;
                unsigned int                                 : 3;
                unsigned int        CRTC_STEREO_EYE_FLAG__VI : 1;
                unsigned int                                 : 3;
                unsigned int CRTC_STEREO_FORCE_NEXT_EYE_PENDING : 2;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int            CRTC_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int           CRTC_TEST_DEBUG_INDEX : 8;
                unsigned int        CRTC_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TEST_PATTERN_COLOR__SI__VI {
	struct {
                unsigned int          CRTC_TEST_PATTERN_DATA : 16;
                unsigned int          CRTC_TEST_PATTERN_MASK : 6;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TEST_PATTERN_CONTROL__SI__VI {
	struct {
                unsigned int            CRTC_TEST_PATTERN_EN : 1;
                unsigned int                                 : 7;
                unsigned int          CRTC_TEST_PATTERN_MODE : 3;
                unsigned int                                 : 5;
                unsigned int CRTC_TEST_PATTERN_DYNAMIC_RANGE : 1;
                unsigned int                                 : 7;
                unsigned int  CRTC_TEST_PATTERN_COLOR_FORMAT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TEST_PATTERN_PARAMETERS__SI__VI {
	struct {
                unsigned int          CRTC_TEST_PATTERN_INC0 : 4;
                unsigned int          CRTC_TEST_PATTERN_INC1 : 4;
                unsigned int          CRTC_TEST_PATTERN_VRES : 4;
                unsigned int          CRTC_TEST_PATTERN_HRES : 4;
                unsigned int  CRTC_TEST_PATTERN_RAMP0_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TRIGA_CNTL__SI {
	struct {
		unsigned int        CRTC_TRIGA_SOURCE_SELECT : 4;
		unsigned int      CRTC_TRIGA_POLARITY_SELECT : 3;
		unsigned int                                 : 1;
		unsigned int     CRTC_TRIGA_RESYNC_BYPASS_EN : 1;
		unsigned int         CRTC_TRIGA_INPUT_STATUS : 1;
		unsigned int      CRTC_TRIGA_POLARITY_STATUS : 1;
		unsigned int             CRTC_TRIGA_OCCURRED : 1;
		unsigned int CRTC_TRIGA_RISING_EDGE_DETECT_CNTL : 2;
		unsigned int                                 : 2;
		unsigned int CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL : 2;
		unsigned int                                 : 2;
		unsigned int     CRTC_TRIGA_FREQUENCY_SELECT : 2;
		unsigned int                                 : 2;
		unsigned int                CRTC_TRIGA_DELAY : 5;
		unsigned int                                 : 2;
		unsigned int                CRTC_TRIGA_CLEAR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TRIGA_CNTL__VI {
	struct {
		unsigned int        CRTC_TRIGA_SOURCE_SELECT : 5;
		unsigned int      CRTC_TRIGA_POLARITY_SELECT : 3;
		unsigned int     CRTC_TRIGA_RESYNC_BYPASS_EN : 1;
		unsigned int         CRTC_TRIGA_INPUT_STATUS : 1;
		unsigned int      CRTC_TRIGA_POLARITY_STATUS : 1;
		unsigned int             CRTC_TRIGA_OCCURRED : 1;
		unsigned int CRTC_TRIGA_RISING_EDGE_DETECT_CNTL : 2;
		unsigned int                                 : 2;
		unsigned int CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL : 2;
		unsigned int                                 : 2;
		unsigned int     CRTC_TRIGA_FREQUENCY_SELECT : 2;
		unsigned int                                 : 2;
		unsigned int                CRTC_TRIGA_DELAY : 5;
		unsigned int                                 : 2;
		unsigned int                CRTC_TRIGA_CLEAR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TRIGA_MANUAL_TRIG__SI__VI {
	struct {
                unsigned int          CRTC_TRIGA_MANUAL_TRIG : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TRIGB_CNTL__SI {
	struct {
		unsigned int        CRTC_TRIGB_SOURCE_SELECT : 4;
		unsigned int      CRTC_TRIGB_POLARITY_SELECT : 3;
		unsigned int                                 : 1;
		unsigned int     CRTC_TRIGB_RESYNC_BYPASS_EN : 1;
		unsigned int         CRTC_TRIGB_INPUT_STATUS : 1;
		unsigned int      CRTC_TRIGB_POLARITY_STATUS : 1;
		unsigned int             CRTC_TRIGB_OCCURRED : 1;
		unsigned int CRTC_TRIGB_RISING_EDGE_DETECT_CNTL : 2;
		unsigned int                                 : 2;
		unsigned int CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL : 2;
		unsigned int                                 : 2;
		unsigned int     CRTC_TRIGB_FREQUENCY_SELECT : 2;
		unsigned int                                 : 2;
		unsigned int                CRTC_TRIGB_DELAY : 5;
		unsigned int                                 : 2;
		unsigned int                CRTC_TRIGB_CLEAR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TRIGB_CNTL__VI {
	struct {
		unsigned int        CRTC_TRIGB_SOURCE_SELECT : 5;
		unsigned int      CRTC_TRIGB_POLARITY_SELECT : 3;
		unsigned int     CRTC_TRIGB_RESYNC_BYPASS_EN : 1;
		unsigned int         CRTC_TRIGB_INPUT_STATUS : 1;
		unsigned int      CRTC_TRIGB_POLARITY_STATUS : 1;
		unsigned int             CRTC_TRIGB_OCCURRED : 1;
		unsigned int CRTC_TRIGB_RISING_EDGE_DETECT_CNTL : 2;
		unsigned int                                 : 2;
		unsigned int CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL : 2;
		unsigned int                                 : 2;
		unsigned int     CRTC_TRIGB_FREQUENCY_SELECT : 2;
		unsigned int                                 : 2;
		unsigned int                CRTC_TRIGB_DELAY : 5;
		unsigned int                                 : 2;
		unsigned int                CRTC_TRIGB_CLEAR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_TRIGB_MANUAL_TRIG__SI__VI {
	struct {
                unsigned int          CRTC_TRIGB_MANUAL_TRIG : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_UPDATE_LOCK__SI__VI {
	struct {
                unsigned int                CRTC_UPDATE_LOCK : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_VBI_END__SI__VI {
	struct {
                unsigned int                  CRTC_VBI_V_END : 14;
                unsigned int                                 : 2;
                unsigned int                  CRTC_VBI_H_END : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_VERT_SYNC_CONTROL__SI__VI {
	struct {
                unsigned int CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED : 1;
                unsigned int                                 : 7;
                unsigned int CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR : 1;
                unsigned int                                 : 7;
                unsigned int      CRTC_AUTO_FORCE_VSYNC_MODE : 2;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_VGA_PARAMETER_CAPTURE_MODE__SI__VI {
	struct {
                unsigned int CRTC_VGA_PARAMETER_CAPTURE_MODE : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_VSYNC_NOM_INT_STATUS__SI__VI {
	struct {
                unsigned int                  CRTC_VSYNC_NOM : 1;
                unsigned int                                 : 3;
                unsigned int        CRTC_VSYNC_NOM_INT_CLEAR : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_BLANK_START_END__SI__VI {
	struct {
                unsigned int              CRTC_V_BLANK_START : 14;
                unsigned int                                 : 2;
                unsigned int                CRTC_V_BLANK_END : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_SYNC_A_CNTL__SI__VI {
	struct {
                unsigned int               CRTC_V_SYNC_A_POL : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_SYNC_A__SI__VI {
	struct {
                unsigned int             CRTC_V_SYNC_A_START : 14;
                unsigned int                                 : 2;
                unsigned int               CRTC_V_SYNC_A_END : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_SYNC_B_CNTL__SI__VI {
	struct {
                unsigned int               CRTC_V_SYNC_B_POL : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_SYNC_B__SI__VI {
	struct {
                unsigned int             CRTC_V_SYNC_B_START : 14;
                unsigned int                                 : 2;
                unsigned int               CRTC_V_SYNC_B_END : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_TOTAL_CONTROL__SI__VI {
	struct {
                unsigned int            CRTC_V_TOTAL_MIN_SEL : 1;
                unsigned int                                 : 3;
                unsigned int            CRTC_V_TOTAL_MAX_SEL : 1;
                unsigned int                                 : 3;
                unsigned int        CRTC_FORCE_LOCK_ON_EVENT : 1;
                unsigned int                                 : 3;
                unsigned int CRTC_FORCE_LOCK_TO_MASTER_VSYNC : 1;
                unsigned int                                 : 2;
                unsigned int CRTC_SET_V_TOTAL_MIN_MASK_EN__VI : 1;
                unsigned int       CRTC_SET_V_TOTAL_MIN_MASK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_TOTAL_INT_STATUS__SI__VI {
	struct {
                unsigned int CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED : 1;
                unsigned int                                 : 3;
                unsigned int CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1;
                unsigned int                                 : 3;
                unsigned int CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK : 1;
                unsigned int                                 : 3;
                unsigned int CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_TOTAL_MAX__SI__VI {
	struct {
                unsigned int                CRTC_V_TOTAL_MAX : 14;
                unsigned int                                 : 2;
                unsigned int CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_TOTAL_MIN__SI__VI {
	struct {
                unsigned int                CRTC_V_TOTAL_MIN : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_TOTAL__SI__VI {
	struct {
                unsigned int                    CRTC_V_TOTAL : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_V_UPDATE_INT_STATUS__SI__VI {
	struct {
                unsigned int      CRTC_V_UPDATE_INT_OCCURRED : 1;
                unsigned int                                 : 7;
                unsigned int         CRTC_V_UPDATE_INT_CLEAR : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CSPRIV_CONNECT__CI__VI {
	struct {
                unsigned int                 DOORBELL_OFFSET : 21;
                unsigned int                        QUEUE_ID : 3;
                unsigned int                                 : 2;
                unsigned int                            VMID : 4;
                unsigned int                                 : 1;
                unsigned int                      UNORD_DISP : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CSPRIV_THREAD_TRACE_EVENT__CI__VI {
	struct {
                unsigned int                        EVENT_ID : 5;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CSPRIV_THREAD_TRACE_TG0__CI__VI {
	struct {
                unsigned int                          TGID_X : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CSPRIV_THREAD_TRACE_TG1__CI__VI {
	struct {
                unsigned int                          TGID_Y : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CSPRIV_THREAD_TRACE_TG2__CI__VI {
	struct {
                unsigned int                          TGID_Z : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CSPRIV_THREAD_TRACE_TG3__CI__VI {
	struct {
                unsigned int                    WAVE_ID_BASE : 12;
                unsigned int                THREADS_IN_GROUP : 12;
                unsigned int                  PARTIAL_X_FLAG : 1;
                unsigned int                  PARTIAL_Y_FLAG : 1;
                unsigned int                  PARTIAL_Z_FLAG : 1;
                unsigned int                         LAST_TG : 1;
                unsigned int                        FIRST_TG : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CS_COPY_STATE {
	struct {
		unsigned int                    SRC_STATE_ID : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_COLOR1__SI__VI {
	struct {
                unsigned int                 CUR_COLOR1_BLUE : 8;
                unsigned int                CUR_COLOR1_GREEN : 8;
                unsigned int                  CUR_COLOR1_RED : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_COLOR2__SI__VI {
	struct {
                unsigned int                 CUR_COLOR2_BLUE : 8;
                unsigned int                CUR_COLOR2_GREEN : 8;
                unsigned int                  CUR_COLOR2_RED : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_CONTROL__SI__VI {
	struct {
                unsigned int                       CURSOR_EN : 1;
                unsigned int                                 : 3;
                unsigned int         CUR_INV_TRANS_CLAMP__VI : 1;
                unsigned int                                 : 3;
                unsigned int                     CURSOR_MODE : 2;
                unsigned int                                 : 6;
                unsigned int               CURSOR_2X_MAGNIFY : 1;
                unsigned int                                 : 3;
                unsigned int              CURSOR_FORCE_MC_ON : 1;
                unsigned int                                 : 3;
                unsigned int       CURSOR_URGENT_CONTROL__VI : 3;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_HOT_SPOT__SI__VI {
	struct {
                unsigned int               CURSOR_HOT_SPOT_Y : 7;
                unsigned int                                 : 9;
                unsigned int               CURSOR_HOT_SPOT_X : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_POSITION__SI__VI {
	struct {
                unsigned int               CURSOR_Y_POSITION : 14;
                unsigned int                                 : 2;
                unsigned int               CURSOR_X_POSITION : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_SIZE__SI__VI {
	struct {
                unsigned int                   CURSOR_HEIGHT : 7;
                unsigned int                                 : 9;
                unsigned int                    CURSOR_WIDTH : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_SURFACE_ADDRESS_HIGH__SI__VI {
	struct {
                unsigned int     CURSOR_SURFACE_ADDRESS_HIGH : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_SURFACE_ADDRESS__SI__VI {
	struct {
                unsigned int          CURSOR_SURFACE_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_UPDATE__SI__VI {
	struct {
                unsigned int           CURSOR_UPDATE_PENDING : 1;
                unsigned int             CURSOR_UPDATE_TAKEN : 1;
                unsigned int                                 : 14;
                unsigned int              CURSOR_UPDATE_LOCK : 1;
                unsigned int                                 : 7;
                unsigned int  CURSOR_DISABLE_MULTIPLE_UPDATE : 1;
                unsigned int   CURSOR_UPDATE_STEREO_MODE__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union D1VGA_CONTROL__SI__VI {
	struct {
                unsigned int               D1VGA_MODE_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int             D1VGA_TIMING_SELECT : 1;
                unsigned int      D1VGA_SYNC_POLARITY_SELECT : 1;
                unsigned int                                 : 6;
                unsigned int         D1VGA_OVERSCAN_COLOR_EN : 1;
                unsigned int                                 : 7;
                unsigned int                    D1VGA_ROTATE : 2;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union D2VGA_CONTROL__SI__VI {
	struct {
                unsigned int               D2VGA_MODE_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int             D2VGA_TIMING_SELECT : 1;
                unsigned int      D2VGA_SYNC_POLARITY_SELECT : 1;
                unsigned int                                 : 6;
                unsigned int         D2VGA_OVERSCAN_COLOR_EN : 1;
                unsigned int                                 : 7;
                unsigned int                    D2VGA_ROTATE : 2;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union D3VGA_CONTROL__SI__VI {
	struct {
                unsigned int               D3VGA_MODE_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int             D3VGA_TIMING_SELECT : 1;
                unsigned int      D3VGA_SYNC_POLARITY_SELECT : 1;
                unsigned int                                 : 6;
                unsigned int         D3VGA_OVERSCAN_COLOR_EN : 1;
                unsigned int                                 : 7;
                unsigned int                    D3VGA_ROTATE : 2;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union D4VGA_CONTROL__SI__VI {
	struct {
                unsigned int               D4VGA_MODE_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int             D4VGA_TIMING_SELECT : 1;
                unsigned int      D4VGA_SYNC_POLARITY_SELECT : 1;
                unsigned int                                 : 6;
                unsigned int         D4VGA_OVERSCAN_COLOR_EN : 1;
                unsigned int                                 : 7;
                unsigned int                    D4VGA_ROTATE : 2;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union D5VGA_CONTROL__SI__VI {
	struct {
                unsigned int               D5VGA_MODE_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int             D5VGA_TIMING_SELECT : 1;
                unsigned int      D5VGA_SYNC_POLARITY_SELECT : 1;
                unsigned int                                 : 6;
                unsigned int         D5VGA_OVERSCAN_COLOR_EN : 1;
                unsigned int                                 : 7;
                unsigned int                    D5VGA_ROTATE : 2;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union D6VGA_CONTROL__SI__VI {
	struct {
                unsigned int               D6VGA_MODE_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int             D6VGA_TIMING_SELECT : 1;
                unsigned int      D6VGA_SYNC_POLARITY_SELECT : 1;
                unsigned int                                 : 6;
                unsigned int         D6VGA_OVERSCAN_COLOR_EN : 1;
                unsigned int                                 : 7;
                unsigned int                    D6VGA_ROTATE : 2;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_AUTODETECT_CONTROL2__SI__VI {
	struct {
                unsigned int  DAC_AUTODETECT_POWERUP_COUNTER : 8;
                unsigned int         DAC_AUTODETECT_TESTMODE : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_AUTODETECT_CONTROL3__SI__VI {
	struct {
                unsigned int DAC_AUTODET_COMPARATOR_IN_DELAY : 8;
                unsigned int DAC_AUTODET_COMPARATOR_OUT_DELAY : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_AUTODETECT_CONTROL__SI__VI {
	struct {
                unsigned int             DAC_AUTODETECT_MODE : 2;
                unsigned int                                 : 6;
                unsigned int DAC_AUTODETECT_FRAME_TIME_COUNTER : 8;
                unsigned int       DAC_AUTODETECT_CHECK_MASK : 3;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_AUTODETECT_INT_CONTROL__SI__VI {
	struct {
                unsigned int              DAC_AUTODETECT_ACK : 1;
                unsigned int                                 : 15;
                unsigned int       DAC_AUTODETECT_INT_ENABLE : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_AUTODETECT_STATUS__SI__VI {
	struct {
                unsigned int           DAC_AUTODETECT_STATUS : 1;
                unsigned int                                 : 3;
                unsigned int          DAC_AUTODETECT_CONNECT : 1;
                unsigned int                                 : 3;
                unsigned int        DAC_AUTODETECT_RED_SENSE : 2;
                unsigned int                                 : 6;
                unsigned int      DAC_AUTODETECT_GREEN_SENSE : 2;
                unsigned int                                 : 6;
                unsigned int       DAC_AUTODETECT_BLUE_SENSE : 2;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_AUTO_CALIB_CONTROL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 10;
		unsigned int                                 : 6;
		unsigned int                                 : 3;
		unsigned int                                 : 5;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_COMPARATOR_ENABLE__SI__VI {
	struct {
                unsigned int            DAC_COMP_DDET_REF_EN : 1;
                unsigned int                                 : 7;
                unsigned int            DAC_COMP_SDET_REF_EN : 1;
                unsigned int                                 : 7;
                unsigned int              DAC_R_ASYNC_ENABLE : 1;
                unsigned int              DAC_G_ASYNC_ENABLE : 1;
                unsigned int              DAC_B_ASYNC_ENABLE : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_COMPARATOR_OUTPUT__SI__VI {
	struct {
                unsigned int           DAC_COMPARATOR_OUTPUT : 1;
                unsigned int      DAC_COMPARATOR_OUTPUT_BLUE : 1;
                unsigned int     DAC_COMPARATOR_OUTPUT_GREEN : 1;
                unsigned int       DAC_COMPARATOR_OUTPUT_RED : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_CONTROL__SI__VI {
	struct {
                unsigned int                   DAC_DFORCE_EN : 1;
                unsigned int                                 : 7;
                unsigned int                   DAC_TV_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int                DAC_ZSCALE_SHIFT : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_CRC_CONTROL__SI {
	struct {
		unsigned int                   DAC_CRC_FIELD : 1;
		unsigned int                                 : 7;
		unsigned int             DAC_CRC_ONLY_BLANKb : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_CRC_CONTROL__VI {
	struct {
		unsigned int                   DAC_CRC_FIELD : 1;
		unsigned int                                 : 7;
		unsigned int             DAC_CRC_ONLY_BLANKB : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_CRC_EN__SI__VI {
	struct {
                unsigned int                      DAC_CRC_EN : 1;
                unsigned int                                 : 15;
                unsigned int                 DAC_CRC_CONT_EN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_CRC_SIG_CONTROL_MASK__SI__VI {
	struct {
                unsigned int        DAC_CRC_SIG_CONTROL_MASK : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_CRC_SIG_CONTROL__SI__VI {
	struct {
                unsigned int             DAC_CRC_SIG_CONTROL : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_CRC_SIG_RGB_MASK__SI__VI {
	struct {
                unsigned int           DAC_CRC_SIG_BLUE_MASK : 10;
                unsigned int          DAC_CRC_SIG_GREEN_MASK : 10;
                unsigned int            DAC_CRC_SIG_RED_MASK : 10;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_CRC_SIG_RGB__SI__VI {
	struct {
                unsigned int                DAC_CRC_SIG_BLUE : 10;
                unsigned int               DAC_CRC_SIG_GREEN : 10;
                unsigned int                 DAC_CRC_SIG_RED : 10;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_DATA__SI__VI {
	struct {
                unsigned int                        DAC_DATA : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_DFT_CONFIG__SI__VI {
	struct {
                unsigned int                  DAC_DFT_CONFIG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_ENABLE__SI__VI {
	struct {
                unsigned int                      DAC_ENABLE : 1;
                unsigned int      DAC_RESYNC_FIFO_ENABLE__VI : 1;
                unsigned int DAC_RESYNC_FIFO_POINTER_SKEW__VI : 2;
                unsigned int       DAC_RESYNC_FIFO_ERROR__VI : 1;
                unsigned int   DAC_RESYNC_FIFO_ERROR_ACK__VI : 1;
                unsigned int                                 : 2;
                unsigned int   DAC_RESYNC_FIFO_TVOUT_SIM__VI : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_FORCE_DATA__SI__VI {
	struct {
                unsigned int                  DAC_FORCE_DATA : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_FORCE_OUTPUT_CNTL__SI {
	struct {
		unsigned int               DAC_FORCE_DATA_EN : 1;
		unsigned int                                 : 7;
		unsigned int              DAC_FORCE_DATA_SEL : 3;
		unsigned int                                 : 13;
		unsigned int   DAC_FORCE_DATA_ON_BLANKb_ONLY : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_FORCE_OUTPUT_CNTL__VI {
	struct {
		unsigned int               DAC_FORCE_DATA_EN : 1;
		unsigned int                                 : 7;
		unsigned int              DAC_FORCE_DATA_SEL : 3;
		unsigned int                                 : 13;
		unsigned int   DAC_FORCE_DATA_ON_BLANKB_ONLY : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_MACRO_CNTL__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int                                 : 6;
		unsigned int                                 : 6;
		unsigned int                                 : 2;
		unsigned int                                 : 6;
		unsigned int                                 : 2;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_MASK__SI__VI {
	struct {
                unsigned int                        DAC_MASK : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_POWERDOWN__SI__VI {
	struct {
                unsigned int                   DAC_POWERDOWN : 1;
                unsigned int                                 : 7;
                unsigned int              DAC_POWERDOWN_BLUE : 1;
                unsigned int                                 : 7;
                unsigned int             DAC_POWERDOWN_GREEN : 1;
                unsigned int                                 : 7;
                unsigned int               DAC_POWERDOWN_RED : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_PWR_CNTL__SI__VI {
	struct {
                unsigned int                     DAC_BG_MODE : 2;
                unsigned int                                 : 14;
                unsigned int                     DAC_PWRCNTL : 2;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_R_INDEX__SI__VI {
	struct {
                unsigned int                     DAC_R_INDEX : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_SOURCE_SELECT__SI__VI {
	struct {
                unsigned int               DAC_SOURCE_SELECT : 3;
                unsigned int                   DAC_TV_SELECT : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_STEREOSYNC_SELECT__SI__VI {
	struct {
                unsigned int           DAC_STEREOSYNC_SELECT : 3;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_SYNC_TRISTATE_CONTROL__SI__VI {
	struct {
                unsigned int             DAC_HSYNCA_TRISTATE : 1;
                unsigned int                                 : 7;
                unsigned int             DAC_VSYNCA_TRISTATE : 1;
                unsigned int                                 : 7;
                unsigned int              DAC_SYNCA_TRISTATE : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_W_INDEX__SI__VI {
	struct {
                unsigned int                     DAC_W_INDEX : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DATA_FORMAT__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 5;
		unsigned int                                 : 3;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DBG_BYPASS_SRBM_ACCESS__CI {
	struct {
		unsigned int       DBG_BYPASS_SRBM_ACCESS_EN : 1;
		unsigned int                     DBG_APER_AD : 4;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_ALPHA_TO_MASK {
	struct {
		unsigned int            ALPHA_TO_MASK_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
		unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
		unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
		unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
		unsigned int                    OFFSET_ROUND : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_CGTT_CLK_CTRL_0 {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                        RESERVED : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_COUNT_CONTROL {
	struct {
                unsigned int         ZPASS_INCREMENT_DISABLE : 1;
                unsigned int            PERFECT_ZPASS_COUNTS : 1;
                unsigned int                                 : 2;
                unsigned int                     SAMPLE_RATE : 3;
                unsigned int                                 : 1;
                unsigned int            ZPASS_ENABLE__CI__VI : 4;
                unsigned int            ZFAIL_ENABLE__CI__VI : 4;
                unsigned int            SFAIL_ENABLE__CI__VI : 4;
                unsigned int           DBFAIL_ENABLE__CI__VI : 4;
                unsigned int       SLICE_EVEN_ENABLE__CI__VI : 4;
                unsigned int        SLICE_ODD_ENABLE__CI__VI : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_CREDIT_LIMIT {
	struct {
		unsigned int              DB_SC_TILE_CREDITS : 5;
		unsigned int              DB_SC_QUAD_CREDITS : 5;
		unsigned int             DB_CB_LQUAD_CREDITS : 3;
		unsigned int                                 : 11;
		unsigned int              DB_CB_TILE_CREDITS : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEBUG {
	struct {
		unsigned int  DEBUG_STENCIL_COMPRESS_DISABLE : 1;
		unsigned int    DEBUG_DEPTH_COMPRESS_DISABLE : 1;
		unsigned int               FETCH_FULL_Z_TILE : 1;
		unsigned int         FETCH_FULL_STENCIL_TILE : 1;
		unsigned int                    FORCE_Z_MODE : 2;
		unsigned int          DEBUG_FORCE_DEPTH_READ : 1;
		unsigned int        DEBUG_FORCE_STENCIL_READ : 1;
		unsigned int          DEBUG_FORCE_HIZ_ENABLE : 2;
		unsigned int         DEBUG_FORCE_HIS_ENABLE0 : 2;
		unsigned int         DEBUG_FORCE_HIS_ENABLE1 : 2;
		unsigned int            DEBUG_FAST_Z_DISABLE : 1;
		unsigned int      DEBUG_FAST_STENCIL_DISABLE : 1;
		unsigned int         DEBUG_NOOP_CULL_DISABLE : 1;
		unsigned int             DISABLE_SUMM_SQUADS : 1;
		unsigned int          DEPTH_CACHE_FORCE_MISS : 1;
		unsigned int        DEBUG_FORCE_FULL_Z_RANGE : 2;
		unsigned int               NEVER_FREE_Z_ONLY : 1;
		unsigned int ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS : 1;
		unsigned int DISABLE_VPORT_ZPLANE_OPTIMIZATION : 1;
		unsigned int      DECOMPRESS_AFTER_N_ZPLANES : 4;
		unsigned int              ONE_FREE_IN_FLIGHT : 1;
		unsigned int      FORCE_MISS_IF_NOT_INFLIGHT : 1;
		unsigned int      DISABLE_DEPTH_SURFACE_SYNC : 1;
		unsigned int      DISABLE_HTILE_SURFACE_SYNC : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEBUG2__CI__VI {
	struct {
                unsigned int        ALLOW_COMPZ_BYTE_MASKING : 1;
                unsigned int      DISABLE_TC_ZRANGE_L0_CACHE : 1;
                unsigned int        DISABLE_TC_MASK_L0_CACHE : 1;
                unsigned int             DTR_ROUND_ROBIN_ARB : 1;
                unsigned int    DTR_PREZ_STALLS_FOR_ETF_ROOM : 1;
                unsigned int         DISABLE_PREZL_LPF_STALL : 1;
                unsigned int           ENABLE_PREZL_CB_STALL : 1;
                unsigned int     DISABLE_PREZL_LPF_STALL_REZ : 1;
                unsigned int      DISABLE_PREZL_CB_STALL_REZ : 1;
                unsigned int                   CLK_OFF_DELAY : 5;
                unsigned int DISABLE_TILE_COVERED_FOR_PS_ITER : 1;
                unsigned int         ENABLE_SUBTILE_GROUPING : 1;
                unsigned int      DISABLE_HTILE_PAIRED_PIPES : 1;
                unsigned int     DISABLE_NULL_EOT_FORWARDING : 1;
                unsigned int     DISABLE_DTT_DATA_FORWARDING : 1;
                unsigned int    DISABLE_QUAD_COHERENCY_STALL : 1;
                unsigned int                                 : 8;
                unsigned int         ENABLE_PREZ_OF_REZ_SUMM : 1;
                unsigned int    DISABLE_PREZL_VIEWPORT_STALL : 1;
                unsigned int DISABLE_SINGLE_STENCIL_QUAD_SUMM : 1;
                unsigned int DISABLE_WRITE_STALL_ON_RDWR_CONFLICT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEBUG2__SI {
	struct {
		unsigned int        ALLOW_COMPZ_BYTE_MASKING : 1;
		unsigned int      DISABLE_TC_ZRANGE_L0_CACHE : 1;
		unsigned int        DISABLE_TC_MASK_L0_CACHE : 1;
		unsigned int             DTR_ROUND_ROBIN_ARB : 1;
		unsigned int    DTR_PREZ_STALLS_FOR_ETF_ROOM : 1;
		unsigned int         DISABLE_PREZL_LPF_STALL : 1;
		unsigned int           ENABLE_PREZL_CB_STALL : 1;
		unsigned int     DISABLE_PREZL_LPF_STALL_REZ : 1;
		unsigned int      DISABLE_PREZL_CB_STALL_REZ : 1;
		unsigned int                   CLK_OFF_DELAY : 5;
		unsigned int DISABLE_TILE_COVERED_FOR_PS_ITER : 1;
		unsigned int         ENABLE_SUBTILE_GROUPING : 1;
		unsigned int      DISABLE_HTILE_PAIRED_PIPES : 1;
		unsigned int     DISABLE_NULL_EOT_FORWARDING : 1;
		unsigned int     DISABLE_DTT_DATA_FORWARDING : 1;
		unsigned int    DISABLE_QUAD_COHERENCY_STALL : 1;
		unsigned int                                 : 8;
		unsigned int         ENABLE_PREZ_OF_REZ_SUMM : 1;
		unsigned int    DISABLE_PREZL_VIEWPORT_STALL : 1;
		unsigned int                                 : 1;
		unsigned int DISABLE_SINGLE_STENCIL_QUAD_SUMM : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEBUG3__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                FORCE_DB_IS_GOOD : 1;
		unsigned int DISABLE_TL_SSO_NULL_SUPPRESSION : 1;
		unsigned int      DISABLE_HIZ_ON_VPORT_CLAMP : 1;
		unsigned int         EQAA_INTERPOLATE_COMP_Z : 1;
		unsigned int          EQAA_INTERPOLATE_SRC_Z : 1;
		unsigned int          DISABLE_TCP_CAM_BYPASS : 1;
		unsigned int  DISABLE_ZCMP_DIRTY_SUPPRESSION : 1;
		unsigned int DISABLE_REDUNDANT_PLANE_FLUSHES_OPT : 1;
		unsigned int DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP : 1;
		unsigned int    ENABLE_INCOHERENT_EQAA_READS : 1;
		unsigned int    DISABLE_OP_Z_DATA_FORWARDING : 1;
		unsigned int            DISABLE_OP_DF_BYPASS : 1;
		unsigned int     DISABLE_OP_DF_WRITE_COMBINE : 1;
		unsigned int   DISABLE_OP_DF_DIRECT_FEEDBACK : 1;
		unsigned int         ALLOW_RF2P_RW_COLLISION : 1;
		unsigned int     SLOW_PREZ_TO_A2M_OMASK_RATE : 1;
		unsigned int    DISABLE_OP_S_DATA_FORWARDING : 1;
		unsigned int DISABLE_TC_UPDATE_WRITE_COMBINE : 1;
		unsigned int     DISABLE_HZ_TC_WRITE_COMBINE : 1;
		unsigned int ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT : 1;
		unsigned int    ENABLE_TC_MA_ROUND_ROBIN_ARB : 1;
		unsigned int DISABLE_RAM_READ_SUPPRESION_ON_FWD : 1;
		unsigned int       DISABLE_EQAA_A2M_PERF_OPT : 1;
		unsigned int             DISABLE_DI_DT_STALL : 1;
		unsigned int         ENABLE_DB_PROCESS_RESET : 1;
		unsigned int   DISABLE_OVERRASTERIZATION_FIX : 1;
		unsigned int     DONT_INSERT_CONTEXT_SUSPEND : 1;
		unsigned int     DONT_DELETE_CONTEXT_SUSPEND : 1;
		unsigned int                 DB_EXTRA_DEBUG3 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEBUG3__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                FORCE_DB_IS_GOOD : 1;
		unsigned int DISABLE_TL_SSO_NULL_SUPPRESSION : 1;
		unsigned int      DISABLE_HIZ_ON_VPORT_CLAMP : 1;
		unsigned int         EQAA_INTERPOLATE_COMP_Z : 1;
		unsigned int          EQAA_INTERPOLATE_SRC_Z : 1;
		unsigned int          DISABLE_TCP_CAM_BYPASS : 1;
		unsigned int  DISABLE_ZCMP_DIRTY_SUPPRESSION : 1;
		unsigned int DISABLE_REDUNDANT_PLANE_FLUSHES_OPT : 1;
		unsigned int DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP : 1;
		unsigned int    ENABLE_INCOHERENT_EQAA_READS : 1;
		unsigned int    DISABLE_OP_Z_DATA_FORWARDING : 1;
		unsigned int            DISABLE_OP_DF_BYPASS : 1;
		unsigned int     DISABLE_OP_DF_WRITE_COMBINE : 1;
		unsigned int   DISABLE_OP_DF_DIRECT_FEEDBACK : 1;
		unsigned int         ALLOW_RF2P_RW_COLLISION : 1;
		unsigned int     SLOW_PREZ_TO_A2M_OMASK_RATE : 1;
		unsigned int    DISABLE_OP_S_DATA_FORWARDING : 1;
		unsigned int DISABLE_TC_UPDATE_WRITE_COMBINE : 1;
		unsigned int     DISABLE_HZ_TC_WRITE_COMBINE : 1;
		unsigned int ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT : 1;
		unsigned int    ENABLE_TC_MA_ROUND_ROBIN_ARB : 1;
		unsigned int DISABLE_RAM_READ_SUPPRESION_ON_FWD : 1;
		unsigned int       DISABLE_EQAA_A2M_PERF_OPT : 1;
		unsigned int             DISABLE_DI_DT_STALL : 1;
		unsigned int         ENABLE_DB_PROCESS_RESET : 1;
		unsigned int   DISABLE_OVERRASTERIZATION_FIX : 1;
		unsigned int     DONT_INSERT_CONTEXT_SUSPEND : 1;
		unsigned int     DONT_DELETE_CONTEXT_SUSPEND : 1;
		unsigned int   DISABLE_4XAA_2P_DELAYED_WRITE : 1;
		unsigned int DISABLE_4XAA_2P_INTERLEAVED_PMASK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEBUG3__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int                FORCE_DB_IS_GOOD : 1;
		unsigned int DISABLE_TL_SSO_NULL_SUPPRESSION : 1;
		unsigned int      DISABLE_HIZ_ON_VPORT_CLAMP : 1;
		unsigned int         EQAA_INTERPOLATE_COMP_Z : 1;
		unsigned int          EQAA_INTERPOLATE_SRC_Z : 1;
		unsigned int          DISABLE_TCP_CAM_BYPASS : 1;
		unsigned int  DISABLE_ZCMP_DIRTY_SUPPRESSION : 1;
		unsigned int                                 : 1;
		unsigned int DISABLE_REDUNDANT_PLANE_FLUSHES_OPT : 1;
		unsigned int DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP : 1;
		unsigned int    ENABLE_INCOHERENT_EQAA_READS : 1;
		unsigned int    DISABLE_OP_Z_DATA_FORWARDING : 1;
		unsigned int            DISABLE_OP_DF_BYPASS : 1;
		unsigned int     DISABLE_OP_DF_WRITE_COMBINE : 1;
		unsigned int   DISABLE_OP_DF_DIRECT_FEEDBACK : 1;
		unsigned int         ALLOW_RF2P_RW_COLLISION : 1;
		unsigned int     SLOW_PREZ_TO_A2M_OMASK_RATE : 1;
		unsigned int    DISABLE_OP_S_DATA_FORWARDING : 1;
		unsigned int DISABLE_TC_UPDATE_WRITE_COMBINE : 1;
		unsigned int     DISABLE_HZ_TC_WRITE_COMBINE : 1;
		unsigned int ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT : 1;
		unsigned int    ENABLE_TC_MA_ROUND_ROBIN_ARB : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 DB_EXTRA_DEBUG3 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEBUG4__CI {
	struct {
		unsigned int     DISABLE_QC_Z_MASK_SUMMATION : 1;
		unsigned int DISABLE_QC_STENCIL_MASK_SUMMATION : 1;
		unsigned int DISABLE_RESUMM_TO_SINGLE_STENCIL : 1;
		unsigned int DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL : 1;
		unsigned int                 DB_EXTRA_DEBUG4 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEBUG4__VI {
	struct {
		unsigned int     DISABLE_QC_Z_MASK_SUMMATION : 1;
		unsigned int DISABLE_QC_STENCIL_MASK_SUMMATION : 1;
		unsigned int DISABLE_RESUMM_TO_SINGLE_STENCIL : 1;
		unsigned int DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL : 1;
		unsigned int      DISABLE_4XAA_2P_ZD_HOLDOFF : 1;
		unsigned int   ENABLE_A2M_DQUAD_OPTIMIZATION : 1;
		unsigned int                 DB_EXTRA_DEBUG4 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEBUG4__SI {
	struct {
		unsigned int     DISABLE_QC_Z_MASK_SUMMATION : 1;
		unsigned int DISABLE_QC_STENCIL_MASK_SUMMATION : 1;
		unsigned int DISABLE_RESUMM_TO_SINGLE_STENCIL : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL : 1;
		unsigned int                 DB_EXTRA_DEBUG4 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEPTH_BOUNDS_MAX {
	struct {
		unsigned int                             MAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEPTH_BOUNDS_MIN {
	struct {
		unsigned int                             MIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEPTH_CLEAR {
	struct {
		unsigned int                     DEPTH_CLEAR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEPTH_CONTROL {
	struct {
		unsigned int                  STENCIL_ENABLE : 1;
		unsigned int                        Z_ENABLE : 1;
		unsigned int                  Z_WRITE_ENABLE : 1;
		unsigned int             DEPTH_BOUNDS_ENABLE : 1;
		unsigned int                           ZFUNC : 3;
		unsigned int                 BACKFACE_ENABLE : 1;
		unsigned int                     STENCILFUNC : 3;
		unsigned int                                 : 9;
		unsigned int                  STENCILFUNC_BF : 3;
		unsigned int                                 : 7;
		unsigned int ENABLE_COLOR_WRITES_ON_DEPTH_FAIL : 1;
		unsigned int DISABLE_COLOR_WRITES_ON_DEPTH_PASS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEPTH_INFO {
	struct {
                unsigned int              ADDR5_SWIZZLE_MASK : 4;
                unsigned int              ARRAY_MODE__CI__VI : 4;
                unsigned int             PIPE_CONFIG__CI__VI : 5;
                unsigned int              BANK_WIDTH__CI__VI : 2;
                unsigned int             BANK_HEIGHT__CI__VI : 2;
                unsigned int       MACRO_TILE_ASPECT__CI__VI : 2;
                unsigned int               NUM_BANKS__CI__VI : 2;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEPTH_SIZE {
	struct {
		unsigned int                  PITCH_TILE_MAX : 11;
		unsigned int                 HEIGHT_TILE_MAX : 11;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEPTH_SLICE {
	struct {
		unsigned int                  SLICE_TILE_MAX : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_DEPTH_VIEW {
	struct {
		unsigned int                     SLICE_START : 11;
		unsigned int                                 : 2;
		unsigned int                       SLICE_MAX : 11;
		unsigned int                     Z_READ_ONLY : 1;
		unsigned int               STENCIL_READ_ONLY : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_EQAA {
	struct {
		unsigned int              MAX_ANCHOR_SAMPLES : 3;
		unsigned int                                 : 1;
		unsigned int                 PS_ITER_SAMPLES : 3;
		unsigned int                                 : 1;
		unsigned int         MASK_EXPORT_NUM_SAMPLES : 3;
		unsigned int                                 : 1;
		unsigned int       ALPHA_TO_MASK_NUM_SAMPLES : 3;
		unsigned int                                 : 1;
		unsigned int      HIGH_QUALITY_INTERSECTIONS : 1;
		unsigned int           INCOHERENT_EQAA_READS : 1;
		unsigned int              INTERPOLATE_COMP_Z : 1;
		unsigned int               INTERPOLATE_SRC_Z : 1;
		unsigned int      STATIC_ANCHOR_ASSOCIATIONS : 1;
		unsigned int      ALPHA_TO_MASK_EQAA_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int        OVERRASTERIZATION_AMOUNT : 3;
		unsigned int  ENABLE_POSTZ_OVERRASTERIZATION : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_FIFO_DEPTH1 {
	struct {
		unsigned int             MI_RDREQ_FIFO_DEPTH : 5;
		unsigned int             MI_WRREQ_FIFO_DEPTH : 5;
		unsigned int                       MCC_DEPTH : 6;
		unsigned int                        QC_DEPTH : 5;
		unsigned int          LTILE_PROBE_FIFO_DEPTH : 8;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_FIFO_DEPTH2 {
	struct {
		unsigned int                EQUAD_FIFO_DEPTH : 8;
		unsigned int             ETILE_OP_FIFO_DEPTH : 7;
		unsigned int                LQUAD_FIFO_DEPTH : 10;
		unsigned int             LTILE_OP_FIFO_DEPTH : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_FREE_CACHELINES {
	struct {
		unsigned int                FREE_DTILE_DEPTH : 7;
		unsigned int                FREE_PLANE_DEPTH : 7;
		unsigned int                    FREE_Z_DEPTH : 7;
		unsigned int                FREE_HTILE_DEPTH : 4;
		unsigned int                  QUAD_READ_REQS : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_HTILE_DATA_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_HTILE_SURFACE {
	struct {
                unsigned int                          LINEAR : 1;
                unsigned int                      FULL_CACHE : 1;
                unsigned int          HTILE_USES_PRELOAD_WIN : 1;
                unsigned int                         PRELOAD : 1;
                unsigned int                  PREFETCH_WIDTH : 6;
                unsigned int                 PREFETCH_HEIGHT : 6;
                unsigned int         DST_OUTSIDE_ZERO_TO_ONE : 1;
                unsigned int               TC_COMPATIBLE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_OCCLUSION_COUNT0_HI__CI__VI {
	struct {
                unsigned int                        COUNT_HI : 31;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_OCCLUSION_COUNT0_LOW__CI__VI {
	struct {
                unsigned int                       COUNT_LOW : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_OCCLUSION_COUNT1_HI__CI__VI {
	struct {
                unsigned int                        COUNT_HI : 31;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_OCCLUSION_COUNT1_LOW__CI__VI {
	struct {
                unsigned int                       COUNT_LOW : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_OCCLUSION_COUNT2_HI__CI__VI {
	struct {
                unsigned int                        COUNT_HI : 31;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_OCCLUSION_COUNT2_LOW__CI__VI {
	struct {
                unsigned int                       COUNT_LOW : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_OCCLUSION_COUNT3_HI__CI__VI {
	struct {
                unsigned int                        COUNT_HI : 31;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_OCCLUSION_COUNT3_LOW__CI__VI {
	struct {
                unsigned int                       COUNT_LOW : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER0_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int              PERF_MODE1__CI__VI : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE3 : 4;
                unsigned int                      PERF_MODE2 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER1_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int              PERF_MODE1__CI__VI : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER1_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE3 : 4;
                unsigned int                      PERF_MODE2 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER2_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int              PERF_MODE1__CI__VI : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PERFCOUNTER3_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int              PERF_MODE1__CI__VI : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_PRELOAD_CONTROL {
	struct {
		unsigned int                         START_X : 8;
		unsigned int                         START_Y : 8;
		unsigned int                           MAX_X : 8;
		unsigned int                           MAX_Y : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_0 {
	struct {
		unsigned int                      BUSY_DATA0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_1 {
	struct {
		unsigned int                      BUSY_DATA1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_2 {
	struct {
		unsigned int                      BUSY_DATA2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_3 {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_4 {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_5 {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_6 {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_7 {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_8 {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_9 {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_A {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_B {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_C {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_D {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_E {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_READ_DEBUG_F {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_RENDER_CONTROL {
	struct {
                unsigned int              DEPTH_CLEAR_ENABLE : 1;
                unsigned int            STENCIL_CLEAR_ENABLE : 1;
                unsigned int                      DEPTH_COPY : 1;
                unsigned int                    STENCIL_COPY : 1;
                unsigned int              RESUMMARIZE_ENABLE : 1;
                unsigned int        STENCIL_COMPRESS_DISABLE : 1;
                unsigned int          DEPTH_COMPRESS_DISABLE : 1;
                unsigned int                   COPY_CENTROID : 1;
                unsigned int                     COPY_SAMPLE : 4;
                unsigned int           DECOMPRESS_ENABLE__VI : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_RENDER_OVERRIDE {
	struct {
		unsigned int                FORCE_HIZ_ENABLE : 2;
		unsigned int               FORCE_HIS_ENABLE0 : 2;
		unsigned int               FORCE_HIS_ENABLE1 : 2;
		unsigned int            FORCE_SHADER_Z_ORDER : 1;
		unsigned int                  FAST_Z_DISABLE : 1;
		unsigned int            FAST_STENCIL_DISABLE : 1;
		unsigned int               NOOP_CULL_DISABLE : 1;
		unsigned int                FORCE_COLOR_KILL : 1;
		unsigned int                    FORCE_Z_READ : 1;
		unsigned int              FORCE_STENCIL_READ : 1;
		unsigned int              FORCE_FULL_Z_RANGE : 2;
		unsigned int         FORCE_QC_SMASK_CONFLICT : 1;
		unsigned int          DISABLE_VIEWPORT_CLAMP : 1;
		unsigned int                IGNORE_SC_ZRANGE : 1;
		unsigned int           DISABLE_FULLY_COVERED : 1;
		unsigned int              FORCE_Z_LIMIT_SUMM : 2;
		unsigned int                MAX_TILES_IN_DTT : 5;
		unsigned int         DISABLE_TILE_RATE_TILES : 1;
		unsigned int                   FORCE_Z_DIRTY : 1;
		unsigned int             FORCE_STENCIL_DIRTY : 1;
		unsigned int                   FORCE_Z_VALID : 1;
		unsigned int             FORCE_STENCIL_VALID : 1;
		unsigned int            PRESERVE_COMPRESSION : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_RENDER_OVERRIDE2 {
	struct {
                unsigned int    PARTIAL_SQUAD_LAUNCH_CONTROL : 2;
                unsigned int  PARTIAL_SQUAD_LAUNCH_COUNTDOWN : 3;
                unsigned int DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION : 1;
                unsigned int DISABLE_SMEM_EXPCLEAR_OPTIMIZATION : 1;
                unsigned int     DISABLE_COLOR_ON_VALIDATION : 1;
                unsigned int           DECOMPRESS_Z_ON_FLUSH : 1;
                unsigned int               DISABLE_REG_SNOOP : 1;
                unsigned int DEPTH_BOUNDS_HIER_DEPTH_DISABLE : 1;
                unsigned int SEPARATE_HIZS_FUNC_ENABLE__CI__VI : 1;
                unsigned int               HIZ_ZFUNC__CI__VI : 3;
                unsigned int            HIS_SFUNC_FF__CI__VI : 3;
                unsigned int            HIS_SFUNC_BF__CI__VI : 3;
                unsigned int         PRESERVE_ZRANGE__CI__VI : 1;
                unsigned int       PRESERVE_SRESULTS__CI__VI : 1;
                unsigned int       DISABLE_FAST_PASS__CI__VI : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_RING_CONTROL__CI__VI {
	struct {
                unsigned int                 COUNTER_CONTROL : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_SHADER_CONTROL {
	struct {
                unsigned int                 Z_EXPORT_ENABLE : 1;
                unsigned int  STENCIL_TEST_VAL_EXPORT_ENABLE : 1;
                unsigned int    STENCIL_OP_VAL_EXPORT_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int                         Z_ORDER : 2;
                unsigned int                     KILL_ENABLE : 1;
                unsigned int         COVERAGE_TO_MASK_ENABLE : 1;
                unsigned int              MASK_EXPORT_ENABLE : 1;
                unsigned int               EXEC_ON_HIER_FAIL : 1;
                unsigned int                    EXEC_ON_NOOP : 1;
                unsigned int           ALPHA_TO_MASK_DISABLE : 1;
                unsigned int             DEPTH_BEFORE_SHADER : 1;
                unsigned int           CONSERVATIVE_Z_EXPORT : 2;
                unsigned int           DUAL_QUAD_DISABLE__VI : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_SRESULTS_COMPARE_STATE0 {
	struct {
		unsigned int                    COMPAREFUNC0 : 3;
		unsigned int                                 : 1;
		unsigned int                   COMPAREVALUE0 : 8;
		unsigned int                    COMPAREMASK0 : 8;
		unsigned int                                 : 4;
		unsigned int                         ENABLE0 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_SRESULTS_COMPARE_STATE1 {
	struct {
		unsigned int                    COMPAREFUNC1 : 3;
		unsigned int                                 : 1;
		unsigned int                   COMPAREVALUE1 : 8;
		unsigned int                    COMPAREMASK1 : 8;
		unsigned int                                 : 4;
		unsigned int                         ENABLE1 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_STENCILREFMASK {
	struct {
		unsigned int                  STENCILTESTVAL : 8;
		unsigned int                     STENCILMASK : 8;
		unsigned int                STENCILWRITEMASK : 8;
		unsigned int                    STENCILOPVAL : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_STENCILREFMASK_BF {
	struct {
		unsigned int               STENCILTESTVAL_BF : 8;
		unsigned int                  STENCILMASK_BF : 8;
		unsigned int             STENCILWRITEMASK_BF : 8;
		unsigned int                 STENCILOPVAL_BF : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_STENCIL_CLEAR {
	struct {
		unsigned int                           CLEAR : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_STENCIL_CONTROL {
	struct {
		unsigned int                     STENCILFAIL : 4;
		unsigned int                    STENCILZPASS : 4;
		unsigned int                    STENCILZFAIL : 4;
		unsigned int                  STENCILFAIL_BF : 4;
		unsigned int                 STENCILZPASS_BF : 4;
		unsigned int                 STENCILZFAIL_BF : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_STENCIL_INFO {
	struct {
                unsigned int                          FORMAT : 1;
                unsigned int                                 : 12;
                unsigned int              TILE_SPLIT__CI__VI : 3;
                unsigned int                                 : 4;
                unsigned int                 TILE_MODE_INDEX : 3;
                unsigned int                                 : 4;
                unsigned int                  ALLOW_EXPCLEAR : 1;
                unsigned int                                 : 1;
                unsigned int            TILE_STENCIL_DISABLE : 1;
                unsigned int            CLEAR_DISALLOWED__VI : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_STENCIL_READ_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_STENCIL_WRITE_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_SUBTILE_CONTROL {
	struct {
		unsigned int                         MSAA1_X : 2;
		unsigned int                         MSAA1_Y : 2;
		unsigned int                         MSAA2_X : 2;
		unsigned int                         MSAA2_Y : 2;
		unsigned int                         MSAA4_X : 2;
		unsigned int                         MSAA4_Y : 2;
		unsigned int                         MSAA8_X : 2;
		unsigned int                         MSAA8_Y : 2;
		unsigned int                        MSAA16_X : 2;
		unsigned int                        MSAA16_Y : 2;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_WATERMARKS {
	struct {
		unsigned int                      DEPTH_FREE : 5;
		unsigned int                     DEPTH_FLUSH : 6;
		unsigned int                 FORCE_SUMMARIZE : 4;
		unsigned int              DEPTH_PENDING_FREE : 5;
		unsigned int            DEPTH_CACHELINE_FREE : 7;
		unsigned int           EARLY_Z_PANIC_DISABLE : 1;
		unsigned int            LATE_Z_PANIC_DISABLE : 1;
		unsigned int              RE_Z_PANIC_DISABLE : 1;
		unsigned int                AUTO_FLUSH_HTILE : 1;
		unsigned int                 AUTO_FLUSH_QUAD : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_ZPASS_COUNT_HI {
	struct {
		unsigned int                        COUNT_HI : 31;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_ZPASS_COUNT_LOW {
	struct {
		unsigned int                       COUNT_LOW : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_Z_INFO {
	struct {
                unsigned int                          FORMAT : 2;
                unsigned int                     NUM_SAMPLES : 2;
                unsigned int                                 : 9;
                unsigned int              TILE_SPLIT__CI__VI : 3;
                unsigned int                                 : 4;
                unsigned int                 TILE_MODE_INDEX : 3;
                unsigned int     DECOMPRESS_ON_N_ZPLANES__VI : 4;
                unsigned int                  ALLOW_EXPCLEAR : 1;
                unsigned int                       READ_SIZE : 1;
                unsigned int             TILE_SURFACE_ENABLE : 1;
                unsigned int            CLEAR_DISALLOWED__VI : 1;
                unsigned int                ZRANGE_PRECISION : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_Z_READ_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DB_Z_WRITE_BASE {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_AUDIO_DTO0_MODULE__SI {
	struct {
		unsigned int          DCCG_AUDIO_DTO0_MODULE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_AUDIO_DTO0_MODULE__VI {
	struct {
		unsigned int          DCCG_AUDIO_DTO0_MODULE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_AUDIO_DTO0_PHASE__SI {
	struct {
		unsigned int           DCCG_AUDIO_DTO0_PHASE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_AUDIO_DTO0_PHASE__VI {
	struct {
		unsigned int           DCCG_AUDIO_DTO0_PHASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_GATE_DISABLE_CNTL__SI {
	struct {
		unsigned int       DISPCLK_DCCG_GATE_DISABLE : 1;
		unsigned int     DISPCLK_R_DCCG_GATE_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int            DACACLK_GATE_DISABLE : 1;
		unsigned int            DACBCLK_GATE_DISABLE : 1;
		unsigned int            DVOACLK_GATE_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int            SYMCLKA_GATE_DISABLE : 1;
		unsigned int            SYMCLKB_GATE_DISABLE : 1;
		unsigned int            SYMCLKC_GATE_DISABLE : 1;
		unsigned int            SYMCLKD_GATE_DISABLE : 1;
		unsigned int            SYMCLKE_GATE_DISABLE : 1;
		unsigned int            SYMCLKF_GATE_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int            PCLK_TV_GATE_DISABLE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_GATE_DISABLE_CNTL__VI {
	struct {
		unsigned int       DISPCLK_DCCG_GATE_DISABLE : 1;
		unsigned int     DISPCLK_R_DCCG_GATE_DISABLE : 1;
		unsigned int               SCLK_GATE_DISABLE : 1;
		unsigned int           DPREFCLK_GATE_DISABLE : 1;
		unsigned int            DACACLK_GATE_DISABLE : 1;
		unsigned int            DACBCLK_GATE_DISABLE : 1;
		unsigned int            DVOACLK_GATE_DISABLE : 1;
		unsigned int          DPDBG_CLK_GATE_DISABLE : 1;
		unsigned int    DPREFCLK_R_DCCG_GATE_DISABLE : 1;
		unsigned int                                 : 7;
		unsigned int            PCLK_TV_GATE_DISABLE : 1;
		unsigned int            AOMCLK0_GATE_DISABLE : 1;
		unsigned int            AOMCLK1_GATE_DISABLE : 1;
		unsigned int            AOMCLK2_GATE_DISABLE : 1;
		unsigned int     DISPCLK_R_DCCG_RAMP_DISABLE : 1;
		unsigned int     AUDIO_DTO2_CLK_GATE_DISABLE : 1;
		unsigned int       DPREFCLK_GTC_GATE_DISABLE : 1;
		unsigned int         UNB_DB_CLK_GATE_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int             REFCLK_GATE_DISABLE : 1;
		unsigned int       REFCLK_R_DIG_GATE_DISABLE : 1;
		unsigned int             DSICLK_GATE_DISABLE : 1;
		unsigned int            BYTECLK_GATE_DISABLE : 1;
		unsigned int             ESCCLK_GATE_DISABLE : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_TEST_CLK_SEL__SI {
	struct {
		unsigned int      DCCG_TEST_CLK_GENERICA_SEL : 8;
		unsigned int      DCCG_TEST_CLK_GENERICB_SEL : 8;
		unsigned int      DCCG_TEST_CLK_GENERICA_INV : 1;
		unsigned int                                 : 7;
		unsigned int      DCCG_TEST_CLK_GENERICB_INV : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_TEST_CLK_SEL__VI {
	struct {
		unsigned int      DCCG_TEST_CLK_GENERICA_SEL : 9;
		unsigned int                                 : 3;
		unsigned int      DCCG_TEST_CLK_GENERICA_INV : 1;
		unsigned int                                 : 3;
		unsigned int      DCCG_TEST_CLK_GENERICB_SEL : 9;
		unsigned int                                 : 3;
		unsigned int      DCCG_TEST_CLK_GENERICB_INV : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int            DCCG_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int           DCCG_TEST_DEBUG_INDEX : 8;
                unsigned int        DCCG_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_VPCLK_CNTL__SI {
	struct {
		unsigned int                  DCCG_VPCLK_POL : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCDEBUG_BUS_CLK1_SEL__SI__VI {
	struct {
                unsigned int            DCDEBUG_BUS_CLK1_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCDEBUG_BUS_CLK2_SEL__SI__VI {
	struct {
                unsigned int            DCDEBUG_BUS_CLK2_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCDEBUG_BUS_CLK3_SEL__SI__VI {
	struct {
                unsigned int            DCDEBUG_BUS_CLK3_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCDEBUG_BUS_CLK4_SEL__SI__VI {
	struct {
                unsigned int            DCDEBUG_BUS_CLK4_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCDEBUG_OUT_CNTL__SI {
	struct {
		unsigned int               DCDEBUG_BLOCK_SEL : 5;
		unsigned int                  DCDEBUG_OUT_EN : 1;
		unsigned int             DCDEBUG_OUT_PIN_SEL : 1;
		unsigned int        DCDEBUG_OUT_TEST_DATA_EN : 1;
		unsigned int           DCDEBUG_OUT_TEST_DATA : 12;
		unsigned int                 DCDEBUG_OUT_SEL : 2;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCDEBUG_OUT_CNTL__VI {
	struct {
		unsigned int               DCDEBUG_BLOCK_SEL : 5;
		unsigned int                                 : 1;
		unsigned int                  DCDEBUG_OUT_EN : 1;
		unsigned int             DCDEBUG_OUT_PIN_SEL : 1;
		unsigned int        DCDEBUG_OUT_TEST_DATA_EN : 1;
		unsigned int           DCDEBUG_OUT_TEST_DATA : 12;
		unsigned int                 DCDEBUG_OUT_SEL : 2;
		unsigned int           DCDEBUG_OUT_24BIT_SEL : 1;
		unsigned int                 DCDEBUG_CLK_SEL : 5;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCDEBUG_OUT_PIN_OVERRIDE__SI {
	struct {
		unsigned int   DCDEBUG_OUT_OVERRIDE1_PIN_SEL : 4;
		unsigned int DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL : 5;
		unsigned int                                 : 3;
		unsigned int        DCDEBUG_OUT_OVERRIDE1_EN : 1;
		unsigned int                                 : 3;
		unsigned int   DCDEBUG_OUT_OVERRIDE2_PIN_SEL : 4;
		unsigned int DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL : 5;
		unsigned int                                 : 3;
		unsigned int        DCDEBUG_OUT_OVERRIDE2_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCDEBUG_OUT_PIN_OVERRIDE__VI {
	struct {
		unsigned int   DCDEBUG_OUT_OVERRIDE1_PIN_SEL : 5;
		unsigned int DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL : 5;
		unsigned int                                 : 2;
		unsigned int        DCDEBUG_OUT_OVERRIDE1_EN : 1;
		unsigned int                                 : 2;
		unsigned int   DCDEBUG_OUT_OVERRIDE2_PIN_SEL : 5;
		unsigned int DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL : 5;
		unsigned int                                 : 3;
		unsigned int        DCDEBUG_OUT_OVERRIDE2_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG1__SI {
	struct {
		unsigned int    DOUT_DCIO_MVP_DVOCNTL_A0_REG : 2;
		unsigned int  DOUT_DCIO_MVP_DVOCNTL_MASK_REG : 2;
		unsigned int    DOUT_DCIO_MVP_DVOCNTL_EN_REG : 2;
		unsigned int        DOUT_DCIO_MVP_DVOCNTL_A0 : 2;
		unsigned int      DOUT_DCIO_MVP_DVOCNTL_SEL0 : 2;
		unsigned int        DOUT_DCIO_MVP_DVOCNTL_EN : 2;
		unsigned int          DOUT_DCIO_MVP_DVOCLK_C : 1;
		unsigned int       DOUT_DCIO_DVOCNTL1_A0_REG : 1;
		unsigned int    DOUT_DCIO_DVOCNTL1_A0_PREMUX : 1;
		unsigned int           DOUT_DCIO_DVOCNTL1_A0 : 1;
		unsigned int       DOUT_DCIO_DVOCNTL1_EN_REG : 1;
		unsigned int    DOUT_DCIO_DVO_HSYNC_TRISTATE : 1;
		unsigned int      DOUT_DCIO_DVO_CLK_TRISTATE : 1;
		unsigned int    DOUT_DCIO_DVOCNTL1_EN_PREMUX : 1;
		unsigned int           DOUT_DCIO_DVOCNTL1_EN : 1;
		unsigned int          DOUT_DCIO_DVOCNTL1_MUX : 1;
		unsigned int     DOUT_DCIO_DVOCNTL1_MASK_REG : 1;
		unsigned int            DOUT_DCIO_DVO_ENABLE : 1;
		unsigned int    DOUT_DCIO_DVO_VSYNC_TRISTATE : 1;
		unsigned int          DOUT_DCIO_DVO_RATE_SEL : 1;
		unsigned int  DOUT_DCIO_DVOCNTL1_SEL0_PREMUX : 1;
		unsigned int         DOUT_DCIO_DVOCNTL1_SEL0 : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG1__VI {
	struct {
		unsigned int     DCO_DCIO_MVP_DVOCNTL_A0_REG : 2;
		unsigned int   DCO_DCIO_MVP_DVOCNTL_MASK_REG : 2;
		unsigned int     DCO_DCIO_MVP_DVOCNTL_EN_REG : 2;
		unsigned int         DCO_DCIO_MVP_DVOCNTL_A0 : 2;
		unsigned int       DCO_DCIO_MVP_DVOCNTL_SEL0 : 2;
		unsigned int         DCO_DCIO_MVP_DVOCNTL_EN : 2;
		unsigned int           DCO_DCIO_MVP_DVOCLK_C : 1;
		unsigned int        DCO_DCIO_DVOCNTL1_A0_REG : 1;
		unsigned int     DCO_DCIO_DVOCNTL1_A0_PREMUX : 1;
		unsigned int            DCO_DCIO_DVOCNTL1_A0 : 1;
		unsigned int        DCO_DCIO_DVOCNTL1_EN_REG : 1;
		unsigned int     DCO_DCIO_DVO_HSYNC_TRISTATE : 1;
		unsigned int       DCO_DCIO_DVO_CLK_TRISTATE : 1;
		unsigned int     DCO_DCIO_DVOCNTL1_EN_PREMUX : 1;
		unsigned int            DCO_DCIO_DVOCNTL1_EN : 1;
		unsigned int           DCO_DCIO_DVOCNTL1_MUX : 1;
		unsigned int      DCO_DCIO_DVOCNTL1_MASK_REG : 1;
		unsigned int             DCO_DCIO_DVO_ENABLE : 1;
		unsigned int     DCO_DCIO_DVO_VSYNC_TRISTATE : 1;
		unsigned int           DCO_DCIO_DVO_RATE_SEL : 1;
		unsigned int   DCO_DCIO_DVOCNTL1_SEL0_PREMUX : 1;
		unsigned int          DCO_DCIO_DVOCNTL1_SEL0 : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG2__SI__VI {
	struct {
                unsigned int                     DCIO_DEBUG2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG3__SI__VI {
	struct {
                unsigned int                     DCIO_DEBUG3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG4__SI__VI {
	struct {
                unsigned int                     DCIO_DEBUG4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG5__SI__VI {
	struct {
                unsigned int                     DCIO_DEBUG5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG6__SI__VI {
	struct {
                unsigned int                     DCIO_DEBUG6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG7__SI__VI {
	struct {
                unsigned int                     DCIO_DEBUG7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG__SI__VI {
	struct {
                unsigned int                      DCIO_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_IMPCAL_CNTL_AB__SI {
	struct {
		unsigned int              CALR_CNTL_OVERRIDE : 4;
		unsigned int                                 : 1;
		unsigned int               IMPCAL_SOFT_RESET : 1;
		unsigned int                                 : 2;
		unsigned int                   IMPCAL_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int                IMPCAL_ARB_STATE : 3;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_IMPCAL_CNTL_CD__SI__VI {
	struct {
                unsigned int              CALR_CNTL_OVERRIDE : 4;
                unsigned int                                 : 1;
                unsigned int               IMPCAL_SOFT_RESET : 1;
                unsigned int                                 : 2;
                unsigned int                   IMPCAL_STATUS : 2;
                unsigned int                                 : 2;
                unsigned int                IMPCAL_ARB_STATE : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_IMPCAL_CNTL_EF__SI__VI {
	struct {
                unsigned int              CALR_CNTL_OVERRIDE : 4;
                unsigned int                                 : 1;
                unsigned int               IMPCAL_SOFT_RESET : 1;
                unsigned int                                 : 2;
                unsigned int                   IMPCAL_STATUS : 2;
                unsigned int                                 : 2;
                unsigned int                IMPCAL_ARB_STATE : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int             DCI_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int            DCI_TEST_DEBUG_INDEX : 8;
                unsigned int         DCI_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_CRC_CONTROL__SI__VI {
	struct {
                unsigned int                  DCP_CRC_ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int              DCP_CRC_SOURCE_SEL : 3;
                unsigned int                                 : 3;
                unsigned int                DCP_CRC_LINE_SEL : 2;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_CRC_CURRENT__SI__VI {
	struct {
                unsigned int                 DCP_CRC_CURRENT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_CRC_LAST__SI__VI {
	struct {
                unsigned int                    DCP_CRC_LAST : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_CRC_MASK__SI__VI {
	struct {
                unsigned int                    DCP_CRC_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_DEBUG__SI__VI {
	struct {
                unsigned int                       DCP_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI__VI {
	struct {
                unsigned int  DCP_LB_GAP_BETWEEN_CHUNK_20BPP : 4;
                unsigned int  DCP_LB_GAP_BETWEEN_CHUNK_30BPP : 5;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int             DCP_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int            DCP_TEST_DEBUG_INDEX : 8;
                unsigned int         DCP_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_ACE_CNTL_MISC__SI__VI {
	struct {
                unsigned int    ABM1_ACE_REG_WR_MISSED_FRAME : 1;
                unsigned int                                 : 7;
                unsigned int ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_ACE_OFFSET_SLOPE_0__SI__VI {
	struct {
                unsigned int                ABM1_ACE_SLOPE_0 : 15;
                unsigned int                                 : 1;
                unsigned int               ABM1_ACE_OFFSET_0 : 11;
                unsigned int                                 : 4;
                unsigned int                   ABM1_ACE_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_ACE_OFFSET_SLOPE_1__SI__VI {
	struct {
                unsigned int                ABM1_ACE_SLOPE_1 : 15;
                unsigned int                                 : 1;
                unsigned int               ABM1_ACE_OFFSET_1 : 11;
                unsigned int                                 : 4;
                unsigned int                   ABM1_ACE_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_ACE_OFFSET_SLOPE_2__SI__VI {
	struct {
                unsigned int                ABM1_ACE_SLOPE_2 : 15;
                unsigned int                                 : 1;
                unsigned int               ABM1_ACE_OFFSET_2 : 11;
                unsigned int                                 : 4;
                unsigned int                   ABM1_ACE_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_ACE_OFFSET_SLOPE_3__SI__VI {
	struct {
                unsigned int                ABM1_ACE_SLOPE_3 : 15;
                unsigned int                                 : 1;
                unsigned int               ABM1_ACE_OFFSET_3 : 11;
                unsigned int                                 : 4;
                unsigned int                   ABM1_ACE_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_ACE_OFFSET_SLOPE_4__SI__VI {
	struct {
                unsigned int                ABM1_ACE_SLOPE_4 : 15;
                unsigned int                                 : 1;
                unsigned int               ABM1_ACE_OFFSET_4 : 11;
                unsigned int                                 : 4;
                unsigned int                   ABM1_ACE_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_ACE_THRES_12__SI__VI {
	struct {
                unsigned int                ABM1_ACE_THRES_1 : 10;
                unsigned int                                 : 6;
                unsigned int                ABM1_ACE_THRES_2 : 10;
                unsigned int                                 : 5;
                unsigned int                   ABM1_ACE_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_ACE_THRES_34__SI__VI {
	struct {
                unsigned int                ABM1_ACE_THRES_3 : 10;
                unsigned int                                 : 6;
                unsigned int                ABM1_ACE_THRES_4 : 10;
                unsigned int                                 : 2;
                unsigned int  ABM1_ACE_IGNORE_MASTER_LOCK_EN : 1;
                unsigned int ABM1_ACE_READBACK_DB_REG_VALUE_EN : 1;
                unsigned int ABM1_ACE_DBUF_REG_UPDATE_PENDING : 1;
                unsigned int                   ABM1_ACE_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_BL_MASTER_LOCK__SI__VI {
	struct {
                unsigned int                                 : 31;
                unsigned int             ABM1_BL_MASTER_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_CNTL__SI__VI {
	struct {
                unsigned int                         ABM1_EN : 1;
                unsigned int                                 : 7;
                unsigned int              ABM1_SOURCE_SELECT : 3;
                unsigned int                                 : 20;
                unsigned int ABM1_BLANK_MODE_SUPPORT_ENABLE__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_DEBUG_MISC__SI__VI {
	struct {
                unsigned int         ABM1_HG_FORCE_INTERRUPT : 1;
                unsigned int                                 : 7;
                unsigned int         ABM1_LS_FORCE_INTERRUPT : 1;
                unsigned int                                 : 7;
                unsigned int         ABM1_BL_FORCE_INTERRUPT : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HGLS_REG_READ_PROGRESS__SI__VI {
	struct {
                unsigned int    ABM1_HG_REG_READ_IN_PROGRESS : 1;
                unsigned int    ABM1_LS_REG_READ_IN_PROGRESS : 1;
                unsigned int    ABM1_BL_REG_READ_IN_PROGRESS : 1;
                unsigned int                                 : 5;
                unsigned int   ABM1_HG_REG_READ_MISSED_FRAME : 1;
                unsigned int   ABM1_LS_REG_READ_MISSED_FRAME : 1;
                unsigned int   ABM1_BL_REG_READ_MISSED_FRAME : 1;
                unsigned int                                 : 5;
                unsigned int ABM1_HG_REG_READ_MISSED_FRAME_CLEAR : 1;
                unsigned int                                 : 7;
                unsigned int ABM1_LS_REG_READ_MISSED_FRAME_CLEAR : 1;
                unsigned int                                 : 6;
                unsigned int ABM1_BL_REG_READ_MISSED_FRAME_CLEAR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__SI__VI {
	struct {
                unsigned int   ABM1_HG_BIN_17_24_SHIFT_INDEX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__SI__VI {
	struct {
                unsigned int     ABM1_HG_BIN_1_32_SHIFT_FLAG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__SI__VI {
	struct {
                unsigned int     ABM1_HG_BIN_1_8_SHIFT_INDEX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__SI__VI {
	struct {
                unsigned int   ABM1_HG_BIN_25_32_SHIFT_INDEX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__SI__VI {
	struct {
                unsigned int    ABM1_HG_BIN_9_16_SHIFT_INDEX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_MISC_CTRL__SI {
	struct {
		unsigned int         ABM1_HG_NUM_OF_BINS_SEL : 2;
		unsigned int                                 : 6;
		unsigned int                ABM1_HG_VMAX_SEL : 1;
		unsigned int                                 : 3;
		unsigned int       ABM1_HG_FINE_MODE_BIN_SEL : 1;
		unsigned int                                 : 3;
		unsigned int   ABM1_HG_BIN_BITWIDTH_SIZE_SEL : 2;
		unsigned int                                 : 2;
		unsigned int  ABM1_OVR_SCAN_PIXEL_PROCESS_EN : 1;
		unsigned int                                 : 5;
		unsigned int ABM1_HGLS_IGNORE_MASTER_LOCK_EN : 1;
		unsigned int ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN : 1;
		unsigned int ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START : 1;
		unsigned int ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL : 1;
		unsigned int ABM1_DBUF_HGLS_REG_UPDATE_PENDING : 1;
		unsigned int              ABM1_HGLS_REG_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_MISC_CTRL__VI {
	struct {
		unsigned int         ABM1_HG_NUM_OF_BINS_SEL : 2;
		unsigned int                                 : 6;
		unsigned int                ABM1_HG_VMAX_SEL : 1;
		unsigned int                                 : 3;
		unsigned int       ABM1_HG_FINE_MODE_BIN_SEL : 1;
		unsigned int                                 : 3;
		unsigned int   ABM1_HG_BIN_BITWIDTH_SIZE_SEL : 2;
		unsigned int                                 : 2;
		unsigned int  ABM1_OVR_SCAN_PIXEL_PROCESS_EN : 1;
		unsigned int                                 : 2;
		unsigned int ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN : 1;
		unsigned int ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL : 3;
		unsigned int                                 : 1;
		unsigned int ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START : 1;
		unsigned int ABM1_HGLS_IGNORE_MASTER_LOCK_EN : 1;
		unsigned int ABM1_DBUF_HGLS_REG_UPDATE_PENDING : 1;
		unsigned int              ABM1_HGLS_REG_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_10__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_10 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_11__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_11 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_12__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_12 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_13__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_13 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_14__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_14 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_15__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_15 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_16__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_16 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_17__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_17 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_18__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_18 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_19__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_19 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_1__SI__VI {
	struct {
                unsigned int                ABM1_HG_RESULT_1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_20__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_20 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_21__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_21 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_22__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_22 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_23__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_23 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_24__SI__VI {
	struct {
                unsigned int               ABM1_HG_RESULT_24 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_2__SI__VI {
	struct {
                unsigned int                ABM1_HG_RESULT_2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_3__SI__VI {
	struct {
                unsigned int                ABM1_HG_RESULT_3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_4__SI__VI {
	struct {
                unsigned int                ABM1_HG_RESULT_4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_5__SI__VI {
	struct {
                unsigned int                ABM1_HG_RESULT_5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_6__SI__VI {
	struct {
                unsigned int                ABM1_HG_RESULT_6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_7__SI__VI {
	struct {
                unsigned int                ABM1_HG_RESULT_7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_8__SI__VI {
	struct {
                unsigned int                ABM1_HG_RESULT_8 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_RESULT_9__SI__VI {
	struct {
                unsigned int                ABM1_HG_RESULT_9 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_HG_SAMPLE_RATE__SI__VI {
	struct {
                unsigned int    ABM1_HG_SAMPLE_RATE_COUNT_EN : 1;
                unsigned int ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER : 1;
                unsigned int                                 : 6;
                unsigned int ABM1_HG_SAMPLE_RATE_FRAME_COUNT : 8;
                unsigned int ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET : 8;
                unsigned int                                 : 7;
                unsigned int              ABM1_HGLS_REG_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_IPCSC_COEFF_SEL__SI__VI {
	struct {
                unsigned int          ABM1_IPCSC_COEFF_SEL_B : 4;
                unsigned int                                 : 4;
                unsigned int          ABM1_IPCSC_COEFF_SEL_G : 4;
                unsigned int                                 : 4;
                unsigned int          ABM1_IPCSC_COEFF_SEL_R : 4;
                unsigned int                                 : 11;
                unsigned int              ABM1_HGLS_REG_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__SI__VI {
	struct {
                unsigned int       ABM1_LS_FILTERED_MIN_LUMA : 10;
                unsigned int                                 : 6;
                unsigned int       ABM1_LS_FILTERED_MAX_LUMA : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__SI__VI {
	struct {
                unsigned int   ABM1_LS_MAX_PIXEL_VALUE_COUNT : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_LS_MIN_MAX_LUMA__SI__VI {
	struct {
                unsigned int                ABM1_LS_MIN_LUMA : 10;
                unsigned int                                 : 6;
                unsigned int                ABM1_LS_MAX_LUMA : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__SI__VI {
	struct {
                unsigned int   ABM1_LS_MIN_PIXEL_VALUE_THRES : 10;
                unsigned int                                 : 6;
                unsigned int   ABM1_LS_MAX_PIXEL_VALUE_THRES : 10;
                unsigned int                                 : 5;
                unsigned int              ABM1_HGLS_REG_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__SI__VI {
	struct {
                unsigned int   ABM1_LS_MIN_PIXEL_VALUE_COUNT : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_LS_OVR_SCAN_BIN__SI__VI {
	struct {
                unsigned int            ABM1_LS_OVR_SCAN_BIN : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_LS_PIXEL_COUNT__SI__VI {
	struct {
                unsigned int             ABM1_LS_PIXEL_COUNT : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_LS_SAMPLE_RATE__SI__VI {
	struct {
                unsigned int    ABM1_LS_SAMPLE_RATE_COUNT_EN : 1;
                unsigned int ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER : 1;
                unsigned int                                 : 6;
                unsigned int ABM1_LS_SAMPLE_RATE_FRAME_COUNT : 8;
                unsigned int ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET : 8;
                unsigned int                                 : 7;
                unsigned int              ABM1_HGLS_REG_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_LS_SUM_OF_LUMA__SI__VI {
	struct {
                unsigned int             ABM1_LS_SUM_OF_LUMA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_DMCU_SCRATCH__SI__VI {
	struct {
                unsigned int                    DMCU_SCRATCH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GENERICA__SI {
	struct {
		unsigned int                     GENERICA_EN : 1;
		unsigned int                                 : 7;
		unsigned int                    GENERICA_SEL : 4;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GENERICA__VI {
	struct {
		unsigned int                     GENERICA_EN : 1;
		unsigned int                                 : 6;
		unsigned int                    GENERICA_SEL : 5;
		unsigned int  GENERICA_UNIPHY_REFDIV_CLK_SEL : 3;
		unsigned int                                 : 1;
		unsigned int   GENERICA_UNIPHY_FBDIV_CLK_SEL : 3;
		unsigned int                                 : 1;
		unsigned int GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL : 3;
		unsigned int                                 : 1;
		unsigned int GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GENERICB__SI__VI {
	struct {
                unsigned int                     GENERICB_EN : 1;
                unsigned int                                 : 7;
                unsigned int                    GENERICB_SEL : 4;
                unsigned int GENERICB_UNIPHY_REFDIV_CLK_SEL__VI : 3;
                unsigned int                                 : 1;
                unsigned int GENERICB_UNIPHY_FBDIV_CLK_SEL__VI : 3;
                unsigned int                                 : 1;
                unsigned int GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__VI : 3;
                unsigned int                                 : 1;
                unsigned int GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__VI : 3;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC1_A__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC1CLK_A : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC1DATA_A : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC1_EN__SI__VI {
	struct {
                unsigned int              DC_GPIO_DDC1CLK_EN : 1;
                unsigned int                                 : 7;
                unsigned int             DC_GPIO_DDC1DATA_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC1_MASK__SI__VI {
	struct {
                unsigned int            DC_GPIO_DDC1CLK_MASK : 1;
                unsigned int                                 : 3;
                unsigned int           DC_GPIO_DDC1CLK_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int            DC_GPIO_DDC1CLK_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC1DATA_MASK : 1;
                unsigned int                                 : 3;
                unsigned int          DC_GPIO_DDC1DATA_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC1DATA_RECV : 1;
                unsigned int                                 : 1;
                unsigned int                   AUX_PAD1_MODE : 1;
                unsigned int                                 : 3;
                unsigned int                        AUX1_POL : 1;
                unsigned int                                 : 1;
                unsigned int         ALLOW_HW_DDC1_PD_EN__VI : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_DDC1CLK_STR : 4;
                unsigned int            DC_GPIO_DDC1DATA_STR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC1_Y__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC1CLK_Y : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC1DATA_Y : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC2_A__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC2CLK_A : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC2DATA_A : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC2_EN__SI__VI {
	struct {
                unsigned int              DC_GPIO_DDC2CLK_EN : 1;
                unsigned int                                 : 7;
                unsigned int             DC_GPIO_DDC2DATA_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC2_MASK__SI__VI {
	struct {
                unsigned int            DC_GPIO_DDC2CLK_MASK : 1;
                unsigned int                                 : 3;
                unsigned int           DC_GPIO_DDC2CLK_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int            DC_GPIO_DDC2CLK_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC2DATA_MASK : 1;
                unsigned int                                 : 3;
                unsigned int          DC_GPIO_DDC2DATA_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC2DATA_RECV : 1;
                unsigned int                                 : 1;
                unsigned int                   AUX_PAD2_MODE : 1;
                unsigned int                                 : 3;
                unsigned int                        AUX2_POL : 1;
                unsigned int                                 : 1;
                unsigned int         ALLOW_HW_DDC2_PD_EN__VI : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_DDC2CLK_STR : 4;
                unsigned int            DC_GPIO_DDC2DATA_STR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC2_Y__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC2CLK_Y : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC2DATA_Y : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC3_A__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC3CLK_A : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC3DATA_A : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC3_EN__SI__VI {
	struct {
                unsigned int              DC_GPIO_DDC3CLK_EN : 1;
                unsigned int                                 : 7;
                unsigned int             DC_GPIO_DDC3DATA_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC3_MASK__SI__VI {
	struct {
                unsigned int            DC_GPIO_DDC3CLK_MASK : 1;
                unsigned int                                 : 3;
                unsigned int           DC_GPIO_DDC3CLK_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int            DC_GPIO_DDC3CLK_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC3DATA_MASK : 1;
                unsigned int                                 : 3;
                unsigned int          DC_GPIO_DDC3DATA_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC3DATA_RECV : 1;
                unsigned int                                 : 1;
                unsigned int                   AUX_PAD3_MODE : 1;
                unsigned int                                 : 3;
                unsigned int                        AUX3_POL : 1;
                unsigned int                                 : 1;
                unsigned int         ALLOW_HW_DDC3_PD_EN__VI : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_DDC3CLK_STR : 4;
                unsigned int            DC_GPIO_DDC3DATA_STR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC3_Y__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC3CLK_Y : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC3DATA_Y : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC4_A__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC4CLK_A : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC4DATA_A : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC4_EN__SI__VI {
	struct {
                unsigned int              DC_GPIO_DDC4CLK_EN : 1;
                unsigned int                                 : 7;
                unsigned int             DC_GPIO_DDC4DATA_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC4_MASK__SI__VI {
	struct {
                unsigned int            DC_GPIO_DDC4CLK_MASK : 1;
                unsigned int                                 : 3;
                unsigned int           DC_GPIO_DDC4CLK_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int            DC_GPIO_DDC4CLK_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC4DATA_MASK : 1;
                unsigned int                                 : 3;
                unsigned int          DC_GPIO_DDC4DATA_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC4DATA_RECV : 1;
                unsigned int                                 : 1;
                unsigned int                   AUX_PAD4_MODE : 1;
                unsigned int                                 : 3;
                unsigned int                        AUX4_POL : 1;
                unsigned int                                 : 1;
                unsigned int         ALLOW_HW_DDC4_PD_EN__VI : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_DDC4CLK_STR : 4;
                unsigned int            DC_GPIO_DDC4DATA_STR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC4_Y__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC4CLK_Y : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC4DATA_Y : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC5_A__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC5CLK_A : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC5DATA_A : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC5_EN__SI__VI {
	struct {
                unsigned int              DC_GPIO_DDC5CLK_EN : 1;
                unsigned int                                 : 7;
                unsigned int             DC_GPIO_DDC5DATA_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC5_MASK__SI__VI {
	struct {
                unsigned int            DC_GPIO_DDC5CLK_MASK : 1;
                unsigned int                                 : 3;
                unsigned int           DC_GPIO_DDC5CLK_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int            DC_GPIO_DDC5CLK_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC5DATA_MASK : 1;
                unsigned int                                 : 3;
                unsigned int          DC_GPIO_DDC5DATA_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC5DATA_RECV : 1;
                unsigned int                                 : 1;
                unsigned int                   AUX_PAD5_MODE : 1;
                unsigned int                                 : 3;
                unsigned int                        AUX5_POL : 1;
                unsigned int                                 : 1;
                unsigned int         ALLOW_HW_DDC5_PD_EN__VI : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_DDC5CLK_STR : 4;
                unsigned int            DC_GPIO_DDC5DATA_STR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC5_Y__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC5CLK_Y : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC5DATA_Y : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC6_A__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC6CLK_A : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC6DATA_A : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC6_EN__SI__VI {
	struct {
                unsigned int              DC_GPIO_DDC6CLK_EN : 1;
                unsigned int                                 : 7;
                unsigned int             DC_GPIO_DDC6DATA_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC6_MASK__SI__VI {
	struct {
                unsigned int            DC_GPIO_DDC6CLK_MASK : 1;
                unsigned int                                 : 3;
                unsigned int           DC_GPIO_DDC6CLK_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int            DC_GPIO_DDC6CLK_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC6DATA_MASK : 1;
                unsigned int                                 : 3;
                unsigned int          DC_GPIO_DDC6DATA_PD_EN : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_DDC6DATA_RECV : 1;
                unsigned int                                 : 1;
                unsigned int                   AUX_PAD6_MODE : 1;
                unsigned int                                 : 3;
                unsigned int                        AUX6_POL : 1;
                unsigned int                                 : 1;
                unsigned int         ALLOW_HW_DDC6_PD_EN__VI : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_DDC6CLK_STR : 4;
                unsigned int            DC_GPIO_DDC6DATA_STR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDC6_Y__SI__VI {
	struct {
                unsigned int               DC_GPIO_DDC6CLK_Y : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_DDC6DATA_Y : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DEBUG__SI__VI {
	struct {
                unsigned int               DC_GPIO_VIP_DEBUG : 1;
                unsigned int                                 : 7;
                unsigned int             DC_GPIO_MACRO_DEBUG : 2;
                unsigned int                                 : 6;
                unsigned int DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__VI : 1;
                unsigned int   DC_GPIO_DEBUG_BUS_FLOP_EN__VI : 1;
                unsigned int                                 : 13;
                unsigned int        DPRX_LOOPBACK_ENABLE__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DVODATA_A__SI {
	struct {
		unsigned int               DC_GPIO_DVODATA_A : 24;
		unsigned int               DC_GPIO_DVOCNTL_A : 3;
		unsigned int                                 : 1;
		unsigned int                DC_GPIO_DVOCLK_A : 1;
		unsigned int                                 : 1;
		unsigned int           DC_GPIO_MVP_DVOCNTL_A : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DVODATA_A__VI {
	struct {
		unsigned int               DC_GPIO_DVODATA_A : 24;
		unsigned int               DC_GPIO_DVOCNTL_A : 5;
		unsigned int                DC_GPIO_DVOCLK_A : 1;
		unsigned int           DC_GPIO_MVP_DVOCNTL_A : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DVODATA_EN__SI {
	struct {
		unsigned int              DC_GPIO_DVODATA_EN : 24;
		unsigned int              DC_GPIO_DVOCNTL_EN : 3;
		unsigned int                                 : 1;
		unsigned int               DC_GPIO_DVOCLK_EN : 1;
		unsigned int                                 : 1;
		unsigned int          DC_GPIO_MVP_DVOCNTL_EN : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DVODATA_EN__VI {
	struct {
		unsigned int              DC_GPIO_DVODATA_EN : 24;
		unsigned int              DC_GPIO_DVOCNTL_EN : 5;
		unsigned int               DC_GPIO_DVOCLK_EN : 1;
		unsigned int          DC_GPIO_MVP_DVOCNTL_EN : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DVODATA_MASK__SI {
	struct {
		unsigned int            DC_GPIO_DVODATA_MASK : 24;
		unsigned int            DC_GPIO_DVOCNTL_MASK : 3;
		unsigned int                                 : 1;
		unsigned int             DC_GPIO_DVOCLK_MASK : 1;
		unsigned int                                 : 1;
		unsigned int        DC_GPIO_MVP_DVOCNTL_MASK : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DVODATA_MASK__VI {
	struct {
		unsigned int            DC_GPIO_DVODATA_MASK : 24;
		unsigned int            DC_GPIO_DVOCNTL_MASK : 5;
		unsigned int             DC_GPIO_DVOCLK_MASK : 1;
		unsigned int        DC_GPIO_MVP_DVOCNTL_MASK : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DVODATA_Y__SI {
	struct {
		unsigned int               DC_GPIO_DVODATA_Y : 24;
		unsigned int               DC_GPIO_DVOCNTL_Y : 3;
		unsigned int                                 : 1;
		unsigned int                DC_GPIO_DVOCLK_Y : 1;
		unsigned int                                 : 1;
		unsigned int           DC_GPIO_MVP_DVOCNTL_Y : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DVODATA_Y__VI {
	struct {
		unsigned int               DC_GPIO_DVODATA_Y : 24;
		unsigned int               DC_GPIO_DVOCNTL_Y : 5;
		unsigned int                DC_GPIO_DVOCLK_Y : 1;
		unsigned int           DC_GPIO_MVP_DVOCNTL_Y : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_GENERIC_A__SI__VI {
	struct {
                unsigned int              DC_GPIO_GENERICA_A : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_GENERICB_A : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_GENERICC_A : 1;
                unsigned int                                 : 3;
                unsigned int              DC_GPIO_GENERICD_A : 1;
                unsigned int              DC_GPIO_GENERICE_A : 1;
                unsigned int              DC_GPIO_GENERICF_A : 1;
                unsigned int              DC_GPIO_GENERICG_A : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_GENERIC_EN__SI__VI {
	struct {
                unsigned int             DC_GPIO_GENERICA_EN : 1;
                unsigned int                                 : 7;
                unsigned int             DC_GPIO_GENERICB_EN : 1;
                unsigned int                                 : 7;
                unsigned int             DC_GPIO_GENERICC_EN : 1;
                unsigned int                                 : 3;
                unsigned int             DC_GPIO_GENERICD_EN : 1;
                unsigned int             DC_GPIO_GENERICE_EN : 1;
                unsigned int             DC_GPIO_GENERICF_EN : 1;
                unsigned int             DC_GPIO_GENERICG_EN : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_GENERIC_MASK__SI__VI {
	struct {
                unsigned int           DC_GPIO_GENERICA_MASK : 1;
                unsigned int         DC_GPIO_GENERICA_PD_DIS : 1;
                unsigned int           DC_GPIO_GENERICA_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_GENERICB_MASK : 1;
                unsigned int         DC_GPIO_GENERICB_PD_DIS : 1;
                unsigned int           DC_GPIO_GENERICB_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_GENERICC_MASK : 1;
                unsigned int         DC_GPIO_GENERICC_PD_DIS : 1;
                unsigned int           DC_GPIO_GENERICC_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_GENERICD_MASK : 1;
                unsigned int         DC_GPIO_GENERICD_PD_DIS : 1;
                unsigned int           DC_GPIO_GENERICD_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_GENERICE_MASK : 1;
                unsigned int         DC_GPIO_GENERICE_PD_DIS : 1;
                unsigned int           DC_GPIO_GENERICE_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_GENERICF_MASK : 1;
                unsigned int         DC_GPIO_GENERICF_PD_DIS : 1;
                unsigned int           DC_GPIO_GENERICF_RECV : 1;
                unsigned int                                 : 1;
                unsigned int           DC_GPIO_GENERICG_MASK : 1;
                unsigned int         DC_GPIO_GENERICG_PD_DIS : 1;
                unsigned int           DC_GPIO_GENERICG_RECV : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_GENERIC_Y__SI__VI {
	struct {
                unsigned int              DC_GPIO_GENERICA_Y : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_GENERICB_Y : 1;
                unsigned int                                 : 7;
                unsigned int              DC_GPIO_GENERICC_Y : 1;
                unsigned int                                 : 3;
                unsigned int              DC_GPIO_GENERICD_Y : 1;
                unsigned int              DC_GPIO_GENERICE_Y : 1;
                unsigned int              DC_GPIO_GENERICF_Y : 1;
                unsigned int              DC_GPIO_GENERICG_Y : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_HPD_A__SI__VI {
	struct {
                unsigned int                  DC_GPIO_HPD1_A : 1;
                unsigned int                                 : 7;
                unsigned int                  DC_GPIO_HPD2_A : 1;
                unsigned int                                 : 7;
                unsigned int                  DC_GPIO_HPD3_A : 1;
                unsigned int                                 : 7;
                unsigned int                  DC_GPIO_HPD4_A : 1;
                unsigned int                                 : 1;
                unsigned int                  DC_GPIO_HPD5_A : 1;
                unsigned int                                 : 1;
                unsigned int                  DC_GPIO_HPD6_A : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_HPD_EN__SI__VI {
	struct {
                unsigned int                 DC_GPIO_HPD1_EN : 1;
                unsigned int              HPD1_SCHMEN_PI__VI : 1;
                unsigned int              HPD1_SLEWNCORE__VI : 1;
                unsigned int            RX_HPD_SCHMEN_PI__VI : 1;
                unsigned int            RX_HPD_SLEWNCORE__VI : 1;
                unsigned int                                 : 1;
                unsigned int                   HPD1_SEL0__VI : 1;
                unsigned int                 RX_HPD_SEL0__VI : 1;
                unsigned int                 DC_GPIO_HPD2_EN : 1;
                unsigned int                                 : 7;
                unsigned int                 DC_GPIO_HPD3_EN : 1;
                unsigned int                                 : 7;
                unsigned int                 DC_GPIO_HPD4_EN : 1;
                unsigned int                                 : 1;
                unsigned int                 DC_GPIO_HPD5_EN : 1;
                unsigned int                                 : 1;
                unsigned int                 DC_GPIO_HPD6_EN : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_HPD_MASK__SI {
	struct {
		unsigned int               DC_GPIO_HPD1_MASK : 1;
		unsigned int                                 : 3;
		unsigned int             DC_GPIO_HPD1_PD_DIS : 1;
		unsigned int                                 : 1;
		unsigned int               DC_GPIO_HPD1_RECV : 1;
		unsigned int                                 : 1;
		unsigned int               DC_GPIO_HPD2_MASK : 1;
		unsigned int                                 : 7;
		unsigned int               DC_GPIO_HPD3_MASK : 1;
		unsigned int                                 : 7;
		unsigned int               DC_GPIO_HPD4_MASK : 1;
		unsigned int                                 : 1;
		unsigned int               DC_GPIO_HPD5_MASK : 1;
		unsigned int                                 : 1;
		unsigned int               DC_GPIO_HPD6_MASK : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_HPD_MASK__VI {
	struct {
		unsigned int               DC_GPIO_HPD1_MASK : 1;
		unsigned int             DC_GPIO_RX_HPD_MASK : 1;
		unsigned int           DC_GPIO_RX_HPD_PD_DIS : 1;
		unsigned int           DC_GPIO_RX_HPD_RX_SEL : 1;
		unsigned int             DC_GPIO_HPD1_PD_DIS : 1;
		unsigned int                                 : 1;
		unsigned int               DC_GPIO_HPD1_RECV : 1;
		unsigned int                                 : 1;
		unsigned int               DC_GPIO_HPD2_MASK : 1;
		unsigned int             DC_GPIO_HPD2_PD_DIS : 1;
		unsigned int               DC_GPIO_HPD2_RECV : 1;
		unsigned int                                 : 5;
		unsigned int               DC_GPIO_HPD3_MASK : 1;
		unsigned int             DC_GPIO_HPD3_PD_DIS : 1;
		unsigned int               DC_GPIO_HPD3_RECV : 1;
		unsigned int                                 : 1;
		unsigned int               DC_GPIO_HPD4_MASK : 1;
		unsigned int             DC_GPIO_HPD4_PD_DIS : 1;
		unsigned int               DC_GPIO_HPD4_RECV : 1;
		unsigned int                                 : 1;
		unsigned int               DC_GPIO_HPD5_MASK : 1;
		unsigned int             DC_GPIO_HPD5_PD_DIS : 1;
		unsigned int               DC_GPIO_HPD5_RECV : 1;
		unsigned int                                 : 1;
		unsigned int               DC_GPIO_HPD6_MASK : 1;
		unsigned int             DC_GPIO_HPD6_PD_DIS : 1;
		unsigned int               DC_GPIO_HPD6_RECV : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_HPD_Y__SI__VI {
	struct {
                unsigned int                  DC_GPIO_HPD1_Y : 1;
                unsigned int                                 : 7;
                unsigned int                  DC_GPIO_HPD2_Y : 1;
                unsigned int                                 : 7;
                unsigned int                  DC_GPIO_HPD3_Y : 1;
                unsigned int                                 : 7;
                unsigned int                  DC_GPIO_HPD4_Y : 1;
                unsigned int                                 : 1;
                unsigned int                  DC_GPIO_HPD5_Y : 1;
                unsigned int                                 : 1;
                unsigned int                  DC_GPIO_HPD6_Y : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_PAD_STRENGTH_1__SI__VI {
	struct {
                unsigned int           GENLK_STRENGTH_SN__VI : 4;
                unsigned int           GENLK_STRENGTH_SP__VI : 4;
                unsigned int          RX_HPD_STRENGTH_SN__VI : 4;
                unsigned int          RX_HPD_STRENGTH_SP__VI : 4;
                unsigned int                                 : 8;
                unsigned int                SYNC_STRENGTH_SN : 4;
                unsigned int                SYNC_STRENGTH_SP : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_PAD_STRENGTH_2__SI__VI {
	struct {
                unsigned int                     STRENGTH_SN : 4;
                unsigned int                     STRENGTH_SP : 4;
                unsigned int       EXT_RESET_DRVSTRENGTH__VI : 3;
                unsigned int                                 : 1;
                unsigned int          REF_27_DRVSTRENGTH__VI : 3;
                unsigned int                                 : 1;
                unsigned int              PWRSEQ_STRENGTH_SN : 4;
                unsigned int              PWRSEQ_STRENGTH_SP : 4;
                unsigned int                                 : 6;
                unsigned int              REF_27_SRC_SEL__VI : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_PWRSEQ_A__SI__VI {
	struct {
                unsigned int                  DC_GPIO_BLON_A : 1;
                unsigned int                                 : 7;
                unsigned int                 DC_GPIO_DIGON_A : 1;
                unsigned int                                 : 7;
                unsigned int                DC_GPIO_ENA_BL_A : 1;
                unsigned int                                 : 7;
                unsigned int          DC_GPIO_VSYNC_IN_A__VI : 1;
                unsigned int                                 : 6;
                unsigned int          DC_GPIO_HSYNC_IN_A__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_PWRSEQ_EN__SI__VI {
	struct {
                unsigned int                 DC_GPIO_BLON_EN : 1;
                unsigned int     DC_GPIO_VARY_BL_GENERICA_EN : 1;
                unsigned int                                 : 6;
                unsigned int                DC_GPIO_DIGON_EN : 1;
                unsigned int                                 : 7;
                unsigned int               DC_GPIO_ENA_BL_EN : 1;
                unsigned int                                 : 7;
                unsigned int         DC_GPIO_VSYNC_IN_EN__VI : 1;
                unsigned int                                 : 6;
                unsigned int         DC_GPIO_HSYNC_IN_EN__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_PWRSEQ_MASK__SI__VI {
	struct {
                unsigned int               DC_GPIO_BLON_MASK : 1;
                unsigned int                                 : 3;
                unsigned int             DC_GPIO_BLON_PD_DIS : 1;
                unsigned int                                 : 1;
                unsigned int               DC_GPIO_BLON_RECV : 1;
                unsigned int                                 : 1;
                unsigned int              DC_GPIO_DIGON_MASK : 1;
                unsigned int                                 : 3;
                unsigned int            DC_GPIO_DIGON_PD_DIS : 1;
                unsigned int                                 : 1;
                unsigned int              DC_GPIO_DIGON_RECV : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_ENA_BL_MASK : 1;
                unsigned int                                 : 3;
                unsigned int           DC_GPIO_ENA_BL_PD_DIS : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_ENA_BL_RECV : 1;
                unsigned int                                 : 1;
                unsigned int       DC_GPIO_VSYNC_IN_MASK__VI : 1;
                unsigned int     DC_GPIO_VSYNC_IN_PD_DIS__VI : 1;
                unsigned int       DC_GPIO_VSYNC_IN_RECV__VI : 1;
                unsigned int                                 : 1;
                unsigned int       DC_GPIO_HSYNC_IN_MASK__VI : 1;
                unsigned int     DC_GPIO_HSYNC_IN_PD_DIS__VI : 1;
                unsigned int       DC_GPIO_HSYNC_IN_RECV__VI : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_PWRSEQ_Y__SI__VI {
	struct {
                unsigned int                  DC_GPIO_BLON_Y : 1;
                unsigned int                                 : 7;
                unsigned int                 DC_GPIO_DIGON_Y : 1;
                unsigned int                                 : 7;
                unsigned int                DC_GPIO_ENA_BL_Y : 1;
                unsigned int                                 : 7;
                unsigned int            DC_GPIO_VSYNC_IN__VI : 1;
                unsigned int                                 : 6;
                unsigned int            DC_GPIO_HSYNC_IN__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_SYNCA_A__SI__VI {
	struct {
                unsigned int                DC_GPIO_HSYNCA_A : 1;
                unsigned int                                 : 7;
                unsigned int                DC_GPIO_VSYNCA_A : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_SYNCA_EN__SI__VI {
	struct {
                unsigned int               DC_GPIO_HSYNCA_EN : 1;
                unsigned int                                 : 7;
                unsigned int               DC_GPIO_VSYNCA_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_SYNCA_MASK__SI__VI {
	struct {
                unsigned int             DC_GPIO_HSYNCA_MASK : 1;
                unsigned int                                 : 3;
                unsigned int           DC_GPIO_HSYNCA_PD_DIS : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_HSYNCA_RECV : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_VSYNCA_MASK : 1;
                unsigned int                                 : 3;
                unsigned int           DC_GPIO_VSYNCA_PD_DIS : 1;
                unsigned int                                 : 1;
                unsigned int             DC_GPIO_VSYNCA_RECV : 1;
                unsigned int                                 : 9;
                unsigned int DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__VI : 3;
                unsigned int                                 : 1;
                unsigned int DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__VI : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_SYNCA_Y__SI__VI {
	struct {
                unsigned int                DC_GPIO_HSYNCA_Y : 1;
                unsigned int                                 : 7;
                unsigned int                DC_GPIO_VSYNCA_Y : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPU_TIMER_READ_CNTL__SI__VI {
	struct {
                unsigned int        DC_GPU_TIMER_READ_SELECT : 6;
                unsigned int                                 : 2;
                unsigned int DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__VI : 3;
                unsigned int DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__VI : 3;
                unsigned int DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__VI : 3;
                unsigned int DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__VI : 3;
                unsigned int DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__VI : 3;
                unsigned int DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__VI : 3;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPU_TIMER_READ__SI__VI {
	struct {
                unsigned int               DC_GPU_TIMER_READ : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPU_TIMER_START_POSITION__SI {
	struct {
		unsigned int                                 : 3;
		unsigned int                                 : 13;
		unsigned int                                 : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD1_CONTROL__SI {
	struct {
		unsigned int        DC_HPD1_CONNECTION_TIMER : 13;
		unsigned int                                 : 3;
		unsigned int            DC_HPD1_RX_INT_TIMER : 10;
		unsigned int                                 : 2;
		unsigned int                      DC_HPD1_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD1_INT_CONTROL__SI {
	struct {
		unsigned int                 DC_HPD1_INT_ACK : 1;
		unsigned int                                 : 7;
		unsigned int            DC_HPD1_INT_POLARITY : 1;
		unsigned int                                 : 7;
		unsigned int                  DC_HPD1_INT_EN : 1;
		unsigned int                                 : 3;
		unsigned int              DC_HPD1_RX_INT_ACK : 1;
		unsigned int                                 : 3;
		unsigned int               DC_HPD1_RX_INT_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD1_INT_STATUS__SI {
	struct {
		unsigned int              DC_HPD1_INT_STATUS : 1;
		unsigned int                   DC_HPD1_SENSE : 1;
		unsigned int                                 : 6;
		unsigned int           DC_HPD1_RX_INT_STATUS : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD2_CONTROL__SI {
	struct {
		unsigned int        DC_HPD2_CONNECTION_TIMER : 13;
		unsigned int                                 : 3;
		unsigned int            DC_HPD2_RX_INT_TIMER : 10;
		unsigned int                                 : 2;
		unsigned int                      DC_HPD2_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD2_INT_CONTROL__SI {
	struct {
		unsigned int                 DC_HPD2_INT_ACK : 1;
		unsigned int                                 : 7;
		unsigned int            DC_HPD2_INT_POLARITY : 1;
		unsigned int                                 : 7;
		unsigned int                  DC_HPD2_INT_EN : 1;
		unsigned int                                 : 3;
		unsigned int              DC_HPD2_RX_INT_ACK : 1;
		unsigned int                                 : 3;
		unsigned int               DC_HPD2_RX_INT_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD2_INT_STATUS__SI {
	struct {
		unsigned int              DC_HPD2_INT_STATUS : 1;
		unsigned int                   DC_HPD2_SENSE : 1;
		unsigned int                                 : 6;
		unsigned int           DC_HPD2_RX_INT_STATUS : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD3_CONTROL__SI {
	struct {
		unsigned int        DC_HPD3_CONNECTION_TIMER : 13;
		unsigned int                                 : 3;
		unsigned int            DC_HPD3_RX_INT_TIMER : 10;
		unsigned int                                 : 2;
		unsigned int                      DC_HPD3_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD3_INT_CONTROL__SI {
	struct {
		unsigned int                 DC_HPD3_INT_ACK : 1;
		unsigned int                                 : 7;
		unsigned int            DC_HPD3_INT_POLARITY : 1;
		unsigned int                                 : 7;
		unsigned int                  DC_HPD3_INT_EN : 1;
		unsigned int                                 : 3;
		unsigned int              DC_HPD3_RX_INT_ACK : 1;
		unsigned int                                 : 3;
		unsigned int               DC_HPD3_RX_INT_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD3_INT_STATUS__SI {
	struct {
		unsigned int              DC_HPD3_INT_STATUS : 1;
		unsigned int                   DC_HPD3_SENSE : 1;
		unsigned int                                 : 6;
		unsigned int           DC_HPD3_RX_INT_STATUS : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD4_CONTROL__SI {
	struct {
		unsigned int        DC_HPD4_CONNECTION_TIMER : 13;
		unsigned int                                 : 3;
		unsigned int            DC_HPD4_RX_INT_TIMER : 10;
		unsigned int                                 : 2;
		unsigned int                      DC_HPD4_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD4_INT_CONTROL__SI {
	struct {
		unsigned int                 DC_HPD4_INT_ACK : 1;
		unsigned int                                 : 7;
		unsigned int            DC_HPD4_INT_POLARITY : 1;
		unsigned int                                 : 7;
		unsigned int                  DC_HPD4_INT_EN : 1;
		unsigned int                                 : 3;
		unsigned int              DC_HPD4_RX_INT_ACK : 1;
		unsigned int                                 : 3;
		unsigned int               DC_HPD4_RX_INT_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD4_INT_STATUS__SI {
	struct {
		unsigned int              DC_HPD4_INT_STATUS : 1;
		unsigned int                   DC_HPD4_SENSE : 1;
		unsigned int                                 : 6;
		unsigned int           DC_HPD4_RX_INT_STATUS : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD5_CONTROL__SI {
	struct {
		unsigned int        DC_HPD5_CONNECTION_TIMER : 13;
		unsigned int                                 : 3;
		unsigned int            DC_HPD5_RX_INT_TIMER : 10;
		unsigned int                                 : 2;
		unsigned int                      DC_HPD5_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD5_INT_CONTROL__SI {
	struct {
		unsigned int                 DC_HPD5_INT_ACK : 1;
		unsigned int                                 : 7;
		unsigned int            DC_HPD5_INT_POLARITY : 1;
		unsigned int                                 : 7;
		unsigned int                  DC_HPD5_INT_EN : 1;
		unsigned int                                 : 3;
		unsigned int              DC_HPD5_RX_INT_ACK : 1;
		unsigned int                                 : 3;
		unsigned int               DC_HPD5_RX_INT_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD5_INT_STATUS__SI {
	struct {
		unsigned int              DC_HPD5_INT_STATUS : 1;
		unsigned int                   DC_HPD5_SENSE : 1;
		unsigned int                                 : 6;
		unsigned int           DC_HPD5_RX_INT_STATUS : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD6_CONTROL__SI {
	struct {
		unsigned int        DC_HPD6_CONNECTION_TIMER : 13;
		unsigned int                                 : 3;
		unsigned int            DC_HPD6_RX_INT_TIMER : 10;
		unsigned int                                 : 2;
		unsigned int                      DC_HPD6_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD6_INT_CONTROL__SI {
	struct {
		unsigned int                 DC_HPD6_INT_ACK : 1;
		unsigned int                                 : 7;
		unsigned int            DC_HPD6_INT_POLARITY : 1;
		unsigned int                                 : 7;
		unsigned int                  DC_HPD6_INT_EN : 1;
		unsigned int                                 : 3;
		unsigned int              DC_HPD6_RX_INT_ACK : 1;
		unsigned int                                 : 3;
		unsigned int               DC_HPD6_RX_INT_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD6_INT_STATUS__SI {
	struct {
		unsigned int              DC_HPD6_INT_STATUS : 1;
		unsigned int                   DC_HPD6_SENSE : 1;
		unsigned int                                 : 6;
		unsigned int           DC_HPD6_RX_INT_STATUS : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_ARBITRATION__SI__VI {
	struct {
                unsigned int              DC_I2C_SW_PRIORITY : 2;
                unsigned int       DC_I2C_REG_RW_CNTL_STATUS : 2;
                unsigned int          DC_I2C_NO_QUEUED_SW_GO : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 2;
                unsigned int            DC_I2C_ABORT_HW_XFER : 1;
                unsigned int                                 : 3;
                unsigned int            DC_I2C_ABORT_SW_XFER : 1;
                unsigned int                                 : 7;
                unsigned int       DC_I2C_SW_USE_I2C_REG_REQ : 1;
                unsigned int    DC_I2C_SW_DONE_USING_I2C_REG : 1;
                unsigned int                                 : 2;
                unsigned int     DC_I2C_DMCU_USE_I2C_REG_REQ : 1;
                unsigned int  DC_I2C_DMCU_DONE_USING_I2C_REG : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_CONTROL__SI__VI {
	struct {
                unsigned int                       DC_I2C_GO : 1;
                unsigned int               DC_I2C_SOFT_RESET : 1;
                unsigned int               DC_I2C_SEND_RESET : 1;
                unsigned int          DC_I2C_SW_STATUS_RESET : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int               DC_I2C_DDC_SELECT : 3;
                unsigned int                                 : 9;
                unsigned int        DC_I2C_TRANSACTION_COUNT : 2;
                unsigned int                                 : 9;
                unsigned int              DC_I2C_DBG_REF_SEL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DATA__SI__VI {
	struct {
                unsigned int                  DC_I2C_DATA_RW : 1;
                unsigned int                                 : 7;
                unsigned int                     DC_I2C_DATA : 8;
                unsigned int                    DC_I2C_INDEX : 8;
                unsigned int                                 : 7;
                unsigned int              DC_I2C_INDEX_WRITE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC1_HW_STATUS__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC1_HW_STATUS : 2;
                unsigned int                                 : 1;
                unsigned int             DC_I2C_DDC1_HW_DONE : 1;
                unsigned int                                 : 12;
                unsigned int              DC_I2C_DDC1_HW_REQ : 1;
                unsigned int              DC_I2C_DDC1_HW_URG : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC1_EDID_DETECT_STATUS__VI : 1;
                unsigned int                                 : 3;
                unsigned int DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__VI : 4;
                unsigned int DC_I2C_DDC1_EDID_DETECT_STATE__VI : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC1_SETUP__SI__VI {
	struct {
                unsigned int       DC_I2C_DDC1_DATA_DRIVE_EN : 1;
                unsigned int      DC_I2C_DDC1_DATA_DRIVE_SEL : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC1_EDID_DETECT_ENABLE__VI : 1;
                unsigned int DC_I2C_DDC1_EDID_DETECT_MODE__VI : 1;
                unsigned int          DC_I2C_DDC1_ENABLE__VI : 1;
                unsigned int        DC_I2C_DDC1_CLK_DRIVE_EN : 1;
                unsigned int    DC_I2C_DDC1_INTRA_BYTE_DELAY : 8;
                unsigned int DC_I2C_DDC1_INTRA_TRANSACTION_DELAY : 8;
                unsigned int          DC_I2C_DDC1_TIME_LIMIT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC1_SPEED__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC1_THRESHOLD : 2;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL : 1;
                unsigned int                                 : 11;
                unsigned int            DC_I2C_DDC1_PRESCALE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC2_HW_STATUS__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC2_HW_STATUS : 2;
                unsigned int                                 : 1;
                unsigned int             DC_I2C_DDC2_HW_DONE : 1;
                unsigned int                                 : 12;
                unsigned int              DC_I2C_DDC2_HW_REQ : 1;
                unsigned int              DC_I2C_DDC2_HW_URG : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC2_EDID_DETECT_STATUS__VI : 1;
                unsigned int                                 : 3;
                unsigned int DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__VI : 4;
                unsigned int DC_I2C_DDC2_EDID_DETECT_STATE__VI : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC2_SETUP__SI__VI {
	struct {
                unsigned int       DC_I2C_DDC2_DATA_DRIVE_EN : 1;
                unsigned int      DC_I2C_DDC2_DATA_DRIVE_SEL : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC2_EDID_DETECT_ENABLE__VI : 1;
                unsigned int DC_I2C_DDC2_EDID_DETECT_MODE__VI : 1;
                unsigned int          DC_I2C_DDC2_ENABLE__VI : 1;
                unsigned int        DC_I2C_DDC2_CLK_DRIVE_EN : 1;
                unsigned int    DC_I2C_DDC2_INTRA_BYTE_DELAY : 8;
                unsigned int DC_I2C_DDC2_INTRA_TRANSACTION_DELAY : 8;
                unsigned int          DC_I2C_DDC2_TIME_LIMIT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC2_SPEED__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC2_THRESHOLD : 2;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL : 1;
                unsigned int                                 : 11;
                unsigned int            DC_I2C_DDC2_PRESCALE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC3_HW_STATUS__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC3_HW_STATUS : 2;
                unsigned int                                 : 1;
                unsigned int             DC_I2C_DDC3_HW_DONE : 1;
                unsigned int                                 : 12;
                unsigned int              DC_I2C_DDC3_HW_REQ : 1;
                unsigned int              DC_I2C_DDC3_HW_URG : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC3_EDID_DETECT_STATUS__VI : 1;
                unsigned int                                 : 3;
                unsigned int DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__VI : 4;
                unsigned int DC_I2C_DDC3_EDID_DETECT_STATE__VI : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC3_SETUP__SI__VI {
	struct {
                unsigned int       DC_I2C_DDC3_DATA_DRIVE_EN : 1;
                unsigned int      DC_I2C_DDC3_DATA_DRIVE_SEL : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC3_EDID_DETECT_ENABLE__VI : 1;
                unsigned int DC_I2C_DDC3_EDID_DETECT_MODE__VI : 1;
                unsigned int          DC_I2C_DDC3_ENABLE__VI : 1;
                unsigned int        DC_I2C_DDC3_CLK_DRIVE_EN : 1;
                unsigned int    DC_I2C_DDC3_INTRA_BYTE_DELAY : 8;
                unsigned int DC_I2C_DDC3_INTRA_TRANSACTION_DELAY : 8;
                unsigned int          DC_I2C_DDC3_TIME_LIMIT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC3_SPEED__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC3_THRESHOLD : 2;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL : 1;
                unsigned int                                 : 11;
                unsigned int            DC_I2C_DDC3_PRESCALE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC4_HW_STATUS__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC4_HW_STATUS : 2;
                unsigned int                                 : 1;
                unsigned int             DC_I2C_DDC4_HW_DONE : 1;
                unsigned int                                 : 12;
                unsigned int              DC_I2C_DDC4_HW_REQ : 1;
                unsigned int              DC_I2C_DDC4_HW_URG : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC4_EDID_DETECT_STATUS__VI : 1;
                unsigned int                                 : 3;
                unsigned int DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__VI : 4;
                unsigned int DC_I2C_DDC4_EDID_DETECT_STATE__VI : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC4_SETUP__SI__VI {
	struct {
                unsigned int       DC_I2C_DDC4_DATA_DRIVE_EN : 1;
                unsigned int      DC_I2C_DDC4_DATA_DRIVE_SEL : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC4_EDID_DETECT_ENABLE__VI : 1;
                unsigned int DC_I2C_DDC4_EDID_DETECT_MODE__VI : 1;
                unsigned int          DC_I2C_DDC4_ENABLE__VI : 1;
                unsigned int        DC_I2C_DDC4_CLK_DRIVE_EN : 1;
                unsigned int    DC_I2C_DDC4_INTRA_BYTE_DELAY : 8;
                unsigned int DC_I2C_DDC4_INTRA_TRANSACTION_DELAY : 8;
                unsigned int          DC_I2C_DDC4_TIME_LIMIT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC4_SPEED__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC4_THRESHOLD : 2;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL : 1;
                unsigned int                                 : 11;
                unsigned int            DC_I2C_DDC4_PRESCALE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC5_HW_STATUS__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC5_HW_STATUS : 2;
                unsigned int                                 : 1;
                unsigned int             DC_I2C_DDC5_HW_DONE : 1;
                unsigned int                                 : 12;
                unsigned int              DC_I2C_DDC5_HW_REQ : 1;
                unsigned int              DC_I2C_DDC5_HW_URG : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC5_EDID_DETECT_STATUS__VI : 1;
                unsigned int                                 : 3;
                unsigned int DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__VI : 4;
                unsigned int DC_I2C_DDC5_EDID_DETECT_STATE__VI : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC5_SETUP__SI__VI {
	struct {
                unsigned int       DC_I2C_DDC5_DATA_DRIVE_EN : 1;
                unsigned int      DC_I2C_DDC5_DATA_DRIVE_SEL : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC5_EDID_DETECT_ENABLE__VI : 1;
                unsigned int DC_I2C_DDC5_EDID_DETECT_MODE__VI : 1;
                unsigned int          DC_I2C_DDC5_ENABLE__VI : 1;
                unsigned int        DC_I2C_DDC5_CLK_DRIVE_EN : 1;
                unsigned int    DC_I2C_DDC5_INTRA_BYTE_DELAY : 8;
                unsigned int DC_I2C_DDC5_INTRA_TRANSACTION_DELAY : 8;
                unsigned int          DC_I2C_DDC5_TIME_LIMIT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC5_SPEED__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC5_THRESHOLD : 2;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL : 1;
                unsigned int                                 : 11;
                unsigned int            DC_I2C_DDC5_PRESCALE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC6_HW_STATUS__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC6_HW_STATUS : 2;
                unsigned int                                 : 1;
                unsigned int             DC_I2C_DDC6_HW_DONE : 1;
                unsigned int                                 : 12;
                unsigned int              DC_I2C_DDC6_HW_REQ : 1;
                unsigned int              DC_I2C_DDC6_HW_URG : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC6_EDID_DETECT_STATUS__VI : 1;
                unsigned int                                 : 3;
                unsigned int DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__VI : 4;
                unsigned int DC_I2C_DDC6_EDID_DETECT_STATE__VI : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC6_SETUP__SI__VI {
	struct {
                unsigned int       DC_I2C_DDC6_DATA_DRIVE_EN : 1;
                unsigned int      DC_I2C_DDC6_DATA_DRIVE_SEL : 1;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC6_EDID_DETECT_ENABLE__VI : 1;
                unsigned int DC_I2C_DDC6_EDID_DETECT_MODE__VI : 1;
                unsigned int          DC_I2C_DDC6_ENABLE__VI : 1;
                unsigned int        DC_I2C_DDC6_CLK_DRIVE_EN : 1;
                unsigned int    DC_I2C_DDC6_INTRA_BYTE_DELAY : 8;
                unsigned int DC_I2C_DDC6_INTRA_TRANSACTION_DELAY : 8;
                unsigned int          DC_I2C_DDC6_TIME_LIMIT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDC6_SPEED__SI__VI {
	struct {
                unsigned int           DC_I2C_DDC6_THRESHOLD : 2;
                unsigned int                                 : 2;
                unsigned int DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL : 1;
                unsigned int                                 : 11;
                unsigned int            DC_I2C_DDC6_PRESCALE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_INTERRUPT_CONTROL__SI__VI {
	struct {
                unsigned int              DC_I2C_SW_DONE_INT : 1;
                unsigned int              DC_I2C_SW_DONE_ACK : 1;
                unsigned int             DC_I2C_SW_DONE_MASK : 1;
                unsigned int                                 : 1;
                unsigned int         DC_I2C_DDC1_HW_DONE_INT : 1;
                unsigned int         DC_I2C_DDC1_HW_DONE_ACK : 1;
                unsigned int        DC_I2C_DDC1_HW_DONE_MASK : 1;
                unsigned int                                 : 1;
                unsigned int         DC_I2C_DDC2_HW_DONE_INT : 1;
                unsigned int         DC_I2C_DDC2_HW_DONE_ACK : 1;
                unsigned int        DC_I2C_DDC2_HW_DONE_MASK : 1;
                unsigned int                                 : 1;
                unsigned int         DC_I2C_DDC3_HW_DONE_INT : 1;
                unsigned int         DC_I2C_DDC3_HW_DONE_ACK : 1;
                unsigned int        DC_I2C_DDC3_HW_DONE_MASK : 1;
                unsigned int                                 : 1;
                unsigned int         DC_I2C_DDC4_HW_DONE_INT : 1;
                unsigned int         DC_I2C_DDC4_HW_DONE_ACK : 1;
                unsigned int        DC_I2C_DDC4_HW_DONE_MASK : 1;
                unsigned int                                 : 1;
                unsigned int         DC_I2C_DDC5_HW_DONE_INT : 1;
                unsigned int         DC_I2C_DDC5_HW_DONE_ACK : 1;
                unsigned int        DC_I2C_DDC5_HW_DONE_MASK : 1;
                unsigned int                                 : 1;
                unsigned int         DC_I2C_DDC6_HW_DONE_INT : 1;
                unsigned int         DC_I2C_DDC6_HW_DONE_ACK : 1;
                unsigned int        DC_I2C_DDC6_HW_DONE_MASK : 1;
                unsigned int   DC_I2C_DDCVGA_HW_DONE_INT__VI : 1;
                unsigned int   DC_I2C_DDCVGA_HW_DONE_ACK__VI : 1;
                unsigned int  DC_I2C_DDCVGA_HW_DONE_MASK__VI : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_SW_STATUS__SI {
	struct {
		unsigned int                DC_I2C_SW_STATUS : 2;
		unsigned int                  DC_I2C_SW_DONE : 1;
		unsigned int                                 : 1;
		unsigned int               DC_I2C_SW_ABORTED : 1;
		unsigned int               DC_I2C_SW_TIMEOUT : 1;
		unsigned int           DC_I2C_SW_INTERRUPTED : 1;
		unsigned int       DC_I2C_SW_BUFFER_OVERFLOW : 1;
		unsigned int       DC_I2C_SW_STOPPED_ON_NACK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 DC_I2C_SW_NACK0 : 1;
		unsigned int                 DC_I2C_SW_NACK1 : 1;
		unsigned int                 DC_I2C_SW_NACK2 : 1;
		unsigned int                 DC_I2C_SW_NACK3 : 1;
		unsigned int                                 : 2;
		unsigned int                   DC_I2C_SW_REQ : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_SW_STATUS__VI {
	struct {
		unsigned int                DC_I2C_SW_STATUS : 2;
		unsigned int                  DC_I2C_SW_DONE : 1;
		unsigned int                                 : 1;
		unsigned int               DC_I2C_SW_ABORTED : 1;
		unsigned int               DC_I2C_SW_TIMEOUT : 1;
		unsigned int           DC_I2C_SW_INTERRUPTED : 1;
		unsigned int       DC_I2C_SW_BUFFER_OVERFLOW : 1;
		unsigned int       DC_I2C_SW_STOPPED_ON_NACK : 1;
		unsigned int                                 : 3;
		unsigned int                 DC_I2C_SW_NACK0 : 1;
		unsigned int                 DC_I2C_SW_NACK1 : 1;
		unsigned int                 DC_I2C_SW_NACK2 : 1;
		unsigned int                 DC_I2C_SW_NACK3 : 1;
		unsigned int                                 : 2;
		unsigned int                   DC_I2C_SW_REQ : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_TRANSACTION0__SI__VI {
	struct {
                unsigned int                      DC_I2C_RW0 : 1;
                unsigned int                                 : 7;
                unsigned int            DC_I2C_STOP_ON_NACK0 : 1;
                unsigned int                                 : 3;
                unsigned int                   DC_I2C_START0 : 1;
                unsigned int                    DC_I2C_STOP0 : 1;
                unsigned int                                 : 2;
                unsigned int                   DC_I2C_COUNT0 : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_TRANSACTION1__SI__VI {
	struct {
                unsigned int                      DC_I2C_RW1 : 1;
                unsigned int                                 : 7;
                unsigned int            DC_I2C_STOP_ON_NACK1 : 1;
                unsigned int                                 : 3;
                unsigned int                   DC_I2C_START1 : 1;
                unsigned int                    DC_I2C_STOP1 : 1;
                unsigned int                                 : 2;
                unsigned int                   DC_I2C_COUNT1 : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_TRANSACTION2__SI__VI {
	struct {
                unsigned int                      DC_I2C_RW2 : 1;
                unsigned int                                 : 7;
                unsigned int            DC_I2C_STOP_ON_NACK2 : 1;
                unsigned int                                 : 3;
                unsigned int                   DC_I2C_START2 : 1;
                unsigned int                    DC_I2C_STOP2 : 1;
                unsigned int                                 : 2;
                unsigned int                   DC_I2C_COUNT2 : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_TRANSACTION3__SI__VI {
	struct {
                unsigned int                      DC_I2C_RW3 : 1;
                unsigned int                                 : 7;
                unsigned int            DC_I2C_STOP_ON_NACK3 : 1;
                unsigned int                                 : 3;
                unsigned int                   DC_I2C_START3 : 1;
                unsigned int                    DC_I2C_STOP3 : 1;
                unsigned int                                 : 2;
                unsigned int                   DC_I2C_COUNT3 : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_30_COLOR__SI__VI {
	struct {
                unsigned int            DC_LUT_COLOR_10_BLUE : 10;
                unsigned int           DC_LUT_COLOR_10_GREEN : 10;
                unsigned int             DC_LUT_COLOR_10_RED : 10;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_AUTOFILL__SI__VI {
	struct {
                unsigned int                 DC_LUT_AUTOFILL : 1;
                unsigned int            DC_LUT_AUTOFILL_DONE : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_BLACK_OFFSET_BLUE__SI__VI {
	struct {
                unsigned int        DC_LUT_BLACK_OFFSET_BLUE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_BLACK_OFFSET_GREEN__SI__VI {
	struct {
                unsigned int       DC_LUT_BLACK_OFFSET_GREEN : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_BLACK_OFFSET_RED__SI__VI {
	struct {
                unsigned int         DC_LUT_BLACK_OFFSET_RED : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_CONTROL__SI__VI {
	struct {
                unsigned int                    DC_LUT_INC_B : 4;
                unsigned int         DC_LUT_DATA_B_SIGNED_EN : 1;
                unsigned int    DC_LUT_DATA_B_FLOAT_POINT_EN : 1;
                unsigned int        DC_LUT_DATA_B_FORMAT__VI : 2;
                unsigned int                    DC_LUT_INC_G : 4;
                unsigned int         DC_LUT_DATA_G_SIGNED_EN : 1;
                unsigned int    DC_LUT_DATA_G_FLOAT_POINT_EN : 1;
                unsigned int        DC_LUT_DATA_G_FORMAT__VI : 2;
                unsigned int                    DC_LUT_INC_R : 4;
                unsigned int         DC_LUT_DATA_R_SIGNED_EN : 1;
                unsigned int    DC_LUT_DATA_R_FLOAT_POINT_EN : 1;
                unsigned int        DC_LUT_DATA_R_FORMAT__VI : 2;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_PWL_DATA__SI__VI {
	struct {
                unsigned int                     DC_LUT_BASE : 16;
                unsigned int                    DC_LUT_DELTA : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_RW_INDEX__SI__VI {
	struct {
                unsigned int                 DC_LUT_RW_INDEX : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_RW_MODE__SI__VI {
	struct {
                unsigned int                  DC_LUT_RW_MODE : 1;
                unsigned int                                 : 15;
                unsigned int                DC_LUT_ERROR__VI : 1;
                unsigned int            DC_LUT_ERROR_RST__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_SEQ_COLOR__SI__VI {
	struct {
                unsigned int                DC_LUT_SEQ_COLOR : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_WHITE_OFFSET_BLUE__SI__VI {
	struct {
                unsigned int        DC_LUT_WHITE_OFFSET_BLUE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_WHITE_OFFSET_GREEN__SI__VI {
	struct {
                unsigned int       DC_LUT_WHITE_OFFSET_GREEN : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_WHITE_OFFSET_RED__SI__VI {
	struct {
                unsigned int         DC_LUT_WHITE_OFFSET_RED : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_WRITE_EN_MASK__SI__VI {
	struct {
                unsigned int            DC_LUT_WRITE_EN_MASK : 3;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_MVP_LB_CONTROL__SI {
	struct {
		unsigned int           MVP_SWAP_LOCK_IN_MODE : 2;
		unsigned int                                 : 6;
		unsigned int        DC_MVP_SWAP_LOCK_OUT_SEL : 1;
		unsigned int                                 : 3;
		unsigned int  DC_MVP_SWAP_LOCK_OUT_FORCE_ONE : 1;
		unsigned int                                 : 3;
		unsigned int DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int         DC_MVP_SWAP_LOCK_STATUS : 1;
		unsigned int                                 : 7;
		unsigned int         DC_MVP_SWAP_LOCK_IN_CAP : 1;
		unsigned int                                 : 2;
		unsigned int              DC_MVP_SPARE_FLOPS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_MVP_LB_CONTROL__VI {
	struct {
		unsigned int           MVP_SWAP_LOCK_IN_MODE : 2;
		unsigned int                                 : 6;
		unsigned int        DC_MVP_SWAP_LOCK_OUT_SEL : 1;
		unsigned int                                 : 3;
		unsigned int  DC_MVP_SWAP_LOCK_OUT_FORCE_ONE : 1;
		unsigned int                                 : 3;
		unsigned int DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO : 1;
		unsigned int                                 : 3;
		unsigned int         DC_MVP_SWAP_LOCK_STATUS : 1;
		unsigned int                                 : 7;
		unsigned int         DC_MVP_SWAP_LOCK_IN_CAP : 1;
		unsigned int                                 : 2;
		unsigned int              DC_MVP_SPARE_FLOPS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_PAD_EXTERN_SIG__SI__VI {
	struct {
                unsigned int           DC_PAD_EXTERN_SIG_SEL : 4;
                unsigned int            MVP_PIXEL_SRC_STATUS : 2;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_PINSTRAPS__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int         DC_PINSTRAPS_VIP_DEVICE : 1;
		unsigned int                                 : 1;
		unsigned int        DC_PINSTRAPS_SMS_EN_HARD : 1;
		unsigned int              DC_PINSTRAPS_AUDIO : 2;
		unsigned int           DC_PINSTRAPS_CCBYPASS : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_PINSTRAPS__VI {
	struct {
		unsigned int                                 : 10;
		unsigned int        DC_PINSTRAPS_BIF_CEC_DIS : 1;
		unsigned int                                 : 2;
		unsigned int        DC_PINSTRAPS_SMS_EN_HARD : 1;
		unsigned int              DC_PINSTRAPS_AUDIO : 2;
		unsigned int           DC_PINSTRAPS_CCBYPASS : 1;
		unsigned int       DC_PINSTRAPS_CONNECTIVITY : 3;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_REF_CLK_CNTL__SI {
	struct {
		unsigned int               HSYNCA_OUTPUT_SEL : 2;
		unsigned int                                 : 6;
		unsigned int                                 : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_REF_CLK_CNTL__VI {
	struct {
		unsigned int               HSYNCA_OUTPUT_SEL : 2;
		unsigned int                                 : 6;
		unsigned int            GENLK_CLK_OUTPUT_SEL : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int              DC_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int             DC_TEST_DEBUG_INDEX : 8;
                unsigned int          DC_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEBUG_DATA {
	struct {
		unsigned int                      DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEBUG_INDEX {
	struct {
		unsigned int                     DEBUG_INDEX : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DENTIST_DISPCLK_CNTL__SI {
	struct {
		unsigned int        DENTIST_DISPCLK_WDIVIDER : 7;
		unsigned int                                 : 1;
		unsigned int        DENTIST_DISPCLK_RDIVIDER : 7;
		unsigned int                                 : 1;
		unsigned int        DENTIST_DISPCLK_CHG_DONE : 1;
		unsigned int          DENTIST_DISPCLK_CHGTOG : 1;
		unsigned int         DENTIST_DISPCLK_DONETOG : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DENTIST_DISPCLK_CNTL__VI {
	struct {
		unsigned int        DENTIST_DISPCLK_WDIVIDER : 7;
		unsigned int                                 : 1;
		unsigned int        DENTIST_DISPCLK_RDIVIDER : 7;
		unsigned int        DENTIST_DISPCLK_CHG_MODE : 2;
		unsigned int          DENTIST_DISPCLK_CHGTOG : 1;
		unsigned int         DENTIST_DISPCLK_DONETOG : 1;
		unsigned int        DENTIST_DISPCLK_CHG_DONE : 1;
		unsigned int       DENTIST_DPREFCLK_CHG_DONE : 1;
		unsigned int         DENTIST_DPREFCLK_CHGTOG : 1;
		unsigned int        DENTIST_DPREFCLK_DONETOG : 1;
		unsigned int                                 : 1;
		unsigned int       DENTIST_DPREFCLK_WDIVIDER : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DESKTOP_HEIGHT__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEVICE_CAP {
	struct {
		unsigned int             MAX_PAYLOAD_SUPPORT : 3;
		unsigned int                    PHANTOM_FUNC : 2;
		unsigned int                    EXTENDED_TAG : 1;
		unsigned int          L0S_ACCEPTABLE_LATENCY : 3;
		unsigned int           L1_ACCEPTABLE_LATENCY : 3;
		unsigned int                                 : 3;
		unsigned int        ROLE_BASED_ERR_REPORTING : 1;
		unsigned int                                 : 2;
		unsigned int       CAPTURED_SLOT_POWER_LIMIT : 8;
		unsigned int       CAPTURED_SLOT_POWER_SCALE : 2;
		unsigned int                     FLR_CAPABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEVICE_CAP2__CI__VI {
	struct {
                unsigned int     CPL_TIMEOUT_RANGE_SUPPORTED : 4;
                unsigned int       CPL_TIMEOUT_DIS_SUPPORTED : 1;
                unsigned int        ARI_FORWARDING_SUPPORTED : 1;
                unsigned int  ATOMICOP_ROUTING_SUPPORTED__VI : 1;
                unsigned int  ATOMICOP_32CMPLT_SUPPORTED__VI : 1;
                unsigned int  ATOMICOP_64CMPLT_SUPPORTED__VI : 1;
                unsigned int      CAS128_CMPLT_SUPPORTED__VI : 1;
                unsigned int   NO_RO_ENABLED_P2P_PASSING__VI : 1;
                unsigned int               LTR_SUPPORTED__VI : 1;
                unsigned int          TPH_CPLR_SUPPORTED__VI : 2;
                unsigned int                                 : 4;
                unsigned int              OBFF_SUPPORTED__VI : 2;
                unsigned int    EXTENDED_FMT_FIELD_SUPPORTED : 1;
                unsigned int    END_END_TLP_PREFIX_SUPPORTED : 1;
                unsigned int        MAX_END_END_TLP_PREFIXES : 2;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEVICE_CAP2__SI {
	struct {
		unsigned int           CPL_TIMEOUT_RANGE_SUP : 4;
		unsigned int             CPL_TIMEOUT_DIS_SUP : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEVICE_CNTL2 {
	struct {
                unsigned int               CPL_TIMEOUT_VALUE : 4;
                unsigned int                 CPL_TIMEOUT_DIS : 1;
                unsigned int       ARI_FORWARDING_EN__CI__VI : 1;
                unsigned int         ATOMICOP_REQUEST_EN__VI : 1;
                unsigned int    ATOMICOP_EGRESS_BLOCKING__VI : 1;
                unsigned int          IDO_REQUEST_ENABLE__VI : 1;
                unsigned int       IDO_COMPLETION_ENABLE__VI : 1;
                unsigned int                      LTR_EN__VI : 1;
                unsigned int                                 : 2;
                unsigned int                     OBFF_EN__VI : 2;
                unsigned int END_END_TLP_PREFIX_BLOCKING__CI__VI : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEVICE_CNTL__CI__VI {
	struct {
                unsigned int                     CORR_ERR_EN : 1;
                unsigned int                NON_FATAL_ERR_EN : 1;
                unsigned int                    FATAL_ERR_EN : 1;
                unsigned int                   USR_REPORT_EN : 1;
                unsigned int                  RELAXED_ORD_EN : 1;
                unsigned int                MAX_PAYLOAD_SIZE : 3;
                unsigned int                 EXTENDED_TAG_EN : 1;
                unsigned int                 PHANTOM_FUNC_EN : 1;
                unsigned int                 AUX_POWER_PM_EN : 1;
                unsigned int                     NO_SNOOP_EN : 1;
                unsigned int           MAX_READ_REQUEST_SIZE : 3;
                unsigned int                    INITIATE_FLR : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEVICE_CNTL__SI {
	struct {
		unsigned int                     CORR_ERR_EN : 1;
		unsigned int                NON_FATAL_ERR_EN : 1;
		unsigned int                    FATAL_ERR_EN : 1;
		unsigned int                   USR_REPORT_EN : 1;
		unsigned int                  RELAXED_ORD_EN : 1;
		unsigned int                MAX_PAYLOAD_SIZE : 3;
		unsigned int                 EXTENDED_TAG_EN : 1;
		unsigned int                 PHANTOM_FUNC_EN : 1;
		unsigned int                 AUX_POWER_PM_EN : 1;
		unsigned int                     NO_SNOOP_EN : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEVICE_ID {
	struct {
		unsigned int                       DEVICE_ID : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEVICE_STATUS {
	struct {
		unsigned int                        CORR_ERR : 1;
		unsigned int                   NON_FATAL_ERR : 1;
		unsigned int                       FATAL_ERR : 1;
		unsigned int                    USR_DETECTED : 1;
		unsigned int                         AUX_PWR : 1;
		unsigned int               TRANSACTIONS_PEND : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEVICE_STATUS2 {
	struct {
		unsigned int                        RESERVED : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DH_TEST {
	struct {
		unsigned int                         DH_TEST : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DB_CTRL0__CI__VI {
	struct {
                unsigned int                    DIDT_CTRL_EN : 1;
                unsigned int                   USE_REF_CLOCK : 1;
                unsigned int                    PHASE_OFFSET : 2;
                unsigned int                   DIDT_CTRL_RST : 1;
                unsigned int            DIDT_CLK_EN_OVERRIDE : 1;
                unsigned int                                 : 6;
                unsigned int                                 : 6;
                unsigned int                    UNUSED_0__VI : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DB_CTRL1__CI__VI {
	struct {
                unsigned int                       MIN_POWER : 16;
                unsigned int                       MAX_POWER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DB_CTRL2__CI__VI {
	struct {
                unsigned int                 MAX_POWER_DELTA : 14;
                unsigned int                                 : 2;
                unsigned int        SHORT_TERM_INTERVAL_SIZE : 10;
                unsigned int                                 : 1;
                unsigned int        LONG_TERM_INTERVAL_RATIO : 4;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DB_WEIGHT0_3__CI__VI {
	struct {
                unsigned int                         WEIGHT0 : 8;
                unsigned int                         WEIGHT1 : 8;
                unsigned int                         WEIGHT2 : 8;
                unsigned int                         WEIGHT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DB_WEIGHT4_7__CI__VI {
	struct {
                unsigned int                         WEIGHT4 : 8;
                unsigned int                         WEIGHT5 : 8;
                unsigned int                         WEIGHT6 : 8;
                unsigned int                         WEIGHT7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DB_WEIGHT8_11__CI__VI {
	struct {
                unsigned int                         WEIGHT8 : 8;
                unsigned int                         WEIGHT9 : 8;
                unsigned int                        WEIGHT10 : 8;
                unsigned int                        WEIGHT11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_IND_DATA__CI__VI {
	struct {
                unsigned int                   DIDT_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_IND_INDEX__CI__VI {
	struct {
                unsigned int                  DIDT_IND_INDEX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_SQ_CTRL0__CI__VI {
	struct {
                unsigned int                    DIDT_CTRL_EN : 1;
                unsigned int                   USE_REF_CLOCK : 1;
                unsigned int                    PHASE_OFFSET : 2;
                unsigned int                   DIDT_CTRL_RST : 1;
                unsigned int            DIDT_CLK_EN_OVERRIDE : 1;
                unsigned int  DIDT_MAX_STALLS_ALLOWED_HI__VI : 6;
                unsigned int  DIDT_MAX_STALLS_ALLOWED_LO__VI : 6;
                unsigned int                    UNUSED_0__VI : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_SQ_CTRL1__CI__VI {
	struct {
                unsigned int                       MIN_POWER : 16;
                unsigned int                       MAX_POWER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_SQ_CTRL2__CI__VI {
	struct {
                unsigned int                 MAX_POWER_DELTA : 14;
                unsigned int                                 : 2;
                unsigned int        SHORT_TERM_INTERVAL_SIZE : 10;
                unsigned int                                 : 1;
                unsigned int        LONG_TERM_INTERVAL_RATIO : 4;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_SQ_WEIGHT0_3__CI__VI {
	struct {
                unsigned int                         WEIGHT0 : 8;
                unsigned int                         WEIGHT1 : 8;
                unsigned int                         WEIGHT2 : 8;
                unsigned int                         WEIGHT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_SQ_WEIGHT4_7__CI__VI {
	struct {
                unsigned int                         WEIGHT4 : 8;
                unsigned int                         WEIGHT5 : 8;
                unsigned int                         WEIGHT6 : 8;
                unsigned int                         WEIGHT7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_SQ_WEIGHT8_11__CI__VI {
	struct {
                unsigned int                         WEIGHT8 : 8;
                unsigned int                         WEIGHT9 : 8;
                unsigned int                        WEIGHT10 : 8;
                unsigned int                        WEIGHT11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TCP_CTRL0__CI__VI {
	struct {
                unsigned int                    DIDT_CTRL_EN : 1;
                unsigned int                   USE_REF_CLOCK : 1;
                unsigned int                    PHASE_OFFSET : 2;
                unsigned int                   DIDT_CTRL_RST : 1;
                unsigned int            DIDT_CLK_EN_OVERRIDE : 1;
                unsigned int  DIDT_MAX_STALLS_ALLOWED_HI__VI : 6;
                unsigned int  DIDT_MAX_STALLS_ALLOWED_LO__VI : 6;
                unsigned int                    UNUSED_0__VI : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TCP_CTRL1__CI__VI {
	struct {
                unsigned int                       MIN_POWER : 16;
                unsigned int                       MAX_POWER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TCP_CTRL2__CI__VI {
	struct {
                unsigned int                 MAX_POWER_DELTA : 14;
                unsigned int                                 : 2;
                unsigned int        SHORT_TERM_INTERVAL_SIZE : 10;
                unsigned int                                 : 1;
                unsigned int        LONG_TERM_INTERVAL_RATIO : 4;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TCP_WEIGHT0_3__CI__VI {
	struct {
                unsigned int                         WEIGHT0 : 8;
                unsigned int                         WEIGHT1 : 8;
                unsigned int                         WEIGHT2 : 8;
                unsigned int                         WEIGHT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TCP_WEIGHT4_7__CI__VI {
	struct {
                unsigned int                         WEIGHT4 : 8;
                unsigned int                         WEIGHT5 : 8;
                unsigned int                         WEIGHT6 : 8;
                unsigned int                         WEIGHT7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TCP_WEIGHT8_11__CI__VI {
	struct {
                unsigned int                         WEIGHT8 : 8;
                unsigned int                         WEIGHT9 : 8;
                unsigned int                        WEIGHT10 : 8;
                unsigned int                        WEIGHT11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TD_CTRL0__CI__VI {
	struct {
                unsigned int                    DIDT_CTRL_EN : 1;
                unsigned int                   USE_REF_CLOCK : 1;
                unsigned int                    PHASE_OFFSET : 2;
                unsigned int                   DIDT_CTRL_RST : 1;
                unsigned int            DIDT_CLK_EN_OVERRIDE : 1;
                unsigned int  DIDT_MAX_STALLS_ALLOWED_HI__VI : 6;
                unsigned int  DIDT_MAX_STALLS_ALLOWED_LO__VI : 6;
                unsigned int                    UNUSED_0__VI : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TD_CTRL1__CI__VI {
	struct {
                unsigned int                       MIN_POWER : 16;
                unsigned int                       MAX_POWER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TD_CTRL2__CI__VI {
	struct {
                unsigned int                 MAX_POWER_DELTA : 14;
                unsigned int                                 : 2;
                unsigned int        SHORT_TERM_INTERVAL_SIZE : 10;
                unsigned int                                 : 1;
                unsigned int        LONG_TERM_INTERVAL_RATIO : 4;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TD_WEIGHT0_3__CI__VI {
	struct {
                unsigned int                         WEIGHT0 : 8;
                unsigned int                         WEIGHT1 : 8;
                unsigned int                         WEIGHT2 : 8;
                unsigned int                         WEIGHT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TD_WEIGHT4_7__CI__VI {
	struct {
                unsigned int                         WEIGHT4 : 8;
                unsigned int                         WEIGHT5 : 8;
                unsigned int                         WEIGHT6 : 8;
                unsigned int                         WEIGHT7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TD_WEIGHT8_11__CI__VI {
	struct {
                unsigned int                         WEIGHT8 : 8;
                unsigned int                         WEIGHT9 : 8;
                unsigned int                        WEIGHT10 : 8;
                unsigned int                        WEIGHT11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_CLOCK_PATTERN__SI__VI {
	struct {
                unsigned int               DIG_CLOCK_PATTERN : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_OUTPUT_CRC_CNTL__SI__VI {
	struct {
                unsigned int               DIG_OUTPUT_CRC_EN : 1;
                unsigned int                                 : 3;
                unsigned int         DIG_OUTPUT_CRC_LINK_SEL : 1;
                unsigned int                                 : 3;
                unsigned int         DIG_OUTPUT_CRC_DATA_SEL : 2;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_OUTPUT_CRC_RESULT__SI__VI {
	struct {
                unsigned int           DIG_OUTPUT_CRC_RESULT : 30;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_RANDOM_PATTERN_SEED__SI__VI {
	struct {
                unsigned int         DIG_RANDOM_PATTERN_SEED : 24;
                unsigned int      DIG_RAN_PAT_DURING_DE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_TEST_PATTERN__SI__VI {
	struct {
                unsigned int         DIG_TEST_PATTERN_OUT_EN : 1;
                unsigned int      DIG_HALF_CLOCK_PATTERN_SEL : 1;
                unsigned int            LVDS_TEST_CLOCK_DATA : 1;
                unsigned int                                 : 1;
                unsigned int       DIG_RANDOM_PATTERN_OUT_EN : 1;
                unsigned int        DIG_RANDOM_PATTERN_RESET : 1;
                unsigned int DIG_TEST_PATTERN_EXTERNAL_RESET_EN : 1;
                unsigned int                                 : 1;
                unsigned int                LVDS_EYE_PATTERN : 1;
                unsigned int                                 : 7;
                unsigned int         DIG_STATIC_TEST_PATTERN : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISPCLK_CGTT_BLK_CTRL_REG__SI__VI {
	struct {
                unsigned int           DISPCLK_TURN_ON_DELAY : 4;
                unsigned int          DISPCLK_TURN_OFF_DELAY : 8;
                unsigned int       CGTT_DISPCLK_OVERRIDE__VI : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE2__SI {
	struct {
		unsigned int            DC_HPD3_RX_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int          AUX3_SW_DONE_INTERRUPT : 1;
		unsigned int          AUX3_LS_DONE_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE2__VI {
	struct {
		unsigned int SCL_DISP3_MODE_CHANGE_INTERRUPT : 1;
		unsigned int D3BLND_DATA_UNDERFLOW_INTERRUPT : 1;
		unsigned int           LB_D3_VLINE_INTERRUPT : 1;
		unsigned int          LB_D3_VBLANK_INTERRUPT : 1;
		unsigned int        CRTC3_SNAPSHOT_INTERRUPT : 1;
		unsigned int CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1;
		unsigned int CRTC3_FORCE_COUNT_NOW_INTERRUPT : 1;
		unsigned int           CRTC3_TRIGA_INTERRUPT : 1;
		unsigned int           CRTC3_TRIGB_INTERRUPT : 1;
		unsigned int       CRTC3_VSYNC_NOM_INTERRUPT : 1;
		unsigned int CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1;
		unsigned int DIGC_DP_VID_STREAM_DISABLE_INTERRUPT : 1;
		unsigned int               DC_HPD3_INTERRUPT : 1;
		unsigned int            DC_HPD3_RX_INTERRUPT : 1;
		unsigned int          AUX3_SW_DONE_INTERRUPT : 1;
		unsigned int          AUX3_LS_DONE_INTERRUPT : 1;
		unsigned int          LB_D4_VLINE2_INTERRUPT : 1;
		unsigned int          LB_D5_VLINE2_INTERRUPT : 1;
		unsigned int          LB_D6_VLINE2_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1;
		unsigned int CRTC2_EXT_TIMING_SYNC_INTERRUPT : 1;
		unsigned int CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1;
		unsigned int       CRTC2_VERTICAL_INTERRUPT0 : 1;
		unsigned int       CRTC2_VERTICAL_INTERRUPT1 : 1;
		unsigned int       CRTC2_VERTICAL_INTERRUPT2 : 1;
		unsigned int DISP_INTERRUPT_STATUS_CONTINUE3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int            DC_HPD2_RX_INTERRUPT : 1;
		unsigned int DISP_INTERRUPT_STATUS_CONTINUE2 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE__VI {
	struct {
		unsigned int SCL_DISP2_MODE_CHANGE_INTERRUPT : 1;
		unsigned int D2BLND_DATA_UNDERFLOW_INTERRUPT : 1;
		unsigned int           LB_D2_VLINE_INTERRUPT : 1;
		unsigned int          LB_D2_VBLANK_INTERRUPT : 1;
		unsigned int        CRTC2_SNAPSHOT_INTERRUPT : 1;
		unsigned int CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1;
		unsigned int CRTC2_FORCE_COUNT_NOW_INTERRUPT : 1;
		unsigned int           CRTC2_TRIGA_INTERRUPT : 1;
		unsigned int           CRTC2_TRIGB_INTERRUPT : 1;
		unsigned int       CRTC2_VSYNC_NOM_INTERRUPT : 1;
		unsigned int CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1;
		unsigned int DIGB_DP_VID_STREAM_DISABLE_INTERRUPT : 1;
		unsigned int               DC_HPD2_INTERRUPT : 1;
		unsigned int            DC_HPD2_RX_INTERRUPT : 1;
		unsigned int          AUX2_SW_DONE_INTERRUPT : 1;
		unsigned int          AUX2_LS_DONE_INTERRUPT : 1;
		unsigned int          LB_D1_VLINE2_INTERRUPT : 1;
		unsigned int          LB_D2_VLINE2_INTERRUPT : 1;
		unsigned int          LB_D3_VLINE2_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1;
		unsigned int CRTC1_EXT_TIMING_SYNC_INTERRUPT : 1;
		unsigned int CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1;
		unsigned int       CRTC1_VERTICAL_INTERRUPT0 : 1;
		unsigned int       CRTC1_VERTICAL_INTERRUPT1 : 1;
		unsigned int       CRTC1_VERTICAL_INTERRUPT2 : 1;
		unsigned int DISP_INTERRUPT_STATUS_CONTINUE2 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS__SI {
	struct {
		unsigned int SCL_DISP1_MODE_CHANGE_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int           LB_D1_VLINE_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int          LB_D1_VBLANK_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int        CRTC1_SNAPSHOT_INTERRUPT : 1;
		unsigned int CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1;
		unsigned int CRTC1_FORCE_COUNT_NOW_INTERRUPT : 1;
		unsigned int           CRTC1_TRIGA_INTERRUPT : 1;
		unsigned int           CRTC1_TRIGB_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int       DACA_AUTODETECT_INTERRUPT : 1;
		unsigned int       DACB_AUTODETECT_INTERRUPT : 1;
		unsigned int               DC_HPD1_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int        DC_I2C_SW_DONE_INTERRUPT : 1;
		unsigned int        DC_I2C_HW_DONE_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int       CRTC1_VSYNC_NOM_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1;
		unsigned int                                 : 1;
		unsigned int            DMCU_UC_INTERNAL_INT : 1;
		unsigned int               ABM1_HG_READY_INT : 1;
		unsigned int               ABM1_LS_READY_INT : 1;
		unsigned int              ABM1_BL_UPDATE_INT : 1;
		unsigned int  DISP_INTERRUPT_STATUS_CONTINUE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS__VI {
	struct {
		unsigned int SCL_DISP1_MODE_CHANGE_INTERRUPT : 1;
		unsigned int D1BLND_DATA_UNDERFLOW_INTERRUPT : 1;
		unsigned int           LB_D1_VLINE_INTERRUPT : 1;
		unsigned int          LB_D1_VBLANK_INTERRUPT : 1;
		unsigned int        CRTC1_SNAPSHOT_INTERRUPT : 1;
		unsigned int CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1;
		unsigned int CRTC1_FORCE_COUNT_NOW_INTERRUPT : 1;
		unsigned int           CRTC1_TRIGA_INTERRUPT : 1;
		unsigned int           CRTC1_TRIGB_INTERRUPT : 1;
		unsigned int       CRTC1_VSYNC_NOM_INTERRUPT : 1;
		unsigned int CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1;
		unsigned int DIGA_DP_VID_STREAM_DISABLE_INTERRUPT : 1;
		unsigned int               DC_HPD1_INTERRUPT : 1;
		unsigned int            DC_HPD1_RX_INTERRUPT : 1;
		unsigned int          AUX1_SW_DONE_INTERRUPT : 1;
		unsigned int          AUX1_LS_DONE_INTERRUPT : 1;
		unsigned int DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT : 1;
		unsigned int       DACA_AUTODETECT_INTERRUPT : 1;
		unsigned int       DACB_AUTODETECT_INTERRUPT : 1;
		unsigned int        DC_I2C_SW_DONE_INTERRUPT : 1;
		unsigned int        DC_I2C_HW_DONE_INTERRUPT : 1;
		unsigned int            DMCU_UC_INTERNAL_INT : 1;
		unsigned int                    DMCU_SCP_INT : 1;
		unsigned int               ABM1_HG_READY_INT : 1;
		unsigned int               ABM1_LS_READY_INT : 1;
		unsigned int              ABM1_BL_UPDATE_INT : 1;
		unsigned int  DISP_INTERRUPT_STATUS_CONTINUE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_TIMER_CONTROL__SI {
	struct {
		unsigned int            DISP_TIMER_INT_COUNT : 25;
		unsigned int           DISP_TIMER_INT_ENABLE : 1;
		unsigned int          DISP_TIMER_INT_RUNNING : 1;
		unsigned int              DISP_TIMER_INT_MSK : 1;
		unsigned int             DISP_TIMER_INT_STAT : 1;
		unsigned int          DISP_TIMER_INT_STAT_AK : 1;
		unsigned int                  DISP_TIMER_INT : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DLL_CNTL__SI__CI {
	struct {
		unsigned int                  DLL_RESET_TIME : 10;
		unsigned int                                 : 2;
		unsigned int                   DLL_LOCK_TIME : 10;
		unsigned int                                 : 2;
		unsigned int                   MRDCK0_BYPASS : 1;
		unsigned int                   MRDCK1_BYPASS : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMA_POSITION_LOWER_BASE_ADDRESS__SI__VI {
	struct {
                unsigned int      DMA_POSITION_BUFFER_ENABLE : 1;
                unsigned int DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS : 6;
                unsigned int DMA_POSITION_LOWER_BASE_ADDRESS : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMA_POSITION_UPPER_BASE_ADDRESS__SI__VI {
	struct {
                unsigned int DMA_POSITION_UPPER_BASE_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_CTRL__SI {
	struct {
		unsigned int                        RESET_UC : 1;
		unsigned int                   IGNORE_PWRMGT : 1;
		unsigned int               DISABLE_IRQ_TO_UC : 1;
		unsigned int              DISABLE_XIRQ_TO_UC : 1;
		unsigned int                                 : 18;
		unsigned int               UC_REG_RD_TIMEOUT : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_CTRL__VI {
	struct {
		unsigned int                        RESET_UC : 1;
		unsigned int                   IGNORE_PWRMGT : 1;
		unsigned int               DISABLE_IRQ_TO_UC : 1;
		unsigned int              DISABLE_XIRQ_TO_UC : 1;
		unsigned int                     DMCU_ENABLE : 1;
		unsigned int                                 : 11;
		unsigned int               UC_REG_RD_TIMEOUT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_ERAM_RD_CTRL__SI__VI {
	struct {
                unsigned int                    ERAM_RD_ADDR : 16;
                unsigned int                      ERAM_RD_BE : 4;
                unsigned int               ERAM_RD_BYTE_MODE : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_ERAM_RD_DATA__SI__VI {
	struct {
                unsigned int                    ERAM_RD_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_ERAM_WR_CTRL__SI__VI {
	struct {
                unsigned int                    ERAM_WR_ADDR : 16;
                unsigned int                      ERAM_WR_BE : 4;
                unsigned int               ERAM_WR_BYTE_MODE : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_ERAM_WR_DATA__SI__VI {
	struct {
                unsigned int                    ERAM_WR_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_EVENT_TRIGGER__SI__VI {
	struct {
                unsigned int                GEN_SW_INT_TO_UC : 1;
                unsigned int                                 : 15;
                unsigned int            UC_INTERNAL_INT_CODE : 7;
                unsigned int     GEN_UC_INTERNAL_INT_TO_HOST : 1;
                unsigned int                                 : 7;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_FW_CHECKSUM_SMPL_BYTE_POS__SI__VI {
	struct {
                unsigned int DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS : 2;
                unsigned int DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS : 2;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_FW_CS_HI__SI__VI {
	struct {
                unsigned int                  FW_CHECKSUM_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_FW_CS_LO__SI__VI {
	struct {
                unsigned int                  FW_CHECKSUM_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_FW_END_ADDR__SI__VI {
	struct {
                unsigned int                 FW_END_ADDR_LSB : 8;
                unsigned int                 FW_END_ADDR_MSB : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_FW_ISR_START_ADDR__SI__VI {
	struct {
                unsigned int           FW_ISR_START_ADDR_LSB : 8;
                unsigned int           FW_ISR_START_ADDR_MSB : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_FW_START_ADDR__SI__VI {
	struct {
                unsigned int               FW_START_ADDR_LSB : 8;
                unsigned int               FW_START_ADDR_MSB : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_INTERRUPT_STATUS__SI {
	struct {
		unsigned int      ABM1_HG_READY_INT_OCCURRED : 1;
		unsigned int      ABM1_LS_READY_INT_OCCURRED : 1;
		unsigned int     ABM1_BL_UPDATE_INT_OCCURRED : 1;
		unsigned int                MCP_INT_OCCURRED : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int            VBLANK1_INT_OCCURRED : 1;
		unsigned int            VBLANK2_INT_OCCURRED : 1;
		unsigned int        EXTERNAL_SW_INT_OCCURRED : 1;
		unsigned int                SCP_INT_OCCURRED : 1;
		unsigned int        UC_INTERNAL_INT_OCCURRED : 1;
		unsigned int  UC_REG_RD_TIMEOUT_INT_OCCURRED : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_INTERRUPT_STATUS__VI {
	struct {
		unsigned int      ABM1_HG_READY_INT_OCCURRED : 1;
		unsigned int      ABM1_LS_READY_INT_OCCURRED : 1;
		unsigned int     ABM1_BL_UPDATE_INT_OCCURRED : 1;
		unsigned int                MCP_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DSI_POWER_UP_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED : 1;
		unsigned int                                 : 2;
		unsigned int        EXTERNAL_SW_INT_OCCURRED : 1;
		unsigned int                SCP_INT_OCCURRED : 1;
		unsigned int        UC_INTERNAL_INT_OCCURRED : 1;
		unsigned int  UC_REG_RD_TIMEOUT_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED : 1;
		unsigned int DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED : 1;
		unsigned int            VBLANK1_INT_OCCURRED : 1;
		unsigned int            VBLANK2_INT_OCCURRED : 1;
		unsigned int            VBLANK3_INT_OCCURRED : 1;
		unsigned int            VBLANK4_INT_OCCURRED : 1;
		unsigned int            VBLANK5_INT_OCCURRED : 1;
		unsigned int            VBLANK6_INT_OCCURRED : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_INTERRUPT_TO_HOST_EN_MASK__SI__VI {
	struct {
                unsigned int          ABM1_HG_READY_INT_MASK : 1;
                unsigned int          ABM1_LS_READY_INT_MASK : 1;
                unsigned int         ABM1_BL_UPDATE_INT_MASK : 1;
                unsigned int                                 : 1;
                unsigned int DCPG_IHC_DSI_POWER_UP_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DSI_POWER_DOWN_INT_MASK__VI : 1;
                unsigned int                                 : 3;
                unsigned int                    SCP_INT_MASK : 1;
                unsigned int            UC_INTERNAL_INT_MASK : 1;
                unsigned int      UC_REG_RD_TIMEOUT_INT_MASK : 1;
                unsigned int DCPG_IHC_DCFE0_POWER_UP_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE1_POWER_UP_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE2_POWER_UP_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE3_POWER_UP_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE4_POWER_UP_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE5_POWER_UP_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__VI : 1;
                unsigned int DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__VI : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_INTERRUPT_TO_UC_EN_MASK__SI {
	struct {
		unsigned int      ABM1_HG_READY_INT_TO_UC_EN : 1;
		unsigned int      ABM1_LS_READY_INT_TO_UC_EN : 1;
		unsigned int     ABM1_BL_UPDATE_INT_TO_UC_EN : 1;
		unsigned int                MCP_INT_TO_UC_EN : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int            VBLANK1_INT_TO_UC_EN : 1;
		unsigned int            VBLANK2_INT_TO_UC_EN : 1;
		unsigned int        EXTERNAL_SW_INT_TO_UC_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_INTERRUPT_TO_UC_EN_MASK__VI {
	struct {
		unsigned int      ABM1_HG_READY_INT_TO_UC_EN : 1;
		unsigned int      ABM1_LS_READY_INT_TO_UC_EN : 1;
		unsigned int     ABM1_BL_UPDATE_INT_TO_UC_EN : 1;
		unsigned int                MCP_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN : 1;
		unsigned int     STATIC_SCREEN1_INT_TO_UC_EN : 1;
		unsigned int     STATIC_SCREEN2_INT_TO_UC_EN : 1;
		unsigned int        EXTERNAL_SW_INT_TO_UC_EN : 1;
		unsigned int     STATIC_SCREEN3_INT_TO_UC_EN : 1;
		unsigned int     STATIC_SCREEN4_INT_TO_UC_EN : 1;
		unsigned int     STATIC_SCREEN5_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN : 1;
		unsigned int DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN : 1;
		unsigned int            VBLANK1_INT_TO_UC_EN : 1;
		unsigned int            VBLANK2_INT_TO_UC_EN : 1;
		unsigned int            VBLANK3_INT_TO_UC_EN : 1;
		unsigned int            VBLANK4_INT_TO_UC_EN : 1;
		unsigned int            VBLANK5_INT_TO_UC_EN : 1;
		unsigned int            VBLANK6_INT_TO_UC_EN : 1;
		unsigned int     STATIC_SCREEN6_INT_TO_UC_EN : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__SI {
	struct {
		unsigned int  ABM1_HG_READY_INT_XIRQ_IRQ_SEL : 1;
		unsigned int  ABM1_LS_READY_INT_XIRQ_IRQ_SEL : 1;
		unsigned int ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL : 1;
		unsigned int            MCP_INT_XIRQ_IRQ_SEL : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int        VBLANK1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int        VBLANK2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int    EXTERNAL_SW_INT_XIRQ_IRQ_SEL : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VI {
	struct {
		unsigned int  ABM1_HG_READY_INT_XIRQ_IRQ_SEL : 1;
		unsigned int  ABM1_LS_READY_INT_XIRQ_IRQ_SEL : 1;
		unsigned int ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL : 1;
		unsigned int            MCP_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1;
		unsigned int STATIC_SCREEN1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int STATIC_SCREEN2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int    EXTERNAL_SW_INT_XIRQ_IRQ_SEL : 1;
		unsigned int STATIC_SCREEN3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int STATIC_SCREEN4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int STATIC_SCREEN5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1;
		unsigned int        VBLANK1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int        VBLANK2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int        VBLANK3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int        VBLANK4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int        VBLANK5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int        VBLANK6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int STATIC_SCREEN6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_INT_CNT__SI__VI {
	struct {
                unsigned int      DMCU_ABM1_HG_READY_INT_CNT : 8;
                unsigned int      DMCU_ABM1_LS_READY_INT_CNT : 8;
                unsigned int     DMCU_ABM1_BL_UPDATE_INT_CNT : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_IRAM_RD_CTRL__SI__VI {
	struct {
                unsigned int                    IRAM_RD_ADDR : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_IRAM_RD_DATA__SI__VI {
	struct {
                unsigned int                    IRAM_RD_DATA : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_IRAM_WR_CTRL__SI__VI {
	struct {
                unsigned int                    IRAM_WR_ADDR : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_IRAM_WR_DATA__SI__VI {
	struct {
                unsigned int                    IRAM_WR_DATA : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PC_START_ADDR__SI__VI {
	struct {
                unsigned int               PC_START_ADDR_LSB : 8;
                unsigned int               PC_START_ADDR_MSB : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_RAM_ACCESS_CTRL__SI__VI {
	struct {
                unsigned int           ERAM_WR_ADDR_AUTO_INC : 1;
                unsigned int           ERAM_RD_ADDR_AUTO_INC : 1;
                unsigned int           IRAM_WR_ADDR_AUTO_INC : 1;
                unsigned int           IRAM_RD_ADDR_AUTO_INC : 1;
                unsigned int         ERAM_HOST_ACCESS_EN__VI : 1;
                unsigned int         IRAM_HOST_ACCESS_EN__VI : 1;
                unsigned int                                 : 2;
                unsigned int    UC_RST_RELEASE_DELAY_CNT__VI : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_STATUS__SI__VI {
	struct {
                unsigned int                     UC_IN_RESET : 1;
                unsigned int                 UC_IN_WAIT_MODE : 1;
                unsigned int                 UC_IN_STOP_MODE : 1;
                unsigned int                                 : 28;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int            DMCU_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int           DMCU_TEST_DEBUG_INDEX : 8;
                unsigned int        DMCU_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_UC_INTERNAL_INT_STATUS__SI__VI {
	struct {
                unsigned int                UC_INT_IRQ_N_PIN : 1;
                unsigned int               UC_INT_XIRQ_N_PIN : 1;
                unsigned int       UC_INT_SOFTWARE_INTERRUPT : 1;
                unsigned int      UC_INT_ILLEGAL_OPCODE_TRAP : 1;
                unsigned int   UC_INT_TIMER_OUTPUT_COMPARE_4 : 1;
                unsigned int   UC_INT_TIMER_OUTPUT_COMPARE_3 : 1;
                unsigned int   UC_INT_TIMER_OUTPUT_COMPARE_2 : 1;
                unsigned int   UC_INT_TIMER_OUTPUT_COMPARE_1 : 1;
                unsigned int           UC_INT_TIMER_OVERFLOW : 1;
                unsigned int      UC_INT_REAL_TIME_INTERRUPT : 1;
                unsigned int UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5 : 1;
                unsigned int    UC_INT_TIMER_INPUT_CAPTURE_3 : 1;
                unsigned int    UC_INT_TIMER_INPUT_CAPTURE_2 : 1;
                unsigned int    UC_INT_TIMER_INPUT_CAPTURE_1 : 1;
                unsigned int UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE : 1;
                unsigned int UC_INT_PULSE_ACCUMULATOR_OVERFLOW : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_ARBITRATION_CONTROL__SI__VI {
	struct {
                unsigned int DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD : 16;
                unsigned int PIPE_SWITCH_EFFICIENCY_WEIGHT__VI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_CONTROL__SI__VI {
	struct {
                unsigned int                  DMIF_BUFF_SIZE : 2;
                unsigned int DMIF_GROUP_REQUESTS_IN_CHUNK__VI : 1;
                unsigned int                                 : 1;
                unsigned int DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__VI : 1;
                unsigned int                                 : 3;
                unsigned int             DMIF_REQ_BURST_SIZE : 3;
                unsigned int  DMIF_UNDERFLOW_RECOVERY_EN__VI : 1;
                unsigned int DMIF_FORCE_TOTAL_REQ_BURST_SIZE__VI : 4;
                unsigned int DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__VI : 6;
                unsigned int                                 : 2;
                unsigned int      DMIF_DELAY_ARBITRATION__VI : 5;
                unsigned int      DMIF_CHUNK_BUFF_MARGIN__VI : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_DEBUG02__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_HW_DEBUG__SI__VI {
	struct {
                unsigned int                   DMIF_HW_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_STATUS__SI__VI {
	struct {
                unsigned int            DMIF_MC_SEND_ON_IDLE : 8;
                unsigned int      DMIF_CLEAR_MC_SEND_ON_IDLE : 8;
                unsigned int  DMIF_MC_LATENCY_COUNTER_ENABLE : 1;
                unsigned int DMIF_MC_LATENCY_COUNTER_URGENT_ONLY : 1;
                unsigned int                                 : 2;
                unsigned int DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__VI : 3;
                unsigned int                                 : 1;
                unsigned int DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__VI : 3;
                unsigned int                                 : 1;
                unsigned int              DMIF_UNDERFLOW__VI : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int            DMIF_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int           DMIF_TEST_DEBUG_INDEX : 8;
                unsigned int        DMIF_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_POWER_MANAGEMENT_CNTL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                 PM_ASSERT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_SCRATCH0__SI {
	struct {
		unsigned int                   DOUT_SCRATCH0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_SCRATCH1__SI {
	struct {
		unsigned int                   DOUT_SCRATCH1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_SCRATCH2__SI {
	struct {
		unsigned int                   DOUT_SCRATCH2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_SCRATCH3__SI {
	struct {
		unsigned int                   DOUT_SCRATCH3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_SCRATCH4__SI {
	struct {
		unsigned int                   DOUT_SCRATCH4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_SCRATCH5__SI {
	struct {
		unsigned int                   DOUT_SCRATCH5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_SCRATCH6__SI {
	struct {
		unsigned int                   DOUT_SCRATCH6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_SCRATCH7__SI {
	struct {
		unsigned int                   DOUT_SCRATCH7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_TEST_DEBUG_DATA__SI {
	struct {
		unsigned int            DOUT_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DOUT_TEST_DEBUG_INDEX__SI {
	struct {
		unsigned int           DOUT_TEST_DEBUG_INDEX : 8;
		unsigned int        DOUT_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX1_DEBUG_A__SI {
	struct {
		unsigned int                 DP_AUX1_DEBUG_A : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX1_DEBUG_B__SI {
	struct {
		unsigned int                 DP_AUX1_DEBUG_B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX1_DEBUG_C__SI {
	struct {
		unsigned int                 DP_AUX1_DEBUG_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX1_DEBUG_D__SI {
	struct {
		unsigned int                 DP_AUX1_DEBUG_D : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX1_DEBUG_E__SI {
	struct {
		unsigned int                 DP_AUX1_DEBUG_E : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX1_DEBUG_F__SI {
	struct {
		unsigned int                 DP_AUX1_DEBUG_F : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX1_DEBUG_G__SI {
	struct {
		unsigned int                 DP_AUX1_DEBUG_G : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX1_DEBUG_H__SI {
	struct {
		unsigned int                 DP_AUX1_DEBUG_H : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX1_DEBUG_I__SI {
	struct {
		unsigned int                 DP_AUX1_DEBUG_I : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX2_DEBUG_A__SI {
	struct {
		unsigned int                 DP_AUX2_DEBUG_A : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX2_DEBUG_B__SI {
	struct {
		unsigned int                 DP_AUX2_DEBUG_B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX2_DEBUG_C__SI {
	struct {
		unsigned int                 DP_AUX2_DEBUG_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX2_DEBUG_D__SI {
	struct {
		unsigned int                 DP_AUX2_DEBUG_D : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX2_DEBUG_E__SI {
	struct {
		unsigned int                 DP_AUX2_DEBUG_E : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX2_DEBUG_F__SI {
	struct {
		unsigned int                 DP_AUX2_DEBUG_F : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX2_DEBUG_G__SI {
	struct {
		unsigned int                 DP_AUX2_DEBUG_G : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX2_DEBUG_H__SI {
	struct {
		unsigned int                 DP_AUX2_DEBUG_H : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX2_DEBUG_I__SI {
	struct {
		unsigned int                 DP_AUX2_DEBUG_I : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX3_DEBUG_A__SI {
	struct {
		unsigned int                 DP_AUX3_DEBUG_A : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX3_DEBUG_B__SI {
	struct {
		unsigned int                 DP_AUX3_DEBUG_B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX3_DEBUG_C__SI {
	struct {
		unsigned int                 DP_AUX3_DEBUG_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX3_DEBUG_D__SI {
	struct {
		unsigned int                 DP_AUX3_DEBUG_D : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX3_DEBUG_E__SI {
	struct {
		unsigned int                 DP_AUX3_DEBUG_E : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX3_DEBUG_F__SI {
	struct {
		unsigned int                 DP_AUX3_DEBUG_F : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX3_DEBUG_G__SI {
	struct {
		unsigned int                 DP_AUX3_DEBUG_G : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX3_DEBUG_H__SI {
	struct {
		unsigned int                 DP_AUX3_DEBUG_H : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX3_DEBUG_I__SI {
	struct {
		unsigned int                 DP_AUX3_DEBUG_I : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX4_DEBUG_A__SI {
	struct {
		unsigned int                 DP_AUX4_DEBUG_A : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX4_DEBUG_B__SI {
	struct {
		unsigned int                 DP_AUX4_DEBUG_B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX4_DEBUG_C__SI {
	struct {
		unsigned int                 DP_AUX4_DEBUG_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX4_DEBUG_D__SI {
	struct {
		unsigned int                 DP_AUX4_DEBUG_D : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX4_DEBUG_E__SI {
	struct {
		unsigned int                 DP_AUX4_DEBUG_E : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX4_DEBUG_F__SI {
	struct {
		unsigned int                 DP_AUX4_DEBUG_F : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX4_DEBUG_G__SI {
	struct {
		unsigned int                 DP_AUX4_DEBUG_G : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX4_DEBUG_H__SI {
	struct {
		unsigned int                 DP_AUX4_DEBUG_H : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX4_DEBUG_I__SI {
	struct {
		unsigned int                 DP_AUX4_DEBUG_I : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX5_DEBUG_A__SI {
	struct {
		unsigned int                 DP_AUX5_DEBUG_A : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX5_DEBUG_B__SI {
	struct {
		unsigned int                 DP_AUX5_DEBUG_B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX5_DEBUG_C__SI {
	struct {
		unsigned int                 DP_AUX5_DEBUG_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX5_DEBUG_D__SI {
	struct {
		unsigned int                 DP_AUX5_DEBUG_D : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX5_DEBUG_E__SI {
	struct {
		unsigned int                 DP_AUX5_DEBUG_E : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX5_DEBUG_F__SI {
	struct {
		unsigned int                 DP_AUX5_DEBUG_F : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX5_DEBUG_G__SI {
	struct {
		unsigned int                 DP_AUX5_DEBUG_G : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX5_DEBUG_H__SI {
	struct {
		unsigned int                 DP_AUX5_DEBUG_H : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX5_DEBUG_I__SI {
	struct {
		unsigned int                 DP_AUX5_DEBUG_I : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX6_DEBUG_A__SI {
	struct {
		unsigned int                 DP_AUX6_DEBUG_A : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX6_DEBUG_B__SI {
	struct {
		unsigned int                 DP_AUX6_DEBUG_B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX6_DEBUG_C__SI {
	struct {
		unsigned int                 DP_AUX6_DEBUG_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX6_DEBUG_D__SI {
	struct {
		unsigned int                 DP_AUX6_DEBUG_D : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX6_DEBUG_E__SI {
	struct {
		unsigned int                 DP_AUX6_DEBUG_E : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX6_DEBUG_F__SI {
	struct {
		unsigned int                 DP_AUX6_DEBUG_F : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX6_DEBUG_G__SI {
	struct {
		unsigned int                 DP_AUX6_DEBUG_G : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX6_DEBUG_H__SI {
	struct {
		unsigned int                 DP_AUX6_DEBUG_H : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX6_DEBUG_I__SI {
	struct {
		unsigned int                 DP_AUX6_DEBUG_I : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_CONFIG__SI__VI {
	struct {
                unsigned int                    DP_UDI_LANES : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_8B10B_CNTL__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                DPHY_8B10B_RESET : 1;
		unsigned int                                 : 7;
		unsigned int             DPHY_8B10B_EXT_DISP : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_8B10B_CNTL__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int                DPHY_8B10B_RESET : 1;
		unsigned int                                 : 7;
		unsigned int             DPHY_8B10B_EXT_DISP : 1;
		unsigned int                                 : 7;
		unsigned int             DPHY_8B10B_CUR_DISP : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_CNTL__SI__VI {
	struct {
                unsigned int            DPHY_ATEST_SEL_LANE0 : 1;
                unsigned int            DPHY_ATEST_SEL_LANE1 : 1;
                unsigned int            DPHY_ATEST_SEL_LANE2 : 1;
                unsigned int            DPHY_ATEST_SEL_LANE3 : 1;
                unsigned int                                 : 4;
                unsigned int                                 : 1;
                unsigned int                                 : 7;
                unsigned int                     DPHY_BYPASS : 1;
                unsigned int                                 : 7;
                unsigned int                DPHY_SKEW_BYPASS : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_CRC_CNTL__SI__VI {
	struct {
                unsigned int                  DPHY_CRC_FIELD : 1;
                unsigned int                                 : 3;
                unsigned int                    DPHY_CRC_SEL : 2;
                unsigned int                                 : 10;
                unsigned int                   DPHY_CRC_MASK : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_CRC_EN__SI__VI {
	struct {
                unsigned int                     DPHY_CRC_EN : 1;
                unsigned int                                 : 3;
                unsigned int                DPHY_CRC_CONT_EN : 1;
                unsigned int                                 : 3;
                unsigned int       DPHY_CRC_RESULT_VALID__VI : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_CRC_RESULT__SI__VI {
	struct {
                unsigned int                 DPHY_CRC_RESULT : 8;
                unsigned int            DPHY_CRC_RESULT1__VI : 8;
                unsigned int            DPHY_CRC_RESULT2__VI : 8;
                unsigned int            DPHY_CRC_RESULT3__VI : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_FAST_TRAINING__SI {
	struct {
		unsigned int   DPHY_RX_FAST_TRAINING_CAPABLE : 1;
		unsigned int     DPHY_SW_FAST_TRAINING_START : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int     DPHY_FAST_TRAINING_TP1_TIME : 12;
		unsigned int     DPHY_FAST_TRAINING_TP2_TIME : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_FAST_TRAINING__VI {
	struct {
		unsigned int   DPHY_RX_FAST_TRAINING_CAPABLE : 1;
		unsigned int     DPHY_SW_FAST_TRAINING_START : 1;
		unsigned int DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN : 1;
		unsigned int                                 : 5;
		unsigned int     DPHY_FAST_TRAINING_TP1_TIME : 12;
		unsigned int     DPHY_FAST_TRAINING_TP2_TIME : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_PRBS_CNTL__SI__VI {
	struct {
                unsigned int                    DPHY_PRBS_EN : 1;
                unsigned int                                 : 3;
                unsigned int                   DPHY_PRBS_SEL : 2;
                unsigned int                                 : 2;
                unsigned int                  DPHY_PRBS_SEED : 23;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_SYM__SI {
	struct {
		unsigned int                                 : 10;
		unsigned int                                 : 10;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_TRAINING_PATTERN_SEL__SI__VI {
	struct {
                unsigned int       DPHY_TRAINING_PATTERN_SEL : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO0_MODULO__SI__VI {
	struct {
                unsigned int                  DP_DTO0_MODULO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO0_PHASE__SI__VI {
	struct {
                unsigned int                   DP_DTO0_PHASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO1_MODULO__SI__VI {
	struct {
                unsigned int                  DP_DTO1_MODULO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO1_PHASE__SI__VI {
	struct {
                unsigned int                   DP_DTO1_PHASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO2_MODULO__SI__VI {
	struct {
                unsigned int                  DP_DTO2_MODULO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO2_PHASE__SI__VI {
	struct {
                unsigned int                   DP_DTO2_PHASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO3_MODULO__SI__VI {
	struct {
                unsigned int                  DP_DTO3_MODULO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO3_PHASE__SI__VI {
	struct {
                unsigned int                   DP_DTO3_PHASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO4_MODULO__SI__VI {
	struct {
                unsigned int                  DP_DTO4_MODULO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO4_PHASE__SI__VI {
	struct {
                unsigned int                   DP_DTO4_PHASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO5_MODULO__SI__VI {
	struct {
                unsigned int                  DP_DTO5_MODULO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DTO5_PHASE__SI__VI {
	struct {
                unsigned int                   DP_DTO5_PHASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_LINK_CNTL__SI {
	struct {
		unsigned int                                 : 4;
		unsigned int       DP_LINK_TRAINING_COMPLETE : 1;
		unsigned int                                 : 3;
		unsigned int                  DP_LINK_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int          DP_EMBEDDED_PANEL_MODE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_LINK_CNTL__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int       DP_LINK_TRAINING_COMPLETE : 1;
		unsigned int                                 : 3;
		unsigned int                  DP_LINK_STATUS : 1;
		unsigned int                                 : 8;
		unsigned int          DP_EMBEDDED_PANEL_MODE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_PIXEL_FORMAT__SI__VI {
	struct {
                unsigned int               DP_PIXEL_ENCODING : 3;
                unsigned int                                 : 5;
                unsigned int                    DP_DYN_RANGE : 1;
                unsigned int                                 : 7;
                unsigned int                  DP_YCBCR_RANGE : 1;
                unsigned int                                 : 7;
                unsigned int              DP_COMPONENT_DEPTH : 3;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_AUD_M_READBACK__SI__VI {
	struct {
                unsigned int           DP_SEC_AUD_M_READBACK : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_AUD_M__SI__VI {
	struct {
                unsigned int                    DP_SEC_AUD_M : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_AUD_N_READBACK__SI__VI {
	struct {
                unsigned int           DP_SEC_AUD_N_READBACK : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_AUD_N__SI__VI {
	struct {
                unsigned int                    DP_SEC_AUD_N : 24;
                unsigned int                                 : 4;
                unsigned int                                 : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_CNTL__SI {
	struct {
		unsigned int            DP_SEC_STREAM_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               DP_SEC_ASP_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               DP_SEC_ATP_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               DP_SEC_AIP_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int               DP_SEC_AVI_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               DP_SEC_MPG_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_CNTL__VI {
	struct {
		unsigned int            DP_SEC_STREAM_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               DP_SEC_ASP_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               DP_SEC_ATP_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               DP_SEC_AIP_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               DP_SEC_ACM_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int              DP_SEC_GSP0_ENABLE : 1;
		unsigned int              DP_SEC_GSP1_ENABLE : 1;
		unsigned int              DP_SEC_GSP2_ENABLE : 1;
		unsigned int              DP_SEC_GSP3_ENABLE : 1;
		unsigned int               DP_SEC_AVI_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               DP_SEC_MPG_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_FRAMING1__SI__VI {
	struct {
                unsigned int     DP_SEC_FRAME_START_LOCATION : 12;
                unsigned int                                 : 4;
                unsigned int    DP_SEC_VBLANK_TRANSMIT_WIDTH : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_FRAMING2__SI__VI {
	struct {
                unsigned int           DP_SEC_START_POSITION : 16;
                unsigned int    DP_SEC_HBLANK_TRANSMIT_WIDTH : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_FRAMING3__SI__VI {
	struct {
                unsigned int          DP_SEC_IDLE_FRAME_SIZE : 14;
                unsigned int                                 : 2;
                unsigned int      DP_SEC_IDLE_TRANSMIT_WIDTH : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_FRAMING4__SI__VI {
	struct {
                unsigned int                                 : 20;
                unsigned int         DP_SEC_COLLISION_STATUS : 1;
                unsigned int                                 : 3;
                unsigned int            DP_SEC_COLLISION_ACK : 1;
                unsigned int                                 : 3;
                unsigned int               DP_SEC_AUDIO_MUTE : 1;
                unsigned int        DP_SEC_AUDIO_MUTE_STATUS : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_PACKET_CNTL__SI {
	struct {
		unsigned int          DP_SEC_ASP_CODING_TYPE : 4;
		unsigned int             DP_SEC_ASP_PRIORITY : 1;
		unsigned int                                 : 3;
		unsigned int                  DP_SEC_VERSION : 6;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_PACKET_CNTL__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int          DP_SEC_ASP_CODING_TYPE : 3;
		unsigned int             DP_SEC_ASP_PRIORITY : 1;
		unsigned int                                 : 3;
		unsigned int                  DP_SEC_VERSION : 6;
		unsigned int                                 : 2;
		unsigned int DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_TIMESTAMP__SI__VI {
	struct {
                unsigned int           DP_SEC_TIMESTAMP_MODE : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_STEER_FIFO__SI__VI {
	struct {
                unsigned int             DP_STEER_FIFO_RESET : 1;
                unsigned int                                 : 3;
                unsigned int          DP_STEER_OVERFLOW_FLAG : 1;
                unsigned int           DP_STEER_OVERFLOW_INT : 1;
                unsigned int           DP_STEER_OVERFLOW_ACK : 1;
                unsigned int          DP_STEER_OVERFLOW_MASK : 1;
                unsigned int         DP_TU_OVERFLOW_FLAG__VI : 1;
                unsigned int                                 : 3;
                unsigned int          DP_TU_OVERFLOW_ACK__VI : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int              DP_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int             DP_TEST_DEBUG_INDEX : 8;
                unsigned int          DP_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_VID_INTERRUPT_CNTL__SI__VI {
	struct {
                unsigned int       DP_VID_STREAM_DISABLE_INT : 1;
                unsigned int       DP_VID_STREAM_DISABLE_ACK : 1;
                unsigned int      DP_VID_STREAM_DISABLE_MASK : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_VID_MSA_VBID__SI__VI {
	struct {
                unsigned int             DP_VID_MSA_LOCATION : 12;
                unsigned int                                 : 4;
                unsigned int       DP_VID_MSA_TOP_FIELD_MODE : 1;
                unsigned int                                 : 7;
                unsigned int           DP_VID_VBID_FIELD_POL : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_VID_M__SI__VI {
	struct {
                unsigned int                        DP_VID_M : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_VID_N__SI__VI {
	struct {
                unsigned int                        DP_VID_N : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_VID_STREAM_CNTL__SI__VI {
	struct {
                unsigned int            DP_VID_STREAM_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int         DP_VID_STREAM_DIS_DEFER : 2;
                unsigned int                                 : 6;
                unsigned int            DP_VID_STREAM_STATUS : 1;
                unsigned int                                 : 3;
                unsigned int    DP_VID_STREAM_CHANGE_KEEPOUT : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_VID_TIMING__SI__VI {
	struct {
                unsigned int              DP_VID_TIMING_MODE : 1;
                unsigned int                                 : 7;
                unsigned int               DP_VID_M_N_GEN_EN : 1;
                unsigned int                                 : 15;
                unsigned int                    DP_VID_N_DIV : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVOACLKC_CNTL__SI__VI {
	struct {
                unsigned int         DVOACLKC_FINE_SKEW_CNTL : 3;
                unsigned int                                 : 5;
                unsigned int       DVOACLKC_COARSE_SKEW_CNTL : 5;
                unsigned int                                 : 3;
                unsigned int         DVOACLKC_FINE_ADJUST_EN : 1;
                unsigned int       DVOACLKC_COARSE_ADJUST_EN : 1;
                unsigned int               DVOACLKC_IN_PHASE : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVOACLKC_MVP_CNTL__SI__VI {
	struct {
                unsigned int     DVOACLKC_MVP_FINE_SKEW_CNTL : 3;
                unsigned int                                 : 5;
                unsigned int   DVOACLKC_MVP_COARSE_SKEW_CNTL : 5;
                unsigned int                                 : 3;
                unsigned int     DVOACLKC_MVP_FINE_ADJUST_EN : 1;
                unsigned int   DVOACLKC_MVP_COARSE_ADJUST_EN : 1;
                unsigned int           DVOACLKC_MVP_IN_PHASE : 1;
                unsigned int                                 : 1;
                unsigned int DVOACLKC_MVP_SKEW_PHASE_OVERRIDE : 1;
                unsigned int                                 : 3;
                unsigned int               MVP_CLK_A_SRC_SEL : 2;
                unsigned int                                 : 2;
                unsigned int               MVP_CLK_B_SRC_SEL : 2;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVOACLKD_CNTL__SI__VI {
	struct {
                unsigned int         DVOACLKD_FINE_SKEW_CNTL : 3;
                unsigned int                                 : 5;
                unsigned int       DVOACLKD_COARSE_SKEW_CNTL : 5;
                unsigned int                                 : 3;
                unsigned int         DVOACLKD_FINE_ADJUST_EN : 1;
                unsigned int       DVOACLKD_COARSE_ADJUST_EN : 1;
                unsigned int               DVOACLKD_IN_PHASE : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_CONTROL__SI {
	struct {
		unsigned int                 DVO_RATE_SELECT : 1;
		unsigned int                  DVO_SDRCLK_SEL : 1;
		unsigned int                                 : 6;
		unsigned int             DVO_DUAL_CHANNEL_EN : 1;
		unsigned int                                 : 7;
		unsigned int                  DVO_RESET_FIFO : 1;
		unsigned int                  DVO_SYNC_PHASE : 1;
		unsigned int               DVO_INVERT_DVOCLK : 1;
		unsigned int                                 : 5;
		unsigned int                DVO_COLOR_FORMAT : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                        DVO_CTL3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_CONTROL__VI {
	struct {
		unsigned int                 DVO_RATE_SELECT : 1;
		unsigned int                  DVO_SDRCLK_SEL : 1;
		unsigned int                                 : 2;
		unsigned int               DVO_DVPDATA_WIDTH : 2;
		unsigned int                                 : 2;
		unsigned int             DVO_DUAL_CHANNEL_EN : 1;
		unsigned int                                 : 7;
		unsigned int                  DVO_RESET_FIFO : 1;
		unsigned int                  DVO_SYNC_PHASE : 1;
		unsigned int               DVO_INVERT_DVOCLK : 1;
		unsigned int                                 : 1;
		unsigned int              DVO_HSYNC_POLARITY : 1;
		unsigned int              DVO_VSYNC_POLARITY : 1;
		unsigned int                 DVO_DE_POLARITY : 1;
		unsigned int                                 : 1;
		unsigned int                DVO_COLOR_FORMAT : 2;
		unsigned int                                 : 5;
		unsigned int                        DVO_CTL3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_CRC2_SIG_MASK__SI__VI {
	struct {
                unsigned int               DVO_CRC2_SIG_MASK : 27;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_CRC2_SIG_RESULT__SI__VI {
	struct {
                unsigned int             DVO_CRC2_SIG_RESULT : 27;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_CRC_EN__SI__VI {
	struct {
                unsigned int                                 : 16;
                unsigned int                     DVO_CRC2_EN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_ENABLE__SI {
	struct {
		unsigned int                      DVO_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_ENABLE__VI {
	struct {
		unsigned int                      DVO_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int                 DVO_PIXEL_WIDTH : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_OUTPUT__SI__VI {
	struct {
                unsigned int          DVO_OUTPUT_ENABLE_MODE : 2;
                unsigned int                                 : 6;
                unsigned int                  DVO_CLOCK_MODE : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_SOURCE_SELECT__SI__VI {
	struct {
                unsigned int               DVO_SOURCE_SELECT : 3;
                unsigned int                                 : 13;
                unsigned int           DVO_STEREOSYNC_SELECT : 3;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_STRENGTH_CONTROL__SI {
	struct {
		unsigned int                          DVO_SP : 4;
		unsigned int                          DVO_SN : 4;
		unsigned int                       DVOCLK_SP : 4;
		unsigned int                       DVOCLK_SN : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                   DVO_LSB_VMODE : 1;
		unsigned int                   DVO_MSB_VMODE : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_STRENGTH_CONTROL__VI {
	struct {
		unsigned int                          DVO_SP : 4;
		unsigned int                          DVO_SN : 4;
		unsigned int                       DVOCLK_SP : 4;
		unsigned int                       DVOCLK_SN : 4;
		unsigned int                 DVO_DRVSTRENGTH : 3;
		unsigned int                                 : 1;
		unsigned int              DVOCLK_DRVSTRENGTH : 3;
		unsigned int                                 : 1;
		unsigned int          FLDO_VITNE_DRVSTRENGTH : 3;
		unsigned int                                 : 1;
		unsigned int                   DVO_LSB_VMODE : 1;
		unsigned int                   DVO_MSB_VMODE : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EFUSE_STATUS__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 14;
                unsigned int                                 : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXP0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXP1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXP2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXP3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXP4 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXP5 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXP6 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXP7 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXTERN_TRIG_CNTL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXT_OVERSCAN_LEFT_RIGHT__SI__VI {
	struct {
                unsigned int              EXT_OVERSCAN_RIGHT : 13;
                unsigned int                                 : 3;
                unsigned int               EXT_OVERSCAN_LEFT : 13;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union EXT_OVERSCAN_TOP_BOTTOM__SI__VI {
	struct {
                unsigned int             EXT_OVERSCAN_BOTTOM : 13;
                unsigned int                                 : 3;
                unsigned int                EXT_OVERSCAN_TOP : 13;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_CLIENT_REGION_MASK__SI__VI {
	struct {
                unsigned int                                 : 16;
                unsigned int          FBC_MEMORY_REGION_MASK : 4;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_CNTL__SI__VI {
	struct {
                unsigned int                FBC_GRPH_COMP_EN : 1;
                unsigned int                     FBC_SRC_SEL : 3;
                unsigned int                                 : 12;
                unsigned int              FBC_COHERENCY_MODE : 2;
                unsigned int                                 : 7;
                unsigned int            FBC_SOFT_COMPRESS_EN : 1;
                unsigned int                                 : 5;
                unsigned int                          FBC_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_COMP_CNTL__SI__VI {
	struct {
                unsigned int             FBC_MIN_COMPRESSION : 4;
                unsigned int                                 : 12;
                unsigned int             FBC_DEPTH_MONO08_EN : 1;
                unsigned int             FBC_DEPTH_MONO16_EN : 1;
                unsigned int              FBC_DEPTH_RGB04_EN : 1;
                unsigned int              FBC_DEPTH_RGB08_EN : 1;
                unsigned int              FBC_DEPTH_RGB16_EN : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_COMP_MODE__SI__VI {
	struct {
                unsigned int                      FBC_RLE_EN : 1;
                unsigned int                                 : 7;
                unsigned int                FBC_DPCM4_RGB_EN : 1;
                unsigned int                FBC_DPCM8_RGB_EN : 1;
                unsigned int                FBC_DPCM4_YUV_EN : 1;
                unsigned int                FBC_DPCM8_YUV_EN : 1;
                unsigned int                                 : 4;
                unsigned int                      FBC_IND_EN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_CSM_REGION_OFFSET_01__SI__VI {
	struct {
                unsigned int         FBC_CSM_REGION_OFFSET_0 : 10;
                unsigned int                                 : 6;
                unsigned int         FBC_CSM_REGION_OFFSET_1 : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_CSM_REGION_OFFSET_23__SI__VI {
	struct {
                unsigned int         FBC_CSM_REGION_OFFSET_2 : 10;
                unsigned int                                 : 6;
                unsigned int         FBC_CSM_REGION_OFFSET_3 : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_DEBUG0__SI__VI {
	struct {
                unsigned int                   FBC_PERF_MUX0 : 8;
                unsigned int                   FBC_PERF_MUX1 : 8;
                unsigned int               FBC_COMP_WAKE_DIS : 1;
                unsigned int                      FBC_DEBUG0 : 7;
                unsigned int                   FBC_DEBUG_MUX : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_DEBUG1__SI__VI {
	struct {
                unsigned int                      FBC_DEBUG1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_DEBUG2__SI__VI {
	struct {
                unsigned int                      FBC_DEBUG2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_DEBUG_COMP__SI__VI {
	struct {
                unsigned int                   FBC_COMP_SWAP : 2;
                unsigned int                                 : 1;
                unsigned int                  FBC_COMP_RSIZE : 1;
                unsigned int        FBC_COMP_BUSY_HYSTERESIS : 4;
                unsigned int               FBC_COMP_CLK_CNTL : 2;
                unsigned int FBC_COMP_PRIVILEGED_ACCESS_ENABLE__VI : 1;
                unsigned int FBC_COMP_ADDRESS_TRANSLATION_ENABLE__VI : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_DEBUG_CSR_RDATA__SI__VI {
	struct {
                unsigned int             FBC_DEBUG_CSR_RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_DEBUG_CSR_WDATA__SI__VI {
	struct {
                unsigned int             FBC_DEBUG_CSR_WDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_DEBUG_CSR__SI__VI {
	struct {
                unsigned int              FBC_DEBUG_CSR_ADDR : 10;
                unsigned int                                 : 6;
                unsigned int       FBC_DEBUG_CSR_WR_DATA__VI : 1;
                unsigned int       FBC_DEBUG_CSR_RD_DATA__VI : 1;
                unsigned int                                 : 13;
                unsigned int                FBC_DEBUG_CSR_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IDLE_FORCE_CLEAR_MASK__SI__VI {
	struct {
                unsigned int       FBC_IDLE_FORCE_CLEAR_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IDLE_MASK__SI__VI {
	struct {
                unsigned int                   FBC_IDLE_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT0__SI__VI {
	struct {
                unsigned int                    FBC_IND_LUT0 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT10__SI__VI {
	struct {
                unsigned int                   FBC_IND_LUT10 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT11__SI__VI {
	struct {
                unsigned int                   FBC_IND_LUT11 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT12__SI__VI {
	struct {
                unsigned int                   FBC_IND_LUT12 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT13__SI__VI {
	struct {
                unsigned int                   FBC_IND_LUT13 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT14__SI__VI {
	struct {
                unsigned int                   FBC_IND_LUT14 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT15__SI__VI {
	struct {
                unsigned int                   FBC_IND_LUT15 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT1__SI__VI {
	struct {
                unsigned int                    FBC_IND_LUT1 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT2__SI__VI {
	struct {
                unsigned int                    FBC_IND_LUT2 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT3__SI__VI {
	struct {
                unsigned int                    FBC_IND_LUT3 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT4__SI__VI {
	struct {
                unsigned int                    FBC_IND_LUT4 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT5__SI__VI {
	struct {
                unsigned int                    FBC_IND_LUT5 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT6__SI__VI {
	struct {
                unsigned int                    FBC_IND_LUT6 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT7__SI__VI {
	struct {
                unsigned int                    FBC_IND_LUT7 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT8__SI__VI {
	struct {
                unsigned int                    FBC_IND_LUT8 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_IND_LUT9__SI__VI {
	struct {
                unsigned int                    FBC_IND_LUT9 : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_MISC__SI__VI {
	struct {
                unsigned int            FBC_DECOMPRESS_ERROR : 2;
                unsigned int               FBC_STOP_ON_ERROR : 1;
                unsigned int         FBC_INVALIDATE_ON_ERROR : 1;
                unsigned int                 FBC_ERROR_PIXEL : 4;
                unsigned int                    FBC_DIVIDE_X : 2;
                unsigned int                    FBC_DIVIDE_Y : 1;
                unsigned int             FBC_RSM_WRITE_VALUE : 1;
                unsigned int FBC_RSM_UNCOMP_DATA_IMMEDIATELY : 1;
                unsigned int                                 : 3;
                unsigned int      FBC_DECOMPRESS_ERROR_CLEAR : 1;
                unsigned int                                 : 3;
                unsigned int         FBC_RESET_AT_ENABLE__VI : 1;
                unsigned int        FBC_RESET_AT_DISABLE__VI : 1;
                unsigned int                                 : 2;
                unsigned int       FBC_SLOW_REQ_INTERVAL__VI : 5;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_START_STOP_DELAY__SI__VI {
	struct {
                unsigned int          FBC_DECOMP_START_DELAY : 5;
                unsigned int                                 : 2;
                unsigned int           FBC_DECOMP_STOP_DELAY : 1;
                unsigned int            FBC_COMP_START_DELAY : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int             FBC_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int            FBC_TEST_DEBUG_INDEX : 8;
                unsigned int         FBC_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FIRMWARE_FLAGS__CI__VI {
	struct {
                unsigned int              INTERRUPTS_ENABLED : 1;
                unsigned int                                 : 23;
                unsigned int                      TEST_COUNT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_BIT_DEPTH_CONTROL__SI {
	struct {
		unsigned int                 FMT_TRUNCATE_EN : 1;
		unsigned int                                 : 3;
		unsigned int              FMT_TRUNCATE_DEPTH : 1;
		unsigned int                                 : 3;
		unsigned int           FMT_SPATIAL_DITHER_EN : 1;
		unsigned int         FMT_SPATIAL_DITHER_MODE : 2;
		unsigned int                                 : 1;
		unsigned int        FMT_SPATIAL_DITHER_DEPTH : 1;
		unsigned int         FMT_FRAME_RANDOM_ENABLE : 1;
		unsigned int           FMT_RGB_RANDOM_ENABLE : 1;
		unsigned int      FMT_HIGHPASS_RANDOM_ENABLE : 1;
		unsigned int          FMT_TEMPORAL_DITHER_EN : 1;
		unsigned int                                 : 3;
		unsigned int       FMT_TEMPORAL_DITHER_DEPTH : 1;
		unsigned int      FMT_TEMPORAL_DITHER_OFFSET : 2;
		unsigned int                                 : 1;
		unsigned int              FMT_TEMPORAL_LEVEL : 1;
		unsigned int       FMT_TEMPORAL_DITHER_RESET : 1;
		unsigned int                   FMT_25FRC_SEL : 2;
		unsigned int                   FMT_50FRC_SEL : 2;
		unsigned int                   FMT_75FRC_SEL : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_BIT_DEPTH_CONTROL__VI {
	struct {
		unsigned int                 FMT_TRUNCATE_EN : 1;
		unsigned int               FMT_TRUNCATE_MODE : 1;
		unsigned int                                 : 2;
		unsigned int              FMT_TRUNCATE_DEPTH : 2;
		unsigned int                                 : 2;
		unsigned int           FMT_SPATIAL_DITHER_EN : 1;
		unsigned int         FMT_SPATIAL_DITHER_MODE : 2;
		unsigned int        FMT_SPATIAL_DITHER_DEPTH : 2;
		unsigned int         FMT_FRAME_RANDOM_ENABLE : 1;
		unsigned int           FMT_RGB_RANDOM_ENABLE : 1;
		unsigned int      FMT_HIGHPASS_RANDOM_ENABLE : 1;
		unsigned int          FMT_TEMPORAL_DITHER_EN : 1;
		unsigned int       FMT_TEMPORAL_DITHER_DEPTH : 2;
		unsigned int                                 : 2;
		unsigned int      FMT_TEMPORAL_DITHER_OFFSET : 2;
		unsigned int                                 : 1;
		unsigned int              FMT_TEMPORAL_LEVEL : 1;
		unsigned int       FMT_TEMPORAL_DITHER_RESET : 1;
		unsigned int                   FMT_25FRC_SEL : 2;
		unsigned int                   FMT_50FRC_SEL : 2;
		unsigned int                   FMT_75FRC_SEL : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CLAMP_CNTL__SI__VI {
	struct {
                unsigned int               FMT_CLAMP_DATA_EN : 1;
                unsigned int                                 : 15;
                unsigned int          FMT_CLAMP_COLOR_FORMAT : 3;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CONTROL__SI__VI {
	struct {
                unsigned int     FMT_STEREOSYNC_OVERRIDE__VI : 1;
                unsigned int                                 : 3;
                unsigned int      FMT_STEREOSYNC_OVR_POL__VI : 1;
                unsigned int                                 : 3;
                unsigned int FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__VI : 4;
                unsigned int FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__VI : 2;
                unsigned int                                 : 2;
                unsigned int              FMT_PIXEL_ENCODING : 1;
                unsigned int        FMT_SUBSAMPLING_MODE__VI : 1;
                unsigned int       FMT_SUBSAMPLING_ORDER__VI : 1;
                unsigned int                                 : 5;
                unsigned int              FMT_SRC_SELECT__VI : 3;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CRC_CNTL__SI {
	struct {
		unsigned int                      FMT_CRC_EN : 1;
		unsigned int                                 : 3;
		unsigned int                 FMT_CRC_CONT_EN : 1;
		unsigned int                                 : 3;
		unsigned int             FMT_CRC_ONLY_BLANKb : 1;
		unsigned int                                 : 3;
		unsigned int          FMT_CRC_INTERLACE_MODE : 2;
		unsigned int                                 : 2;
		unsigned int FMT_CRC_USE_NEW_AND_REPEATED_PIXELS : 1;
		unsigned int                                 : 3;
		unsigned int     FMT_CRC_EVEN_ODD_PIX_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int     FMT_CRC_EVEN_ODD_PIX_SELECT : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CRC_CNTL__VI {
	struct {
		unsigned int                      FMT_CRC_EN : 1;
		unsigned int              FMT_DTMTEST_CRC_EN : 1;
		unsigned int                                 : 2;
		unsigned int                 FMT_CRC_CONT_EN : 1;
		unsigned int                                 : 3;
		unsigned int             FMT_CRC_ONLY_BLANKB : 1;
		unsigned int                                 : 3;
		unsigned int          FMT_CRC_INTERLACE_MODE : 2;
		unsigned int                                 : 2;
		unsigned int FMT_CRC_USE_NEW_AND_REPEATED_PIXELS : 1;
		unsigned int                                 : 3;
		unsigned int     FMT_CRC_EVEN_ODD_PIX_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int     FMT_CRC_EVEN_ODD_PIX_SELECT : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CRC_SIG_BLUE_CONTROL_MASK__SI__VI {
	struct {
                unsigned int           FMT_CRC_SIG_BLUE_MASK : 16;
                unsigned int        FMT_CRC_SIG_CONTROL_MASK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CRC_SIG_BLUE_CONTROL__SI__VI {
	struct {
                unsigned int                FMT_CRC_SIG_BLUE : 16;
                unsigned int             FMT_CRC_SIG_CONTROL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CRC_SIG_RED_GREEN_MASK__SI__VI {
	struct {
                unsigned int            FMT_CRC_SIG_RED_MASK : 16;
                unsigned int          FMT_CRC_SIG_GREEN_MASK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CRC_SIG_RED_GREEN__SI__VI {
	struct {
                unsigned int                 FMT_CRC_SIG_RED : 16;
                unsigned int               FMT_CRC_SIG_GREEN : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_DEBUG_CNTL__SI__VI {
	struct {
                unsigned int          FMT_DEBUG_COLOR_SELECT : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_DITHER_RAND_B_SEED__SI__VI {
	struct {
                unsigned int                 FMT_RAND_B_SEED : 8;
                unsigned int                                 : 8;
                unsigned int             FMT_OFFSET_B_CB__VI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_DITHER_RAND_G_SEED__SI__VI {
	struct {
                unsigned int                 FMT_RAND_G_SEED : 8;
                unsigned int                                 : 8;
                unsigned int              FMT_OFFSET_G_Y__VI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_DITHER_RAND_R_SEED__SI__VI {
	struct {
                unsigned int                 FMT_RAND_R_SEED : 8;
                unsigned int                                 : 8;
                unsigned int             FMT_OFFSET_R_CR__VI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_DYNAMIC_EXP_CNTL__SI__VI {
	struct {
                unsigned int              FMT_DYNAMIC_EXP_EN : 1;
                unsigned int                                 : 3;
                unsigned int            FMT_DYNAMIC_EXP_MODE : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_FORCE_DATA_0_1__SI__VI {
	struct {
                unsigned int                 FMT_FORCE_DATA0 : 16;
                unsigned int                 FMT_FORCE_DATA1 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_FORCE_DATA_2_3__SI__VI {
	struct {
                unsigned int                 FMT_FORCE_DATA2 : 16;
                unsigned int                 FMT_FORCE_DATA3 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_FORCE_OUTPUT_CNTL__SI {
	struct {
		unsigned int               FMT_FORCE_DATA_EN : 1;
		unsigned int                                 : 7;
		unsigned int        FMT_FORCE_DATA_SEL_COLOR : 3;
		unsigned int                                 : 1;
		unsigned int         FMT_FORCE_DATA_SEL_SLOT : 4;
		unsigned int   FMT_FORCE_DATA_ON_BLANKb_ONLY : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_FORCE_OUTPUT_CNTL__VI {
	struct {
		unsigned int               FMT_FORCE_DATA_EN : 1;
		unsigned int                                 : 7;
		unsigned int        FMT_FORCE_DATA_SEL_COLOR : 3;
		unsigned int                                 : 1;
		unsigned int         FMT_FORCE_DATA_SEL_SLOT : 4;
		unsigned int   FMT_FORCE_DATA_ON_BLANKB_ONLY : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI__VI {
	struct {
                unsigned int FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT : 1;
                unsigned int                                 : 3;
                unsigned int FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0 : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI__VI {
	struct {
                unsigned int FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI__VI {
	struct {
                unsigned int FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_END_0__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                        ADDR_END : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_END_1__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                        ADDR_END : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_END_2__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                        ADDR_END : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_END_3__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                        ADDR_END : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_END_4__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                        ADDR_END : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_END_5__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                        ADDR_END : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_END_6__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                        ADDR_END : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_END_7__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                        ADDR_END : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_START_0__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                            MODE : 1;
                unsigned int                      ADDR_START : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_START_1__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                            MODE : 1;
                unsigned int                      ADDR_START : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_START_2__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                            MODE : 1;
                unsigned int                      ADDR_START : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_START_3__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                            MODE : 1;
                unsigned int                      ADDR_START : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_START_4__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                            MODE : 1;
                unsigned int                      ADDR_START : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_START_5__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                            MODE : 1;
                unsigned int                      ADDR_START : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_START_6__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                            MODE : 1;
                unsigned int                      ADDR_START : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_ADDR_START_7__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                            MODE : 1;
                unsigned int                      ADDR_START : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_CNTL__CI {
	struct {
		unsigned int                     CP_RB0_WPTR : 1;
		unsigned int                     CP_RB1_WPTR : 1;
		unsigned int                     CP_RB2_WPTR : 1;
		unsigned int                 UVD_RBC_RB_WPTR : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int               CP_DMA_ME_COMMAND : 1;
		unsigned int              CP_DMA_PFP_COMMAND : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 VCE_OUT_RB_WPTR : 1;
		unsigned int                    VCE_RB_WPTR2 : 1;
		unsigned int                     VCE_RB_WPTR : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                         DISPLAY : 1;
		unsigned int                                 : 14;
		unsigned int                     DISABLE_ALL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_CNTL__VI {
	struct {
		unsigned int                     CP_RB0_WPTR : 1;
		unsigned int                     CP_RB1_WPTR : 1;
		unsigned int                     CP_RB2_WPTR : 1;
		unsigned int                 UVD_RBC_RB_WPTR : 1;
		unsigned int               SDMA0_GFX_RB_WPTR : 1;
		unsigned int               SDMA1_GFX_RB_WPTR : 1;
		unsigned int               CP_DMA_ME_COMMAND : 1;
		unsigned int              CP_DMA_PFP_COMMAND : 1;
		unsigned int                SAM_SAB_RBI_WPTR : 1;
		unsigned int                SAM_SAB_RBO_WPTR : 1;
		unsigned int                 VCE_OUT_RB_WPTR : 1;
		unsigned int                    VCE_RB_WPTR2 : 1;
		unsigned int                     VCE_RB_WPTR : 1;
		unsigned int                   HOST_DOORBELL : 1;
		unsigned int               SELFRING_DOORBELL : 1;
		unsigned int              CP_DMA_PIO_COMMAND : 1;
		unsigned int                         DISPLAY : 1;
		unsigned int               SDMA2_GFX_RB_WPTR : 1;
		unsigned int               SDMA3_GFX_RB_WPTR : 1;
		unsigned int                                 : 11;
		unsigned int               IGNORE_MC_DISABLE : 1;
		unsigned int                     DISABLE_ALL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_FLUSH_REQ__CI__VI {
	struct {
                unsigned int                       FLUSH_REQ : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_ADDR_CONFIG {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                        NUM_GPUS : 3;
		unsigned int                                 : 1;
		unsigned int             MULTI_GPU_TILE_SIZE : 2;
		unsigned int                                 : 2;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_BACKEND_MAP {
	struct {
		unsigned int                     BACKEND_MAP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_EDC_MODE {
	struct {
		unsigned int                                 : 16;
		unsigned int                FORCE_SEC_ON_DED : 1;
		unsigned int                                 : 3;
		unsigned int                        DED_MODE : 2;
		unsigned int                                 : 7;
		unsigned int                        PROP_FED : 1;
		unsigned int                                 : 1;
		unsigned int                          BYPASS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_GPU_ID {
	struct {
		unsigned int                          GPU_ID : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE0__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE10__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE11__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE12__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE13__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE14__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE15__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE1__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE2__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE3__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE4__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE5__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE6__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE7__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE8__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_MACROTILE_MODE9__CI__VI {
	struct {
                unsigned int                      BANK_WIDTH : 2;
                unsigned int                     BANK_HEIGHT : 2;
                unsigned int               MACRO_TILE_ASPECT : 2;
                unsigned int                       NUM_BANKS : 2;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE0 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE1 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE10 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE11 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE12 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE13 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE14 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE15 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE16 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE17 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE18 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE19 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE2 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE20 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE21 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE22 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE23 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE24 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE25 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE26 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE27 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE28 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE29 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE3 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE30 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE31 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE4 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE5 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE6 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE7 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE8 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GB_TILE_MODE9 {
	struct {
                unsigned int             MICRO_TILE_MODE__SI : 2;
                unsigned int                      ARRAY_MODE : 4;
                unsigned int                     PIPE_CONFIG : 5;
                unsigned int                      TILE_SPLIT : 3;
                unsigned int                  BANK_WIDTH__SI : 2;
                unsigned int                 BANK_HEIGHT__SI : 2;
                unsigned int           MACRO_TILE_ASPECT__SI : 2;
                unsigned int                   NUM_BANKS__SI : 2;
                unsigned int     MICRO_TILE_MODE_NEW__CI__VI : 3;
                unsigned int            SAMPLE_SPLIT__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GCK_PLL_TEST_CNTL__CI {
	struct {
		unsigned int                     TST_SRC_SEL : 4;
		unsigned int                     TST_REF_SEL : 4;
		unsigned int                  REF_TEST_COUNT : 7;
		unsigned int                       TST_RESET : 1;
		unsigned int                TST_CLK_SEL_MODE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GCK_PLL_TEST_CNTL__VI {
	struct {
		unsigned int                     TST_SRC_SEL : 5;
		unsigned int                     TST_REF_SEL : 5;
		unsigned int                  REF_TEST_COUNT : 7;
		unsigned int                       TST_RESET : 1;
		unsigned int                TST_CLK_SEL_MODE : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GCK_SMC_IND_DATA__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GCK_SMC_IND_INDEX__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_USER_PRIM_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 16;
                unsigned int                     INACTIVE_IA : 2;
                unsigned int                                 : 6;
                unsigned int                 INACTIVE_VGT_PA : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_USER_RB_BACKEND_DISABLE {
	struct {
		unsigned int                                 : 16;
		unsigned int                 BACKEND_DISABLE : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_USER_RB_REDUNDANCY__CI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int                      FAILED_RB0 : 4;
                unsigned int                  EN_REDUNDANCY0 : 1;
                unsigned int                                 : 3;
                unsigned int                      FAILED_RB1 : 4;
                unsigned int                  EN_REDUNDANCY1 : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_USER_SHADER_ARRAY_CONFIG__SI__CI {
	struct {
                unsigned int                                 : 1;
                unsigned int                   DPFP_RATE__CI : 2;
                unsigned int         SQC_BALANCE_DISABLE__CI : 1;
                unsigned int                    HALF_LDS__CI : 1;
                unsigned int                                 : 11;
                unsigned int                    INACTIVE_CUS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_USER_SHADER_ARRAY_CONFIG__VI {
	struct {
		unsigned int                                 : 16;
		unsigned int                    INACTIVE_CUS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_USER_SYS_RB_BACKEND_DISABLE {
	struct {
		unsigned int                                 : 16;
		unsigned int                 BACKEND_DISABLE : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_BASE {
	struct {
		unsigned int                            BASE : 16;
		unsigned int                          UNUSED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_CNTL {
	struct {
                unsigned int                            AINC : 6;
                unsigned int                                 : 2;
                unsigned int                           DMODE : 2;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_COMPLETE {
	struct {
		unsigned int                        COMPLETE : 1;
		unsigned int                          UNUSED : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_DST {
	struct {
		unsigned int                             DST : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_OFFSET0 {
	struct {
		unsigned int                         OFFSET0 : 8;
		unsigned int                          UNUSED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_OFFSET1 {
	struct {
		unsigned int                         OFFSET1 : 8;
		unsigned int                          UNUSED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_OP {
	struct {
		unsigned int                              OP : 8;
		unsigned int                          UNUSED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_READ0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_READ0_U {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_READ1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_READ1_U {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_SIZE {
	struct {
		unsigned int                            SIZE : 16;
		unsigned int                          UNUSED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_SRC0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_SRC0_U {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_SRC1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ATOM_SRC1_U {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_CNTL_STATUS {
	struct {
                unsigned int                        GDS_BUSY : 1;
                unsigned int                  GRBM_WBUF_BUSY : 1;
                unsigned int                    ORD_APP_BUSY : 1;
                unsigned int                DS_BANK_CONFLICT : 1;
                unsigned int                DS_ADDR_CONFLICT : 1;
                unsigned int                     DS_WR_CLAMP : 1;
                unsigned int                     DS_RD_CLAMP : 1;
                unsigned int              GRBM_RBUF_BUSY__VI : 1;
                unsigned int                     DS_BUSY__VI : 1;
                unsigned int                    GWS_BUSY__VI : 1;
                unsigned int               ORD_FIFO_BUSY__VI : 1;
                unsigned int                CREDIT_BUSY0__VI : 1;
                unsigned int                CREDIT_BUSY1__VI : 1;
                unsigned int                CREDIT_BUSY2__VI : 1;
                unsigned int                CREDIT_BUSY3__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_COMPUTE_MAX_WAVE_ID__CI__VI {
	struct {
                unsigned int                     MAX_WAVE_ID : 12;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_CONFIG {
	struct {
		unsigned int                                 : 1;
		unsigned int               SH0_GPR_PHASE_SEL : 2;
		unsigned int               SH1_GPR_PHASE_SEL : 2;
		unsigned int               SH2_GPR_PHASE_SEL : 2;
		unsigned int               SH3_GPR_PHASE_SEL : 2;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_CNTL {
	struct {
		unsigned int                  GDS_DEBUG_INDX : 5;
		unsigned int                          UNUSED : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG0__CI__VI {
	struct {
                unsigned int                          spare1 : 6;
                unsigned int                write_buff_valid : 1;
                unsigned int                wr_pixel_nxt_ptr : 5;
                unsigned int                  last_pixel_ptr : 1;
                unsigned int                          cstate : 4;
                unsigned int                      buff_write : 1;
                unsigned int                   flush_request : 1;
                unsigned int           wr_buffer_wr_complete : 1;
                unsigned int                 wbuf_fifo_empty : 1;
                unsigned int                  wbuf_fifo_full : 1;
                unsigned int                           spare : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG0__SI {
	struct {
		unsigned int                          spare1 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                           spare : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG1__CI__VI {
	struct {
                unsigned int                         tag_hit : 1;
                unsigned int                        tag_miss : 1;
                unsigned int                      pixel_addr : 15;
                unsigned int                       pixel_vld : 1;
                unsigned int                      data_ready : 1;
                unsigned int                   awaiting_data : 1;
                unsigned int                  addr_fifo_full : 1;
                unsigned int                 addr_fifo_empty : 1;
                unsigned int                   buffer_loaded : 1;
                unsigned int                  buffer_invalid : 1;
                unsigned int                           spare : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG1__SI {
	struct {
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                           spare : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG2__CI__VI {
	struct {
                unsigned int                         ds_full : 1;
                unsigned int                 ds_credit_avail : 1;
                unsigned int                    ord_idx_free : 1;
                unsigned int                       cmd_write : 1;
                unsigned int                         app_sel : 4;
                unsigned int                             req : 15;
                unsigned int                           spare : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG2__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 15;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                           spare : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG3__CI__VI {
	struct {
                unsigned int                   pipe_num_busy : 11;
                unsigned int                  pipe0_busy_num : 4;
                unsigned int                           spare : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG3__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 9;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
		unsigned int                           spare : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG4__CI__VI {
	struct {
                unsigned int                        gws_busy : 1;
                unsigned int                         gws_req : 1;
                unsigned int                   gws_out_stall : 1;
                unsigned int                        cur_reso : 6;
                unsigned int             cur_reso_head_valid : 1;
                unsigned int             cur_reso_head_dirty : 1;
                unsigned int              cur_reso_head_flag : 1;
                unsigned int                    cur_reso_fed : 1;
                unsigned int                cur_reso_barrier : 1;
                unsigned int                   cur_reso_flag : 1;
                unsigned int                cur_reso_cnt_gt0 : 1;
                unsigned int                  credit_cnt_gt0 : 1;
                unsigned int                       cmd_write : 1;
                unsigned int                grbm_gws_reso_wr : 1;
                unsigned int                grbm_gws_reso_rd : 1;
                unsigned int                   ram_read_busy : 1;
                unsigned int                    gws_bulkfree : 1;
                unsigned int                      ram_gws_re : 1;
                unsigned int                      ram_gws_we : 1;
                unsigned int                           spare : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG4__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                           spare : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG5__CI__VI {
	struct {
                unsigned int                       write_dis : 1;
                unsigned int                       dec_error : 1;
                unsigned int                alloc_opco_error : 1;
                unsigned int              dealloc_opco_error : 1;
                unsigned int                 wrap_opco_error : 1;
                unsigned int                           spare : 3;
                unsigned int                error_ds_address : 14;
                unsigned int                          spare1 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG5__SI {
	struct {
		unsigned int                                 : 3;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                           spare : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG6__CI__VI {
	struct {
                unsigned int                         oa_busy : 1;
                unsigned int                counters_enabled : 4;
                unsigned int                   counters_busy : 16;
                unsigned int                           spare : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DEBUG_REG6__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                           spare : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ENHANCE2__CI__VI {
	struct {
                unsigned int                            MISC : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ENHANCE__CI__VI {
	struct {
                unsigned int                            MISC : 16;
                unsigned int                  AUTO_INC_INDEX : 1;
                unsigned int                    CGPG_RESTORE : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_ENHANCE__SI {
	struct {
		unsigned int                            MISC : 16;
		unsigned int                          UNUSED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GRBM_SECDED_CNT__CI {
	struct {
		unsigned int                             DED : 16;
		unsigned int                             SEC : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GRBM_SECDED_CNT__SI {
	struct {
		unsigned int                             SEC : 16;
		unsigned int                             DED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_RESET0__CI__VI {
	struct {
                unsigned int                 RESOURCE0_RESET : 1;
                unsigned int                 RESOURCE1_RESET : 1;
                unsigned int                 RESOURCE2_RESET : 1;
                unsigned int                 RESOURCE3_RESET : 1;
                unsigned int                 RESOURCE4_RESET : 1;
                unsigned int                 RESOURCE5_RESET : 1;
                unsigned int                 RESOURCE6_RESET : 1;
                unsigned int                 RESOURCE7_RESET : 1;
                unsigned int                 RESOURCE8_RESET : 1;
                unsigned int                 RESOURCE9_RESET : 1;
                unsigned int                RESOURCE10_RESET : 1;
                unsigned int                RESOURCE11_RESET : 1;
                unsigned int                RESOURCE12_RESET : 1;
                unsigned int                RESOURCE13_RESET : 1;
                unsigned int                RESOURCE14_RESET : 1;
                unsigned int                RESOURCE15_RESET : 1;
                unsigned int                RESOURCE16_RESET : 1;
                unsigned int                RESOURCE17_RESET : 1;
                unsigned int                RESOURCE18_RESET : 1;
                unsigned int                RESOURCE19_RESET : 1;
                unsigned int                RESOURCE20_RESET : 1;
                unsigned int                RESOURCE21_RESET : 1;
                unsigned int                RESOURCE22_RESET : 1;
                unsigned int                RESOURCE23_RESET : 1;
                unsigned int                RESOURCE24_RESET : 1;
                unsigned int                RESOURCE25_RESET : 1;
                unsigned int                RESOURCE26_RESET : 1;
                unsigned int                RESOURCE27_RESET : 1;
                unsigned int                RESOURCE28_RESET : 1;
                unsigned int                RESOURCE29_RESET : 1;
                unsigned int                RESOURCE30_RESET : 1;
                unsigned int                RESOURCE31_RESET : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_RESET1__CI__VI {
	struct {
                unsigned int                RESOURCE32_RESET : 1;
                unsigned int                RESOURCE33_RESET : 1;
                unsigned int                RESOURCE34_RESET : 1;
                unsigned int                RESOURCE35_RESET : 1;
                unsigned int                RESOURCE36_RESET : 1;
                unsigned int                RESOURCE37_RESET : 1;
                unsigned int                RESOURCE38_RESET : 1;
                unsigned int                RESOURCE39_RESET : 1;
                unsigned int                RESOURCE40_RESET : 1;
                unsigned int                RESOURCE41_RESET : 1;
                unsigned int                RESOURCE42_RESET : 1;
                unsigned int                RESOURCE43_RESET : 1;
                unsigned int                RESOURCE44_RESET : 1;
                unsigned int                RESOURCE45_RESET : 1;
                unsigned int                RESOURCE46_RESET : 1;
                unsigned int                RESOURCE47_RESET : 1;
                unsigned int                RESOURCE48_RESET : 1;
                unsigned int                RESOURCE49_RESET : 1;
                unsigned int                RESOURCE50_RESET : 1;
                unsigned int                RESOURCE51_RESET : 1;
                unsigned int                RESOURCE52_RESET : 1;
                unsigned int                RESOURCE53_RESET : 1;
                unsigned int                RESOURCE54_RESET : 1;
                unsigned int                RESOURCE55_RESET : 1;
                unsigned int                RESOURCE56_RESET : 1;
                unsigned int                RESOURCE57_RESET : 1;
                unsigned int                RESOURCE58_RESET : 1;
                unsigned int                RESOURCE59_RESET : 1;
                unsigned int                RESOURCE60_RESET : 1;
                unsigned int                RESOURCE61_RESET : 1;
                unsigned int                RESOURCE62_RESET : 1;
                unsigned int                RESOURCE63_RESET : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_RESOURCE_CNTL {
	struct {
		unsigned int                           INDEX : 6;
		unsigned int                          UNUSED : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_RESOURCE_CNT__CI__VI {
	struct {
                unsigned int                    RESOURCE_CNT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_RESOURCE_RESET__CI__VI {
	struct {
                unsigned int                           RESET : 1;
                unsigned int                                 : 7;
                unsigned int                     RESOURCE_ID : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_RESOURCE__CI {
	struct {
		unsigned int                            FLAG : 1;
		unsigned int                         COUNTER : 12;
		unsigned int                            TYPE : 1;
		unsigned int                             DED : 1;
		unsigned int                     RELEASE_ALL : 1;
		unsigned int                      HEAD_QUEUE : 11;
		unsigned int                      HEAD_VALID : 1;
		unsigned int                       HEAD_FLAG : 1;
		unsigned int                         UNUSED1 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_RESOURCE__VI {
	struct {
		unsigned int                            FLAG : 1;
		unsigned int                         COUNTER : 12;
		unsigned int                            TYPE : 1;
		unsigned int                             DED : 1;
		unsigned int                     RELEASE_ALL : 1;
		unsigned int                      HEAD_QUEUE : 12;
		unsigned int                      HEAD_VALID : 1;
		unsigned int                       HEAD_FLAG : 1;
		unsigned int                         UNUSED1 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_RESOURCE__SI {
	struct {
		unsigned int                            FLAG : 1;
		unsigned int                         COUNTER : 12;
		unsigned int                            TYPE : 1;
		unsigned int                             DED : 1;
		unsigned int                          UNUSED : 1;
		unsigned int                      HEAD_QUEUE : 11;
		unsigned int                      HEAD_VALID : 1;
		unsigned int                       HEAD_FLAG : 1;
		unsigned int                         UNUSED1 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID0__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID10__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID11__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID12__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID13__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID14__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID15__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID1__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID2__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID3__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID4__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID5__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID6__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID7__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID8__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GWS_VMID9__CI__VI {
	struct {
                unsigned int                            BASE : 6;
                unsigned int                                 : 10;
                unsigned int                            SIZE : 7;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_ADDRESS__CI {
	struct {
		unsigned int                      DS_ADDRESS : 16;
		unsigned int                    CRAWLER_TYPE : 4;
		unsigned int                         CRAWLER : 4;
		unsigned int                          UNUSED : 6;
		unsigned int                        NO_ALLOC : 1;
		unsigned int                          ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_ADDRESS__VI {
	struct {
		unsigned int                      DS_ADDRESS : 16;
		unsigned int                         CRAWLER : 4;
		unsigned int                    CRAWLER_TYPE : 2;
		unsigned int                          UNUSED : 8;
		unsigned int                        NO_ALLOC : 1;
		unsigned int                          ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_CGPG_RESTORE__CI__VI {
	struct {
                unsigned int                            VMID : 8;
                unsigned int                            MEID : 4;
                unsigned int                          PIPEID : 4;
                unsigned int                     QUEUEID__VI : 4;
                unsigned int                      UNUSED__VI : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_CNTL__CI__VI {
	struct {
                unsigned int                           INDEX : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_COUNTER__CI__VI {
	struct {
                unsigned int                 SPACE_AVAILABLE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_DED__CI {
	struct {
		unsigned int             ME0_GFXHP3D_PIX_DED : 1;
		unsigned int             ME0_GFXHP3D_VTX_DED : 1;
		unsigned int                      ME0_CS_DED : 1;
		unsigned int                         UNUSED0 : 1;
		unsigned int                   ME1_PIPE0_DED : 1;
		unsigned int                   ME1_PIPE1_DED : 1;
		unsigned int                   ME1_PIPE2_DED : 1;
		unsigned int                   ME1_PIPE3_DED : 1;
		unsigned int                   ME2_PIPE0_DED : 1;
		unsigned int                   ME2_PIPE1_DED : 1;
		unsigned int                   ME2_PIPE2_DED : 1;
		unsigned int                   ME2_PIPE3_DED : 1;
		unsigned int                         UNUSED1 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_DED__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                          UNUSED : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_INCDEC__CI__VI {
	struct {
                unsigned int                           VALUE : 31;
                unsigned int                          INCDEC : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_RESET_MASK__CI__VI {
	struct {
                unsigned int           ME0_GFXHP3D_PIX_RESET : 1;
                unsigned int           ME0_GFXHP3D_VTX_RESET : 1;
                unsigned int                    ME0_CS_RESET : 1;
                unsigned int                                 : 1;
                unsigned int                 ME1_PIPE0_RESET : 1;
                unsigned int                 ME1_PIPE1_RESET : 1;
                unsigned int                 ME1_PIPE2_RESET : 1;
                unsigned int                 ME1_PIPE3_RESET : 1;
                unsigned int                 ME2_PIPE0_RESET : 1;
                unsigned int                 ME2_PIPE1_RESET : 1;
                unsigned int                 ME2_PIPE2_RESET : 1;
                unsigned int                 ME2_PIPE3_RESET : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_RESET__CI__VI {
	struct {
                unsigned int                           RESET : 1;
                unsigned int                                 : 7;
                unsigned int                         PIPE_ID : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_RING_SIZE__CI__VI {
	struct {
                unsigned int                       RING_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID0__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID10__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID11__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID12__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID13__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID14__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID15__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID1__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID2__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID3__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID4__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID5__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID6__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID7__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID8__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_OA_VMID9__CI__VI {
	struct {
                unsigned int                            MASK : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER0_SELECT {
	struct {
                unsigned int              PERFCOUNTER_SELECT : 10;
                unsigned int     PERFCOUNTER_SELECT1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int             PERFCOUNTER_SELECT2 : 10;
                unsigned int             PERFCOUNTER_SELECT3 : 10;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER1_SELECT {
	struct {
                unsigned int              PERFCOUNTER_SELECT : 10;
                unsigned int     PERFCOUNTER_SELECT1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER2_SELECT {
	struct {
                unsigned int              PERFCOUNTER_SELECT : 10;
                unsigned int     PERFCOUNTER_SELECT1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PERFCOUNTER3_SELECT {
	struct {
                unsigned int              PERFCOUNTER_SELECT : 10;
                unsigned int     PERFCOUNTER_SELECT1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PROTECTION_FAULT__CI__VI {
	struct {
                unsigned int                       WRITE_DIS : 1;
                unsigned int                  FAULT_DETECTED : 1;
                unsigned int                            GRBM : 1;
                unsigned int                           SH_ID : 3;
                unsigned int                           CU_ID : 4;
                unsigned int                         SIMD_ID : 2;
                unsigned int                         WAVE_ID : 4;
                unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_RD_ADDR {
	struct {
		unsigned int                       READ_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_RD_BURST_ADDR {
	struct {
		unsigned int                      BURST_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_RD_BURST_COUNT {
	struct {
		unsigned int                     BURST_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_RD_BURST_DATA {
	struct {
		unsigned int                      BURST_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_RD_DATA {
	struct {
		unsigned int                       READ_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_SECDED_CNT__CI {
	struct {
		unsigned int                             DED : 16;
		unsigned int                             SEC : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_SECDED_CNT__SI {
	struct {
		unsigned int                             SEC : 16;
		unsigned int                             DED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID0_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID0_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID10_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID10_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID11_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID11_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID12_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID12_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID13_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID13_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID14_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID14_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID15_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID15_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID1_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID1_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID2_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID2_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID3_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID3_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID4_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID4_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID5_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID5_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID6_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID6_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID7_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID7_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID8_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID8_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID9_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VMID9_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 17;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VM_PROTECTION_FAULT__CI__VI {
	struct {
                unsigned int                       WRITE_DIS : 1;
                unsigned int                  FAULT_DETECTED : 1;
                unsigned int                             GWS : 1;
                unsigned int                              OA : 1;
                unsigned int                            GRBM : 1;
                unsigned int                                 : 3;
                unsigned int                            VMID : 4;
                unsigned int                                 : 4;
                unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_WRITE_COMPLETE {
	struct {
		unsigned int                  WRITE_COMPLETE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_WR_ADDR {
	struct {
		unsigned int                      WRITE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_WR_BURST_ADDR {
	struct {
		unsigned int                      WRITE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_WR_BURST_DATA {
	struct {
		unsigned int                      WRITE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_WR_DATA {
	struct {
		unsigned int                      WRITE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENENB__SI__VI {
	struct {
                unsigned int                     BLK_IO_BASE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERAL_PWRMGT__CI__VI {
	struct {
                unsigned int                GLOBAL_PWRMGT_EN : 1;
                unsigned int                    STATIC_PM_EN : 1;
                unsigned int          THERMAL_PROTECTION_DIS : 1;
                unsigned int         THERMAL_PROTECTION_TYPE : 1;
                unsigned int                                 : 2;
                unsigned int                   SW_SMIO_INDEX : 1;
                unsigned int                                 : 1;
                unsigned int                LOW_VOLT_D2_ACPI : 1;
                unsigned int                LOW_VOLT_D3_ACPI : 1;
                unsigned int                  VOLT_PWRMGT_EN : 1;
                unsigned int                         SPARE11 : 1;
                unsigned int                                 : 2;
                unsigned int                GPU_COUNTER_ACPI : 1;
                unsigned int                 GPU_COUNTER_CLK : 1;
                unsigned int                 GPU_COUNTER_OFF : 1;
                unsigned int            GPU_COUNTER_INTF_OFF : 1;
                unsigned int                         SPARE18 : 1;
                unsigned int                     ACPI_D3_VID : 2;
                unsigned int                                 : 2;
                unsigned int          DYN_SPREAD_SPECTRUM_EN : 1;
                unsigned int                                 : 3;
                unsigned int                         SPARE27 : 1;
                unsigned int                           SPARE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERAL_PWRMGT__SI {
	struct {
		unsigned int                GLOBAL_PWRMGT_EN : 1;
		unsigned int                    STATIC_PM_EN : 1;
		unsigned int          THERMAL_PROTECTION_DIS : 1;
		unsigned int         THERMAL_PROTECTION_TYPE : 1;
		unsigned int                                 : 2;
		unsigned int                   SW_SMIO_INDEX : 1;
		unsigned int                                 : 3;
		unsigned int                  VOLT_PWRMGT_EN : 1;
		unsigned int                         SPARE11 : 1;
		unsigned int                                 : 6;
		unsigned int                         SPARE18 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int          DYN_SPREAD_SPECTRUM_EN : 1;
		unsigned int                                 : 3;
		unsigned int                           SPARE : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERIC_I2C_CONTROL__SI__VI {
	struct {
                unsigned int                  GENERIC_I2C_GO : 1;
                unsigned int          GENERIC_I2C_SOFT_RESET : 1;
                unsigned int          GENERIC_I2C_SEND_RESET : 1;
                unsigned int          GENERIC_I2C_ENABLE__VI : 1;
                unsigned int                                 : 27;
                unsigned int         GENERIC_I2C_DBG_REF_SEL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERIC_I2C_DATA__SI__VI {
	struct {
                unsigned int             GENERIC_I2C_DATA_RW : 1;
                unsigned int                                 : 7;
                unsigned int                GENERIC_I2C_DATA : 8;
                unsigned int               GENERIC_I2C_INDEX : 4;
                unsigned int                                 : 11;
                unsigned int         GENERIC_I2C_INDEX_WRITE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERIC_I2C_INTERRUPT_CONTROL__SI__VI {
	struct {
                unsigned int            GENERIC_I2C_DONE_INT : 1;
                unsigned int            GENERIC_I2C_DONE_ACK : 1;
                unsigned int           GENERIC_I2C_DONE_MASK : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERIC_I2C_PIN_DEBUG__SI__VI {
	struct {
                unsigned int          GENERIC_I2C_SCL_OUTPUT : 1;
                unsigned int           GENERIC_I2C_SCL_INPUT : 1;
                unsigned int              GENERIC_I2C_SCL_EN : 1;
                unsigned int                                 : 1;
                unsigned int          GENERIC_I2C_SDA_OUTPUT : 1;
                unsigned int           GENERIC_I2C_SDA_INPUT : 1;
                unsigned int              GENERIC_I2C_SDA_EN : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERIC_I2C_PIN_SELECTION__SI__VI {
	struct {
                unsigned int         GENERIC_I2C_SCL_PIN_SEL : 7;
                unsigned int                                 : 1;
                unsigned int         GENERIC_I2C_SDA_PIN_SEL : 7;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERIC_I2C_SETUP__SI__VI {
	struct {
                unsigned int       GENERIC_I2C_DATA_DRIVE_EN : 1;
                unsigned int      GENERIC_I2C_DATA_DRIVE_SEL : 1;
                unsigned int                                 : 5;
                unsigned int        GENERIC_I2C_CLK_DRIVE_EN : 1;
                unsigned int    GENERIC_I2C_INTRA_BYTE_DELAY : 8;
                unsigned int                                 : 8;
                unsigned int          GENERIC_I2C_TIME_LIMIT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERIC_I2C_SPEED__SI__VI {
	struct {
                unsigned int           GENERIC_I2C_THRESHOLD : 2;
                unsigned int                                 : 2;
                unsigned int GENERIC_I2C_DISABLE_FILTER_DURING_STALL : 1;
                unsigned int                                 : 11;
                unsigned int            GENERIC_I2C_PRESCALE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERIC_I2C_STATUS__SI__VI {
	struct {
                unsigned int              GENERIC_I2C_STATUS : 4;
                unsigned int                GENERIC_I2C_DONE : 1;
                unsigned int             GENERIC_I2C_ABORTED : 1;
                unsigned int             GENERIC_I2C_TIMEOUT : 1;
                unsigned int                                 : 2;
                unsigned int     GENERIC_I2C_STOPPED_ON_NACK : 1;
                unsigned int                GENERIC_I2C_NACK : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENERIC_I2C_TRANSACTION__SI__VI {
	struct {
                unsigned int                  GENERIC_I2C_RW : 1;
                unsigned int                                 : 7;
                unsigned int        GENERIC_I2C_STOP_ON_NACK : 1;
                unsigned int         GENERIC_I2C_ACK_ON_READ : 1;
                unsigned int                                 : 2;
                unsigned int               GENERIC_I2C_START : 1;
                unsigned int                GENERIC_I2C_STOP : 1;
                unsigned int                                 : 2;
                unsigned int               GENERIC_I2C_COUNT : 4;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENFC_RD__SI__VI {
	struct {
                unsigned int                                 : 3;
                unsigned int                     VSYNC_SEL_R : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENFC_WT__SI__VI {
	struct {
                unsigned int                                 : 3;
                unsigned int                     VSYNC_SEL_W : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENMO_RD__SI__VI {
	struct {
                unsigned int            GENMO_MONO_ADDRESS_B : 1;
                unsigned int                      VGA_RAM_EN : 1;
                unsigned int                       VGA_CKSEL : 2;
                unsigned int                                 : 1;
                unsigned int               ODD_EVEN_MD_PGSEL : 1;
                unsigned int                   VGA_HSYNC_POL : 1;
                unsigned int                   VGA_VSYNC_POL : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENMO_WT__SI__VI {
	struct {
                unsigned int            GENMO_MONO_ADDRESS_B : 1;
                unsigned int                      VGA_RAM_EN : 1;
                unsigned int                       VGA_CKSEL : 2;
                unsigned int                                 : 1;
                unsigned int               ODD_EVEN_MD_PGSEL : 1;
                unsigned int                   VGA_HSYNC_POL : 1;
                unsigned int                   VGA_VSYNC_POL : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENS0__SI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int                    SENSE_SWITCH : 1;
                unsigned int                                 : 2;
                unsigned int                        CRT_INTR : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GENS1__SI__VI {
	struct {
                unsigned int                      NO_DISPLAY : 1;
                unsigned int                                 : 2;
                unsigned int                     VGA_VSTATUS : 1;
                unsigned int                 PIXEL_READ_BACK : 2;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GFX_COPY_STATE {
	struct {
		unsigned int                    SRC_STATE_ID : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GFX_PIPE_CONTROL__CI__VI {
	struct {
                unsigned int                  HYSTERESIS_CNT : 13;
                unsigned int                                 : 3;
                unsigned int              CONTEXT_SUSPEND_EN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GFX_PIPE_PRIORITY__CI__VI {
	struct {
                unsigned int                  HP_PIPE_SELECT : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GLOBAL_CAPABILITIES__SI__VI {
	struct {
                unsigned int SIXTY_FOUR_BIT_ADDRESS_SUPPORTED : 1;
                unsigned int NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS : 2;
                unsigned int NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED : 5;
                unsigned int NUMBER_OF_INPUT_STREAMS_SUPPORTED : 4;
                unsigned int NUMBER_OF_OUTPUT_STREAMS_SUPPORTED : 4;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GLOBAL_CONTROL__SI__VI {
	struct {
                unsigned int                CONTROLLER_RESET : 1;
                unsigned int                   FLUSH_CONTROL : 1;
                unsigned int                                 : 6;
                unsigned int ACCEPT_UNSOLICITED_RESPONSE_ENABLE : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GLOBAL_STATUS__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                    FLUSH_STATUS : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_DEBUG__CI {
	struct {
		unsigned int                       GFX_STALL : 1;
		unsigned int                       GFX_CLEAR : 1;
		unsigned int                      MISC_FLAGS : 28;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_DEBUG__VI {
	struct {
		unsigned int                       GFX_STALL : 1;
		unsigned int                       GFX_CLEAR : 1;
		unsigned int           GMCON_DEBUG_RESERVED0 : 1;
		unsigned int                 SR_COMMIT_STATE : 1;
		unsigned int                       STCTRL_ST : 4;
		unsigned int                      MISC_FLAGS : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_MASK__CI__VI {
	struct {
                unsigned int         STCTRL_BUSY_MASK_ACP_RD : 1;
                unsigned int         STCTRL_BUSY_MASK_ACP_WR : 1;
                unsigned int         STCTRL_BUSY_MASK_VCE_RD : 1;
                unsigned int         STCTRL_BUSY_MASK_VCE_WR : 1;
                unsigned int        STCTRL_SR_HANDSHAKE_MASK : 8;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_MISC2__CI {
	struct {
		unsigned int   RENG_MEM_POWER_CTRL_OVERRIDE0 : 3;
		unsigned int   RENG_MEM_POWER_CTRL_OVERRIDE1 : 3;
		unsigned int   STCTRL_NONDISP_IDLE_THRESHOLD : 5;
		unsigned int          RENG_SR_HOLD_THRESHOLD : 6;
		unsigned int               STCTRL_LPT_TARGET : 12;
		unsigned int          STCTRL_IGNORE_ARB_BUSY : 1;
		unsigned int       STCTRL_EXTEND_GMC_OFFLINE : 1;
		unsigned int     STCTRL_TIMER_PULSE_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_MISC2__VI {
	struct {
		unsigned int           GMCON_MISC2_RESERVED0 : 6;
		unsigned int   STCTRL_NONDISP_IDLE_THRESHOLD : 5;
		unsigned int          RENG_SR_HOLD_THRESHOLD : 6;
		unsigned int           GMCON_MISC2_RESERVED1 : 12;
		unsigned int          STCTRL_IGNORE_ARB_BUSY : 1;
		unsigned int       STCTRL_EXTEND_GMC_OFFLINE : 1;
		unsigned int     STCTRL_TIMER_PULSE_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_MISC3__CI {
	struct {
		unsigned int                RENG_DISABLE_MCC : 6;
		unsigned int                RENG_DISABLE_MCD : 6;
		unsigned int     STCTRL_FORCE_PGFSM_CMD_DONE : 12;
		unsigned int     STCTRL_IGNORE_ALLOW_STUTTER : 1;
		unsigned int              RENG_MEM_LS_ENABLE : 1;
		unsigned int   STCTRL_EXCLUDE_NONMEM_CLIENTS : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_MISC3__VI {
	struct {
		unsigned int                RENG_DISABLE_MCC : 8;
		unsigned int                RENG_DISABLE_MCD : 8;
		unsigned int     STCTRL_FORCE_PGFSM_CMD_DONE : 12;
		unsigned int     STCTRL_IGNORE_ALLOW_STUTTER : 1;
		unsigned int              RENG_MEM_LS_ENABLE : 1;
		unsigned int   STCTRL_EXCLUDE_NONMEM_CLIENTS : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_MISC__CI__VI {
	struct {
                unsigned int                                 : 10;
                unsigned int           RENG_EXECUTE_NOW_MODE : 1;
                unsigned int      RENG_EXECUTE_ON_REG_UPDATE : 1;
                unsigned int           RENG_SRBM_CREDITS_MCD : 4;
                unsigned int               STCTRL_STUTTER_EN : 1;
                unsigned int       STCTRL_GMC_IDLE_THRESHOLD : 2;
                unsigned int      STCTRL_SRBM_IDLE_THRESHOLD : 2;
                unsigned int            STCTRL_IGNORE_PRE_SR : 1;
                unsigned int        STCTRL_IGNORE_ALLOW_STOP : 1;
                unsigned int         STCTRL_IGNORE_SR_COMMIT : 1;
                unsigned int  STCTRL_IGNORE_PROTECTION_FAULT : 1;
                unsigned int         STCTRL_DISABLE_ALLOW_SR : 1;
                unsigned int      STCTRL_DISABLE_GMC_OFFLINE : 1;
                unsigned int              CRITICAL_REGS_LOCK : 1;
                unsigned int           ALLOW_DEEP_SLEEP_MODE : 3;
                unsigned int           STCTRL_FORCE_ALLOW_SR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_PERF_MON_CNTL0__CI__VI {
	struct {
                unsigned int                    START_THRESH : 12;
                unsigned int                     STOP_THRESH : 12;
                unsigned int                      START_MODE : 2;
                unsigned int                       STOP_MODE : 2;
                unsigned int                      ALLOW_WRAP : 1;
                unsigned int          THRESH_CNTR_ID_EXT__VI : 1;
                unsigned int           START_TRIG_ID_EXT__VI : 1;
                unsigned int            STOP_TRIG_ID_EXT__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_PERF_MON_CNTL1__CI {
	struct {
		unsigned int                  THRESH_CNTR_ID : 6;
		unsigned int                   START_TRIG_ID : 6;
		unsigned int                    STOP_TRIG_ID : 6;
		unsigned int                         MON0_ID : 6;
		unsigned int                         MON1_ID : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_PERF_MON_CNTL1__VI {
	struct {
		unsigned int                  THRESH_CNTR_ID : 6;
		unsigned int                   START_TRIG_ID : 6;
		unsigned int                    STOP_TRIG_ID : 6;
		unsigned int                         MON0_ID : 7;
		unsigned int                         MON1_ID : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_PERF_MON_RSLT0__CI__VI {
	struct {
                unsigned int                           COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_PERF_MON_RSLT1__CI__VI {
	struct {
                unsigned int                           COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_PGFSM_CONFIG__CI__VI {
	struct {
                unsigned int                        FSM_ADDR : 8;
                unsigned int                      POWER_DOWN : 1;
                unsigned int                        POWER_UP : 1;
                unsigned int                       P1_SELECT : 1;
                unsigned int                       P2_SELECT : 1;
                unsigned int                           WRITE : 1;
                unsigned int                            READ : 1;
                unsigned int                           RSRVD : 13;
                unsigned int                   SRBM_OVERRIDE : 1;
                unsigned int                        REG_ADDR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_PGFSM_READ__CI__VI {
	struct {
                unsigned int                      READ_VALUE : 24;
                unsigned int                    PGFSM_SELECT : 4;
                unsigned int              SERDES_MASTER_BUSY : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_PGFSM_WRITE__CI__VI {
	struct {
                unsigned int                     WRITE_VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_RENG_EXECUTE__CI__VI {
	struct {
                unsigned int          RENG_EXECUTE_ON_PWR_UP : 1;
                unsigned int                RENG_EXECUTE_NOW : 1;
                unsigned int      RENG_EXECUTE_NOW_START_PTR : 10;
                unsigned int        RENG_EXECUTE_DSP_END_PTR : 10;
                unsigned int            RENG_EXECUTE_END_PTR : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_RENG_RAM_DATA__CI__VI {
	struct {
                unsigned int                   RENG_RAM_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_RENG_RAM_INDEX__CI__VI {
	struct {
                unsigned int                  RENG_RAM_INDEX : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__CI__VI {
	struct {
                unsigned int      STCTRL_REGISTER_SAVE_EXCL0 : 16;
                unsigned int      STCTRL_REGISTER_SAVE_EXCL1 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__CI__VI {
	struct {
                unsigned int      STCTRL_REGISTER_SAVE_EXCL2 : 16;
                unsigned int      STCTRL_REGISTER_SAVE_EXCL3 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_STCTRL_REGISTER_SAVE_RANGE0__CI__VI {
	struct {
                unsigned int      STCTRL_REGISTER_SAVE_BASE0 : 16;
                unsigned int     STCTRL_REGISTER_SAVE_LIMIT0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_STCTRL_REGISTER_SAVE_RANGE1__CI__VI {
	struct {
                unsigned int      STCTRL_REGISTER_SAVE_BASE1 : 16;
                unsigned int     STCTRL_REGISTER_SAVE_LIMIT1 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_STCTRL_REGISTER_SAVE_RANGE2__CI__VI {
	struct {
                unsigned int      STCTRL_REGISTER_SAVE_BASE2 : 16;
                unsigned int     STCTRL_REGISTER_SAVE_LIMIT2 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_A {
	struct {
		unsigned int                          GPIO_A : 31;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_EN {
	struct {
		unsigned int                         GPIO_EN : 31;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_EXTERN_TRIG_CNTL {
	struct {
		unsigned int                 EXTERN_TRIG_SEL : 5;
		unsigned int                 EXTERN_TRIG_CLR : 1;
		unsigned int                EXTERN_TRIG_READ : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_INT_EN {
	struct {
		unsigned int                     GPIO_INT_EN : 29;
		unsigned int                                 : 2;
		unsigned int             SW_INITIATED_INT_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_INT_POLARITY {
	struct {
		unsigned int               GPIO_INT_POLARITY : 29;
		unsigned int                                 : 2;
		unsigned int       SW_INITIATED_INT_POLARITY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_INT_STAT {
	struct {
		unsigned int                   GPIO_INT_STAT : 29;
		unsigned int                                 : 2;
		unsigned int           SW_INITIATED_INT_STAT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_INT_STAT_AK {
	struct {
		unsigned int              GPIO_INT_STAT_AK_0 : 1;
		unsigned int              GPIO_INT_STAT_AK_1 : 1;
		unsigned int              GPIO_INT_STAT_AK_2 : 1;
		unsigned int              GPIO_INT_STAT_AK_3 : 1;
		unsigned int              GPIO_INT_STAT_AK_4 : 1;
		unsigned int              GPIO_INT_STAT_AK_5 : 1;
		unsigned int              GPIO_INT_STAT_AK_6 : 1;
		unsigned int              GPIO_INT_STAT_AK_7 : 1;
		unsigned int              GPIO_INT_STAT_AK_8 : 1;
		unsigned int              GPIO_INT_STAT_AK_9 : 1;
		unsigned int             GPIO_INT_STAT_AK_10 : 1;
		unsigned int             GPIO_INT_STAT_AK_11 : 1;
		unsigned int             GPIO_INT_STAT_AK_12 : 1;
		unsigned int             GPIO_INT_STAT_AK_13 : 1;
		unsigned int             GPIO_INT_STAT_AK_14 : 1;
		unsigned int             GPIO_INT_STAT_AK_15 : 1;
		unsigned int             GPIO_INT_STAT_AK_16 : 1;
		unsigned int             GPIO_INT_STAT_AK_17 : 1;
		unsigned int             GPIO_INT_STAT_AK_18 : 1;
		unsigned int             GPIO_INT_STAT_AK_19 : 1;
		unsigned int             GPIO_INT_STAT_AK_20 : 1;
		unsigned int             GPIO_INT_STAT_AK_21 : 1;
		unsigned int             GPIO_INT_STAT_AK_22 : 1;
		unsigned int             GPIO_INT_STAT_AK_23 : 1;
		unsigned int             GPIO_INT_STAT_AK_24 : 1;
		unsigned int             GPIO_INT_STAT_AK_25 : 1;
		unsigned int             GPIO_INT_STAT_AK_26 : 1;
		unsigned int             GPIO_INT_STAT_AK_27 : 1;
		unsigned int             GPIO_INT_STAT_AK_28 : 1;
		unsigned int                                 : 2;
		unsigned int        SW_INITIATED_INT_STAT_AK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_INT_STAT_EN {
	struct {
		unsigned int                GPIO_INT_STAT_EN : 29;
		unsigned int                                 : 2;
		unsigned int        SW_INITIATED_INT_STAT_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_INT_TYPE {
	struct {
		unsigned int                   GPIO_INT_TYPE : 29;
		unsigned int                                 : 2;
		unsigned int           SW_INITIATED_INT_TYPE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_MASK {
	struct {
		unsigned int                       GPIO_MASK : 31;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_PD_EN {
	struct {
		unsigned int                      GPIO_PD_EN : 31;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_PINSTRAPS {
	struct {
		unsigned int                 GPIO_PINSTRAP_0 : 1;
		unsigned int                 GPIO_PINSTRAP_1 : 1;
		unsigned int                 GPIO_PINSTRAP_2 : 1;
		unsigned int                 GPIO_PINSTRAP_3 : 1;
		unsigned int                 GPIO_PINSTRAP_4 : 1;
		unsigned int                 GPIO_PINSTRAP_5 : 1;
		unsigned int                 GPIO_PINSTRAP_6 : 1;
		unsigned int                 GPIO_PINSTRAP_7 : 1;
		unsigned int                 GPIO_PINSTRAP_8 : 1;
		unsigned int                 GPIO_PINSTRAP_9 : 1;
		unsigned int                GPIO_PINSTRAP_10 : 1;
		unsigned int                GPIO_PINSTRAP_11 : 1;
		unsigned int                GPIO_PINSTRAP_12 : 1;
		unsigned int                GPIO_PINSTRAP_13 : 1;
		unsigned int                GPIO_PINSTRAP_14 : 1;
		unsigned int                GPIO_PINSTRAP_15 : 1;
		unsigned int                GPIO_PINSTRAP_16 : 1;
		unsigned int                GPIO_PINSTRAP_17 : 1;
		unsigned int                GPIO_PINSTRAP_18 : 1;
		unsigned int                GPIO_PINSTRAP_19 : 1;
		unsigned int                GPIO_PINSTRAP_20 : 1;
		unsigned int                GPIO_PINSTRAP_21 : 1;
		unsigned int                GPIO_PINSTRAP_22 : 1;
		unsigned int                GPIO_PINSTRAP_23 : 1;
		unsigned int                GPIO_PINSTRAP_24 : 1;
		unsigned int                GPIO_PINSTRAP_25 : 1;
		unsigned int                GPIO_PINSTRAP_26 : 1;
		unsigned int                GPIO_PINSTRAP_27 : 1;
		unsigned int                GPIO_PINSTRAP_28 : 1;
		unsigned int                GPIO_PINSTRAP_29 : 1;
		unsigned int                GPIO_PINSTRAP_30 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_PU_EN {
	struct {
		unsigned int                      GPIO_PU_EN : 31;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_RCVR_SEL {
	struct {
		unsigned int                   GPIO_RCVR_SEL : 31;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_STRENGTH {
	struct {
		unsigned int                GPIO_STRENGTH_SN : 4;
		unsigned int                GPIO_STRENGTH_SP : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_SW_INT_STAT {
	struct {
		unsigned int                     SW_INT_STAT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPIOPAD_Y {
	struct {
		unsigned int                          GPIO_Y : 31;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPU_GARLIC_FLUSH_DONE__CI__VI {
	struct {
                unsigned int                             CP0 : 1;
                unsigned int                             CP1 : 1;
                unsigned int                             CP2 : 1;
                unsigned int                             CP3 : 1;
                unsigned int                             CP4 : 1;
                unsigned int                             CP5 : 1;
                unsigned int                             CP6 : 1;
                unsigned int                             CP7 : 1;
                unsigned int                             CP8 : 1;
                unsigned int                             CP9 : 1;
                unsigned int                           SDMA0 : 1;
                unsigned int                           SDMA1 : 1;
                unsigned int                       SDMA2__VI : 1;
                unsigned int                       SDMA3__VI : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPU_GARLIC_FLUSH_REQ__CI__VI {
	struct {
                unsigned int                             CP0 : 1;
                unsigned int                             CP1 : 1;
                unsigned int                             CP2 : 1;
                unsigned int                             CP3 : 1;
                unsigned int                             CP4 : 1;
                unsigned int                             CP5 : 1;
                unsigned int                             CP6 : 1;
                unsigned int                             CP7 : 1;
                unsigned int                             CP8 : 1;
                unsigned int                             CP9 : 1;
                unsigned int                           SDMA0 : 1;
                unsigned int                           SDMA1 : 1;
                unsigned int                       SDMA2__VI : 1;
                unsigned int                       SDMA3__VI : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPU_HDP_FLUSH_DONE__CI__VI {
	struct {
                unsigned int                             CP0 : 1;
                unsigned int                             CP1 : 1;
                unsigned int                             CP2 : 1;
                unsigned int                             CP3 : 1;
                unsigned int                             CP4 : 1;
                unsigned int                             CP5 : 1;
                unsigned int                             CP6 : 1;
                unsigned int                             CP7 : 1;
                unsigned int                             CP8 : 1;
                unsigned int                             CP9 : 1;
                unsigned int                           SDMA0 : 1;
                unsigned int                           SDMA1 : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPU_HDP_FLUSH_REQ__CI__VI {
	struct {
                unsigned int                             CP0 : 1;
                unsigned int                             CP1 : 1;
                unsigned int                             CP2 : 1;
                unsigned int                             CP3 : 1;
                unsigned int                             CP4 : 1;
                unsigned int                             CP5 : 1;
                unsigned int                             CP6 : 1;
                unsigned int                             CP7 : 1;
                unsigned int                             CP8 : 1;
                unsigned int                             CP9 : 1;
                unsigned int                           SDMA0 : 1;
                unsigned int                           SDMA1 : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRA00__SI__VI {
	struct {
                unsigned int                 GRPH_SET_RESET0 : 1;
                unsigned int                 GRPH_SET_RESET1 : 1;
                unsigned int                 GRPH_SET_RESET2 : 1;
                unsigned int                 GRPH_SET_RESET3 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRA01__SI__VI {
	struct {
                unsigned int             GRPH_SET_RESET_ENA0 : 1;
                unsigned int             GRPH_SET_RESET_ENA1 : 1;
                unsigned int             GRPH_SET_RESET_ENA2 : 1;
                unsigned int             GRPH_SET_RESET_ENA3 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRA02__SI__VI {
	struct {
                unsigned int                      GRPH_CCOMP : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRA03__SI__VI {
	struct {
                unsigned int                     GRPH_ROTATE : 3;
                unsigned int                     GRPH_FN_SEL : 2;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRA04__SI__VI {
	struct {
                unsigned int                       GRPH_RMAP : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRA05__SI__VI {
	struct {
                unsigned int                 GRPH_WRITE_MODE : 2;
                unsigned int                                 : 1;
                unsigned int                      GRPH_READ1 : 1;
                unsigned int                     CGA_ODDEVEN : 1;
                unsigned int                        GRPH_OES : 1;
                unsigned int                       GRPH_PACK : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRA06__SI__VI {
	struct {
                unsigned int                   GRPH_GRAPHICS : 1;
                unsigned int                    GRPH_ODDEVEN : 1;
                unsigned int                     GRPH_ADRSEL : 2;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRA07__SI__VI {
	struct {
                unsigned int                     GRPH_XCARE0 : 1;
                unsigned int                     GRPH_XCARE1 : 1;
                unsigned int                     GRPH_XCARE2 : 1;
                unsigned int                     GRPH_XCARE3 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRA08__SI__VI {
	struct {
                unsigned int                       GRPH_BMSK : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_CAM_DATA {
	struct {
		unsigned int                        CAM_ADDR : 16;
		unsigned int                   CAM_REMAPADDR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_CAM_INDEX {
	struct {
		unsigned int                       CAM_INDEX : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_CNTL {
	struct {
                unsigned int                    READ_TIMEOUT : 8;
                unsigned int                                 : 23;
                unsigned int           REPORT_LAST_RDERR__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_DEBUG {
	struct {
                unsigned int                                 : 1;
                unsigned int                      IGNORE_RDY : 1;
                unsigned int                                 : 3;
                unsigned int                      IGNORE_FAO : 1;
                unsigned int            DISABLE_READ_TIMEOUT : 1;
                unsigned int             SNAPSHOT_FREE_CNTRS : 1;
                unsigned int           HYSTERESIS_GUI_ACTIVE : 4;
                unsigned int       GFX_CLOCK_DOMAIN_OVERRIDE : 1;
                unsigned int            GRBM_TRAP_ENABLE__VI : 1;
                unsigned int                                 : 17;
                unsigned int           DEBUG_BUS_FGCG_EN__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_DEBUG_CNTL {
	struct {
		unsigned int                GRBM_DEBUG_INDEX : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_DEBUG_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_DEBUG_SNAPSHOT__CI__VI {
	struct {
                unsigned int                         CPF_RDY : 1;
                unsigned int                         CPG_RDY : 1;
                unsigned int                        SRBM_RDY : 1;
                unsigned int                 WD_ME0PIPE0_RDY : 1;
                unsigned int                 WD_ME0PIPE1_RDY : 1;
                unsigned int                         GDS_RDY : 1;
                unsigned int            SE0SPI_ME0PIPE0_RDY0 : 1;
                unsigned int            SE0SPI_ME0PIPE1_RDY0 : 1;
                unsigned int            SE1SPI_ME0PIPE0_RDY0 : 1;
                unsigned int            SE1SPI_ME0PIPE1_RDY0 : 1;
                unsigned int            SE2SPI_ME0PIPE0_RDY0 : 1;
                unsigned int            SE2SPI_ME0PIPE1_RDY0 : 1;
                unsigned int            SE3SPI_ME0PIPE0_RDY0 : 1;
                unsigned int            SE3SPI_ME0PIPE1_RDY0 : 1;
                unsigned int            SE0SPI_ME0PIPE0_RDY1 : 1;
                unsigned int            SE0SPI_ME0PIPE1_RDY1 : 1;
                unsigned int            SE1SPI_ME0PIPE0_RDY1 : 1;
                unsigned int            SE1SPI_ME0PIPE1_RDY1 : 1;
                unsigned int            SE2SPI_ME0PIPE0_RDY1 : 1;
                unsigned int            SE2SPI_ME0PIPE1_RDY1 : 1;
                unsigned int            SE3SPI_ME0PIPE0_RDY1 : 1;
                unsigned int            SE3SPI_ME0PIPE1_RDY1 : 1;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_DEBUG_SNAPSHOT__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                        SRBM_RDY : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                         GDS_RDY : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_GFX_CLKEN_CNTL {
	struct {
		unsigned int                PREFIX_DELAY_CNT : 4;
		unsigned int                                 : 4;
		unsigned int                  POST_DELAY_CNT : 5;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_GFX_INDEX {
	struct {
		unsigned int                  INSTANCE_INDEX : 8;
		unsigned int                        SH_INDEX : 8;
		unsigned int                        SE_INDEX : 8;
		unsigned int                                 : 5;
		unsigned int             SH_BROADCAST_WRITES : 1;
		unsigned int       INSTANCE_BROADCAST_WRITES : 1;
		unsigned int             SE_BROADCAST_WRITES : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_INT_CNTL {
	struct {
		unsigned int                RDERR_INT_ENABLE : 1;
		unsigned int                                 : 18;
		unsigned int             GUI_IDLE_INT_ENABLE : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_NOWHERE {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_PERFCOUNTER0_SELECT {
	struct {
                unsigned int                        PERF_SEL : 6;
                unsigned int                                 : 4;
                unsigned int      DB_CLEAN_USER_DEFINED_MASK : 1;
                unsigned int      CB_CLEAN_USER_DEFINED_MASK : 1;
                unsigned int      VGT_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       TA_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       SX_BUSY_USER_DEFINED_MASK : 1;
                unsigned int                                 : 1;
                unsigned int      SPI_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       SC_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       PA_BUSY_USER_DEFINED_MASK : 1;
                unsigned int     GRBM_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       DB_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       CB_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       CP_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       IA_BUSY_USER_DEFINED_MASK : 1;
                unsigned int      GDS_BUSY_USER_DEFINED_MASK : 1;
                unsigned int      BCI_BUSY_USER_DEFINED_MASK : 1;
                unsigned int      RLC_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       TC_BUSY_USER_DEFINED_MASK : 1;
                unsigned int WD_BUSY_USER_DEFINED_MASK__CI__VI : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_PERFCOUNTER1_SELECT {
	struct {
                unsigned int                        PERF_SEL : 6;
                unsigned int                                 : 4;
                unsigned int      DB_CLEAN_USER_DEFINED_MASK : 1;
                unsigned int      CB_CLEAN_USER_DEFINED_MASK : 1;
                unsigned int      VGT_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       TA_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       SX_BUSY_USER_DEFINED_MASK : 1;
                unsigned int                                 : 1;
                unsigned int      SPI_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       SC_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       PA_BUSY_USER_DEFINED_MASK : 1;
                unsigned int     GRBM_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       DB_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       CB_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       CP_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       IA_BUSY_USER_DEFINED_MASK : 1;
                unsigned int      GDS_BUSY_USER_DEFINED_MASK : 1;
                unsigned int      BCI_BUSY_USER_DEFINED_MASK : 1;
                unsigned int      RLC_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       TC_BUSY_USER_DEFINED_MASK : 1;
                unsigned int WD_BUSY_USER_DEFINED_MASK__CI__VI : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_PWR_CNTL__SI__CI {
	struct {
		unsigned int                        REQ_TYPE : 4;
		unsigned int                        RSP_TYPE : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_PWR_CNTL__VI {
	struct {
		unsigned int                    ALL_REQ_TYPE : 2;
		unsigned int                    GFX_REQ_TYPE : 2;
		unsigned int                    ALL_RSP_TYPE : 2;
		unsigned int                    GFX_RSP_TYPE : 2;
		unsigned int                                 : 6;
		unsigned int                      GFX_REQ_EN : 1;
		unsigned int                      ALL_REQ_EN : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_READ_ERROR2__CI__VI {
	struct {
                unsigned int                                 : 17;
                unsigned int             READ_REQUESTER_SRBM : 1;
                unsigned int              READ_REQUESTER_RLC : 1;
                unsigned int          READ_REQUESTER_GDS_DMA : 1;
                unsigned int      READ_REQUESTER_ME0PIPE0_CF : 1;
                unsigned int      READ_REQUESTER_ME0PIPE0_PF : 1;
                unsigned int      READ_REQUESTER_ME0PIPE1_CF : 1;
                unsigned int      READ_REQUESTER_ME0PIPE1_PF : 1;
                unsigned int         READ_REQUESTER_ME1PIPE0 : 1;
                unsigned int         READ_REQUESTER_ME1PIPE1 : 1;
                unsigned int         READ_REQUESTER_ME1PIPE2 : 1;
                unsigned int         READ_REQUESTER_ME1PIPE3 : 1;
                unsigned int         READ_REQUESTER_ME2PIPE0 : 1;
                unsigned int         READ_REQUESTER_ME2PIPE1 : 1;
                unsigned int         READ_REQUESTER_ME2PIPE2 : 1;
                unsigned int         READ_REQUESTER_ME2PIPE3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_READ_ERROR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                    READ_ADDRESS : 16;
                unsigned int                                 : 2;
                unsigned int                     READ_PIPEID : 2;
                unsigned int                       READ_MEID : 2;
                unsigned int                                 : 7;
                unsigned int                      READ_ERROR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_READ_ERROR__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int                    READ_ADDRESS : 16;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                      READ_ERROR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SCRATCH_REG0 {
	struct {
		unsigned int                    SCRATCH_REG0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SCRATCH_REG1 {
	struct {
		unsigned int                    SCRATCH_REG1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SCRATCH_REG2 {
	struct {
		unsigned int                    SCRATCH_REG2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SCRATCH_REG3 {
	struct {
		unsigned int                    SCRATCH_REG3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SCRATCH_REG4 {
	struct {
		unsigned int                    SCRATCH_REG4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SCRATCH_REG5 {
	struct {
		unsigned int                    SCRATCH_REG5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SCRATCH_REG6 {
	struct {
		unsigned int                    SCRATCH_REG6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SCRATCH_REG7 {
	struct {
		unsigned int                    SCRATCH_REG7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE0_PERFCOUNTER_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE0_PERFCOUNTER_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE0_PERFCOUNTER_SELECT {
	struct {
		unsigned int                        PERF_SEL : 6;
		unsigned int                                 : 4;
		unsigned int      DB_CLEAN_USER_DEFINED_MASK : 1;
		unsigned int      CB_CLEAN_USER_DEFINED_MASK : 1;
		unsigned int       TA_BUSY_USER_DEFINED_MASK : 1;
		unsigned int       SX_BUSY_USER_DEFINED_MASK : 1;
		unsigned int                                 : 1;
		unsigned int      SPI_BUSY_USER_DEFINED_MASK : 1;
		unsigned int       SC_BUSY_USER_DEFINED_MASK : 1;
		unsigned int       DB_BUSY_USER_DEFINED_MASK : 1;
		unsigned int       CB_BUSY_USER_DEFINED_MASK : 1;
		unsigned int      VGT_BUSY_USER_DEFINED_MASK : 1;
		unsigned int       PA_BUSY_USER_DEFINED_MASK : 1;
		unsigned int      BCI_BUSY_USER_DEFINED_MASK : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE1_PERFCOUNTER_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE1_PERFCOUNTER_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE1_PERFCOUNTER_SELECT {
	struct {
		unsigned int                        PERF_SEL : 6;
		unsigned int                                 : 4;
		unsigned int      DB_CLEAN_USER_DEFINED_MASK : 1;
		unsigned int      CB_CLEAN_USER_DEFINED_MASK : 1;
		unsigned int       TA_BUSY_USER_DEFINED_MASK : 1;
		unsigned int       SX_BUSY_USER_DEFINED_MASK : 1;
		unsigned int                                 : 1;
		unsigned int      SPI_BUSY_USER_DEFINED_MASK : 1;
		unsigned int       SC_BUSY_USER_DEFINED_MASK : 1;
		unsigned int       DB_BUSY_USER_DEFINED_MASK : 1;
		unsigned int       CB_BUSY_USER_DEFINED_MASK : 1;
		unsigned int      VGT_BUSY_USER_DEFINED_MASK : 1;
		unsigned int       PA_BUSY_USER_DEFINED_MASK : 1;
		unsigned int      BCI_BUSY_USER_DEFINED_MASK : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE2_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE2_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE2_PERFCOUNTER_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 6;
                unsigned int                                 : 4;
                unsigned int      DB_CLEAN_USER_DEFINED_MASK : 1;
                unsigned int      CB_CLEAN_USER_DEFINED_MASK : 1;
                unsigned int       TA_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       SX_BUSY_USER_DEFINED_MASK : 1;
                unsigned int                                 : 1;
                unsigned int      SPI_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       SC_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       DB_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       CB_BUSY_USER_DEFINED_MASK : 1;
                unsigned int      VGT_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       PA_BUSY_USER_DEFINED_MASK : 1;
                unsigned int      BCI_BUSY_USER_DEFINED_MASK : 1;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE3_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE3_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SE3_PERFCOUNTER_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 6;
                unsigned int                                 : 4;
                unsigned int      DB_CLEAN_USER_DEFINED_MASK : 1;
                unsigned int      CB_CLEAN_USER_DEFINED_MASK : 1;
                unsigned int       TA_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       SX_BUSY_USER_DEFINED_MASK : 1;
                unsigned int                                 : 1;
                unsigned int      SPI_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       SC_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       DB_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       CB_BUSY_USER_DEFINED_MASK : 1;
                unsigned int      VGT_BUSY_USER_DEFINED_MASK : 1;
                unsigned int       PA_BUSY_USER_DEFINED_MASK : 1;
                unsigned int      BCI_BUSY_USER_DEFINED_MASK : 1;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SKEW_CNTL {
	struct {
		unsigned int              SKEW_TOP_THRESHOLD : 6;
		unsigned int                      SKEW_COUNT : 6;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_SOFT_RESET {
	struct {
                unsigned int                   SOFT_RESET_CP : 1;
                unsigned int                                 : 1;
                unsigned int                  SOFT_RESET_RLC : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int          SOFT_RESET_GFX__CI__VI : 1;
                unsigned int          SOFT_RESET_CPF__CI__VI : 1;
                unsigned int          SOFT_RESET_CPC__CI__VI : 1;
                unsigned int          SOFT_RESET_CPG__CI__VI : 1;
                unsigned int              SOFT_RESET_CAC__VI : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_STATUS2__CI__VI {
	struct {
                unsigned int          ME0PIPE1_CMDFIFO_AVAIL : 4;
                unsigned int          ME0PIPE1_CF_RQ_PENDING : 1;
                unsigned int          ME0PIPE1_PF_RQ_PENDING : 1;
                unsigned int             ME1PIPE0_RQ_PENDING : 1;
                unsigned int             ME1PIPE1_RQ_PENDING : 1;
                unsigned int             ME1PIPE2_RQ_PENDING : 1;
                unsigned int             ME1PIPE3_RQ_PENDING : 1;
                unsigned int             ME2PIPE0_RQ_PENDING : 1;
                unsigned int             ME2PIPE1_RQ_PENDING : 1;
                unsigned int             ME2PIPE2_RQ_PENDING : 1;
                unsigned int             ME2PIPE3_RQ_PENDING : 1;
                unsigned int                  RLC_RQ_PENDING : 1;
                unsigned int                                 : 9;
                unsigned int                        RLC_BUSY : 1;
                unsigned int                         TC_BUSY : 1;
                unsigned int             TCC_CC_RESIDENT__VI : 1;
                unsigned int                                 : 1;
                unsigned int                        CPF_BUSY : 1;
                unsigned int                        CPC_BUSY : 1;
                unsigned int                        CPG_BUSY : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_STATUS2__SI {
	struct {
		unsigned int                  RLC_RQ_PENDING : 1;
		unsigned int                                 : 7;
		unsigned int                        RLC_BUSY : 1;
		unsigned int                         TC_BUSY : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_STATUS_SE0 {
	struct {
		unsigned int                                 : 1;
		unsigned int                        DB_CLEAN : 1;
		unsigned int                        CB_CLEAN : 1;
		unsigned int                                 : 19;
		unsigned int                        BCI_BUSY : 1;
		unsigned int                        VGT_BUSY : 1;
		unsigned int                         PA_BUSY : 1;
		unsigned int                         TA_BUSY : 1;
		unsigned int                         SX_BUSY : 1;
		unsigned int                        SPI_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                         SC_BUSY : 1;
		unsigned int                         DB_BUSY : 1;
		unsigned int                         CB_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_STATUS_SE1 {
	struct {
		unsigned int                                 : 1;
		unsigned int                        DB_CLEAN : 1;
		unsigned int                        CB_CLEAN : 1;
		unsigned int                                 : 19;
		unsigned int                        BCI_BUSY : 1;
		unsigned int                        VGT_BUSY : 1;
		unsigned int                         PA_BUSY : 1;
		unsigned int                         TA_BUSY : 1;
		unsigned int                         SX_BUSY : 1;
		unsigned int                        SPI_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                         SC_BUSY : 1;
		unsigned int                         DB_BUSY : 1;
		unsigned int                         CB_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_STATUS_SE2__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                        DB_CLEAN : 1;
                unsigned int                        CB_CLEAN : 1;
                unsigned int                                 : 19;
                unsigned int                        BCI_BUSY : 1;
                unsigned int                        VGT_BUSY : 1;
                unsigned int                         PA_BUSY : 1;
                unsigned int                         TA_BUSY : 1;
                unsigned int                         SX_BUSY : 1;
                unsigned int                        SPI_BUSY : 1;
                unsigned int                                 : 1;
                unsigned int                         SC_BUSY : 1;
                unsigned int                         DB_BUSY : 1;
                unsigned int                         CB_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_STATUS_SE3__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                        DB_CLEAN : 1;
                unsigned int                        CB_CLEAN : 1;
                unsigned int                                 : 19;
                unsigned int                        BCI_BUSY : 1;
                unsigned int                        VGT_BUSY : 1;
                unsigned int                         PA_BUSY : 1;
                unsigned int                         TA_BUSY : 1;
                unsigned int                         SX_BUSY : 1;
                unsigned int                        SPI_BUSY : 1;
                unsigned int                                 : 1;
                unsigned int                         SC_BUSY : 1;
                unsigned int                         DB_BUSY : 1;
                unsigned int                         CB_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_STATUS__CI__VI {
	struct {
                unsigned int          ME0PIPE0_CMDFIFO_AVAIL : 4;
                unsigned int                                 : 1;
                unsigned int                 SRBM_RQ_PENDING : 1;
                unsigned int                                 : 1;
                unsigned int          ME0PIPE0_CF_RQ_PENDING : 1;
                unsigned int          ME0PIPE0_PF_RQ_PENDING : 1;
                unsigned int              GDS_DMA_RQ_PENDING : 1;
                unsigned int                                 : 2;
                unsigned int                        DB_CLEAN : 1;
                unsigned int                        CB_CLEAN : 1;
                unsigned int                         TA_BUSY : 1;
                unsigned int                        GDS_BUSY : 1;
                unsigned int                  WD_BUSY_NO_DMA : 1;
                unsigned int                        VGT_BUSY : 1;
                unsigned int                  IA_BUSY_NO_DMA : 1;
                unsigned int                         IA_BUSY : 1;
                unsigned int                         SX_BUSY : 1;
                unsigned int                         WD_BUSY : 1;
                unsigned int                        SPI_BUSY : 1;
                unsigned int                        BCI_BUSY : 1;
                unsigned int                         SC_BUSY : 1;
                unsigned int                         PA_BUSY : 1;
                unsigned int                         DB_BUSY : 1;
                unsigned int                                 : 1;
                unsigned int               CP_COHERENCY_BUSY : 1;
                unsigned int                         CP_BUSY : 1;
                unsigned int                         CB_BUSY : 1;
                unsigned int                      GUI_ACTIVE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_STATUS__SI {
	struct {
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                 SRBM_RQ_PENDING : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int              GDS_DMA_RQ_PENDING : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                        DB_CLEAN : 1;
		unsigned int                        CB_CLEAN : 1;
		unsigned int                         TA_BUSY : 1;
		unsigned int                        GDS_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                        VGT_BUSY : 1;
		unsigned int                  IA_BUSY_NO_DMA : 1;
		unsigned int                         IA_BUSY : 1;
		unsigned int                         SX_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                        SPI_BUSY : 1;
		unsigned int                        BCI_BUSY : 1;
		unsigned int                         SC_BUSY : 1;
		unsigned int                         PA_BUSY : 1;
		unsigned int                         DB_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int               CP_COHERENCY_BUSY : 1;
		unsigned int                         CP_BUSY : 1;
		unsigned int                         CB_BUSY : 1;
		unsigned int                      GUI_ACTIVE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_WAIT_IDLE_CLOCKS {
	struct {
		unsigned int                WAIT_IDLE_CLOCKS : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH8_DATA__SI__VI {
	struct {
                unsigned int                       GRPH_DATA : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH8_IDX__SI__VI {
	struct {
                unsigned int                        GRPH_IDX : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_ALPHA__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_COMPRESS_PITCH__SI__VI {
	struct {
                unsigned int                                 : 6;
                unsigned int             GRPH_COMPRESS_PITCH : 11;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI__VI {
	struct {
                unsigned int GRPH_COMPRESS_SURFACE_ADDRESS_HIGH : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_COMPRESS_SURFACE_ADDRESS__SI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int   GRPH_COMPRESS_SURFACE_ADDRESS : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_CONTROL {
	struct {
                unsigned int                      GRPH_DEPTH : 2;
                unsigned int                  GRPH_NUM_BANKS : 2;
                unsigned int                          GRPH_Z : 2;
                unsigned int                 GRPH_BANK_WIDTH : 2;
                unsigned int                     GRPH_FORMAT : 3;
                unsigned int                GRPH_BANK_HEIGHT : 2;
                unsigned int                 GRPH_TILE_SPLIT : 3;
                unsigned int GRPH_ADDRESS_TRANSLATION_ENABLE : 1;
                unsigned int   GRPH_PRIVILEGED_ACCESS_ENABLE : 1;
                unsigned int          GRPH_MACRO_TILE_ASPECT : 2;
                unsigned int                 GRPH_ARRAY_MODE : 4;
                unsigned int                GRPH_PIPE_CONFIG : 5;
                unsigned int    GRPH_MICRO_TILE_MODE__CI__VI : 2;
                unsigned int       GRPH_COLOR_EXPANSION_MODE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_DFQ_CONTROL__SI__VI {
	struct {
                unsigned int                  GRPH_DFQ_RESET : 1;
                unsigned int                                 : 3;
                unsigned int                   GRPH_DFQ_SIZE : 3;
                unsigned int                                 : 1;
                unsigned int       GRPH_DFQ_MIN_FREE_ENTRIES : 3;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_DFQ_STATUS__SI__VI {
	struct {
                unsigned int    GRPH_PRIMARY_DFQ_NUM_ENTRIES : 4;
                unsigned int  GRPH_SECONDARY_DFQ_NUM_ENTRIES : 4;
                unsigned int             GRPH_DFQ_RESET_FLAG : 1;
                unsigned int              GRPH_DFQ_RESET_ACK : 1;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_ENABLE__SI__VI {
	struct {
                unsigned int                     GRPH_ENABLE : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_FLIP_CONTROL {
	struct {
                unsigned int GRPH_SURFACE_UPDATE_H_RETRACE_EN : 1;
                unsigned int       GRPH_XDMA_SUPER_AA_EN__VI : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_INTERRUPT_CONTROL__SI__VI {
	struct {
                unsigned int             GRPH_PFLIP_INT_MASK : 1;
                unsigned int                                 : 7;
                unsigned int             GRPH_PFLIP_INT_TYPE : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_INTERRUPT_STATUS__SI__VI {
	struct {
                unsigned int         GRPH_PFLIP_INT_OCCURRED : 1;
                unsigned int                                 : 7;
                unsigned int            GRPH_PFLIP_INT_CLEAR : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_LUT_10BIT_BYPASS__SI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int        GRPH_LUT_10BIT_BYPASS_EN : 1;
                unsigned int                                 : 7;
                unsigned int GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_PITCH {
	struct {
                unsigned int                      GRPH_PITCH : 15;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_PRIMARY_SURFACE_ADDRESS {
	struct {
		unsigned int         GRPH_PRIMARY_DFQ_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int    GRPH_PRIMARY_SURFACE_ADDRESS : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_PRIMARY_SURFACE_ADDRESS_HIGH {
	struct {
		unsigned int GRPH_PRIMARY_SURFACE_ADDRESS_HIGH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI__VI {
	struct {
                unsigned int GRPH_SECONDARY_SURFACE_ADDRESS_HIGH : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_SECONDARY_SURFACE_ADDRESS__SI__VI {
	struct {
                unsigned int       GRPH_SECONDARY_DFQ_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int  GRPH_SECONDARY_SURFACE_ADDRESS : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI__VI {
	struct {
                unsigned int GRPH_SURFACE_ADDRESS_HIGH_INUSE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_SURFACE_ADDRESS_INUSE__SI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int      GRPH_SURFACE_ADDRESS_INUSE : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_SURFACE_OFFSET_X__SI__VI {
	struct {
                unsigned int           GRPH_SURFACE_OFFSET_X : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_SURFACE_OFFSET_Y__SI__VI {
	struct {
                unsigned int           GRPH_SURFACE_OFFSET_Y : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_SWAP_CNTL__SI__VI {
	struct {
                unsigned int                GRPH_ENDIAN_SWAP : 2;
                unsigned int                                 : 2;
                unsigned int               GRPH_RED_CROSSBAR : 2;
                unsigned int             GRPH_GREEN_CROSSBAR : 2;
                unsigned int              GRPH_BLUE_CROSSBAR : 2;
                unsigned int             GRPH_ALPHA_CROSSBAR : 2;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_UPDATE {
	struct {
                unsigned int        GRPH_MODE_UPDATE_PENDING : 1;
                unsigned int          GRPH_MODE_UPDATE_TAKEN : 1;
                unsigned int     GRPH_SURFACE_UPDATE_PENDING : 1;
                unsigned int       GRPH_SURFACE_UPDATE_TAKEN : 1;
                unsigned int                                 : 4;
                unsigned int GRPH_SURFACE_XDMA_PENDING_ENABLE__VI : 1;
                unsigned int                                 : 7;
                unsigned int                GRPH_UPDATE_LOCK : 1;
                unsigned int                                 : 3;
                unsigned int GRPH_SURFACE_IGNORE_UPDATE_LOCK__VI : 1;
                unsigned int                                 : 3;
                unsigned int GRPH_MODE_DISABLE_MULTIPLE_UPDATE : 1;
                unsigned int                                 : 3;
                unsigned int GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_X_END__SI__VI {
	struct {
                unsigned int                      GRPH_X_END : 15;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_X_START__SI__VI {
	struct {
                unsigned int                    GRPH_X_START : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_Y_END__SI__VI {
	struct {
                unsigned int                      GRPH_Y_END : 15;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_Y_START__SI__VI {
	struct {
                unsigned int                    GRPH_Y_START : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_ACR_32_0__SI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int                 HDMI_ACR_CTS_32 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_ACR_32_1__SI__VI {
	struct {
                unsigned int                   HDMI_ACR_N_32 : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_ACR_44_0__SI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int                 HDMI_ACR_CTS_44 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_ACR_44_1__SI__VI {
	struct {
                unsigned int                   HDMI_ACR_N_44 : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_ACR_48_0__SI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int                 HDMI_ACR_CTS_48 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_ACR_48_1__SI__VI {
	struct {
                unsigned int                   HDMI_ACR_N_48 : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_ACR_PACKET_CONTROL__SI__VI {
	struct {
                unsigned int                   HDMI_ACR_SEND : 1;
                unsigned int                   HDMI_ACR_CONT : 1;
                unsigned int                                 : 2;
                unsigned int                 HDMI_ACR_SELECT : 2;
                unsigned int                                 : 2;
                unsigned int                 HDMI_ACR_SOURCE : 1;
                unsigned int                                 : 3;
                unsigned int              HDMI_ACR_AUTO_SEND : 1;
                unsigned int                                 : 3;
                unsigned int             HDMI_ACR_N_MULTIPLE : 3;
                unsigned int                                 : 12;
                unsigned int         HDMI_ACR_AUDIO_PRIORITY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_ACR_STATUS_0__SI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int                    HDMI_ACR_CTS : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_ACR_STATUS_1__SI__VI {
	struct {
                unsigned int                      HDMI_ACR_N : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_AUDIO_PACKET_CONTROL__SI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int             HDMI_AUDIO_DELAY_EN : 2;
                unsigned int                                 : 2;
                unsigned int     HDMI_AUDIO_SEND_MAX_PACKETS : 1;
                unsigned int                                 : 7;
                unsigned int     HDMI_AUDIO_PACKETS_PER_LINE : 5;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_CONTROL__SI__VI {
	struct {
                unsigned int               HDMI_KEEPOUT_MODE : 1;
                unsigned int                                 : 3;
                unsigned int         HDMI_PACKET_GEN_VERSION : 1;
                unsigned int                                 : 3;
                unsigned int                  HDMI_ERROR_ACK : 1;
                unsigned int                 HDMI_ERROR_MASK : 1;
                unsigned int                                 : 14;
                unsigned int          HDMI_DEEP_COLOR_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int           HDMI_DEEP_COLOR_DEPTH : 2;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_GC__SI__VI {
	struct {
                unsigned int                  HDMI_GC_AVMUTE : 1;
                unsigned int                                 : 1;
                unsigned int             HDMI_GC_AVMUTE_CONT : 1;
                unsigned int                                 : 1;
                unsigned int              HDMI_DEFAULT_PHASE : 1;
                unsigned int                                 : 3;
                unsigned int              HDMI_PACKING_PHASE : 4;
                unsigned int     HDMI_PACKING_PHASE_OVERRIDE : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_GENERIC_PACKET_CONTROL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 10;
		unsigned int                                 : 6;
		unsigned int                                 : 2;
		unsigned int                                 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_INFOFRAME_CONTROL0__SI__VI {
	struct {
                unsigned int              HDMI_AVI_INFO_SEND : 1;
                unsigned int              HDMI_AVI_INFO_CONT : 1;
                unsigned int                                 : 2;
                unsigned int            HDMI_AUDIO_INFO_SEND : 1;
                unsigned int            HDMI_AUDIO_INFO_CONT : 1;
                unsigned int                                 : 2;
                unsigned int             HDMI_MPEG_INFO_SEND : 1;
                unsigned int             HDMI_MPEG_INFO_CONT : 1;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_INFOFRAME_CONTROL1__SI__VI {
	struct {
                unsigned int              HDMI_AVI_INFO_LINE : 6;
                unsigned int                                 : 2;
                unsigned int            HDMI_AUDIO_INFO_LINE : 6;
                unsigned int                                 : 2;
                unsigned int             HDMI_MPEG_INFO_LINE : 6;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_STATUS__SI__VI {
	struct {
                unsigned int              HDMI_ACTIVE_AVMUTE : 1;
                unsigned int                                 : 15;
                unsigned int         HDMI_AUDIO_PACKET_ERROR : 1;
                unsigned int                                 : 3;
                unsigned int           HDMI_VBI_PACKET_ERROR : 1;
                unsigned int                                 : 6;
                unsigned int                  HDMI_ERROR_INT : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_VBI_PACKET_CONTROL__SI__VI {
	struct {
                unsigned int                  HDMI_NULL_SEND : 1;
                unsigned int                                 : 3;
                unsigned int                    HDMI_GC_SEND : 1;
                unsigned int                    HDMI_GC_CONT : 1;
                unsigned int                                 : 2;
                unsigned int                  HDMI_ISRC_SEND : 1;
                unsigned int                  HDMI_ISRC_CONT : 1;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 3;
                unsigned int                  HDMI_ISRC_LINE : 6;
                unsigned int                                 : 2;
                unsigned int                                 : 6;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_DEBUG0 {
	struct {
		unsigned int                       HDP_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_DEBUG1 {
	struct {
		unsigned int                       HDP_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_HOST_PATH_CNTL {
	struct {
		unsigned int                BIF_RDRET_CREDIT : 3;
		unsigned int                 MC_WRREQ_CREDIT : 6;
		unsigned int                  WR_STALL_TIMER : 2;
		unsigned int                  RD_STALL_TIMER : 2;
		unsigned int                                 : 6;
		unsigned int             WRITE_COMBINE_TIMER : 2;
		unsigned int                WRITE_COMBINE_EN : 1;
		unsigned int                CACHE_INVALIDATE : 1;
		unsigned int                CLOCK_GATING_DIS : 1;
		unsigned int            REG_CLK_ENABLE_COUNT : 4;
		unsigned int                                 : 1;
		unsigned int                ALL_SURFACES_DIS : 1;
		unsigned int         WRITE_THROUGH_CACHE_DIS : 1;
		unsigned int                LIN_RD_CACHE_DIS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_LAST_SURFACE_HIT {
	struct {
		unsigned int                LAST_SURFACE_HIT : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_MEM_COHERENCY_FLUSH_CNTL {
	struct {
		unsigned int              HDP_MEM_FLUSH_ADDR : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_NONSURFACE_BASE {
	struct {
		unsigned int                    NONSURF_BASE : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_NONSURFACE_INFO {
	struct {
                unsigned int               NONSURF_ADDR_TYPE : 1;
                unsigned int              NONSURF_ARRAY_MODE : 4;
                unsigned int                  NONSURF_ENDIAN : 2;
                unsigned int              NONSURF_PIXEL_SIZE : 3;
                unsigned int              NONSURF_SAMPLE_NUM : 3;
                unsigned int             NONSURF_SAMPLE_SIZE : 2;
                unsigned int                    NONSURF_PRIV : 1;
                unsigned int            NONSURF_TILE_COMPACT : 1;
                unsigned int          NONSURF_TILE_SPLIT__VI : 3;
                unsigned int           NONSURF_NUM_BANKS__VI : 2;
                unsigned int          NONSURF_BANK_WIDTH__VI : 2;
                unsigned int         NONSURF_BANK_HEIGHT__VI : 2;
                unsigned int   NONSURF_MACRO_TILE_ASPECT__VI : 2;
                unsigned int     NONSURF_MICRO_TILE_MODE__VI : 3;
                unsigned int  NONSURF_SLICE_TILE_MAX_MSB__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_NONSURFACE_SIZE {
	struct {
		unsigned int          NONSURF_PITCH_TILE_MAX : 10;
		unsigned int          NONSURF_SLICE_TILE_MAX : 20;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_NONSURF_FLAGS {
	struct {
		unsigned int              NONSURF_WRITE_FLAG : 1;
		unsigned int               NONSURF_READ_FLAG : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_NONSURF_FLAGS_CLR {
	struct {
		unsigned int          NONSURF_WRITE_FLAG_CLR : 1;
		unsigned int           NONSURF_READ_FLAG_CLR : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_OUTSTANDING_REQ {
	struct {
		unsigned int                       WRITE_REQ : 8;
		unsigned int                        READ_REQ : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_REG_COHERENCY_FLUSH_CNTL {
	struct {
		unsigned int              HDP_REG_FLUSH_ADDR : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_SC_MULTI_CHIP_CNTL {
	struct {
		unsigned int                  LOG2_NUM_CHIPS : 3;
		unsigned int            MULTI_CHIP_TILE_SIZE : 2;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_SW_SEMAPHORE {
	struct {
		unsigned int                    SW_SEMAPHORE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_TILING_CONFIG {
	struct {
		unsigned int                                 : 1;
		unsigned int                     PIPE_TILING : 3;
		unsigned int                     BANK_TILING : 2;
		unsigned int                      GROUP_SIZE : 2;
		unsigned int                      ROW_TILING : 3;
		unsigned int                      BANK_SWAPS : 3;
		unsigned int                    SAMPLE_SPLIT : 2;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_BUSY_STS {
	struct {
                unsigned int                       BUSY_BITS : 18;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_CGTT_BLK_CTRL {
	struct {
		unsigned int        CGTT_BLK_CTRL_0_ON_DELAY : 4;
		unsigned int       CGTT_BLK_CTRL_1_OFF_DELAY : 8;
		unsigned int            CGTT_BLK_CTRL_2_RSVD : 18;
		unsigned int CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE : 1;
		unsigned int CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_CHKN {
	struct {
		unsigned int                     CHKN_0_RSVD : 8;
		unsigned int                     CHKN_1_RSVD : 8;
		unsigned int                     CHKN_2_RSVD : 8;
		unsigned int                     CHKN_3_RSVD : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_BAR_UPDATE {
	struct {
		unsigned int             D2H_BAR_UPDATE_ADDR : 16;
		unsigned int        D2H_BAR_UPDATE_FLUSH_NUM : 4;
		unsigned int          D2H_BAR_UPDATE_BAR_NUM : 3;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_FLUSH {
	struct {
		unsigned int             D2H_FLUSH_FLUSH_NUM : 4;
		unsigned int          D2H_FLUSH_MBX_ENC_DATA : 4;
		unsigned int          D2H_FLUSH_MBX_ADDR_SEL : 3;
		unsigned int               D2H_FLUSH_XPB_CLG : 5;
		unsigned int             D2H_FLUSH_SEND_HOST : 1;
		unsigned int             D2H_FLUSH_SEND_SIDE : 1;
		unsigned int       D2H_FLUSH_ALTER_FLUSH_NUM : 1;
		unsigned int                D2H_FLUSH_RSVD_0 : 1;
		unsigned int                D2H_FLUSH_RSVD_1 : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_10 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_11 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_12 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_13 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_14 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_15 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_16 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_17 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_18 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_19 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_20 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_21 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_22 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_23 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_24 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_25 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_26 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_27 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_28 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_29 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_30 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_31 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_32 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_33 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_34 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_4 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_5 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_6 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_7 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_8 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_D2H_RSVD_9 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_DBG_ADDR {
	struct {
		unsigned int                             STS : 16;
		unsigned int                            CTRL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_DBG_DATA {
	struct {
		unsigned int                             STS : 16;
		unsigned int                            CTRL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_DBG_MASK {
	struct {
		unsigned int                             STS : 16;
		unsigned int                            CTRL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_DIRECT2HDP_FIRST {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_DIRECT2HDP_LAST {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_FLUSH_ARMED_STS {
	struct {
		unsigned int                 FLUSH_ARMED_STS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_FLUSH_CNTR0_STS {
	struct {
		unsigned int                 FLUSH_CNTR0_STS : 26;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_HDP_IPH_CFG {
	struct {
                unsigned int HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE : 6;
                unsigned int HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE : 6;
                unsigned int HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING : 1;
                unsigned int       HDP_IPH_CFG_P2P_RD_EN__VI : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_HDP_MBX_MC_CFG {
	struct {
                unsigned int   HDP_MBX_MC_CFG_TAP_WRREQ_PRIV : 1;
                unsigned int   HDP_MBX_MC_CFG_TAP_WRREQ_SWAP : 2;
                unsigned int   HDP_MBX_MC_CFG_TAP_WRREQ_TRAN : 1;
                unsigned int HDP_MBX_MC_CFG_TAP_WRREQ_VMID__VI : 4;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_HDP_MC_CFG {
	struct {
                unsigned int   HDP_MC_CFG_HST_TAP_WRREQ_PRIV : 1;
                unsigned int   HDP_MC_CFG_HST_TAP_WRREQ_SWAP : 2;
                unsigned int   HDP_MC_CFG_HST_TAP_WRREQ_TRAN : 1;
                unsigned int   HDP_MC_CFG_SID_TAP_WRREQ_PRIV : 1;
                unsigned int   HDP_MC_CFG_SID_TAP_WRREQ_SWAP : 2;
                unsigned int   HDP_MC_CFG_SID_TAP_WRREQ_TRAN : 1;
                unsigned int HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE : 6;
                unsigned int HDP_MC_CFG_XDP_HIGHER_PRI_THRESH : 6;
                unsigned int HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK : 3;
                unsigned int HDP_MC_CFG_HST_TAP_WRREQ_VMID__VI : 4;
                unsigned int HDP_MC_CFG_SID_TAP_WRREQ_VMID__VI : 4;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_HST_CFG {
	struct {
		unsigned int           HST_CFG_WR_COMBINE_EN : 1;
		unsigned int        HST_CFG_WR_COMBINE_TIMER : 2;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_BAR0 {
	struct {
		unsigned int                            ADDR : 16;
		unsigned int                           FLUSH : 4;
		unsigned int                           VALID : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_BAR1 {
	struct {
		unsigned int                            ADDR : 16;
		unsigned int                           FLUSH : 4;
		unsigned int                           VALID : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_BAR2 {
	struct {
		unsigned int                            ADDR : 16;
		unsigned int                           FLUSH : 4;
		unsigned int                           VALID : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_BAR3 {
	struct {
		unsigned int                            ADDR : 16;
		unsigned int                           FLUSH : 4;
		unsigned int                           VALID : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_BAR4 {
	struct {
		unsigned int                            ADDR : 16;
		unsigned int                           FLUSH : 4;
		unsigned int                           VALID : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_BAR5 {
	struct {
		unsigned int                            ADDR : 16;
		unsigned int                           FLUSH : 4;
		unsigned int                           VALID : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_BAR6 {
	struct {
		unsigned int                            ADDR : 16;
		unsigned int                           FLUSH : 4;
		unsigned int                           VALID : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_BAR7 {
	struct {
		unsigned int                            ADDR : 16;
		unsigned int                           FLUSH : 4;
		unsigned int                           VALID : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_BAR_CFG {
	struct {
		unsigned int           P2P_BAR_CFG_ADDR_SIZE : 4;
		unsigned int            P2P_BAR_CFG_BAR_FROM : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_MBX_ADDR0 {
	struct {
                unsigned int                           VALID : 1;
                unsigned int                            ADDR : 20;
                unsigned int                  ADDR_39_36__VI : 4;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_MBX_ADDR1 {
	struct {
                unsigned int                           VALID : 1;
                unsigned int                            ADDR : 20;
                unsigned int                  ADDR_39_36__VI : 4;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_MBX_ADDR2 {
	struct {
                unsigned int                           VALID : 1;
                unsigned int                            ADDR : 20;
                unsigned int                  ADDR_39_36__VI : 4;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_MBX_ADDR3 {
	struct {
                unsigned int                           VALID : 1;
                unsigned int                            ADDR : 20;
                unsigned int                  ADDR_39_36__VI : 4;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_MBX_ADDR4 {
	struct {
                unsigned int                           VALID : 1;
                unsigned int                            ADDR : 20;
                unsigned int                  ADDR_39_36__VI : 4;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_MBX_ADDR5 {
	struct {
                unsigned int                           VALID : 1;
                unsigned int                            ADDR : 20;
                unsigned int                  ADDR_39_36__VI : 4;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_MBX_ADDR6 {
	struct {
                unsigned int                           VALID : 1;
                unsigned int                            ADDR : 20;
                unsigned int                  ADDR_39_36__VI : 4;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_P2P_MBX_OFFSET {
	struct {
		unsigned int                  P2P_MBX_OFFSET : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_SID_CFG {
	struct {
		unsigned int           SID_CFG_WR_COMBINE_EN : 1;
		unsigned int        SID_CFG_WR_COMBINE_TIMER : 2;
		unsigned int           SID_CFG_FLNUM_MSB_SEL : 2;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_SRBM_CFG {
	struct {
		unsigned int   SRBM_CFG_REG_CLK_ENABLE_COUNT : 6;
		unsigned int     SRBM_CFG_REG_CLK_GATING_DIS : 1;
		unsigned int           SRBM_CFG_WAKE_DYN_CLK : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_STICKY {
	struct {
		unsigned int                      STICKY_STS : 16;
		unsigned int                      STICKY_W1C : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HEADER {
	struct {
		unsigned int                     HEADER_TYPE : 7;
		unsigned int                     DEVICE_TYPE : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HFS_SEED0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HFS_SEED1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HFS_SEED2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HFS_SEED3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HOST_BUSNUM {
	struct {
                unsigned int                         HOST_ID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HW_DEBUG {
	struct {
		unsigned int                     HW_00_DEBUG : 1;
		unsigned int                     HW_01_DEBUG : 1;
		unsigned int                     HW_02_DEBUG : 1;
		unsigned int                     HW_03_DEBUG : 1;
		unsigned int                     HW_04_DEBUG : 1;
		unsigned int                     HW_05_DEBUG : 1;
		unsigned int                     HW_06_DEBUG : 1;
		unsigned int                     HW_07_DEBUG : 1;
		unsigned int                     HW_08_DEBUG : 1;
		unsigned int                     HW_09_DEBUG : 1;
		unsigned int                     HW_10_DEBUG : 1;
		unsigned int                     HW_11_DEBUG : 1;
		unsigned int                     HW_12_DEBUG : 1;
		unsigned int                     HW_13_DEBUG : 1;
		unsigned int                     HW_14_DEBUG : 1;
		unsigned int                     HW_15_DEBUG : 1;
		unsigned int                     HW_16_DEBUG : 1;
		unsigned int                     HW_17_DEBUG : 1;
		unsigned int                     HW_18_DEBUG : 1;
		unsigned int                     HW_19_DEBUG : 1;
		unsigned int                     HW_20_DEBUG : 1;
		unsigned int                     HW_21_DEBUG : 1;
		unsigned int                     HW_22_DEBUG : 1;
		unsigned int                     HW_23_DEBUG : 1;
		unsigned int                     HW_24_DEBUG : 1;
		unsigned int                     HW_25_DEBUG : 1;
		unsigned int                     HW_26_DEBUG : 1;
		unsigned int                     HW_27_DEBUG : 1;
		unsigned int                     HW_28_DEBUG : 1;
		unsigned int                     HW_29_DEBUG : 1;
		unsigned int                     HW_30_DEBUG : 1;
		unsigned int                     HW_31_DEBUG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union I2C_DATA__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_CNTL_STATUS {
	struct {
		unsigned int                         IA_BUSY : 1;
		unsigned int                     IA_DMA_BUSY : 1;
		unsigned int                 IA_DMA_REQ_BUSY : 1;
		unsigned int                     IA_GRP_BUSY : 1;
		unsigned int                     IA_ADC_BUSY : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_CNTL {
	struct {
		unsigned int                   IA_DEBUG_INDX : 6;
		unsigned int              IA_DEBUG_SEL_BUS_B : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG0__CI__VI {
	struct {
                unsigned int                ia_busy_extended : 1;
                unsigned int          ia_nodma_busy_extended : 1;
                unsigned int                         ia_busy : 1;
                unsigned int                   ia_nodma_busy : 1;
                unsigned int                          SPARE0 : 1;
                unsigned int                    dma_req_busy : 1;
                unsigned int                        dma_busy : 1;
                unsigned int                    mc_xl8r_busy : 1;
                unsigned int                        grp_busy : 1;
                unsigned int                          SPARE1 : 1;
                unsigned int                   dma_grp_valid : 1;
                unsigned int                    grp_dma_read : 1;
                unsigned int                dma_grp_hp_valid : 1;
                unsigned int                 grp_dma_hp_read : 1;
                unsigned int                          SPARE2 : 10;
                unsigned int                    reg_clk_busy : 1;
                unsigned int                   core_clk_busy : 1;
                unsigned int                          SPARE3 : 1;
                unsigned int                          SPARE4 : 1;
                unsigned int                    sclk_reg_vld : 1;
                unsigned int                   sclk_core_vld : 1;
                unsigned int                          SPARE5 : 1;
                unsigned int                          SPARE6 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG0__SI {
	struct {
		unsigned int                ia_busy_extended : 1;
		unsigned int          ia_nodma_busy_extended : 1;
		unsigned int                         ia_busy : 1;
		unsigned int                   ia_nodma_busy : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                        dma_busy : 1;
		unsigned int                    mc_xl8r_busy : 1;
		unsigned int                        grp_busy : 1;
		unsigned int                                 : 1;
		unsigned int                   dma_grp_valid : 1;
		unsigned int                    grp_dma_read : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                          SPARE3 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                    reg_clk_busy : 1;
		unsigned int                                 : 1;
		unsigned int                   core_clk_busy : 1;
		unsigned int                                 : 1;
		unsigned int                    sclk_reg_vld : 1;
		unsigned int                   sclk_core_vld : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG1__CI__VI {
	struct {
                unsigned int            dma_input_fifo_empty : 1;
                unsigned int             dma_input_fifo_full : 1;
                unsigned int                start_new_packet : 1;
                unsigned int                  dma_rdreq_dr_q : 1;
                unsigned int              dma_zero_indices_q : 1;
                unsigned int                  dma_buf_type_q : 2;
                unsigned int                  dma_req_path_q : 1;
                unsigned int               discard_1st_chunk : 1;
                unsigned int               discard_2nd_chunk : 1;
                unsigned int            second_tc_ret_data_q : 1;
                unsigned int                dma_tc_ret_sel_q : 1;
                unsigned int            last_rdreq_in_dma_op : 1;
                unsigned int             dma_mask_fifo_empty : 1;
                unsigned int           dma_data_fifo_empty_q : 1;
                unsigned int              dma_data_fifo_full : 1;
                unsigned int              dma_req_fifo_empty : 1;
                unsigned int               dma_req_fifo_full : 1;
                unsigned int                       stage2_dr : 1;
                unsigned int                      stage2_rtr : 1;
                unsigned int                       stage3_dr : 1;
                unsigned int                      stage3_rtr : 1;
                unsigned int                       stage4_dr : 1;
                unsigned int                      stage4_rtr : 1;
                unsigned int             dma_skid_fifo_empty : 1;
                unsigned int              dma_skid_fifo_full : 1;
                unsigned int                   dma_grp_valid : 1;
                unsigned int                    grp_dma_read : 1;
                unsigned int              current_data_valid : 1;
                unsigned int               out_of_range_r2_q : 1;
                unsigned int                dma_mask_fifo_we : 1;
                unsigned int               dma_ret_data_we_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG1__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 3;
		unsigned int                                 : 6;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG2__CI__VI {
	struct {
                unsigned int         hp_dma_input_fifo_empty : 1;
                unsigned int          hp_dma_input_fifo_full : 1;
                unsigned int             hp_start_new_packet : 1;
                unsigned int               hp_dma_rdreq_dr_q : 1;
                unsigned int           hp_dma_zero_indices_q : 1;
                unsigned int               hp_dma_buf_type_q : 2;
                unsigned int               hp_dma_req_path_q : 1;
                unsigned int            hp_discard_1st_chunk : 1;
                unsigned int            hp_discard_2nd_chunk : 1;
                unsigned int         hp_second_tc_ret_data_q : 1;
                unsigned int             hp_dma_tc_ret_sel_q : 1;
                unsigned int         hp_last_rdreq_in_dma_op : 1;
                unsigned int          hp_dma_mask_fifo_empty : 1;
                unsigned int        hp_dma_data_fifo_empty_q : 1;
                unsigned int           hp_dma_data_fifo_full : 1;
                unsigned int           hp_dma_req_fifo_empty : 1;
                unsigned int            hp_dma_req_fifo_full : 1;
                unsigned int                    hp_stage2_dr : 1;
                unsigned int                   hp_stage2_rtr : 1;
                unsigned int                    hp_stage3_dr : 1;
                unsigned int                   hp_stage3_rtr : 1;
                unsigned int                    hp_stage4_dr : 1;
                unsigned int                   hp_stage4_rtr : 1;
                unsigned int          hp_dma_skid_fifo_empty : 1;
                unsigned int           hp_dma_skid_fifo_full : 1;
                unsigned int                hp_dma_grp_valid : 1;
                unsigned int                 hp_grp_dma_read : 1;
                unsigned int           hp_current_data_valid : 1;
                unsigned int            hp_out_of_range_r2_q : 1;
                unsigned int             hp_dma_mask_fifo_we : 1;
                unsigned int            hp_dma_ret_data_we_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG2__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG3__CI__VI {
	struct {
                unsigned int           dma_pipe0_rdreq_valid : 1;
                unsigned int            dma_pipe0_rdreq_read : 1;
                unsigned int        dma_pipe0_rdreq_null_out : 1;
                unsigned int         dma_pipe0_rdreq_eop_out : 1;
                unsigned int      dma_pipe0_rdreq_use_tc_out : 1;
                unsigned int           grp_dma_draw_is_pipe0 : 1;
                unsigned int          must_service_pipe0_req : 1;
                unsigned int                  send_pipe1_req : 1;
                unsigned int           dma_pipe1_rdreq_valid : 1;
                unsigned int            dma_pipe1_rdreq_read : 1;
                unsigned int        dma_pipe1_rdreq_null_out : 1;
                unsigned int         dma_pipe1_rdreq_eop_out : 1;
                unsigned int      dma_pipe1_rdreq_use_tc_out : 1;
                unsigned int               ia_mc_rdreq_rtr_q : 1;
                unsigned int                      mc_out_rtr : 1;
                unsigned int              dma_rdreq_send_out : 1;
                unsigned int                        pipe0_dr : 1;
                unsigned int                       pipe0_rtr : 1;
                unsigned int               ia_tc_rdreq_rtr_q : 1;
                unsigned int                      tc_out_rtr : 1;
                unsigned int                  pair0_valid_p1 : 1;
                unsigned int                  pair1_valid_p1 : 1;
                unsigned int                  pair2_valid_p1 : 1;
                unsigned int                  pair3_valid_p1 : 1;
                unsigned int                  tc_req_count_q : 2;
                unsigned int               discard_1st_chunk : 1;
                unsigned int               discard_2nd_chunk : 1;
                unsigned int                  last_tc_req_p1 : 1;
                unsigned int            IA_TC_rdreq_send_out : 1;
                unsigned int            TC_IA_rdret_valid_in : 1;
                unsigned int             TAP_IA_rdret_vld_in : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG3__SI {
	struct {
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG4__CI__VI {
	struct {
                unsigned int                        pipe0_dr : 1;
                unsigned int                        pipe1_dr : 1;
                unsigned int                        pipe2_dr : 1;
                unsigned int                        pipe3_dr : 1;
                unsigned int                        pipe4_dr : 1;
                unsigned int                        pipe5_dr : 1;
                unsigned int              grp_se0_fifo_empty : 1;
                unsigned int               grp_se0_fifo_full : 1;
                unsigned int                       pipe0_rtr : 1;
                unsigned int                       pipe1_rtr : 1;
                unsigned int                       pipe2_rtr : 1;
                unsigned int                       pipe3_rtr : 1;
                unsigned int                       pipe4_rtr : 1;
                unsigned int                       pipe5_rtr : 1;
                unsigned int               ia_vgt_prim_rtr_q : 1;
                unsigned int            ia_se1vgt_prim_rtr_q : 1;
                unsigned int              di_major_mode_p1_q : 1;
                unsigned int                    gs_mode_p1_q : 3;
                unsigned int              di_event_flag_p1_q : 1;
                unsigned int               di_state_sel_p1_q : 3;
                unsigned int               draw_opaq_en_p1_q : 1;
                unsigned int              draw_opaq_active_q : 1;
                unsigned int           di_source_select_p1_q : 2;
                unsigned int                ready_to_read_di : 1;
                unsigned int        di_first_group_of_draw_q : 1;
                unsigned int              last_shift_of_draw : 1;
                unsigned int        current_shift_is_vect1_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG4__SI {
	struct {
		unsigned int                        pipe0_dr : 1;
		unsigned int                        pipe1_dr : 1;
		unsigned int                        pipe2_dr : 1;
		unsigned int                        pipe3_dr : 1;
		unsigned int                        pipe4_dr : 1;
		unsigned int                        pipe5_dr : 1;
		unsigned int              grp_se0_fifo_empty : 1;
		unsigned int               grp_se0_fifo_full : 1;
		unsigned int                       pipe0_rtr : 1;
		unsigned int                       pipe1_rtr : 1;
		unsigned int                       pipe2_rtr : 1;
		unsigned int                       pipe3_rtr : 1;
		unsigned int                       pipe4_rtr : 1;
		unsigned int                       pipe5_rtr : 1;
		unsigned int               ia_vgt_prim_rtr_q : 1;
		unsigned int            ia_se1vgt_prim_rtr_q : 1;
		unsigned int                                 : 1;
		unsigned int                    gs_mode_p1_q : 3;
		unsigned int              di_event_flag_p1_q : 1;
		unsigned int               di_state_sel_p1_q : 3;
		unsigned int               draw_opaq_en_p1_q : 1;
		unsigned int              draw_opaq_active_q : 1;
		unsigned int           di_source_select_p1_q : 2;
		unsigned int                ready_to_read_di : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int        current_shift_is_vect1_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG5__CI__VI {
	struct {
                unsigned int         di_index_counter_q_15_0 : 16;
                unsigned int                 instanceid_13_0 : 14;
                unsigned int            draw_input_fifo_full : 1;
                unsigned int           draw_input_fifo_empty : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG5__SI {
	struct {
		unsigned int         di_index_counter_q_15_0 : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG6__CI__VI {
	struct {
                unsigned int                 current_shift_q : 4;
                unsigned int              current_stride_pre : 4;
                unsigned int                current_stride_q : 5;
                unsigned int             first_group_partial : 1;
                unsigned int            second_group_partial : 1;
                unsigned int               curr_prim_partial : 1;
                unsigned int                   next_stride_q : 5;
                unsigned int              next_group_partial : 1;
                unsigned int             after_group_partial : 1;
                unsigned int                   extract_group : 1;
                unsigned int            grp_shift_debug_data : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG6__SI {
	struct {
		unsigned int                 current_shift_q : 4;
		unsigned int              current_stride_pre : 4;
		unsigned int                current_stride_q : 5;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int               curr_prim_partial : 1;
		unsigned int                   next_stride_q : 5;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                   extract_group : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG7__CI__VI {
	struct {
                unsigned int              reset_indx_state_q : 4;
                unsigned int           shift_vect_valid_p2_q : 4;
                unsigned int          shift_vect1_valid_p2_q : 4;
                unsigned int    shift_vect0_reset_match_p2_q : 4;
                unsigned int    shift_vect1_reset_match_p2_q : 4;
                unsigned int          num_indx_in_group_p2_q : 3;
                unsigned int         last_group_of_draw_p2_q : 1;
                unsigned int           shift_event_flag_p2_q : 1;
                unsigned int          indx_shift_is_one_p2_q : 1;
                unsigned int          indx_shift_is_two_p2_q : 1;
                unsigned int        indx_stride_is_four_p2_q : 1;
                unsigned int          shift_prim1_reset_p3_q : 1;
                unsigned int        shift_prim1_partial_p3_q : 1;
                unsigned int          shift_prim0_reset_p3_q : 1;
                unsigned int        shift_prim0_partial_p3_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG7__SI {
	struct {
		unsigned int              reset_indx_state_q : 4;
		unsigned int           shift_vect_valid_p2_q : 4;
		unsigned int                                 : 4;
		unsigned int    shift_vect0_reset_match_p2_q : 4;
		unsigned int    shift_vect1_reset_match_p2_q : 4;
		unsigned int          num_indx_in_group_p2_q : 3;
		unsigned int                                 : 1;
		unsigned int           shift_event_flag_p2_q : 1;
		unsigned int          indx_shift_is_one_p2_q : 1;
		unsigned int          indx_shift_is_two_p2_q : 1;
		unsigned int        indx_stride_is_four_p2_q : 1;
		unsigned int          shift_prim1_reset_p3_q : 1;
		unsigned int        shift_prim1_partial_p3_q : 1;
		unsigned int          shift_prim0_reset_p3_q : 1;
		unsigned int        shift_prim0_partial_p3_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG8 {
	struct {
		unsigned int               di_prim_type_p1_q : 5;
		unsigned int             two_cycle_xfer_p1_q : 1;
		unsigned int             two_prim_input_p1_q : 1;
		unsigned int   shift_vect_end_of_packet_p5_q : 1;
		unsigned int         last_group_of_inst_p5_q : 1;
		unsigned int      shift_prim1_null_flag_p5_q : 1;
		unsigned int      shift_prim0_null_flag_p5_q : 1;
		unsigned int                   grp_continued : 1;
		unsigned int                   grp_state_sel : 3;
		unsigned int               grp_sub_prim_type : 6;
		unsigned int                 grp_output_path : 3;
		unsigned int              grp_null_primitive : 1;
		unsigned int                         grp_eop : 1;
		unsigned int                        grp_eopg : 1;
		unsigned int                  grp_event_flag : 1;
		unsigned int            grp_components_valid : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG9__CI__VI {
	struct {
                unsigned int                  send_to_se1_p6 : 1;
                unsigned int                gfx_se_switch_p6 : 1;
                unsigned int          null_eoi_xfer_prim1_p6 : 1;
                unsigned int          null_eoi_xfer_prim0_p6 : 1;
                unsigned int                    prim1_eoi_p6 : 1;
                unsigned int                    prim0_eoi_p6 : 1;
                unsigned int             prim1_valid_eopg_p6 : 1;
                unsigned int             prim0_valid_eopg_p6 : 1;
                unsigned int            prim1_to_other_se_p6 : 1;
                unsigned int            eopg_on_last_prim_p6 : 1;
                unsigned int           eopg_between_prims_p6 : 1;
                unsigned int     prim_count_eq_group_size_p6 : 1;
                unsigned int     prim_count_gt_group_size_p6 : 1;
                unsigned int            two_prim_output_p5_q : 1;
                unsigned int                          SPARE0 : 1;
                unsigned int                          SPARE1 : 1;
                unsigned int   shift_vect_end_of_packet_p5_q : 1;
                unsigned int                   prim1_xfer_p6 : 1;
                unsigned int              grp_se1_fifo_empty : 1;
                unsigned int               grp_se1_fifo_full : 1;
                unsigned int                  prim_counter_q : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_DEBUG_REG9__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                gfx_se_switch_p6 : 1;
		unsigned int          null_eoi_xfer_prim1_p6 : 1;
		unsigned int          null_eoi_xfer_prim0_p6 : 1;
		unsigned int                    prim1_eoi_p6 : 1;
		unsigned int                    prim0_eoi_p6 : 1;
		unsigned int             prim1_valid_eopg_p6 : 1;
		unsigned int             prim0_valid_eopg_p6 : 1;
		unsigned int            prim1_to_other_se_p6 : 1;
		unsigned int            eopg_on_last_prim_p6 : 1;
		unsigned int           eopg_between_prims_p6 : 1;
		unsigned int     prim_count_eq_group_size_p6 : 1;
		unsigned int     prim_count_gt_group_size_p6 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                   prim1_xfer_p6 : 1;
		unsigned int                  prim_counter_q : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_ENHANCE {
	struct {
		unsigned int                            MISC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_MULTI_VGT_PARAM {
	struct {
                unsigned int                  PRIMGROUP_SIZE : 16;
                unsigned int              PARTIAL_VS_WAVE_ON : 1;
                unsigned int                   SWITCH_ON_EOP : 1;
                unsigned int              PARTIAL_ES_WAVE_ON : 1;
                unsigned int                   SWITCH_ON_EOI : 1;
                unsigned int        WD_SWITCH_ON_EOP__CI__VI : 1;
                unsigned int                                 : 7;
                unsigned int         MAX_PRIMGRP_IN_WAVE__VI : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE3 : 4;
                unsigned int                      PERF_MODE2 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                       PERF_SEL1 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER0_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER1_SELECT {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER2_SELECT {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_PERFCOUNTER3_SELECT {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IA_VMID_OVERRIDE__SI__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                            VMID : 4;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IDDCCIF02_DBG_DCCIF_C__SI__VI {
	struct {
                unsigned int                     DBG_DCCIF_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IDDCCIF04_DBG_DCCIF_E__SI__VI {
	struct {
                unsigned int                     DBG_DCCIF_E : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IDDCCIF05_DBG_DCCIF_F__SI__VI {
	struct {
                unsigned int                     DBG_DCCIF_F : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_ADVFAULT_CNTL__SI__CI {
	struct {
		unsigned int                       WATERMARK : 3;
		unsigned int                WATERMARK_ENABLE : 1;
		unsigned int               WATERMARK_REACHED : 1;
		unsigned int                                 : 3;
		unsigned int              NUM_FAULTS_DROPPED : 8;
		unsigned int                      WAIT_TIMER : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_CNTL {
	struct {
                unsigned int                     ENABLE_INTR : 1;
                unsigned int                         MC_SWAP : 2;
                unsigned int                         MC_TRAN : 1;
                unsigned int                      RPTR_REARM : 1;
                unsigned int                                 : 3;
                unsigned int           CLIENT_FIFO_HIGHWATER : 2;
                unsigned int               MC_FIFO_HIGHWATER : 5;
                unsigned int                 MC_WRREQ_CREDIT : 5;
                unsigned int                 MC_WR_CLEAN_CNT : 5;
                unsigned int                 MC_VMID__CI__VI : 4;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_LEVEL_STATUS {
	struct {
                unsigned int                       DC_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int                      ROM_STATUS : 1;
                unsigned int                     SRBM_STATUS : 1;
                unsigned int                      BIF_STATUS : 1;
                unsigned int             XDMA_STATUS__CI__VI : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_PERFCOUNTER0_RESULT__CI__VI {
	struct {
                unsigned int                      PERF_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_PERFCOUNTER1_RESULT__CI__VI {
	struct {
                unsigned int                      PERF_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_PERFMON_CNTL__CI__VI {
	struct {
                unsigned int                         ENABLE0 : 1;
                unsigned int                          CLEAR0 : 1;
                unsigned int                       PERF_SEL0 : 6;
                unsigned int                         ENABLE1 : 1;
                unsigned int                          CLEAR1 : 1;
                unsigned int                       PERF_SEL1 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_RB_BASE {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_RB_CNTL {
	struct {
                unsigned int                       RB_ENABLE : 1;
                unsigned int                         RB_SIZE : 5;
                unsigned int            RB_FULL_DRAIN_ENABLE : 1;
                unsigned int                RB_GPU_TS_ENABLE : 1;
                unsigned int           WPTR_WRITEBACK_ENABLE : 1;
                unsigned int            WPTR_WRITEBACK_TIMER : 5;
                unsigned int                                 : 2;
                unsigned int            WPTR_OVERFLOW_ENABLE : 1;
                unsigned int                 ENABLE_INTR__VI : 1;
                unsigned int                     MC_SWAP__VI : 2;
                unsigned int                                 : 1;
                unsigned int                  RPTR_REARM__VI : 1;
                unsigned int                                 : 2;
                unsigned int                     MC_VMID__VI : 4;
                unsigned int                                 : 3;
                unsigned int             WPTR_OVERFLOW_CLEAR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_RB_RPTR {
	struct {
		unsigned int                                 : 2;
		unsigned int                          OFFSET : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_RB_WPTR {
	struct {
                unsigned int                     RB_OVERFLOW : 1;
                unsigned int                                 : 1;
                unsigned int                          OFFSET : 16;
                unsigned int                RB_LEFT_NONE__VI : 1;
                unsigned int             RB_MAY_OVERFLOW__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_RB_WPTR_ADDR_HI {
	struct {
		unsigned int                            ADDR : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_RB_WPTR_ADDR_LO {
	struct {
		unsigned int                                 : 2;
		unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_STATUS {
	struct {
                unsigned int                            IDLE : 1;
                unsigned int                      INPUT_IDLE : 1;
                unsigned int                         RB_IDLE : 1;
                unsigned int                         RB_FULL : 1;
                unsigned int                   RB_FULL_DRAIN : 1;
                unsigned int                     RB_OVERFLOW : 1;
                unsigned int                      MC_WR_IDLE : 1;
                unsigned int                     MC_WR_STALL : 1;
                unsigned int             MC_WR_CLEAN_PENDING : 1;
                unsigned int               MC_WR_CLEAN_STALL : 1;
                unsigned int              BIF_INTERRUPT_LINE : 1;
                unsigned int                SWITCH_READY__VI : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_0_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_10_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_11_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_12_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_13_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_14_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_15_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_1_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_2_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_3_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_4_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_5_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_6_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_7_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_8_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VMID_9_LUT__CI__VI {
	struct {
                unsigned int                           PASID : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__SI__VI {
	struct {
                unsigned int         IMMEDIATE_COMMAND_WRITE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__SI__VI {
	struct {
                unsigned int         IMMEDIATE_COMMAND_WRITE : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IMMEDIATE_COMMAND_OUTPUT_INTERFACE__SI__VI {
	struct {
                unsigned int IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD : 28;
                unsigned int IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IMMEDIATE_COMMAND_STATUS__SI__VI {
	struct {
                unsigned int          IMMEDIATE_COMMAND_BUSY : 1;
                unsigned int          IMMEDIATE_RESULT_VALID : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IMMEDIATE_RESPONSE_INPUT_INTERFACE__SI__VI {
	struct {
                unsigned int         IMMEDIATE_RESPONSE_READ : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IMPCTL_RESET__CI__VI {
	struct {
                unsigned int                    IMP_SW_RESET : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_PAYLOAD_CAPABILITY__SI__VI {
	struct {
                unsigned int        INPUT_PAYLOAD_CAPABILITY : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INTERRUPT_CNTL {
	struct {
                unsigned int            IH_DUMMY_RD_OVERRIDE : 1;
                unsigned int                  IH_DUMMY_RD_EN : 1;
                unsigned int                                 : 1;
                unsigned int              IH_REQ_NONSNOOP_EN : 1;
                unsigned int                IH_INTR_DLY_CNTR : 4;
                unsigned int                   GEN_IH_INT_EN : 1;
                unsigned int                 GEN_GPIO_INT_EN : 4;
                unsigned int          SELECT_INT_GPIO_OUTPUT : 2;
                unsigned int      BIF_RB_REQ_NONSNOOP_EN__VI : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INTERRUPT_CNTL2 {
	struct {
		unsigned int                IH_DUMMY_RD_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INTERRUPT_CONTROL__SI {
	struct {
		unsigned int OUTPUT_STREAM_0_INTERRUPT_ENABLE : 1;
		unsigned int                                 : 29;
		unsigned int     CONTROLLER_INTERRUPT_ENABLE : 1;
		unsigned int         GLOBAL_INTERRUPT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INTERRUPT_CONTROL__VI {
	struct {
		unsigned int       STREAM_0_INTERRUPT_ENABLE : 1;
		unsigned int       STREAM_1_INTERRUPT_ENABLE : 1;
		unsigned int       STREAM_2_INTERRUPT_ENABLE : 1;
		unsigned int       STREAM_3_INTERRUPT_ENABLE : 1;
		unsigned int       STREAM_4_INTERRUPT_ENABLE : 1;
		unsigned int       STREAM_5_INTERRUPT_ENABLE : 1;
		unsigned int       STREAM_6_INTERRUPT_ENABLE : 1;
		unsigned int       STREAM_7_INTERRUPT_ENABLE : 1;
		unsigned int       STREAM_8_INTERRUPT_ENABLE : 1;
		unsigned int       STREAM_9_INTERRUPT_ENABLE : 1;
		unsigned int      STREAM_10_INTERRUPT_ENABLE : 1;
		unsigned int      STREAM_11_INTERRUPT_ENABLE : 1;
		unsigned int      STREAM_12_INTERRUPT_ENABLE : 1;
		unsigned int      STREAM_13_INTERRUPT_ENABLE : 1;
		unsigned int      STREAM_14_INTERRUPT_ENABLE : 1;
		unsigned int      STREAM_15_INTERRUPT_ENABLE : 1;
		unsigned int                                 : 14;
		unsigned int     CONTROLLER_INTERRUPT_ENABLE : 1;
		unsigned int         GLOBAL_INTERRUPT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INTERRUPT_LINE {
	struct {
		unsigned int                  INTERRUPT_LINE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INTERRUPT_PIN {
	struct {
		unsigned int                   INTERRUPT_PIN : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INTERRUPT_STATUS__SI {
	struct {
		unsigned int OUTPUT_STREAM_0_INTERRUPT_STATUS : 1;
		unsigned int                                 : 29;
		unsigned int     CONTROLLER_INTERRUPT_STATUS : 1;
		unsigned int         GLOBAL_INTERRUPT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INTERRUPT_STATUS__VI {
	struct {
		unsigned int       STREAM_0_INTERRUPT_STATUS : 1;
		unsigned int       STREAM_1_INTERRUPT_STATUS : 1;
		unsigned int       STREAM_2_INTERRUPT_STATUS : 1;
		unsigned int       STREAM_3_INTERRUPT_STATUS : 1;
		unsigned int       STREAM_4_INTERRUPT_STATUS : 1;
		unsigned int       STREAM_5_INTERRUPT_STATUS : 1;
		unsigned int       STREAM_6_INTERRUPT_STATUS : 1;
		unsigned int       STREAM_7_INTERRUPT_STATUS : 1;
		unsigned int       STREAM_8_INTERRUPT_STATUS : 1;
		unsigned int       STREAM_9_INTERRUPT_STATUS : 1;
		unsigned int      STREAM_10_INTERRUPT_STATUS : 1;
		unsigned int      STREAM_11_INTERRUPT_STATUS : 1;
		unsigned int      STREAM_12_INTERRUPT_STATUS : 1;
		unsigned int      STREAM_13_INTERRUPT_STATUS : 1;
		unsigned int      STREAM_14_INTERRUPT_STATUS : 1;
		unsigned int      STREAM_15_INTERRUPT_STATUS : 1;
		unsigned int                                 : 14;
		unsigned int     CONTROLLER_INTERRUPT_STATUS : 1;
		unsigned int         GLOBAL_INTERRUPT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INT_MASK__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 25;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IT_INT_EN__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IT_STAT__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KEFUSE0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KEFUSE1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KEFUSE2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KEFUSE3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KHFS0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KHFS1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KHFS2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KHFS3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KSESSION0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KSESSION1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KSESSION2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KSESSION3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KSIG0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KSIG1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KSIG2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KSIG3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LATENCY {
	struct {
		unsigned int                   LATENCY_TIMER : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_DEBUG__SI__VI {
	struct {
                unsigned int                        LB_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_SYNC_RESET_SEL__SI__VI {
	struct {
                unsigned int               LB_SYNC_RESET_SEL : 2;
                unsigned int                                 : 2;
                unsigned int          LB_SYNC_RESET_SEL2__VI : 1;
                unsigned int                                 : 3;
                unsigned int         LB_SYNC_RESET_DELAY__VI : 8;
                unsigned int                                 : 6;
                unsigned int            LB_SYNC_DURATION__VI : 2;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int              LB_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int             LB_TEST_DEBUG_INDEX : 8;
                unsigned int          LB_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_CPL_CNTL__CI__VI {
	struct {
                unsigned int                      CPL_ENABLE : 1;
                unsigned int                   CPL_THRESHOLD : 16;
                unsigned int                    CPL_BLOCK_ID : 5;
                unsigned int                   CPL_SIGNAL_ID : 8;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_CPL_OVR_SEL__CI__VI {
	struct {
                unsigned int                     CPL_OVR_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_CPL_OVR_VAL__CI__VI {
	struct {
                unsigned int                     CPL_OVR_VAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC0_CNTL {
	struct {
                unsigned int                      MC0_ENABLE : 1;
                unsigned int                   MC0_THRESHOLD : 16;
                unsigned int            MC0_BLOCK_ID__CI__VI : 5;
                unsigned int           MC0_SIGNAL_ID__CI__VI : 8;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC0_OVR_SEL {
	struct {
		unsigned int                     MC0_OVR_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC0_OVR_VAL {
	struct {
		unsigned int                     MC0_OVR_VAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC1_CNTL {
	struct {
                unsigned int                      MC1_ENABLE : 1;
                unsigned int                   MC1_THRESHOLD : 16;
                unsigned int            MC1_BLOCK_ID__CI__VI : 5;
                unsigned int           MC1_SIGNAL_ID__CI__VI : 8;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC1_OVR_SEL {
	struct {
		unsigned int                     MC1_OVR_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC1_OVR_VAL {
	struct {
		unsigned int                     MC1_OVR_VAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC2_CNTL {
	struct {
                unsigned int                      MC2_ENABLE : 1;
                unsigned int                   MC2_THRESHOLD : 16;
                unsigned int            MC2_BLOCK_ID__CI__VI : 5;
                unsigned int           MC2_SIGNAL_ID__CI__VI : 8;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC2_OVR_SEL {
	struct {
		unsigned int                     MC2_OVR_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC2_OVR_VAL {
	struct {
		unsigned int                     MC2_OVR_VAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC3_CNTL {
	struct {
                unsigned int                      MC3_ENABLE : 1;
                unsigned int                   MC3_THRESHOLD : 16;
                unsigned int            MC3_BLOCK_ID__CI__VI : 5;
                unsigned int           MC3_SIGNAL_ID__CI__VI : 8;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC3_OVR_SEL {
	struct {
		unsigned int                     MC3_OVR_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC3_OVR_VAL {
	struct {
		unsigned int                     MC3_OVR_VAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC4_CNTL__SI__VI {
	struct {
                unsigned int                      MC4_ENABLE : 1;
                unsigned int                   MC4_THRESHOLD : 16;
                unsigned int                MC4_BLOCK_ID__VI : 5;
                unsigned int               MC4_SIGNAL_ID__VI : 8;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC4_OVR_SEL__SI__VI {
	struct {
                unsigned int                     MC4_OVR_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC4_OVR_VAL__SI__VI {
	struct {
                unsigned int                     MC4_OVR_VAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC5_CNTL__SI__VI {
	struct {
                unsigned int                      MC5_ENABLE : 1;
                unsigned int                   MC5_THRESHOLD : 16;
                unsigned int                MC5_BLOCK_ID__VI : 5;
                unsigned int               MC5_SIGNAL_ID__VI : 8;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC5_OVR_SEL__SI__VI {
	struct {
                unsigned int                     MC5_OVR_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC5_OVR_VAL__SI__VI {
	struct {
                unsigned int                     MC5_OVR_VAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_SX0_CNTL__CI {
	struct {
		unsigned int                      SX0_ENABLE : 1;
		unsigned int                   SX0_THRESHOLD : 16;
		unsigned int                    SX0_BLOCK_ID : 5;
		unsigned int                   SX0_SIGNAL_ID : 8;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_SX0_OVR_SEL__CI {
	struct {
		unsigned int                     SX0_OVR_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_SX0_OVR_VAL__CI {
	struct {
		unsigned int                     SX0_OVR_VAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCLK_DEEP_SLEEP_CNTL2__CI__VI {
	struct {
                unsigned int                   RFE_BUSY_MASK : 1;
                unsigned int           BIF_CG_LCLK_BUSY_MASK : 1;
                unsigned int             L1IMU_SMU_IDLE_MASK : 1;
                unsigned int                                 : 1;
                unsigned int               SCLK_RUNNING_MASK : 1;
                unsigned int                   SMU_BUSY_MASK : 1;
                unsigned int            PCIE_LCLK_IDLE1_MASK : 1;
                unsigned int            PCIE_LCLK_IDLE2_MASK : 1;
                unsigned int            PCIE_LCLK_IDLE3_MASK : 1;
                unsigned int            PCIE_LCLK_IDLE4_MASK : 1;
                unsigned int              L1IMUGPP_IDLE_MASK : 1;
                unsigned int            L1IMUGPPSB_IDLE_MASK : 1;
                unsigned int              L1IMUBIF_IDLE_MASK : 1;
                unsigned int           L1IMUINTGEN_IDLE_MASK : 1;
                unsigned int                 L2IMU_IDLE_MASK : 1;
                unsigned int                   ORB_IDLE_MASK : 1;
                unsigned int                ON_INB_WAKE_MASK : 1;
                unsigned int            ON_INB_WAKE_ACK_MASK : 1;
                unsigned int               ON_OUTB_WAKE_MASK : 1;
                unsigned int           ON_OUTB_WAKE_ACK_MASK : 1;
                unsigned int                  DMAACTIVE_MASK : 1;
                unsigned int     RLC_SMU_GFXCLK_OFF_MASK__VI : 1;
                unsigned int                    RESERVED__VI : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCLK_DEEP_SLEEP_CNTL__CI__VI {
	struct {
                unsigned int                          DIV_ID : 3;
                unsigned int                        RAMP_DIS : 1;
                unsigned int                      HYSTERESIS : 12;
                unsigned int                                 : 15;
                unsigned int                       ENABLE_DS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LINK_CAP {
	struct {
                unsigned int                      LINK_SPEED : 4;
                unsigned int                      LINK_WIDTH : 6;
                unsigned int                      PM_SUPPORT : 2;
                unsigned int                L0S_EXIT_LATENCY : 3;
                unsigned int                 L1_EXIT_LATENCY : 3;
                unsigned int          CLOCK_POWER_MANAGEMENT : 1;
                unsigned int     SURPRISE_DOWN_ERR_REPORTING : 1;
                unsigned int     DL_ACTIVE_REPORTING_CAPABLE : 1;
                unsigned int        LINK_BW_NOTIFICATION_CAP : 1;
                unsigned int ASPM_OPTIONALITY_COMPLIANCE__CI__VI : 1;
                unsigned int                                 : 1;
                unsigned int                     PORT_NUMBER : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LINK_CAP2__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int            SUPPORTED_LINK_SPEED : 7;
                unsigned int             CROSSLINK_SUPPORTED : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LINK_CAP2__SI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LINK_CNTL {
	struct {
		unsigned int                      PM_CONTROL : 2;
		unsigned int                                 : 1;
		unsigned int               READ_CPL_BOUNDARY : 1;
		unsigned int                        LINK_DIS : 1;
		unsigned int                    RETRAIN_LINK : 1;
		unsigned int                COMMON_CLOCK_CFG : 1;
		unsigned int                   EXTENDED_SYNC : 1;
		unsigned int       CLOCK_POWER_MANAGEMENT_EN : 1;
		unsigned int     HW_AUTONOMOUS_WIDTH_DISABLE : 1;
		unsigned int       LINK_BW_MANAGEMENT_INT_EN : 1;
		unsigned int       LINK_AUTONOMOUS_BW_INT_EN : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LINK_CNTL2 {
	struct {
                unsigned int               TARGET_LINK_SPEED : 4;
                unsigned int                ENTER_COMPLIANCE : 1;
                unsigned int     HW_AUTONOMOUS_SPEED_DISABLE : 1;
                unsigned int           SELECTABLE_DEEMPHASIS : 1;
                unsigned int                     XMIT_MARGIN : 3;
                unsigned int            ENTER_MOD_COMPLIANCE : 1;
                unsigned int                  COMPLIANCE_SOS : 1;
                unsigned int           COMPLIANCE_DEEMPHASIS : 4;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LINK_STATUS {
	struct {
		unsigned int              CURRENT_LINK_SPEED : 4;
		unsigned int           NEGOTIATED_LINK_WIDTH : 6;
		unsigned int                                 : 1;
		unsigned int                   LINK_TRAINING : 1;
		unsigned int                  SLOT_CLOCK_CFG : 1;
		unsigned int                       DL_ACTIVE : 1;
		unsigned int       LINK_BW_MANAGEMENT_STATUS : 1;
		unsigned int       LINK_AUTONOMOUS_BW_STATUS : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LINK_STATUS2 {
	struct {
                unsigned int            CUR_DEEMPHASIS_LEVEL : 1;
                unsigned int   EQUALIZATION_COMPLETE__CI__VI : 1;
                unsigned int EQUALIZATION_PHASE1_SUCCESS__CI__VI : 1;
                unsigned int EQUALIZATION_PHASE2_SUCCESS__CI__VI : 1;
                unsigned int EQUALIZATION_PHASE3_SUCCESS__CI__VI : 1;
                unsigned int LINK_EQUALIZATION_REQUEST__CI__VI : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LNCNT_CONTROL__CI {
	struct {
		unsigned int                  LNCNT_ACC_MODE : 1;
		unsigned int              LNCNT_REF_TIMEBASE : 2;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LNCNT_CONTROL__VI {
	struct {
		unsigned int              CFG_LNC_WINDOW_EN0 : 1;
		unsigned int              CFG_LNC_BW_CNT_EN1 : 1;
		unsigned int             CFG_LNC_CMN_CNT_EN2 : 1;
		unsigned int                CFG_LNC_OVRD_EN3 : 1;
		unsigned int               CFG_LNC_OVRD_VAL4 : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LVDS_DATA_CNTL__SI__VI {
	struct {
                unsigned int               LVDS_24BIT_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int               LVDS_24BIT_FORMAT : 1;
                unsigned int                                 : 3;
                unsigned int                LVDS_2ND_CHAN_DE : 1;
                unsigned int                LVDS_2ND_CHAN_VS : 1;
                unsigned int                LVDS_2ND_CHAN_HS : 1;
                unsigned int                                 : 1;
                unsigned int         LVDS_2ND_LINK_CNTL_BITS : 3;
                unsigned int                                 : 1;
                unsigned int                     LVDS_FP_POL : 1;
                unsigned int                     LVDS_LP_POL : 1;
                unsigned int                   LVDS_DTMG_POL : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LVTMA_PWRSEQ_CNTL__SI__VI {
	struct {
                unsigned int                 LVTMA_PWRSEQ_EN : 1;
                unsigned int LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int       LVTMA_PWRSEQ_TARGET_STATE : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 2;
                unsigned int                    LVTMA_SYNCEN : 1;
                unsigned int               LVTMA_SYNCEN_OVRD : 1;
                unsigned int                LVTMA_SYNCEN_POL : 1;
                unsigned int                                 : 5;
                unsigned int                     LVTMA_DIGON : 1;
                unsigned int                LVTMA_DIGON_OVRD : 1;
                unsigned int                 LVTMA_DIGON_POL : 1;
                unsigned int                                 : 5;
                unsigned int                      LVTMA_BLON : 1;
                unsigned int                 LVTMA_BLON_OVRD : 1;
                unsigned int                  LVTMA_BLON_POL : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LVTMA_PWRSEQ_DELAY1__SI__VI {
	struct {
                unsigned int              LVTMA_PWRUP_DELAY1 : 8;
                unsigned int              LVTMA_PWRUP_DELAY2 : 8;
                unsigned int              LVTMA_PWRDN_DELAY1 : 8;
                unsigned int              LVTMA_PWRDN_DELAY2 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LVTMA_PWRSEQ_DELAY2__SI__VI {
	struct {
                unsigned int          LVTMA_PWRDN_MIN_LENGTH : 8;
                unsigned int          LVTMA_PWRUP_DELAY3__VI : 8;
                unsigned int          LVTMA_PWRDN_DELAY3__VI : 8;
                unsigned int   LVTMA_VARY_BL_OVERRIDE_EN__VI : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LVTMA_PWRSEQ_REF_DIV__SI__VI {
	struct {
                unsigned int            LVTMA_PWRSEQ_REF_DIV : 12;
                unsigned int                                 : 4;
                unsigned int                  BL_PWM_REF_DIV : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LVTMA_PWRSEQ_STATE__SI__VI {
	struct {
                unsigned int     LVTMA_PWRSEQ_TARGET_STATE_R : 1;
                unsigned int              LVTMA_PWRSEQ_DIGON : 1;
                unsigned int             LVTMA_PWRSEQ_SYNCEN : 1;
                unsigned int               LVTMA_PWRSEQ_BLON : 1;
                unsigned int               LVTMA_PWRSEQ_DONE : 1;
                unsigned int                                 : 3;
                unsigned int              LVTMA_PWRSEQ_STATE : 4;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LX0 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LX1 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LX2 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LX3 {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAJOR_VERSION__SI__VI {
	struct {
                unsigned int                   MAJOR_VERSION : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MASTER_COMM_CMD_REG__SI__VI {
	struct {
                unsigned int       MASTER_COMM_CMD_REG_BYTE0 : 8;
                unsigned int       MASTER_COMM_CMD_REG_BYTE1 : 8;
                unsigned int       MASTER_COMM_CMD_REG_BYTE2 : 8;
                unsigned int       MASTER_COMM_CMD_REG_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MASTER_COMM_CNTL_REG__SI__VI {
	struct {
                unsigned int           MASTER_COMM_INTERRUPT : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MASTER_COMM_DATA_REG1__SI__VI {
	struct {
                unsigned int     MASTER_COMM_DATA_REG1_BYTE0 : 8;
                unsigned int     MASTER_COMM_DATA_REG1_BYTE1 : 8;
                unsigned int     MASTER_COMM_DATA_REG1_BYTE2 : 8;
                unsigned int     MASTER_COMM_DATA_REG1_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MASTER_COMM_DATA_REG2__SI__VI {
	struct {
                unsigned int     MASTER_COMM_DATA_REG2_BYTE0 : 8;
                unsigned int     MASTER_COMM_DATA_REG2_BYTE1 : 8;
                unsigned int     MASTER_COMM_DATA_REG2_BYTE2 : 8;
                unsigned int     MASTER_COMM_DATA_REG2_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MASTER_COMM_DATA_REG3__SI__VI {
	struct {
                unsigned int     MASTER_COMM_DATA_REG3_BYTE0 : 8;
                unsigned int     MASTER_COMM_DATA_REG3_BYTE1 : 8;
                unsigned int     MASTER_COMM_DATA_REG3_BYTE2 : 8;
                unsigned int     MASTER_COMM_DATA_REG3_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MASTER_CREDIT_CNTL {
	struct {
                unsigned int             BIF_MC_RDRET_CREDIT : 7;
                unsigned int                                 : 9;
                unsigned int             BIF_AZ_RDRET_CREDIT : 6;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MASTER_UPDATE_LOCK__SI__VI {
	struct {
                unsigned int              MASTER_UPDATE_LOCK : 1;
                unsigned int                                 : 7;
                unsigned int GSL_CONTROL_MASTER_UPDATE_LOCK__VI : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MASTER_UPDATE_MODE {
	struct {
		unsigned int              MASTER_UPDATE_MODE : 3;
		unsigned int                                 : 13;
		unsigned int   MASTER_UPDATE_INTERLACED_MODE : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAX_LATENCY {
	struct {
		unsigned int                         MAX_LAT : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_CONTROL__SI__VI {
	struct {
                unsigned int                  MCIF_BUFF_SIZE : 2;
                unsigned int                                 : 2;
                unsigned int      ADDRESS_TRANSLATION_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int        PRIVILEGED_ACCESS_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int      MCIF_SLOW_REQ_INTERVAL__VI : 4;
                unsigned int              LOW_READ_URG_LEVEL : 8;
                unsigned int       MC_CLEAN_DEASSERT_LATENCY : 6;
                unsigned int  MCIF_MC_LATENCY_COUNTER_ENABLE : 1;
                unsigned int MCIF_MC_LATENCY_COUNTER_URGENT_ONLY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int            MCIF_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int           MCIF_TEST_DEBUG_INDEX : 8;
                unsigned int        MCIF_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WRITE_COMBINE_CONTROL__SI__VI {
	struct {
                unsigned int      MCIF_WRITE_COMBINE_TIMEOUT : 8;
                unsigned int       VIP_WRITE_COMBINE_TIMEOUT : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCLK_PWRMGT_CNTL__SI__CI {
	struct {
		unsigned int                       DLL_SPEED : 5;
		unsigned int                                 : 1;
		unsigned int                       DLL_READY : 1;
		unsigned int                     MC_INT_CNTL : 1;
		unsigned int                     MRDCK0_PDNB : 1;
		unsigned int                     MRDCK1_PDNB : 1;
		unsigned int                                 : 6;
		unsigned int                    MRDCK0_RESET : 1;
		unsigned int                    MRDCK1_RESET : 1;
		unsigned int                                 : 6;
		unsigned int                  DLL_READY_READ : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_ADDR_HASH {
	struct {
		unsigned int                 BANK_XOR_ENABLE : 4;
		unsigned int                         COL_XOR : 8;
		unsigned int                         ROW_XOR : 16;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_ADDR_SWIZ0__CI__VI {
	struct {
                unsigned int                              A8 : 4;
                unsigned int                              A9 : 4;
                unsigned int                             A10 : 4;
                unsigned int                             A11 : 4;
                unsigned int                             A12 : 4;
                unsigned int                             A13 : 4;
                unsigned int                             A14 : 4;
                unsigned int                             A15 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_ADDR_SWIZ1__CI__VI {
	struct {
                unsigned int                             A16 : 4;
                unsigned int                             A17 : 4;
                unsigned int                             A18 : 4;
                unsigned int                             A19 : 4;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_AGE_CNTL__CI__VI {
	struct {
                unsigned int                 RESET_RD_GROUP0 : 1;
                unsigned int                 RESET_RD_GROUP1 : 1;
                unsigned int                 RESET_RD_GROUP2 : 1;
                unsigned int                 RESET_RD_GROUP3 : 1;
                unsigned int                 RESET_RD_GROUP4 : 1;
                unsigned int                 RESET_RD_GROUP5 : 1;
                unsigned int                 RESET_RD_GROUP6 : 1;
                unsigned int                 RESET_RD_GROUP7 : 1;
                unsigned int                 RESET_WR_GROUP0 : 1;
                unsigned int                 RESET_WR_GROUP1 : 1;
                unsigned int                 RESET_WR_GROUP2 : 1;
                unsigned int                 RESET_WR_GROUP3 : 1;
                unsigned int                 RESET_WR_GROUP4 : 1;
                unsigned int                 RESET_WR_GROUP5 : 1;
                unsigned int                 RESET_WR_GROUP6 : 1;
                unsigned int                 RESET_WR_GROUP7 : 1;
                unsigned int                 AGE_LOW_RATE_RD : 3;
                unsigned int                 AGE_LOW_RATE_WR : 3;
                unsigned int              TIMER_STALL_RD__VI : 1;
                unsigned int              TIMER_STALL_WR__VI : 1;
                unsigned int            EXTEND_WEIGHT_RD__VI : 1;
                unsigned int            EXTEND_WEIGHT_WR__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_AGE_RD {
	struct {
		unsigned int                     RATE_GROUP0 : 2;
		unsigned int                     RATE_GROUP1 : 2;
		unsigned int                     RATE_GROUP2 : 2;
		unsigned int                     RATE_GROUP3 : 2;
		unsigned int                     RATE_GROUP4 : 2;
		unsigned int                     RATE_GROUP5 : 2;
		unsigned int                     RATE_GROUP6 : 2;
		unsigned int                     RATE_GROUP7 : 2;
		unsigned int                   ENABLE_GROUP0 : 1;
		unsigned int                   ENABLE_GROUP1 : 1;
		unsigned int                   ENABLE_GROUP2 : 1;
		unsigned int                   ENABLE_GROUP3 : 1;
		unsigned int                   ENABLE_GROUP4 : 1;
		unsigned int                   ENABLE_GROUP5 : 1;
		unsigned int                   ENABLE_GROUP6 : 1;
		unsigned int                   ENABLE_GROUP7 : 1;
		unsigned int                   DIVIDE_GROUP0 : 1;
		unsigned int                   DIVIDE_GROUP1 : 1;
		unsigned int                   DIVIDE_GROUP2 : 1;
		unsigned int                   DIVIDE_GROUP3 : 1;
		unsigned int                   DIVIDE_GROUP4 : 1;
		unsigned int                   DIVIDE_GROUP5 : 1;
		unsigned int                   DIVIDE_GROUP6 : 1;
		unsigned int                   DIVIDE_GROUP7 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_AGE_WR {
	struct {
		unsigned int                     RATE_GROUP0 : 2;
		unsigned int                     RATE_GROUP1 : 2;
		unsigned int                     RATE_GROUP2 : 2;
		unsigned int                     RATE_GROUP3 : 2;
		unsigned int                     RATE_GROUP4 : 2;
		unsigned int                     RATE_GROUP5 : 2;
		unsigned int                     RATE_GROUP6 : 2;
		unsigned int                     RATE_GROUP7 : 2;
		unsigned int                   ENABLE_GROUP0 : 1;
		unsigned int                   ENABLE_GROUP1 : 1;
		unsigned int                   ENABLE_GROUP2 : 1;
		unsigned int                   ENABLE_GROUP3 : 1;
		unsigned int                   ENABLE_GROUP4 : 1;
		unsigned int                   ENABLE_GROUP5 : 1;
		unsigned int                   ENABLE_GROUP6 : 1;
		unsigned int                   ENABLE_GROUP7 : 1;
		unsigned int                   DIVIDE_GROUP0 : 1;
		unsigned int                   DIVIDE_GROUP1 : 1;
		unsigned int                   DIVIDE_GROUP2 : 1;
		unsigned int                   DIVIDE_GROUP3 : 1;
		unsigned int                   DIVIDE_GROUP4 : 1;
		unsigned int                   DIVIDE_GROUP5 : 1;
		unsigned int                   DIVIDE_GROUP6 : 1;
		unsigned int                   DIVIDE_GROUP7 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_BANKMAP {
	struct {
		unsigned int                           BANK0 : 4;
		unsigned int                           BANK1 : 4;
		unsigned int                           BANK2 : 4;
		unsigned int                           BANK3 : 4;
		unsigned int                            RANK : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_BURST_TIME {
	struct {
		unsigned int                          STATE0 : 5;
		unsigned int                          STATE1 : 5;
		unsigned int                          STATE2 : 5;
		unsigned int                          STATE3 : 5;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_BUSY_STATUS__CI {
	struct {
		unsigned int                          LM_RD0 : 1;
		unsigned int                          LM_RD1 : 1;
		unsigned int                          LM_WR0 : 1;
		unsigned int                          LM_WR1 : 1;
		unsigned int                          HM_RD0 : 1;
		unsigned int                          HM_RD1 : 1;
		unsigned int                          HM_WR0 : 1;
		unsigned int                          HM_WR1 : 1;
		unsigned int                         WDE_RD0 : 1;
		unsigned int                         WDE_RD1 : 1;
		unsigned int                         WDE_WR0 : 1;
		unsigned int                         WDE_WR1 : 1;
		unsigned int                            POP0 : 1;
		unsigned int                            POP1 : 1;
		unsigned int                        TAGFIFO0 : 1;
		unsigned int                        TAGFIFO1 : 1;
		unsigned int                         REPLAY0 : 1;
		unsigned int                         REPLAY1 : 1;
		unsigned int                          RDRET0 : 1;
		unsigned int                          RDRET1 : 1;
		unsigned int                       GECC2_RD0 : 1;
		unsigned int                       GECC2_RD1 : 1;
		unsigned int                       GECC2_WR0 : 1;
		unsigned int                       GECC2_WR1 : 1;
		unsigned int                           WCDR0 : 1;
		unsigned int                           WCDR1 : 1;
		unsigned int                            RTT0 : 1;
		unsigned int                            RTT1 : 1;
		unsigned int                         REM_RD0 : 1;
		unsigned int                         REM_RD1 : 1;
		unsigned int                         REM_WR0 : 1;
		unsigned int                         REM_WR1 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_BUSY_STATUS__VI {
	struct {
		unsigned int                          LM_RD0 : 1;
		unsigned int                          LM_RD1 : 1;
		unsigned int                          LM_WR0 : 1;
		unsigned int                          LM_WR1 : 1;
		unsigned int                          HM_RD0 : 1;
		unsigned int                          HM_RD1 : 1;
		unsigned int                          HM_WR0 : 1;
		unsigned int                          HM_WR1 : 1;
		unsigned int                         WDE_RD0 : 1;
		unsigned int                         WDE_RD1 : 1;
		unsigned int                         WDE_WR0 : 1;
		unsigned int                         WDE_WR1 : 1;
		unsigned int                            POP0 : 1;
		unsigned int                            POP1 : 1;
		unsigned int                        TAGFIFO0 : 1;
		unsigned int                        TAGFIFO1 : 1;
		unsigned int                         REPLAY0 : 1;
		unsigned int                         REPLAY1 : 1;
		unsigned int                          RDRET0 : 1;
		unsigned int                          RDRET1 : 1;
		unsigned int                       GECC2_RD0 : 1;
		unsigned int                       GECC2_RD1 : 1;
		unsigned int                       GECC2_WR0 : 1;
		unsigned int                       GECC2_WR1 : 1;
		unsigned int                          WRRET0 : 1;
		unsigned int                          WRRET1 : 1;
		unsigned int                            RTT0 : 1;
		unsigned int                            RTT1 : 1;
		unsigned int                         REM_RD0 : 1;
		unsigned int                         REM_RD1 : 1;
		unsigned int                         REM_WR0 : 1;
		unsigned int                         REM_WR1 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_CAC_CNTL {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                     READ_WEIGHT : 6;
		unsigned int                    WRITE_WEIGHT : 6;
		unsigned int                  ALLOW_OVERFLOW : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_CG__CI__VI {
	struct {
                unsigned int                      CG_ARB_REQ : 8;
                unsigned int                     CG_ARB_RESP : 8;
                unsigned int                           RSV_0 : 8;
                unsigned int                           RSV_1 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_CG__SI {
	struct {
		unsigned int                      CG_ARB_REQ : 8;
		unsigned int                     CG_ARB_RESP : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_DRAM_TIMING {
	struct {
		unsigned int                           ACTRD : 8;
		unsigned int                           ACTWR : 8;
		unsigned int                       RASMACTRD : 8;
		unsigned int                       RASMACTWR : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_DRAM_TIMING2 {
	struct {
		unsigned int                         RAS2RAS : 8;
		unsigned int                              RP : 8;
		unsigned int                        WRPLUSRP : 8;
		unsigned int                        BUS_TURN : 5;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_DRAM_TIMING2_1 {
	struct {
		unsigned int                         RAS2RAS : 8;
		unsigned int                              RP : 8;
		unsigned int                        WRPLUSRP : 8;
		unsigned int                        BUS_TURN : 5;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_DRAM_TIMING_1 {
	struct {
		unsigned int                           ACTRD : 8;
		unsigned int                           ACTWR : 8;
		unsigned int                       RASMACTRD : 8;
		unsigned int                       RASMACTWR : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_FED_CNTL {
	struct {
                unsigned int                            MODE : 2;
                unsigned int                          WR_ERR : 2;
                unsigned int             KEEP_POISON_IN_PAGE : 1;
                unsigned int       RDRET_PARITY_NACK__CI__VI : 1;
                unsigned int         USE_LEGACY_NACK__CI__VI : 1;
                unsigned int               DEBUG_RSV__CI__VI : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GDEC_RD_CNTL {
	struct {
		unsigned int                        PAGEBIT0 : 4;
		unsigned int                        PAGEBIT1 : 4;
		unsigned int                        USE_RANK : 1;
		unsigned int                        USE_RSNO : 1;
		unsigned int                 REM_DEFAULT_GRP : 4;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GDEC_WR_CNTL {
	struct {
		unsigned int                        PAGEBIT0 : 4;
		unsigned int                        PAGEBIT1 : 4;
		unsigned int                        USE_RANK : 1;
		unsigned int                        USE_RSNO : 1;
		unsigned int                 REM_DEFAULT_GRP : 4;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GECC2 {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        ECC_MODE : 2;
                unsigned int                       PAGE_BIT0 : 2;
                unsigned int                   EXOR_BANK_SEL : 2;
                unsigned int                     NO_GECC_CLI : 4;
                unsigned int                        READ_ERR : 3;
                unsigned int                  CLOSE_BANK_RMW : 1;
                unsigned int                   COLFIFO_WATER : 6;
                unsigned int             WRADDR_CONV__CI__VI : 1;
                unsigned int      RMWRD_UNCOR_POISON__CI__VI : 1;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GECC2_CLI {
	struct {
		unsigned int                    NO_GECC_CLI0 : 8;
		unsigned int                    NO_GECC_CLI1 : 8;
		unsigned int                    NO_GECC_CLI2 : 8;
		unsigned int                    NO_GECC_CLI3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GECC2_DEBUG {
	struct {
		unsigned int                    NUM_ERR_BITS : 2;
		unsigned int                       DIRECTION : 1;
		unsigned int                      DATA_FIELD : 2;
		unsigned int                    SW_INJECTION : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GECC2_DEBUG2 {
	struct {
		unsigned int                          PERIOD : 8;
		unsigned int                      ERR0_START : 8;
		unsigned int                      ERR1_START : 8;
		unsigned int                      ERR2_START : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GECC2_MISC__SI__CI {
	struct {
                unsigned int                    STREAK_BREAK : 4;
                unsigned int                  COL10_HACK__CI : 1;
                unsigned int              CWRD_IN_REPLAY__CI : 1;
                unsigned int     NO_EOB_ALL_WR_IN_REPLAY__CI : 1;
                unsigned int                   DEBUG_RSV__CI : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GECC2_MISC__VI {
	struct {
		unsigned int                    STREAK_BREAK : 4;
		unsigned int                      COL10_HACK : 1;
		unsigned int                  CWRD_IN_REPLAY : 1;
		unsigned int         NO_EOB_ALL_WR_IN_REPLAY : 1;
		unsigned int                 RMW_LM_WR_STALL : 1;
		unsigned int               RMW_STALL_RELEASE : 1;
		unsigned int              WR_EDC_MASK_REPLAY : 1;
		unsigned int               CWRD_REPLAY_AGAIN : 1;
		unsigned int             WRRDWR_REPLAY_AGAIN : 1;
		unsigned int      ALLOW_RMW_ERR_AFTER_REPLAY : 1;
		unsigned int                       DEBUG_RSV : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GECC2_STATUS {
	struct {
                unsigned int                       CORR_STS0 : 1;
                unsigned int                     UNCORR_STS0 : 1;
                unsigned int                        FED_STS0 : 1;
                unsigned int                           RSVD0 : 1;
                unsigned int                       CORR_STS1 : 1;
                unsigned int                     UNCORR_STS1 : 1;
                unsigned int                        FED_STS1 : 1;
                unsigned int                           RSVD1 : 1;
                unsigned int                     CORR_CLEAR0 : 1;
                unsigned int                   UNCORR_CLEAR0 : 1;
                unsigned int                      FED_CLEAR0 : 1;
                unsigned int                           RSVD2 : 1;
                unsigned int                     CORR_CLEAR1 : 1;
                unsigned int                   UNCORR_CLEAR1 : 1;
                unsigned int                      FED_CLEAR1 : 1;
                unsigned int                   RSVD3__CI__VI : 1;
                unsigned int         RMWRD_CORR_STS0__CI__VI : 1;
                unsigned int       RMWRD_UNCORR_STS0__CI__VI : 1;
                unsigned int                   RSVD4__CI__VI : 2;
                unsigned int         RMWRD_CORR_STS1__CI__VI : 1;
                unsigned int       RMWRD_UNCORR_STS1__CI__VI : 1;
                unsigned int                   RSVD5__CI__VI : 2;
                unsigned int       RMWRD_CORR_CLEAR0__CI__VI : 1;
                unsigned int     RMWRD_UNCORR_CLEAR0__CI__VI : 1;
                unsigned int                   RSVD6__CI__VI : 2;
                unsigned int       RMWRD_CORR_CLEAR1__CI__VI : 1;
                unsigned int     RMWRD_UNCORR_CLEAR1__CI__VI : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_BWCNT0_RD__CI__VI {
	struct {
                unsigned int                          GROUP0 : 8;
                unsigned int                          GROUP1 : 8;
                unsigned int                          GROUP2 : 8;
                unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_BWCNT0_WR__CI__VI {
	struct {
                unsigned int                          GROUP0 : 8;
                unsigned int                          GROUP1 : 8;
                unsigned int                          GROUP2 : 8;
                unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_BWCNT1_RD__CI__VI {
	struct {
                unsigned int                          GROUP4 : 8;
                unsigned int                          GROUP5 : 8;
                unsigned int                          GROUP6 : 8;
                unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_BWCNT1_WR__CI__VI {
	struct {
                unsigned int                          GROUP4 : 8;
                unsigned int                          GROUP5 : 8;
                unsigned int                          GROUP6 : 8;
                unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_BWPERIOD0_RD__CI__VI {
	struct {
                unsigned int                          GROUP0 : 8;
                unsigned int                          GROUP1 : 8;
                unsigned int                          GROUP2 : 8;
                unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_BWPERIOD0_WR__CI__VI {
	struct {
                unsigned int                          GROUP0 : 8;
                unsigned int                          GROUP1 : 8;
                unsigned int                          GROUP2 : 8;
                unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_BWPERIOD1_RD__CI__VI {
	struct {
                unsigned int                          GROUP4 : 8;
                unsigned int                          GROUP5 : 8;
                unsigned int                          GROUP6 : 8;
                unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_BWPERIOD1_WR__CI__VI {
	struct {
                unsigned int                          GROUP4 : 8;
                unsigned int                          GROUP5 : 8;
                unsigned int                          GROUP6 : 8;
                unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_CTL_RD__CI__VI {
	struct {
                unsigned int                   FORCE_HIGHEST : 8;
                unsigned int                        HARSH_RR : 1;
                unsigned int                   BANK_AGE_ONLY : 1;
                unsigned int                USE_LEGACY_HARSH : 1;
                unsigned int                   BWCNT_CATCHUP : 1;
                unsigned int                         ST_MODE : 2;
                unsigned int                     FORCE_STALL : 8;
                unsigned int                    PERF_MON_SEL : 3;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_CTL_WR__CI__VI {
	struct {
                unsigned int                   FORCE_HIGHEST : 8;
                unsigned int                        HARSH_RR : 1;
                unsigned int                   BANK_AGE_ONLY : 1;
                unsigned int                USE_LEGACY_HARSH : 1;
                unsigned int                   BWCNT_CATCHUP : 1;
                unsigned int                         ST_MODE : 2;
                unsigned int                     FORCE_STALL : 8;
                unsigned int                    PERF_MON_SEL : 3;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_EN_RD__CI__VI {
	struct {
                unsigned int                          TX_PRI : 8;
                unsigned int                          BW_PRI : 8;
                unsigned int                         FIX_PRI : 8;
                unsigned int                          ST_PRI : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_EN_WR__CI__VI {
	struct {
                unsigned int                          TX_PRI : 8;
                unsigned int                          BW_PRI : 8;
                unsigned int                         FIX_PRI : 8;
                unsigned int                          ST_PRI : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_SAT0_RD__CI__VI {
	struct {
                unsigned int                          GROUP0 : 8;
                unsigned int                          GROUP1 : 8;
                unsigned int                          GROUP2 : 8;
                unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_SAT0_WR__CI__VI {
	struct {
                unsigned int                          GROUP0 : 8;
                unsigned int                          GROUP1 : 8;
                unsigned int                          GROUP2 : 8;
                unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_SAT1_RD__CI__VI {
	struct {
                unsigned int                          GROUP4 : 8;
                unsigned int                          GROUP5 : 8;
                unsigned int                          GROUP6 : 8;
                unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_SAT1_WR__CI__VI {
	struct {
                unsigned int                          GROUP4 : 8;
                unsigned int                          GROUP5 : 8;
                unsigned int                          GROUP6 : 8;
                unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_TX_HI0_RD__CI__VI {
	struct {
                unsigned int                          GROUP0 : 8;
                unsigned int                          GROUP1 : 8;
                unsigned int                          GROUP2 : 8;
                unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_TX_HI0_WR__CI__VI {
	struct {
                unsigned int                          GROUP0 : 8;
                unsigned int                          GROUP1 : 8;
                unsigned int                          GROUP2 : 8;
                unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_TX_HI1_RD__CI__VI {
	struct {
                unsigned int                          GROUP4 : 8;
                unsigned int                          GROUP5 : 8;
                unsigned int                          GROUP6 : 8;
                unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_TX_HI1_WR__CI__VI {
	struct {
                unsigned int                          GROUP4 : 8;
                unsigned int                          GROUP5 : 8;
                unsigned int                          GROUP6 : 8;
                unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_TX_LO0_RD__CI__VI {
	struct {
                unsigned int                          GROUP0 : 8;
                unsigned int                          GROUP1 : 8;
                unsigned int                          GROUP2 : 8;
                unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_TX_LO0_WR__CI__VI {
	struct {
                unsigned int                          GROUP0 : 8;
                unsigned int                          GROUP1 : 8;
                unsigned int                          GROUP2 : 8;
                unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_TX_LO1_RD__CI__VI {
	struct {
                unsigned int                          GROUP4 : 8;
                unsigned int                          GROUP5 : 8;
                unsigned int                          GROUP6 : 8;
                unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_HARSH_TX_LO1_WR__CI__VI {
	struct {
                unsigned int                          GROUP4 : 8;
                unsigned int                          GROUP5 : 8;
                unsigned int                          GROUP6 : 8;
                unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_LAZY0_RD {
	struct {
		unsigned int                          GROUP0 : 8;
		unsigned int                          GROUP1 : 8;
		unsigned int                          GROUP2 : 8;
		unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_LAZY0_WR {
	struct {
		unsigned int                          GROUP0 : 8;
		unsigned int                          GROUP1 : 8;
		unsigned int                          GROUP2 : 8;
		unsigned int                          GROUP3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_LAZY1_RD {
	struct {
		unsigned int                          GROUP4 : 8;
		unsigned int                          GROUP5 : 8;
		unsigned int                          GROUP6 : 8;
		unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_LAZY1_WR {
	struct {
		unsigned int                          GROUP4 : 8;
		unsigned int                          GROUP5 : 8;
		unsigned int                          GROUP6 : 8;
		unsigned int                          GROUP7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_LM_RD {
	struct {
		unsigned int                    STREAK_LIMIT : 8;
		unsigned int               STREAK_LIMIT_UBER : 8;
		unsigned int                    STREAK_BREAK : 1;
		unsigned int                     STREAK_UBER : 1;
		unsigned int                 ENABLE_TWO_LIST : 1;
		unsigned int             POPIDLE_RST_TWOLIST : 1;
		unsigned int               SKID1_RST_TWOLIST : 1;
		unsigned int                BANKGROUP_CONFIG : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_LM_WR {
	struct {
                unsigned int                    STREAK_LIMIT : 8;
                unsigned int               STREAK_LIMIT_UBER : 8;
                unsigned int                    STREAK_BREAK : 1;
                unsigned int                     STREAK_UBER : 1;
                unsigned int                 ENABLE_TWO_LIST : 1;
                unsigned int             POPIDLE_RST_TWOLIST : 1;
                unsigned int               SKID1_RST_TWOLIST : 1;
                unsigned int                BANKGROUP_CONFIG : 3;
                unsigned int               MASKWR_LM_EOB__VI : 1;
                unsigned int               ATOMIC_LM_EOB__VI : 1;
                unsigned int           ATOMIC_RTN_LM_EOB__VI : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_MAX_LAT_CID__CI__VI {
	struct {
                unsigned int                         CID_CH0 : 8;
                unsigned int                         CID_CH1 : 8;
                unsigned int                       WRITE_CH0 : 1;
                unsigned int                       WRITE_CH1 : 1;
                unsigned int                    REALTIME_CH0 : 1;
                unsigned int                    REALTIME_CH1 : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_MAX_LAT_RSLT0__CI__VI {
	struct {
                unsigned int                     MAX_LATENCY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_MAX_LAT_RSLT1__CI__VI {
	struct {
                unsigned int                     MAX_LATENCY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_MINCLKS {
	struct {
                unsigned int                       READ_CLKS : 8;
                unsigned int                      WRITE_CLKS : 8;
                unsigned int                   ARB_RW_SWITCH : 1;
                unsigned int         RW_SWITCH_HARSH__CI__VI : 2;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_MISC {
	struct {
                unsigned int                     STICKY_RFSH : 1;
                unsigned int                       IDLE_RFSH : 1;
                unsigned int                    STUTTER_RFSH : 1;
                unsigned int                     CHAN_COUPLE : 8;
                unsigned int                       HARSHNESS : 8;
                unsigned int                   SMART_RDWR_SW : 1;
                unsigned int                     CALI_ENABLE : 1;
                unsigned int                      CALI_RATES : 2;
                unsigned int                DISPURGVLD_NOWRT : 1;
                unsigned int                 DISPURG_NOSW2WR : 1;
                unsigned int                   DISPURG_STALL : 1;
                unsigned int                DISPURG_THROTTLE : 4;
                unsigned int           EXTEND_WEIGHT__CI__VI : 1;
                unsigned int            ACPURG_STALL__CI__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_MISC2 {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int      TCCDL4_BANKBIT3_XOR_ENABLE : 1;
		unsigned int     TCCDL4_BANKBIT3_XOR_COLBIT4 : 1;
		unsigned int     TCCDL4_BANKBIT3_XOR_COLBIT5 : 1;
		unsigned int     TCCDL4_BANKBIT3_XOR_COLBIT6 : 1;
		unsigned int     TCCDL4_BANKBIT3_XOR_COLBIT7 : 1;
		unsigned int     TCCDL4_BANKBIT3_XOR_COLBIT8 : 1;
		unsigned int                 POP_IDLE_REPLAY : 1;
		unsigned int             RDRET_NO_REORDERING : 1;
		unsigned int                     RDRET_NO_BP : 1;
		unsigned int                  RDRET_SEQ_SKID : 4;
		unsigned int                            GECC : 1;
		unsigned int                        GECC_RST : 1;
		unsigned int                     GECC_STATUS : 1;
		unsigned int               TAGFIFO_THRESHOLD : 4;
		unsigned int             WCDR_REPLAY_MASKCNT : 3;
		unsigned int                    REPLAY_DEBUG : 1;
		unsigned int                     ARB_DEBUG29 : 1;
		unsigned int                SEQ_RDY_POP_IDLE : 1;
		unsigned int               TCCDL4_REPLAY_EOB : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_MISC3__CI {
	struct {
		unsigned int                 NO_GECC_EXT_EOB : 1;
		unsigned int                       TBD_FIELD : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_MISC3__VI {
	struct {
		unsigned int                 NO_GECC_EXT_EOB : 1;
		unsigned int                        CHAN4_EN : 1;
		unsigned int                   CHAN4_ARB_SEL : 1;
		unsigned int                    UVD_URG_MODE : 1;
		unsigned int            UVD_DMIF_HARSH_WT_EN : 1;
		unsigned int                       TBD_FIELD : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PERFCOUNTER0_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PERFCOUNTER1_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PERFCOUNTER2_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PERFCOUNTER3_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                      COUNTER_HI : 16;
                unsigned int                   COMPARE_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                      COUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PERFCOUNTER_RSLT_CNTL__CI__VI {
	struct {
                unsigned int             PERF_COUNTER_SELECT : 4;
                unsigned int                                 : 4;
                unsigned int                   START_TRIGGER : 8;
                unsigned int                    STOP_TRIGGER : 8;
                unsigned int                      ENABLE_ANY : 1;
                unsigned int                       CLEAR_ALL : 1;
                unsigned int            STOP_ALL_ON_SATURATE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PERF_MON_CNTL0_ECC__CI {
	struct {
		unsigned int                      ALLOW_WRAP : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PERF_MON_CNTL0__SI {
	struct {
		unsigned int                                 : 12;
		unsigned int                                 : 12;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PM_CNTL__CI {
	struct {
		unsigned int                OVERRIDE_CGSTATE : 2;
		unsigned int                     OVRR_CGRFSH : 1;
		unsigned int                      OVRR_CGSQM : 1;
		unsigned int                     SRFSH_ON_D1 : 1;
		unsigned int                    BLKOUT_ON_D1 : 1;
		unsigned int                      IDLE_ON_D1 : 1;
		unsigned int                         OVRR_PM : 1;
		unsigned int                   OVRR_PM_STATE : 2;
		unsigned int                         OVRR_RD : 1;
		unsigned int                   OVRR_RD_STATE : 1;
		unsigned int                         OVRR_WR : 1;
		unsigned int                   OVRR_WR_STATE : 1;
		unsigned int                       OVRR_RFSH : 1;
		unsigned int                 OVRR_RFSH_STATE : 1;
		unsigned int                           RSV_0 : 2;
		unsigned int                      IDLE_ON_D2 : 1;
		unsigned int                      IDLE_ON_D3 : 1;
		unsigned int                        IDLE_CNT : 4;
		unsigned int                           RSV_1 : 1;
		unsigned int                           RSV_2 : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PM_CNTL__VI {
	struct {
		unsigned int                OVERRIDE_CGSTATE : 2;
		unsigned int                     OVRR_CGRFSH : 1;
		unsigned int                      OVRR_CGSQM : 1;
		unsigned int                     SRFSH_ON_D1 : 1;
		unsigned int                    BLKOUT_ON_D1 : 1;
		unsigned int                      IDLE_ON_D1 : 1;
		unsigned int                         OVRR_PM : 1;
		unsigned int                   OVRR_PM_STATE : 2;
		unsigned int                         OVRR_RD : 1;
		unsigned int                   OVRR_RD_STATE : 1;
		unsigned int                         OVRR_WR : 1;
		unsigned int                   OVRR_WR_STATE : 1;
		unsigned int                       OVRR_RFSH : 1;
		unsigned int                 OVRR_RFSH_STATE : 1;
		unsigned int                   OVRR_RD0_BUSY : 1;
		unsigned int                   OVRR_RD1_BUSY : 1;
		unsigned int                      IDLE_ON_D2 : 1;
		unsigned int                      IDLE_ON_D3 : 1;
		unsigned int                        IDLE_CNT : 4;
		unsigned int                   OVRR_WR0_BUSY : 1;
		unsigned int                   OVRR_WR1_BUSY : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PM_CNTL__SI {
	struct {
		unsigned int                OVERRIDE_CGSTATE : 2;
		unsigned int                     OVRR_CGRFSH : 1;
		unsigned int                      OVRR_CGSQM : 1;
		unsigned int                     SRFSH_ON_D1 : 1;
		unsigned int                    BLKOUT_ON_D1 : 1;
		unsigned int                      IDLE_ON_D1 : 1;
		unsigned int                         OVRR_PM : 1;
		unsigned int                   OVRR_PM_STATE : 2;
		unsigned int                         OVRR_RD : 1;
		unsigned int                   OVRR_RD_STATE : 1;
		unsigned int                         OVRR_WR : 1;
		unsigned int                   OVRR_WR_STATE : 1;
		unsigned int                       OVRR_RFSH : 1;
		unsigned int                 OVRR_RFSH_STATE : 1;
		unsigned int                                 : 2;
		unsigned int                      IDLE_ON_D2 : 1;
		unsigned int                      IDLE_ON_D3 : 1;
		unsigned int                        IDLE_CNT : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_POP {
	struct {
		unsigned int                      ENABLE_ARB : 1;
		unsigned int                       SPEC_OPEN : 1;
		unsigned int                       POP_DEPTH : 4;
		unsigned int               WRDATAINDEX_DEPTH : 6;
		unsigned int                      SKID_DEPTH : 3;
		unsigned int                 WAIT_AFTER_RFSH : 2;
		unsigned int                      QUICK_STOP : 1;
		unsigned int                 ENABLE_TWO_PAGE : 1;
		unsigned int        ALLOW_EOB_BY_WRRET_STALL : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RAMCFG__CI__VI {
	struct {
                unsigned int                        NOOFBANK : 2;
                unsigned int                       NOOFRANKS : 1;
                unsigned int                        NOOFROWS : 3;
                unsigned int                        NOOFCOLS : 2;
                unsigned int                        CHANSIZE : 1;
                unsigned int                           RSV_1 : 1;
                unsigned int                           RSV_2 : 1;
                unsigned int                           RSV_3 : 1;
                unsigned int                      NOOFGROUPS : 1;
                unsigned int                           RSV_4 : 5;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RAMCFG__SI {
	struct {
		unsigned int                        NOOFBANK : 2;
		unsigned int                       NOOFRANKS : 1;
		unsigned int                        NOOFROWS : 3;
		unsigned int                        NOOFCOLS : 2;
		unsigned int                        CHANSIZE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                      NOOFGROUPS : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_REMREQ {
	struct {
                unsigned int                        RD_WATER : 8;
                unsigned int                        WR_WATER : 8;
                unsigned int                WR_MAXBURST_SIZE : 4;
                unsigned int                   WR_LAZY_TIMER : 4;
                unsigned int      ENABLE_REMOTE_NACK_REQ__VI : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_REPLAY {
	struct {
                unsigned int                       ENABLE_RD : 1;
                unsigned int                       ENABLE_WR : 1;
                unsigned int                      WRACK_MODE : 1;
                unsigned int                      WAW_ENABLE : 1;
                unsigned int                      RAW_ENABLE : 1;
                unsigned int                   IGNORE_WR_CDC : 1;
                unsigned int                  BREAK_ON_STALL : 1;
                unsigned int             BOS_ENABLE_WAIT_CYC : 1;
                unsigned int                    BOS_WAIT_CYC : 7;
                unsigned int  NO_PCH_AT_REPLAY_START__CI__VI : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RET_CREDITS2__CI__VI {
	struct {
                unsigned int                          ACP_WR : 8;
                unsigned int         NECKDOWN_CNTR_EN_RD__VI : 1;
                unsigned int         NECKDOWN_CNTR_EN_WR__VI : 1;
                unsigned int               ACP_RDRET_URG__VI : 1;
                unsigned int               HDP_RDRET_URG__VI : 1;
                unsigned int    NECKDOWN_CNTR_MONITOR_RD__VI : 1;
                unsigned int    NECKDOWN_CNTR_MONITOR_WR__VI : 1;
                unsigned int         DISABLE_DISP_RDY_RD__VI : 1;
                unsigned int          DISABLE_ACP_RDY_WR__VI : 1;
                unsigned int            RDRET_CREDIT_MED__VI : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RET_CREDITS_RD {
	struct {
		unsigned int                             LCL : 8;
		unsigned int                             HUB : 8;
		unsigned int                            DISP : 8;
		unsigned int                   RETURN_CREDIT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RET_CREDITS_WR {
	struct {
                unsigned int                             LCL : 8;
                unsigned int                             HUB : 8;
                unsigned int                   RETURN_CREDIT : 8;
                unsigned int                  WRRET_SEQ_SKID : 4;
                unsigned int                    WRRET_BP__VI : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RFSH_CNTL {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                            URG0 : 5;
                unsigned int                            URG1 : 5;
                unsigned int                           ACCUM : 1;
                unsigned int                 SINGLE_BANK__VI : 1;
                unsigned int    PUSH_SINGLE_BANK_REFRESH__VI : 1;
                unsigned int            PENDING_RATE_SEL__VI : 3;
                unsigned int              REFSB_PER_PAGE__VI : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RFSH_RATE {
	struct {
                unsigned int                      POWERMODE0 : 8;
                unsigned int                                 : 8;
                unsigned int                                 : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RTT_CNTL0 {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                      START_IDLE : 1;
		unsigned int                       START_R2W : 2;
		unsigned int                  FLUSH_ON_ENTER : 1;
		unsigned int                     HARSH_START : 1;
		unsigned int              TPS_HARSH_PRIORITY : 1;
		unsigned int             TWRT_HARSH_PRIORITY : 1;
		unsigned int                  BREAK_ON_HARSH : 1;
		unsigned int               BREAK_ON_URGENTRD : 1;
		unsigned int               BREAK_ON_URGENTWR : 1;
		unsigned int                    TRAIN_PERIOD : 3;
		unsigned int                  START_R2W_RFSH : 1;
		unsigned int                     DEBUG_RSV_0 : 1;
		unsigned int                     DEBUG_RSV_1 : 1;
		unsigned int                     DEBUG_RSV_2 : 1;
		unsigned int                     DEBUG_RSV_3 : 1;
		unsigned int                     DEBUG_RSV_4 : 1;
		unsigned int                     DEBUG_RSV_5 : 1;
		unsigned int                     DEBUG_RSV_6 : 1;
		unsigned int                     DEBUG_RSV_7 : 1;
		unsigned int                     DEBUG_RSV_8 : 1;
		unsigned int                       DATA_CNTL : 1;
		unsigned int                    NEIGHBOR_BIT : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RTT_CNTL1 {
	struct {
		unsigned int                     WINDOW_SIZE : 5;
		unsigned int                   WINDOW_UPDATE : 1;
		unsigned int            WINDOW_INC_THRESHOLD : 7;
		unsigned int            WINDOW_DEC_THRESHOLD : 7;
		unsigned int                 WINDOW_SIZE_MAX : 5;
		unsigned int                 WINDOW_SIZE_MIN : 5;
		unsigned int             WINDOW_UPDATE_COUNT : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RTT_CNTL2 {
	struct {
		unsigned int                      SAMPLE_CNT : 6;
		unsigned int          PHASE_ADJUST_THRESHOLD : 6;
		unsigned int               PHASE_ADJUST_SIZE : 1;
		unsigned int                     FILTER_CNTL : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RTT_DATA {
	struct {
		unsigned int                         PATTERN : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_RTT_DEBUG {
	struct {
		unsigned int                  DEBUG_BYTE_CH0 : 2;
		unsigned int                  DEBUG_BYTE_CH1 : 2;
		unsigned int               SHIFTED_PHASE_CH0 : 8;
		unsigned int                 WINDOW_SIZE_CH0 : 5;
		unsigned int               SHIFTED_PHASE_CH1 : 8;
		unsigned int                 WINDOW_SIZE_CH1 : 5;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_SQM_CNTL__CI__VI {
	struct {
                unsigned int                       MIN_PENAL : 8;
                unsigned int                  DYN_SQM_ENABLE : 1;
                unsigned int                       SQM_RDY16 : 1;
                unsigned int                     SQM_RESERVE : 6;
                unsigned int                           RATIO : 8;
                unsigned int                     RATIO_DEBUG : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_SQM_CNTL__SI {
	struct {
		unsigned int                       MIN_PENAL : 8;
		unsigned int                  DYN_SQM_ENABLE : 1;
		unsigned int                     SQM_RESERVE : 7;
		unsigned int                           RATIO : 8;
		unsigned int                     RATIO_DEBUG : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_SSM__CI {
	struct {
		unsigned int                          FORMAT : 5;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_TM_CNTL_RD {
	struct {
		unsigned int                    GROUPBY_RANK : 1;
		unsigned int                     BANK_SELECT : 2;
		unsigned int                      MATCH_RANK : 1;
		unsigned int                      MATCH_BANK : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_TM_CNTL_WR {
	struct {
		unsigned int                    GROUPBY_RANK : 1;
		unsigned int                     BANK_SELECT : 2;
		unsigned int                      MATCH_RANK : 1;
		unsigned int                      MATCH_BANK : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_WCDR__SI__CI {
	struct {
		unsigned int                     IDLE_ENABLE : 1;
		unsigned int                        SEQ_IDLE : 1;
		unsigned int                     IDLE_PERIOD : 5;
		unsigned int                      IDLE_BURST : 6;
		unsigned int                 IDLE_BURST_MODE : 1;
		unsigned int                     IDLE_WAKEUP : 2;
		unsigned int            IDLE_DEGLITCH_ENABLE : 1;
		unsigned int                     WPRE_ENABLE : 1;
		unsigned int                  WPRE_THRESHOLD : 4;
		unsigned int                  WPRE_MAX_BURST : 3;
		unsigned int                   WPRE_INC_READ : 1;
		unsigned int               WPRE_INC_SKIDIDLE : 1;
		unsigned int                WPRE_INC_SEQIDLE : 1;
		unsigned int                    WPRE_TWOPAGE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_WCDR_2__SI__CI {
	struct {
		unsigned int                   WPRE_INC_STEP : 4;
		unsigned int              WPRE_MIN_THRESHOLD : 5;
		unsigned int                         DEBUG_0 : 1;
		unsigned int                         DEBUG_1 : 1;
		unsigned int                         DEBUG_2 : 1;
		unsigned int                         DEBUG_3 : 1;
		unsigned int                         DEBUG_4 : 1;
		unsigned int                         DEBUG_5 : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_WTM_CNTL_RD {
	struct {
                unsigned int                          WTMODE : 2;
                unsigned int                       HARSH_PRI : 1;
                unsigned int              ALLOW_STUTTER_GRP0 : 1;
                unsigned int              ALLOW_STUTTER_GRP1 : 1;
                unsigned int              ALLOW_STUTTER_GRP2 : 1;
                unsigned int              ALLOW_STUTTER_GRP3 : 1;
                unsigned int              ALLOW_STUTTER_GRP4 : 1;
                unsigned int              ALLOW_STUTTER_GRP5 : 1;
                unsigned int              ALLOW_STUTTER_GRP6 : 1;
                unsigned int              ALLOW_STUTTER_GRP7 : 1;
                unsigned int           ACP_HARSH_PRI__CI__VI : 1;
                unsigned int           ACP_OVER_DISP__CI__VI : 1;
                unsigned int           FORCE_ACP_URG__CI__VI : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_WTM_CNTL_WR {
	struct {
                unsigned int                          WTMODE : 2;
                unsigned int                       HARSH_PRI : 1;
                unsigned int              ALLOW_STUTTER_GRP0 : 1;
                unsigned int              ALLOW_STUTTER_GRP1 : 1;
                unsigned int              ALLOW_STUTTER_GRP2 : 1;
                unsigned int              ALLOW_STUTTER_GRP3 : 1;
                unsigned int              ALLOW_STUTTER_GRP4 : 1;
                unsigned int              ALLOW_STUTTER_GRP5 : 1;
                unsigned int              ALLOW_STUTTER_GRP6 : 1;
                unsigned int              ALLOW_STUTTER_GRP7 : 1;
                unsigned int           ACP_HARSH_PRI__CI__VI : 1;
                unsigned int           ACP_OVER_DISP__CI__VI : 1;
                unsigned int           FORCE_ACP_URG__CI__VI : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_WTM_GRPWT_RD {
	struct {
		unsigned int                            GRP0 : 2;
		unsigned int                            GRP1 : 2;
		unsigned int                            GRP2 : 2;
		unsigned int                            GRP3 : 2;
		unsigned int                            GRP4 : 2;
		unsigned int                            GRP5 : 2;
		unsigned int                            GRP6 : 2;
		unsigned int                            GRP7 : 2;
		unsigned int                         GRP_EXT : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_WTM_GRPWT_WR {
	struct {
		unsigned int                            GRP0 : 2;
		unsigned int                            GRP1 : 2;
		unsigned int                            GRP2 : 2;
		unsigned int                            GRP3 : 2;
		unsigned int                            GRP4 : 2;
		unsigned int                            GRP5 : 2;
		unsigned int                            GRP6 : 2;
		unsigned int                            GRP7 : 2;
		unsigned int                         GRP_EXT : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_AUTO_CNTL__SI__CI {
	struct {
		unsigned int                             MOP : 2;
		unsigned int                                 : 2;
		unsigned int                         ADR_GEN : 4;
		unsigned int                        LFSR_KEY : 16;
		unsigned int                      LFSR_RESET : 1;
		unsigned int                       ADR_RESET : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_CMD_CNTL__SI__CI {
	struct {
		unsigned int                           RESET : 1;
		unsigned int                  CMD_ISSUE_MODE : 1;
		unsigned int                  CMD_ISSUE_LOOP : 1;
		unsigned int              LOOP_END_CONDITION : 1;
		unsigned int                    LOOP_CNT_MAX : 12;
		unsigned int                CMD_ISSUE_MODE_U : 1;
		unsigned int                   CMD_ISSUE_RUN : 1;
		unsigned int                     LOOP_CNT_RD : 10;
		unsigned int                       ENABLE_D0 : 1;
		unsigned int                       ENABLE_D1 : 1;
		unsigned int                       STATUS_CH : 1;
		unsigned int                            DONE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_CMP_CNTL__SI__CI {
	struct {
		unsigned int                   CMP_MASK_BYTE : 4;
		unsigned int                    CMP_MASK_BIT : 8;
		unsigned int                      LOAD_RTEDC : 1;
		unsigned int                  DATA_STORE_SEL : 1;
		unsigned int                   EDC_STORE_SEL : 1;
		unsigned int                 ENABLE_CMD_FIFO : 1;
		unsigned int                             CMP : 2;
		unsigned int                        DAT_MODE : 1;
		unsigned int                  EDC_STORE_MODE : 1;
		unsigned int                 DATA_STORE_MODE : 2;
		unsigned int                    MISMATCH_CNT : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_CMP_CNTL_2__SI__CI {
	struct {
		unsigned int                  DATA_STORE_CNT : 5;
		unsigned int                                 : 3;
		unsigned int              DATA_STORE_CNT_RST : 1;
		unsigned int                                 : 3;
		unsigned int                   EDC_STORE_CNT : 5;
		unsigned int                                 : 3;
		unsigned int               EDC_STORE_CNT_RST : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_CNTL__SI__CI {
	struct {
		unsigned int                           RESET : 1;
		unsigned int                             RUN : 1;
		unsigned int                      PTR_RST_D0 : 1;
		unsigned int                      PTR_RST_D1 : 1;
		unsigned int                        MOP_MODE : 1;
		unsigned int                        ADR_MODE : 1;
		unsigned int                        DAT_MODE : 1;
		unsigned int                                 : 3;
		unsigned int                            LOOP : 2;
		unsigned int                       ENABLE_D0 : 1;
		unsigned int                       ENABLE_D1 : 1;
		unsigned int                  LOAD_RTDATA_CH : 1;
		unsigned int                                 : 1;
		unsigned int                        LOOP_CNT : 12;
		unsigned int                                 : 2;
		unsigned int                            DONE : 1;
		unsigned int                     LOAD_RTDATA : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_CNTL__VI {
	struct {
		unsigned int                           RESET : 1;
		unsigned int                             RUN : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                        LOOP_CNT : 12;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DATA_MASK__SI__CI {
	struct {
		unsigned int                            MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DATA_WORD0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DATA_WORD1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DATA_WORD2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DATA_WORD3 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DATA_WORD4 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DATA_WORD5 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DATA_WORD6 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DATA_WORD7 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DIR_CNTL__SI__CI {
	struct {
		unsigned int                             MOP : 3;
		unsigned int                             EOB : 1;
		unsigned int                        MOP_LOAD : 1;
		unsigned int                       DATA_LOAD : 1;
		unsigned int                      CMD_RTR_D0 : 1;
		unsigned int                      DAT_RTR_D0 : 1;
		unsigned int                      CMD_RTR_D1 : 1;
		unsigned int                      DAT_RTR_D1 : 1;
		unsigned int                            MOP3 : 1;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_EADDR__SI__CI {
	struct {
		unsigned int                             COL : 10;
		unsigned int                             ROW : 14;
		unsigned int                            BANK : 4;
		unsigned int                            RANK : 1;
		unsigned int                            COLH : 1;
		unsigned int                            ROWH : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_MISMATCH_ADDR__SI__CI {
	struct {
		unsigned int                             COL : 10;
		unsigned int                             ROW : 14;
		unsigned int                            BANK : 4;
		unsigned int                            RANK : 1;
		unsigned int                            COLH : 1;
		unsigned int                            ROWH : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_MISMATCH_ADDR__VI {
	struct {
		unsigned int                             COL : 8;
		unsigned int                             ROW : 16;
		unsigned int                            BANK : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_RDATA_EDC__SI__CI {
	struct {
		unsigned int                             EDC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_RDATA_MASK__SI__CI {
	struct {
		unsigned int                            MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_RDATA_WORD0 {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_RDATA_WORD1 {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_RDATA_WORD2 {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_RDATA_WORD3 {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_RDATA_WORD4 {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_RDATA_WORD5 {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_RDATA_WORD6 {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_RDATA_WORD7 {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_SADDR__SI__CI {
	struct {
		unsigned int                             COL : 10;
		unsigned int                             ROW : 14;
		unsigned int                            BANK : 4;
		unsigned int                            RANK : 1;
		unsigned int                            COLH : 1;
		unsigned int                            ROWH : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CG_CONFIG {
	struct {
		unsigned int                  MCDW_WR_ENABLE : 1;
		unsigned int                  MCDX_WR_ENABLE : 1;
		unsigned int                  MCDY_WR_ENABLE : 1;
		unsigned int                  MCDZ_WR_ENABLE : 1;
		unsigned int                    MC_RD_ENABLE : 2;
		unsigned int                           INDEX : 16;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CG_CONFIG_MCD {
	struct {
                unsigned int                  MCD0_WR_ENABLE : 1;
                unsigned int                  MCD1_WR_ENABLE : 1;
                unsigned int                  MCD2_WR_ENABLE : 1;
                unsigned int                  MCD3_WR_ENABLE : 1;
                unsigned int                  MCD4_WR_ENABLE : 1;
                unsigned int                  MCD5_WR_ENABLE : 1;
                unsigned int              MCD6_WR_ENABLE__VI : 1;
                unsigned int              MCD7_WR_ENABLE__VI : 1;
                unsigned int                    MC_RD_ENABLE : 3;
                unsigned int            MC_RD_ENABLE_SUB__VI : 1;
                unsigned int                                 : 1;
                unsigned int                           INDEX : 16;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CG_DATAPORT {
	struct {
		unsigned int                      DATA_FIELD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_CNTL__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                        IGNOREPM : 1;
		unsigned int                        EXEMPTPM : 1;
		unsigned int               GFX_IDLE_OVERRIDE : 2;
		unsigned int            MCD_SRBM_MASK_ENABLE : 1;
		unsigned int                 CNTR_CHMAP_MODE : 1;
		unsigned int        REMOTE_RB_CONNECT_ENABLE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_CNTL__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                        IGNOREPM : 1;
		unsigned int                        EXEMPTPM : 1;
		unsigned int               GFX_IDLE_OVERRIDE : 2;
		unsigned int            MCD_SRBM_MASK_ENABLE : 1;
		unsigned int                 CNTR_CHMAP_MODE : 2;
		unsigned int        REMOTE_RB_CONNECT_ENABLE : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_CNTL__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int                        IGNOREPM : 1;
		unsigned int                        EXEMPTPM : 1;
		unsigned int               GFX_IDLE_OVERRIDE : 2;
		unsigned int            MCD_SRBM_MASK_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_CREDITS_ARB_RD {
	struct {
		unsigned int                        READ_LCL : 8;
		unsigned int                        READ_HUB : 8;
		unsigned int                        READ_PRI : 8;
		unsigned int                         LCL_PRI : 1;
		unsigned int                         HUB_PRI : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_CREDITS_ARB_WR__SI__CI {
	struct {
                unsigned int                       WRITE_LCL : 8;
                unsigned int                       WRITE_HUB : 8;
                unsigned int                         HUB_PRI : 1;
                unsigned int                     LCL_PRI__CI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_CREDITS_ARB_WR__VI {
	struct {
		unsigned int                       WRITE_LCL : 8;
		unsigned int                       WRITE_HUB : 8;
		unsigned int                       WRITE_PRI : 8;
		unsigned int                         HUB_PRI : 1;
		unsigned int                         LCL_PRI : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_CREDITS_VM {
	struct {
		unsigned int                        READ_ALL : 6;
		unsigned int                       WRITE_ALL : 6;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_CREDITS_XBAR {
	struct {
		unsigned int                        READ_LCL : 8;
		unsigned int                       WRITE_LCL : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_DAGB_CNTL {
	struct {
                unsigned int                      JUMP_AHEAD : 1;
                unsigned int             CENTER_RD_MAX_BURST : 4;
                unsigned int               DISABLE_SELF_INIT : 1;
                unsigned int     CENTER_WR_MAX_BURST__CI__VI : 4;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_DAGB_DLY {
	struct {
                unsigned int                             DLY : 6;
                unsigned int                                 : 10;
                unsigned int                             CLI : 6;
                unsigned int                                 : 2;
                unsigned int                             POS : 6;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_INT_CREDITS {
	struct {
		unsigned int                        REMRDRET : 6;
		unsigned int                                 : 6;
		unsigned int                  CNTR_RD_HUB_LP : 6;
		unsigned int                  CNTR_RD_HUB_HP : 6;
		unsigned int                     CNTR_RD_LCL : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_INT_CREDITS_WR__CI__VI {
	struct {
                unsigned int                     CNTR_WR_HUB : 6;
                unsigned int                     CNTR_WR_LCL : 6;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_MISC_RD_CG {
	struct {
		unsigned int                           ONDLY : 6;
		unsigned int                          OFFDLY : 6;
		unsigned int                          RDYDLY : 6;
		unsigned int                          ENABLE : 1;
		unsigned int                   MEM_LS_ENABLE : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_MISC_VM_CG {
	struct {
		unsigned int                           ONDLY : 6;
		unsigned int                          OFFDLY : 6;
		unsigned int                          RDYDLY : 6;
		unsigned int                          ENABLE : 1;
		unsigned int                   MEM_LS_ENABLE : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_MISC_WR_CG {
	struct {
		unsigned int                           ONDLY : 6;
		unsigned int                          OFFDLY : 6;
		unsigned int                          RDYDLY : 6;
		unsigned int                          ENABLE : 1;
		unsigned int                   MEM_LS_ENABLE : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_PERFCOUNTER0_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_PERFCOUNTER1_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_PERFCOUNTER2_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_PERFCOUNTER3_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                      COUNTER_HI : 16;
                unsigned int                   COMPARE_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                      COUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_PERFCOUNTER_RSLT_CNTL__CI__VI {
	struct {
                unsigned int             PERF_COUNTER_SELECT : 4;
                unsigned int                                 : 4;
                unsigned int                   START_TRIGGER : 8;
                unsigned int                    STOP_TRIGGER : 8;
                unsigned int                      ENABLE_ANY : 1;
                unsigned int                       CLEAR_ALL : 1;
                unsigned int            STOP_ALL_ON_SATURATE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_PERF_MON_CNTL2 {
	struct {
                unsigned int                             CID : 9;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_PERF_MON_RSLT2__SI__CI {
	struct {
                unsigned int                                 : 6;
                unsigned int                      CB_RD_BUSY : 1;
                unsigned int                      DB_RD_BUSY : 1;
                unsigned int                     TC0_RD_BUSY : 1;
                unsigned int                     VC0_RD_BUSY : 1;
                unsigned int                     TC1_RD_BUSY : 1;
                unsigned int                     VC1_RD_BUSY : 1;
                unsigned int                      CB_WR_BUSY : 1;
                unsigned int                      DB_WR_BUSY : 1;
                unsigned int                      SX_WR_BUSY : 1;
                unsigned int                     TC2_RD_BUSY : 1;
                unsigned int                     TC0_WR_BUSY : 1;
                unsigned int                     TC1_WR_BUSY : 1;
                unsigned int                     TC2_WR_BUSY : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_PERF_MON_RSLT2__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                      CB_RD_BUSY : 1;
		unsigned int                      DB_RD_BUSY : 1;
		unsigned int                     TC0_RD_BUSY : 1;
		unsigned int                     VC0_RD_BUSY : 1;
		unsigned int                     TC1_RD_BUSY : 1;
		unsigned int                     VC1_RD_BUSY : 1;
		unsigned int                      CB_WR_BUSY : 1;
		unsigned int                      DB_WR_BUSY : 1;
		unsigned int                      SX_WR_BUSY : 1;
		unsigned int                     TC2_RD_BUSY : 1;
		unsigned int                     TC0_WR_BUSY : 1;
		unsigned int                     TC1_WR_BUSY : 1;
		unsigned int                     TC2_WR_BUSY : 1;
		unsigned int                   TC0_ATOM_BUSY : 1;
		unsigned int                   TC1_ATOM_BUSY : 1;
		unsigned int                   TC2_ATOM_BUSY : 1;
		unsigned int                    CB_ATOM_BUSY : 1;
		unsigned int                    DB_ATOM_BUSY : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_REMREQ {
	struct {
		unsigned int                    READ_CREDITS : 7;
		unsigned int                   WRITE_CREDITS : 7;
		unsigned int                  CREDITS_ENABLE : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_RET_MODE {
	struct {
                unsigned int                      INORDER_RD : 1;
                unsigned int                      INORDER_WR : 1;
                unsigned int                       REMPRI_RD : 1;
                unsigned int                       REMPRI_WR : 1;
                unsigned int                       LCLPRI_RD : 1;
                unsigned int                       LCLPRI_WR : 1;
                unsigned int              RDRET_STALL_EN__VI : 1;
                unsigned int       RDRET_STALL_THRESHOLD__VI : 8;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_WTM_RD_CNTL__CI__VI {
	struct {
                unsigned int                GROUP0_DECREMENT : 3;
                unsigned int                GROUP1_DECREMENT : 3;
                unsigned int                GROUP2_DECREMENT : 3;
                unsigned int                GROUP3_DECREMENT : 3;
                unsigned int                GROUP4_DECREMENT : 3;
                unsigned int                GROUP5_DECREMENT : 3;
                unsigned int                GROUP6_DECREMENT : 3;
                unsigned int                GROUP7_DECREMENT : 3;
                unsigned int                  DISABLE_REMOTE : 1;
                unsigned int                   DISABLE_LOCAL : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_WTM_RD_CNTL__SI {
	struct {
		unsigned int                GROUP0_DECREMENT : 3;
		unsigned int                GROUP1_DECREMENT : 3;
		unsigned int                GROUP2_DECREMENT : 3;
		unsigned int                GROUP3_DECREMENT : 3;
		unsigned int                GROUP4_DECREMENT : 3;
		unsigned int                GROUP5_DECREMENT : 3;
		unsigned int                GROUP6_DECREMENT : 3;
		unsigned int                GROUP7_DECREMENT : 3;
		unsigned int                  DISABLE_REMOTE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_WTM_WR_CNTL__CI__VI {
	struct {
                unsigned int                GROUP0_DECREMENT : 3;
                unsigned int                GROUP1_DECREMENT : 3;
                unsigned int                GROUP2_DECREMENT : 3;
                unsigned int                GROUP3_DECREMENT : 3;
                unsigned int                GROUP4_DECREMENT : 3;
                unsigned int                GROUP5_DECREMENT : 3;
                unsigned int                GROUP6_DECREMENT : 3;
                unsigned int                GROUP7_DECREMENT : 3;
                unsigned int                  DISABLE_REMOTE : 1;
                unsigned int                   DISABLE_LOCAL : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_WTM_WR_CNTL__SI {
	struct {
		unsigned int                GROUP0_DECREMENT : 3;
		unsigned int                GROUP1_DECREMENT : 3;
		unsigned int                GROUP2_DECREMENT : 3;
		unsigned int                GROUP3_DECREMENT : 3;
		unsigned int                GROUP4_DECREMENT : 3;
		unsigned int                GROUP5_DECREMENT : 3;
		unsigned int                GROUP6_DECREMENT : 3;
		unsigned int                GROUP7_DECREMENT : 3;
		unsigned int                  DISABLE_REMOTE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_XTRA_ENABLE {
	struct {
                unsigned int                          CB1_RD : 1;
                unsigned int                          CB1_WR : 1;
                unsigned int                          DB1_RD : 1;
                unsigned int                          DB1_WR : 1;
                unsigned int                          TC2_RD : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                         ARB_DBG : 4;
                unsigned int                          TC2_WR : 1;
                unsigned int        CB0_CONNECT_CNTL__CI__VI : 2;
                unsigned int        DB0_CONNECT_CNTL__CI__VI : 2;
                unsigned int        CB1_CONNECT_CNTL__CI__VI : 2;
                unsigned int        DB1_CONNECT_CNTL__CI__VI : 2;
                unsigned int        TC0_CONNECT_CNTL__CI__VI : 2;
                unsigned int        TC1_CONNECT_CNTL__CI__VI : 2;
                unsigned int     CB0_CID_CNTL_ENABLE__CI__VI : 1;
                unsigned int     DB0_CID_CNTL_ENABLE__CI__VI : 1;
                unsigned int     CB1_CID_CNTL_ENABLE__CI__VI : 1;
                unsigned int     DB1_CID_CNTL_ENABLE__CI__VI : 1;
                unsigned int       TC2_REPAIR_ENABLE__CI__VI : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CONFIG__SI__CI {
	struct {
		unsigned int                  MCDW_WR_ENABLE : 1;
		unsigned int                  MCDX_WR_ENABLE : 1;
		unsigned int                  MCDY_WR_ENABLE : 1;
		unsigned int                  MCDZ_WR_ENABLE : 1;
		unsigned int                    MC_RD_ENABLE : 2;
		unsigned int                                 : 25;
		unsigned int           MCC_INDEX_MODE_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CONFIG__VI {
	struct {
		unsigned int                  MCDW_WR_ENABLE : 1;
		unsigned int                  MCDX_WR_ENABLE : 1;
		unsigned int                  MCDY_WR_ENABLE : 1;
		unsigned int                  MCDZ_WR_ENABLE : 1;
		unsigned int                  MCDS_WR_ENABLE : 1;
		unsigned int                  MCDT_WR_ENABLE : 1;
		unsigned int                  MCDU_WR_ENABLE : 1;
		unsigned int                  MCDV_WR_ENABLE : 1;
		unsigned int                    MC_RD_ENABLE : 3;
		unsigned int                                 : 20;
		unsigned int           MCC_INDEX_MODE_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CONFIG_MCD {
	struct {
                unsigned int                  MCD0_WR_ENABLE : 1;
                unsigned int                  MCD1_WR_ENABLE : 1;
                unsigned int                  MCD2_WR_ENABLE : 1;
                unsigned int                  MCD3_WR_ENABLE : 1;
                unsigned int                  MCD4_WR_ENABLE : 1;
                unsigned int                  MCD5_WR_ENABLE : 1;
                unsigned int              MCD6_WR_ENABLE__VI : 1;
                unsigned int              MCD7_WR_ENABLE__VI : 1;
                unsigned int                    MC_RD_ENABLE : 3;
                unsigned int            MC_RD_ENABLE_SUB__VI : 1;
                unsigned int              ARB0_WR_ENABLE__VI : 1;
                unsigned int              ARB1_WR_ENABLE__VI : 1;
                unsigned int                                 : 17;
                unsigned int           MCD_INDEX_MODE_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DC_INTERFACE_NACK_STATUS__SI__VI {
	struct {
                unsigned int        DMIF_RDRET_NACK_OCCURRED : 1;
                unsigned int                                 : 3;
                unsigned int           DMIF_RDRET_NACK_CLEAR : 1;
                unsigned int                                 : 3;
                unsigned int         VIP_WRRET_NACK_OCCURRED : 1;
                unsigned int                                 : 3;
                unsigned int            VIP_WRRET_NACK_CLEAR : 1;
                unsigned int                                 : 3;
                unsigned int        MCIF_RDRET_NACK_OCCURRED : 1;
                unsigned int                                 : 3;
                unsigned int           MCIF_RDRET_NACK_CLEAR : 1;
                unsigned int                                 : 3;
                unsigned int        MCIF_WRRET_NACK_OCCURRED : 1;
                unsigned int                                 : 3;
                unsigned int           MCIF_WRRET_NACK_CLEAR : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_CONFIG0__CI {
	struct {
		unsigned int                     CONF_EN_CH0 : 1;
		unsigned int                     CONF_EN_CH1 : 1;
		unsigned int                    CONF_AUTO_EN : 1;
		unsigned int                                 : 1;
		unsigned int                            MASK : 4;
		unsigned int                             PTR : 10;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_CONFIG1__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_MISCCTRL0__CI {
	struct {
		unsigned int              UDD_ON_STATUS_BITS : 1;
		unsigned int                   LOAD_DATA_SEL : 1;
		unsigned int                        LOAD_UDD : 1;
		unsigned int                  ADR_STATUS_SEL : 1;
		unsigned int                        DATA_SEL : 4;
		unsigned int               PRBS_CHK_LOAD_CNT : 7;
		unsigned int                                 : 1;
		unsigned int                             UDD : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_MISCCTRL1__CI {
	struct {
		unsigned int              PRBS_ERR_CNT_LIMIT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_MISCCTRL2__CI {
	struct {
		unsigned int                 PRBS_RUN_LENGTH : 17;
		unsigned int                    PRBS_FREERUN : 1;
		unsigned int                     PRBS15_MODE : 1;
		unsigned int                     PRBS23_MODE : 1;
		unsigned int                STOP_ON_NEXT_ERR : 1;
		unsigned int                        STOP_CLK : 1;
		unsigned int                                 : 2;
		unsigned int                       SWEEP_DLY : 2;
		unsigned int                    GRAY_CODE_EN : 1;
		unsigned int                                 : 1;
		unsigned int                SEL_PHY_PRBS_CHK : 1;
		unsigned int                 SEL_AC_PRBS_CHK : 1;
		unsigned int                      STATUS_SEL : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_SETUPFIFO__CI {
	struct {
		unsigned int                  WRITE_FIFO_RST : 1;
		unsigned int                   READ_FIFO_RST : 1;
		unsigned int                   BOTH_FIFO_RST : 1;
		unsigned int                        SYNC_RST : 1;
		unsigned int                   SYNC_RST_MASK : 2;
		unsigned int                   OUTPUT_EN_RST : 1;
		unsigned int                                 : 1;
		unsigned int               SHIFT_WR_FIFO_PTR : 2;
		unsigned int               DELAY_RD_FIFO_PTR : 3;
		unsigned int                                 : 3;
		unsigned int                          STROBE : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_SETUPSWEEP__CI {
	struct {
		unsigned int                         DLL_RST : 1;
		unsigned int                          CONFIG : 1;
		unsigned int                          MASTER : 1;
		unsigned int                                 : 1;
		unsigned int                          DLLDLY : 4;
		unsigned int                        DLLSTEPS : 5;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_SETUP__CI {
	struct {
		unsigned int                          DLB_EN : 1;
		unsigned int                     DLB_FIFO_EN : 1;
		unsigned int                   DLB_STATUS_EN : 1;
		unsigned int                   DLB_CONFIG_EN : 1;
		unsigned int                     DLB_PRBS_EN : 1;
		unsigned int                    PRBS_GEN_RST : 1;
		unsigned int                    PRBS_CHK_RST : 1;
		unsigned int                    PRBS_PHY_RST : 1;
		unsigned int                        QDR_MODE : 1;
		unsigned int                                 : 7;
		unsigned int                   CHK_DATA_BITS : 8;
		unsigned int                     MEM_BIT_SEL : 5;
		unsigned int                                 : 2;
		unsigned int                       RXTXLP_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_STATUS_MISC0__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_STATUS_MISC1__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_STATUS_MISC2__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_STATUS_MISC3__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_STATUS_MISC4__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_STATUS_MISC5__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_STATUS_MISC6__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_STATUS_MISC7__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_STATUS__CI {
	struct {
		unsigned int                     STICK_ERROR : 4;
		unsigned int                            LOCK : 4;
		unsigned int                      SWEEP_DONE : 4;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_DLB_WRITE_MASK__CI {
	struct {
		unsigned int                        BIT_MASK : 22;
		unsigned int                                 : 2;
		unsigned int                         CH_MASK : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_DBG__SI__CI {
	struct {
                unsigned int                         SELECT0 : 4;
                unsigned int                         SELECT1 : 4;
                unsigned int                       CTRL0__CI : 5;
                unsigned int                       CTRL1__CI : 5;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_FRAMING {
	struct {
		unsigned int                            BITS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_HUB_CG {
	struct {
		unsigned int                           ONDLY : 6;
		unsigned int                          OFFDLY : 6;
		unsigned int                          RDYDLY : 6;
		unsigned int                          ENABLE : 1;
		unsigned int                   MEM_LS_ENABLE : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_IDLE_STATUS__CI {
	struct {
		unsigned int            OUTSTANDING_GFX_READ : 1;
		unsigned int           OUTSTANDING_GFX_WRITE : 1;
		unsigned int            OUTSTANDING_RLC_READ : 1;
		unsigned int           OUTSTANDING_RLC_WRITE : 1;
		unsigned int          OUTSTANDING_SDMA0_READ : 1;
		unsigned int         OUTSTANDING_SDMA0_WRITE : 1;
		unsigned int          OUTSTANDING_SDMA1_READ : 1;
		unsigned int         OUTSTANDING_SDMA1_WRITE : 1;
		unsigned int           OUTSTANDING_DISP_READ : 1;
		unsigned int          OUTSTANDING_DISP_WRITE : 1;
		unsigned int            OUTSTANDING_UVD_READ : 1;
		unsigned int           OUTSTANDING_UVD_WRITE : 1;
		unsigned int            OUTSTANDING_SMU_READ : 1;
		unsigned int           OUTSTANDING_SMU_WRITE : 1;
		unsigned int            OUTSTANDING_HDP_READ : 1;
		unsigned int           OUTSTANDING_HDP_WRITE : 1;
		unsigned int            OUTSTANDING_OTH_READ : 1;
		unsigned int           OUTSTANDING_OTH_WRITE : 1;
		unsigned int            OUTSTANDING_VMC_READ : 1;
		unsigned int           OUTSTANDING_VMC_WRITE : 1;
		unsigned int             OUTSTANDING_IA_READ : 1;
		unsigned int            OUTSTANDING_IA_WRITE : 1;
		unsigned int            OUTSTANDING_VCE_READ : 1;
		unsigned int           OUTSTANDING_VCE_WRITE : 1;
		unsigned int            OUTSTANDING_ACP_READ : 1;
		unsigned int           OUTSTANDING_ACP_WRITE : 1;
		unsigned int             OUTSTANDING_CP_READ : 1;
		unsigned int            OUTSTANDING_CP_WRITE : 1;
		unsigned int           OUTSTANDING_XDMA_READ : 1;
		unsigned int          OUTSTANDING_XDMA_WRITE : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_IDLE_STATUS__VI {
	struct {
		unsigned int            OUTSTANDING_GFX_READ : 1;
		unsigned int           OUTSTANDING_GFX_WRITE : 1;
		unsigned int            OUTSTANDING_RLC_READ : 1;
		unsigned int           OUTSTANDING_RLC_WRITE : 1;
		unsigned int          OUTSTANDING_SDMA0_READ : 1;
		unsigned int         OUTSTANDING_SDMA0_WRITE : 1;
		unsigned int          OUTSTANDING_SDMA1_READ : 1;
		unsigned int         OUTSTANDING_SDMA1_WRITE : 1;
		unsigned int           OUTSTANDING_DISP_READ : 1;
		unsigned int          OUTSTANDING_DISP_WRITE : 1;
		unsigned int            OUTSTANDING_UVD_READ : 1;
		unsigned int           OUTSTANDING_UVD_WRITE : 1;
		unsigned int            OUTSTANDING_SMU_READ : 1;
		unsigned int           OUTSTANDING_SMU_WRITE : 1;
		unsigned int            OUTSTANDING_HDP_READ : 1;
		unsigned int           OUTSTANDING_HDP_WRITE : 1;
		unsigned int            OUTSTANDING_OTH_READ : 1;
		unsigned int           OUTSTANDING_OTH_WRITE : 1;
		unsigned int            OUTSTANDING_VMC_READ : 1;
		unsigned int           OUTSTANDING_VMC_WRITE : 1;
		unsigned int            OUTSTANDING_VCE_READ : 1;
		unsigned int           OUTSTANDING_VCE_WRITE : 1;
		unsigned int            OUTSTANDING_ACP_READ : 1;
		unsigned int           OUTSTANDING_ACP_WRITE : 1;
		unsigned int         OUTSTANDING_SAMMSP_READ : 1;
		unsigned int        OUTSTANDING_SAMMSP_WRITE : 1;
		unsigned int           OUTSTANDING_XDMA_READ : 1;
		unsigned int          OUTSTANDING_XDMA_WRITE : 1;
		unsigned int            OUTSTANDING_ISP_READ : 1;
		unsigned int           OUTSTANDING_ISP_WRITE : 1;
		unsigned int            OUTSTANDING_VP8_READ : 1;
		unsigned int           OUTSTANDING_VP8_WRITE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_IDLE_STATUS__SI {
	struct {
		unsigned int             OUTSTANDING_CP_READ : 1;
		unsigned int            OUTSTANDING_CP_WRITE : 1;
		unsigned int            OUTSTANDING_GFX_READ : 1;
		unsigned int           OUTSTANDING_GFX_WRITE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int            OUTSTANDING_RLC_READ : 1;
		unsigned int           OUTSTANDING_RLC_WRITE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int           OUTSTANDING_DISP_READ : 1;
		unsigned int          OUTSTANDING_DISP_WRITE : 1;
		unsigned int            OUTSTANDING_UVD_READ : 1;
		unsigned int           OUTSTANDING_UVD_WRITE : 1;
		unsigned int            OUTSTANDING_SMU_READ : 1;
		unsigned int           OUTSTANDING_SMU_WRITE : 1;
		unsigned int            OUTSTANDING_HDP_READ : 1;
		unsigned int           OUTSTANDING_HDP_WRITE : 1;
		unsigned int            OUTSTANDING_OTH_READ : 1;
		unsigned int           OUTSTANDING_OTH_WRITE : 1;
		unsigned int            OUTSTANDING_VMC_READ : 1;
		unsigned int           OUTSTANDING_VMC_WRITE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int            OUTSTANDING_VCE_READ : 1;
		unsigned int           OUTSTANDING_VCE_WRITE : 1;
		unsigned int           OUTSTANDING_XDMA_READ : 1;
		unsigned int          OUTSTANDING_XDMA_WRITE : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_OVERRIDE {
	struct {
		unsigned int                            IDLE : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_POWER {
	struct {
                unsigned int                                 : 2;
                unsigned int              SRBM_GATE_OVERRIDE : 1;
                unsigned int                PM_BLACKOUT_CNTL : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_SIP_CG {
	struct {
		unsigned int                           ONDLY : 6;
		unsigned int                          OFFDLY : 6;
		unsigned int                          RDYDLY : 6;
		unsigned int                          ENABLE : 1;
		unsigned int                   MEM_LS_ENABLE : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_STATUS__SI__CI {
	struct {
		unsigned int                OUTSTANDING_READ : 1;
		unsigned int               OUTSTANDING_WRITE : 1;
		unsigned int           OUTSTANDING_HUB_RDREQ : 1;
		unsigned int           OUTSTANDING_HUB_RDRET : 1;
		unsigned int           OUTSTANDING_HUB_WRREQ : 1;
		unsigned int           OUTSTANDING_HUB_WRRET : 1;
		unsigned int            OUTSTANDING_RPB_READ : 1;
		unsigned int           OUTSTANDING_RPB_WRITE : 1;
		unsigned int            OUTSTANDING_MCD_READ : 1;
		unsigned int           OUTSTANDING_MCD_WRITE : 1;
		unsigned int                        RPB_BUSY : 1;
		unsigned int          WRITE_DEADLOCK_WARNING : 1;
		unsigned int           READ_DEADLOCK_WARNING : 1;
		unsigned int                        GFX_BUSY : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_STATUS__VI {
	struct {
		unsigned int                OUTSTANDING_READ : 1;
		unsigned int               OUTSTANDING_WRITE : 1;
		unsigned int              OUTSTANDING_ATOMIC : 1;
		unsigned int           OUTSTANDING_HUB_RDREQ : 1;
		unsigned int           OUTSTANDING_HUB_RDRET : 1;
		unsigned int           OUTSTANDING_HUB_WRREQ : 1;
		unsigned int           OUTSTANDING_HUB_WRRET : 1;
		unsigned int      OUTSTANDING_HUB_ATOMIC_REQ : 1;
		unsigned int      OUTSTANDING_HUB_ATOMIC_RET : 1;
		unsigned int            OUTSTANDING_RPB_READ : 1;
		unsigned int           OUTSTANDING_RPB_WRITE : 1;
		unsigned int          OUTSTANDING_RPB_ATOMIC : 1;
		unsigned int            OUTSTANDING_MCD_READ : 1;
		unsigned int           OUTSTANDING_MCD_WRITE : 1;
		unsigned int          OUTSTANDING_MCD_ATOMIC : 1;
		unsigned int                        RPB_BUSY : 1;
		unsigned int          WRITE_DEADLOCK_WARNING : 1;
		unsigned int           READ_DEADLOCK_WARNING : 1;
		unsigned int         ATOMIC_DEADLOCK_WARNING : 1;
		unsigned int                        GFX_BUSY : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_VM_CG {
	struct {
		unsigned int                           ONDLY : 6;
		unsigned int                          OFFDLY : 6;
		unsigned int                          RDYDLY : 6;
		unsigned int                          ENABLE : 1;
		unsigned int                   MEM_LS_ENABLE : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_PERFCOUNTER0_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_PERFCOUNTER1_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_PERFCOUNTER2_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_PERFCOUNTER3_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                      COUNTER_HI : 16;
                unsigned int                   COMPARE_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                      COUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_PERFCOUNTER_RSLT_CNTL__CI__VI {
	struct {
                unsigned int             PERF_COUNTER_SELECT : 4;
                unsigned int                                 : 4;
                unsigned int                   START_TRIGGER : 8;
                unsigned int                    STOP_TRIGGER : 8;
                unsigned int                      ENABLE_ANY : 1;
                unsigned int                       CLEAR_ALL : 1;
                unsigned int            STOP_ALL_ON_SATURATE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_ACPG_LIMIT__CI__VI {
	struct {
                unsigned int                          ENABLE : 2;
                unsigned int                     LIMIT_COUNT : 5;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_ACPG__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int                PRIORITY_DISABLE : 1;
                unsigned int             STALL_FILTER_ENABLE : 1;
                unsigned int                 STALL_THRESHOLD : 6;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_ACPO__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int                PRIORITY_DISABLE : 1;
                unsigned int             STALL_FILTER_ENABLE : 1;
                unsigned int                 STALL_THRESHOLD : 6;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_CNTL__SI__CI {
	struct {
                unsigned int                 REMOTE_BLACKOUT : 1;
                unsigned int                                 : 1;
                unsigned int                  JUMPAHEAD_GBL0 : 1;
                unsigned int                  JUMPAHEAD_GBL1 : 1;
                unsigned int           OVERRIDE_STALL_ENABLE : 1;
                unsigned int                 MCDW_STALL_MODE : 1;
                unsigned int                 MCDX_STALL_MODE : 1;
                unsigned int                 MCDY_STALL_MODE : 1;
                unsigned int                 MCDZ_STALL_MODE : 1;
                unsigned int              BREAK_HDP_DEADLOCK : 1;
                unsigned int                       DEBUG_REG : 7;
                unsigned int          DISABLE_SELF_INIT_GBL0 : 1;
                unsigned int          DISABLE_SELF_INIT_GBL1 : 1;
                unsigned int                  PWRXPRESS_MODE : 1;
                unsigned int     ACPG_HP_TO_MCD_OVERRIDE__CI : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_CNTL__VI {
	struct {
		unsigned int                 REMOTE_BLACKOUT : 1;
		unsigned int                                 : 1;
		unsigned int                  JUMPAHEAD_GBL0 : 1;
		unsigned int                  JUMPAHEAD_GBL1 : 1;
		unsigned int           OVERRIDE_STALL_ENABLE : 1;
		unsigned int                 MCDW_STALL_MODE : 1;
		unsigned int                 MCDX_STALL_MODE : 1;
		unsigned int                 MCDY_STALL_MODE : 1;
		unsigned int                 MCDZ_STALL_MODE : 1;
		unsigned int                 MCDS_STALL_MODE : 1;
		unsigned int                 MCDT_STALL_MODE : 1;
		unsigned int                 MCDU_STALL_MODE : 1;
		unsigned int                 MCDV_STALL_MODE : 1;
		unsigned int              BREAK_HDP_DEADLOCK : 1;
		unsigned int                       DEBUG_REG : 7;
		unsigned int          DISABLE_SELF_INIT_GBL0 : 1;
		unsigned int          DISABLE_SELF_INIT_GBL1 : 1;
		unsigned int                  PWRXPRESS_MODE : 1;
		unsigned int         ACPG_HP_TO_MCD_OVERRIDE : 1;
		unsigned int                 GBL0_PRI_ENABLE : 1;
		unsigned int            UVD_TRANSCODE_ENABLE : 1;
		unsigned int              DMIF_URG_THRESHOLD : 4;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_CPC__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_CPF__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_CPG__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_CP__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_CREDITS {
	struct {
		unsigned int                             VM0 : 8;
		unsigned int                             VM1 : 8;
		unsigned int                           STOR0 : 8;
		unsigned int                           STOR1 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_CREDITS2__SI__CI {
	struct {
		unsigned int                       STOR1_PRI : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_CREDITS2__VI {
	struct {
		unsigned int                       STOR0_PRI : 8;
		unsigned int                       STOR1_PRI : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_DMIF {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_DMIF_LIMIT {
	struct {
		unsigned int                          ENABLE : 2;
		unsigned int                     LIMIT_COUNT : 5;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_GBL0 {
	struct {
                unsigned int                 STALL_THRESHOLD : 8;
                unsigned int         STALL_THRESHOLD_PRI__VI : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_GBL1 {
	struct {
                unsigned int                 STALL_THRESHOLD : 8;
                unsigned int         STALL_THRESHOLD_PRI__VI : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_HDP {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_IA0__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_IA1__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_IA__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDW__SI__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                 STALL_THRESHOLD : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDW__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                     MED_CREDITS : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDX__SI__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                 STALL_THRESHOLD : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDX__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                     MED_CREDITS : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDY__SI__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                 STALL_THRESHOLD : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDY__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                     MED_CREDITS : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDZ__SI__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                 STALL_THRESHOLD : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDZ__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                     MED_CREDITS : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCIF {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_RLC {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_SAM__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_SDMA0__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_SDMA1__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_SEM {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_SIP__SI__CI {
	struct {
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                           DUMMY : 1;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_SIP__VI {
	struct {
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                  MED_CREDIT_SEL : 1;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_SMU {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_STATUS__SI__CI {
	struct {
		unsigned int                       SIP_AVAIL : 1;
		unsigned int                   MCDW_RD_AVAIL : 1;
		unsigned int                   MCDX_RD_AVAIL : 1;
		unsigned int                   MCDY_RD_AVAIL : 1;
		unsigned int                   MCDZ_RD_AVAIL : 1;
		unsigned int                    GBL0_VM_FULL : 1;
		unsigned int                  GBL0_STOR_FULL : 1;
		unsigned int           GBL0_BYPASS_STOR_FULL : 1;
		unsigned int                    GBL1_VM_FULL : 1;
		unsigned int                  GBL1_STOR_FULL : 1;
		unsigned int           GBL1_BYPASS_STOR_FULL : 1;
		unsigned int                   PWRXPRESS_ERR : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_STATUS__VI {
	struct {
		unsigned int                       SIP_AVAIL : 1;
		unsigned int                   MCDW_RD_AVAIL : 1;
		unsigned int                   MCDX_RD_AVAIL : 1;
		unsigned int                   MCDY_RD_AVAIL : 1;
		unsigned int                   MCDZ_RD_AVAIL : 1;
		unsigned int                   MCDS_RD_AVAIL : 1;
		unsigned int                   MCDT_RD_AVAIL : 1;
		unsigned int                   MCDU_RD_AVAIL : 1;
		unsigned int                   MCDV_RD_AVAIL : 1;
		unsigned int                    GBL0_VM_FULL : 1;
		unsigned int                  GBL0_STOR_FULL : 1;
		unsigned int           GBL0_BYPASS_STOR_FULL : 1;
		unsigned int                    GBL1_VM_FULL : 1;
		unsigned int                  GBL1_STOR_FULL : 1;
		unsigned int           GBL1_BYPASS_STOR_FULL : 1;
		unsigned int                   PWRXPRESS_ERR : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_UMC {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                   VM_BYPASS__VI : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_UVD {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                       VM_BYPASS : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_VCE__SI__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_VCEU__SI__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_VMC {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_WTM_CNTL {
	struct {
		unsigned int                GROUP0_DECREMENT : 3;
		unsigned int                GROUP1_DECREMENT : 3;
		unsigned int                GROUP2_DECREMENT : 3;
		unsigned int                GROUP3_DECREMENT : 3;
		unsigned int                GROUP4_DECREMENT : 3;
		unsigned int                GROUP5_DECREMENT : 3;
		unsigned int                GROUP6_DECREMENT : 3;
		unsigned int                GROUP7_DECREMENT : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_XDMAM {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_SHARED_DAGB_DLY {
	struct {
                unsigned int                             DLY : 6;
                unsigned int                                 : 10;
                unsigned int                             CLI : 6;
                unsigned int                                 : 2;
                unsigned int                             POS : 5;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_ACPG__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int                PRIORITY_DISABLE : 1;
                unsigned int             STALL_FILTER_ENABLE : 1;
                unsigned int                 STALL_THRESHOLD : 6;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_ACPO__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int                PRIORITY_DISABLE : 1;
                unsigned int             STALL_FILTER_ENABLE : 1;
                unsigned int                 STALL_THRESHOLD : 6;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_BP {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                           RDRET : 17;
		unsigned int                           WRREQ : 12;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CNTL {
	struct {
                unsigned int                                 : 1;
                unsigned int                  JUMPAHEAD_GBL0 : 1;
                unsigned int                  JUMPAHEAD_GBL1 : 1;
                unsigned int              JUMPAHEAD_INTERNAL : 1;
                unsigned int           OVERRIDE_STALL_ENABLE : 1;
                unsigned int                       DEBUG_REG : 8;
                unsigned int          DISABLE_SELF_INIT_GBL0 : 1;
                unsigned int          DISABLE_SELF_INIT_GBL1 : 1;
                unsigned int      DISABLE_SELF_INIT_INTERNAL : 1;
                unsigned int                      FAIR_CH_SW : 1;
                unsigned int                 LCLWRREQ_BYPASS : 1;
                unsigned int                   DISP_WAIT_EOP : 1;
                unsigned int                    MCD_WAIT_EOP : 1;
                unsigned int                    SIP_WAIT_EOP : 1;
                unsigned int        UVD_VCE_WRITE_PRI_EN__VI : 1;
                unsigned int                WRITE_PRI_EN__VI : 1;
                unsigned int          IH_PHYSADDR_ENABLE__VI : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CPC__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CPF__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CPG__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CP__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS {
	struct {
		unsigned int                             VM0 : 8;
		unsigned int                             VM1 : 8;
		unsigned int                           STOR0 : 8;
		unsigned int                           STOR1 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_ERR {
	struct {
		unsigned int                  MGPU1_TARG_SYS : 1;
		unsigned int                  MGPU2_TARG_SYS : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_GBL0 {
	struct {
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int                 STALL_THRESHOLD : 8;
                unsigned int                      STALL_MODE : 1;
                unsigned int         STALL_THRESHOLD_PRI__VI : 8;
                unsigned int         STALL_THRESHOLD_URG__VI : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_GBL1 {
	struct {
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int                 STALL_THRESHOLD : 8;
                unsigned int                      STALL_MODE : 1;
                unsigned int         STALL_THRESHOLD_PRI__VI : 8;
                unsigned int         STALL_THRESHOLD_URG__VI : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_HDP {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_IH {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MCDW {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                     ASK_CREDITS : 6;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                 STALL_THRESHOLD : 7;
		unsigned int                   ASK_CREDITS_W : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MCDX {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                     ASK_CREDITS : 6;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                 STALL_THRESHOLD : 7;
		unsigned int                   ASK_CREDITS_W : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MCDY {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                     ASK_CREDITS : 6;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                 STALL_THRESHOLD : 7;
		unsigned int                   ASK_CREDITS_W : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MCDZ {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                     ASK_CREDITS : 6;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                 STALL_THRESHOLD : 7;
		unsigned int                   ASK_CREDITS_W : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MCIF {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MGPU__SI__CI {
	struct {
		unsigned int                            STOR : 8;
		unsigned int                             CID : 8;
		unsigned int              MGPU_PRIORITY_TIME : 7;
		unsigned int                          ENABLE : 1;
		unsigned int               OTH_PRIORITY_TIME : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MGPU2__SI__CI {
	struct {
		unsigned int                            CID2 : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_RLC {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SAM__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SDMA0__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SDMA1__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SEM {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SH0 {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SH1 {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SH2__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SH3__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SIP {
	struct {
		unsigned int                      STALL_MODE : 2;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SMU {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_STATUS__SI__CI {
	struct {
                unsigned int                       SIP_AVAIL : 1;
                unsigned int                   MCDW_RD_AVAIL : 1;
                unsigned int                   MCDX_RD_AVAIL : 1;
                unsigned int                   MCDY_RD_AVAIL : 1;
                unsigned int                   MCDZ_RD_AVAIL : 1;
                unsigned int                    GBL0_VM_FULL : 1;
                unsigned int                  GBL0_STOR_FULL : 1;
                unsigned int           GBL0_BYPASS_STOR_FULL : 1;
                unsigned int                    GBL1_VM_FULL : 1;
                unsigned int                  GBL1_STOR_FULL : 1;
                unsigned int           GBL1_BYPASS_STOR_FULL : 1;
                unsigned int                   MCDW_WR_AVAIL : 1;
                unsigned int                   MCDX_WR_AVAIL : 1;
                unsigned int                   MCDY_WR_AVAIL : 1;
                unsigned int                   MCDZ_WR_AVAIL : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_STATUS__VI {
	struct {
		unsigned int                       SIP_AVAIL : 1;
		unsigned int                   MCDW_RD_AVAIL : 1;
		unsigned int                   MCDX_RD_AVAIL : 1;
		unsigned int                   MCDY_RD_AVAIL : 1;
		unsigned int                   MCDZ_RD_AVAIL : 1;
		unsigned int                   MCDS_RD_AVAIL : 1;
		unsigned int                   MCDT_RD_AVAIL : 1;
		unsigned int                   MCDU_RD_AVAIL : 1;
		unsigned int                   MCDV_RD_AVAIL : 1;
		unsigned int                   MCDW_WR_AVAIL : 1;
		unsigned int                   MCDX_WR_AVAIL : 1;
		unsigned int                   MCDY_WR_AVAIL : 1;
		unsigned int                   MCDZ_WR_AVAIL : 1;
		unsigned int                   MCDS_WR_AVAIL : 1;
		unsigned int                   MCDT_WR_AVAIL : 1;
		unsigned int                   MCDU_WR_AVAIL : 1;
		unsigned int                   MCDV_WR_AVAIL : 1;
		unsigned int                    GBL0_VM_FULL : 1;
		unsigned int                  GBL0_STOR_FULL : 1;
		unsigned int           GBL0_BYPASS_STOR_FULL : 1;
		unsigned int                    GBL1_VM_FULL : 1;
		unsigned int                  GBL1_STOR_FULL : 1;
		unsigned int           GBL1_BYPASS_STOR_FULL : 1;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_UMC {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_UVD {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                       VM_BYPASS : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_VCE__SI__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_VCEU__SI__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_WTM_CNTL {
	struct {
		unsigned int                GROUP0_DECREMENT : 3;
		unsigned int                GROUP1_DECREMENT : 3;
		unsigned int                GROUP2_DECREMENT : 3;
		unsigned int                GROUP3_DECREMENT : 3;
		unsigned int                GROUP4_DECREMENT : 3;
		unsigned int                GROUP5_DECREMENT : 3;
		unsigned int                GROUP6_DECREMENT : 3;
		unsigned int                GROUP7_DECREMENT : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_XDMA {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_XDMAM {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_XDP {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int       BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int   URG_BYPASS_AVAIL_OVERRIDE__VI : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WRRET_CNTL {
	struct {
		unsigned int                       JUMPAHEAD : 1;
		unsigned int                              BP : 20;
		unsigned int                       BP_ENABLE : 1;
		unsigned int                       DEBUG_REG : 8;
		unsigned int               DISABLE_SELF_INIT : 1;
		unsigned int                      FAIR_CH_SW : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WRRET_MCDW {
	struct {
		unsigned int                      STALL_MODE : 1;
		unsigned int                    CREDIT_COUNT : 7;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WRRET_MCDX {
	struct {
		unsigned int                      STALL_MODE : 1;
		unsigned int                    CREDIT_COUNT : 7;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WRRET_MCDY {
	struct {
		unsigned int                      STALL_MODE : 1;
		unsigned int                    CREDIT_COUNT : 7;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WRRET_MCDZ {
	struct {
		unsigned int                      STALL_MODE : 1;
		unsigned int                    CREDIT_COUNT : 7;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WRRET_STATUS {
	struct {
                unsigned int                      MCDW_AVAIL : 1;
                unsigned int                      MCDX_AVAIL : 1;
                unsigned int                      MCDY_AVAIL : 1;
                unsigned int                      MCDZ_AVAIL : 1;
                unsigned int                  MCDS_AVAIL__VI : 1;
                unsigned int                  MCDT_AVAIL__VI : 1;
                unsigned int                  MCDU_AVAIL__VI : 1;
                unsigned int                  MCDV_AVAIL__VI : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IMP_CNTL__SI__CI {
	struct {
		unsigned int              MEM_IO_UPDATE_RATE : 5;
		unsigned int                    CAL_VREF_SEL : 1;
		unsigned int                    CAL_VREFMODE : 1;
		unsigned int                                 : 1;
		unsigned int                     TIMEOUT_ERR : 1;
		unsigned int               CLEAR_TIMEOUT_ERR : 1;
		unsigned int                                 : 3;
		unsigned int               MEM_IO_SAMPLE_CNT : 3;
		unsigned int                        CAL_VREF : 7;
		unsigned int                                 : 6;
		unsigned int                   CAL_WHEN_IDLE : 1;
		unsigned int                CAL_WHEN_REFRESH : 1;
		unsigned int                       CAL_PWRON : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IMP_DEBUG__SI__CI {
	struct {
                unsigned int                   TSTARTUP_CNTR : 8;
                unsigned int                    TIMEOUT_CNTR : 8;
                unsigned int                 PMVCAL_RESERVED : 12;
                unsigned int                    DEBUG_CAL_EN : 1;
                unsigned int                 DEBUG_CAL_START : 1;
                unsigned int                  DEBUG_CAL_INTR : 1;
                unsigned int                  DEBUG_CAL_DONE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IMP_DQ_STATUS__SI__CI {
	struct {
		unsigned int                     CH0_DQ_PSTR : 8;
		unsigned int                     CH0_DQ_NSTR : 8;
		unsigned int                     CH1_DQ_PSTR : 8;
		unsigned int                     CH1_DQ_NSTR : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IMP_STATUS__SI__CI {
	struct {
		unsigned int                        PSTR_CAL : 8;
		unsigned int                  PSTR_ACCUM_VAL : 8;
		unsigned int                        NSTR_CAL : 8;
		unsigned int                  NSTR_ACCUM_VAL : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_APHY_STR_CNTL_D0__SI__CI {
	struct {
		unsigned int                      PSTR_OFF_A : 6;
		unsigned int                      NSTR_OFF_A : 6;
		unsigned int                   PSTR_OFF_D_RD : 6;
		unsigned int                                 : 6;
		unsigned int                       USE_A_CAL : 1;
		unsigned int                    USE_D_RD_CAL : 1;
		unsigned int                         CAL_SEL : 2;
		unsigned int                      LOAD_A_STR : 1;
		unsigned int                   LOAD_D_RD_STR : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_APHY_STR_CNTL_D1__SI__CI {
	struct {
		unsigned int                      PSTR_OFF_A : 6;
		unsigned int                      NSTR_OFF_A : 6;
		unsigned int                   PSTR_OFF_D_RD : 6;
		unsigned int                                 : 6;
		unsigned int                       USE_A_CAL : 1;
		unsigned int                    USE_D_RD_CAL : 1;
		unsigned int                         CAL_SEL : 2;
		unsigned int                      LOAD_A_STR : 1;
		unsigned int                   LOAD_D_RD_STR : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_CDRCNTL1_D0__SI__CI {
	struct {
		unsigned int                   DQ_RXPHASE_B0 : 8;
		unsigned int                   DQ_RXPHASE_B1 : 8;
		unsigned int                 WCDR_TXPHASE_B0 : 8;
		unsigned int                 WCDR_TXPHASE_B1 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_CDRCNTL1_D1__SI__CI {
	struct {
		unsigned int                   DQ_RXPHASE_B0 : 8;
		unsigned int                   DQ_RXPHASE_B1 : 8;
		unsigned int                 WCDR_TXPHASE_B0 : 8;
		unsigned int                 WCDR_TXPHASE_B1 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_CDRCNTL2_D0__SI__CI {
	struct {
                unsigned int                     CDR_FB_SEL0 : 1;
                unsigned int                     CDR_FB_SEL1 : 1;
                unsigned int                   EDC_RXEN_OVR0 : 1;
                unsigned int                   EDC_RXEN_OVR1 : 1;
                unsigned int                    TXCDRBYPASS0 : 1;
                unsigned int                    TXCDRBYPASS1 : 1;
                unsigned int                   WCK_RXEN_OVR0 : 1;
                unsigned int                   WCK_RXEN_OVR1 : 1;
                unsigned int                 WCDRTXPWRON__CI : 4;
                unsigned int                   WCDRTXSEL__CI : 4;
                unsigned int                 WCDRTRACK01__CI : 4;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_CDRCNTL2_D1__SI__CI {
	struct {
                unsigned int                     CDR_FB_SEL0 : 1;
                unsigned int                     CDR_FB_SEL1 : 1;
                unsigned int                   EDC_RXEN_OVR0 : 1;
                unsigned int                   EDC_RXEN_OVR1 : 1;
                unsigned int                    TXCDRBYPASS0 : 1;
                unsigned int                    TXCDRBYPASS1 : 1;
                unsigned int                   WCK_RXEN_OVR0 : 1;
                unsigned int                   WCK_RXEN_OVR1 : 1;
                unsigned int                 WCDRTXPWRON__CI : 4;
                unsigned int                   WCDRTXSEL__CI : 4;
                unsigned int                 WCDRTRACK01__CI : 4;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_CDRCNTL_D0__SI__CI {
	struct {
		unsigned int                     RXPHASE_B01 : 4;
		unsigned int                     RXPHASE_B23 : 4;
		unsigned int                     RXCDREN_B01 : 1;
		unsigned int                     RXCDREN_B23 : 1;
		unsigned int                 RXCDRBYPASS_B01 : 1;
		unsigned int                 RXCDRBYPASS_B23 : 1;
		unsigned int                    RXPHASE1_B01 : 4;
		unsigned int                    RXPHASE1_B23 : 4;
		unsigned int                    DQTXCDREN_B0 : 1;
		unsigned int                    DQTXCDREN_B1 : 1;
		unsigned int                    DQRXCDREN_B0 : 1;
		unsigned int                    DQRXCDREN_B1 : 1;
		unsigned int                  WCDRRXCDREN_B0 : 1;
		unsigned int                  WCDRRXCDREN_B1 : 1;
		unsigned int                      WCDREDC_B0 : 1;
		unsigned int                      WCDREDC_B1 : 1;
		unsigned int                      DQRXSEL_B0 : 1;
		unsigned int                      DQRXSEL_B1 : 1;
		unsigned int                      DQTXSEL_B0 : 1;
		unsigned int                      DQTXSEL_B1 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_CDRCNTL_D1__SI__CI {
	struct {
		unsigned int                     RXPHASE_B01 : 4;
		unsigned int                     RXPHASE_B23 : 4;
		unsigned int                     RXCDREN_B01 : 1;
		unsigned int                     RXCDREN_B23 : 1;
		unsigned int                 RXCDRBYPASS_B01 : 1;
		unsigned int                 RXCDRBYPASS_B23 : 1;
		unsigned int                    RXPHASE1_B01 : 4;
		unsigned int                    RXPHASE1_B23 : 4;
		unsigned int                    DQTXCDREN_B0 : 1;
		unsigned int                    DQTXCDREN_B1 : 1;
		unsigned int                    DQRXCDREN_B0 : 1;
		unsigned int                    DQRXCDREN_B1 : 1;
		unsigned int                  WCDRRXCDREN_B0 : 1;
		unsigned int                  WCDRRXCDREN_B1 : 1;
		unsigned int                      WCDREDC_B0 : 1;
		unsigned int                      WCDREDC_B1 : 1;
		unsigned int                      DQRXSEL_B0 : 1;
		unsigned int                      DQRXSEL_B1 : 1;
		unsigned int                      DQTXSEL_B0 : 1;
		unsigned int                      DQTXSEL_B1 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ACMD_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRH_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_ADDRL_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CK_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_CMD_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DBI_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0H_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0L_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1H_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1L_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2H_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2L_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3H_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3L_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_RX_DYN_PM_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_RX_DYN_PM_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_RX_EQ_PM_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_RX_EQ_PM_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_EDC_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_0 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_1 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_10 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_100 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_101 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_102 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_103 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_104 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_105 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_106 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_107 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_108 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_109 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_11 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_110 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_111 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_112 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_113 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_114 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_115 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_116 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_117 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_118 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_119 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_12 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_120 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_121 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_122 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_123 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_124 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_125 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_126 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_127 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_128 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_129 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_13 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_130 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_131 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_132 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_133 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_134 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_135 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_136 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_137 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_138 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_139 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_14 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_140 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_141 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_142 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_143 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_144 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_145 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_146 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_147 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_148 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_149 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_15 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_150 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_151 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_152 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_153 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_154 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_155 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_156 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_157 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_158 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_159 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_16 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_17 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_18 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_19 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_2 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_20 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_21 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_22 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_23 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_24 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_25 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_26 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_27 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_28 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_29 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_3 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_30 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_31 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_32 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_33 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_34 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_35 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_36 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_37 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_38 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_39 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_4 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_40 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_41 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_42 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_43 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_44 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_45 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_46 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_47 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_48 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_49 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_5 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_50 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_51 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_52 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_53 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_54 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_55 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_56 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_57 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_58 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_59 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_6 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_60 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_61 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_62 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_63 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_64 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_65 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_66 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_67 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_68 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_69 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_7 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_70 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_71 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_72 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_73 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_74 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_75 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_76 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_77 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_78 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_79 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_8 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_80 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_81 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_82 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_83 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_84 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_85 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_86 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_87 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_88 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_89 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_9 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_90 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_91 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_92 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_93 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_94 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_95 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_96 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_97 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_98 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_UP_99 {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCDR_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_CLKSEL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_CLKSEL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_MISC_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_MISC_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_OFSCAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_OFSCAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_RXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_RXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_RX_EQ_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_RX_EQ_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_TXBST_PD_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_TXBST_PD_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_TXBST_PU_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_TXBST_PU_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_TXPHASE_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_TXPHASE_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_TXSLF_D0__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DEBUG_WCK_TXSLF_D1__SI__CI {
	struct {
		unsigned int                          VALUE0 : 8;
		unsigned int                          VALUE1 : 8;
		unsigned int                          VALUE2 : 8;
		unsigned int                          VALUE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DPHY_STR_CNTL_D0__SI__CI {
	struct {
                unsigned int                      PSTR_OFF_D : 6;
                unsigned int                      NSTR_OFF_D : 6;
                unsigned int                      PSTR_OFF_S : 6;
                unsigned int                      NSTR_OFF_S : 6;
                unsigned int                       USE_D_CAL : 1;
                unsigned int                       USE_S_CAL : 1;
                unsigned int                         CAL_SEL : 2;
                unsigned int                      LOAD_D_STR : 1;
                unsigned int                      LOAD_S_STR : 1;
                unsigned int                 AUTO_LD_STR__CI : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_DPHY_STR_CNTL_D1__SI__CI {
	struct {
                unsigned int                      PSTR_OFF_D : 6;
                unsigned int                      NSTR_OFF_D : 6;
                unsigned int                      PSTR_OFF_S : 6;
                unsigned int                      NSTR_OFF_S : 6;
                unsigned int                       USE_D_CAL : 1;
                unsigned int                       USE_S_CAL : 1;
                unsigned int                         CAL_SEL : 2;
                unsigned int                      LOAD_D_STR : 1;
                unsigned int                      LOAD_S_STR : 1;
                unsigned int                 AUTO_LD_STR__CI : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_PAD_CNTL__SI__CI {
	struct {
		unsigned int                  MEM_IO_IMP_MIN : 8;
		unsigned int                  MEM_IO_IMP_MAX : 8;
		unsigned int                    TXPHASE_GRAY : 1;
		unsigned int                    RXPHASE_GRAY : 1;
		unsigned int                   OVL_YCLKON_D0 : 1;
		unsigned int                   OVL_YCLKON_D1 : 1;
		unsigned int                          ATBSEL : 4;
		unsigned int                           ATBEN : 6;
		unsigned int                       ATBSEL_D1 : 1;
		unsigned int                       ATBSEL_D0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_PAD_CNTL_D0__SI__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  DELAY_CLK_SYNC : 1;
		unsigned int                  DELAY_CMD_SYNC : 1;
		unsigned int                  DELAY_ADR_SYNC : 1;
		unsigned int                                 : 2;
		unsigned int                MEM_FALL_OUT_CLK : 1;
		unsigned int                MEM_FALL_OUT_CMD : 1;
		unsigned int                MEM_FALL_OUT_ADR : 1;
		unsigned int                 FORCE_EN_RD_STR : 1;
		unsigned int                   EN_RD_STR_DLY : 1;
		unsigned int                     DISABLE_CMD : 1;
		unsigned int                     DISABLE_ADR : 1;
		unsigned int                        VREFI_EN : 1;
		unsigned int                       VREFI_SEL : 5;
		unsigned int                      CK_AUTO_EN : 1;
		unsigned int                    CK_DELAY_SEL : 1;
		unsigned int                      CK_DELAY_N : 2;
		unsigned int                      CK_DELAY_P : 2;
		unsigned int                                 : 1;
		unsigned int                    TXPWROFF_CKE : 1;
		unsigned int                         UNI_STR : 1;
		unsigned int                        DIFF_STR : 1;
		unsigned int                      GDDR_PWRON : 1;
		unsigned int                    TXPWROFF_CLK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_PAD_CNTL_D1__SI__CI {
	struct {
		unsigned int                 DELAY_DATA_SYNC : 1;
		unsigned int                  DELAY_STR_SYNC : 1;
		unsigned int                  DELAY_CLK_SYNC : 1;
		unsigned int                  DELAY_CMD_SYNC : 1;
		unsigned int                  DELAY_ADR_SYNC : 1;
		unsigned int               MEM_FALL_OUT_DATA : 1;
		unsigned int                MEM_FALL_OUT_STR : 1;
		unsigned int                MEM_FALL_OUT_CLK : 1;
		unsigned int                MEM_FALL_OUT_CMD : 1;
		unsigned int                MEM_FALL_OUT_ADR : 1;
		unsigned int                 FORCE_EN_RD_STR : 1;
		unsigned int                   EN_RD_STR_DLY : 1;
		unsigned int                     DISABLE_CMD : 1;
		unsigned int                     DISABLE_ADR : 1;
		unsigned int                        VREFI_EN : 1;
		unsigned int                       VREFI_SEL : 5;
		unsigned int                      CK_AUTO_EN : 1;
		unsigned int                    CK_DELAY_SEL : 1;
		unsigned int                      CK_DELAY_N : 2;
		unsigned int                      CK_DELAY_P : 2;
		unsigned int                                 : 1;
		unsigned int                    TXPWROFF_CKE : 1;
		unsigned int                         UNI_STR : 1;
		unsigned int                        DIFF_STR : 1;
		unsigned int                      GDDR_PWRON : 1;
		unsigned int                    TXPWROFF_CLK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL1_DPHY0_D0__CI {
	struct {
		unsigned int                    VREFCAL1_MSB : 4;
		unsigned int                    VREFCAL2_MSB : 4;
		unsigned int                        VREFCAL3 : 8;
		unsigned int                        VREFSEL2 : 1;
		unsigned int                        VREFSEL3 : 1;
		unsigned int                      VREFPDNB_1 : 1;
		unsigned int                 DLL_PWRGOOD_OVR : 1;
		unsigned int                 DLL_VCTRLADC_EN : 1;
		unsigned int                   DLL_MSTR_STBY : 1;
		unsigned int                        RXLEQ_EN : 1;
		unsigned int                       RXLEQ_NXT : 1;
		unsigned int                                 : 1;
		unsigned int                    PMD_LOOPBACK : 3;
		unsigned int                         DLL_RSV : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL1_DPHY0_D0__SI {
	struct {
		unsigned int                    VREFCAL1_MSB : 4;
		unsigned int                    VREFCAL2_MSB : 4;
		unsigned int                        VREFCAL3 : 8;
		unsigned int                        VREFSEL2 : 1;
		unsigned int                        VREFSEL3 : 1;
		unsigned int                      VREFPDNB_1 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                    PMD_LOOPBACK : 3;
		unsigned int                         DLL_RSV : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL1_DPHY0_D1__CI {
	struct {
		unsigned int                    VREFCAL1_MSB : 4;
		unsigned int                    VREFCAL2_MSB : 4;
		unsigned int                        VREFCAL3 : 8;
		unsigned int                        VREFSEL2 : 1;
		unsigned int                        VREFSEL3 : 1;
		unsigned int                      VREFPDNB_1 : 1;
		unsigned int                 DLL_PWRGOOD_OVR : 1;
		unsigned int                 DLL_VCTRLADC_EN : 1;
		unsigned int                   DLL_MSTR_STBY : 1;
		unsigned int                        RXLEQ_EN : 1;
		unsigned int                       RXLEQ_NXT : 1;
		unsigned int                                 : 1;
		unsigned int                    PMD_LOOPBACK : 3;
		unsigned int                         DLL_RSV : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL1_DPHY0_D1__SI {
	struct {
		unsigned int                    VREFCAL1_MSB : 4;
		unsigned int                    VREFCAL2_MSB : 4;
		unsigned int                        VREFCAL3 : 8;
		unsigned int                        VREFSEL2 : 1;
		unsigned int                        VREFSEL3 : 1;
		unsigned int                      VREFPDNB_1 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                    PMD_LOOPBACK : 3;
		unsigned int                         DLL_RSV : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL1_DPHY1_D0__CI {
	struct {
		unsigned int                    VREFCAL1_MSB : 4;
		unsigned int                    VREFCAL2_MSB : 4;
		unsigned int                        VREFCAL3 : 8;
		unsigned int                        VREFSEL2 : 1;
		unsigned int                        VREFSEL3 : 1;
		unsigned int                      VREFPDNB_1 : 1;
		unsigned int                 DLL_PWRGOOD_OVR : 1;
		unsigned int                 DLL_VCTRLADC_EN : 1;
		unsigned int                   DLL_MSTR_STBY : 1;
		unsigned int                        RXLEQ_EN : 1;
		unsigned int                       RXLEQ_NXT : 1;
		unsigned int                                 : 1;
		unsigned int                    PMD_LOOPBACK : 3;
		unsigned int                         DLL_RSV : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL1_DPHY1_D0__SI {
	struct {
		unsigned int                    VREFCAL1_MSB : 4;
		unsigned int                    VREFCAL2_MSB : 4;
		unsigned int                        VREFCAL3 : 8;
		unsigned int                        VREFSEL2 : 1;
		unsigned int                        VREFSEL3 : 1;
		unsigned int                      VREFPDNB_1 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                    PMD_LOOPBACK : 3;
		unsigned int                         DLL_RSV : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL1_DPHY1_D1__CI {
	struct {
		unsigned int                    VREFCAL1_MSB : 4;
		unsigned int                    VREFCAL2_MSB : 4;
		unsigned int                        VREFCAL3 : 8;
		unsigned int                        VREFSEL2 : 1;
		unsigned int                        VREFSEL3 : 1;
		unsigned int                      VREFPDNB_1 : 1;
		unsigned int                 DLL_PWRGOOD_OVR : 1;
		unsigned int                 DLL_VCTRLADC_EN : 1;
		unsigned int                   DLL_MSTR_STBY : 1;
		unsigned int                        RXLEQ_EN : 1;
		unsigned int                       RXLEQ_NXT : 1;
		unsigned int                                 : 1;
		unsigned int                    PMD_LOOPBACK : 3;
		unsigned int                         DLL_RSV : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL1_DPHY1_D1__SI {
	struct {
		unsigned int                    VREFCAL1_MSB : 4;
		unsigned int                    VREFCAL2_MSB : 4;
		unsigned int                        VREFCAL3 : 8;
		unsigned int                        VREFSEL2 : 1;
		unsigned int                        VREFSEL3 : 1;
		unsigned int                      VREFPDNB_1 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                    PMD_LOOPBACK : 3;
		unsigned int                         DLL_RSV : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL_DPHY0_D0__SI__CI {
	struct {
		unsigned int                       RXBIASSEL : 2;
		unsigned int                          RCVSEL : 1;
		unsigned int                        VREFPDNB : 1;
		unsigned int                    RXDPWRON_DLY : 2;
		unsigned int                          RXPDNB : 1;
		unsigned int                            RXLP : 1;
		unsigned int                         VREFCAL : 4;
		unsigned int                     VREFCAL_STR : 4;
		unsigned int                         VREFSEL : 1;
		unsigned int                                 : 1;
		unsigned int                      RX_PEAKSEL : 2;
		unsigned int                      DLL_ADJ_B0 : 3;
		unsigned int                                 : 1;
		unsigned int                      DLL_ADJ_B1 : 3;
		unsigned int                                 : 1;
		unsigned int                       DLL_ADJ_M : 1;
		unsigned int                    REFCLK_PWRON : 1;
		unsigned int                     DLL_BW_CTRL : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL_DPHY0_D1__SI__CI {
	struct {
		unsigned int                       RXBIASSEL : 2;
		unsigned int                          RCVSEL : 1;
		unsigned int                        VREFPDNB : 1;
		unsigned int                    RXDPWRON_DLY : 2;
		unsigned int                          RXPDNB : 1;
		unsigned int                            RXLP : 1;
		unsigned int                         VREFCAL : 4;
		unsigned int                     VREFCAL_STR : 4;
		unsigned int                         VREFSEL : 1;
		unsigned int                                 : 1;
		unsigned int                      RX_PEAKSEL : 2;
		unsigned int                      DLL_ADJ_B0 : 3;
		unsigned int                                 : 1;
		unsigned int                      DLL_ADJ_B1 : 3;
		unsigned int                                 : 1;
		unsigned int                       DLL_ADJ_M : 1;
		unsigned int                    REFCLK_PWRON : 1;
		unsigned int                     DLL_BW_CTRL : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL_DPHY1_D0__SI__CI {
	struct {
		unsigned int                       RXBIASSEL : 2;
		unsigned int                          RCVSEL : 1;
		unsigned int                        VREFPDNB : 1;
		unsigned int                    RXDPWRON_DLY : 2;
		unsigned int                          RXPDNB : 1;
		unsigned int                            RXLP : 1;
		unsigned int                         VREFCAL : 4;
		unsigned int                     VREFCAL_STR : 4;
		unsigned int                         VREFSEL : 1;
		unsigned int                                 : 1;
		unsigned int                      RX_PEAKSEL : 2;
		unsigned int                      DLL_ADJ_B0 : 3;
		unsigned int                                 : 1;
		unsigned int                      DLL_ADJ_B1 : 3;
		unsigned int                                 : 1;
		unsigned int                       DLL_ADJ_M : 1;
		unsigned int                    REFCLK_PWRON : 1;
		unsigned int                     DLL_BW_CTRL : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_RXCNTL_DPHY1_D1__SI__CI {
	struct {
		unsigned int                       RXBIASSEL : 2;
		unsigned int                          RCVSEL : 1;
		unsigned int                        VREFPDNB : 1;
		unsigned int                    RXDPWRON_DLY : 2;
		unsigned int                          RXPDNB : 1;
		unsigned int                            RXLP : 1;
		unsigned int                         VREFCAL : 4;
		unsigned int                     VREFCAL_STR : 4;
		unsigned int                         VREFSEL : 1;
		unsigned int                                 : 1;
		unsigned int                      RX_PEAKSEL : 2;
		unsigned int                      DLL_ADJ_B0 : 3;
		unsigned int                                 : 1;
		unsigned int                      DLL_ADJ_B1 : 3;
		unsigned int                                 : 1;
		unsigned int                       DLL_ADJ_M : 1;
		unsigned int                    REFCLK_PWRON : 1;
		unsigned int                     DLL_BW_CTRL : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_TXCNTL_APHY_D0__SI__CI {
	struct {
		unsigned int                         BIASSEL : 2;
		unsigned int                         DRVDUTY : 2;
		unsigned int                         LOWCMEN : 1;
		unsigned int                             QDR : 1;
		unsigned int                            EMPH : 1;
		unsigned int                            TXPD : 1;
		unsigned int                           PTERM : 4;
		unsigned int                     TXBPASS_SEL : 1;
		unsigned int                    PMA_LOOPBACK : 3;
		unsigned int                            PDRV : 4;
		unsigned int                            NDRV : 3;
		unsigned int                          YCLKON : 1;
		unsigned int                           TSTEN : 1;
		unsigned int                         TXRESET : 1;
		unsigned int                        TXBYPASS : 1;
		unsigned int                   TXBYPASS_DATA : 3;
		unsigned int                         CKE_BIT : 1;
		unsigned int                         CKE_SEL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_TXCNTL_APHY_D1__SI__CI {
	struct {
		unsigned int                         BIASSEL : 2;
		unsigned int                         DRVDUTY : 2;
		unsigned int                         LOWCMEN : 1;
		unsigned int                             QDR : 1;
		unsigned int                            EMPH : 1;
		unsigned int                            TXPD : 1;
		unsigned int                           PTERM : 4;
		unsigned int                     TXBPASS_SEL : 1;
		unsigned int                    PMA_LOOPBACK : 3;
		unsigned int                            PDRV : 4;
		unsigned int                            NDRV : 3;
		unsigned int                          YCLKON : 1;
		unsigned int                           TSTEN : 1;
		unsigned int                         TXRESET : 1;
		unsigned int                        TXBYPASS : 1;
		unsigned int                   TXBYPASS_DATA : 3;
		unsigned int                         CKE_BIT : 1;
		unsigned int                         CKE_SEL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_TXCNTL_DPHY0_D0__SI__CI {
	struct {
		unsigned int                         BIASSEL : 2;
		unsigned int                         DRVDUTY : 2;
		unsigned int                         LOWCMEN : 1;
		unsigned int                             QDR : 1;
		unsigned int                            EMPH : 1;
		unsigned int                            TXPD : 1;
		unsigned int                           PTERM : 4;
		unsigned int                           NTERM : 4;
		unsigned int                            PDRV : 4;
		unsigned int                            NDRV : 4;
		unsigned int                           TSTEN : 1;
		unsigned int                EDCTX_CLKGATE_EN : 1;
		unsigned int                        TXBYPASS : 1;
		unsigned int                     PLL_LOOPBCK : 1;
		unsigned int                   TXBYPASS_DATA : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_TXCNTL_DPHY0_D1__SI__CI {
	struct {
		unsigned int                         BIASSEL : 2;
		unsigned int                         DRVDUTY : 2;
		unsigned int                         LOWCMEN : 1;
		unsigned int                             QDR : 1;
		unsigned int                            EMPH : 1;
		unsigned int                            TXPD : 1;
		unsigned int                           PTERM : 4;
		unsigned int                           NTERM : 4;
		unsigned int                            PDRV : 4;
		unsigned int                            NDRV : 4;
		unsigned int                           TSTEN : 1;
		unsigned int                EDCTX_CLKGATE_EN : 1;
		unsigned int                        TXBYPASS : 1;
		unsigned int                     PLL_LOOPBCK : 1;
		unsigned int                   TXBYPASS_DATA : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_TXCNTL_DPHY1_D0__SI__CI {
	struct {
		unsigned int                         BIASSEL : 2;
		unsigned int                         DRVDUTY : 2;
		unsigned int                         LOWCMEN : 1;
		unsigned int                             QDR : 1;
		unsigned int                            EMPH : 1;
		unsigned int                            TXPD : 1;
		unsigned int                           PTERM : 4;
		unsigned int                           NTERM : 4;
		unsigned int                            PDRV : 4;
		unsigned int                            NDRV : 4;
		unsigned int                           TSTEN : 1;
		unsigned int                EDCTX_CLKGATE_EN : 1;
		unsigned int                        TXBYPASS : 1;
		unsigned int                     PLL_LOOPBCK : 1;
		unsigned int                   TXBYPASS_DATA : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_IO_TXCNTL_DPHY1_D1__SI__CI {
	struct {
		unsigned int                         BIASSEL : 2;
		unsigned int                         DRVDUTY : 2;
		unsigned int                         LOWCMEN : 1;
		unsigned int                             QDR : 1;
		unsigned int                            EMPH : 1;
		unsigned int                            TXPD : 1;
		unsigned int                           PTERM : 4;
		unsigned int                           NTERM : 4;
		unsigned int                            PDRV : 4;
		unsigned int                            NDRV : 4;
		unsigned int                           TSTEN : 1;
		unsigned int                EDCTX_CLKGATE_EN : 1;
		unsigned int                        TXBYPASS : 1;
		unsigned int                     PLL_LOOPBCK : 1;
		unsigned int                   TXBYPASS_DATA : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCBVM_PERFCOUNTER0_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCBVM_PERFCOUNTER1_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCBVM_PERFCOUNTER2_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCBVM_PERFCOUNTER3_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCBVM_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                      COUNTER_HI : 16;
                unsigned int                   COMPARE_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCBVM_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                      COUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CI__VI {
	struct {
                unsigned int             PERF_COUNTER_SELECT : 4;
                unsigned int                                 : 4;
                unsigned int                   START_TRIGGER : 8;
                unsigned int                    STOP_TRIGGER : 8;
                unsigned int                      ENABLE_ANY : 1;
                unsigned int                       CLEAR_ALL : 1;
                unsigned int            STOP_ALL_ON_SATURATE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCDVM_PERFCOUNTER0_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCDVM_PERFCOUNTER1_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCDVM_PERFCOUNTER2_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCDVM_PERFCOUNTER3_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCDVM_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                      COUNTER_HI : 16;
                unsigned int                   COMPARE_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCDVM_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                      COUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CI__VI {
	struct {
                unsigned int             PERF_COUNTER_SELECT : 4;
                unsigned int                                 : 4;
                unsigned int                   START_TRIGGER : 8;
                unsigned int                    STOP_TRIGGER : 8;
                unsigned int                      ENABLE_ANY : 1;
                unsigned int                       CLEAR_ALL : 1;
                unsigned int            STOP_ALL_ON_SATURATE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_MEM_POWER_LS {
	struct {
		unsigned int                        LS_SETUP : 6;
		unsigned int                         LS_HOLD : 6;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_NPL_STATUS__SI__CI {
	struct {
		unsigned int                       D0_PDELAY : 2;
		unsigned int                       D0_NDELAY : 2;
		unsigned int                       D0_PEARLY : 1;
		unsigned int                       D0_NEARLY : 1;
		unsigned int                       D1_PDELAY : 2;
		unsigned int                       D1_NDELAY : 2;
		unsigned int                       D1_PEARLY : 1;
		unsigned int                       D1_NEARLY : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PHY_TIMING_2__SI__CI {
	struct {
                unsigned int                      IND_LD_CNT : 7;
                unsigned int                                 : 1;
                unsigned int                        RXC0_INV : 1;
                unsigned int                        RXC1_INV : 1;
                unsigned int                        TXC0_INV : 1;
                unsigned int                        TXC1_INV : 1;
                unsigned int                        RXC0_FRC : 1;
                unsigned int                        RXC1_FRC : 1;
                unsigned int                        TXC0_FRC : 1;
                unsigned int                        TXC1_FRC : 1;
                unsigned int                     TX_CDREN_D0 : 1;
                unsigned int                     TX_CDREN_D1 : 1;
                unsigned int                    ADR_CLKEN_D0 : 1;
                unsigned int                    ADR_CLKEN_D1 : 1;
                unsigned int                          WR_DLY : 4;
                unsigned int              RXDPWRONC0_FRC__CI : 1;
                unsigned int              RXDPWRONC1_FRC__CI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PHY_TIMING_D0__SI__CI {
	struct {
		unsigned int                        RXC0_DLY : 4;
		unsigned int                        RXC0_EXT : 4;
		unsigned int                        RXC1_DLY : 4;
		unsigned int                        RXC1_EXT : 4;
		unsigned int                        TXC0_DLY : 3;
		unsigned int                                 : 1;
		unsigned int                        TXC0_EXT : 4;
		unsigned int                        TXC1_DLY : 3;
		unsigned int                                 : 1;
		unsigned int                        TXC1_EXT : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PHY_TIMING_D1__SI__CI {
	struct {
		unsigned int                        RXC0_DLY : 4;
		unsigned int                        RXC0_EXT : 4;
		unsigned int                        RXC1_DLY : 4;
		unsigned int                        RXC1_EXT : 4;
		unsigned int                        TXC0_DLY : 3;
		unsigned int                                 : 1;
		unsigned int                        TXC0_EXT : 4;
		unsigned int                        TXC1_DLY : 3;
		unsigned int                                 : 1;
		unsigned int                        TXC1_EXT : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_AUTO_CFG__SI__CI {
	struct {
                unsigned int                         SYC_CLK : 1;
                unsigned int                         RST_MRS : 1;
                unsigned int                         TRI_MIO : 1;
                unsigned int                                 : 1;
                unsigned int                         XSR_TMR : 4;
                unsigned int                   SS_ALWAYS_SLF : 1;
                unsigned int                        SS_S_SLF : 1;
                unsigned int                       SCDS_MODE : 1;
                unsigned int                 EXIT_ALLOW_STOP : 1;
                unsigned int                         RFS_SRX : 1;
                unsigned int                        PREA_SRX : 1;
                unsigned int                      STUTTER_EN : 1;
                unsigned int               SELFREFR_COMMIT_0 : 1;
                unsigned int                    MRS_WAIT_CNT : 4;
                unsigned int              WRITE_DURING_DLOCK : 1;
                unsigned int                     YCLK_ON__CI : 1;
                unsigned int                          RXPDNB : 1;
                unsigned int               SELFREFR_COMMIT_1 : 1;
                unsigned int                         DLL_CNT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_AUTO_CMD__SI__CI {
	struct {
		unsigned int                             ADR : 17;
		unsigned int                                 : 11;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_CFG__SI__CI {
	struct {
                unsigned int                         SYC_CLK : 1;
                unsigned int                         RST_MRS : 1;
                unsigned int                        RST_EMRS : 1;
                unsigned int                         TRI_MIO : 1;
                unsigned int                         XSR_TMR : 4;
                unsigned int                        RST_MRS1 : 1;
                unsigned int                        RST_MRS2 : 1;
                unsigned int                        DPM_WAKE : 1;
                unsigned int                                 : 1;
                unsigned int                         RFS_SRX : 1;
                unsigned int                        PREA_SRX : 1;
                unsigned int                                 : 2;
                unsigned int                    MRS_WAIT_CNT : 4;
                unsigned int              WRITE_DURING_DLOCK : 1;
                unsigned int                     YCLK_ON__CI : 1;
                unsigned int                  EARLY_ACK_ACPI : 1;
                unsigned int                                 : 2;
                unsigned int                          RXPDNB : 1;
                unsigned int                       ZQCL_SEND : 2;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_CFG__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int              WRITE_DURING_DLOCK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                  EARLY_ACK_ACPI : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_CMD_EMRS__SI__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 3;
		unsigned int                         BNK_MSB : 1;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                                 : 5;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_CMD_EMRS__VI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                                 : 4;
		unsigned int                             MOP : 4;
		unsigned int                             END : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_CMD_MRS__SI__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 3;
		unsigned int                         BNK_MSB : 1;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                                 : 5;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_CMD_MRS__VI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                                 : 4;
		unsigned int                             MOP : 4;
		unsigned int                             END : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_CMD_MRS1__SI__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 3;
		unsigned int                         BNK_MSB : 1;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                                 : 5;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_CMD_MRS1__VI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                                 : 4;
		unsigned int                             MOP : 4;
		unsigned int                             END : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_CMD_MRS2__SI__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 3;
		unsigned int                         BNK_MSB : 1;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                                 : 5;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_PMG_CMD_MRS2__VI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                                 : 4;
		unsigned int                             MOP : 4;
		unsigned int                             END : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_CB {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                       MAX_BURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_DB {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                       MAX_BURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_GRP_EXT {
	struct {
		unsigned int                         DBSTEN0 : 4;
		unsigned int                             TC0 : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_GRP_GFX__CI {
	struct {
		unsigned int                              CP : 4;
		unsigned int                              SH : 4;
		unsigned int                              IA : 4;
		unsigned int                            ACPG : 4;
		unsigned int                            ACPO : 4;
		unsigned int                           XDMAM : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_GRP_GFX__VI {
	struct {
		unsigned int                              CP : 4;
		unsigned int                              SH : 4;
		unsigned int                              IA : 4;
		unsigned int                            ACPG : 4;
		unsigned int                            ACPO : 4;
		unsigned int                             ISP : 4;
		unsigned int                             VP8 : 4;
		unsigned int                           XDMAM : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_GRP_GFX__SI {
	struct {
		unsigned int                              CP : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                           XDMAM : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_GRP_LCL {
	struct {
		unsigned int                                 : 12;
		unsigned int                             CB0 : 4;
		unsigned int                        CBCMASK0 : 4;
		unsigned int                        CBFMASK0 : 4;
		unsigned int                             DB0 : 4;
		unsigned int                        DBHTILE0 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_GRP_OTH__CI {
	struct {
		unsigned int                        UVD_EXT0 : 4;
		unsigned int                           SDMA0 : 4;
		unsigned int                             HDP : 4;
		unsigned int                             SEM : 4;
		unsigned int                             UMC : 4;
		unsigned int                             UVD : 4;
		unsigned int                        UVD_EXT1 : 4;
		unsigned int                             SAM : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_GRP_OTH__VI {
	struct {
		unsigned int                        UVD_EXT0 : 4;
		unsigned int                           SDMA0 : 4;
		unsigned int                             HDP : 4;
		unsigned int                             SEM : 4;
		unsigned int                             UMC : 4;
		unsigned int                             UVD : 4;
		unsigned int                        UVD_EXT1 : 4;
		unsigned int                          SAMMSP : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_GRP_OTH__SI {
	struct {
		unsigned int                        UVD_EXT0 : 4;
		unsigned int                                 : 4;
		unsigned int                             HDP : 4;
		unsigned int                             SEM : 4;
		unsigned int                             UMC : 4;
		unsigned int                             UVD : 4;
		unsigned int                        UVD_EXT1 : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_GRP_SYS__CI__VI {
	struct {
                unsigned int                             RLC : 4;
                unsigned int                             VMC : 4;
                unsigned int                           SDMA1 : 4;
                unsigned int                            DMIF : 4;
                unsigned int                            MCIF : 4;
                unsigned int                             SMU : 4;
                unsigned int                             VCE : 4;
                unsigned int                            VCEU : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_GRP_SYS__SI {
	struct {
		unsigned int                             RLC : 4;
		unsigned int                             VMC : 4;
		unsigned int                                 : 4;
		unsigned int                            DMIF : 4;
		unsigned int                            MCIF : 4;
		unsigned int                             SMU : 4;
		unsigned int                             VCE : 4;
		unsigned int                            VCEU : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_HUB {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                       MAX_BURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_TC0 {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                       MAX_BURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RD_TC1 {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                       MAX_BURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_ARB_CNTL {
	struct {
		unsigned int                   WR_SWITCH_NUM : 8;
		unsigned int                   RD_SWITCH_NUM : 8;
		unsigned int                  ATC_SWITCH_NUM : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_BIF_CNTL {
	struct {
                unsigned int                  ARB_SWITCH_NUM : 8;
                unsigned int                  XPB_SWITCH_NUM : 8;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_CID_QUEUE_EX {
	struct {
		unsigned int                           START : 1;
		unsigned int                          OFFSET : 5;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_CID_QUEUE_EX_DATA {
	struct {
		unsigned int                   WRITE_ENTRIES : 16;
		unsigned int                    READ_ENTRIES : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_CID_QUEUE_RD {
	struct {
		unsigned int                       CLIENT_ID : 8;
		unsigned int                     WRITE_QUEUE : 2;
		unsigned int                      READ_QUEUE : 2;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_CID_QUEUE_WR {
	struct {
		unsigned int                       CLIENT_ID : 8;
		unsigned int                     UPDATE_MODE : 1;
		unsigned int                     WRITE_QUEUE : 2;
		unsigned int                      READ_QUEUE : 2;
		unsigned int                          UPDATE : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_CONF {
	struct {
		unsigned int                                 : 15;
		unsigned int                  XPB_PCIE_ORDER : 1;
		unsigned int               RPB_RD_PCIE_ORDER : 1;
		unsigned int               RPB_WR_PCIE_ORDER : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_DBG1 {
	struct {
		unsigned int          RPB_BIF_OUTSTANDING_RD : 8;
		unsigned int      RPB_BIF_OUTSTANDING_RD_32B : 12;
		unsigned int                      DEBUG_BITS : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_EFF_CNTL {
	struct {
		unsigned int                   WR_LAZY_TIMER : 8;
		unsigned int                   RD_LAZY_TIMER : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_IF_CONF {
	struct {
		unsigned int                 RPB_BIF_CREDITS : 8;
		unsigned int           OUTSTANDING_WRRET_ASK : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_PERFCOUNTER0_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_PERFCOUNTER1_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_PERFCOUNTER2_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_PERFCOUNTER3_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                      COUNTER_HI : 16;
                unsigned int                   COMPARE_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                      COUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_PERFCOUNTER_RSLT_CNTL__CI__VI {
	struct {
                unsigned int             PERF_COUNTER_SELECT : 4;
                unsigned int                                 : 4;
                unsigned int                   START_TRIGGER : 8;
                unsigned int                    STOP_TRIGGER : 8;
                unsigned int                      ENABLE_ANY : 1;
                unsigned int                       CLEAR_ALL : 1;
                unsigned int            STOP_ALL_ON_SATURATE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_PERF_COUNTER_CNTL {
	struct {
		unsigned int             PERF_COUNTER_SELECT : 2;
		unsigned int     CLEAR_SELECTED_PERF_COUNTER : 1;
		unsigned int         CLEAR_ALL_PERF_COUNTERS : 1;
		unsigned int      STOP_ON_COUNTER_SATURATION : 1;
		unsigned int            ENABLE_PERF_COUNTERS : 4;
		unsigned int           PERF_COUNTER_ASSIGN_0 : 5;
		unsigned int           PERF_COUNTER_ASSIGN_1 : 5;
		unsigned int           PERF_COUNTER_ASSIGN_2 : 5;
		unsigned int           PERF_COUNTER_ASSIGN_3 : 5;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_PERF_COUNTER_STATUS {
	struct {
		unsigned int       PERFORMANCE_COUNTER_VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_RD_SWITCH_CNTL {
	struct {
		unsigned int               QUEUE0_SWITCH_NUM : 8;
		unsigned int               QUEUE1_SWITCH_NUM : 8;
		unsigned int               QUEUE2_SWITCH_NUM : 8;
		unsigned int               QUEUE3_SWITCH_NUM : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_WR_COMBINE_CNTL {
	struct {
		unsigned int                       WC_ENABLE : 1;
		unsigned int              WC_MAX_PACKET_SIZE : 2;
		unsigned int                  WC_FLUSH_TIMER : 4;
		unsigned int                        WC_ALIGN : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_WR_SWITCH_CNTL {
	struct {
		unsigned int               QUEUE0_SWITCH_NUM : 8;
		unsigned int               QUEUE1_SWITCH_NUM : 8;
		unsigned int               QUEUE2_SWITCH_NUM : 8;
		unsigned int               QUEUE3_SWITCH_NUM : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_BIT_REMAP_B0_D0__SI__CI {
	struct {
		unsigned int                            BIT0 : 3;
		unsigned int                            BIT1 : 3;
		unsigned int                            BIT2 : 3;
		unsigned int                            BIT3 : 3;
		unsigned int                            BIT4 : 3;
		unsigned int                            BIT5 : 3;
		unsigned int                            BIT6 : 3;
		unsigned int                            BIT7 : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_BIT_REMAP_B0_D1__SI__CI {
	struct {
		unsigned int                            BIT0 : 3;
		unsigned int                            BIT1 : 3;
		unsigned int                            BIT2 : 3;
		unsigned int                            BIT3 : 3;
		unsigned int                            BIT4 : 3;
		unsigned int                            BIT5 : 3;
		unsigned int                            BIT6 : 3;
		unsigned int                            BIT7 : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_BIT_REMAP_B1_D0__SI__CI {
	struct {
		unsigned int                            BIT0 : 3;
		unsigned int                            BIT1 : 3;
		unsigned int                            BIT2 : 3;
		unsigned int                            BIT3 : 3;
		unsigned int                            BIT4 : 3;
		unsigned int                            BIT5 : 3;
		unsigned int                            BIT6 : 3;
		unsigned int                            BIT7 : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_BIT_REMAP_B1_D1__SI__CI {
	struct {
		unsigned int                            BIT0 : 3;
		unsigned int                            BIT1 : 3;
		unsigned int                            BIT2 : 3;
		unsigned int                            BIT3 : 3;
		unsigned int                            BIT4 : 3;
		unsigned int                            BIT5 : 3;
		unsigned int                            BIT6 : 3;
		unsigned int                            BIT7 : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_BIT_REMAP_B2_D0__SI__CI {
	struct {
		unsigned int                            BIT0 : 3;
		unsigned int                            BIT1 : 3;
		unsigned int                            BIT2 : 3;
		unsigned int                            BIT3 : 3;
		unsigned int                            BIT4 : 3;
		unsigned int                            BIT5 : 3;
		unsigned int                            BIT6 : 3;
		unsigned int                            BIT7 : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_BIT_REMAP_B2_D1__SI__CI {
	struct {
		unsigned int                            BIT0 : 3;
		unsigned int                            BIT1 : 3;
		unsigned int                            BIT2 : 3;
		unsigned int                            BIT3 : 3;
		unsigned int                            BIT4 : 3;
		unsigned int                            BIT5 : 3;
		unsigned int                            BIT6 : 3;
		unsigned int                            BIT7 : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_BIT_REMAP_B3_D0__SI__CI {
	struct {
		unsigned int                            BIT0 : 3;
		unsigned int                            BIT1 : 3;
		unsigned int                            BIT2 : 3;
		unsigned int                            BIT3 : 3;
		unsigned int                            BIT4 : 3;
		unsigned int                            BIT5 : 3;
		unsigned int                            BIT6 : 3;
		unsigned int                            BIT7 : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_BIT_REMAP_B3_D1__SI__CI {
	struct {
		unsigned int                            BIT0 : 3;
		unsigned int                            BIT1 : 3;
		unsigned int                            BIT2 : 3;
		unsigned int                            BIT3 : 3;
		unsigned int                            BIT4 : 3;
		unsigned int                            BIT5 : 3;
		unsigned int                            BIT6 : 3;
		unsigned int                            BIT7 : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_BYTE_REMAP_D0__SI__CI {
	struct {
		unsigned int                           BYTE0 : 2;
		unsigned int                           BYTE1 : 2;
		unsigned int                           BYTE2 : 2;
		unsigned int                           BYTE3 : 2;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_BYTE_REMAP_D1__SI__CI {
	struct {
		unsigned int                           BYTE0 : 2;
		unsigned int                           BYTE1 : 2;
		unsigned int                           BYTE2 : 2;
		unsigned int                           BYTE3 : 2;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CAS_TIMING__SI__CI {
	struct {
		unsigned int                           TNOPW : 2;
		unsigned int                           TNOPR : 2;
		unsigned int                            TR2W : 5;
		unsigned int                           TCCDL : 3;
		unsigned int                            TR2R : 4;
		unsigned int                            TW2R : 5;
		unsigned int                                 : 3;
		unsigned int                             TCL : 5;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CAS_TIMING__VI {
	struct {
		unsigned int                           TNOPW : 2;
		unsigned int                           TNOPR : 2;
		unsigned int                            TR2W : 5;
		unsigned int                           TCCDL : 3;
		unsigned int                            TR2R : 4;
		unsigned int                            TW2R : 5;
		unsigned int                             TCL : 5;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CAS_TIMING_LP__SI__CI {
	struct {
		unsigned int                           TNOPW : 2;
		unsigned int                           TNOPR : 2;
		unsigned int                            TR2W : 5;
		unsigned int                           TCCDL : 3;
		unsigned int                            TR2R : 4;
		unsigned int                            TW2R : 5;
		unsigned int                                 : 3;
		unsigned int                             TCL : 5;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CAS_TIMING_LP__VI {
	struct {
		unsigned int                           TNOPW : 2;
		unsigned int                           TNOPR : 2;
		unsigned int                            TR2W : 5;
		unsigned int                           TCCDL : 3;
		unsigned int                            TR2R : 4;
		unsigned int                            TW2R : 5;
		unsigned int                             TCL : 5;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CG {
	struct {
		unsigned int                      CG_SEQ_REQ : 8;
		unsigned int                     CG_SEQ_RESP : 8;
		unsigned int                      SEQ_CG_REQ : 8;
		unsigned int                     SEQ_CG_RESP : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CMD__SI__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 4;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                                 : 1;
		unsigned int                           CHAN0 : 1;
		unsigned int                           CHAN1 : 1;
		unsigned int                                 : 2;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CMD__VI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                                 : 4;
		unsigned int                             MOP : 4;
		unsigned int                             END : 1;
		unsigned int                                 : 3;
		unsigned int                           CHAN0 : 1;
		unsigned int                           CHAN1 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CNTL__SI__CI {
	struct {
                unsigned int               MEM_ADDR_MAP_COLS : 2;
                unsigned int               MEM_ADDR_MAP_BANK : 2;
                unsigned int                       SAFE_MODE : 2;
                unsigned int                         DAT_INV : 1;
                unsigned int                         MSK_DF1 : 1;
                unsigned int                 CHANNEL_DISABLE : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                   MSKOFF_DAT_TL : 1;
                unsigned int                   MSKOFF_DAT_TH : 1;
                unsigned int                    RET_HOLD_EOP : 1;
                unsigned int                  BANKGROUP_SIZE : 1;
                unsigned int                   BANKGROUP_ENB : 1;
                unsigned int                    RTR_OVERRIDE : 1;
                unsigned int                  ARB_REQCMD_WMK : 4;
                unsigned int                  ARB_REQDAT_WMK : 4;
                unsigned int                   ARB_RTDAT_WMK : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CNTL__VI {
	struct {
		unsigned int                 CHANNEL_DISABLE : 4;
		unsigned int                       SAFE_MODE : 2;
		unsigned int                         DAT_INV : 1;
		unsigned int                    RET_HOLD_EOP : 1;
		unsigned int                  BANKGROUP_SIZE : 1;
		unsigned int                   BANKGROUP_ENB : 1;
		unsigned int                   MSKOFF_DAT_TL : 1;
		unsigned int                   MSKOFF_DAT_TH : 1;
		unsigned int                  ARB_REQCMD_WMK : 4;
		unsigned int                  ARB_REQDAT_WMK : 4;
		unsigned int                   ARB_RTDAT_WMK : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                    RTR_OVERRIDE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CNTL_2__CI {
	struct {
		unsigned int                       DRST_PDRV : 4;
		unsigned int                         DRST_PU : 1;
		unsigned int                         DRST_PD : 1;
		unsigned int                                 : 2;
		unsigned int               ARB_RTDAT_WMK_MSB : 2;
		unsigned int                       DRST_NSTR : 6;
		unsigned int                       DRST_PSTR : 6;
		unsigned int                 PLL_TX_PWRON_D0 : 1;
		unsigned int                 PLL_TX_PWRON_D1 : 1;
		unsigned int                 PLL_RX_PWRON_D0 : 4;
		unsigned int                 PLL_RX_PWRON_D1 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CNTL_2__VI {
	struct {
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CNTL_2__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int               ARB_RTDAT_WMK_MSB : 2;
		unsigned int                       DRST_NSTR : 6;
		unsigned int                       DRST_PSTR : 6;
		unsigned int                 PLL_TX_PWRON_D0 : 1;
		unsigned int                 PLL_TX_PWRON_D1 : 1;
		unsigned int                 PLL_RX_PWRON_D0 : 4;
		unsigned int                 PLL_RX_PWRON_D1 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CNTL_3__CI {
	struct {
		unsigned int               PIPE_DELAY_OUT_D0 : 3;
		unsigned int                PIPE_DELAY_IN_D0 : 3;
		unsigned int               PIPE_DELAY_OUT_D1 : 3;
		unsigned int                PIPE_DELAY_IN_D1 : 3;
		unsigned int                     REPCG_EN_D0 : 1;
		unsigned int                     REPCG_EN_D1 : 1;
		unsigned int                                 : 2;
		unsigned int                   REPCG_OFF_DLY : 4;
		unsigned int                         FCK_FRC : 1;
		unsigned int                         DBI_FRC : 1;
		unsigned int                       PRGRM_CDC : 1;
		unsigned int                         DQS_FRC : 1;
		unsigned int                     DQS_FRC_PAT : 4;
		unsigned int                                 : 2;
		unsigned int                         IDSC_EN : 1;
		unsigned int                          CAC_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_CNTL_3__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_DLL_STBY_LP__CI {
	struct {
		unsigned int                              EN : 1;
		unsigned int                    VCTRLADC_FRC : 1;
		unsigned int                    VCTRLADC_VAL : 1;
		unsigned int                    MSTRSTBY_FRC : 1;
		unsigned int                    MSTRSTBY_VAL : 1;
		unsigned int                        ENTR_DLY : 3;
		unsigned int                        STBY_DLY : 4;
		unsigned int                 TCKE_PULSE_EXTN : 4;
		unsigned int                       TCKE_EXTN : 8;
		unsigned int                        EXIT_DLY : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_DLL_STBY__CI {
	struct {
		unsigned int                              EN : 1;
		unsigned int                    VCTRLADC_FRC : 1;
		unsigned int                    VCTRLADC_VAL : 1;
		unsigned int                    MSTRSTBY_FRC : 1;
		unsigned int                    MSTRSTBY_VAL : 1;
		unsigned int                        ENTR_DLY : 3;
		unsigned int                        STBY_DLY : 4;
		unsigned int                 TCKE_PULSE_EXTN : 4;
		unsigned int                       TCKE_EXTN : 8;
		unsigned int                        EXIT_DLY : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_DRAM__SI__CI {
	struct {
                unsigned int                         ADR_2CK : 1;
                unsigned int                         ADR_MUX : 1;
                unsigned int                         ADR_DF1 : 1;
                unsigned int                             AP8 : 1;
                unsigned int                         DAT_DF1 : 1;
                unsigned int                         DQS_DF1 : 1;
                unsigned int                         DQM_DF1 : 1;
                unsigned int                         DQM_ACT : 1;
                unsigned int                         STB_CNT : 4;
                unsigned int                         CKE_DYN : 1;
                unsigned int                         CKE_ACT : 1;
                unsigned int                             BO4 : 1;
                unsigned int                         DLL_CLR : 1;
                unsigned int                         DLL_CNT : 8;
                unsigned int                         DAT_INV : 1;
                unsigned int                         INV_ACM : 1;
                unsigned int                         ODT_ENB : 1;
                unsigned int                         ODT_ACT : 1;
                unsigned int                         RST_CTL : 1;
                unsigned int                     TRI_MIO_DYN : 1;
                unsigned int                         TRI_CKE : 1;
                unsigned int             RDSTRB_RSYC_DIS__CI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_DRAM__VI {
	struct {
		unsigned int                         STB_CNT : 4;
		unsigned int                         CKE_DYN : 1;
		unsigned int                         CKE_ACT : 1;
		unsigned int                         DAT_INV : 1;
		unsigned int                         INV_ACM : 1;
		unsigned int                         RST_CTL : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                         DQM_ACT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_DRAM_2__SI__CI {
	struct {
		unsigned int                         ADR_DDR : 1;
		unsigned int                         ADR_DBI : 1;
		unsigned int                     ADR_DBI_ACM : 1;
		unsigned int                         CMD_QDR : 1;
		unsigned int                         DAT_QDR : 1;
		unsigned int                        WDAT_EDC : 1;
		unsigned int                        RDAT_EDC : 1;
		unsigned int                         DQM_EST : 1;
		unsigned int                          RD_DQS : 1;
		unsigned int                          WR_DQS : 1;
		unsigned int                         PLL_EST : 1;
		unsigned int                         PLL_CLR : 1;
		unsigned int                         DLL_EST : 1;
		unsigned int                         BNK_MRS : 1;
		unsigned int                         DBI_OVR : 1;
		unsigned int                         TRI_CLK : 1;
		unsigned int                         PLL_CNT : 8;
		unsigned int                         PCH_BNK : 1;
		unsigned int                        ADBI_DF1 : 1;
		unsigned int                        ADBI_ACT : 1;
		unsigned int                         DBI_DF1 : 1;
		unsigned int                         DBI_ACT : 1;
		unsigned int                     DBI_EDC_DF1 : 1;
		unsigned int                     TESTCHIP_EN : 1;
		unsigned int                         CS_BY16 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_DRAM_2__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         PCH_BNK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                        WDAT_EDC : 1;
		unsigned int                        RDAT_EDC : 1;
		unsigned int                                 : 4;
		unsigned int                         DLL_EST : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_DRAM_ERROR_INSERTION__SI__CI {
	struct {
		unsigned int                              TX : 16;
		unsigned int                              RX : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_FIFO_CTL__SI__CI {
	struct {
                unsigned int                    W_LD_INIT_D0 : 2;
                unsigned int                       W_SYC_SEL : 2;
                unsigned int                       R_LD_INIT : 2;
                unsigned int                       R_SYC_SEL : 2;
                unsigned int                       CG_DIS_D0 : 1;
                unsigned int                       CG_DIS_D1 : 1;
                unsigned int                    W_LD_INIT_D1 : 2;
                unsigned int                         SYC_DLY : 3;
                unsigned int                                 : 1;
                unsigned int                      W_ASYC_EXT : 2;
                unsigned int                      W_DSYC_EXT : 2;
                unsigned int               R_DQS_LD_INIT__CI : 4;
                unsigned int                  R_DQS_STEP__CI : 4;
                unsigned int                   R_DQS_FRC__CI : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_FIFO_CTL__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_G5PDX_CMD0_LP__CI {
	struct {
		unsigned int                             CMD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_G5PDX_CMD0__CI {
	struct {
		unsigned int                             CMD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_G5PDX_CMD1_LP__CI {
	struct {
		unsigned int                             CMD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_G5PDX_CMD1__CI {
	struct {
		unsigned int                             CMD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_G5PDX_CTRL_LP__CI {
	struct {
		unsigned int                      CH0_ENABLE : 1;
		unsigned int                      CH1_ENABLE : 1;
		unsigned int                    WCKOFF_EARLY : 1;
		unsigned int                     WCKOFF_LATE : 1;
		unsigned int                         TPD2MRS : 6;
		unsigned int                                 : 2;
		unsigned int                        TMRS2WCK : 4;
		unsigned int                        TWCK2MRS : 4;
		unsigned int                            TMRD : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_G5PDX_CTRL__CI {
	struct {
		unsigned int                      CH0_ENABLE : 1;
		unsigned int                      CH1_ENABLE : 1;
		unsigned int                    WCKOFF_EARLY : 1;
		unsigned int                     WCKOFF_LATE : 1;
		unsigned int                         TPD2MRS : 6;
		unsigned int                                 : 2;
		unsigned int                        TMRS2WCK : 4;
		unsigned int                        TWCK2MRS : 4;
		unsigned int                            TMRD : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_DEBUG_DATA {
	struct {
		unsigned int                   IO_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_DEBUG_INDEX {
	struct {
		unsigned int                  IO_DEBUG_INDEX : 9;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RDBI__SI__CI {
	struct {
		unsigned int                            MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_REDC__SI__CI {
	struct {
		unsigned int                             EDC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RESERVE_D0__SI__CI {
	struct {
		unsigned int                       DPHY0_RSV : 12;
		unsigned int                       DPHY1_RSV : 12;
		unsigned int                        APHY_RSV : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RESERVE_D1__SI__CI {
	struct {
		unsigned int                       DPHY0_RSV : 12;
		unsigned int                       DPHY1_RSV : 12;
		unsigned int                        APHY_RSV : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RWORD0__SI__CI {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RWORD1__SI__CI {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RWORD2__SI__CI {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RWORD3__SI__CI {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RWORD4__SI__CI {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RWORD5__SI__CI {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RWORD6__SI__CI {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RWORD7__SI__CI {
	struct {
		unsigned int                           RDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC0 {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC1 {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC3 {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC4 {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC5 {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC6 {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC7 {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC8 {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC9 {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC_TIMING__SI__CI {
	struct {
		unsigned int                         TRP_WRA : 6;
		unsigned int                                 : 2;
		unsigned int                         TRP_RDA : 6;
		unsigned int                                 : 1;
		unsigned int                             TRP : 5;
		unsigned int                            TRFC : 9;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC_TIMING__VI {
	struct {
		unsigned int                         TRP_WRA : 6;
		unsigned int                         TRP_RDA : 6;
		unsigned int                             TRP : 5;
		unsigned int                            TRFC : 7;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC_TIMING2__SI__CI {
	struct {
		unsigned int                        PA2RDATA : 3;
		unsigned int                                 : 1;
		unsigned int                        PA2WDATA : 3;
		unsigned int                                 : 1;
		unsigned int                             FAW : 5;
		unsigned int                           TREDC : 3;
		unsigned int                           TWEDC : 5;
		unsigned int                           T32AW : 4;
		unsigned int                                 : 3;
		unsigned int                        TWDATATR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC_TIMING2__VI {
	struct {
		unsigned int                        PA2RDATA : 3;
		unsigned int                        PA2WDATA : 3;
		unsigned int                             FAW : 5;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                           T32AW : 4;
		unsigned int                        TWDATATR : 4;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC_TIMING2_LP__SI__CI {
	struct {
		unsigned int                        PA2RDATA : 3;
		unsigned int                                 : 1;
		unsigned int                        PA2WDATA : 3;
		unsigned int                                 : 1;
		unsigned int                             FAW : 5;
		unsigned int                           TREDC : 3;
		unsigned int                           TWEDC : 5;
		unsigned int                            TADR : 3;
		unsigned int                          TFCKTR : 4;
		unsigned int                        TWDATATR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC_TIMING2_LP__VI {
	struct {
		unsigned int                        PA2RDATA : 3;
		unsigned int                        PA2WDATA : 3;
		unsigned int                             FAW : 5;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 4;
		unsigned int                        TWDATATR : 4;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC_TIMING_LP__SI__CI {
	struct {
		unsigned int                         TRP_WRA : 6;
		unsigned int                                 : 2;
		unsigned int                         TRP_RDA : 6;
		unsigned int                                 : 1;
		unsigned int                             TRP : 5;
		unsigned int                            TRFC : 9;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MISC_TIMING_LP__VI {
	struct {
		unsigned int                         TRP_WRA : 6;
		unsigned int                         TRP_RDA : 6;
		unsigned int                             TRP : 5;
		unsigned int                            TRFC : 7;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_MPLL_OVERRIDE__SI__CI {
	struct {
		unsigned int           AD_PLL_RESET_OVERRIDE : 1;
		unsigned int       DQ_0_0_PLL_RESET_OVERRIDE : 1;
		unsigned int       DQ_0_1_PLL_RESET_OVERRIDE : 1;
		unsigned int       DQ_1_0_PLL_RESET_OVERRIDE : 1;
		unsigned int       DQ_1_1_PLL_RESET_OVERRIDE : 1;
		unsigned int           ATGM_CLK_SEL_OVERRIDE : 1;
		unsigned int     TEST_BYPASS_CLK_EN_OVERRIDE : 1;
		unsigned int    TEST_BYPASS_CLK_SEL_OVERRIDE : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_CNTL__SI__CI {
	struct {
		unsigned int                  MONITOR_PERIOD : 30;
		unsigned int                            CNTL : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_CNTL_1__SI__CI {
	struct {
		unsigned int                           PAUSE : 1;
		unsigned int                                 : 7;
		unsigned int                       SEL_A_MSB : 1;
		unsigned int                       SEL_B_MSB : 1;
		unsigned int                   SEL_CH0_C_MSB : 1;
		unsigned int                   SEL_CH0_D_MSB : 1;
		unsigned int                   SEL_CH1_A_MSB : 1;
		unsigned int                   SEL_CH1_B_MSB : 1;
		unsigned int                   SEL_CH1_C_MSB : 1;
		unsigned int                   SEL_CH1_D_MSB : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_SEQ_CNT_A_I0__SI__CI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_SEQ_CNT_A_I1__SI__CI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_SEQ_CNT_B_I0__SI__CI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_SEQ_CNT_B_I1__SI__CI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_SEQ_CNT_C_I0__SI__CI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_SEQ_CNT_C_I1__SI__CI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_SEQ_CNT_D_I0__SI__CI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_SEQ_CNT_D_I1__SI__CI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PERF_SEQ_CTL__SI__CI {
	struct {
		unsigned int                           SEL_A : 4;
		unsigned int                           SEL_B : 4;
		unsigned int                       SEL_CH0_C : 4;
		unsigned int                       SEL_CH0_D : 4;
		unsigned int                       SEL_CH1_A : 4;
		unsigned int                       SEL_CH1_B : 4;
		unsigned int                       SEL_CH1_C : 4;
		unsigned int                       SEL_CH1_D : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PHYREG_BCAST__CI {
	struct {
		unsigned int                          CH0_EN : 1;
		unsigned int                          CH1_EN : 1;
		unsigned int                                 : 5;
		unsigned int                        CKE_MASK : 1;
		unsigned int                         DQ_MASK : 1;
		unsigned int                        DBI_MASK : 1;
		unsigned int                        EDC_MASK : 1;
		unsigned int                        WCK_MASK : 1;
		unsigned int                       WCDR_MASK : 1;
		unsigned int                        CLK_MASK : 1;
		unsigned int                        CMD_MASK : 1;
		unsigned int                        ADR_MASK : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_CMD_EMRS_LP__SI__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 3;
		unsigned int                         BNK_MSB : 1;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                                 : 5;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_CMD_MRS1_LP__SI__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 3;
		unsigned int                         BNK_MSB : 1;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                                 : 5;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_CMD_MRS2_LP__SI__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 3;
		unsigned int                         BNK_MSB : 1;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                                 : 5;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_CMD_MRS_LP__SI__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 3;
		unsigned int                         BNK_MSB : 1;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                                 : 5;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_DVS_CMD_LP__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 3;
		unsigned int                         BNK_MSB : 1;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_DVS_CMD__CI {
	struct {
		unsigned int                             ADR : 16;
		unsigned int                             MOP : 3;
		unsigned int                         BNK_MSB : 1;
		unsigned int                             END : 1;
		unsigned int                             CSB : 2;
		unsigned int                        ADR_MSB1 : 1;
		unsigned int                        ADR_MSB0 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_DVS_CTL_LP__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                            TDVS : 5;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_DVS_CTL__CI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                            TDVS : 5;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_PG_HWCNTL__SI__CI {
	struct {
		unsigned int                      PWRGATE_EN : 1;
		unsigned int                      STAGGER_EN : 1;
		unsigned int                           TPGCG : 4;
		unsigned int                           D_DLY : 2;
		unsigned int                          AC_DLY : 2;
		unsigned int                           G_DLY : 4;
		unsigned int                                 : 2;
		unsigned int                            TXAO : 1;
		unsigned int                            RXAO : 1;
		unsigned int                            ACAO : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_PG_SWCNTL_0__SI__CI {
	struct {
		unsigned int                  PMD0_DQ_TX_ENB : 1;
		unsigned int                 PMD0_DBI_TX_ENB : 1;
		unsigned int                 PMD0_EDC_TX_ENB : 1;
		unsigned int               PMD0_WCLKX_TX_ENB : 1;
		unsigned int                  PMD0_DQ_RX_ENB : 1;
		unsigned int                 PMD0_DBI_RX_ENB : 1;
		unsigned int                 PMD0_EDC_RX_ENB : 1;
		unsigned int               PMD0_WCLKX_RX_ENB : 1;
		unsigned int                  PMD1_DQ_TX_ENB : 1;
		unsigned int                 PMD1_DBI_TX_ENB : 1;
		unsigned int                 PMD1_EDC_TX_ENB : 1;
		unsigned int               PMD1_WCLKX_TX_ENB : 1;
		unsigned int                  PMD1_DQ_RX_ENB : 1;
		unsigned int                 PMD1_DBI_RX_ENB : 1;
		unsigned int                 PMD1_EDC_RX_ENB : 1;
		unsigned int               PMD1_WCLKX_RX_ENB : 1;
		unsigned int                     PMA0_AC_ENB : 1;
		unsigned int                                 : 14;
		unsigned int                 GMCON_SR_COMMIT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_PG_SWCNTL_1__SI__CI {
	struct {
		unsigned int                  PMD2_DQ_TX_ENB : 1;
		unsigned int                 PMD2_DBI_TX_ENB : 1;
		unsigned int                 PMD2_EDC_TX_ENB : 1;
		unsigned int               PMD2_WCLKX_TX_ENB : 1;
		unsigned int                  PMD2_DQ_RX_ENB : 1;
		unsigned int                 PMD2_DBI_RX_ENB : 1;
		unsigned int                 PMD2_EDC_RX_ENB : 1;
		unsigned int               PMD2_WCLKX_RX_ENB : 1;
		unsigned int                  PMD3_DQ_TX_ENB : 1;
		unsigned int                 PMD3_DBI_TX_ENB : 1;
		unsigned int                 PMD3_EDC_TX_ENB : 1;
		unsigned int               PMD3_WCLKX_TX_ENB : 1;
		unsigned int                  PMD3_DQ_RX_ENB : 1;
		unsigned int                 PMD3_DBI_RX_ENB : 1;
		unsigned int                 PMD3_EDC_RX_ENB : 1;
		unsigned int               PMD3_WCLKX_RX_ENB : 1;
		unsigned int                     PMA1_AC_ENB : 1;
		unsigned int                                 : 14;
		unsigned int                 GMCON_SR_COMMIT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_TIMING__SI__CI {
	struct {
                unsigned int                          TCKSRE : 3;
                unsigned int                                 : 1;
                unsigned int                          TCKSRX : 3;
                unsigned int                                 : 1;
                unsigned int                      TCKE_PULSE : 4;
                unsigned int                            TCKE : 6;
                unsigned int                        SEQ_IDLE : 3;
                unsigned int                                 : 2;
                unsigned int                  TCKE_PULSE_MSB : 1;
                unsigned int                 SEQ_IDLE_SS__CI : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_TIMING__VI {
	struct {
		unsigned int                          TCKSRE : 3;
		unsigned int                          TCKSRX : 3;
		unsigned int                      TCKE_PULSE : 5;
		unsigned int                            TCKE : 8;
		unsigned int                        SEQ_IDLE : 3;
		unsigned int                     SEQ_IDLE_SS : 8;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_TIMING_LP__SI__CI {
	struct {
                unsigned int                          TCKSRE : 3;
                unsigned int                                 : 1;
                unsigned int                          TCKSRX : 3;
                unsigned int                                 : 1;
                unsigned int                      TCKE_PULSE : 4;
                unsigned int                            TCKE : 6;
                unsigned int                        SEQ_IDLE : 3;
                unsigned int                                 : 2;
                unsigned int                  TCKE_PULSE_MSB : 1;
                unsigned int                 SEQ_IDLE_SS__CI : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_PMG_TIMING_LP__VI {
	struct {
		unsigned int                          TCKSRE : 3;
		unsigned int                          TCKSRX : 3;
		unsigned int                      TCKE_PULSE : 5;
		unsigned int                            TCKE : 8;
		unsigned int                        SEQ_IDLE : 3;
		unsigned int                     SEQ_IDLE_SS : 8;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RAS_TIMING {
	struct {
		unsigned int                           TRCDW : 5;
		unsigned int                          TRCDWA : 5;
		unsigned int                           TRCDR : 5;
		unsigned int                          TRCDRA : 5;
		unsigned int                            TRRD : 4;
		unsigned int                             TRC : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RAS_TIMING_LP {
	struct {
		unsigned int                           TRCDW : 5;
		unsigned int                          TRCDWA : 5;
		unsigned int                           TRCDR : 5;
		unsigned int                          TRCDRA : 5;
		unsigned int                            TRRD : 4;
		unsigned int                             TRC : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RD_CTL_D0__SI__CI {
	struct {
		unsigned int                         RCV_DLY : 3;
		unsigned int                         RCV_EXT : 5;
		unsigned int                         RST_SEL : 2;
		unsigned int                    RXDPWRON_DLY : 2;
		unsigned int                         RST_HLD : 4;
		unsigned int                         STR_PRE : 1;
		unsigned int                         STR_PST : 1;
		unsigned int                                 : 2;
		unsigned int                         RBS_DLY : 5;
		unsigned int                    RBS_WEDC_DLY : 5;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RD_CTL_D0__VI {
	struct {
		unsigned int                         RCV_DLY : 3;
		unsigned int                         RCV_EXT : 5;
		unsigned int                         RST_SEL : 2;
		unsigned int                         RST_HLD : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                         RBS_DLY : 5;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RD_CTL_D0_LP__SI__CI {
	struct {
		unsigned int                         RCV_DLY : 3;
		unsigned int                         RCV_EXT : 5;
		unsigned int                         RST_SEL : 2;
		unsigned int                    RXDPWRON_DLY : 2;
		unsigned int                         RST_HLD : 4;
		unsigned int                         STR_PRE : 1;
		unsigned int                         STR_PST : 1;
		unsigned int                                 : 2;
		unsigned int                         RBS_DLY : 5;
		unsigned int                    RBS_WEDC_DLY : 5;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RD_CTL_D0_LP__VI {
	struct {
		unsigned int                         RCV_DLY : 3;
		unsigned int                         RCV_EXT : 5;
		unsigned int                         RST_SEL : 2;
		unsigned int                         RST_HLD : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                         RBS_DLY : 5;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RD_CTL_D1__SI__CI {
	struct {
		unsigned int                         RCV_DLY : 3;
		unsigned int                         RCV_EXT : 5;
		unsigned int                         RST_SEL : 2;
		unsigned int                    RXDPWRON_DLY : 2;
		unsigned int                         RST_HLD : 4;
		unsigned int                         STR_PRE : 1;
		unsigned int                         STR_PST : 1;
		unsigned int                                 : 2;
		unsigned int                         RBS_DLY : 5;
		unsigned int                    RBS_WEDC_DLY : 5;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RD_CTL_D1__VI {
	struct {
		unsigned int                         RCV_DLY : 3;
		unsigned int                         RCV_EXT : 5;
		unsigned int                         RST_SEL : 2;
		unsigned int                         RST_HLD : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                         RBS_DLY : 5;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RD_CTL_D1_LP__SI__CI {
	struct {
		unsigned int                         RCV_DLY : 3;
		unsigned int                         RCV_EXT : 5;
		unsigned int                         RST_SEL : 2;
		unsigned int                    RXDPWRON_DLY : 2;
		unsigned int                         RST_HLD : 4;
		unsigned int                         STR_PRE : 1;
		unsigned int                         STR_PST : 1;
		unsigned int                                 : 2;
		unsigned int                         RBS_DLY : 5;
		unsigned int                    RBS_WEDC_DLY : 5;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RD_CTL_D1_LP__VI {
	struct {
		unsigned int                         RCV_DLY : 3;
		unsigned int                         RCV_EXT : 5;
		unsigned int                         RST_SEL : 2;
		unsigned int                         RST_HLD : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                         RBS_DLY : 5;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RESERVE_0_S {
	struct {
		unsigned int                      SCLK_FIELD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RESERVE_1_S {
	struct {
		unsigned int                      SCLK_FIELD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RESERVE_M {
	struct {
		unsigned int                      MCLK_FIELD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_BYTE0_D0__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_BYTE0_D1__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_BYTE1_D0__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_BYTE1_D1__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_BYTE2_D0__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_BYTE2_D1__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_BYTE3_D0__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_BYTE3_D1__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_DBI_D0__SI__CI {
	struct {
		unsigned int                            DBI0 : 4;
		unsigned int                            DBI1 : 4;
		unsigned int                            DBI2 : 4;
		unsigned int                            DBI3 : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_DBI_D1__SI__CI {
	struct {
		unsigned int                            DBI0 : 4;
		unsigned int                            DBI1 : 4;
		unsigned int                            DBI2 : 4;
		unsigned int                            DBI3 : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_EDC_D0__SI__CI {
	struct {
		unsigned int                            EDC0 : 4;
		unsigned int                            EDC1 : 4;
		unsigned int                            EDC2 : 4;
		unsigned int                            EDC3 : 4;
		unsigned int                           WCDR0 : 4;
		unsigned int                           WCDR1 : 4;
		unsigned int                           WCDR2 : 4;
		unsigned int                           WCDR3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_RXFRAMING_EDC_D1__SI__CI {
	struct {
		unsigned int                            EDC0 : 4;
		unsigned int                            EDC1 : 4;
		unsigned int                            EDC2 : 4;
		unsigned int                            EDC3 : 4;
		unsigned int                           WCDR0 : 4;
		unsigned int                           WCDR1 : 4;
		unsigned int                           WCDR2 : 4;
		unsigned int                           WCDR3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SREG_READ__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SREG_STATUS__CI__VI {
	struct {
                unsigned int                       AVAIL_RTN : 4;
                unsigned int                                 : 4;
                unsigned int                          PND_RD : 4;
                unsigned int                          PND_WR : 4;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_STATUS_M__SI__CI {
	struct {
                unsigned int                  PWRUP_COMPL_D0 : 1;
                unsigned int                  PWRUP_COMPL_D1 : 1;
                unsigned int                      CMD_RDY_D0 : 1;
                unsigned int                      CMD_RDY_D1 : 1;
                unsigned int                          SLF_D0 : 1;
                unsigned int                          SLF_D1 : 1;
                unsigned int                       SS_SLF_D0 : 1;
                unsigned int                       SS_SLF_D1 : 1;
                unsigned int         SEQ0_ARB_CMD_FIFO_EMPTY : 1;
                unsigned int         SEQ1_ARB_CMD_FIFO_EMPTY : 1;
                unsigned int                                 : 2;
                unsigned int          SEQ0_RS_DATA_FIFO_FULL : 1;
                unsigned int          SEQ1_RS_DATA_FIFO_FULL : 1;
                unsigned int                       SEQ0_BUSY : 1;
                unsigned int                       SEQ1_BUSY : 1;
                unsigned int                    PMG_PWRSTATE : 1;
                unsigned int                                 : 3;
                unsigned int                    PMG_FSMSTATE : 5;
                unsigned int                   SEQ0_BUSY_HYS : 1;
                unsigned int                   SEQ1_BUSY_HYS : 1;
                unsigned int              SEQ0_ALLOWSTOP__CI : 1;
                unsigned int              SEQ1_ALLOWSTOP__CI : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_STATUS_M__VI {
	struct {
		unsigned int                  PWRUP_COMPL_D0 : 1;
		unsigned int                  PWRUP_COMPL_D1 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                      CMD_RDY_D0 : 1;
		unsigned int                      CMD_RDY_D1 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int         SEQ0_ARB_CMD_FIFO_EMPTY : 1;
		unsigned int         SEQ1_ARB_CMD_FIFO_EMPTY : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int          SEQ0_RS_DATA_FIFO_FULL : 1;
		unsigned int          SEQ1_RS_DATA_FIFO_FULL : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                       SEQ0_BUSY : 1;
		unsigned int                       SEQ1_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 11;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_STATUS_S {
	struct {
                unsigned int         SEQ0_ARB_DATA_FIFO_FULL : 1;
                unsigned int         SEQ1_ARB_DATA_FIFO_FULL : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int          SEQ0_ARB_CMD_FIFO_FULL : 1;
                unsigned int          SEQ1_ARB_CMD_FIFO_FULL : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int         SEQ0_RS_DATA_FIFO_EMPTY : 1;
                unsigned int         SEQ1_RS_DATA_FIFO_EMPTY : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_CNTL__SI__CI {
	struct {
		unsigned int                             RUN : 1;
		unsigned int                     SINGLE_STEP : 1;
		unsigned int                         SW_WAKE : 1;
		unsigned int                        RESET_PC : 1;
		unsigned int                       PGM_WRITE : 1;
		unsigned int                        PGM_READ : 1;
		unsigned int                      FAST_WRITE : 1;
		unsigned int                      BKPT_CLEAR : 1;
		unsigned int                                 : 15;
		unsigned int                      PGM_CHKSUM : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_CNTL__VI {
	struct {
		unsigned int                             RUN : 1;
		unsigned int                     SINGLE_STEP : 1;
		unsigned int                         SW_WAKE : 1;
		unsigned int                        RESET_PC : 1;
		unsigned int                       PGM_WRITE : 1;
		unsigned int                        PGM_READ : 1;
		unsigned int                      FAST_WRITE : 1;
		unsigned int                      BKPT_CLEAR : 1;
		unsigned int                                 : 16;
		unsigned int                      PGM_CHKSUM : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_DEC_STAT {
	struct {
		unsigned int                          STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_GP0_STAT {
	struct {
		unsigned int                          STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_GP1_STAT {
	struct {
		unsigned int                          STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_GP2_STAT {
	struct {
		unsigned int                          STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_GP3_STAT {
	struct {
		unsigned int                          STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_IR_STAT {
	struct {
		unsigned int                          STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_PGM {
	struct {
		unsigned int                            CNTL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_PGM_STAT {
	struct {
		unsigned int                          STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_SUP_R_PGM {
	struct {
		unsigned int                             PGM : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TCG_CNTL__SI__CI {
	struct {
                unsigned int                           RESET : 1;
                unsigned int                       ENABLE_D0 : 1;
                unsigned int                       ENABLE_D1 : 1;
                unsigned int                           START : 1;
                unsigned int                           NFIFO : 3;
                unsigned int                    INFINITE_CMD : 1;
                unsigned int                             MOP : 4;
                unsigned int                        DATA_CNT : 4;
                unsigned int                       LOAD_FIFO : 1;
                unsigned int                      SHORT_LDFF : 1;
                unsigned int                     FRAME_TRAIN : 1;
                unsigned int                       BURST_NUM : 3;
                unsigned int                      ISSUE_AREF : 1;
                unsigned int                      TXDBI_CNTL : 1;
                unsigned int                       VPTR_MASK : 1;
                unsigned int                       AREF_LAST : 1;
                unsigned int                       AREF_BOTH : 1;
                unsigned int                                 : 1;
                unsigned int               LD_RTDATA_OVR__CI : 1;
                unsigned int                LD_RTDATA_CH__CI : 1;
                unsigned int                                 : 1;
                unsigned int                            DONE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TIMER_RD {
	struct {
		unsigned int                         COUNTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TIMER_WR {
	struct {
		unsigned int                         COUNTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_CAPTURE__SI__CI {
	struct {
                unsigned int                   D0_ARF_WAKEUP : 1;
                unsigned int                   D1_ARF_WAKEUP : 1;
                unsigned int                  D0_REDC_WAKEUP : 1;
                unsigned int                  D1_REDC_WAKEUP : 1;
                unsigned int                  D0_WEDC_WAKEUP : 1;
                unsigned int                  D1_WEDC_WAKEUP : 1;
                unsigned int         MCLK_FREQ_CHANGE_WAKEUP : 1;
                unsigned int          SCLK_SRBM_READY_WAKEUP : 1;
                unsigned int        D0_CMD_FIFO_READY_WAKEUP : 1;
                unsigned int        D1_CMD_FIFO_READY_WAKEUP : 1;
                unsigned int       D0_DATA_FIFO_READY_WAKEUP : 1;
                unsigned int       D1_DATA_FIFO_READY_WAKEUP : 1;
                unsigned int          SOFTWARE_WAKEUP_WAKEUP : 1;
                unsigned int                 RESERVE0_WAKEUP : 1;
                unsigned int                 TSM_DONE_WAKEUP : 1;
                unsigned int               TIMER_DONE_WAKEUP : 1;
                unsigned int                                 : 1;
                unsigned int                 TCG_DONE_WAKEUP : 1;
                unsigned int               ALLOWSTOP0_WAKEUP : 1;
                unsigned int               ALLOWSTOP1_WAKEUP : 1;
                unsigned int                      DPM_WAKEUP : 1;
                unsigned int              ALLOWSTOPB0_WAKEUP : 1;
                unsigned int              ALLOWSTOPB1_WAKEUP : 1;
                unsigned int                  DPM_LPT_WAKEUP : 1;
                unsigned int                 D0_IDLEH_WAKEUP : 1;
                unsigned int                 D1_IDLEH_WAKEUP : 1;
                unsigned int               PHY_PG_WAKEUP__CI : 1;
                unsigned int                 SREG_WAKEUP__CI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_CAPTURE__VI {
	struct {
		unsigned int                 D0_IDLEH_WAKEUP : 1;
		unsigned int                 D1_IDLEH_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int          SCLK_SRBM_READY_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 SOFTWARE_WAKEUP : 1;
		unsigned int                                 : 2;
		unsigned int               TIMER_DONE_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_EDC_THRESHOLD__SI__CI {
	struct {
		unsigned int             WRITE_EDC_THRESHOLD : 16;
		unsigned int              READ_EDC_THRESHOLD : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_EDC_THRESHOLD2__SI__CI {
	struct {
		unsigned int                THRESHOLD_PERIOD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_EDC_THRESHOLD3__SI__CI {
	struct {
		unsigned int         CH0_LINK_RETRAIN_STATUS : 1;
		unsigned int         CH1_LINK_RETRAIN_STATUS : 1;
		unsigned int            CLEAR_RETRAIN_STATUS : 1;
		unsigned int                     RETRAIN_VBI : 1;
		unsigned int                 RETRAIN_MONITOR : 2;
		unsigned int                                 : 2;
		unsigned int    CH0_LINK_RETRAIN_IN_PROGRESS : 1;
		unsigned int    CH1_LINK_RETRAIN_IN_PROGRESS : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_TIMING__SI__CI {
	struct {
		unsigned int                          TWT2RT : 5;
		unsigned int                          TARF2T : 5;
		unsigned int                          TT2ROW : 5;
		unsigned int                          TLD2LD : 5;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_WAKEUP_CLEAR__SI__CI {
	struct {
                unsigned int                   D0_ARF_WAKEUP : 1;
                unsigned int                   D1_ARF_WAKEUP : 1;
                unsigned int                  D0_REDC_WAKEUP : 1;
                unsigned int                  D1_REDC_WAKEUP : 1;
                unsigned int                  D0_WEDC_WAKEUP : 1;
                unsigned int                  D1_WEDC_WAKEUP : 1;
                unsigned int         MCLK_FREQ_CHANGE_WAKEUP : 1;
                unsigned int          SCLK_SRBM_READY_WAKEUP : 1;
                unsigned int        D0_CMD_FIFO_READY_WAKEUP : 1;
                unsigned int        D1_CMD_FIFO_READY_WAKEUP : 1;
                unsigned int       D0_DATA_FIFO_READY_WAKEUP : 1;
                unsigned int       D1_DATA_FIFO_READY_WAKEUP : 1;
                unsigned int          SOFTWARE_WAKEUP_WAKEUP : 1;
                unsigned int                 RESERVE0_WAKEUP : 1;
                unsigned int                 TSM_DONE_WAKEUP : 1;
                unsigned int               TIMER_DONE_WAKEUP : 1;
                unsigned int                        CLEARALL : 1;
                unsigned int                 TCG_DONE_WAKEUP : 1;
                unsigned int               ALLOWSTOP0_WAKEUP : 1;
                unsigned int               ALLOWSTOP1_WAKEUP : 1;
                unsigned int                      DPM_WAKEUP : 1;
                unsigned int              ALLOWSTOPB0_WAKEUP : 1;
                unsigned int              ALLOWSTOPB1_WAKEUP : 1;
                unsigned int                  DPM_LPT_WAKEUP : 1;
                unsigned int                 D0_IDLEH_WAKEUP : 1;
                unsigned int                 D1_IDLEH_WAKEUP : 1;
                unsigned int               PHY_PG_WAKEUP__CI : 1;
                unsigned int                 SREG_WAKEUP__CI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_WAKEUP_CLEAR__VI {
	struct {
		unsigned int                 D0_IDLEH_WAKEUP : 1;
		unsigned int                 D1_IDLEH_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int          SCLK_SRBM_READY_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 SOFTWARE_WAKEUP : 1;
		unsigned int                                 : 2;
		unsigned int               TIMER_DONE_WAKEUP : 1;
		unsigned int                        CLEARALL : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_WAKEUP_CNTL__SI__CI {
	struct {
		unsigned int              BOOT_UP_ADDR_TRAIN : 1;
		unsigned int               BOOT_UP_WCK_TRAIN : 1;
		unsigned int              BOOT_UP_READ_TRAIN : 1;
		unsigned int             BOOT_UP_WRITE_TRAIN : 1;
		unsigned int         SELF_REFRESH_ADDR_TRAIN : 1;
		unsigned int          SELF_REFRESH_WCK_TRAIN : 1;
		unsigned int         SELF_REFRESH_READ_TRAIN : 1;
		unsigned int        SELF_REFRESH_WRITE_TRAIN : 1;
		unsigned int         AUTO_REFRESH_ADDR_TRAIN : 1;
		unsigned int          AUTO_REFRESH_WCK_TRAIN : 1;
		unsigned int         AUTO_REFRESH_READ_TRAIN : 1;
		unsigned int        AUTO_REFRESH_WRITE_TRAIN : 1;
		unsigned int            WRITE_ECC_ADDR_TRAIN : 1;
		unsigned int             WRITE_ECC_WCK_TRAIN : 1;
		unsigned int            WRITE_ECC_READ_TRAIN : 1;
		unsigned int           WRITE_ECC_WRITE_TRAIN : 1;
		unsigned int             READ_ECC_ADDR_TRAIN : 1;
		unsigned int              READ_ECC_WCK_TRAIN : 1;
		unsigned int             READ_ECC_READ_TRAIN : 1;
		unsigned int            READ_ECC_WRITE_TRAIN : 1;
		unsigned int       AUTO_REFRESH_WAKEUP_EARLY : 1;
		unsigned int                     STOP_WCK_D0 : 1;
		unsigned int                     STOP_WCK_D1 : 1;
		unsigned int                                 : 1;
		unsigned int                 BLOCK_ARB_RD_D0 : 1;
		unsigned int                 BLOCK_ARB_WR_D0 : 1;
		unsigned int                 BLOCK_ARB_RD_D1 : 1;
		unsigned int                 BLOCK_ARB_WR_D1 : 1;
		unsigned int                       SW_WAKEUP : 1;
		unsigned int               DISP_ASTOP_WAKEUP : 1;
		unsigned int                   TRAIN_DONE_D0 : 1;
		unsigned int                   TRAIN_DONE_D1 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_WAKEUP_CNTL__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int       AUTO_REFRESH_WAKEUP_EARLY : 1;
		unsigned int                       SW_WAKEUP : 1;
		unsigned int                 BLOCK_ARB_RD_D0 : 1;
		unsigned int                 BLOCK_ARB_RD_D1 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 BLOCK_ARB_WR_D0 : 1;
		unsigned int                 BLOCK_ARB_WR_D1 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                   TRAIN_DONE_D0 : 1;
		unsigned int                   TRAIN_DONE_D1 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_WAKEUP_EDGE__SI__CI {
	struct {
                unsigned int                   D0_ARF_WAKEUP : 1;
                unsigned int                   D1_ARF_WAKEUP : 1;
                unsigned int                  D0_REDC_WAKEUP : 1;
                unsigned int                  D1_REDC_WAKEUP : 1;
                unsigned int                  D0_WEDC_WAKEUP : 1;
                unsigned int                  D1_WEDC_WAKEUP : 1;
                unsigned int         MCLK_FREQ_CHANGE_WAKEUP : 1;
                unsigned int          SCLK_SRBM_READY_WAKEUP : 1;
                unsigned int        D0_CMD_FIFO_READY_WAKEUP : 1;
                unsigned int        D1_CMD_FIFO_READY_WAKEUP : 1;
                unsigned int       D0_DATA_FIFO_READY_WAKEUP : 1;
                unsigned int       D1_DATA_FIFO_READY_WAKEUP : 1;
                unsigned int          SOFTWARE_WAKEUP_WAKEUP : 1;
                unsigned int                 RESERVE0_WAKEUP : 1;
                unsigned int                 TSM_DONE_WAKEUP : 1;
                unsigned int               TIMER_DONE_WAKEUP : 1;
                unsigned int                                 : 1;
                unsigned int                 TCG_DONE_WAKEUP : 1;
                unsigned int               ALLOWSTOP0_WAKEUP : 1;
                unsigned int               ALLOWSTOP1_WAKEUP : 1;
                unsigned int                      DPM_WAKEUP : 1;
                unsigned int              ALLOWSTOPB0_WAKEUP : 1;
                unsigned int              ALLOWSTOPB1_WAKEUP : 1;
                unsigned int                  DPM_LPT_WAKEUP : 1;
                unsigned int                 D0_IDLEH_WAKEUP : 1;
                unsigned int                 D1_IDLEH_WAKEUP : 1;
                unsigned int               PHY_PG_WAKEUP__CI : 1;
                unsigned int                 SREG_WAKEUP__CI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_WAKEUP_EDGE__VI {
	struct {
		unsigned int                 D0_IDLEH_WAKEUP : 1;
		unsigned int                 D1_IDLEH_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int          SCLK_SRBM_READY_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 SOFTWARE_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int               TIMER_DONE_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_WAKEUP_MASK__SI__CI {
	struct {
                unsigned int                   D0_ARF_WAKEUP : 1;
                unsigned int                   D1_ARF_WAKEUP : 1;
                unsigned int                  D0_REDC_WAKEUP : 1;
                unsigned int                  D1_REDC_WAKEUP : 1;
                unsigned int                  D0_WEDC_WAKEUP : 1;
                unsigned int                  D1_WEDC_WAKEUP : 1;
                unsigned int         MCLK_FREQ_CHANGE_WAKEUP : 1;
                unsigned int          SCLK_SRBM_READY_WAKEUP : 1;
                unsigned int        D0_CMD_FIFO_READY_WAKEUP : 1;
                unsigned int        D1_CMD_FIFO_READY_WAKEUP : 1;
                unsigned int       D0_DATA_FIFO_READY_WAKEUP : 1;
                unsigned int       D1_DATA_FIFO_READY_WAKEUP : 1;
                unsigned int          SOFTWARE_WAKEUP_WAKEUP : 1;
                unsigned int                 RESERVE0_WAKEUP : 1;
                unsigned int                 TSM_DONE_WAKEUP : 1;
                unsigned int               TIMER_DONE_WAKEUP : 1;
                unsigned int                                 : 1;
                unsigned int                 TCG_DONE_WAKEUP : 1;
                unsigned int               ALLOWSTOP0_WAKEUP : 1;
                unsigned int               ALLOWSTOP1_WAKEUP : 1;
                unsigned int                      DPM_WAKEUP : 1;
                unsigned int              ALLOWSTOPB0_WAKEUP : 1;
                unsigned int              ALLOWSTOPB1_WAKEUP : 1;
                unsigned int                  DPM_LPT_WAKEUP : 1;
                unsigned int                 D0_IDLEH_WAKEUP : 1;
                unsigned int                 D1_IDLEH_WAKEUP : 1;
                unsigned int               PHY_PG_WAKEUP__CI : 1;
                unsigned int                 SREG_WAKEUP__CI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TRAIN_WAKEUP_MASK__VI {
	struct {
		unsigned int                 D0_IDLEH_WAKEUP : 1;
		unsigned int                 D1_IDLEH_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int          SCLK_SRBM_READY_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 SOFTWARE_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int               TIMER_DONE_WAKEUP : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_BCNT__SI__CI {
	struct {
		unsigned int                        TRUE_ACT : 4;
		unsigned int                       FALSE_ACT : 4;
		unsigned int                      BCNT_TESTS : 8;
		unsigned int                      COMP_VALUE : 8;
		unsigned int                      DONE_TESTS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_CTRL__SI__CI {
	struct {
                unsigned int                           START : 1;
                unsigned int                   CAPTURE_START : 1;
                unsigned int                            DONE : 1;
                unsigned int                             ERR : 1;
                unsigned int                            STEP : 1;
                unsigned int                       DIRECTION : 1;
                unsigned int                          INVERT : 1;
                unsigned int                       MASK_BITS : 1;
                unsigned int                     UPDATE_LOOP : 2;
                unsigned int                         ROT_INV : 1;
                unsigned int                  DUAL_CH_EN__CI : 1;
                unsigned int                       DONE0__CI : 1;
                unsigned int                       DONE1__CI : 1;
                unsigned int                                 : 2;
                unsigned int                         POINTER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_DBI__SI__CI {
	struct {
		unsigned int                             DBI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_DEBUG_DATA__SI__CI {
	struct {
		unsigned int                  TSM_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_DEBUG_INDEX__SI__CI {
	struct {
		unsigned int                 TSM_DEBUG_INDEX : 5;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_EDC__SI__CI {
	struct {
		unsigned int                             EDC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_FLAG__SI__CI {
	struct {
		unsigned int                        TRUE_ACT : 4;
		unsigned int                       FALSE_ACT : 4;
		unsigned int                      FLAG_TESTS : 8;
		unsigned int                       NBBL_MASK : 4;
		unsigned int                                 : 4;
		unsigned int                     ERROR_TESTS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_GCNT__SI__CI {
	struct {
		unsigned int                        TRUE_ACT : 4;
		unsigned int                       FALSE_ACT : 4;
		unsigned int                           TESTS : 8;
		unsigned int                      COMP_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_MISC__SI__CI {
	struct {
                unsigned int                        WCDR_PTR : 16;
                unsigned int                       WCDR_MASK : 4;
                unsigned int                  CH1_OFFSET__CI : 6;
                unsigned int             CH1_WCDR_OFFSET__CI : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_NCNT__SI__CI {
	struct {
		unsigned int                        TRUE_ACT : 4;
		unsigned int                       FALSE_ACT : 4;
		unsigned int                           TESTS : 8;
		unsigned int                       RANGE_LOW : 4;
		unsigned int                      RANGE_HIGH : 4;
		unsigned int                     NIBBLE_SKIP : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_OCNT__SI__CI {
	struct {
		unsigned int                        TRUE_ACT : 4;
		unsigned int                       FALSE_ACT : 4;
		unsigned int                           TESTS : 8;
		unsigned int                       CMP_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_UPDATE__SI__CI {
	struct {
		unsigned int                        TRUE_ACT : 4;
		unsigned int                       FALSE_ACT : 4;
		unsigned int                      UPDT_TESTS : 8;
		unsigned int                      AREF_COUNT : 8;
		unsigned int                     CAPTR_TESTS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TSM_WCDR__SI__CI {
	struct {
		unsigned int                            WCDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_BYTE0_D0__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_BYTE0_D1__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_BYTE1_D0__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_BYTE1_D1__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_BYTE2_D0__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_BYTE2_D1__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_BYTE3_D0__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_BYTE3_D1__SI__CI {
	struct {
		unsigned int                             DQ0 : 4;
		unsigned int                             DQ1 : 4;
		unsigned int                             DQ2 : 4;
		unsigned int                             DQ3 : 4;
		unsigned int                             DQ4 : 4;
		unsigned int                             DQ5 : 4;
		unsigned int                             DQ6 : 4;
		unsigned int                             DQ7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_DBI_D0__SI__CI {
	struct {
		unsigned int                            DBI0 : 4;
		unsigned int                            DBI1 : 4;
		unsigned int                            DBI2 : 4;
		unsigned int                            DBI3 : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_DBI_D1__SI__CI {
	struct {
		unsigned int                            DBI0 : 4;
		unsigned int                            DBI1 : 4;
		unsigned int                            DBI2 : 4;
		unsigned int                            DBI3 : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_EDC_D0__SI__CI {
	struct {
		unsigned int                            EDC0 : 4;
		unsigned int                            EDC1 : 4;
		unsigned int                            EDC2 : 4;
		unsigned int                            EDC3 : 4;
		unsigned int                           WCDR0 : 4;
		unsigned int                           WCDR1 : 4;
		unsigned int                           WCDR2 : 4;
		unsigned int                           WCDR3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_EDC_D1__SI__CI {
	struct {
		unsigned int                            EDC0 : 4;
		unsigned int                            EDC1 : 4;
		unsigned int                            EDC2 : 4;
		unsigned int                            EDC3 : 4;
		unsigned int                           WCDR0 : 4;
		unsigned int                           WCDR1 : 4;
		unsigned int                           WCDR2 : 4;
		unsigned int                           WCDR3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_FCK_D0__SI__CI {
	struct {
		unsigned int                            FCK0 : 4;
		unsigned int                            FCK1 : 4;
		unsigned int                            FCK2 : 4;
		unsigned int                            FCK3 : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_TXFRAMING_FCK_D1__SI__CI {
	struct {
		unsigned int                            FCK0 : 4;
		unsigned int                            FCK1 : 4;
		unsigned int                            FCK2 : 4;
		unsigned int                            FCK3 : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_VENDOR_ID_I0__SI__CI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_VENDOR_ID_I1__SI__CI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WCDR_CTRL__SI__CI {
	struct {
		unsigned int                        WCDR_PRE : 8;
		unsigned int                        WCDR_TIM : 4;
		unsigned int                           WR_EN : 1;
		unsigned int                           RD_EN : 1;
		unsigned int                         AREF_EN : 1;
		unsigned int                        TRAIN_EN : 1;
		unsigned int                          TWCDRL : 4;
		unsigned int                         PRBS_EN : 1;
		unsigned int                        PRBS_RST : 1;
		unsigned int                                 : 2;
		unsigned int                        PREAMBLE : 4;
		unsigned int                        PRE_MASK : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WR_CTL_2__SI__CI {
	struct {
		unsigned int                    DAT_DLY_H_D0 : 1;
		unsigned int                    DQS_DLY_H_D0 : 1;
		unsigned int                    OEN_DLY_H_D0 : 1;
		unsigned int                    DAT_DLY_H_D1 : 1;
		unsigned int                    DQS_DLY_H_D1 : 1;
		unsigned int                    OEN_DLY_H_D1 : 1;
		unsigned int                         WCDR_EN : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WR_CTL_2_LP__SI__CI {
	struct {
		unsigned int                    DAT_DLY_H_D0 : 1;
		unsigned int                    DQS_DLY_H_D0 : 1;
		unsigned int                    OEN_DLY_H_D0 : 1;
		unsigned int                    DAT_DLY_H_D1 : 1;
		unsigned int                    DQS_DLY_H_D1 : 1;
		unsigned int                    OEN_DLY_H_D1 : 1;
		unsigned int                         WCDR_EN : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WR_CTL_D0__SI__CI {
	struct {
		unsigned int                         DAT_DLY : 4;
		unsigned int                         DQS_DLY : 4;
		unsigned int                         DQS_XTR : 1;
		unsigned int                      DAT_2Y_DLY : 1;
		unsigned int                      ADR_2Y_DLY : 1;
		unsigned int                      CMD_2Y_DLY : 1;
		unsigned int                         OEN_DLY : 4;
		unsigned int                         OEN_EXT : 4;
		unsigned int                         OEN_SEL : 2;
		unsigned int                                 : 2;
		unsigned int                         ODT_DLY : 4;
		unsigned int                         ODT_EXT : 1;
		unsigned int                         ADR_DLY : 1;
		unsigned int                         CMD_DLY : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WR_CTL_D0__VI {
	struct {
		unsigned int                         DAT_DLY : 5;
		unsigned int                         DQS_DLY : 5;
		unsigned int                         DQS_XTR : 1;
		unsigned int                         OEN_DLY : 5;
		unsigned int                         OEN_EXT : 4;
		unsigned int                         OEN_SEL : 2;
		unsigned int                         CMD_DLY : 1;
		unsigned int                         ADR_DLY : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WR_CTL_D0_LP__SI__CI {
	struct {
		unsigned int                         DAT_DLY : 4;
		unsigned int                         DQS_DLY : 4;
		unsigned int                         DQS_XTR : 1;
		unsigned int                      DAT_2Y_DLY : 1;
		unsigned int                      ADR_2Y_DLY : 1;
		unsigned int                      CMD_2Y_DLY : 1;
		unsigned int                         OEN_DLY : 4;
		unsigned int                         OEN_EXT : 4;
		unsigned int                         OEN_SEL : 2;
		unsigned int                                 : 2;
		unsigned int                         ODT_DLY : 4;
		unsigned int                         ODT_EXT : 1;
		unsigned int                         ADR_DLY : 1;
		unsigned int                         CMD_DLY : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WR_CTL_D0_LP__VI {
	struct {
		unsigned int                         DAT_DLY : 5;
		unsigned int                         DQS_DLY : 5;
		unsigned int                         DQS_XTR : 1;
		unsigned int                         OEN_DLY : 5;
		unsigned int                         OEN_EXT : 4;
		unsigned int                         OEN_SEL : 2;
		unsigned int                         CMD_DLY : 1;
		unsigned int                         ADR_DLY : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WR_CTL_D1__SI__CI {
	struct {
		unsigned int                         DAT_DLY : 4;
		unsigned int                         DQS_DLY : 4;
		unsigned int                         DQS_XTR : 1;
		unsigned int                      DAT_2Y_DLY : 1;
		unsigned int                      ADR_2Y_DLY : 1;
		unsigned int                      CMD_2Y_DLY : 1;
		unsigned int                         OEN_DLY : 4;
		unsigned int                         OEN_EXT : 4;
		unsigned int                         OEN_SEL : 2;
		unsigned int                                 : 2;
		unsigned int                         ODT_DLY : 4;
		unsigned int                         ODT_EXT : 1;
		unsigned int                         ADR_DLY : 1;
		unsigned int                         CMD_DLY : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WR_CTL_D1__VI {
	struct {
		unsigned int                         DAT_DLY : 5;
		unsigned int                         DQS_DLY : 5;
		unsigned int                         DQS_XTR : 1;
		unsigned int                         OEN_DLY : 5;
		unsigned int                         OEN_EXT : 4;
		unsigned int                         OEN_SEL : 2;
		unsigned int                         CMD_DLY : 1;
		unsigned int                         ADR_DLY : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WR_CTL_D1_LP__SI__CI {
	struct {
		unsigned int                         DAT_DLY : 4;
		unsigned int                         DQS_DLY : 4;
		unsigned int                         DQS_XTR : 1;
		unsigned int                      DAT_2Y_DLY : 1;
		unsigned int                      ADR_2Y_DLY : 1;
		unsigned int                      CMD_2Y_DLY : 1;
		unsigned int                         OEN_DLY : 4;
		unsigned int                         OEN_EXT : 4;
		unsigned int                         OEN_SEL : 2;
		unsigned int                                 : 2;
		unsigned int                         ODT_DLY : 4;
		unsigned int                         ODT_EXT : 1;
		unsigned int                         ADR_DLY : 1;
		unsigned int                         CMD_DLY : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_WR_CTL_D1_LP__VI {
	struct {
		unsigned int                         DAT_DLY : 5;
		unsigned int                         DQS_DLY : 5;
		unsigned int                         DQS_XTR : 1;
		unsigned int                         OEN_DLY : 5;
		unsigned int                         OEN_EXT : 4;
		unsigned int                         OEN_SEL : 2;
		unsigned int                         CMD_DLY : 1;
		unsigned int                         ADR_DLY : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SHARED_BLACKOUT_CNTL__SI__CI {
	struct {
                unsigned int                   BLACKOUT_MODE : 3;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SHARED_BLACKOUT_CNTL__VI {
	struct {
                unsigned int                   BLACKOUT_MODE : 3;
                unsigned int               BLACKOUT_SEQ_FREE : 1;
                unsigned int                BLACKOUT_MCD_NUM : 8;
                unsigned int                   FREE_TIE_HIGH : 1;
                unsigned int          SRBM_DUMMY_READ_RETURN : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SHARED_CHMAP {
	struct {
                unsigned int                           CHAN0 : 4;
                unsigned int                           CHAN1 : 4;
                unsigned int                           CHAN2 : 4;
                unsigned int                        NOOFCHAN : 4;
                unsigned int                       CHAN3__VI : 4;
                unsigned int                       CHAN4__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SHARED_CHREMAP__SI__CI {
	struct {
		unsigned int                           CHAN0 : 3;
		unsigned int                           CHAN1 : 3;
		unsigned int                           CHAN2 : 3;
		unsigned int                           CHAN3 : 3;
		unsigned int                           CHAN4 : 3;
		unsigned int                           CHAN5 : 3;
		unsigned int                           CHAN6 : 3;
		unsigned int                           CHAN7 : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SHARED_CHREMAP__VI {
	struct {
		unsigned int                           CHAN0 : 4;
		unsigned int                           CHAN1 : 4;
		unsigned int                           CHAN2 : 4;
		unsigned int                           CHAN3 : 4;
		unsigned int                           CHAN4 : 4;
		unsigned int                           CHAN5 : 4;
		unsigned int                           CHAN6 : 4;
		unsigned int                           CHAN7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TRAIN_EDCCDR_R_D0__SI__CI {
	struct {
		unsigned int                            EDC0 : 8;
		unsigned int                            EDC1 : 8;
		unsigned int                            EDC2 : 8;
		unsigned int                            EDC3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TRAIN_EDCCDR_R_D1__SI__CI {
	struct {
		unsigned int                            EDC0 : 8;
		unsigned int                            EDC1 : 8;
		unsigned int                            EDC2 : 8;
		unsigned int                            EDC3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TRAIN_EDC_STATUS_D0__SI__CI {
	struct {
		unsigned int                        WEDC_CNT : 16;
		unsigned int                        REDC_CNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TRAIN_EDC_STATUS_D1__SI__CI {
	struct {
		unsigned int                        WEDC_CNT : 16;
		unsigned int                        REDC_CNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TRAIN_PRBSERR_0_D0__SI__CI {
	struct {
		unsigned int                       DQ_STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TRAIN_PRBSERR_0_D1__SI__CI {
	struct {
		unsigned int                       DQ_STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TRAIN_PRBSERR_1_D0__SI__CI {
	struct {
		unsigned int                      DBI_STATUS : 4;
		unsigned int                      EDC_STATUS : 4;
		unsigned int                      WCK_STATUS : 4;
		unsigned int                     WCDR_STATUS : 4;
		unsigned int                                 : 12;
		unsigned int                     PMA_PRBSCLR : 1;
		unsigned int                    PMD0_PRBSCLR : 1;
		unsigned int                    PMD1_PRBSCLR : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TRAIN_PRBSERR_1_D1__SI__CI {
	struct {
		unsigned int                      DBI_STATUS : 4;
		unsigned int                      EDC_STATUS : 4;
		unsigned int                      WCK_STATUS : 4;
		unsigned int                     WCDR_STATUS : 4;
		unsigned int                                 : 12;
		unsigned int                     PMA_PRBSCLR : 1;
		unsigned int                    PMD0_PRBSCLR : 1;
		unsigned int                    PMD1_PRBSCLR : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TRAIN_PRBSERR_2_D0__SI__CI {
	struct {
		unsigned int                       CK_STATUS : 1;
		unsigned int                      CKB_STATUS : 1;
		unsigned int                                 : 2;
		unsigned int                       CS_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int                      CKE_STATUS : 1;
		unsigned int                      RAS_STATUS : 1;
		unsigned int                      CAS_STATUS : 1;
		unsigned int                       WE_STATUS : 1;
		unsigned int                                 : 4;
		unsigned int                     ADDR_STATUS : 10;
		unsigned int                                 : 2;
		unsigned int                      ABI_STATUS : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TRAIN_PRBSERR_2_D1__SI__CI {
	struct {
		unsigned int                       CK_STATUS : 1;
		unsigned int                      CKB_STATUS : 1;
		unsigned int                                 : 2;
		unsigned int                       CS_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int                      CKE_STATUS : 1;
		unsigned int                      RAS_STATUS : 1;
		unsigned int                      CAS_STATUS : 1;
		unsigned int                       WE_STATUS : 1;
		unsigned int                                 : 4;
		unsigned int                     ADDR_STATUS : 10;
		unsigned int                                 : 2;
		unsigned int                      ABI_STATUS : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT0__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT1__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT10__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT2__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT3__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT4__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT5__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT6__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT7__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT8__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BCNT9__SI__CI {
	struct {
		unsigned int                           BYTE0 : 8;
		unsigned int                           BYTE1 : 8;
		unsigned int                           BYTE2 : 8;
		unsigned int                           BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_BKPT__SI__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_FLAG__SI__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_GCNT__SI__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_MISC__SI__CI {
	struct {
		unsigned int                            FLAG : 8;
		unsigned int                         NCNT_RD : 4;
		unsigned int                         NCNT_WR : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_ST01__SI__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_ST23__SI__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_TSM_DEBUG_ST45__SI__CI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_AGP_BASE {
	struct {
		unsigned int                        AGP_BASE : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_AGP_BOT {
	struct {
		unsigned int                         AGP_BOT : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_AGP_TOP {
	struct {
		unsigned int                         AGP_TOP : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_DC_WRITE_CNTL {
	struct {
		unsigned int      DC_WRITE_HIT_REGION_0_MODE : 2;
		unsigned int      DC_WRITE_HIT_REGION_1_MODE : 2;
		unsigned int      DC_WRITE_HIT_REGION_2_MODE : 2;
		unsigned int      DC_WRITE_HIT_REGION_3_MODE : 2;
		unsigned int           DC_MEMORY_WRITE_LOCAL : 1;
		unsigned int          DC_MEMORY_WRITE_SYSTEM : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR {
	struct {
		unsigned int                PHYSICAL_ADDRESS : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR {
	struct {
		unsigned int                PHYSICAL_ADDRESS : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR {
	struct {
		unsigned int                PHYSICAL_ADDRESS : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR {
	struct {
		unsigned int                PHYSICAL_ADDRESS : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR {
	struct {
		unsigned int                PHYSICAL_ADDRESS : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR {
	struct {
		unsigned int                PHYSICAL_ADDRESS : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR {
	struct {
		unsigned int                PHYSICAL_ADDRESS : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR {
	struct {
		unsigned int                PHYSICAL_ADDRESS : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_LOCATION {
	struct {
		unsigned int                         FB_BASE : 16;
		unsigned int                          FB_TOP : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_OFFSET {
	struct {
		unsigned int                       FB_OFFSET : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_L2_PERFCOUNTER0_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_L2_PERFCOUNTER1_CFG__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                    PERF_SEL_END : 8;
                unsigned int                                 : 8;
                unsigned int                       PERF_MODE : 4;
                unsigned int                          ENABLE : 1;
                unsigned int                           CLEAR : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_L2_PERFCOUNTER_HI__CI__VI {
	struct {
                unsigned int                      COUNTER_HI : 16;
                unsigned int                   COMPARE_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_L2_PERFCOUNTER_LO__CI__VI {
	struct {
                unsigned int                      COUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CI__VI {
	struct {
                unsigned int             PERF_COUNTER_SELECT : 4;
                unsigned int                                 : 4;
                unsigned int                   START_TRIGGER : 8;
                unsigned int                    STOP_TRIGGER : 8;
                unsigned int                      ENABLE_ANY : 1;
                unsigned int                       CLEAR_ALL : 1;
                unsigned int            STOP_ALL_ON_SATURATE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLB0_DEBUG {
	struct {
                unsigned int               INVALIDATE_L1_TLB : 1;
                unsigned int                                 : 7;
                unsigned int                SEND_FREE_AT_RTN : 1;
                unsigned int           EFFECTIVE_L1_TLB_SIZE : 3;
                unsigned int         EFFECTIVE_L1_QUEUE_SIZE : 3;
                unsigned int                    L1_TLB_DEBUG : 4;
                unsigned int       L1_TLB_FORCE_MISS__CI__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLB0_STATUS {
	struct {
		unsigned int                            BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLB1_STATUS {
	struct {
		unsigned int                            BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLB2_DEBUG {
	struct {
                unsigned int               INVALIDATE_L1_TLB : 1;
                unsigned int                                 : 7;
                unsigned int                SEND_FREE_AT_RTN : 1;
                unsigned int           EFFECTIVE_L1_TLB_SIZE : 3;
                unsigned int         EFFECTIVE_L1_QUEUE_SIZE : 3;
                unsigned int                    L1_TLB_DEBUG : 4;
                unsigned int       L1_TLB_FORCE_MISS__CI__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLB2_STATUS {
	struct {
		unsigned int                            BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLB3_DEBUG {
	struct {
                unsigned int               INVALIDATE_L1_TLB : 1;
                unsigned int                                 : 7;
                unsigned int                SEND_FREE_AT_RTN : 1;
                unsigned int           EFFECTIVE_L1_TLB_SIZE : 3;
                unsigned int         EFFECTIVE_L1_QUEUE_SIZE : 3;
                unsigned int                    L1_TLB_DEBUG : 4;
                unsigned int       L1_TLB_FORCE_MISS__CI__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLB3_STATUS {
	struct {
		unsigned int                            BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L2ARBITER_L2_CREDITS {
	struct {
		unsigned int                   L2_IF_CREDITS : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MD_L1_TLB0_DEBUG {
	struct {
                unsigned int               INVALIDATE_L1_TLB : 1;
                unsigned int                                 : 7;
                unsigned int                SEND_FREE_AT_RTN : 1;
                unsigned int           EFFECTIVE_L1_TLB_SIZE : 3;
                unsigned int         EFFECTIVE_L1_QUEUE_SIZE : 3;
                unsigned int                    L1_TLB_DEBUG : 4;
                unsigned int       L1_TLB_FORCE_MISS__CI__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MD_L1_TLB0_STATUS {
	struct {
		unsigned int                            BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MD_L1_TLB1_DEBUG {
	struct {
                unsigned int               INVALIDATE_L1_TLB : 1;
                unsigned int                                 : 7;
                unsigned int                SEND_FREE_AT_RTN : 1;
                unsigned int           EFFECTIVE_L1_TLB_SIZE : 3;
                unsigned int         EFFECTIVE_L1_QUEUE_SIZE : 3;
                unsigned int                    L1_TLB_DEBUG : 4;
                unsigned int       L1_TLB_FORCE_MISS__CI__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MD_L1_TLB1_STATUS {
	struct {
		unsigned int                            BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MD_L1_TLB2_DEBUG {
	struct {
                unsigned int               INVALIDATE_L1_TLB : 1;
                unsigned int                                 : 7;
                unsigned int                SEND_FREE_AT_RTN : 1;
                unsigned int           EFFECTIVE_L1_TLB_SIZE : 3;
                unsigned int         EFFECTIVE_L1_QUEUE_SIZE : 3;
                unsigned int                    L1_TLB_DEBUG : 4;
                unsigned int       L1_TLB_FORCE_MISS__CI__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MD_L1_TLB2_STATUS {
	struct {
		unsigned int                            BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MD_L1_TLB3_DEBUG {
	struct {
                unsigned int               INVALIDATE_L1_TLB : 1;
                unsigned int                                 : 7;
                unsigned int                SEND_FREE_AT_RTN : 1;
                unsigned int           EFFECTIVE_L1_TLB_SIZE : 3;
                unsigned int         EFFECTIVE_L1_QUEUE_SIZE : 3;
                unsigned int                    L1_TLB_DEBUG : 4;
                unsigned int       L1_TLB_FORCE_MISS__CI__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MD_L1_TLB3_STATUS {
	struct {
		unsigned int                            BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MD_L2ARBITER_L2_CREDITS {
	struct {
		unsigned int                   L2_IF_CREDITS : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MX_L1_TLB_CNTL {
	struct {
		unsigned int                   ENABLE_L1_TLB : 1;
		unsigned int   ENABLE_L1_FRAGMENT_PROCESSING : 1;
		unsigned int                                 : 1;
		unsigned int              SYSTEM_ACCESS_MODE : 2;
		unsigned int SYSTEM_APERTURE_UNMAPPED_ACCESS : 1;
		unsigned int    ENABLE_ADVANCED_DRIVER_MODEL : 1;
		unsigned int                        ECO_BITS : 4;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_STEERING__CI__VI {
	struct {
                unsigned int                DEFAULT_STEERING : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_SYSTEM_APERTURE_HIGH_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_SYSTEM_APERTURE_LOW_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_CB {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                       MAX_BURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_DB {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                       MAX_BURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_GRP_EXT {
	struct {
		unsigned int                         DBSTEN0 : 4;
		unsigned int                             TC0 : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_GRP_GFX__CI {
	struct {
		unsigned int                              CP : 4;
		unsigned int                              SH : 4;
		unsigned int                            ACPG : 4;
		unsigned int                            ACPO : 4;
		unsigned int                            XDMA : 4;
		unsigned int                           XDMAM : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_GRP_GFX__VI {
	struct {
		unsigned int                              CP : 4;
		unsigned int                              SH : 4;
		unsigned int                            ACPG : 4;
		unsigned int                            ACPO : 4;
		unsigned int                             ISP : 4;
		unsigned int                             VP8 : 4;
		unsigned int                            XDMA : 4;
		unsigned int                           XDMAM : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_GRP_GFX__SI {
	struct {
		unsigned int                              CP : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                            XDMA : 4;
		unsigned int                           XDMAM : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_GRP_LCL {
	struct {
                unsigned int                             CB0 : 4;
                unsigned int                        CBCMASK0 : 4;
                unsigned int                        CBFMASK0 : 4;
                unsigned int                             DB0 : 4;
                unsigned int                        DBHTILE0 : 4;
                unsigned int                             SX0 : 4;
                unsigned int                                 : 4;
                unsigned int                        CBIMMED0 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_GRP_OTH__CI__VI {
	struct {
                unsigned int                        UVD_EXT0 : 4;
                unsigned int                           SDMA0 : 4;
                unsigned int                             HDP : 4;
                unsigned int                             SEM : 4;
                unsigned int                             UMC : 4;
                unsigned int                             UVD : 4;
                unsigned int                             XDP : 4;
                unsigned int                        UVD_EXT1 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_GRP_OTH__SI {
	struct {
		unsigned int                        UVD_EXT0 : 4;
		unsigned int                                 : 4;
		unsigned int                             HDP : 4;
		unsigned int                             SEM : 4;
		unsigned int                             UMC : 4;
		unsigned int                             UVD : 4;
		unsigned int                             XDP : 4;
		unsigned int                        UVD_EXT1 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_GRP_SYS__CI {
	struct {
		unsigned int                              IH : 4;
		unsigned int                            MCIF : 4;
		unsigned int                             RLC : 4;
		unsigned int                             SAM : 4;
		unsigned int                             SMU : 4;
		unsigned int                           SDMA1 : 4;
		unsigned int                             VCE : 4;
		unsigned int                            VCEU : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_GRP_SYS__VI {
	struct {
		unsigned int                              IH : 4;
		unsigned int                            MCIF : 4;
		unsigned int                             RLC : 4;
		unsigned int                          SAMMSP : 4;
		unsigned int                             SMU : 4;
		unsigned int                           SDMA1 : 4;
		unsigned int                             VCE : 4;
		unsigned int                            VCEU : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_GRP_SYS__SI {
	struct {
		unsigned int                              IH : 4;
		unsigned int                            MCIF : 4;
		unsigned int                             RLC : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                             SMU : 4;
		unsigned int                             VCE : 4;
		unsigned int                            VCEU : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_HUB {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                       MAX_BURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_TC0 {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                       MAX_BURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_WR_TC1 {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                       MAX_BURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_ADDR_DEC {
	struct {
                unsigned int                     NO_DIV_BY_3 : 1;
                unsigned int                            GECC : 1;
                unsigned int                        RB_SPLIT : 1;
                unsigned int                  RB_SPLIT_COLHI : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_ARB {
	struct {
                unsigned int                   HUBRD_HIGHEST : 1;
                unsigned int       DISABLE_HUB_STALL_HIGHEST : 1;
                unsigned int          BREAK_BURST_CID_CHANGE : 1;
                unsigned int               ACP_RDRET_URG__VI : 1;
                unsigned int               HDP_RDRET_URG__VI : 1;
                unsigned int          BREAK_BURST_BY_URG__VI : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_ARB_MAX_BURST {
	struct {
		unsigned int                        RD_PORT0 : 4;
		unsigned int                        RD_PORT1 : 4;
		unsigned int                        RD_PORT2 : 4;
		unsigned int                        RD_PORT3 : 4;
		unsigned int                        WR_PORT0 : 4;
		unsigned int                        WR_PORT1 : 4;
		unsigned int                        WR_PORT2 : 4;
		unsigned int                        WR_PORT3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_CHTRIREMAP {
	struct {
		unsigned int                             CH0 : 2;
		unsigned int                             CH1 : 2;
		unsigned int                             CH2 : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_PERF_MON_CNTL0__SI__CI {
	struct {
		unsigned int                    START_THRESH : 12;
		unsigned int                     STOP_THRESH : 12;
		unsigned int                      START_MODE : 2;
		unsigned int                       STOP_MODE : 2;
		unsigned int                      ALLOW_WRAP : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_PERF_MON_CNTL1__SI__CI {
	struct {
		unsigned int                  THRESH_CNTR_ID : 8;
		unsigned int                   START_TRIG_ID : 8;
		unsigned int                    STOP_TRIG_ID : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_PERF_MON_CNTL2__SI__CI {
	struct {
		unsigned int                         MON0_ID : 8;
		unsigned int                         MON1_ID : 8;
		unsigned int                         MON2_ID : 8;
		unsigned int                         MON3_ID : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_PERF_MON_MAX_THSH__SI__CI {
	struct {
		unsigned int                            MON0 : 8;
		unsigned int                            MON1 : 8;
		unsigned int                            MON2 : 8;
		unsigned int                            MON3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_PERF_MON_RSLT0__SI__CI {
	struct {
		unsigned int                           COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_PERF_MON_RSLT1__SI__CI {
	struct {
		unsigned int                           COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_PERF_MON_RSLT2__SI__CI {
	struct {
		unsigned int                           COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_PERF_MON_RSLT3__SI__CI {
	struct {
		unsigned int                           COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_RDREQ_CREDIT {
	struct {
		unsigned int                            OUT0 : 8;
		unsigned int                            OUT1 : 8;
		unsigned int                            OUT2 : 8;
		unsigned int                            OUT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_RDREQ_PRI_CREDIT {
	struct {
		unsigned int                            OUT0 : 8;
		unsigned int                            OUT1 : 8;
		unsigned int                            OUT2 : 8;
		unsigned int                            OUT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_RDRET_CREDIT1 {
	struct {
		unsigned int                            OUT0 : 8;
		unsigned int                            OUT1 : 8;
		unsigned int                            OUT2 : 8;
		unsigned int                            OUT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_RDRET_CREDIT2 {
	struct {
		unsigned int                            OUT4 : 8;
		unsigned int                            OUT5 : 8;
		unsigned int               HUB_LP_RDRET_SKID : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_RDRET_PRI_CREDIT1 {
	struct {
		unsigned int                            OUT0 : 8;
		unsigned int                            OUT1 : 8;
		unsigned int                            OUT2 : 8;
		unsigned int                            OUT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_RDRET_PRI_CREDIT2 {
	struct {
		unsigned int                            OUT4 : 8;
		unsigned int                            OUT5 : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_REMOTE {
	struct {
		unsigned int                    WRREQ_EN_GOQ : 1;
		unsigned int                    RDREQ_EN_GOQ : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_SPARE0 {
	struct {
		unsigned int                             BIT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_SPARE1 {
	struct {
		unsigned int                             BIT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_TWOCHAN {
	struct {
                unsigned int                 DISABLE_ONEPORT : 1;
                unsigned int                             CH0 : 2;
                unsigned int                             CH1 : 2;
                unsigned int                                 : 2;
                unsigned int                                 : 2;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_WRREQ_CREDIT {
	struct {
		unsigned int                            OUT0 : 8;
		unsigned int                            OUT1 : 8;
		unsigned int                            OUT2 : 8;
		unsigned int                            OUT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_WRRET_CREDIT1 {
	struct {
		unsigned int                            OUT0 : 8;
		unsigned int                            OUT1 : 8;
		unsigned int                            OUT2 : 8;
		unsigned int                            OUT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_WRRET_CREDIT2 {
	struct {
		unsigned int                            OUT4 : 8;
		unsigned int                            OUT5 : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG0 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG1 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG10 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG11 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG12 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG13 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG14 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG15 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG16 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG17 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG18 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG19 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG2 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG20 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG21 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG22 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG23 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG24 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG25 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG26 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG27 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG28 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG29 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG3 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG30 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG31 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG32 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG33 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG34 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG35 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG36 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG4 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG5 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG6 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG7 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG8 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_CFG9 {
	struct {
		unsigned int                         WCB_NUM : 4;
		unsigned int                         LB_TYPE : 3;
		unsigned int                         P2P_BAR : 3;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                      SIDE_FLUSH : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_EXTRA {
	struct {
		unsigned int                            CMP0 : 8;
		unsigned int                            MSK0 : 8;
		unsigned int                            VLD0 : 1;
		unsigned int                            CMP1 : 8;
		unsigned int                            VLD1 : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLG_EXTRA_RD {
	struct {
		unsigned int                            CMP0 : 8;
		unsigned int                            MSK0 : 8;
		unsigned int                            VLD0 : 1;
		unsigned int                            CMP1 : 8;
		unsigned int                            VLD1 : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_CLK_GAT {
	struct {
		unsigned int                           ONDLY : 6;
		unsigned int                          OFFDLY : 6;
		unsigned int                          RDYDLY : 6;
		unsigned int                          ENABLE : 1;
		unsigned int                   MEM_LS_ENABLE : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_INTF_CFG {
	struct {
		unsigned int                   RPB_WRREQ_CRD : 8;
		unsigned int                    MC_WRRET_ASK : 8;
		unsigned int                     XSP_REQ_CRD : 7;
		unsigned int               BIF_REG_SNOOP_SEL : 1;
		unsigned int               BIF_REG_SNOOP_VAL : 1;
		unsigned int               BIF_MEM_SNOOP_SEL : 1;
		unsigned int               BIF_MEM_SNOOP_VAL : 1;
		unsigned int                   XSP_SNOOP_SEL : 2;
		unsigned int                   XSP_SNOOP_VAL : 1;
		unsigned int                XSP_ORDERING_SEL : 1;
		unsigned int                XSP_ORDERING_VAL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_INTF_CFG2 {
	struct {
		unsigned int                   RPB_RDREQ_CRD : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_INTF_STS {
	struct {
		unsigned int                   RPB_WRREQ_CRD : 8;
		unsigned int                     XSP_REQ_CRD : 7;
		unsigned int               HOP_DATA_BUF_FULL : 1;
		unsigned int               HOP_ATTR_BUF_FULL : 1;
		unsigned int                    CNS_BUF_FULL : 1;
		unsigned int                    CNS_BUF_BUSY : 1;
		unsigned int                   RPB_RDREQ_CRD : 8;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_LB_ADDR {
	struct {
		unsigned int                            CMP0 : 10;
		unsigned int                           MASK0 : 10;
		unsigned int                            CMP1 : 6;
		unsigned int                           MASK1 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_MAP_INVERT_FLUSH_NUM_LSB {
	struct {
		unsigned int                 ALTER_FLUSH_NUM : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_MISC_CFG {
	struct {
		unsigned int                      FIELDNAME0 : 8;
		unsigned int                      FIELDNAME1 : 8;
		unsigned int                      FIELDNAME2 : 8;
		unsigned int                      FIELDNAME3 : 7;
		unsigned int                     TRIGGERNAME : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR0 {
	struct {
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                     REG_SYS_BAR : 4;
		unsigned int                     MEM_SYS_BAR : 4;
		unsigned int                           VALID : 1;
		unsigned int                        SEND_DIS : 1;
		unsigned int                    COMPRESS_DIS : 1;
		unsigned int                        RESERVED : 1;
		unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR1 {
	struct {
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                     REG_SYS_BAR : 4;
		unsigned int                     MEM_SYS_BAR : 4;
		unsigned int                           VALID : 1;
		unsigned int                        SEND_DIS : 1;
		unsigned int                    COMPRESS_DIS : 1;
		unsigned int                        RESERVED : 1;
		unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR2 {
	struct {
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                     REG_SYS_BAR : 4;
		unsigned int                     MEM_SYS_BAR : 4;
		unsigned int                           VALID : 1;
		unsigned int                        SEND_DIS : 1;
		unsigned int                    COMPRESS_DIS : 1;
		unsigned int                        RESERVED : 1;
		unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR3 {
	struct {
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                     REG_SYS_BAR : 4;
		unsigned int                     MEM_SYS_BAR : 4;
		unsigned int                           VALID : 1;
		unsigned int                        SEND_DIS : 1;
		unsigned int                    COMPRESS_DIS : 1;
		unsigned int                        RESERVED : 1;
		unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR4 {
	struct {
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                     REG_SYS_BAR : 4;
		unsigned int                     MEM_SYS_BAR : 4;
		unsigned int                           VALID : 1;
		unsigned int                        SEND_DIS : 1;
		unsigned int                    COMPRESS_DIS : 1;
		unsigned int                        RESERVED : 1;
		unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR5 {
	struct {
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                     REG_SYS_BAR : 4;
		unsigned int                     MEM_SYS_BAR : 4;
		unsigned int                           VALID : 1;
		unsigned int                        SEND_DIS : 1;
		unsigned int                    COMPRESS_DIS : 1;
		unsigned int                        RESERVED : 1;
		unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR6 {
	struct {
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                     REG_SYS_BAR : 4;
		unsigned int                     MEM_SYS_BAR : 4;
		unsigned int                           VALID : 1;
		unsigned int                        SEND_DIS : 1;
		unsigned int                    COMPRESS_DIS : 1;
		unsigned int                        RESERVED : 1;
		unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR7 {
	struct {
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                     REG_SYS_BAR : 4;
		unsigned int                     MEM_SYS_BAR : 4;
		unsigned int                           VALID : 1;
		unsigned int                        SEND_DIS : 1;
		unsigned int                    COMPRESS_DIS : 1;
		unsigned int                        RESERVED : 1;
		unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR_CFG {
	struct {
		unsigned int                       ADDR_SIZE : 4;
		unsigned int                        SEND_BAR : 2;
		unsigned int                           SNOOP : 1;
		unsigned int                        SEND_DIS : 1;
		unsigned int                    COMPRESS_DIS : 1;
		unsigned int                      UPDATE_DIS : 1;
		unsigned int              REGBAR_FROM_SYSBAR : 1;
		unsigned int                           RD_EN : 1;
		unsigned int                  ATC_TRANSLATED : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR_DEBUG {
	struct {
		unsigned int                             SEL : 8;
		unsigned int                      HOST_FLUSH : 4;
		unsigned int                     MEM_SYS_BAR : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR_DELTA_ABOVE {
	struct {
		unsigned int                              EN : 8;
		unsigned int                           DELTA : 20;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR_DELTA_BELOW {
	struct {
		unsigned int                              EN : 8;
		unsigned int                           DELTA : 20;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_P2P_BAR_SETUP {
	struct {
		unsigned int                             SEL : 8;
		unsigned int                     REG_SYS_BAR : 4;
		unsigned int                           VALID : 1;
		unsigned int                        SEND_DIS : 1;
		unsigned int                    COMPRESS_DIS : 1;
		unsigned int                        RESERVED : 1;
		unsigned int                         ADDRESS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PEER_SYS_BAR0 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PEER_SYS_BAR1 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PEER_SYS_BAR2 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PEER_SYS_BAR3 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PEER_SYS_BAR4 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PEER_SYS_BAR5 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PEER_SYS_BAR6 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PEER_SYS_BAR7 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PEER_SYS_BAR8 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PEER_SYS_BAR9 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PERF_KNOBS {
	struct {
		unsigned int                  CNS_FIFO_DEPTH : 6;
		unsigned int              WCB_HST_FIFO_DEPTH : 6;
		unsigned int              WCB_SID_FIFO_DEPTH : 6;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_PIPE_STS {
	struct {
		unsigned int                    WCB_ANY_PBUF : 1;
		unsigned int            WCB_HST_DATA_BUF_CNT : 7;
		unsigned int            WCB_SID_DATA_BUF_CNT : 7;
		unsigned int         WCB_HST_RD_PTR_BUF_FULL : 1;
		unsigned int         WCB_SID_RD_PTR_BUF_FULL : 1;
		unsigned int           WCB_HST_REQ_FIFO_FULL : 1;
		unsigned int           WCB_SID_REQ_FIFO_FULL : 1;
		unsigned int           WCB_HST_REQ_OBUF_FULL : 1;
		unsigned int           WCB_SID_REQ_OBUF_FULL : 1;
		unsigned int          WCB_HST_DATA_OBUF_FULL : 1;
		unsigned int          WCB_SID_DATA_OBUF_FULL : 1;
		unsigned int                    RET_BUF_FULL : 1;
		unsigned int               XPB_CLK_BUSY_BITS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_DEST_MAP0 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_DEST_MAP1 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_DEST_MAP2 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_DEST_MAP3 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_DEST_MAP4 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_DEST_MAP5 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_DEST_MAP6 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_DEST_MAP7 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_DEST_MAP8 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_DEST_MAP9 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_SRC_APRTR0 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_SRC_APRTR1 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_SRC_APRTR2 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_SRC_APRTR3 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_SRC_APRTR4 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_SRC_APRTR5 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_SRC_APRTR6 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_SRC_APRTR7 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_SRC_APRTR8 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_RTR_SRC_APRTR9 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_STICKY {
	struct {
		unsigned int                            BITS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_STICKY_W1C {
	struct {
		unsigned int                            BITS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_SUB_CTRL {
	struct {
		unsigned int                WRREQ_BYPASS_XPB : 1;
		unsigned int               STALL_CNS_RTR_REQ : 1;
		unsigned int             STALL_RTR_RPB_WRREQ : 1;
		unsigned int               STALL_RTR_MAP_REQ : 1;
		unsigned int               STALL_MAP_WCB_REQ : 1;
		unsigned int               STALL_WCB_SID_REQ : 1;
		unsigned int           STALL_MC_XSP_REQ_SEND : 1;
		unsigned int               STALL_WCB_HST_REQ : 1;
		unsigned int               STALL_HST_HOP_REQ : 1;
		unsigned int          STALL_XPB_RPB_REQ_ATTR : 1;
		unsigned int                       RESET_CNS : 1;
		unsigned int                       RESET_RTR : 1;
		unsigned int                       RESET_RET : 1;
		unsigned int                       RESET_MAP : 1;
		unsigned int                       RESET_WCB : 1;
		unsigned int                       RESET_HST : 1;
		unsigned int                       RESET_HOP : 1;
		unsigned int                       RESET_SID : 1;
		unsigned int                       RESET_SRB : 1;
		unsigned int                       RESET_CGR : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_UNC_THRESH_HST {
	struct {
		unsigned int                     CHANGE_PREF : 6;
		unsigned int                     STRONG_PREF : 6;
		unsigned int                      USE_UNFULL : 6;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_UNC_THRESH_SID {
	struct {
		unsigned int                     CHANGE_PREF : 6;
		unsigned int                     STRONG_PREF : 6;
		unsigned int                      USE_UNFULL : 6;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_WCB_CFG {
	struct {
		unsigned int                         TIMEOUT : 16;
		unsigned int                         HST_MAX : 2;
		unsigned int                         SID_MAX : 2;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_WCB_STS {
	struct {
		unsigned int                        PBUF_VLD : 16;
		unsigned int            WCB_HST_DATA_BUF_CNT : 7;
		unsigned int            WCB_SID_DATA_BUF_CNT : 7;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_PEER_SYS_BAR0 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_PEER_SYS_BAR1 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_PEER_SYS_BAR2 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_PEER_SYS_BAR3 {
	struct {
		unsigned int                           VALID : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                            ADDR : 25;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_RTR_DEST_MAP0 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_RTR_DEST_MAP1 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_RTR_DEST_MAP2 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_RTR_DEST_MAP3 {
	struct {
		unsigned int                             NMR : 1;
		unsigned int                     DEST_OFFSET : 19;
		unsigned int                        DEST_SEL : 4;
		unsigned int                    DEST_SEL_RPB : 1;
		unsigned int                         SIDE_OK : 1;
		unsigned int                      APRTR_SIZE : 5;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_RTR_SRC_APRTR0 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_RTR_SRC_APRTR1 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_RTR_SRC_APRTR2 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XPB_XDMA_RTR_SRC_APRTR3 {
	struct {
		unsigned int                       BASE_ADDR : 25;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MEM_TYPE_CNTL__CI__VI {
	struct {
                unsigned int                BF_MEM_PHY_G5_G3 : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MICROSECOND_TIME_BASE_DIV__SI__VI {
	struct {
                unsigned int       MICROSECOND_TIME_BASE_DIV : 7;
                unsigned int                                 : 1;
                unsigned int                    XTAL_REF_DIV : 7;
                unsigned int                                 : 1;
                unsigned int                    XTAL_REF_SEL : 1;
                unsigned int       XTAL_REF_CLOCK_SOURCE_SEL : 1;
                unsigned int                                 : 2;
                unsigned int MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL : 1;
                unsigned int                                 : 3;
                unsigned int                                 : 1;
                unsigned int                                 : 3;
                unsigned int                                 : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MINOR_VERSION__SI__VI {
	struct {
                unsigned int                   MINOR_VERSION : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MIN_GRANT {
	struct {
		unsigned int                         MIN_GNT : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MISC_CLK_CTRL__CI__VI {
	struct {
                unsigned int              DEEP_SLEEP_CLK_SEL : 8;
                unsigned int                        ZCLK_SEL : 8;
                unsigned int              DFT_SMS_PG_CLK_SEL : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MM_CFGREGS_CNTL {
	struct {
		unsigned int                 MM_CFG_FUNC_SEL : 3;
		unsigned int                 MM_WR_TO_CFG_EN : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MM_DATA {
	struct {
		unsigned int                         MM_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MM_INDEX {
	struct {
		unsigned int                       MM_OFFSET : 31;
		unsigned int                         MM_APER : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MM_INDEX_HI__CI__VI {
	struct {
                unsigned int                    MM_OFFSET_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_AD_FUNC_CNTL__SI__CI {
	struct {
		unsigned int                   YCLK_POST_DIV : 3;
		unsigned int                           SPARE : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_AD_STATUS__SI__CI {
	struct {
		unsigned int                        VCTRLADC : 3;
		unsigned int                                 : 1;
		unsigned int                 TEST_FBDIV_FRAC : 3;
		unsigned int                  TEST_FBDIV_INT : 10;
		unsigned int                      OINT_RESET : 1;
		unsigned int                       FREQ_LOCK : 1;
		unsigned int              FREQ_UNLOCK_STICKY : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_BYPASSCLK_SEL {
	struct {
		unsigned int                                 : 8;
		unsigned int                 MPLL_CLKOUT_SEL : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_CNTL_MODE__SI__CI {
	struct {
		unsigned int                     INSTR_DELAY : 8;
		unsigned int             MPLL_SW_DIR_CONTROL : 1;
		unsigned int                                 : 2;
		unsigned int                   MPLL_MCLK_SEL : 1;
		unsigned int                         SPARE_1 : 1;
		unsigned int                             QDR : 1;
		unsigned int                     MPLL_CTLREQ : 1;
		unsigned int                                 : 1;
		unsigned int                 MPLL_CHG_STATUS : 1;
		unsigned int                  FORCE_TESTMODE : 1;
		unsigned int                                 : 2;
		unsigned int                    FAST_LOCK_EN : 1;
		unsigned int                 FAST_LOCK_CNTRL : 2;
		unsigned int                         SPARE_2 : 1;
		unsigned int                         SS_SSEN : 2;
		unsigned int                    SS_DSMODE_EN : 1;
		unsigned int                 VTOI_BIAS_CNTRL : 1;
		unsigned int                         SPARE_3 : 3;
		unsigned int               GLOBAL_MPLL_RESET : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_CONTROL__SI__CI {
	struct {
		unsigned int                      GDDR_PWRON : 1;
		unsigned int                    REFCLK_PWRON : 1;
		unsigned int                PLL_BUF_PWRON_TX : 1;
		unsigned int                                 : 9;
		unsigned int                     AD_BG_PWRON : 1;
		unsigned int                    AD_PLL_PWRON : 1;
		unsigned int                    AD_PLL_RESET : 1;
		unsigned int                      SPARE_AD_0 : 1;
		unsigned int                 DQ_0_0_BG_PWRON : 1;
		unsigned int                DQ_0_0_PLL_PWRON : 1;
		unsigned int                DQ_0_0_PLL_RESET : 1;
		unsigned int                    SPARE_DQ_0_0 : 1;
		unsigned int                 DQ_0_1_BG_PWRON : 1;
		unsigned int                DQ_0_1_PLL_PWRON : 1;
		unsigned int                DQ_0_1_PLL_RESET : 1;
		unsigned int                    SPARE_DQ_0_1 : 1;
		unsigned int                 DQ_1_0_BG_PWRON : 1;
		unsigned int                DQ_1_0_PLL_PWRON : 1;
		unsigned int                DQ_1_0_PLL_RESET : 1;
		unsigned int                    SPARE_DQ_1_0 : 1;
		unsigned int                 DQ_1_1_BG_PWRON : 1;
		unsigned int                DQ_1_1_PLL_PWRON : 1;
		unsigned int                DQ_1_1_PLL_RESET : 1;
		unsigned int                    SPARE_DQ_1_1 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_DQ_0_0_STATUS__SI__CI {
	struct {
		unsigned int                        VCTRLADC : 3;
		unsigned int                                 : 1;
		unsigned int                 TEST_FBDIV_FRAC : 3;
		unsigned int                  TEST_FBDIV_INT : 10;
		unsigned int                      OINT_RESET : 1;
		unsigned int                       FREQ_LOCK : 1;
		unsigned int              FREQ_UNLOCK_STICKY : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_DQ_0_1_STATUS__SI__CI {
	struct {
		unsigned int                        VCTRLADC : 3;
		unsigned int                                 : 1;
		unsigned int                 TEST_FBDIV_FRAC : 3;
		unsigned int                  TEST_FBDIV_INT : 10;
		unsigned int                      OINT_RESET : 1;
		unsigned int                       FREQ_LOCK : 1;
		unsigned int              FREQ_UNLOCK_STICKY : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_DQ_1_0_STATUS__SI__CI {
	struct {
		unsigned int                        VCTRLADC : 3;
		unsigned int                                 : 1;
		unsigned int                 TEST_FBDIV_FRAC : 3;
		unsigned int                  TEST_FBDIV_INT : 10;
		unsigned int                      OINT_RESET : 1;
		unsigned int                       FREQ_LOCK : 1;
		unsigned int              FREQ_UNLOCK_STICKY : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_DQ_1_1_STATUS__SI__CI {
	struct {
		unsigned int                        VCTRLADC : 3;
		unsigned int                                 : 1;
		unsigned int                 TEST_FBDIV_FRAC : 3;
		unsigned int                  TEST_FBDIV_INT : 10;
		unsigned int                      OINT_RESET : 1;
		unsigned int                       FREQ_LOCK : 1;
		unsigned int              FREQ_UNLOCK_STICKY : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_DQ_FUNC_CNTL__SI__CI {
	struct {
		unsigned int                   YCLK_POST_DIV : 3;
		unsigned int                         SPARE_0 : 1;
		unsigned int                        YCLK_SEL : 1;
		unsigned int                           SPARE : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_FUNC_CNTL__SI__CI {
	struct {
		unsigned int                                 : 5;
		unsigned int                         SPARE_0 : 1;
		unsigned int                                 : 2;
		unsigned int                       BG_100ADJ : 4;
		unsigned int                                 : 4;
		unsigned int                       BG_135ADJ : 4;
		unsigned int                          BWCTRL : 8;
		unsigned int                                 : 2;
		unsigned int                        REG_BIAS : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_FUNC_CNTL_1__SI__CI {
	struct {
		unsigned int                        VCO_MODE : 2;
		unsigned int                         SPARE_0 : 2;
		unsigned int                         CLKFRAC : 12;
		unsigned int                            CLKF : 12;
		unsigned int                         SPARE_1 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_FUNC_CNTL_2__CI {
	struct {
		unsigned int                     VCTRLADC_EN : 1;
		unsigned int                    TEST_VCTL_EN : 1;
		unsigned int                        RESET_EN : 1;
		unsigned int                  TEST_BYPCLK_EN : 1;
		unsigned int                 TEST_BYPCLK_SRC : 1;
		unsigned int          TEST_FBDIV_FRAC_BYPASS : 1;
		unsigned int                    TEST_BYPMCLK : 1;
		unsigned int               MPLL_UNLOCK_CLEAR : 1;
		unsigned int                 TEST_VCTL_CNTRL : 1;
		unsigned int           TEST_FBDIV_SSC_BYPASS : 1;
		unsigned int                     RESET_TIMER : 2;
		unsigned int                 PFD_RESET_CNTRL : 2;
		unsigned int                    RISEFBVCO_EN : 1;
		unsigned int                     PWRGOOD_OVR : 1;
		unsigned int                       ISO_DIS_P : 1;
		unsigned int                        BACKUP_2 : 3;
		unsigned int                        LF_CNTRL : 7;
		unsigned int                          BACKUP : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_FUNC_CNTL_2__SI {
	struct {
		unsigned int                     VCTRLADC_EN : 1;
		unsigned int                    TEST_VCTL_EN : 1;
		unsigned int                        RESET_EN : 1;
		unsigned int                  TEST_BYPCLK_EN : 1;
		unsigned int                 TEST_BYPCLK_SRC : 1;
		unsigned int          TEST_FBDIV_FRAC_BYPASS : 1;
		unsigned int                    TEST_BYPMCLK : 1;
		unsigned int               MPLL_UNLOCK_CLEAR : 1;
		unsigned int                 TEST_VCTL_CNTRL : 1;
		unsigned int           TEST_FBDIV_SSC_BYPASS : 1;
		unsigned int                     RESET_TIMER : 2;
		unsigned int                 PFD_RESET_CNTRL : 2;
		unsigned int                                 : 3;
		unsigned int                        BACKUP_2 : 3;
		unsigned int                        LF_CNTRL : 7;
		unsigned int                          BACKUP : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_SEQ_UCODE_1__SI__CI {
	struct {
		unsigned int                          INSTR0 : 4;
		unsigned int                          INSTR1 : 4;
		unsigned int                          INSTR2 : 4;
		unsigned int                          INSTR3 : 4;
		unsigned int                          INSTR4 : 4;
		unsigned int                          INSTR5 : 4;
		unsigned int                          INSTR6 : 4;
		unsigned int                          INSTR7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_SEQ_UCODE_2__SI__CI {
	struct {
		unsigned int                          INSTR8 : 4;
		unsigned int                          INSTR9 : 4;
		unsigned int                         INSTR10 : 4;
		unsigned int                         INSTR11 : 4;
		unsigned int                         INSTR12 : 4;
		unsigned int                         INSTR13 : 4;
		unsigned int                         INSTR14 : 4;
		unsigned int                         INSTR15 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_SS1__SI__CI {
	struct {
		unsigned int                            CLKV : 26;
		unsigned int                           SPARE : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_SS2__SI__CI {
	struct {
		unsigned int                            CLKS : 12;
		unsigned int                           SPARE : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MPLL_TIME__SI__CI {
	struct {
		unsigned int                  MPLL_LOCK_TIME : 16;
		unsigned int                 MPLL_RESET_TIME : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MP_INT_EN__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MP_INT_STAT__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MP_STAT__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 4;
                unsigned int                                 : 8;
                unsigned int                                 : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MSI_CAP_LIST {
	struct {
		unsigned int                          CAP_ID : 8;
		unsigned int                        NEXT_PTR : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MSI_MSG_ADDR_HI {
	struct {
		unsigned int                 MSI_MSG_ADDR_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MSI_MSG_ADDR_LO {
	struct {
		unsigned int                                 : 2;
		unsigned int                 MSI_MSG_ADDR_LO : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MSI_MSG_CNTL {
	struct {
                unsigned int                          MSI_EN : 1;
                unsigned int                   MSI_MULTI_CAP : 3;
                unsigned int                    MSI_MULTI_EN : 3;
                unsigned int                       MSI_64BIT : 1;
                unsigned int   MSI_PERVECTOR_MASKING_CAP__VI : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MSI_MSG_DATA {
	struct {
		unsigned int                        MSI_DATA : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MSI_MSG_DATA_64 {
	struct {
		unsigned int                     MSI_DATA_64 : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_AFR_FLIP_FIFO_CNTL__SI__VI {
	struct {
                unsigned int   MVP_AFR_FLIP_FIFO_NUM_ENTRIES : 4;
                unsigned int         MVP_AFR_FLIP_FIFO_RESET : 1;
                unsigned int                                 : 3;
                unsigned int    MVP_AFR_FLIP_FIFO_RESET_FLAG : 1;
                unsigned int                                 : 3;
                unsigned int     MVP_AFR_FLIP_FIFO_RESET_ACK : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_AFR_FLIP_MODE__SI__VI {
	struct {
                unsigned int               MVP_AFR_FLIP_MODE : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_BLACK_KEYER__SI__VI {
	struct {
                unsigned int               MVP_BLACK_KEYER_R : 10;
                unsigned int               MVP_BLACK_KEYER_G : 10;
                unsigned int               MVP_BLACK_KEYER_B : 10;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_CONTROL1__SI__VI {
	struct {
                unsigned int                          MVP_EN : 1;
                unsigned int                                 : 3;
                unsigned int                  MVP_MIXER_MODE : 3;
                unsigned int                                 : 1;
                unsigned int             MVP_MIXER_SLAVE_SEL : 1;
                unsigned int MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK : 1;
                unsigned int MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE : 1;
                unsigned int                                 : 1;
                unsigned int                MVP_RATE_CONTROL : 1;
                unsigned int                                 : 3;
                unsigned int             MVP_CHANNEL_CONTROL : 1;
                unsigned int                                 : 3;
                unsigned int          MVP_GPU_CHAIN_LOCATION : 2;
                unsigned int                                 : 2;
                unsigned int          MVP_DISABLE_MSB_EXPAND : 1;
                unsigned int                                 : 3;
                unsigned int                    MVP_30BPP_EN : 1;
                unsigned int                                 : 1;
                unsigned int          MVP_TERMINATION_CNTL_A : 1;
                unsigned int          MVP_TERMINATION_CNTL_B : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_CONTROL2__SI__VI {
	struct {
                unsigned int         MVP_MUX_DE_DVOCNTL0_SEL : 1;
                unsigned int                                 : 3;
                unsigned int         MVP_MUX_DE_DVOCNTL2_SEL : 1;
                unsigned int                                 : 3;
                unsigned int                MVP_MUXA_CLK_SEL : 1;
                unsigned int                                 : 3;
                unsigned int                MVP_MUXB_CLK_SEL : 1;
                unsigned int                                 : 3;
                unsigned int                 MVP_DVOCNTL_MUX : 1;
                unsigned int                                 : 3;
                unsigned int         MVP_FLOW_CONTROL_OUT_EN : 1;
                unsigned int                                 : 3;
                unsigned int            MVP_SWAP_LOCK_OUT_EN : 1;
                unsigned int                                 : 3;
                unsigned int           MVP_SWAP_AB_IN_DC_DDR : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_CONTROL3__SI__VI {
	struct {
                unsigned int     MVP_RESET_IN_BETWEEN_FRAMES : 1;
                unsigned int                                 : 3;
                unsigned int               MVP_DDR_SC_AB_SEL : 1;
                unsigned int                                 : 3;
                unsigned int         MVP_DDR_SC_B_START_MODE : 1;
                unsigned int                                 : 3;
                unsigned int  MVP_FLOW_CONTROL_OUT_FORCE_ONE : 1;
                unsigned int                                 : 3;
                unsigned int MVP_FLOW_CONTROL_OUT_FORCE_ZERO : 1;
                unsigned int                                 : 3;
                unsigned int     MVP_FLOW_CONTROL_CASCADE_EN : 1;
                unsigned int                                 : 3;
                unsigned int               MVP_SWAP_48BIT_EN : 1;
                unsigned int                                 : 3;
                unsigned int         MVP_FLOW_CONTROL_IN_CAP : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_CRC_CNTL__SI__VI {
	struct {
                unsigned int               MVP_CRC_BLUE_MASK : 8;
                unsigned int              MVP_CRC_GREEN_MASK : 8;
                unsigned int                MVP_CRC_RED_MASK : 8;
                unsigned int                                 : 4;
                unsigned int                      MVP_CRC_EN : 1;
                unsigned int                 MVP_CRC_CONT_EN : 1;
                unsigned int MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_CRC_RESULT_BLUE_GREEN__SI__VI {
	struct {
                unsigned int             MVP_CRC_BLUE_RESULT : 16;
                unsigned int            MVP_CRC_GREEN_RESULT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_CRC_RESULT_RED__SI__VI {
	struct {
                unsigned int              MVP_CRC_RED_RESULT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_DEBUG_05__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int     IDE0_MVP_GPU_CHAIN_LOCATION : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 3;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_DEBUG_09__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION : 2;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_DEBUG_12__SI__VI {
	struct {
                unsigned int               IDEC_MVP_DATA_A_H : 1;
                unsigned int                 IDEC_MVP_DATA_A : 24;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_DEBUG_13__SI__VI {
	struct {
                unsigned int               IDED_MVP_DATA_B_H : 1;
                unsigned int                 IDED_MVP_DATA_B : 24;
                unsigned int               IDED_START_READ_B : 1;
                unsigned int       IDED_READ_FIFO_ENTRY_DE_B : 1;
                unsigned int                IDED_WRITE_ADD_B : 3;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_DEBUG_14__SI__VI {
	struct {
                unsigned int                   IDEE_READ_ADD : 3;
                unsigned int                IDEE_WRITE_ADD_A : 3;
                unsigned int                IDEE_WRITE_ADD_B : 3;
                unsigned int                 IDEE_START_READ : 1;
                unsigned int               IDEE_START_READ_B : 1;
                unsigned int            IDEE_START_INCR_WR_A : 1;
                unsigned int            IDEE_START_INCR_WR_B : 1;
                unsigned int                 IDEE_WRITE2FIFO : 1;
                unsigned int         IDEE_READ_FIFO_ENTRY_DE : 1;
                unsigned int       IDEE_READ_FIFO_ENTRY_DE_B : 1;
                unsigned int               IDEE_READ_FIFO_DE : 1;
                unsigned int             IDEE_READ_FIFO_DE_B : 1;
                unsigned int           IDEE_READ_FIFO_ENABLE : 1;
                unsigned int IDEE_CRTC1_CNTL_CAPTURE_START_A : 1;
                unsigned int                  IDEE_CRC_PHASE : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_DEBUG_15__SI__VI {
	struct {
                unsigned int         IDEF_MVP_ASYNC_FIFO_WEN : 1;
                unsigned int                                 : 3;
                unsigned int       IDEF_MVP_ASYNC_FIFO_WDATA : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_DEBUG_16__SI__VI {
	struct {
                unsigned int        IDCC_MVP_ASYNC_FIFO_READ : 1;
                unsigned int IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL : 1;
                unsigned int IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL : 1;
                unsigned int           IDCC_FLOW_CONTROL_OUT : 1;
                unsigned int IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES : 8;
                unsigned int    IDCC_MVP_ASYNC_FIFO_OVERFLOW : 1;
                unsigned int   IDCC_MVP_ASYNC_FIFO_UNDERFLOW : 1;
                unsigned int                                 : 2;
                unsigned int        IDCC_MVP_ASYNC_READ_ADDR : 8;
                unsigned int       IDCC_MVP_ASYNC_WRITE_ADDR : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_DEBUG_17__SI__VI {
	struct {
                unsigned int        IDCD_MVP_ASYNC_FIFO_READ : 1;
                unsigned int       IDCD_MVP_ASYNC_FIFO_PHASE : 1;
                unsigned int   IDCD_MVP_ASYNC_FIFO_READ_DATA : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_FIFO_CONTROL__SI__VI {
	struct {
                unsigned int               MVP_STOP_SLAVE_WM : 8;
                unsigned int              MVP_PAUSE_SLAVE_WM : 8;
                unsigned int             MVP_PAUSE_SLAVE_CNT : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_FIFO_STATUS__SI__VI {
	struct {
                unsigned int                  MVP_FIFO_LEVEL : 8;
                unsigned int               MVP_FIFO_OVERFLOW : 1;
                unsigned int                                 : 3;
                unsigned int      MVP_FIFO_OVERFLOW_OCCURRED : 1;
                unsigned int                                 : 3;
                unsigned int           MVP_FIFO_OVERFLOW_ACK : 1;
                unsigned int                                 : 3;
                unsigned int              MVP_FIFO_UNDERFLOW : 1;
                unsigned int                                 : 3;
                unsigned int     MVP_FIFO_UNDERFLOW_OCCURRED : 1;
                unsigned int                                 : 3;
                unsigned int          MVP_FIFO_UNDERFLOW_ACK : 1;
                unsigned int                                 : 1;
                unsigned int             MVP_FIFO_ERROR_MASK : 1;
                unsigned int       MVP_FIFO_ERROR_INT_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_FLIP_LINE_NUM_INSERT__SI__VI {
	struct {
                unsigned int   MVP_FLIP_LINE_NUM_INSERT_MODE : 2;
                unsigned int                                 : 6;
                unsigned int        MVP_FLIP_LINE_NUM_INSERT : 15;
                unsigned int                                 : 1;
                unsigned int        MVP_FLIP_LINE_NUM_OFFSET : 6;
                unsigned int            MVP_FLIP_AUTO_ENABLE : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_INBAND_CNTL_CAP__SI__VI {
	struct {
                unsigned int           MVP_IGNOR_INBAND_CNTL : 1;
                unsigned int                                 : 3;
                unsigned int      MVP_PASSING_INBAND_CNTL_EN : 1;
                unsigned int                                 : 3;
                unsigned int        MVP_INBAND_CNTL_CHAR_CAP : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_RECEIVE_CNT_CNTL1__SI__VI {
	struct {
                unsigned int       MVP_SLAVE_PIXEL_ERROR_CNT : 13;
                unsigned int                                 : 3;
                unsigned int        MVP_SLAVE_LINE_ERROR_CNT : 13;
                unsigned int                                 : 2;
                unsigned int           MVP_SLAVE_DATA_CHK_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_RECEIVE_CNT_CNTL2__SI__VI {
	struct {
                unsigned int       MVP_SLAVE_FRAME_ERROR_CNT : 13;
                unsigned int                                 : 18;
                unsigned int MVP_SLAVE_FRAME_ERROR_CNT_RESET : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_SLAVE_STATUS__SI__VI {
	struct {
                unsigned int MVP_SLAVE_PIXELS_PER_LINE_RCVED : 13;
                unsigned int                                 : 3;
                unsigned int MVP_SLAVE_LINES_PER_FRAME_RCVED : 13;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int             MVP_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int            MVP_TEST_DEBUG_INDEX : 8;
                unsigned int         MVP_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union NEW_REFCLKB_TIMER_1__CI {
	struct {
		unsigned int              PHY_PLL_PDWN_TIMER : 10;
		unsigned int                    PLL0_PDNB_EN : 1;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union NEW_REFCLKB_TIMER__CI {
	struct {
		unsigned int              REG_STOP_REFCLK_EN : 1;
		unsigned int               STOP_REFCLK_TIMER : 20;
		unsigned int                       REFCLK_ON : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_PAYLOAD_CAPABILITY__SI__VI {
	struct {
                unsigned int       OUTPUT_PAYLOAD_CAPABILITY : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVLSCL_EDGE_PIXEL_CNTL__SI__VI {
	struct {
                unsigned int          OVLSCL_BLACK_COLOR_BCB : 10;
                unsigned int           OVLSCL_BLACK_COLOR_GY : 10;
                unsigned int          OVLSCL_BLACK_COLOR_RCR : 10;
                unsigned int                                 : 1;
                unsigned int           OVLSCL_EDGE_PIXEL_SEL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_ALPHA__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_CONTROL1__SI {
	struct {
		unsigned int                       OVL_DEPTH : 2;
		unsigned int                                 : 2;
		unsigned int                           OVL_Z : 2;
		unsigned int                                 : 2;
		unsigned int                      OVL_FORMAT : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int  OVL_ADDRESS_TRANSLATION_ENABLE : 1;
		unsigned int    OVL_PRIVILEGED_ACCESS_ENABLE : 1;
		unsigned int                                 : 2;
		unsigned int                  OVL_ARRAY_MODE : 4;
		unsigned int        OVL_COLOR_EXPANSION_MODE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_CONTROL1__VI {
	struct {
		unsigned int                       OVL_DEPTH : 2;
		unsigned int                   OVL_NUM_BANKS : 2;
		unsigned int                           OVL_Z : 2;
		unsigned int                  OVL_BANK_WIDTH : 2;
		unsigned int                      OVL_FORMAT : 3;
		unsigned int                 OVL_BANK_HEIGHT : 2;
		unsigned int                  OVL_TILE_SPLIT : 3;
		unsigned int  OVL_ADDRESS_TRANSLATION_ENABLE : 1;
		unsigned int    OVL_PRIVILEGED_ACCESS_ENABLE : 1;
		unsigned int           OVL_MACRO_TILE_ASPECT : 2;
		unsigned int                  OVL_ARRAY_MODE : 4;
		unsigned int        OVL_COLOR_EXPANSION_MODE : 1;
		unsigned int                 OVL_PIPE_CONFIG : 5;
		unsigned int             OVL_MICRO_TILE_MODE : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_CONTROL2__SI__VI {
	struct {
                unsigned int      OVL_HALF_RESOLUTION_ENABLE : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_DFQ_CONTROL__SI__VI {
	struct {
                unsigned int                   OVL_DFQ_RESET : 1;
                unsigned int                                 : 3;
                unsigned int                    OVL_DFQ_SIZE : 3;
                unsigned int                                 : 1;
                unsigned int        OVL_DFQ_MIN_FREE_ENTRIES : 3;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_DFQ_STATUS__SI__VI {
	struct {
                unsigned int             OVL_DFQ_NUM_ENTRIES : 4;
                unsigned int OVL_SECONDARY_DFQ_NUM_ENTRIES__VI : 4;
                unsigned int              OVL_DFQ_RESET_FLAG : 1;
                unsigned int               OVL_DFQ_RESET_ACK : 1;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_ENABLE__SI__VI {
	struct {
                unsigned int                      OVL_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int                       OVLSCL_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_END__SI__VI {
	struct {
                unsigned int                       OVL_Y_END : 15;
                unsigned int                                 : 1;
                unsigned int                       OVL_X_END : 15;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_PITCH__SI__VI {
	struct {
                unsigned int                       OVL_PITCH : 15;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_START__SI__VI {
	struct {
                unsigned int                     OVL_Y_START : 14;
                unsigned int                                 : 2;
                unsigned int                     OVL_X_START : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_SURFACE_ADDRESS {
	struct {
		unsigned int                  OVL_DFQ_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int             OVL_SURFACE_ADDRESS : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_SURFACE_ADDRESS_HIGH {
	struct {
		unsigned int        OVL_SURFACE_ADDRESS_HIGH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_SURFACE_ADDRESS_HIGH_INUSE__SI__VI {
	struct {
                unsigned int  OVL_SURFACE_ADDRESS_HIGH_INUSE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_SURFACE_ADDRESS_INUSE__SI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int       OVL_SURFACE_ADDRESS_INUSE : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_SURFACE_OFFSET_X__SI__VI {
	struct {
                unsigned int            OVL_SURFACE_OFFSET_X : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_SURFACE_OFFSET_Y__SI__VI {
	struct {
                unsigned int            OVL_SURFACE_OFFSET_Y : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_SWAP_CNTL__SI__VI {
	struct {
                unsigned int                 OVL_ENDIAN_SWAP : 2;
                unsigned int                                 : 2;
                unsigned int                OVL_RED_CROSSBAR : 2;
                unsigned int              OVL_GREEN_CROSSBAR : 2;
                unsigned int               OVL_BLUE_CROSSBAR : 2;
                unsigned int              OVL_ALPHA_CROSSBAR : 2;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_UPDATE__SI__VI {
	struct {
                unsigned int              OVL_UPDATE_PENDING : 1;
                unsigned int                OVL_UPDATE_TAKEN : 1;
                unsigned int                                 : 14;
                unsigned int                 OVL_UPDATE_LOCK : 1;
                unsigned int                                 : 7;
                unsigned int     OVL_DISABLE_MULTIPLE_UPDATE : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PAGE_MIRROR_CNTL {
	struct {
		unsigned int           PAGE_MIRROR_BASE_ADDR : 24;
		unsigned int          PAGE_MIRROR_INVALIDATE : 1;
		unsigned int              PAGE_MIRROR_ENABLE : 1;
		unsigned int               PAGE_MIRROR_USAGE : 2;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_CLIP_CNTL {
	struct {
		unsigned int                       UCP_ENA_0 : 1;
		unsigned int                       UCP_ENA_1 : 1;
		unsigned int                       UCP_ENA_2 : 1;
		unsigned int                       UCP_ENA_3 : 1;
		unsigned int                       UCP_ENA_4 : 1;
		unsigned int                       UCP_ENA_5 : 1;
		unsigned int                                 : 7;
		unsigned int              PS_UCP_Y_SCALE_NEG : 1;
		unsigned int                     PS_UCP_MODE : 2;
		unsigned int                    CLIP_DISABLE : 1;
		unsigned int               UCP_CULL_ONLY_ENA : 1;
		unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
		unsigned int               DX_CLIP_SPACE_DEF : 1;
		unsigned int             DIS_CLIP_ERR_DETECT : 1;
		unsigned int                     VTX_KILL_OR : 1;
		unsigned int           DX_RASTERIZATION_KILL : 1;
		unsigned int                                 : 1;
		unsigned int         DX_LINEAR_ATTR_CLIP_ENA : 1;
		unsigned int       VTE_VPORT_PROVOKE_DISABLE : 1;
		unsigned int              ZCLIP_NEAR_DISABLE : 1;
		unsigned int               ZCLIP_FAR_DISABLE : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_CNTL_STATUS {
	struct {
		unsigned int                                 : 31;
		unsigned int                         CL_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_ENHANCE {
	struct {
		unsigned int            CLIP_VTX_REORDER_ENA : 1;
		unsigned int                    NUM_CLIP_SEQ : 2;
		unsigned int          CLIPPED_PRIM_SEQ_STALL : 1;
		unsigned int             VE_NAN_PROC_DISABLE : 1;
		unsigned int              XTRA_DEBUG_REG_SEL : 1;
		unsigned int                                 : 22;
		unsigned int                      ECO_SPARE3 : 1;
		unsigned int                      ECO_SPARE2 : 1;
		unsigned int                      ECO_SPARE1 : 1;
		unsigned int                      ECO_SPARE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_GB_HORZ_CLIP_ADJ {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_GB_HORZ_DISC_ADJ {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_GB_VERT_CLIP_ADJ {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_GB_VERT_DISC_ADJ {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_NANINF_CNTL {
	struct {
		unsigned int              VTE_XY_INF_DISCARD : 1;
		unsigned int               VTE_Z_INF_DISCARD : 1;
		unsigned int               VTE_W_INF_DISCARD : 1;
		unsigned int               VTE_0XNANINF_IS_0 : 1;
		unsigned int               VTE_XY_NAN_RETAIN : 1;
		unsigned int                VTE_Z_NAN_RETAIN : 1;
		unsigned int                VTE_W_NAN_RETAIN : 1;
		unsigned int            VTE_W_RECIP_NAN_IS_0 : 1;
		unsigned int                VS_XY_NAN_TO_INF : 1;
		unsigned int                VS_XY_INF_RETAIN : 1;
		unsigned int                 VS_Z_NAN_TO_INF : 1;
		unsigned int                 VS_Z_INF_RETAIN : 1;
		unsigned int                 VS_W_NAN_TO_INF : 1;
		unsigned int                 VS_W_INF_RETAIN : 1;
		unsigned int        VS_CLIP_DIST_INF_DISCARD : 1;
		unsigned int                                 : 5;
		unsigned int             VTE_NO_OUTPUT_NEG_0 : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_POINT_CULL_RAD {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_POINT_SIZE {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_POINT_X_RAD {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_POINT_Y_RAD {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_RESET_DEBUG__CI__VI {
	struct {
                unsigned int            CL_TRIV_DISC_DISABLE : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_0_W {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_0_X {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_0_Y {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_0_Z {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_1_W {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_1_X {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_1_Y {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_1_Z {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_2_W {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_2_X {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_2_Y {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_2_Z {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_3_W {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_3_X {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_3_Y {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_3_Z {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_4_W {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_4_X {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_4_Y {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_4_Z {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_5_W {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_5_X {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_5_Y {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_UCP_5_Z {
	struct {
		unsigned int                   DATA_REGISTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_1 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_10 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_11 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_12 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_13 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_14 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_15 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_2 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_3 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_4 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_5 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_6 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_7 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_8 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XOFFSET_9 {
	struct {
		unsigned int                   VPORT_XOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_1 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_10 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_11 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_12 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_13 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_14 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_15 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_2 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_3 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_4 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_5 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_6 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_7 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_8 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_XSCALE_9 {
	struct {
		unsigned int                    VPORT_XSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_1 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_10 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_11 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_12 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_13 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_14 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_15 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_2 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_3 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_4 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_5 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_6 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_7 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_8 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YOFFSET_9 {
	struct {
		unsigned int                   VPORT_YOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_1 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_10 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_11 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_12 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_13 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_14 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_15 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_2 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_3 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_4 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_5 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_6 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_7 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_8 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_YSCALE_9 {
	struct {
		unsigned int                    VPORT_YSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_1 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_10 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_11 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_12 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_13 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_14 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_15 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_2 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_3 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_4 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_5 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_6 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_7 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_8 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZOFFSET_9 {
	struct {
		unsigned int                   VPORT_ZOFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_1 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_10 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_11 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_12 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_13 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_14 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_15 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_2 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_3 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_4 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_5 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_6 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_7 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_8 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VPORT_ZSCALE_9 {
	struct {
		unsigned int                    VPORT_ZSCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VS_OUT_CNTL {
	struct {
                unsigned int                 CLIP_DIST_ENA_0 : 1;
                unsigned int                 CLIP_DIST_ENA_1 : 1;
                unsigned int                 CLIP_DIST_ENA_2 : 1;
                unsigned int                 CLIP_DIST_ENA_3 : 1;
                unsigned int                 CLIP_DIST_ENA_4 : 1;
                unsigned int                 CLIP_DIST_ENA_5 : 1;
                unsigned int                 CLIP_DIST_ENA_6 : 1;
                unsigned int                 CLIP_DIST_ENA_7 : 1;
                unsigned int                 CULL_DIST_ENA_0 : 1;
                unsigned int                 CULL_DIST_ENA_1 : 1;
                unsigned int                 CULL_DIST_ENA_2 : 1;
                unsigned int                 CULL_DIST_ENA_3 : 1;
                unsigned int                 CULL_DIST_ENA_4 : 1;
                unsigned int                 CULL_DIST_ENA_5 : 1;
                unsigned int                 CULL_DIST_ENA_6 : 1;
                unsigned int                 CULL_DIST_ENA_7 : 1;
                unsigned int              USE_VTX_POINT_SIZE : 1;
                unsigned int               USE_VTX_EDGE_FLAG : 1;
                unsigned int      USE_VTX_RENDER_TARGET_INDX : 1;
                unsigned int           USE_VTX_VIEWPORT_INDX : 1;
                unsigned int               USE_VTX_KILL_FLAG : 1;
                unsigned int             VS_OUT_MISC_VEC_ENA : 1;
                unsigned int          VS_OUT_CCDIST0_VEC_ENA : 1;
                unsigned int          VS_OUT_CCDIST1_VEC_ENA : 1;
                unsigned int        VS_OUT_MISC_SIDE_BUS_ENA : 1;
                unsigned int             USE_VTX_GS_CUT_FLAG : 1;
                unsigned int          USE_VTX_LINE_WIDTH__VI : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_CL_VTE_CNTL {
	struct {
		unsigned int               VPORT_X_SCALE_ENA : 1;
		unsigned int              VPORT_X_OFFSET_ENA : 1;
		unsigned int               VPORT_Y_SCALE_ENA : 1;
		unsigned int              VPORT_Y_OFFSET_ENA : 1;
		unsigned int               VPORT_Z_SCALE_ENA : 1;
		unsigned int              VPORT_Z_OFFSET_ENA : 1;
		unsigned int                                 : 2;
		unsigned int                      VTX_XY_FMT : 1;
		unsigned int                       VTX_Z_FMT : 1;
		unsigned int                      VTX_W0_FMT : 1;
		unsigned int                 PERFCOUNTER_REF : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_CONFIG {
	struct {
		unsigned int                MSAA_NUM_SAMPLES : 3;
		unsigned int                                 : 1;
		unsigned int           AA_MASK_CENTROID_DTMN : 1;
		unsigned int                                 : 8;
		unsigned int                 MAX_SAMPLE_DIST : 4;
		unsigned int                                 : 3;
		unsigned int            MSAA_EXPOSED_SAMPLES : 3;
		unsigned int                                 : 1;
		unsigned int          DETAIL_TO_EXPOSED_MODE : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_MASK_X0Y0_X1Y0 {
	struct {
		unsigned int                    AA_MASK_X0Y0 : 16;
		unsigned int                    AA_MASK_X1Y0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_MASK_X0Y1_X1Y1 {
	struct {
		unsigned int                    AA_MASK_X0Y1 : 16;
		unsigned int                    AA_MASK_X1Y1 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 {
	struct {
		unsigned int                            S0_X : 4;
		unsigned int                            S0_Y : 4;
		unsigned int                            S1_X : 4;
		unsigned int                            S1_Y : 4;
		unsigned int                            S2_X : 4;
		unsigned int                            S2_Y : 4;
		unsigned int                            S3_X : 4;
		unsigned int                            S3_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 {
	struct {
		unsigned int                            S4_X : 4;
		unsigned int                            S4_Y : 4;
		unsigned int                            S5_X : 4;
		unsigned int                            S5_Y : 4;
		unsigned int                            S6_X : 4;
		unsigned int                            S6_Y : 4;
		unsigned int                            S7_X : 4;
		unsigned int                            S7_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 {
	struct {
		unsigned int                            S8_X : 4;
		unsigned int                            S8_Y : 4;
		unsigned int                            S9_X : 4;
		unsigned int                            S9_Y : 4;
		unsigned int                           S10_X : 4;
		unsigned int                           S10_Y : 4;
		unsigned int                           S11_X : 4;
		unsigned int                           S11_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 {
	struct {
		unsigned int                           S12_X : 4;
		unsigned int                           S12_Y : 4;
		unsigned int                           S13_X : 4;
		unsigned int                           S13_Y : 4;
		unsigned int                           S14_X : 4;
		unsigned int                           S14_Y : 4;
		unsigned int                           S15_X : 4;
		unsigned int                           S15_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 {
	struct {
		unsigned int                            S0_X : 4;
		unsigned int                            S0_Y : 4;
		unsigned int                            S1_X : 4;
		unsigned int                            S1_Y : 4;
		unsigned int                            S2_X : 4;
		unsigned int                            S2_Y : 4;
		unsigned int                            S3_X : 4;
		unsigned int                            S3_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 {
	struct {
		unsigned int                            S4_X : 4;
		unsigned int                            S4_Y : 4;
		unsigned int                            S5_X : 4;
		unsigned int                            S5_Y : 4;
		unsigned int                            S6_X : 4;
		unsigned int                            S6_Y : 4;
		unsigned int                            S7_X : 4;
		unsigned int                            S7_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 {
	struct {
		unsigned int                            S8_X : 4;
		unsigned int                            S8_Y : 4;
		unsigned int                            S9_X : 4;
		unsigned int                            S9_Y : 4;
		unsigned int                           S10_X : 4;
		unsigned int                           S10_Y : 4;
		unsigned int                           S11_X : 4;
		unsigned int                           S11_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 {
	struct {
		unsigned int                           S12_X : 4;
		unsigned int                           S12_Y : 4;
		unsigned int                           S13_X : 4;
		unsigned int                           S13_Y : 4;
		unsigned int                           S14_X : 4;
		unsigned int                           S14_Y : 4;
		unsigned int                           S15_X : 4;
		unsigned int                           S15_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 {
	struct {
		unsigned int                            S0_X : 4;
		unsigned int                            S0_Y : 4;
		unsigned int                            S1_X : 4;
		unsigned int                            S1_Y : 4;
		unsigned int                            S2_X : 4;
		unsigned int                            S2_Y : 4;
		unsigned int                            S3_X : 4;
		unsigned int                            S3_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 {
	struct {
		unsigned int                            S4_X : 4;
		unsigned int                            S4_Y : 4;
		unsigned int                            S5_X : 4;
		unsigned int                            S5_Y : 4;
		unsigned int                            S6_X : 4;
		unsigned int                            S6_Y : 4;
		unsigned int                            S7_X : 4;
		unsigned int                            S7_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 {
	struct {
		unsigned int                            S8_X : 4;
		unsigned int                            S8_Y : 4;
		unsigned int                            S9_X : 4;
		unsigned int                            S9_Y : 4;
		unsigned int                           S10_X : 4;
		unsigned int                           S10_Y : 4;
		unsigned int                           S11_X : 4;
		unsigned int                           S11_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 {
	struct {
		unsigned int                           S12_X : 4;
		unsigned int                           S12_Y : 4;
		unsigned int                           S13_X : 4;
		unsigned int                           S13_Y : 4;
		unsigned int                           S14_X : 4;
		unsigned int                           S14_Y : 4;
		unsigned int                           S15_X : 4;
		unsigned int                           S15_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 {
	struct {
		unsigned int                            S0_X : 4;
		unsigned int                            S0_Y : 4;
		unsigned int                            S1_X : 4;
		unsigned int                            S1_Y : 4;
		unsigned int                            S2_X : 4;
		unsigned int                            S2_Y : 4;
		unsigned int                            S3_X : 4;
		unsigned int                            S3_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 {
	struct {
		unsigned int                            S4_X : 4;
		unsigned int                            S4_Y : 4;
		unsigned int                            S5_X : 4;
		unsigned int                            S5_Y : 4;
		unsigned int                            S6_X : 4;
		unsigned int                            S6_Y : 4;
		unsigned int                            S7_X : 4;
		unsigned int                            S7_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 {
	struct {
		unsigned int                            S8_X : 4;
		unsigned int                            S8_Y : 4;
		unsigned int                            S9_X : 4;
		unsigned int                            S9_Y : 4;
		unsigned int                           S10_X : 4;
		unsigned int                           S10_Y : 4;
		unsigned int                           S11_X : 4;
		unsigned int                           S11_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 {
	struct {
		unsigned int                           S12_X : 4;
		unsigned int                           S12_Y : 4;
		unsigned int                           S13_X : 4;
		unsigned int                           S13_Y : 4;
		unsigned int                           S14_X : 4;
		unsigned int                           S14_Y : 4;
		unsigned int                           S15_X : 4;
		unsigned int                           S15_Y : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CENTROID_PRIORITY_0 {
	struct {
		unsigned int                      DISTANCE_0 : 4;
		unsigned int                      DISTANCE_1 : 4;
		unsigned int                      DISTANCE_2 : 4;
		unsigned int                      DISTANCE_3 : 4;
		unsigned int                      DISTANCE_4 : 4;
		unsigned int                      DISTANCE_5 : 4;
		unsigned int                      DISTANCE_6 : 4;
		unsigned int                      DISTANCE_7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CENTROID_PRIORITY_1 {
	struct {
		unsigned int                      DISTANCE_8 : 4;
		unsigned int                      DISTANCE_9 : 4;
		unsigned int                     DISTANCE_10 : 4;
		unsigned int                     DISTANCE_11 : 4;
		unsigned int                     DISTANCE_12 : 4;
		unsigned int                     DISTANCE_13 : 4;
		unsigned int                     DISTANCE_14 : 4;
		unsigned int                     DISTANCE_15 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CLIPRECT_0_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CLIPRECT_0_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CLIPRECT_1_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CLIPRECT_1_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CLIPRECT_2_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CLIPRECT_2_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CLIPRECT_3_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CLIPRECT_3_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_CLIPRECT_RULE {
	struct {
		unsigned int                       CLIP_RULE : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_DEBUG_CNTL {
	struct {
		unsigned int                   SC_DEBUG_INDX : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_DEBUG_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_DEBUG_REG0 {
	struct {
		unsigned int                     REG0_FIELD0 : 2;
		unsigned int                     REG0_FIELD1 : 2;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_DEBUG_REG1 {
	struct {
		unsigned int                     REG1_FIELD0 : 2;
		unsigned int                     REG1_FIELD1 : 2;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_EDGERULE {
	struct {
		unsigned int                          ER_TRI : 4;
		unsigned int                        ER_POINT : 4;
		unsigned int                         ER_RECT : 4;
		unsigned int                      ER_LINE_LR : 6;
		unsigned int                      ER_LINE_RL : 6;
		unsigned int                      ER_LINE_TB : 4;
		unsigned int                      ER_LINE_BT : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_ENHANCE__CI__VI {
	struct {
                unsigned int       ENABLE_PA_SC_OUT_OF_ORDER : 1;
                unsigned int          DISABLE_SC_DB_TILE_FIX : 1;
                unsigned int        DISABLE_AA_MASK_FULL_FIX : 1;
                unsigned int  ENABLE_1XMSAA_SAMPLE_LOCATIONS : 1;
                unsigned int ENABLE_1XMSAA_SAMPLE_LOC_CENTROID : 1;
                unsigned int             DISABLE_SCISSOR_FIX : 1;
                unsigned int      DISABLE_PW_BUBBLE_COLLAPSE : 2;
                unsigned int     SEND_UNLIT_STILES_TO_PACKER : 1;
                unsigned int DISABLE_DUALGRAD_PERF_OPTIMIZATION : 1;
                unsigned int   DISABLE_SC_PROCESS_RESET_PRIM : 1;
                unsigned int DISABLE_SC_PROCESS_RESET_SUPERTILE : 1;
                unsigned int   DISABLE_SC_PROCESS_RESET_TILE : 1;
                unsigned int          DISABLE_PA_SC_GUIDANCE : 1;
                unsigned int DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS : 1;
                unsigned int ENABLE_MULTICYCLE_BUBBLE_FREEZE : 1;
                unsigned int DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE : 1;
                unsigned int   ENABLE_OUT_OF_ORDER_POLY_MODE : 1;
                unsigned int DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST : 1;
                unsigned int DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING : 1;
                unsigned int ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY : 1;
                unsigned int DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING : 1;
                unsigned int DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING : 1;
                unsigned int DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS : 1;
                unsigned int ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID : 1;
                unsigned int DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO : 1;
                unsigned int OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT : 1;
                unsigned int OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING : 1;
                unsigned int  DISABLE_EOP_LINE_STIPPLE_RESET : 1;
                unsigned int DISABLE_VPZ_EOP_LINE_STIPPLE_RESET : 1;
                unsigned int                      ECO_SPARE1 : 1;
                unsigned int                      ECO_SPARE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_ENHANCE__SI {
	struct {
		unsigned int       ENABLE_PA_SC_OUT_OF_ORDER : 1;
		unsigned int          DISABLE_SC_DB_TILE_FIX : 1;
		unsigned int        DISABLE_AA_MASK_FULL_FIX : 1;
		unsigned int  ENABLE_1XMSAA_SAMPLE_LOCATIONS : 1;
		unsigned int ENABLE_1XMSAA_SAMPLE_LOC_CENTROID : 1;
		unsigned int             DISABLE_SCISSOR_FIX : 1;
		unsigned int      DISABLE_PW_BUBBLE_COLLAPSE : 2;
		unsigned int     SEND_UNLIT_STILES_TO_PACKER : 1;
		unsigned int DISABLE_DUALGRAD_PERF_OPTIMIZATION : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 12;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                      ECO_SPARE1 : 1;
		unsigned int                      ECO_SPARE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_FIFO_DEPTH_CNTL {
	struct {
                unsigned int                           DEPTH : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_FIFO_SIZE {
	struct {
		unsigned int      SC_FRONTEND_PRIM_FIFO_SIZE : 6;
		unsigned int       SC_BACKEND_PRIM_FIFO_SIZE : 9;
		unsigned int           SC_HIZ_TILE_FIFO_SIZE : 6;
		unsigned int                                 : 2;
		unsigned int        SC_EARLYZ_TILE_FIFO_SIZE : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_FORCE_EOV_MAX_CNTS {
	struct {
		unsigned int           FORCE_EOV_MAX_CLK_CNT : 16;
		unsigned int           FORCE_EOV_MAX_REZ_CNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_GENERIC_SCISSOR_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_GENERIC_SCISSOR_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_HP3D_TRAP_SCREEN_COUNT__CI__VI {
	struct {
                unsigned int                           COUNT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_HP3D_TRAP_SCREEN_HV_EN__CI__VI {
	struct {
                unsigned int            ENABLE_HV_PRE_SHADER : 1;
                unsigned int     FORCE_PRE_SHADER_ALL_PIXELS : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__CI__VI {
	struct {
                unsigned int         DISABLE_NON_PRIV_WRITES : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_HP3D_TRAP_SCREEN_H__CI__VI {
	struct {
                unsigned int                         X_COORD : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__CI__VI {
	struct {
                unsigned int                           COUNT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_HP3D_TRAP_SCREEN_V__CI__VI {
	struct {
                unsigned int                         Y_COORD : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_IF_FIFO_SIZE {
	struct {
		unsigned int         SC_DB_TILE_IF_FIFO_SIZE : 6;
		unsigned int         SC_DB_QUAD_IF_FIFO_SIZE : 6;
		unsigned int             SC_SPI_IF_FIFO_SIZE : 6;
		unsigned int             SC_BCI_IF_FIFO_SIZE : 6;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_LINE_CNTL {
	struct {
		unsigned int                                 : 9;
		unsigned int               EXPAND_LINE_WIDTH : 1;
		unsigned int                      LAST_PIXEL : 1;
		unsigned int        PERPENDICULAR_ENDCAP_ENA : 1;
		unsigned int           DX10_DIAMOND_TEST_ENA : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_LINE_STIPPLE {
	struct {
		unsigned int                    LINE_PATTERN : 16;
		unsigned int                    REPEAT_COUNT : 8;
		unsigned int                                 : 4;
		unsigned int               PATTERN_BIT_ORDER : 1;
		unsigned int                 AUTO_RESET_CNTL : 2;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_LINE_STIPPLE_STATE {
	struct {
		unsigned int                     CURRENT_PTR : 4;
		unsigned int                                 : 4;
		unsigned int                   CURRENT_COUNT : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_MODE_CNTL_0 {
	struct {
		unsigned int                     MSAA_ENABLE : 1;
		unsigned int            VPORT_SCISSOR_ENABLE : 1;
		unsigned int             LINE_STIPPLE_ENABLE : 1;
		unsigned int        SEND_UNLIT_STILES_TO_PKR : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_MODE_CNTL_1 {
	struct {
		unsigned int                       WALK_SIZE : 1;
		unsigned int                  WALK_ALIGNMENT : 1;
		unsigned int        WALK_ALIGN8_PRIM_FITS_ST : 1;
		unsigned int               WALK_FENCE_ENABLE : 1;
		unsigned int                 WALK_FENCE_SIZE : 3;
		unsigned int     SUPERTILE_WALK_ORDER_ENABLE : 1;
		unsigned int          TILE_WALK_ORDER_ENABLE : 1;
		unsigned int              TILE_COVER_DISABLE : 1;
		unsigned int           TILE_COVER_NO_SCISSOR : 1;
		unsigned int                 ZMM_LINE_EXTENT : 1;
		unsigned int                 ZMM_LINE_OFFSET : 1;
		unsigned int                 ZMM_RECT_EXTENT : 1;
		unsigned int              KILL_PIX_POST_HI_Z : 1;
		unsigned int       KILL_PIX_POST_DETAIL_MASK : 1;
		unsigned int                  PS_ITER_SAMPLE : 1;
		unsigned int MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE : 1;
		unsigned int      MULTI_GPU_SUPERTILE_ENABLE : 1;
		unsigned int          GPU_ID_OVERRIDE_ENABLE : 1;
		unsigned int                 GPU_ID_OVERRIDE : 4;
		unsigned int   MULTI_GPU_PRIM_DISCARD_ENABLE : 1;
		unsigned int         FORCE_EOV_CNTDWN_ENABLE : 1;
		unsigned int            FORCE_EOV_REZ_ENABLE : 1;
		unsigned int   OUT_OF_ORDER_PRIMITIVE_ENABLE : 1;
		unsigned int         OUT_OF_ORDER_WATER_MARK : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_P3D_TRAP_SCREEN_COUNT__CI__VI {
	struct {
                unsigned int                           COUNT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_P3D_TRAP_SCREEN_HV_EN__CI__VI {
	struct {
                unsigned int            ENABLE_HV_PRE_SHADER : 1;
                unsigned int     FORCE_PRE_SHADER_ALL_PIXELS : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_P3D_TRAP_SCREEN_HV_LOCK__CI__VI {
	struct {
                unsigned int         DISABLE_NON_PRIV_WRITES : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_P3D_TRAP_SCREEN_H__CI__VI {
	struct {
                unsigned int                         X_COORD : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__CI__VI {
	struct {
                unsigned int                           COUNT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_P3D_TRAP_SCREEN_V__CI__VI {
	struct {
                unsigned int                         Y_COORD : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER0_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER1_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER2_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER3_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER4_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER4_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER4_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER5_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER5_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER5_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER6_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER6_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER6_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER7_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER7_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_PERFCOUNTER7_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_RASTER_CONFIG {
	struct {
                unsigned int                     RB_MAP_PKR0 : 2;
                unsigned int                     RB_MAP_PKR1 : 2;
                unsigned int                        RB_XSEL2 : 2;
                unsigned int                         RB_XSEL : 1;
                unsigned int                         RB_YSEL : 1;
                unsigned int                         PKR_MAP : 2;
                unsigned int                        PKR_XSEL : 2;
                unsigned int                        PKR_YSEL : 2;
                unsigned int               PKR_XSEL2__CI__VI : 2;
                unsigned int                          SC_MAP : 2;
                unsigned int                         SC_XSEL : 2;
                unsigned int                         SC_YSEL : 2;
                unsigned int                                 : 2;
                unsigned int                          SE_MAP : 2;
                unsigned int                         SE_XSEL : 2;
                unsigned int                         SE_YSEL : 2;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_RASTER_CONFIG_1__CI__VI {
	struct {
                unsigned int                     SE_PAIR_MAP : 2;
                unsigned int                    SE_PAIR_XSEL : 2;
                unsigned int                    SE_PAIR_YSEL : 2;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_SCREEN_SCISSOR_BR {
	struct {
		unsigned int                            BR_X : 16;
		unsigned int                            BR_Y : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_SCREEN_SCISSOR_TL {
	struct {
		unsigned int                            TL_X : 16;
		unsigned int                            TL_Y : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_TRAP_SCREEN_COUNT__CI__VI {
	struct {
                unsigned int                           COUNT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_TRAP_SCREEN_HV_EN__CI__VI {
	struct {
                unsigned int            ENABLE_HV_PRE_SHADER : 1;
                unsigned int     FORCE_PRE_SHADER_ALL_PIXELS : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_TRAP_SCREEN_HV_LOCK__CI__VI {
	struct {
                unsigned int         DISABLE_NON_PRIV_WRITES : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_TRAP_SCREEN_H__CI__VI {
	struct {
                unsigned int                         X_COORD : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_TRAP_SCREEN_OCCURRENCE__CI__VI {
	struct {
                unsigned int                           COUNT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_TRAP_SCREEN_V__CI__VI {
	struct {
                unsigned int                         Y_COORD : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_0_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_0_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_10_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_10_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_11_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_11_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_12_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_12_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_13_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_13_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_14_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_14_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_15_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_15_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_1_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_1_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_2_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_2_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_3_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_3_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_4_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_4_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_5_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_5_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_6_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_6_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_7_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_7_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_8_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_8_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_9_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_SCISSOR_9_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_0 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_1 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_10 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_11 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_12 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_13 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_14 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_15 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_2 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_3 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_4 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_5 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_6 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_7 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_8 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMAX_9 {
	struct {
		unsigned int                      VPORT_ZMAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_0 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_1 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_10 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_11 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_12 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_13 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_14 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_15 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_2 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_3 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_4 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_5 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_6 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_7 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_8 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_VPORT_ZMIN_9 {
	struct {
		unsigned int                      VPORT_ZMIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_WINDOW_OFFSET {
	struct {
		unsigned int                 WINDOW_X_OFFSET : 16;
		unsigned int                 WINDOW_Y_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_WINDOW_SCISSOR_BR {
	struct {
		unsigned int                            BR_X : 15;
		unsigned int                                 : 1;
		unsigned int                            BR_Y : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SC_WINDOW_SCISSOR_TL {
	struct {
		unsigned int                            TL_X : 15;
		unsigned int                                 : 1;
		unsigned int                            TL_Y : 15;
		unsigned int           WINDOW_OFFSET_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_CNTL_STATUS {
	struct {
		unsigned int                                 : 31;
		unsigned int                         SU_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_DEBUG_CNTL {
	struct {
		unsigned int                   SU_DEBUG_INDX : 5;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_DEBUG_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_HARDWARE_SCREEN_OFFSET {
	struct {
		unsigned int              HW_SCREEN_OFFSET_X : 9;
		unsigned int                                 : 7;
		unsigned int              HW_SCREEN_OFFSET_Y : 9;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_LINE_CNTL {
	struct {
		unsigned int                           WIDTH : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_LINE_STIPPLE_CNTL {
	struct {
		unsigned int              LINE_STIPPLE_RESET : 2;
		unsigned int              EXPAND_FULL_LENGTH : 1;
		unsigned int                FRACTIONAL_ACCUM : 1;
		unsigned int                  DIAMOND_ADJUST : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_LINE_STIPPLE_SCALE {
	struct {
		unsigned int              LINE_STIPPLE_SCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_LINE_STIPPLE_VALUE {
	struct {
		unsigned int              LINE_STIPPLE_VALUE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER0_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER1_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER1_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER2_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PERFCOUNTER3_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_POINT_MINMAX {
	struct {
		unsigned int                        MIN_SIZE : 16;
		unsigned int                        MAX_SIZE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_POINT_SIZE {
	struct {
		unsigned int                          HEIGHT : 16;
		unsigned int                           WIDTH : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_POLY_OFFSET_BACK_OFFSET {
	struct {
		unsigned int                          OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_POLY_OFFSET_BACK_SCALE {
	struct {
		unsigned int                           SCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_POLY_OFFSET_CLAMP {
	struct {
		unsigned int                           CLAMP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_POLY_OFFSET_DB_FMT_CNTL {
	struct {
		unsigned int     POLY_OFFSET_NEG_NUM_DB_BITS : 8;
		unsigned int     POLY_OFFSET_DB_IS_FLOAT_FMT : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_POLY_OFFSET_FRONT_OFFSET {
	struct {
		unsigned int                          OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_POLY_OFFSET_FRONT_SCALE {
	struct {
		unsigned int                           SCALE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_PRIM_FILTER_CNTL {
	struct {
                unsigned int         TRIANGLE_FILTER_DISABLE : 1;
                unsigned int             LINE_FILTER_DISABLE : 1;
                unsigned int            POINT_FILTER_DISABLE : 1;
                unsigned int        RECTANGLE_FILTER_DISABLE : 1;
                unsigned int             TRIANGLE_EXPAND_ENA : 1;
                unsigned int                 LINE_EXPAND_ENA : 1;
                unsigned int                POINT_EXPAND_ENA : 1;
                unsigned int            RECTANGLE_EXPAND_ENA : 1;
                unsigned int            PRIM_EXPAND_CONSTANT : 8;
                unsigned int                                 : 14;
                unsigned int    XMAX_RIGHT_EXCLUSION__CI__VI : 1;
                unsigned int   YMAX_BOTTOM_EXCLUSION__CI__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_SC_MODE_CNTL {
	struct {
		unsigned int                      CULL_FRONT : 1;
		unsigned int                       CULL_BACK : 1;
		unsigned int                            FACE : 1;
		unsigned int                       POLY_MODE : 2;
		unsigned int            POLYMODE_FRONT_PTYPE : 3;
		unsigned int             POLYMODE_BACK_PTYPE : 3;
		unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
		unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
		unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
		unsigned int                                 : 2;
		unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
		unsigned int                                 : 2;
		unsigned int              PROVOKING_VTX_LAST : 1;
		unsigned int                  PERSP_CORR_DIS : 1;
		unsigned int               MULTI_PRIM_IB_ENA : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PA_SU_VTX_CNTL {
	struct {
		unsigned int                      PIX_CENTER : 1;
		unsigned int                      ROUND_MODE : 2;
		unsigned int                      QUANT_MODE : 3;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_DFT_DEBUG_CTRL_REG0__CI__VI {
	struct {
                unsigned int                DFT_PHY_DEBUG_EN : 1;
                unsigned int              DFT_PHY_DEBUG_MODE : 5;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_DFT_JIT_INJ_REG0__CI__VI {
	struct {
                unsigned int                   DFT_NUM_STEPS : 6;
                unsigned int                                 : 1;
                unsigned int                 DFT_DISABLE_ERR : 1;
                unsigned int                DFT_CLK_PER_STEP : 4;
                unsigned int                                 : 8;
                unsigned int                 DFT_MODE_CDR_EN : 1;
                unsigned int                 DFT_EN_RECOVERY : 1;
                unsigned int                 DFT_INCR_SWP_EN : 1;
                unsigned int                 DFT_DECR_SWP_EN : 1;
                unsigned int               DFT_RECOVERY_TIME : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_DFT_JIT_INJ_REG1__CI__VI {
	struct {
                unsigned int                DFT_BYPASS_VALUE : 8;
                unsigned int                   DFT_BYPASS_EN : 1;
                unsigned int                                 : 7;
                unsigned int                    DFT_BLOCK_EN : 1;
                unsigned int                DFT_NUM_OF_TESTS : 3;
                unsigned int                  DFT_CHECK_TIME : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_DFT_JIT_INJ_REG2__CI__VI {
	struct {
                unsigned int                     DFT_LANE_EN : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_DFT_JIT_INJ_STAT_REG0__CI__VI {
	struct {
                unsigned int                   DFT_STAT_DECR : 8;
                unsigned int                   DFT_STAT_INCR : 8;
                unsigned int               DFT_STAT_FINISHED : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_CTRL_REG0__CI__VI {
	struct {
                unsigned int                          BACKUP : 16;
                unsigned int                  CFG_IDLEDET_TH : 2;
                unsigned int                                 : 2;
                unsigned int                DBG_RX2TXBYP_SEL : 3;
                unsigned int                  DBG_RXFEBYP_EN : 1;
                unsigned int                  DBG_RXPRBS_CLR : 1;
                unsigned int                 DBG_RXTOGGLE_EN : 1;
                unsigned int               DBG_TX2RXLBACK_EN : 1;
                unsigned int                                 : 3;
                unsigned int              TXCFG_CMGOOD_RANGE : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_CTRL_REG1__CI__VI {
	struct {
                unsigned int             RXDBG_CDR_FR_BYP_EN : 1;
                unsigned int            RXDBG_CDR_FR_BYP_VAL : 6;
                unsigned int             RXDBG_CDR_PH_BYP_EN : 1;
                unsigned int            RXDBG_CDR_PH_BYP_VAL : 6;
                unsigned int               RXDBG_D0TH_BYP_EN : 1;
                unsigned int              RXDBG_D0TH_BYP_VAL : 7;
                unsigned int               RXDBG_D1TH_BYP_EN : 1;
                unsigned int              RXDBG_D1TH_BYP_VAL : 7;
                unsigned int                 TST_LOSPDTST_EN : 1;
                unsigned int             PLL_CFG_DISPCLK_DIV : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_CTRL_REG2__CI__VI {
	struct {
                unsigned int               RXDBG_D2TH_BYP_EN : 1;
                unsigned int              RXDBG_D2TH_BYP_VAL : 7;
                unsigned int               RXDBG_D3TH_BYP_EN : 1;
                unsigned int              RXDBG_D3TH_BYP_VAL : 7;
                unsigned int               RXDBG_DXTH_BYP_EN : 1;
                unsigned int              RXDBG_DXTH_BYP_VAL : 7;
                unsigned int                RXDBG_ETH_BYP_EN : 1;
                unsigned int               RXDBG_ETH_BYP_VAL : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_CTRL_REG3__CI__VI {
	struct {
                unsigned int                       RXDBG_SEL : 5;
                unsigned int         BG_CFG_LC_REG_VREF0_SEL : 2;
                unsigned int         BG_CFG_LC_REG_VREF1_SEL : 2;
                unsigned int          BG_CFG_RO_REG_VREF_SEL : 2;
                unsigned int               BG_DBG_VREFBYP_EN : 1;
                unsigned int               BG_DBG_IREFBYP_EN : 1;
                unsigned int                                 : 1;
                unsigned int               BG_DBG_ANALOG_SEL : 3;
                unsigned int                                 : 1;
                unsigned int                 DBG_DLL_CLK_SEL : 3;
                unsigned int            PLL_DISPCLK_CMOS_SEL : 1;
                unsigned int          DBG_RXPI_OFFSET_BYP_EN : 1;
                unsigned int         DBG_RXPI_OFFSET_BYP_VAL : 4;
                unsigned int             DBG_RXSWAPDX_BYP_EN : 1;
                unsigned int            DBG_RXSWAPDX_BYP_VAL : 3;
                unsigned int DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_CTRL_REG4__CI__VI {
	struct {
                unsigned int                  DBG_RXAPU_INST : 16;
                unsigned int            DBG_RXDFEMUX_BYP_VAL : 2;
                unsigned int             DBG_RXDFEMUX_BYP_EN : 1;
                unsigned int                                 : 3;
                unsigned int                  DBG_RXAPU_EXEC : 4;
                unsigned int          DBG_RXDLL_VREG_REF_SEL : 1;
                unsigned int                    PWRGOOD_OVRD : 1;
                unsigned int      DBG_RXRDATA_GATING_DISABLE : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_CTRL_REG5__CI__VI {
	struct {
                unsigned int                  DBG_RXAPU_MODE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TXPDTERM_VAL_OVRD_VAL : 16;
                unsigned int           TXPUTERM_VAL_OVRD_VAL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_OVRD_REG1__CI__VI {
	struct {
                unsigned int            TXPDTERM_VAL_OVRD_EN : 1;
                unsigned int            TXPUTERM_VAL_OVRD_EN : 1;
                unsigned int        TST_LOSPDTST_RST_OVRD_EN : 1;
                unsigned int       TST_LOSPDTST_RST_OVRD_VAL : 1;
                unsigned int                                 : 11;
                unsigned int              RXTERM_VAL_OVRD_EN : 1;
                unsigned int             RXTERM_VAL_OVRD_VAL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_OVRD_REG2__CI__VI {
	struct {
                unsigned int                BG_PWRON_OVRD_EN : 1;
                unsigned int               BG_PWRON_OVRD_VAL : 1;
                unsigned int PLL_DBG_LC_EXT_RESET_OVRD_EN__VI : 1;
                unsigned int PLL_DBG_LC_EXT_RESET_OVRD_VAL__VI : 1;
                unsigned int PLL_DBG_RO_EXT_RESET_OVRD_EN__VI : 1;
                unsigned int PLL_DBG_RO_EXT_RESET_OVRD_VAL__VI : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int          IGNR_ALL_SCI_UPDT_L0T3 : 1;
		unsigned int          IGNR_ALL_SCI_UPDT_L4T7 : 1;
		unsigned int         IGNR_ALL_SCI_UPDT_L8T11 : 1;
		unsigned int        IGNR_ALL_SCI_UPDT_L12T15 : 1;
		unsigned int     IGNR_IMPCAL_ACTIVE_SCI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                          TXNIMP : 4;
		unsigned int                          TXPIMP : 4;
		unsigned int                           RXIMP : 4;
		unsigned int                   IMPCAL_ACTIVE : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int          IGNR_ALL_CBI_UPDT_L0T3 : 1;
		unsigned int          IGNR_ALL_CBI_UPDT_L4T7 : 1;
		unsigned int         IGNR_ALL_CBI_UPDT_L8T11 : 1;
		unsigned int        IGNR_ALL_CBI_UPDT_L12T15 : 1;
		unsigned int     IGNR_IMPCAL_ACTIVE_CBI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                          TXNIMP : 4;
		unsigned int                          TXPIMP : 4;
		unsigned int                           RXIMP : 4;
		unsigned int                   IMPCAL_ACTIVE : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_SCI_STAT_OVRD_REG1__CI {
	struct {
		unsigned int         IGNR_MODE_SCI_UPDT_L0T3 : 1;
		unsigned int      IGNR_FREQDIV_SCI_UPDT_L0T3 : 1;
		unsigned int     IGNR_DLL_LOCK_SCI_UPDT_L0T3 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_0 : 1;
		unsigned int                      DLL_LOCK_1 : 1;
		unsigned int                      DLL_LOCK_2 : 1;
		unsigned int                      DLL_LOCK_3 : 1;
		unsigned int                          MODE_0 : 2;
		unsigned int                       FREQDIV_0 : 2;
		unsigned int                          MODE_1 : 2;
		unsigned int                       FREQDIV_1 : 2;
		unsigned int                          MODE_2 : 2;
		unsigned int                       FREQDIV_2 : 2;
		unsigned int                          MODE_3 : 2;
		unsigned int                       FREQDIV_3 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_SCI_STAT_OVRD_REG1__VI {
	struct {
		unsigned int    IGNR_LINKSPEED_CBI_UPDT_L0T3 : 1;
		unsigned int      IGNR_FREQDIV_CBI_UPDT_L0T3 : 1;
		unsigned int     IGNR_DLL_LOCK_CBI_UPDT_L0T3 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_0 : 1;
		unsigned int                      DLL_LOCK_1 : 1;
		unsigned int                      DLL_LOCK_2 : 1;
		unsigned int                      DLL_LOCK_3 : 1;
		unsigned int                     LINKSPEED_0 : 2;
		unsigned int                       FREQDIV_0 : 2;
		unsigned int                     LINKSPEED_1 : 2;
		unsigned int                       FREQDIV_1 : 2;
		unsigned int                     LINKSPEED_2 : 2;
		unsigned int                       FREQDIV_2 : 2;
		unsigned int                     LINKSPEED_3 : 2;
		unsigned int                       FREQDIV_3 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_SCI_STAT_OVRD_REG2__CI {
	struct {
		unsigned int         IGNR_MODE_SCI_UPDT_L4T7 : 1;
		unsigned int      IGNR_FREQDIV_SCI_UPDT_L4T7 : 1;
		unsigned int     IGNR_DLL_LOCK_SCI_UPDT_L4T7 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_4 : 1;
		unsigned int                      DLL_LOCK_5 : 1;
		unsigned int                      DLL_LOCK_6 : 1;
		unsigned int                      DLL_LOCK_7 : 1;
		unsigned int                          MODE_4 : 2;
		unsigned int                       FREQDIV_4 : 2;
		unsigned int                          MODE_5 : 2;
		unsigned int                       FREQDIV_5 : 2;
		unsigned int                          MODE_6 : 2;
		unsigned int                       FREQDIV_6 : 2;
		unsigned int                          MODE_7 : 2;
		unsigned int                       FREQDIV_7 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_SCI_STAT_OVRD_REG2__VI {
	struct {
		unsigned int    IGNR_LINKSPEED_CBI_UPDT_L4T7 : 1;
		unsigned int      IGNR_FREQDIV_CBI_UPDT_L4T7 : 1;
		unsigned int     IGNR_DLL_LOCK_CBI_UPDT_L4T7 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_4 : 1;
		unsigned int                      DLL_LOCK_5 : 1;
		unsigned int                      DLL_LOCK_6 : 1;
		unsigned int                      DLL_LOCK_7 : 1;
		unsigned int                     LINKSPEED_4 : 2;
		unsigned int                       FREQDIV_4 : 2;
		unsigned int                     LINKSPEED_5 : 2;
		unsigned int                       FREQDIV_5 : 2;
		unsigned int                     LINKSPEED_6 : 2;
		unsigned int                       FREQDIV_6 : 2;
		unsigned int                     LINKSPEED_7 : 2;
		unsigned int                       FREQDIV_7 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_SCI_STAT_OVRD_REG3__CI {
	struct {
		unsigned int        IGNR_MODE_SCI_UPDT_L8T11 : 1;
		unsigned int     IGNR_FREQDIV_SCI_UPDT_L8T11 : 1;
		unsigned int    IGNR_DLL_LOCK_SCI_UPDT_L8T11 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_8 : 1;
		unsigned int                      DLL_LOCK_9 : 1;
		unsigned int                     DLL_LOCK_10 : 1;
		unsigned int                     DLL_LOCK_11 : 1;
		unsigned int                          MODE_8 : 2;
		unsigned int                       FREQDIV_8 : 2;
		unsigned int                          MODE_9 : 2;
		unsigned int                       FREQDIV_9 : 2;
		unsigned int                         MODE_10 : 2;
		unsigned int                      FREQDIV_10 : 2;
		unsigned int                         MODE_11 : 2;
		unsigned int                      FREQDIV_11 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_SCI_STAT_OVRD_REG3__VI {
	struct {
		unsigned int   IGNR_LINKSPEED_CBI_UPDT_L8T11 : 1;
		unsigned int     IGNR_FREQDIV_CBI_UPDT_L8T11 : 1;
		unsigned int    IGNR_DLL_LOCK_CBI_UPDT_L8T11 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_8 : 1;
		unsigned int                      DLL_LOCK_9 : 1;
		unsigned int                     DLL_LOCK_10 : 1;
		unsigned int                     DLL_LOCK_11 : 1;
		unsigned int                     LINKSPEED_8 : 2;
		unsigned int                       FREQDIV_8 : 2;
		unsigned int                     LINKSPEED_9 : 2;
		unsigned int                       FREQDIV_9 : 2;
		unsigned int                    LINKSPEED_10 : 2;
		unsigned int                      FREQDIV_10 : 2;
		unsigned int                    LINKSPEED_11 : 2;
		unsigned int                      FREQDIV_11 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_SCI_STAT_OVRD_REG4__CI {
	struct {
		unsigned int       IGNR_MODE_SCI_UPDT_L12T15 : 1;
		unsigned int    IGNR_FREQDIV_SCI_UPDT_L12T15 : 1;
		unsigned int   IGNR_DLL_LOCK_SCI_UPDT_L12T15 : 1;
		unsigned int                                 : 9;
		unsigned int                     DLL_LOCK_12 : 1;
		unsigned int                     DLL_LOCK_13 : 1;
		unsigned int                     DLL_LOCK_14 : 1;
		unsigned int                     DLL_LOCK_15 : 1;
		unsigned int                         MODE_12 : 2;
		unsigned int                      FREQDIV_12 : 2;
		unsigned int                         MODE_13 : 2;
		unsigned int                      FREQDIV_13 : 2;
		unsigned int                         MODE_14 : 2;
		unsigned int                      FREQDIV_14 : 2;
		unsigned int                         MODE_15 : 2;
		unsigned int                      FREQDIV_15 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_GLB_SCI_STAT_OVRD_REG4__VI {
	struct {
		unsigned int  IGNR_LINKSPEED_CBI_UPDT_L12T15 : 1;
		unsigned int    IGNR_FREQDIV_CBI_UPDT_L12T15 : 1;
		unsigned int   IGNR_DLL_LOCK_CBI_UPDT_L12T15 : 1;
		unsigned int                                 : 9;
		unsigned int                     DLL_LOCK_12 : 1;
		unsigned int                     DLL_LOCK_13 : 1;
		unsigned int                     DLL_LOCK_14 : 1;
		unsigned int                     DLL_LOCK_15 : 1;
		unsigned int                    LINKSPEED_12 : 2;
		unsigned int                      FREQDIV_12 : 2;
		unsigned int                    LINKSPEED_13 : 2;
		unsigned int                      FREQDIV_13 : 2;
		unsigned int                    LINKSPEED_14 : 2;
		unsigned int                      FREQDIV_14 : 2;
		unsigned int                    LINKSPEED_15 : 2;
		unsigned int                      FREQDIV_15 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_HW_DEBUG__CI {
	struct {
		unsigned int                 PB0_HW_00_DEBUG : 1;
		unsigned int                 PB0_HW_01_DEBUG : 1;
		unsigned int                 PB0_HW_02_DEBUG : 1;
		unsigned int                 PB0_HW_03_DEBUG : 1;
		unsigned int                 PB0_HW_04_DEBUG : 1;
		unsigned int                 PB0_HW_05_DEBUG : 1;
		unsigned int                 PB0_HW_06_DEBUG : 1;
		unsigned int                 PB0_HW_07_DEBUG : 1;
		unsigned int                 PB0_HW_08_DEBUG : 1;
		unsigned int                 PB0_HW_09_DEBUG : 1;
		unsigned int                 PB0_HW_10_DEBUG : 1;
		unsigned int                 PB0_HW_11_DEBUG : 1;
		unsigned int                 PB0_HW_12_DEBUG : 1;
		unsigned int                 PB0_HW_13_DEBUG : 1;
		unsigned int                 PB0_HW_14_DEBUG : 1;
		unsigned int                 PB0_HW_15_DEBUG : 1;
		unsigned int                 PB0_HW_16_DEBUG : 1;
		unsigned int                 PB0_HW_17_DEBUG : 1;
		unsigned int                 PB0_HW_18_DEBUG : 1;
		unsigned int                 PB0_HW_19_DEBUG : 1;
		unsigned int                 PB0_HW_20_DEBUG : 1;
		unsigned int                 PB0_HW_21_DEBUG : 1;
		unsigned int                 PB0_HW_22_DEBUG : 1;
		unsigned int                 PB0_HW_23_DEBUG : 1;
		unsigned int                 PB0_HW_24_DEBUG : 1;
		unsigned int                 PB0_HW_25_DEBUG : 1;
		unsigned int                 PB0_HW_26_DEBUG : 1;
		unsigned int                 PB0_HW_27_DEBUG : 1;
		unsigned int                 PB0_HW_28_DEBUG : 1;
		unsigned int                 PB0_HW_29_DEBUG : 1;
		unsigned int                 PB0_HW_30_DEBUG : 1;
		unsigned int                 PB0_HW_31_DEBUG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_HW_DEBUG__VI {
	struct {
		unsigned int                     HW_00_DEBUG : 1;
		unsigned int                     HW_01_DEBUG : 1;
		unsigned int                     HW_02_DEBUG : 1;
		unsigned int                     HW_03_DEBUG : 1;
		unsigned int                     HW_04_DEBUG : 1;
		unsigned int                     HW_05_DEBUG : 1;
		unsigned int                     HW_06_DEBUG : 1;
		unsigned int                     HW_07_DEBUG : 1;
		unsigned int                     HW_08_DEBUG : 1;
		unsigned int                     HW_09_DEBUG : 1;
		unsigned int                     HW_10_DEBUG : 1;
		unsigned int                     HW_11_DEBUG : 1;
		unsigned int                     HW_12_DEBUG : 1;
		unsigned int                     HW_13_DEBUG : 1;
		unsigned int                     HW_14_DEBUG : 1;
		unsigned int                     HW_15_DEBUG : 1;
		unsigned int                     HW_16_DEBUG : 1;
		unsigned int                     HW_17_DEBUG : 1;
		unsigned int                     HW_18_DEBUG : 1;
		unsigned int                     HW_19_DEBUG : 1;
		unsigned int                     HW_20_DEBUG : 1;
		unsigned int                     HW_21_DEBUG : 1;
		unsigned int                     HW_22_DEBUG : 1;
		unsigned int                     HW_23_DEBUG : 1;
		unsigned int                     HW_24_DEBUG : 1;
		unsigned int                     HW_25_DEBUG : 1;
		unsigned int                     HW_26_DEBUG : 1;
		unsigned int                     HW_27_DEBUG : 1;
		unsigned int                     HW_28_DEBUG : 1;
		unsigned int                     HW_29_DEBUG : 1;
		unsigned int                     HW_30_DEBUG : 1;
		unsigned int                     HW_31_DEBUG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_CNTL2__CI {
	struct {
		unsigned int                                 : 1;
		unsigned int             RXDETECT_SAMPL_TIME : 2;
		unsigned int                                 : 4;
		unsigned int            RXDETECT_OVERRIDE_EN : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_0 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_1 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_2 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_3 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_4 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_5 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_6 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_7 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_8 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_9 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_10 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_11 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_12 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_13 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_14 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_15 : 1;
		unsigned int               RXPHYSTATUS_DELAY : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_CNTL__CI {
	struct {
		unsigned int               SERIAL_CFG_ENABLE : 1;
		unsigned int                 DA_FIFO_RESET_0 : 1;
		unsigned int                  PHY_CR_EN_MODE : 1;
		unsigned int               PHYCMD_CR_EN_MODE : 1;
		unsigned int               EI_DET_CYCLE_MODE : 1;
		unsigned int                 DA_FIFO_RESET_1 : 1;
		unsigned int        RXDETECT_FIFO_RESET_MODE : 1;
		unsigned int            RXDETECT_TX_PWR_MODE : 1;
		unsigned int                    DIVINIT_MODE : 1;
		unsigned int                 DA_FIFO_RESET_2 : 1;
		unsigned int              PLL_BINDING_ENABLE : 1;
		unsigned int              SC_CALIB_DONE_CNTL : 1;
		unsigned int                                 : 1;
		unsigned int                 DA_FIFO_RESET_3 : 1;
		unsigned int                                 : 2;
		unsigned int                      TXGND_TIME : 1;
		unsigned int                   LS2_EXIT_TIME : 3;
		unsigned int               EI_CYCLE_OFF_TIME : 3;
		unsigned int               EXIT_L0S_INIT_DIS : 1;
		unsigned int                      RXEN_GATER : 4;
		unsigned int          EXTEND_WAIT_FOR_RAMPUP : 1;
		unsigned int       IGNORE_TxDataValid_EP_DIS : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_HW_DEBUG__CI {
	struct {
		unsigned int             PB0_PIF_HW_00_DEBUG : 1;
		unsigned int             PB0_PIF_HW_01_DEBUG : 1;
		unsigned int             PB0_PIF_HW_02_DEBUG : 1;
		unsigned int             PB0_PIF_HW_03_DEBUG : 1;
		unsigned int             PB0_PIF_HW_04_DEBUG : 1;
		unsigned int             PB0_PIF_HW_05_DEBUG : 1;
		unsigned int             PB0_PIF_HW_06_DEBUG : 1;
		unsigned int             PB0_PIF_HW_07_DEBUG : 1;
		unsigned int             PB0_PIF_HW_08_DEBUG : 1;
		unsigned int             PB0_PIF_HW_09_DEBUG : 1;
		unsigned int             PB0_PIF_HW_10_DEBUG : 1;
		unsigned int             PB0_PIF_HW_11_DEBUG : 1;
		unsigned int             PB0_PIF_HW_12_DEBUG : 1;
		unsigned int             PB0_PIF_HW_13_DEBUG : 1;
		unsigned int             PB0_PIF_HW_14_DEBUG : 1;
		unsigned int             PB0_PIF_HW_15_DEBUG : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_HW_DEBUG__VI {
	struct {
		unsigned int                     HW_00_DEBUG : 1;
		unsigned int                     HW_01_DEBUG : 1;
		unsigned int                     HW_02_DEBUG : 1;
		unsigned int                     HW_03_DEBUG : 1;
		unsigned int                     HW_04_DEBUG : 1;
		unsigned int                     HW_05_DEBUG : 1;
		unsigned int                     HW_06_DEBUG : 1;
		unsigned int                     HW_07_DEBUG : 1;
		unsigned int                     HW_08_DEBUG : 1;
		unsigned int                     HW_09_DEBUG : 1;
		unsigned int                     HW_10_DEBUG : 1;
		unsigned int                     HW_11_DEBUG : 1;
		unsigned int                     HW_12_DEBUG : 1;
		unsigned int                     HW_13_DEBUG : 1;
		unsigned int                     HW_14_DEBUG : 1;
		unsigned int                     HW_15_DEBUG : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PAIRING__CI {
	struct {
		unsigned int                     X2_LANE_1_0 : 1;
		unsigned int                     X2_LANE_3_2 : 1;
		unsigned int                     X2_LANE_5_4 : 1;
		unsigned int                     X2_LANE_7_6 : 1;
		unsigned int                     X2_LANE_9_8 : 1;
		unsigned int                   X2_LANE_11_10 : 1;
		unsigned int                   X2_LANE_13_12 : 1;
		unsigned int                   X2_LANE_15_14 : 1;
		unsigned int                     X4_LANE_3_0 : 1;
		unsigned int                     X4_LANE_7_4 : 1;
		unsigned int                    X4_LANE_11_8 : 1;
		unsigned int                   X4_LANE_15_12 : 1;
		unsigned int                                 : 4;
		unsigned int                     X8_LANE_7_0 : 1;
		unsigned int                    X8_LANE_15_8 : 1;
		unsigned int                                 : 2;
		unsigned int                   X16_LANE_15_0 : 1;
		unsigned int                                 : 4;
		unsigned int                       MULTI_PIF : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_0__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_0 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_0 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_0 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_0 : 3;
		unsigned int              RXEN_OVERRIDE_EN_0 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_0 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_0 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_0 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_0 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_0 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_10__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_10 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_10 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_10 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_10 : 3;
		unsigned int             RXEN_OVERRIDE_EN_10 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_10 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_10 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_10 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_10 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_10 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_11__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_11 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_11 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_11 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_11 : 3;
		unsigned int             RXEN_OVERRIDE_EN_11 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_11 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_11 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_11 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_11 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_11 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_12__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_12 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_12 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_12 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_12 : 3;
		unsigned int             RXEN_OVERRIDE_EN_12 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_12 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_12 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_12 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_12 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_12 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_13__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_13 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_13 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_13 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_13 : 3;
		unsigned int             RXEN_OVERRIDE_EN_13 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_13 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_13 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_13 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_13 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_13 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_14__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_14 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_14 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_14 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_14 : 3;
		unsigned int             RXEN_OVERRIDE_EN_14 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_14 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_14 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_14 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_14 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_14 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_15__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_15 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_15 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_15 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_15 : 3;
		unsigned int             RXEN_OVERRIDE_EN_15 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_15 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_15 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_15 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_15 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_15 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_1__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_1 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_1 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_1 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_1 : 3;
		unsigned int              RXEN_OVERRIDE_EN_1 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_1 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_1 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_1 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_1 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_1 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_2__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_2 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_2 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_2 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_2 : 3;
		unsigned int              RXEN_OVERRIDE_EN_2 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_2 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_2 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_2 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_2 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_2 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_3__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_3 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_3 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_3 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_3 : 3;
		unsigned int              RXEN_OVERRIDE_EN_3 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_3 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_3 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_3 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_3 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_3 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_4__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_4 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_4 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_4 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_4 : 3;
		unsigned int              RXEN_OVERRIDE_EN_4 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_4 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_4 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_4 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_4 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_4 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_5__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_5 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_5 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_5 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_5 : 3;
		unsigned int              RXEN_OVERRIDE_EN_5 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_5 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_5 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_5 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_5 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_5 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_6__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_6 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_6 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_6 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_6 : 3;
		unsigned int              RXEN_OVERRIDE_EN_6 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_6 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_6 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_6 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_6 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_6 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_7__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_7 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_7 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_7 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_7 : 3;
		unsigned int              RXEN_OVERRIDE_EN_7 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_7 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_7 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_7 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_7 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_7 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_8__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_8 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_8 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_8 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_8 : 3;
		unsigned int              RXEN_OVERRIDE_EN_8 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_8 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_8 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_8 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_8 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_8 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PDNB_OVERRIDE_9__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_9 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_9 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_9 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_9 : 3;
		unsigned int              RXEN_OVERRIDE_EN_9 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_9 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_9 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_9 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_9 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_9 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PWRDOWN_0__CI {
	struct {
		unsigned int        TX_POWER_STATE_IN_TXS2_0 : 3;
		unsigned int             FORCE_RXEN_IN_L0s_0 : 1;
		unsigned int        RX_POWER_STATE_IN_RXS2_0 : 3;
		unsigned int       PLL_POWER_STATE_IN_TXS2_0 : 3;
		unsigned int        PLL_POWER_STATE_IN_OFF_0 : 3;
		unsigned int                                 : 3;
		unsigned int      TX2P5CLK_CLOCK_GATING_EN_0 : 1;
		unsigned int                                 : 7;
		unsigned int              PLL_RAMP_UP_TIME_0 : 3;
		unsigned int                                 : 1;
		unsigned int            PLLPWR_OVERRIDE_EN_0 : 1;
		unsigned int           PLLPWR_OVERRIDE_VAL_0 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PWRDOWN_1__CI {
	struct {
		unsigned int        TX_POWER_STATE_IN_TXS2_1 : 3;
		unsigned int             FORCE_RXEN_IN_L0s_1 : 1;
		unsigned int        RX_POWER_STATE_IN_RXS2_1 : 3;
		unsigned int       PLL_POWER_STATE_IN_TXS2_1 : 3;
		unsigned int        PLL_POWER_STATE_IN_OFF_1 : 3;
		unsigned int                                 : 3;
		unsigned int      TX2P5CLK_CLOCK_GATING_EN_1 : 1;
		unsigned int                                 : 7;
		unsigned int              PLL_RAMP_UP_TIME_1 : 3;
		unsigned int                                 : 1;
		unsigned int            PLLPWR_OVERRIDE_EN_1 : 1;
		unsigned int           PLLPWR_OVERRIDE_VAL_1 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PWRDOWN_2__CI {
	struct {
		unsigned int        TX_POWER_STATE_IN_TXS2_2 : 3;
		unsigned int             FORCE_RXEN_IN_L0s_2 : 1;
		unsigned int        RX_POWER_STATE_IN_RXS2_2 : 3;
		unsigned int       PLL_POWER_STATE_IN_TXS2_2 : 3;
		unsigned int        PLL_POWER_STATE_IN_OFF_2 : 3;
		unsigned int                                 : 3;
		unsigned int      TX2P5CLK_CLOCK_GATING_EN_2 : 1;
		unsigned int                                 : 7;
		unsigned int              PLL_RAMP_UP_TIME_2 : 3;
		unsigned int                                 : 1;
		unsigned int            PLLPWR_OVERRIDE_EN_2 : 1;
		unsigned int           PLLPWR_OVERRIDE_VAL_2 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_PWRDOWN_3__CI {
	struct {
		unsigned int        TX_POWER_STATE_IN_TXS2_3 : 3;
		unsigned int             FORCE_RXEN_IN_L0s_3 : 1;
		unsigned int        RX_POWER_STATE_IN_RXS2_3 : 3;
		unsigned int       PLL_POWER_STATE_IN_TXS2_3 : 3;
		unsigned int        PLL_POWER_STATE_IN_OFF_3 : 3;
		unsigned int                                 : 3;
		unsigned int      TX2P5CLK_CLOCK_GATING_EN_3 : 1;
		unsigned int                                 : 7;
		unsigned int              PLL_RAMP_UP_TIME_3 : 3;
		unsigned int                                 : 1;
		unsigned int            PLLPWR_OVERRIDE_EN_3 : 1;
		unsigned int           PLLPWR_OVERRIDE_VAL_3 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SCRATCH__CI__VI {
	struct {
                unsigned int                     PIF_SCRATCH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SC_CTL__CI {
	struct {
		unsigned int                  SC_CALIBRATION : 1;
		unsigned int                     SC_RXDETECT : 1;
		unsigned int               SC_EXIT_L1_TO_L0S : 1;
		unsigned int                SC_EXIT_L1_TO_L0 : 1;
		unsigned int            SC_ENTER_L1_FROM_L0S : 1;
		unsigned int             SC_ENTER_L1_FROM_L0 : 1;
		unsigned int                 SC_SPEED_CHANGE : 1;
		unsigned int                                 : 1;
		unsigned int                      SC_PHASE_1 : 1;
		unsigned int                      SC_PHASE_2 : 1;
		unsigned int                      SC_PHASE_3 : 1;
		unsigned int                      SC_PHASE_4 : 1;
		unsigned int                      SC_PHASE_5 : 1;
		unsigned int                      SC_PHASE_6 : 1;
		unsigned int                      SC_PHASE_7 : 1;
		unsigned int                      SC_PHASE_8 : 1;
		unsigned int                SC_LANE_0_RESUME : 1;
		unsigned int                SC_LANE_1_RESUME : 1;
		unsigned int                SC_LANE_2_RESUME : 1;
		unsigned int                SC_LANE_3_RESUME : 1;
		unsigned int                SC_LANE_4_RESUME : 1;
		unsigned int                SC_LANE_5_RESUME : 1;
		unsigned int                SC_LANE_6_RESUME : 1;
		unsigned int                SC_LANE_7_RESUME : 1;
		unsigned int                SC_LANE_8_RESUME : 1;
		unsigned int                SC_LANE_9_RESUME : 1;
		unsigned int               SC_LANE_10_RESUME : 1;
		unsigned int               SC_LANE_11_RESUME : 1;
		unsigned int               SC_LANE_12_RESUME : 1;
		unsigned int               SC_LANE_13_RESUME : 1;
		unsigned int               SC_LANE_14_RESUME : 1;
		unsigned int               SC_LANE_15_RESUME : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_0__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_0 : 1;
		unsigned int                  SEQ_RXDETECT_0 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_0 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_0 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_0 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_0 : 1;
		unsigned int              SEQ_SPEED_CHANGE_0 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_0 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_10__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_10 : 1;
		unsigned int                 SEQ_RXDETECT_10 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_10 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_10 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_10 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_10 : 1;
		unsigned int             SEQ_SPEED_CHANGE_10 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_10 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_11__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_11 : 1;
		unsigned int                 SEQ_RXDETECT_11 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_11 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_11 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_11 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_11 : 1;
		unsigned int             SEQ_SPEED_CHANGE_11 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_11 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_12__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_12 : 1;
		unsigned int                 SEQ_RXDETECT_12 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_12 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_12 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_12 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_12 : 1;
		unsigned int             SEQ_SPEED_CHANGE_12 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_12 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_13__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_13 : 1;
		unsigned int                 SEQ_RXDETECT_13 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_13 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_13 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_13 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_13 : 1;
		unsigned int             SEQ_SPEED_CHANGE_13 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_13 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_14__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_14 : 1;
		unsigned int                 SEQ_RXDETECT_14 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_14 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_14 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_14 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_14 : 1;
		unsigned int             SEQ_SPEED_CHANGE_14 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_14 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_15__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_15 : 1;
		unsigned int                 SEQ_RXDETECT_15 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_15 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_15 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_15 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_15 : 1;
		unsigned int             SEQ_SPEED_CHANGE_15 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_15 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_1__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_1 : 1;
		unsigned int                  SEQ_RXDETECT_1 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_1 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_1 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_1 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_1 : 1;
		unsigned int              SEQ_SPEED_CHANGE_1 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_1 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_2__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_2 : 1;
		unsigned int                  SEQ_RXDETECT_2 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_2 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_2 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_2 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_2 : 1;
		unsigned int              SEQ_SPEED_CHANGE_2 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_2 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_3__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_3 : 1;
		unsigned int                  SEQ_RXDETECT_3 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_3 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_3 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_3 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_3 : 1;
		unsigned int              SEQ_SPEED_CHANGE_3 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_3 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_4__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_4 : 1;
		unsigned int                  SEQ_RXDETECT_4 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_4 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_4 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_4 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_4 : 1;
		unsigned int              SEQ_SPEED_CHANGE_4 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_4 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_5__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_5 : 1;
		unsigned int                  SEQ_RXDETECT_5 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_5 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_5 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_5 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_5 : 1;
		unsigned int              SEQ_SPEED_CHANGE_5 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_5 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_6__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_6 : 1;
		unsigned int                  SEQ_RXDETECT_6 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_6 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_6 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_6 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_6 : 1;
		unsigned int              SEQ_SPEED_CHANGE_6 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_6 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_7__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_7 : 1;
		unsigned int                  SEQ_RXDETECT_7 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_7 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_7 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_7 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_7 : 1;
		unsigned int              SEQ_SPEED_CHANGE_7 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_7 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_8__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_8 : 1;
		unsigned int                  SEQ_RXDETECT_8 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_8 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_8 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_8 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_8 : 1;
		unsigned int              SEQ_SPEED_CHANGE_8 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_8 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_SEQ_STATUS_9__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_9 : 1;
		unsigned int                  SEQ_RXDETECT_9 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_9 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_9 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_9 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_9 : 1;
		unsigned int              SEQ_SPEED_CHANGE_9 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_9 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_TXPHYSTATUS__CI {
	struct {
		unsigned int                   TXPHYSTATUS_0 : 1;
		unsigned int                   TXPHYSTATUS_1 : 1;
		unsigned int                   TXPHYSTATUS_2 : 1;
		unsigned int                   TXPHYSTATUS_3 : 1;
		unsigned int                   TXPHYSTATUS_4 : 1;
		unsigned int                   TXPHYSTATUS_5 : 1;
		unsigned int                   TXPHYSTATUS_6 : 1;
		unsigned int                   TXPHYSTATUS_7 : 1;
		unsigned int                   TXPHYSTATUS_8 : 1;
		unsigned int                   TXPHYSTATUS_9 : 1;
		unsigned int                  TXPHYSTATUS_10 : 1;
		unsigned int                  TXPHYSTATUS_11 : 1;
		unsigned int                  TXPHYSTATUS_12 : 1;
		unsigned int                  TXPHYSTATUS_13 : 1;
		unsigned int                  TXPHYSTATUS_14 : 1;
		unsigned int                  TXPHYSTATUS_15 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC0_CTRL_REG0__CI__VI {
	struct {
                unsigned int         PLL_DBG_LC_ANALOG_SEL_0 : 2;
                unsigned int       PLL_DBG_LC_EXT_RESET_EN_0 : 1;
                unsigned int        PLL_DBG_LC_VCTL_ADC_EN_0 : 1;
                unsigned int         PLL_TST_LC_USAMPLE_EN_0 : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC0_OVRD_REG0__CI__VI {
	struct {
                unsigned int  PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 : 3;
                unsigned int   PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 : 1;
                unsigned int PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0 : 3;
                unsigned int PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 : 1;
                unsigned int PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 : 1;
                unsigned int PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 : 1;
                unsigned int     PLL_CFG_LC_FBDIV_OVRD_VAL_0 : 8;
                unsigned int      PLL_CFG_LC_FBDIV_OVRD_EN_0 : 1;
                unsigned int  PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 : 9;
                unsigned int   PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 : 1;
                unsigned int    PLL_CFG_LC_REFDIV_OVRD_VAL_0 : 2;
                unsigned int     PLL_CFG_LC_REFDIV_OVRD_EN_0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC0_OVRD_REG1__CI__VI {
	struct {
                unsigned int PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0 : 3;
                unsigned int PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 : 1;
                unsigned int PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 : 1;
                unsigned int  PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 : 1;
                unsigned int PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0 : 1;
                unsigned int PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 : 1;
                unsigned int         PLL_LC_PWRON_OVRD_VAL_0 : 1;
                unsigned int          PLL_LC_PWRON_OVRD_EN_0 : 1;
                unsigned int                                 : 4;
                unsigned int  PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 : 4;
                unsigned int   PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC0_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_LC0_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_LC0_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_LC0_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_LC0_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC0_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_LC0_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                  PLL_LC0_PLLPWR : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC1_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_LC1_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_LC1_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_LC1_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_LC1_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC1_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_LC1_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                  PLL_LC1_PLLPWR : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC2_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_LC2_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_LC2_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_LC2_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_LC2_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC2_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_LC2_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                  PLL_LC2_PLLPWR : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC3_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_LC3_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_LC3_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_LC3_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_LC3_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_LC3_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_LC3_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                  PLL_LC3_PLLPWR : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO0_CTRL_REG0__CI__VI {
	struct {
                unsigned int         PLL_DBG_RO_ANALOG_SEL_0 : 2;
                unsigned int       PLL_DBG_RO_EXT_RESET_EN_0 : 1;
                unsigned int        PLL_DBG_RO_VCTL_ADC_EN_0 : 1;
                unsigned int           PLL_DBG_RO_LF_CNTRL_0 : 7;
                unsigned int         PLL_TST_RO_USAMPLE_EN_0 : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO0_OVRD_REG0__CI__VI {
	struct {
                unsigned int  PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 : 8;
                unsigned int   PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 : 1;
                unsigned int PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 : 3;
                unsigned int PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 : 1;
                unsigned int PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 : 1;
                unsigned int PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 : 1;
                unsigned int     PLL_CFG_RO_FBDIV_OVRD_VAL_0 : 13;
                unsigned int      PLL_CFG_RO_FBDIV_OVRD_EN_0 : 1;
                unsigned int                                 : 1;
                unsigned int PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0 : 1;
                unsigned int PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO0_OVRD_REG1__CI__VI {
	struct {
                unsigned int    PLL_CFG_RO_REFDIV_OVRD_VAL_0 : 5;
                unsigned int     PLL_CFG_RO_REFDIV_OVRD_EN_0 : 1;
                unsigned int  PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 : 2;
                unsigned int   PLL_CFG_RO_VCO_MODE_OVRD_EN_0 : 1;
                unsigned int PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 : 1;
                unsigned int  PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 : 1;
                unsigned int PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0 : 1;
                unsigned int PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 : 1;
                unsigned int         PLL_RO_PWRON_OVRD_VAL_0 : 1;
                unsigned int          PLL_RO_PWRON_OVRD_EN_0 : 1;
                unsigned int                                 : 4;
                unsigned int PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0 : 3;
                unsigned int PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 : 1;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO0_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_RO0_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_RO0_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO0_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_RO0_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO0_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_RO0_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int   PLL_RO0_IGNR_PLLFREQ_CBI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO0_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                 PLL_RO0_PLLFREQ : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO1_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_RO1_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_RO1_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO1_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_RO1_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO1_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_RO1_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int   PLL_RO1_IGNR_PLLFREQ_CBI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO1_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                 PLL_RO1_PLLFREQ : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO2_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_RO2_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_RO2_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO2_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_RO2_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO2_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_RO2_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int   PLL_RO2_IGNR_PLLFREQ_CBI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO2_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                 PLL_RO2_PLLFREQ : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO3_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_RO3_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_RO3_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO3_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_RO3_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO3_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_RO3_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int   PLL_RO3_IGNR_PLLFREQ_CBI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO3_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                 PLL_RO3_PLLFREQ : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO_GLB_CTRL_REG0__CI {
	struct {
		unsigned int            PLL_TST_LOSPDTST_SRC : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int      PLL_RO_PWRON_LUT_ENTRY_LS2 : 1;
		unsigned int      PLL_LC_PWRON_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int                                 : 1;
		unsigned int PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN : 1;
		unsigned int PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PLL_RO_GLB_CTRL_REG0__VI {
	struct {
		unsigned int            PLL_TST_LOSPDTST_SRC : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int      PLL_RO_PWRON_LUT_ENTRY_LS2 : 1;
		unsigned int      PLL_LC_PWRON_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int  PLL_RO_HSCLK_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_GATING_EN : 1;
		unsigned int  PLL_LC_HSCLK_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_GATING_EN : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_CTRL_REG0__CI__VI {
	struct {
                unsigned int          RX_CFG_ADAPT_MODE_GEN1 : 10;
                unsigned int          RX_CFG_ADAPT_MODE_GEN2 : 10;
                unsigned int          RX_CFG_ADAPT_MODE_GEN3 : 10;
                unsigned int           RX_CFG_ADAPT_RST_MODE : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_CTRL_REG1__CI__VI {
	struct {
                unsigned int         RX_CFG_CDR_FR_GAIN_GEN1 : 4;
                unsigned int         RX_CFG_CDR_FR_GAIN_GEN2 : 4;
                unsigned int         RX_CFG_CDR_FR_GAIN_GEN3 : 4;
                unsigned int         RX_CFG_CDR_PH_GAIN_GEN1 : 4;
                unsigned int         RX_CFG_CDR_PH_GAIN_GEN2 : 4;
                unsigned int         RX_CFG_CDR_PH_GAIN_GEN3 : 4;
                unsigned int        RX_CFG_CDR_PI_STPSZ_GEN1 : 1;
                unsigned int        RX_CFG_CDR_PI_STPSZ_GEN2 : 1;
                unsigned int        RX_CFG_CDR_PI_STPSZ_GEN3 : 1;
                unsigned int   RX_CFG_LEQ_DCATTN_BYP_EN_GEN1 : 1;
                unsigned int   RX_CFG_LEQ_DCATTN_BYP_EN_GEN2 : 1;
                unsigned int   RX_CFG_LEQ_DCATTN_BYP_EN_GEN3 : 1;
                unsigned int    RX_ADAPT_HLD_ASRT_TO_DCLK_EN : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_CTRL_REG2__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int            RX_CFG_CDR_TIME_GEN1 : 4;
                unsigned int            RX_CFG_CDR_TIME_GEN2 : 4;
                unsigned int            RX_CFG_CDR_TIME_GEN3 : 4;
                unsigned int       RX_CFG_LEQ_LOOP_GAIN_GEN1 : 2;
                unsigned int       RX_CFG_LEQ_LOOP_GAIN_GEN2 : 2;
                unsigned int       RX_CFG_LEQ_LOOP_GAIN_GEN3 : 2;
                unsigned int    RX_DCLK_EN_ASRT_TO_ADAPT_HLD : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_CTRL_REG3__CI__VI {
	struct {
                unsigned int           RX_CFG_CDR_FR_EN_GEN1 : 1;
                unsigned int           RX_CFG_CDR_FR_EN_GEN2 : 1;
                unsigned int           RX_CFG_CDR_FR_EN_GEN3 : 1;
                unsigned int      RX_ADAPT_RST_MODE_GEN1__VI : 2;
                unsigned int      RX_ADAPT_RST_MODE_GEN2__VI : 2;
                unsigned int      RX_ADAPT_RST_MODE_GEN3__VI : 2;
                unsigned int       RX_ADAPT_RST_SUB_MODE__VI : 3;
                unsigned int       RX_L0_ENTRY_MODE_GEN1__VI : 2;
                unsigned int       RX_L0_ENTRY_MODE_GEN2__VI : 2;
                unsigned int       RX_L0_ENTRY_MODE_GEN3__VI : 2;
                unsigned int                                 : 2;
                unsigned int            RX_CFG_DFE_TIME_GEN1 : 4;
                unsigned int            RX_CFG_DFE_TIME_GEN2 : 4;
                unsigned int            RX_CFG_DFE_TIME_GEN3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_CTRL_REG4__CI__VI {
	struct {
                unsigned int             RX_CFG_FOM_BER_GEN1 : 3;
                unsigned int             RX_CFG_FOM_BER_GEN2 : 3;
                unsigned int             RX_CFG_FOM_BER_GEN3 : 3;
                unsigned int    RX_CFG_LEQ_POLE_BYP_VAL_GEN1 : 3;
                unsigned int    RX_CFG_LEQ_POLE_BYP_VAL_GEN2 : 3;
                unsigned int    RX_CFG_LEQ_POLE_BYP_VAL_GEN3 : 3;
                unsigned int                                 : 2;
                unsigned int            RX_CFG_FOM_TIME_GEN1 : 4;
                unsigned int            RX_CFG_FOM_TIME_GEN2 : 4;
                unsigned int            RX_CFG_FOM_TIME_GEN3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_CTRL_REG5__CI__VI {
	struct {
                unsigned int  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 : 5;
                unsigned int  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 : 5;
                unsigned int  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 : 5;
                unsigned int     RX_CFG_LEQ_POLE_BYP_EN_GEN1 : 1;
                unsigned int     RX_CFG_LEQ_POLE_BYP_EN_GEN2 : 1;
                unsigned int     RX_CFG_LEQ_POLE_BYP_EN_GEN3 : 1;
                unsigned int        RX_CFG_LEQ_SHUNT_EN_GEN1 : 1;
                unsigned int        RX_CFG_LEQ_SHUNT_EN_GEN2 : 1;
                unsigned int        RX_CFG_LEQ_SHUNT_EN_GEN3 : 1;
                unsigned int                                 : 6;
                unsigned int           RX_CFG_TERM_MODE_GEN1 : 1;
                unsigned int           RX_CFG_TERM_MODE_GEN2 : 1;
                unsigned int           RX_CFG_TERM_MODE_GEN3 : 1;
                unsigned int RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0 : 1;
                unsigned int     RX_ADAPT_AUX_PWRON_MODE__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_CTRL_REG6__CI__VI {
	struct {
                unsigned int            RX_CFG_LEQ_TIME_GEN1 : 4;
                unsigned int            RX_CFG_LEQ_TIME_GEN2 : 4;
                unsigned int            RX_CFG_LEQ_TIME_GEN3 : 4;
                unsigned int             RX_CFG_OC_TIME_GEN1 : 4;
                unsigned int             RX_CFG_OC_TIME_GEN2 : 4;
                unsigned int             RX_CFG_OC_TIME_GEN3 : 4;
                unsigned int RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0 : 1;
                unsigned int                                 : 1;
                unsigned int RX_FRONTEND_PWRON_LUT_ENTRY_LS2 : 1;
                unsigned int      RX_AUX_PWRON_LUT_ENTRY_LS2 : 1;
                unsigned int RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__VI : 1;
                unsigned int     RX_ADAPT_HLD_L1_DLL_OFF__VI : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_CTRL_REG7__CI {
	struct {
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN1 : 4;
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN2 : 4;
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN3 : 4;
		unsigned int RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 : 1;
		unsigned int        RX_DCLK_EN_LUT_ENTRY_LS2 : 1;
		unsigned int                                 : 3;
		unsigned int      RX_DLL_PWRON_LUT_ENTRY_LS2 : 1;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN1 : 3;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN2 : 3;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN3 : 3;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN1 : 1;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN2 : 1;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN3 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_CTRL_REG7__VI {
	struct {
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN1 : 4;
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN2 : 4;
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN3 : 4;
		unsigned int RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 : 1;
		unsigned int        RX_DCLK_EN_LUT_ENTRY_LS2 : 1;
		unsigned int       RX_DCLK_EN_AFTER_DLL_LOCK : 1;
		unsigned int                                 : 1;
		unsigned int      RX_DLL_PWRON_LUT_ENTRY_PS3 : 1;
		unsigned int      RX_DLL_PWRON_LUT_ENTRY_PS2 : 1;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN1 : 3;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN2 : 3;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN3 : 3;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN1 : 1;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN2 : 1;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN3 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_CTRL_REG8__CI__VI {
	struct {
                unsigned int            RX_DLL_LOCK_TIME__VI : 2;
                unsigned int RX_DLL_SPEEDCHANGE_RESET_TIME__VI : 2;
                unsigned int    RX_DLL_PWRON_IN_RAMPDOWN__VI : 1;
                unsigned int        RX_FSM_L0S_IF_RX_RDY__VI : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_OVRD_REG0__CI__VI {
	struct {
                unsigned int           RX_ADAPT_HLD_OVRD_VAL : 1;
                unsigned int            RX_ADAPT_HLD_OVRD_EN : 1;
                unsigned int           RX_ADAPT_RST_OVRD_VAL : 1;
                unsigned int            RX_ADAPT_RST_OVRD_EN : 1;
                unsigned int                                 : 2;
                unsigned int        RX_CFG_DCLK_DIV_OVRD_VAL : 2;
                unsigned int         RX_CFG_DCLK_DIV_OVRD_EN : 1;
                unsigned int   RX_CFG_DLL_FREQ_MODE_OVRD_VAL : 1;
                unsigned int    RX_CFG_DLL_FREQ_MODE_OVRD_EN : 1;
                unsigned int      RX_CFG_PLLCLK_SEL_OVRD_VAL : 1;
                unsigned int       RX_CFG_PLLCLK_SEL_OVRD_EN : 1;
                unsigned int        RX_CFG_RCLK_DIV_OVRD_VAL : 1;
                unsigned int         RX_CFG_RCLK_DIV_OVRD_EN : 1;
                unsigned int             RX_DCLK_EN_OVRD_VAL : 1;
                unsigned int              RX_DCLK_EN_OVRD_EN : 1;
                unsigned int           RX_DLL_PWRON_OVRD_VAL : 1;
                unsigned int            RX_DLL_PWRON_OVRD_EN : 1;
                unsigned int      RX_FRONTEND_PWRON_OVRD_VAL : 1;
                unsigned int       RX_FRONTEND_PWRON_OVRD_EN : 1;
                unsigned int       RX_IDLEDET_PWRON_OVRD_VAL : 1;
                unsigned int        RX_IDLEDET_PWRON_OVRD_EN : 1;
                unsigned int             RX_TERM_EN_OVRD_VAL : 1;
                unsigned int              RX_TERM_EN_OVRD_EN : 1;
                unsigned int                                 : 3;
                unsigned int           RX_AUX_PWRON_OVRD_VAL : 1;
                unsigned int            RX_AUX_PWRON_OVRD_EN : 1;
                unsigned int           RX_ADAPT_FOM_OVRD_VAL : 1;
                unsigned int            RX_ADAPT_FOM_OVRD_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_OVRD_REG1__CI__VI {
	struct {
                unsigned int           RX_ADAPT_TRK_OVRD_VAL : 1;
                unsigned int            RX_ADAPT_TRK_OVRD_EN : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int        IGNR_RXPWR_SCI_UPDT_L0T3 : 1;
		unsigned int        IGNR_RXPWR_SCI_UPDT_L4T7 : 1;
		unsigned int       IGNR_RXPWR_SCI_UPDT_L8T11 : 1;
		unsigned int      IGNR_RXPWR_SCI_UPDT_L12T15 : 1;
		unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3 : 1;
		unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15 : 1;
		unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L0T3 : 1;
		unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L12T15 : 1;
		unsigned int    IGNR_ENABLEFOM_SCI_UPDT_L0T3 : 1;
		unsigned int    IGNR_ENABLEFOM_SCI_UPDT_L4T7 : 1;
		unsigned int   IGNR_ENABLEFOM_SCI_UPDT_L8T11 : 1;
		unsigned int  IGNR_ENABLEFOM_SCI_UPDT_L12T15 : 1;
		unsigned int   IGNR_REQUESTFOM_SCI_UPDT_L0T3 : 1;
		unsigned int   IGNR_REQUESTFOM_SCI_UPDT_L4T7 : 1;
		unsigned int  IGNR_REQUESTFOM_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_REQUESTFOM_SCI_UPDT_L12T15 : 1;
		unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L0T3 : 1;
		unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L12T15 : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_GLB_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int        IGNR_RXPWR_CBI_UPDT_L0T3 : 1;
		unsigned int        IGNR_RXPWR_CBI_UPDT_L4T7 : 1;
		unsigned int       IGNR_RXPWR_CBI_UPDT_L8T11 : 1;
		unsigned int      IGNR_RXPWR_CBI_UPDT_L12T15 : 1;
		unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3 : 1;
		unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7 : 1;
		unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15 : 1;
		unsigned int   IGNR_REQUESTTRK_CBI_UPDT_L0T3 : 1;
		unsigned int   IGNR_REQUESTTRK_CBI_UPDT_L4T7 : 1;
		unsigned int  IGNR_REQUESTTRK_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_REQUESTTRK_CBI_UPDT_L12T15 : 1;
		unsigned int    IGNR_ENABLEFOM_CBI_UPDT_L0T3 : 1;
		unsigned int    IGNR_ENABLEFOM_CBI_UPDT_L4T7 : 1;
		unsigned int   IGNR_ENABLEFOM_CBI_UPDT_L8T11 : 1;
		unsigned int  IGNR_ENABLEFOM_CBI_UPDT_L12T15 : 1;
		unsigned int   IGNR_REQUESTFOM_CBI_UPDT_L0T3 : 1;
		unsigned int   IGNR_REQUESTFOM_CBI_UPDT_L4T7 : 1;
		unsigned int  IGNR_REQUESTFOM_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_REQUESTFOM_CBI_UPDT_L12T15 : 1;
		unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L0T3 : 1;
		unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L4T7 : 1;
		unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L12T15 : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE0_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_0 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_0 : 2;
                unsigned int               RX_TST_BSCAN_EN_0 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_0 : 1;
                unsigned int                RX_TERM_EN_0__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE0_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_0 : 3;
		unsigned int                 ELECIDLEDETEN_0 : 1;
		unsigned int                  RXPRESETHINT_0 : 3;
		unsigned int                     ENABLEFOM_0 : 1;
		unsigned int                    REQUESTFOM_0 : 1;
		unsigned int                  RESPONSEMODE_0 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE0_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_0 : 3;
		unsigned int                 ELECIDLEDETEN_0 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_0 : 1;
		unsigned int                     ENABLEFOM_0 : 1;
		unsigned int                    REQUESTFOM_0 : 1;
		unsigned int                  RESPONSEMODE_0 : 1;
		unsigned int                      RXEYEFOM_0 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE10_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_10 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_10 : 2;
                unsigned int              RX_TST_BSCAN_EN_10 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_10 : 1;
                unsigned int               RX_TERM_EN_10__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE10_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_10 : 3;
		unsigned int                ELECIDLEDETEN_10 : 1;
		unsigned int                 RXPRESETHINT_10 : 3;
		unsigned int                    ENABLEFOM_10 : 1;
		unsigned int                   REQUESTFOM_10 : 1;
		unsigned int                 RESPONSEMODE_10 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE10_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_10 : 3;
		unsigned int                ELECIDLEDETEN_10 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_10 : 1;
		unsigned int                    ENABLEFOM_10 : 1;
		unsigned int                   REQUESTFOM_10 : 1;
		unsigned int                 RESPONSEMODE_10 : 1;
		unsigned int                     RXEYEFOM_10 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE11_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_11 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_11 : 2;
                unsigned int              RX_TST_BSCAN_EN_11 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_11 : 1;
                unsigned int               RX_TERM_EN_11__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE11_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_11 : 3;
		unsigned int                ELECIDLEDETEN_11 : 1;
		unsigned int                 RXPRESETHINT_11 : 3;
		unsigned int                    ENABLEFOM_11 : 1;
		unsigned int                   REQUESTFOM_11 : 1;
		unsigned int                 RESPONSEMODE_11 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE11_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_11 : 3;
		unsigned int                ELECIDLEDETEN_11 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_11 : 1;
		unsigned int                    ENABLEFOM_11 : 1;
		unsigned int                   REQUESTFOM_11 : 1;
		unsigned int                 RESPONSEMODE_11 : 1;
		unsigned int                     RXEYEFOM_11 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE12_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_12 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_12 : 2;
                unsigned int              RX_TST_BSCAN_EN_12 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_12 : 1;
                unsigned int               RX_TERM_EN_12__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE12_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_12 : 3;
		unsigned int                ELECIDLEDETEN_12 : 1;
		unsigned int                 RXPRESETHINT_12 : 3;
		unsigned int                    ENABLEFOM_12 : 1;
		unsigned int                   REQUESTFOM_12 : 1;
		unsigned int                 RESPONSEMODE_12 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE12_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_12 : 3;
		unsigned int                ELECIDLEDETEN_12 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_12 : 1;
		unsigned int                    ENABLEFOM_12 : 1;
		unsigned int                   REQUESTFOM_12 : 1;
		unsigned int                 RESPONSEMODE_12 : 1;
		unsigned int                     RXEYEFOM_12 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE13_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_13 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_13 : 2;
                unsigned int              RX_TST_BSCAN_EN_13 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_13 : 1;
                unsigned int               RX_TERM_EN_13__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE13_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_13 : 3;
		unsigned int                ELECIDLEDETEN_13 : 1;
		unsigned int                 RXPRESETHINT_13 : 3;
		unsigned int                    ENABLEFOM_13 : 1;
		unsigned int                   REQUESTFOM_13 : 1;
		unsigned int                 RESPONSEMODE_13 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE13_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_13 : 3;
		unsigned int                ELECIDLEDETEN_13 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_13 : 1;
		unsigned int                    ENABLEFOM_13 : 1;
		unsigned int                   REQUESTFOM_13 : 1;
		unsigned int                 RESPONSEMODE_13 : 1;
		unsigned int                     RXEYEFOM_13 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE14_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_14 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_14 : 2;
                unsigned int              RX_TST_BSCAN_EN_14 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_14 : 1;
                unsigned int               RX_TERM_EN_14__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE14_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_14 : 3;
		unsigned int                ELECIDLEDETEN_14 : 1;
		unsigned int                 RXPRESETHINT_14 : 3;
		unsigned int                    ENABLEFOM_14 : 1;
		unsigned int                   REQUESTFOM_14 : 1;
		unsigned int                 RESPONSEMODE_14 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE14_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_14 : 3;
		unsigned int                ELECIDLEDETEN_14 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_14 : 1;
		unsigned int                    ENABLEFOM_14 : 1;
		unsigned int                   REQUESTFOM_14 : 1;
		unsigned int                 RESPONSEMODE_14 : 1;
		unsigned int                     RXEYEFOM_14 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE15_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_15 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_15 : 2;
                unsigned int              RX_TST_BSCAN_EN_15 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_15 : 1;
                unsigned int               RX_TERM_EN_15__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE15_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_15 : 3;
		unsigned int                ELECIDLEDETEN_15 : 1;
		unsigned int                 RXPRESETHINT_15 : 3;
		unsigned int                    ENABLEFOM_15 : 1;
		unsigned int                   REQUESTFOM_15 : 1;
		unsigned int                 RESPONSEMODE_15 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE15_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_15 : 3;
		unsigned int                ELECIDLEDETEN_15 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_15 : 1;
		unsigned int                    ENABLEFOM_15 : 1;
		unsigned int                   REQUESTFOM_15 : 1;
		unsigned int                 RESPONSEMODE_15 : 1;
		unsigned int                     RXEYEFOM_15 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE1_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_1 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_1 : 2;
                unsigned int               RX_TST_BSCAN_EN_1 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_1 : 1;
                unsigned int                RX_TERM_EN_1__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE1_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_1 : 3;
		unsigned int                 ELECIDLEDETEN_1 : 1;
		unsigned int                  RXPRESETHINT_1 : 3;
		unsigned int                     ENABLEFOM_1 : 1;
		unsigned int                    REQUESTFOM_1 : 1;
		unsigned int                  RESPONSEMODE_1 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE1_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_1 : 3;
		unsigned int                 ELECIDLEDETEN_1 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_1 : 1;
		unsigned int                     ENABLEFOM_1 : 1;
		unsigned int                    REQUESTFOM_1 : 1;
		unsigned int                  RESPONSEMODE_1 : 1;
		unsigned int                      RXEYEFOM_1 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE2_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_2 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_2 : 2;
                unsigned int               RX_TST_BSCAN_EN_2 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_2 : 1;
                unsigned int                RX_TERM_EN_2__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE2_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_2 : 3;
		unsigned int                 ELECIDLEDETEN_2 : 1;
		unsigned int                  RXPRESETHINT_2 : 3;
		unsigned int                     ENABLEFOM_2 : 1;
		unsigned int                    REQUESTFOM_2 : 1;
		unsigned int                  RESPONSEMODE_2 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE2_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_2 : 3;
		unsigned int                 ELECIDLEDETEN_2 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_2 : 1;
		unsigned int                     ENABLEFOM_2 : 1;
		unsigned int                    REQUESTFOM_2 : 1;
		unsigned int                  RESPONSEMODE_2 : 1;
		unsigned int                      RXEYEFOM_2 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE3_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_3 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_3 : 2;
                unsigned int               RX_TST_BSCAN_EN_3 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_3 : 1;
                unsigned int                RX_TERM_EN_3__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE3_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_3 : 3;
		unsigned int                 ELECIDLEDETEN_3 : 1;
		unsigned int                  RXPRESETHINT_3 : 3;
		unsigned int                     ENABLEFOM_3 : 1;
		unsigned int                    REQUESTFOM_3 : 1;
		unsigned int                  RESPONSEMODE_3 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE3_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_3 : 3;
		unsigned int                 ELECIDLEDETEN_3 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_3 : 1;
		unsigned int                     ENABLEFOM_3 : 1;
		unsigned int                    REQUESTFOM_3 : 1;
		unsigned int                  RESPONSEMODE_3 : 1;
		unsigned int                      RXEYEFOM_3 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE4_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_4 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_4 : 2;
                unsigned int               RX_TST_BSCAN_EN_4 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_4 : 1;
                unsigned int                RX_TERM_EN_4__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE4_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_4 : 3;
		unsigned int                 ELECIDLEDETEN_4 : 1;
		unsigned int                  RXPRESETHINT_4 : 3;
		unsigned int                     ENABLEFOM_4 : 1;
		unsigned int                    REQUESTFOM_4 : 1;
		unsigned int                  RESPONSEMODE_4 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE4_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_4 : 3;
		unsigned int                 ELECIDLEDETEN_4 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_4 : 1;
		unsigned int                     ENABLEFOM_4 : 1;
		unsigned int                    REQUESTFOM_4 : 1;
		unsigned int                  RESPONSEMODE_4 : 1;
		unsigned int                      RXEYEFOM_4 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE5_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_5 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_5 : 2;
                unsigned int               RX_TST_BSCAN_EN_5 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_5 : 1;
                unsigned int                RX_TERM_EN_5__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE5_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_5 : 3;
		unsigned int                 ELECIDLEDETEN_5 : 1;
		unsigned int                  RXPRESETHINT_5 : 3;
		unsigned int                     ENABLEFOM_5 : 1;
		unsigned int                    REQUESTFOM_5 : 1;
		unsigned int                  RESPONSEMODE_5 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE5_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_5 : 3;
		unsigned int                 ELECIDLEDETEN_5 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_5 : 1;
		unsigned int                     ENABLEFOM_5 : 1;
		unsigned int                    REQUESTFOM_5 : 1;
		unsigned int                  RESPONSEMODE_5 : 1;
		unsigned int                      RXEYEFOM_5 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE6_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_6 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_6 : 2;
                unsigned int               RX_TST_BSCAN_EN_6 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_6 : 1;
                unsigned int                RX_TERM_EN_6__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE6_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_6 : 3;
		unsigned int                 ELECIDLEDETEN_6 : 1;
		unsigned int                  RXPRESETHINT_6 : 3;
		unsigned int                     ENABLEFOM_6 : 1;
		unsigned int                    REQUESTFOM_6 : 1;
		unsigned int                  RESPONSEMODE_6 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE6_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_6 : 3;
		unsigned int                 ELECIDLEDETEN_6 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_6 : 1;
		unsigned int                     ENABLEFOM_6 : 1;
		unsigned int                    REQUESTFOM_6 : 1;
		unsigned int                  RESPONSEMODE_6 : 1;
		unsigned int                      RXEYEFOM_6 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE7_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_7 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_7 : 2;
                unsigned int               RX_TST_BSCAN_EN_7 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_7 : 1;
                unsigned int                RX_TERM_EN_7__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE7_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_7 : 3;
		unsigned int                 ELECIDLEDETEN_7 : 1;
		unsigned int                  RXPRESETHINT_7 : 3;
		unsigned int                     ENABLEFOM_7 : 1;
		unsigned int                    REQUESTFOM_7 : 1;
		unsigned int                  RESPONSEMODE_7 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE7_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_7 : 3;
		unsigned int                 ELECIDLEDETEN_7 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_7 : 1;
		unsigned int                     ENABLEFOM_7 : 1;
		unsigned int                    REQUESTFOM_7 : 1;
		unsigned int                  RESPONSEMODE_7 : 1;
		unsigned int                      RXEYEFOM_7 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE8_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_8 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_8 : 2;
                unsigned int               RX_TST_BSCAN_EN_8 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_8 : 1;
                unsigned int                RX_TERM_EN_8__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE8_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_8 : 3;
		unsigned int                 ELECIDLEDETEN_8 : 1;
		unsigned int                  RXPRESETHINT_8 : 3;
		unsigned int                     ENABLEFOM_8 : 1;
		unsigned int                    REQUESTFOM_8 : 1;
		unsigned int                  RESPONSEMODE_8 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE8_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_8 : 3;
		unsigned int                 ELECIDLEDETEN_8 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_8 : 1;
		unsigned int                     ENABLEFOM_8 : 1;
		unsigned int                    REQUESTFOM_8 : 1;
		unsigned int                  RESPONSEMODE_8 : 1;
		unsigned int                      RXEYEFOM_8 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE9_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_9 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_9 : 2;
                unsigned int               RX_TST_BSCAN_EN_9 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_9 : 1;
                unsigned int                RX_TERM_EN_9__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE9_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_9 : 3;
		unsigned int                 ELECIDLEDETEN_9 : 1;
		unsigned int                  RXPRESETHINT_9 : 3;
		unsigned int                     ENABLEFOM_9 : 1;
		unsigned int                    REQUESTFOM_9 : 1;
		unsigned int                  RESPONSEMODE_9 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_RX_LANE9_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_9 : 3;
		unsigned int                 ELECIDLEDETEN_9 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_9 : 1;
		unsigned int                     ENABLEFOM_9 : 1;
		unsigned int                    REQUESTFOM_9 : 1;
		unsigned int                  RESPONSEMODE_9 : 1;
		unsigned int                      RXEYEFOM_9 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_STRAP_GLB_REG0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int           STRAP_QUICK_SIM_START : 1;
                unsigned int        STRAP_DFT_RXBSCAN_EN_VAL : 1;
                unsigned int          STRAP_DFT_CALIB_BYPASS : 1;
                unsigned int       STRAP_FORCE_LC_PLL_ON__VI : 1;
                unsigned int            STRAP_CFG_IDLEDET_TH : 2;
                unsigned int STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL : 5;
                unsigned int          STRAP_RX_CFG_OVR_PWRSF : 1;
                unsigned int            STRAP_RX_TRK_MODE_0_ : 1;
                unsigned int              STRAP_PWRGOOD_OVRD : 1;
                unsigned int    STRAP_DBG_RXDLL_VREG_REF_SEL : 1;
                unsigned int       STRAP_PLL_CFG_LC_VCO_TUNE : 4;
                unsigned int STRAP_DBG_RXRDATA_GATING_DISABLE : 1;
                unsigned int   STRAP_DBG_RXPI_OFFSET_BYP_VAL : 4;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_STRAP_PIN_REG0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int              STRAP_TX_DEEMPH_EN : 1;
                unsigned int             STRAP_TX_FULL_SWING : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_STRAP_PLL_REG0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int       STRAP_PLL_CFG_LC_BW_CNTRL : 3;
                unsigned int       STRAP_PLL_CFG_LC_LF_CNTRL : 9;
                unsigned int           STRAP_TX_RXDET_X1_SSF : 1;
                unsigned int                                 : 1;
                unsigned int STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS : 1;
                unsigned int       STRAP_PLL_CFG_RO_BW_CNTRL : 8;
                unsigned int             STRAP_PLL_STRAP_SEL : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_STRAP_RX_REG0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int       STRAP_RX_CFG_TH_LOOP_GAIN : 4;
                unsigned int  STRAP_RX_CFG_DLL_FLOCK_DISABLE : 1;
                unsigned int    STRAP_DBG_RXPI_OFFSET_BYP_EN : 1;
                unsigned int STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS : 1;
                unsigned int   STRAP_BG_CFG_LC_REG_VREF0_SEL : 2;
                unsigned int   STRAP_BG_CFG_LC_REG_VREF1_SEL : 2;
                unsigned int           STRAP_RX_CFG_CDR_TIME : 4;
                unsigned int           STRAP_RX_CFG_FOM_TIME : 4;
                unsigned int           STRAP_RX_CFG_LEQ_TIME : 4;
                unsigned int            STRAP_RX_CFG_OC_TIME : 4;
                unsigned int       STRAP_TX_CFG_RPTR_RST_VAL : 3;
                unsigned int          STRAP_RX_CFG_TERM_MODE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_STRAP_RX_REG1__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int       STRAP_RX_CFG_CDR_PI_STPSZ : 1;
                unsigned int      STRAP_TX_DEEMPH_PRSHT_STNG : 3;
                unsigned int    STRAP_BG_CFG_RO_REG_VREF_SEL : 2;
                unsigned int   STRAP_RX_CFG_LEQ_POLE_BYP_DIS : 1;
                unsigned int   STRAP_RX_CFG_LEQ_POLE_BYP_VAL : 3;
                unsigned int        STRAP_RX_CFG_CDR_PH_GAIN : 4;
                unsigned int         STRAP_RX_CFG_ADAPT_MODE : 10;
                unsigned int           STRAP_RX_CFG_DFE_TIME : 4;
                unsigned int      STRAP_RX_CFG_LEQ_LOOP_GAIN : 2;
                unsigned int      STRAP_RX_CFG_LEQ_SHUNT_DIS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_STRAP_TX_REG0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int            STRAP_TX_CFG_DRV0_EN : 4;
                unsigned int       STRAP_TX_CFG_DRV0_TAP_SEL : 4;
                unsigned int            STRAP_TX_CFG_DRV1_EN : 5;
                unsigned int       STRAP_TX_CFG_DRV1_TAP_SEL : 5;
                unsigned int            STRAP_TX_CFG_DRV2_EN : 4;
                unsigned int       STRAP_TX_CFG_DRV2_TAP_SEL : 4;
                unsigned int            STRAP_TX_CFG_DRVX_EN : 1;
                unsigned int       STRAP_TX_CFG_DRVX_TAP_SEL : 1;
                unsigned int            STRAP_RX_TRK_MODE_1_ : 1;
                unsigned int     STRAP_TX_CFG_SWING_BOOST_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI {
	struct {
                unsigned int                  ACCEPT_ENTRY_0 : 1;
                unsigned int                  ACCEPT_ENTRY_1 : 1;
                unsigned int                  ACCEPT_ENTRY_2 : 1;
                unsigned int                  ACCEPT_ENTRY_3 : 1;
                unsigned int                  ACCEPT_ENTRY_4 : 1;
                unsigned int                  ACCEPT_ENTRY_5 : 1;
                unsigned int                  ACCEPT_ENTRY_6 : 1;
                unsigned int                  ACCEPT_ENTRY_7 : 1;
                unsigned int                  ACCEPT_ENTRY_8 : 1;
                unsigned int                  ACCEPT_ENTRY_9 : 1;
                unsigned int                 ACCEPT_ENTRY_10 : 1;
                unsigned int                 ACCEPT_ENTRY_11 : 1;
                unsigned int                 ACCEPT_ENTRY_12 : 1;
                unsigned int                 ACCEPT_ENTRY_13 : 1;
                unsigned int                 ACCEPT_ENTRY_14 : 1;
                unsigned int                 ACCEPT_ENTRY_15 : 1;
                unsigned int                 ACCEPT_ENTRY_16 : 1;
                unsigned int                 ACCEPT_ENTRY_17 : 1;
                unsigned int                 ACCEPT_ENTRY_18 : 1;
                unsigned int                 ACCEPT_ENTRY_19 : 1;
                unsigned int                 ACCEPT_ENTRY_20 : 1;
                unsigned int                 ACCEPT_ENTRY_21 : 1;
                unsigned int                 ACCEPT_ENTRY_22 : 1;
                unsigned int                 ACCEPT_ENTRY_23 : 1;
                unsigned int                 ACCEPT_ENTRY_24 : 1;
                unsigned int                 ACCEPT_ENTRY_25 : 1;
                unsigned int                 ACCEPT_ENTRY_26 : 1;
                unsigned int                 ACCEPT_ENTRY_27 : 1;
                unsigned int                 ACCEPT_ENTRY_28 : 1;
                unsigned int                 ACCEPT_ENTRY_29 : 1;
                unsigned int                 ACCEPT_ENTRY_30 : 1;
                unsigned int                 ACCEPT_ENTRY_31 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI {
	struct {
                unsigned int                 ACCEPT_ENTRY_32 : 1;
                unsigned int                 ACCEPT_ENTRY_33 : 1;
                unsigned int                 ACCEPT_ENTRY_34 : 1;
                unsigned int                 ACCEPT_ENTRY_35 : 1;
                unsigned int                 ACCEPT_ENTRY_36 : 1;
                unsigned int                 ACCEPT_ENTRY_37 : 1;
                unsigned int                 ACCEPT_ENTRY_38 : 1;
                unsigned int                 ACCEPT_ENTRY_39 : 1;
                unsigned int                 ACCEPT_ENTRY_40 : 1;
                unsigned int                 ACCEPT_ENTRY_41 : 1;
                unsigned int                 ACCEPT_ENTRY_42 : 1;
                unsigned int                 ACCEPT_ENTRY_43 : 1;
                unsigned int                 ACCEPT_ENTRY_44 : 1;
                unsigned int                 ACCEPT_ENTRY_45 : 1;
                unsigned int                 ACCEPT_ENTRY_46 : 1;
                unsigned int                 ACCEPT_ENTRY_47 : 1;
                unsigned int                 ACCEPT_ENTRY_48 : 1;
                unsigned int                 ACCEPT_ENTRY_49 : 1;
                unsigned int                 ACCEPT_ENTRY_50 : 1;
                unsigned int                 ACCEPT_ENTRY_51 : 1;
                unsigned int                 ACCEPT_ENTRY_52 : 1;
                unsigned int                 ACCEPT_ENTRY_53 : 1;
                unsigned int                 ACCEPT_ENTRY_54 : 1;
                unsigned int                 ACCEPT_ENTRY_55 : 1;
                unsigned int                 ACCEPT_ENTRY_56 : 1;
                unsigned int                 ACCEPT_ENTRY_57 : 1;
                unsigned int                 ACCEPT_ENTRY_58 : 1;
                unsigned int                 ACCEPT_ENTRY_59 : 1;
                unsigned int                 ACCEPT_ENTRY_60 : 1;
                unsigned int                 ACCEPT_ENTRY_61 : 1;
                unsigned int                 ACCEPT_ENTRY_62 : 1;
                unsigned int                 ACCEPT_ENTRY_63 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI {
	struct {
                unsigned int                 ACCEPT_ENTRY_64 : 1;
                unsigned int                 ACCEPT_ENTRY_65 : 1;
                unsigned int                 ACCEPT_ENTRY_66 : 1;
                unsigned int                 ACCEPT_ENTRY_67 : 1;
                unsigned int                 ACCEPT_ENTRY_68 : 1;
                unsigned int                 ACCEPT_ENTRY_69 : 1;
                unsigned int                 ACCEPT_ENTRY_70 : 1;
                unsigned int                 ACCEPT_ENTRY_71 : 1;
                unsigned int                 ACCEPT_ENTRY_72 : 1;
                unsigned int                 ACCEPT_ENTRY_73 : 1;
                unsigned int                 ACCEPT_ENTRY_74 : 1;
                unsigned int                 ACCEPT_ENTRY_75 : 1;
                unsigned int                 ACCEPT_ENTRY_76 : 1;
                unsigned int                 ACCEPT_ENTRY_77 : 1;
                unsigned int                 ACCEPT_ENTRY_78 : 1;
                unsigned int                 ACCEPT_ENTRY_79 : 1;
                unsigned int                 ACCEPT_ENTRY_80 : 1;
                unsigned int                 ACCEPT_ENTRY_81 : 1;
                unsigned int                 ACCEPT_ENTRY_82 : 1;
                unsigned int                 ACCEPT_ENTRY_83 : 1;
                unsigned int                 ACCEPT_ENTRY_84 : 1;
                unsigned int                 ACCEPT_ENTRY_85 : 1;
                unsigned int                 ACCEPT_ENTRY_86 : 1;
                unsigned int                 ACCEPT_ENTRY_87 : 1;
                unsigned int                 ACCEPT_ENTRY_88 : 1;
                unsigned int                 ACCEPT_ENTRY_89 : 1;
                unsigned int                 ACCEPT_ENTRY_90 : 1;
                unsigned int                 ACCEPT_ENTRY_91 : 1;
                unsigned int                 ACCEPT_ENTRY_92 : 1;
                unsigned int                 ACCEPT_ENTRY_93 : 1;
                unsigned int                 ACCEPT_ENTRY_94 : 1;
                unsigned int                 ACCEPT_ENTRY_95 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI {
	struct {
                unsigned int                 ACCEPT_ENTRY_96 : 1;
                unsigned int                 ACCEPT_ENTRY_97 : 1;
                unsigned int                 ACCEPT_ENTRY_98 : 1;
                unsigned int                 ACCEPT_ENTRY_99 : 1;
                unsigned int                ACCEPT_ENTRY_100 : 1;
                unsigned int                ACCEPT_ENTRY_101 : 1;
                unsigned int                ACCEPT_ENTRY_102 : 1;
                unsigned int                ACCEPT_ENTRY_103 : 1;
                unsigned int                ACCEPT_ENTRY_104 : 1;
                unsigned int                ACCEPT_ENTRY_105 : 1;
                unsigned int                ACCEPT_ENTRY_106 : 1;
                unsigned int                ACCEPT_ENTRY_107 : 1;
                unsigned int                ACCEPT_ENTRY_108 : 1;
                unsigned int                ACCEPT_ENTRY_109 : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_CTRL_REG0__CI {
	struct {
		unsigned int        TX_DRV_DATA_ASRT_DLY_VAL : 3;
		unsigned int        TX_DRV_DATA_DSRT_DLY_VAL : 3;
		unsigned int                                 : 2;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN1 : 3;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN2 : 3;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN3 : 3;
		unsigned int                 TX_STAGGER_CTRL : 2;
		unsigned int              TX_DATA_CLK_GATING : 1;
		unsigned int          TX_PRESET_TABLE_BYPASS : 1;
		unsigned int               TX_COEFF_ROUND_EN : 1;
		unsigned int          TX_COEFF_ROUND_DIR_VER : 1;
		unsigned int        TX_DCLK_EN_LSX_ALWAYS_ON : 1;
		unsigned int        TX_FRONTEND_PWRON_IN_OFF : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_CTRL_REG0__VI {
	struct {
		unsigned int        TX_DRV_DATA_ASRT_DLY_VAL : 3;
		unsigned int        TX_DRV_DATA_DSRT_DLY_VAL : 3;
		unsigned int                                 : 2;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN1 : 3;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN2 : 3;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN3 : 3;
		unsigned int                 TX_STAGGER_CTRL : 2;
		unsigned int              TX_DATA_CLK_GATING : 1;
		unsigned int          TX_PRESET_TABLE_BYPASS : 1;
		unsigned int               TX_COEFF_ROUND_EN : 1;
		unsigned int          TX_COEFF_ROUND_DIR_VER : 1;
		unsigned int        TX_DCLK_EN_LSX_ALWAYS_ON : 1;
		unsigned int        TX_FRONTEND_PWRON_IN_PS4 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_LANE_SKEW_CTRL__CI__VI {
	struct {
                unsigned int             TX_CFG_GROUPX1_EN_0 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_1 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_2 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_3 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_4 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_5 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_6 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_7 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_8 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_9 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_10 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_11 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_12 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_13 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_14 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_15 : 1;
                unsigned int          TX_CFG_GROUPX2_EN_L0T1 : 1;
                unsigned int          TX_CFG_GROUPX2_EN_L2T3 : 1;
                unsigned int          TX_CFG_GROUPX2_EN_L4T5 : 1;
                unsigned int          TX_CFG_GROUPX2_EN_L6T7 : 1;
                unsigned int          TX_CFG_GROUPX2_EN_L8T9 : 1;
                unsigned int        TX_CFG_GROUPX2_EN_L10T11 : 1;
                unsigned int        TX_CFG_GROUPX2_EN_L12T13 : 1;
                unsigned int        TX_CFG_GROUPX2_EN_L14T15 : 1;
                unsigned int          TX_CFG_GROUPX4_EN_L0T3 : 1;
                unsigned int          TX_CFG_GROUPX4_EN_L4T7 : 1;
                unsigned int         TX_CFG_GROUPX4_EN_L8T11 : 1;
                unsigned int        TX_CFG_GROUPX4_EN_L12T15 : 1;
                unsigned int          TX_CFG_GROUPX8_EN_L0T7 : 1;
                unsigned int         TX_CFG_GROUPX8_EN_L8T15 : 1;
                unsigned int        TX_CFG_GROUPX16_EN_L0T15 : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_OVRD_REG0__CI__VI {
	struct {
                unsigned int        TX_CFG_DCLK_DIV_OVRD_VAL : 3;
                unsigned int         TX_CFG_DCLK_DIV_OVRD_EN : 1;
                unsigned int    TX_CFG_DRV0_EN_GEN1_OVRD_VAL : 4;
                unsigned int          TX_CFG_DRV0_EN_OVRD_EN : 1;
                unsigned int TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL : 4;
                unsigned int     TX_CFG_DRV0_TAP_SEL_OVRD_EN : 1;
                unsigned int    TX_CFG_DRV1_EN_GEN1_OVRD_VAL : 5;
                unsigned int          TX_CFG_DRV1_EN_OVRD_EN : 1;
                unsigned int TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL : 5;
                unsigned int     TX_CFG_DRV1_TAP_SEL_OVRD_EN : 1;
                unsigned int    TX_CFG_DRV2_EN_GEN1_OVRD_VAL : 4;
                unsigned int          TX_CFG_DRV2_EN_OVRD_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_OVRD_REG1__CI__VI {
	struct {
                unsigned int TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL : 4;
                unsigned int     TX_CFG_DRV2_TAP_SEL_OVRD_EN : 1;
                unsigned int    TX_CFG_DRVX_EN_GEN1_OVRD_VAL : 1;
                unsigned int          TX_CFG_DRVX_EN_OVRD_EN : 1;
                unsigned int TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL : 1;
                unsigned int     TX_CFG_DRVX_TAP_SEL_OVRD_EN : 1;
                unsigned int      TX_CFG_PLLCLK_SEL_OVRD_VAL : 1;
                unsigned int       TX_CFG_PLLCLK_SEL_OVRD_EN : 1;
                unsigned int        TX_CFG_TCLK_DIV_OVRD_VAL : 1;
                unsigned int         TX_CFG_TCLK_DIV_OVRD_EN : 1;
                unsigned int            TX_CMDET_EN_OVRD_VAL : 1;
                unsigned int             TX_CMDET_EN_OVRD_EN : 1;
                unsigned int             TX_DATA_IN_OVRD_VAL : 10;
                unsigned int              TX_DATA_IN_OVRD_EN : 1;
                unsigned int           TX_RPTR_RSTN_OVRD_VAL : 1;
                unsigned int            TX_RPTR_RSTN_OVRD_EN : 1;
                unsigned int            TX_RXDET_EN_OVRD_VAL : 1;
                unsigned int             TX_RXDET_EN_OVRD_EN : 1;
                unsigned int           TX_WPTR_RSTN_OVRD_VAL : 1;
                unsigned int            TX_WPTR_RSTN_OVRD_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_OVRD_REG2__CI__VI {
	struct {
                unsigned int            TX_WRITE_EN_OVRD_VAL : 1;
                unsigned int             TX_WRITE_EN_OVRD_EN : 1;
                unsigned int      TX_CFG_GROUPX1_EN_OVRD_VAL : 1;
                unsigned int       TX_CFG_GROUPX1_EN_OVRD_EN : 1;
                unsigned int      TX_CFG_GROUPX2_EN_OVRD_VAL : 1;
                unsigned int       TX_CFG_GROUPX2_EN_OVRD_EN : 1;
                unsigned int      TX_CFG_GROUPX4_EN_OVRD_VAL : 1;
                unsigned int       TX_CFG_GROUPX4_EN_OVRD_EN : 1;
                unsigned int      TX_CFG_GROUPX8_EN_OVRD_VAL : 1;
                unsigned int       TX_CFG_GROUPX8_EN_OVRD_EN : 1;
                unsigned int     TX_CFG_GROUPX16_EN_OVRD_VAL : 1;
                unsigned int      TX_CFG_GROUPX16_EN_OVRD_EN : 1;
                unsigned int    TX_CFG_DRV0_EN_GEN2_OVRD_VAL : 4;
                unsigned int TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL : 4;
                unsigned int    TX_CFG_DRV1_EN_GEN2_OVRD_VAL : 5;
                unsigned int TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL : 5;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_OVRD_REG3__CI__VI {
	struct {
                unsigned int    TX_CFG_DRV2_EN_GEN2_OVRD_VAL : 4;
                unsigned int TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL : 4;
                unsigned int    TX_CFG_DRVX_EN_GEN2_OVRD_VAL : 1;
                unsigned int TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL : 1;
                unsigned int    TX_CFG_DRV0_EN_GEN3_OVRD_VAL : 4;
                unsigned int TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL : 4;
                unsigned int    TX_CFG_DRV1_EN_GEN3_OVRD_VAL : 5;
                unsigned int TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL : 5;
                unsigned int    TX_CFG_DRV2_EN_GEN3_OVRD_VAL : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_OVRD_REG4__CI__VI {
	struct {
                unsigned int TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL : 4;
                unsigned int    TX_CFG_DRVX_EN_GEN3_OVRD_VAL : 1;
                unsigned int TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int        IGNR_TXPWR_SCI_UPDT_L0T3 : 1;
		unsigned int        IGNR_TXPWR_SCI_UPDT_L4T7 : 1;
		unsigned int       IGNR_TXPWR_SCI_UPDT_L8T11 : 1;
		unsigned int      IGNR_TXPWR_SCI_UPDT_L12T15 : 1;
		unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L0T3 : 1;
		unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L12T15 : 1;
		unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L0T3 : 1;
		unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L12T15 : 1;
		unsigned int  IGNR_COEFFICIENT_SCI_UPDT_L0T3 : 1;
		unsigned int  IGNR_COEFFICIENT_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_COEFFICIENT_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_COEFFICIENT_SCI_UPDT_L12T15 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_GLB_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int        IGNR_TXPWR_CBI_UPDT_L0T3 : 1;
		unsigned int        IGNR_TXPWR_CBI_UPDT_L4T7 : 1;
		unsigned int       IGNR_TXPWR_CBI_UPDT_L8T11 : 1;
		unsigned int      IGNR_TXPWR_CBI_UPDT_L12T15 : 1;
		unsigned int                                 : 4;
		unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L0T3 : 1;
		unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L4T7 : 1;
		unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L12T15 : 1;
		unsigned int  IGNR_COEFFICIENT_CBI_UPDT_L0T3 : 1;
		unsigned int  IGNR_COEFFICIENT_CBI_UPDT_L4T7 : 1;
		unsigned int IGNR_COEFFICIENT_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_COEFFICIENT_CBI_UPDT_L12T15 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE0_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_0 : 1;
                unsigned int               TX_CFG_INV_DATA_0 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_0 : 1;
                unsigned int                TX_DBG_PRBS_EN_0 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE0_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_0 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_0 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_0 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_0 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_0 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_0 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_0 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_0 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_0 : 3;
                unsigned int          INCOHERENTCK_0__SI__CI : 1;
                unsigned int                        TXMARG_0 : 3;
                unsigned int                        DEEMPH_0 : 1;
                unsigned int                 COEFFICIENTID_0 : 2;
                unsigned int                   COEFFICIENT_0 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE10_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_10 : 1;
                unsigned int              TX_CFG_INV_DATA_10 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_10 : 1;
                unsigned int               TX_DBG_PRBS_EN_10 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE10_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_10 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_10 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_10 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_10 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_10 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_10 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_10 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_10 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_10 : 3;
                unsigned int         INCOHERENTCK_10__SI__CI : 1;
                unsigned int                       TXMARG_10 : 3;
                unsigned int                       DEEMPH_10 : 1;
                unsigned int                COEFFICIENTID_10 : 2;
                unsigned int                  COEFFICIENT_10 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE11_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_11 : 1;
                unsigned int              TX_CFG_INV_DATA_11 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_11 : 1;
                unsigned int               TX_DBG_PRBS_EN_11 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE11_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_11 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_11 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_11 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_11 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_11 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_11 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_11 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_11 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_11 : 3;
                unsigned int         INCOHERENTCK_11__SI__CI : 1;
                unsigned int                       TXMARG_11 : 3;
                unsigned int                       DEEMPH_11 : 1;
                unsigned int                COEFFICIENTID_11 : 2;
                unsigned int                  COEFFICIENT_11 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE12_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_12 : 1;
                unsigned int              TX_CFG_INV_DATA_12 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_12 : 1;
                unsigned int               TX_DBG_PRBS_EN_12 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE12_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_12 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_12 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_12 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_12 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_12 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_12 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_12 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_12 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_12 : 3;
                unsigned int         INCOHERENTCK_12__SI__CI : 1;
                unsigned int                       TXMARG_12 : 3;
                unsigned int                       DEEMPH_12 : 1;
                unsigned int                COEFFICIENTID_12 : 2;
                unsigned int                  COEFFICIENT_12 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE13_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_13 : 1;
                unsigned int              TX_CFG_INV_DATA_13 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_13 : 1;
                unsigned int               TX_DBG_PRBS_EN_13 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE13_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_13 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_13 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_13 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_13 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_13 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_13 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_13 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_13 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_13 : 3;
                unsigned int         INCOHERENTCK_13__SI__CI : 1;
                unsigned int                       TXMARG_13 : 3;
                unsigned int                       DEEMPH_13 : 1;
                unsigned int                COEFFICIENTID_13 : 2;
                unsigned int                  COEFFICIENT_13 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE14_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_14 : 1;
                unsigned int              TX_CFG_INV_DATA_14 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_14 : 1;
                unsigned int               TX_DBG_PRBS_EN_14 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE14_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_14 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_14 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_14 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_14 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_14 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_14 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_14 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_14 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_14 : 3;
                unsigned int         INCOHERENTCK_14__SI__CI : 1;
                unsigned int                       TXMARG_14 : 3;
                unsigned int                       DEEMPH_14 : 1;
                unsigned int                COEFFICIENTID_14 : 2;
                unsigned int                  COEFFICIENT_14 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE15_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_15 : 1;
                unsigned int              TX_CFG_INV_DATA_15 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_15 : 1;
                unsigned int               TX_DBG_PRBS_EN_15 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE15_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_15 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_15 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_15 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_15 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_15 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_15 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_15 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_15 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_15 : 3;
                unsigned int         INCOHERENTCK_15__SI__CI : 1;
                unsigned int                       TXMARG_15 : 3;
                unsigned int                       DEEMPH_15 : 1;
                unsigned int                COEFFICIENTID_15 : 2;
                unsigned int                  COEFFICIENT_15 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE1_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_1 : 1;
                unsigned int               TX_CFG_INV_DATA_1 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_1 : 1;
                unsigned int                TX_DBG_PRBS_EN_1 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE1_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_1 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_1 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_1 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_1 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_1 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_1 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_1 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_1 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_1 : 3;
                unsigned int          INCOHERENTCK_1__SI__CI : 1;
                unsigned int                        TXMARG_1 : 3;
                unsigned int                        DEEMPH_1 : 1;
                unsigned int                 COEFFICIENTID_1 : 2;
                unsigned int                   COEFFICIENT_1 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE2_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_2 : 1;
                unsigned int               TX_CFG_INV_DATA_2 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_2 : 1;
                unsigned int                TX_DBG_PRBS_EN_2 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE2_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_2 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_2 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_2 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_2 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_2 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_2 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_2 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_2 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_2 : 3;
                unsigned int          INCOHERENTCK_2__SI__CI : 1;
                unsigned int                        TXMARG_2 : 3;
                unsigned int                        DEEMPH_2 : 1;
                unsigned int                 COEFFICIENTID_2 : 2;
                unsigned int                   COEFFICIENT_2 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE3_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_3 : 1;
                unsigned int               TX_CFG_INV_DATA_3 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_3 : 1;
                unsigned int                TX_DBG_PRBS_EN_3 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE3_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_3 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_3 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_3 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_3 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_3 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_3 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_3 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_3 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_3 : 3;
                unsigned int          INCOHERENTCK_3__SI__CI : 1;
                unsigned int                        TXMARG_3 : 3;
                unsigned int                        DEEMPH_3 : 1;
                unsigned int                 COEFFICIENTID_3 : 2;
                unsigned int                   COEFFICIENT_3 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE4_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_4 : 1;
                unsigned int               TX_CFG_INV_DATA_4 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_4 : 1;
                unsigned int                TX_DBG_PRBS_EN_4 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE4_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_4 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_4 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_4 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_4 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_4 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_4 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_4 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_4 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_4 : 3;
                unsigned int          INCOHERENTCK_4__SI__CI : 1;
                unsigned int                        TXMARG_4 : 3;
                unsigned int                        DEEMPH_4 : 1;
                unsigned int                 COEFFICIENTID_4 : 2;
                unsigned int                   COEFFICIENT_4 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE5_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_5 : 1;
                unsigned int               TX_CFG_INV_DATA_5 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_5 : 1;
                unsigned int                TX_DBG_PRBS_EN_5 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE5_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_5 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_5 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_5 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_5 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_5 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_5 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_5 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_5 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_5 : 3;
                unsigned int          INCOHERENTCK_5__SI__CI : 1;
                unsigned int                        TXMARG_5 : 3;
                unsigned int                        DEEMPH_5 : 1;
                unsigned int                 COEFFICIENTID_5 : 2;
                unsigned int                   COEFFICIENT_5 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE6_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_6 : 1;
                unsigned int               TX_CFG_INV_DATA_6 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_6 : 1;
                unsigned int                TX_DBG_PRBS_EN_6 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE6_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_6 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_6 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_6 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_6 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_6 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_6 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_6 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_6 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_6 : 3;
                unsigned int          INCOHERENTCK_6__SI__CI : 1;
                unsigned int                        TXMARG_6 : 3;
                unsigned int                        DEEMPH_6 : 1;
                unsigned int                 COEFFICIENTID_6 : 2;
                unsigned int                   COEFFICIENT_6 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE7_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_7 : 1;
                unsigned int               TX_CFG_INV_DATA_7 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_7 : 1;
                unsigned int                TX_DBG_PRBS_EN_7 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE7_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_7 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_7 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_7 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_7 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_7 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_7 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_7 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_7 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_7 : 3;
                unsigned int          INCOHERENTCK_7__SI__CI : 1;
                unsigned int                        TXMARG_7 : 3;
                unsigned int                        DEEMPH_7 : 1;
                unsigned int                 COEFFICIENTID_7 : 2;
                unsigned int                   COEFFICIENT_7 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE8_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_8 : 1;
                unsigned int               TX_CFG_INV_DATA_8 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_8 : 1;
                unsigned int                TX_DBG_PRBS_EN_8 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE8_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_8 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_8 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_8 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_8 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_8 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_8 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_8 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_8 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_8 : 3;
                unsigned int          INCOHERENTCK_8__SI__CI : 1;
                unsigned int                        TXMARG_8 : 3;
                unsigned int                        DEEMPH_8 : 1;
                unsigned int                 COEFFICIENTID_8 : 2;
                unsigned int                   COEFFICIENT_8 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE9_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_9 : 1;
                unsigned int               TX_CFG_INV_DATA_9 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_9 : 1;
                unsigned int                TX_DBG_PRBS_EN_9 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE9_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_9 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_9 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_9 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_9 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_9 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_9 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_9 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_9 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_9 : 3;
                unsigned int          INCOHERENTCK_9__SI__CI : 1;
                unsigned int                        TXMARG_9 : 3;
                unsigned int                        DEEMPH_9 : 1;
                unsigned int                 COEFFICIENTID_9 : 2;
                unsigned int                   COEFFICIENT_9 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_DFT_DEBUG_CTRL_REG0__CI__VI {
	struct {
                unsigned int                DFT_PHY_DEBUG_EN : 1;
                unsigned int              DFT_PHY_DEBUG_MODE : 5;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_DFT_JIT_INJ_REG0__CI__VI {
	struct {
                unsigned int                   DFT_NUM_STEPS : 6;
                unsigned int                                 : 1;
                unsigned int                 DFT_DISABLE_ERR : 1;
                unsigned int                DFT_CLK_PER_STEP : 4;
                unsigned int                                 : 8;
                unsigned int                 DFT_MODE_CDR_EN : 1;
                unsigned int                 DFT_EN_RECOVERY : 1;
                unsigned int                 DFT_INCR_SWP_EN : 1;
                unsigned int                 DFT_DECR_SWP_EN : 1;
                unsigned int               DFT_RECOVERY_TIME : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_DFT_JIT_INJ_REG1__CI__VI {
	struct {
                unsigned int                DFT_BYPASS_VALUE : 8;
                unsigned int                   DFT_BYPASS_EN : 1;
                unsigned int                                 : 7;
                unsigned int                    DFT_BLOCK_EN : 1;
                unsigned int                DFT_NUM_OF_TESTS : 3;
                unsigned int                  DFT_CHECK_TIME : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_DFT_JIT_INJ_REG2__CI__VI {
	struct {
                unsigned int                     DFT_LANE_EN : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_DFT_JIT_INJ_STAT_REG0__CI__VI {
	struct {
                unsigned int                   DFT_STAT_DECR : 8;
                unsigned int                   DFT_STAT_INCR : 8;
                unsigned int               DFT_STAT_FINISHED : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_CTRL_REG0__CI__VI {
	struct {
                unsigned int                          BACKUP : 16;
                unsigned int                  CFG_IDLEDET_TH : 2;
                unsigned int                                 : 2;
                unsigned int                DBG_RX2TXBYP_SEL : 3;
                unsigned int                  DBG_RXFEBYP_EN : 1;
                unsigned int                  DBG_RXPRBS_CLR : 1;
                unsigned int                 DBG_RXTOGGLE_EN : 1;
                unsigned int               DBG_TX2RXLBACK_EN : 1;
                unsigned int                                 : 3;
                unsigned int              TXCFG_CMGOOD_RANGE : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_CTRL_REG1__CI__VI {
	struct {
                unsigned int             RXDBG_CDR_FR_BYP_EN : 1;
                unsigned int            RXDBG_CDR_FR_BYP_VAL : 6;
                unsigned int             RXDBG_CDR_PH_BYP_EN : 1;
                unsigned int            RXDBG_CDR_PH_BYP_VAL : 6;
                unsigned int               RXDBG_D0TH_BYP_EN : 1;
                unsigned int              RXDBG_D0TH_BYP_VAL : 7;
                unsigned int               RXDBG_D1TH_BYP_EN : 1;
                unsigned int              RXDBG_D1TH_BYP_VAL : 7;
                unsigned int                 TST_LOSPDTST_EN : 1;
                unsigned int             PLL_CFG_DISPCLK_DIV : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_CTRL_REG2__CI__VI {
	struct {
                unsigned int               RXDBG_D2TH_BYP_EN : 1;
                unsigned int              RXDBG_D2TH_BYP_VAL : 7;
                unsigned int               RXDBG_D3TH_BYP_EN : 1;
                unsigned int              RXDBG_D3TH_BYP_VAL : 7;
                unsigned int               RXDBG_DXTH_BYP_EN : 1;
                unsigned int              RXDBG_DXTH_BYP_VAL : 7;
                unsigned int                RXDBG_ETH_BYP_EN : 1;
                unsigned int               RXDBG_ETH_BYP_VAL : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_CTRL_REG3__CI__VI {
	struct {
                unsigned int                       RXDBG_SEL : 5;
                unsigned int         BG_CFG_LC_REG_VREF0_SEL : 2;
                unsigned int         BG_CFG_LC_REG_VREF1_SEL : 2;
                unsigned int          BG_CFG_RO_REG_VREF_SEL : 2;
                unsigned int               BG_DBG_VREFBYP_EN : 1;
                unsigned int               BG_DBG_IREFBYP_EN : 1;
                unsigned int                                 : 1;
                unsigned int               BG_DBG_ANALOG_SEL : 3;
                unsigned int                                 : 1;
                unsigned int                 DBG_DLL_CLK_SEL : 3;
                unsigned int            PLL_DISPCLK_CMOS_SEL : 1;
                unsigned int          DBG_RXPI_OFFSET_BYP_EN : 1;
                unsigned int         DBG_RXPI_OFFSET_BYP_VAL : 4;
                unsigned int             DBG_RXSWAPDX_BYP_EN : 1;
                unsigned int            DBG_RXSWAPDX_BYP_VAL : 3;
                unsigned int DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_CTRL_REG4__CI__VI {
	struct {
                unsigned int                  DBG_RXAPU_INST : 16;
                unsigned int            DBG_RXDFEMUX_BYP_VAL : 2;
                unsigned int             DBG_RXDFEMUX_BYP_EN : 1;
                unsigned int                                 : 3;
                unsigned int                  DBG_RXAPU_EXEC : 4;
                unsigned int          DBG_RXDLL_VREG_REF_SEL : 1;
                unsigned int                    PWRGOOD_OVRD : 1;
                unsigned int      DBG_RXRDATA_GATING_DISABLE : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_CTRL_REG5__CI__VI {
	struct {
                unsigned int                  DBG_RXAPU_MODE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TXPDTERM_VAL_OVRD_VAL : 16;
                unsigned int           TXPUTERM_VAL_OVRD_VAL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_OVRD_REG1__CI__VI {
	struct {
                unsigned int            TXPDTERM_VAL_OVRD_EN : 1;
                unsigned int            TXPUTERM_VAL_OVRD_EN : 1;
                unsigned int        TST_LOSPDTST_RST_OVRD_EN : 1;
                unsigned int       TST_LOSPDTST_RST_OVRD_VAL : 1;
                unsigned int                                 : 11;
                unsigned int              RXTERM_VAL_OVRD_EN : 1;
                unsigned int             RXTERM_VAL_OVRD_VAL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_OVRD_REG2__CI__VI {
	struct {
                unsigned int                BG_PWRON_OVRD_EN : 1;
                unsigned int               BG_PWRON_OVRD_VAL : 1;
                unsigned int PLL_DBG_LC_EXT_RESET_OVRD_EN__VI : 1;
                unsigned int PLL_DBG_LC_EXT_RESET_OVRD_VAL__VI : 1;
                unsigned int PLL_DBG_RO_EXT_RESET_OVRD_EN__VI : 1;
                unsigned int PLL_DBG_RO_EXT_RESET_OVRD_VAL__VI : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int          IGNR_ALL_SCI_UPDT_L0T3 : 1;
		unsigned int          IGNR_ALL_SCI_UPDT_L4T7 : 1;
		unsigned int         IGNR_ALL_SCI_UPDT_L8T11 : 1;
		unsigned int        IGNR_ALL_SCI_UPDT_L12T15 : 1;
		unsigned int     IGNR_IMPCAL_ACTIVE_SCI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                          TXNIMP : 4;
		unsigned int                          TXPIMP : 4;
		unsigned int                           RXIMP : 4;
		unsigned int                   IMPCAL_ACTIVE : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int          IGNR_ALL_CBI_UPDT_L0T3 : 1;
		unsigned int          IGNR_ALL_CBI_UPDT_L4T7 : 1;
		unsigned int         IGNR_ALL_CBI_UPDT_L8T11 : 1;
		unsigned int        IGNR_ALL_CBI_UPDT_L12T15 : 1;
		unsigned int     IGNR_IMPCAL_ACTIVE_CBI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                          TXNIMP : 4;
		unsigned int                          TXPIMP : 4;
		unsigned int                           RXIMP : 4;
		unsigned int                   IMPCAL_ACTIVE : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_SCI_STAT_OVRD_REG1__CI {
	struct {
		unsigned int         IGNR_MODE_SCI_UPDT_L0T3 : 1;
		unsigned int      IGNR_FREQDIV_SCI_UPDT_L0T3 : 1;
		unsigned int     IGNR_DLL_LOCK_SCI_UPDT_L0T3 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_0 : 1;
		unsigned int                      DLL_LOCK_1 : 1;
		unsigned int                      DLL_LOCK_2 : 1;
		unsigned int                      DLL_LOCK_3 : 1;
		unsigned int                          MODE_0 : 2;
		unsigned int                       FREQDIV_0 : 2;
		unsigned int                          MODE_1 : 2;
		unsigned int                       FREQDIV_1 : 2;
		unsigned int                          MODE_2 : 2;
		unsigned int                       FREQDIV_2 : 2;
		unsigned int                          MODE_3 : 2;
		unsigned int                       FREQDIV_3 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_SCI_STAT_OVRD_REG1__VI {
	struct {
		unsigned int    IGNR_LINKSPEED_CBI_UPDT_L0T3 : 1;
		unsigned int      IGNR_FREQDIV_CBI_UPDT_L0T3 : 1;
		unsigned int     IGNR_DLL_LOCK_CBI_UPDT_L0T3 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_0 : 1;
		unsigned int                      DLL_LOCK_1 : 1;
		unsigned int                      DLL_LOCK_2 : 1;
		unsigned int                      DLL_LOCK_3 : 1;
		unsigned int                     LINKSPEED_0 : 2;
		unsigned int                       FREQDIV_0 : 2;
		unsigned int                     LINKSPEED_1 : 2;
		unsigned int                       FREQDIV_1 : 2;
		unsigned int                     LINKSPEED_2 : 2;
		unsigned int                       FREQDIV_2 : 2;
		unsigned int                     LINKSPEED_3 : 2;
		unsigned int                       FREQDIV_3 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_SCI_STAT_OVRD_REG2__CI {
	struct {
		unsigned int         IGNR_MODE_SCI_UPDT_L4T7 : 1;
		unsigned int      IGNR_FREQDIV_SCI_UPDT_L4T7 : 1;
		unsigned int     IGNR_DLL_LOCK_SCI_UPDT_L4T7 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_4 : 1;
		unsigned int                      DLL_LOCK_5 : 1;
		unsigned int                      DLL_LOCK_6 : 1;
		unsigned int                      DLL_LOCK_7 : 1;
		unsigned int                          MODE_4 : 2;
		unsigned int                       FREQDIV_4 : 2;
		unsigned int                          MODE_5 : 2;
		unsigned int                       FREQDIV_5 : 2;
		unsigned int                          MODE_6 : 2;
		unsigned int                       FREQDIV_6 : 2;
		unsigned int                          MODE_7 : 2;
		unsigned int                       FREQDIV_7 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_SCI_STAT_OVRD_REG2__VI {
	struct {
		unsigned int    IGNR_LINKSPEED_CBI_UPDT_L4T7 : 1;
		unsigned int      IGNR_FREQDIV_CBI_UPDT_L4T7 : 1;
		unsigned int     IGNR_DLL_LOCK_CBI_UPDT_L4T7 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_4 : 1;
		unsigned int                      DLL_LOCK_5 : 1;
		unsigned int                      DLL_LOCK_6 : 1;
		unsigned int                      DLL_LOCK_7 : 1;
		unsigned int                     LINKSPEED_4 : 2;
		unsigned int                       FREQDIV_4 : 2;
		unsigned int                     LINKSPEED_5 : 2;
		unsigned int                       FREQDIV_5 : 2;
		unsigned int                     LINKSPEED_6 : 2;
		unsigned int                       FREQDIV_6 : 2;
		unsigned int                     LINKSPEED_7 : 2;
		unsigned int                       FREQDIV_7 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_SCI_STAT_OVRD_REG3__CI {
	struct {
		unsigned int        IGNR_MODE_SCI_UPDT_L8T11 : 1;
		unsigned int     IGNR_FREQDIV_SCI_UPDT_L8T11 : 1;
		unsigned int    IGNR_DLL_LOCK_SCI_UPDT_L8T11 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_8 : 1;
		unsigned int                      DLL_LOCK_9 : 1;
		unsigned int                     DLL_LOCK_10 : 1;
		unsigned int                     DLL_LOCK_11 : 1;
		unsigned int                          MODE_8 : 2;
		unsigned int                       FREQDIV_8 : 2;
		unsigned int                          MODE_9 : 2;
		unsigned int                       FREQDIV_9 : 2;
		unsigned int                         MODE_10 : 2;
		unsigned int                      FREQDIV_10 : 2;
		unsigned int                         MODE_11 : 2;
		unsigned int                      FREQDIV_11 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_SCI_STAT_OVRD_REG3__VI {
	struct {
		unsigned int   IGNR_LINKSPEED_CBI_UPDT_L8T11 : 1;
		unsigned int     IGNR_FREQDIV_CBI_UPDT_L8T11 : 1;
		unsigned int    IGNR_DLL_LOCK_CBI_UPDT_L8T11 : 1;
		unsigned int                                 : 9;
		unsigned int                      DLL_LOCK_8 : 1;
		unsigned int                      DLL_LOCK_9 : 1;
		unsigned int                     DLL_LOCK_10 : 1;
		unsigned int                     DLL_LOCK_11 : 1;
		unsigned int                     LINKSPEED_8 : 2;
		unsigned int                       FREQDIV_8 : 2;
		unsigned int                     LINKSPEED_9 : 2;
		unsigned int                       FREQDIV_9 : 2;
		unsigned int                    LINKSPEED_10 : 2;
		unsigned int                      FREQDIV_10 : 2;
		unsigned int                    LINKSPEED_11 : 2;
		unsigned int                      FREQDIV_11 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_SCI_STAT_OVRD_REG4__CI {
	struct {
		unsigned int       IGNR_MODE_SCI_UPDT_L12T15 : 1;
		unsigned int    IGNR_FREQDIV_SCI_UPDT_L12T15 : 1;
		unsigned int   IGNR_DLL_LOCK_SCI_UPDT_L12T15 : 1;
		unsigned int                                 : 9;
		unsigned int                     DLL_LOCK_12 : 1;
		unsigned int                     DLL_LOCK_13 : 1;
		unsigned int                     DLL_LOCK_14 : 1;
		unsigned int                     DLL_LOCK_15 : 1;
		unsigned int                         MODE_12 : 2;
		unsigned int                      FREQDIV_12 : 2;
		unsigned int                         MODE_13 : 2;
		unsigned int                      FREQDIV_13 : 2;
		unsigned int                         MODE_14 : 2;
		unsigned int                      FREQDIV_14 : 2;
		unsigned int                         MODE_15 : 2;
		unsigned int                      FREQDIV_15 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_GLB_SCI_STAT_OVRD_REG4__VI {
	struct {
		unsigned int  IGNR_LINKSPEED_CBI_UPDT_L12T15 : 1;
		unsigned int    IGNR_FREQDIV_CBI_UPDT_L12T15 : 1;
		unsigned int   IGNR_DLL_LOCK_CBI_UPDT_L12T15 : 1;
		unsigned int                                 : 9;
		unsigned int                     DLL_LOCK_12 : 1;
		unsigned int                     DLL_LOCK_13 : 1;
		unsigned int                     DLL_LOCK_14 : 1;
		unsigned int                     DLL_LOCK_15 : 1;
		unsigned int                    LINKSPEED_12 : 2;
		unsigned int                      FREQDIV_12 : 2;
		unsigned int                    LINKSPEED_13 : 2;
		unsigned int                      FREQDIV_13 : 2;
		unsigned int                    LINKSPEED_14 : 2;
		unsigned int                      FREQDIV_14 : 2;
		unsigned int                    LINKSPEED_15 : 2;
		unsigned int                      FREQDIV_15 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_HW_DEBUG__CI {
	struct {
		unsigned int                 PB1_HW_00_DEBUG : 1;
		unsigned int                 PB1_HW_01_DEBUG : 1;
		unsigned int                 PB1_HW_02_DEBUG : 1;
		unsigned int                 PB1_HW_03_DEBUG : 1;
		unsigned int                 PB1_HW_04_DEBUG : 1;
		unsigned int                 PB1_HW_05_DEBUG : 1;
		unsigned int                 PB1_HW_06_DEBUG : 1;
		unsigned int                 PB1_HW_07_DEBUG : 1;
		unsigned int                 PB1_HW_08_DEBUG : 1;
		unsigned int                 PB1_HW_09_DEBUG : 1;
		unsigned int                 PB1_HW_10_DEBUG : 1;
		unsigned int                 PB1_HW_11_DEBUG : 1;
		unsigned int                 PB1_HW_12_DEBUG : 1;
		unsigned int                 PB1_HW_13_DEBUG : 1;
		unsigned int                 PB1_HW_14_DEBUG : 1;
		unsigned int                 PB1_HW_15_DEBUG : 1;
		unsigned int                 PB1_HW_16_DEBUG : 1;
		unsigned int                 PB1_HW_17_DEBUG : 1;
		unsigned int                 PB1_HW_18_DEBUG : 1;
		unsigned int                 PB1_HW_19_DEBUG : 1;
		unsigned int                 PB1_HW_20_DEBUG : 1;
		unsigned int                 PB1_HW_21_DEBUG : 1;
		unsigned int                 PB1_HW_22_DEBUG : 1;
		unsigned int                 PB1_HW_23_DEBUG : 1;
		unsigned int                 PB1_HW_24_DEBUG : 1;
		unsigned int                 PB1_HW_25_DEBUG : 1;
		unsigned int                 PB1_HW_26_DEBUG : 1;
		unsigned int                 PB1_HW_27_DEBUG : 1;
		unsigned int                 PB1_HW_28_DEBUG : 1;
		unsigned int                 PB1_HW_29_DEBUG : 1;
		unsigned int                 PB1_HW_30_DEBUG : 1;
		unsigned int                 PB1_HW_31_DEBUG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_HW_DEBUG__VI {
	struct {
		unsigned int                     HW_00_DEBUG : 1;
		unsigned int                     HW_01_DEBUG : 1;
		unsigned int                     HW_02_DEBUG : 1;
		unsigned int                     HW_03_DEBUG : 1;
		unsigned int                     HW_04_DEBUG : 1;
		unsigned int                     HW_05_DEBUG : 1;
		unsigned int                     HW_06_DEBUG : 1;
		unsigned int                     HW_07_DEBUG : 1;
		unsigned int                     HW_08_DEBUG : 1;
		unsigned int                     HW_09_DEBUG : 1;
		unsigned int                     HW_10_DEBUG : 1;
		unsigned int                     HW_11_DEBUG : 1;
		unsigned int                     HW_12_DEBUG : 1;
		unsigned int                     HW_13_DEBUG : 1;
		unsigned int                     HW_14_DEBUG : 1;
		unsigned int                     HW_15_DEBUG : 1;
		unsigned int                     HW_16_DEBUG : 1;
		unsigned int                     HW_17_DEBUG : 1;
		unsigned int                     HW_18_DEBUG : 1;
		unsigned int                     HW_19_DEBUG : 1;
		unsigned int                     HW_20_DEBUG : 1;
		unsigned int                     HW_21_DEBUG : 1;
		unsigned int                     HW_22_DEBUG : 1;
		unsigned int                     HW_23_DEBUG : 1;
		unsigned int                     HW_24_DEBUG : 1;
		unsigned int                     HW_25_DEBUG : 1;
		unsigned int                     HW_26_DEBUG : 1;
		unsigned int                     HW_27_DEBUG : 1;
		unsigned int                     HW_28_DEBUG : 1;
		unsigned int                     HW_29_DEBUG : 1;
		unsigned int                     HW_30_DEBUG : 1;
		unsigned int                     HW_31_DEBUG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_CNTL2__CI {
	struct {
		unsigned int                                 : 1;
		unsigned int             RXDETECT_SAMPL_TIME : 2;
		unsigned int                                 : 4;
		unsigned int            RXDETECT_OVERRIDE_EN : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_0 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_1 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_2 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_3 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_4 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_5 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_6 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_7 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_8 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_9 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_10 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_11 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_12 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_13 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_14 : 1;
		unsigned int        RXDETECT_OVERRIDE_VAL_15 : 1;
		unsigned int               RXPHYSTATUS_DELAY : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_CNTL__CI {
	struct {
		unsigned int               SERIAL_CFG_ENABLE : 1;
		unsigned int                 DA_FIFO_RESET_0 : 1;
		unsigned int                  PHY_CR_EN_MODE : 1;
		unsigned int               PHYCMD_CR_EN_MODE : 1;
		unsigned int               EI_DET_CYCLE_MODE : 1;
		unsigned int                 DA_FIFO_RESET_1 : 1;
		unsigned int        RXDETECT_FIFO_RESET_MODE : 1;
		unsigned int            RXDETECT_TX_PWR_MODE : 1;
		unsigned int                    DIVINIT_MODE : 1;
		unsigned int                 DA_FIFO_RESET_2 : 1;
		unsigned int              PLL_BINDING_ENABLE : 1;
		unsigned int              SC_CALIB_DONE_CNTL : 1;
		unsigned int                                 : 1;
		unsigned int                 DA_FIFO_RESET_3 : 1;
		unsigned int                                 : 2;
		unsigned int                      TXGND_TIME : 1;
		unsigned int                   LS2_EXIT_TIME : 3;
		unsigned int               EI_CYCLE_OFF_TIME : 3;
		unsigned int               EXIT_L0S_INIT_DIS : 1;
		unsigned int                      RXEN_GATER : 4;
		unsigned int          EXTEND_WAIT_FOR_RAMPUP : 1;
		unsigned int       IGNORE_TxDataValid_EP_DIS : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_HW_DEBUG__CI {
	struct {
		unsigned int             PB1_PIF_HW_00_DEBUG : 1;
		unsigned int             PB1_PIF_HW_01_DEBUG : 1;
		unsigned int             PB1_PIF_HW_02_DEBUG : 1;
		unsigned int             PB1_PIF_HW_03_DEBUG : 1;
		unsigned int             PB1_PIF_HW_04_DEBUG : 1;
		unsigned int             PB1_PIF_HW_05_DEBUG : 1;
		unsigned int             PB1_PIF_HW_06_DEBUG : 1;
		unsigned int             PB1_PIF_HW_07_DEBUG : 1;
		unsigned int             PB1_PIF_HW_08_DEBUG : 1;
		unsigned int             PB1_PIF_HW_09_DEBUG : 1;
		unsigned int             PB1_PIF_HW_10_DEBUG : 1;
		unsigned int             PB1_PIF_HW_11_DEBUG : 1;
		unsigned int             PB1_PIF_HW_12_DEBUG : 1;
		unsigned int             PB1_PIF_HW_13_DEBUG : 1;
		unsigned int             PB1_PIF_HW_14_DEBUG : 1;
		unsigned int             PB1_PIF_HW_15_DEBUG : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_HW_DEBUG__VI {
	struct {
		unsigned int                     HW_00_DEBUG : 1;
		unsigned int                     HW_01_DEBUG : 1;
		unsigned int                     HW_02_DEBUG : 1;
		unsigned int                     HW_03_DEBUG : 1;
		unsigned int                     HW_04_DEBUG : 1;
		unsigned int                     HW_05_DEBUG : 1;
		unsigned int                     HW_06_DEBUG : 1;
		unsigned int                     HW_07_DEBUG : 1;
		unsigned int                     HW_08_DEBUG : 1;
		unsigned int                     HW_09_DEBUG : 1;
		unsigned int                     HW_10_DEBUG : 1;
		unsigned int                     HW_11_DEBUG : 1;
		unsigned int                     HW_12_DEBUG : 1;
		unsigned int                     HW_13_DEBUG : 1;
		unsigned int                     HW_14_DEBUG : 1;
		unsigned int                     HW_15_DEBUG : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PAIRING__CI {
	struct {
		unsigned int                     X2_LANE_1_0 : 1;
		unsigned int                     X2_LANE_3_2 : 1;
		unsigned int                     X2_LANE_5_4 : 1;
		unsigned int                     X2_LANE_7_6 : 1;
		unsigned int                     X2_LANE_9_8 : 1;
		unsigned int                   X2_LANE_11_10 : 1;
		unsigned int                   X2_LANE_13_12 : 1;
		unsigned int                   X2_LANE_15_14 : 1;
		unsigned int                     X4_LANE_3_0 : 1;
		unsigned int                     X4_LANE_7_4 : 1;
		unsigned int                    X4_LANE_11_8 : 1;
		unsigned int                   X4_LANE_15_12 : 1;
		unsigned int                                 : 4;
		unsigned int                     X8_LANE_7_0 : 1;
		unsigned int                    X8_LANE_15_8 : 1;
		unsigned int                                 : 2;
		unsigned int                   X16_LANE_15_0 : 1;
		unsigned int                                 : 4;
		unsigned int                       MULTI_PIF : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_0__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_0 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_0 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_0 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_0 : 3;
		unsigned int              RXEN_OVERRIDE_EN_0 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_0 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_0 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_0 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_0 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_0 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_10__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_10 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_10 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_10 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_10 : 3;
		unsigned int             RXEN_OVERRIDE_EN_10 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_10 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_10 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_10 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_10 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_10 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_11__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_11 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_11 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_11 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_11 : 3;
		unsigned int             RXEN_OVERRIDE_EN_11 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_11 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_11 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_11 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_11 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_11 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_12__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_12 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_12 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_12 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_12 : 3;
		unsigned int             RXEN_OVERRIDE_EN_12 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_12 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_12 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_12 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_12 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_12 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_13__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_13 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_13 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_13 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_13 : 3;
		unsigned int             RXEN_OVERRIDE_EN_13 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_13 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_13 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_13 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_13 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_13 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_14__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_14 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_14 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_14 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_14 : 3;
		unsigned int             RXEN_OVERRIDE_EN_14 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_14 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_14 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_14 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_14 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_14 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_15__CI {
	struct {
		unsigned int          TX_PDNB_OVERRIDE_EN_15 : 1;
		unsigned int         TX_PDNB_OVERRIDE_VAL_15 : 3;
		unsigned int          RX_PDNB_OVERRIDE_EN_15 : 1;
		unsigned int         RX_PDNB_OVERRIDE_VAL_15 : 3;
		unsigned int             RXEN_OVERRIDE_EN_15 : 1;
		unsigned int            RXEN_OVERRIDE_VAL_15 : 1;
		unsigned int            TXPWR_OVERRIDE_EN_15 : 1;
		unsigned int           TXPWR_OVERRIDE_VAL_15 : 3;
		unsigned int            RXPWR_OVERRIDE_EN_15 : 1;
		unsigned int           RXPWR_OVERRIDE_VAL_15 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_1__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_1 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_1 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_1 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_1 : 3;
		unsigned int              RXEN_OVERRIDE_EN_1 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_1 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_1 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_1 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_1 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_1 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_2__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_2 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_2 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_2 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_2 : 3;
		unsigned int              RXEN_OVERRIDE_EN_2 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_2 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_2 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_2 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_2 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_2 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_3__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_3 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_3 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_3 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_3 : 3;
		unsigned int              RXEN_OVERRIDE_EN_3 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_3 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_3 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_3 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_3 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_3 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_4__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_4 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_4 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_4 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_4 : 3;
		unsigned int              RXEN_OVERRIDE_EN_4 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_4 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_4 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_4 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_4 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_4 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_5__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_5 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_5 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_5 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_5 : 3;
		unsigned int              RXEN_OVERRIDE_EN_5 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_5 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_5 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_5 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_5 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_5 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_6__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_6 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_6 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_6 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_6 : 3;
		unsigned int              RXEN_OVERRIDE_EN_6 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_6 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_6 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_6 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_6 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_6 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_7__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_7 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_7 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_7 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_7 : 3;
		unsigned int              RXEN_OVERRIDE_EN_7 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_7 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_7 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_7 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_7 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_7 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_8__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_8 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_8 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_8 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_8 : 3;
		unsigned int              RXEN_OVERRIDE_EN_8 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_8 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_8 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_8 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_8 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_8 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PDNB_OVERRIDE_9__CI {
	struct {
		unsigned int           TX_PDNB_OVERRIDE_EN_9 : 1;
		unsigned int          TX_PDNB_OVERRIDE_VAL_9 : 3;
		unsigned int           RX_PDNB_OVERRIDE_EN_9 : 1;
		unsigned int          RX_PDNB_OVERRIDE_VAL_9 : 3;
		unsigned int              RXEN_OVERRIDE_EN_9 : 1;
		unsigned int             RXEN_OVERRIDE_VAL_9 : 1;
		unsigned int             TXPWR_OVERRIDE_EN_9 : 1;
		unsigned int            TXPWR_OVERRIDE_VAL_9 : 3;
		unsigned int             RXPWR_OVERRIDE_EN_9 : 1;
		unsigned int            RXPWR_OVERRIDE_VAL_9 : 3;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PWRDOWN_0__CI {
	struct {
		unsigned int        TX_POWER_STATE_IN_TXS2_0 : 3;
		unsigned int             FORCE_RXEN_IN_L0s_0 : 1;
		unsigned int        RX_POWER_STATE_IN_RXS2_0 : 3;
		unsigned int       PLL_POWER_STATE_IN_TXS2_0 : 3;
		unsigned int        PLL_POWER_STATE_IN_OFF_0 : 3;
		unsigned int                                 : 3;
		unsigned int      TX2P5CLK_CLOCK_GATING_EN_0 : 1;
		unsigned int                                 : 7;
		unsigned int              PLL_RAMP_UP_TIME_0 : 3;
		unsigned int                                 : 1;
		unsigned int            PLLPWR_OVERRIDE_EN_0 : 1;
		unsigned int           PLLPWR_OVERRIDE_VAL_0 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PWRDOWN_1__CI {
	struct {
		unsigned int        TX_POWER_STATE_IN_TXS2_1 : 3;
		unsigned int             FORCE_RXEN_IN_L0s_1 : 1;
		unsigned int        RX_POWER_STATE_IN_RXS2_1 : 3;
		unsigned int       PLL_POWER_STATE_IN_TXS2_1 : 3;
		unsigned int        PLL_POWER_STATE_IN_OFF_1 : 3;
		unsigned int                                 : 3;
		unsigned int      TX2P5CLK_CLOCK_GATING_EN_1 : 1;
		unsigned int                                 : 7;
		unsigned int              PLL_RAMP_UP_TIME_1 : 3;
		unsigned int                                 : 1;
		unsigned int            PLLPWR_OVERRIDE_EN_1 : 1;
		unsigned int           PLLPWR_OVERRIDE_VAL_1 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PWRDOWN_2__CI {
	struct {
		unsigned int        TX_POWER_STATE_IN_TXS2_2 : 3;
		unsigned int             FORCE_RXEN_IN_L0s_2 : 1;
		unsigned int        RX_POWER_STATE_IN_RXS2_2 : 3;
		unsigned int       PLL_POWER_STATE_IN_TXS2_2 : 3;
		unsigned int        PLL_POWER_STATE_IN_OFF_2 : 3;
		unsigned int                                 : 3;
		unsigned int      TX2P5CLK_CLOCK_GATING_EN_2 : 1;
		unsigned int                                 : 7;
		unsigned int              PLL_RAMP_UP_TIME_2 : 3;
		unsigned int                                 : 1;
		unsigned int            PLLPWR_OVERRIDE_EN_2 : 1;
		unsigned int           PLLPWR_OVERRIDE_VAL_2 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_PWRDOWN_3__CI {
	struct {
		unsigned int        TX_POWER_STATE_IN_TXS2_3 : 3;
		unsigned int             FORCE_RXEN_IN_L0s_3 : 1;
		unsigned int        RX_POWER_STATE_IN_RXS2_3 : 3;
		unsigned int       PLL_POWER_STATE_IN_TXS2_3 : 3;
		unsigned int        PLL_POWER_STATE_IN_OFF_3 : 3;
		unsigned int                                 : 3;
		unsigned int      TX2P5CLK_CLOCK_GATING_EN_3 : 1;
		unsigned int                                 : 7;
		unsigned int              PLL_RAMP_UP_TIME_3 : 3;
		unsigned int                                 : 1;
		unsigned int            PLLPWR_OVERRIDE_EN_3 : 1;
		unsigned int           PLLPWR_OVERRIDE_VAL_3 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SCRATCH__CI__VI {
	struct {
                unsigned int                     PIF_SCRATCH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SC_CTL__CI {
	struct {
		unsigned int                  SC_CALIBRATION : 1;
		unsigned int                     SC_RXDETECT : 1;
		unsigned int               SC_EXIT_L1_TO_L0S : 1;
		unsigned int                SC_EXIT_L1_TO_L0 : 1;
		unsigned int            SC_ENTER_L1_FROM_L0S : 1;
		unsigned int             SC_ENTER_L1_FROM_L0 : 1;
		unsigned int                 SC_SPEED_CHANGE : 1;
		unsigned int                                 : 1;
		unsigned int                      SC_PHASE_1 : 1;
		unsigned int                      SC_PHASE_2 : 1;
		unsigned int                      SC_PHASE_3 : 1;
		unsigned int                      SC_PHASE_4 : 1;
		unsigned int                      SC_PHASE_5 : 1;
		unsigned int                      SC_PHASE_6 : 1;
		unsigned int                      SC_PHASE_7 : 1;
		unsigned int                      SC_PHASE_8 : 1;
		unsigned int                SC_LANE_0_RESUME : 1;
		unsigned int                SC_LANE_1_RESUME : 1;
		unsigned int                SC_LANE_2_RESUME : 1;
		unsigned int                SC_LANE_3_RESUME : 1;
		unsigned int                SC_LANE_4_RESUME : 1;
		unsigned int                SC_LANE_5_RESUME : 1;
		unsigned int                SC_LANE_6_RESUME : 1;
		unsigned int                SC_LANE_7_RESUME : 1;
		unsigned int                SC_LANE_8_RESUME : 1;
		unsigned int                SC_LANE_9_RESUME : 1;
		unsigned int               SC_LANE_10_RESUME : 1;
		unsigned int               SC_LANE_11_RESUME : 1;
		unsigned int               SC_LANE_12_RESUME : 1;
		unsigned int               SC_LANE_13_RESUME : 1;
		unsigned int               SC_LANE_14_RESUME : 1;
		unsigned int               SC_LANE_15_RESUME : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_0__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_0 : 1;
		unsigned int                  SEQ_RXDETECT_0 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_0 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_0 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_0 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_0 : 1;
		unsigned int              SEQ_SPEED_CHANGE_0 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_0 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_10__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_10 : 1;
		unsigned int                 SEQ_RXDETECT_10 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_10 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_10 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_10 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_10 : 1;
		unsigned int             SEQ_SPEED_CHANGE_10 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_10 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_11__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_11 : 1;
		unsigned int                 SEQ_RXDETECT_11 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_11 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_11 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_11 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_11 : 1;
		unsigned int             SEQ_SPEED_CHANGE_11 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_11 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_12__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_12 : 1;
		unsigned int                 SEQ_RXDETECT_12 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_12 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_12 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_12 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_12 : 1;
		unsigned int             SEQ_SPEED_CHANGE_12 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_12 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_13__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_13 : 1;
		unsigned int                 SEQ_RXDETECT_13 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_13 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_13 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_13 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_13 : 1;
		unsigned int             SEQ_SPEED_CHANGE_13 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_13 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_14__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_14 : 1;
		unsigned int                 SEQ_RXDETECT_14 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_14 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_14 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_14 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_14 : 1;
		unsigned int             SEQ_SPEED_CHANGE_14 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_14 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_15__CI {
	struct {
		unsigned int              SEQ_CALIBRATION_15 : 1;
		unsigned int                 SEQ_RXDETECT_15 : 1;
		unsigned int           SEQ_EXIT_L1_TO_L0S_15 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0_15 : 1;
		unsigned int        SEQ_ENTER_L1_FROM_L0S_15 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0_15 : 1;
		unsigned int             SEQ_SPEED_CHANGE_15 : 1;
		unsigned int                                 : 1;
		unsigned int                    SEQ_PHASE_15 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_1__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_1 : 1;
		unsigned int                  SEQ_RXDETECT_1 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_1 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_1 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_1 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_1 : 1;
		unsigned int              SEQ_SPEED_CHANGE_1 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_1 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_2__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_2 : 1;
		unsigned int                  SEQ_RXDETECT_2 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_2 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_2 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_2 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_2 : 1;
		unsigned int              SEQ_SPEED_CHANGE_2 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_2 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_3__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_3 : 1;
		unsigned int                  SEQ_RXDETECT_3 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_3 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_3 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_3 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_3 : 1;
		unsigned int              SEQ_SPEED_CHANGE_3 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_3 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_4__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_4 : 1;
		unsigned int                  SEQ_RXDETECT_4 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_4 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_4 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_4 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_4 : 1;
		unsigned int              SEQ_SPEED_CHANGE_4 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_4 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_5__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_5 : 1;
		unsigned int                  SEQ_RXDETECT_5 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_5 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_5 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_5 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_5 : 1;
		unsigned int              SEQ_SPEED_CHANGE_5 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_5 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_6__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_6 : 1;
		unsigned int                  SEQ_RXDETECT_6 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_6 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_6 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_6 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_6 : 1;
		unsigned int              SEQ_SPEED_CHANGE_6 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_6 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_7__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_7 : 1;
		unsigned int                  SEQ_RXDETECT_7 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_7 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_7 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_7 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_7 : 1;
		unsigned int              SEQ_SPEED_CHANGE_7 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_7 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_8__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_8 : 1;
		unsigned int                  SEQ_RXDETECT_8 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_8 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_8 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_8 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_8 : 1;
		unsigned int              SEQ_SPEED_CHANGE_8 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_8 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_SEQ_STATUS_9__CI {
	struct {
		unsigned int               SEQ_CALIBRATION_9 : 1;
		unsigned int                  SEQ_RXDETECT_9 : 1;
		unsigned int            SEQ_EXIT_L1_TO_L0S_9 : 1;
		unsigned int             SEQ_EXIT_L1_TO_L0_9 : 1;
		unsigned int         SEQ_ENTER_L1_FROM_L0S_9 : 1;
		unsigned int          SEQ_ENTER_L1_FROM_L0_9 : 1;
		unsigned int              SEQ_SPEED_CHANGE_9 : 1;
		unsigned int                                 : 1;
		unsigned int                     SEQ_PHASE_9 : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_TXPHYSTATUS__CI {
	struct {
		unsigned int                   TXPHYSTATUS_0 : 1;
		unsigned int                   TXPHYSTATUS_1 : 1;
		unsigned int                   TXPHYSTATUS_2 : 1;
		unsigned int                   TXPHYSTATUS_3 : 1;
		unsigned int                   TXPHYSTATUS_4 : 1;
		unsigned int                   TXPHYSTATUS_5 : 1;
		unsigned int                   TXPHYSTATUS_6 : 1;
		unsigned int                   TXPHYSTATUS_7 : 1;
		unsigned int                   TXPHYSTATUS_8 : 1;
		unsigned int                   TXPHYSTATUS_9 : 1;
		unsigned int                  TXPHYSTATUS_10 : 1;
		unsigned int                  TXPHYSTATUS_11 : 1;
		unsigned int                  TXPHYSTATUS_12 : 1;
		unsigned int                  TXPHYSTATUS_13 : 1;
		unsigned int                  TXPHYSTATUS_14 : 1;
		unsigned int                  TXPHYSTATUS_15 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC0_CTRL_REG0__CI__VI {
	struct {
                unsigned int         PLL_DBG_LC_ANALOG_SEL_0 : 2;
                unsigned int       PLL_DBG_LC_EXT_RESET_EN_0 : 1;
                unsigned int        PLL_DBG_LC_VCTL_ADC_EN_0 : 1;
                unsigned int         PLL_TST_LC_USAMPLE_EN_0 : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC0_OVRD_REG0__CI__VI {
	struct {
                unsigned int  PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 : 3;
                unsigned int   PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 : 1;
                unsigned int PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0 : 3;
                unsigned int PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 : 1;
                unsigned int PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 : 1;
                unsigned int PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 : 1;
                unsigned int     PLL_CFG_LC_FBDIV_OVRD_VAL_0 : 8;
                unsigned int      PLL_CFG_LC_FBDIV_OVRD_EN_0 : 1;
                unsigned int  PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 : 9;
                unsigned int   PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 : 1;
                unsigned int    PLL_CFG_LC_REFDIV_OVRD_VAL_0 : 2;
                unsigned int     PLL_CFG_LC_REFDIV_OVRD_EN_0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC0_OVRD_REG1__CI__VI {
	struct {
                unsigned int PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0 : 3;
                unsigned int PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 : 1;
                unsigned int PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 : 1;
                unsigned int  PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 : 1;
                unsigned int PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0 : 1;
                unsigned int PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 : 1;
                unsigned int         PLL_LC_PWRON_OVRD_VAL_0 : 1;
                unsigned int          PLL_LC_PWRON_OVRD_EN_0 : 1;
                unsigned int                                 : 4;
                unsigned int  PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 : 4;
                unsigned int   PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC0_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_LC0_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_LC0_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_LC0_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_LC0_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC0_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_LC0_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                  PLL_LC0_PLLPWR : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC1_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_LC1_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_LC1_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_LC1_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_LC1_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC1_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_LC1_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                  PLL_LC1_PLLPWR : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC2_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_LC2_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_LC2_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_LC2_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_LC2_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC2_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_LC2_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                  PLL_LC2_PLLPWR : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC3_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_LC3_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_LC3_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_LC3_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_LC3_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_LC3_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_LC3_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int                                 : 3;
		unsigned int                  PLL_LC3_PLLPWR : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO0_CTRL_REG0__CI__VI {
	struct {
                unsigned int         PLL_DBG_RO_ANALOG_SEL_0 : 2;
                unsigned int       PLL_DBG_RO_EXT_RESET_EN_0 : 1;
                unsigned int        PLL_DBG_RO_VCTL_ADC_EN_0 : 1;
                unsigned int           PLL_DBG_RO_LF_CNTRL_0 : 7;
                unsigned int         PLL_TST_RO_USAMPLE_EN_0 : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO0_OVRD_REG0__CI__VI {
	struct {
                unsigned int  PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 : 8;
                unsigned int   PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 : 1;
                unsigned int PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 : 3;
                unsigned int PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 : 1;
                unsigned int PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 : 1;
                unsigned int PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 : 1;
                unsigned int     PLL_CFG_RO_FBDIV_OVRD_VAL_0 : 13;
                unsigned int      PLL_CFG_RO_FBDIV_OVRD_EN_0 : 1;
                unsigned int                                 : 1;
                unsigned int PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0 : 1;
                unsigned int PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO0_OVRD_REG1__CI__VI {
	struct {
                unsigned int    PLL_CFG_RO_REFDIV_OVRD_VAL_0 : 5;
                unsigned int     PLL_CFG_RO_REFDIV_OVRD_EN_0 : 1;
                unsigned int  PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 : 2;
                unsigned int   PLL_CFG_RO_VCO_MODE_OVRD_EN_0 : 1;
                unsigned int PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 : 1;
                unsigned int  PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 : 1;
                unsigned int PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0 : 1;
                unsigned int PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 : 1;
                unsigned int         PLL_RO_PWRON_OVRD_VAL_0 : 1;
                unsigned int          PLL_RO_PWRON_OVRD_EN_0 : 1;
                unsigned int                                 : 4;
                unsigned int PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0 : 3;
                unsigned int PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 : 1;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO0_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_RO0_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_RO0_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO0_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_RO0_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO0_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_RO0_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int   PLL_RO0_IGNR_PLLFREQ_CBI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO0_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                 PLL_RO0_PLLFREQ : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO1_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_RO1_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_RO1_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO1_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_RO1_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO1_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_RO1_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int   PLL_RO1_IGNR_PLLFREQ_CBI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO1_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                 PLL_RO1_PLLFREQ : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO2_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_RO2_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_RO2_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO2_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_RO2_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO2_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_RO2_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int   PLL_RO2_IGNR_PLLFREQ_CBI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO2_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                 PLL_RO2_PLLFREQ : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO3_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int    PLL_RO3_IGNR_PLLPWR_SCI_UPDT : 1;
		unsigned int  PLL_RO3_IGNR_FREQMODE_SCI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO3_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                PLL_RO3_FREQMODE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO3_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int    PLL_RO3_IGNR_PLLPWR_CBI_UPDT : 1;
		unsigned int   PLL_RO3_IGNR_PLLFREQ_CBI_UPDT : 1;
		unsigned int                                 : 2;
		unsigned int                  PLL_RO3_PLLPWR : 3;
		unsigned int                                 : 1;
		unsigned int                 PLL_RO3_PLLFREQ : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO_GLB_CTRL_REG0__CI {
	struct {
		unsigned int            PLL_TST_LOSPDTST_SRC : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int      PLL_RO_PWRON_LUT_ENTRY_LS2 : 1;
		unsigned int      PLL_LC_PWRON_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int                                 : 1;
		unsigned int PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN : 1;
		unsigned int PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PLL_RO_GLB_CTRL_REG0__VI {
	struct {
		unsigned int            PLL_TST_LOSPDTST_SRC : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int      PLL_RO_PWRON_LUT_ENTRY_LS2 : 1;
		unsigned int      PLL_LC_PWRON_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1;
		unsigned int  PLL_RO_HSCLK_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_RO_HSCLK_RIGHT_EN_GATING_EN : 1;
		unsigned int  PLL_LC_HSCLK_LEFT_EN_GATING_EN : 1;
		unsigned int PLL_LC_HSCLK_RIGHT_EN_GATING_EN : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_CTRL_REG0__CI__VI {
	struct {
                unsigned int          RX_CFG_ADAPT_MODE_GEN1 : 10;
                unsigned int          RX_CFG_ADAPT_MODE_GEN2 : 10;
                unsigned int          RX_CFG_ADAPT_MODE_GEN3 : 10;
                unsigned int           RX_CFG_ADAPT_RST_MODE : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_CTRL_REG1__CI__VI {
	struct {
                unsigned int         RX_CFG_CDR_FR_GAIN_GEN1 : 4;
                unsigned int         RX_CFG_CDR_FR_GAIN_GEN2 : 4;
                unsigned int         RX_CFG_CDR_FR_GAIN_GEN3 : 4;
                unsigned int         RX_CFG_CDR_PH_GAIN_GEN1 : 4;
                unsigned int         RX_CFG_CDR_PH_GAIN_GEN2 : 4;
                unsigned int         RX_CFG_CDR_PH_GAIN_GEN3 : 4;
                unsigned int        RX_CFG_CDR_PI_STPSZ_GEN1 : 1;
                unsigned int        RX_CFG_CDR_PI_STPSZ_GEN2 : 1;
                unsigned int        RX_CFG_CDR_PI_STPSZ_GEN3 : 1;
                unsigned int   RX_CFG_LEQ_DCATTN_BYP_EN_GEN1 : 1;
                unsigned int   RX_CFG_LEQ_DCATTN_BYP_EN_GEN2 : 1;
                unsigned int   RX_CFG_LEQ_DCATTN_BYP_EN_GEN3 : 1;
                unsigned int    RX_ADAPT_HLD_ASRT_TO_DCLK_EN : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_CTRL_REG2__CI__VI {
	struct {
                unsigned int                                 : 12;
                unsigned int            RX_CFG_CDR_TIME_GEN1 : 4;
                unsigned int            RX_CFG_CDR_TIME_GEN2 : 4;
                unsigned int            RX_CFG_CDR_TIME_GEN3 : 4;
                unsigned int       RX_CFG_LEQ_LOOP_GAIN_GEN1 : 2;
                unsigned int       RX_CFG_LEQ_LOOP_GAIN_GEN2 : 2;
                unsigned int       RX_CFG_LEQ_LOOP_GAIN_GEN3 : 2;
                unsigned int    RX_DCLK_EN_ASRT_TO_ADAPT_HLD : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_CTRL_REG3__CI__VI {
	struct {
                unsigned int           RX_CFG_CDR_FR_EN_GEN1 : 1;
                unsigned int           RX_CFG_CDR_FR_EN_GEN2 : 1;
                unsigned int           RX_CFG_CDR_FR_EN_GEN3 : 1;
                unsigned int      RX_ADAPT_RST_MODE_GEN1__VI : 2;
                unsigned int      RX_ADAPT_RST_MODE_GEN2__VI : 2;
                unsigned int      RX_ADAPT_RST_MODE_GEN3__VI : 2;
                unsigned int       RX_ADAPT_RST_SUB_MODE__VI : 3;
                unsigned int       RX_L0_ENTRY_MODE_GEN1__VI : 2;
                unsigned int       RX_L0_ENTRY_MODE_GEN2__VI : 2;
                unsigned int       RX_L0_ENTRY_MODE_GEN3__VI : 2;
                unsigned int                                 : 2;
                unsigned int            RX_CFG_DFE_TIME_GEN1 : 4;
                unsigned int            RX_CFG_DFE_TIME_GEN2 : 4;
                unsigned int            RX_CFG_DFE_TIME_GEN3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_CTRL_REG4__CI__VI {
	struct {
                unsigned int             RX_CFG_FOM_BER_GEN1 : 3;
                unsigned int             RX_CFG_FOM_BER_GEN2 : 3;
                unsigned int             RX_CFG_FOM_BER_GEN3 : 3;
                unsigned int    RX_CFG_LEQ_POLE_BYP_VAL_GEN1 : 3;
                unsigned int    RX_CFG_LEQ_POLE_BYP_VAL_GEN2 : 3;
                unsigned int    RX_CFG_LEQ_POLE_BYP_VAL_GEN3 : 3;
                unsigned int                                 : 2;
                unsigned int            RX_CFG_FOM_TIME_GEN1 : 4;
                unsigned int            RX_CFG_FOM_TIME_GEN2 : 4;
                unsigned int            RX_CFG_FOM_TIME_GEN3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_CTRL_REG5__CI__VI {
	struct {
                unsigned int  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 : 5;
                unsigned int  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 : 5;
                unsigned int  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 : 5;
                unsigned int     RX_CFG_LEQ_POLE_BYP_EN_GEN1 : 1;
                unsigned int     RX_CFG_LEQ_POLE_BYP_EN_GEN2 : 1;
                unsigned int     RX_CFG_LEQ_POLE_BYP_EN_GEN3 : 1;
                unsigned int        RX_CFG_LEQ_SHUNT_EN_GEN1 : 1;
                unsigned int        RX_CFG_LEQ_SHUNT_EN_GEN2 : 1;
                unsigned int        RX_CFG_LEQ_SHUNT_EN_GEN3 : 1;
                unsigned int                                 : 6;
                unsigned int           RX_CFG_TERM_MODE_GEN1 : 1;
                unsigned int           RX_CFG_TERM_MODE_GEN2 : 1;
                unsigned int           RX_CFG_TERM_MODE_GEN3 : 1;
                unsigned int RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0 : 1;
                unsigned int     RX_ADAPT_AUX_PWRON_MODE__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_CTRL_REG6__CI__VI {
	struct {
                unsigned int            RX_CFG_LEQ_TIME_GEN1 : 4;
                unsigned int            RX_CFG_LEQ_TIME_GEN2 : 4;
                unsigned int            RX_CFG_LEQ_TIME_GEN3 : 4;
                unsigned int             RX_CFG_OC_TIME_GEN1 : 4;
                unsigned int             RX_CFG_OC_TIME_GEN2 : 4;
                unsigned int             RX_CFG_OC_TIME_GEN3 : 4;
                unsigned int RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0 : 1;
                unsigned int                                 : 1;
                unsigned int RX_FRONTEND_PWRON_LUT_ENTRY_LS2 : 1;
                unsigned int      RX_AUX_PWRON_LUT_ENTRY_LS2 : 1;
                unsigned int RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__VI : 1;
                unsigned int     RX_ADAPT_HLD_L1_DLL_OFF__VI : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_CTRL_REG7__CI {
	struct {
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN1 : 4;
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN2 : 4;
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN3 : 4;
		unsigned int RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 : 1;
		unsigned int        RX_DCLK_EN_LUT_ENTRY_LS2 : 1;
		unsigned int                                 : 3;
		unsigned int      RX_DLL_PWRON_LUT_ENTRY_LS2 : 1;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN1 : 3;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN2 : 3;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN3 : 3;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN1 : 1;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN2 : 1;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN3 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_CTRL_REG7__VI {
	struct {
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN1 : 4;
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN2 : 4;
		unsigned int        RX_CFG_TH_LOOP_GAIN_GEN3 : 4;
		unsigned int RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 : 1;
		unsigned int        RX_DCLK_EN_LUT_ENTRY_LS2 : 1;
		unsigned int       RX_DCLK_EN_AFTER_DLL_LOCK : 1;
		unsigned int                                 : 1;
		unsigned int      RX_DLL_PWRON_LUT_ENTRY_PS3 : 1;
		unsigned int      RX_DLL_PWRON_LUT_ENTRY_PS2 : 1;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN1 : 3;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN2 : 3;
		unsigned int         RX_CFG_DLL_CPI_SEL_GEN3 : 3;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN1 : 1;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN2 : 1;
		unsigned int   RX_CFG_DLL_FLOCK_DISABLE_GEN3 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_CTRL_REG8__CI__VI {
	struct {
                unsigned int            RX_DLL_LOCK_TIME__VI : 2;
                unsigned int RX_DLL_SPEEDCHANGE_RESET_TIME__VI : 2;
                unsigned int    RX_DLL_PWRON_IN_RAMPDOWN__VI : 1;
                unsigned int        RX_FSM_L0S_IF_RX_RDY__VI : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_OVRD_REG0__CI__VI {
	struct {
                unsigned int           RX_ADAPT_HLD_OVRD_VAL : 1;
                unsigned int            RX_ADAPT_HLD_OVRD_EN : 1;
                unsigned int           RX_ADAPT_RST_OVRD_VAL : 1;
                unsigned int            RX_ADAPT_RST_OVRD_EN : 1;
                unsigned int                                 : 2;
                unsigned int        RX_CFG_DCLK_DIV_OVRD_VAL : 2;
                unsigned int         RX_CFG_DCLK_DIV_OVRD_EN : 1;
                unsigned int   RX_CFG_DLL_FREQ_MODE_OVRD_VAL : 1;
                unsigned int    RX_CFG_DLL_FREQ_MODE_OVRD_EN : 1;
                unsigned int      RX_CFG_PLLCLK_SEL_OVRD_VAL : 1;
                unsigned int       RX_CFG_PLLCLK_SEL_OVRD_EN : 1;
                unsigned int        RX_CFG_RCLK_DIV_OVRD_VAL : 1;
                unsigned int         RX_CFG_RCLK_DIV_OVRD_EN : 1;
                unsigned int             RX_DCLK_EN_OVRD_VAL : 1;
                unsigned int              RX_DCLK_EN_OVRD_EN : 1;
                unsigned int           RX_DLL_PWRON_OVRD_VAL : 1;
                unsigned int            RX_DLL_PWRON_OVRD_EN : 1;
                unsigned int      RX_FRONTEND_PWRON_OVRD_VAL : 1;
                unsigned int       RX_FRONTEND_PWRON_OVRD_EN : 1;
                unsigned int       RX_IDLEDET_PWRON_OVRD_VAL : 1;
                unsigned int        RX_IDLEDET_PWRON_OVRD_EN : 1;
                unsigned int             RX_TERM_EN_OVRD_VAL : 1;
                unsigned int              RX_TERM_EN_OVRD_EN : 1;
                unsigned int                                 : 3;
                unsigned int           RX_AUX_PWRON_OVRD_VAL : 1;
                unsigned int            RX_AUX_PWRON_OVRD_EN : 1;
                unsigned int           RX_ADAPT_FOM_OVRD_VAL : 1;
                unsigned int            RX_ADAPT_FOM_OVRD_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_OVRD_REG1__CI__VI {
	struct {
                unsigned int           RX_ADAPT_TRK_OVRD_VAL : 1;
                unsigned int            RX_ADAPT_TRK_OVRD_EN : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int        IGNR_RXPWR_SCI_UPDT_L0T3 : 1;
		unsigned int        IGNR_RXPWR_SCI_UPDT_L4T7 : 1;
		unsigned int       IGNR_RXPWR_SCI_UPDT_L8T11 : 1;
		unsigned int      IGNR_RXPWR_SCI_UPDT_L12T15 : 1;
		unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3 : 1;
		unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15 : 1;
		unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L0T3 : 1;
		unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L12T15 : 1;
		unsigned int    IGNR_ENABLEFOM_SCI_UPDT_L0T3 : 1;
		unsigned int    IGNR_ENABLEFOM_SCI_UPDT_L4T7 : 1;
		unsigned int   IGNR_ENABLEFOM_SCI_UPDT_L8T11 : 1;
		unsigned int  IGNR_ENABLEFOM_SCI_UPDT_L12T15 : 1;
		unsigned int   IGNR_REQUESTFOM_SCI_UPDT_L0T3 : 1;
		unsigned int   IGNR_REQUESTFOM_SCI_UPDT_L4T7 : 1;
		unsigned int  IGNR_REQUESTFOM_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_REQUESTFOM_SCI_UPDT_L12T15 : 1;
		unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L0T3 : 1;
		unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L12T15 : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_GLB_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int        IGNR_RXPWR_CBI_UPDT_L0T3 : 1;
		unsigned int        IGNR_RXPWR_CBI_UPDT_L4T7 : 1;
		unsigned int       IGNR_RXPWR_CBI_UPDT_L8T11 : 1;
		unsigned int      IGNR_RXPWR_CBI_UPDT_L12T15 : 1;
		unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3 : 1;
		unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7 : 1;
		unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15 : 1;
		unsigned int   IGNR_REQUESTTRK_CBI_UPDT_L0T3 : 1;
		unsigned int   IGNR_REQUESTTRK_CBI_UPDT_L4T7 : 1;
		unsigned int  IGNR_REQUESTTRK_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_REQUESTTRK_CBI_UPDT_L12T15 : 1;
		unsigned int    IGNR_ENABLEFOM_CBI_UPDT_L0T3 : 1;
		unsigned int    IGNR_ENABLEFOM_CBI_UPDT_L4T7 : 1;
		unsigned int   IGNR_ENABLEFOM_CBI_UPDT_L8T11 : 1;
		unsigned int  IGNR_ENABLEFOM_CBI_UPDT_L12T15 : 1;
		unsigned int   IGNR_REQUESTFOM_CBI_UPDT_L0T3 : 1;
		unsigned int   IGNR_REQUESTFOM_CBI_UPDT_L4T7 : 1;
		unsigned int  IGNR_REQUESTFOM_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_REQUESTFOM_CBI_UPDT_L12T15 : 1;
		unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L0T3 : 1;
		unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L4T7 : 1;
		unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L12T15 : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE0_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_0 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_0 : 2;
                unsigned int               RX_TST_BSCAN_EN_0 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_0 : 1;
                unsigned int                RX_TERM_EN_0__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE0_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_0 : 3;
		unsigned int                 ELECIDLEDETEN_0 : 1;
		unsigned int                  RXPRESETHINT_0 : 3;
		unsigned int                     ENABLEFOM_0 : 1;
		unsigned int                    REQUESTFOM_0 : 1;
		unsigned int                  RESPONSEMODE_0 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE0_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_0 : 3;
		unsigned int                 ELECIDLEDETEN_0 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_0 : 1;
		unsigned int                     ENABLEFOM_0 : 1;
		unsigned int                    REQUESTFOM_0 : 1;
		unsigned int                  RESPONSEMODE_0 : 1;
		unsigned int                      RXEYEFOM_0 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE10_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_10 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_10 : 2;
                unsigned int              RX_TST_BSCAN_EN_10 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_10 : 1;
                unsigned int               RX_TERM_EN_10__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE10_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_10 : 3;
		unsigned int                ELECIDLEDETEN_10 : 1;
		unsigned int                 RXPRESETHINT_10 : 3;
		unsigned int                    ENABLEFOM_10 : 1;
		unsigned int                   REQUESTFOM_10 : 1;
		unsigned int                 RESPONSEMODE_10 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE10_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_10 : 3;
		unsigned int                ELECIDLEDETEN_10 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_10 : 1;
		unsigned int                    ENABLEFOM_10 : 1;
		unsigned int                   REQUESTFOM_10 : 1;
		unsigned int                 RESPONSEMODE_10 : 1;
		unsigned int                     RXEYEFOM_10 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE11_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_11 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_11 : 2;
                unsigned int              RX_TST_BSCAN_EN_11 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_11 : 1;
                unsigned int               RX_TERM_EN_11__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE11_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_11 : 3;
		unsigned int                ELECIDLEDETEN_11 : 1;
		unsigned int                 RXPRESETHINT_11 : 3;
		unsigned int                    ENABLEFOM_11 : 1;
		unsigned int                   REQUESTFOM_11 : 1;
		unsigned int                 RESPONSEMODE_11 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE11_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_11 : 3;
		unsigned int                ELECIDLEDETEN_11 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_11 : 1;
		unsigned int                    ENABLEFOM_11 : 1;
		unsigned int                   REQUESTFOM_11 : 1;
		unsigned int                 RESPONSEMODE_11 : 1;
		unsigned int                     RXEYEFOM_11 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE12_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_12 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_12 : 2;
                unsigned int              RX_TST_BSCAN_EN_12 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_12 : 1;
                unsigned int               RX_TERM_EN_12__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE12_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_12 : 3;
		unsigned int                ELECIDLEDETEN_12 : 1;
		unsigned int                 RXPRESETHINT_12 : 3;
		unsigned int                    ENABLEFOM_12 : 1;
		unsigned int                   REQUESTFOM_12 : 1;
		unsigned int                 RESPONSEMODE_12 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE12_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_12 : 3;
		unsigned int                ELECIDLEDETEN_12 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_12 : 1;
		unsigned int                    ENABLEFOM_12 : 1;
		unsigned int                   REQUESTFOM_12 : 1;
		unsigned int                 RESPONSEMODE_12 : 1;
		unsigned int                     RXEYEFOM_12 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE13_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_13 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_13 : 2;
                unsigned int              RX_TST_BSCAN_EN_13 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_13 : 1;
                unsigned int               RX_TERM_EN_13__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE13_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_13 : 3;
		unsigned int                ELECIDLEDETEN_13 : 1;
		unsigned int                 RXPRESETHINT_13 : 3;
		unsigned int                    ENABLEFOM_13 : 1;
		unsigned int                   REQUESTFOM_13 : 1;
		unsigned int                 RESPONSEMODE_13 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE13_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_13 : 3;
		unsigned int                ELECIDLEDETEN_13 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_13 : 1;
		unsigned int                    ENABLEFOM_13 : 1;
		unsigned int                   REQUESTFOM_13 : 1;
		unsigned int                 RESPONSEMODE_13 : 1;
		unsigned int                     RXEYEFOM_13 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE14_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_14 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_14 : 2;
                unsigned int              RX_TST_BSCAN_EN_14 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_14 : 1;
                unsigned int               RX_TERM_EN_14__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE14_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_14 : 3;
		unsigned int                ELECIDLEDETEN_14 : 1;
		unsigned int                 RXPRESETHINT_14 : 3;
		unsigned int                    ENABLEFOM_14 : 1;
		unsigned int                   REQUESTFOM_14 : 1;
		unsigned int                 RESPONSEMODE_14 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE14_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_14 : 3;
		unsigned int                ELECIDLEDETEN_14 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_14 : 1;
		unsigned int                    ENABLEFOM_14 : 1;
		unsigned int                   REQUESTFOM_14 : 1;
		unsigned int                 RESPONSEMODE_14 : 1;
		unsigned int                     RXEYEFOM_14 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE15_CTRL_REG0__CI__VI {
	struct {
                unsigned int                    RX_BACKUP_15 : 8;
                unsigned int                                 : 2;
                unsigned int            RX_DBG_ANALOG_SEL_15 : 2;
                unsigned int              RX_TST_BSCAN_EN_15 : 1;
                unsigned int             RX_CFG_OVR_PWRSF_15 : 1;
                unsigned int               RX_TERM_EN_15__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE15_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                        RXPWR_15 : 3;
		unsigned int                ELECIDLEDETEN_15 : 1;
		unsigned int                 RXPRESETHINT_15 : 3;
		unsigned int                    ENABLEFOM_15 : 1;
		unsigned int                   REQUESTFOM_15 : 1;
		unsigned int                 RESPONSEMODE_15 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE15_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                        RXPWR_15 : 3;
		unsigned int                ELECIDLEDETEN_15 : 1;
		unsigned int                                 : 2;
		unsigned int                   REQUESTTRK_15 : 1;
		unsigned int                    ENABLEFOM_15 : 1;
		unsigned int                   REQUESTFOM_15 : 1;
		unsigned int                 RESPONSEMODE_15 : 1;
		unsigned int                     RXEYEFOM_15 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE1_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_1 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_1 : 2;
                unsigned int               RX_TST_BSCAN_EN_1 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_1 : 1;
                unsigned int                RX_TERM_EN_1__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE1_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_1 : 3;
		unsigned int                 ELECIDLEDETEN_1 : 1;
		unsigned int                  RXPRESETHINT_1 : 3;
		unsigned int                     ENABLEFOM_1 : 1;
		unsigned int                    REQUESTFOM_1 : 1;
		unsigned int                  RESPONSEMODE_1 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE1_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_1 : 3;
		unsigned int                 ELECIDLEDETEN_1 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_1 : 1;
		unsigned int                     ENABLEFOM_1 : 1;
		unsigned int                    REQUESTFOM_1 : 1;
		unsigned int                  RESPONSEMODE_1 : 1;
		unsigned int                      RXEYEFOM_1 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE2_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_2 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_2 : 2;
                unsigned int               RX_TST_BSCAN_EN_2 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_2 : 1;
                unsigned int                RX_TERM_EN_2__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE2_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_2 : 3;
		unsigned int                 ELECIDLEDETEN_2 : 1;
		unsigned int                  RXPRESETHINT_2 : 3;
		unsigned int                     ENABLEFOM_2 : 1;
		unsigned int                    REQUESTFOM_2 : 1;
		unsigned int                  RESPONSEMODE_2 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE2_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_2 : 3;
		unsigned int                 ELECIDLEDETEN_2 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_2 : 1;
		unsigned int                     ENABLEFOM_2 : 1;
		unsigned int                    REQUESTFOM_2 : 1;
		unsigned int                  RESPONSEMODE_2 : 1;
		unsigned int                      RXEYEFOM_2 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE3_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_3 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_3 : 2;
                unsigned int               RX_TST_BSCAN_EN_3 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_3 : 1;
                unsigned int                RX_TERM_EN_3__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE3_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_3 : 3;
		unsigned int                 ELECIDLEDETEN_3 : 1;
		unsigned int                  RXPRESETHINT_3 : 3;
		unsigned int                     ENABLEFOM_3 : 1;
		unsigned int                    REQUESTFOM_3 : 1;
		unsigned int                  RESPONSEMODE_3 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE3_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_3 : 3;
		unsigned int                 ELECIDLEDETEN_3 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_3 : 1;
		unsigned int                     ENABLEFOM_3 : 1;
		unsigned int                    REQUESTFOM_3 : 1;
		unsigned int                  RESPONSEMODE_3 : 1;
		unsigned int                      RXEYEFOM_3 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE4_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_4 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_4 : 2;
                unsigned int               RX_TST_BSCAN_EN_4 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_4 : 1;
                unsigned int                RX_TERM_EN_4__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE4_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_4 : 3;
		unsigned int                 ELECIDLEDETEN_4 : 1;
		unsigned int                  RXPRESETHINT_4 : 3;
		unsigned int                     ENABLEFOM_4 : 1;
		unsigned int                    REQUESTFOM_4 : 1;
		unsigned int                  RESPONSEMODE_4 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE4_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_4 : 3;
		unsigned int                 ELECIDLEDETEN_4 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_4 : 1;
		unsigned int                     ENABLEFOM_4 : 1;
		unsigned int                    REQUESTFOM_4 : 1;
		unsigned int                  RESPONSEMODE_4 : 1;
		unsigned int                      RXEYEFOM_4 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE5_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_5 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_5 : 2;
                unsigned int               RX_TST_BSCAN_EN_5 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_5 : 1;
                unsigned int                RX_TERM_EN_5__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE5_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_5 : 3;
		unsigned int                 ELECIDLEDETEN_5 : 1;
		unsigned int                  RXPRESETHINT_5 : 3;
		unsigned int                     ENABLEFOM_5 : 1;
		unsigned int                    REQUESTFOM_5 : 1;
		unsigned int                  RESPONSEMODE_5 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE5_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_5 : 3;
		unsigned int                 ELECIDLEDETEN_5 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_5 : 1;
		unsigned int                     ENABLEFOM_5 : 1;
		unsigned int                    REQUESTFOM_5 : 1;
		unsigned int                  RESPONSEMODE_5 : 1;
		unsigned int                      RXEYEFOM_5 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE6_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_6 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_6 : 2;
                unsigned int               RX_TST_BSCAN_EN_6 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_6 : 1;
                unsigned int                RX_TERM_EN_6__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE6_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_6 : 3;
		unsigned int                 ELECIDLEDETEN_6 : 1;
		unsigned int                  RXPRESETHINT_6 : 3;
		unsigned int                     ENABLEFOM_6 : 1;
		unsigned int                    REQUESTFOM_6 : 1;
		unsigned int                  RESPONSEMODE_6 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE6_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_6 : 3;
		unsigned int                 ELECIDLEDETEN_6 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_6 : 1;
		unsigned int                     ENABLEFOM_6 : 1;
		unsigned int                    REQUESTFOM_6 : 1;
		unsigned int                  RESPONSEMODE_6 : 1;
		unsigned int                      RXEYEFOM_6 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE7_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_7 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_7 : 2;
                unsigned int               RX_TST_BSCAN_EN_7 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_7 : 1;
                unsigned int                RX_TERM_EN_7__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE7_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_7 : 3;
		unsigned int                 ELECIDLEDETEN_7 : 1;
		unsigned int                  RXPRESETHINT_7 : 3;
		unsigned int                     ENABLEFOM_7 : 1;
		unsigned int                    REQUESTFOM_7 : 1;
		unsigned int                  RESPONSEMODE_7 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE7_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_7 : 3;
		unsigned int                 ELECIDLEDETEN_7 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_7 : 1;
		unsigned int                     ENABLEFOM_7 : 1;
		unsigned int                    REQUESTFOM_7 : 1;
		unsigned int                  RESPONSEMODE_7 : 1;
		unsigned int                      RXEYEFOM_7 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE8_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_8 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_8 : 2;
                unsigned int               RX_TST_BSCAN_EN_8 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_8 : 1;
                unsigned int                RX_TERM_EN_8__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE8_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_8 : 3;
		unsigned int                 ELECIDLEDETEN_8 : 1;
		unsigned int                  RXPRESETHINT_8 : 3;
		unsigned int                     ENABLEFOM_8 : 1;
		unsigned int                    REQUESTFOM_8 : 1;
		unsigned int                  RESPONSEMODE_8 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE8_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_8 : 3;
		unsigned int                 ELECIDLEDETEN_8 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_8 : 1;
		unsigned int                     ENABLEFOM_8 : 1;
		unsigned int                    REQUESTFOM_8 : 1;
		unsigned int                  RESPONSEMODE_8 : 1;
		unsigned int                      RXEYEFOM_8 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE9_CTRL_REG0__CI__VI {
	struct {
                unsigned int                     RX_BACKUP_9 : 8;
                unsigned int                                 : 2;
                unsigned int             RX_DBG_ANALOG_SEL_9 : 2;
                unsigned int               RX_TST_BSCAN_EN_9 : 1;
                unsigned int              RX_CFG_OVR_PWRSF_9 : 1;
                unsigned int                RX_TERM_EN_9__VI : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE9_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int                         RXPWR_9 : 3;
		unsigned int                 ELECIDLEDETEN_9 : 1;
		unsigned int                  RXPRESETHINT_9 : 3;
		unsigned int                     ENABLEFOM_9 : 1;
		unsigned int                    REQUESTFOM_9 : 1;
		unsigned int                  RESPONSEMODE_9 : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_RX_LANE9_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int                         RXPWR_9 : 3;
		unsigned int                 ELECIDLEDETEN_9 : 1;
		unsigned int                                 : 2;
		unsigned int                    REQUESTTRK_9 : 1;
		unsigned int                     ENABLEFOM_9 : 1;
		unsigned int                    REQUESTFOM_9 : 1;
		unsigned int                  RESPONSEMODE_9 : 1;
		unsigned int                      RXEYEFOM_9 : 8;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_STRAP_GLB_REG0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int           STRAP_QUICK_SIM_START : 1;
                unsigned int        STRAP_DFT_RXBSCAN_EN_VAL : 1;
                unsigned int          STRAP_DFT_CALIB_BYPASS : 1;
                unsigned int       STRAP_FORCE_LC_PLL_ON__VI : 1;
                unsigned int            STRAP_CFG_IDLEDET_TH : 2;
                unsigned int STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL : 5;
                unsigned int          STRAP_RX_CFG_OVR_PWRSF : 1;
                unsigned int            STRAP_RX_TRK_MODE_0_ : 1;
                unsigned int              STRAP_PWRGOOD_OVRD : 1;
                unsigned int    STRAP_DBG_RXDLL_VREG_REF_SEL : 1;
                unsigned int       STRAP_PLL_CFG_LC_VCO_TUNE : 4;
                unsigned int STRAP_DBG_RXRDATA_GATING_DISABLE : 1;
                unsigned int   STRAP_DBG_RXPI_OFFSET_BYP_VAL : 4;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_STRAP_PIN_REG0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int              STRAP_TX_DEEMPH_EN : 1;
                unsigned int             STRAP_TX_FULL_SWING : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_STRAP_PLL_REG0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int       STRAP_PLL_CFG_LC_BW_CNTRL : 3;
                unsigned int       STRAP_PLL_CFG_LC_LF_CNTRL : 9;
                unsigned int           STRAP_TX_RXDET_X1_SSF : 1;
                unsigned int                                 : 1;
                unsigned int STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS : 1;
                unsigned int       STRAP_PLL_CFG_RO_BW_CNTRL : 8;
                unsigned int             STRAP_PLL_STRAP_SEL : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_STRAP_RX_REG0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int       STRAP_RX_CFG_TH_LOOP_GAIN : 4;
                unsigned int  STRAP_RX_CFG_DLL_FLOCK_DISABLE : 1;
                unsigned int    STRAP_DBG_RXPI_OFFSET_BYP_EN : 1;
                unsigned int STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS : 1;
                unsigned int   STRAP_BG_CFG_LC_REG_VREF0_SEL : 2;
                unsigned int   STRAP_BG_CFG_LC_REG_VREF1_SEL : 2;
                unsigned int           STRAP_RX_CFG_CDR_TIME : 4;
                unsigned int           STRAP_RX_CFG_FOM_TIME : 4;
                unsigned int           STRAP_RX_CFG_LEQ_TIME : 4;
                unsigned int            STRAP_RX_CFG_OC_TIME : 4;
                unsigned int       STRAP_TX_CFG_RPTR_RST_VAL : 3;
                unsigned int          STRAP_RX_CFG_TERM_MODE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_STRAP_RX_REG1__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int       STRAP_RX_CFG_CDR_PI_STPSZ : 1;
                unsigned int      STRAP_TX_DEEMPH_PRSHT_STNG : 3;
                unsigned int    STRAP_BG_CFG_RO_REG_VREF_SEL : 2;
                unsigned int   STRAP_RX_CFG_LEQ_POLE_BYP_DIS : 1;
                unsigned int   STRAP_RX_CFG_LEQ_POLE_BYP_VAL : 3;
                unsigned int        STRAP_RX_CFG_CDR_PH_GAIN : 4;
                unsigned int         STRAP_RX_CFG_ADAPT_MODE : 10;
                unsigned int           STRAP_RX_CFG_DFE_TIME : 4;
                unsigned int      STRAP_RX_CFG_LEQ_LOOP_GAIN : 2;
                unsigned int      STRAP_RX_CFG_LEQ_SHUNT_DIS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_STRAP_TX_REG0__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int            STRAP_TX_CFG_DRV0_EN : 4;
                unsigned int       STRAP_TX_CFG_DRV0_TAP_SEL : 4;
                unsigned int            STRAP_TX_CFG_DRV1_EN : 5;
                unsigned int       STRAP_TX_CFG_DRV1_TAP_SEL : 5;
                unsigned int            STRAP_TX_CFG_DRV2_EN : 4;
                unsigned int       STRAP_TX_CFG_DRV2_TAP_SEL : 4;
                unsigned int            STRAP_TX_CFG_DRVX_EN : 1;
                unsigned int       STRAP_TX_CFG_DRVX_TAP_SEL : 1;
                unsigned int            STRAP_RX_TRK_MODE_1_ : 1;
                unsigned int     STRAP_TX_CFG_SWING_BOOST_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI {
	struct {
                unsigned int                  ACCEPT_ENTRY_0 : 1;
                unsigned int                  ACCEPT_ENTRY_1 : 1;
                unsigned int                  ACCEPT_ENTRY_2 : 1;
                unsigned int                  ACCEPT_ENTRY_3 : 1;
                unsigned int                  ACCEPT_ENTRY_4 : 1;
                unsigned int                  ACCEPT_ENTRY_5 : 1;
                unsigned int                  ACCEPT_ENTRY_6 : 1;
                unsigned int                  ACCEPT_ENTRY_7 : 1;
                unsigned int                  ACCEPT_ENTRY_8 : 1;
                unsigned int                  ACCEPT_ENTRY_9 : 1;
                unsigned int                 ACCEPT_ENTRY_10 : 1;
                unsigned int                 ACCEPT_ENTRY_11 : 1;
                unsigned int                 ACCEPT_ENTRY_12 : 1;
                unsigned int                 ACCEPT_ENTRY_13 : 1;
                unsigned int                 ACCEPT_ENTRY_14 : 1;
                unsigned int                 ACCEPT_ENTRY_15 : 1;
                unsigned int                 ACCEPT_ENTRY_16 : 1;
                unsigned int                 ACCEPT_ENTRY_17 : 1;
                unsigned int                 ACCEPT_ENTRY_18 : 1;
                unsigned int                 ACCEPT_ENTRY_19 : 1;
                unsigned int                 ACCEPT_ENTRY_20 : 1;
                unsigned int                 ACCEPT_ENTRY_21 : 1;
                unsigned int                 ACCEPT_ENTRY_22 : 1;
                unsigned int                 ACCEPT_ENTRY_23 : 1;
                unsigned int                 ACCEPT_ENTRY_24 : 1;
                unsigned int                 ACCEPT_ENTRY_25 : 1;
                unsigned int                 ACCEPT_ENTRY_26 : 1;
                unsigned int                 ACCEPT_ENTRY_27 : 1;
                unsigned int                 ACCEPT_ENTRY_28 : 1;
                unsigned int                 ACCEPT_ENTRY_29 : 1;
                unsigned int                 ACCEPT_ENTRY_30 : 1;
                unsigned int                 ACCEPT_ENTRY_31 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI {
	struct {
                unsigned int                 ACCEPT_ENTRY_32 : 1;
                unsigned int                 ACCEPT_ENTRY_33 : 1;
                unsigned int                 ACCEPT_ENTRY_34 : 1;
                unsigned int                 ACCEPT_ENTRY_35 : 1;
                unsigned int                 ACCEPT_ENTRY_36 : 1;
                unsigned int                 ACCEPT_ENTRY_37 : 1;
                unsigned int                 ACCEPT_ENTRY_38 : 1;
                unsigned int                 ACCEPT_ENTRY_39 : 1;
                unsigned int                 ACCEPT_ENTRY_40 : 1;
                unsigned int                 ACCEPT_ENTRY_41 : 1;
                unsigned int                 ACCEPT_ENTRY_42 : 1;
                unsigned int                 ACCEPT_ENTRY_43 : 1;
                unsigned int                 ACCEPT_ENTRY_44 : 1;
                unsigned int                 ACCEPT_ENTRY_45 : 1;
                unsigned int                 ACCEPT_ENTRY_46 : 1;
                unsigned int                 ACCEPT_ENTRY_47 : 1;
                unsigned int                 ACCEPT_ENTRY_48 : 1;
                unsigned int                 ACCEPT_ENTRY_49 : 1;
                unsigned int                 ACCEPT_ENTRY_50 : 1;
                unsigned int                 ACCEPT_ENTRY_51 : 1;
                unsigned int                 ACCEPT_ENTRY_52 : 1;
                unsigned int                 ACCEPT_ENTRY_53 : 1;
                unsigned int                 ACCEPT_ENTRY_54 : 1;
                unsigned int                 ACCEPT_ENTRY_55 : 1;
                unsigned int                 ACCEPT_ENTRY_56 : 1;
                unsigned int                 ACCEPT_ENTRY_57 : 1;
                unsigned int                 ACCEPT_ENTRY_58 : 1;
                unsigned int                 ACCEPT_ENTRY_59 : 1;
                unsigned int                 ACCEPT_ENTRY_60 : 1;
                unsigned int                 ACCEPT_ENTRY_61 : 1;
                unsigned int                 ACCEPT_ENTRY_62 : 1;
                unsigned int                 ACCEPT_ENTRY_63 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI {
	struct {
                unsigned int                 ACCEPT_ENTRY_64 : 1;
                unsigned int                 ACCEPT_ENTRY_65 : 1;
                unsigned int                 ACCEPT_ENTRY_66 : 1;
                unsigned int                 ACCEPT_ENTRY_67 : 1;
                unsigned int                 ACCEPT_ENTRY_68 : 1;
                unsigned int                 ACCEPT_ENTRY_69 : 1;
                unsigned int                 ACCEPT_ENTRY_70 : 1;
                unsigned int                 ACCEPT_ENTRY_71 : 1;
                unsigned int                 ACCEPT_ENTRY_72 : 1;
                unsigned int                 ACCEPT_ENTRY_73 : 1;
                unsigned int                 ACCEPT_ENTRY_74 : 1;
                unsigned int                 ACCEPT_ENTRY_75 : 1;
                unsigned int                 ACCEPT_ENTRY_76 : 1;
                unsigned int                 ACCEPT_ENTRY_77 : 1;
                unsigned int                 ACCEPT_ENTRY_78 : 1;
                unsigned int                 ACCEPT_ENTRY_79 : 1;
                unsigned int                 ACCEPT_ENTRY_80 : 1;
                unsigned int                 ACCEPT_ENTRY_81 : 1;
                unsigned int                 ACCEPT_ENTRY_82 : 1;
                unsigned int                 ACCEPT_ENTRY_83 : 1;
                unsigned int                 ACCEPT_ENTRY_84 : 1;
                unsigned int                 ACCEPT_ENTRY_85 : 1;
                unsigned int                 ACCEPT_ENTRY_86 : 1;
                unsigned int                 ACCEPT_ENTRY_87 : 1;
                unsigned int                 ACCEPT_ENTRY_88 : 1;
                unsigned int                 ACCEPT_ENTRY_89 : 1;
                unsigned int                 ACCEPT_ENTRY_90 : 1;
                unsigned int                 ACCEPT_ENTRY_91 : 1;
                unsigned int                 ACCEPT_ENTRY_92 : 1;
                unsigned int                 ACCEPT_ENTRY_93 : 1;
                unsigned int                 ACCEPT_ENTRY_94 : 1;
                unsigned int                 ACCEPT_ENTRY_95 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI {
	struct {
                unsigned int                 ACCEPT_ENTRY_96 : 1;
                unsigned int                 ACCEPT_ENTRY_97 : 1;
                unsigned int                 ACCEPT_ENTRY_98 : 1;
                unsigned int                 ACCEPT_ENTRY_99 : 1;
                unsigned int                ACCEPT_ENTRY_100 : 1;
                unsigned int                ACCEPT_ENTRY_101 : 1;
                unsigned int                ACCEPT_ENTRY_102 : 1;
                unsigned int                ACCEPT_ENTRY_103 : 1;
                unsigned int                ACCEPT_ENTRY_104 : 1;
                unsigned int                ACCEPT_ENTRY_105 : 1;
                unsigned int                ACCEPT_ENTRY_106 : 1;
                unsigned int                ACCEPT_ENTRY_107 : 1;
                unsigned int                ACCEPT_ENTRY_108 : 1;
                unsigned int                ACCEPT_ENTRY_109 : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_CTRL_REG0__CI {
	struct {
		unsigned int        TX_DRV_DATA_ASRT_DLY_VAL : 3;
		unsigned int        TX_DRV_DATA_DSRT_DLY_VAL : 3;
		unsigned int                                 : 2;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN1 : 3;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN2 : 3;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN3 : 3;
		unsigned int                 TX_STAGGER_CTRL : 2;
		unsigned int              TX_DATA_CLK_GATING : 1;
		unsigned int          TX_PRESET_TABLE_BYPASS : 1;
		unsigned int               TX_COEFF_ROUND_EN : 1;
		unsigned int          TX_COEFF_ROUND_DIR_VER : 1;
		unsigned int        TX_DCLK_EN_LSX_ALWAYS_ON : 1;
		unsigned int        TX_FRONTEND_PWRON_IN_OFF : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_CTRL_REG0__VI {
	struct {
		unsigned int        TX_DRV_DATA_ASRT_DLY_VAL : 3;
		unsigned int        TX_DRV_DATA_DSRT_DLY_VAL : 3;
		unsigned int                                 : 2;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN1 : 3;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN2 : 3;
		unsigned int        TX_CFG_RPTR_RST_VAL_GEN3 : 3;
		unsigned int                 TX_STAGGER_CTRL : 2;
		unsigned int              TX_DATA_CLK_GATING : 1;
		unsigned int          TX_PRESET_TABLE_BYPASS : 1;
		unsigned int               TX_COEFF_ROUND_EN : 1;
		unsigned int          TX_COEFF_ROUND_DIR_VER : 1;
		unsigned int        TX_DCLK_EN_LSX_ALWAYS_ON : 1;
		unsigned int        TX_FRONTEND_PWRON_IN_PS4 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_LANE_SKEW_CTRL__CI__VI {
	struct {
                unsigned int             TX_CFG_GROUPX1_EN_0 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_1 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_2 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_3 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_4 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_5 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_6 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_7 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_8 : 1;
                unsigned int             TX_CFG_GROUPX1_EN_9 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_10 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_11 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_12 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_13 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_14 : 1;
                unsigned int            TX_CFG_GROUPX1_EN_15 : 1;
                unsigned int          TX_CFG_GROUPX2_EN_L0T1 : 1;
                unsigned int          TX_CFG_GROUPX2_EN_L2T3 : 1;
                unsigned int          TX_CFG_GROUPX2_EN_L4T5 : 1;
                unsigned int          TX_CFG_GROUPX2_EN_L6T7 : 1;
                unsigned int          TX_CFG_GROUPX2_EN_L8T9 : 1;
                unsigned int        TX_CFG_GROUPX2_EN_L10T11 : 1;
                unsigned int        TX_CFG_GROUPX2_EN_L12T13 : 1;
                unsigned int        TX_CFG_GROUPX2_EN_L14T15 : 1;
                unsigned int          TX_CFG_GROUPX4_EN_L0T3 : 1;
                unsigned int          TX_CFG_GROUPX4_EN_L4T7 : 1;
                unsigned int         TX_CFG_GROUPX4_EN_L8T11 : 1;
                unsigned int        TX_CFG_GROUPX4_EN_L12T15 : 1;
                unsigned int          TX_CFG_GROUPX8_EN_L0T7 : 1;
                unsigned int         TX_CFG_GROUPX8_EN_L8T15 : 1;
                unsigned int        TX_CFG_GROUPX16_EN_L0T15 : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_OVRD_REG0__CI__VI {
	struct {
                unsigned int        TX_CFG_DCLK_DIV_OVRD_VAL : 3;
                unsigned int         TX_CFG_DCLK_DIV_OVRD_EN : 1;
                unsigned int    TX_CFG_DRV0_EN_GEN1_OVRD_VAL : 4;
                unsigned int          TX_CFG_DRV0_EN_OVRD_EN : 1;
                unsigned int TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL : 4;
                unsigned int     TX_CFG_DRV0_TAP_SEL_OVRD_EN : 1;
                unsigned int    TX_CFG_DRV1_EN_GEN1_OVRD_VAL : 5;
                unsigned int          TX_CFG_DRV1_EN_OVRD_EN : 1;
                unsigned int TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL : 5;
                unsigned int     TX_CFG_DRV1_TAP_SEL_OVRD_EN : 1;
                unsigned int    TX_CFG_DRV2_EN_GEN1_OVRD_VAL : 4;
                unsigned int          TX_CFG_DRV2_EN_OVRD_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_OVRD_REG1__CI__VI {
	struct {
                unsigned int TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL : 4;
                unsigned int     TX_CFG_DRV2_TAP_SEL_OVRD_EN : 1;
                unsigned int    TX_CFG_DRVX_EN_GEN1_OVRD_VAL : 1;
                unsigned int          TX_CFG_DRVX_EN_OVRD_EN : 1;
                unsigned int TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL : 1;
                unsigned int     TX_CFG_DRVX_TAP_SEL_OVRD_EN : 1;
                unsigned int      TX_CFG_PLLCLK_SEL_OVRD_VAL : 1;
                unsigned int       TX_CFG_PLLCLK_SEL_OVRD_EN : 1;
                unsigned int        TX_CFG_TCLK_DIV_OVRD_VAL : 1;
                unsigned int         TX_CFG_TCLK_DIV_OVRD_EN : 1;
                unsigned int            TX_CMDET_EN_OVRD_VAL : 1;
                unsigned int             TX_CMDET_EN_OVRD_EN : 1;
                unsigned int             TX_DATA_IN_OVRD_VAL : 10;
                unsigned int              TX_DATA_IN_OVRD_EN : 1;
                unsigned int           TX_RPTR_RSTN_OVRD_VAL : 1;
                unsigned int            TX_RPTR_RSTN_OVRD_EN : 1;
                unsigned int            TX_RXDET_EN_OVRD_VAL : 1;
                unsigned int             TX_RXDET_EN_OVRD_EN : 1;
                unsigned int           TX_WPTR_RSTN_OVRD_VAL : 1;
                unsigned int            TX_WPTR_RSTN_OVRD_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_OVRD_REG2__CI__VI {
	struct {
                unsigned int            TX_WRITE_EN_OVRD_VAL : 1;
                unsigned int             TX_WRITE_EN_OVRD_EN : 1;
                unsigned int      TX_CFG_GROUPX1_EN_OVRD_VAL : 1;
                unsigned int       TX_CFG_GROUPX1_EN_OVRD_EN : 1;
                unsigned int      TX_CFG_GROUPX2_EN_OVRD_VAL : 1;
                unsigned int       TX_CFG_GROUPX2_EN_OVRD_EN : 1;
                unsigned int      TX_CFG_GROUPX4_EN_OVRD_VAL : 1;
                unsigned int       TX_CFG_GROUPX4_EN_OVRD_EN : 1;
                unsigned int      TX_CFG_GROUPX8_EN_OVRD_VAL : 1;
                unsigned int       TX_CFG_GROUPX8_EN_OVRD_EN : 1;
                unsigned int     TX_CFG_GROUPX16_EN_OVRD_VAL : 1;
                unsigned int      TX_CFG_GROUPX16_EN_OVRD_EN : 1;
                unsigned int    TX_CFG_DRV0_EN_GEN2_OVRD_VAL : 4;
                unsigned int TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL : 4;
                unsigned int    TX_CFG_DRV1_EN_GEN2_OVRD_VAL : 5;
                unsigned int TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL : 5;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_OVRD_REG3__CI__VI {
	struct {
                unsigned int    TX_CFG_DRV2_EN_GEN2_OVRD_VAL : 4;
                unsigned int TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL : 4;
                unsigned int    TX_CFG_DRVX_EN_GEN2_OVRD_VAL : 1;
                unsigned int TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL : 1;
                unsigned int    TX_CFG_DRV0_EN_GEN3_OVRD_VAL : 4;
                unsigned int TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL : 4;
                unsigned int    TX_CFG_DRV1_EN_GEN3_OVRD_VAL : 5;
                unsigned int TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL : 5;
                unsigned int    TX_CFG_DRV2_EN_GEN3_OVRD_VAL : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_OVRD_REG4__CI__VI {
	struct {
                unsigned int TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL : 4;
                unsigned int    TX_CFG_DRVX_EN_GEN3_OVRD_VAL : 1;
                unsigned int TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_SCI_STAT_OVRD_REG0__CI {
	struct {
		unsigned int        IGNR_TXPWR_SCI_UPDT_L0T3 : 1;
		unsigned int        IGNR_TXPWR_SCI_UPDT_L4T7 : 1;
		unsigned int       IGNR_TXPWR_SCI_UPDT_L8T11 : 1;
		unsigned int      IGNR_TXPWR_SCI_UPDT_L12T15 : 1;
		unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L0T3 : 1;
		unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L12T15 : 1;
		unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L0T3 : 1;
		unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L12T15 : 1;
		unsigned int  IGNR_COEFFICIENT_SCI_UPDT_L0T3 : 1;
		unsigned int  IGNR_COEFFICIENT_SCI_UPDT_L4T7 : 1;
		unsigned int IGNR_COEFFICIENT_SCI_UPDT_L8T11 : 1;
		unsigned int IGNR_COEFFICIENT_SCI_UPDT_L12T15 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_GLB_SCI_STAT_OVRD_REG0__VI {
	struct {
		unsigned int        IGNR_TXPWR_CBI_UPDT_L0T3 : 1;
		unsigned int        IGNR_TXPWR_CBI_UPDT_L4T7 : 1;
		unsigned int       IGNR_TXPWR_CBI_UPDT_L8T11 : 1;
		unsigned int      IGNR_TXPWR_CBI_UPDT_L12T15 : 1;
		unsigned int                                 : 4;
		unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L0T3 : 1;
		unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L4T7 : 1;
		unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L12T15 : 1;
		unsigned int  IGNR_COEFFICIENT_CBI_UPDT_L0T3 : 1;
		unsigned int  IGNR_COEFFICIENT_CBI_UPDT_L4T7 : 1;
		unsigned int IGNR_COEFFICIENT_CBI_UPDT_L8T11 : 1;
		unsigned int IGNR_COEFFICIENT_CBI_UPDT_L12T15 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE0_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_0 : 1;
                unsigned int               TX_CFG_INV_DATA_0 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_0 : 1;
                unsigned int                TX_DBG_PRBS_EN_0 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE0_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_0 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_0 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_0 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_0 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_0 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_0 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_0 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_0 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_0 : 3;
                unsigned int          INCOHERENTCK_0__SI__CI : 1;
                unsigned int                        TXMARG_0 : 3;
                unsigned int                        DEEMPH_0 : 1;
                unsigned int                 COEFFICIENTID_0 : 2;
                unsigned int                   COEFFICIENT_0 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE10_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_10 : 1;
                unsigned int              TX_CFG_INV_DATA_10 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_10 : 1;
                unsigned int               TX_DBG_PRBS_EN_10 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE10_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_10 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_10 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_10 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_10 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_10 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_10 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_10 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_10 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_10 : 3;
                unsigned int         INCOHERENTCK_10__SI__CI : 1;
                unsigned int                       TXMARG_10 : 3;
                unsigned int                       DEEMPH_10 : 1;
                unsigned int                COEFFICIENTID_10 : 2;
                unsigned int                  COEFFICIENT_10 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE11_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_11 : 1;
                unsigned int              TX_CFG_INV_DATA_11 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_11 : 1;
                unsigned int               TX_DBG_PRBS_EN_11 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE11_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_11 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_11 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_11 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_11 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_11 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_11 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_11 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_11 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_11 : 3;
                unsigned int         INCOHERENTCK_11__SI__CI : 1;
                unsigned int                       TXMARG_11 : 3;
                unsigned int                       DEEMPH_11 : 1;
                unsigned int                COEFFICIENTID_11 : 2;
                unsigned int                  COEFFICIENT_11 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE12_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_12 : 1;
                unsigned int              TX_CFG_INV_DATA_12 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_12 : 1;
                unsigned int               TX_DBG_PRBS_EN_12 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE12_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_12 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_12 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_12 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_12 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_12 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_12 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_12 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_12 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_12 : 3;
                unsigned int         INCOHERENTCK_12__SI__CI : 1;
                unsigned int                       TXMARG_12 : 3;
                unsigned int                       DEEMPH_12 : 1;
                unsigned int                COEFFICIENTID_12 : 2;
                unsigned int                  COEFFICIENT_12 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE13_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_13 : 1;
                unsigned int              TX_CFG_INV_DATA_13 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_13 : 1;
                unsigned int               TX_DBG_PRBS_EN_13 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE13_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_13 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_13 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_13 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_13 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_13 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_13 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_13 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_13 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_13 : 3;
                unsigned int         INCOHERENTCK_13__SI__CI : 1;
                unsigned int                       TXMARG_13 : 3;
                unsigned int                       DEEMPH_13 : 1;
                unsigned int                COEFFICIENTID_13 : 2;
                unsigned int                  COEFFICIENT_13 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE14_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_14 : 1;
                unsigned int              TX_CFG_INV_DATA_14 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_14 : 1;
                unsigned int               TX_DBG_PRBS_EN_14 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE14_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_14 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_14 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_14 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_14 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_14 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_14 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_14 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_14 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_14 : 3;
                unsigned int         INCOHERENTCK_14__SI__CI : 1;
                unsigned int                       TXMARG_14 : 3;
                unsigned int                       DEEMPH_14 : 1;
                unsigned int                COEFFICIENTID_14 : 2;
                unsigned int                  COEFFICIENT_14 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE15_CTRL_REG0__CI__VI {
	struct {
                unsigned int          TX_CFG_DISPCLK_MODE_15 : 1;
                unsigned int              TX_CFG_INV_DATA_15 : 1;
                unsigned int        TX_CFG_SWING_BOOST_EN_15 : 1;
                unsigned int               TX_DBG_PRBS_EN_15 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE15_OVRD_REG0__CI__VI {
	struct {
                unsigned int          TX_DCLK_EN_OVRD_VAL_15 : 1;
                unsigned int           TX_DCLK_EN_OVRD_EN_15 : 1;
                unsigned int      TX_DRV_DATA_EN_OVRD_VAL_15 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_EN_15 : 1;
                unsigned int        TX_DRV_PWRON_OVRD_VAL_15 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_EN_15 : 1;
                unsigned int   TX_FRONTEND_PWRON_OVRD_VAL_15 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_EN_15 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                        TXPWR_15 : 3;
                unsigned int         INCOHERENTCK_15__SI__CI : 1;
                unsigned int                       TXMARG_15 : 3;
                unsigned int                       DEEMPH_15 : 1;
                unsigned int                COEFFICIENTID_15 : 2;
                unsigned int                  COEFFICIENT_15 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE1_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_1 : 1;
                unsigned int               TX_CFG_INV_DATA_1 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_1 : 1;
                unsigned int                TX_DBG_PRBS_EN_1 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE1_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_1 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_1 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_1 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_1 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_1 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_1 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_1 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_1 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_1 : 3;
                unsigned int          INCOHERENTCK_1__SI__CI : 1;
                unsigned int                        TXMARG_1 : 3;
                unsigned int                        DEEMPH_1 : 1;
                unsigned int                 COEFFICIENTID_1 : 2;
                unsigned int                   COEFFICIENT_1 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE2_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_2 : 1;
                unsigned int               TX_CFG_INV_DATA_2 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_2 : 1;
                unsigned int                TX_DBG_PRBS_EN_2 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE2_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_2 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_2 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_2 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_2 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_2 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_2 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_2 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_2 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_2 : 3;
                unsigned int          INCOHERENTCK_2__SI__CI : 1;
                unsigned int                        TXMARG_2 : 3;
                unsigned int                        DEEMPH_2 : 1;
                unsigned int                 COEFFICIENTID_2 : 2;
                unsigned int                   COEFFICIENT_2 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE3_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_3 : 1;
                unsigned int               TX_CFG_INV_DATA_3 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_3 : 1;
                unsigned int                TX_DBG_PRBS_EN_3 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE3_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_3 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_3 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_3 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_3 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_3 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_3 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_3 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_3 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_3 : 3;
                unsigned int          INCOHERENTCK_3__SI__CI : 1;
                unsigned int                        TXMARG_3 : 3;
                unsigned int                        DEEMPH_3 : 1;
                unsigned int                 COEFFICIENTID_3 : 2;
                unsigned int                   COEFFICIENT_3 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE4_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_4 : 1;
                unsigned int               TX_CFG_INV_DATA_4 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_4 : 1;
                unsigned int                TX_DBG_PRBS_EN_4 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE4_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_4 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_4 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_4 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_4 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_4 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_4 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_4 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_4 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_4 : 3;
                unsigned int          INCOHERENTCK_4__SI__CI : 1;
                unsigned int                        TXMARG_4 : 3;
                unsigned int                        DEEMPH_4 : 1;
                unsigned int                 COEFFICIENTID_4 : 2;
                unsigned int                   COEFFICIENT_4 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE5_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_5 : 1;
                unsigned int               TX_CFG_INV_DATA_5 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_5 : 1;
                unsigned int                TX_DBG_PRBS_EN_5 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE5_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_5 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_5 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_5 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_5 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_5 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_5 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_5 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_5 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_5 : 3;
                unsigned int          INCOHERENTCK_5__SI__CI : 1;
                unsigned int                        TXMARG_5 : 3;
                unsigned int                        DEEMPH_5 : 1;
                unsigned int                 COEFFICIENTID_5 : 2;
                unsigned int                   COEFFICIENT_5 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE6_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_6 : 1;
                unsigned int               TX_CFG_INV_DATA_6 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_6 : 1;
                unsigned int                TX_DBG_PRBS_EN_6 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE6_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_6 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_6 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_6 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_6 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_6 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_6 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_6 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_6 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_6 : 3;
                unsigned int          INCOHERENTCK_6__SI__CI : 1;
                unsigned int                        TXMARG_6 : 3;
                unsigned int                        DEEMPH_6 : 1;
                unsigned int                 COEFFICIENTID_6 : 2;
                unsigned int                   COEFFICIENT_6 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE7_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_7 : 1;
                unsigned int               TX_CFG_INV_DATA_7 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_7 : 1;
                unsigned int                TX_DBG_PRBS_EN_7 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE7_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_7 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_7 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_7 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_7 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_7 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_7 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_7 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_7 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_7 : 3;
                unsigned int          INCOHERENTCK_7__SI__CI : 1;
                unsigned int                        TXMARG_7 : 3;
                unsigned int                        DEEMPH_7 : 1;
                unsigned int                 COEFFICIENTID_7 : 2;
                unsigned int                   COEFFICIENT_7 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE8_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_8 : 1;
                unsigned int               TX_CFG_INV_DATA_8 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_8 : 1;
                unsigned int                TX_DBG_PRBS_EN_8 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE8_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_8 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_8 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_8 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_8 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_8 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_8 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_8 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_8 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_8 : 3;
                unsigned int          INCOHERENTCK_8__SI__CI : 1;
                unsigned int                        TXMARG_8 : 3;
                unsigned int                        DEEMPH_8 : 1;
                unsigned int                 COEFFICIENTID_8 : 2;
                unsigned int                   COEFFICIENT_8 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE9_CTRL_REG0__CI__VI {
	struct {
                unsigned int           TX_CFG_DISPCLK_MODE_9 : 1;
                unsigned int               TX_CFG_INV_DATA_9 : 1;
                unsigned int         TX_CFG_SWING_BOOST_EN_9 : 1;
                unsigned int                TX_DBG_PRBS_EN_9 : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE9_OVRD_REG0__CI__VI {
	struct {
                unsigned int           TX_DCLK_EN_OVRD_VAL_9 : 1;
                unsigned int            TX_DCLK_EN_OVRD_EN_9 : 1;
                unsigned int       TX_DRV_DATA_EN_OVRD_VAL_9 : 1;
                unsigned int        TX_DRV_DATA_EN_OVRD_EN_9 : 1;
                unsigned int         TX_DRV_PWRON_OVRD_VAL_9 : 1;
                unsigned int          TX_DRV_PWRON_OVRD_EN_9 : 1;
                unsigned int    TX_FRONTEND_PWRON_OVRD_VAL_9 : 1;
                unsigned int     TX_FRONTEND_PWRON_OVRD_EN_9 : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI {
	struct {
                unsigned int                         TXPWR_9 : 3;
                unsigned int          INCOHERENTCK_9__SI__CI : 1;
                unsigned int                        TXMARG_9 : 3;
                unsigned int                        DEEMPH_9 : 1;
                unsigned int                 COEFFICIENTID_9 : 2;
                unsigned int                   COEFFICIENT_9 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_BCH_ECC_CNTL__CI__VI {
	struct {
                unsigned int                STRAP_BCH_ECC_EN : 1;
                unsigned int                                 : 7;
                unsigned int         BCH_ECC_ERROR_THRESHOLD : 8;
                unsigned int            BCH_ECC_ERROR_STATUS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_HW_DEBUG {
	struct {
		unsigned int                     HW_00_DEBUG : 1;
		unsigned int                     HW_01_DEBUG : 1;
		unsigned int                     HW_02_DEBUG : 1;
		unsigned int                     HW_03_DEBUG : 1;
		unsigned int                     HW_04_DEBUG : 1;
		unsigned int                     HW_05_DEBUG : 1;
		unsigned int                     HW_06_DEBUG : 1;
		unsigned int                     HW_07_DEBUG : 1;
		unsigned int                     HW_08_DEBUG : 1;
		unsigned int                     HW_09_DEBUG : 1;
		unsigned int                     HW_10_DEBUG : 1;
		unsigned int                     HW_11_DEBUG : 1;
		unsigned int                     HW_12_DEBUG : 1;
		unsigned int                     HW_13_DEBUG : 1;
		unsigned int                     HW_14_DEBUG : 1;
		unsigned int                     HW_15_DEBUG : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_PORT_CNTL__CI__VI {
	struct {
                unsigned int                 SLV_PORT_REQ_EN : 1;
                unsigned int               CI_SNOOP_OVERRIDE : 1;
                unsigned int                  HOTPLUG_MSG_EN : 1;
                unsigned int                   NATIVE_PME_EN : 1;
                unsigned int                    PWR_FAULT_EN : 1;
                unsigned int                      PMI_BM_DIS : 1;
                unsigned int               SEQNUM_DEBUG_MODE : 1;
                unsigned int                                 : 1;
                unsigned int CI_SLV_CPL_STATIC_ALLOC_LIMIT_S : 7;
                unsigned int                                 : 1;
                unsigned int    CI_MAX_CPL_PAYLOAD_SIZE_MODE : 2;
                unsigned int    CI_PRIV_MAX_CPL_PAYLOAD_SIZE : 3;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_PORT_CNTL__SI {
	struct {
		unsigned int                 SLV_PORT_REQ_EN : 1;
		unsigned int               CI_SNOOP_OVERRIDE : 1;
		unsigned int                  HOTPLUG_MSG_EN : 1;
		unsigned int                   NATIVE_PME_EN : 1;
		unsigned int               SEQNUM_DEBUG_MODE : 1;
		unsigned int                      PMI_BM_DIS : 1;
		unsigned int                                 : 2;
		unsigned int CI_SLV_CPL_STATIC_ALLOC_LIMIT_S : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_RESERVED {
	struct {
		unsigned int                  PCIEP_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_SCRATCH {
	struct {
		unsigned int                   PCIEP_SCRATCH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_STRAP_LC {
	struct {
		unsigned int            STRAP_FTS_yTSx_COUNT : 2;
		unsigned int           STRAP_LONG_yTSx_COUNT : 2;
		unsigned int            STRAP_MED_yTSx_COUNT : 2;
		unsigned int          STRAP_SHORT_yTSx_COUNT : 2;
		unsigned int             STRAP_SKIP_INTERVAL : 3;
		unsigned int           STRAP_BYPASS_RCVR_DET : 1;
		unsigned int            STRAP_COMPLIANCE_DIS : 1;
		unsigned int          STRAP_FORCE_COMPLIANCE : 1;
		unsigned int          STRAP_REVERSE_LC_LANES : 1;
		unsigned int STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS : 1;
		unsigned int          STRAP_LANE_NEGOTIATION : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_STRAP_MISC__CI__VI {
	struct {
                unsigned int             STRAP_REVERSE_LANES : 1;
                unsigned int             STRAP_E2E_PREFIX_EN : 1;
                unsigned int    STRAP_EXTENDED_FMT_SUPPORTED : 1;
                unsigned int            STRAP_OBFF_SUPPORTED : 2;
                unsigned int             STRAP_LTR_SUPPORTED : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_STRAP_MISC__SI {
	struct {
		unsigned int                                 : 4;
		unsigned int             STRAP_REVERSE_LANES : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ACS_CAP__CI__VI {
	struct {
                unsigned int               SOURCE_VALIDATION : 1;
                unsigned int            TRANSLATION_BLOCKING : 1;
                unsigned int            P2P_REQUEST_REDIRECT : 1;
                unsigned int         P2P_COMPLETION_REDIRECT : 1;
                unsigned int             UPSTREAM_FORWARDING : 1;
                unsigned int              P2P_EGRESS_CONTROL : 1;
                unsigned int           DIRECT_TRANSLATED_P2P : 1;
                unsigned int                                 : 1;
                unsigned int      EGRESS_CONTROL_VECTOR_SIZE : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ACS_CNTL__CI__VI {
	struct {
                unsigned int            SOURCE_VALIDATION_EN : 1;
                unsigned int         TRANSLATION_BLOCKING_EN : 1;
                unsigned int         P2P_REQUEST_REDIRECT_EN : 1;
                unsigned int      P2P_COMPLETION_REDIRECT_EN : 1;
                unsigned int          UPSTREAM_FORWARDING_EN : 1;
                unsigned int           P2P_EGRESS_CONTROL_EN : 1;
                unsigned int        DIRECT_TRANSLATED_P2P_EN : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ACS_ENH_CAP_LIST__CI__VI {
	struct {
                unsigned int                          CAP_ID : 16;
                unsigned int                         CAP_VER : 4;
                unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ADV_ERR_CAP_CNTL__SI__CI {
	struct {
                unsigned int                   FIRST_ERR_PTR : 5;
                unsigned int                    ECRC_GEN_CAP : 1;
                unsigned int                     ECRC_GEN_EN : 1;
                unsigned int                  ECRC_CHECK_CAP : 1;
                unsigned int                   ECRC_CHECK_EN : 1;
                unsigned int          MULTI_HDR_RECD_CAP__CI : 1;
                unsigned int           MULTI_HDR_RECD_EN__CI : 1;
                unsigned int                                 : 4;
                unsigned int      TLP_PREFIX_LOG_PRESENT__CI : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ADV_ERR_CAP_CNTL__VI {
	struct {
		unsigned int                   FIRST_ERR_PTR : 5;
		unsigned int                    ECRC_GEN_CAP : 1;
		unsigned int                     ECRC_GEN_EN : 1;
		unsigned int                  ECRC_CHECK_CAP : 1;
		unsigned int                   ECRC_CHECK_EN : 1;
		unsigned int              MULTI_HDR_RECD_CAP : 1;
		unsigned int               MULTI_HDR_RECD_EN : 1;
		unsigned int          TLP_PREFIX_LOG_PRESENT : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ADV_ERR_RPT_ENH_CAP_LIST {
	struct {
		unsigned int                          CAP_ID : 16;
		unsigned int                         CAP_VER : 4;
		unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ATS_CAP__CI {
	struct {
		unsigned int              INVALIDATE_Q_DEPTH : 5;
		unsigned int            PAGE_ALIGNED_REQUEST : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ATS_CAP__VI {
	struct {
		unsigned int              INVALIDATE_Q_DEPTH : 5;
		unsigned int            PAGE_ALIGNED_REQUEST : 1;
		unsigned int     GLOBAL_INVALIDATE_SUPPORTED : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ATS_CNTL__CI__VI {
	struct {
                unsigned int                             STU : 5;
                unsigned int                                 : 10;
                unsigned int                      ATC_ENABLE : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ATS_ENH_CAP_LIST__CI__VI {
	struct {
                unsigned int                          CAP_ID : 16;
                unsigned int                         CAP_VER : 4;
                unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR1_CAP__CI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int              BAR_SIZE_SUPPORTED : 20;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR1_CNTL__CI__VI {
	struct {
                unsigned int                       BAR_INDEX : 3;
                unsigned int                                 : 2;
                unsigned int                   BAR_TOTAL_NUM : 3;
                unsigned int                        BAR_SIZE : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR2_CAP__CI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int              BAR_SIZE_SUPPORTED : 20;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR2_CNTL__CI__VI {
	struct {
                unsigned int                       BAR_INDEX : 3;
                unsigned int                                 : 2;
                unsigned int                   BAR_TOTAL_NUM : 3;
                unsigned int                        BAR_SIZE : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR3_CAP__CI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int              BAR_SIZE_SUPPORTED : 20;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR3_CNTL__CI__VI {
	struct {
                unsigned int                       BAR_INDEX : 3;
                unsigned int                                 : 2;
                unsigned int                   BAR_TOTAL_NUM : 3;
                unsigned int                        BAR_SIZE : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR4_CAP__CI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int              BAR_SIZE_SUPPORTED : 20;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR4_CNTL__CI__VI {
	struct {
                unsigned int                       BAR_INDEX : 3;
                unsigned int                                 : 2;
                unsigned int                   BAR_TOTAL_NUM : 3;
                unsigned int                        BAR_SIZE : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR5_CAP__CI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int              BAR_SIZE_SUPPORTED : 20;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR5_CNTL__CI__VI {
	struct {
                unsigned int                       BAR_INDEX : 3;
                unsigned int                                 : 2;
                unsigned int                   BAR_TOTAL_NUM : 3;
                unsigned int                        BAR_SIZE : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR6_CAP__CI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int              BAR_SIZE_SUPPORTED : 20;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR6_CNTL__CI__VI {
	struct {
                unsigned int                       BAR_INDEX : 3;
                unsigned int                                 : 2;
                unsigned int                   BAR_TOTAL_NUM : 3;
                unsigned int                        BAR_SIZE : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BAR_ENH_CAP_LIST__CI__VI {
	struct {
                unsigned int                          CAP_ID : 16;
                unsigned int                         CAP_VER : 4;
                unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_BUS_CNTL {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 5;
                unsigned int                     PMI_INT_DIS : 1;
                unsigned int               IMMEDIATE_PMI_DIS : 1;
                unsigned int                                 : 4;
                unsigned int       TRUE_PM_STATUS_EN__CI__VI : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CAP {
	struct {
                unsigned int                         VERSION : 4;
                unsigned int                     DEVICE_TYPE : 4;
                unsigned int                SLOT_IMPLEMENTED : 1;
                unsigned int                 INT_MESSAGE_NUM : 5;
                unsigned int                                 : 1;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CAP_LIST {
	struct {
		unsigned int                          CAP_ID : 8;
		unsigned int                        NEXT_PTR : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CFG_CNTL__CI__VI {
	struct {
                unsigned int        CFG_EN_DEC_TO_HIDDEN_REG : 1;
                unsigned int   CFG_EN_DEC_TO_GEN2_HIDDEN_REG : 1;
                unsigned int   CFG_EN_DEC_TO_GEN3_HIDDEN_REG : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CFG_CNTL__SI {
	struct {
		unsigned int   CFG_EN_DEC_TO_GEN2_HIDDEN_REG : 1;
		unsigned int        CFG_EN_DEC_TO_HIDDEN_REG : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CI_CNTL__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int             CI_SLAVE_SPLIT_MODE : 1;
                unsigned int            CI_SLAVE_GEN_USR_DIS : 1;
                unsigned int          CI_MST_CMPL_DUMMY_DATA : 1;
                unsigned int                                 : 1;
                unsigned int           CI_SLV_RC_RD_REQ_SIZE : 2;
                unsigned int             CI_SLV_ORDERING_DIS : 1;
                unsigned int              CI_RC_ORDERING_DIS : 1;
                unsigned int            CI_SLV_CPL_ALLOC_DIS : 1;
                unsigned int           CI_SLV_CPL_ALLOC_MODE : 1;
                unsigned int            CI_SLV_CPL_ALLOC_SOR : 1;
                unsigned int CI_MST_IGNORE_PAGE_ALIGNED_REQUEST : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CI_CNTL__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int             CI_SLAVE_SPLIT_MODE : 1;
		unsigned int            CI_SLAVE_GEN_USR_DIS : 1;
		unsigned int          CI_MST_CMPL_DUMMY_DATA : 1;
		unsigned int                                 : 1;
		unsigned int           CI_SLV_RC_RD_REQ_SIZE : 2;
		unsigned int             CI_SLV_ORDERING_DIS : 1;
		unsigned int              CI_RC_ORDERING_DIS : 1;
		unsigned int            CI_SLV_CPL_ALLOC_DIS : 1;
		unsigned int           CI_SLV_CPL_ALLOC_MODE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 10;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CNTL2 {
	struct {
                unsigned int           TX_ARB_ROUND_ROBIN_EN : 1;
                unsigned int                TX_ARB_SLV_LIMIT : 5;
                unsigned int                TX_ARB_MST_LIMIT : 5;
                unsigned int      TX_BLOCK_TLP_ON_PM_DIS__VI : 1;
                unsigned int TX_NP_MEM_WRITE_SWP_ENCODING__VI : 1;
                unsigned int       TX_ATOMIC_OPS_DISABLE__VI : 1;
                unsigned int      TX_ATOMIC_ORDERING_DIS__VI : 1;
                unsigned int                                 : 1;
                unsigned int           SLV_MEM_LS_EN__CI__VI : 1;
                unsigned int SLV_MEM_AGGRESSIVE_LS_EN__CI__VI : 1;
                unsigned int           MST_MEM_LS_EN__CI__VI : 1;
                unsigned int        REPLAY_MEM_LS_EN__CI__VI : 1;
                unsigned int           SLV_MEM_SD_EN__CI__VI : 1;
                unsigned int SLV_MEM_AGGRESSIVE_SD_EN__CI__VI : 1;
                unsigned int           MST_MEM_SD_EN__CI__VI : 1;
                unsigned int        REPLAY_MEM_SD_EN__CI__VI : 1;
                unsigned int RX_NP_MEM_WRITE_ENCODING__CI__VI : 5;
                unsigned int               SLV_MEM_DS_EN__VI : 1;
                unsigned int               MST_MEM_DS_EN__VI : 1;
                unsigned int            REPLAY_MEM_DS_EN__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CNTL__CI {
	struct {
		unsigned int                  HWINIT_WR_LOCK : 1;
		unsigned int           LC_HOT_PLUG_DELAY_SEL : 3;
		unsigned int                                 : 3;
		unsigned int               UR_ERR_REPORT_DIS : 1;
		unsigned int         PCIE_MALFORM_ATOMIC_OPS : 1;
		unsigned int            PCIE_HT_NP_MEM_WRITE : 1;
		unsigned int          RX_SB_ADJ_PAYLOAD_SIZE : 3;
		unsigned int                                 : 2;
		unsigned int               RX_RCB_ATS_UC_DIS : 1;
		unsigned int               RX_RCB_REORDER_EN : 1;
		unsigned int         RX_RCB_INVALID_SIZE_DIS : 1;
		unsigned int            RX_RCB_UNEXP_CPL_DIS : 1;
		unsigned int    RX_RCB_CPL_TIMEOUT_TEST_MODE : 1;
		unsigned int         RX_RCB_CHANNEL_ORDERING : 1;
		unsigned int           RX_RCB_WRONG_ATTR_DIS : 1;
		unsigned int        RX_RCB_WRONG_FUNCNUM_DIS : 1;
		unsigned int       RX_ATS_TRAN_CPL_SPLIT_DIS : 1;
		unsigned int                    TX_CPL_DEBUG : 6;
		unsigned int            RX_IGNORE_LTR_MSG_UR : 1;
		unsigned int        RX_CPL_POSTED_REQ_ORD_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CNTL__VI {
	struct {
		unsigned int                  HWINIT_WR_LOCK : 1;
		unsigned int           LC_HOT_PLUG_DELAY_SEL : 3;
		unsigned int                                 : 3;
		unsigned int               UR_ERR_REPORT_DIS : 1;
		unsigned int         PCIE_MALFORM_ATOMIC_OPS : 1;
		unsigned int            PCIE_HT_NP_MEM_WRITE : 1;
		unsigned int          RX_SB_ADJ_PAYLOAD_SIZE : 3;
		unsigned int                                 : 2;
		unsigned int               RX_RCB_ATS_UC_DIS : 1;
		unsigned int               RX_RCB_REORDER_EN : 1;
		unsigned int         RX_RCB_INVALID_SIZE_DIS : 1;
		unsigned int            RX_RCB_UNEXP_CPL_DIS : 1;
		unsigned int    RX_RCB_CPL_TIMEOUT_TEST_MODE : 1;
		unsigned int         RX_RCB_WRONG_PREFIX_DIS : 1;
		unsigned int           RX_RCB_WRONG_ATTR_DIS : 1;
		unsigned int        RX_RCB_WRONG_FUNCNUM_DIS : 1;
		unsigned int       RX_ATS_TRAN_CPL_SPLIT_DIS : 1;
		unsigned int                    TX_CPL_DEBUG : 6;
		unsigned int            RX_IGNORE_LTR_MSG_UR : 1;
		unsigned int        RX_CPL_POSTED_REQ_ORD_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CNTL__SI {
	struct {
		unsigned int                  HWINIT_WR_LOCK : 1;
		unsigned int                                 : 6;
		unsigned int               UR_ERR_REPORT_DIS : 1;
		unsigned int                                 : 1;
		unsigned int            PCIE_HT_NP_MEM_WRITE : 1;
		unsigned int          RX_SB_ADJ_PAYLOAD_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int               RX_RCB_REORDER_EN : 1;
		unsigned int         RX_RCB_INVALID_SIZE_DIS : 1;
		unsigned int            RX_RCB_UNEXP_CPL_DIS : 1;
		unsigned int    RX_RCB_CPL_TIMEOUT_TEST_MODE : 1;
		unsigned int         RX_RCB_CHANNEL_ORDERING : 1;
		unsigned int           RX_RCB_WRONG_ATTR_DIS : 1;
		unsigned int        RX_RCB_WRONG_FUNCNUM_DIS : 1;
		unsigned int                                 : 1;
		unsigned int                    TX_CPL_DEBUG : 6;
		unsigned int                                 : 1;
		unsigned int        RX_CPL_POSTED_REQ_ORD_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CONFIG_CNTL {
	struct {
                unsigned int                 DYN_CLK_LATENCY : 4;
                unsigned int                                 : 12;
                unsigned int CI_MAX_PAYLOAD_SIZE_MODE__CI__VI : 1;
                unsigned int CI_PRIV_MAX_PAYLOAD_SIZE__CI__VI : 3;
                unsigned int CI_MAX_READ_REQUEST_SIZE_MODE__CI__VI : 1;
                unsigned int CI_PRIV_MAX_READ_REQUEST_SIZE__CI__VI : 3;
                unsigned int   CI_MAX_READ_SAFE_MODE__CI__VI : 1;
                unsigned int CI_EXTENDED_TAG_EN_OVERRIDE__CI__VI : 2;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CORR_ERR_MASK {
	struct {
                unsigned int                    RCV_ERR_MASK : 1;
                unsigned int                                 : 5;
                unsigned int                    BAD_TLP_MASK : 1;
                unsigned int                   BAD_DLLP_MASK : 1;
                unsigned int        REPLAY_NUM_ROLLOVER_MASK : 1;
                unsigned int                                 : 3;
                unsigned int       REPLAY_TIMER_TIMEOUT_MASK : 1;
                unsigned int      ADVISORY_NONFATAL_ERR_MASK : 1;
                unsigned int       CORR_INT_ERR_MASK__CI__VI : 1;
                unsigned int       HDR_LOG_OVFL_MASK__CI__VI : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_CORR_ERR_STATUS {
	struct {
                unsigned int                  RCV_ERR_STATUS : 1;
                unsigned int                                 : 5;
                unsigned int                  BAD_TLP_STATUS : 1;
                unsigned int                 BAD_DLLP_STATUS : 1;
                unsigned int      REPLAY_NUM_ROLLOVER_STATUS : 1;
                unsigned int                                 : 3;
                unsigned int     REPLAY_TIMER_TIMEOUT_STATUS : 1;
                unsigned int    ADVISORY_NONFATAL_ERR_STATUS : 1;
                unsigned int     CORR_INT_ERR_STATUS__CI__VI : 1;
                unsigned int     HDR_LOG_OVFL_STATUS__CI__VI : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DATA {
	struct {
		unsigned int                       PCIE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DATA_2__CI__VI {
	struct {
                unsigned int                       PCIE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DEBUG_CNTL {
	struct {
		unsigned int                   DEBUG_PORT_EN : 8;
		unsigned int                    DEBUG_SELECT : 1;
		unsigned int                                 : 7;
		unsigned int                   DEBUG_LANE_EN : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DEV_SERIAL_NUM_DW1 {
	struct {
		unsigned int                SERIAL_NUMBER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DEV_SERIAL_NUM_DW2 {
	struct {
		unsigned int                SERIAL_NUMBER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST {
	struct {
		unsigned int                          CAP_ID : 16;
		unsigned int                         CAP_VER : 4;
		unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_CAP__CI__VI {
	struct {
                unsigned int                    SUBSTATE_MAX : 5;
                unsigned int                                 : 3;
                unsigned int                  TRANS_LAT_UNIT : 2;
                unsigned int                                 : 2;
                unsigned int                 PWR_ALLOC_SCALE : 2;
                unsigned int                                 : 2;
                unsigned int                 TRANS_LAT_VAL_0 : 8;
                unsigned int                 TRANS_LAT_VAL_1 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_CNTL__CI__VI {
	struct {
                unsigned int                   SUBSTATE_CNTL : 5;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_ENH_CAP_LIST__CI__VI {
	struct {
                unsigned int                          CAP_ID : 16;
                unsigned int                         CAP_VER : 4;
                unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_LATENCY_INDICATOR__CI__VI {
	struct {
                unsigned int        TRANS_LAT_INDICATOR_BITS : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_STATUS__CI__VI {
	struct {
                unsigned int                 SUBSTATE_STATUS : 5;
                unsigned int                                 : 3;
                unsigned int           SUBSTATE_CNTL_ENABLED : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ERR_CNTL__CI__VI {
	struct {
                unsigned int               ERR_REPORTING_DIS : 1;
                unsigned int        STRAP_FIRST_RCVD_ERR_LOG : 1;
                unsigned int           RX_DROP_ECRC_FAILURES : 1;
                unsigned int                                 : 1;
                unsigned int            TX_GENERATE_LCRC_ERR : 1;
                unsigned int            RX_GENERATE_LCRC_ERR : 1;
                unsigned int            TX_GENERATE_ECRC_ERR : 1;
                unsigned int            RX_GENERATE_ECRC_ERR : 1;
                unsigned int             AER_HDR_LOG_TIMEOUT : 3;
                unsigned int    AER_HDR_LOG_F0_TIMER_EXPIRED : 1;
                unsigned int    AER_HDR_LOG_F1_TIMER_EXPIRED : 1;
                unsigned int    AER_HDR_LOG_F2_TIMER_EXPIRED : 1;
                unsigned int     CI_P_SLV_BUF_RD_HALT_STATUS : 1;
                unsigned int    CI_NP_SLV_BUF_RD_HALT_STATUS : 1;
                unsigned int           CI_SLV_BUF_HALT_RESET : 1;
                unsigned int    SEND_ERR_MSG_IMMEDIATELY__VI : 1;
                unsigned int STRAP_POISONED_ADVISORY_NONFATAL__VI : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ERR_CNTL__SI {
	struct {
		unsigned int               ERR_REPORTING_DIS : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_CAP__CI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int                  TRANS_LAT_UNIT : 2;
                unsigned int                                 : 2;
                unsigned int                 PWR_ALLOC_SCALE : 2;
                unsigned int                                 : 2;
                unsigned int                 TRANS_LAT_VAL_0 : 8;
                unsigned int                 TRANS_LAT_VAL_1 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_CNTL__CI__VI {
	struct {
                unsigned int                 SUBSTATE_STATUS : 5;
                unsigned int                                 : 3;
                unsigned int         DPA_COMPLIANCE_MODE__VI : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_LATENCY_INDICATOR__CI__VI {
	struct {
                unsigned int        TRANS_LAT_INDICATOR_BITS : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI {
	struct {
                unsigned int              SUBSTATE_PWR_ALLOC : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_FC_CPL {
	struct {
		unsigned int                    CPLD_CREDITS : 8;
		unsigned int                    CPLH_CREDITS : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_FC_NP {
	struct {
		unsigned int                     NPD_CREDITS : 8;
		unsigned int                     NPH_CREDITS : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_FC_P {
	struct {
		unsigned int                      PD_CREDITS : 8;
		unsigned int                      PH_CREDITS : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_HDR_LOG0 {
	struct {
		unsigned int                         TLP_HDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_HDR_LOG1 {
	struct {
		unsigned int                         TLP_HDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_HDR_LOG2 {
	struct {
		unsigned int                         TLP_HDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_HDR_LOG3 {
	struct {
		unsigned int                         TLP_HDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_HW_DEBUG {
	struct {
		unsigned int                     HW_00_DEBUG : 1;
		unsigned int                     HW_01_DEBUG : 1;
		unsigned int                     HW_02_DEBUG : 1;
		unsigned int                     HW_03_DEBUG : 1;
		unsigned int                     HW_04_DEBUG : 1;
		unsigned int                     HW_05_DEBUG : 1;
		unsigned int                     HW_06_DEBUG : 1;
		unsigned int                     HW_07_DEBUG : 1;
		unsigned int                     HW_08_DEBUG : 1;
		unsigned int                     HW_09_DEBUG : 1;
		unsigned int                     HW_10_DEBUG : 1;
		unsigned int                     HW_11_DEBUG : 1;
		unsigned int                     HW_12_DEBUG : 1;
		unsigned int                     HW_13_DEBUG : 1;
		unsigned int                     HW_14_DEBUG : 1;
		unsigned int                     HW_15_DEBUG : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_I2C_REG_ADDR_EXPAND {
	struct {
                unsigned int                    I2C_REG_ADDR : 17;
                unsigned int                                 : 4;
                unsigned int                                 : 4;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_I2C_REG_DATA {
	struct {
		unsigned int                    I2C_REG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_INDEX_2__CI__VI {
	struct {
                unsigned int                      PCIE_INDEX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_INDEX__CI__VI {
	struct {
                unsigned int                      PCIE_INDEX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_INDEX__SI {
	struct {
		unsigned int                      PCIE_INDEX : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_INT_CNTL {
	struct {
                unsigned int                 CORR_ERR_INT_EN : 1;
                unsigned int            NON_FATAL_ERR_INT_EN : 1;
                unsigned int                FATAL_ERR_INT_EN : 1;
                unsigned int             USR_DETECTED_INT_EN : 1;
                unsigned int                 MISC_ERR_INT_EN : 1;
                unsigned int                                 : 1;
                unsigned int          POWER_STATE_CHG_INT_EN : 1;
                unsigned int                  LINK_BW_INT_EN : 1;
                unsigned int     QUIESCE_RCVD_INT_EN__CI__VI : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_INT_STATUS {
	struct {
                unsigned int             CORR_ERR_INT_STATUS : 1;
                unsigned int        NON_FATAL_ERR_INT_STATUS : 1;
                unsigned int            FATAL_ERR_INT_STATUS : 1;
                unsigned int         USR_DETECTED_INT_STATUS : 1;
                unsigned int             MISC_ERR_INT_STATUS : 1;
                unsigned int                                 : 1;
                unsigned int      POWER_STATE_CHG_INT_STATUS : 1;
                unsigned int              LINK_BW_INT_STATUS : 1;
                unsigned int QUIESCE_RCVD_INT_STATUS__CI__VI : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_0_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_10_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_11_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_12_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_13_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_14_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_15_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_1_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_2_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_3_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_4_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_5_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_6_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_7_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_8_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_9_EQUALIZATION_CNTL__CI__VI {
	struct {
                unsigned int       DOWNSTREAM_PORT_TX_PRESET : 4;
                unsigned int  DOWNSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 1;
                unsigned int         UPSTREAM_PORT_TX_PRESET : 4;
                unsigned int    UPSTREAM_PORT_RX_PRESET_HINT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LANE_ERROR_STATUS__CI__VI {
	struct {
                unsigned int          LANE_ERROR_STATUS_BITS : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_BW_CHANGE_CNTL {
	struct {
		unsigned int             LC_BW_CHANGE_INT_EN : 1;
		unsigned int         LC_HW_INIT_SPEED_CHANGE : 1;
		unsigned int         LC_SW_INIT_SPEED_CHANGE : 1;
		unsigned int      LC_OTHER_INIT_SPEED_CHANGE : 1;
		unsigned int     LC_RELIABILITY_SPEED_CHANGE : 1;
		unsigned int             LC_FAILED_SPEED_NEG : 1;
		unsigned int               LC_LONG_LW_CHANGE : 1;
		unsigned int              LC_SHORT_LW_CHANGE : 1;
		unsigned int              LC_LW_CHANGE_OTHER : 1;
		unsigned int             LC_LW_CHANGE_FAILED : 1;
		unsigned int LC_LINK_BW_NOTIFICATION_DETECT_MODE : 1;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_CDR_CNTL {
	struct {
		unsigned int                 LC_CDR_TEST_OFF : 12;
		unsigned int                LC_CDR_TEST_SETS : 12;
		unsigned int                 LC_CDR_SET_TYPE : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_CNTL {
	struct {
                unsigned int                                 : 1;
                unsigned int         LC_DONT_ENTER_L23_IN_D0 : 1;
                unsigned int        LC_RESET_L_IDLE_COUNT_EN : 1;
                unsigned int                   LC_RESET_LINK : 1;
                unsigned int            LC_16X_CLEAR_TX_PIPE : 4;
                unsigned int               LC_L0S_INACTIVITY : 4;
                unsigned int                LC_L1_INACTIVITY : 4;
                unsigned int                LC_PMI_TO_L1_DIS : 1;
                unsigned int                 LC_INC_N_FTS_EN : 1;
                unsigned int       LC_LOOK_FOR_IDLE_IN_L1L23 : 2;
                unsigned int           LC_FACTOR_IN_EXT_SYNC : 1;
                unsigned int          LC_WAIT_FOR_PM_ACK_DIS : 1;
                unsigned int                LC_WAKE_FROM_L23 : 1;
                unsigned int             LC_L1_IMMEDIATE_ACK : 1;
                unsigned int               LC_ASPM_TO_L1_DIS : 1;
                unsigned int                  LC_DELAY_COUNT : 2;
                unsigned int               LC_DELAY_L0S_EXIT : 1;
                unsigned int                LC_DELAY_L1_EXIT : 1;
                unsigned int      LC_EXTEND_WAIT_FOR_EL_IDLE : 1;
                unsigned int              LC_ESCAPE_L1L23_EN : 1;
                unsigned int               LC_GATE_RCVR_IDLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_CNTL2__CI__VI {
	struct {
                unsigned int              LC_TIMED_OUT_STATE : 6;
                unsigned int              LC_STATE_TIMED_OUT : 1;
                unsigned int        LC_LOOK_FOR_BW_REDUCTION : 1;
                unsigned int                  LC_MORE_TS2_EN : 1;
                unsigned int          LC_X12_NEGOTIATION_DIS : 1;
                unsigned int          LC_LINK_UP_REVERSAL_EN : 1;
                unsigned int                LC_ILLEGAL_STATE : 1;
                unsigned int     LC_ILLEGAL_STATE_RESTART_EN : 1;
                unsigned int    LC_WAIT_FOR_OTHER_LANES_MODE : 1;
                unsigned int               LC_ELEC_IDLE_MODE : 2;
                unsigned int LC_DISABLE_INFERRED_ELEC_IDLE_DET : 1;
                unsigned int             LC_ALLOW_PDWN_IN_L1 : 1;
                unsigned int            LC_ALLOW_PDWN_IN_L23 : 1;
                unsigned int        LC_DEASSERT_RX_EN_IN_L0S : 1;
                unsigned int          LC_BLOCK_EL_IDLE_IN_L0 : 1;
                unsigned int        LC_RCV_L0_TO_RCV_L0S_DIS : 1;
                unsigned int  LC_ASSERT_INACTIVE_DURING_HOLD : 1;
                unsigned int     LC_WAIT_FOR_LANES_IN_LW_NEG : 2;
                unsigned int       LC_PWR_DOWN_NEG_OFF_LANES : 1;
                unsigned int   LC_DISABLE_LOST_SYM_LOCK_ARCS : 1;
                unsigned int     LC_LINK_BW_NOTIFICATION_DIS : 1;
                unsigned int     LC_PMI_L1_WAIT_FOR_SLV_IDLE : 1;
                unsigned int               LC_TEST_TIMER_SEL : 2;
                unsigned int LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_CNTL2__SI {
	struct {
		unsigned int              LC_TIMED_OUT_STATE : 6;
		unsigned int              LC_STATE_TIMED_OUT : 1;
		unsigned int        LC_LOOK_FOR_BW_REDUCTION : 1;
		unsigned int                  LC_MORE_TS2_EN : 1;
		unsigned int          LC_X12_NEGOTIATION_DIS : 1;
		unsigned int          LC_LINK_UP_REVERSAL_EN : 1;
		unsigned int                LC_ILLEGAL_STATE : 1;
		unsigned int     LC_ILLEGAL_STATE_RESTART_EN : 1;
		unsigned int    LC_WAIT_FOR_OTHER_LANES_MODE : 1;
		unsigned int               LC_ELEC_IDLE_MODE : 2;
		unsigned int LC_DISABLE_INFERRED_ELEC_IDLE_DET : 1;
		unsigned int             LC_ALLOW_PDWN_IN_L1 : 1;
		unsigned int            LC_ALLOW_PDWN_IN_L23 : 1;
		unsigned int        LC_DEASSERT_RX_EN_IN_L0S : 1;
		unsigned int          LC_BLOCK_EL_IDLE_IN_L0 : 1;
		unsigned int        LC_RCV_L0_TO_RCV_L0S_DIS : 1;
		unsigned int  LC_ASSERT_INACTIVE_DURING_HOLD : 1;
		unsigned int     LC_WAIT_FOR_LANES_IN_LW_NEG : 2;
		unsigned int       LC_PWR_DOWN_NEG_OFF_LANES : 1;
		unsigned int   LC_DISABLE_LOST_SYM_LOCK_ARCS : 1;
		unsigned int     LC_LINK_BW_NOTIFICATION_DIS : 1;
		unsigned int                                 : 1;
		unsigned int               LC_TEST_TIMER_SEL : 2;
		unsigned int LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_CNTL3 {
	struct {
                unsigned int            LC_SELECT_DEEMPHASIS : 1;
                unsigned int       LC_SELECT_DEEMPHASIS_CNTL : 2;
                unsigned int              LC_RCVD_DEEMPHASIS : 1;
                unsigned int               LC_COMP_TO_DETECT : 1;
                unsigned int    LC_RESET_TSX_CNT_IN_RLOCK_EN : 1;
                unsigned int LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__CI__VI : 2;
                unsigned int LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__CI__VI : 1;
                unsigned int LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__CI__VI : 1;
                unsigned int LC_ENHANCED_HOT_PLUG_EN__CI__VI : 1;
                unsigned int LC_RCVR_DET_EN_OVERRIDE__CI__VI : 1;
                unsigned int       LC_EHP_RX_PHY_CMD__CI__VI : 2;
                unsigned int       LC_EHP_TX_PHY_CMD__CI__VI : 2;
                unsigned int LC_CHIP_BIF_USB_IDLE_EN__CI__VI : 1;
                unsigned int LC_L1_BLOCK_RECONFIG_EN__CI__VI : 1;
                unsigned int LC_AUTO_DISABLE_SPEED_SUPPORT_EN__CI__VI : 1;
                unsigned int LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__CI__VI : 2;
                unsigned int LC_FAST_L1_ENTRY_EXIT_EN__CI__VI : 1;
                unsigned int LC_RXPHYCMD_INACTIVE_EN_MODE__CI__VI : 1;
                unsigned int LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__CI__VI : 1;
                unsigned int LC_HW_VOLTAGE_IF_CONTROL__CI__VI : 2;
                unsigned int    LC_VOLTAGE_TIMER_SEL__CI__VI : 4;
                unsigned int       LC_GO_TO_RECOVERY__CI__VI : 1;
                unsigned int            LC_N_EIE_SEL__CI__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_CNTL4__CI {
	struct {
		unsigned int          LC_TX_ENABLE_BEHAVIOUR : 2;
		unsigned int                                 : 2;
		unsigned int                    LC_BYPASS_EQ : 1;
		unsigned int                      LC_REDO_EQ : 1;
		unsigned int                 LC_EXTEND_EIEOS : 1;
		unsigned int                LC_IGNORE_PARITY : 1;
		unsigned int               LC_EQ_SEARCH_MODE : 2;
		unsigned int                                 : 1;
		unsigned int              LC_USC_EQ_NOT_REQD : 1;
		unsigned int                 LC_USC_GO_TO_EQ : 1;
		unsigned int                  LC_SET_QUIESCE : 1;
		unsigned int                 LC_QUIESCE_RCVD : 1;
		unsigned int       LC_UNEXPECTED_COEFFS_RCVD : 1;
		unsigned int          LC_BYPASS_EQ_REQ_PHASE : 1;
		unsigned int LC_FORCE_PRESET_IN_EQ_REQ_PHASE : 1;
		unsigned int           LC_FORCE_PRESET_VALUE : 4;
		unsigned int              LC_USC_DELAY_DLLPS : 1;
		unsigned int           LC_PCIE_TX_FULL_SWING : 1;
		unsigned int        LC_EQ_WAIT_FOR_EVAL_DONE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_CNTL4__VI {
	struct {
		unsigned int          LC_TX_ENABLE_BEHAVIOUR : 2;
		unsigned int     LC_DIS_CONTIG_END_SET_CHECK : 1;
		unsigned int  LC_DIS_ASPM_L1_IN_SPEED_CHANGE : 1;
		unsigned int                    LC_BYPASS_EQ : 1;
		unsigned int                      LC_REDO_EQ : 1;
		unsigned int                 LC_EXTEND_EIEOS : 1;
		unsigned int                LC_IGNORE_PARITY : 1;
		unsigned int               LC_EQ_SEARCH_MODE : 2;
		unsigned int    LC_DSC_CHECK_COEFFS_IN_RLOCK : 1;
		unsigned int              LC_USC_EQ_NOT_REQD : 1;
		unsigned int                 LC_USC_GO_TO_EQ : 1;
		unsigned int                  LC_SET_QUIESCE : 1;
		unsigned int                 LC_QUIESCE_RCVD : 1;
		unsigned int       LC_UNEXPECTED_COEFFS_RCVD : 1;
		unsigned int          LC_BYPASS_EQ_REQ_PHASE : 1;
		unsigned int LC_FORCE_PRESET_IN_EQ_REQ_PHASE : 1;
		unsigned int           LC_FORCE_PRESET_VALUE : 4;
		unsigned int              LC_USC_DELAY_DLLPS : 1;
		unsigned int           LC_PCIE_TX_FULL_SWING : 1;
		unsigned int        LC_EQ_WAIT_FOR_EVAL_DONE : 1;
		unsigned int            LC_8GT_SKIP_ORDER_EN : 1;
		unsigned int    LC_WAIT_FOR_MORE_TS_IN_RLOCK : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_CNTL5__CI__VI {
	struct {
                unsigned int                      LC_EQ_FS_0 : 6;
                unsigned int                      LC_EQ_FS_8 : 6;
                unsigned int                      LC_EQ_LF_0 : 6;
                unsigned int                      LC_EQ_LF_8 : 6;
                unsigned int LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__VI : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_FORCE_COEFF__CI__VI {
	struct {
                unsigned int                  LC_FORCE_COEFF : 1;
                unsigned int             LC_FORCE_PRE_CURSOR : 6;
                unsigned int                 LC_FORCE_CURSOR : 6;
                unsigned int            LC_FORCE_POST_CURSOR : 6;
                unsigned int      LC_3X3_COEFF_SEARCH_EN__VI : 1;
                unsigned int             LC_PRESET_10_EN__VI : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_LANE_CNTL {
	struct {
		unsigned int              LC_CORRUPTED_LANES : 16;
		unsigned int                     LC_LANE_DIS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_LINK_WIDTH_CNTL {
	struct {
                unsigned int                   LC_LINK_WIDTH : 3;
                unsigned int                                 : 1;
                unsigned int                LC_LINK_WIDTH_RD : 3;
                unsigned int  LC_RECONFIG_ARC_MISSING_ESCAPE : 1;
                unsigned int                 LC_RECONFIG_NOW : 1;
                unsigned int        LC_RENEGOTIATION_SUPPORT : 1;
                unsigned int               LC_RENEGOTIATE_EN : 1;
                unsigned int            LC_SHORT_RECONFIG_EN : 1;
                unsigned int          LC_UPCONFIGURE_SUPPORT : 1;
                unsigned int              LC_UPCONFIGURE_DIS : 1;
                unsigned int      LC_UPCFG_WAIT_FOR_RCVR_DIS : 1;
                unsigned int              LC_UPCFG_TIMER_SEL : 1;
                unsigned int             LC_DEASSERT_TX_PDNB : 1;
                unsigned int               LC_L1_RECONFIG_EN : 1;
                unsigned int       LC_DYNLINK_MST_EN__CI__VI : 1;
                unsigned int LC_DUAL_END_RECONFIG_EN__CI__VI : 1;
                unsigned int  LC_UPCONFIGURE_CAPABLE__CI__VI : 1;
                unsigned int  LC_DYN_LANES_PWR_STATE__CI__VI : 2;
                unsigned int LC_EQ_REVERSAL_LOGIC_EN__CI__VI : 1;
                unsigned int   LC_MULT_REVERSE_ATTEMP_EN__VI : 1;
                unsigned int LC_RESET_TSX_CNT_IN_RCONFIG_EN__VI : 1;
                unsigned int LC_WAIT_FOR_L_IDLE_IN_R_IDLE__VI : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_N_FTS_CNTL {
	struct {
		unsigned int                   LC_XMIT_N_FTS : 8;
		unsigned int       LC_XMIT_N_FTS_OVERRIDE_EN : 1;
		unsigned int     LC_XMIT_FTS_BEFORE_RECOVERY : 1;
		unsigned int                                 : 6;
		unsigned int             LC_XMIT_N_FTS_LIMIT : 8;
		unsigned int                        LC_N_FTS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_SPEED_CNTL__CI__VI {
	struct {
                unsigned int                LC_GEN2_EN_STRAP : 1;
                unsigned int                LC_GEN3_EN_STRAP : 1;
                unsigned int LC_TARGET_LINK_SPEED_OVERRIDE_EN : 1;
                unsigned int   LC_TARGET_LINK_SPEED_OVERRIDE : 2;
                unsigned int     LC_FORCE_EN_SW_SPEED_CHANGE : 1;
                unsigned int    LC_FORCE_DIS_SW_SPEED_CHANGE : 1;
                unsigned int     LC_FORCE_EN_HW_SPEED_CHANGE : 1;
                unsigned int    LC_FORCE_DIS_HW_SPEED_CHANGE : 1;
                unsigned int   LC_INITIATE_LINK_SPEED_CHANGE : 1;
                unsigned int LC_SPEED_CHANGE_ATTEMPTS_ALLOWED : 2;
                unsigned int  LC_SPEED_CHANGE_ATTEMPT_FAILED : 1;
                unsigned int            LC_CURRENT_DATA_RATE : 2;
                unsigned int LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS : 1;
                unsigned int    LC_CLR_FAILED_SPD_CHANGE_CNT : 1;
                unsigned int   LC_1_OR_MORE_TS2_SPEED_ARC_EN : 1;
                unsigned int    LC_OTHER_SIDE_EVER_SENT_GEN2 : 1;
                unsigned int     LC_OTHER_SIDE_SUPPORTS_GEN2 : 1;
                unsigned int    LC_OTHER_SIDE_EVER_SENT_GEN3 : 1;
                unsigned int     LC_OTHER_SIDE_SUPPORTS_GEN3 : 1;
                unsigned int            LC_AUTO_RECOVERY_DIS : 1;
                unsigned int          LC_SPEED_CHANGE_STATUS : 1;
                unsigned int         LC_DATA_RATE_ADVERTISED : 2;
                unsigned int              LC_CHECK_DATA_RATE : 1;
                unsigned int LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN : 1;
                unsigned int     LC_INIT_SPEED_NEG_IN_L0s_EN : 1;
                unsigned int      LC_INIT_SPEED_NEG_IN_L1_EN : 1;
                unsigned int      LC_DONT_CHECK_EQTS_IN_RCFG : 1;
                unsigned int       LC_DELAY_COEFF_UPDATE_DIS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_SPEED_CNTL__SI {
	struct {
		unsigned int                LC_GEN2_EN_STRAP : 1;
		unsigned int LC_TARGET_LINK_SPEED_OVERRIDE_EN : 1;
		unsigned int   LC_TARGET_LINK_SPEED_OVERRIDE : 1;
		unsigned int     LC_FORCE_EN_SW_SPEED_CHANGE : 1;
		unsigned int    LC_FORCE_DIS_SW_SPEED_CHANGE : 1;
		unsigned int     LC_FORCE_EN_HW_SPEED_CHANGE : 1;
		unsigned int    LC_FORCE_DIS_HW_SPEED_CHANGE : 1;
		unsigned int   LC_INITIATE_LINK_SPEED_CHANGE : 1;
		unsigned int LC_SPEED_CHANGE_ATTEMPTS_ALLOWED : 2;
		unsigned int  LC_SPEED_CHANGE_ATTEMPT_FAILED : 1;
		unsigned int            LC_CURRENT_DATA_RATE : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS : 1;
		unsigned int    LC_CLR_FAILED_SPD_CHANGE_CNT : 1;
		unsigned int   LC_1_OR_MORE_TS2_SPEED_ARC_EN : 1;
		unsigned int    LC_OTHER_SIDE_EVER_SENT_GEN2 : 1;
		unsigned int     LC_OTHER_SIDE_SUPPORTS_GEN2 : 1;
		unsigned int            LC_AUTO_RECOVERY_DIS : 1;
		unsigned int          LC_SPEED_CHANGE_STATUS : 1;
		unsigned int         LC_DATA_RATE_ADVERTISED : 1;
		unsigned int              LC_CHECK_DATA_RATE : 1;
		unsigned int LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN : 1;
		unsigned int     LC_INIT_SPEED_NEG_IN_L0s_EN : 1;
		unsigned int      LC_INIT_SPEED_NEG_IN_L1_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE0 {
	struct {
		unsigned int                LC_CURRENT_STATE : 6;
		unsigned int                                 : 2;
		unsigned int                  LC_PREV_STATE1 : 6;
		unsigned int                                 : 2;
		unsigned int                  LC_PREV_STATE2 : 6;
		unsigned int                                 : 2;
		unsigned int                  LC_PREV_STATE3 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE1 {
	struct {
		unsigned int                  LC_PREV_STATE4 : 6;
		unsigned int                                 : 2;
		unsigned int                  LC_PREV_STATE5 : 6;
		unsigned int                                 : 2;
		unsigned int                  LC_PREV_STATE6 : 6;
		unsigned int                                 : 2;
		unsigned int                  LC_PREV_STATE7 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE10 {
	struct {
		unsigned int                 LC_PREV_STATE40 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE41 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE42 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE43 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE11 {
	struct {
		unsigned int                 LC_PREV_STATE44 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE45 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE46 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE47 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE2 {
	struct {
		unsigned int                  LC_PREV_STATE8 : 6;
		unsigned int                                 : 2;
		unsigned int                  LC_PREV_STATE9 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE10 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE11 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE3 {
	struct {
		unsigned int                 LC_PREV_STATE12 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE13 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE14 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE15 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE4 {
	struct {
		unsigned int                 LC_PREV_STATE16 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE17 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE18 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE19 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE5 {
	struct {
		unsigned int                 LC_PREV_STATE20 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE21 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE22 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE23 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE6 {
	struct {
		unsigned int                 LC_PREV_STATE24 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE25 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE26 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE27 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE7 {
	struct {
		unsigned int                 LC_PREV_STATE28 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE29 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE30 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE31 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE8 {
	struct {
		unsigned int                 LC_PREV_STATE32 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE33 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE34 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE35 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATE9 {
	struct {
		unsigned int                 LC_PREV_STATE36 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE37 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE38 : 6;
		unsigned int                                 : 2;
		unsigned int                 LC_PREV_STATE39 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATUS1 {
	struct {
		unsigned int                 LC_REVERSE_RCVR : 1;
		unsigned int                 LC_REVERSE_XMIT : 1;
		unsigned int         LC_OPERATING_LINK_WIDTH : 3;
		unsigned int          LC_DETECTED_LINK_WIDTH : 3;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_STATUS2 {
	struct {
		unsigned int         LC_TOTAL_INACTIVE_LANES : 16;
		unsigned int                 LC_TURN_ON_LANE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_TRAINING_CNTL__CI {
	struct {
		unsigned int                LC_TRAINING_CNTL : 4;
		unsigned int           LC_COMPLIANCE_RECEIVE : 1;
		unsigned int LC_LOOK_FOR_MORE_NON_MATCHING_TS1 : 1;
		unsigned int      LC_L0S_L1_TRAINING_CNTL_EN : 1;
		unsigned int          LC_L1_LONG_WAKE_FIX_EN : 1;
		unsigned int                  LC_POWER_STATE : 3;
		unsigned int   LC_DONT_GO_TO_L0S_IF_L1_ARMED : 1;
		unsigned int     LC_INIT_SPD_CHG_WITH_CSR_EN : 1;
		unsigned int    LC_DISABLE_TRAINING_BIT_ARCH : 1;
		unsigned int                                 : 2;
		unsigned int          LC_EXTEND_WAIT_FOR_SKP : 1;
		unsigned int        LC_AUTONOMOUS_CHANGE_OFF : 1;
		unsigned int          LC_UPCONFIGURE_CAP_OFF : 1;
		unsigned int               LC_HW_LINK_DIS_EN : 1;
		unsigned int               LC_LINK_DIS_BY_HW : 1;
		unsigned int      LC_STATIC_TX_PIPE_COUNT_EN : 1;
		unsigned int        LC_ASPM_L1_NAK_TIMER_SEL : 2;
		unsigned int LC_DONT_DEASSERT_RX_EN_IN_R_SPEED : 1;
		unsigned int  LC_DONT_DEASSERT_RX_EN_IN_TEST : 1;
		unsigned int      LC_RESET_ASPM_L1_NAK_TIMER : 1;
		unsigned int           LC_SHORT_RCFG_TIMEOUT : 1;
		unsigned int          LC_ALLOW_TX_L1_CONTROL : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_TRAINING_CNTL__VI {
	struct {
		unsigned int                LC_TRAINING_CNTL : 4;
		unsigned int           LC_COMPLIANCE_RECEIVE : 1;
		unsigned int LC_LOOK_FOR_MORE_NON_MATCHING_TS1 : 1;
		unsigned int      LC_L0S_L1_TRAINING_CNTL_EN : 1;
		unsigned int          LC_L1_LONG_WAKE_FIX_EN : 1;
		unsigned int                  LC_POWER_STATE : 3;
		unsigned int   LC_DONT_GO_TO_L0S_IF_L1_ARMED : 1;
		unsigned int     LC_INIT_SPD_CHG_WITH_CSR_EN : 1;
		unsigned int    LC_DISABLE_TRAINING_BIT_ARCH : 1;
		unsigned int        LC_WAIT_FOR_SETS_IN_RCFG : 1;
		unsigned int      LC_HOT_RESET_QUICK_EXIT_EN : 1;
		unsigned int          LC_EXTEND_WAIT_FOR_SKP : 1;
		unsigned int        LC_AUTONOMOUS_CHANGE_OFF : 1;
		unsigned int          LC_UPCONFIGURE_CAP_OFF : 1;
		unsigned int               LC_HW_LINK_DIS_EN : 1;
		unsigned int               LC_LINK_DIS_BY_HW : 1;
		unsigned int      LC_STATIC_TX_PIPE_COUNT_EN : 1;
		unsigned int        LC_ASPM_L1_NAK_TIMER_SEL : 2;
		unsigned int LC_DONT_DEASSERT_RX_EN_IN_R_SPEED : 1;
		unsigned int  LC_DONT_DEASSERT_RX_EN_IN_TEST : 1;
		unsigned int      LC_RESET_ASPM_L1_NAK_TIMER : 1;
		unsigned int           LC_SHORT_RCFG_TIMEOUT : 1;
		unsigned int          LC_ALLOW_TX_L1_CONTROL : 1;
		unsigned int LC_WAIT_FOR_FOM_VALID_AFTER_TRACK : 1;
		unsigned int           LC_EXTEND_EQ_REQ_TIME : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_TRAINING_CNTL__SI {
	struct {
		unsigned int                LC_TRAINING_CNTL : 4;
		unsigned int           LC_COMPLIANCE_RECEIVE : 1;
		unsigned int LC_LOOK_FOR_MORE_NON_MATCHING_TS1 : 1;
		unsigned int      LC_L0S_L1_TRAINING_CNTL_EN : 1;
		unsigned int          LC_L1_LONG_WAKE_FIX_EN : 1;
		unsigned int                  LC_POWER_STATE : 3;
		unsigned int   LC_DONT_GO_TO_L0S_IF_L1_ARMED : 1;
		unsigned int     LC_INIT_SPD_CHG_WITH_CSR_EN : 1;
		unsigned int                                 : 3;
		unsigned int          LC_EXTEND_WAIT_FOR_SKP : 1;
		unsigned int        LC_AUTONOMOUS_CHANGE_OFF : 1;
		unsigned int          LC_UPCONFIGURE_CAP_OFF : 1;
		unsigned int                                 : 2;
		unsigned int      LC_STATIC_TX_PIPE_COUNT_EN : 1;
		unsigned int        LC_ASPM_L1_NAK_TIMER_SEL : 2;
		unsigned int LC_DONT_DEASSERT_RX_EN_IN_R_SPEED : 1;
		unsigned int  LC_DONT_DEASSERT_RX_EN_IN_TEST : 1;
		unsigned int      LC_RESET_ASPM_L1_NAK_TIMER : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LINK_CNTL3__CI__VI {
	struct {
                unsigned int            PERFORM_EQUALIZATION : 1;
                unsigned int    LINK_EQUALIZATION_REQ_INT_EN : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI {
	struct {
                unsigned int         OUTSTAND_PAGE_REQ_ALLOC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI {
	struct {
                unsigned int      OUTSTAND_PAGE_REQ_CAPACITY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PAGE_REQ_CNTL__CI__VI {
	struct {
                unsigned int                      PRI_ENABLE : 1;
                unsigned int                       PRI_RESET : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI {
	struct {
                unsigned int                          CAP_ID : 16;
                unsigned int                         CAP_VER : 4;
                unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PAGE_REQ_STATUS__CI__VI {
	struct {
                unsigned int                RESPONSE_FAILURE : 1;
                unsigned int   UNEXPECTED_PAGE_REQ_GRP_INDEX : 1;
                unsigned int                                 : 6;
                unsigned int                         STOPPED : 1;
                unsigned int                                 : 6;
                unsigned int PRG_RESPONSE_PASID_REQUIRED__VI : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PASID_CAP__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int  PASID_EXE_PERMISSION_SUPPORTED : 1;
                unsigned int       PASID_PRIV_MODE_SUPPORTED : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 4;
                unsigned int                 MAX_PASID_WIDTH : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PASID_CNTL__CI__VI {
	struct {
                unsigned int                    PASID_ENABLE : 1;
                unsigned int     PASID_EXE_PERMISSION_ENABLE : 1;
                unsigned int PASID_PRIV_MODE_SUPPORTED_ENABLE : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PASID_ENH_CAP_LIST__CI__VI {
	struct {
                unsigned int                          CAP_ID : 16;
                unsigned int                         CAP_VER : 4;
                unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_CNTL_EVENT0_PORT_SEL {
	struct {
		unsigned int            PERF0_PORT_SEL_TXCLK : 4;
		unsigned int        PERF0_PORT_SEL_MST_R_CLK : 4;
		unsigned int        PERF0_PORT_SEL_MST_C_CLK : 4;
		unsigned int        PERF0_PORT_SEL_SLV_R_CLK : 4;
		unsigned int      PERF0_PORT_SEL_SLV_S_C_CLK : 4;
		unsigned int     PERF0_PORT_SEL_SLV_NS_C_CLK : 4;
		unsigned int           PERF0_PORT_SEL_TXCLK2 : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_CNTL_EVENT1_PORT_SEL {
	struct {
		unsigned int            PERF1_PORT_SEL_TXCLK : 4;
		unsigned int        PERF1_PORT_SEL_MST_R_CLK : 4;
		unsigned int        PERF1_PORT_SEL_MST_C_CLK : 4;
		unsigned int        PERF1_PORT_SEL_SLV_R_CLK : 4;
		unsigned int      PERF1_PORT_SEL_SLV_S_C_CLK : 4;
		unsigned int     PERF1_PORT_SEL_SLV_NS_C_CLK : 4;
		unsigned int           PERF1_PORT_SEL_TXCLK2 : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_CNTL_MST_C_CLK {
	struct {
		unsigned int                      EVENT0_SEL : 8;
		unsigned int                      EVENT1_SEL : 8;
		unsigned int                  COUNTER0_UPPER : 8;
		unsigned int                  COUNTER1_UPPER : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_CNTL_MST_R_CLK {
	struct {
		unsigned int                      EVENT0_SEL : 8;
		unsigned int                      EVENT1_SEL : 8;
		unsigned int                  COUNTER0_UPPER : 8;
		unsigned int                  COUNTER1_UPPER : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_CNTL_SLV_NS_C_CLK {
	struct {
		unsigned int                      EVENT0_SEL : 8;
		unsigned int                      EVENT1_SEL : 8;
		unsigned int                  COUNTER0_UPPER : 8;
		unsigned int                  COUNTER1_UPPER : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_CNTL_SLV_R_CLK {
	struct {
		unsigned int                      EVENT0_SEL : 8;
		unsigned int                      EVENT1_SEL : 8;
		unsigned int                  COUNTER0_UPPER : 8;
		unsigned int                  COUNTER1_UPPER : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_CNTL_SLV_S_C_CLK {
	struct {
		unsigned int                      EVENT0_SEL : 8;
		unsigned int                      EVENT1_SEL : 8;
		unsigned int                  COUNTER0_UPPER : 8;
		unsigned int                  COUNTER1_UPPER : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_CNTL_TXCLK {
	struct {
		unsigned int                      EVENT0_SEL : 8;
		unsigned int                      EVENT1_SEL : 8;
		unsigned int                  COUNTER0_UPPER : 8;
		unsigned int                  COUNTER1_UPPER : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_CNTL_TXCLK2 {
	struct {
		unsigned int                      EVENT0_SEL : 8;
		unsigned int                      EVENT1_SEL : 8;
		unsigned int                  COUNTER0_UPPER : 8;
		unsigned int                  COUNTER1_UPPER : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT0_MST_C_CLK {
	struct {
		unsigned int                        COUNTER0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT0_MST_R_CLK {
	struct {
		unsigned int                        COUNTER0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT0_SLV_NS_C_CLK {
	struct {
		unsigned int                        COUNTER0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT0_SLV_R_CLK {
	struct {
		unsigned int                        COUNTER0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT0_SLV_S_C_CLK {
	struct {
		unsigned int                        COUNTER0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT0_TXCLK {
	struct {
		unsigned int                        COUNTER0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT0_TXCLK2 {
	struct {
		unsigned int                        COUNTER0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT1_MST_C_CLK {
	struct {
		unsigned int                        COUNTER1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT1_MST_R_CLK {
	struct {
		unsigned int                        COUNTER1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT1_SLV_NS_C_CLK {
	struct {
		unsigned int                        COUNTER1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT1_SLV_R_CLK {
	struct {
		unsigned int                        COUNTER1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT1_SLV_S_C_CLK {
	struct {
		unsigned int                        COUNTER1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT1_TXCLK {
	struct {
		unsigned int                        COUNTER1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT1_TXCLK2 {
	struct {
		unsigned int                        COUNTER1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PERF_COUNT_CNTL {
	struct {
		unsigned int                 GLOBAL_COUNT_EN : 1;
		unsigned int                GLOBAL_SHADOW_WR : 1;
		unsigned int              GLOBAL_COUNT_RESET : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PORT_DATA__SI {
	struct {
		unsigned int                       PCIE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PORT_INDEX__SI {
	struct {
		unsigned int                      PCIE_INDEX : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PORT_VC_CAP_REG1 {
	struct {
		unsigned int                    EXT_VC_COUNT : 3;
		unsigned int                                 : 1;
		unsigned int       LOW_PRIORITY_EXT_VC_COUNT : 3;
		unsigned int                                 : 1;
		unsigned int                         REF_CLK : 2;
		unsigned int       PORT_ARB_TABLE_ENTRY_SIZE : 2;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PORT_VC_CAP_REG2 {
	struct {
		unsigned int                      VC_ARB_CAP : 8;
		unsigned int                                 : 16;
		unsigned int             VC_ARB_TABLE_OFFSET : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PORT_VC_CNTL {
	struct {
		unsigned int               LOAD_VC_ARB_TABLE : 1;
		unsigned int                   VC_ARB_SELECT : 3;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PORT_VC_STATUS {
	struct {
		unsigned int             VC_ARB_TABLE_STATUS : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_CLR {
	struct {
		unsigned int                        PRBS_CLR : 16;
		unsigned int   PRBS_CHECKER_DEBUG_BUS_SELECT : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_0 {
	struct {
		unsigned int                   PRBS_ERRCNT_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_1 {
	struct {
		unsigned int                   PRBS_ERRCNT_1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_10 {
	struct {
		unsigned int                  PRBS_ERRCNT_10 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_11 {
	struct {
		unsigned int                  PRBS_ERRCNT_11 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_12 {
	struct {
		unsigned int                  PRBS_ERRCNT_12 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_13 {
	struct {
		unsigned int                  PRBS_ERRCNT_13 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_14 {
	struct {
		unsigned int                  PRBS_ERRCNT_14 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_15 {
	struct {
		unsigned int                  PRBS_ERRCNT_15 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_2 {
	struct {
		unsigned int                   PRBS_ERRCNT_2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_3 {
	struct {
		unsigned int                   PRBS_ERRCNT_3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_4 {
	struct {
		unsigned int                   PRBS_ERRCNT_4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_5 {
	struct {
		unsigned int                   PRBS_ERRCNT_5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_6 {
	struct {
		unsigned int                   PRBS_ERRCNT_6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_7 {
	struct {
		unsigned int                   PRBS_ERRCNT_7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_8 {
	struct {
		unsigned int                   PRBS_ERRCNT_8 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_ERRCNT_9 {
	struct {
		unsigned int                   PRBS_ERRCNT_9 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_FREERUN {
	struct {
		unsigned int                    PRBS_FREERUN : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_HI_BITCNT {
	struct {
		unsigned int                  PRBS_HI_BITCNT : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_LO_BITCNT {
	struct {
		unsigned int                  PRBS_LO_BITCNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_MISC__CI {
	struct {
		unsigned int                         PRBS_EN : 1;
		unsigned int                  PRBS_TEST_MODE : 2;
		unsigned int        PRBS_USER_PATTERN_TOGGLE : 1;
		unsigned int                   PRBS_8BIT_SEL : 1;
		unsigned int                  PRBS_COMMA_NUM : 2;
		unsigned int                   PRBS_LOCK_CNT : 5;
		unsigned int                                 : 2;
		unsigned int                  PRBS_DATA_RATE : 2;
		unsigned int               PRBS_CHK_ERR_MASK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_MISC__VI {
	struct {
		unsigned int                         PRBS_EN : 1;
		unsigned int                  PRBS_TEST_MODE : 3;
		unsigned int        PRBS_USER_PATTERN_TOGGLE : 1;
		unsigned int                   PRBS_8BIT_SEL : 1;
		unsigned int                  PRBS_COMMA_NUM : 2;
		unsigned int                   PRBS_LOCK_CNT : 5;
		unsigned int                                 : 1;
		unsigned int                  PRBS_DATA_RATE : 2;
		unsigned int               PRBS_CHK_ERR_MASK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_MISC__SI {
	struct {
		unsigned int                         PRBS_EN : 1;
		unsigned int                  PRBS_TEST_MODE : 2;
		unsigned int        PRBS_USER_PATTERN_TOGGLE : 1;
		unsigned int                   PRBS_8BIT_SEL : 1;
		unsigned int                  PRBS_COMMA_NUM : 2;
		unsigned int                   PRBS_LOCK_CNT : 5;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int               PRBS_CHK_ERR_MASK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_STATUS1 {
	struct {
		unsigned int                    PRBS_ERRSTAT : 16;
		unsigned int                     PRBS_LOCKED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_STATUS2 {
	struct {
		unsigned int                PRBS_BITCNT_DONE : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_USER_PATTERN__CI__VI {
	struct {
                unsigned int               PRBS_USER_PATTERN : 30;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PRBS_USER_PATTERN__SI {
	struct {
		unsigned int                                 : 30;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PWR_BUDGET_CAP__CI__VI {
	struct {
                unsigned int                SYSTEM_ALLOCATED : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PWR_BUDGET_DATA_SELECT__CI__VI {
	struct {
                unsigned int                     DATA_SELECT : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PWR_BUDGET_DATA__CI__VI {
	struct {
                unsigned int                      BASE_POWER : 8;
                unsigned int                      DATA_SCALE : 2;
                unsigned int                    PM_SUB_STATE : 3;
                unsigned int                        PM_STATE : 2;
                unsigned int                            TYPE : 3;
                unsigned int                      POWER_RAIL : 3;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI {
	struct {
                unsigned int                          CAP_ID : 16;
                unsigned int                         CAP_VER : 4;
                unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_P_BUF_STATUS__CI__VI {
	struct {
                unsigned int                  P_OVERFLOW_ERR : 16;
                unsigned int                 P_UNDERFLOW_ERR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_P_BUF_STATUS__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_P_CNTL__CI__VI {
	struct {
                unsigned int                      P_PWRDN_EN : 1;
                unsigned int                 P_SYMALIGN_MODE : 1;
                unsigned int             P_SYMALIGN_HW_DEBUG : 1;
                unsigned int          P_ELASTDESKEW_HW_DEBUG : 1;
                unsigned int                P_IGNORE_CRC_ERR : 1;
                unsigned int                P_IGNORE_LEN_ERR : 1;
                unsigned int                P_IGNORE_EDB_ERR : 1;
                unsigned int                P_IGNORE_IDL_ERR : 1;
                unsigned int                P_IGNORE_TOK_ERR : 1;
                unsigned int                                 : 3;
                unsigned int                 P_BLK_LOCK_MODE : 1;
                unsigned int         P_ALWAYS_USE_FAST_TXCLK : 1;
                unsigned int                P_ELEC_IDLE_MODE : 2;
                unsigned int             DLP_IGNORE_IN_L1_EN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_P_CNTL__SI {
	struct {
		unsigned int                      P_PWRDN_EN : 1;
		unsigned int                 P_SYMALIGN_MODE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int         P_ALWAYS_USE_FAST_TXCLK : 1;
		unsigned int                P_ELEC_IDLE_MODE : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_P_DECODER_STATUS__CI__VI {
	struct {
                unsigned int                    P_DECODE_ERR : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_P_DECODER_STATUS__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_P_MISC_STATUS__CI__VI {
	struct {
                unsigned int                    P_DESKEW_ERR : 8;
                unsigned int                                 : 8;
                unsigned int                 P_SYMUNLOCK_ERR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_P_PORT_LANE_STATUS {
	struct {
		unsigned int              PORT_LANE_REVERSAL : 1;
		unsigned int                  PHY_LINK_WIDTH : 6;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_P_RCV_L0S_FTS_DET__CI__VI {
	struct {
                unsigned int           P_RCV_L0S_FTS_DET_MIN : 8;
                unsigned int           P_RCV_L0S_FTS_DET_MAX : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RESERVED {
	struct {
		unsigned int                   PCIE_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_CNTL2__CI__VI {
	struct {
                unsigned int    RX_IGNORE_EP_INVALIDPASID_UR : 1;
                unsigned int        RX_IGNORE_EP_TRANSMRD_UR : 1;
                unsigned int        RX_IGNORE_EP_TRANSMWR_UR : 1;
                unsigned int     RX_IGNORE_EP_ATSTRANSREQ_UR : 1;
                unsigned int      RX_IGNORE_EP_PAGEREQMSG_UR : 1;
                unsigned int          RX_IGNORE_EP_INVCPL_UR : 1;
                unsigned int                                 : 2;
                unsigned int           RX_RCB_LATENCY_EN__VI : 1;
                unsigned int        RX_RCB_LATENCY_SCALE__VI : 3;
                unsigned int                                 : 4;
                unsigned int    RX_RCB_LATENCY_MAX_COUNT__VI : 10;
                unsigned int                                 : 2;
                unsigned int             FLR_EXTEND_MODE__VI : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_CNTL3__CI__VI {
	struct {
                unsigned int   RX_IGNORE_RC_TRANSMRDPASID_UR : 1;
                unsigned int   RX_IGNORE_RC_TRANSMWRPASID_UR : 1;
                unsigned int      RX_IGNORE_RC_PRGRESPMSG_UR : 1;
                unsigned int          RX_IGNORE_RC_INVREQ_UR : 1;
                unsigned int     RX_IGNORE_RC_INVCPLPASID_UR : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_CNTL__CI__VI {
	struct {
                unsigned int                RX_IGNORE_IO_ERR : 1;
                unsigned int                RX_IGNORE_BE_ERR : 1;
                unsigned int               RX_IGNORE_MSG_ERR : 1;
                unsigned int               RX_IGNORE_CRC_ERR : 1;
                unsigned int               RX_IGNORE_CFG_ERR : 1;
                unsigned int               RX_IGNORE_CPL_ERR : 1;
                unsigned int                RX_IGNORE_EP_ERR : 1;
                unsigned int      RX_IGNORE_LEN_MISMATCH_ERR : 1;
                unsigned int       RX_IGNORE_MAX_PAYLOAD_ERR : 1;
                unsigned int                RX_IGNORE_TC_ERR : 1;
                unsigned int                RX_IGNORE_CFG_UR : 1;
                unsigned int                 RX_IGNORE_IO_UR : 1;
                unsigned int                RX_IGNORE_AT_ERR : 1;
                unsigned int             RX_NAK_IF_FIFO_FULL : 1;
                unsigned int                  RX_GEN_ONE_NAK : 1;
                unsigned int             RX_FC_INIT_FROM_REG : 1;
                unsigned int              RX_RCB_CPL_TIMEOUT : 3;
                unsigned int         RX_RCB_CPL_TIMEOUT_MODE : 1;
                unsigned int         RX_PCIE_CPL_TIMEOUT_DIS : 1;
                unsigned int       RX_IGNORE_SHORTPREFIX_ERR : 1;
                unsigned int         RX_IGNORE_MAXPREFIX_ERR : 1;
                unsigned int         RX_IGNORE_CPLPREFIX_ERR : 1;
                unsigned int      RX_IGNORE_INVALIDPASID_ERR : 1;
                unsigned int          RX_IGNORE_NOT_PASID_UR : 1;
                unsigned int                  RX_TPH_DIS__VI : 1;
                unsigned int      RX_RCB_FLR_TIMEOUT_DIS__VI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_CNTL__SI {
	struct {
		unsigned int                RX_IGNORE_IO_ERR : 1;
		unsigned int                RX_IGNORE_BE_ERR : 1;
		unsigned int               RX_IGNORE_MSG_ERR : 1;
		unsigned int               RX_IGNORE_CRC_ERR : 1;
		unsigned int               RX_IGNORE_CFG_ERR : 1;
		unsigned int               RX_IGNORE_CPL_ERR : 1;
		unsigned int                RX_IGNORE_EP_ERR : 1;
		unsigned int      RX_IGNORE_LEN_MISMATCH_ERR : 1;
		unsigned int       RX_IGNORE_MAX_PAYLOAD_ERR : 1;
		unsigned int                RX_IGNORE_TC_ERR : 1;
		unsigned int                RX_IGNORE_CFG_UR : 1;
		unsigned int                 RX_IGNORE_IO_UR : 1;
		unsigned int                                 : 1;
		unsigned int             RX_NAK_IF_FIFO_FULL : 1;
		unsigned int                  RX_GEN_ONE_NAK : 1;
		unsigned int             RX_FC_INIT_FROM_REG : 1;
		unsigned int              RX_RCB_CPL_TIMEOUT : 3;
		unsigned int         RX_RCB_CPL_TIMEOUT_MODE : 1;
		unsigned int         RX_PCIE_CPL_TIMEOUT_DIS : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_CREDITS_ALLOCATED_CPL {
	struct {
		unsigned int       RX_CREDITS_ALLOCATED_CPLD : 12;
		unsigned int                                 : 4;
		unsigned int       RX_CREDITS_ALLOCATED_CPLH : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_CREDITS_ALLOCATED_NP {
	struct {
		unsigned int        RX_CREDITS_ALLOCATED_NPD : 12;
		unsigned int                                 : 4;
		unsigned int        RX_CREDITS_ALLOCATED_NPH : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_CREDITS_ALLOCATED_P {
	struct {
		unsigned int         RX_CREDITS_ALLOCATED_PD : 12;
		unsigned int                                 : 4;
		unsigned int         RX_CREDITS_ALLOCATED_PH : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_EXPECTED_SEQNUM__CI__VI {
	struct {
                unsigned int              RX_EXPECTED_SEQNUM : 12;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_LAST_TLP0 {
	struct {
		unsigned int                    RX_LAST_TLP0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_LAST_TLP1 {
	struct {
		unsigned int                    RX_LAST_TLP1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_LAST_TLP2 {
	struct {
		unsigned int                    RX_LAST_TLP2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_LAST_TLP3 {
	struct {
		unsigned int                    RX_LAST_TLP3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_NUM_NAK_GENERATED__CI__VI {
	struct {
                unsigned int            RX_NUM_NAK_GENERATED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_NUM_NAK__CI__VI {
	struct {
                unsigned int                      RX_NUM_NAK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RX_VENDOR_SPECIFIC {
	struct {
		unsigned int                  RX_VENDOR_DATA : 24;
		unsigned int                RX_VENDOR_STATUS : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SCRATCH {
	struct {
		unsigned int                    PCIE_SCRATCH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SECONDARY_ENH_CAP_LIST__CI__VI {
	struct {
                unsigned int                          CAP_ID : 16;
                unsigned int                         CAP_VER : 4;
                unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_F0__CI {
	struct {
		unsigned int                     STRAP_F0_EN : 1;
		unsigned int  STRAP_F0_LEGACY_DEVICE_TYPE_EN : 1;
		unsigned int                 STRAP_F0_MSI_EN : 1;
		unsigned int                  STRAP_F0_VC_EN : 1;
		unsigned int                 STRAP_F0_DSN_EN : 1;
		unsigned int                 STRAP_F0_AER_EN : 1;
		unsigned int                 STRAP_F0_ACS_EN : 1;
		unsigned int                 STRAP_F0_BAR_EN : 1;
		unsigned int                 STRAP_F0_PWR_EN : 1;
		unsigned int                 STRAP_F0_DPA_EN : 1;
		unsigned int                 STRAP_F0_ATS_EN : 1;
		unsigned int            STRAP_F0_PAGE_REQ_EN : 1;
		unsigned int               STRAP_F0_PASID_EN : 1;
		unsigned int                  STRAP_F0_MC_EN : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_F0__VI {
	struct {
                unsigned int                     STRAP_F0_EN : 1;
                unsigned int  STRAP_F0_LEGACY_DEVICE_TYPE_EN : 1;
                unsigned int                 STRAP_F0_MSI_EN : 1;
                unsigned int                  STRAP_F0_VC_EN : 1;
                unsigned int                 STRAP_F0_DSN_EN : 1;
                unsigned int                 STRAP_F0_AER_EN : 1;
                unsigned int                 STRAP_F0_ACS_EN : 1;
                unsigned int                 STRAP_F0_BAR_EN : 1;
                unsigned int                 STRAP_F0_PWR_EN : 1;
                unsigned int                 STRAP_F0_DPA_EN : 1;
                unsigned int                 STRAP_F0_ATS_EN : 1;
                unsigned int            STRAP_F0_PAGE_REQ_EN : 1;
                unsigned int               STRAP_F0_PASID_EN : 1;
                unsigned int          STRAP_F0_ECRC_CHECK_EN : 1;
                unsigned int            STRAP_F0_ECRC_GEN_EN : 1;
                unsigned int       STRAP_F0_CPL_ABORT_ERR_EN : 1;
                unsigned int STRAP_F0_POISONED_ADVISORY_NONFATAL : 1;
                unsigned int                  STRAP_F0_MC_EN : 1;
                unsigned int              STRAP_F0_ATOMIC_EN : 1;
                unsigned int        STRAP_F0_ATOMIC_64BIT_EN : 1;
                unsigned int      STRAP_F0_ATOMIC_ROUTING_EN : 1;
                unsigned int          STRAP_F0_MSI_MULTI_CAP : 3;
                unsigned int      STRAP_F0_VFn_MSI_MULTI_CAP : 3;
                unsigned int STRAP_F0_MSI_PERVECTOR_MASK_CAP : 1;
                unsigned int STRAP_F0_NO_RO_ENABLED_P2P_PASSING : 1;
                unsigned int                 STRAP_F0_ARI_EN : 1;
                unsigned int               STRAP_F0_SRIOV_EN : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_F1__CI__VI {
	struct {
                unsigned int             STRAP_F1_EN__SI__CI : 1;
                unsigned int  STRAP_F1_LEGACY_DEVICE_TYPE_EN : 1;
                unsigned int                 STRAP_F1_MSI_EN : 1;
                unsigned int                  STRAP_F1_VC_EN : 1;
                unsigned int                 STRAP_F1_DSN_EN : 1;
                unsigned int                 STRAP_F1_AER_EN : 1;
                unsigned int                 STRAP_F1_ACS_EN : 1;
                unsigned int                 STRAP_F1_BAR_EN : 1;
                unsigned int                 STRAP_F1_PWR_EN : 1;
                unsigned int                 STRAP_F1_DPA_EN : 1;
                unsigned int                 STRAP_F1_ATS_EN : 1;
                unsigned int            STRAP_F1_PAGE_REQ_EN : 1;
                unsigned int               STRAP_F1_PASID_EN : 1;
                unsigned int      STRAP_F1_ECRC_CHECK_EN__VI : 1;
                unsigned int        STRAP_F1_ECRC_GEN_EN__VI : 1;
                unsigned int   STRAP_F1_CPL_ABORT_ERR_EN__VI : 1;
                unsigned int STRAP_F1_POISONED_ADVISORY_NONFATAL__VI : 1;
                unsigned int                                 : 1;
                unsigned int          STRAP_F1_ATOMIC_EN__VI : 1;
                unsigned int    STRAP_F1_ATOMIC_64BIT_EN__VI : 1;
                unsigned int  STRAP_F1_ATOMIC_ROUTING_EN__VI : 1;
                unsigned int      STRAP_F1_MSI_MULTI_CAP__VI : 3;
                unsigned int                                 : 3;
                unsigned int STRAP_F1_MSI_PERVECTOR_MASK_CAP__VI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_F2__CI__VI {
	struct {
                unsigned int             STRAP_F2_EN__SI__CI : 1;
                unsigned int  STRAP_F2_LEGACY_DEVICE_TYPE_EN : 1;
                unsigned int                 STRAP_F2_MSI_EN : 1;
                unsigned int                  STRAP_F2_VC_EN : 1;
                unsigned int                 STRAP_F2_DSN_EN : 1;
                unsigned int                 STRAP_F2_AER_EN : 1;
                unsigned int                 STRAP_F2_ACS_EN : 1;
                unsigned int                 STRAP_F2_BAR_EN : 1;
                unsigned int                 STRAP_F2_PWR_EN : 1;
                unsigned int                 STRAP_F2_DPA_EN : 1;
                unsigned int                 STRAP_F2_ATS_EN : 1;
                unsigned int            STRAP_F2_PAGE_REQ_EN : 1;
                unsigned int               STRAP_F2_PASID_EN : 1;
                unsigned int      STRAP_F2_ECRC_CHECK_EN__VI : 1;
                unsigned int        STRAP_F2_ECRC_GEN_EN__VI : 1;
                unsigned int   STRAP_F2_CPL_ABORT_ERR_EN__VI : 1;
                unsigned int STRAP_F2_POISONED_ADVISORY_NONFATAL__VI : 1;
                unsigned int                                 : 1;
                unsigned int          STRAP_F2_ATOMIC_EN__VI : 1;
                unsigned int    STRAP_F2_ATOMIC_64BIT_EN__VI : 1;
                unsigned int  STRAP_F2_ATOMIC_ROUTING_EN__VI : 1;
                unsigned int      STRAP_F2_MSI_MULTI_CAP__VI : 3;
                unsigned int                                 : 3;
                unsigned int STRAP_F2_MSI_PERVECTOR_MASK_CAP__VI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_F3__CI__VI {
	struct {
                unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_F4__CI__VI {
	struct {
                unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_F5__CI__VI {
	struct {
                unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_F6__CI__VI {
	struct {
                unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_F7__CI__VI {
	struct {
                unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_I2C_BD {
	struct {
		unsigned int           STRAP_BIF_I2C_SLV_ADR : 7;
		unsigned int            STRAP_BIF_DBG_I2C_EN : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_MISC2 {
	struct {
                unsigned int                                 : 1;
                unsigned int           STRAP_GEN2_COMPLIANCE : 1;
                unsigned int         STRAP_MSTCPL_TIMEOUT_EN : 1;
                unsigned int   STRAP_GEN3_COMPLIANCE__CI__VI : 1;
                unsigned int     STRAP_TPH_SUPPORTED__CI__VI : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_MISC__CI__VI {
	struct {
                unsigned int       STRAP_LINK_CONFIG__SI__CI : 4;
                unsigned int             STRAP_TL_ALT_BUF_EN : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int           STRAP_MAX_PASID_WIDTH : 5;
                unsigned int STRAP_PASID_EXE_PERMISSION_SUPPORTED : 1;
                unsigned int STRAP_PASID_PRIV_MODE_SUPPORTED : 1;
                unsigned int STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED : 1;
                unsigned int                                 : 8;
                unsigned int                 STRAP_CLK_PM_EN : 1;
                unsigned int                 STRAP_ECN1P1_EN : 1;
                unsigned int              STRAP_EXT_VC_COUNT : 1;
                unsigned int                                 : 1;
                unsigned int               STRAP_REVERSE_ALL : 1;
                unsigned int              STRAP_MST_ADR64_EN : 1;
                unsigned int                    STRAP_FLR_EN : 1;
                unsigned int       STRAP_INTERNAL_ERR_EN__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_MISC__SI {
	struct {
		unsigned int               STRAP_LINK_CONFIG : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 STRAP_CLK_PM_EN : 1;
		unsigned int                 STRAP_ECN1P1_EN : 1;
		unsigned int              STRAP_EXT_VC_COUNT : 1;
		unsigned int                                 : 1;
		unsigned int               STRAP_REVERSE_ALL : 1;
		unsigned int              STRAP_MST_ADR64_EN : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_STRAP_PI {
	struct {
                unsigned int            STRAP_QUICKSIM_START : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 4;
                unsigned int                                 : 4;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 4;
                unsigned int                                 : 1;
                unsigned int                                 : 2;
                unsigned int       STRAP_TEST_TOGGLE_PATTERN : 1;
                unsigned int          STRAP_TEST_TOGGLE_MODE : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TLP_PREFIX_LOG0__CI__VI {
	struct {
                unsigned int                      TLP_PREFIX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TLP_PREFIX_LOG1__CI__VI {
	struct {
                unsigned int                      TLP_PREFIX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TLP_PREFIX_LOG2__CI__VI {
	struct {
                unsigned int                      TLP_PREFIX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TLP_PREFIX_LOG3__CI__VI {
	struct {
                unsigned int                      TLP_PREFIX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_ACK_LATENCY_LIMIT__CI__VI {
	struct {
                unsigned int            TX_ACK_LATENCY_LIMIT : 12;
                unsigned int  TX_ACK_LATENCY_LIMIT_OVERWRITE : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_ACK_LATENCY_LIMIT__SI {
	struct {
		unsigned int            TX_ACK_LATENCY_LIMIT : 8;
		unsigned int  TX_ACK_LATENCY_LIMIT_OVERWRITE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_CNTL__CI__VI {
	struct {
                unsigned int                                 : 10;
                unsigned int                 TX_SNR_OVERRIDE : 2;
                unsigned int                  TX_RO_OVERRIDE : 2;
                unsigned int              TX_PACK_PACKET_DIS : 1;
                unsigned int                TX_FLUSH_TLP_DIS : 1;
                unsigned int                                 : 4;
                unsigned int                   TX_CPL_PASS_P : 1;
                unsigned int                    TX_NP_PASS_P : 1;
                unsigned int          TX_CLEAR_EXTRA_PM_REQS : 1;
                unsigned int        TX_FC_UPDATE_TIMEOUT_DIS : 1;
                unsigned int                   TX_F0_TPH_DIS : 1;
                unsigned int                   TX_F1_TPH_DIS : 1;
                unsigned int                   TX_F2_TPH_DIS : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_CNTL__SI {
	struct {
		unsigned int                                 : 10;
		unsigned int                 TX_SNR_OVERRIDE : 2;
		unsigned int                  TX_RO_OVERRIDE : 2;
		unsigned int              TX_PACK_PACKET_DIS : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                TX_FLUSH_TLP_DIS : 1;
		unsigned int                   TX_CPL_PASS_P : 1;
		unsigned int                    TX_NP_PASS_P : 1;
		unsigned int          TX_CLEAR_EXTRA_PM_REQS : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int            TX_FC_UPDATE_TIMEOUT : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_CREDITS_ADVT_CPL {
	struct {
		unsigned int            TX_CREDITS_ADVT_CPLD : 12;
		unsigned int                                 : 4;
		unsigned int            TX_CREDITS_ADVT_CPLH : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_CREDITS_ADVT_NP {
	struct {
		unsigned int             TX_CREDITS_ADVT_NPD : 12;
		unsigned int                                 : 4;
		unsigned int             TX_CREDITS_ADVT_NPH : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_CREDITS_ADVT_P {
	struct {
		unsigned int              TX_CREDITS_ADVT_PD : 12;
		unsigned int                                 : 4;
		unsigned int              TX_CREDITS_ADVT_PH : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_CREDITS_FCU_THRESHOLD__CI__VI {
	struct {
                unsigned int          TX_FCU_THRESHOLD_P_VC0 : 3;
                unsigned int                                 : 1;
                unsigned int         TX_FCU_THRESHOLD_NP_VC0 : 3;
                unsigned int                                 : 1;
                unsigned int        TX_FCU_THRESHOLD_CPL_VC0 : 3;
                unsigned int                                 : 5;
                unsigned int          TX_FCU_THRESHOLD_P_VC1 : 3;
                unsigned int                                 : 1;
                unsigned int         TX_FCU_THRESHOLD_NP_VC1 : 3;
                unsigned int                                 : 1;
                unsigned int        TX_FCU_THRESHOLD_CPL_VC1 : 3;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_CREDITS_INIT_CPL {
	struct {
		unsigned int            TX_CREDITS_INIT_CPLD : 12;
		unsigned int                                 : 4;
		unsigned int            TX_CREDITS_INIT_CPLH : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_CREDITS_INIT_NP {
	struct {
		unsigned int             TX_CREDITS_INIT_NPD : 12;
		unsigned int                                 : 4;
		unsigned int             TX_CREDITS_INIT_NPH : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_CREDITS_INIT_P {
	struct {
		unsigned int              TX_CREDITS_INIT_PD : 12;
		unsigned int                                 : 4;
		unsigned int              TX_CREDITS_INIT_PH : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_CREDITS_STATUS {
	struct {
		unsigned int               TX_CREDITS_ERR_PD : 1;
		unsigned int               TX_CREDITS_ERR_PH : 1;
		unsigned int              TX_CREDITS_ERR_NPD : 1;
		unsigned int              TX_CREDITS_ERR_NPH : 1;
		unsigned int             TX_CREDITS_ERR_CPLD : 1;
		unsigned int             TX_CREDITS_ERR_CPLH : 1;
		unsigned int                                 : 10;
		unsigned int        TX_CREDITS_CUR_STATUS_PD : 1;
		unsigned int        TX_CREDITS_CUR_STATUS_PH : 1;
		unsigned int       TX_CREDITS_CUR_STATUS_NPD : 1;
		unsigned int       TX_CREDITS_CUR_STATUS_NPH : 1;
		unsigned int      TX_CREDITS_CUR_STATUS_CPLD : 1;
		unsigned int      TX_CREDITS_CUR_STATUS_CPLH : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_F0_ATTR_CNTL__CI__VI {
	struct {
                unsigned int            TX_F0_IDO_OVERRIDE_P : 2;
                unsigned int           TX_F0_IDO_OVERRIDE_NP : 2;
                unsigned int          TX_F0_IDO_OVERRIDE_CPL : 2;
                unsigned int             TX_F0_RO_OVERRIDE_P : 2;
                unsigned int            TX_F0_RO_OVERRIDE_NP : 2;
                unsigned int            TX_F0_SNR_OVERRIDE_P : 2;
                unsigned int           TX_F0_SNR_OVERRIDE_NP : 2;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_F1_F2_ATTR_CNTL__CI__VI {
	struct {
                unsigned int            TX_F1_IDO_OVERRIDE_P : 2;
                unsigned int           TX_F1_IDO_OVERRIDE_NP : 2;
                unsigned int          TX_F1_IDO_OVERRIDE_CPL : 2;
                unsigned int             TX_F1_RO_OVERRIDE_P : 2;
                unsigned int            TX_F1_RO_OVERRIDE_NP : 2;
                unsigned int            TX_F1_SNR_OVERRIDE_P : 2;
                unsigned int           TX_F1_SNR_OVERRIDE_NP : 2;
                unsigned int                                 : 2;
                unsigned int            TX_F2_IDO_OVERRIDE_P : 2;
                unsigned int           TX_F2_IDO_OVERRIDE_NP : 2;
                unsigned int          TX_F2_IDO_OVERRIDE_CPL : 2;
                unsigned int             TX_F2_RO_OVERRIDE_P : 2;
                unsigned int            TX_F2_RO_OVERRIDE_NP : 2;
                unsigned int            TX_F2_SNR_OVERRIDE_P : 2;
                unsigned int           TX_F2_SNR_OVERRIDE_NP : 2;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_LAST_TLP0 {
	struct {
		unsigned int                    TX_LAST_TLP0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_LAST_TLP1 {
	struct {
		unsigned int                    TX_LAST_TLP1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_LAST_TLP2 {
	struct {
		unsigned int                    TX_LAST_TLP2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_LAST_TLP3 {
	struct {
		unsigned int                    TX_LAST_TLP3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_REPLAY {
	struct {
                unsigned int                   TX_REPLAY_NUM : 10;
                unsigned int                                 : 5;
                unsigned int       TX_REPLAY_TIMER_OVERWRITE : 1;
                unsigned int                 TX_REPLAY_TIMER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_REQUESTER_ID {
	struct {
		unsigned int        TX_REQUESTER_ID_FUNCTION : 3;
		unsigned int          TX_REQUESTER_ID_DEVICE : 5;
		unsigned int             TX_REQUESTER_ID_BUS : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_REQUEST_NUM_CNTL {
	struct {
                unsigned int                                 : 6;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 6;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 6;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int           TX_NUM_OUTSTANDING_NP : 6;
                unsigned int    TX_NUM_OUTSTANDING_NP_VC1_EN : 1;
                unsigned int        TX_NUM_OUTSTANDING_NP_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_SEQ {
	struct {
		unsigned int            TX_NEXT_TRANSMIT_SEQ : 12;
		unsigned int                                 : 4;
		unsigned int                     TX_ACKD_SEQ : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_VENDOR_SPECIFIC {
	struct {
		unsigned int                  TX_VENDOR_DATA : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_UNCORR_ERR_MASK {
	struct {
                unsigned int                                 : 4;
                unsigned int                    DLP_ERR_MASK : 1;
                unsigned int                 SURPDN_ERR_MASK : 1;
                unsigned int                                 : 6;
                unsigned int                    PSN_ERR_MASK : 1;
                unsigned int                     FC_ERR_MASK : 1;
                unsigned int                CPL_TIMEOUT_MASK : 1;
                unsigned int              CPL_ABORT_ERR_MASK : 1;
                unsigned int                  UNEXP_CPL_MASK : 1;
                unsigned int                   RCV_OVFL_MASK : 1;
                unsigned int                    MAL_TLP_MASK : 1;
                unsigned int                   ECRC_ERR_MASK : 1;
                unsigned int             UNSUPP_REQ_ERR_MASK : 1;
                unsigned int              ACS_VIOLATION_MASK : 1;
                unsigned int     UNCORR_INT_ERR_MASK__CI__VI : 1;
                unsigned int     MC_BLOCKED_TLP_MASK__CI__VI : 1;
                unsigned int ATOMICOP_EGRESS_BLOCKED_MASK__CI__VI : 1;
                unsigned int TLP_PREFIX_BLOCKED_ERR_MASK__CI__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_UNCORR_ERR_SEVERITY {
	struct {
                unsigned int                                 : 4;
                unsigned int                DLP_ERR_SEVERITY : 1;
                unsigned int             SURPDN_ERR_SEVERITY : 1;
                unsigned int                                 : 6;
                unsigned int                PSN_ERR_SEVERITY : 1;
                unsigned int                 FC_ERR_SEVERITY : 1;
                unsigned int            CPL_TIMEOUT_SEVERITY : 1;
                unsigned int          CPL_ABORT_ERR_SEVERITY : 1;
                unsigned int              UNEXP_CPL_SEVERITY : 1;
                unsigned int               RCV_OVFL_SEVERITY : 1;
                unsigned int                MAL_TLP_SEVERITY : 1;
                unsigned int               ECRC_ERR_SEVERITY : 1;
                unsigned int         UNSUPP_REQ_ERR_SEVERITY : 1;
                unsigned int          ACS_VIOLATION_SEVERITY : 1;
                unsigned int UNCORR_INT_ERR_SEVERITY__CI__VI : 1;
                unsigned int MC_BLOCKED_TLP_SEVERITY__CI__VI : 1;
                unsigned int ATOMICOP_EGRESS_BLOCKED_SEVERITY__CI__VI : 1;
                unsigned int TLP_PREFIX_BLOCKED_ERR_SEVERITY__CI__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_UNCORR_ERR_STATUS {
	struct {
                unsigned int                                 : 4;
                unsigned int                  DLP_ERR_STATUS : 1;
                unsigned int               SURPDN_ERR_STATUS : 1;
                unsigned int                                 : 6;
                unsigned int                  PSN_ERR_STATUS : 1;
                unsigned int                   FC_ERR_STATUS : 1;
                unsigned int              CPL_TIMEOUT_STATUS : 1;
                unsigned int            CPL_ABORT_ERR_STATUS : 1;
                unsigned int                UNEXP_CPL_STATUS : 1;
                unsigned int                 RCV_OVFL_STATUS : 1;
                unsigned int                  MAL_TLP_STATUS : 1;
                unsigned int                 ECRC_ERR_STATUS : 1;
                unsigned int           UNSUPP_REQ_ERR_STATUS : 1;
                unsigned int            ACS_VIOLATION_STATUS : 1;
                unsigned int   UNCORR_INT_ERR_STATUS__CI__VI : 1;
                unsigned int   MC_BLOCKED_TLP_STATUS__CI__VI : 1;
                unsigned int ATOMICOP_EGRESS_BLOCKED_STATUS__CI__VI : 1;
                unsigned int TLP_PREFIX_BLOCKED_ERR_STATUS__CI__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VC0_RESOURCE_CAP {
	struct {
		unsigned int                    PORT_ARB_CAP : 8;
		unsigned int                                 : 7;
		unsigned int              REJECT_SNOOP_TRANS : 1;
		unsigned int                  MAX_TIME_SLOTS : 6;
		unsigned int                                 : 2;
		unsigned int           PORT_ARB_TABLE_OFFSET : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VC0_RESOURCE_CNTL {
	struct {
		unsigned int                   TC_VC_MAP_TC0 : 1;
		unsigned int                 TC_VC_MAP_TC1_7 : 7;
		unsigned int                                 : 8;
		unsigned int             LOAD_PORT_ARB_TABLE : 1;
		unsigned int                 PORT_ARB_SELECT : 3;
		unsigned int                                 : 4;
		unsigned int                           VC_ID : 3;
		unsigned int                                 : 4;
		unsigned int                       VC_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VC0_RESOURCE_STATUS {
	struct {
		unsigned int           PORT_ARB_TABLE_STATUS : 1;
		unsigned int          VC_NEGOTIATION_PENDING : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VC1_RESOURCE_CAP {
	struct {
		unsigned int                    PORT_ARB_CAP : 8;
		unsigned int                                 : 7;
		unsigned int              REJECT_SNOOP_TRANS : 1;
		unsigned int                  MAX_TIME_SLOTS : 6;
		unsigned int                                 : 2;
		unsigned int           PORT_ARB_TABLE_OFFSET : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VC1_RESOURCE_CNTL {
	struct {
		unsigned int                   TC_VC_MAP_TC0 : 1;
		unsigned int                 TC_VC_MAP_TC1_7 : 7;
		unsigned int                                 : 8;
		unsigned int             LOAD_PORT_ARB_TABLE : 1;
		unsigned int                 PORT_ARB_SELECT : 3;
		unsigned int                                 : 4;
		unsigned int                           VC_ID : 3;
		unsigned int                                 : 4;
		unsigned int                       VC_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VC1_RESOURCE_STATUS {
	struct {
		unsigned int           PORT_ARB_TABLE_STATUS : 1;
		unsigned int          VC_NEGOTIATION_PENDING : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VC_ENH_CAP_LIST {
	struct {
		unsigned int                          CAP_ID : 16;
		unsigned int                         CAP_VER : 4;
		unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VENDOR_SPECIFIC1 {
	struct {
		unsigned int                         SCRATCH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VENDOR_SPECIFIC2 {
	struct {
		unsigned int                         SCRATCH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST {
	struct {
		unsigned int                          CAP_ID : 16;
		unsigned int                         CAP_VER : 4;
		unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VENDOR_SPECIFIC_HDR {
	struct {
		unsigned int                         VSEC_ID : 16;
		unsigned int                        VSEC_REV : 4;
		unsigned int                     VSEC_LENGTH : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_WPR_CNTL {
	struct {
		unsigned int            WPR_RESET_HOT_RST_EN : 1;
		unsigned int            WPR_RESET_LNK_DWN_EN : 1;
		unsigned int            WPR_RESET_LNK_DIS_EN : 1;
		unsigned int                WPR_RESET_COR_EN : 1;
		unsigned int                WPR_RESET_REG_EN : 1;
		unsigned int                WPR_RESET_STY_EN : 1;
		unsigned int                WPR_RESET_PHY_EN : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PEER0_FB_OFFSET_HI__CI__VI {
	struct {
                unsigned int              PEER0_FB_OFFSET_HI : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PEER0_FB_OFFSET_LO__CI__VI {
	struct {
                unsigned int              PEER0_FB_OFFSET_LO : 20;
                unsigned int                                 : 11;
                unsigned int                     PEER0_FB_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PEER1_FB_OFFSET_HI__CI__VI {
	struct {
                unsigned int              PEER1_FB_OFFSET_HI : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PEER1_FB_OFFSET_LO__CI__VI {
	struct {
                unsigned int              PEER1_FB_OFFSET_LO : 20;
                unsigned int                                 : 11;
                unsigned int                     PEER1_FB_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PEER2_FB_OFFSET_HI__CI__VI {
	struct {
                unsigned int              PEER2_FB_OFFSET_HI : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PEER2_FB_OFFSET_LO__CI__VI {
	struct {
                unsigned int              PEER2_FB_OFFSET_LO : 20;
                unsigned int                                 : 11;
                unsigned int                     PEER2_FB_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PEER3_FB_OFFSET_HI__CI__VI {
	struct {
                unsigned int              PEER3_FB_OFFSET_HI : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PEER3_FB_OFFSET_LO__CI__VI {
	struct {
                unsigned int              PEER3_FB_OFFSET_LO : 20;
                unsigned int                                 : 11;
                unsigned int                     PEER3_FB_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PEER_REG_RANGE0 {
	struct {
		unsigned int                      START_ADDR : 16;
		unsigned int                        END_ADDR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PEER_REG_RANGE1 {
	struct {
		unsigned int                      START_ADDR : 16;
		unsigned int                        END_ADDR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PHY_AUX_CNTL__SI__VI {
	struct {
                unsigned int          AUXSLAVE_PAD_SLEWN__VI : 1;
                unsigned int           AUXSLAVE_PAD_WAKE__VI : 1;
                unsigned int          AUXSLAVE_PAD_RXSEL__VI : 1;
                unsigned int           AUXSLAVE_PAD_MODE__VI : 1;
                unsigned int         DDCSLAVE_DATA_PD_EN__VI : 1;
                unsigned int            DDCSLAVE_DATA_EN__VI : 1;
                unsigned int          DDCSLAVE_CLK_PD_EN__VI : 1;
                unsigned int             DDCSLAVE_CLK_EN__VI : 1;
                unsigned int                                 : 4;
                unsigned int                   AUX_PAD_SLEWN : 1;
                unsigned int          AUXSLAVE_CLK_PD_EN__VI : 1;
                unsigned int                    AUX_PAD_WAKE : 1;
                unsigned int                                 : 1;
                unsigned int                   AUX_PAD_RXSEL : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE0_ARBITRATION_CONTROL3__SI__VI {
	struct {
                unsigned int               EFFICIENCY_WEIGHT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE1_ARBITRATION_CONTROL3__SI__VI {
	struct {
                unsigned int               EFFICIENCY_WEIGHT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE2_ARBITRATION_CONTROL3__SI__VI {
	struct {
                unsigned int               EFFICIENCY_WEIGHT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE3_ARBITRATION_CONTROL3__SI__VI {
	struct {
                unsigned int               EFFICIENCY_WEIGHT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE4_ARBITRATION_CONTROL3__SI__VI {
	struct {
                unsigned int               EFFICIENCY_WEIGHT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE5_ARBITRATION_CONTROL3__SI__VI {
	struct {
                unsigned int               EFFICIENCY_WEIGHT : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIXCLK1_RESYNC_CNTL__SI__VI {
	struct {
                unsigned int           PIXCLK1_RESYNC_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int           DCCG_DEEP_COLOR_CNTL1 : 2;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIXCLK2_RESYNC_CNTL__SI__VI {
	struct {
                unsigned int           PIXCLK2_RESYNC_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int           DCCG_DEEP_COLOR_CNTL2 : 2;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_TEST_CNTL {
	struct {
		unsigned int                     TST_SRC_SEL : 4;
		unsigned int                     TST_REF_SEL : 4;
		unsigned int                  REF_TEST_COUNT : 7;
		unsigned int                       TST_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                      TEST_COUNT : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PMI_CAP {
	struct {
		unsigned int                         VERSION : 3;
		unsigned int                       PME_CLOCK : 1;
		unsigned int                                 : 1;
		unsigned int               DEV_SPECIFIC_INIT : 1;
		unsigned int                     AUX_CURRENT : 3;
		unsigned int                      D1_SUPPORT : 1;
		unsigned int                      D2_SUPPORT : 1;
		unsigned int                     PME_SUPPORT : 5;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PMI_CAP_LIST {
	struct {
		unsigned int                          CAP_ID : 8;
		unsigned int                        NEXT_PTR : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PMI_STATUS_CNTL {
	struct {
		unsigned int                     POWER_STATE : 2;
		unsigned int                                 : 1;
		unsigned int                   NO_SOFT_RESET : 1;
		unsigned int                                 : 4;
		unsigned int                          PME_EN : 1;
		unsigned int                     DATA_SELECT : 4;
		unsigned int                      DATA_SCALE : 2;
		unsigned int                      PME_STATUS : 1;
		unsigned int                                 : 6;
		unsigned int                   B2_B3_SUPPORT : 1;
		unsigned int                      BUS_PWR_EN : 1;
		unsigned int                        PMI_DATA : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PROG_INTERFACE {
	struct {
		unsigned int                  PROG_INTERFACE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_BCI_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_BCI_SIGNATURE1 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_CB_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_DB_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_IA_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_IA_SIGNATURE1 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_PA_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SC_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SC_SIGNATURE1 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SC_SIGNATURE2 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SC_SIGNATURE3 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SC_SIGNATURE4 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SC_SIGNATURE5 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SC_SIGNATURE6 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SC_SIGNATURE7 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SIGNATURE_CONTROL {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SIGNATURE_MASK {
	struct {
		unsigned int                  INPUT_BUS_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SPI_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SPI_SIGNATURE1 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SQ_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SX_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SX_SIGNATURE1 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SX_SIGNATURE2 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_SX_SIGNATURE3 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_TA_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_TD_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_VGT_SIGNATURE0 {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RCU_MISC_CTRL__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                REG_DRV_RST_MODE : 1;
                unsigned int                                 : 1;
                unsigned int              REG_RCU_MEMREP_DIS : 1;
                unsigned int             REG_CC_FUSE_DISABLE : 1;
                unsigned int           REG_SAMU_FUSE_DISABLE : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int          REG_CC_SRBM_RD_DISABLE : 1;
                unsigned int                                 : 7;
                unsigned int                  BREAK_PT1_DONE : 1;
                unsigned int                  BREAK_PT2_DONE : 1;
                unsigned int                                 : 3;
                unsigned int                                 : 1;
                unsigned int                      SAMU_START : 1;
                unsigned int                 RST_PULSE_WIDTH : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RCU_MISC_CTRL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 RST_PULSE_WIDTH : 10;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RCU_UC_EVENTS__CI__VI {
	struct {
                unsigned int             RCU_TST_jpc_rep_req : 1;
                unsigned int            TST_RCU_jpc_rep_done : 1;
                unsigned int                    drv_rst_mode : 1;
                unsigned int     SMU_DC_efuse_status_invalid : 1;
                unsigned int                                 : 2;
                unsigned int                       TP_Tester : 1;
                unsigned int                   boot_seq_done : 1;
                unsigned int            sclk_deep_sleep_exit : 1;
                unsigned int                BREAK_PT1_ACTIVE : 1;
                unsigned int                BREAK_PT2_ACTIVE : 1;
                unsigned int                        FCH_HALT : 1;
                unsigned int                                 : 1;
                unsigned int            RCU_GIO_fch_lockdown : 1;
                unsigned int                                 : 2;
                unsigned int              INTERRUPTS_ENABLED : 1;
                unsigned int                RCU_DtmCnt0_Done : 1;
                unsigned int                RCU_DtmCnt1_Done : 1;
                unsigned int                RCU_DtmCnt2_Done : 1;
                unsigned int                                 : 4;
                unsigned int                                 : 2;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RCU_UC_EVENTS__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RESPONSE_INTERRUPT_COUNT__SI__VI {
	struct {
                unsigned int      N_RESPONSE_INTERRUPT_COUNT : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REVISION_ID {
	struct {
		unsigned int                    MINOR_REV_ID : 4;
		unsigned int                    MAJOR_REV_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RE_STAT__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RINGOSC_MASK {
	struct {
		unsigned int                            MASK : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RIRB_CONTROL__SI__VI {
	struct {
                unsigned int      RESPONSE_INTERRUPT_CONTROL : 1;
                unsigned int                 RIRB_DMA_ENABLE : 1;
                unsigned int RESPONSE_OVERRUN_INTERRUPT_CONTROL : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RIRB_LOWER_BASE_ADDRESS__SI__VI {
	struct {
                unsigned int RIRB_LOWER_BASE_UNIMPLEMENTED_BITS : 7;
                unsigned int         RIRB_LOWER_BASE_ADDRESS : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RIRB_SIZE__SI__VI {
	struct {
                unsigned int                       RIRB_SIZE : 2;
                unsigned int                                 : 2;
                unsigned int            RIRB_SIZE_CAPABILITY : 4;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RIRB_STATUS__SI__VI {
	struct {
                unsigned int              RESPONSE_INTERRUPT : 1;
                unsigned int                                 : 1;
                unsigned int RESPONSE_OVERRUN_INTERRUPT_STATUS : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RIRB_UPPER_BASE_ADDRESS__SI__VI {
	struct {
                unsigned int         RIRB_UPPER_BASE_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RIRB_WRITE_POINTER__SI__VI {
	struct {
                unsigned int              RIRB_WRITE_POINTER : 8;
                unsigned int                                 : 7;
                unsigned int        RIRB_WRITE_POINTER_RESET : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_AUTO_PG_CTRL {
	struct {
		unsigned int                      AUTO_PG_EN : 1;
		unsigned int   AUTO_GRBM_REG_SAVE_ON_IDLE_EN : 1;
		unsigned int                 AUTO_WAKE_UP_EN : 1;
		unsigned int GRBM_REG_SAVE_GFX_IDLE_THRESHOLD : 16;
		unsigned int PG_AFTER_GRBM_REG_SAVE_THRESHOLD : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CAPTURE_GPU_CLOCK_COUNT {
	struct {
		unsigned int                         CAPTURE : 1;
		unsigned int                        RESERVED : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CGCG_CGLS_CTRL__CI {
	struct {
		unsigned int                         CGCG_EN : 1;
		unsigned int                         CGLS_EN : 1;
		unsigned int        CGLS_REP_COMPANSAT_DELAY : 6;
		unsigned int         CGCG_GFX_IDLE_THRESHOLD : 19;
		unsigned int                 CGCG_CONTROLLER : 1;
		unsigned int                   CGCG_REG_CTRL : 1;
		unsigned int                      SLEEP_MODE : 2;
		unsigned int                           SPARE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CGCG_CGLS_CTRL__VI {
	struct {
		unsigned int                         CGCG_EN : 1;
		unsigned int                         CGLS_EN : 1;
		unsigned int        CGLS_REP_COMPANSAT_DELAY : 6;
		unsigned int         CGCG_GFX_IDLE_THRESHOLD : 19;
		unsigned int                 CGCG_CONTROLLER : 1;
		unsigned int                   CGCG_REG_CTRL : 1;
		unsigned int                      SLEEP_MODE : 2;
		unsigned int                  SIM_SILICON_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CGCG_CGLS_CTRL__SI {
	struct {
		unsigned int                         CGCG_EN : 1;
		unsigned int                         CGLS_EN : 1;
		unsigned int        CGLS_REP_COMPANSAT_DELAY : 6;
		unsigned int         CGCG_GFX_IDLE_THRESHOLD : 8;
		unsigned int                                 : 11;
		unsigned int                 CGCG_CONTROLLER : 1;
		unsigned int                   CGCG_REG_CTRL : 1;
		unsigned int                      SLEEP_MODE : 2;
		unsigned int                           SPARE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CGCG_RAMP_CTRL {
	struct {
		unsigned int             DOWN_DIV_START_UNIT : 4;
		unsigned int              DOWN_DIV_STEP_UNIT : 4;
		unsigned int               UP_DIV_START_UNIT : 4;
		unsigned int                UP_DIV_STEP_UNIT : 4;
		unsigned int                  STEP_DELAY_CNT : 12;
		unsigned int                 STEP_DELAY_UNIT : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CGTT_MGCG_OVERRIDE {
	struct {
		unsigned int                        OVERRIDE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CNTL {
	struct {
		unsigned int                  RLC_ENABLE_F32 : 1;
		unsigned int                     FORCE_RETRY : 1;
		unsigned int              READ_CACHE_DISABLE : 1;
		unsigned int                    RLC_STEP_F32 : 1;
		unsigned int           SOFT_RESET_DEBUG_MODE : 1;
		unsigned int                                 : 3;
		unsigned int                        RESERVED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CU_STATUS__CI__VI {
	struct {
                unsigned int                    WORK_PENDING : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CU_STATUS__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_DEBUG {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_DEBUG_SELECT {
	struct {
                unsigned int                          SELECT : 8;
                unsigned int                                 : 6;
                unsigned int                                 : 1;
                unsigned int                        RESERVED : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_DRIVER_CPDMA_STATUS {
	struct {
		unsigned int                  DRIVER_REQUEST : 1;
		unsigned int                       RESERVED1 : 3;
		unsigned int                      DRIVER_ACK : 1;
		unsigned int                        RESERVED : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_DYN_PG_REQUEST__CI__VI {
	struct {
                unsigned int              PG_REQUEST_CU_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_DYN_PG_REQUEST__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_DYN_PG_STATUS__CI__VI {
	struct {
                unsigned int               PG_STATUS_CU_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_DYN_PG_STATUS__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_CU_PD_TIMEOUT__CI__VI {
	struct {
                unsigned int                         TIMEOUT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_DEBUG_SELECT__CI__VI {
	struct {
                unsigned int                          SELECT : 8;
                unsigned int            F32_DEBUG_SELECT__VI : 2;
                unsigned int                    RESERVED__VI : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_DEBUG__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_GENERAL_0__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_GENERAL_1__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_GENERAL_2__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_GENERAL_3__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_GENERAL_4__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_GENERAL_5__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_GENERAL_6__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_GENERAL_7__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_LOG_ADDR__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_LOG_CONT__CI__VI {
	struct {
                unsigned int                            CONT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_LOG_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_PERF_COUNT_0__CI__VI {
	struct {
                unsigned int                     FEATURE_SEL : 4;
                unsigned int                        SE_INDEX : 4;
                unsigned int                        SH_INDEX : 4;
                unsigned int                        CU_INDEX : 4;
                unsigned int                       EVENT_SEL : 2;
                unsigned int                                 : 2;
                unsigned int                          ENABLE : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_PERF_COUNT_1__CI__VI {
	struct {
                unsigned int                     FEATURE_SEL : 4;
                unsigned int                        SE_INDEX : 4;
                unsigned int                        SH_INDEX : 4;
                unsigned int                        CU_INDEX : 4;
                unsigned int                       EVENT_SEL : 2;
                unsigned int                                 : 2;
                unsigned int                          ENABLE : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_SCRATCH_ADDR__CI__VI {
	struct {
                unsigned int                            ADDR : 9;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_SCRATCH_DATA__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_STAT__CI__VI {
	struct {
                unsigned int                        RLC_BUSY : 1;
                unsigned int                GFX_POWER_STATUS : 1;
                unsigned int                GFX_CLOCK_STATUS : 1;
                unsigned int                   GFX_LS_STATUS : 1;
                unsigned int   GFX_PIPELINE_POWER_STATUS__VI : 1;
                unsigned int   CNTX_IDLE_BEING_PROCESSED__VI : 1;
                unsigned int   CNTX_BUSY_BEING_PROCESSED__VI : 1;
                unsigned int    GFX_IDLE_BEING_PROCESSED__VI : 1;
                unsigned int    CMP_BUSY_BEING_PROCESSED__VI : 1;
                unsigned int            SAVING_REGISTERS__VI : 1;
                unsigned int         RESTORING_REGISTERS__VI : 1;
                unsigned int GFX3D_BLOCKS_CHANGING_POWER_STATE__VI : 1;
                unsigned int CMP_BLOCKS_CHANGING_POWER_STATE__VI : 1;
                unsigned int       STATIC_CU_POWERING_UP__VI : 1;
                unsigned int     STATIC_CU_POWERING_DOWN__VI : 1;
                unsigned int          DYN_CU_POWERING_UP__VI : 1;
                unsigned int        DYN_CU_POWERING_DOWN__VI : 1;
                unsigned int         ABORTED_PD_SEQUENCE__VI : 1;
                unsigned int                    RESERVED__VI : 6;
                unsigned int             PG_ERROR_STATUS__VI : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_THREAD_ENABLE__CI__VI {
	struct {
                unsigned int                  THREAD0_ENABLE : 1;
                unsigned int                  THREAD1_ENABLE : 1;
                unsigned int                  THREAD2_ENABLE : 1;
                unsigned int                  THREAD3_ENABLE : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_THREAD_PRIORITY__CI__VI {
	struct {
                unsigned int                THREAD0_PRIORITY : 8;
                unsigned int                THREAD1_PRIORITY : 8;
                unsigned int                THREAD2_PRIORITY : 8;
                unsigned int                THREAD3_PRIORITY : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_UCODE_ADDR__CI__VI {
	struct {
                unsigned int                      UCODE_ADDR : 12;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_UCODE_DATA__CI__VI {
	struct {
                unsigned int                      UCODE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_VMID_THREAD0__CI__VI {
	struct {
                unsigned int                        RLC_VMID : 4;
                unsigned int                                 : 4;
                unsigned int                 RLC_QUEUEID__VI : 3;
                unsigned int                   RESERVED1__VI : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_VMID_THREAD1__CI__VI {
	struct {
                unsigned int                        RLC_VMID : 4;
                unsigned int                                 : 4;
                unsigned int                 RLC_QUEUEID__VI : 3;
                unsigned int                   RESERVED1__VI : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPR_REG1__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPR_REG2__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_CLOCK_32 {
	struct {
		unsigned int                    GPU_CLOCK_32 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_CLOCK_32_RES_SEL {
	struct {
		unsigned int                         RES_SEL : 6;
		unsigned int                        RESERVED : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_CLOCK_COUNT_LSB {
	struct {
		unsigned int                  GPU_CLOCKS_LSB : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_CLOCK_COUNT_MSB {
	struct {
		unsigned int                  GPU_CLOCKS_MSB : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_JUMP_TABLE_RESTORE__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_LB_ALWAYS_ACTIVE_CU_MASK__CI__VI {
	struct {
                unsigned int           ALWAYS_ACTIVE_CU_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_LB_ALWAYS_ACTIVE_CU_MASK__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_LB_CNTL {
	struct {
                unsigned int             LOAD_BALANCE_ENABLE : 1;
                unsigned int                  LB_CNT_CP_BUSY : 1;
                unsigned int              LB_CNT_SPIM_ACTIVE : 1;
                unsigned int                  LB_CNT_REG_INC : 1;
                unsigned int   CU_MASK_USED_OFF_HYST__CI__VI : 8;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_LB_CNTR_INIT {
	struct {
		unsigned int                    LB_CNTR_INIT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_LB_CNTR_MAX {
	struct {
		unsigned int                     LB_CNTR_MAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_LB_INIT_CU_MASK__CI__VI {
	struct {
                unsigned int                    INIT_CU_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_LB_INIT_CU_MASK__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_LB_PARAMS {
	struct {
		unsigned int                   SKIP_L2_CHECK : 1;
		unsigned int                    FIFO_SAMPLES : 7;
		unsigned int                 PG_IDLE_SAMPLES : 8;
		unsigned int         PG_IDLE_SAMPLE_INTERVAL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_LOAD_BALANCE_CNTR {
	struct {
		unsigned int           RLC_LOAD_BALANCE_CNTR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_MAX_PG_CU {
	struct {
		unsigned int               MAX_POWERED_UP_CU : 8;
		unsigned int                           SPARE : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_MC_CNTL {
	struct {
		unsigned int                      WRREQ_SWAP : 2;
		unsigned int                      WRREQ_TRAN : 1;
		unsigned int                      WRREQ_PRIV : 1;
		unsigned int                     WRNFO_STALL : 1;
		unsigned int                       WRNFO_URG : 4;
		unsigned int                  WRREQ_DW_IMASK : 4;
		unsigned int                      RESERVED_B : 7;
		unsigned int                       RDNFO_URG : 4;
		unsigned int                      RDREQ_SWAP : 2;
		unsigned int                      RDREQ_TRAN : 1;
		unsigned int                      RDREQ_PRIV : 1;
		unsigned int                     RDNFO_STALL : 1;
		unsigned int                        RESERVED : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_MEM_SLP_CNTL {
	struct {
                unsigned int                   RLC_MEM_LS_EN : 1;
                unsigned int                   RLC_MEM_DS_EN : 1;
                unsigned int                    RESERVED__VI : 5;
                unsigned int     RLC_LS_DS_BUSY_OVERRIDE__VI : 1;
                unsigned int             RLC_MEM_LS_ON_DELAY : 8;
                unsigned int            RLC_MEM_LS_OFF_DELAY : 8;
                unsigned int                       RESERVED1 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PERFCOUNTER0_SELECT {
	struct {
		unsigned int              PERFCOUNTER_SELECT : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PERFCOUNTER1_SELECT {
	struct {
		unsigned int              PERFCOUNTER_SELECT : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PERFMON_CNTL {
	struct {
		unsigned int                   PERFMON_STATE : 3;
		unsigned int                                 : 7;
		unsigned int           PERFMON_SAMPLE_ENABLE : 1;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PG_ALWAYS_ON_CU_MASK__CI__VI {
	struct {
                unsigned int                     AON_CU_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PG_ALWAYS_ON_CU_MASK__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PG_CNTL {
	struct {
                unsigned int         GFX_POWER_GATING_ENABLE : 1;
                unsigned int            GFX_POWER_GATING_SRC : 1;
                unsigned int            DYN_PER_CU_PG_ENABLE : 1;
                unsigned int         STATIC_PER_CU_PG_ENABLE : 1;
                unsigned int      GFX_PIPELINE_PG_ENABLE__VI : 1;
                unsigned int                    RESERVED__VI : 9;
                unsigned int                 PG_OVERRIDE__VI : 1;
                unsigned int               CP_PG_DISABLE__VI : 1;
                unsigned int   CHUB_HANDSHAKE_ENABLE__CI__VI : 1;
                unsigned int SMU_CLK_SLOWDOWN_ON_PU_ENABLE__CI__VI : 1;
                unsigned int SMU_CLK_SLOWDOWN_ON_PD_ENABLE__CI__VI : 1;
                unsigned int        SMU_HANDSHAKE_ENABLE__VI : 1;
                unsigned int                   RESERVED1__VI : 4;
                unsigned int             PG_ERROR_STATUS__CI : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PG_DELAY_2__CI__VI {
	struct {
                unsigned int            SERDES_TIMEOUT_VALUE : 8;
                unsigned int                SERDES_CMD_DELAY : 8;
                unsigned int             PERCU_TIMEOUT_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PG_DELAY__CI__VI {
	struct {
                unsigned int                  POWER_UP_DELAY : 8;
                unsigned int                POWER_DOWN_DELAY : 8;
                unsigned int             CMD_PROPAGATE_DELAY : 8;
                unsigned int                 MEM_SLEEP_DELAY : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SAFE_MODE__CI {
	struct {
		unsigned int                             REQ : 1;
		unsigned int                         MESSAGE : 4;
		unsigned int                        RESERVED : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SAFE_MODE__VI {
	struct {
		unsigned int                             CMD : 1;
		unsigned int                         MESSAGE : 4;
		unsigned int                       RESERVED1 : 3;
		unsigned int                        RESPONSE : 4;
		unsigned int                        RESERVED : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SAVE_AND_RESTORE_BASE {
	struct {
		unsigned int                            BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_CU_MASTER_BUSY__CI__VI {
	struct {
                unsigned int                       BUSY_BUSY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_NONCU_MASTER_BUSY__CI {
	struct {
		unsigned int                  SE_MASTER_BUSY : 16;
		unsigned int                  GC_MASTER_BUSY : 1;
		unsigned int                 TC0_MASTER_BUSY : 1;
		unsigned int                 TC1_MASTER_BUSY : 1;
		unsigned int              SPARE0_MASTER_BUSY : 1;
		unsigned int              SPARE1_MASTER_BUSY : 1;
		unsigned int              SPARE2_MASTER_BUSY : 1;
		unsigned int              SPARE3_MASTER_BUSY : 1;
		unsigned int                        RESERVED : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_NONCU_MASTER_BUSY__VI {
	struct {
		unsigned int                  SE_MASTER_BUSY : 16;
		unsigned int                  GC_MASTER_BUSY : 1;
		unsigned int              GC_GFX_MASTER_BUSY : 1;
		unsigned int                 TC0_MASTER_BUSY : 1;
		unsigned int                 TC1_MASTER_BUSY : 1;
		unsigned int              SPARE0_MASTER_BUSY : 1;
		unsigned int              SPARE1_MASTER_BUSY : 1;
		unsigned int              SPARE2_MASTER_BUSY : 1;
		unsigned int              SPARE3_MASTER_BUSY : 1;
		unsigned int                        RESERVED : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_RD_DATA_0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_RD_DATA_1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_RD_DATA_2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_RD_MASTER_INDEX__CI {
	struct {
		unsigned int                           CU_ID : 4;
		unsigned int                           SH_ID : 2;
		unsigned int                           SE_ID : 3;
		unsigned int                     SE_NONCU_ID : 1;
		unsigned int                        SE_NONCU : 1;
		unsigned int                          NON_SE : 3;
		unsigned int                     DATA_REG_ID : 2;
		unsigned int                           SPARE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_RD_MASTER_INDEX__VI {
	struct {
		unsigned int                           CU_ID : 4;
		unsigned int                           SH_ID : 2;
		unsigned int                           SE_ID : 3;
		unsigned int                     SE_NONCU_ID : 1;
		unsigned int                        SE_NONCU : 1;
		unsigned int                          NON_SE : 4;
		unsigned int                     DATA_REG_ID : 2;
		unsigned int                           SPARE : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_RD_MASTER_INDEX__SI {
	struct {
		unsigned int                                 : 6;
		unsigned int                                 : 6;
		unsigned int                                 : 2;
		unsigned int                           SPARE : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_WR_CTRL__CI {
	struct {
		unsigned int                        BPM_ADDR : 8;
		unsigned int                      POWER_DOWN : 1;
		unsigned int                        POWER_UP : 1;
		unsigned int                       P1_SELECT : 1;
		unsigned int                       P2_SELECT : 1;
		unsigned int                   WRITE_COMMAND : 1;
		unsigned int                    READ_COMMAND : 1;
		unsigned int                      RESERVED_1 : 2;
		unsigned int                     CGLS_ENABLE : 1;
		unsigned int                    CGLS_DISABLE : 1;
		unsigned int                         CGLS_ON : 1;
		unsigned int                        CGLS_OFF : 1;
		unsigned int                 CGCG_OVERRIDE_0 : 1;
		unsigned int                 CGCG_OVERRIDE_1 : 1;
		unsigned int                 MGCG_OVERRIDE_0 : 1;
		unsigned int                 MGCG_OVERRIDE_1 : 1;
		unsigned int                      RESERVED_2 : 4;
		unsigned int                        REG_ADDR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_WR_CTRL__VI {
	struct {
		unsigned int                        BPM_ADDR : 8;
		unsigned int                      POWER_DOWN : 1;
		unsigned int                        POWER_UP : 1;
		unsigned int                       P1_SELECT : 1;
		unsigned int                       P2_SELECT : 1;
		unsigned int                   WRITE_COMMAND : 1;
		unsigned int                    READ_COMMAND : 1;
		unsigned int                    RDDATA_RESET : 1;
		unsigned int                    SHORT_FORMAT : 1;
		unsigned int                        BPM_DATA : 10;
		unsigned int                   SRBM_OVERRIDE : 1;
		unsigned int                   RSVD_BPM_ADDR : 1;
		unsigned int                        REG_ADDR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_WR_CTRL__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_WR_CU_MASTER_MASK__CI__VI {
	struct {
                unsigned int                     MASTER_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_WR_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_WR_NONCU_MASTER_MASK__CI {
	struct {
		unsigned int                  SE_MASTER_MASK : 16;
		unsigned int                  GC_MASTER_MASK : 1;
		unsigned int                 TC0_MASTER_MASK : 1;
		unsigned int                 TC1_MASTER_MASK : 1;
		unsigned int              SPARE0_MASTER_MASK : 1;
		unsigned int              SPARE1_MASTER_MASK : 1;
		unsigned int              SPARE2_MASTER_MASK : 1;
		unsigned int              SPARE3_MASTER_MASK : 1;
		unsigned int                        RESERVED : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SERDES_WR_NONCU_MASTER_MASK__VI {
	struct {
		unsigned int                  SE_MASTER_MASK : 16;
		unsigned int                  GC_MASTER_MASK : 1;
		unsigned int              GC_GFX_MASTER_MASK : 1;
		unsigned int                 TC0_MASTER_MASK : 1;
		unsigned int                 TC1_MASTER_MASK : 1;
		unsigned int              SPARE0_MASTER_MASK : 1;
		unsigned int              SPARE1_MASTER_MASK : 1;
		unsigned int              SPARE2_MASTER_MASK : 1;
		unsigned int              SPARE3_MASTER_MASK : 1;
		unsigned int                        RESERVED : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SMU_GRBM_REG_SAVE_CTRL {
	struct {
		unsigned int             START_GRBM_REG_SAVE : 1;
		unsigned int                           SPARE : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SMU_PG_CTRL {
	struct {
		unsigned int                        START_PG : 1;
		unsigned int                           SPARE : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SMU_PG_WAKE_UP_CTRL {
	struct {
		unsigned int                START_PG_WAKE_UP : 1;
		unsigned int                           SPARE : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SOFT_RESET_GPU {
	struct {
		unsigned int                  SOFT_RESET_GPU : 1;
		unsigned int                        RESERVED : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_CB_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_DB_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_DEBUG_SELECT__CI__VI {
	struct {
                unsigned int                          SELECT : 8;
                unsigned int                                 : 7;
                unsigned int              RLC_SPM_DEBUG_MODE : 1;
                unsigned int              RLC_SPM_NUM_SAMPLE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_DEBUG__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_GLOBAL_MUXSEL_ADDR__CI__VI {
	struct {
                unsigned int                PERFMON_SEL_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_GLOBAL_MUXSEL_DATA__CI__VI {
	struct {
                unsigned int                PERFMON_SEL_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_IA_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_INT_CNTL__CI__VI {
	struct {
                unsigned int                RLC_SPM_INT_CNTL : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_INT_STATUS__CI__VI {
	struct {
                unsigned int              RLC_SPM_INT_STATUS : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_PA_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_PERFMON_CNTL__CI__VI {
	struct {
                unsigned int                       RESERVED1 : 12;
                unsigned int               PERFMON_RING_MODE : 2;
                unsigned int                                 : 2;
                unsigned int         PERFMON_SAMPLE_INTERVAL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_PERFMON_RING_BASE_HI__CI__VI {
	struct {
                unsigned int                    RING_BASE_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_PERFMON_RING_BASE_LO__CI__VI {
	struct {
                unsigned int                    RING_BASE_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_PERFMON_RING_SIZE__CI__VI {
	struct {
                unsigned int                  RING_BASE_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_PERFMON_SEGMENT_SIZE__CI__VI {
	struct {
                unsigned int            PERFMON_SEGMENT_SIZE : 8;
                unsigned int                                 : 3;
                unsigned int                 GLOBAL_NUM_LINE : 5;
                unsigned int                    SE0_NUM_LINE : 5;
                unsigned int                    SE1_NUM_LINE : 5;
                unsigned int                    SE2_NUM_LINE : 5;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_RING_RDPTR__CI__VI {
	struct {
                unsigned int              PERFMON_RING_RDPTR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_SC_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_SEGMENT_THRESHOLD__CI__VI {
	struct {
                unsigned int           NUM_SEGMENT_THRESHOLD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_SE_MUXSEL_ADDR__CI__VI {
	struct {
                unsigned int                PERFMON_SEL_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_SE_MUXSEL_DATA__CI__VI {
	struct {
                unsigned int                PERFMON_SEL_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_SX_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_TA_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__CI {
	struct {
		unsigned int            PERFMON_SAMPLE_DELAY : 8;
		unsigned int                        RESERVED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_TD_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__CI__VI {
	struct {
                unsigned int            PERFMON_SAMPLE_DELAY : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_VMID__CI__VI {
	struct {
                unsigned int                    RLC_SPM_VMID : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_STATIC_PG_STATUS__CI__VI {
	struct {
                unsigned int               PG_STATUS_CU_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_STAT__CI__VI {
	struct {
                unsigned int                        RLC_BUSY : 1;
                unsigned int                    RLC_GPM_BUSY : 1;
                unsigned int                    RLC_SPM_BUSY : 1;
                unsigned int                RLC_SRM_BUSY__VI : 1;
                unsigned int                    RESERVED__VI : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_STAT__SI {
	struct {
		unsigned int                        RLC_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                        RESERVED : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_THREAD1_DELAY {
	struct {
		unsigned int                   CU_IDEL_DELAY : 8;
		unsigned int           LBPW_INNER_LOOP_DELAY : 8;
		unsigned int           LBPW_OUTER_LOOP_DELAY : 8;
		unsigned int                           SPARE : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_UCODE_CNTL {
	struct {
		unsigned int                 RLC_UCODE_FLAGS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_VMID__SI {
	struct {
		unsigned int                                 : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_BASE_ADDR {
	struct {
		unsigned int                       BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_CNTL {
	struct {
		unsigned int                                 : 1;
		unsigned int                   SCK_OVERWRITE : 1;
		unsigned int                 CLOCK_GATING_EN : 1;
		unsigned int                                 : 5;
		unsigned int    CSB_ACTIVE_TO_SCK_SETUP_TIME : 8;
		unsigned int     CSB_ACTIVE_TO_SCK_HOLD_TIME : 8;
		unsigned int             SCK_PRESCALE_REFCLK : 4;
		unsigned int        SCK_PRESCALE_CRYSTAL_CLK : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_DATA {
	struct {
		unsigned int                        ROM_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_INDEX {
	struct {
		unsigned int                       ROM_INDEX : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SMC_IND_DATA__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SMC_IND_INDEX__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_START {
	struct {
		unsigned int                       ROM_START : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_STATUS {
	struct {
		unsigned int                        ROM_BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_CNTL {
	struct {
		unsigned int                       DATA_SIZE : 16;
		unsigned int                    COMMAND_SIZE : 2;
		unsigned int       ROM_SW_RETURN_DATA_ENABLE : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_COMMAND {
	struct {
		unsigned int              ROM_SW_INSTRUCTION : 8;
		unsigned int                  ROM_SW_ADDRESS : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_1 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_10 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_11 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_12 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_13 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_14 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_15 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_16 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_17 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_18 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_19 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_2 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_20 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_21 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_22 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_23 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_24 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_25 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_26 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_27 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_28 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_29 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_3 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_30 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_31 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_32 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_33 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_34 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_35 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_36 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_37 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_38 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_39 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_4 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_40 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_41 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_42 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_43 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_44 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_45 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_46 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_47 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_48 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_49 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_5 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_50 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_51 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_52 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_53 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_54 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_55 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_56 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_57 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_58 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_59 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_6 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_60 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_61 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_62 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_63 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_64 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_7 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_8 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_DATA_9 {
	struct {
		unsigned int                     ROM_SW_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ROM_SW_STATUS {
	struct {
		unsigned int                     ROM_SW_DONE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLK_CGTT_BLK_CTRL_REG__SI__VI {
	struct {
                unsigned int              SCLK_TURN_ON_DELAY : 4;
                unsigned int             SCLK_TURN_OFF_DELAY : 8;
                unsigned int          CGTT_SCLK_OVERRIDE__VI : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLK_DEEP_SLEEP_CNTL2__CI {
	struct {
		unsigned int                   RLC_BUSY_MASK : 1;
		unsigned int                   HDP_BUSY_MASK : 1;
		unsigned int                   ROM_BUSY_MASK : 1;
		unsigned int                IH_SEM_BUSY_MASK : 1;
		unsigned int                  PDMA_BUSY_MASK : 1;
		unsigned int                                 : 1;
		unsigned int                  IDCT_BUSY_MASK : 1;
		unsigned int                  SDMA_BUSY_MASK : 1;
		unsigned int                 DC_AZ_BUSY_MASK : 1;
		unsigned int ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK : 1;
		unsigned int        UVD_CG_MC_STAT_BUSY_MASK : 1;
		unsigned int        VCE_CG_MC_STAT_BUSY_MASK : 1;
		unsigned int        SAM_CG_MC_STAT_BUSY_MASK : 1;
		unsigned int         SAM_CG_STATUS_BUSY_MASK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                  SHALLOW_DIV_ID : 3;
		unsigned int                   INOUT_CUSHION : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLK_DEEP_SLEEP_CNTL2__VI {
	struct {
		unsigned int                   RLC_BUSY_MASK : 1;
		unsigned int                   HDP_BUSY_MASK : 1;
		unsigned int                   ROM_BUSY_MASK : 1;
		unsigned int                IH_SEM_BUSY_MASK : 1;
		unsigned int                  PDMA_BUSY_MASK : 1;
		unsigned int                                 : 1;
		unsigned int                  IDCT_BUSY_MASK : 1;
		unsigned int                  SDMA_BUSY_MASK : 1;
		unsigned int                 DC_AZ_BUSY_MASK : 1;
		unsigned int ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK : 1;
		unsigned int        UVD_CG_MC_STAT_BUSY_MASK : 1;
		unsigned int        VCE_CG_MC_STAT_BUSY_MASK : 1;
		unsigned int        SAM_CG_MC_STAT_BUSY_MASK : 1;
		unsigned int         SAM_CG_STATUS_BUSY_MASK : 1;
		unsigned int         RLC_SMU_GFXCLK_OFF_MASK : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 1;
		unsigned int                  SHALLOW_DIV_ID : 3;
		unsigned int                   INOUT_CUSHION : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLK_DEEP_SLEEP_CNTL3__CI__VI {
	struct {
                unsigned int            GRBM_0_SMU_BUSY_MASK : 1;
                unsigned int            GRBM_1_SMU_BUSY_MASK : 1;
                unsigned int            GRBM_2_SMU_BUSY_MASK : 1;
                unsigned int            GRBM_3_SMU_BUSY_MASK : 1;
                unsigned int            GRBM_4_SMU_BUSY_MASK : 1;
                unsigned int            GRBM_5_SMU_BUSY_MASK : 1;
                unsigned int            GRBM_6_SMU_BUSY_MASK : 1;
                unsigned int            GRBM_7_SMU_BUSY_MASK : 1;
                unsigned int            GRBM_8_SMU_BUSY_MASK : 1;
                unsigned int            GRBM_9_SMU_BUSY_MASK : 1;
                unsigned int           GRBM_10_SMU_BUSY_MASK : 1;
                unsigned int           GRBM_11_SMU_BUSY_MASK : 1;
                unsigned int           GRBM_12_SMU_BUSY_MASK : 1;
                unsigned int           GRBM_13_SMU_BUSY_MASK : 1;
                unsigned int           GRBM_14_SMU_BUSY_MASK : 1;
                unsigned int           GRBM_15_SMU_BUSY_MASK : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLK_DEEP_SLEEP_CNTL__CI__VI {
	struct {
                unsigned int                          DIV_ID : 3;
                unsigned int                        RAMP_DIS : 1;
                unsigned int                      HYSTERESIS : 12;
                unsigned int               SCLK_RUNNING_MASK : 1;
                unsigned int               SELF_REFRESH_MASK : 1;
                unsigned int             ALLOW_NBPSTATE_MASK : 1;
                unsigned int                   BIF_BUSY_MASK : 1;
                unsigned int                   UVD_BUSY_MASK : 1;
                unsigned int               MC0SRBM_BUSY_MASK : 1;
                unsigned int               MC1SRBM_BUSY_MASK : 1;
                unsigned int                   MC_ALLOW_MASK : 1;
                unsigned int                   SMU_BUSY_MASK : 1;
                unsigned int           SELF_REFRESH_NLC_MASK : 1;
                unsigned int          FAST_EXIT_REQ_NBPSTATE : 1;
                unsigned int           DEEP_SLEEP_ENTRY_MODE : 1;
                unsigned int               MBUS2_ACTIVE_MASK : 1;
                unsigned int                   VCE_BUSY_MASK : 1;
                unsigned int                    AZ_BUSY_MASK : 1;
                unsigned int                       ENABLE_DS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLK_DEEP_SLEEP_MISC_CNTL__CI__VI {
	struct {
                unsigned int                   DPM_DS_DIV_ID : 3;
                unsigned int                   DPM_SS_DIV_ID : 3;
                unsigned int                                 : 10;
                unsigned int                      OCP_ENABLE : 1;
                unsigned int                   OCP_DS_DIV_ID : 3;
                unsigned int                   OCP_SS_DIV_ID : 3;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLK_MIN_DIV__CI__VI {
	struct {
                unsigned int                           FRACV : 12;
                unsigned int                            INTV : 7;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLK_PWRMGT_CNTL__CI__VI {
	struct {
                unsigned int                 SCLK_PWRMGT_OFF : 1;
                unsigned int                     SCLK_LOW_D1 : 1;
                unsigned int                 DYN_PWR_DOWN_EN : 1;
                unsigned int                                 : 1;
                unsigned int                  RESET_BUSY_CNT : 1;
                unsigned int                  RESET_SCLK_CNT : 1;
                unsigned int                                 : 1;
                unsigned int              DYN_GFX_CLK_OFF_EN : 1;
                unsigned int                GFX_CLK_FORCE_ON : 1;
                unsigned int             GFX_CLK_REQUEST_OFF : 1;
                unsigned int               GFX_CLK_FORCE_OFF : 1;
                unsigned int             GFX_CLK_OFF_ACPI_D1 : 1;
                unsigned int             GFX_CLK_OFF_ACPI_D2 : 1;
                unsigned int             GFX_CLK_OFF_ACPI_D3 : 1;
                unsigned int              DYN_LIGHT_SLEEP_EN : 1;
                unsigned int            AUTO_SCLK_PULSE_SKIP : 1;
                unsigned int             LIGHT_SLEEP_COUNTER : 5;
                unsigned int                   DYNAMIC_PM_EN : 1;
                unsigned int           DPM_DYN_PWR_DOWN_CNTL : 1;
                unsigned int             DPM_DYN_PWR_DOWN_EN : 1;
                unsigned int                                 : 1;
                unsigned int               VOLTAGE_UPDATE_EN : 1;
                unsigned int                                 : 2;
                unsigned int             FORCE_PM0_INTERRUPT : 1;
                unsigned int             FORCE_PM1_INTERRUPT : 1;
                unsigned int           GFX_VOLTAGE_CHANGE_EN : 1;
                unsigned int         GFX_VOLTAGE_CHANGE_MODE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLK_PWRMGT_CNTL__SI {
	struct {
		unsigned int                 SCLK_PWRMGT_OFF : 1;
		unsigned int                     SCLK_LOW_D1 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int              DYN_GFX_CLK_OFF_EN : 1;
		unsigned int                GFX_CLK_FORCE_ON : 1;
		unsigned int             GFX_CLK_REQUEST_OFF : 1;
		unsigned int               GFX_CLK_FORCE_OFF : 1;
		unsigned int             GFX_CLK_OFF_ACPI_D1 : 1;
		unsigned int             GFX_CLK_OFF_ACPI_D2 : 1;
		unsigned int             GFX_CLK_OFF_ACPI_D3 : 1;
		unsigned int              DYN_LIGHT_SLEEP_EN : 1;
		unsigned int                                 : 1;
		unsigned int             LIGHT_SLEEP_COUNTER : 5;
		unsigned int                                 : 7;
		unsigned int             FORCE_PM0_INTERRUPT : 1;
		unsigned int             FORCE_PM1_INTERRUPT : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_ALU_CONTROL__SI__VI {
	struct {
                unsigned int                 SCL_ALU_DISABLE : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_AUTOMATIC_MODE_CONTROL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_AUTOMATIC_MODE_CONTROL__VI {
	struct {
		unsigned int        SCL_V_CALC_AUTO_RATIO_EN : 1;
		unsigned int                                 : 15;
		unsigned int        SCL_H_CALC_AUTO_RATIO_EN : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_BYPASS_CONTROL__SI__VI {
	struct {
                unsigned int                 SCL_BYPASS_MODE : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_COEF_RAM_CONFLICT_STATUS__SI__VI {
	struct {
                unsigned int          SCL_HOST_CONFLICT_FLAG : 1;
                unsigned int                                 : 7;
                unsigned int           SCL_HOST_CONFLICT_ACK : 1;
                unsigned int                                 : 3;
                unsigned int          SCL_HOST_CONFLICT_MASK : 1;
                unsigned int                                 : 3;
                unsigned int    SCL_HOST_CONFLICT_INT_STATUS : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_COEF_RAM_SELECT__SI__VI {
	struct {
                unsigned int          SCL_C_RAM_TAP_PAIR_IDX : 4;
                unsigned int                                 : 4;
                unsigned int                 SCL_C_RAM_PHASE : 4;
                unsigned int                                 : 4;
                unsigned int           SCL_C_RAM_FILTER_TYPE : 3;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_COEF_RAM_TAP_DATA__SI__VI {
	struct {
                unsigned int         SCL_C_RAM_EVEN_TAP_COEF : 14;
                unsigned int                                 : 1;
                unsigned int      SCL_C_RAM_EVEN_TAP_COEF_EN : 1;
                unsigned int          SCL_C_RAM_ODD_TAP_COEF : 14;
                unsigned int                                 : 1;
                unsigned int       SCL_C_RAM_ODD_TAP_COEF_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_CONTROL__SI {
	struct {
		unsigned int                                 : 16;
		unsigned int                                 : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_CONTROL__VI {
	struct {
		unsigned int               SCL_BOUNDARY_MODE : 1;
		unsigned int                                 : 3;
		unsigned int              SCL_EARLY_EOL_MODE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_DEBUG__SI__VI {
	struct {
                unsigned int                       SCL_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_F_SHARP_CONTROL__SI__VI {
	struct {
                unsigned int       SCL_HF_SHARP_SCALE_FACTOR : 3;
                unsigned int                                 : 1;
                unsigned int                 SCL_HF_SHARP_EN : 1;
                unsigned int                                 : 3;
                unsigned int       SCL_VF_SHARP_SCALE_FACTOR : 3;
                unsigned int                                 : 1;
                unsigned int                 SCL_VF_SHARP_EN : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_HORZ_FILTER_CONTROL__SI {
	struct {
		unsigned int       SCL_H_FILTER_PICK_NEAREST : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_HORZ_FILTER_CONTROL__VI {
	struct {
		unsigned int       SCL_H_FILTER_PICK_NEAREST : 1;
		unsigned int                                 : 7;
		unsigned int     SCL_H_2TAP_HARDCODE_COEF_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_HORZ_FILTER_SCALE_RATIO__SI__VI {
	struct {
                unsigned int               SCL_H_SCALE_RATIO : 26;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_MANUAL_REPLICATE_CONTROL__SI__VI {
	struct {
                unsigned int   SCL_V_MANUAL_REPLICATE_FACTOR : 4;
                unsigned int                                 : 4;
                unsigned int   SCL_H_MANUAL_REPLICATE_FACTOR : 4;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_MODE_CHANGE_DET1__SI__VI {
	struct {
                unsigned int                 SCL_MODE_CHANGE : 1;
                unsigned int                                 : 3;
                unsigned int             SCL_MODE_CHANGE_ACK : 1;
                unsigned int                                 : 2;
                unsigned int           SCL_ALU_H_SCALE_RATIO : 21;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_MODE_CHANGE_DET2__SI__VI {
	struct {
                unsigned int           SCL_ALU_V_SCALE_RATIO : 21;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_MODE_CHANGE_DET3__SI__VI {
	struct {
                unsigned int           SCL_ALU_SOURCE_HEIGHT : 14;
                unsigned int                                 : 2;
                unsigned int            SCL_ALU_SOURCE_WIDTH : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_MODE_CHANGE_MASK__SI__VI {
	struct {
                unsigned int            SCL_MODE_CHANGE_MASK : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_TAP_CONTROL__SI {
	struct {
		unsigned int                                 : 3;
		unsigned int                                 : 5;
		unsigned int                                 : 4;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_TAP_CONTROL__VI {
	struct {
		unsigned int               SCL_V_NUM_OF_TAPS : 3;
		unsigned int                                 : 5;
		unsigned int               SCL_H_NUM_OF_TAPS : 4;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int             SCL_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int            SCL_TEST_DEBUG_INDEX : 8;
                unsigned int         SCL_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_UPDATE__SI__VI {
	struct {
                unsigned int              SCL_UPDATE_PENDING : 1;
                unsigned int                                 : 7;
                unsigned int                SCL_UPDATE_TAKEN : 1;
                unsigned int                                 : 7;
                unsigned int                 SCL_UPDATE_LOCK : 1;
                unsigned int                                 : 7;
                unsigned int    SCL_COEF_UPDATE_COMPLETE__VI : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_VERT_FILTER_CONTROL__SI {
	struct {
		unsigned int       SCL_V_FILTER_PICK_NEAREST : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 2;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_VERT_FILTER_CONTROL__VI {
	struct {
		unsigned int       SCL_V_FILTER_PICK_NEAREST : 1;
		unsigned int                                 : 7;
		unsigned int     SCL_V_2TAP_HARDCODE_COEF_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_VERT_FILTER_INIT_BOT__SI {
	struct {
		unsigned int             SCL_V_INIT_FRAC_BOT : 16;
		unsigned int              SCL_V_INIT_INT_BOT : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_VERT_FILTER_INIT_BOT__VI {
	struct {
		unsigned int             SCL_V_INIT_FRAC_BOT : 24;
		unsigned int              SCL_V_INIT_INT_BOT : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_VERT_FILTER_INIT__SI {
	struct {
		unsigned int                 SCL_V_INIT_FRAC : 16;
		unsigned int                  SCL_V_INIT_INT : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_VERT_FILTER_INIT__VI {
	struct {
		unsigned int                 SCL_V_INIT_FRAC : 24;
		unsigned int                  SCL_V_INIT_INT : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_VERT_FILTER_SCALE_RATIO__SI__VI {
	struct {
                unsigned int               SCL_V_SCALE_RATIO : 26;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_ADDR__CI__VI {
	struct {
                unsigned int                   OBSOLETE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_ADDR__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_REG0 {
	struct {
		unsigned int                    SCRATCH_REG0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_REG1 {
	struct {
		unsigned int                    SCRATCH_REG1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_REG2 {
	struct {
		unsigned int                    SCRATCH_REG2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_REG3 {
	struct {
		unsigned int                    SCRATCH_REG3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_REG4 {
	struct {
		unsigned int                    SCRATCH_REG4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_REG5 {
	struct {
		unsigned int                    SCRATCH_REG5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_REG6 {
	struct {
		unsigned int                    SCRATCH_REG6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_REG7 {
	struct {
		unsigned int                    SCRATCH_REG7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_UMSK__CI__VI {
	struct {
                unsigned int                   OBSOLETE_UMSK : 8;
                unsigned int                                 : 8;
                unsigned int                   OBSOLETE_SWAP : 2;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCRATCH_UMSK__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 8;
		unsigned int                                 : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_CHICKEN_BITS__CI__VI {
	struct {
                unsigned int          COPY_EFFICIENCY_ENABLE : 1;
                unsigned int  STALL_ON_TRANS_FULL_ENABLE__VI : 1;
                unsigned int STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__VI : 1;
                unsigned int                                 : 13;
                unsigned int             COPY_OVERLAP_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int              SRBM_POLL_RETRYING : 1;
                unsigned int                                 : 2;
                unsigned int                CG_STATUS_OUTPUT : 1;
                unsigned int                                 : 2;
                unsigned int          CE_AFIFO_WATERMARK__VI : 2;
                unsigned int          CE_DFIFO_WATERMARK__VI : 2;
                unsigned int          CE_LFIFO_WATERMARK__VI : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_CLK_CTRL__CI__VI {
	struct {
                unsigned int                        ON_DELAY : 4;
                unsigned int                  OFF_HYSTERESIS : 8;
                unsigned int                                 : 12;
                unsigned int                  SOFT_OVERRIDE7 : 1;
                unsigned int                  SOFT_OVERRIDE6 : 1;
                unsigned int                  SOFT_OVERRIDE5 : 1;
                unsigned int                  SOFT_OVERRIDE4 : 1;
                unsigned int                  SOFT_OVERRIDE3 : 1;
                unsigned int                  SOFT_OVERRIDE2 : 1;
                unsigned int                  SOFT_OVERRIDE1 : 1;
                unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_CNTL__CI {
	struct {
		unsigned int                     TRAP_ENABLE : 1;
		unsigned int       SEM_INCOMPLETE_INT_ENABLE : 1;
		unsigned int             SEM_WAIT_INT_ENABLE : 1;
		unsigned int                DATA_SWAP_ENABLE : 1;
		unsigned int               FENCE_SWAP_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                 MC_WRREQ_CREDIT : 6;
		unsigned int                                 : 1;
		unsigned int               AUTO_CTXSW_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int                 MC_RDREQ_CREDIT : 6;
		unsigned int             CTXEMPTY_INT_ENABLE : 1;
		unsigned int               FROZEN_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_CNTL__VI {
	struct {
		unsigned int                     TRAP_ENABLE : 1;
		unsigned int                   ATC_L1_ENABLE : 1;
		unsigned int             SEM_WAIT_INT_ENABLE : 1;
		unsigned int                DATA_SWAP_ENABLE : 1;
		unsigned int               FENCE_SWAP_ENABLE : 1;
		unsigned int           MIDCMD_PREEMPT_ENABLE : 1;
		unsigned int                                 : 5;
		unsigned int                 MC_WRREQ_CREDIT : 6;
		unsigned int       MIDCMD_WORLDSWITCH_ENABLE : 1;
		unsigned int               AUTO_CTXSW_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                 MC_RDREQ_CREDIT : 6;
		unsigned int             CTXEMPTY_INT_ENABLE : 1;
		unsigned int               FROZEN_INT_ENABLE : 1;
		unsigned int           IB_PREEMPT_INT_ENABLE : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_F32_CNTL__CI__VI {
	struct {
                unsigned int                            HALT : 1;
                unsigned int                            STEP : 1;
                unsigned int             DBG_SELECT_BITS__VI : 6;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_FREEZE__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 3;
                unsigned int                          FREEZE : 1;
                unsigned int                          FROZEN : 1;
                unsigned int                  F32_FREEZE__VI : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_APE1_CNTL__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                           LIMIT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_CONTEXT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 16;
                unsigned int                      RESUME_CTX : 1;
                unsigned int                                 : 7;
                unsigned int                     SESSION_SEL : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_CONTEXT_STATUS__CI__VI {
	struct {
                unsigned int                        SELECTED : 1;
                unsigned int                                 : 1;
                unsigned int                            IDLE : 1;
                unsigned int                         EXPIRED : 1;
                unsigned int                       EXCEPTION : 3;
                unsigned int                      CTXSW_ABLE : 1;
                unsigned int                     CTXSW_READY : 1;
                unsigned int                   PREEMPTED__VI : 1;
                unsigned int             PREEMPT_DISABLE__VI : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_IB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_IB_BASE_LO__CI__VI {
	struct {
                unsigned int                                 : 5;
                unsigned int                            ADDR : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_IB_CNTL__CI__VI {
	struct {
                unsigned int                       IB_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                  IB_SWAP_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                SWITCH_INSIDE_IB : 1;
                unsigned int                                 : 7;
                unsigned int                        CMD_VMID : 4;
                unsigned int                                 : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_IB_OFFSET__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_IB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_IB_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_RB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_RB_BASE__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_RB_CNTL__CI__VI {
	struct {
                unsigned int                       RB_ENABLE : 1;
                unsigned int                         RB_SIZE : 5;
                unsigned int                                 : 3;
                unsigned int                  RB_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int           RPTR_WRITEBACK_ENABLE : 1;
                unsigned int      RPTR_WRITEBACK_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int            RPTR_WRITEBACK_TIMER : 5;
                unsigned int                                 : 2;
                unsigned int                         RB_PRIV : 1;
                unsigned int                         RB_VMID : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_RB_RPTR_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_RB_RPTR_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_RB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_RB_WPTR_POLL_CNTL__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                     SWAP_ENABLE : 1;
                unsigned int             F32_POLL_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int                       FREQUENCY : 12;
                unsigned int                 IDLE_POLL_COUNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_RB_WPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_SKIP_CNTL__CI__VI {
	struct {
                unsigned int                      SKIP_COUNT : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_VIRTUAL_ADDR__CI__VI {
	struct {
                unsigned int                             ATC : 1;
                unsigned int                       INVAL__VI : 1;
                unsigned int                                 : 2;
                unsigned int                           PTR32 : 1;
                unsigned int                                 : 3;
                unsigned int                     SHARED_BASE : 3;
                unsigned int                                 : 19;
                unsigned int                         VM_HOLE : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_HASH__CI__VI {
	struct {
                unsigned int                    CHANNEL_BITS : 3;
                unsigned int                                 : 1;
                unsigned int                       BANK_BITS : 3;
                unsigned int                                 : 1;
                unsigned int               CHANNEL_XOR_COUNT : 3;
                unsigned int                                 : 1;
                unsigned int                  BANK_XOR_COUNT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_IB_OFFSET_FETCH__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_PERFCOUNTER0_RESULT__CI__VI {
	struct {
                unsigned int                      PERF_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_PERFCOUNTER1_RESULT__CI__VI {
	struct {
                unsigned int                      PERF_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_PERFMON_CNTL__CI__VI {
	struct {
                unsigned int                    PERF_ENABLE0 : 1;
                unsigned int                     PERF_CLEAR0 : 1;
                unsigned int                       PERF_SEL0 : 6;
                unsigned int                    PERF_ENABLE1 : 1;
                unsigned int                     PERF_CLEAR1 : 1;
                unsigned int                       PERF_SEL1 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_PHASE0_QUANTUM__CI__VI {
	struct {
                unsigned int                            UNIT : 4;
                unsigned int                                 : 4;
                unsigned int                           VALUE : 16;
                unsigned int                                 : 6;
                unsigned int                          PREFER : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_PHASE1_QUANTUM__CI__VI {
	struct {
                unsigned int                            UNIT : 4;
                unsigned int                                 : 4;
                unsigned int                           VALUE : 16;
                unsigned int                                 : 6;
                unsigned int                          PREFER : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_POWER_CNTL__CI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int              MEM_POWER_OVERRIDE : 1;
                unsigned int             MEM_POWER_LS_EN__VI : 1;
                unsigned int             MEM_POWER_DS_EN__VI : 1;
                unsigned int             MEM_POWER_SD_EN__VI : 1;
                unsigned int                                 : 6;
                unsigned int                                 : 4;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_PROGRAM__CI__VI {
	struct {
                unsigned int                          STREAM : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RB_RPTR_FETCH__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_APE1_CNTL__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                           LIMIT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_CONTEXT_STATUS__CI__VI {
	struct {
                unsigned int                        SELECTED : 1;
                unsigned int                                 : 1;
                unsigned int                            IDLE : 1;
                unsigned int                         EXPIRED : 1;
                unsigned int                       EXCEPTION : 3;
                unsigned int                      CTXSW_ABLE : 1;
                unsigned int                     CTXSW_READY : 1;
                unsigned int                   PREEMPTED__VI : 1;
                unsigned int             PREEMPT_DISABLE__VI : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_DOORBELL_LOG__CI__VI {
	struct {
                unsigned int                        BE_ERROR : 1;
                unsigned int                                 : 1;
                unsigned int                            DATA : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_DOORBELL__CI__VI {
	struct {
                unsigned int                          OFFSET : 21;
                unsigned int                                 : 7;
                unsigned int                          ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int                        CAPTURED : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_IB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_IB_BASE_LO__CI__VI {
	struct {
                unsigned int                                 : 5;
                unsigned int                            ADDR : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_IB_CNTL__CI__VI {
	struct {
                unsigned int                       IB_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                  IB_SWAP_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                SWITCH_INSIDE_IB : 1;
                unsigned int                                 : 7;
                unsigned int                        CMD_VMID : 4;
                unsigned int                                 : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_IB_OFFSET__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_IB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_IB_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_RB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_RB_BASE__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_RB_CNTL__CI__VI {
	struct {
                unsigned int                       RB_ENABLE : 1;
                unsigned int                         RB_SIZE : 5;
                unsigned int                                 : 3;
                unsigned int                  RB_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int           RPTR_WRITEBACK_ENABLE : 1;
                unsigned int      RPTR_WRITEBACK_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int            RPTR_WRITEBACK_TIMER : 5;
                unsigned int                                 : 2;
                unsigned int                         RB_PRIV : 1;
                unsigned int                         RB_VMID : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_RB_RPTR_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_RB_RPTR_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_RB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_RB_WPTR_POLL_CNTL__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                     SWAP_ENABLE : 1;
                unsigned int             F32_POLL_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int                       FREQUENCY : 12;
                unsigned int                 IDLE_POLL_COUNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_RB_WPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_SKIP_CNTL__CI__VI {
	struct {
                unsigned int                      SKIP_COUNT : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_VIRTUAL_ADDR__CI__VI {
	struct {
                unsigned int                             ATC : 1;
                unsigned int                       INVAL__VI : 1;
                unsigned int                                 : 2;
                unsigned int                           PTR32 : 1;
                unsigned int                                 : 3;
                unsigned int                     SHARED_BASE : 3;
                unsigned int                                 : 19;
                unsigned int                         VM_HOLE : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_APE1_CNTL__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                           LIMIT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_CONTEXT_STATUS__CI__VI {
	struct {
                unsigned int                        SELECTED : 1;
                unsigned int                                 : 1;
                unsigned int                            IDLE : 1;
                unsigned int                         EXPIRED : 1;
                unsigned int                       EXCEPTION : 3;
                unsigned int                      CTXSW_ABLE : 1;
                unsigned int                     CTXSW_READY : 1;
                unsigned int                   PREEMPTED__VI : 1;
                unsigned int             PREEMPT_DISABLE__VI : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_DOORBELL_LOG__CI__VI {
	struct {
                unsigned int                        BE_ERROR : 1;
                unsigned int                                 : 1;
                unsigned int                            DATA : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_DOORBELL__CI__VI {
	struct {
                unsigned int                          OFFSET : 21;
                unsigned int                                 : 7;
                unsigned int                          ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int                        CAPTURED : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_IB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_IB_BASE_LO__CI__VI {
	struct {
                unsigned int                                 : 5;
                unsigned int                            ADDR : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_IB_CNTL__CI__VI {
	struct {
                unsigned int                       IB_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                  IB_SWAP_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                SWITCH_INSIDE_IB : 1;
                unsigned int                                 : 7;
                unsigned int                        CMD_VMID : 4;
                unsigned int                                 : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_IB_OFFSET__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_IB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_IB_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_RB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_RB_BASE__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_RB_CNTL__CI__VI {
	struct {
                unsigned int                       RB_ENABLE : 1;
                unsigned int                         RB_SIZE : 5;
                unsigned int                                 : 3;
                unsigned int                  RB_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int           RPTR_WRITEBACK_ENABLE : 1;
                unsigned int      RPTR_WRITEBACK_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int            RPTR_WRITEBACK_TIMER : 5;
                unsigned int                                 : 2;
                unsigned int                         RB_PRIV : 1;
                unsigned int                         RB_VMID : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_RB_RPTR_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_RB_RPTR_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_RB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_RB_WPTR_POLL_CNTL__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                     SWAP_ENABLE : 1;
                unsigned int             F32_POLL_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int                       FREQUENCY : 12;
                unsigned int                 IDLE_POLL_COUNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_RB_WPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_SKIP_CNTL__CI__VI {
	struct {
                unsigned int                      SKIP_COUNT : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_VIRTUAL_ADDR__CI__VI {
	struct {
                unsigned int                             ATC : 1;
                unsigned int                       INVAL__VI : 1;
                unsigned int                                 : 2;
                unsigned int                           PTR32 : 1;
                unsigned int                                 : 3;
                unsigned int                     SHARED_BASE : 3;
                unsigned int                                 : 19;
                unsigned int                         VM_HOLE : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_SEM_INCOMPLETE_TIMER_CNTL__CI {
	struct {
		unsigned int                           TIMER : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI {
	struct {
                unsigned int                           TIMER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_STATUS1_REG__CI__VI {
	struct {
                unsigned int                    CE_WREQ_IDLE : 1;
                unsigned int                      CE_WR_IDLE : 1;
                unsigned int                   CE_SPLIT_IDLE : 1;
                unsigned int                    CE_RREQ_IDLE : 1;
                unsigned int                     CE_OUT_IDLE : 1;
                unsigned int                      CE_IN_IDLE : 1;
                unsigned int                     CE_DST_IDLE : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                 CE_CMD_IDLE__VI : 1;
                unsigned int                   CE_AFIFO_FULL : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                    CE_INFO_FULL : 1;
                unsigned int                   CE_INFO1_FULL : 1;
                unsigned int                                 : 2;
                unsigned int                     CE_RD_STALL : 1;
                unsigned int                     CE_WR_STALL : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_STATUS_REG__CI {
	struct {
		unsigned int                            IDLE : 1;
		unsigned int                        REG_IDLE : 1;
		unsigned int                        RB_EMPTY : 1;
		unsigned int                         RB_FULL : 1;
		unsigned int                     RB_CMD_IDLE : 1;
		unsigned int                     RB_CMD_FULL : 1;
		unsigned int                     IB_CMD_IDLE : 1;
		unsigned int                     IB_CMD_FULL : 1;
		unsigned int                      BLOCK_IDLE : 1;
		unsigned int                       INSIDE_IB : 1;
		unsigned int                         EX_IDLE : 1;
		unsigned int       EX_IDLE_POLL_TIMER_EXPIRE : 1;
		unsigned int                    PACKET_READY : 1;
		unsigned int                      MC_WR_IDLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 RB_MC_RREQ_IDLE : 1;
		unsigned int                 IB_MC_RREQ_IDLE : 1;
		unsigned int                      MC_RD_IDLE : 1;
		unsigned int                                 : 1;
		unsigned int                 MC_RD_RET_STALL : 1;
		unsigned int              MC_RD_NO_POLL_IDLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                   PREV_CMD_IDLE : 1;
		unsigned int                        SEM_IDLE : 1;
		unsigned int                   SEM_REQ_STALL : 1;
		unsigned int                  SEM_RESP_STATE : 2;
		unsigned int                        INT_IDLE : 1;
		unsigned int                   INT_REQ_STALL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_STATUS_REG__VI {
	struct {
		unsigned int                            IDLE : 1;
		unsigned int                        REG_IDLE : 1;
		unsigned int                        RB_EMPTY : 1;
		unsigned int                         RB_FULL : 1;
		unsigned int                     RB_CMD_IDLE : 1;
		unsigned int                     RB_CMD_FULL : 1;
		unsigned int                     IB_CMD_IDLE : 1;
		unsigned int                     IB_CMD_FULL : 1;
		unsigned int                      BLOCK_IDLE : 1;
		unsigned int                       INSIDE_IB : 1;
		unsigned int                         EX_IDLE : 1;
		unsigned int       EX_IDLE_POLL_TIMER_EXPIRE : 1;
		unsigned int                    PACKET_READY : 1;
		unsigned int                      MC_WR_IDLE : 1;
		unsigned int                       SRBM_IDLE : 1;
		unsigned int                   CONTEXT_EMPTY : 1;
		unsigned int                 DELTA_RPTR_FULL : 1;
		unsigned int                 RB_MC_RREQ_IDLE : 1;
		unsigned int                 IB_MC_RREQ_IDLE : 1;
		unsigned int                      MC_RD_IDLE : 1;
		unsigned int                DELTA_RPTR_EMPTY : 1;
		unsigned int                 MC_RD_RET_STALL : 1;
		unsigned int              MC_RD_NO_POLL_IDLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                   PREV_CMD_IDLE : 1;
		unsigned int                        SEM_IDLE : 1;
		unsigned int                   SEM_REQ_STALL : 1;
		unsigned int                  SEM_RESP_STATE : 2;
		unsigned int                        INT_IDLE : 1;
		unsigned int                   INT_REQ_STALL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_TILING_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int            PIPE_INTERLEAVE_SIZE : 3;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_UCODE_ADDR__CI__VI {
	struct {
                unsigned int                           VALUE : 13;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_UCODE_DATA__CI__VI {
	struct {
                unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_CHICKEN_BITS__CI__VI {
	struct {
                unsigned int          COPY_EFFICIENCY_ENABLE : 1;
                unsigned int  STALL_ON_TRANS_FULL_ENABLE__VI : 1;
                unsigned int STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__VI : 1;
                unsigned int                                 : 13;
                unsigned int             COPY_OVERLAP_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int              SRBM_POLL_RETRYING : 1;
                unsigned int                                 : 2;
                unsigned int                CG_STATUS_OUTPUT : 1;
                unsigned int                                 : 2;
                unsigned int          CE_AFIFO_WATERMARK__VI : 2;
                unsigned int          CE_DFIFO_WATERMARK__VI : 2;
                unsigned int          CE_LFIFO_WATERMARK__VI : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_CLK_CTRL__CI__VI {
	struct {
                unsigned int                        ON_DELAY : 4;
                unsigned int                  OFF_HYSTERESIS : 8;
                unsigned int                                 : 12;
                unsigned int                  SOFT_OVERRIDE7 : 1;
                unsigned int                  SOFT_OVERRIDE6 : 1;
                unsigned int                  SOFT_OVERRIDE5 : 1;
                unsigned int                  SOFT_OVERRIDE4 : 1;
                unsigned int                  SOFT_OVERRIDE3 : 1;
                unsigned int                  SOFT_OVERRIDE2 : 1;
                unsigned int                  SOFT_OVERRIDE1 : 1;
                unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_CNTL__CI {
	struct {
		unsigned int                     TRAP_ENABLE : 1;
		unsigned int       SEM_INCOMPLETE_INT_ENABLE : 1;
		unsigned int             SEM_WAIT_INT_ENABLE : 1;
		unsigned int                DATA_SWAP_ENABLE : 1;
		unsigned int               FENCE_SWAP_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                 MC_WRREQ_CREDIT : 6;
		unsigned int                                 : 1;
		unsigned int               AUTO_CTXSW_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int                 MC_RDREQ_CREDIT : 6;
		unsigned int             CTXEMPTY_INT_ENABLE : 1;
		unsigned int               FROZEN_INT_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_CNTL__VI {
	struct {
		unsigned int                     TRAP_ENABLE : 1;
		unsigned int                   ATC_L1_ENABLE : 1;
		unsigned int             SEM_WAIT_INT_ENABLE : 1;
		unsigned int                DATA_SWAP_ENABLE : 1;
		unsigned int               FENCE_SWAP_ENABLE : 1;
		unsigned int           MIDCMD_PREEMPT_ENABLE : 1;
		unsigned int                                 : 5;
		unsigned int                 MC_WRREQ_CREDIT : 6;
		unsigned int       MIDCMD_WORLDSWITCH_ENABLE : 1;
		unsigned int               AUTO_CTXSW_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                 MC_RDREQ_CREDIT : 6;
		unsigned int             CTXEMPTY_INT_ENABLE : 1;
		unsigned int               FROZEN_INT_ENABLE : 1;
		unsigned int           IB_PREEMPT_INT_ENABLE : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int                  SDMA_RDREQ_URG : 4;
                unsigned int                                 : 4;
                unsigned int                   SDMA_REQ_TRAN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_F32_CNTL__CI__VI {
	struct {
                unsigned int                            HALT : 1;
                unsigned int                            STEP : 1;
                unsigned int             DBG_SELECT_BITS__VI : 6;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_FREEZE__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 3;
                unsigned int                          FREEZE : 1;
                unsigned int                          FROZEN : 1;
                unsigned int                  F32_FREEZE__VI : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_APE1_CNTL__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                           LIMIT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_CONTEXT_CNTL__CI__VI {
	struct {
                unsigned int                                 : 16;
                unsigned int                      RESUME_CTX : 1;
                unsigned int                                 : 7;
                unsigned int                     SESSION_SEL : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_CONTEXT_STATUS__CI__VI {
	struct {
                unsigned int                        SELECTED : 1;
                unsigned int                                 : 1;
                unsigned int                            IDLE : 1;
                unsigned int                         EXPIRED : 1;
                unsigned int                       EXCEPTION : 3;
                unsigned int                      CTXSW_ABLE : 1;
                unsigned int                     CTXSW_READY : 1;
                unsigned int                   PREEMPTED__VI : 1;
                unsigned int             PREEMPT_DISABLE__VI : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_IB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_IB_BASE_LO__CI__VI {
	struct {
                unsigned int                                 : 5;
                unsigned int                            ADDR : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_IB_CNTL__CI__VI {
	struct {
                unsigned int                       IB_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                  IB_SWAP_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                SWITCH_INSIDE_IB : 1;
                unsigned int                                 : 7;
                unsigned int                        CMD_VMID : 4;
                unsigned int                                 : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_IB_OFFSET__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_IB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_IB_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_RB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_RB_BASE__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_RB_CNTL__CI__VI {
	struct {
                unsigned int                       RB_ENABLE : 1;
                unsigned int                         RB_SIZE : 5;
                unsigned int                                 : 3;
                unsigned int                  RB_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int           RPTR_WRITEBACK_ENABLE : 1;
                unsigned int      RPTR_WRITEBACK_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int            RPTR_WRITEBACK_TIMER : 5;
                unsigned int                                 : 2;
                unsigned int                         RB_PRIV : 1;
                unsigned int                         RB_VMID : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_RB_RPTR_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_RB_RPTR_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_RB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_RB_WPTR_POLL_CNTL__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                     SWAP_ENABLE : 1;
                unsigned int             F32_POLL_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int                       FREQUENCY : 12;
                unsigned int                 IDLE_POLL_COUNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_RB_WPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_SKIP_CNTL__CI__VI {
	struct {
                unsigned int                      SKIP_COUNT : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_VIRTUAL_ADDR__CI__VI {
	struct {
                unsigned int                             ATC : 1;
                unsigned int                       INVAL__VI : 1;
                unsigned int                                 : 2;
                unsigned int                           PTR32 : 1;
                unsigned int                                 : 3;
                unsigned int                     SHARED_BASE : 3;
                unsigned int                                 : 19;
                unsigned int                         VM_HOLE : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_HASH__CI__VI {
	struct {
                unsigned int                    CHANNEL_BITS : 3;
                unsigned int                                 : 1;
                unsigned int                       BANK_BITS : 3;
                unsigned int                                 : 1;
                unsigned int               CHANNEL_XOR_COUNT : 3;
                unsigned int                                 : 1;
                unsigned int                  BANK_XOR_COUNT : 3;
                unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_IB_OFFSET_FETCH__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_PERFCOUNTER0_RESULT__CI__VI {
	struct {
                unsigned int                      PERF_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_PERFCOUNTER1_RESULT__CI__VI {
	struct {
                unsigned int                      PERF_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_PERFMON_CNTL__CI__VI {
	struct {
                unsigned int                    PERF_ENABLE0 : 1;
                unsigned int                     PERF_CLEAR0 : 1;
                unsigned int                       PERF_SEL0 : 6;
                unsigned int                    PERF_ENABLE1 : 1;
                unsigned int                     PERF_CLEAR1 : 1;
                unsigned int                       PERF_SEL1 : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_PHASE0_QUANTUM__CI__VI {
	struct {
                unsigned int                            UNIT : 4;
                unsigned int                                 : 4;
                unsigned int                           VALUE : 16;
                unsigned int                                 : 6;
                unsigned int                          PREFER : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_PHASE1_QUANTUM__CI__VI {
	struct {
                unsigned int                            UNIT : 4;
                unsigned int                                 : 4;
                unsigned int                           VALUE : 16;
                unsigned int                                 : 6;
                unsigned int                          PREFER : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_POWER_CNTL__CI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int              MEM_POWER_OVERRIDE : 1;
                unsigned int             MEM_POWER_LS_EN__VI : 1;
                unsigned int             MEM_POWER_DS_EN__VI : 1;
                unsigned int             MEM_POWER_SD_EN__VI : 1;
                unsigned int                                 : 6;
                unsigned int                                 : 4;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_PROGRAM__CI__VI {
	struct {
                unsigned int                          STREAM : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RB_RPTR_FETCH__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_APE1_CNTL__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                           LIMIT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_CONTEXT_STATUS__CI__VI {
	struct {
                unsigned int                        SELECTED : 1;
                unsigned int                                 : 1;
                unsigned int                            IDLE : 1;
                unsigned int                         EXPIRED : 1;
                unsigned int                       EXCEPTION : 3;
                unsigned int                      CTXSW_ABLE : 1;
                unsigned int                     CTXSW_READY : 1;
                unsigned int                   PREEMPTED__VI : 1;
                unsigned int             PREEMPT_DISABLE__VI : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_DOORBELL_LOG__CI__VI {
	struct {
                unsigned int                        BE_ERROR : 1;
                unsigned int                                 : 1;
                unsigned int                            DATA : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_DOORBELL__CI__VI {
	struct {
                unsigned int                          OFFSET : 21;
                unsigned int                                 : 7;
                unsigned int                          ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int                        CAPTURED : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_IB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_IB_BASE_LO__CI__VI {
	struct {
                unsigned int                                 : 5;
                unsigned int                            ADDR : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_IB_CNTL__CI__VI {
	struct {
                unsigned int                       IB_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                  IB_SWAP_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                SWITCH_INSIDE_IB : 1;
                unsigned int                                 : 7;
                unsigned int                        CMD_VMID : 4;
                unsigned int                                 : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_IB_OFFSET__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_IB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_IB_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_RB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_RB_BASE__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_RB_CNTL__CI__VI {
	struct {
                unsigned int                       RB_ENABLE : 1;
                unsigned int                         RB_SIZE : 5;
                unsigned int                                 : 3;
                unsigned int                  RB_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int           RPTR_WRITEBACK_ENABLE : 1;
                unsigned int      RPTR_WRITEBACK_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int            RPTR_WRITEBACK_TIMER : 5;
                unsigned int                                 : 2;
                unsigned int                         RB_PRIV : 1;
                unsigned int                         RB_VMID : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_RB_RPTR_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_RB_RPTR_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_RB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_RB_WPTR_POLL_CNTL__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                     SWAP_ENABLE : 1;
                unsigned int             F32_POLL_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int                       FREQUENCY : 12;
                unsigned int                 IDLE_POLL_COUNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_RB_WPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_SKIP_CNTL__CI__VI {
	struct {
                unsigned int                      SKIP_COUNT : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_VIRTUAL_ADDR__CI__VI {
	struct {
                unsigned int                             ATC : 1;
                unsigned int                       INVAL__VI : 1;
                unsigned int                                 : 2;
                unsigned int                           PTR32 : 1;
                unsigned int                                 : 3;
                unsigned int                     SHARED_BASE : 3;
                unsigned int                                 : 19;
                unsigned int                         VM_HOLE : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_APE1_CNTL__CI__VI {
	struct {
                unsigned int                            BASE : 16;
                unsigned int                           LIMIT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_CONTEXT_STATUS__CI__VI {
	struct {
                unsigned int                        SELECTED : 1;
                unsigned int                                 : 1;
                unsigned int                            IDLE : 1;
                unsigned int                         EXPIRED : 1;
                unsigned int                       EXCEPTION : 3;
                unsigned int                      CTXSW_ABLE : 1;
                unsigned int                     CTXSW_READY : 1;
                unsigned int                   PREEMPTED__VI : 1;
                unsigned int             PREEMPT_DISABLE__VI : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_DOORBELL_LOG__CI__VI {
	struct {
                unsigned int                        BE_ERROR : 1;
                unsigned int                                 : 1;
                unsigned int                            DATA : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_DOORBELL__CI__VI {
	struct {
                unsigned int                          OFFSET : 21;
                unsigned int                                 : 7;
                unsigned int                          ENABLE : 1;
                unsigned int                                 : 1;
                unsigned int                        CAPTURED : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_IB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_IB_BASE_LO__CI__VI {
	struct {
                unsigned int                                 : 5;
                unsigned int                            ADDR : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_IB_CNTL__CI__VI {
	struct {
                unsigned int                       IB_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                  IB_SWAP_ENABLE : 1;
                unsigned int                                 : 3;
                unsigned int                SWITCH_INSIDE_IB : 1;
                unsigned int                                 : 7;
                unsigned int                        CMD_VMID : 4;
                unsigned int                                 : 11;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_IB_OFFSET__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_IB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 20;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_IB_SIZE__CI__VI {
	struct {
                unsigned int                            SIZE : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_RB_BASE_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_RB_BASE__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_RB_CNTL__CI__VI {
	struct {
                unsigned int                       RB_ENABLE : 1;
                unsigned int                         RB_SIZE : 5;
                unsigned int                                 : 3;
                unsigned int                  RB_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int           RPTR_WRITEBACK_ENABLE : 1;
                unsigned int      RPTR_WRITEBACK_SWAP_ENABLE : 1;
                unsigned int                                 : 2;
                unsigned int            RPTR_WRITEBACK_TIMER : 5;
                unsigned int                                 : 2;
                unsigned int                         RB_PRIV : 1;
                unsigned int                         RB_VMID : 4;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_RB_RPTR_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_RB_RPTR_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_RB_RPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI {
	struct {
                unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_RB_WPTR_POLL_CNTL__CI__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                     SWAP_ENABLE : 1;
                unsigned int             F32_POLL_ENABLE__VI : 1;
                unsigned int                                 : 1;
                unsigned int                       FREQUENCY : 12;
                unsigned int                 IDLE_POLL_COUNT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_RB_WPTR__CI__VI {
	struct {
                unsigned int                                 : 2;
                unsigned int                          OFFSET : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_SKIP_CNTL__CI__VI {
	struct {
                unsigned int                      SKIP_COUNT : 14;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_VIRTUAL_ADDR__CI__VI {
	struct {
                unsigned int                             ATC : 1;
                unsigned int                       INVAL__VI : 1;
                unsigned int                                 : 2;
                unsigned int                           PTR32 : 1;
                unsigned int                                 : 3;
                unsigned int                     SHARED_BASE : 3;
                unsigned int                                 : 19;
                unsigned int                         VM_HOLE : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_SEM_INCOMPLETE_TIMER_CNTL__CI {
	struct {
		unsigned int                           TIMER : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI {
	struct {
                unsigned int                           TIMER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_STATUS1_REG__CI__VI {
	struct {
                unsigned int                    CE_WREQ_IDLE : 1;
                unsigned int                      CE_WR_IDLE : 1;
                unsigned int                   CE_SPLIT_IDLE : 1;
                unsigned int                    CE_RREQ_IDLE : 1;
                unsigned int                     CE_OUT_IDLE : 1;
                unsigned int                      CE_IN_IDLE : 1;
                unsigned int                     CE_DST_IDLE : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                 CE_CMD_IDLE__VI : 1;
                unsigned int                   CE_AFIFO_FULL : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                    CE_INFO_FULL : 1;
                unsigned int                   CE_INFO1_FULL : 1;
                unsigned int                                 : 2;
                unsigned int                     CE_RD_STALL : 1;
                unsigned int                     CE_WR_STALL : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_STATUS_REG__CI {
	struct {
		unsigned int                            IDLE : 1;
		unsigned int                        REG_IDLE : 1;
		unsigned int                        RB_EMPTY : 1;
		unsigned int                         RB_FULL : 1;
		unsigned int                     RB_CMD_IDLE : 1;
		unsigned int                     RB_CMD_FULL : 1;
		unsigned int                     IB_CMD_IDLE : 1;
		unsigned int                     IB_CMD_FULL : 1;
		unsigned int                      BLOCK_IDLE : 1;
		unsigned int                       INSIDE_IB : 1;
		unsigned int                         EX_IDLE : 1;
		unsigned int       EX_IDLE_POLL_TIMER_EXPIRE : 1;
		unsigned int                    PACKET_READY : 1;
		unsigned int                      MC_WR_IDLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 RB_MC_RREQ_IDLE : 1;
		unsigned int                 IB_MC_RREQ_IDLE : 1;
		unsigned int                      MC_RD_IDLE : 1;
		unsigned int                                 : 1;
		unsigned int                 MC_RD_RET_STALL : 1;
		unsigned int              MC_RD_NO_POLL_IDLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                   PREV_CMD_IDLE : 1;
		unsigned int                        SEM_IDLE : 1;
		unsigned int                   SEM_REQ_STALL : 1;
		unsigned int                  SEM_RESP_STATE : 2;
		unsigned int                        INT_IDLE : 1;
		unsigned int                   INT_REQ_STALL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_STATUS_REG__VI {
	struct {
		unsigned int                            IDLE : 1;
		unsigned int                        REG_IDLE : 1;
		unsigned int                        RB_EMPTY : 1;
		unsigned int                         RB_FULL : 1;
		unsigned int                     RB_CMD_IDLE : 1;
		unsigned int                     RB_CMD_FULL : 1;
		unsigned int                     IB_CMD_IDLE : 1;
		unsigned int                     IB_CMD_FULL : 1;
		unsigned int                      BLOCK_IDLE : 1;
		unsigned int                       INSIDE_IB : 1;
		unsigned int                         EX_IDLE : 1;
		unsigned int       EX_IDLE_POLL_TIMER_EXPIRE : 1;
		unsigned int                    PACKET_READY : 1;
		unsigned int                      MC_WR_IDLE : 1;
		unsigned int                       SRBM_IDLE : 1;
		unsigned int                   CONTEXT_EMPTY : 1;
		unsigned int                 DELTA_RPTR_FULL : 1;
		unsigned int                 RB_MC_RREQ_IDLE : 1;
		unsigned int                 IB_MC_RREQ_IDLE : 1;
		unsigned int                      MC_RD_IDLE : 1;
		unsigned int                DELTA_RPTR_EMPTY : 1;
		unsigned int                 MC_RD_RET_STALL : 1;
		unsigned int              MC_RD_NO_POLL_IDLE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                   PREV_CMD_IDLE : 1;
		unsigned int                        SEM_IDLE : 1;
		unsigned int                   SEM_REQ_STALL : 1;
		unsigned int                  SEM_RESP_STATE : 2;
		unsigned int                        INT_IDLE : 1;
		unsigned int                   INT_REQ_STALL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_TILING_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int            PIPE_INTERLEAVE_SIZE : 3;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_UCODE_ADDR__CI__VI {
	struct {
                unsigned int                           VALUE : 13;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_UCODE_DATA__CI__VI {
	struct {
                unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int                  SDMA_RDREQ_URG : 4;
                unsigned int                                 : 4;
                unsigned int                   SDMA_REQ_TRAN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA_PGFSM_CONFIG__CI__VI {
	struct {
                unsigned int                        FSM_ADDR : 8;
                unsigned int                      POWER_DOWN : 1;
                unsigned int                        POWER_UP : 1;
                unsigned int                       P1_SELECT : 1;
                unsigned int                       P2_SELECT : 1;
                unsigned int                           WRITE : 1;
                unsigned int                            READ : 1;
                unsigned int                                 : 13;
                unsigned int                   SRBM_OVERRIDE : 1;
                unsigned int                        REG_ADDR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA_PGFSM_READ__CI__VI {
	struct {
                unsigned int                           VALUE : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA_PGFSM_WRITE__CI__VI {
	struct {
                unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA_POWER_GATING__CI__VI {
	struct {
                unsigned int                  PG_CNTL_ENABLE : 1;
                unsigned int         AUTOMATIC_STATUS_ENABLE : 1;
                unsigned int                  PG_STATE_VALID : 1;
                unsigned int                                 : 1;
                unsigned int                  PG_CNTL_STATUS : 2;
                unsigned int              SDMA0_ON_CONDITION : 1;
                unsigned int              SDMA1_ON_CONDITION : 1;
                unsigned int                 POWER_OFF_DELAY : 12;
                unsigned int                  POWER_ON_DELAY : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_CHICKEN_BITS__CI__VI {
	struct {
                unsigned int                VMID_PIPELINE_EN : 1;
                unsigned int               ENTRY_PIPELINE_EN : 1;
                unsigned int            CHECK_COUNTER_EN__VI : 1;
                unsigned int                ECC_BEHAVIOR__VI : 2;
                unsigned int                 SIGNAL_FAIL__VI : 1;
                unsigned int                 PHY_TRAN_EN__VI : 1;
                unsigned int          ADDR_CMP_UNTRAN_EN__VI : 1;
                unsigned int          IDLE_COUNTER_INDEX__VI : 4;
                unsigned int                ATCL2_BUS_ID__VI : 2;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_EDC_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                         DIS_EDC : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_MAILBOX {
	struct {
                unsigned int                        SIDEPORT : 8;
                unsigned int                        HOSTPORT : 8;
                unsigned int              SIDEPORT_EXTRA__VI : 8;
                unsigned int              HOSTPORT_EXTRA__VI : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_MAILBOX_CLIENTCONFIG__CI__VI {
	struct {
                unsigned int                      CP_CLIENT0 : 3;
                unsigned int                      CP_CLIENT1 : 3;
                unsigned int                      CP_CLIENT2 : 3;
                unsigned int                      CP_CLIENT3 : 3;
                unsigned int                    SDMA_CLIENT0 : 3;
                unsigned int                     UVD_CLIENT0 : 3;
                unsigned int                   SDMA1_CLIENT0 : 3;
                unsigned int                     VCE_CLIENT0 : 3;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_MAILBOX_CLIENTCONFIG__SI {
	struct {
		unsigned int                      CP_CLIENT0 : 3;
		unsigned int                      CP_CLIENT1 : 3;
		unsigned int                      CP_CLIENT2 : 3;
		unsigned int                      CP_CLIENT3 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_MAILBOX_CONTROL {
	struct {
                unsigned int                 SIDEPORT_ENABLE : 8;
                unsigned int                 HOSTPORT_ENABLE : 8;
                unsigned int       SIDEPORT_ENABLE_EXTRA__VI : 8;
                unsigned int       HOSTPORT_ENABLE_EXTRA__VI : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_MCIF_CONFIG {
	struct {
                unsigned int                     MC_REQ_SWAP : 2;
                unsigned int         MC_WRREQ_CREDIT__CI__VI : 6;
                unsigned int         MC_RDREQ_CREDIT__CI__VI : 6;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_STATUS__CI__VI {
	struct {
                unsigned int                        SEM_IDLE : 1;
                unsigned int               SEM_INTERNAL_IDLE : 1;
                unsigned int              MC_RDREQ_FIFO_FULL : 1;
                unsigned int              MC_WRREQ_FIFO_FULL : 1;
                unsigned int                WRITE1_FIFO_FULL : 1;
                unsigned int                CHECK0_FIFO_FULL : 1;
                unsigned int                MC_RDREQ_PENDING : 1;
                unsigned int                MC_WRREQ_PENDING : 1;
                unsigned int           SDMA0_MAILBOX_PENDING : 1;
                unsigned int           SDMA1_MAILBOX_PENDING : 1;
                unsigned int             UVD_MAILBOX_PENDING : 1;
                unsigned int             VCE_MAILBOX_PENDING : 1;
                unsigned int            CPG1_MAILBOX_PENDING : 1;
                unsigned int            CPG2_MAILBOX_PENDING : 1;
                unsigned int        VCE1_MAILBOX_PENDING__VI : 1;
                unsigned int             ATC_REQ_PENDING__VI : 1;
                unsigned int                                 : 15;
                unsigned int                SWITCH_READY__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEQ00__SI__VI {
	struct {
                unsigned int                       SEQ_RST0B : 1;
                unsigned int                       SEQ_RST1B : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEQ01__SI__VI {
	struct {
                unsigned int                        SEQ_DOT8 : 1;
                unsigned int                                 : 1;
                unsigned int                      SEQ_SHIFT2 : 1;
                unsigned int                     SEQ_PCLKBY2 : 1;
                unsigned int                      SEQ_SHIFT4 : 1;
                unsigned int                       SEQ_MAXBW : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEQ02__SI__VI {
	struct {
                unsigned int                     SEQ_MAP0_EN : 1;
                unsigned int                     SEQ_MAP1_EN : 1;
                unsigned int                     SEQ_MAP2_EN : 1;
                unsigned int                     SEQ_MAP3_EN : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEQ03__SI__VI {
	struct {
                unsigned int                     SEQ_FONT_B1 : 1;
                unsigned int                     SEQ_FONT_B2 : 1;
                unsigned int                     SEQ_FONT_A1 : 1;
                unsigned int                     SEQ_FONT_A2 : 1;
                unsigned int                     SEQ_FONT_B0 : 1;
                unsigned int                     SEQ_FONT_A0 : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEQ04__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                        SEQ_256K : 1;
                unsigned int                     SEQ_ODDEVEN : 1;
                unsigned int                       SEQ_CHAIN : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEQ8_DATA__SI__VI {
	struct {
                unsigned int                        SEQ_DATA : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEQ8_IDX__SI__VI {
	struct {
                unsigned int                         SEQ_IDX : 3;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SETUP_DEBUG_REG0 {
	struct {
		unsigned int             su_baryc_cntl_state : 2;
		unsigned int                   su_cntl_state : 4;
		unsigned int                                 : 2;
		unsigned int                     pmode_state : 6;
		unsigned int                       ge_stallb : 1;
		unsigned int                     geom_enable : 1;
		unsigned int              su_clip_baryc_free : 2;
		unsigned int                     su_clip_rtr : 1;
		unsigned int                      pfifo_busy : 1;
		unsigned int                    su_cntl_busy : 1;
		unsigned int                       geom_busy : 1;
		unsigned int                  event_id_gated : 6;
		unsigned int                     event_gated : 1;
		unsigned int                pmode_prim_gated : 1;
		unsigned int                 su_dyn_sclk_vld : 1;
		unsigned int                 cl_dyn_sclk_vld : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SETUP_DEBUG_REG1 {
	struct {
		unsigned int              y_sort0_gated_23_8 : 16;
		unsigned int              x_sort0_gated_23_8 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SETUP_DEBUG_REG2 {
	struct {
		unsigned int              y_sort1_gated_23_8 : 16;
		unsigned int              x_sort1_gated_23_8 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SETUP_DEBUG_REG3 {
	struct {
		unsigned int              y_sort2_gated_23_8 : 16;
		unsigned int              x_sort2_gated_23_8 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SETUP_DEBUG_REG4 {
	struct {
		unsigned int           attr_indx_sort0_gated : 14;
		unsigned int                 null_prim_gated : 1;
		unsigned int                backfacing_gated : 1;
		unsigned int                   st_indx_gated : 3;
		unsigned int                   clipped_gated : 1;
		unsigned int              dealloc_slot_gated : 3;
		unsigned int                    xmajor_gated : 1;
		unsigned int              diamond_rule_gated : 2;
		unsigned int                      type_gated : 3;
		unsigned int                      fpov_gated : 2;
		unsigned int                       eop_gated : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SETUP_DEBUG_REG5 {
	struct {
		unsigned int           attr_indx_sort2_gated : 14;
		unsigned int           attr_indx_sort1_gated : 14;
		unsigned int             provoking_vtx_gated : 2;
		unsigned int                valid_prim_gated : 1;
		unsigned int                 pa_reg_sclk_vld : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SH_HIDDEN_PRIVATE_BASE_VMID__CI__VI {
	struct {
                unsigned int                         ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SH_MEM_APE1_BASE__CI__VI {
	struct {
                unsigned int                            BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SH_MEM_APE1_LIMIT__CI__VI {
	struct {
                unsigned int                           LIMIT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SH_MEM_BASES__CI__VI {
	struct {
                unsigned int                    PRIVATE_BASE : 16;
                unsigned int                     SHARED_BASE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SH_MEM_CONFIG__CI {
	struct {
		unsigned int                           PTR32 : 1;
		unsigned int                     PRIVATE_ATC : 1;
		unsigned int                  ALIGNMENT_MODE : 2;
		unsigned int                   DEFAULT_MTYPE : 3;
		unsigned int                      APE1_MTYPE : 3;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SH_MEM_CONFIG__VI {
	struct {
		unsigned int                    ADDRESS_MODE : 2;
		unsigned int                     PRIVATE_ATC : 1;
		unsigned int                  ALIGNMENT_MODE : 2;
		unsigned int                   DEFAULT_MTYPE : 3;
		unsigned int                      APE1_MTYPE : 3;
		unsigned int                        APE1_ATC : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SH_STATIC_MEM_CONFIG__CI__VI {
	struct {
                unsigned int                  SWIZZLE_ENABLE : 1;
                unsigned int                    ELEMENT_SIZE : 2;
                unsigned int                    INDEX_STRIDE : 2;
                unsigned int                   PRIVATE_MTYPE : 3;
                unsigned int                  READ_ONLY_CNTL : 8;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SLAVE_COMM_CMD_REG__SI__VI {
	struct {
                unsigned int        SLAVE_COMM_CMD_REG_BYTE0 : 8;
                unsigned int        SLAVE_COMM_CMD_REG_BYTE1 : 8;
                unsigned int        SLAVE_COMM_CMD_REG_BYTE2 : 8;
                unsigned int        SLAVE_COMM_CMD_REG_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SLAVE_COMM_CNTL_REG__SI__VI {
	struct {
                unsigned int            SLAVE_COMM_INTERRUPT : 1;
                unsigned int                                 : 7;
                unsigned int COMM_PORT_MSG_TO_HOST_IN_PROGRESS : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SLAVE_COMM_DATA_REG1__SI__VI {
	struct {
                unsigned int      SLAVE_COMM_DATA_REG1_BYTE0 : 8;
                unsigned int      SLAVE_COMM_DATA_REG1_BYTE1 : 8;
                unsigned int      SLAVE_COMM_DATA_REG1_BYTE2 : 8;
                unsigned int      SLAVE_COMM_DATA_REG1_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SLAVE_COMM_DATA_REG2__SI__VI {
	struct {
                unsigned int      SLAVE_COMM_DATA_REG2_BYTE0 : 8;
                unsigned int      SLAVE_COMM_DATA_REG2_BYTE1 : 8;
                unsigned int      SLAVE_COMM_DATA_REG2_BYTE2 : 8;
                unsigned int      SLAVE_COMM_DATA_REG2_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SLAVE_COMM_DATA_REG3__SI__VI {
	struct {
                unsigned int      SLAVE_COMM_DATA_REG3_BYTE0 : 8;
                unsigned int      SLAVE_COMM_DATA_REG3_BYTE1 : 8;
                unsigned int      SLAVE_COMM_DATA_REG3_BYTE2 : 8;
                unsigned int      SLAVE_COMM_DATA_REG3_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SLAVE_HANG_ERROR {
	struct {
                unsigned int                 SRBM_HANG_ERROR : 1;
                unsigned int                  HDP_HANG_ERROR : 1;
                unsigned int                  VGA_HANG_ERROR : 1;
                unsigned int                  ROM_HANG_ERROR : 1;
                unsigned int                AUDIO_HANG_ERROR : 1;
                unsigned int          CEC_HANG_ERROR__CI__VI : 1;
                unsigned int                                 : 1;
                unsigned int         XDMA_HANG_ERROR__CI__VI : 1;
                unsigned int     DOORBELL_HANG_ERROR__CI__VI : 1;
                unsigned int       GARLIC_HANG_ERROR__CI__VI : 1;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SLAVE_HANG_PROTECTION_CNTL {
	struct {
                unsigned int                                 : 1;
                unsigned int       HANG_PROTECTION_TIMER_SEL : 3;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SLAVE_REQ_CREDIT_CNTL {
	struct {
                unsigned int             BIF_SRBM_REQ_CREDIT : 5;
                unsigned int              BIF_VGA_REQ_CREDIT : 4;
                unsigned int                                 : 1;
                unsigned int              BIF_HDP_REQ_CREDIT : 5;
                unsigned int              BIF_ROM_REQ_CREDIT : 1;
                unsigned int                                 : 4;
                unsigned int               BIF_AZ_REQ_CREDIT : 1;
                unsigned int                                 : 4;
                unsigned int         BIF_XDMA_REQ_CREDIT__VI : 6;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMBCLK_PAD_CNTL__CI {
	struct {
		unsigned int                    SMBCLK_PAD_A : 1;
		unsigned int                  SMBCLK_PAD_SEL : 1;
		unsigned int                 SMBCLK_PAD_MODE : 1;
		unsigned int                SMBCLK_PAD_SPARE : 2;
		unsigned int                  SMBCLK_PAD_SN0 : 1;
		unsigned int                  SMBCLK_PAD_SN1 : 1;
		unsigned int                  SMBCLK_PAD_SN2 : 1;
		unsigned int                  SMBCLK_PAD_SN3 : 1;
		unsigned int                SMBCLK_PAD_SLEWN : 1;
		unsigned int                 SMBCLK_PAD_WAKE : 1;
		unsigned int               SMBCLK_PAD_SCHMEN : 1;
		unsigned int              SMBCLK_PAD_CNTL_EN : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMBCLK_PAD_CNTL__VI {
	struct {
		unsigned int                    SMBCLK_PAD_A : 1;
		unsigned int                  SMBCLK_PAD_SEL : 1;
		unsigned int                 SMBCLK_PAD_MODE : 1;
		unsigned int                SMBCLK_PAD_SPARE : 2;
		unsigned int                  SMBCLK_PAD_SN0 : 1;
		unsigned int                  SMBCLK_PAD_SN1 : 1;
		unsigned int                  SMBCLK_PAD_SN2 : 1;
		unsigned int                  SMBCLK_PAD_SN3 : 1;
		unsigned int                 SMBCLK_PAD_SLEW : 1;
		unsigned int                 SMBCLK_PAD_WAKE : 1;
		unsigned int               SMBCLK_PAD_SCHMEN : 1;
		unsigned int              SMBCLK_PAD_CNTL_EN : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMBDAT_PAD_CNTL__CI {
	struct {
		unsigned int                    SMBDAT_PAD_A : 1;
		unsigned int                  SMBDAT_PAD_SEL : 1;
		unsigned int                 SMBDAT_PAD_MODE : 1;
		unsigned int                SMBDAT_PAD_SPARE : 2;
		unsigned int                  SMBDAT_PAD_SN0 : 1;
		unsigned int                  SMBDAT_PAD_SN1 : 1;
		unsigned int                  SMBDAT_PAD_SN2 : 1;
		unsigned int                  SMBDAT_PAD_SN3 : 1;
		unsigned int                SMBDAT_PAD_SLEWN : 1;
		unsigned int                 SMBDAT_PAD_WAKE : 1;
		unsigned int               SMBDAT_PAD_SCHMEN : 1;
		unsigned int              SMBDAT_PAD_CNTL_EN : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMBDAT_PAD_CNTL__VI {
	struct {
		unsigned int                    SMBDAT_PAD_A : 1;
		unsigned int                  SMBDAT_PAD_SEL : 1;
		unsigned int                 SMBDAT_PAD_MODE : 1;
		unsigned int                SMBDAT_PAD_SPARE : 2;
		unsigned int                  SMBDAT_PAD_SN0 : 1;
		unsigned int                  SMBDAT_PAD_SN1 : 1;
		unsigned int                  SMBDAT_PAD_SN2 : 1;
		unsigned int                  SMBDAT_PAD_SN3 : 1;
		unsigned int                 SMBDAT_PAD_SLEW : 1;
		unsigned int                 SMBDAT_PAD_WAKE : 1;
		unsigned int               SMBDAT_PAD_SCHMEN : 1;
		unsigned int              SMBDAT_PAD_CNTL_EN : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMBUS_SLV_CNTL__CI {
	struct {
		unsigned int                  SMB_SOFT_RESET : 1;
		unsigned int                     SMB_SLV_ADR : 7;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_ACCESS_CNTL__SI__CI {
	struct {
                unsigned int            AUTO_INCREMENT_IND_0 : 1;
                unsigned int        AUTO_INCREMENT_IND_1__CI : 1;
                unsigned int        AUTO_INCREMENT_IND_2__CI : 1;
                unsigned int        AUTO_INCREMENT_IND_3__CI : 1;
                unsigned int        AUTO_INCREMENT_IND_4__CI : 1;
                unsigned int        AUTO_INCREMENT_IND_5__CI : 1;
                unsigned int        AUTO_INCREMENT_IND_6__CI : 1;
                unsigned int        AUTO_INCREMENT_IND_7__CI : 1;
                unsigned int        AUTO_INCREMENT_IND_1__SI : 1;
                unsigned int                                 : 7;
                unsigned int        AUTO_INCREMENT_IND_2__SI : 1;
                unsigned int                                 : 7;
                unsigned int        AUTO_INCREMENT_IND_3__SI : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_ACCESS_CNTL__VI {
	struct {
                unsigned int            AUTO_INCREMENT_IND_0 : 1;
                unsigned int            AUTO_INCREMENT_IND_1 : 1;
                unsigned int            AUTO_INCREMENT_IND_2 : 1;
                unsigned int            AUTO_INCREMENT_IND_3 : 1;
                unsigned int            AUTO_INCREMENT_IND_4 : 1;
                unsigned int            AUTO_INCREMENT_IND_5 : 1;
                unsigned int            AUTO_INCREMENT_IND_6 : 1;
                unsigned int            AUTO_INCREMENT_IND_7 : 1;
                unsigned int            AUTO_INCREMENT_IND_8 : 1;
                unsigned int            AUTO_INCREMENT_IND_9 : 1;
                unsigned int           AUTO_INCREMENT_IND_10 : 1;
                unsigned int           AUTO_INCREMENT_IND_11 : 1;
                unsigned int           AUTO_INCREMENT_IND_12 : 1;
                unsigned int           AUTO_INCREMENT_IND_13 : 1;
                unsigned int           AUTO_INCREMENT_IND_14 : 1;
                unsigned int           AUTO_INCREMENT_IND_15 : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_DATA {
	struct {
		unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_DATA_0__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_DATA_1__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_DATA_2__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_DATA_3__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_DATA_4__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_DATA_5__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_DATA_6__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_DATA_7__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_INDEX {
	struct {
		unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_INDEX_0__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_INDEX_1__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_INDEX_2__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_INDEX_3__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_INDEX_4__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_INDEX_5__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_INDEX_6__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_IND_INDEX_7__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_0__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_0__SI {
	struct {
		unsigned int                         SMC_MSG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_10__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_11__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_1__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_1__SI {
	struct {
		unsigned int                         SMC_MSG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_2__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_3__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_4__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_5__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_6__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_7__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_8__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MESSAGE_9__CI__VI {
	struct {
                unsigned int                         SMC_MSG : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_0__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_10__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_11__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_1__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_2__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_3__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_4__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_5__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_6__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_7__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_8__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_MSG_ARG_9__CI__VI {
	struct {
                unsigned int                     SMC_MSG_ARG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_PC_C__CI__VI {
	struct {
                unsigned int                        smc_pc_c : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_PC__SI {
	struct {
		unsigned int                                 : 30;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_0__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_0__SI {
	struct {
		unsigned int                        SMC_RESP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_10__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_11__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_1__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_1__SI {
	struct {
		unsigned int                        SMC_RESP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_2__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_3__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_4__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_5__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_6__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_7__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_8__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_RESP_9__CI__VI {
	struct {
                unsigned int                        SMC_RESP : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_SCRATCH9 {
	struct {
		unsigned int                   SCRATCH_VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_SYSCON_MISC_CNTL__CI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int          dma_no_outstanding__VI : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMC_SYSCON_MSG_ARG_0__CI__VI {
	struct {
                unsigned int                     smc_msg_arg : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_EFUSE_0__CI__VI {
	struct {
                unsigned int                      EFUSE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_MAIN_PLL_OP_FREQ__CI__VI {
	struct {
                unsigned int                     PLL_OP_FREQ : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_SMC_IND_DATA__CI__VI {
	struct {
                unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_SMC_IND_INDEX__CI__VI {
	struct {
                unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SNAPSHOT_V_COUNTER__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_ARB_CYCLES_0 {
	struct {
		unsigned int                    TS0_DURATION : 16;
		unsigned int                    TS1_DURATION : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_ARB_CYCLES_1 {
	struct {
                unsigned int                    TS2_DURATION : 16;
                unsigned int            TS3_DURATION__CI__VI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_ARB_PRIORITY__CI__VI {
	struct {
                unsigned int                  PIPE_ORDER_TS0 : 3;
                unsigned int                  PIPE_ORDER_TS1 : 3;
                unsigned int                  PIPE_ORDER_TS2 : 3;
                unsigned int                  PIPE_ORDER_TS3 : 3;
                unsigned int                    TS0_DUR_MULT : 2;
                unsigned int                    TS1_DUR_MULT : 2;
                unsigned int                    TS2_DUR_MULT : 2;
                unsigned int                    TS3_DUR_MULT : 2;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_ARB_PRIORITY__SI {
	struct {
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 3;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_BARYC_CNTL {
	struct {
		unsigned int               PERSP_CENTER_CNTL : 1;
		unsigned int                                 : 3;
		unsigned int             PERSP_CENTROID_CNTL : 1;
		unsigned int                                 : 3;
		unsigned int              LINEAR_CENTER_CNTL : 1;
		unsigned int                                 : 3;
		unsigned int            LINEAR_CENTROID_CNTL : 1;
		unsigned int                                 : 3;
		unsigned int              POS_FLOAT_LOCATION : 2;
		unsigned int                                 : 2;
		unsigned int                   POS_FLOAT_ULC : 1;
		unsigned int                                 : 3;
		unsigned int             FRONT_FACE_ALL_BITS : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CDBG_SYS_CS0__CI__VI {
	struct {
                unsigned int                           PIPE0 : 8;
                unsigned int                           PIPE1 : 8;
                unsigned int                           PIPE2 : 8;
                unsigned int                           PIPE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CDBG_SYS_CS1__CI__VI {
	struct {
                unsigned int                           PIPE0 : 8;
                unsigned int                           PIPE1 : 8;
                unsigned int                           PIPE2 : 8;
                unsigned int                           PIPE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CDBG_SYS_GFX__CI__VI {
	struct {
                unsigned int                           PS_EN : 1;
                unsigned int                           VS_EN : 1;
                unsigned int                           GS_EN : 1;
                unsigned int                           ES_EN : 1;
                unsigned int                           HS_EN : 1;
                unsigned int                           LS_EN : 1;
                unsigned int                           CS_EN : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CDBG_SYS_HP3D__CI__VI {
	struct {
                unsigned int                           PS_EN : 1;
                unsigned int                           VS_EN : 1;
                unsigned int                           GS_EN : 1;
                unsigned int                           ES_EN : 1;
                unsigned int                           HS_EN : 1;
                unsigned int                           LS_EN : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_COMPUTE_QUEUE_RESET__CI__VI {
	struct {
                unsigned int                           RESET : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CONFIG_CNTL {
	struct {
                unsigned int              GPR_WRITE_PRIORITY : 21;
                unsigned int              EXP_PRIORITY_ORDER : 3;
                unsigned int           ENABLE_SQG_TOP_EVENTS : 1;
                unsigned int           ENABLE_SQG_BOP_EVENTS : 1;
                unsigned int                 RSRC_MGMT_RESET : 1;
                unsigned int        TTRACE_STALL_ALL__CI__VI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CONFIG_CNTL_1 {
	struct {
                unsigned int                  VTX_DONE_DELAY : 4;
                unsigned int         INTERP_ONE_PRIM_PER_ROW : 1;
                unsigned int                                 : 1;
                unsigned int                 PC_LIMIT_ENABLE : 1;
                unsigned int                 PC_LIMIT_STRICT : 1;
                unsigned int       CRC_SIMD_ID_WADDR_DISABLE : 1;
                unsigned int        LBPW_CU_CHK_MODE__CI__VI : 1;
                unsigned int         LBPW_CU_CHK_CNT__CI__VI : 4;
                unsigned int                                 : 2;
                unsigned int                   PC_LIMIT_SIZE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CSQ_WF_ACTIVE_COUNT_0__CI__VI {
	struct {
                unsigned int                           COUNT : 11;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CSQ_WF_ACTIVE_COUNT_1__CI__VI {
	struct {
                unsigned int                           COUNT : 11;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CSQ_WF_ACTIVE_COUNT_2__CI__VI {
	struct {
                unsigned int                           COUNT : 11;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CSQ_WF_ACTIVE_COUNT_3__CI__VI {
	struct {
                unsigned int                           COUNT : 11;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CSQ_WF_ACTIVE_COUNT_4__CI__VI {
	struct {
                unsigned int                           COUNT : 11;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CSQ_WF_ACTIVE_COUNT_5__CI__VI {
	struct {
                unsigned int                           COUNT : 11;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CSQ_WF_ACTIVE_COUNT_6__CI__VI {
	struct {
                unsigned int                           COUNT : 11;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CSQ_WF_ACTIVE_COUNT_7__CI__VI {
	struct {
                unsigned int                           COUNT : 11;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CSQ_WF_ACTIVE_STATUS__CI__VI {
	struct {
                unsigned int                          ACTIVE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_DEBUG_BUSY__CI__VI {
	struct {
                unsigned int                         LS_BUSY : 1;
                unsigned int                         HS_BUSY : 1;
                unsigned int                         ES_BUSY : 1;
                unsigned int                         GS_BUSY : 1;
                unsigned int                         VS_BUSY : 1;
                unsigned int                        PS0_BUSY : 1;
                unsigned int                        PS1_BUSY : 1;
                unsigned int                        CSG_BUSY : 1;
                unsigned int                        CS0_BUSY : 1;
                unsigned int                        CS1_BUSY : 1;
                unsigned int                        CS2_BUSY : 1;
                unsigned int                        CS3_BUSY : 1;
                unsigned int                        CS4_BUSY : 1;
                unsigned int                        CS5_BUSY : 1;
                unsigned int                        CS6_BUSY : 1;
                unsigned int                        CS7_BUSY : 1;
                unsigned int                LDS_WR_CTL0_BUSY : 1;
                unsigned int                LDS_WR_CTL1_BUSY : 1;
                unsigned int                RSRC_ALLOC0_BUSY : 1;
                unsigned int                RSRC_ALLOC1_BUSY : 1;
                unsigned int                 PC_DEALLOC_BUSY : 1;
                unsigned int                EVENT_CLCTR_BUSY : 1;
                unsigned int                       GRBM_BUSY : 1;
                unsigned int                       SPIS_BUSY : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_DEBUG_BUSY__SI {
	struct {
		unsigned int                         LS_BUSY : 1;
		unsigned int                         HS_BUSY : 1;
		unsigned int                         ES_BUSY : 1;
		unsigned int                         GS_BUSY : 1;
		unsigned int                         VS_BUSY : 1;
		unsigned int                        PS0_BUSY : 1;
		unsigned int                        PS1_BUSY : 1;
		unsigned int                        CS0_BUSY : 1;
		unsigned int                        CS1_BUSY : 1;
		unsigned int                        CS2_BUSY : 1;
		unsigned int                LDS_WR_CTL0_BUSY : 1;
		unsigned int                LDS_WR_CTL1_BUSY : 1;
		unsigned int                RSRC_ALLOC0_BUSY : 1;
		unsigned int                RSRC_ALLOC1_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                EVENT_CLCTR_BUSY : 1;
		unsigned int                       GRBM_BUSY : 1;
		unsigned int                       SPIS_BUSY : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_DEBUG_CNTL__CI__VI {
	struct {
                unsigned int             DEBUG_GRBM_OVERRIDE : 1;
                unsigned int           DEBUG_THREAD_TYPE_SEL : 3;
                unsigned int                 DEBUG_GROUP_SEL : 6;
                unsigned int                  DEBUG_SIMD_SEL : 6;
                unsigned int                    DEBUG_SH_SEL : 1;
                unsigned int                 SPI_ECO_SPARE_0 : 1;
                unsigned int                 SPI_ECO_SPARE_1 : 1;
                unsigned int                 SPI_ECO_SPARE_2 : 1;
                unsigned int                 SPI_ECO_SPARE_3 : 1;
                unsigned int                 SPI_ECO_SPARE_4 : 1;
                unsigned int                 SPI_ECO_SPARE_5 : 1;
                unsigned int                 SPI_ECO_SPARE_6 : 1;
                unsigned int                 SPI_ECO_SPARE_7 : 1;
                unsigned int                  DEBUG_PIPE_SEL : 3;
                unsigned int                                 : 3;
                unsigned int                    DEBUG_REG_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_DEBUG_CNTL__SI {
	struct {
		unsigned int             DEBUG_GRBM_OVERRIDE : 1;
		unsigned int           DEBUG_THREAD_TYPE_SEL : 4;
		unsigned int                 DEBUG_GROUP_SEL : 5;
		unsigned int                  DEBUG_SIMD_SEL : 6;
		unsigned int                    DEBUG_SH_SEL : 1;
		unsigned int                 SPI_ECO_SPARE_0 : 1;
		unsigned int                 SPI_ECO_SPARE_1 : 1;
		unsigned int                 SPI_ECO_SPARE_2 : 1;
		unsigned int                 SPI_ECO_SPARE_3 : 1;
		unsigned int                 SPI_ECO_SPARE_4 : 1;
		unsigned int                 SPI_ECO_SPARE_5 : 1;
		unsigned int                 SPI_ECO_SPARE_6 : 1;
		unsigned int                 SPI_ECO_SPARE_7 : 1;
		unsigned int                                 : 6;
		unsigned int                    DEBUG_REG_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_DEBUG_READ {
	struct {
		unsigned int                            DATA : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GDBG_TBA_HI__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GDBG_TBA_LO__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GDBG_TMA_HI__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GDBG_TMA_LO__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GDBG_TRAP_CONFIG__CI__VI {
	struct {
                unsigned int                          ME_SEL : 2;
                unsigned int                        PIPE_SEL : 2;
                unsigned int                       QUEUE_SEL : 3;
                unsigned int                        ME_MATCH : 1;
                unsigned int                      PIPE_MATCH : 1;
                unsigned int                     QUEUE_MATCH : 1;
                unsigned int                                 : 5;
                unsigned int                         TRAP_EN : 1;
                unsigned int                        VMID_SEL : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GDBG_TRAP_DATA0__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GDBG_TRAP_DATA1__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GDBG_TRAP_MASK__CI__VI {
	struct {
                unsigned int                         EXCP_EN : 9;
                unsigned int                         REPLACE : 1;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GDBG_WAVE_CNTL__CI__VI {
	struct {
                unsigned int                        STALL_RA : 1;
                unsigned int                  STALL_VMID__VI : 16;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GDS_CREDITS {
	struct {
		unsigned int                 DS_DATA_CREDITS : 8;
		unsigned int                  DS_CMD_CREDITS : 8;
		unsigned int                          UNUSED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_INTERP_CONTROL_0 {
	struct {
		unsigned int                  FLAT_SHADE_ENA : 1;
		unsigned int                  PNT_SPRITE_ENA : 1;
		unsigned int               PNT_SPRITE_OVRD_X : 3;
		unsigned int               PNT_SPRITE_OVRD_Y : 3;
		unsigned int               PNT_SPRITE_OVRD_Z : 3;
		unsigned int               PNT_SPRITE_OVRD_W : 3;
		unsigned int                PNT_SPRITE_TOP_1 : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_LB_CTR_CTRL {
	struct {
		unsigned int                            LOAD : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_LB_CU_MASK {
	struct {
		unsigned int                         CU_MASK : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_LB_DATA_REG {
	struct {
		unsigned int                        CNT_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_P0_TRAP_SCREEN_GPR_MIN__CI__VI {
	struct {
                unsigned int                        VGPR_MIN : 6;
                unsigned int                        SGPR_MIN : 4;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_P0_TRAP_SCREEN_PSBA_HI__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_P0_TRAP_SCREEN_PSBA_LO__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_P0_TRAP_SCREEN_PSMA_HI__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_P0_TRAP_SCREEN_PSMA_LO__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_P1_TRAP_SCREEN_GPR_MIN__CI__VI {
	struct {
                unsigned int                        VGPR_MIN : 6;
                unsigned int                        SGPR_MIN : 4;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_P1_TRAP_SCREEN_PSBA_HI__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_P1_TRAP_SCREEN_PSBA_LO__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_P1_TRAP_SCREEN_PSMA_HI__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_P1_TRAP_SCREEN_PSMA_LO__CI__VI {
	struct {
                unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER0_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER1_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER1_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER2_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER2_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER3_SELECT {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int               PERF_SEL1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER3_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER4_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER4_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER4_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER5_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER5_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER5_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PERFCOUNTER_BINS {
	struct {
		unsigned int                        BIN0_MIN : 4;
		unsigned int                        BIN0_MAX : 4;
		unsigned int                        BIN1_MIN : 4;
		unsigned int                        BIN1_MAX : 4;
		unsigned int                        BIN2_MIN : 4;
		unsigned int                        BIN2_MAX : 4;
		unsigned int                        BIN3_MIN : 4;
		unsigned int                        BIN3_MAX : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PG_ENABLE_STATIC_CU_MASK {
	struct {
		unsigned int                         CU_MASK : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_ADDR {
	struct {
		unsigned int                PERSP_SAMPLE_ENA : 1;
		unsigned int                PERSP_CENTER_ENA : 1;
		unsigned int              PERSP_CENTROID_ENA : 1;
		unsigned int            PERSP_PULL_MODEL_ENA : 1;
		unsigned int               LINEAR_SAMPLE_ENA : 1;
		unsigned int               LINEAR_CENTER_ENA : 1;
		unsigned int             LINEAR_CENTROID_ENA : 1;
		unsigned int            LINE_STIPPLE_TEX_ENA : 1;
		unsigned int                 POS_X_FLOAT_ENA : 1;
		unsigned int                 POS_Y_FLOAT_ENA : 1;
		unsigned int                 POS_Z_FLOAT_ENA : 1;
		unsigned int                 POS_W_FLOAT_ENA : 1;
		unsigned int                  FRONT_FACE_ENA : 1;
		unsigned int                   ANCILLARY_ENA : 1;
		unsigned int             SAMPLE_COVERAGE_ENA : 1;
		unsigned int                POS_FIXED_PT_ENA : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_0 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_1 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_10 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_11 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_12 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_13 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_14 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_15 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_16 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_17 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_18 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_19 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_2 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_20 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_21 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_22 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_23 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_24 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_25 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_26 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_27 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_28 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_29 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_3 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_30 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_31 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 7;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int                                 : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_4 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_5 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_6 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_7 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_8 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_CNTL_9 {
	struct {
                unsigned int                          OFFSET : 6;
                unsigned int                                 : 2;
                unsigned int                     DEFAULT_VAL : 2;
                unsigned int                      FLAT_SHADE : 1;
                unsigned int                                 : 2;
                unsigned int                        CYL_WRAP : 4;
                unsigned int                   PT_SPRITE_TEX : 1;
                unsigned int                     DUP__CI__VI : 1;
                unsigned int            FP16_INTERP_MODE__VI : 1;
                unsigned int           USE_DEFAULT_ATTR1__VI : 1;
                unsigned int           DEFAULT_VAL_ATTR1__VI : 2;
                unsigned int         PT_SPRITE_TEX_ATTR1__VI : 1;
                unsigned int                 ATTR0_VALID__VI : 1;
                unsigned int                 ATTR1_VALID__VI : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_INPUT_ENA {
	struct {
		unsigned int                PERSP_SAMPLE_ENA : 1;
		unsigned int                PERSP_CENTER_ENA : 1;
		unsigned int              PERSP_CENTROID_ENA : 1;
		unsigned int            PERSP_PULL_MODEL_ENA : 1;
		unsigned int               LINEAR_SAMPLE_ENA : 1;
		unsigned int               LINEAR_CENTER_ENA : 1;
		unsigned int             LINEAR_CENTROID_ENA : 1;
		unsigned int            LINE_STIPPLE_TEX_ENA : 1;
		unsigned int                 POS_X_FLOAT_ENA : 1;
		unsigned int                 POS_Y_FLOAT_ENA : 1;
		unsigned int                 POS_Z_FLOAT_ENA : 1;
		unsigned int                 POS_W_FLOAT_ENA : 1;
		unsigned int                  FRONT_FACE_ENA : 1;
		unsigned int                   ANCILLARY_ENA : 1;
		unsigned int             SAMPLE_COVERAGE_ENA : 1;
		unsigned int                POS_FIXED_PT_ENA : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_IN_CONTROL {
	struct {
                unsigned int                      NUM_INTERP : 6;
                unsigned int                       PARAM_GEN : 1;
                unsigned int                                 : 7;
                unsigned int             BC_OPTIMIZE_DISABLE : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_PS_MAX_WAVE_ID {
	struct {
		unsigned int                     MAX_WAVE_ID : 12;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESET_DEBUG__CI__VI {
	struct {
                unsigned int               DISABLE_GFX_RESET : 1;
                unsigned int      DISABLE_GFX_RESET_PER_VMID : 1;
                unsigned int      DISABLE_GFX_RESET_ALL_VMID : 1;
                unsigned int      DISABLE_GFX_RESET_RESOURCE : 1;
                unsigned int      DISABLE_GFX_RESET_PRIORITY : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_0__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_10__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_11__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_1__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_2__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_3__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_4__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_5__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_6__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_7__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_8__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_9__CI__VI {
	struct {
                unsigned int                            VGPR : 4;
                unsigned int                            SGPR : 4;
                unsigned int                             LDS : 4;
                unsigned int                           WAVES : 3;
                unsigned int                        BARRIERS : 4;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_0__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_10__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_11__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_1__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_2__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_3__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_4__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_5__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_6__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_7__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_8__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_9__CI__VI {
	struct {
                unsigned int                              EN : 1;
                unsigned int                       TYPE_MASK : 15;
                unsigned int                      QUEUE_MASK : 8;
                unsigned int              RESERVE_SPACE_ONLY : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_COL_FORMAT {
	struct {
		unsigned int              COL0_EXPORT_FORMAT : 4;
		unsigned int              COL1_EXPORT_FORMAT : 4;
		unsigned int              COL2_EXPORT_FORMAT : 4;
		unsigned int              COL3_EXPORT_FORMAT : 4;
		unsigned int              COL4_EXPORT_FORMAT : 4;
		unsigned int              COL5_EXPORT_FORMAT : 4;
		unsigned int              COL6_EXPORT_FORMAT : 4;
		unsigned int              COL7_EXPORT_FORMAT : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_LATE_ALLOC_VS__CI__VI {
	struct {
                unsigned int                           LIMIT : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_HI_ES {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_HI_GS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_HI_HS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_HI_LS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_HI_PS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_HI_VS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_LO_ES {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_LO_GS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_LO_HS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_LO_LS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_LO_PS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_LO_VS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC1_ES {
	struct {
                unsigned int                           VGPRS : 6;
                unsigned int                           SGPRS : 4;
                unsigned int                        PRIORITY : 2;
                unsigned int                      FLOAT_MODE : 8;
                unsigned int                            PRIV : 1;
                unsigned int                      DX10_CLAMP : 1;
                unsigned int                      DEBUG_MODE : 1;
                unsigned int                       IEEE_MODE : 1;
                unsigned int                   VGPR_COMP_CNT : 2;
                unsigned int                 CU_GROUP_ENABLE : 1;
                unsigned int               CACHE_CTL__CI__VI : 3;
                unsigned int               CDBG_USER__CI__VI : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC1_GS {
	struct {
                unsigned int                           VGPRS : 6;
                unsigned int                           SGPRS : 4;
                unsigned int                        PRIORITY : 2;
                unsigned int                      FLOAT_MODE : 8;
                unsigned int                            PRIV : 1;
                unsigned int                      DX10_CLAMP : 1;
                unsigned int                      DEBUG_MODE : 1;
                unsigned int                       IEEE_MODE : 1;
                unsigned int                 CU_GROUP_ENABLE : 1;
                unsigned int               CACHE_CTL__CI__VI : 3;
                unsigned int               CDBG_USER__CI__VI : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC1_HS {
	struct {
                unsigned int                           VGPRS : 6;
                unsigned int                           SGPRS : 4;
                unsigned int                        PRIORITY : 2;
                unsigned int                      FLOAT_MODE : 8;
                unsigned int                            PRIV : 1;
                unsigned int                      DX10_CLAMP : 1;
                unsigned int                      DEBUG_MODE : 1;
                unsigned int                       IEEE_MODE : 1;
                unsigned int               CACHE_CTL__CI__VI : 3;
                unsigned int               CDBG_USER__CI__VI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC1_LS {
	struct {
                unsigned int                           VGPRS : 6;
                unsigned int                           SGPRS : 4;
                unsigned int                        PRIORITY : 2;
                unsigned int                      FLOAT_MODE : 8;
                unsigned int                            PRIV : 1;
                unsigned int                      DX10_CLAMP : 1;
                unsigned int                      DEBUG_MODE : 1;
                unsigned int                       IEEE_MODE : 1;
                unsigned int                   VGPR_COMP_CNT : 2;
                unsigned int               CACHE_CTL__CI__VI : 3;
                unsigned int               CDBG_USER__CI__VI : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC1_PS {
	struct {
                unsigned int                           VGPRS : 6;
                unsigned int                           SGPRS : 4;
                unsigned int                        PRIORITY : 2;
                unsigned int                      FLOAT_MODE : 8;
                unsigned int                            PRIV : 1;
                unsigned int                      DX10_CLAMP : 1;
                unsigned int                      DEBUG_MODE : 1;
                unsigned int                       IEEE_MODE : 1;
                unsigned int                CU_GROUP_DISABLE : 1;
                unsigned int               CACHE_CTL__CI__VI : 3;
                unsigned int               CDBG_USER__CI__VI : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC1_VS {
	struct {
                unsigned int                           VGPRS : 6;
                unsigned int                           SGPRS : 4;
                unsigned int                        PRIORITY : 2;
                unsigned int                      FLOAT_MODE : 8;
                unsigned int                            PRIV : 1;
                unsigned int                      DX10_CLAMP : 1;
                unsigned int                      DEBUG_MODE : 1;
                unsigned int                       IEEE_MODE : 1;
                unsigned int                   VGPR_COMP_CNT : 2;
                unsigned int                 CU_GROUP_ENABLE : 1;
                unsigned int               CACHE_CTL__CI__VI : 3;
                unsigned int               CDBG_USER__CI__VI : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_ES {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                       OC_LDS_EN : 1;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 3;
                unsigned int                LDS_SIZE__CI__VI : 9;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_ES_GS__CI__VI {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                       OC_LDS_EN : 1;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 3;
                unsigned int                        LDS_SIZE : 9;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_ES_VS__CI__VI {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                       OC_LDS_EN : 1;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 3;
                unsigned int                        LDS_SIZE : 9;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_GS {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_HS {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                       OC_LDS_EN : 1;
                unsigned int                      TG_SIZE_EN : 1;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_LS {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                        LDS_SIZE : 9;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_LS_ES__CI__VI {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                        LDS_SIZE : 9;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_LS_HS__CI__VI {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                        LDS_SIZE : 9;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_LS_VS__CI__VI {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                        LDS_SIZE : 9;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_PS {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                     WAVE_CNT_EN : 1;
                unsigned int                  EXTRA_LDS_SIZE : 8;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC2_VS {
	struct {
                unsigned int                      SCRATCH_EN : 1;
                unsigned int                       USER_SGPR : 5;
                unsigned int                    TRAP_PRESENT : 1;
                unsigned int                       OC_LDS_EN : 1;
                unsigned int                     SO_BASE0_EN : 1;
                unsigned int                     SO_BASE1_EN : 1;
                unsigned int                     SO_BASE2_EN : 1;
                unsigned int                     SO_BASE3_EN : 1;
                unsigned int                           SO_EN : 1;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 2;
                unsigned int            DISPATCH_DRAW_EN__VI : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC3_ES__CI__VI {
	struct {
                unsigned int                           CU_EN : 16;
                unsigned int                      WAVE_LIMIT : 6;
                unsigned int              LOCK_LOW_THRESHOLD : 4;
                unsigned int            GROUP_FIFO_DEPTH__VI : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC3_GS__CI__VI {
	struct {
                unsigned int                           CU_EN : 16;
                unsigned int                      WAVE_LIMIT : 6;
                unsigned int              LOCK_LOW_THRESHOLD : 4;
                unsigned int            GROUP_FIFO_DEPTH__VI : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC3_HS__CI__VI {
	struct {
                unsigned int                      WAVE_LIMIT : 6;
                unsigned int              LOCK_LOW_THRESHOLD : 4;
                unsigned int            GROUP_FIFO_DEPTH__VI : 6;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC3_LS__CI__VI {
	struct {
                unsigned int                           CU_EN : 16;
                unsigned int                      WAVE_LIMIT : 6;
                unsigned int              LOCK_LOW_THRESHOLD : 4;
                unsigned int            GROUP_FIFO_DEPTH__VI : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC3_PS__CI__VI {
	struct {
                unsigned int                           CU_EN : 16;
                unsigned int                      WAVE_LIMIT : 6;
                unsigned int              LOCK_LOW_THRESHOLD : 4;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_PGM_RSRC3_VS__CI__VI {
	struct {
                unsigned int                           CU_EN : 16;
                unsigned int                      WAVE_LIMIT : 6;
                unsigned int              LOCK_LOW_THRESHOLD : 4;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_POS_FORMAT {
	struct {
		unsigned int              POS0_EXPORT_FORMAT : 4;
		unsigned int              POS1_EXPORT_FORMAT : 4;
		unsigned int              POS2_EXPORT_FORMAT : 4;
		unsigned int              POS3_EXPORT_FORMAT : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_HI_ES {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_HI_GS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_HI_HS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_HI_LS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_HI_PS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_HI_VS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_LO_ES {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_LO_GS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_LO_HS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_LO_LS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_LO_PS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TBA_LO_VS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_HI_ES {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_HI_GS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_HI_HS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_HI_LS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_HI_PS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_HI_VS {
	struct {
		unsigned int                        MEM_BASE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_LO_ES {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_LO_GS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_LO_HS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_LO_LS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_LO_PS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_TMA_LO_VS {
	struct {
		unsigned int                        MEM_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_10 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_11 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_12 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_13 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_14 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_15 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_3 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_4 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_5 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_6 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_7 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_8 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_ES_9 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_10 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_11 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_12 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_13 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_14 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_15 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_3 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_4 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_5 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_6 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_7 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_8 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_GS_9 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_10 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_11 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_12 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_13 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_14 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_15 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_3 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_4 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_5 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_6 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_7 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_8 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_HS_9 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_10 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_11 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_12 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_13 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_14 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_15 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_3 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_4 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_5 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_6 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_7 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_8 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_LS_9 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_10 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_11 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_12 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_13 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_14 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_15 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_3 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_4 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_5 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_6 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_7 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_8 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_PS_9 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_10 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_11 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_12 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_13 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_14 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_15 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_3 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_4 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_5 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_6 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_7 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_8 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_USER_DATA_VS_9 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SHADER_Z_FORMAT {
	struct {
		unsigned int                 Z_EXPORT_FORMAT : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SLAVE_DEBUG_BUSY {
	struct {
                unsigned int                     LS_VTX_BUSY : 1;
                unsigned int                     HS_VTX_BUSY : 1;
                unsigned int                     ES_VTX_BUSY : 1;
                unsigned int                     GS_VTX_BUSY : 1;
                unsigned int                     VS_VTX_BUSY : 1;
                unsigned int                  VGPR_WC00_BUSY : 1;
                unsigned int                  VGPR_WC01_BUSY : 1;
                unsigned int                  VGPR_WC10_BUSY : 1;
                unsigned int                  VGPR_WC11_BUSY : 1;
                unsigned int                  SGPR_WC00_BUSY : 1;
                unsigned int                  SGPR_WC01_BUSY : 1;
                unsigned int                  SGPR_WC02_BUSY : 1;
                unsigned int                  SGPR_WC03_BUSY : 1;
                unsigned int                  SGPR_WC10_BUSY : 1;
                unsigned int                  SGPR_WC11_BUSY : 1;
                unsigned int                  SGPR_WC12_BUSY : 1;
                unsigned int                  SGPR_WC13_BUSY : 1;
                unsigned int                WAVEBUFFER0_BUSY : 1;
                unsigned int                WAVEBUFFER1_BUSY : 1;
                unsigned int                   WAVE_WC0_BUSY : 1;
                unsigned int                   WAVE_WC1_BUSY : 1;
                unsigned int                 EVENT_CNTL_BUSY : 1;
                unsigned int               SAVE_CTX_BUSY__VI : 1;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_STATIC_THREAD_MGMT_1__SI {
	struct {
		unsigned int                                 : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_STATIC_THREAD_MGMT_2__SI {
	struct {
		unsigned int                                 : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_STATIC_THREAD_MGMT_3__SI {
	struct {
		unsigned int                      LSHS_CU_EN : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SX_EXPORT_BUFFER_SIZES {
	struct {
		unsigned int               COLOR_BUFFER_SIZE : 16;
		unsigned int            POSITION_BUFFER_SIZE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_SX_SCOREBOARD_BUFFER_SIZES {
	struct {
		unsigned int           COLOR_SCOREBOARD_SIZE : 16;
		unsigned int        POSITION_SCOREBOARD_SIZE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_TMPRING_SIZE {
	struct {
		unsigned int                           WAVES : 12;
		unsigned int                        WAVESIZE : 13;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_VS_OUT_CONFIG {
	struct {
                unsigned int                                 : 1;
                unsigned int                 VS_EXPORT_COUNT : 5;
                unsigned int                    VS_HALF_PACK : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WCL_PIPE_PERCENT_CS0__CI__VI {
	struct {
                unsigned int                           VALUE : 7;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WCL_PIPE_PERCENT_CS1__CI__VI {
	struct {
                unsigned int                           VALUE : 7;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WCL_PIPE_PERCENT_CS2__CI__VI {
	struct {
                unsigned int                           VALUE : 7;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WCL_PIPE_PERCENT_CS3__CI__VI {
	struct {
                unsigned int                           VALUE : 7;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WCL_PIPE_PERCENT_CS4__CI__VI {
	struct {
                unsigned int                           VALUE : 7;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WCL_PIPE_PERCENT_CS5__CI__VI {
	struct {
                unsigned int                           VALUE : 7;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WCL_PIPE_PERCENT_CS6__CI__VI {
	struct {
                unsigned int                           VALUE : 7;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WCL_PIPE_PERCENT_CS7__CI__VI {
	struct {
                unsigned int                           VALUE : 7;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WCL_PIPE_PERCENT_GFX__CI__VI {
	struct {
                unsigned int                           VALUE : 7;
                unsigned int                LS_GRP_VALUE__VI : 5;
                unsigned int                HS_GRP_VALUE__VI : 5;
                unsigned int                ES_GRP_VALUE__VI : 5;
                unsigned int                GS_GRP_VALUE__VI : 5;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WCL_PIPE_PERCENT_HP3D__CI__VI {
	struct {
                unsigned int                           VALUE : 7;
                unsigned int                LS_GRP_VALUE__VI : 5;
                unsigned int                HS_GRP_VALUE__VI : 5;
                unsigned int                ES_GRP_VALUE__VI : 5;
                unsigned int                GS_GRP_VALUE__VI : 5;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_CNTL__CI__VI {
	struct {
                unsigned int                   SAMPLE_PERIOD : 4;
                unsigned int                              EN : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_DEBUG__CI__VI {
	struct {
                unsigned int                     START_VALUE : 31;
                unsigned int                     OVERRIDE_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_LIMIT_0__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                         EN_WARN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_LIMIT_1__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                         EN_WARN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_LIMIT_2__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                         EN_WARN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_LIMIT_3__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                         EN_WARN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_LIMIT_4__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                         EN_WARN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_LIMIT_5__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                         EN_WARN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_LIMIT_6__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                         EN_WARN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_LIMIT_7__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                         EN_WARN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_LIMIT_8__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                         EN_WARN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_LIMIT_9__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                         EN_WARN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_0__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_10__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_11__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_12__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_13__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_14__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_15__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_16__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_17__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_18__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_19__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_1__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_20__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_2__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_3__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_4__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_5__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_6__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_7__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_8__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_WF_LIFETIME_STATUS_9__CI__VI {
	struct {
                unsigned int                         MAX_CNT : 31;
                unsigned int                        INT_SENT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPLL_CNTL_MODE__CI__VI {
	struct {
                unsigned int             SPLL_SW_DIR_CONTROL : 1;
                unsigned int                SPLL_LEGACY_PDIV : 1;
                unsigned int                       SPLL_TEST : 1;
                unsigned int                     SPLL_FASTEN : 1;
                unsigned int                      SPLL_ENSAT : 1;
                unsigned int                                 : 5;
                unsigned int           SPLL_TEST_CLK_EXT_DIV : 2;
                unsigned int             SPLL_CTLREQ_DLY_CNT : 8;
                unsigned int                                 : 8;
                unsigned int                   SPLL_RESET_EN : 1;
                unsigned int                   SPLL_VCO_MODE : 2;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPLL_CNTL_MODE__SI {
	struct {
		unsigned int             SPLL_SW_DIR_CONTROL : 1;
		unsigned int                SPLL_LEGACY_PDIV : 1;
		unsigned int                       SPLL_TEST : 1;
		unsigned int                     SPLL_FASTEN : 1;
		unsigned int                      SPLL_ENSAT : 1;
		unsigned int                                 : 5;
		unsigned int           SPLL_TEST_CLK_EXT_DIV : 2;
		unsigned int             SPLL_CTLREQ_DLY_CNT : 8;
		unsigned int                                 : 6;
		unsigned int                                 : 2;
		unsigned int                   SPLL_RESET_EN : 1;
		unsigned int                   SPLL_VCO_MODE : 2;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_C6_STATE_0__CI__VI {
	struct {
                unsigned int        SPMI_IF_C6_STATE_ENTERED : 1;
                unsigned int SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY : 1;
                unsigned int      SPMI_IF_COUNTER_ADDRESS_C6 : 15;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_C6_STATE_1__CI {
	struct {
		unsigned int        SPMI_IF_C6_STATE_ENTERED : 1;
		unsigned int SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY : 1;
		unsigned int      SPMI_IF_COUNTER_ADDRESS_C6 : 15;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_FSM_BUSY_0__CI__VI {
	struct {
                unsigned int                        FSM_BUSY : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_FSM_BUSY_1__CI {
	struct {
		unsigned int                        FSM_BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_FSM_READ_TRIGGER_0__CI__VI {
	struct {
                unsigned int                FSM_READ_TRIGGER : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_FSM_READ_TRIGGER_1__CI {
	struct {
		unsigned int                FSM_READ_TRIGGER : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_FSM_RESET_TRIGGER_0__CI__VI {
	struct {
                unsigned int               FSM_RESET_TRIGGER : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_FSM_RESET_TRIGGER_1__CI {
	struct {
		unsigned int               FSM_RESET_TRIGGER : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_FSM_WRITE_TRIGGER_0__CI__VI {
	struct {
                unsigned int               FSM_WRITE_TRIGGER : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_FSM_WRITE_TRIGGER_1__CI {
	struct {
		unsigned int               FSM_WRITE_TRIGGER : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_JTAG_OVER_0__CI__VI {
	struct {
                unsigned int      SPMI_IF_JTAG_OVER_HAPPENED : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_JTAG_OVER_1__CI {
	struct {
		unsigned int      SPMI_IF_JTAG_OVER_HAPPENED : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_PATH_0__CI__VI {
	struct {
                unsigned int                 PATH_ENABLE_REQ : 1;
                unsigned int                 PATH_ENABLE_ACK : 1;
                unsigned int                                 : 2;
                unsigned int      PATH_ENABLE_REQ_auto_clear : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_PATH_1__CI {
	struct {
		unsigned int                 PATH_ENABLE_REQ : 1;
		unsigned int                 PATH_ENABLE_ACK : 1;
		unsigned int                                 : 2;
		unsigned int      PATH_ENABLE_REQ_auto_clear : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_RESET__CI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_RESET__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 30;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_SRAM_ADDRESS__CI__VI {
	struct {
                unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_SRAM_DATA__CI__VI {
	struct {
                unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_CACHES__SI__CI {
	struct {
                unsigned int                 INST_INVALIDATE : 1;
                unsigned int                 DATA_INVALIDATE : 1;
                unsigned int         INVALIDATE_VOLATILE__CI : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_CACHES__VI {
	struct {
		unsigned int                     TARGET_INST : 1;
		unsigned int                     TARGET_DATA : 1;
		unsigned int                      INVALIDATE : 1;
		unsigned int                       WRITEBACK : 1;
		unsigned int                             VOL : 1;
		unsigned int                                 : 11;
		unsigned int                        COMPLETE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_CONFIG {
	struct {
                unsigned int                 INST_CACHE_SIZE : 2;
                unsigned int                 DATA_CACHE_SIZE : 2;
                unsigned int                 MISS_FIFO_DEPTH : 2;
                unsigned int                  HIT_FIFO_DEPTH : 1;
                unsigned int               FORCE_ALWAYS_MISS : 1;
                unsigned int                  FORCE_IN_ORDER : 1;
                unsigned int              IDENTITY_HASH_BANK : 1;
                unsigned int               IDENTITY_HASH_SET : 1;
                unsigned int    PER_VMID_INV_DISABLE__CI__VI : 1;
                unsigned int                   EVICT_LRU__VI : 2;
                unsigned int                FORCE_2_BANK__VI : 1;
                unsigned int                FORCE_1_BANK__VI : 1;
                unsigned int           LS_DISABLE_CLOCKS__VI : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_POLICY__CI {
	struct {
		unsigned int                DATA_L1_POLICY_0 : 1;
		unsigned int                DATA_L1_POLICY_1 : 1;
		unsigned int                DATA_L1_POLICY_2 : 1;
		unsigned int                DATA_L1_POLICY_3 : 1;
		unsigned int                DATA_L1_POLICY_4 : 1;
		unsigned int                DATA_L1_POLICY_5 : 1;
		unsigned int                DATA_L1_POLICY_6 : 1;
		unsigned int                DATA_L1_POLICY_7 : 1;
		unsigned int                DATA_L2_POLICY_0 : 2;
		unsigned int                DATA_L2_POLICY_1 : 2;
		unsigned int                DATA_L2_POLICY_2 : 2;
		unsigned int                DATA_L2_POLICY_3 : 2;
		unsigned int                DATA_L2_POLICY_4 : 2;
		unsigned int                DATA_L2_POLICY_5 : 2;
		unsigned int                DATA_L2_POLICY_6 : 2;
		unsigned int                DATA_L2_POLICY_7 : 2;
		unsigned int                  INST_L2_POLICY : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_SECDED_CNT__SI__CI {
	struct {
		unsigned int                        INST_SEC : 8;
		unsigned int                        INST_DED : 8;
		unsigned int                        DATA_SEC : 8;
		unsigned int                        DATA_DED : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_VOLATILE__CI {
	struct {
		unsigned int                         DATA_L1 : 4;
		unsigned int                         DATA_L2 : 4;
		unsigned int                         INST_L2 : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_ALU_CLK_CTRL {
	struct {
		unsigned int                 FORCE_CU_ON_SH0 : 16;
		unsigned int                 FORCE_CU_ON_SH1 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_BUF_RSRC_WORD0 {
	struct {
		unsigned int                    BASE_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_BUF_RSRC_WORD1 {
	struct {
		unsigned int                 BASE_ADDRESS_HI : 16;
		unsigned int                          STRIDE : 14;
		unsigned int                   CACHE_SWIZZLE : 1;
		unsigned int                  SWIZZLE_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_BUF_RSRC_WORD2 {
	struct {
		unsigned int                     NUM_RECORDS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_BUF_RSRC_WORD3 {
	struct {
                unsigned int                       DST_SEL_X : 3;
                unsigned int                       DST_SEL_Y : 3;
                unsigned int                       DST_SEL_Z : 3;
                unsigned int                       DST_SEL_W : 3;
                unsigned int                      NUM_FORMAT : 3;
                unsigned int                     DATA_FORMAT : 4;
                unsigned int                    ELEMENT_SIZE : 2;
                unsigned int                    INDEX_STRIDE : 2;
                unsigned int                  ADD_TID_ENABLE : 1;
                unsigned int                     ATC__CI__VI : 1;
                unsigned int                     HASH_ENABLE : 1;
                unsigned int                            HEAP : 1;
                unsigned int                   MTYPE__CI__VI : 3;
                unsigned int                            TYPE : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_CMD_TIMESTAMP__CI__VI {
	struct {
                unsigned int                       TIMESTAMP : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_CMD__CI {
	struct {
		unsigned int                             CMD : 3;
		unsigned int                                 : 1;
		unsigned int                            MODE : 3;
		unsigned int                      CHECK_VMID : 1;
		unsigned int                         TRAP_ID : 3;
		unsigned int                                 : 5;
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                                 : 2;
		unsigned int                        QUEUE_ID : 3;
		unsigned int                                 : 1;
		unsigned int                           VM_ID : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_CMD__VI {
	struct {
		unsigned int                             CMD : 3;
		unsigned int                                 : 1;
		unsigned int                            MODE : 3;
		unsigned int                      CHECK_VMID : 1;
		unsigned int                            DATA : 3;
		unsigned int                                 : 5;
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                                 : 2;
		unsigned int                        QUEUE_ID : 3;
		unsigned int                                 : 1;
		unsigned int                           VM_ID : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_CONFIG__SI__CI {
	struct {
                unsigned int                          UNUSED : 8;
                unsigned int                        DEBUG_EN : 1;
                unsigned int              DISABLE_SCA_BYPASS : 1;
                unsigned int            DISABLE_IB_DEP_CHECK : 1;
                unsigned int          ENABLE_SOFT_CLAUSE__CI : 1;
                unsigned int       EARLY_TA_DONE_DISABLE__CI : 1;
                unsigned int        DUA_FLAT_LOCK_ENABLE__CI : 1;
                unsigned int      DUA_LDS_BYPASS_DISABLE__CI : 1;
                unsigned int DUA_FLAT_LDS_PINGPONG_DISABLE__CI : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_CONFIG__VI {
	struct {
		unsigned int                          UNUSED : 8;
		unsigned int                        DEBUG_EN : 1;
		unsigned int              DEBUG_SINGLE_MEMOP : 1;
		unsigned int           DEBUG_ONE_INST_CLAUSE : 1;
		unsigned int                                 : 1;
		unsigned int           EARLY_TA_DONE_DISABLE : 1;
		unsigned int            DUA_FLAT_LOCK_ENABLE : 1;
		unsigned int          DUA_LDS_BYPASS_DISABLE : 1;
		unsigned int   DUA_FLAT_LDS_PINGPONG_DISABLE : 1;
		unsigned int        DISABLE_VMEM_SOFT_CLAUSE : 1;
		unsigned int        DISABLE_SMEM_SOFT_CLAUSE : 1;
		unsigned int     ENABLE_HIPRIO_ON_EXP_RDY_VS : 1;
		unsigned int          PRIO_VAL_ON_EXP_RDY_VS : 2;
		unsigned int                REPLAY_SLEEP_CNT : 4;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DEBUG_CTRL_LOCAL {
	struct {
		unsigned int                          UNUSED : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DEBUG_STS_GLOBAL {
	struct {
                unsigned int                            BUSY : 1;
                unsigned int      INTERRUPT_MSG_BUSY__CI__VI : 1;
                unsigned int                                 : 2;
                unsigned int                  WAVE_LEVEL_SH0 : 12;
                unsigned int                  WAVE_LEVEL_SH1 : 12;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DEBUG_STS_GLOBAL2__CI__VI {
	struct {
                unsigned int                 FIFO_LEVEL_GFX0 : 8;
                unsigned int                 FIFO_LEVEL_GFX1 : 8;
                unsigned int                FIFO_LEVEL_IMMED : 8;
                unsigned int                 FIFO_LEVEL_HOST : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DEBUG_STS_GLOBAL3__CI__VI {
	struct {
                unsigned int             FIFO_LEVEL_HOST_CMD : 4;
                unsigned int             FIFO_LEVEL_HOST_REG : 6;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DEBUG_STS_LOCAL {
	struct {
		unsigned int                            BUSY : 1;
		unsigned int                                 : 3;
		unsigned int                      WAVE_LEVEL : 6;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DED_CNT__SI__CI {
	struct {
		unsigned int                         LDS_DED : 6;
		unsigned int                                 : 2;
		unsigned int                        SGPR_DED : 5;
		unsigned int                                 : 3;
		unsigned int                        VGPR_DED : 9;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DED_INFO__SI__CI {
	struct {
                unsigned int                         WAVE_ID : 4;
                unsigned int                         SIMD_ID : 2;
                unsigned int                          SOURCE : 3;
                unsigned int                           VM_ID : 4;
                unsigned int                                 : 3;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DS_0__SI__CI {
	struct {
		unsigned int                         OFFSET0 : 8;
		unsigned int                         OFFSET1 : 8;
		unsigned int                                 : 1;
		unsigned int                             GDS : 1;
		unsigned int                              OP : 8;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DS_0__VI {
	struct {
		unsigned int                         OFFSET0 : 8;
		unsigned int                         OFFSET1 : 8;
		unsigned int                             GDS : 1;
		unsigned int                              OP : 8;
		unsigned int                                 : 1;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DS_1 {
	struct {
		unsigned int                            ADDR : 8;
		unsigned int                           DATA0 : 8;
		unsigned int                           DATA1 : 8;
		unsigned int                            VDST : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_EXP_0 {
	struct {
		unsigned int                              EN : 4;
		unsigned int                             TGT : 6;
		unsigned int                           COMPR : 1;
		unsigned int                            DONE : 1;
		unsigned int                              VM : 1;
		unsigned int                                 : 13;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_EXP_1 {
	struct {
		unsigned int                           VSRC0 : 8;
		unsigned int                           VSRC1 : 8;
		unsigned int                           VSRC2 : 8;
		unsigned int                           VSRC3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_FIFO_SIZES {
	struct {
		unsigned int             INTERRUPT_FIFO_SIZE : 4;
		unsigned int                                 : 4;
		unsigned int                TTRACE_FIFO_SIZE : 4;
		unsigned int                                 : 4;
		unsigned int                 EXPORT_BUF_SIZE : 2;
		unsigned int             VMEM_DATA_FIFO_SIZE : 2;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_FLAT_0__CI__VI {
	struct {
                unsigned int                                 : 16;
                unsigned int                             GLC : 1;
                unsigned int                             SLC : 1;
                unsigned int                              OP : 7;
                unsigned int                                 : 1;
                unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_FLAT_1__CI__VI {
	struct {
                unsigned int                            ADDR : 8;
                unsigned int                            DATA : 8;
                unsigned int                                 : 7;
                unsigned int                             TFE : 1;
                unsigned int                            VDST : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_FLAT_SCRATCH_WORD0__CI__VI {
	struct {
                unsigned int                            SIZE : 19;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_FLAT_SCRATCH_WORD1__CI__VI {
	struct {
                unsigned int                          OFFSET : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_HV_VMID_CTRL__CI__VI {
	struct {
                unsigned int                    DEFAULT_VMID : 4;
                unsigned int               ALLOWED_VMID_MASK : 16;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_RSRC_WORD0 {
	struct {
		unsigned int                    BASE_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_RSRC_WORD1 {
	struct {
                unsigned int                 BASE_ADDRESS_HI : 8;
                unsigned int                         MIN_LOD : 12;
                unsigned int                     DATA_FORMAT : 6;
                unsigned int                      NUM_FORMAT : 4;
                unsigned int                   MTYPE__CI__VI : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_RSRC_WORD2 {
	struct {
		unsigned int                           WIDTH : 14;
		unsigned int                          HEIGHT : 14;
		unsigned int                        PERF_MOD : 3;
		unsigned int                      INTERLACED : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_RSRC_WORD3 {
	struct {
                unsigned int                       DST_SEL_X : 3;
                unsigned int                       DST_SEL_Y : 3;
                unsigned int                       DST_SEL_Z : 3;
                unsigned int                       DST_SEL_W : 3;
                unsigned int                      BASE_LEVEL : 4;
                unsigned int                      LAST_LEVEL : 4;
                unsigned int                    TILING_INDEX : 5;
                unsigned int                        POW2_PAD : 1;
                unsigned int                   MTYPE__CI__VI : 1;
                unsigned int                     ATC__CI__VI : 1;
                unsigned int                            TYPE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_RSRC_WORD4 {
	struct {
		unsigned int                           DEPTH : 13;
		unsigned int                           PITCH : 14;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_RSRC_WORD5 {
	struct {
		unsigned int                      BASE_ARRAY : 13;
		unsigned int                      LAST_ARRAY : 13;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_RSRC_WORD6 {
	struct {
                unsigned int                    MIN_LOD_WARN : 12;
                unsigned int         COUNTER_BANK_ID__CI__VI : 8;
                unsigned int          LOD_HDW_CNT_EN__CI__VI : 1;
                unsigned int              COMPRESSION_EN__VI : 1;
                unsigned int             ALPHA_IS_ON_MSB__VI : 1;
                unsigned int             COLOR_TRANSFORM__VI : 1;
                unsigned int             LOST_ALPHA_BITS__VI : 4;
                unsigned int             LOST_COLOR_BITS__VI : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_RSRC_WORD7 {
	struct {
                unsigned int           META_DATA_ADDRESS__VI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_SAMP_WORD0 {
	struct {
                unsigned int                         CLAMP_X : 3;
                unsigned int                         CLAMP_Y : 3;
                unsigned int                         CLAMP_Z : 3;
                unsigned int                 MAX_ANISO_RATIO : 3;
                unsigned int              DEPTH_COMPARE_FUNC : 3;
                unsigned int              FORCE_UNNORMALIZED : 1;
                unsigned int                 ANISO_THRESHOLD : 3;
                unsigned int                  MC_COORD_TRUNC : 1;
                unsigned int                   FORCE_DEGAMMA : 1;
                unsigned int                      ANISO_BIAS : 6;
                unsigned int                     TRUNC_COORD : 1;
                unsigned int               DISABLE_CUBE_WRAP : 1;
                unsigned int                     FILTER_MODE : 2;
                unsigned int                 COMPAT_MODE__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_SAMP_WORD1 {
	struct {
		unsigned int                         MIN_LOD : 12;
		unsigned int                         MAX_LOD : 12;
		unsigned int                        PERF_MIP : 4;
		unsigned int                          PERF_Z : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_SAMP_WORD2 {
	struct {
                unsigned int                        LOD_BIAS : 14;
                unsigned int                    LOD_BIAS_SEC : 6;
                unsigned int                   XY_MAG_FILTER : 2;
                unsigned int                   XY_MIN_FILTER : 2;
                unsigned int                        Z_FILTER : 2;
                unsigned int                      MIP_FILTER : 2;
                unsigned int              MIP_POINT_PRECLAMP : 1;
                unsigned int                DISABLE_LSB_CEIL : 1;
                unsigned int                 FILTER_PREC_FIX : 1;
                unsigned int              ANISO_OVERRIDE__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IMG_SAMP_WORD3 {
	struct {
		unsigned int                BORDER_COLOR_PTR : 12;
		unsigned int                                 : 18;
		unsigned int               BORDER_COLOR_TYPE : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IND_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_IND_INDEX {
	struct {
                unsigned int                         WAVE_ID : 4;
                unsigned int                         SIMD_ID : 2;
                unsigned int                       THREAD_ID : 6;
                unsigned int               AUTO_INCR__CI__VI : 1;
                unsigned int              FORCE_READ__CI__VI : 1;
                unsigned int                    READ_TIMEOUT : 1;
                unsigned int                       UNINDEXED : 1;
                unsigned int                           INDEX : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_INST {
	struct {
		unsigned int                        ENCODING : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_INTERRUPT_AUTO_MASK__CI__VI {
	struct {
                unsigned int                            MASK : 24;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_INTERRUPT_MSG_CTRL__CI__VI {
	struct {
                unsigned int                           STALL : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_INTERRUPT_WORD_AUTO__CI__VI {
	struct {
                unsigned int                    THREAD_TRACE : 1;
                unsigned int                             WLT : 1;
                unsigned int           THREAD_TRACE_BUF_FULL : 1;
                unsigned int                   REG_TIMESTAMP : 1;
                unsigned int                   CMD_TIMESTAMP : 1;
                unsigned int               HOST_CMD_OVERFLOW : 1;
                unsigned int               HOST_REG_OVERFLOW : 1;
                unsigned int                  IMMED_OVERFLOW : 1;
                unsigned int                                 : 16;
                unsigned int                           SE_ID : 2;
                unsigned int                        ENCODING : 2;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_INTERRUPT_WORD_AUTO__SI {
	struct {
		unsigned int                    THREAD_TRACE : 1;
		unsigned int                                 : 24;
		unsigned int                           SE_ID : 1;
		unsigned int                        ENCODING : 2;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_INTERRUPT_WORD_CMN__CI__VI {
	struct {
                unsigned int                                 : 24;
                unsigned int                           SE_ID : 2;
                unsigned int                        ENCODING : 2;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_INTERRUPT_WORD_CMN__SI {
	struct {
		unsigned int                                 : 25;
		unsigned int                           SE_ID : 1;
		unsigned int                        ENCODING : 2;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_INTERRUPT_WORD_WAVE__CI__VI {
	struct {
                unsigned int                            DATA : 8;
                unsigned int                           SH_ID : 1;
                unsigned int                            PRIV : 1;
                unsigned int                           VM_ID : 4;
                unsigned int                         WAVE_ID : 4;
                unsigned int                         SIMD_ID : 2;
                unsigned int                           CU_ID : 4;
                unsigned int                           SE_ID : 2;
                unsigned int                        ENCODING : 2;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_INTERRUPT_WORD_WAVE__SI {
	struct {
		unsigned int                            DATA : 8;
		unsigned int                                 : 2;
		unsigned int                           VM_ID : 4;
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                           CU_ID : 4;
		unsigned int                           SH_ID : 1;
		unsigned int                           SE_ID : 1;
		unsigned int                        ENCODING : 2;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_LB_CTR_CTRL {
	struct {
		unsigned int                           START : 1;
		unsigned int                            LOAD : 1;
		unsigned int                           CLEAR : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_LB_DATA_ALU_CYCLES {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_LB_DATA_ALU_STALLS {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_LB_DATA_TEX_CYCLES {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_LB_DATA_TEX_STALLS {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_LDS_CLK_CTRL__CI__VI {
	struct {
                unsigned int                 FORCE_CU_ON_SH0 : 16;
                unsigned int                 FORCE_CU_ON_SH1 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_MIMG_0 {
	struct {
		unsigned int                                 : 8;
		unsigned int                           DMASK : 4;
		unsigned int                           UNORM : 1;
		unsigned int                             GLC : 1;
		unsigned int                              DA : 1;
		unsigned int                            R128 : 1;
		unsigned int                             TFE : 1;
		unsigned int                             LWE : 1;
		unsigned int                              OP : 7;
		unsigned int                             SLC : 1;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_MIMG_1 {
	struct {
                unsigned int                           VADDR : 8;
                unsigned int                           VDATA : 8;
                unsigned int                           SRSRC : 5;
                unsigned int                           SSAMP : 5;
                unsigned int                                 : 5;
                unsigned int                         D16__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_MTBUF_0__SI__CI {
	struct {
		unsigned int                          OFFSET : 12;
		unsigned int                           OFFEN : 1;
		unsigned int                           IDXEN : 1;
		unsigned int                             GLC : 1;
		unsigned int                          ADDR64 : 1;
		unsigned int                              OP : 3;
		unsigned int                            DFMT : 4;
		unsigned int                            NFMT : 3;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_MTBUF_0__VI {
	struct {
		unsigned int                          OFFSET : 12;
		unsigned int                           OFFEN : 1;
		unsigned int                           IDXEN : 1;
		unsigned int                             GLC : 1;
		unsigned int                              OP : 4;
		unsigned int                            DFMT : 4;
		unsigned int                            NFMT : 3;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_MTBUF_1 {
	struct {
		unsigned int                           VADDR : 8;
		unsigned int                           VDATA : 8;
		unsigned int                           SRSRC : 5;
		unsigned int                                 : 1;
		unsigned int                             SLC : 1;
		unsigned int                             TFE : 1;
		unsigned int                         SOFFSET : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_MUBUF_0 {
	struct {
                unsigned int                          OFFSET : 12;
                unsigned int                           OFFEN : 1;
                unsigned int                           IDXEN : 1;
                unsigned int                             GLC : 1;
                unsigned int                  ADDR64__SI__CI : 1;
                unsigned int                             LDS : 1;
                unsigned int                         SLC__VI : 1;
                unsigned int                              OP : 7;
                unsigned int                                 : 1;
                unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_MUBUF_1__SI__CI {
	struct {
		unsigned int                           VADDR : 8;
		unsigned int                           VDATA : 8;
		unsigned int                           SRSRC : 5;
		unsigned int                                 : 1;
		unsigned int                             SLC : 1;
		unsigned int                             TFE : 1;
		unsigned int                         SOFFSET : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_MUBUF_1__VI {
	struct {
		unsigned int                           VADDR : 8;
		unsigned int                           VDATA : 8;
		unsigned int                           SRSRC : 5;
		unsigned int                                 : 2;
		unsigned int                             TFE : 1;
		unsigned int                         SOFFSET : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER0_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER10_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER10_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER10_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER10_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER11_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER11_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER11_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER11_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER12_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER12_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER12_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER12_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER13_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER13_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER13_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER13_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER14_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER14_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER14_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER14_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER15_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER15_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER15_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER15_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER1_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER2_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER2_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER3_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER3_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER4_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER4_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER4_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER4_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER5_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER5_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER5_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER5_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER6_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER6_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER6_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER6_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER7_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER7_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER7_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER7_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER8_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER8_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER8_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER8_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER9_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER9_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER9_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 9;
                unsigned int                                 : 3;
                unsigned int                   SQC_BANK_MASK : 4;
                unsigned int                 SQC_CLIENT_MASK : 4;
                unsigned int                        SPM_MODE : 4;
                unsigned int                       SIMD_MASK : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER9_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 9;
		unsigned int                                 : 15;
		unsigned int                       SIMD_MASK : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER_CTRL {
	struct {
		unsigned int                           PS_EN : 1;
		unsigned int                           VS_EN : 1;
		unsigned int                           GS_EN : 1;
		unsigned int                           ES_EN : 1;
		unsigned int                           HS_EN : 1;
		unsigned int                           LS_EN : 1;
		unsigned int                           CS_EN : 1;
		unsigned int                                 : 1;
		unsigned int                       CNTR_RATE : 5;
		unsigned int                   DISABLE_FLUSH : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER_CTRL2__CI__VI {
	struct {
                unsigned int                        FORCE_EN : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_PERFCOUNTER_MASK__CI__VI {
	struct {
                unsigned int                        SH0_MASK : 16;
                unsigned int                        SH1_MASK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_POWER_THROTTLE {
	struct {
		unsigned int                       MIN_POWER : 14;
		unsigned int                                 : 2;
		unsigned int                       MAX_POWER : 14;
		unsigned int                    PHASE_OFFSET : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_POWER_THROTTLE2 {
	struct {
		unsigned int                 MAX_POWER_DELTA : 14;
		unsigned int                                 : 2;
		unsigned int        SHORT_TERM_INTERVAL_SIZE : 10;
		unsigned int                                 : 1;
		unsigned int        LONG_TERM_INTERVAL_RATIO : 4;
		unsigned int                   USE_REF_CLOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_RANDOM_WAVE_PRI {
	struct {
		unsigned int                             RET : 7;
		unsigned int                             RUI : 3;
		unsigned int                             RNG : 11;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_REG_CREDITS {
	struct {
                unsigned int                    SRBM_CREDITS : 6;
                unsigned int                                 : 2;
                unsigned int                     CMD_CREDITS : 4;
                unsigned int                                 : 16;
                unsigned int                REG_BUSY__CI__VI : 1;
                unsigned int           SRBM_OVERFLOW__CI__VI : 1;
                unsigned int          IMMED_OVERFLOW__CI__VI : 1;
                unsigned int            CMD_OVERFLOW__CI__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_REG_TIMESTAMP__CI__VI {
	struct {
                unsigned int                       TIMESTAMP : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_SEC_CNT__SI__CI {
	struct {
		unsigned int                         LDS_SEC : 6;
		unsigned int                                 : 2;
		unsigned int                        SGPR_SEC : 5;
		unsigned int                                 : 3;
		unsigned int                        VGPR_SEC : 9;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_SMRD__SI__CI {
	struct {
		unsigned int                          OFFSET : 8;
		unsigned int                             IMM : 1;
		unsigned int                           SBASE : 6;
		unsigned int                            SDST : 7;
		unsigned int                              OP : 5;
		unsigned int                        ENCODING : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_SOP1 {
	struct {
		unsigned int                           SSRC0 : 8;
		unsigned int                              OP : 8;
		unsigned int                            SDST : 7;
		unsigned int                        ENCODING : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_SOP2 {
	struct {
		unsigned int                           SSRC0 : 8;
		unsigned int                           SSRC1 : 8;
		unsigned int                            SDST : 7;
		unsigned int                              OP : 7;
		unsigned int                        ENCODING : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_SOPC {
	struct {
		unsigned int                           SSRC0 : 8;
		unsigned int                           SSRC1 : 8;
		unsigned int                              OP : 7;
		unsigned int                        ENCODING : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_SOPK {
	struct {
		unsigned int                          SIMM16 : 16;
		unsigned int                            SDST : 7;
		unsigned int                              OP : 5;
		unsigned int                        ENCODING : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_SOPP {
	struct {
		unsigned int                          SIMM16 : 16;
		unsigned int                              OP : 7;
		unsigned int                        ENCODING : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_TEX_CLK_CTRL {
	struct {
		unsigned int                 FORCE_CU_ON_SH0 : 16;
		unsigned int                 FORCE_CU_ON_SH1 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_BASE {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_BASE2__CI__VI {
	struct {
                unsigned int                         ADDR_HI : 4;
                unsigned int                             ATC : 1;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_CNTR {
	struct {
		unsigned int                            CNTR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_CTRL {
	struct {
		unsigned int                                 : 31;
		unsigned int                    RESET_BUFFER : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_HIWATER {
	struct {
		unsigned int                         HIWATER : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_MASK {
	struct {
                unsigned int                          CU_SEL : 5;
                unsigned int                          SH_SEL : 1;
                unsigned int                                 : 1;
                unsigned int            REG_STALL_EN__CI__VI : 1;
                unsigned int                         SIMD_EN : 4;
                unsigned int                      VM_ID_MASK : 2;
                unsigned int            SPI_STALL_EN__CI__VI : 1;
                unsigned int             SQ_STALL_EN__CI__VI : 1;
                unsigned int                     RANDOM_SEED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_MODE {
	struct {
		unsigned int                         MASK_PS : 3;
		unsigned int                         MASK_VS : 3;
		unsigned int                         MASK_GS : 3;
		unsigned int                         MASK_ES : 3;
		unsigned int                         MASK_HS : 3;
		unsigned int                         MASK_LS : 3;
		unsigned int                         MASK_CS : 3;
		unsigned int                            MODE : 2;
		unsigned int                    CAPTURE_MODE : 2;
		unsigned int                    AUTOFLUSH_EN : 1;
		unsigned int                            PRIV : 1;
		unsigned int                      ISSUE_MASK : 2;
		unsigned int                       TEST_MODE : 1;
		unsigned int                    INTERRUPT_EN : 1;
		unsigned int                            WRAP : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_PERF_MASK {
	struct {
		unsigned int                        SH0_MASK : 16;
		unsigned int                        SH1_MASK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_SIZE {
	struct {
		unsigned int                            SIZE : 22;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_STATUS {
	struct {
                unsigned int                  FINISH_PENDING : 10;
                unsigned int                                 : 6;
                unsigned int                     FINISH_DONE : 10;
                unsigned int                                 : 3;
                unsigned int                         NEW_BUF : 1;
                unsigned int                            BUSY : 1;
                unsigned int                            FULL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_TOKEN_MASK {
	struct {
                unsigned int                      TOKEN_MASK : 16;
                unsigned int                        REG_MASK : 8;
                unsigned int       REG_DROP_ON_STALL__CI__VI : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_TOKEN_MASK2__CI {
	struct {
		unsigned int                       INST_MASK : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_TOKEN_MASK2__VI {
	struct {
		unsigned int                       INST_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_USERDATA_0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_USERDATA_1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_USERDATA_2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_USERDATA_3 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_CMN {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_EVENT {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                           SH_ID : 1;
		unsigned int                           STAGE : 3;
		unsigned int                                 : 1;
		unsigned int                      EVENT_TYPE : 6;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_INST__SI__CI {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                            SIZE : 1;
		unsigned int                       INST_TYPE : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_INST__VI {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                       INST_TYPE : 5;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                                 : 5;
		unsigned int                           PC_LO : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 {
	struct {
		unsigned int                           PC_HI : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                           SH_ID : 1;
		unsigned int                           CU_ID : 4;
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                         DATA_LO : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 {
	struct {
		unsigned int                         DATA_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_ISSUE {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                         SIMD_ID : 2;
		unsigned int                                 : 1;
		unsigned int                           INST0 : 2;
		unsigned int                           INST1 : 2;
		unsigned int                           INST2 : 2;
		unsigned int                           INST3 : 2;
		unsigned int                           INST4 : 2;
		unsigned int                           INST5 : 2;
		unsigned int                           INST6 : 2;
		unsigned int                           INST7 : 2;
		unsigned int                           INST8 : 2;
		unsigned int                           INST9 : 2;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_MISC__CI__VI {
	struct {
                unsigned int                      TOKEN_TYPE : 4;
                unsigned int                      TIME_DELTA : 8;
                unsigned int                           SH_ID : 1;
                unsigned int                 MISC_TOKEN_TYPE : 3;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_MISC__SI {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                           SH_ID : 1;
		unsigned int                 MISC_TOKEN_TYPE : 2;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_PERF_1_OF_2 {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                           SH_ID : 1;
		unsigned int                           CU_ID : 4;
		unsigned int                       CNTR_BANK : 2;
		unsigned int                           CNTR0 : 13;
		unsigned int                        CNTR1_LO : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_PERF_2_OF_2 {
	struct {
		unsigned int                        CNTR1_HI : 6;
		unsigned int                           CNTR2 : 13;
		unsigned int                           CNTR3 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_REG_1_OF_2__CI__VI {
	struct {
                unsigned int                      TOKEN_TYPE : 4;
                unsigned int                      TIME_DELTA : 1;
                unsigned int                         PIPE_ID : 2;
                unsigned int                           ME_ID : 2;
                unsigned int                REG_DROPPED_PREV : 1;
                unsigned int                        REG_TYPE : 3;
                unsigned int                                 : 1;
                unsigned int                        REG_PRIV : 1;
                unsigned int                          REG_OP : 1;
                unsigned int                        REG_ADDR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_REG_1_OF_2__SI {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                                 : 5;
		unsigned int                        REG_TYPE : 3;
		unsigned int                                 : 1;
		unsigned int                        REG_PRIV : 1;
		unsigned int                          REG_OP : 1;
		unsigned int                        REG_ADDR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_REG_2_OF_2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__CI__VI {
	struct {
                unsigned int                      TOKEN_TYPE : 4;
                unsigned int                      TIME_DELTA : 1;
                unsigned int                         PIPE_ID : 2;
                unsigned int                           ME_ID : 2;
                unsigned int                        REG_ADDR : 7;
                unsigned int                         DATA_LO : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__CI__VI {
	struct {
                unsigned int                         DATA_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                                 : 12;
		unsigned int                         TIME_LO : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 {
	struct {
		unsigned int                         TIME_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_TIME__SI {
	struct {
		unsigned int                                 : 4;
		unsigned int                                 : 10;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_WAVE {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                           SH_ID : 1;
		unsigned int                           CU_ID : 4;
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WORD_WAVE_START {
	struct {
		unsigned int                      TOKEN_TYPE : 4;
		unsigned int                      TIME_DELTA : 1;
		unsigned int                           SH_ID : 1;
		unsigned int                           CU_ID : 4;
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                      DISPATCHER : 5;
		unsigned int          VS_NO_ALLOC_OR_GROUPED : 1;
		unsigned int                           COUNT : 7;
		unsigned int                           TG_ID : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_THREAD_TRACE_WPTR {
	struct {
		unsigned int                            WPTR : 30;
		unsigned int                     READ_OFFSET : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_TIME_HI {
	struct {
		unsigned int                            TIME : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_TIME_LO {
	struct {
		unsigned int                            TIME : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VINTRP {
	struct {
		unsigned int                            VSRC : 8;
		unsigned int                        ATTRCHAN : 2;
		unsigned int                            ATTR : 6;
		unsigned int                              OP : 2;
		unsigned int                            VDST : 8;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VOP1 {
	struct {
		unsigned int                            SRC0 : 9;
		unsigned int                              OP : 8;
		unsigned int                            VDST : 8;
		unsigned int                        ENCODING : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VOP2 {
	struct {
		unsigned int                            SRC0 : 9;
		unsigned int                           VSRC1 : 8;
		unsigned int                            VDST : 8;
		unsigned int                              OP : 6;
		unsigned int                        ENCODING : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VOP3_0__SI__CI {
	struct {
		unsigned int                            VDST : 8;
		unsigned int                             ABS : 3;
		unsigned int                           CLAMP : 1;
		unsigned int                                 : 5;
		unsigned int                              OP : 9;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VOP3_0__VI {
	struct {
		unsigned int                            VDST : 8;
		unsigned int                             ABS : 3;
		unsigned int                                 : 4;
		unsigned int                           CLAMP : 1;
		unsigned int                              OP : 10;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VOP3_0_SDST_ENC__SI__CI {
	struct {
		unsigned int                            VDST : 8;
		unsigned int                            SDST : 7;
		unsigned int                                 : 2;
		unsigned int                              OP : 9;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VOP3_0_SDST_ENC__VI {
	struct {
		unsigned int                            VDST : 8;
		unsigned int                            SDST : 7;
		unsigned int                           CLAMP : 1;
		unsigned int                              OP : 10;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VOP3_1 {
	struct {
		unsigned int                            SRC0 : 9;
		unsigned int                            SRC1 : 9;
		unsigned int                            SRC2 : 9;
		unsigned int                            OMOD : 2;
		unsigned int                             NEG : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VOPC {
	struct {
		unsigned int                            SRC0 : 9;
		unsigned int                           VSRC1 : 8;
		unsigned int                              OP : 8;
		unsigned int                        ENCODING : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_EXEC_HI {
	struct {
		unsigned int                         EXEC_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_EXEC_LO {
	struct {
		unsigned int                         EXEC_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_GPR_ALLOC {
	struct {
		unsigned int                       VGPR_BASE : 6;
		unsigned int                                 : 2;
		unsigned int                       VGPR_SIZE : 6;
		unsigned int                                 : 2;
		unsigned int                       SGPR_BASE : 6;
		unsigned int                                 : 2;
		unsigned int                       SGPR_SIZE : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_HW_ID__CI__VI {
	struct {
                unsigned int                         WAVE_ID : 4;
                unsigned int                         SIMD_ID : 2;
                unsigned int                         PIPE_ID : 2;
                unsigned int                           CU_ID : 4;
                unsigned int                           SH_ID : 1;
                unsigned int                           SE_ID : 2;
                unsigned int                                 : 1;
                unsigned int                           TG_ID : 4;
                unsigned int                           VM_ID : 4;
                unsigned int                        QUEUE_ID : 3;
                unsigned int                        STATE_ID : 3;
                unsigned int                           ME_ID : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_HW_ID__SI {
	struct {
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                                 : 2;
		unsigned int                           CU_ID : 4;
		unsigned int                           SH_ID : 1;
		unsigned int                           SE_ID : 1;
		unsigned int                                 : 2;
		unsigned int                           TG_ID : 4;
		unsigned int                           VM_ID : 4;
		unsigned int                                 : 3;
		unsigned int                        STATE_ID : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_IB_DBG0__SI__CI {
	struct {
                unsigned int                         IBUF_ST : 3;
                unsigned int                      PC_INVALID : 1;
                unsigned int                    NEED_NEXT_DW : 1;
                unsigned int                 NO_PREFETCH_CNT : 3;
                unsigned int                       IBUF_RPTR : 2;
                unsigned int                       IBUF_WPTR : 2;
                unsigned int                                 : 4;
                unsigned int                     INST_STR_ST : 3;
                unsigned int                        MISC_CNT : 3;
                unsigned int                          ECC_ST : 2;
                unsigned int                          IS_HYB : 1;
                unsigned int                         HYB_CNT : 2;
                unsigned int                        KILL__CI : 1;
                unsigned int            NEED_KILL_IFETCH__CI : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_IB_DBG0__VI {
	struct {
		unsigned int                         IBUF_ST : 3;
		unsigned int                      PC_INVALID : 1;
		unsigned int                    NEED_NEXT_DW : 1;
		unsigned int                 NO_PREFETCH_CNT : 3;
		unsigned int                       IBUF_RPTR : 2;
		unsigned int                       IBUF_WPTR : 2;
		unsigned int                                 : 4;
		unsigned int                     INST_STR_ST : 4;
		unsigned int                        MISC_CNT : 4;
		unsigned int                          ECC_ST : 2;
		unsigned int                          IS_HYB : 1;
		unsigned int                         HYB_CNT : 2;
		unsigned int                            KILL : 1;
		unsigned int                NEED_KILL_IFETCH : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_IB_STS__CI__VI {
	struct {
                unsigned int                          VM_CNT : 4;
                unsigned int                         EXP_CNT : 3;
                unsigned int                                 : 1;
                unsigned int                        LGKM_CNT : 4;
                unsigned int                        VALU_CNT : 3;
                unsigned int                FIRST_REPLAY__VI : 1;
                unsigned int                        RCNT__VI : 4;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_IB_STS__SI {
	struct {
		unsigned int                          VM_CNT : 4;
		unsigned int                         EXP_CNT : 3;
		unsigned int                                 : 1;
		unsigned int                        LGKM_CNT : 5;
		unsigned int                        VALU_CNT : 3;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_INST_DW0 {
	struct {
		unsigned int                        INST_DW0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_INST_DW1 {
	struct {
		unsigned int                        INST_DW1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_LDS_ALLOC {
	struct {
		unsigned int                        LDS_BASE : 8;
		unsigned int                                 : 4;
		unsigned int                        LDS_SIZE : 9;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_M0 {
	struct {
		unsigned int                              M0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_MODE {
	struct {
                unsigned int                        FP_ROUND : 4;
                unsigned int                       FP_DENORM : 4;
                unsigned int                      DX10_CLAMP : 1;
                unsigned int                            IEEE : 1;
                unsigned int                     LOD_CLAMPED : 1;
                unsigned int                        DEBUG_EN : 1;
                unsigned int                         EXCP_EN : 9;
                unsigned int                                 : 6;
                unsigned int                  GPR_IDX_EN__VI : 1;
                unsigned int                           VSKIP : 1;
                unsigned int                             CSP : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_PC_HI {
	struct {
                unsigned int                           PC_HI : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_PC_LO {
	struct {
		unsigned int                           PC_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_STATUS__SI__CI {
	struct {
                unsigned int                             SCC : 1;
                unsigned int                        SPI_PRIO : 2;
                unsigned int                       WAVE_PRIO : 2;
                unsigned int                            PRIV : 1;
                unsigned int                         TRAP_EN : 1;
                unsigned int                       TTRACE_EN : 1;
                unsigned int                      EXPORT_RDY : 1;
                unsigned int                           EXECZ : 1;
                unsigned int                            VCCZ : 1;
                unsigned int                           IN_TG : 1;
                unsigned int                      IN_BARRIER : 1;
                unsigned int                            HALT : 1;
                unsigned int                            TRAP : 1;
                unsigned int                    TTRACE_CU_EN : 1;
                unsigned int                           VALID : 1;
                unsigned int                         ECC_ERR : 1;
                unsigned int                     SKIP_EXPORT : 1;
                unsigned int                         PERF_EN : 1;
                unsigned int               COND_DBG_USER__CI : 1;
                unsigned int                COND_DBG_SYS__CI : 1;
                unsigned int                    DATA_ATC__CI : 1;
                unsigned int                    INST_ATC__CI : 1;
                unsigned int         DISPATCH_CACHE_CTRL__CI : 3;
                unsigned int                 MUST_EXPORT__CI : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_STATUS__VI {
	struct {
		unsigned int                             SCC : 1;
		unsigned int                        SPI_PRIO : 2;
		unsigned int                       USER_PRIO : 2;
		unsigned int                            PRIV : 1;
		unsigned int                         TRAP_EN : 1;
		unsigned int                       TTRACE_EN : 1;
		unsigned int                      EXPORT_RDY : 1;
		unsigned int                           EXECZ : 1;
		unsigned int                            VCCZ : 1;
		unsigned int                           IN_TG : 1;
		unsigned int                      IN_BARRIER : 1;
		unsigned int                            HALT : 1;
		unsigned int                            TRAP : 1;
		unsigned int                    TTRACE_CU_EN : 1;
		unsigned int                           VALID : 1;
		unsigned int                         ECC_ERR : 1;
		unsigned int                     SKIP_EXPORT : 1;
		unsigned int                         PERF_EN : 1;
		unsigned int                   COND_DBG_USER : 1;
		unsigned int                    COND_DBG_SYS : 1;
		unsigned int                    ALLOW_REPLAY : 1;
		unsigned int                        INST_ATC : 1;
		unsigned int                                 : 3;
		unsigned int                     MUST_EXPORT : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TBA_HI {
	struct {
		unsigned int                         ADDR_HI : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TBA_LO {
	struct {
		unsigned int                         ADDR_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TMA_HI {
	struct {
		unsigned int                         ADDR_HI : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TMA_LO {
	struct {
		unsigned int                         ADDR_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TRAPSTS {
	struct {
                unsigned int                            EXCP : 9;
                unsigned int                                 : 1;
                unsigned int                     SAVECTX__VI : 1;
                unsigned int                                 : 5;
                unsigned int                      EXCP_CYCLE : 6;
                unsigned int                                 : 7;
                unsigned int                         DP_RATE : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP0 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP1 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP10 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP11 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP2 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP3 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP4 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP5 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP6 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP7 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP8 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_TTMP9 {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_CAM_DATA {
	struct {
		unsigned int                        CAM_ADDR : 16;
		unsigned int                   CAM_REMAPADDR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_CAM_INDEX {
	struct {
                unsigned int                       CAM_INDEX : 3;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_CHIP_REVISION {
	struct {
		unsigned int                   CHIP_REVISION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_CNTL {
	struct {
                unsigned int                    READ_TIMEOUT : 10;
                unsigned int                                 : 6;
                unsigned int                PWR_REQUEST_HALT : 1;
                unsigned int       COMBINE_SYSTEM_MC__CI__VI : 1;
                unsigned int           REPORT_LAST_RDERR__VI : 1;
                unsigned int      PWR_GFX3D_REQUEST_HALT__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DEBUG_CNTL {
	struct {
		unsigned int                SRBM_DEBUG_INDEX : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DEBUG_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DEBUG_SNAPSHOT__SI__CI {
	struct {
                unsigned int                         MCB_RDY : 1;
                unsigned int                   ROPLL_RDY__CI : 1;
                unsigned int                     SMU_RDY__CI : 1;
                unsigned int                     SAM_RDY__CI : 1;
                unsigned int                     ACP_RDY__CI : 1;
                unsigned int                        GRBM_RDY : 1;
                unsigned int                          DC_RDY : 1;
                unsigned int                         BIF_RDY : 1;
                unsigned int                        XDMA_RDY : 1;
                unsigned int                         UVD_RDY : 1;
                unsigned int                         XSP_RDY : 1;
                unsigned int                       REGBB_RDY : 1;
                unsigned int                         ORB_RDY : 1;
                unsigned int                        MCD7_RDY : 1;
                unsigned int                        MCD6_RDY : 1;
                unsigned int                        MCD5_RDY : 1;
                unsigned int                        MCD4_RDY : 1;
                unsigned int                        MCD3_RDY : 1;
                unsigned int                        MCD2_RDY : 1;
                unsigned int                        MCD1_RDY : 1;
                unsigned int                        MCD0_RDY : 1;
                unsigned int                        MCC7_RDY : 1;
                unsigned int                        MCC6_RDY : 1;
                unsigned int                        MCC5_RDY : 1;
                unsigned int                        MCC4_RDY : 1;
                unsigned int                        MCC3_RDY : 1;
                unsigned int                        MCC2_RDY : 1;
                unsigned int                        MCC1_RDY : 1;
                unsigned int                        MCC0_RDY : 1;
                unsigned int                         VCE_RDY : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DEBUG_SNAPSHOT__VI {
	struct {
		unsigned int                         MCB_RDY : 1;
		unsigned int                       GIONB_RDY : 1;
		unsigned int                         SMU_RDY : 1;
		unsigned int                      SAMMSP_RDY : 1;
		unsigned int                         ACP_RDY : 1;
		unsigned int                        GRBM_RDY : 1;
		unsigned int                          DC_RDY : 1;
		unsigned int                         BIF_RDY : 1;
		unsigned int                        XDMA_RDY : 1;
		unsigned int                         UVD_RDY : 1;
		unsigned int                         VP8_RDY : 1;
		unsigned int                       REGBB_RDY : 1;
		unsigned int                         ODE_RDY : 1;
		unsigned int                        MCD7_RDY : 1;
		unsigned int                        MCD6_RDY : 1;
		unsigned int                        MCD5_RDY : 1;
		unsigned int                        MCD4_RDY : 1;
		unsigned int                        MCD3_RDY : 1;
		unsigned int                        MCD2_RDY : 1;
		unsigned int                        MCD1_RDY : 1;
		unsigned int                        MCD0_RDY : 1;
		unsigned int                        MCC7_RDY : 1;
		unsigned int                        MCC6_RDY : 1;
		unsigned int                        MCC5_RDY : 1;
		unsigned int                        MCC4_RDY : 1;
		unsigned int                        MCC3_RDY : 1;
		unsigned int                        MCC2_RDY : 1;
		unsigned int                        MCC1_RDY : 1;
		unsigned int                        MCC0_RDY : 1;
		unsigned int                        VCE0_RDY : 1;
		unsigned int                      SAMSCP_RDY : 1;
		unsigned int                         ISP_RDY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DEBUG__CI__VI {
	struct {
                unsigned int                      IGNORE_RDY : 1;
                unsigned int            DISABLE_READ_TIMEOUT : 1;
                unsigned int             SNAPSHOT_FREE_CNTRS : 1;
                unsigned int                                 : 1;
                unsigned int       SYS_CLOCK_DOMAIN_OVERRIDE : 1;
                unsigned int       VCE_CLOCK_DOMAIN_OVERRIDE : 1;
                unsigned int       UVD_CLOCK_DOMAIN_OVERRIDE : 1;
                unsigned int      SDMA_CLOCK_DOMAIN_OVERRIDE : 1;
                unsigned int        MC_CLOCK_DOMAIN_OVERRIDE : 1;
                unsigned int       SAM_CLOCK_DOMAIN_OVERRIDE : 1;
                unsigned int   ISP_CLOCK_DOMAIN_OVERRIDE__VI : 1;
                unsigned int   VP8_CLOCK_DOMAIN_OVERRIDE__VI : 1;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DEBUG__SI {
	struct {
		unsigned int                      IGNORE_RDY : 1;
		unsigned int            DISABLE_READ_TIMEOUT : 1;
		unsigned int             SNAPSHOT_FREE_CNTRS : 1;
		unsigned int                                 : 1;
		unsigned int       SYS_CLOCK_DOMAIN_OVERRIDE : 1;
		unsigned int       VCE_CLOCK_DOMAIN_OVERRIDE : 1;
		unsigned int       UVD_CLOCK_DOMAIN_OVERRIDE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_GFX_CNTL__CI__VI {
	struct {
                unsigned int                          PIPEID : 2;
                unsigned int                            MEID : 2;
                unsigned int                            VMID : 4;
                unsigned int                         QUEUEID : 3;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_GFX_CNTL__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                            VMID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_INT_ACK {
	struct {
                unsigned int                   RDERR_INT_ACK : 1;
                unsigned int               RAERR_INT_ACK__VI : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_INT_CNTL {
	struct {
                unsigned int                  RDERR_INT_MASK : 1;
                unsigned int              RAERR_INT_MASK__VI : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_INT_STATUS {
	struct {
                unsigned int                  RDERR_INT_STAT : 1;
                unsigned int              RAERR_INT_STAT__VI : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_MC_CLKEN_CNTL__CI__VI {
	struct {
                unsigned int                PREFIX_DELAY_CNT : 4;
                unsigned int                                 : 4;
                unsigned int                  POST_DELAY_CNT : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERF_COUNT0_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERF_COUNT0_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_PERFCOUNTER0_SELECT {
	struct {
		unsigned int                        PERF_SEL : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERF_COUNT1_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERF_COUNT1_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_PERFCOUNTER1_SELECT {
	struct {
		unsigned int                        PERF_SEL : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_PERFMON_CNTL {
	struct {
		unsigned int                   PERFMON_STATE : 4;
		unsigned int                                 : 4;
		unsigned int             PERFMON_ENABLE_MODE : 2;
		unsigned int           PERFMON_SAMPLE_ENABLE : 1;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_READ_ERROR__CI {
	struct {
		unsigned int                                 : 2;
		unsigned int                    READ_ADDRESS : 16;
		unsigned int                                 : 2;
		unsigned int              READ_REQUESTER_VCE : 1;
		unsigned int            READ_REQUESTER_SDMA1 : 1;
		unsigned int              READ_REQUESTER_TST : 1;
		unsigned int              READ_REQUESTER_SAM : 1;
		unsigned int               READ_REQUESTER_HI : 1;
		unsigned int             READ_REQUESTER_GRBM : 1;
		unsigned int              READ_REQUESTER_SMU : 1;
		unsigned int              READ_REQUESTER_ACP : 1;
		unsigned int             READ_REQUESTER_SDMA : 1;
		unsigned int              READ_REQUESTER_UVD : 1;
		unsigned int                                 : 1;
		unsigned int                      READ_ERROR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_READ_ERROR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                    READ_ADDRESS : 16;
		unsigned int            READ_REQUESTER_SDMA3 : 1;
		unsigned int            READ_REQUESTER_SDMA2 : 1;
		unsigned int             READ_REQUESTER_VCE0 : 1;
		unsigned int            READ_REQUESTER_SDMA1 : 1;
		unsigned int              READ_REQUESTER_TST : 1;
		unsigned int           READ_REQUESTER_SAMMSP : 1;
		unsigned int               READ_REQUESTER_HI : 1;
		unsigned int             READ_REQUESTER_GRBM : 1;
		unsigned int              READ_REQUESTER_SMU : 1;
		unsigned int           READ_REQUESTER_SAMSCP : 1;
		unsigned int             READ_REQUESTER_SDMA : 1;
		unsigned int              READ_REQUESTER_UVD : 1;
		unsigned int                                 : 1;
		unsigned int                      READ_ERROR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_READ_ERROR__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int                    READ_ADDRESS : 16;
		unsigned int                                 : 2;
		unsigned int              READ_REQUESTER_VCE : 1;
		unsigned int                                 : 1;
		unsigned int              READ_REQUESTER_TST : 1;
		unsigned int                                 : 1;
		unsigned int               READ_REQUESTER_HI : 1;
		unsigned int             READ_REQUESTER_GRBM : 1;
		unsigned int              READ_REQUESTER_SMU : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int              READ_REQUESTER_UVD : 1;
		unsigned int                                 : 1;
		unsigned int                      READ_ERROR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SAM_CLKEN_CNTL__CI__VI {
	struct {
                unsigned int                PREFIX_DELAY_CNT : 4;
                unsigned int                                 : 4;
                unsigned int                  POST_DELAY_CNT : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SDMA_CLKEN_CNTL__CI__VI {
	struct {
                unsigned int                PREFIX_DELAY_CNT : 4;
                unsigned int                                 : 4;
                unsigned int                  POST_DELAY_CNT : 5;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SOFT_RESET__CI {
	struct {
		unsigned int                                 : 1;
		unsigned int                  SOFT_RESET_BIF : 1;
		unsigned int                                 : 2;
		unsigned int                SOFT_RESET_ROPLL : 1;
		unsigned int                   SOFT_RESET_DC : 1;
		unsigned int                SOFT_RESET_SDMA1 : 1;
		unsigned int                                 : 1;
		unsigned int                 SOFT_RESET_GRBM : 1;
		unsigned int                  SOFT_RESET_HDP : 1;
		unsigned int                   SOFT_RESET_IH : 1;
		unsigned int                   SOFT_RESET_MC : 1;
		unsigned int                 SOFT_RESET_CHUB : 1;
		unsigned int                                 : 1;
		unsigned int                  SOFT_RESET_ROM : 1;
		unsigned int                  SOFT_RESET_SEM : 1;
		unsigned int                  SOFT_RESET_SMU : 1;
		unsigned int                  SOFT_RESET_VMC : 1;
		unsigned int                  SOFT_RESET_UVD : 1;
		unsigned int                  SOFT_RESET_XSP : 1;
		unsigned int                 SOFT_RESET_SDMA : 1;
		unsigned int                  SOFT_RESET_TST : 1;
		unsigned int                SOFT_RESET_REGBB : 1;
		unsigned int                  SOFT_RESET_ORB : 1;
		unsigned int                  SOFT_RESET_VCE : 1;
		unsigned int                 SOFT_RESET_XDMA : 1;
		unsigned int                  SOFT_RESET_ACP : 1;
		unsigned int                  SOFT_RESET_SAM : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SOFT_RESET__VI {
	struct {
		unsigned int                SOFT_RESET_ATCL2 : 1;
		unsigned int                  SOFT_RESET_BIF : 1;
		unsigned int                SOFT_RESET_SDMA3 : 1;
		unsigned int                SOFT_RESET_SDMA2 : 1;
		unsigned int                SOFT_RESET_GIONB : 1;
		unsigned int                   SOFT_RESET_DC : 1;
		unsigned int                SOFT_RESET_SDMA1 : 1;
		unsigned int                                 : 1;
		unsigned int                 SOFT_RESET_GRBM : 1;
		unsigned int                  SOFT_RESET_HDP : 1;
		unsigned int                   SOFT_RESET_IH : 1;
		unsigned int                   SOFT_RESET_MC : 1;
		unsigned int                 SOFT_RESET_CHUB : 1;
		unsigned int                SOFT_RESET_ESRAM : 1;
		unsigned int                  SOFT_RESET_ROM : 1;
		unsigned int                  SOFT_RESET_SEM : 1;
		unsigned int                  SOFT_RESET_SMU : 1;
		unsigned int                  SOFT_RESET_VMC : 1;
		unsigned int                  SOFT_RESET_UVD : 1;
		unsigned int                  SOFT_RESET_VP8 : 1;
		unsigned int                 SOFT_RESET_SDMA : 1;
		unsigned int                  SOFT_RESET_TST : 1;
		unsigned int                SOFT_RESET_REGBB : 1;
		unsigned int                  SOFT_RESET_ODE : 1;
		unsigned int                 SOFT_RESET_VCE0 : 1;
		unsigned int                 SOFT_RESET_XDMA : 1;
		unsigned int                  SOFT_RESET_ACP : 1;
		unsigned int               SOFT_RESET_SAMMSP : 1;
		unsigned int               SOFT_RESET_SAMSCP : 1;
		unsigned int                  SOFT_RESET_GRN : 1;
		unsigned int                  SOFT_RESET_ISP : 1;
		unsigned int                 SOFT_RESET_VCE1 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SOFT_RESET__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                  SOFT_RESET_BIF : 1;
		unsigned int                                 : 3;
		unsigned int                   SOFT_RESET_DC : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 SOFT_RESET_GRBM : 1;
		unsigned int                  SOFT_RESET_HDP : 1;
		unsigned int                   SOFT_RESET_IH : 1;
		unsigned int                   SOFT_RESET_MC : 1;
		unsigned int                                 : 2;
		unsigned int                  SOFT_RESET_ROM : 1;
		unsigned int                  SOFT_RESET_SEM : 1;
		unsigned int                                 : 1;
		unsigned int                  SOFT_RESET_VMC : 1;
		unsigned int                  SOFT_RESET_UVD : 1;
		unsigned int                  SOFT_RESET_XSP : 1;
		unsigned int                                 : 1;
		unsigned int                  SOFT_RESET_TST : 1;
		unsigned int                SOFT_RESET_REGBB : 1;
		unsigned int                  SOFT_RESET_ORB : 1;
		unsigned int                  SOFT_RESET_VCE : 1;
		unsigned int                 SOFT_RESET_XDMA : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_STATUS__SI__CI {
	struct {
                unsigned int                                 : 1;
                unsigned int                  UVD_RQ_PENDING : 1;
                unsigned int              SAM_RQ_PENDING__CI : 1;
                unsigned int              ACP_RQ_PENDING__CI : 1;
                unsigned int                  SMU_RQ_PENDING : 1;
                unsigned int                 GRBM_RQ_PENDING : 1;
                unsigned int                   HI_RQ_PENDING : 1;
                unsigned int                IO_EXTERN_SIGNAL : 1;
                unsigned int                        VMC_BUSY : 1;
                unsigned int                        MCB_BUSY : 1;
                unsigned int            MCB_NON_DISPLAY_BUSY : 1;
                unsigned int                        MCC_BUSY : 1;
                unsigned int                        MCD_BUSY : 1;
                unsigned int                                 : 1;
                unsigned int                        SEM_BUSY : 1;
                unsigned int                                 : 1;
                unsigned int                    ACP_BUSY__CI : 1;
                unsigned int                         IH_BUSY : 1;
                unsigned int                                 : 1;
                unsigned int                        UVD_BUSY : 1;
                unsigned int                    SAM_BUSY__CI : 1;
                unsigned int                                 : 8;
                unsigned int                        BIF_BUSY : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_STATUS__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                  UVD_RQ_PENDING : 1;
		unsigned int               SAMMSP_RQ_PENDING : 1;
		unsigned int                  ACP_RQ_PENDING : 1;
		unsigned int                  SMU_RQ_PENDING : 1;
		unsigned int                 GRBM_RQ_PENDING : 1;
		unsigned int                   HI_RQ_PENDING : 1;
		unsigned int                                 : 1;
		unsigned int                        VMC_BUSY : 1;
		unsigned int                        MCB_BUSY : 1;
		unsigned int            MCB_NON_DISPLAY_BUSY : 1;
		unsigned int                        MCC_BUSY : 1;
		unsigned int                        MCD_BUSY : 1;
		unsigned int                       VMC1_BUSY : 1;
		unsigned int                        SEM_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                        ACP_BUSY : 1;
		unsigned int                         IH_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                        UVD_BUSY : 1;
		unsigned int                     SAMMSP_BUSY : 1;
		unsigned int                    GCATCL2_BUSY : 1;
		unsigned int                    OSATCL2_BUSY : 1;
		unsigned int                                 : 6;
		unsigned int                        BIF_BUSY : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_STATUS2__CI {
	struct {
		unsigned int                 SDMA_RQ_PENDING : 1;
		unsigned int                  TST_RQ_PENDING : 1;
		unsigned int                SDMA1_RQ_PENDING : 1;
		unsigned int                  VCE_RQ_PENDING : 1;
		unsigned int                        XSP_BUSY : 1;
		unsigned int                       SDMA_BUSY : 1;
		unsigned int                      SDMA1_BUSY : 1;
		unsigned int                        VCE_BUSY : 1;
		unsigned int                       XDMA_BUSY : 1;
		unsigned int                       CHUB_BUSY : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_STATUS2__VI {
	struct {
		unsigned int                 SDMA_RQ_PENDING : 1;
		unsigned int                  TST_RQ_PENDING : 1;
		unsigned int                SDMA1_RQ_PENDING : 1;
		unsigned int                 VCE0_RQ_PENDING : 1;
		unsigned int                        VP8_BUSY : 1;
		unsigned int                       SDMA_BUSY : 1;
		unsigned int                      SDMA1_BUSY : 1;
		unsigned int                       VCE0_BUSY : 1;
		unsigned int                       XDMA_BUSY : 1;
		unsigned int                       CHUB_BUSY : 1;
		unsigned int                      SDMA2_BUSY : 1;
		unsigned int                      SDMA3_BUSY : 1;
		unsigned int                     SAMSCP_BUSY : 1;
		unsigned int                        ISP_BUSY : 1;
		unsigned int                       VCE1_BUSY : 1;
		unsigned int                        ODE_BUSY : 1;
		unsigned int                SDMA2_RQ_PENDING : 1;
		unsigned int                SDMA3_RQ_PENDING : 1;
		unsigned int               SAMSCP_RQ_PENDING : 1;
		unsigned int                  ISP_RQ_PENDING : 1;
		unsigned int                 VCE1_RQ_PENDING : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_STATUS2__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                  TST_RQ_PENDING : 1;
		unsigned int                                 : 1;
		unsigned int                  VCE_RQ_PENDING : 1;
		unsigned int                        XSP_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                        VCE_BUSY : 1;
		unsigned int                       XDMA_BUSY : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SYS_CLKEN_CNTL {
	struct {
		unsigned int                PREFIX_DELAY_CNT : 4;
		unsigned int                                 : 4;
		unsigned int                  POST_DELAY_CNT : 5;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_UVD_CLKEN_CNTL {
	struct {
		unsigned int                PREFIX_DELAY_CNT : 4;
		unsigned int                                 : 4;
		unsigned int                  POST_DELAY_CNT : 5;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_VCE_CLKEN_CNTL {
	struct {
		unsigned int                PREFIX_DELAY_CNT : 4;
		unsigned int                                 : 4;
		unsigned int                  POST_DELAY_CNT : 5;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union STATE_CHANGE_STATUS__SI__VI {
	struct {
                unsigned int             STATE_CHANGE_STATUS : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union STATUS {
	struct {
                unsigned int                                 : 3;
                unsigned int                      INT_STATUS : 1;
                unsigned int                        CAP_LIST : 1;
                unsigned int                       PCI_66_EN : 1;
                unsigned int                                 : 1;
                unsigned int               FAST_BACK_CAPABLE : 1;
                unsigned int        MASTER_DATA_PARITY_ERROR : 1;
                unsigned int                   DEVSEL_TIMING : 2;
                unsigned int             SIGNAL_TARGET_ABORT : 1;
                unsigned int           RECEIVED_TARGET_ABORT : 1;
                unsigned int           RECEIVED_MASTER_ABORT : 1;
                unsigned int           SIGNALED_SYSTEM_ERROR : 1;
                unsigned int           PARITY_ERROR_DETECTED : 1;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union STREAM_SYNCHRONIZATION__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union STREAM_SYNCHRONIZATION__VI {
	struct {
		unsigned int        STREAM_0_SYNCHRONIZATION : 1;
		unsigned int        STREAM_1_SYNCHRONIZATION : 1;
		unsigned int        STREAM_2_SYNCHRONIZATION : 1;
		unsigned int        STREAM_3_SYNCHRONIZATION : 1;
		unsigned int        STREAM_4_SYNCHRONIZATION : 1;
		unsigned int        STREAM_5_SYNCHRONIZATION : 1;
		unsigned int        STREAM_6_SYNCHRONIZATION : 1;
		unsigned int        STREAM_7_SYNCHRONIZATION : 1;
		unsigned int        STREAM_8_SYNCHRONIZATION : 1;
		unsigned int        STREAM_9_SYNCHRONIZATION : 1;
		unsigned int       STREAM_10_SYNCHRONIZATION : 1;
		unsigned int       STREAM_11_SYNCHRONIZATION : 1;
		unsigned int       STREAM_12_SYNCHRONIZATION : 1;
		unsigned int       STREAM_13_SYNCHRONIZATION : 1;
		unsigned int       STREAM_14_SYNCHRONIZATION : 1;
		unsigned int       STREAM_15_SYNCHRONIZATION : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SUB_CLASS {
	struct {
		unsigned int                       SUB_CLASS : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SXIFCCG_DEBUG_REG0 {
	struct {
		unsigned int                position_address : 6;
		unsigned int                   point_address : 3;
		unsigned int    sx_pending_rd_state_var_indx : 3;
		unsigned int          sx_pending_rd_req_mask : 4;
		unsigned int               sx_pending_rd_pci : 10;
		unsigned int           sx_pending_rd_aux_sel : 2;
		unsigned int             sx_pending_rd_sp_id : 2;
		unsigned int           sx_pending_rd_aux_inc : 1;
		unsigned int           sx_pending_rd_advance : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SXIFCCG_DEBUG_REG1 {
	struct {
		unsigned int             available_positions : 7;
		unsigned int                 sx_receive_indx : 3;
		unsigned int        sx_pending_fifo_contents : 5;
		unsigned int statevar_bits_vs_out_misc_vec_ena : 1;
		unsigned int        statevar_bits_disable_sp : 4;
		unsigned int                         aux_sel : 2;
		unsigned int                sx_to_pa_empty_1 : 1;
		unsigned int                sx_to_pa_empty_0 : 1;
		unsigned int                  pasx_req_cnt_1 : 4;
		unsigned int                  pasx_req_cnt_0 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SXIFCCG_DEBUG_REG2 {
	struct {
		unsigned int                param_cache_base : 7;
		unsigned int                          sx_aux : 2;
		unsigned int                 sx_request_indx : 6;
		unsigned int         req_active_verts_loaded : 1;
		unsigned int                req_active_verts : 7;
		unsigned int     vgt_to_ccgen_state_var_indx : 3;
		unsigned int       vgt_to_ccgen_active_verts : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SXIFCCG_DEBUG_REG3 {
	struct {
		unsigned int                     ALWAYS_ZERO : 8;
		unsigned int    vertex_fifo_entriesavailable : 4;
		unsigned int statevar_bits_vs_out_ccdist1_vec_ena : 1;
		unsigned int statevar_bits_vs_out_ccdist0_vec_ena : 1;
		unsigned int             available_positions : 7;
		unsigned int                   current_state : 2;
		unsigned int               vertex_fifo_empty : 1;
		unsigned int                vertex_fifo_full : 1;
		unsigned int          sx0_receive_fifo_empty : 1;
		unsigned int           sx0_receive_fifo_full : 1;
		unsigned int         vgt_to_ccgen_fifo_empty : 1;
		unsigned int          vgt_to_ccgen_fifo_full : 1;
		unsigned int       ccgen_to_clipcc_fifo_full : 1;
		unsigned int          sx0_receive_fifo_write : 1;
		unsigned int           ccgen_to_clipcc_write : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_DEBUG_1__SI__CI {
	struct {
		unsigned int               SX_DB_QUAD_CREDIT : 7;
		unsigned int                      DEBUG_DATA : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_DEBUG_1__VI {
	struct {
		unsigned int               SX_DB_QUAD_CREDIT : 7;
		unsigned int                                 : 1;
		unsigned int   DISABLE_BLEND_OPT_DONT_RD_DST : 1;
		unsigned int        DISABLE_BLEND_OPT_BYPASS : 1;
		unsigned int DISABLE_BLEND_OPT_DISCARD_PIXEL : 1;
		unsigned int           DISABLE_QUAD_PAIR_OPT : 1;
		unsigned int         DISABLE_PIX_EN_ZERO_OPT : 1;
		unsigned int                      DEBUG_DATA : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_DEBUG_BUSY {
	struct {
		unsigned int              POS_FREE_OR_VALIDS : 1;
		unsigned int              POS_REQUESTER_BUSY : 1;
		unsigned int                      PA_SX_BUSY : 1;
		unsigned int                   POS_SCBD_BUSY : 1;
		unsigned int              POS_BANK3VAL3_BUSY : 1;
		unsigned int              POS_BANK3VAL2_BUSY : 1;
		unsigned int              POS_BANK3VAL1_BUSY : 1;
		unsigned int              POS_BANK3VAL0_BUSY : 1;
		unsigned int              POS_BANK2VAL3_BUSY : 1;
		unsigned int              POS_BANK2VAL2_BUSY : 1;
		unsigned int              POS_BANK2VAL1_BUSY : 1;
		unsigned int              POS_BANK2VAL0_BUSY : 1;
		unsigned int              POS_BANK1VAL3_BUSY : 1;
		unsigned int              POS_BANK1VAL2_BUSY : 1;
		unsigned int              POS_BANK1VAL1_BUSY : 1;
		unsigned int              POS_BANK1VAL0_BUSY : 1;
		unsigned int              POS_BANK0VAL3_BUSY : 1;
		unsigned int              POS_BANK0VAL2_BUSY : 1;
		unsigned int              POS_BANK0VAL1_BUSY : 1;
		unsigned int              POS_BANK0VAL0_BUSY : 1;
		unsigned int                 POS_INMUX_VALID : 1;
		unsigned int                 WRCTRL1_VALIDQ3 : 1;
		unsigned int                 WRCTRL1_VALIDQ2 : 1;
		unsigned int                 WRCTRL1_VALIDQ1 : 1;
		unsigned int                 WRCTRL0_VALIDQ3 : 1;
		unsigned int                 WRCTRL0_VALIDQ2 : 1;
		unsigned int                 WRCTRL0_VALIDQ1 : 1;
		unsigned int                     PCCMD_VALID : 1;
		unsigned int                    VDATA1_VALID : 1;
		unsigned int                    VDATA0_VALID : 1;
		unsigned int                   CMD_BUSYORVAL : 1;
		unsigned int                  ADDR_BUSYORVAL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_DEBUG_BUSY_2__CI__VI {
	struct {
                unsigned int                   COL_SCBD_BUSY : 1;
                unsigned int            COL_REQ3_FREECNT_NE0 : 1;
                unsigned int                   COL_REQ3_IDLE : 1;
                unsigned int                   COL_REQ3_BUSY : 1;
                unsigned int            COL_REQ2_FREECNT_NE0 : 1;
                unsigned int                   COL_REQ2_IDLE : 1;
                unsigned int                   COL_REQ2_BUSY : 1;
                unsigned int            COL_REQ1_FREECNT_NE0 : 1;
                unsigned int                   COL_REQ1_IDLE : 1;
                unsigned int                   COL_REQ1_BUSY : 1;
                unsigned int            COL_REQ0_FREECNT_NE0 : 1;
                unsigned int                   COL_REQ0_IDLE : 1;
                unsigned int                   COL_REQ0_BUSY : 1;
                unsigned int         COL_DBIF3_SENDFREE_BUSY : 1;
                unsigned int             COL_DBIF3_FIFO_BUSY : 1;
                unsigned int            COL_DBIF3_READ_VALID : 1;
                unsigned int         COL_DBIF2_SENDFREE_BUSY : 1;
                unsigned int             COL_DBIF2_FIFO_BUSY : 1;
                unsigned int            COL_DBIF2_READ_VALID : 1;
                unsigned int         COL_DBIF1_SENDFREE_BUSY : 1;
                unsigned int             COL_DBIF1_FIFO_BUSY : 1;
                unsigned int            COL_DBIF1_READ_VALID : 1;
                unsigned int         COL_DBIF0_SENDFREE_BUSY : 1;
                unsigned int             COL_DBIF0_FIFO_BUSY : 1;
                unsigned int            COL_DBIF0_READ_VALID : 1;
                unsigned int       COL_BUFF3_BANK3_VAL3_BUSY : 1;
                unsigned int       COL_BUFF3_BANK3_VAL2_BUSY : 1;
                unsigned int       COL_BUFF3_BANK3_VAL1_BUSY : 1;
                unsigned int       COL_BUFF3_BANK3_VAL0_BUSY : 1;
                unsigned int       COL_BUFF3_BANK2_VAL3_BUSY : 1;
                unsigned int       COL_BUFF3_BANK2_VAL2_BUSY : 1;
                unsigned int       COL_BUFF3_BANK2_VAL1_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_DEBUG_BUSY_2__SI {
	struct {
		unsigned int                   COL_SCBD_BUSY : 1;
		unsigned int                                 : 6;
		unsigned int            COL_REQ1_FREECNT_NE0 : 1;
		unsigned int                   COL_REQ1_IDLE : 1;
		unsigned int                   COL_REQ1_BUSY : 1;
		unsigned int            COL_REQ0_FREECNT_NE0 : 1;
		unsigned int                   COL_REQ0_IDLE : 1;
		unsigned int                   COL_REQ0_BUSY : 1;
		unsigned int                                 : 6;
		unsigned int         COL_DBIF1_SENDFREE_BUSY : 1;
		unsigned int             COL_DBIF1_FIFO_BUSY : 1;
		unsigned int            COL_DBIF1_READ_VALID : 1;
		unsigned int         COL_DBIF0_SENDFREE_BUSY : 1;
		unsigned int             COL_DBIF0_FIFO_BUSY : 1;
		unsigned int            COL_DBIF0_READ_VALID : 1;
		unsigned int       COL_BUFF3_BANK3_VAL3_BUSY : 1;
		unsigned int       COL_BUFF3_BANK3_VAL2_BUSY : 1;
		unsigned int       COL_BUFF3_BANK3_VAL1_BUSY : 1;
		unsigned int       COL_BUFF3_BANK3_VAL0_BUSY : 1;
		unsigned int       COL_BUFF3_BANK2_VAL3_BUSY : 1;
		unsigned int       COL_BUFF3_BANK2_VAL2_BUSY : 1;
		unsigned int       COL_BUFF3_BANK2_VAL1_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_DEBUG_BUSY_3 {
	struct {
		unsigned int       COL_BUFF3_BANK2_VAL0_BUSY : 1;
		unsigned int       COL_BUFF3_BANK1_VAL3_BUSY : 1;
		unsigned int       COL_BUFF3_BANK1_VAL2_BUSY : 1;
		unsigned int       COL_BUFF3_BANK1_VAL1_BUSY : 1;
		unsigned int       COL_BUFF3_BANK1_VAL0_BUSY : 1;
		unsigned int       COL_BUFF3_BANK0_VAL3_BUSY : 1;
		unsigned int       COL_BUFF3_BANK0_VAL2_BUSY : 1;
		unsigned int       COL_BUFF3_BANK0_VAL1_BUSY : 1;
		unsigned int       COL_BUFF3_BANK0_VAL0_BUSY : 1;
		unsigned int       COL_BUFF2_BANK3_VAL3_BUSY : 1;
		unsigned int       COL_BUFF2_BANK3_VAL2_BUSY : 1;
		unsigned int       COL_BUFF2_BANK3_VAL1_BUSY : 1;
		unsigned int       COL_BUFF2_BANK3_VAL0_BUSY : 1;
		unsigned int       COL_BUFF2_BANK2_VAL3_BUSY : 1;
		unsigned int       COL_BUFF2_BANK2_VAL2_BUSY : 1;
		unsigned int       COL_BUFF2_BANK2_VAL1_BUSY : 1;
		unsigned int       COL_BUFF2_BANK2_VAL0_BUSY : 1;
		unsigned int       COL_BUFF2_BANK1_VAL3_BUSY : 1;
		unsigned int       COL_BUFF2_BANK1_VAL2_BUSY : 1;
		unsigned int       COL_BUFF2_BANK1_VAL1_BUSY : 1;
		unsigned int       COL_BUFF2_BANK1_VAL0_BUSY : 1;
		unsigned int       COL_BUFF2_BANK0_VAL3_BUSY : 1;
		unsigned int       COL_BUFF2_BANK0_VAL2_BUSY : 1;
		unsigned int       COL_BUFF2_BANK0_VAL1_BUSY : 1;
		unsigned int       COL_BUFF2_BANK0_VAL0_BUSY : 1;
		unsigned int       COL_BUFF1_BANK3_VAL3_BUSY : 1;
		unsigned int       COL_BUFF1_BANK3_VAL2_BUSY : 1;
		unsigned int       COL_BUFF1_BANK3_VAL1_BUSY : 1;
		unsigned int       COL_BUFF1_BANK3_VAL0_BUSY : 1;
		unsigned int       COL_BUFF1_BANK2_VAL3_BUSY : 1;
		unsigned int       COL_BUFF1_BANK2_VAL2_BUSY : 1;
		unsigned int       COL_BUFF1_BANK2_VAL1_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_DEBUG_BUSY_4 {
	struct {
		unsigned int       COL_BUFF1_BANK2_VAL0_BUSY : 1;
		unsigned int       COL_BUFF1_BANK1_VAL3_BUSY : 1;
		unsigned int       COL_BUFF1_BANK1_VAL2_BUSY : 1;
		unsigned int       COL_BUFF1_BANK1_VAL1_BUSY : 1;
		unsigned int       COL_BUFF1_BANK1_VAL0_BUSY : 1;
		unsigned int       COL_BUFF1_BANK0_VAL3_BUSY : 1;
		unsigned int       COL_BUFF1_BANK0_VAL2_BUSY : 1;
		unsigned int       COL_BUFF1_BANK0_VAL1_BUSY : 1;
		unsigned int       COL_BUFF1_BANK0_VAL0_BUSY : 1;
		unsigned int       COL_BUFF0_BANK3_VAL3_BUSY : 1;
		unsigned int       COL_BUFF0_BANK3_VAL2_BUSY : 1;
		unsigned int       COL_BUFF0_BANK3_VAL1_BUSY : 1;
		unsigned int       COL_BUFF0_BANK3_VAL0_BUSY : 1;
		unsigned int       COL_BUFF0_BANK2_VAL3_BUSY : 1;
		unsigned int       COL_BUFF0_BANK2_VAL2_BUSY : 1;
		unsigned int       COL_BUFF0_BANK2_VAL1_BUSY : 1;
		unsigned int       COL_BUFF0_BANK2_VAL0_BUSY : 1;
		unsigned int       COL_BUFF0_BANK1_VAL3_BUSY : 1;
		unsigned int       COL_BUFF0_BANK1_VAL2_BUSY : 1;
		unsigned int       COL_BUFF0_BANK1_VAL1_BUSY : 1;
		unsigned int       COL_BUFF0_BANK1_VAL0_BUSY : 1;
		unsigned int       COL_BUFF0_BANK0_VAL3_BUSY : 1;
		unsigned int       COL_BUFF0_BANK0_VAL2_BUSY : 1;
		unsigned int       COL_BUFF0_BANK0_VAL1_BUSY : 1;
		unsigned int       COL_BUFF0_BANK0_VAL0_BUSY : 1;
		unsigned int                        RESERVED : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER0_SELECT {
	struct {
                unsigned int              PERFCOUNTER_SELECT : 10;
                unsigned int     PERFCOUNTER_SELECT1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int             PERFCOUNTER_SELECT2 : 10;
                unsigned int             PERFCOUNTER_SELECT3 : 10;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER1_SELECT {
	struct {
                unsigned int              PERFCOUNTER_SELECT : 10;
                unsigned int     PERFCOUNTER_SELECT1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER1_SELECT1__CI__VI {
	struct {
                unsigned int             PERFCOUNTER_SELECT2 : 10;
                unsigned int             PERFCOUNTER_SELECT3 : 10;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER2_SELECT {
	struct {
                unsigned int              PERFCOUNTER_SELECT : 10;
                unsigned int     PERFCOUNTER_SELECT1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PERFCOUNTER3_SELECT {
	struct {
                unsigned int              PERFCOUNTER_SELECT : 10;
                unsigned int     PERFCOUNTER_SELECT1__CI__VI : 10;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TARGET_AND_CURRENT_PROFILE_INDEX_1 {
	struct {
		unsigned int                CURR_VDDCI_INDEX : 4;
		unsigned int                TARG_VDDCI_INDEX : 4;
		unsigned int                 CURR_MVDD_INDEX : 4;
		unsigned int                 TARG_MVDD_INDEX : 4;
		unsigned int                 CURR_VDDC_INDEX : 4;
		unsigned int                 TARG_VDDC_INDEX : 4;
		unsigned int                 CURR_PCIE_INDEX : 4;
		unsigned int                 TARG_PCIE_INDEX : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TARGET_AND_CURRENT_PROFILE_INDEX__CI__VI {
	struct {
                unsigned int                    TARGET_STATE : 4;
                unsigned int                   CURRENT_STATE : 4;
                unsigned int                 CURR_MCLK_INDEX : 4;
                unsigned int                 TARG_MCLK_INDEX : 4;
                unsigned int                 CURR_SCLK_INDEX : 5;
                unsigned int                 TARG_SCLK_INDEX : 5;
                unsigned int                 CURR_LCLK_INDEX : 3;
                unsigned int                 TARG_LCLK_INDEX : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TARGET_AND_CURRENT_PROFILE_INDEX__SI {
	struct {
		unsigned int                    TARGET_STATE : 4;
		unsigned int                   CURRENT_STATE : 4;
		unsigned int                 CURR_MCLK_INDEX : 4;
		unsigned int                 TARG_MCLK_INDEX : 4;
		unsigned int                 CURR_SCLK_INDEX : 5;
		unsigned int                 TARG_SCLK_INDEX : 5;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_BC_BASE_ADDR {
	struct {
		unsigned int                         ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_BC_BASE_ADDR_HI__CI__VI {
	struct {
                unsigned int                         ADDRESS : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_CGTT_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_CNTL {
	struct {
                unsigned int             FX_XNACK_CREDIT__VI : 7;
                unsigned int                                 : 2;
                unsigned int             SQ_XNACK_CREDIT__VI : 4;
                unsigned int                  TC_DATA_CREDIT : 3;
                unsigned int                  ALIGNER_CREDIT : 5;
                unsigned int                                 : 1;
                unsigned int                  TD_FIFO_CREDIT : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_CNTL_AUX {
	struct {
                unsigned int            SCOAL_DSWIZZLE_N__VI : 1;
                unsigned int                    RESERVED__VI : 3;
                unsigned int            D16_PACK_DISABLE__VI : 1;
                unsigned int                                 : 11;
                unsigned int               ANISO_WEIGHT_MODE : 1;
                unsigned int             ANISO_RATIO_LUT__VI : 1;
                unsigned int                   ANISO_TAP__VI : 1;
                unsigned int          ANISO_MIP_ADJ_MODE__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_CS_BC_BASE_ADDR {
	struct {
		unsigned int                         ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_CS_BC_BASE_ADDR_HI__CI__VI {
	struct {
                unsigned int                         ADDRESS : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_DEBUG_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_DEBUG_INDEX {
	struct {
		unsigned int                           INDEX : 5;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_PERFCOUNTER0_SELECT {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                                 : 2;
                unsigned int               PERF_SEL1__CI__VI : 8;
                unsigned int                                 : 2;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int              PERF_MODE1__CI__VI : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 8;
                unsigned int                                 : 2;
                unsigned int                       PERF_SEL3 : 8;
                unsigned int                                 : 6;
                unsigned int                      PERF_MODE3 : 4;
                unsigned int                      PERF_MODE2 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_PERFCOUNTER1_SELECT {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                                 : 2;
                unsigned int               PERF_SEL1__CI__VI : 8;
                unsigned int                                 : 2;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int              PERF_MODE1__CI__VI : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_RESERVED_010C__CI__VI {
	struct {
                unsigned int                          Unused : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_SCRATCH {
	struct {
		unsigned int                         SCRATCH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TA_STATUS {
	struct {
		unsigned int                                 : 12;
		unsigned int                 FG_PFIFO_EMPTYB : 1;
		unsigned int                 FG_LFIFO_EMPTYB : 1;
		unsigned int                 FG_SFIFO_EMPTYB : 1;
		unsigned int                                 : 1;
		unsigned int                 FL_PFIFO_EMPTYB : 1;
		unsigned int                 FL_LFIFO_EMPTYB : 1;
		unsigned int                 FL_SFIFO_EMPTYB : 1;
		unsigned int                                 : 1;
		unsigned int                 FA_PFIFO_EMPTYB : 1;
		unsigned int                 FA_LFIFO_EMPTYB : 1;
		unsigned int                 FA_SFIFO_EMPTYB : 1;
		unsigned int                                 : 1;
		unsigned int                         IN_BUSY : 1;
		unsigned int                         FG_BUSY : 1;
		unsigned int                         LA_BUSY : 1;
		unsigned int                         FL_BUSY : 1;
		unsigned int                         TA_BUSY : 1;
		unsigned int                         FA_BUSY : 1;
		unsigned int                         AL_BUSY : 1;
		unsigned int                            BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_CGTT_SCLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_CTRL {
	struct {
		unsigned int                    HOLE_TIMEOUT : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE2 : 4;
                unsigned int                      PERF_MODE3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                       PERF_SEL1 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER0_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER1_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE2 : 4;
                unsigned int                      PERF_MODE3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                       PERF_SEL1 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER1_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER2_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                                 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER2_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER3_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                                 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCA_PERFCOUNTER3_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_CGTT_SCLK_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_CTRL {
	struct {
                unsigned int                      CACHE_SIZE : 2;
                unsigned int                            RATE : 2;
                unsigned int                WRITEBACK_MARGIN : 4;
                unsigned int  METADATA_LATENCY_FIFO_SIZE__VI : 4;
                unsigned int                   SRC_FIFO_SIZE : 4;
                unsigned int               LATENCY_FIFO_SIZE : 4;
                unsigned int     WB_OR_INV_ALL_VMIDS__CI__VI : 1;
                unsigned int                                 : 3;
                unsigned int                    MDC_SIZE__VI : 2;
                unsigned int             MDC_SECTOR_SIZE__VI : 2;
                unsigned int      MDC_SIDEBAND_FIFO_SIZE__VI : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_EDC_COUNTER__SI__CI {
	struct {
		unsigned int                       SEC_COUNT : 4;
		unsigned int                                 : 12;
		unsigned int                       DED_COUNT : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE2 : 4;
                unsigned int                      PERF_MODE3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                       PERF_SEL1 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER0_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER1_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE2 : 4;
                unsigned int                      PERF_MODE3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                       PERF_SEL1 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER1_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER2_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                                 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER2_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER3_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                                 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_PERFCOUNTER3_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_REDUNDANCY__CI__VI {
	struct {
                unsigned int                         MC_SEL0 : 1;
                unsigned int                         MC_SEL1 : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCI_CNTL_1 {
	struct {
		unsigned int              WBINVL1_NUM_CYCLES : 16;
		unsigned int                  REQ_FIFO_DEPTH : 8;
		unsigned int                 WDATA_RAM_DEPTH : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCI_CNTL_2 {
	struct {
		unsigned int             L1_INVAL_ON_WBINVL2 : 1;
		unsigned int                  TCA_MAX_CREDIT : 8;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCI_STATUS {
	struct {
		unsigned int                        TCI_BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_ADDR_CONFIG {
	struct {
		unsigned int                   NUM_TCC_BANKS : 4;
		unsigned int                       NUM_BANKS : 2;
		unsigned int                     COLHI_WIDTH : 3;
		unsigned int                  RB_SPLIT_COLHI : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_BUFFER_ADDR_HASH_CNTL {
	struct {
		unsigned int                    CHANNEL_BITS : 3;
		unsigned int                                 : 5;
		unsigned int                       BANK_BITS : 3;
		unsigned int                                 : 5;
		unsigned int               CHANNEL_XOR_COUNT : 3;
		unsigned int                                 : 5;
		unsigned int                  BANK_XOR_COUNT : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_CHAN_STEER_HI {
	struct {
		unsigned int                           CHAN8 : 4;
		unsigned int                           CHAN9 : 4;
		unsigned int                           CHANA : 4;
		unsigned int                           CHANB : 4;
		unsigned int                           CHANC : 4;
		unsigned int                           CHAND : 4;
		unsigned int                           CHANE : 4;
		unsigned int                           CHANF : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_CHAN_STEER_LO {
	struct {
		unsigned int                           CHAN0 : 4;
		unsigned int                           CHAN1 : 4;
		unsigned int                           CHAN2 : 4;
		unsigned int                           CHAN3 : 4;
		unsigned int                           CHAN4 : 4;
		unsigned int                           CHAN5 : 4;
		unsigned int                           CHAN6 : 4;
		unsigned int                           CHAN7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_CNTL {
	struct {
                unsigned int                       FORCE_HIT : 1;
                unsigned int                      FORCE_MISS : 1;
                unsigned int                         L1_SIZE : 2;
                unsigned int    FLAT_BUF_HASH_ENABLE__CI__VI : 1;
                unsigned int  FLAT_BUF_CACHE_SWIZZLE__CI__VI : 1;
                unsigned int                                 : 9;
                unsigned int             FORCE_EOW_TOTAL_CNT : 6;
                unsigned int                                 : 1;
                unsigned int            FORCE_EOW_TAGRAM_CNT : 6;
                unsigned int                   DISABLE_Z_MAP : 1;
                unsigned int           INV_ALL_VMIDS__CI__VI : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_CREDIT {
	struct {
		unsigned int                    LFIFO_CREDIT : 10;
		unsigned int                                 : 6;
		unsigned int                 REQ_FIFO_CREDIT : 7;
		unsigned int                                 : 6;
		unsigned int                       TD_CREDIT : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_EDC_COUNTER__SI__CI {
	struct {
		unsigned int                       SEC_COUNT : 4;
		unsigned int                                 : 12;
		unsigned int                       DED_COUNT : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_INVALIDATE {
	struct {
		unsigned int                           START : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE3 : 4;
                unsigned int                      PERF_MODE2 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                       PERF_SEL1 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER0_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER1_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE3 : 4;
                unsigned int                      PERF_MODE2 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                       PERF_SEL1 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER1_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER2_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                                 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER2_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER3_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                                 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                                 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_PERFCOUNTER3_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_STATUS {
	struct {
                unsigned int                        TCP_BUSY : 1;
                unsigned int                  INPUT_BUSY__VI : 1;
                unsigned int                   ADRS_BUSY__VI : 1;
                unsigned int                TAGRAMS_BUSY__VI : 1;
                unsigned int                  CNTRL_BUSY__VI : 1;
                unsigned int                  LFIFO_BUSY__VI : 1;
                unsigned int                   READ_BUSY__VI : 1;
                unsigned int                 FORMAT_BUSY__VI : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH0_ADDR_H__CI__VI {
	struct {
                unsigned int                            ADDR : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH0_ADDR_L__CI__VI {
	struct {
                unsigned int                                 : 6;
                unsigned int                            ADDR : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH0_CNTL__CI__VI {
	struct {
                unsigned int                            MASK : 24;
                unsigned int                            VMID : 4;
                unsigned int                         ATC__VI : 1;
                unsigned int                            MODE : 2;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH1_ADDR_H__CI__VI {
	struct {
                unsigned int                            ADDR : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH1_ADDR_L__CI__VI {
	struct {
                unsigned int                                 : 6;
                unsigned int                            ADDR : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH1_CNTL__CI__VI {
	struct {
                unsigned int                            MASK : 24;
                unsigned int                            VMID : 4;
                unsigned int                         ATC__VI : 1;
                unsigned int                            MODE : 2;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH2_ADDR_H__CI__VI {
	struct {
                unsigned int                            ADDR : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH2_ADDR_L__CI__VI {
	struct {
                unsigned int                                 : 6;
                unsigned int                            ADDR : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH2_CNTL__CI__VI {
	struct {
                unsigned int                            MASK : 24;
                unsigned int                            VMID : 4;
                unsigned int                         ATC__VI : 1;
                unsigned int                            MODE : 2;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH3_ADDR_H__CI__VI {
	struct {
                unsigned int                            ADDR : 16;
                unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH3_ADDR_L__CI__VI {
	struct {
                unsigned int                                 : 6;
                unsigned int                            ADDR : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_WATCH3_CNTL__CI__VI {
	struct {
                unsigned int                            MASK : 24;
                unsigned int                            VMID : 4;
                unsigned int                         ATC__VI : 1;
                unsigned int                            MODE : 2;
                unsigned int                           VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_CGTT_SCLK_CTRL__CI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_CTRL__CI {
	struct {
		unsigned int                            RATE : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER0_HI__CI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER0_LO__CI {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER0_SELECT1__CI {
	struct {
		unsigned int                       PERF_SEL2 : 10;
		unsigned int                       PERF_SEL3 : 10;
		unsigned int                                 : 4;
		unsigned int                      PERF_MODE2 : 4;
		unsigned int                      PERF_MODE3 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER0_SELECT__CI {
	struct {
		unsigned int                        PERF_SEL : 10;
		unsigned int                       PERF_SEL1 : 10;
		unsigned int                       CNTR_MODE : 4;
		unsigned int                      PERF_MODE1 : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER1_HI__CI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER1_LO__CI {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER1_SELECT__CI {
	struct {
		unsigned int                        PERF_SEL : 10;
		unsigned int                                 : 10;
		unsigned int                       CNTR_MODE : 4;
		unsigned int                                 : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER2_HI__CI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER2_LO__CI {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER2_SELECT__CI {
	struct {
		unsigned int                        PERF_SEL : 10;
		unsigned int                                 : 10;
		unsigned int                       CNTR_MODE : 4;
		unsigned int                                 : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER3_HI__CI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER3_LO__CI {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCS_PERFCOUNTER3_SELECT__CI {
	struct {
		unsigned int                        PERF_SEL : 10;
		unsigned int                                 : 10;
		unsigned int                       CNTR_MODE : 4;
		unsigned int                                 : 4;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TC_CFG_L1_LOAD_POLICY0__CI__VI {
	struct {
                unsigned int                        POLICY_0 : 2;
                unsigned int                        POLICY_1 : 2;
                unsigned int                        POLICY_2 : 2;
                unsigned int                        POLICY_3 : 2;
                unsigned int                        POLICY_4 : 2;
                unsigned int                        POLICY_5 : 2;
                unsigned int                        POLICY_6 : 2;
                unsigned int                        POLICY_7 : 2;
                unsigned int                        POLICY_8 : 2;
                unsigned int                        POLICY_9 : 2;
                unsigned int                       POLICY_10 : 2;
                unsigned int                       POLICY_11 : 2;
                unsigned int                       POLICY_12 : 2;
                unsigned int                       POLICY_13 : 2;
                unsigned int                       POLICY_14 : 2;
                unsigned int                       POLICY_15 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TC_CFG_L1_LOAD_POLICY1__CI__VI {
	struct {
                unsigned int                       POLICY_16 : 2;
                unsigned int                       POLICY_17 : 2;
                unsigned int                       POLICY_18 : 2;
                unsigned int                       POLICY_19 : 2;
                unsigned int                       POLICY_20 : 2;
                unsigned int                       POLICY_21 : 2;
                unsigned int                       POLICY_22 : 2;
                unsigned int                       POLICY_23 : 2;
                unsigned int                       POLICY_24 : 2;
                unsigned int                       POLICY_25 : 2;
                unsigned int                       POLICY_26 : 2;
                unsigned int                       POLICY_27 : 2;
                unsigned int                       POLICY_28 : 2;
                unsigned int                       POLICY_29 : 2;
                unsigned int                       POLICY_30 : 2;
                unsigned int                       POLICY_31 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TC_CFG_L1_STORE_POLICY__CI__VI {
	struct {
                unsigned int                        POLICY_0 : 1;
                unsigned int                        POLICY_1 : 1;
                unsigned int                        POLICY_2 : 1;
                unsigned int                        POLICY_3 : 1;
                unsigned int                        POLICY_4 : 1;
                unsigned int                        POLICY_5 : 1;
                unsigned int                        POLICY_6 : 1;
                unsigned int                        POLICY_7 : 1;
                unsigned int                        POLICY_8 : 1;
                unsigned int                        POLICY_9 : 1;
                unsigned int                       POLICY_10 : 1;
                unsigned int                       POLICY_11 : 1;
                unsigned int                       POLICY_12 : 1;
                unsigned int                       POLICY_13 : 1;
                unsigned int                       POLICY_14 : 1;
                unsigned int                       POLICY_15 : 1;
                unsigned int                       POLICY_16 : 1;
                unsigned int                       POLICY_17 : 1;
                unsigned int                       POLICY_18 : 1;
                unsigned int                       POLICY_19 : 1;
                unsigned int                       POLICY_20 : 1;
                unsigned int                       POLICY_21 : 1;
                unsigned int                       POLICY_22 : 1;
                unsigned int                       POLICY_23 : 1;
                unsigned int                       POLICY_24 : 1;
                unsigned int                       POLICY_25 : 1;
                unsigned int                       POLICY_26 : 1;
                unsigned int                       POLICY_27 : 1;
                unsigned int                       POLICY_28 : 1;
                unsigned int                       POLICY_29 : 1;
                unsigned int                       POLICY_30 : 1;
                unsigned int                       POLICY_31 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TC_CFG_L1_VOLATILE__CI__VI {
	struct {
                unsigned int                             VOL : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TC_CFG_L2_ATOMIC_POLICY__CI__VI {
	struct {
                unsigned int                        POLICY_0 : 2;
                unsigned int                        POLICY_1 : 2;
                unsigned int                        POLICY_2 : 2;
                unsigned int                        POLICY_3 : 2;
                unsigned int                        POLICY_4 : 2;
                unsigned int                        POLICY_5 : 2;
                unsigned int                        POLICY_6 : 2;
                unsigned int                        POLICY_7 : 2;
                unsigned int                        POLICY_8 : 2;
                unsigned int                        POLICY_9 : 2;
                unsigned int                       POLICY_10 : 2;
                unsigned int                       POLICY_11 : 2;
                unsigned int                       POLICY_12 : 2;
                unsigned int                       POLICY_13 : 2;
                unsigned int                       POLICY_14 : 2;
                unsigned int                       POLICY_15 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TC_CFG_L2_LOAD_POLICY0__CI__VI {
	struct {
                unsigned int                        POLICY_0 : 2;
                unsigned int                        POLICY_1 : 2;
                unsigned int                        POLICY_2 : 2;
                unsigned int                        POLICY_3 : 2;
                unsigned int                        POLICY_4 : 2;
                unsigned int                        POLICY_5 : 2;
                unsigned int                        POLICY_6 : 2;
                unsigned int                        POLICY_7 : 2;
                unsigned int                        POLICY_8 : 2;
                unsigned int                        POLICY_9 : 2;
                unsigned int                       POLICY_10 : 2;
                unsigned int                       POLICY_11 : 2;
                unsigned int                       POLICY_12 : 2;
                unsigned int                       POLICY_13 : 2;
                unsigned int                       POLICY_14 : 2;
                unsigned int                       POLICY_15 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TC_CFG_L2_LOAD_POLICY1__CI__VI {
	struct {
                unsigned int                       POLICY_16 : 2;
                unsigned int                       POLICY_17 : 2;
                unsigned int                       POLICY_18 : 2;
                unsigned int                       POLICY_19 : 2;
                unsigned int                       POLICY_20 : 2;
                unsigned int                       POLICY_21 : 2;
                unsigned int                       POLICY_22 : 2;
                unsigned int                       POLICY_23 : 2;
                unsigned int                       POLICY_24 : 2;
                unsigned int                       POLICY_25 : 2;
                unsigned int                       POLICY_26 : 2;
                unsigned int                       POLICY_27 : 2;
                unsigned int                       POLICY_28 : 2;
                unsigned int                       POLICY_29 : 2;
                unsigned int                       POLICY_30 : 2;
                unsigned int                       POLICY_31 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TC_CFG_L2_STORE_POLICY0__CI__VI {
	struct {
                unsigned int                        POLICY_0 : 2;
                unsigned int                        POLICY_1 : 2;
                unsigned int                        POLICY_2 : 2;
                unsigned int                        POLICY_3 : 2;
                unsigned int                        POLICY_4 : 2;
                unsigned int                        POLICY_5 : 2;
                unsigned int                        POLICY_6 : 2;
                unsigned int                        POLICY_7 : 2;
                unsigned int                        POLICY_8 : 2;
                unsigned int                        POLICY_9 : 2;
                unsigned int                       POLICY_10 : 2;
                unsigned int                       POLICY_11 : 2;
                unsigned int                       POLICY_12 : 2;
                unsigned int                       POLICY_13 : 2;
                unsigned int                       POLICY_14 : 2;
                unsigned int                       POLICY_15 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TC_CFG_L2_STORE_POLICY1__CI__VI {
	struct {
                unsigned int                       POLICY_16 : 2;
                unsigned int                       POLICY_17 : 2;
                unsigned int                       POLICY_18 : 2;
                unsigned int                       POLICY_19 : 2;
                unsigned int                       POLICY_20 : 2;
                unsigned int                       POLICY_21 : 2;
                unsigned int                       POLICY_22 : 2;
                unsigned int                       POLICY_23 : 2;
                unsigned int                       POLICY_24 : 2;
                unsigned int                       POLICY_25 : 2;
                unsigned int                       POLICY_26 : 2;
                unsigned int                       POLICY_27 : 2;
                unsigned int                       POLICY_28 : 2;
                unsigned int                       POLICY_29 : 2;
                unsigned int                       POLICY_30 : 2;
                unsigned int                       POLICY_31 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TC_CFG_L2_VOLATILE__CI__VI {
	struct {
                unsigned int                             VOL : 4;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_CGTT_CTRL {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 12;
		unsigned int                  SOFT_OVERRIDE7 : 1;
		unsigned int                  SOFT_OVERRIDE6 : 1;
		unsigned int                  SOFT_OVERRIDE5 : 1;
		unsigned int                  SOFT_OVERRIDE4 : 1;
		unsigned int                  SOFT_OVERRIDE3 : 1;
		unsigned int                  SOFT_OVERRIDE2 : 1;
		unsigned int                  SOFT_OVERRIDE1 : 1;
		unsigned int                  SOFT_OVERRIDE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_CNTL {
	struct {
                unsigned int                   SYNC_PHASE_SH : 2;
                unsigned int                                 : 2;
                unsigned int               SYNC_PHASE_VC_SMX : 2;
                unsigned int                                 : 2;
                unsigned int                    PAD_STALL_EN : 1;
                unsigned int                EXTEND_LDS_STALL : 2;
                unsigned int          LDS_STALL_PHASE_ADJUST : 2;
                unsigned int                                 : 2;
                unsigned int PRECISION_COMPATIBILITY__CI__VI : 1;
                unsigned int              GATHER4_FLOAT_MODE : 1;
                unsigned int                                 : 1;
                unsigned int                   LD_FLOAT_MODE : 1;
                unsigned int                GATHER4_DX9_MODE : 1;
                unsigned int  DISABLE_POWER_THROTTLE__CI__VI : 1;
                unsigned int        ENABLE_ROUND_TO_ZERO__VI : 1;
                unsigned int         DISABLE_D16_PACKING__VI : 1;
                unsigned int  DISABLE_2BIT_SIGNED_FORMAT__VI : 1;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_DEBUG_DATA__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_DEBUG_DATA__SI {
	struct {
		unsigned int                            DATA : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_DEBUG_INDEX {
	struct {
		unsigned int                           INDEX : 5;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_PERFCOUNTER0_SELECT {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                                 : 2;
                unsigned int               PERF_SEL1__CI__VI : 8;
                unsigned int                                 : 2;
                unsigned int               CNTR_MODE__CI__VI : 4;
                unsigned int              PERF_MODE1__CI__VI : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 8;
                unsigned int                                 : 2;
                unsigned int                       PERF_SEL3 : 8;
                unsigned int                                 : 6;
                unsigned int                      PERF_MODE3 : 4;
                unsigned int                      PERF_MODE2 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_PERFCOUNTER1_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_PERFCOUNTER1_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                                 : 2;
                unsigned int                       PERF_SEL1 : 8;
                unsigned int                                 : 2;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_SCRATCH {
	struct {
		unsigned int                         SCRATCH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_STATUS {
	struct {
		unsigned int                                 : 31;
		unsigned int                            BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_CLK_CNTL {
	struct {
                unsigned int                    CMON_CLK_SEL : 8;
                unsigned int                    TMON_CLK_SEL : 8;
                unsigned int          CTF_CLK_SHUTOFF_EN__VI : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_DEBUG {
	struct {
		unsigned int                       DEBUG_RDI : 5;
		unsigned int                         DEBUG_Z : 11;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_INT_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL0_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL10_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL11_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL12_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL13_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL14_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL15_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL1_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL2_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL3_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL4_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL5_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL6_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL7_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL8_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIL9_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR0_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR10_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR11_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR12_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR13_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR14_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR15_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR1_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR2_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR3_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR4_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR5_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR6_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR7_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR8_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_RDIR9_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_DEBUG {
	struct {
		unsigned int                       DEBUG_RDI : 5;
		unsigned int                         DEBUG_Z : 11;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_INT_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL0_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL10_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL11_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL12_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL13_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL14_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL15_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL1_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL2_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL3_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL4_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL5_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL6_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL7_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL8_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIL9_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR0_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR10_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR11_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR12_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR13_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR14_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR15_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR1_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR2_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR3_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR4_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR5_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR6_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR7_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR8_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_RDIR9_DATA {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_CNTL__SI__VI {
	struct {
                unsigned int                 TMDS_SYNC_PHASE : 1;
                unsigned int                                 : 3;
                unsigned int             TMDS_PIXEL_ENCODING : 1;
                unsigned int                                 : 3;
                unsigned int               TMDS_COLOR_FORMAT : 2;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_CONTROL0_FEEDBACK__SI__VI {
	struct {
                unsigned int   TMDS_CONTROL0_FEEDBACK_SELECT : 2;
                unsigned int                                 : 6;
                unsigned int    TMDS_CONTROL0_FEEDBACK_DELAY : 2;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_CONTROL_CHAR__SI__VI {
	struct {
                unsigned int       TMDS_CONTROL_CHAR0_OUT_EN : 1;
                unsigned int       TMDS_CONTROL_CHAR1_OUT_EN : 1;
                unsigned int       TMDS_CONTROL_CHAR2_OUT_EN : 1;
                unsigned int       TMDS_CONTROL_CHAR3_OUT_EN : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_CTL0_1_GEN_CNTL__SI__VI {
	struct {
                unsigned int              TMDS_CTL0_DATA_SEL : 4;
                unsigned int            TMDS_CTL0_DATA_DELAY : 3;
                unsigned int           TMDS_CTL0_DATA_INVERT : 1;
                unsigned int       TMDS_CTL0_DATA_MODULATION : 2;
                unsigned int     TMDS_CTL0_USE_FEEDBACK_PATH : 1;
                unsigned int          TMDS_CTL0_FB_SYNC_CONT : 1;
                unsigned int        TMDS_CTL0_PATTERN_OUT_EN : 1;
                unsigned int                                 : 3;
                unsigned int              TMDS_CTL1_DATA_SEL : 4;
                unsigned int            TMDS_CTL1_DATA_DELAY : 3;
                unsigned int           TMDS_CTL1_DATA_INVERT : 1;
                unsigned int       TMDS_CTL1_DATA_MODULATION : 2;
                unsigned int     TMDS_CTL1_USE_FEEDBACK_PATH : 1;
                unsigned int          TMDS_CTL1_FB_SYNC_CONT : 1;
                unsigned int        TMDS_CTL1_PATTERN_OUT_EN : 1;
                unsigned int                                 : 2;
                unsigned int            TMDS_2BIT_COUNTER_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_CTL2_3_GEN_CNTL__SI__VI {
	struct {
                unsigned int              TMDS_CTL2_DATA_SEL : 4;
                unsigned int            TMDS_CTL2_DATA_DELAY : 3;
                unsigned int           TMDS_CTL2_DATA_INVERT : 1;
                unsigned int       TMDS_CTL2_DATA_MODULATION : 2;
                unsigned int     TMDS_CTL2_USE_FEEDBACK_PATH : 1;
                unsigned int          TMDS_CTL2_FB_SYNC_CONT : 1;
                unsigned int        TMDS_CTL2_PATTERN_OUT_EN : 1;
                unsigned int                                 : 3;
                unsigned int              TMDS_CTL3_DATA_SEL : 4;
                unsigned int            TMDS_CTL3_DATA_DELAY : 3;
                unsigned int           TMDS_CTL3_DATA_INVERT : 1;
                unsigned int       TMDS_CTL3_DATA_MODULATION : 2;
                unsigned int     TMDS_CTL3_USE_FEEDBACK_PATH : 1;
                unsigned int          TMDS_CTL3_FB_SYNC_CONT : 1;
                unsigned int        TMDS_CTL3_PATTERN_OUT_EN : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_CTL_BITS__SI__VI {
	struct {
                unsigned int                       TMDS_CTL0 : 1;
                unsigned int                                 : 7;
                unsigned int                       TMDS_CTL1 : 1;
                unsigned int                                 : 7;
                unsigned int                       TMDS_CTL2 : 1;
                unsigned int                                 : 7;
                unsigned int                       TMDS_CTL3 : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_DCBALANCER_CONTROL__SI__VI {
	struct {
                unsigned int              TMDS_DCBALANCER_EN : 1;
                unsigned int                                 : 3;
                unsigned int              TMDS_SYNC_DCBAL_EN : 3;
                unsigned int                                 : 1;
                unsigned int         TMDS_DCBALANCER_TEST_EN : 1;
                unsigned int                                 : 7;
                unsigned int         TMDS_DCBALANCER_TEST_IN : 4;
                unsigned int                                 : 4;
                unsigned int           TMDS_DCBALANCER_FORCE : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_DEBUG__SI__VI {
	struct {
                unsigned int                   TMDS_DEBUG_EN : 1;
                unsigned int                                 : 7;
                unsigned int                TMDS_DEBUG_HSYNC : 1;
                unsigned int             TMDS_DEBUG_HSYNC_EN : 1;
                unsigned int                                 : 6;
                unsigned int                TMDS_DEBUG_VSYNC : 1;
                unsigned int             TMDS_DEBUG_VSYNC_EN : 1;
                unsigned int                                 : 6;
                unsigned int                   TMDS_DEBUG_DE : 1;
                unsigned int                TMDS_DEBUG_DE_EN : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_STEREOSYNC_CTL_SEL__SI__VI {
	struct {
                unsigned int         TMDS_STEREOSYNC_CTL_SEL : 2;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_SYNC_CHAR_PATTERN_0_1__SI__VI {
	struct {
                unsigned int         TMDS_SYNC_CHAR_PATTERN0 : 10;
                unsigned int                                 : 6;
                unsigned int         TMDS_SYNC_CHAR_PATTERN1 : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TMDS_SYNC_CHAR_PATTERN_2_3__SI__VI {
	struct {
                unsigned int         TMDS_SYNC_CHAR_PATTERN2 : 10;
                unsigned int                                 : 6;
                unsigned int         TMDS_SYNC_CHAR_PATTERN3 : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_DATA_SYNCHRONIZATION__SI {
	struct {
		unsigned int                  UNIPHY_DSYNSEL : 1;
		unsigned int                                 : 3;
		unsigned int               UNIPHY_DSYN_LEVEL : 2;
		unsigned int               UNIPHY_DSYN_ERROR : 1;
		unsigned int                                 : 1;
		unsigned int            UNIPHY_SOURCE_SELECT : 1;
		unsigned int                                 : 3;
		unsigned int              UNIPHY_LINK_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int          UNIPHY_DUAL_LINK_PHASE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_DATA_SYNCHRONIZATION__VI {
	struct {
		unsigned int                  UNIPHY_DSYNSEL : 1;
		unsigned int                                 : 3;
		unsigned int               UNIPHY_DSYN_LEVEL : 2;
		unsigned int               UNIPHY_DSYN_ERROR : 1;
		unsigned int                                 : 1;
		unsigned int            UNIPHY_SOURCE_SELECT : 1;
		unsigned int                                 : 7;
		unsigned int          UNIPHY_DUAL_LINK_PHASE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKA__SI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKA : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKA : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKA : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKA_AK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKA : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKA : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKA : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKA__VI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKA : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKA : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKA : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKA_AK : 1;
		unsigned int                                 : 5;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKA : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKA : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKA : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA : 1;
		unsigned int                                 : 1;
		unsigned int         UNIPHY_IMPCAL_SEL_LINKA : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKB__SI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKB : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKB : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKB : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKB_AK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKB : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKB : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKB : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKB__VI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKB : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKB : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKB : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKB_AK : 1;
		unsigned int                                 : 5;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKB : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKB : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKB : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB : 1;
		unsigned int                                 : 1;
		unsigned int         UNIPHY_IMPCAL_SEL_LINKB : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKC__SI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKC : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKC : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKC : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKC_AK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKC : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKC : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKC : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKC__VI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKC : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKC : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKC : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKC_AK : 1;
		unsigned int                                 : 5;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKC : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKC : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKC : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC : 1;
		unsigned int                                 : 1;
		unsigned int         UNIPHY_IMPCAL_SEL_LINKC : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKD__SI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKD : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKD : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKD : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKD_AK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKD : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKD : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKD : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKD__VI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKD : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKD : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKD : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKD_AK : 1;
		unsigned int                                 : 5;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKD : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKD : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKD : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD : 1;
		unsigned int                                 : 1;
		unsigned int         UNIPHY_IMPCAL_SEL_LINKD : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKE__SI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKE : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKE : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKE : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKE_AK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKE : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKE : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKE : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKE__VI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKE : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKE : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKE : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKE_AK : 1;
		unsigned int                                 : 5;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKE : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKE : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKE : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE : 1;
		unsigned int                                 : 1;
		unsigned int         UNIPHY_IMPCAL_SEL_LINKE : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKF__SI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKF : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKF : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKF : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKF_AK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKF : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKF : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKF : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_LINKF__VI {
	struct {
		unsigned int      UNIPHY_IMPCAL_ENABLE_LINKF : 1;
		unsigned int                                 : 7;
		unsigned int      UNIPHY_IMPCAL_CALOUT_LINKF : 1;
		unsigned int       UNIPHY_CALOUT_ERROR_LINKF : 1;
		unsigned int    UNIPHY_CALOUT_ERROR_LINKF_AK : 1;
		unsigned int                                 : 5;
		unsigned int       UNIPHY_IMPCAL_VALUE_LINKF : 4;
		unsigned int  UNIPHY_IMPCAL_STEP_DELAY_LINKF : 4;
		unsigned int    UNIPHY_IMPCAL_OVERRIDE_LINKF : 4;
		unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF : 1;
		unsigned int                                 : 1;
		unsigned int         UNIPHY_IMPCAL_SEL_LINKF : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_PERIOD__SI__VI {
	struct {
                unsigned int            UNIPHY_IMPCAL_PERIOD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_REG_TEST_OUTPUT__SI {
	struct {
		unsigned int                UNIPHY_TEST_CNTL : 4;
		unsigned int                                 : 6;
		unsigned int                                 : 2;
		unsigned int                                 : 1;
		unsigned int           UNIPHY_DIG_BIST_RESET : 1;
		unsigned int                                 : 2;
		unsigned int           UNIPHY_DIG_BIST_ERROR : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_REG_TEST_OUTPUT__VI {
	struct {
		unsigned int                UNIPHY_TEST_CNTL : 5;
		unsigned int            UNIPHY_PLL_TEST_VCTL : 4;
		unsigned int        UNIPHY_PLL_TEST_SSAMP_EN : 1;
		unsigned int      UNIPHY_PLL_TEST_UNLOCK_CLR : 1;
		unsigned int                                 : 4;
		unsigned int           UNIPHY_DIG_BIST_RESET : 1;
		unsigned int             UNIPHY_DIG_BIST_SEL : 1;
		unsigned int             UNIPHY_TEST_VCTL_EN : 1;
		unsigned int                                 : 2;
		unsigned int           UNIPHY_DIG_BIST_ERROR : 5;
		unsigned int        UNIPHY_PLL_TEST_VCTL_ADC : 3;
		unsigned int       UNIPHY_PLL_TEST_FREQ_LOCK : 1;
		unsigned int             UNIPHY_PLL_INTRESET : 1;
		unsigned int   UNIPHY_PLL_TEST_UNLOCK_STICKY : 1;
		unsigned int            UNIPHY_PLL_TEST_LOCK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union URGENCY_STAT__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 12;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union USER_SQC_BANK_DISABLE {
	struct {
                unsigned int                                 : 16;
                unsigned int               SQC0_BANK_DISABLE : 4;
                unsigned int               SQC1_BANK_DISABLE : 4;
                unsigned int       SQC2_BANK_DISABLE__CI__VI : 4;
                unsigned int       SQC3_BANK_DISABLE__CI__VI : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CGC_CTRL__SI {
	struct {
		unsigned int                  DYN_CLOCK_MODE : 1;
		unsigned int                                 : 7;
		unsigned int                   CLK_OFF_DELAY : 4;
		unsigned int              CLK_GATE_DLY_TIMER : 4;
		unsigned int                        SYS_MODE : 1;
		unsigned int                       UDEC_MODE : 1;
		unsigned int                      MPEG2_MODE : 1;
		unsigned int                       REGS_MODE : 1;
		unsigned int                        RBC_MODE : 1;
		unsigned int                     LMI_MC_MODE : 1;
		unsigned int                    LMI_UMC_MODE : 1;
		unsigned int                       IDCT_MODE : 1;
		unsigned int                       MPRD_MODE : 1;
		unsigned int                        MPC_MODE : 1;
		unsigned int                       LBSI_MODE : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CGC_CTRL__VI {
	struct {
		unsigned int                  DYN_CLOCK_MODE : 1;
		unsigned int                      JPEG2_MODE : 1;
		unsigned int              CLK_GATE_DLY_TIMER : 4;
		unsigned int                   CLK_OFF_DELAY : 5;
		unsigned int                    UDEC_RE_MODE : 1;
		unsigned int                    UDEC_CM_MODE : 1;
		unsigned int                    UDEC_IT_MODE : 1;
		unsigned int                    UDEC_DB_MODE : 1;
		unsigned int                    UDEC_MP_MODE : 1;
		unsigned int                        SYS_MODE : 1;
		unsigned int                       UDEC_MODE : 1;
		unsigned int                      MPEG2_MODE : 1;
		unsigned int                       REGS_MODE : 1;
		unsigned int                        RBC_MODE : 1;
		unsigned int                     LMI_MC_MODE : 1;
		unsigned int                    LMI_UMC_MODE : 1;
		unsigned int                       IDCT_MODE : 1;
		unsigned int                       MPRD_MODE : 1;
		unsigned int                        MPC_MODE : 1;
		unsigned int                       LBSI_MODE : 1;
		unsigned int                      LRBBM_MODE : 1;
		unsigned int                        WCB_MODE : 1;
		unsigned int                       VCPU_MODE : 1;
		unsigned int                       SCPU_MODE : 1;
		unsigned int                       JPEG_MODE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CGC_GATE__SI__VI {
	struct {
                unsigned int                             SYS : 1;
                unsigned int                            UDEC : 1;
                unsigned int                           MPEG2 : 1;
                unsigned int                            REGS : 1;
                unsigned int                             RBC : 1;
                unsigned int                          LMI_MC : 1;
                unsigned int                         LMI_UMC : 1;
                unsigned int                            IDCT : 1;
                unsigned int                            MPRD : 1;
                unsigned int                             MPC : 1;
                unsigned int                            LBSI : 1;
                unsigned int                       LRBBM__VI : 1;
                unsigned int                     UDEC_RE__VI : 1;
                unsigned int                     UDEC_CM__VI : 1;
                unsigned int                     UDEC_IT__VI : 1;
                unsigned int                     UDEC_DB__VI : 1;
                unsigned int                     UDEC_MP__VI : 1;
                unsigned int                         WCB__VI : 1;
                unsigned int                        VCPU__VI : 1;
                unsigned int                        SCPU__VI : 1;
                unsigned int                        JPEG__VI : 1;
                unsigned int                       JPEG2__VI : 1;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CGC_STATUS__SI__VI {
	struct {
                unsigned int                        SYS_SCLK : 1;
                unsigned int                        SYS_DCLK : 1;
                unsigned int                        SYS_VCLK : 1;
                unsigned int                       UDEC_SCLK : 1;
                unsigned int                       UDEC_DCLK : 1;
                unsigned int                       UDEC_VCLK : 1;
                unsigned int                      MPEG2_SCLK : 1;
                unsigned int                      MPEG2_DCLK : 1;
                unsigned int                      MPEG2_VCLK : 1;
                unsigned int                       REGS_SCLK : 1;
                unsigned int                       REGS_VCLK : 1;
                unsigned int                        RBC_SCLK : 1;
                unsigned int                     LMI_MC_SCLK : 1;
                unsigned int                    LMI_UMC_SCLK : 1;
                unsigned int                       IDCT_SCLK : 1;
                unsigned int                       IDCT_VCLK : 1;
                unsigned int                       MPRD_SCLK : 1;
                unsigned int                       MPRD_DCLK : 1;
                unsigned int                       MPRD_VCLK : 1;
                unsigned int                        MPC_SCLK : 1;
                unsigned int                        MPC_DCLK : 1;
                unsigned int                       LBSI_SCLK : 1;
                unsigned int                       LBSI_VCLK : 1;
                unsigned int                  LRBBM_SCLK__VI : 1;
                unsigned int                    WCB_SCLK__VI : 1;
                unsigned int                   VCPU_SCLK__VI : 1;
                unsigned int                   VCPU_VCLK__VI : 1;
                unsigned int                   SCPU_SCLK__VI : 1;
                unsigned int                   SCPU_VCLK__VI : 1;
                unsigned int                                 : 1;
                unsigned int                 JPEG_ACTIVE__VI : 1;
                unsigned int              ALL_DEC_ACTIVE__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CONFIG {
	struct {
		unsigned int                                 : 8;
		unsigned int                   UVD_RDREQ_URG : 4;
		unsigned int                                 : 4;
		unsigned int                    UVD_REQ_TRAN : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CONTEXT_ID__SI__VI {
	struct {
                unsigned int                      CONTEXT_ID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CTX_DATA__SI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CTX_INDEX__SI__VI {
	struct {
                unsigned int                           INDEX : 9;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_ENGINE_CNTL__SI__VI {
	struct {
                unsigned int                    ENGINE_START : 1;
                unsigned int               ENGINE_START_MODE : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_GPCOM_VCPU_CMD__SI__VI {
	struct {
                unsigned int                        CMD_SEND : 1;
                unsigned int                             CMD : 30;
                unsigned int                      CMD_SOURCE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_GPCOM_VCPU_DATA0__SI__VI {
	struct {
                unsigned int                           DATA0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_GPCOM_VCPU_DATA1__SI__VI {
	struct {
                unsigned int                           DATA1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_ADDR_EXT__SI__VI {
	struct {
                unsigned int                   VCPU_ADDR_EXT : 4;
                unsigned int                     CM_ADDR_EXT : 4;
                unsigned int                     IT_ADDR_EXT : 4;
                unsigned int                VCPU_VM_ADDR_EXT : 4;
                unsigned int                 RE_ADDR_EXT__VI : 4;
                unsigned int                 MP_ADDR_EXT__VI : 4;
                unsigned int           VCPU_NC0_ADDR_EXT__VI : 4;
                unsigned int           VCPU_NC1_ADDR_EXT__VI : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_CACHE_CTRL__SI__VI {
	struct {
                unsigned int                           IT_EN : 1;
                unsigned int                        IT_FLUSH : 1;
                unsigned int                           CM_EN : 1;
                unsigned int                        CM_FLUSH : 1;
                unsigned int                         VCPU_EN : 1;
                unsigned int                      VCPU_FLUSH : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_CTRL2__SI__VI {
	struct {
                unsigned int                         SPH_DIS : 1;
                unsigned int                       STALL_ARB : 1;
                unsigned int               ASSERT_UMC_URGENT : 1;
                unsigned int                 MASK_UMC_URGENT : 1;
                unsigned int               MCIF_WR_WATERMARK : 3;
                unsigned int           DRCITF_BUBBLE_FIX_DIS : 1;
                unsigned int                   STALL_ARB_UMC : 1;
                unsigned int              MC_READ_ID_SEL__VI : 2;
                unsigned int             MC_WRITE_ID_SEL__VI : 2;
                unsigned int             VCPU_NC0_EXT_EN__VI : 1;
                unsigned int             VCPU_NC1_EXT_EN__VI : 1;
                unsigned int            SPU_EXTRA_CID_EN__VI : 1;
                unsigned int               RE_OFFLOAD_EN__VI : 1;
                unsigned int      RE_OFLD_MIF_WR_REQ_NUM__VI : 8;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_CTRL__SI {
	struct {
		unsigned int               WRITE_CLEAN_TIMER : 8;
		unsigned int            WRITE_CLEAN_TIMER_EN : 1;
		unsigned int                        REQ_MODE : 1;
		unsigned int                                 : 1;
		unsigned int                ASSERT_MC_URGENT : 1;
		unsigned int                  MASK_MC_URGENT : 1;
		unsigned int               DATA_COHERENCY_EN : 1;
		unsigned int                       CRC_RESET : 1;
		unsigned int                         CRC_SEL : 5;
		unsigned int             DISABLE_ON_FWV_FAIL : 1;
		unsigned int          VCPU_DATA_COHERENCY_EN : 1;
		unsigned int            CM_DATA_COHERENCY_EN : 1;
		unsigned int         DB_DB_DATA_COHERENCY_EN : 1;
		unsigned int         DB_IT_DATA_COHERENCY_EN : 1;
		unsigned int         IT_IT_DATA_COHERENCY_EN : 1;
		unsigned int                             RFU : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_CTRL__VI {
	struct {
		unsigned int               WRITE_CLEAN_TIMER : 8;
		unsigned int            WRITE_CLEAN_TIMER_EN : 1;
		unsigned int                        REQ_MODE : 1;
		unsigned int                                 : 1;
		unsigned int                ASSERT_MC_URGENT : 1;
		unsigned int                  MASK_MC_URGENT : 1;
		unsigned int               DATA_COHERENCY_EN : 1;
		unsigned int                       CRC_RESET : 1;
		unsigned int                         CRC_SEL : 5;
		unsigned int             DISABLE_ON_FWV_FAIL : 1;
		unsigned int          VCPU_DATA_COHERENCY_EN : 1;
		unsigned int            CM_DATA_COHERENCY_EN : 1;
		unsigned int         DB_DB_DATA_COHERENCY_EN : 1;
		unsigned int         DB_IT_DATA_COHERENCY_EN : 1;
		unsigned int         IT_IT_DATA_COHERENCY_EN : 1;
		unsigned int       MIF_MIF_DATA_COHERENCY_EN : 1;
		unsigned int                             RFU : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_EXT40_ADDR__SI__VI {
	struct {
                unsigned int                            ADDR : 8;
                unsigned int                                 : 8;
                unsigned int                           INDEX : 5;
                unsigned int                                 : 10;
                unsigned int                      WRITE_ADDR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_STATUS__SI__VI {
	struct {
                unsigned int                      READ_CLEAN : 1;
                unsigned int                     WRITE_CLEAN : 1;
                unsigned int                 WRITE_CLEAN_RAW : 1;
                unsigned int            VCPU_LMI_WRITE_CLEAN : 1;
                unsigned int                  UMC_READ_CLEAN : 1;
                unsigned int                 UMC_WRITE_CLEAN : 1;
                unsigned int             UMC_WRITE_CLEAN_RAW : 1;
                unsigned int            PENDING_UVD_MC_WRITE : 1;
                unsigned int                  READ_CLEAN_RAW : 1;
                unsigned int              UMC_READ_CLEAN_RAW : 1;
                unsigned int                    UMC_UVD_IDLE : 1;
                unsigned int                    UMC_AVP_IDLE : 1;
                unsigned int               ADP_MC_READ_CLEAN : 1;
                unsigned int              ADP_UMC_READ_CLEAN : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_SWAP_CNTL__SI__VI {
	struct {
                unsigned int                      RB_MC_SWAP : 2;
                unsigned int                      IB_MC_SWAP : 2;
                unsigned int                 RB_RPTR_MC_SWAP : 2;
                unsigned int                  VCPU_R_MC_SWAP : 2;
                unsigned int                  VCPU_W_MC_SWAP : 2;
                unsigned int                      CM_MC_SWAP : 2;
                unsigned int                      IT_MC_SWAP : 2;
                unsigned int                    DB_R_MC_SWAP : 2;
                unsigned int                    DB_W_MC_SWAP : 2;
                unsigned int                     CSM_MC_SWAP : 2;
                unsigned int                                 : 2;
                unsigned int                MP_REF16_MC_SWAP : 2;
                unsigned int                     DBW_MC_SWAP : 2;
                unsigned int                   RB_WR_MC_SWAP : 2;
                unsigned int                  RE_MC_SWAP__VI : 2;
                unsigned int                  MP_MC_SWAP__VI : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MASTINT_EN__SI__VI {
	struct {
                unsigned int                     OVERRUN_RST : 1;
                unsigned int                         VCPU_EN : 1;
                unsigned int                          SYS_EN : 1;
                unsigned int                                 : 1;
                unsigned int                     INT_OVERRUN : 19;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MPC_CNTL__SI__VI {
	struct {
                unsigned int                                 : 3;
                unsigned int                REPLACEMENT_MODE : 3;
                unsigned int                        PERF_RST : 1;
                unsigned int                                 : 1;
                unsigned int                         DBG_MUX : 4;
                unsigned int                                 : 4;
                unsigned int                      AVE_WEIGHT : 2;
                unsigned int                       URGENT_EN : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MPC_SET_ALU__SI__VI {
	struct {
                unsigned int                           FUNCT : 3;
                unsigned int                                 : 1;
                unsigned int                         OPERAND : 8;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MPC_SET_MUXA0__SI__VI {
	struct {
                unsigned int                          VARA_0 : 6;
                unsigned int                          VARA_1 : 6;
                unsigned int                          VARA_2 : 6;
                unsigned int                          VARA_3 : 6;
                unsigned int                          VARA_4 : 6;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MPC_SET_MUXA1__SI__VI {
	struct {
                unsigned int                          VARA_5 : 6;
                unsigned int                          VARA_6 : 6;
                unsigned int                          VARA_7 : 6;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MPC_SET_MUXB0__SI__VI {
	struct {
                unsigned int                          VARB_0 : 6;
                unsigned int                          VARB_1 : 6;
                unsigned int                          VARB_2 : 6;
                unsigned int                          VARB_3 : 6;
                unsigned int                          VARB_4 : 6;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MPC_SET_MUXB1__SI__VI {
	struct {
                unsigned int                          VARB_5 : 6;
                unsigned int                          VARB_6 : 6;
                unsigned int                          VARB_7 : 6;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MPC_SET_MUX__SI__VI {
	struct {
                unsigned int                           SET_0 : 3;
                unsigned int                           SET_1 : 3;
                unsigned int                           SET_2 : 3;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MP_SWAP_CNTL__SI__VI {
	struct {
                unsigned int                 MP_REF0_MC_SWAP : 2;
                unsigned int                 MP_REF1_MC_SWAP : 2;
                unsigned int                 MP_REF2_MC_SWAP : 2;
                unsigned int                 MP_REF3_MC_SWAP : 2;
                unsigned int                 MP_REF4_MC_SWAP : 2;
                unsigned int                 MP_REF5_MC_SWAP : 2;
                unsigned int                 MP_REF6_MC_SWAP : 2;
                unsigned int                 MP_REF7_MC_SWAP : 2;
                unsigned int                 MP_REF8_MC_SWAP : 2;
                unsigned int                 MP_REF9_MC_SWAP : 2;
                unsigned int                MP_REF10_MC_SWAP : 2;
                unsigned int                MP_REF11_MC_SWAP : 2;
                unsigned int                MP_REF12_MC_SWAP : 2;
                unsigned int                MP_REF13_MC_SWAP : 2;
                unsigned int                MP_REF14_MC_SWAP : 2;
                unsigned int                MP_REF15_MC_SWAP : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_RBC_IB_BASE__SI {
	struct {
		unsigned int                                 : 6;
		unsigned int                         IB_BASE : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_RBC_IB_SIZE__SI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int                         IB_SIZE : 19;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_RBC_RB_BASE__SI {
	struct {
		unsigned int                                 : 6;
		unsigned int                         RB_BASE : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_RBC_RB_CNTL__SI__VI {
	struct {
                unsigned int                        RB_BUFSZ : 5;
                unsigned int                                 : 3;
                unsigned int                        RB_BLKSZ : 5;
                unsigned int                                 : 3;
                unsigned int                     RB_NO_FETCH : 1;
                unsigned int                                 : 3;
                unsigned int                 RB_WPTR_POLL_EN : 1;
                unsigned int                                 : 3;
                unsigned int                    RB_NO_UPDATE : 1;
                unsigned int                                 : 3;
                unsigned int                   RB_RPTR_WR_EN : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_RBC_RB_RPTR_ADDR__SI__VI {
	struct {
                unsigned int                    RB_RPTR_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_RBC_RB_RPTR__SI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int                         RB_RPTR : 19;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_RBC_RB_WPTR__SI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int                         RB_WPTR : 19;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SEMA_ADDR_HIGH__SI__VI {
	struct {
                unsigned int                      ADDR_42_23 : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SEMA_ADDR_LOW__SI__VI {
	struct {
                unsigned int                       ADDR_22_3 : 20;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SEMA_CMD__SI__VI {
	struct {
                unsigned int                         REQ_CMD : 4;
                unsigned int                        WR_PHASE : 2;
                unsigned int                            MODE : 1;
                unsigned int                     VMID_EN__VI : 1;
                unsigned int                        VMID__VI : 4;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SEMA_CNTL__SI__VI {
	struct {
                unsigned int                    SEMAPHORE_EN : 1;
                unsigned int               ADVANCED_MODE_DIS : 1;
                unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SI__VI {
	struct {
                unsigned int            SIGNAL_INCOMPLETE_EN : 1;
                unsigned int         SIGNAL_INCOMPLETE_COUNT : 20;
                unsigned int                                 : 3;
                unsigned int                    RESEND_TIMER : 3;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SEMA_TIMEOUT_STATUS__SI__VI {
	struct {
                unsigned int SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT : 1;
                unsigned int SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT : 1;
                unsigned int SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT : 1;
                unsigned int         SEMAPHORE_TIMEOUT_CLEAR : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__SI__VI {
	struct {
                unsigned int                   WAIT_FAULT_EN : 1;
                unsigned int                WAIT_FAULT_COUNT : 20;
                unsigned int                                 : 3;
                unsigned int                    RESEND_TIMER : 3;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__SI__VI {
	struct {
                unsigned int              WAIT_INCOMPLETE_EN : 1;
                unsigned int           WAIT_INCOMPLETE_COUNT : 20;
                unsigned int                                 : 3;
                unsigned int                    RESEND_TIMER : 3;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SOFT_RESET__SI {
	struct {
		unsigned int                  RBC_SOFT_RESET : 1;
		unsigned int                 LBSI_SOFT_RESET : 1;
		unsigned int                  LMI_SOFT_RESET : 1;
		unsigned int                 VCPU_SOFT_RESET : 1;
		unsigned int                 UDEC_SOFT_RESET : 1;
		unsigned int                  CSM_SOFT_RESET : 1;
		unsigned int                  CXW_SOFT_RESET : 1;
		unsigned int                  TAP_SOFT_RESET : 1;
		unsigned int                  MPC_SOFT_RESET : 1;
		unsigned int                  FWV_SOFT_RESET : 1;
		unsigned int                   IH_SOFT_RESET : 1;
		unsigned int                 MPRD_SOFT_RESET : 1;
		unsigned int                 IDCT_SOFT_RESET : 1;
		unsigned int              LMI_UMC_SOFT_RESET : 1;
		unsigned int                  SPH_SOFT_RESET : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SOFT_RESET__VI {
	struct {
		unsigned int                  RBC_SOFT_RESET : 1;
		unsigned int                 LBSI_SOFT_RESET : 1;
		unsigned int                  LMI_SOFT_RESET : 1;
		unsigned int                 VCPU_SOFT_RESET : 1;
		unsigned int                 UDEC_SOFT_RESET : 1;
		unsigned int                  CSM_SOFT_RESET : 1;
		unsigned int                  CXW_SOFT_RESET : 1;
		unsigned int                  TAP_SOFT_RESET : 1;
		unsigned int                  MPC_SOFT_RESET : 1;
		unsigned int          JPEG_SCLK_RESET_STATUS : 1;
		unsigned int                   IH_SOFT_RESET : 1;
		unsigned int                 MPRD_SOFT_RESET : 1;
		unsigned int                 IDCT_SOFT_RESET : 1;
		unsigned int              LMI_UMC_SOFT_RESET : 1;
		unsigned int                  SPH_SOFT_RESET : 1;
		unsigned int                  MIF_SOFT_RESET : 1;
		unsigned int                  LCM_SOFT_RESET : 1;
		unsigned int                 SUVD_SOFT_RESET : 1;
		unsigned int          LBSI_VCLK_RESET_STATUS : 1;
		unsigned int          VCPU_VCLK_RESET_STATUS : 1;
		unsigned int          UDEC_VCLK_RESET_STATUS : 1;
		unsigned int          UDEC_DCLK_RESET_STATUS : 1;
		unsigned int           MPC_DCLK_RESET_STATUS : 1;
		unsigned int          MPRD_VCLK_RESET_STATUS : 1;
		unsigned int          MPRD_DCLK_RESET_STATUS : 1;
		unsigned int          IDCT_VCLK_RESET_STATUS : 1;
		unsigned int           MIF_DCLK_RESET_STATUS : 1;
		unsigned int           LCM_DCLK_RESET_STATUS : 1;
		unsigned int          SUVD_VCLK_RESET_STATUS : 1;
		unsigned int          SUVD_DCLK_RESET_STATUS : 1;
		unsigned int            RE_DCLK_RESET_STATUS : 1;
		unsigned int           SRE_DCLK_RESET_STATUS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_STATUS__SI__VI {
	struct {
                unsigned int                        RBC_BUSY : 1;
                unsigned int                     VCPU_REPORT : 7;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 13;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_VCPU_CACHE_OFFSET0__SI__VI {
	struct {
                unsigned int                   CACHE_OFFSET0 : 25;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_VCPU_CACHE_OFFSET1__SI__VI {
	struct {
                unsigned int                   CACHE_OFFSET1 : 25;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_VCPU_CACHE_OFFSET2__SI__VI {
	struct {
                unsigned int                   CACHE_OFFSET2 : 25;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_VCPU_CACHE_SIZE0__SI__VI {
	struct {
                unsigned int                     CACHE_SIZE0 : 21;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_VCPU_CACHE_SIZE1__SI__VI {
	struct {
                unsigned int                     CACHE_SIZE1 : 21;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_VCPU_CACHE_SIZE2__SI__VI {
	struct {
                unsigned int                     CACHE_SIZE2 : 21;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_VCPU_CNTL__SI {
	struct {
		unsigned int                         IRQ_ERR : 4;
		unsigned int          AXI_MAX_BRST_SIZE_IS_4 : 1;
		unsigned int                   PMB_ED_ENABLE : 1;
		unsigned int                  PMB_SOFT_RESET : 1;
		unsigned int                 RBBM_SOFT_RESET : 1;
		unsigned int                       ABORT_REQ : 1;
		unsigned int                          CLK_EN : 1;
		unsigned int                         TRCE_EN : 1;
		unsigned int                        TRCE_MUX : 2;
		unsigned int                         DBG_MUX : 3;
		unsigned int                         JTAG_EN : 1;
		unsigned int                      CLK_ACTIVE : 1;
		unsigned int                     TIMEOUT_DIS : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_VCPU_CNTL__VI {
	struct {
		unsigned int                         IRQ_ERR : 4;
		unsigned int          AXI_MAX_BRST_SIZE_IS_4 : 1;
		unsigned int                   PMB_ED_ENABLE : 1;
		unsigned int                  PMB_SOFT_RESET : 1;
		unsigned int                 RBBM_SOFT_RESET : 1;
		unsigned int                       ABORT_REQ : 1;
		unsigned int                          CLK_EN : 1;
		unsigned int                         TRCE_EN : 1;
		unsigned int                        TRCE_MUX : 2;
		unsigned int                         DBG_MUX : 3;
		unsigned int                         JTAG_EN : 1;
		unsigned int         MIF_WR_LOW_THRESHOLD_BP : 1;
		unsigned int                     TIMEOUT_DIS : 1;
		unsigned int                         SUVD_EN : 1;
		unsigned int                 PRB_TIMEOUT_VAL : 8;
		unsigned int                    CABAC_MB_ACC : 1;
		unsigned int                                 : 1;
		unsigned int                         WMV9_EN : 1;
		unsigned int                   RE_OFFLOAD_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VBLANK_STATUS__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int                   VCE_RDREQ_URG : 4;
                unsigned int                                 : 4;
                unsigned int                    VCE_REQ_TRAN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VENDOR_CAP_LIST__CI__VI {
	struct {
                unsigned int                          CAP_ID : 8;
                unsigned int                        NEXT_PTR : 8;
                unsigned int                          LENGTH : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VENDOR_ID {
	struct {
		unsigned int                       VENDOR_ID : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA25_PPLL_FB_DIV__SI__VI {
	struct {
                unsigned int      VGA25_PPLL_FB_DIV_FRACTION : 4;
                unsigned int VGA25_PPLL_FB_DIV_FRACTION_CNTL : 2;
                unsigned int                                 : 10;
                unsigned int               VGA25_PPLL_FB_DIV : 11;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA25_PPLL_POST_DIV__SI {
	struct {
		unsigned int             VGA25_PPLL_POST_DIV : 7;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA25_PPLL_POST_DIV__VI {
	struct {
		unsigned int      VGA25_PPLL_POST_DIV_PIXCLK : 7;
		unsigned int                                 : 1;
		unsigned int      VGA25_PPLL_POST_DIV_DVOCLK : 7;
		unsigned int                                 : 1;
		unsigned int       VGA25_PPLL_POST_DIV_IDCLK : 7;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA25_PPLL_REF_DIV__SI__VI {
	struct {
                unsigned int              VGA25_PPLL_REF_DIV : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA28_PPLL_FB_DIV__SI__VI {
	struct {
                unsigned int      VGA28_PPLL_FB_DIV_FRACTION : 4;
                unsigned int VGA28_PPLL_FB_DIV_FRACTION_CNTL : 2;
                unsigned int                                 : 10;
                unsigned int               VGA28_PPLL_FB_DIV : 11;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA28_PPLL_POST_DIV__SI {
	struct {
		unsigned int             VGA28_PPLL_POST_DIV : 7;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA28_PPLL_POST_DIV__VI {
	struct {
		unsigned int      VGA28_PPLL_POST_DIV_PIXCLK : 7;
		unsigned int                                 : 1;
		unsigned int      VGA28_PPLL_POST_DIV_DVOCLK : 7;
		unsigned int                                 : 1;
		unsigned int       VGA28_PPLL_POST_DIV_IDCLK : 7;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA28_PPLL_REF_DIV__SI__VI {
	struct {
                unsigned int              VGA28_PPLL_REF_DIV : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA41_PPLL_FB_DIV__SI__VI {
	struct {
                unsigned int      VGA41_PPLL_FB_DIV_FRACTION : 4;
                unsigned int VGA41_PPLL_FB_DIV_FRACTION_CNTL : 2;
                unsigned int                                 : 10;
                unsigned int               VGA41_PPLL_FB_DIV : 11;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA41_PPLL_POST_DIV__SI {
	struct {
		unsigned int             VGA41_PPLL_POST_DIV : 7;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA41_PPLL_POST_DIV__VI {
	struct {
		unsigned int      VGA41_PPLL_POST_DIV_PIXCLK : 7;
		unsigned int                                 : 1;
		unsigned int      VGA41_PPLL_POST_DIV_DVOCLK : 7;
		unsigned int                                 : 1;
		unsigned int       VGA41_PPLL_POST_DIV_IDCLK : 7;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA41_PPLL_REF_DIV__SI__VI {
	struct {
                unsigned int              VGA41_PPLL_REF_DIV : 10;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGADCC_DBG_DCCIF_C__SI__VI {
	struct {
                unsigned int                     DBG_DCCIF_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_CACHE_CONTROL__SI__VI {
	struct {
                unsigned int     VGA_WRITE_THROUGH_CACHE_DIS : 1;
                unsigned int                                 : 7;
                unsigned int          VGA_READ_CACHE_DISABLE : 1;
                unsigned int                                 : 7;
                unsigned int      VGA_READ_BUFFER_INVALIDATE : 1;
                unsigned int                                 : 3;
                unsigned int              VGA_DCCIF_W256ONLY : 1;
                unsigned int                                 : 3;
                unsigned int            VGA_DCCIF_WC_TIMEOUT : 6;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_CRTC__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 5;
                unsigned int                                 : 4;
                unsigned int                                 : 11;
                unsigned int                                 : 8;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_DEBUG_READBACK_DATA__SI__VI {
	struct {
                unsigned int         VGA_DEBUG_READBACK_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_DEBUG_READBACK_INDEX__SI__VI {
	struct {
                unsigned int        VGA_DEBUG_READBACK_INDEX : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_DISPBUF1_SURFACE_ADDR__SI__VI {
	struct {
                unsigned int       VGA_DISPBUF1_SURFACE_ADDR : 25;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_DISPBUF2_SURFACE_ADDR__SI__VI {
	struct {
                unsigned int       VGA_DISPBUF2_SURFACE_ADDR : 25;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_HDP_CONTROL__SI__VI {
	struct {
                unsigned int          VGA_MEM_PAGE_SELECT_EN : 1;
                unsigned int                                 : 3;
                unsigned int              VGA_MEMORY_DISABLE : 1;
                unsigned int                                 : 3;
                unsigned int           VGA_RBBM_LOCK_DISABLE : 1;
                unsigned int                                 : 7;
                unsigned int                  VGA_SOFT_RESET : 1;
                unsigned int                                 : 7;
                unsigned int          VGA_TEST_RESET_CONTROL : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_HDP__SI__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int                                 : 5;
                unsigned int                                 : 1;
                unsigned int                                 : 6;
                unsigned int                                 : 1;
                unsigned int                                 : 15;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_HW_DEBUG__SI__VI {
	struct {
                unsigned int                    VGA_HW_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_INTERRUPT_CONTROL__SI__VI {
	struct {
                unsigned int         VGA_MEM_ACCESS_INT_MASK : 1;
                unsigned int                                 : 7;
                unsigned int         VGA_REG_ACCESS_INT_MASK : 1;
                unsigned int                                 : 7;
                unsigned int     VGA_DISPLAY_SWITCH_INT_MASK : 1;
                unsigned int                                 : 7;
                unsigned int  VGA_MODE_AUTO_TRIGGER_INT_MASK : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_INTERRUPT_STATUS__SI__VI {
	struct {
                unsigned int       VGA_MEM_ACCESS_INT_STATUS : 1;
                unsigned int       VGA_REG_ACCESS_INT_STATUS : 1;
                unsigned int   VGA_DISPLAY_SWITCH_INT_STATUS : 1;
                unsigned int VGA_MODE_AUTO_TRIGGER_INT_STATUS : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_MAIN_CONTROL__SI__VI {
	struct {
                unsigned int                VGA_CRTC_TIMEOUT : 2;
                unsigned int                                 : 1;
                unsigned int        VGA_RENDER_TIMEOUT_COUNT : 2;
                unsigned int VGA_VIRTUAL_VERTICAL_RETRACE_DURATION : 3;
                unsigned int VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT : 2;
                unsigned int                                 : 2;
                unsigned int VGA_MC_WRITE_CLEAN_WAIT_DELAY__VI : 4;
                unsigned int VGA_READBACK_NO_DISPLAY_SOURCE_SELECT : 2;
                unsigned int                                 : 6;
                unsigned int VGA_READBACK_CRT_INTR_SOURCE_SELECT : 2;
                unsigned int VGA_READBACK_SENSE_SWITCH_SELECT : 1;
                unsigned int          VGA_READ_URGENT_ENABLE : 1;
                unsigned int        VGA_WRITES_URGENT_ENABLE : 1;
                unsigned int          VGA_EXTERNAL_DAC_SENSE : 1;
                unsigned int                                 : 1;
                unsigned int VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_MAIN__SI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_MEMORY_BASE_ADDRESS_HIGH__SI__VI {
	struct {
                unsigned int    VGA_MEMORY_BASE_ADDRESS_HIGH : 8;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_MEMORY_BASE_ADDRESS__SI__VI {
	struct {
                unsigned int         VGA_MEMORY_BASE_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_MEM_READ_PAGE_ADDR__SI__VI {
	struct {
                unsigned int         VGA_MEM_READ_PAGE0_ADDR : 10;
                unsigned int                                 : 6;
                unsigned int         VGA_MEM_READ_PAGE1_ADDR : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_MEM_WRITE_PAGE_ADDR__SI__VI {
	struct {
                unsigned int        VGA_MEM_WRITE_PAGE0_ADDR : 10;
                unsigned int                                 : 6;
                unsigned int        VGA_MEM_WRITE_PAGE1_ADDR : 10;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_MODE_CONTROL__SI__VI {
	struct {
                unsigned int                  VGA_ATI_LINEAR : 1;
                unsigned int                                 : 3;
                unsigned int     VGA_LUT_PALETTE_UPDATE_MODE : 2;
                unsigned int                                 : 2;
                unsigned int        VGA_128K_APERTURE_PAGING : 1;
                unsigned int                                 : 7;
                unsigned int         VGA_TEXT_132_COLUMNS_EN : 1;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_REG__SI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int                                 : 4;
                unsigned int                                 : 4;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 8;
                unsigned int                                 : 4;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_RENDER_CONTROL__SI__VI {
	struct {
                unsigned int                  VGA_BLINK_RATE : 5;
                unsigned int                  VGA_BLINK_MODE : 2;
                unsigned int         VGA_CURSOR_BLINK_INVERT : 1;
                unsigned int      VGA_EXTD_ADDR_COUNT_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int                VGA_VSTATUS_CNTL : 2;
                unsigned int                                 : 6;
                unsigned int                   VGA_LOCK_8DOT : 1;
                unsigned int VGAREG_LINECMP_COMPATIBILITY_SEL : 1;
                unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_SEQUENCER_RESET_CONTROL__SI__VI {
	struct {
                unsigned int D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1;
                unsigned int D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1;
                unsigned int D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1;
                unsigned int D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1;
                unsigned int D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1;
                unsigned int D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1;
                unsigned int                                 : 2;
                unsigned int D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1;
                unsigned int D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1;
                unsigned int D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1;
                unsigned int D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1;
                unsigned int D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1;
                unsigned int D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1;
                unsigned int                                 : 2;
                unsigned int    VGA_MODE_AUTO_TRIGGER_ENABLE : 1;
                unsigned int VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT : 1;
                unsigned int VGA_MODE_AUTO_TRIGGER_INDEX_SELECT : 6;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_SOURCE_SELECT__SI__VI {
	struct {
                unsigned int                VGA_SOURCE_SEL_A : 3;
                unsigned int                                 : 5;
                unsigned int                VGA_SOURCE_SEL_B : 3;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_STATUS_CLEAR__SI__VI {
	struct {
                unsigned int        VGA_MEM_ACCESS_INT_CLEAR : 1;
                unsigned int                                 : 7;
                unsigned int        VGA_REG_ACCESS_INT_CLEAR : 1;
                unsigned int                                 : 7;
                unsigned int    VGA_DISPLAY_SWITCH_INT_CLEAR : 1;
                unsigned int                                 : 7;
                unsigned int VGA_MODE_AUTO_TRIGGER_INT_CLEAR : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_STATUS__SI__VI {
	struct {
                unsigned int           VGA_MEM_ACCESS_STATUS : 1;
                unsigned int           VGA_REG_ACCESS_STATUS : 1;
                unsigned int       VGA_DISPLAY_SWITCH_STATUS : 1;
                unsigned int    VGA_MODE_AUTO_TRIGGER_STATUS : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_SURFACE_PITCH_SELECT__SI__VI {
	struct {
                unsigned int        VGA_SURFACE_PITCH_SELECT : 2;
                unsigned int                                 : 6;
                unsigned int       VGA_SURFACE_HEIGHT_SELECT : 2;
                unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_TEST_CONTROL__SI__VI {
	struct {
                unsigned int                 VGA_TEST_ENABLE : 1;
                unsigned int                                 : 7;
                unsigned int           VGA_TEST_RENDER_START : 1;
                unsigned int                                 : 7;
                unsigned int            VGA_TEST_RENDER_DONE : 1;
                unsigned int                                 : 7;
                unsigned int  VGA_TEST_RENDER_DISPBUF_SELECT : 1;
                unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_TEST_DEBUG_DATA__SI__VI {
	struct {
                unsigned int             VGA_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_TEST_DEBUG_INDEX__SI__VI {
	struct {
                unsigned int            VGA_TEST_DEBUG_INDEX : 8;
                unsigned int         VGA_TEST_DEBUG_WRITE_EN : 1;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA_TEXT__SI__VI {
	struct {
                unsigned int                                 : 4;
                unsigned int                                 : 4;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 2;
                unsigned int                                 : 3;
                unsigned int                                 : 3;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_CACHE_INVALIDATION {
	struct {
                unsigned int              CACHE_INVALIDATION : 2;
                unsigned int                                 : 2;
                unsigned int          DIS_INSTANCING_OPT__VI : 1;
                unsigned int              VS_NO_EXTRA_BUFFER : 1;
                unsigned int                   AUTO_INVLD_EN : 2;
                unsigned int                                 : 1;
                unsigned int                     USE_GS_DONE : 1;
                unsigned int                                 : 1;
                unsigned int            DIS_RANGE_FULL_INVLD : 1;
                unsigned int                GS_LATE_ALLOC_EN : 1;
                unsigned int            STREAMOUT_FULL_FLUSH : 1;
                unsigned int                                 : 2;
                unsigned int                        ES_LIMIT : 5;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_CNTL_STATUS {
	struct {
		unsigned int                        VGT_BUSY : 1;
		unsigned int               VGT_OUT_INDX_BUSY : 1;
		unsigned int                    VGT_OUT_BUSY : 1;
		unsigned int                     VGT_PT_BUSY : 1;
		unsigned int                     VGT_TE_BUSY : 1;
		unsigned int                     VGT_VR_BUSY : 1;
		unsigned int                     VGT_PI_BUSY : 1;
		unsigned int                     VGT_GS_BUSY : 1;
		unsigned int                     VGT_HS_BUSY : 1;
		unsigned int                   VGT_TE11_BUSY : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_CNTL {
	struct {
		unsigned int                  VGT_DEBUG_INDX : 6;
		unsigned int             VGT_DEBUG_SEL_BUS_B : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG0 {
	struct {
		unsigned int               vgt_busy_extended : 1;
		unsigned int                          SPARE9 : 1;
		unsigned int                        vgt_busy : 1;
		unsigned int                          SPARE8 : 1;
		unsigned int                          SPARE7 : 1;
		unsigned int                          SPARE6 : 1;
		unsigned int                          SPARE5 : 1;
		unsigned int                          SPARE4 : 1;
		unsigned int                         pi_busy : 1;
		unsigned int                      vr_pi_busy : 1;
		unsigned int                      pt_pi_busy : 1;
		unsigned int                      te_pi_busy : 1;
		unsigned int                         gs_busy : 1;
		unsigned int                        rcm_busy : 1;
		unsigned int                         tm_busy : 1;
		unsigned int                         cm_busy : 1;
		unsigned int                        gog_busy : 1;
		unsigned int                       frmt_busy : 1;
		unsigned int                         SPARE10 : 1;
		unsigned int                    te11_pi_busy : 1;
		unsigned int                          SPARE3 : 1;
		unsigned int               combined_out_busy : 1;
		unsigned int          spi_vs_interfaces_busy : 1;
		unsigned int              pa_interfaces_busy : 1;
		unsigned int                    reg_clk_busy : 1;
		unsigned int                          SPARE2 : 1;
		unsigned int                   core_clk_busy : 1;
		unsigned int                     gs_clk_busy : 1;
		unsigned int                          SPARE1 : 1;
		unsigned int                   sclk_core_vld : 1;
		unsigned int                     sclk_gs_vld : 1;
		unsigned int                          SPARE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG1 {
	struct {
		unsigned int                          SPARE9 : 1;
		unsigned int                          SPARE8 : 1;
		unsigned int                          SPARE7 : 1;
		unsigned int                          SPARE6 : 1;
		unsigned int                          SPARE5 : 1;
		unsigned int                          SPARE4 : 1;
		unsigned int                          SPARE3 : 1;
		unsigned int                          SPARE2 : 1;
		unsigned int                          SPARE1 : 1;
		unsigned int                          SPARE0 : 1;
		unsigned int                     pi_vr_valid : 1;
		unsigned int                      vr_pi_read : 1;
		unsigned int                     pi_pt_valid : 1;
		unsigned int                      pt_pi_read : 1;
		unsigned int                     pi_te_valid : 1;
		unsigned int                     te_grp_read : 1;
		unsigned int               vr_out_indx_valid : 1;
		unsigned int                         SPARE12 : 1;
		unsigned int               vr_out_prim_valid : 1;
		unsigned int                         SPARE11 : 1;
		unsigned int               pt_out_indx_valid : 1;
		unsigned int                         SPARE10 : 1;
		unsigned int               pt_out_prim_valid : 1;
		unsigned int                         SPARE23 : 1;
		unsigned int               te_out_data_valid : 1;
		unsigned int                         SPARE25 : 1;
		unsigned int                     pi_gs_valid : 1;
		unsigned int                      gs_pi_read : 1;
		unsigned int              gog_out_indx_valid : 1;
		unsigned int                   out_indx_read : 1;
		unsigned int              gog_out_prim_valid : 1;
		unsigned int                   out_prim_read : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG10__CI__VI {
	struct {
                unsigned int         index_buffer_depth_r1_q : 5;
                unsigned int                       eopg_r2_q : 1;
                unsigned int                       eotg_r2_q : 1;
                unsigned int               onchip_gs_en_r0_q : 2;
                unsigned int                          SPARE2 : 2;
                unsigned int            rcm_mem_gsprim_re_qq : 1;
                unsigned int             rcm_mem_gsprim_re_q : 1;
                unsigned int      gs_rb_space_avail_r3_q_9_0 : 10;
                unsigned int      es_rb_space_avail_r2_q_8_0 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG10__SI {
	struct {
		unsigned int         index_buffer_depth_r1_q : 5;
		unsigned int                       eopg_r2_q : 1;
		unsigned int                       eotg_r2_q : 1;
		unsigned int                                 : 4;
		unsigned int            rcm_mem_gsprim_re_qq : 1;
		unsigned int             rcm_mem_gsprim_re_q : 1;
		unsigned int      gs_rb_space_avail_r3_q_9_0 : 10;
		unsigned int      es_rb_space_avail_r2_q_8_0 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG11__CI__VI {
	struct {
                unsigned int                       tm_busy_q : 1;
                unsigned int                  tm_noif_busy_q : 1;
                unsigned int                   tm_out_busy_q : 1;
                unsigned int         es_rb_dealloc_fifo_busy : 1;
                unsigned int             vs_dealloc_tbl_busy : 1;
                unsigned int                          SPARE1 : 1;
                unsigned int          spi_gsthread_fifo_busy : 1;
                unsigned int          spi_esthread_fifo_busy : 1;
                unsigned int                     hold_eswave : 1;
                unsigned int              es_rb_roll_over_r3 : 1;
                unsigned int                counters_busy_r0 : 1;
                unsigned int               counters_avail_r0 : 1;
                unsigned int           counters_available_r0 : 1;
                unsigned int               vs_event_fifo_rtr : 1;
                unsigned int          VGT_SPI_gsthread_rtr_q : 1;
                unsigned int          VGT_SPI_esthread_rtr_q : 1;
                unsigned int                    gs_issue_rtr : 1;
                unsigned int                 tm_pt_event_rtr : 1;
                unsigned int                          SPARE0 : 1;
                unsigned int                       gs_r0_rtr : 1;
                unsigned int                       es_r0_rtr : 1;
                unsigned int             gog_tm_vs_event_rtr : 1;
                unsigned int             tm_rcm_gs_event_rtr : 1;
                unsigned int               tm_rcm_gs_tbl_rtr : 1;
                unsigned int               tm_rcm_es_tbl_rtr : 1;
                unsigned int             vs_event_fifo_empty : 1;
                unsigned int              vs_event_fifo_full : 1;
                unsigned int         es_rb_dealloc_fifo_full : 1;
                unsigned int             vs_dealloc_tbl_full : 1;
                unsigned int                    send_event_q : 1;
                unsigned int                    es_tbl_empty : 1;
                unsigned int             no_active_states_r0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG11__SI {
	struct {
		unsigned int                         tm_busy : 1;
		unsigned int                    tm_noif_busy : 1;
		unsigned int                     tm_out_busy : 1;
		unsigned int         es_rb_dealloc_fifo_busy : 1;
		unsigned int             vs_dealloc_tbl_busy : 1;
		unsigned int                          SPARE1 : 1;
		unsigned int          spi_gsthread_fifo_busy : 1;
		unsigned int          spi_esthread_fifo_busy : 1;
		unsigned int                     hold_eswave : 1;
		unsigned int              es_rb_roll_over_r3 : 1;
		unsigned int                counters_busy_r0 : 1;
		unsigned int               counters_avail_r0 : 1;
		unsigned int           counters_available_r0 : 1;
		unsigned int               vs_event_fifo_rtr : 1;
		unsigned int          VGT_SPI_gsthread_rtr_q : 1;
		unsigned int          VGT_SPI_esthread_rtr_q : 1;
		unsigned int                    gs_issue_rtr : 1;
		unsigned int                 tm_pt_event_rtr : 1;
		unsigned int                          SPARE0 : 1;
		unsigned int                       gs_r0_rtr : 1;
		unsigned int                       es_r0_rtr : 1;
		unsigned int             gog_tm_vs_event_rtr : 1;
		unsigned int             tm_rcm_gs_event_rtr : 1;
		unsigned int               tm_rcm_gs_tbl_rtr : 1;
		unsigned int               tm_rcm_es_tbl_rtr : 1;
		unsigned int             vs_event_fifo_empty : 1;
		unsigned int              vs_event_fifo_full : 1;
		unsigned int         es_rb_dealloc_fifo_full : 1;
		unsigned int             vs_dealloc_tbl_full : 1;
		unsigned int                    send_event_q : 1;
		unsigned int                    es_tbl_empty : 1;
		unsigned int             no_active_states_r0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG12 {
	struct {
		unsigned int                  gs_state0_r0_q : 3;
		unsigned int                  gs_state1_r0_q : 3;
		unsigned int                  gs_state2_r0_q : 3;
		unsigned int                  gs_state3_r0_q : 3;
		unsigned int                  gs_state4_r0_q : 3;
		unsigned int                  gs_state5_r0_q : 3;
		unsigned int                  gs_state6_r0_q : 3;
		unsigned int                  gs_state7_r0_q : 3;
		unsigned int                  gs_state8_r0_q : 3;
		unsigned int                  gs_state9_r0_q : 3;
		unsigned int                 hold_eswave_eop : 1;
		unsigned int                          SPARE0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG13 {
	struct {
		unsigned int                 gs_state10_r0_q : 3;
		unsigned int                 gs_state11_r0_q : 3;
		unsigned int                 gs_state12_r0_q : 3;
		unsigned int                 gs_state13_r0_q : 3;
		unsigned int                 gs_state14_r0_q : 3;
		unsigned int                 gs_state15_r0_q : 3;
		unsigned int           gs_tbl_wrptr_r0_q_3_0 : 4;
		unsigned int   gsfetch_done_fifo_cnt_q_not_0 : 1;
		unsigned int        gsfetch_done_cnt_q_not_0 : 1;
		unsigned int                     es_tbl_full : 1;
		unsigned int                          SPARE1 : 1;
		unsigned int                          SPARE0 : 1;
		unsigned int               active_cm_sm_r0_q : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG14 {
	struct {
		unsigned int                          SPARE3 : 4;
		unsigned int          gsfetch_done_fifo_full : 1;
		unsigned int            gs_rb_space_avail_r0 : 1;
		unsigned int      smx_es_done_cnt_r0_q_not_0 : 1;
		unsigned int                          SPARE8 : 2;
		unsigned int             vs_done_cnt_q_not_0 : 1;
		unsigned int             es_flush_cnt_busy_q : 1;
		unsigned int                  gs_tbl_full_r0 : 1;
		unsigned int                          SPARE2 : 9;
		unsigned int       se1spi_gsthread_fifo_busy : 1;
		unsigned int                           SPARE : 3;
		unsigned int       VGT_SE1SPI_gsthread_rtr_q : 1;
		unsigned int     smx1_es_done_cnt_r0_q_not_0 : 1;
		unsigned int       se1spi_esthread_fifo_busy : 1;
		unsigned int                          SPARE1 : 1;
		unsigned int    gsfetch_done_se1_cnt_q_not_0 : 1;
		unsigned int                          SPARE0 : 1;
		unsigned int       VGT_SE1SPI_esthread_rtr_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG15__CI__VI {
	struct {
                unsigned int                       cm_busy_q : 1;
                unsigned int                 counters_busy_q : 1;
                unsigned int               output_fifo_empty : 1;
                unsigned int                output_fifo_full : 1;
                unsigned int                   counters_full : 1;
                unsigned int                     active_sm_q : 5;
                unsigned int                   entry_rdptr_q : 5;
                unsigned int                cntr_tbl_wrptr_q : 5;
                unsigned int                         SPARE25 : 6;
                unsigned int                   st_cut_mode_q : 2;
                unsigned int           gs_done_array_q_not_0 : 1;
                unsigned int                         SPARE31 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG15__SI {
	struct {
		unsigned int                         cm_busy : 1;
		unsigned int                   counters_busy : 1;
		unsigned int               output_fifo_empty : 1;
		unsigned int                output_fifo_full : 1;
		unsigned int                   counters_full : 1;
		unsigned int                     active_sm_q : 5;
		unsigned int                   entry_rdptr_q : 5;
		unsigned int                cntr_tbl_wrptr_q : 5;
		unsigned int                         SPARE25 : 6;
		unsigned int                   st_cut_mode_q : 2;
		unsigned int           gs_done_array_q_not_0 : 1;
		unsigned int                         SPARE31 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG16__CI__VI {
	struct {
                unsigned int                        gog_busy : 1;
                unsigned int                     gog_state_q : 3;
                unsigned int                          r0_rtr : 1;
                unsigned int                          r1_rtr : 1;
                unsigned int                 r1_upstream_rtr : 1;
                unsigned int                   r2_vs_tbl_rtr : 1;
                unsigned int                     r2_prim_rtr : 1;
                unsigned int                     r2_indx_rtr : 1;
                unsigned int                          r2_rtr : 1;
                unsigned int             gog_tm_vs_event_rtr : 1;
                unsigned int          r3_force_vs_tbl_we_rtr : 1;
                unsigned int                 indx_valid_r2_q : 1;
                unsigned int                 prim_valid_r2_q : 1;
                unsigned int                      valid_r2_q : 1;
                unsigned int                 prim_valid_r1_q : 1;
                unsigned int                 indx_valid_r1_q : 1;
                unsigned int                      valid_r1_q : 1;
                unsigned int                 indx_valid_r0_q : 1;
                unsigned int                 prim_valid_r0_q : 1;
                unsigned int                      valid_r0_q : 1;
                unsigned int                    send_event_q : 1;
                unsigned int                         SPARE24 : 1;
                unsigned int       vert_seen_since_sopg_r2_q : 1;
                unsigned int          gog_out_prim_state_sel : 3;
                unsigned int        multiple_streams_en_r1_q : 1;
                unsigned int        vs_vert_count_r2_q_not_0 : 1;
                unsigned int               num_gs_r2_q_not_0 : 1;
                unsigned int                new_vs_thread_r2 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG16__SI {
	struct {
		unsigned int                        gog_busy : 1;
		unsigned int                     gog_state_q : 3;
		unsigned int                          r0_rtr : 1;
		unsigned int                          r1_rtr : 1;
		unsigned int                 r1_upstream_rtr : 1;
		unsigned int                   r2_vs_tbl_rtr : 1;
		unsigned int                     r2_prim_rtr : 1;
		unsigned int                     r2_indx_rtr : 1;
		unsigned int                          r2_rtr : 1;
		unsigned int             gog_tm_vs_event_rtr : 1;
		unsigned int          r3_force_vs_tbl_we_rtr : 1;
		unsigned int                 indx_valid_r2_q : 1;
		unsigned int                 prim_valid_r2_q : 1;
		unsigned int                      valid_r2_q : 1;
		unsigned int                 prim_valid_r1_q : 1;
		unsigned int                 indx_valid_r1_q : 1;
		unsigned int                      valid_r1_q : 1;
		unsigned int                 indx_valid_r0_q : 1;
		unsigned int                 prim_valid_r0_q : 1;
		unsigned int                      valid_r0_q : 1;
		unsigned int                    send_event_q : 1;
		unsigned int                         SPARE24 : 2;
		unsigned int          gog_out_prim_state_sel : 3;
		unsigned int        multiple_streams_en_r1_q : 1;
		unsigned int                                 : 1;
		unsigned int               num_gs_r2_q_not_0 : 1;
		unsigned int                new_vs_thread_r2 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG17 {
	struct {
		unsigned int      gog_out_prim_rel_indx2_5_0 : 6;
		unsigned int      gog_out_prim_rel_indx1_5_0 : 6;
		unsigned int      gog_out_prim_rel_indx0_5_0 : 6;
		unsigned int               gog_out_indx_13_0 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG18__CI__VI {
	struct {
                unsigned int                    grp_vr_valid : 1;
                unsigned int                        pipe0_dr : 1;
                unsigned int                        pipe1_dr : 1;
                unsigned int                     vr_grp_read : 1;
                unsigned int                       pipe0_rtr : 1;
                unsigned int                       pipe1_rtr : 1;
                unsigned int                out_vr_indx_read : 1;
                unsigned int                out_vr_prim_read : 1;
                unsigned int               indices_to_send_q : 3;
                unsigned int                   valid_indices : 1;
                unsigned int               last_indx_of_prim : 1;
                unsigned int                     indx0_new_d : 1;
                unsigned int                     indx1_new_d : 1;
                unsigned int                     indx2_new_d : 1;
                unsigned int                     indx2_hit_d : 1;
                unsigned int                     indx1_hit_d : 1;
                unsigned int                     indx0_hit_d : 1;
                unsigned int        st_vertex_reuse_off_r0_q : 1;
                unsigned int     last_group_of_instance_r0_q : 1;
                unsigned int             null_primitive_r0_q : 1;
                unsigned int                        eop_r0_q : 1;
                unsigned int             eject_vtx_vect_r1_d : 1;
                unsigned int              sub_prim_type_r0_q : 3;
                unsigned int              gs_scenario_a_r0_q : 1;
                unsigned int              gs_scenario_b_r0_q : 1;
                unsigned int           components_valid_r0_q : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG18__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG19__CI__VI {
	struct {
                unsigned int             separate_out_busy_q : 1;
                unsigned int        separate_out_indx_busy_q : 1;
                unsigned int               prim_buffer_empty : 1;
                unsigned int                prim_buffer_full : 1;
                unsigned int            pa_clips_fifo_busy_q : 1;
                unsigned int            pa_clipp_fifo_busy_q : 1;
                unsigned int              VGT_PA_clips_rtr_q : 1;
                unsigned int              VGT_PA_clipp_rtr_q : 1;
                unsigned int        spi_vsthread_fifo_busy_q : 1;
                unsigned int          spi_vsvert_fifo_busy_q : 1;
                unsigned int            pa_clipv_fifo_busy_q : 1;
                unsigned int                       hold_prim : 1;
                unsigned int          VGT_SPI_vsthread_rtr_q : 1;
                unsigned int            VGT_SPI_vsvert_rtr_q : 1;
                unsigned int              VGT_PA_clipv_rtr_q : 1;
                unsigned int                    new_packet_q : 1;
                unsigned int             buffered_prim_event : 1;
                unsigned int    buffered_prim_null_primitive : 1;
                unsigned int               buffered_prim_eop : 1;
                unsigned int    buffered_prim_eject_vtx_vect : 1;
                unsigned int        buffered_prim_type_event : 6;
                unsigned int         VGT_SE1SPI_vswave_rtr_q : 1;
                unsigned int         VGT_SE1SPI_vsvert_rtr_q : 1;
                unsigned int         num_new_unique_rel_indx : 2;
                unsigned int       null_terminate_vtx_vector : 1;
                unsigned int                    filter_event : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG19__SI {
	struct {
		unsigned int               separate_out_busy : 1;
		unsigned int          separate_out_indx_busy : 1;
		unsigned int               prim_buffer_empty : 1;
		unsigned int                prim_buffer_full : 1;
		unsigned int              pa_clips_fifo_busy : 1;
		unsigned int              pa_clipp_fifo_busy : 1;
		unsigned int              VGT_PA_clips_rtr_q : 1;
		unsigned int              VGT_PA_clipp_rtr_q : 1;
		unsigned int          spi_vsthread_fifo_busy : 1;
		unsigned int            spi_vsvert_fifo_busy : 1;
		unsigned int              pa_clipv_fifo_busy : 1;
		unsigned int                       hold_prim : 1;
		unsigned int          VGT_SPI_vsthread_rtr_q : 1;
		unsigned int            VGT_SPI_vsvert_rtr_q : 1;
		unsigned int              VGT_PA_clipv_rtr_q : 1;
		unsigned int                    new_packet_q : 1;
		unsigned int             buffered_prim_event : 1;
		unsigned int    buffered_prim_null_primitive : 1;
		unsigned int               buffered_prim_eop : 1;
		unsigned int    buffered_prim_eject_vtx_vect : 1;
		unsigned int        buffered_prim_type_event : 6;
		unsigned int         VGT_SE1SPI_vswave_rtr_q : 1;
		unsigned int         VGT_SE1SPI_vsvert_rtr_q : 1;
		unsigned int         num_new_unique_rel_indx : 2;
		unsigned int       null_terminate_vtx_vector : 1;
		unsigned int                    filter_event : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG20 {
	struct {
		unsigned int dbg_VGT_SPI_vsthread_sovertexindex : 16;
		unsigned int dbg_VGT_SPI_vsthread_sovertexcount_not_0 : 1;
		unsigned int                         SPARE17 : 1;
		unsigned int                 alloc_counter_q : 4;
		unsigned int         curr_dealloc_distance_q : 7;
		unsigned int                  new_allocate_q : 1;
		unsigned int   curr_slot_in_vtx_vect_q_not_0 : 1;
		unsigned int         int_vtx_counter_q_not_0 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG21 {
	struct {
		unsigned int             out_indx_fifo_empty : 1;
		unsigned int            indx_side_fifo_empty : 1;
		unsigned int                        pipe0_dr : 1;
		unsigned int                        pipe1_dr : 1;
		unsigned int                        pipe2_dr : 1;
		unsigned int             vsthread_buff_empty : 1;
		unsigned int              out_indx_fifo_full : 1;
		unsigned int             indx_side_fifo_full : 1;
		unsigned int                       pipe0_rtr : 1;
		unsigned int                       pipe1_rtr : 1;
		unsigned int                       pipe2_rtr : 1;
		unsigned int              vsthread_buff_full : 1;
		unsigned int                  interfaces_rtr : 1;
		unsigned int              indx_count_q_not_0 : 1;
		unsigned int        wait_for_external_eopg_q : 1;
		unsigned int                 full_state_p1_q : 1;
		unsigned int            indx_side_indx_valid : 1;
		unsigned int                    stateid_p0_q : 3;
		unsigned int                   is_event_p0_q : 1;
		unsigned int                 lshs_dealloc_p1 : 1;
		unsigned int                  stream_id_r2_q : 1;
		unsigned int        vtx_vect_counter_q_not_0 : 1;
		unsigned int                    buff_full_p1 : 1;
		unsigned int                strmout_valid_p1 : 1;
		unsigned int                       eotg_r2_q : 1;
		unsigned int                       null_r2_q : 1;
		unsigned int                           p0_dr : 1;
		unsigned int                          p0_rtr : 1;
		unsigned int                       eopg_p0_q : 1;
		unsigned int                         p0_nobp : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG22 {
	struct {
		unsigned int                      cm_state16 : 2;
		unsigned int                      cm_state17 : 2;
		unsigned int                      cm_state18 : 2;
		unsigned int                      cm_state19 : 2;
		unsigned int                      cm_state20 : 2;
		unsigned int                      cm_state21 : 2;
		unsigned int                      cm_state22 : 2;
		unsigned int                      cm_state23 : 2;
		unsigned int                      cm_state24 : 2;
		unsigned int                      cm_state25 : 2;
		unsigned int                      cm_state26 : 2;
		unsigned int                      cm_state27 : 2;
		unsigned int                      cm_state28 : 2;
		unsigned int                      cm_state29 : 2;
		unsigned int                      cm_state30 : 2;
		unsigned int                      cm_state31 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG23 {
	struct {
		unsigned int                       frmt_busy : 1;
		unsigned int               rcm_frmt_vert_rtr : 1;
		unsigned int               rcm_frmt_prim_rtr : 1;
		unsigned int                     prim_r3_rtr : 1;
		unsigned int                     prim_r2_rtr : 1;
		unsigned int                     vert_r3_rtr : 1;
		unsigned int                     vert_r2_rtr : 1;
		unsigned int                     vert_r1_rtr : 1;
		unsigned int                     vert_r0_rtr : 1;
		unsigned int                 prim_fifo_empty : 1;
		unsigned int                  prim_fifo_full : 1;
		unsigned int                    vert_dr_r2_q : 1;
		unsigned int                    prim_dr_r2_q : 1;
		unsigned int                    vert_dr_r1_q : 1;
		unsigned int                    vert_dr_r0_q : 1;
		unsigned int                  new_verts_r2_q : 2;
		unsigned int                 verts_sent_r2_q : 4;
		unsigned int             prim_state_sel_r2_q : 3;
		unsigned int                           SPARE : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG24 {
	struct {
		unsigned int     avail_es_rb_space_r0_q_23_0 : 24;
		unsigned int         dependent_st_cut_mode_q : 2;
		unsigned int                         SPARE31 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG25 {
	struct {
		unsigned int     avail_gs_rb_space_r0_q_25_0 : 26;
		unsigned int                  active_sm_r0_q : 4;
		unsigned int            add_gs_rb_space_r1_q : 1;
		unsigned int            add_gs_rb_space_r0_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG26__CI__VI {
	struct {
                unsigned int                       cm_state0 : 2;
                unsigned int                       cm_state1 : 2;
                unsigned int                       cm_state2 : 2;
                unsigned int                       cm_state3 : 2;
                unsigned int                       cm_state4 : 2;
                unsigned int                       cm_state5 : 2;
                unsigned int                       cm_state6 : 2;
                unsigned int                       cm_state7 : 2;
                unsigned int                       cm_state8 : 2;
                unsigned int                       cm_state9 : 2;
                unsigned int                      cm_state10 : 2;
                unsigned int                      cm_state11 : 2;
                unsigned int                      cm_state12 : 2;
                unsigned int                      cm_state13 : 2;
                unsigned int                      cm_state14 : 2;
                unsigned int                      cm_state15 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG26__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG27 {
	struct {
		unsigned int                        pipe0_dr : 1;
		unsigned int                         gsc0_dr : 1;
		unsigned int                        pipe1_dr : 1;
		unsigned int                 tm_pt_event_rtr : 1;
		unsigned int                       pipe0_rtr : 1;
		unsigned int                        gsc0_rtr : 1;
		unsigned int                       pipe1_rtr : 1;
		unsigned int          last_indx_of_prim_p1_q : 1;
		unsigned int            indices_to_send_p0_q : 2;
		unsigned int                 event_flag_p1_q : 1;
		unsigned int                        eop_p1_q : 1;
		unsigned int           gs_out_prim_type_p0_q : 2;
		unsigned int         gsc_null_primitive_p0_q : 1;
		unsigned int                    gsc_eop_p0_q : 1;
		unsigned int               gsc_2cycle_output : 1;
		unsigned int              gsc_2nd_cycle_p0_q : 1;
		unsigned int             last_indx_of_vsprim : 1;
		unsigned int     first_vsprim_of_gsprim_p0_q : 1;
		unsigned int             gsc_indx_count_p0_q : 11;
		unsigned int           last_vsprim_of_gsprim : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG28 {
	struct {
		unsigned int                     con_state_q : 4;
		unsigned int                  second_cycle_q : 1;
		unsigned int         process_tri_middle_p0_q : 1;
		unsigned int   process_tri_1st_2nd_half_p0_q : 1;
		unsigned int    process_tri_center_poly_p0_q : 1;
		unsigned int                  pipe0_patch_dr : 1;
		unsigned int                   pipe0_edge_dr : 1;
		unsigned int                        pipe1_dr : 1;
		unsigned int                 pipe0_patch_rtr : 1;
		unsigned int                  pipe0_edge_rtr : 1;
		unsigned int                       pipe1_rtr : 1;
		unsigned int               outer_parity_p0_q : 1;
		unsigned int            parallel_parity_p0_q : 1;
		unsigned int        first_ring_of_patch_p0_q : 1;
		unsigned int         last_ring_of_patch_p0_q : 1;
		unsigned int    last_edge_of_outer_ring_p0_q : 1;
		unsigned int     last_point_of_outer_ring_p1 : 1;
		unsigned int     last_point_of_inner_ring_p1 : 1;
		unsigned int       outer_edge_tf_eq_one_p0_q : 1;
		unsigned int          advance_outer_point_p1 : 1;
		unsigned int          advance_inner_point_p1 : 1;
		unsigned int          next_ring_is_rect_p0_q : 1;
		unsigned int                pipe1_outer1_rtr : 1;
		unsigned int                pipe1_outer2_rtr : 1;
		unsigned int                pipe1_inner1_rtr : 1;
		unsigned int                pipe1_inner2_rtr : 1;
		unsigned int                 pipe1_patch_rtr : 1;
		unsigned int                  pipe1_edge_rtr : 1;
		unsigned int        use_stored_inner_q_ring2 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG29 {
	struct {
		unsigned int                     con_state_q : 4;
		unsigned int                  second_cycle_q : 1;
		unsigned int         process_tri_middle_p0_q : 1;
		unsigned int   process_tri_1st_2nd_half_p0_q : 1;
		unsigned int    process_tri_center_poly_p0_q : 1;
		unsigned int                  pipe0_patch_dr : 1;
		unsigned int                   pipe0_edge_dr : 1;
		unsigned int                        pipe1_dr : 1;
		unsigned int                 pipe0_patch_rtr : 1;
		unsigned int                  pipe0_edge_rtr : 1;
		unsigned int                       pipe1_rtr : 1;
		unsigned int               outer_parity_p0_q : 1;
		unsigned int            parallel_parity_p0_q : 1;
		unsigned int        first_ring_of_patch_p0_q : 1;
		unsigned int         last_ring_of_patch_p0_q : 1;
		unsigned int    last_edge_of_outer_ring_p0_q : 1;
		unsigned int     last_point_of_outer_ring_p1 : 1;
		unsigned int     last_point_of_inner_ring_p1 : 1;
		unsigned int       outer_edge_tf_eq_one_p0_q : 1;
		unsigned int          advance_outer_point_p1 : 1;
		unsigned int          advance_inner_point_p1 : 1;
		unsigned int          next_ring_is_rect_p0_q : 1;
		unsigned int                pipe1_outer1_rtr : 1;
		unsigned int                pipe1_outer2_rtr : 1;
		unsigned int                pipe1_inner1_rtr : 1;
		unsigned int                pipe1_inner2_rtr : 1;
		unsigned int                 pipe1_patch_rtr : 1;
		unsigned int                  pipe1_edge_rtr : 1;
		unsigned int        use_stored_inner_q_ring3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG2__CI__VI {
	struct {
                unsigned int                     hs_grp_busy : 1;
                unsigned int                    hs_noif_busy : 1;
                unsigned int                      tfmmIsBusy : 1;
                unsigned int                  lsVertIfBusy_0 : 1;
                unsigned int          te11_hs_tess_input_rtr : 1;
                unsigned int                  lsWaveIfBusy_0 : 1;
                unsigned int          hs_te11_tess_input_rts : 1;
                unsigned int                      grpModBusy : 1;
                unsigned int                 lsVertFifoEmpty : 1;
                unsigned int                 lsWaveFifoEmpty : 1;
                unsigned int                 hsVertFifoEmpty : 1;
                unsigned int                 hsWaveFifoEmpty : 1;
                unsigned int                hsInputFifoEmpty : 1;
                unsigned int                  hsTifFifoEmpty : 1;
                unsigned int                  lsVertFifoFull : 1;
                unsigned int                  lsWaveFifoFull : 1;
                unsigned int                  hsVertFifoFull : 1;
                unsigned int                  hsWaveFifoFull : 1;
                unsigned int                 hsInputFifoFull : 1;
                unsigned int                   hsTifFifoFull : 1;
                unsigned int                          p0_rtr : 1;
                unsigned int                          p1_rtr : 1;
                unsigned int                           p0_dr : 1;
                unsigned int                           p1_dr : 1;
                unsigned int                          p0_rts : 1;
                unsigned int                          p1_rts : 1;
                unsigned int                        ls_sh_id : 1;
                unsigned int                     lsFwaveFlag : 1;
                unsigned int                 lsWaveSendFlush : 1;
                unsigned int                           SPARE : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG2__SI {
	struct {
		unsigned int                           SPARE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG30__CI {
	struct {
		unsigned int                        pipe0_dr : 1;
		unsigned int                     pipe0_tf_dr : 1;
		unsigned int                        pipe2_dr : 1;
		unsigned int              event_or_null_p0_q : 1;
		unsigned int                       pipe0_rtr : 1;
		unsigned int                       pipe1_rtr : 1;
		unsigned int                    pipe1_tf_rtr : 1;
		unsigned int                       pipe2_rtr : 1;
		unsigned int             ttp_patch_fifo_full : 1;
		unsigned int            ttp_patch_fifo_empty : 1;
		unsigned int              ttp_tf0_fifo_empty : 1;
		unsigned int              ttp_tf1_fifo_empty : 1;
		unsigned int              ttp_tf2_fifo_empty : 1;
		unsigned int              ttp_tf3_fifo_empty : 1;
		unsigned int              ttp_tf4_fifo_empty : 1;
		unsigned int              ttp_tf5_fifo_empty : 1;
		unsigned int                tf_fetch_state_q : 3;
		unsigned int                   last_tf_of_tg : 1;
		unsigned int                 tf_pointer_p0_q : 4;
		unsigned int                 dynamic_hs_p0_q : 1;
		unsigned int          first_fetch_of_tg_p0_q : 1;
		unsigned int      first_data_ret_of_req_p0_q : 1;
		unsigned int   first_data_chunk_invalid_p0_q : 1;
		unsigned int              tf_xfer_count_p2_q : 2;
		unsigned int                        pipe4_dr : 1;
		unsigned int                       pipe4_rtr : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG30__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG31__CI__VI {
	struct {
                unsigned int                        pipe0_dr : 1;
                unsigned int                       pipe0_rtr : 1;
                unsigned int                  pipe1_outer_dr : 1;
                unsigned int                  pipe1_inner_dr : 1;
                unsigned int                  pipe2_outer_dr : 1;
                unsigned int                  pipe2_inner_dr : 1;
                unsigned int                  pipe3_outer_dr : 1;
                unsigned int                  pipe3_inner_dr : 1;
                unsigned int                  pipe4_outer_dr : 1;
                unsigned int                  pipe4_inner_dr : 1;
                unsigned int                  pipe5_outer_dr : 1;
                unsigned int                  pipe5_inner_dr : 1;
                unsigned int                 pipe2_outer_rtr : 1;
                unsigned int                 pipe2_inner_rtr : 1;
                unsigned int                 pipe3_outer_rtr : 1;
                unsigned int                 pipe3_inner_rtr : 1;
                unsigned int                 pipe4_outer_rtr : 1;
                unsigned int                 pipe4_inner_rtr : 1;
                unsigned int                 pipe5_outer_rtr : 1;
                unsigned int                 pipe5_inner_rtr : 1;
                unsigned int         pg_con_outer_point1_rts : 1;
                unsigned int         pg_con_outer_point2_rts : 1;
                unsigned int         pg_con_inner_point1_rts : 1;
                unsigned int         pg_con_inner_point2_rts : 1;
                unsigned int             pg_patch_fifo_empty : 1;
                unsigned int              pg_edge_fifo_empty : 1;
                unsigned int       pg_inner3_perp_fifo_empty : 1;
                unsigned int              pg_patch_fifo_full : 1;
                unsigned int               pg_edge_fifo_full : 1;
                unsigned int         pg_inner_perp_fifo_full : 1;
                unsigned int               outer_ring_done_q : 1;
                unsigned int               inner_ring_done_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG31__SI {
	struct {
		unsigned int                                 : 12;
		unsigned int                                 : 6;
		unsigned int                                 : 8;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG32__CI__VI {
	struct {
                unsigned int             first_ring_of_patch : 1;
                unsigned int              last_ring_of_patch : 1;
                unsigned int         last_edge_of_outer_ring : 1;
                unsigned int        last_point_of_outer_edge : 1;
                unsigned int         last_edge_of_inner_ring : 1;
                unsigned int        last_point_of_inner_edge : 1;
                unsigned int           last_patch_of_tg_p0_q : 1;
                unsigned int         event_null_special_p0_q : 1;
                unsigned int                 event_flag_p5_q : 1;
                unsigned int       first_point_of_patch_p5_q : 1;
                unsigned int        first_point_of_edge_p5_q : 1;
                unsigned int           last_patch_of_tg_p5_q : 1;
                unsigned int              tess_topology_p5_q : 2;
                unsigned int                pipe5_inner3_rtr : 1;
                unsigned int                pipe5_inner2_rtr : 1;
                unsigned int              pg_edge_fifo3_full : 1;
                unsigned int              pg_edge_fifo2_full : 1;
                unsigned int       pg_inner3_point_fifo_full : 1;
                unsigned int       pg_outer3_point_fifo_full : 1;
                unsigned int       pg_inner2_point_fifo_full : 1;
                unsigned int       pg_outer2_point_fifo_full : 1;
                unsigned int        pg_inner_point_fifo_full : 1;
                unsigned int        pg_outer_point_fifo_full : 1;
                unsigned int                inner2_fifos_rtr : 1;
                unsigned int                 inner_fifos_rtr : 1;
                unsigned int                 outer_fifos_rtr : 1;
                unsigned int                       fifos_rtr : 1;
                unsigned int                           SPARE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG32__SI {
	struct {
		unsigned int                                 : 8;
		unsigned int                                 : 16;
		unsigned int                                 : 5;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                           SPARE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG33__CI__VI {
	struct {
                unsigned int                  pipe0_patch_dr : 1;
                unsigned int                  ring3_pipe1_dr : 1;
                unsigned int                        pipe1_dr : 1;
                unsigned int                        pipe2_dr : 1;
                unsigned int                 pipe0_patch_rtr : 1;
                unsigned int                  ring2_pipe1_dr : 1;
                unsigned int                  ring1_pipe1_dr : 1;
                unsigned int                       pipe2_rtr : 1;
                unsigned int                        pipe3_dr : 1;
                unsigned int                       pipe3_rtr : 1;
                unsigned int                 ring2_in_sync_q : 1;
                unsigned int                 ring1_in_sync_q : 1;
                unsigned int                 pipe1_patch_rtr : 1;
                unsigned int                 ring3_in_sync_q : 1;
                unsigned int               tm_te11_event_rtr : 1;
                unsigned int           first_prim_of_patch_q : 1;
                unsigned int              con_prim_fifo_full : 1;
                unsigned int              con_vert_fifo_full : 1;
                unsigned int             con_prim_fifo_empty : 1;
                unsigned int             con_vert_fifo_empty : 1;
                unsigned int           last_patch_of_tg_p0_q : 1;
                unsigned int                  ring3_valid_p2 : 1;
                unsigned int                  ring2_valid_p2 : 1;
                unsigned int                  ring1_valid_p2 : 1;
                unsigned int                  tess_type_p0_q : 2;
                unsigned int              tess_topology_p0_q : 2;
                unsigned int             te11_out_vert_gs_en : 1;
                unsigned int                  con_ring3_busy : 1;
                unsigned int                  con_ring2_busy : 1;
                unsigned int                  con_ring1_busy : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG33__SI {
	struct {
		unsigned int                                 : 3;
		unsigned int                                 : 5;
		unsigned int                                 : 3;
		unsigned int                                 : 5;
		unsigned int                                 : 3;
		unsigned int                                 : 5;
		unsigned int                                 : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG34__CI__VI {
	struct {
                unsigned int                     con_state_q : 4;
                unsigned int                  second_cycle_q : 1;
                unsigned int         process_tri_middle_p0_q : 1;
                unsigned int   process_tri_1st_2nd_half_p0_q : 1;
                unsigned int    process_tri_center_poly_p0_q : 1;
                unsigned int                  pipe0_patch_dr : 1;
                unsigned int                   pipe0_edge_dr : 1;
                unsigned int                        pipe1_dr : 1;
                unsigned int                 pipe0_patch_rtr : 1;
                unsigned int                  pipe0_edge_rtr : 1;
                unsigned int                       pipe1_rtr : 1;
                unsigned int               outer_parity_p0_q : 1;
                unsigned int            parallel_parity_p0_q : 1;
                unsigned int        first_ring_of_patch_p0_q : 1;
                unsigned int         last_ring_of_patch_p0_q : 1;
                unsigned int    last_edge_of_outer_ring_p0_q : 1;
                unsigned int     last_point_of_outer_ring_p1 : 1;
                unsigned int     last_point_of_inner_ring_p1 : 1;
                unsigned int       outer_edge_tf_eq_one_p0_q : 1;
                unsigned int          advance_outer_point_p1 : 1;
                unsigned int          advance_inner_point_p1 : 1;
                unsigned int          next_ring_is_rect_p0_q : 1;
                unsigned int                pipe1_outer1_rtr : 1;
                unsigned int                pipe1_outer2_rtr : 1;
                unsigned int                pipe1_inner1_rtr : 1;
                unsigned int                pipe1_inner2_rtr : 1;
                unsigned int                 pipe1_patch_rtr : 1;
                unsigned int                  pipe1_edge_rtr : 1;
                unsigned int        use_stored_inner_q_ring1 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG34__SI {
	struct {
		unsigned int                                 : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG35__CI {
	struct {
		unsigned int                        pipe0_dr : 1;
		unsigned int                        pipe1_dr : 1;
		unsigned int                       pipe0_rtr : 1;
		unsigned int                       pipe1_rtr : 1;
		unsigned int             tfreq_tg_fifo_empty : 1;
		unsigned int              tfreq_tg_fifo_full : 1;
		unsigned int             tf_data_fifo_busy_q : 1;
		unsigned int              tf_data_fifo_rtr_q : 1;
		unsigned int              tf_skid_fifo_empty : 1;
		unsigned int               tf_skid_fifo_full : 1;
		unsigned int              vgt_tc_rdreq_rtr_q : 1;
		unsigned int               last_req_of_tg_p2 : 1;
		unsigned int           spi_vgt_hs_done_cnt_q : 6;
		unsigned int                 event_flag_p1_q : 1;
		unsigned int                  null_flag_p1_q : 1;
		unsigned int              tf_data_fifo_cnt_q : 7;
		unsigned int            second_tf_ret_data_q : 1;
		unsigned int            first_req_of_tg_p1_q : 1;
		unsigned int           VGT_TC_rdreq_send_out : 1;
		unsigned int          VGT_TC_rdnfo_stall_out : 1;
		unsigned int            TC_VGT_rdret_data_in : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG35__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 11;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG36__SI {
	struct {
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG36__VI {
	struct {
		unsigned int                VGT_PA_clipp_eop : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG3__CI__VI {
	struct {
                unsigned int                      lsTgRelInd : 12;
                unsigned int                    lsWaveRelInd : 6;
                unsigned int                      lsPatchCnt : 8;
                unsigned int                    hsWaveRelInd : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG3__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG4__CI__VI {
	struct {
                unsigned int                      hsPatchCnt : 8;
                unsigned int                   hsPrimId_15_0 : 16;
                unsigned int                         hsCpCnt : 5;
                unsigned int                 hsWaveSendFlush : 1;
                unsigned int                     hsFwaveFlag : 1;
                unsigned int                           SPARE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG4__SI {
	struct {
		unsigned int                           SPARE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG5__CI__VI {
	struct {
                unsigned int                          SPARE4 : 3;
                unsigned int               hsWaveCreditCnt_0 : 5;
                unsigned int                          SPARE3 : 3;
                unsigned int               hsVertCreditCnt_0 : 5;
                unsigned int                          SPARE2 : 3;
                unsigned int               lsWaveCreditCnt_0 : 5;
                unsigned int                          SPARE1 : 3;
                unsigned int               lsVertCreditCnt_0 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG5__SI {
	struct {
		unsigned int                           SPARE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG6__CI__VI {
	struct {
                unsigned int                      debug_BASE : 16;
                unsigned int                      debug_SIZE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG6__SI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG7__CI__VI {
	struct {
                unsigned int             debug_tfmmFifoEmpty : 1;
                unsigned int              debug_tfmmFifoFull : 1;
                unsigned int                     hs_pipe0_dr : 1;
                unsigned int                    hs_pipe0_rtr : 1;
                unsigned int                    hs_pipe1_rtr : 1;
                unsigned int                           SPARE : 11;
                unsigned int                         TF_addr : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG7__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG8__CI__VI {
	struct {
                unsigned int                      rcm_busy_q : 1;
                unsigned int                 rcm_noif_busy_q : 1;
                unsigned int                     r1_inst_rtr : 1;
                unsigned int          spi_gsprim_fifo_busy_q : 1;
                unsigned int          spi_esvert_fifo_busy_q : 1;
                unsigned int               gs_tbl_valid_r3_q : 1;
                unsigned int                      valid_r0_q : 1;
                unsigned int                      valid_r1_q : 1;
                unsigned int                        valid_r2 : 1;
                unsigned int                      valid_r2_q : 1;
                unsigned int                          r0_rtr : 1;
                unsigned int                          r1_rtr : 1;
                unsigned int                     r2_indx_rtr : 1;
                unsigned int                          r2_rtr : 1;
                unsigned int                       es_gs_rtr : 1;
                unsigned int               gs_event_fifo_rtr : 1;
                unsigned int             tm_rcm_gs_event_rtr : 1;
                unsigned int                   gs_tbl_r3_rtr : 1;
                unsigned int            prim_skid_fifo_empty : 1;
                unsigned int            VGT_SPI_gsprim_rtr_q : 1;
                unsigned int               tm_rcm_gs_tbl_rtr : 1;
                unsigned int               tm_rcm_es_tbl_rtr : 1;
                unsigned int            VGT_SPI_esvert_rtr_q : 1;
                unsigned int                    r2_no_bp_rtr : 1;
                unsigned int               hold_for_es_flush : 1;
                unsigned int             gs_event_fifo_empty : 1;
                unsigned int             gsprim_buff_empty_q : 1;
                unsigned int              gsprim_buff_full_q : 1;
                unsigned int              te_prim_fifo_empty : 1;
                unsigned int               te_prim_fifo_full : 1;
                unsigned int              te_vert_fifo_empty : 1;
                unsigned int               te_vert_fifo_full : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG8__SI {
	struct {
		unsigned int                        rcm_busy : 1;
		unsigned int                   rcm_noif_busy : 1;
		unsigned int                     r1_inst_rtr : 1;
		unsigned int          spi_gsprim_fifo_busy_q : 1;
		unsigned int          spi_esvert_fifo_busy_q : 1;
		unsigned int               gs_tbl_valid_r3_q : 1;
		unsigned int                      valid_r0_q : 1;
		unsigned int                      valid_r1_q : 1;
		unsigned int                        valid_r2 : 1;
		unsigned int                      valid_r2_q : 1;
		unsigned int                          r0_rtr : 1;
		unsigned int                          r1_rtr : 1;
		unsigned int                     r2_indx_rtr : 1;
		unsigned int                          r2_rtr : 1;
		unsigned int                       es_gs_rtr : 1;
		unsigned int               gs_event_fifo_rtr : 1;
		unsigned int             tm_rcm_gs_event_rtr : 1;
		unsigned int                   gs_tbl_r3_rtr : 1;
		unsigned int            prim_skid_fifo_empty : 1;
		unsigned int            VGT_SPI_gsprim_rtr_q : 1;
		unsigned int               tm_rcm_gs_tbl_rtr : 1;
		unsigned int               tm_rcm_es_tbl_rtr : 1;
		unsigned int            VGT_SPI_esvert_rtr_q : 1;
		unsigned int                    r2_no_bp_rtr : 1;
		unsigned int               hold_for_es_flush : 1;
		unsigned int             gs_event_fifo_empty : 1;
		unsigned int             gsprim_buff_empty_q : 1;
		unsigned int              gsprim_buff_full_q : 1;
		unsigned int              te_prim_fifo_empty : 1;
		unsigned int               te_prim_fifo_full : 1;
		unsigned int              te_vert_fifo_empty : 1;
		unsigned int               te_vert_fifo_full : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DEBUG_REG9 {
	struct {
		unsigned int            indices_to_send_r2_q : 2;
		unsigned int                valid_indices_r3 : 1;
		unsigned int                       gs_eov_r3 : 1;
		unsigned int                     eop_indx_r3 : 1;
		unsigned int                     eop_prim_r3 : 1;
		unsigned int                       es_eov_r3 : 1;
		unsigned int             es_tbl_state_r3_q_0 : 1;
		unsigned int            pending_es_send_r3_q : 1;
		unsigned int             pending_es_flush_r3 : 1;
		unsigned int gs_tbl_num_es_per_gs_r3_q_not_0 : 1;
		unsigned int            gs_tbl_prim_cnt_r3_q : 7;
		unsigned int                 gs_tbl_eop_r3_q : 1;
		unsigned int               gs_tbl_state_r3_q : 3;
		unsigned int           gs_pending_state_r3_q : 1;
		unsigned int       invalidate_rb_roll_over_q : 1;
		unsigned int           gs_instancing_state_q : 1;
		unsigned int   es_per_gs_vert_cnt_r3_q_not_0 : 1;
		unsigned int   gs_prim_per_es_ctr_r3_q_not_0 : 1;
		unsigned int                      pre_r0_rtr : 1;
		unsigned int                      valid_r3_q : 1;
		unsigned int                  valid_pre_r0_q : 1;
		unsigned int                          SPARE0 : 1;
		unsigned int                off_chip_hs_r2_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_BASE {
	struct {
		unsigned int                       BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_BASE_HI {
	struct {
		unsigned int                       BASE_ADDR : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_CONTROL__CI__VI {
	struct {
                unsigned int                  PRIMGROUP_SIZE : 16;
                unsigned int                                 : 1;
                unsigned int                IA_SWITCH_ON_EOP : 1;
                unsigned int                                 : 2;
                unsigned int                WD_SWITCH_ON_EOP : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_DATA_FIFO_DEPTH {
	struct {
                unsigned int             DMA_DATA_FIFO_DEPTH : 9;
                unsigned int         DMA2DRAW_FIFO_DEPTH__VI : 10;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_INDEX_TYPE__SI__CI {
	struct {
                unsigned int                      INDEX_TYPE : 2;
                unsigned int                       SWAP_MODE : 2;
                unsigned int                    BUF_TYPE__CI : 2;
                unsigned int                RDREQ_POLICY__CI : 2;
                unsigned int                         ATC__CI : 1;
                unsigned int                     NOT_EOP__CI : 1;
                unsigned int                    REQ_PATH__CI : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_INDEX_TYPE__VI {
	struct {
		unsigned int                      INDEX_TYPE : 2;
		unsigned int                       SWAP_MODE : 2;
		unsigned int                        BUF_TYPE : 2;
		unsigned int                    RDREQ_POLICY : 1;
		unsigned int                                 : 2;
		unsigned int                         NOT_EOP : 1;
		unsigned int                        REQ_PATH : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_LS_HS_CONFIG__CI__VI {
	struct {
                unsigned int                                 : 8;
                unsigned int                 HS_NUM_INPUT_CP : 6;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_MAX_SIZE {
	struct {
		unsigned int                        MAX_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_NUM_INSTANCES {
	struct {
		unsigned int                   NUM_INSTANCES : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_PRIMITIVE_TYPE__CI__VI {
	struct {
                unsigned int                       PRIM_TYPE : 6;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_REQ_FIFO_DEPTH {
	struct {
		unsigned int              DMA_REQ_FIFO_DEPTH : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DMA_SIZE {
	struct {
		unsigned int                     NUM_INDICES : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DRAW_INITIATOR {
	struct {
		unsigned int                   SOURCE_SELECT : 2;
		unsigned int                      MAJOR_MODE : 2;
		unsigned int                  SPRITE_EN_R6XX : 1;
		unsigned int                         NOT_EOP : 1;
		unsigned int                      USE_OPAQUE : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DRAW_INIT_FIFO_DEPTH {
	struct {
		unsigned int            DRAW_INIT_FIFO_DEPTH : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_ENHANCE {
	struct {
		unsigned int                            MISC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_ESGS_RING_ITEMSIZE {
	struct {
		unsigned int                        ITEMSIZE : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_ESGS_RING_SIZE {
	struct {
		unsigned int                        MEM_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_ES_PER_GS {
	struct {
		unsigned int                       ES_PER_GS : 11;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_EVENT_ADDRESS_REG {
	struct {
		unsigned int                     ADDRESS_LOW : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_EVENT_INITIATOR {
	struct {
		unsigned int                      EVENT_TYPE : 6;
		unsigned int                                 : 12;
		unsigned int                      ADDRESS_HI : 9;
		unsigned int                  EXTENDED_EVENT : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_FIFO_DEPTHS {
	struct {
                unsigned int            VS_DEALLOC_TBL_DEPTH : 7;
                unsigned int                                 : 1;
                unsigned int                CLIPP_FIFO_DEPTH : 14;
                unsigned int          HSINPUT_FIFO_DEPTH__VI : 6;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GROUP_DECR {
	struct {
		unsigned int                            DECR : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GROUP_FIRST_DECR {
	struct {
		unsigned int                      FIRST_DECR : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GROUP_PRIM_TYPE {
	struct {
		unsigned int                       PRIM_TYPE : 5;
		unsigned int                                 : 9;
		unsigned int                    RETAIN_ORDER : 1;
		unsigned int                    RETAIN_QUADS : 1;
		unsigned int                      PRIM_ORDER : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GROUP_VECT_0_CNTL {
	struct {
		unsigned int                       COMP_X_EN : 1;
		unsigned int                       COMP_Y_EN : 1;
		unsigned int                       COMP_Z_EN : 1;
		unsigned int                       COMP_W_EN : 1;
		unsigned int                                 : 4;
		unsigned int                          STRIDE : 8;
		unsigned int                           SHIFT : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GROUP_VECT_0_FMT_CNTL {
	struct {
		unsigned int                          X_CONV : 4;
		unsigned int                        X_OFFSET : 4;
		unsigned int                          Y_CONV : 4;
		unsigned int                        Y_OFFSET : 4;
		unsigned int                          Z_CONV : 4;
		unsigned int                        Z_OFFSET : 4;
		unsigned int                          W_CONV : 4;
		unsigned int                        W_OFFSET : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GROUP_VECT_1_CNTL {
	struct {
		unsigned int                       COMP_X_EN : 1;
		unsigned int                       COMP_Y_EN : 1;
		unsigned int                       COMP_Z_EN : 1;
		unsigned int                       COMP_W_EN : 1;
		unsigned int                                 : 4;
		unsigned int                          STRIDE : 8;
		unsigned int                           SHIFT : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GROUP_VECT_1_FMT_CNTL {
	struct {
		unsigned int                          X_CONV : 4;
		unsigned int                        X_OFFSET : 4;
		unsigned int                          Y_CONV : 4;
		unsigned int                        Y_OFFSET : 4;
		unsigned int                          Z_CONV : 4;
		unsigned int                        Z_OFFSET : 4;
		unsigned int                          W_CONV : 4;
		unsigned int                        W_OFFSET : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GSVS_RING_ITEMSIZE {
	struct {
		unsigned int                        ITEMSIZE : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GSVS_RING_OFFSET_1 {
	struct {
		unsigned int                          OFFSET : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GSVS_RING_OFFSET_2 {
	struct {
		unsigned int                          OFFSET : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GSVS_RING_OFFSET_3 {
	struct {
		unsigned int                          OFFSET : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GSVS_RING_SIZE {
	struct {
		unsigned int                        MEM_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_INSTANCE_CNT {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                             CNT : 7;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_MAX_VERT_OUT {
	struct {
		unsigned int                    MAX_VERT_OUT : 11;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_MODE {
	struct {
                unsigned int                            MODE : 3;
                unsigned int                  RESERVED_0__VI : 1;
                unsigned int                        CUT_MODE : 2;
                unsigned int                  RESERVED_1__VI : 5;
                unsigned int                    GS_C_PACK_EN : 1;
                unsigned int                  RESERVED_2__VI : 1;
                unsigned int                     ES_PASSTHRU : 1;
                unsigned int                    COMPUTE_MODE : 1;
                unsigned int               FAST_COMPUTE_MODE : 1;
                unsigned int                 ELEMENT_INFO_EN : 1;
                unsigned int              PARTIAL_THD_AT_EOI : 1;
                unsigned int                   SUPPRESS_CUTS : 1;
                unsigned int               ES_WRITE_OPTIMIZE : 1;
                unsigned int               GS_WRITE_OPTIMIZE : 1;
                unsigned int                  ONCHIP__CI__VI : 2;
                unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_ONCHIP_CNTL__CI__VI {
	struct {
                unsigned int             ES_VERTS_PER_SUBGRP : 11;
                unsigned int             GS_PRIMS_PER_SUBGRP : 11;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_OUT_PRIM_TYPE {
	struct {
		unsigned int                    OUTPRIM_TYPE : 6;
		unsigned int                                 : 2;
		unsigned int                  OUTPRIM_TYPE_1 : 6;
		unsigned int                                 : 2;
		unsigned int                  OUTPRIM_TYPE_2 : 6;
		unsigned int                  OUTPRIM_TYPE_3 : 6;
		unsigned int                                 : 3;
		unsigned int          UNIQUE_TYPE_PER_STREAM : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_PER_ES {
	struct {
		unsigned int                       GS_PER_ES : 11;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_PER_VS {
	struct {
		unsigned int                       GS_PER_VS : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_VERTEX_REUSE {
	struct {
		unsigned int                      VERT_REUSE : 5;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_VERT_ITEMSIZE {
	struct {
		unsigned int                        ITEMSIZE : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_VERT_ITEMSIZE_1 {
	struct {
		unsigned int                        ITEMSIZE : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_VERT_ITEMSIZE_2 {
	struct {
		unsigned int                        ITEMSIZE : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_GS_VERT_ITEMSIZE_3 {
	struct {
		unsigned int                        ITEMSIZE : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_HOS_CNTL {
	struct {
		unsigned int                       TESS_MODE : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_HOS_MAX_TESS_LEVEL {
	struct {
		unsigned int                        MAX_TESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_HOS_MIN_TESS_LEVEL {
	struct {
		unsigned int                        MIN_TESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_HOS_REUSE_DEPTH {
	struct {
		unsigned int                     REUSE_DEPTH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_HS_OFFCHIP_PARAM {
	struct {
                unsigned int               OFFCHIP_BUFFERING : 9;
                unsigned int     OFFCHIP_GRANULARITY__CI__VI : 2;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_IMMED_DATA {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_INDEX_TYPE {
	struct {
		unsigned int                      INDEX_TYPE : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_INDX_OFFSET {
	struct {
		unsigned int                     INDX_OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_INSTANCE_STEP_RATE_0 {
	struct {
		unsigned int                       STEP_RATE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_INSTANCE_STEP_RATE_1 {
	struct {
		unsigned int                       STEP_RATE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_LAST_COPY_STATE {
	struct {
		unsigned int                    SRC_STATE_ID : 3;
		unsigned int                                 : 13;
		unsigned int                    DST_STATE_ID : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_LS_HS_CONFIG {
	struct {
		unsigned int                     NUM_PATCHES : 8;
		unsigned int                 HS_NUM_INPUT_CP : 6;
		unsigned int                HS_NUM_OUTPUT_CP : 6;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_MAX_VTX_INDX {
	struct {
		unsigned int                        MAX_INDX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_MC_LAT_CNTL {
	struct {
		unsigned int               MC_TIME_STAMP_RES : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_MIN_VTX_INDX {
	struct {
		unsigned int                        MIN_INDX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_MULTI_PRIM_IB_RESET_EN {
	struct {
		unsigned int                        RESET_EN : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_MULTI_PRIM_IB_RESET_INDX {
	struct {
		unsigned int                      RESET_INDX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_NUM_INDICES {
	struct {
		unsigned int                     NUM_INDICES : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_NUM_INSTANCES {
	struct {
		unsigned int                   NUM_INSTANCES : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_OUTPUT_PATH_CNTL {
	struct {
		unsigned int                     PATH_SELECT : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_OUT_DEALLOC_CNTL {
	struct {
		unsigned int                    DEALLOC_DIST : 7;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER0_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER0_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER0_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE3 : 4;
                unsigned int                      PERF_MODE2 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                       PERF_SEL1 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER0_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER1_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER1_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER1_SELECT1__CI__VI {
	struct {
                unsigned int                       PERF_SEL2 : 10;
                unsigned int                       PERF_SEL3 : 10;
                unsigned int                                 : 4;
                unsigned int                      PERF_MODE3 : 4;
                unsigned int                      PERF_MODE2 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 10;
                unsigned int                       PERF_SEL1 : 10;
                unsigned int                       CNTR_MODE : 4;
                unsigned int                      PERF_MODE1 : 4;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER1_SELECT__SI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER2_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER2_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER2_SELECT {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER3_HI {
	struct {
		unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER3_LO {
	struct {
		unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER3_SELECT {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                                 : 20;
		unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PERFCOUNTER_SEID_MASK {
	struct {
		unsigned int           PERF_SEID_IGNORE_MASK : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PRIMITIVEID_EN {
	struct {
		unsigned int                  PRIMITIVEID_EN : 1;
		unsigned int            DISABLE_RESET_ON_EOI : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PRIMITIVEID_RESET {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_PRIMITIVE_TYPE {
	struct {
		unsigned int                       PRIM_TYPE : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_RESET_DEBUG__CI__VI {
	struct {
                unsigned int                      GS_DISABLE : 1;
                unsigned int                    TESS_DISABLE : 1;
                unsigned int                      WD_DISABLE : 1;
                unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_REUSE_OFF {
	struct {
		unsigned int                       REUSE_OFF : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_SHADER_STAGES_EN {
	struct {
                unsigned int                           LS_EN : 2;
                unsigned int                           HS_EN : 1;
                unsigned int                           ES_EN : 2;
                unsigned int                           GS_EN : 1;
                unsigned int                           VS_EN : 2;
                unsigned int                      DYNAMIC_HS : 1;
                unsigned int            DISPATCH_DRAW_EN__VI : 1;
                unsigned int         DIS_DEALLOC_ACCUM_0__VI : 1;
                unsigned int         DIS_DEALLOC_ACCUM_1__VI : 1;
                unsigned int               VS_WAVE_ID_EN__VI : 1;
                unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_CONFIG {
	struct {
		unsigned int              STREAM_0_BUFFER_EN : 4;
		unsigned int              STREAM_1_BUFFER_EN : 4;
		unsigned int              STREAM_2_BUFFER_EN : 4;
		unsigned int              STREAM_3_BUFFER_EN : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_FILLED_SIZE_0 {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_FILLED_SIZE_1 {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_FILLED_SIZE_2 {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_FILLED_SIZE_3 {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_OFFSET_0 {
	struct {
		unsigned int                          OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_OFFSET_1 {
	struct {
		unsigned int                          OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_OFFSET_2 {
	struct {
		unsigned int                          OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_OFFSET_3 {
	struct {
		unsigned int                          OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_SIZE_0 {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_SIZE_1 {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_SIZE_2 {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_BUFFER_SIZE_3 {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_CONFIG {
	struct {
		unsigned int                  STREAMOUT_0_EN : 1;
		unsigned int                  STREAMOUT_1_EN : 1;
		unsigned int                  STREAMOUT_2_EN : 1;
		unsigned int                  STREAMOUT_3_EN : 1;
		unsigned int                     RAST_STREAM : 3;
		unsigned int                                 : 1;
		unsigned int                RAST_STREAM_MASK : 4;
		unsigned int                                 : 19;
		unsigned int            USE_RAST_STREAM_MASK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_DELAY__CI__VI {
	struct {
                unsigned int                      SKIP_DELAY : 8;
                unsigned int                    SE0_WD_DELAY : 3;
                unsigned int                    SE1_WD_DELAY : 3;
                unsigned int                    SE2_WD_DELAY : 3;
                unsigned int                    SE3_WD_DELAY : 3;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE {
	struct {
		unsigned int                            SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_DRAW_OPAQUE_OFFSET {
	struct {
		unsigned int                          OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE {
	struct {
		unsigned int                   VERTEX_STRIDE : 9;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_VTX_STRIDE_0 {
	struct {
		unsigned int                          STRIDE : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_VTX_STRIDE_1 {
	struct {
		unsigned int                          STRIDE : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_VTX_STRIDE_2 {
	struct {
		unsigned int                          STRIDE : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_STRMOUT_VTX_STRIDE_3 {
	struct {
		unsigned int                          STRIDE : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_SYS_CONFIG {
	struct {
		unsigned int                    DUAL_CORE_EN : 1;
		unsigned int                MAX_LS_HS_THDGRP : 6;
		unsigned int        ADC_EVENT_FILTER_DISABLE : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_TF_MEMORY_BASE {
	struct {
		unsigned int                            BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_TF_PARAM {
	struct {
                unsigned int                            TYPE : 2;
                unsigned int                    PARTITIONING : 3;
                unsigned int                        TOPOLOGY : 3;
                unsigned int                                 : 1;
                unsigned int                      DEPRECATED : 1;
                unsigned int           NUM_DS_WAVES_PER_SIMD : 4;
                unsigned int                  DISABLE_DONUTS : 1;
                unsigned int            RDREQ_POLICY__CI__VI : 2;
                unsigned int           DISTRIBUTION_MODE__VI : 2;
                unsigned int                       MTYPE__VI : 2;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_TF_RING_SIZE {
	struct {
		unsigned int                            SIZE : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_VERTEX_REUSE_BLOCK_CNTL {
	struct {
		unsigned int                 VTX_REUSE_DEPTH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_VS_MAX_WAVE_ID__CI__VI {
	struct {
                unsigned int                     MAX_WAVE_ID : 12;
                unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_VTX_CNT_EN {
	struct {
		unsigned int                      VTX_CNT_EN : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_VTX_VECT_EJECT_REG {
	struct {
		unsigned int                      PRIM_COUNT : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VIEWPORT_SIZE__SI__VI {
	struct {
                unsigned int                 VIEWPORT_HEIGHT : 14;
                unsigned int                                 : 2;
                unsigned int                  VIEWPORT_WIDTH : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VIEWPORT_START__SI__VI {
	struct {
                unsigned int                VIEWPORT_Y_START : 14;
                unsigned int                                 : 2;
                unsigned int                VIEWPORT_X_START : 14;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VLINE_START_END__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int                                 : 2;
		unsigned int                                 : 14;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VLINE_STATUS__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT0_CNTL__SI__CI {
	struct {
		unsigned int                  ENABLE_CONTEXT : 1;
		unsigned int                PAGE_TABLE_DEPTH : 2;
		unsigned int RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int RANGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int                                 : 1;
		unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int                                 : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int           PAGE_TABLE_BLOCK_SIZE : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT0_CNTL__VI {
	struct {
		unsigned int                  ENABLE_CONTEXT : 1;
		unsigned int                PAGE_TABLE_DEPTH : 2;
		unsigned int RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int RANGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int                                 : 1;
		unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int                                 : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int           PAGE_TABLE_BLOCK_SIZE : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT0_CNTL2 {
	struct {
		unsigned int CLEAR_PROTECTION_FAULT_STATUS_ADDR : 1;
		unsigned int ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT : 1;
		unsigned int ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT : 1;
		unsigned int ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES : 1;
		unsigned int   WAIT_FOR_IDLE_WHEN_INVALIDATE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT0_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT0_PAGE_TABLE_END_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT0_PAGE_TABLE_START_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT0_PROTECTION_FAULT_ADDR {
	struct {
		unsigned int               LOGICAL_PAGE_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR {
	struct {
		unsigned int              PHYSICAL_PAGE_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__CI__VI {
	struct {
                unsigned int                            NAME : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT0_PROTECTION_FAULT_STATUS {
	struct {
                unsigned int                     PROTECTIONS : 8;
                unsigned int                                 : 4;
                unsigned int                MEMORY_CLIENT_ID : 9;
                unsigned int                                 : 3;
                unsigned int                MEMORY_CLIENT_RW : 1;
                unsigned int                            VMID : 4;
                unsigned int                      ATOMIC__VI : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT10_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT11_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT12_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT13_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT14_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT15_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT1_CNTL__SI__CI {
	struct {
		unsigned int                  ENABLE_CONTEXT : 1;
		unsigned int                PAGE_TABLE_DEPTH : 2;
		unsigned int RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int RANGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int                                 : 1;
		unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int                                 : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int           PAGE_TABLE_BLOCK_SIZE : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT1_CNTL__VI {
	struct {
		unsigned int                  ENABLE_CONTEXT : 1;
		unsigned int                PAGE_TABLE_DEPTH : 2;
		unsigned int RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int RANGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int                                 : 1;
		unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int                                 : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int PDE0_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int VALID_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int READ_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int WRITE_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1;
		unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT : 1;
		unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_SAVE : 1;
		unsigned int           PAGE_TABLE_BLOCK_SIZE : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT1_CNTL2 {
	struct {
		unsigned int CLEAR_PROTECTION_FAULT_STATUS_ADDR : 1;
		unsigned int ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT : 1;
		unsigned int ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT : 1;
		unsigned int ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES : 1;
		unsigned int   WAIT_FOR_IDLE_WHEN_INVALIDATE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT1_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT1_PAGE_TABLE_END_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT1_PAGE_TABLE_START_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT1_PROTECTION_FAULT_ADDR {
	struct {
		unsigned int               LOGICAL_PAGE_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR {
	struct {
		unsigned int              PHYSICAL_PAGE_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__CI__VI {
	struct {
                unsigned int                            NAME : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT1_PROTECTION_FAULT_STATUS {
	struct {
                unsigned int                     PROTECTIONS : 8;
                unsigned int                                 : 4;
                unsigned int                MEMORY_CLIENT_ID : 9;
                unsigned int                                 : 3;
                unsigned int                MEMORY_CLIENT_RW : 1;
                unsigned int                            VMID : 4;
                unsigned int                      ATOMIC__VI : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT2_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT3_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT4_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT5_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT6_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT7_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT8_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXT9_PAGE_TABLE_BASE_ADDR {
	struct {
		unsigned int            PHYSICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_CONTEXTS_DISABLE {
	struct {
		unsigned int               DISABLE_CONTEXT_0 : 1;
		unsigned int               DISABLE_CONTEXT_1 : 1;
		unsigned int               DISABLE_CONTEXT_2 : 1;
		unsigned int               DISABLE_CONTEXT_3 : 1;
		unsigned int               DISABLE_CONTEXT_4 : 1;
		unsigned int               DISABLE_CONTEXT_5 : 1;
		unsigned int               DISABLE_CONTEXT_6 : 1;
		unsigned int               DISABLE_CONTEXT_7 : 1;
		unsigned int               DISABLE_CONTEXT_8 : 1;
		unsigned int               DISABLE_CONTEXT_9 : 1;
		unsigned int              DISABLE_CONTEXT_10 : 1;
		unsigned int              DISABLE_CONTEXT_11 : 1;
		unsigned int              DISABLE_CONTEXT_12 : 1;
		unsigned int              DISABLE_CONTEXT_13 : 1;
		unsigned int              DISABLE_CONTEXT_14 : 1;
		unsigned int              DISABLE_CONTEXT_15 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_DEBUG {
	struct {
		unsigned int                           FLAGS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_DUMMY_PAGE_FAULT_ADDR {
	struct {
		unsigned int                 DUMMY_PAGE_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_DUMMY_PAGE_FAULT_CNTL {
	struct {
		unsigned int         DUMMY_PAGE_FAULT_ENABLE : 1;
		unsigned int      DUMMY_PAGE_ADDRESS_LOGICAL : 1;
		unsigned int         DUMMY_PAGE_COMPARE_MASK : 2;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_FAULT_CLIENT_ID {
	struct {
                unsigned int                   MEMORY_CLIENT : 9;
                unsigned int              MEMORY_CLIENT_MASK : 9;
                unsigned int        MEMORY_CLIENT_ID_MSB__VI : 1;
                unsigned int   MEMORY_CLIENT_ID_MASK_MSB__VI : 1;
                unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_INVALIDATE_REQUEST {
	struct {
		unsigned int             INVALIDATE_DOMAIN_0 : 1;
		unsigned int             INVALIDATE_DOMAIN_1 : 1;
		unsigned int             INVALIDATE_DOMAIN_2 : 1;
		unsigned int             INVALIDATE_DOMAIN_3 : 1;
		unsigned int             INVALIDATE_DOMAIN_4 : 1;
		unsigned int             INVALIDATE_DOMAIN_5 : 1;
		unsigned int             INVALIDATE_DOMAIN_6 : 1;
		unsigned int             INVALIDATE_DOMAIN_7 : 1;
		unsigned int             INVALIDATE_DOMAIN_8 : 1;
		unsigned int             INVALIDATE_DOMAIN_9 : 1;
		unsigned int            INVALIDATE_DOMAIN_10 : 1;
		unsigned int            INVALIDATE_DOMAIN_11 : 1;
		unsigned int            INVALIDATE_DOMAIN_12 : 1;
		unsigned int            INVALIDATE_DOMAIN_13 : 1;
		unsigned int            INVALIDATE_DOMAIN_14 : 1;
		unsigned int            INVALIDATE_DOMAIN_15 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_INVALIDATE_RESPONSE {
	struct {
		unsigned int            DOMAIN_INVALIDATED_0 : 1;
		unsigned int            DOMAIN_INVALIDATED_1 : 1;
		unsigned int            DOMAIN_INVALIDATED_2 : 1;
		unsigned int            DOMAIN_INVALIDATED_3 : 1;
		unsigned int            DOMAIN_INVALIDATED_4 : 1;
		unsigned int            DOMAIN_INVALIDATED_5 : 1;
		unsigned int            DOMAIN_INVALIDATED_6 : 1;
		unsigned int            DOMAIN_INVALIDATED_7 : 1;
		unsigned int            DOMAIN_INVALIDATED_8 : 1;
		unsigned int            DOMAIN_INVALIDATED_9 : 1;
		unsigned int           DOMAIN_INVALIDATED_10 : 1;
		unsigned int           DOMAIN_INVALIDATED_11 : 1;
		unsigned int           DOMAIN_INVALIDATED_12 : 1;
		unsigned int           DOMAIN_INVALIDATED_13 : 1;
		unsigned int           DOMAIN_INVALIDATED_14 : 1;
		unsigned int           DOMAIN_INVALIDATED_15 : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_BANK_SELECT_MASKA {
	struct {
		unsigned int                BANK_SELECT_MASK : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_BANK_SELECT_MASKB {
	struct {
                unsigned int                BANK_SELECT_MASK : 9;
                unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_CG {
	struct {
                unsigned int                                 : 6;
                unsigned int                          OFFDLY : 6;
                unsigned int                                 : 6;
                unsigned int                          ENABLE : 1;
                unsigned int                   MEM_LS_ENABLE : 1;
                unsigned int                    OVERRIDE__VI : 1;
                unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_CNTL2 {
	struct {
                unsigned int          INVALIDATE_ALL_L1_TLBS : 1;
                unsigned int             INVALIDATE_L2_CACHE : 1;
                unsigned int                                 : 19;
                unsigned int   DISABLE_INVALIDATE_PER_DOMAIN : 1;
                unsigned int DISABLE_BIGK_CACHE_OPTIMIZATION : 1;
                unsigned int         L2_CACHE_BIGK_VMID_MODE : 3;
                unsigned int           INVALIDATE_CACHE_MODE : 2;
                unsigned int PDE_CACHE_EFFECTIVE_SIZE__CI__VI : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_CNTL3 {
	struct {
                unsigned int                     BANK_SELECT : 6;
                unsigned int            L2_CACHE_UPDATE_MODE : 2;
                unsigned int L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE : 5;
                unsigned int                                 : 2;
                unsigned int     L2_CACHE_BIGK_FRAGMENT_SIZE : 5;
                unsigned int     L2_CACHE_BIGK_ASSOCIATIVITY : 1;
                unsigned int      L2_CACHE_4K_EFFECTIVE_SIZE : 3;
                unsigned int    L2_CACHE_BIGK_EFFECTIVE_SIZE : 4;
                unsigned int          L2_CACHE_4K_FORCE_MISS : 1;
                unsigned int        L2_CACHE_BIGK_FORCE_MISS : 1;
                unsigned int    PDE_CACHE_FORCE_MISS__CI__VI : 1;
                unsigned int   L2_CACHE_4K_ASSOCIATIVITY__VI : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_CNTL__CI__VI {
	struct {
                unsigned int                 ENABLE_L2_CACHE : 1;
                unsigned int   ENABLE_L2_FRAGMENT_PROCESSING : 1;
                unsigned int   L2_CACHE_PTE_ENDIAN_SWAP_MODE : 2;
                unsigned int   L2_CACHE_PDE_ENDIAN_SWAP_MODE : 2;
                unsigned int                                 : 2;
                unsigned int L2_PDE0_CACHE_TAG_GENERATION_MODE : 1;
                unsigned int ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE : 1;
                unsigned int ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE : 1;
                unsigned int ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY : 1;
                unsigned int        L2_PDE0_CACHE_SPLIT_MODE : 3;
                unsigned int         EFFECTIVE_L2_QUEUE_SIZE : 3;
                unsigned int        PDE_FAULT_CLASSIFICATION : 1;
                unsigned int   CONTEXT1_IDENTITY_ACCESS_MODE : 2;
                unsigned int     IDENTITY_MODE_FRAGMENT_SIZE : 5;
                unsigned int L2_CACHE_4K_SWAP_TAG_INDEX_LSBS : 2;
                unsigned int L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS : 3;
                unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_CNTL__SI {
	struct {
		unsigned int                 ENABLE_L2_CACHE : 1;
		unsigned int   ENABLE_L2_FRAGMENT_PROCESSING : 1;
		unsigned int   L2_CACHE_PTE_ENDIAN_SWAP_MODE : 2;
		unsigned int   L2_CACHE_PDE_ENDIAN_SWAP_MODE : 2;
		unsigned int                                 : 2;
		unsigned int L2_PDE0_CACHE_TAG_GENERATION_MODE : 1;
		unsigned int ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE : 1;
		unsigned int ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE : 1;
		unsigned int                                 : 1;
		unsigned int        L2_PDE0_CACHE_SPLIT_MODE : 3;
		unsigned int         EFFECTIVE_L2_QUEUE_SIZE : 3;
		unsigned int        PDE_FAULT_CLASSIFICATION : 1;
		unsigned int   CONTEXT1_IDENTITY_ACCESS_MODE : 2;
		unsigned int     IDENTITY_MODE_FRAGMENT_SIZE : 5;
		unsigned int L2_CACHE_4K_SWAP_TAG_INDEX_LSBS : 2;
		unsigned int L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET {
	struct {
		unsigned int            PHYSICAL_PAGE_OFFSET : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_STATUS {
	struct {
		unsigned int                         L2_BUSY : 1;
		unsigned int             CONTEXT_DOMAIN_BUSY : 16;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_PRT_APERTURE0_HIGH_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_PRT_APERTURE0_LOW_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_PRT_APERTURE1_HIGH_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_PRT_APERTURE1_LOW_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_PRT_APERTURE2_HIGH_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_PRT_APERTURE2_LOW_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_PRT_APERTURE3_HIGH_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_PRT_APERTURE3_LOW_ADDR {
	struct {
		unsigned int             LOGICAL_PAGE_NUMBER : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_PRT_CNTL__CI__VI {
	struct {
                unsigned int CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS : 1;
                unsigned int TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS : 1;
                unsigned int  L2_CACHE_STORE_INVALID_ENTRIES : 1;
                unsigned int    L1_TLB_STORE_INVALID_ENTRIES : 1;
                unsigned int CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS : 1;
                unsigned int TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS : 1;
                unsigned int                 MASK_PDE0_FAULT : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_PRT_CNTL__SI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int  L2_CACHE_STORE_INVALID_ENTRIES : 1;
		unsigned int    L1_TLB_STORE_INVALID_ENTRIES : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union V_COUNTER__SI {
	struct {
		unsigned int                                 : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WAKE_ENABLE__SI__VI {
	struct {
                unsigned int           SDIN_WAKE_ENABLE_FLAG : 1;
                unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WALL_CLOCK_COUNTER_ALIAS__SI__VI {
	struct {
                unsigned int        WALL_CLOCK_COUNTER_ALIAS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WALL_CLOCK_COUNTER__SI__VI {
	struct {
                unsigned int              WALL_CLOCK_COUNTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_CNTL_STATUS__CI__VI {
	struct {
                unsigned int                         WD_BUSY : 1;
                unsigned int                 WD_SPL_DMA_BUSY : 1;
                unsigned int                  WD_SPL_DI_BUSY : 1;
                unsigned int                     WD_ADC_BUSY : 1;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_CNTL__CI__VI {
	struct {
                unsigned int                   WD_DEBUG_INDX : 6;
                unsigned int              WD_DEBUG_SEL_BUS_B : 1;
                unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_DATA__CI__VI {
	struct {
                unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG0__CI__VI {
	struct {
                unsigned int                wd_busy_extended : 1;
                unsigned int          wd_nodma_busy_extended : 1;
                unsigned int                         wd_busy : 1;
                unsigned int                   wd_nodma_busy : 1;
                unsigned int                       rbiu_busy : 1;
                unsigned int                    spl_dma_busy : 1;
                unsigned int                     spl_di_busy : 1;
                unsigned int                   vgt0_active_q : 1;
                unsigned int                   vgt1_active_q : 1;
                unsigned int                 spl_dma_p1_busy : 1;
                unsigned int            rbiu_dr_p1_fifo_busy : 1;
                unsigned int            rbiu_di_p1_fifo_busy : 1;
                unsigned int                          SPARE2 : 1;
                unsigned int               rbiu_dr_fifo_busy : 1;
                unsigned int               rbiu_spl_dr_valid : 1;
                unsigned int                spl_rbiu_dr_read : 1;
                unsigned int                          SPARE3 : 1;
                unsigned int               rbiu_di_fifo_busy : 1;
                unsigned int               rbiu_spl_di_valid : 1;
                unsigned int                spl_rbiu_di_read : 1;
                unsigned int                    se0_synced_q : 1;
                unsigned int                    se1_synced_q : 1;
                unsigned int                    se2_synced_q : 1;
                unsigned int                    se3_synced_q : 1;
                unsigned int                    reg_clk_busy : 1;
                unsigned int                  input_clk_busy : 1;
                unsigned int                   core_clk_busy : 1;
                unsigned int                   vgt2_active_q : 1;
                unsigned int                    sclk_reg_vld : 1;
                unsigned int                  sclk_input_vld : 1;
                unsigned int                   sclk_core_vld : 1;
                unsigned int                   vgt3_active_q : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG1__CI__VI {
	struct {
                unsigned int                 grbm_fifo_empty : 1;
                unsigned int                  grbm_fifo_full : 1;
                unsigned int                    grbm_fifo_we : 1;
                unsigned int                    grbm_fifo_re : 1;
                unsigned int          draw_initiator_valid_q : 1;
                unsigned int         event_initiator_valid_q : 1;
                unsigned int              event_addr_valid_q : 1;
                unsigned int             dma_request_valid_q : 1;
                unsigned int                          SPARE0 : 1;
                unsigned int                min_indx_valid_q : 1;
                unsigned int                max_indx_valid_q : 1;
                unsigned int             indx_offset_valid_q : 1;
                unsigned int          grbm_fifo_rdata_reg_id : 5;
                unsigned int           grbm_fifo_rdata_state : 3;
                unsigned int                      free_cnt_q : 6;
                unsigned int                 rbiu_di_fifo_we : 1;
                unsigned int                 rbiu_dr_fifo_we : 1;
                unsigned int              rbiu_di_fifo_empty : 1;
                unsigned int               rbiu_di_fifo_full : 1;
                unsigned int              rbiu_dr_fifo_empty : 1;
                unsigned int               rbiu_dr_fifo_full : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG2__CI__VI {
	struct {
                unsigned int              p1_grbm_fifo_empty : 1;
                unsigned int               p1_grbm_fifo_full : 1;
                unsigned int                 p1_grbm_fifo_we : 1;
                unsigned int                 p1_grbm_fifo_re : 1;
                unsigned int       p1_draw_initiator_valid_q : 1;
                unsigned int      p1_event_initiator_valid_q : 1;
                unsigned int           p1_event_addr_valid_q : 1;
                unsigned int          p1_dma_request_valid_q : 1;
                unsigned int                          SPARE0 : 1;
                unsigned int             p1_min_indx_valid_q : 1;
                unsigned int             p1_max_indx_valid_q : 1;
                unsigned int          p1_indx_offset_valid_q : 1;
                unsigned int       p1_grbm_fifo_rdata_reg_id : 5;
                unsigned int        p1_grbm_fifo_rdata_state : 3;
                unsigned int                   p1_free_cnt_q : 6;
                unsigned int              p1_rbiu_di_fifo_we : 1;
                unsigned int              p1_rbiu_dr_fifo_we : 1;
                unsigned int           p1_rbiu_di_fifo_empty : 1;
                unsigned int            p1_rbiu_di_fifo_full : 1;
                unsigned int           p1_rbiu_dr_fifo_empty : 1;
                unsigned int            p1_rbiu_dr_fifo_full : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG3__CI__VI {
	struct {
                unsigned int               rbiu_spl_dr_valid : 1;
                unsigned int                          SPARE0 : 1;
                unsigned int                        pipe0_dr : 1;
                unsigned int                       pipe0_rtr : 1;
                unsigned int                        pipe1_dr : 1;
                unsigned int                       pipe1_rtr : 1;
                unsigned int            wd_subdma_fifo_empty : 1;
                unsigned int             wd_subdma_fifo_full : 1;
                unsigned int               dma_buf_type_p0_q : 2;
                unsigned int           dma_zero_indices_p0_q : 1;
                unsigned int               dma_req_path_p3_q : 1;
                unsigned int                dma_not_eop_p1_q : 1;
                unsigned int                 out_of_range_p4 : 1;
                unsigned int               last_sub_dma_p3_q : 1;
                unsigned int        last_rdreq_of_sub_dma_p4 : 1;
                unsigned int                WD_IA_dma_send_d : 1;
                unsigned int                   WD_IA_dma_rtr : 1;
                unsigned int               WD_IA1_dma_send_d : 1;
                unsigned int                  WD_IA1_dma_rtr : 1;
                unsigned int             last_inst_of_dma_p2 : 1;
                unsigned int              last_sd_of_inst_p2 : 1;
                unsigned int               last_sd_of_dma_p2 : 1;
                unsigned int                          SPARE1 : 1;
                unsigned int                  WD_IA_dma_busy : 1;
                unsigned int                 WD_IA1_dma_busy : 1;
                unsigned int                send_to_ia1_p3_q : 1;
                unsigned int       dma_wd_switch_on_eop_p3_q : 1;
                unsigned int                        pipe3_dr : 1;
                unsigned int                       pipe3_rtr : 1;
                unsigned int          wd_dma2draw_fifo_empty : 1;
                unsigned int           wd_dma2draw_fifo_full : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG4__CI__VI {
	struct {
                unsigned int               rbiu_spl_di_valid : 1;
                unsigned int                spl_rbiu_di_read : 1;
                unsigned int            rbiu_spl_p1_di_valid : 1;
                unsigned int             spl_rbiu_p1_di_read : 1;
                unsigned int                        pipe0_dr : 1;
                unsigned int                       pipe0_rtr : 1;
                unsigned int                        pipe1_dr : 1;
                unsigned int                       pipe1_rtr : 1;
                unsigned int                        pipe2_dr : 1;
                unsigned int                       pipe2_rtr : 1;
                unsigned int                        pipe3_ld : 1;
                unsigned int                       pipe3_rtr : 1;
                unsigned int               WD_IA_draw_send_d : 1;
                unsigned int                  WD_IA_draw_rtr : 1;
                unsigned int                      di_type_p0 : 2;
                unsigned int               di_state_sel_p1_q : 3;
                unsigned int        di_wd_switch_on_eop_p1_q : 1;
                unsigned int          rbiu_spl_pipe0_lockout : 1;
                unsigned int              last_inst_of_di_p2 : 1;
                unsigned int              last_sd_of_inst_p2 : 1;
                unsigned int                last_sd_of_di_p2 : 1;
                unsigned int               not_eop_wait_p1_q : 1;
                unsigned int                  not_eop_wait_q : 1;
                unsigned int             ext_event_wait_p1_q : 1;
                unsigned int                ext_event_wait_q : 1;
                unsigned int              WD_IA1_draw_send_d : 1;
                unsigned int                 WD_IA1_draw_rtr : 1;
                unsigned int                   send_to_ia1_q : 1;
                unsigned int                    dual_ia_mode : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG5__CI__VI {
	struct {
                unsigned int            p1_rbiu_spl_dr_valid : 1;
                unsigned int                          SPARE0 : 1;
                unsigned int                     p1_pipe0_dr : 1;
                unsigned int                    p1_pipe0_rtr : 1;
                unsigned int                     p1_pipe1_dr : 1;
                unsigned int                    p1_pipe1_rtr : 1;
                unsigned int         p1_wd_subdma_fifo_empty : 1;
                unsigned int          p1_wd_subdma_fifo_full : 1;
                unsigned int            p1_dma_buf_type_p0_q : 2;
                unsigned int        p1_dma_zero_indices_p0_q : 1;
                unsigned int            p1_dma_req_path_p3_q : 1;
                unsigned int             p1_dma_not_eop_p1_q : 1;
                unsigned int              p1_out_of_range_p4 : 1;
                unsigned int            p1_last_sub_dma_p3_q : 1;
                unsigned int     p1_last_rdreq_of_sub_dma_p4 : 1;
                unsigned int             p1_WD_IA_dma_send_d : 1;
                unsigned int                p1_WD_IA_dma_rtr : 1;
                unsigned int            p1_WD_IA1_dma_send_d : 1;
                unsigned int               p1_WD_IA1_dma_rtr : 1;
                unsigned int          p1_last_inst_of_dma_p2 : 1;
                unsigned int           p1_last_sd_of_inst_p2 : 1;
                unsigned int            p1_last_sd_of_dma_p2 : 1;
                unsigned int                          SPARE1 : 1;
                unsigned int               p1_WD_IA_dma_busy : 1;
                unsigned int              p1_WD_IA1_dma_busy : 1;
                unsigned int             p1_send_to_ia1_p3_q : 1;
                unsigned int    p1_dma_wd_switch_on_eop_p3_q : 1;
                unsigned int                     p1_pipe3_dr : 1;
                unsigned int                    p1_pipe3_rtr : 1;
                unsigned int       p1_wd_dma2draw_fifo_empty : 1;
                unsigned int        p1_wd_dma2draw_fifo_full : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_ENHANCE__CI__VI {
	struct {
                unsigned int                            MISC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER0_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER0_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER0_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                                 : 20;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER1_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER1_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER1_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                                 : 20;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER2_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER2_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER2_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                                 : 20;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER3_HI__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER3_LO__CI__VI {
	struct {
                unsigned int                  PERFCOUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_PERFCOUNTER3_SELECT__CI__VI {
	struct {
                unsigned int                        PERF_SEL : 8;
                unsigned int                                 : 20;
                unsigned int                       PERF_MODE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

//Merged Registers

	union AFMT_AUDIO_DBG_DTO_CNTL__VI {
	struct {
		unsigned int       AFMT_AUDIO_DTO_FS_DIV_SEL : 3;
		unsigned int                                 : 5;
		unsigned int         AFMT_AUDIO_DTO_DBG_BASE : 1;
		unsigned int                                 : 3;
		unsigned int        AFMT_AUDIO_DTO_DBG_MULTI : 3;
		unsigned int                                 : 1;
		unsigned int          AFMT_AUDIO_DTO_DBG_DIV : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_AUDIO_SRC_CONTROL__VI {
	struct {
		unsigned int           AFMT_AUDIO_SRC_SELECT : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_GENERIC_0__VI {
	struct {
		unsigned int              AFMT_GENERIC_BYTE0 : 8;
		unsigned int              AFMT_GENERIC_BYTE1 : 8;
		unsigned int              AFMT_GENERIC_BYTE2 : 8;
		unsigned int              AFMT_GENERIC_BYTE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_GENERIC_1__VI {
	struct {
		unsigned int              AFMT_GENERIC_BYTE4 : 8;
		unsigned int              AFMT_GENERIC_BYTE5 : 8;
		unsigned int              AFMT_GENERIC_BYTE6 : 8;
		unsigned int              AFMT_GENERIC_BYTE7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_GENERIC_2__VI {
	struct {
		unsigned int              AFMT_GENERIC_BYTE8 : 8;
		unsigned int              AFMT_GENERIC_BYTE9 : 8;
		unsigned int             AFMT_GENERIC_BYTE10 : 8;
		unsigned int             AFMT_GENERIC_BYTE11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_GENERIC_3__VI {
	struct {
		unsigned int             AFMT_GENERIC_BYTE12 : 8;
		unsigned int             AFMT_GENERIC_BYTE13 : 8;
		unsigned int             AFMT_GENERIC_BYTE14 : 8;
		unsigned int             AFMT_GENERIC_BYTE15 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_GENERIC_4__VI {
	struct {
		unsigned int             AFMT_GENERIC_BYTE16 : 8;
		unsigned int             AFMT_GENERIC_BYTE17 : 8;
		unsigned int             AFMT_GENERIC_BYTE18 : 8;
		unsigned int             AFMT_GENERIC_BYTE19 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_GENERIC_5__VI {
	struct {
		unsigned int             AFMT_GENERIC_BYTE20 : 8;
		unsigned int             AFMT_GENERIC_BYTE21 : 8;
		unsigned int             AFMT_GENERIC_BYTE22 : 8;
		unsigned int             AFMT_GENERIC_BYTE23 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_GENERIC_6__VI {
	struct {
		unsigned int             AFMT_GENERIC_BYTE24 : 8;
		unsigned int             AFMT_GENERIC_BYTE25 : 8;
		unsigned int             AFMT_GENERIC_BYTE26 : 8;
		unsigned int             AFMT_GENERIC_BYTE27 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_GENERIC_7__VI {
	struct {
		unsigned int             AFMT_GENERIC_BYTE28 : 8;
		unsigned int             AFMT_GENERIC_BYTE29 : 8;
		unsigned int             AFMT_GENERIC_BYTE30 : 8;
		unsigned int             AFMT_GENERIC_BYTE31 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AFMT_GENERIC_HDR__VI {
	struct {
		unsigned int                AFMT_GENERIC_HB0 : 8;
		unsigned int                AFMT_GENERIC_HB1 : 8;
		unsigned int                AFMT_GENERIC_HB2 : 8;
		unsigned int                AFMT_GENERIC_HB3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ALPHA_CONTROL__VI {
	struct {
		unsigned int          ALPHA_ROUND_TRUNC_MODE : 1;
		unsigned int           CURSOR_ALPHA_BLND_ENA : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_FAULT_STATUS_INFO2__VI {
	struct {
                unsigned int                              VF : 1;
                unsigned int                            VFID : 5;
                unsigned int                                 : 3;
                unsigned int                           L1_ID : 8;
                unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_SMU_STATUS__VI {
	struct {
		unsigned int             VDDGFX_POWERED_DOWN : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_ATS_VMID_STATUS__VI {
	struct {
		unsigned int               VMID0_OUTSTANDING : 1;
		unsigned int               VMID1_OUTSTANDING : 1;
		unsigned int               VMID2_OUTSTANDING : 1;
		unsigned int               VMID3_OUTSTANDING : 1;
		unsigned int               VMID4_OUTSTANDING : 1;
		unsigned int               VMID5_OUTSTANDING : 1;
		unsigned int               VMID6_OUTSTANDING : 1;
		unsigned int               VMID7_OUTSTANDING : 1;
		unsigned int               VMID8_OUTSTANDING : 1;
		unsigned int               VMID9_OUTSTANDING : 1;
		unsigned int              VMID10_OUTSTANDING : 1;
		unsigned int              VMID11_OUTSTANDING : 1;
		unsigned int              VMID12_OUTSTANDING : 1;
		unsigned int              VMID13_OUTSTANDING : 1;
		unsigned int              VMID14_OUTSTANDING : 1;
		unsigned int              VMID15_OUTSTANDING : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L1RD_DEBUG2_TLB__VI {
	struct {
		unsigned int                                 : 10;
		unsigned int                                 : 2;
		unsigned int        INJECT_SOFT_PARITY_ERROR : 1;
		unsigned int        INJECT_HARD_PARITY_ERROR : 1;
		unsigned int          CLEAR_CAM_PARITY_ERROR : 1;
		unsigned int                       CAM_INDEX : 5;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L1WR_DEBUG2_TLB__VI {
	struct {
		unsigned int                                 : 10;
		unsigned int                                 : 2;
		unsigned int        INJECT_SOFT_PARITY_ERROR : 1;
		unsigned int        INJECT_HARD_PARITY_ERROR : 1;
		unsigned int          CLEAR_CAM_PARITY_ERROR : 1;
		unsigned int                       CAM_INDEX : 5;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_CACHE_DATA0__VI {
	struct {
		unsigned int             DATA_REGISTER_VALID : 1;
		unsigned int               CACHE_ENTRY_VALID : 1;
		unsigned int               CACHED_ATTRIBUTES : 18;
		unsigned int       VIRTUAL_PAGE_ADDRESS_HIGH : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_CACHE_DATA1__VI {
	struct {
		unsigned int        VIRTUAL_PAGE_ADDRESS_LOW : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_CACHE_DATA2__VI {
	struct {
		unsigned int       PHYSICAL_PAGE_ADDRESS_LOW : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_CNTL3__VI {
	struct {
		unsigned int ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING : 7;
		unsigned int             ENABLE_FREE_COUNTER : 1;
		unsigned int     L2_CACHE_EVICTION_THRESHOLD : 5;
		unsigned int DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION : 1;
		unsigned int L2_DELAY_SEND_INVALIDATION_REQUEST : 3;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_STATUS__VI {
	struct {
		unsigned int                            BUSY : 1;
		unsigned int               PARITY_ERROR_INFO : 29;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ATC_L2_STATUS2__VI {
	struct {
		unsigned int              CACHE_ADDRESS_MODE : 3;
		unsigned int               PARITY_ERROR_INFO : 8;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_GTC_SYNC_CONTROL__VI {
	struct {
		unsigned int                 AUX_GTC_SYNC_EN : 1;
		unsigned int                                 : 3;
		unsigned int          AUX_GTC_SYNC_IMPCAL_EN : 1;
		unsigned int                                 : 3;
		unsigned int    AUX_GTC_SYNC_IMPCAL_INTERVAL : 4;
		unsigned int    AUX_GTC_SYNC_LOCK_ACQ_PERIOD : 4;
		unsigned int  AUX_GTC_SYNC_LOCK_MAINT_PERIOD : 3;
		unsigned int                                 : 1;
		unsigned int          AUX_GTC_SYNC_BLOCK_REQ : 1;
		unsigned int                                 : 1;
		unsigned int AUX_GTC_SYNC_INTERVAL_RESET_WINDOW : 2;
		unsigned int AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT : 2;
		unsigned int                                 : 2;
		unsigned int AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_GTC_SYNC_CONTROLLER_STATUS__VI {
	struct {
		unsigned int  AUX_GTC_SYNC_LOCK_ACQ_COMPLETE : 1;
		unsigned int                                 : 3;
		unsigned int          AUX_GTC_SYNC_LOCK_LOST : 1;
		unsigned int                                 : 3;
		unsigned int AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED : 1;
		unsigned int AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE : 4;
		unsigned int                                 : 3;
		unsigned int AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL : 1;
		unsigned int                                 : 3;
		unsigned int AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED : 1;
		unsigned int AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK : 1;
		unsigned int AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED : 1;
		unsigned int AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK : 1;
		unsigned int AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED : 1;
		unsigned int AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK : 1;
		unsigned int                                 : 2;
		unsigned int         AUX_GTC_SYNC_CTRL_STATE : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_GTC_SYNC_DATA__VI {
	struct {
		unsigned int                 AUX_GTC_DATA_RW : 1;
		unsigned int                                 : 7;
		unsigned int                    AUX_GTC_DATA : 8;
		unsigned int                   AUX_GTC_INDEX : 6;
		unsigned int                                 : 9;
		unsigned int AUX_GTC_INDEX_AUTOINCREMENT_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_GTC_SYNC_ERROR_CONTROL__VI {
	struct {
		unsigned int AUX_GTC_POTENTIAL_ERROR_THRESHOLD : 5;
		unsigned int                                 : 3;
		unsigned int AUX_GTC_DEFINITE_ERROR_THRESHOLD : 5;
		unsigned int                                 : 3;
		unsigned int AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN : 2;
		unsigned int                                 : 2;
		unsigned int AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT : 2;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI {
	struct {
		unsigned int AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN : 1;
		unsigned int                                 : 3;
		unsigned int AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE : 16;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_GTC_SYNC_STATUS__VI {
	struct {
		unsigned int               AUX_GTC_SYNC_DONE : 1;
		unsigned int                AUX_GTC_SYNC_REQ : 1;
		unsigned int                                 : 2;
		unsigned int   AUX_GTC_SYNC_RX_TIMEOUT_STATE : 3;
		unsigned int            AUX_GTC_SYNC_TIMEOUT : 1;
		unsigned int        AUX_GTC_SYNC_RX_OVERFLOW : 1;
		unsigned int         AUX_GTC_SYNC_HPD_DISCON : 1;
		unsigned int    AUX_GTC_SYNC_RX_PARTIAL_BYTE : 1;
		unsigned int       AUX_GTC_SYNC_NON_AUX_MODE : 1;
		unsigned int  AUX_GTC_SYNC_RX_MIN_COUNT_VIOL : 1;
		unsigned int                                 : 1;
		unsigned int    AUX_GTC_SYNC_RX_INVALID_STOP : 1;
		unsigned int                                 : 2;
		unsigned int  AUX_GTC_SYNC_RX_SYNC_INVALID_L : 1;
		unsigned int  AUX_GTC_SYNC_RX_SYNC_INVALID_H : 1;
		unsigned int   AUX_GTC_SYNC_RX_INVALID_START : 1;
		unsigned int     AUX_GTC_SYNC_RX_RECV_NO_DET : 1;
		unsigned int                                 : 1;
		unsigned int  AUX_GTC_SYNC_RX_RECV_INVALID_H : 1;
		unsigned int  AUX_GTC_SYNC_RX_RECV_INVALID_L : 1;
		unsigned int   AUX_GTC_SYNC_REPLY_BYTE_COUNT : 5;
		unsigned int             AUX_GTC_SYNC_NACKED : 1;
		unsigned int        AUX_GTC_MASTER_REQ_BY_RX : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int             AUX_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AUX_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int            AUX_TEST_DEBUG_INDEX : 8;
		unsigned int         AUX_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AVSYNC_COUNTER_CONTROL__VI {
	struct {
		unsigned int           AVSYNC_COUNTER_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AVSYNC_COUNTER_READ__VI {
	struct {
		unsigned int          AVSYNC_COUNTER_RDVALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AVSYNC_COUNTER_WRITE__VI {
	struct {
		unsigned int          AVSYNC_COUNTER_WRVALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CONTROLLER_CLOCK_GATING__VI {
	struct {
		unsigned int             ENABLE_CLOCK_GATING : 1;
		unsigned int                                 : 3;
		unsigned int                  CLOCK_ON_STATE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CONTROLLER_DEBUG__VI {
	struct {
		unsigned int                CONTROLLER_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CHANNEL0__VI {
	struct {
		unsigned int                    CRC_CHANNEL0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CHANNEL1__VI {
	struct {
		unsigned int                    CRC_CHANNEL1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CHANNEL2__VI {
	struct {
		unsigned int                    CRC_CHANNEL2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CHANNEL3__VI {
	struct {
		unsigned int                    CRC_CHANNEL3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CHANNEL4__VI {
	struct {
		unsigned int                    CRC_CHANNEL4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CHANNEL5__VI {
	struct {
		unsigned int                    CRC_CHANNEL5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CHANNEL6__VI {
	struct {
		unsigned int                    CRC_CHANNEL6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CHANNEL7__VI {
	struct {
		unsigned int                    CRC_CHANNEL7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CONTROL0__VI {
	struct {
		unsigned int                          CRC_EN : 1;
		unsigned int                                 : 3;
		unsigned int                  CRC_BLOCK_MODE : 1;
		unsigned int                                 : 3;
		unsigned int                CRC_INSTANCE_SEL : 3;
		unsigned int                                 : 1;
		unsigned int                  CRC_SOURCE_SEL : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CONTROL1__VI {
	struct {
		unsigned int                  CRC_BLOCK_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CONTROL2__VI {
	struct {
		unsigned int             CRC_BLOCK_ITERATION : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_CONTROL3__VI {
	struct {
		unsigned int                    CRC_COMPLETE : 1;
		unsigned int                                 : 3;
		unsigned int        CRC_BLOCK_COMPLETE_PHASE : 1;
		unsigned int                                 : 3;
		unsigned int          CRC_CHANNEL_RESULT_SEL : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC0_RESULT__VI {
	struct {
		unsigned int                      CRC_RESULT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CHANNEL0__VI {
	struct {
		unsigned int                    CRC_CHANNEL0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CHANNEL1__VI {
	struct {
		unsigned int                    CRC_CHANNEL1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CHANNEL2__VI {
	struct {
		unsigned int                    CRC_CHANNEL2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CHANNEL3__VI {
	struct {
		unsigned int                    CRC_CHANNEL3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CHANNEL4__VI {
	struct {
		unsigned int                    CRC_CHANNEL4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CHANNEL5__VI {
	struct {
		unsigned int                    CRC_CHANNEL5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CHANNEL6__VI {
	struct {
		unsigned int                    CRC_CHANNEL6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CHANNEL7__VI {
	struct {
		unsigned int                    CRC_CHANNEL7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CONTROL0__VI {
	struct {
		unsigned int                          CRC_EN : 1;
		unsigned int                                 : 3;
		unsigned int                  CRC_BLOCK_MODE : 1;
		unsigned int                                 : 3;
		unsigned int                CRC_INSTANCE_SEL : 3;
		unsigned int                                 : 1;
		unsigned int                  CRC_SOURCE_SEL : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CONTROL1__VI {
	struct {
		unsigned int                  CRC_BLOCK_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CONTROL2__VI {
	struct {
		unsigned int             CRC_BLOCK_ITERATION : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_CONTROL3__VI {
	struct {
		unsigned int                    CRC_COMPLETE : 1;
		unsigned int                                 : 3;
		unsigned int        CRC_BLOCK_COMPLETE_PHASE : 1;
		unsigned int                                 : 3;
		unsigned int          CRC_CHANNEL_RESULT_SEL : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_CRC1_RESULT__VI {
	struct {
		unsigned int                      CRC_RESULT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_AUDIO_DISABLED_INT_STATUS__VI {
	struct {
		unsigned int             AUDIO_DISABLED_FLAG : 1;
		unsigned int                                 : 3;
		unsigned int             AUDIO_DISABLED_MASK : 1;
		unsigned int                                 : 3;
		unsigned int             AUDIO_DISABLED_TYPE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_AUDIO_ENABLED_INT_STATUS__VI {
	struct {
		unsigned int              AUDIO_ENABLED_FLAG : 1;
		unsigned int                                 : 3;
		unsigned int              AUDIO_ENABLED_MASK : 1;
		unsigned int                                 : 3;
		unsigned int              AUDIO_ENABLED_TYPE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_AUDIO_ENABLE_STATUS__VI {
	struct {
		unsigned int             AUDIO_ENABLE_STATUS : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__VI {
	struct {
		unsigned int       AUDIO_FORMAT_CHANGED_FLAG : 1;
		unsigned int                                 : 3;
		unsigned int       AUDIO_FORMAT_CHANGED_MASK : 1;
		unsigned int                                 : 3;
		unsigned int       AUDIO_FORMAT_CHANGED_TYPE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__VI {
	struct {
		unsigned int               HBR_CHANNEL_COUNT : 3;
		unsigned int                                 : 1;
		unsigned int        COMPRESSED_CHANNEL_COUNT : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__VI {
	struct {
		unsigned int              NUMBER_OF_CHANNELS : 4;
		unsigned int                 BITS_PER_SAMPLE : 3;
		unsigned int                                 : 1;
		unsigned int             SAMPLE_BASE_DIVISOR : 3;
		unsigned int            SAMPLE_BASE_MULTIPLE : 3;
		unsigned int                SAMPLE_BASE_RATE : 1;
		unsigned int                     STREAM_TYPE : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI {
	struct {
		unsigned int                           DIGEN : 1;
		unsigned int                               V : 1;
		unsigned int                            VCFG : 1;
		unsigned int                             PRE : 1;
		unsigned int                            COPY : 1;
		unsigned int                       NON_AUDIO : 1;
		unsigned int                             PRO : 1;
		unsigned int                               L : 1;
		unsigned int                              CC : 7;
		unsigned int                                 : 8;
		unsigned int                       KEEPALIVE : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__VI {
	struct {
		unsigned int PRESENTATION_TIME_EMBEDDING_ENABLE : 1;
		unsigned int PRESENTATION_TIME_OFFSET_CHANGED : 1;
		unsigned int CLEAR_GTC_COUNTER_MIN_MAX_DELTA : 1;
		unsigned int                                 : 1;
		unsigned int PRESENTATION_TIME_EMBEDDING_GROUP : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__VI {
	struct {
		unsigned int  PRESENTATION_TIME_OFFSET_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__VI {
	struct {
		unsigned int                       RAMP_RATE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__VI {
	struct {
		unsigned int               GTC_COUNTER_DELTA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__VI {
	struct {
		unsigned int           GTC_COUNTER_DELTA_MAX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__VI {
	struct {
		unsigned int           GTC_COUNTER_DELTA_MIN : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI {
	struct {
		unsigned int      AUDIO_CHANNEL_CAPABILITIES : 1;
		unsigned int         INPUT_AMPLIFIER_PRESENT : 1;
		unsigned int        OUTPUT_AMPLIFIER_PRESENT : 1;
		unsigned int    AMPLIFIER_PARAMETER_OVERRIDE : 1;
		unsigned int                 FORMAT_OVERRIDE : 1;
		unsigned int                          STRIPE : 1;
		unsigned int               PROCESSING_WIDGET : 1;
		unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1;
		unsigned int                 CONNECTION_LIST : 1;
		unsigned int                         DIGITAL : 1;
		unsigned int                   POWER_CONTROL : 1;
		unsigned int                         LR_SWAP : 1;
		unsigned int                                 : 4;
		unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4;
		unsigned int                            TYPE : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__VI {
	struct {
		unsigned int                  STREAM_FORMATS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI {
	struct {
		unsigned int         AUDIO_RATE_CAPABILITIES : 12;
		unsigned int                                 : 4;
		unsigned int          AUDIO_BIT_CAPABILITIES : 5;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__VI {
	struct {
		unsigned int                    AZALIA_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__VI {
	struct {
		unsigned int                  STRIPE_CONTROL : 2;
		unsigned int                                 : 18;
		unsigned int               STRIPE_CAPABILITY : 3;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_DEBUG__VI {
	struct {
		unsigned int       DISABLE_FORMAT_COMPARISON : 6;
		unsigned int                     CODEC_DEBUG : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_ENDPOINT_DATA__VI {
	struct {
		unsigned int        AZALIA_ENDPOINT_REG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_ENDPOINT_INDEX__VI {
	struct {
		unsigned int       AZALIA_ENDPOINT_REG_INDEX : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__VI {
	struct {
		unsigned int       CONVERTER_SYNCHRONIZATION : 7;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI {
	struct {
		unsigned int                      CHANNEL_ID : 4;
		unsigned int                       STREAM_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__VI {
	struct {
		unsigned int              NUMBER_OF_CHANNELS : 4;
		unsigned int                 BITS_PER_SAMPLE : 3;
		unsigned int                                 : 1;
		unsigned int             SAMPLE_BASE_DIVISOR : 3;
		unsigned int            SAMPLE_BASE_MULTIPLE : 3;
		unsigned int                SAMPLE_BASE_RATE : 1;
		unsigned int                     STREAM_TYPE : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI {
	struct {
		unsigned int                           DIGEN : 1;
		unsigned int                               V : 1;
		unsigned int                            VCFG : 1;
		unsigned int                             PRE : 1;
		unsigned int                            COPY : 1;
		unsigned int                       NON_AUDIO : 1;
		unsigned int                             PRO : 1;
		unsigned int                               L : 1;
		unsigned int                              CC : 7;
		unsigned int                                 : 8;
		unsigned int                       KEEPALIVE : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI {
	struct {
		unsigned int      AUDIO_CHANNEL_CAPABILITIES : 1;
		unsigned int         INPUT_AMPLIFIER_PRESENT : 1;
		unsigned int        OUTPUT_AMPLIFIER_PRESENT : 1;
		unsigned int    AMPLIFIER_PARAMETER_OVERRIDE : 1;
		unsigned int                 FORMAT_OVERRIDE : 1;
		unsigned int                          STRIPE : 1;
		unsigned int               PROCESSING_WIDGET : 1;
		unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1;
		unsigned int                 CONNECTION_LIST : 1;
		unsigned int                         DIGITAL : 1;
		unsigned int                   POWER_CONTROL : 1;
		unsigned int                         LR_SWAP : 1;
		unsigned int                                 : 4;
		unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4;
		unsigned int                            TYPE : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__VI {
	struct {
		unsigned int                  STREAM_FORMATS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI {
	struct {
		unsigned int         AUDIO_RATE_CAPABILITIES : 12;
		unsigned int                                 : 4;
		unsigned int          AUDIO_BIT_CAPABILITIES : 5;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__VI {
	struct {
		unsigned int              AZALIA_INPUT_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI {
	struct {
		unsigned int  AZALIA_INPUT_ENDPOINT_REG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI {
	struct {
		unsigned int AZALIA_INPUT_ENDPOINT_REG_INDEX : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__VI {
	struct {
		unsigned int              CHANNEL_ALLOCATION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__VI {
	struct {
		unsigned int            CLOCK_GATING_DISABLE : 1;
		unsigned int                                 : 3;
		unsigned int                  CLOCK_ON_STATE : 1;
		unsigned int                                 : 26;
		unsigned int                   AUDIO_ENABLED : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__VI {
	struct {
		unsigned int                   CHANNEL_COUNT : 3;
		unsigned int                                 : 5;
		unsigned int              CHANNEL_ALLOCATION : 8;
		unsigned int                INFOFRAME_BYTE_5 : 8;
		unsigned int                                 : 7;
		unsigned int                 INFOFRAME_VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__VI {
	struct {
		unsigned int                  INPUT_ACTIVITY : 1;
		unsigned int                  CHANNEL_LAYOUT : 2;
		unsigned int                                 : 1;
		unsigned int        INPUT_ACTIVITY_UR_ENABLE : 1;
		unsigned int INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__VI {
	struct {
		unsigned int                            LPIB : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI {
	struct {
		unsigned int              LPIB_SNAPSHOT_LOCK : 1;
		unsigned int                                 : 7;
		unsigned int        CYCLIC_BUFFER_WRAP_COUNT : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI {
	struct {
		unsigned int             LPIB_TIMER_SNAPSHOT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL0_ENABLE : 1;
		unsigned int              MULTICHANNEL0_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL0_CHANNEL_ID : 4;
		unsigned int            MULTICHANNEL1_ENABLE : 1;
		unsigned int              MULTICHANNEL1_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL1_CHANNEL_ID : 4;
		unsigned int            MULTICHANNEL2_ENABLE : 1;
		unsigned int              MULTICHANNEL2_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL2_CHANNEL_ID : 4;
		unsigned int            MULTICHANNEL3_ENABLE : 1;
		unsigned int              MULTICHANNEL3_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL3_CHANNEL_ID : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__VI {
	struct {
		unsigned int            MULTICHANNEL4_ENABLE : 1;
		unsigned int              MULTICHANNEL4_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL4_CHANNEL_ID : 4;
		unsigned int            MULTICHANNEL5_ENABLE : 1;
		unsigned int              MULTICHANNEL5_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL5_CHANNEL_ID : 4;
		unsigned int            MULTICHANNEL6_ENABLE : 1;
		unsigned int              MULTICHANNEL6_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL6_CHANNEL_ID : 4;
		unsigned int            MULTICHANNEL7_ENABLE : 1;
		unsigned int              MULTICHANNEL7_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL7_CHANNEL_ID : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI {
	struct {
		unsigned int                        SEQUENCE : 4;
		unsigned int             DEFAULT_ASSOCIATION : 4;
		unsigned int                            MISC : 4;
		unsigned int                           COLOR : 4;
		unsigned int                 CONNECTION_TYPE : 4;
		unsigned int                  DEFAULT_DEVICE : 4;
		unsigned int                        LOCATION : 6;
		unsigned int               PORT_CONNECTIVITY : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__VI {
	struct {
		unsigned int                     HBR_CAPABLE : 1;
		unsigned int                                 : 3;
		unsigned int                      HBR_ENABLE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__VI {
	struct {
		unsigned int                 IMPEDANCE_SENSE : 31;
		unsigned int                 PRESENCE_DETECT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__VI {
	struct {
		unsigned int                             TAG : 6;
		unsigned int                                 : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__VI {
	struct {
		unsigned int    UNSOLICITED_RESPONSE_PAYLOAD : 26;
		unsigned int                                 : 2;
		unsigned int      UNSOLICITED_RESPONSE_FORCE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__VI {
	struct {
		unsigned int                                 : 5;
		unsigned int                       IN_ENABLE : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI {
	struct {
		unsigned int      AUDIO_CHANNEL_CAPABILITIES : 1;
		unsigned int         INPUT_AMPLIFIER_PRESENT : 1;
		unsigned int        OUTPUT_AMPLIFIER_PRESENT : 1;
		unsigned int    AMPLIFIER_PARAMETER_OVERRIDE : 1;
		unsigned int                                 : 1;
		unsigned int                          STRIPE : 1;
		unsigned int               PROCESSING_WIDGET : 1;
		unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1;
		unsigned int                 CONNECTION_LIST : 1;
		unsigned int                         DIGITAL : 1;
		unsigned int                   POWER_CONTROL : 1;
		unsigned int                         LR_SWAP : 1;
		unsigned int                                 : 4;
		unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4;
		unsigned int                            TYPE : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VI {
	struct {
		unsigned int         IMPEDANCE_SENSE_CAPABLE : 1;
		unsigned int                TRIGGER_REQUIRED : 1;
		unsigned int       JACK_DETECTION_CAPABILITY : 1;
		unsigned int         HEADPHONE_DRIVE_CAPABLE : 1;
		unsigned int                  OUTPUT_CAPABLE : 1;
		unsigned int                   INPUT_CAPABLE : 1;
		unsigned int               BALANCED_I_O_PINS : 1;
		unsigned int                            HDMI : 1;
		unsigned int                    VREF_CONTROL : 8;
		unsigned int                    EAPD_CAPABLE : 1;
		unsigned int                                 : 7;
		unsigned int                              DP : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__VI {
	struct {
		unsigned int                ASSOCIATION_INFO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                                 : 5;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__VI {
	struct {
		unsigned int              SPEAKER_ALLOCATION : 7;
		unsigned int                                 : 1;
		unsigned int              CHANNEL_ALLOCATION : 8;
		unsigned int                 HDMI_CONNECTION : 1;
		unsigned int                   DP_CONNECTION : 1;
		unsigned int           EXTRA_CONNECTION_INFO : 6;
		unsigned int              LFE_PLAYBACK_LEVEL : 2;
		unsigned int                                 : 1;
		unsigned int                     LEVEL_SHIFT : 4;
		unsigned int                DOWN_MIX_INHIBIT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__VI {
	struct {
		unsigned int                     CODING_TYPE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__VI {
	struct {
		unsigned int                   OUTPUT_ACTIVE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__VI {
	struct {
		unsigned int                  FORMAT_CHANGED : 1;
		unsigned int    FORMAT_CHANGED_ACK_UR_ENABLE : 1;
		unsigned int                                 : 6;
		unsigned int            FORMAT_CHANGE_REASON : 8;
		unsigned int          FORMAT_CHANGE_RESPONSE : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__VI {
	struct {
		unsigned int            CLOCK_GATING_DISABLE : 1;
		unsigned int                                 : 3;
		unsigned int                  CLOCK_ON_STATE : 1;
		unsigned int                                 : 26;
		unsigned int                   AUDIO_ENABLED : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_LPIB__VI {
	struct {
		unsigned int                            LPIB : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI {
	struct {
		unsigned int              LPIB_SNAPSHOT_LOCK : 1;
		unsigned int                                 : 7;
		unsigned int        CYCLIC_BUFFER_WRAP_COUNT : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI {
	struct {
		unsigned int             LPIB_TIMER_SNAPSHOT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__VI {
	struct {
		unsigned int           MULTICHANNEL01_ENABLE : 1;
		unsigned int             MULTICHANNEL01_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int       MULTICHANNEL01_CHANNEL_ID : 4;
		unsigned int           MULTICHANNEL23_ENABLE : 1;
		unsigned int             MULTICHANNEL23_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int       MULTICHANNEL23_CHANNEL_ID : 4;
		unsigned int           MULTICHANNEL45_ENABLE : 1;
		unsigned int             MULTICHANNEL45_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int       MULTICHANNEL45_CHANNEL_ID : 4;
		unsigned int           MULTICHANNEL67_ENABLE : 1;
		unsigned int             MULTICHANNEL67_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int       MULTICHANNEL67_CHANNEL_ID : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__VI {
	struct {
		unsigned int            MULTICHANNEL1_ENABLE : 1;
		unsigned int              MULTICHANNEL1_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL1_CHANNEL_ID : 4;
		unsigned int            MULTICHANNEL3_ENABLE : 1;
		unsigned int              MULTICHANNEL3_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL3_CHANNEL_ID : 4;
		unsigned int            MULTICHANNEL5_ENABLE : 1;
		unsigned int              MULTICHANNEL5_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL5_CHANNEL_ID : 4;
		unsigned int            MULTICHANNEL7_ENABLE : 1;
		unsigned int              MULTICHANNEL7_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL7_CHANNEL_ID : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__VI {
	struct {
		unsigned int               MULTICHANNEL_MODE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__VI {
	struct {
		unsigned int        REMOTE_KEEP_ALIVE_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int    REMOTE_KEEP_ALIVE_CAPABILITY : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI {
	struct {
		unsigned int                        SEQUENCE : 4;
		unsigned int             DEFAULT_ASSOCIATION : 4;
		unsigned int                            MISC : 4;
		unsigned int                           COLOR : 4;
		unsigned int                 CONNECTION_TYPE : 4;
		unsigned int                  DEFAULT_DEVICE : 4;
		unsigned int                        LOCATION : 6;
		unsigned int               PORT_CONNECTIVITY : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__VI {
	struct {
		unsigned int                     HBR_CAPABLE : 1;
		unsigned int                                 : 3;
		unsigned int                      HBR_ENABLE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VI {
	struct {
		unsigned int                   VIDEO_LIPSYNC : 8;
		unsigned int                   AUDIO_LIPSYNC : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__VI {
	struct {
		unsigned int                 IMPEDANCE_SENSE : 31;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__VI {
	struct {
		unsigned int                 MANUFACTURER_ID : 16;
		unsigned int                      PRODUCT_ID : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__VI {
	struct {
		unsigned int            SINK_DESCRIPTION_LEN : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__VI {
	struct {
		unsigned int                        PORT_ID0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__VI {
	struct {
		unsigned int                        PORT_ID1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__VI {
	struct {
		unsigned int                    DESCRIPTION0 : 8;
		unsigned int                    DESCRIPTION1 : 8;
		unsigned int                    DESCRIPTION2 : 8;
		unsigned int                    DESCRIPTION3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__VI {
	struct {
		unsigned int                    DESCRIPTION4 : 8;
		unsigned int                    DESCRIPTION5 : 8;
		unsigned int                    DESCRIPTION6 : 8;
		unsigned int                    DESCRIPTION7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__VI {
	struct {
		unsigned int                    DESCRIPTION8 : 8;
		unsigned int                    DESCRIPTION9 : 8;
		unsigned int                   DESCRIPTION10 : 8;
		unsigned int                   DESCRIPTION11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__VI {
	struct {
		unsigned int                   DESCRIPTION12 : 8;
		unsigned int                   DESCRIPTION13 : 8;
		unsigned int                   DESCRIPTION14 : 8;
		unsigned int                   DESCRIPTION15 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__VI {
	struct {
		unsigned int                   DESCRIPTION16 : 8;
		unsigned int                   DESCRIPTION17 : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__VI {
	struct {
		unsigned int    UNSOLICITED_RESPONSE_PAYLOAD : 26;
		unsigned int                                 : 2;
		unsigned int      UNSOLICITED_RESPONSE_FORCE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__VI {
	struct {
		unsigned int WIRELESS_DISPLAY_IDENTIFICATION : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI {
	struct {
		unsigned int      AUDIO_CHANNEL_CAPABILITIES : 1;
		unsigned int         INPUT_AMPLIFIER_PRESENT : 1;
		unsigned int        OUTPUT_AMPLIFIER_PRESENT : 1;
		unsigned int    AMPLIFIER_PARAMETER_OVERRIDE : 1;
		unsigned int                                 : 1;
		unsigned int                          STRIPE : 1;
		unsigned int               PROCESSING_WIDGET : 1;
		unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1;
		unsigned int                 CONNECTION_LIST : 1;
		unsigned int                         DIGITAL : 1;
		unsigned int                   POWER_CONTROL : 1;
		unsigned int                         LR_SWAP : 1;
		unsigned int                                 : 4;
		unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4;
		unsigned int                            TYPE : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VI {
	struct {
		unsigned int         IMPEDANCE_SENSE_CAPABLE : 1;
		unsigned int                TRIGGER_REQUIRED : 1;
		unsigned int       JACK_DETECTION_CAPABILITY : 1;
		unsigned int         HEADPHONE_DRIVE_CAPABLE : 1;
		unsigned int                  OUTPUT_CAPABLE : 1;
		unsigned int                   INPUT_CAPABLE : 1;
		unsigned int               BALANCED_I_O_PINS : 1;
		unsigned int                            HDMI : 1;
		unsigned int                    VREF_CONTROL : 8;
		unsigned int                    EAPD_CAPABLE : 1;
		unsigned int                                 : 7;
		unsigned int                              DP : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__VI {
	struct {
		unsigned int RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW : 6;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_GTC_GROUP_OFFSET0__VI {
	struct {
		unsigned int               GTC_GROUP_OFFSET0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_GTC_GROUP_OFFSET1__VI {
	struct {
		unsigned int               GTC_GROUP_OFFSET1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_GTC_GROUP_OFFSET2__VI {
	struct {
		unsigned int               GTC_GROUP_OFFSET2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_GTC_GROUP_OFFSET3__VI {
	struct {
		unsigned int               GTC_GROUP_OFFSET3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_GTC_GROUP_OFFSET4__VI {
	struct {
		unsigned int               GTC_GROUP_OFFSET4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_GTC_GROUP_OFFSET5__VI {
	struct {
		unsigned int               GTC_GROUP_OFFSET5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_GTC_GROUP_OFFSET6__VI {
	struct {
		unsigned int               GTC_GROUP_OFFSET6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__VI {
	struct {
		unsigned int               IEC_60958_CS_MODE : 2;
		unsigned int      IEC_60958_CS_SOURCE_NUMBER : 4;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__VI {
	struct {
		unsigned int     IEC_60958_CS_CLOCK_ACCURACY : 2;
		unsigned int IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN : 1;
		unsigned int        IEC_60958_CS_WORD_LENGTH : 4;
		unsigned int IEC_60958_CS_WORD_LENGTH_OVRRD_EN : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__VI {
	struct {
		unsigned int IEC_60958_CS_SAMPLING_FREQUENCY : 6;
		unsigned int IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__VI {
	struct {
		unsigned int IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY : 4;
		unsigned int IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__VI {
	struct {
		unsigned int IEC_60958_CS_SAMPLING_FREQUENCY_COEFF : 4;
		unsigned int IEC_60958_CS_MPEG_SURROUND_INFO : 1;
		unsigned int             IEC_60958_CS_CGMS_A : 2;
		unsigned int       IEC_60958_CS_CGMS_A_VALID : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__VI {
	struct {
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_L : 4;
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_R : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__VI {
	struct {
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_2 : 4;
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_3 : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__VI {
	struct {
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_4 : 4;
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_5 : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__VI {
	struct {
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_6 : 4;
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_7 : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI {
	struct {
		unsigned int                      CHANNEL_ID : 4;
		unsigned int                       STREAM_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__VI {
	struct {
		unsigned int              NUMBER_OF_CHANNELS : 4;
		unsigned int                 BITS_PER_SAMPLE : 3;
		unsigned int                                 : 1;
		unsigned int             SAMPLE_BASE_DIVISOR : 3;
		unsigned int            SAMPLE_BASE_MULTIPLE : 3;
		unsigned int                SAMPLE_BASE_RATE : 1;
		unsigned int                     STREAM_TYPE : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI {
	struct {
		unsigned int                           DIGEN : 1;
		unsigned int                               V : 1;
		unsigned int                            VCFG : 1;
		unsigned int                             PRE : 1;
		unsigned int                            COPY : 1;
		unsigned int                       NON_AUDIO : 1;
		unsigned int                             PRO : 1;
		unsigned int                               L : 1;
		unsigned int                              CC : 7;
		unsigned int                                 : 8;
		unsigned int                       KEEPALIVE : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__VI {
	struct {
		unsigned int                              CC : 7;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__VI {
	struct {
		unsigned int                                 : 7;
		unsigned int                       KEEPALIVE : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__VI {
	struct {
		unsigned int PRESENTATION_TIME_EMBEDDING_ENABLE : 1;
		unsigned int PRESENTATION_TIME_OFFSET_CHANGED : 1;
		unsigned int                                 : 2;
		unsigned int PRESENTATION_TIME_EMBEDDING_GROUP : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__VI {
	struct {
		unsigned int                       RAMP_RATE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI {
	struct {
		unsigned int      AUDIO_CHANNEL_CAPABILITIES : 1;
		unsigned int         INPUT_AMPLIFIER_PRESENT : 1;
		unsigned int        OUTPUT_AMPLIFIER_PRESENT : 1;
		unsigned int    AMPLIFIER_PARAMETER_OVERRIDE : 1;
		unsigned int                 FORMAT_OVERRIDE : 1;
		unsigned int                          STRIPE : 1;
		unsigned int               PROCESSING_WIDGET : 1;
		unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1;
		unsigned int                 CONNECTION_LIST : 1;
		unsigned int                         DIGITAL : 1;
		unsigned int                   POWER_CONTROL : 1;
		unsigned int                         LR_SWAP : 1;
		unsigned int                                 : 4;
		unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4;
		unsigned int                            TYPE : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__VI {
	struct {
		unsigned int                  STREAM_FORMATS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI {
	struct {
		unsigned int         AUDIO_RATE_CAPABILITIES : 12;
		unsigned int                                 : 4;
		unsigned int          AUDIO_BIT_CAPABILITIES : 5;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__VI {
	struct {
		unsigned int                  STRIPE_CONTROL : 2;
		unsigned int                                 : 18;
		unsigned int               STRIPE_CAPABILITY : 3;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__VI {
	struct {
		unsigned int       CONVERTER_SYNCHRONIZATION : 7;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI {
	struct {
		unsigned int                      CHANNEL_ID : 4;
		unsigned int                       STREAM_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__VI {
	struct {
		unsigned int              NUMBER_OF_CHANNELS : 4;
		unsigned int                 BITS_PER_SAMPLE : 3;
		unsigned int                                 : 1;
		unsigned int             SAMPLE_BASE_DIVISOR : 3;
		unsigned int            SAMPLE_BASE_MULTIPLE : 3;
		unsigned int                SAMPLE_BASE_RATE : 1;
		unsigned int                     STREAM_TYPE : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI {
	struct {
		unsigned int                           DIGEN : 1;
		unsigned int                               V : 1;
		unsigned int                            VCFG : 1;
		unsigned int                             PRE : 1;
		unsigned int                            COPY : 1;
		unsigned int                       NON_AUDIO : 1;
		unsigned int                             PRO : 1;
		unsigned int                               L : 1;
		unsigned int                              CC : 7;
		unsigned int                                 : 8;
		unsigned int                       KEEPALIVE : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI {
	struct {
		unsigned int      AUDIO_CHANNEL_CAPABILITIES : 1;
		unsigned int         INPUT_AMPLIFIER_PRESENT : 1;
		unsigned int        OUTPUT_AMPLIFIER_PRESENT : 1;
		unsigned int    AMPLIFIER_PARAMETER_OVERRIDE : 1;
		unsigned int                 FORMAT_OVERRIDE : 1;
		unsigned int                          STRIPE : 1;
		unsigned int               PROCESSING_WIDGET : 1;
		unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1;
		unsigned int                 CONNECTION_LIST : 1;
		unsigned int                         DIGITAL : 1;
		unsigned int                   POWER_CONTROL : 1;
		unsigned int                         LR_SWAP : 1;
		unsigned int                                 : 4;
		unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4;
		unsigned int                            TYPE : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__VI {
	struct {
		unsigned int                  STREAM_FORMATS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI {
	struct {
		unsigned int         AUDIO_RATE_CAPABILITIES : 12;
		unsigned int                                 : 4;
		unsigned int          AUDIO_BIT_CAPABILITIES : 5;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__VI {
	struct {
		unsigned int              CHANNEL_ALLOCATION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__VI {
	struct {
		unsigned int                CHANNEL_STATUS_H : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__VI {
	struct {
		unsigned int                CHANNEL_STATUS_L : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__VI {
	struct {
		unsigned int                     HBR_CAPABLE : 1;
		unsigned int                                 : 3;
		unsigned int                      HBR_ENABLE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__VI {
	struct {
		unsigned int                   CHANNEL_COUNT : 3;
		unsigned int                                 : 5;
		unsigned int              CHANNEL_ALLOCATION : 8;
		unsigned int                INFOFRAME_BYTE_5 : 8;
		unsigned int                                 : 7;
		unsigned int                 INFOFRAME_VALID : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__VI {
	struct {
		unsigned int                  INPUT_ACTIVITY : 1;
		unsigned int                  CHANNEL_LAYOUT : 2;
		unsigned int                                 : 1;
		unsigned int        INPUT_ACTIVITY_UR_ENABLE : 1;
		unsigned int INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__VI {
	struct {
		unsigned int                            LPIB : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI {
	struct {
		unsigned int              LPIB_SNAPSHOT_LOCK : 1;
		unsigned int                                 : 7;
		unsigned int        CYCLIC_BUFFER_WRAP_COUNT : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI {
	struct {
		unsigned int             LPIB_TIMER_SNAPSHOT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL0_ENABLE : 1;
		unsigned int              MULTICHANNEL0_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL0_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL1_ENABLE : 1;
		unsigned int              MULTICHANNEL1_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL1_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL2_ENABLE : 1;
		unsigned int              MULTICHANNEL2_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL2_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL3_ENABLE : 1;
		unsigned int              MULTICHANNEL3_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL3_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL4_ENABLE : 1;
		unsigned int              MULTICHANNEL4_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL4_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL5_ENABLE : 1;
		unsigned int              MULTICHANNEL5_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL5_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL6_ENABLE : 1;
		unsigned int              MULTICHANNEL6_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL6_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL7_ENABLE : 1;
		unsigned int              MULTICHANNEL7_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL7_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI {
	struct {
		unsigned int                        SEQUENCE : 4;
		unsigned int             DEFAULT_ASSOCIATION : 4;
		unsigned int                            MISC : 4;
		unsigned int                           COLOR : 4;
		unsigned int                 CONNECTION_TYPE : 4;
		unsigned int                  DEFAULT_DEVICE : 4;
		unsigned int                        LOCATION : 6;
		unsigned int               PORT_CONNECTIVITY : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__VI {
	struct {
		unsigned int                            MISC : 4;
		unsigned int                           COLOR : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__VI {
	struct {
		unsigned int                 CONNECTION_TYPE : 4;
		unsigned int                  DEFAULT_DEVICE : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__VI {
	struct {
		unsigned int                        LOCATION : 6;
		unsigned int               PORT_CONNECTIVITY : 2;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__VI {
	struct {
		unsigned int                 IMPEDANCE_SENSE : 31;
		unsigned int                 PRESENCE_DETECT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__VI {
	struct {
		unsigned int                             TAG : 6;
		unsigned int                                 : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__VI {
	struct {
		unsigned int                                 : 5;
		unsigned int                       IN_ENABLE : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI {
	struct {
		unsigned int      AUDIO_CHANNEL_CAPABILITIES : 1;
		unsigned int         INPUT_AMPLIFIER_PRESENT : 1;
		unsigned int        OUTPUT_AMPLIFIER_PRESENT : 1;
		unsigned int    AMPLIFIER_PARAMETER_OVERRIDE : 1;
		unsigned int                                 : 1;
		unsigned int                          STRIPE : 1;
		unsigned int               PROCESSING_WIDGET : 1;
		unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1;
		unsigned int                 CONNECTION_LIST : 1;
		unsigned int                         DIGITAL : 1;
		unsigned int                   POWER_CONTROL : 1;
		unsigned int                         LR_SWAP : 1;
		unsigned int                                 : 4;
		unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4;
		unsigned int                            TYPE : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VI {
	struct {
		unsigned int         IMPEDANCE_SENSE_CAPABLE : 1;
		unsigned int                TRIGGER_REQUIRED : 1;
		unsigned int       JACK_DETECTION_CAPABILITY : 1;
		unsigned int         HEADPHONE_DRIVE_CAPABLE : 1;
		unsigned int                  OUTPUT_CAPABLE : 1;
		unsigned int                   INPUT_CAPABLE : 1;
		unsigned int               BALANCED_I_O_PINS : 1;
		unsigned int                            HDMI : 1;
		unsigned int                    VREF_CONTROL : 8;
		unsigned int                    EAPD_CAPABLE : 1;
		unsigned int                                 : 7;
		unsigned int                              DP : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__VI {
	struct {
		unsigned int                ASSOCIATION_INFO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__VI {
	struct {
		unsigned int                    MAX_CHANNELS : 3;
		unsigned int                     FORMAT_CODE : 4;
		unsigned int                                 : 1;
		unsigned int           SUPPORTED_FREQUENCIES : 8;
		unsigned int               DESCRIPTOR_BYTE_2 : 8;
		unsigned int    SUPPORTED_FREQUENCIES_STEREO : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__VI {
	struct {
		unsigned int                      DESCRIPTOR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__VI {
	struct {
		unsigned int                       SINK_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__VI {
	struct {
		unsigned int                 SINK_INFO_INDEX : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__VI {
	struct {
		unsigned int              CHANNEL_ALLOCATION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__VI {
	struct {
		unsigned int                     CODING_TYPE : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__VI {
	struct {
		unsigned int                   OUTPUT_ACTIVE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__VI {
	struct {
		unsigned int              LFE_PLAYBACK_LEVEL : 2;
		unsigned int                                 : 1;
		unsigned int                     LEVEL_SHIFT : 4;
		unsigned int                DOWN_MIX_INHIBIT : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__VI {
	struct {
		unsigned int                  FORMAT_CHANGED : 1;
		unsigned int    FORMAT_CHANGED_ACK_UR_ENABLE : 1;
		unsigned int                                 : 6;
		unsigned int            FORMAT_CHANGE_REASON : 8;
		unsigned int          FORMAT_CHANGE_RESPONSE : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_HBR__VI {
	struct {
		unsigned int                     HBR_CAPABLE : 1;
		unsigned int                                 : 3;
		unsigned int                      HBR_ENABLE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VI {
	struct {
		unsigned int                   VIDEO_LIPSYNC : 8;
		unsigned int                   AUDIO_LIPSYNC : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_LPIB__VI {
	struct {
		unsigned int                            LPIB : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI {
	struct {
		unsigned int              LPIB_SNAPSHOT_LOCK : 1;
		unsigned int                                 : 7;
		unsigned int        CYCLIC_BUFFER_WRAP_COUNT : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI {
	struct {
		unsigned int             LPIB_TIMER_SNAPSHOT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__VI {
	struct {
		unsigned int                 MANUFACTURER_ID : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__VI {
	struct {
		unsigned int           MULTICHANNEL01_ENABLE : 1;
		unsigned int             MULTICHANNEL01_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int       MULTICHANNEL01_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL1_ENABLE : 1;
		unsigned int              MULTICHANNEL1_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL1_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__VI {
	struct {
		unsigned int           MULTICHANNEL23_ENABLE : 1;
		unsigned int             MULTICHANNEL23_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int       MULTICHANNEL23_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL3_ENABLE : 1;
		unsigned int              MULTICHANNEL3_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL3_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__VI {
	struct {
		unsigned int           MULTICHANNEL45_ENABLE : 1;
		unsigned int             MULTICHANNEL45_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int       MULTICHANNEL45_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL5_ENABLE : 1;
		unsigned int              MULTICHANNEL5_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL5_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__VI {
	struct {
		unsigned int           MULTICHANNEL67_ENABLE : 1;
		unsigned int             MULTICHANNEL67_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int       MULTICHANNEL67_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__VI {
	struct {
		unsigned int            MULTICHANNEL7_ENABLE : 1;
		unsigned int              MULTICHANNEL7_MUTE : 1;
		unsigned int                                 : 2;
		unsigned int        MULTICHANNEL7_CHANNEL_ID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__VI {
	struct {
		unsigned int               MULTICHANNEL_MODE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__VI {
	struct {
		unsigned int                          PORTID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__VI {
	struct {
		unsigned int                          PORTID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__VI {
	struct {
		unsigned int                      PRODUCT_ID : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__VI {
	struct {
		unsigned int        REMOTE_KEEP_ALIVE_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int    REMOTE_KEEP_ALIVE_CAPABILITY : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI {
	struct {
		unsigned int                        SEQUENCE : 4;
		unsigned int             DEFAULT_ASSOCIATION : 4;
		unsigned int                            MISC : 4;
		unsigned int                           COLOR : 4;
		unsigned int                 CONNECTION_TYPE : 4;
		unsigned int                  DEFAULT_DEVICE : 4;
		unsigned int                        LOCATION : 6;
		unsigned int               PORT_CONNECTIVITY : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__VI {
	struct {
		unsigned int                            MISC : 4;
		unsigned int                           COLOR : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__VI {
	struct {
		unsigned int                 CONNECTION_TYPE : 4;
		unsigned int                  DEFAULT_DEVICE : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__VI {
	struct {
		unsigned int                        LOCATION : 6;
		unsigned int               PORT_CONNECTIVITY : 2;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__VI {
	struct {
		unsigned int           CONNECTION_LIST_ENTRY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__VI {
	struct {
		unsigned int                 IMPEDANCE_SENSE : 31;
		unsigned int                 PRESENCE_DETECT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__VI {
	struct {
		unsigned int              SPEAKER_ALLOCATION : 7;
		unsigned int                                 : 1;
		unsigned int                 HDMI_CONNECTION : 1;
		unsigned int                   DP_CONNECTION : 1;
		unsigned int           EXTRA_CONNECTION_INFO : 6;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__VI {
	struct {
		unsigned int            SINK_DESCRIPTION_LEN : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__VI {
	struct {
		unsigned int                             TAG : 6;
		unsigned int                                 : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__VI {
	struct {
		unsigned int                                 : 6;
		unsigned int                      OUT_ENABLE : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__VI {
	struct {
		unsigned int WIRELESS_DISPLAY_IDENTIFICATION : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI {
	struct {
		unsigned int      AUDIO_CHANNEL_CAPABILITIES : 1;
		unsigned int         INPUT_AMPLIFIER_PRESENT : 1;
		unsigned int        OUTPUT_AMPLIFIER_PRESENT : 1;
		unsigned int    AMPLIFIER_PARAMETER_OVERRIDE : 1;
		unsigned int                                 : 1;
		unsigned int                          STRIPE : 1;
		unsigned int               PROCESSING_WIDGET : 1;
		unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1;
		unsigned int                 CONNECTION_LIST : 1;
		unsigned int                         DIGITAL : 1;
		unsigned int                   POWER_CONTROL : 1;
		unsigned int                         LR_SWAP : 1;
		unsigned int                                 : 4;
		unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4;
		unsigned int                            TYPE : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VI {
	struct {
		unsigned int         IMPEDANCE_SENSE_CAPABLE : 1;
		unsigned int                TRIGGER_REQUIRED : 1;
		unsigned int       JACK_DETECTION_CAPABILITY : 1;
		unsigned int         HEADPHONE_DRIVE_CAPABLE : 1;
		unsigned int                  OUTPUT_CAPABLE : 1;
		unsigned int                   INPUT_CAPABLE : 1;
		unsigned int               BALANCED_I_O_PINS : 1;
		unsigned int                            HDMI : 1;
		unsigned int                    VREF_CONTROL : 8;
		unsigned int                    EAPD_CAPABLE : 1;
		unsigned int                                 : 7;
		unsigned int                              DP : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__VI {
	struct {
		unsigned int          CONNECTION_LIST_LENGTH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__VI {
	struct {
		unsigned int               IEC_60958_CS_MODE : 2;
		unsigned int      IEC_60958_CS_SOURCE_NUMBER : 4;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__VI {
	struct {
		unsigned int     IEC_60958_CS_CLOCK_ACCURACY : 2;
		unsigned int IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN : 1;
		unsigned int        IEC_60958_CS_WORD_LENGTH : 4;
		unsigned int IEC_60958_CS_WORD_LENGTH_OVRRD_EN : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__VI {
	struct {
		unsigned int IEC_60958_CS_SAMPLING_FREQUENCY : 6;
		unsigned int IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__VI {
	struct {
		unsigned int IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY : 4;
		unsigned int IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__VI {
	struct {
		unsigned int IEC_60958_CS_SAMPLING_FREQUENCY_COEFF : 4;
		unsigned int IEC_60958_CS_MPEG_SURROUND_INFO : 1;
		unsigned int             IEC_60958_CS_CGMS_A : 2;
		unsigned int       IEC_60958_CS_CGMS_A_VALID : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__VI {
	struct {
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_L : 4;
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_R : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__VI {
	struct {
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_2 : 4;
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_3 : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__VI {
	struct {
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_4 : 4;
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_5 : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__VI {
	struct {
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_6 : 4;
		unsigned int   IEC_60958_CS_CHANNEL_NUMBER_7 : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_FIFO_SIZE_CONTROL__VI {
	struct {
		unsigned int                   MIN_FIFO_SIZE : 7;
		unsigned int                                 : 1;
		unsigned int                   MAX_FIFO_SIZE : 7;
		unsigned int                                 : 1;
		unsigned int             MAX_LATENCY_SUPPORT : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_GLOBAL_CAPABILITIES__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS : 2;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CHANNEL0__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CHANNEL1__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CHANNEL2__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CHANNEL3__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CHANNEL4__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CHANNEL5__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CHANNEL6__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CHANNEL7__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CONTROL0__VI {
	struct {
		unsigned int                    INPUT_CRC_EN : 1;
		unsigned int                                 : 3;
		unsigned int            INPUT_CRC_BLOCK_MODE : 1;
		unsigned int                                 : 3;
		unsigned int          INPUT_CRC_INSTANCE_SEL : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CONTROL1__VI {
	struct {
		unsigned int            INPUT_CRC_BLOCK_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CONTROL2__VI {
	struct {
		unsigned int       INPUT_CRC_BLOCK_ITERATION : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_CONTROL3__VI {
	struct {
		unsigned int              INPUT_CRC_COMPLETE : 1;
		unsigned int                                 : 3;
		unsigned int  INPUT_CRC_BLOCK_COMPLETE_PHASE : 1;
		unsigned int                                 : 3;
		unsigned int    INPUT_CRC_CHANNEL_RESULT_SEL : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC0_RESULT__VI {
	struct {
		unsigned int                INPUT_CRC_RESULT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CHANNEL0__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CHANNEL1__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CHANNEL2__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CHANNEL3__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CHANNEL4__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CHANNEL5__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CHANNEL6__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CHANNEL7__VI {
	struct {
		unsigned int              INPUT_CRC_CHANNEL7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CONTROL0__VI {
	struct {
		unsigned int                    INPUT_CRC_EN : 1;
		unsigned int                                 : 3;
		unsigned int            INPUT_CRC_BLOCK_MODE : 1;
		unsigned int                                 : 3;
		unsigned int          INPUT_CRC_INSTANCE_SEL : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CONTROL1__VI {
	struct {
		unsigned int            INPUT_CRC_BLOCK_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CONTROL2__VI {
	struct {
		unsigned int       INPUT_CRC_BLOCK_ITERATION : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_CONTROL3__VI {
	struct {
		unsigned int              INPUT_CRC_COMPLETE : 1;
		unsigned int                                 : 3;
		unsigned int  INPUT_CRC_BLOCK_COMPLETE_PHASE : 1;
		unsigned int                                 : 3;
		unsigned int    INPUT_CRC_CHANNEL_RESULT_SEL : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_CRC1_RESULT__VI {
	struct {
		unsigned int                INPUT_CRC_RESULT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_INPUT_PAYLOAD_CAPABILITY__VI {
	struct {
		unsigned int        INPUT_PAYLOAD_CAPABILITY : 16;
		unsigned int                       INSTRMPAY : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_MEM_PWR_CTRL__VI {
	struct {
		unsigned int                AZ_MEM_PWR_FORCE : 2;
		unsigned int                  AZ_MEM_PWR_DIS : 1;
		unsigned int  AZ_INPUT_STREAM0_MEM_PWR_FORCE : 2;
		unsigned int    AZ_INPUT_STREAM0_MEM_PWR_DIS : 1;
		unsigned int  AZ_INPUT_STREAM1_MEM_PWR_FORCE : 2;
		unsigned int    AZ_INPUT_STREAM1_MEM_PWR_DIS : 1;
		unsigned int  AZ_INPUT_STREAM2_MEM_PWR_FORCE : 2;
		unsigned int    AZ_INPUT_STREAM2_MEM_PWR_DIS : 1;
		unsigned int  AZ_INPUT_STREAM3_MEM_PWR_FORCE : 2;
		unsigned int    AZ_INPUT_STREAM3_MEM_PWR_DIS : 1;
		unsigned int  AZ_INPUT_STREAM4_MEM_PWR_FORCE : 2;
		unsigned int    AZ_INPUT_STREAM4_MEM_PWR_DIS : 1;
		unsigned int  AZ_INPUT_STREAM5_MEM_PWR_FORCE : 2;
		unsigned int    AZ_INPUT_STREAM5_MEM_PWR_DIS : 1;
		unsigned int                                 : 7;
		unsigned int             AZ_MEM_PWR_MODE_SEL : 2;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_MEM_PWR_STATUS__VI {
	struct {
		unsigned int                AZ_MEM_PWR_STATE : 2;
		unsigned int  AZ_INPUT_STREAM0_MEM_PWR_STATE : 2;
		unsigned int  AZ_INPUT_STREAM1_MEM_PWR_STATE : 2;
		unsigned int  AZ_INPUT_STREAM2_MEM_PWR_STATE : 2;
		unsigned int  AZ_INPUT_STREAM3_MEM_PWR_STATE : 2;
		unsigned int  AZ_INPUT_STREAM4_MEM_PWR_STATE : 2;
		unsigned int  AZ_INPUT_STREAM5_MEM_PWR_STATE : 2;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_OUTPUT_PAYLOAD_CAPABILITY__VI {
	struct {
		unsigned int       OUTPUT_PAYLOAD_CAPABILITY : 16;
		unsigned int                      OUTSTRMPAY : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__VI {
	struct {
		unsigned int            LATENCY_HIDING_LEVEL : 8;
		unsigned int           SYS_MEM_ACTIVE_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int      INPUT_LATENCY_HIDING_LEVEL : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_SCLK_CONTROL__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int              AUDIO_SCLK_CONTROL : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_STREAM_DATA__VI {
	struct {
		unsigned int          AZALIA_STREAM_REG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_STREAM_DEBUG__VI {
	struct {
		unsigned int               STREAM_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZALIA_STREAM_INDEX__VI {
	struct {
		unsigned int         AZALIA_STREAM_REG_INDEX : 8;
		unsigned int      AZALIA_STREAM_REG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__VI {
	struct {
		unsigned int         IMMEDIATE_COMMAND_WRITE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__VI {
	struct {
		unsigned int         IMMEDIATE_COMMAND_WRITE : 17;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__VI {
	struct {
		unsigned int         IMMEDIATE_COMMAND_WRITE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__VI {
	struct {
		unsigned int         IMMEDIATE_COMMAND_WRITE : 17;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__VI {
	struct {
		unsigned int         IMMEDIATE_COMMAND_WRITE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__VI {
	struct {
		unsigned int         IMMEDIATE_COMMAND_WRITE : 17;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BF_ANA_ISO_CNTL__VI {
	struct {
		unsigned int             BF_ANA_ISO_DIS_MASK : 1;
		unsigned int            BF_VDDC_ISO_DIS_MASK : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_ATOMIC_ERR_LOG__VI {
	struct {
		unsigned int                UR_ATOMIC_OPCODE : 1;
		unsigned int             UR_ATOMIC_REQEN_LOW : 1;
		unsigned int                                 : 14;
		unsigned int          CLEAR_UR_ATOMIC_OPCODE : 1;
		unsigned int       CLEAR_UR_ATOMIC_REQEN_LOW : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_BME_STATUS__VI {
	struct {
		unsigned int                  DMA_ON_BME_LOW : 1;
		unsigned int                                 : 15;
		unsigned int            CLEAR_DMA_ON_BME_LOW : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_CLK_CTRL__VI {
	struct {
		unsigned int                BIF_XSTCLK_READY : 1;
		unsigned int       BACO_XSTCLK_SWITCH_BYPASS : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DOORBELL_APER_EN__VI {
	struct {
		unsigned int            BIF_DOORBELL_APER_EN : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DOORBELL_GBLAPER1_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int         DOORBELL_GBLAPER1_LOWER : 10;
		unsigned int                                 : 19;
		unsigned int            DOORBELL_GBLAPER1_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DOORBELL_GBLAPER1_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int         DOORBELL_GBLAPER1_UPPER : 10;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DOORBELL_GBLAPER2_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int         DOORBELL_GBLAPER2_LOWER : 10;
		unsigned int                                 : 19;
		unsigned int            DOORBELL_GBLAPER2_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_DOORBELL_GBLAPER2_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int         DOORBELL_GBLAPER2_UPPER : 10;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_GPUIOV_FB_TOTAL_FB_INFO__VI {
	struct {
		unsigned int              TOTAL_FB_AVAILABLE : 16;
		unsigned int               TOTAL_FB_CONSUMED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_GPUIOV_RESET_NOTIFICATION__VI {
	struct {
		unsigned int              RESET_NOTIFICATION : 17;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_GPUIOV_VM_INIT_STATUS__VI {
	struct {
		unsigned int                  VM_INIT_STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_IOV_FUNC_IDENTIFIER__VI {
	struct {
		unsigned int                 FUNC_IDENTIFIER : 1;
		unsigned int                                 : 30;
		unsigned int                      IOV_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_MM_INDACCESS_CNTL__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                MM_INDACCESS_DIS : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_MST_TRANS_PENDING__VI {
	struct {
		unsigned int           BIF_MST_TRANS_PENDING : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RB_BASE__VI {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RB_CNTL__VI {
	struct {
		unsigned int                       RB_ENABLE : 1;
		unsigned int                         RB_SIZE : 5;
		unsigned int                                 : 2;
		unsigned int           WPTR_WRITEBACK_ENABLE : 1;
		unsigned int            WPTR_WRITEBACK_TIMER : 5;
		unsigned int                                 : 3;
		unsigned int                     BIF_RB_TRAN : 1;
		unsigned int                                 : 13;
		unsigned int             WPTR_OVERFLOW_CLEAR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RB_RPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                          OFFSET : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RB_WPTR__VI {
	struct {
		unsigned int                 BIF_RB_OVERFLOW : 1;
		unsigned int                                 : 1;
		unsigned int                          OFFSET : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RB_WPTR_ADDR_HI__VI {
	struct {
		unsigned int                            ADDR : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RB_WPTR_ADDR_LO__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_MST_SMBUS_CMDSTATUS__VI {
	struct {
		unsigned int         REG_SMBUS_clkGate_timer : 8;
		unsigned int        REG_SMBUS_clkSetup_timer : 4;
		unsigned int                                 : 4;
		unsigned int         REG_SMBUS_timeout_timer : 8;
		unsigned int            SMBUS_RFE_mstTimeout : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RFE_WARMRST_CNTL__VI {
	struct {
		unsigned int            REG_RST_warmRstRfeEn : 1;
		unsigned int            REG_RST_warmRstImpEn : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_RLC_INTR_CNTL__VI {
	struct {
		unsigned int             RLC_HVCMD_INTERRUPT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SLV_TRANS_PENDING__VI {
	struct {
		unsigned int           BIF_SLV_TRANS_PENDING : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SMU_DATA__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                    BIF_SMU_DATA : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_SMU_INDEX__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                   BIF_SMU_INDEX : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_FB_CMP__VI {
	struct {
		unsigned int            VDDGFX_FB_HDP_CMP_EN : 1;
		unsigned int          VDDGFX_FB_HDP_STALL_EN : 1;
		unsigned int           VDDGFX_FB_XDMA_CMP_EN : 1;
		unsigned int         VDDGFX_FB_XDMA_STALL_EN : 1;
		unsigned int            VDDGFX_FB_VGA_CMP_EN : 1;
		unsigned int          VDDGFX_FB_VGA_STALL_EN : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX0_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX0_REG_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int          VDDGFX_GFX0_REG_CMP_EN : 1;
		unsigned int        VDDGFX_GFX0_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX0_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX0_REG_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX1_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX1_REG_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int          VDDGFX_GFX1_REG_CMP_EN : 1;
		unsigned int        VDDGFX_GFX1_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX1_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX1_REG_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX2_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX2_REG_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int          VDDGFX_GFX2_REG_CMP_EN : 1;
		unsigned int        VDDGFX_GFX2_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX2_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX2_REG_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX3_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX3_REG_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int          VDDGFX_GFX3_REG_CMP_EN : 1;
		unsigned int        VDDGFX_GFX3_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX3_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX3_REG_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX4_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX4_REG_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int          VDDGFX_GFX4_REG_CMP_EN : 1;
		unsigned int        VDDGFX_GFX4_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX4_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX4_REG_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX5_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX5_REG_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int          VDDGFX_GFX5_REG_CMP_EN : 1;
		unsigned int        VDDGFX_GFX5_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_GFX5_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_GFX5_REG_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_RSV1_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_RSV1_REG_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int          VDDGFX_RSV1_REG_CMP_EN : 1;
		unsigned int        VDDGFX_RSV1_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_RSV1_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_RSV1_REG_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_RSV2_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_RSV2_REG_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int          VDDGFX_RSV2_REG_CMP_EN : 1;
		unsigned int        VDDGFX_RSV2_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_RSV2_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_RSV2_REG_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_RSV3_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_RSV3_REG_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int          VDDGFX_RSV3_REG_CMP_EN : 1;
		unsigned int        VDDGFX_RSV3_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_RSV3_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_RSV3_REG_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_RSV4_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_RSV4_REG_LOWER : 16;
		unsigned int                                 : 12;
		unsigned int          VDDGFX_RSV4_REG_CMP_EN : 1;
		unsigned int        VDDGFX_RSV4_REG_STALL_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VDDGFX_RSV4_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int           VDDGFX_RSV4_REG_UPPER : 16;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BIF_VIRT_RESET_REQ__VI {
	struct {
		unsigned int               VIRT_RESET_REQ_VF : 16;
		unsigned int                                 : 15;
		unsigned int           VIRT_RESET_REQ_SOFTPF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BLND_CONTROL__VI {
	struct {
		unsigned int                BLND_GLOBAL_GAIN : 8;
		unsigned int                       BLND_MODE : 2;
		unsigned int                BLND_STEREO_TYPE : 2;
		unsigned int            BLND_STEREO_POLARITY : 1;
		unsigned int             BLND_FEEDTHROUGH_EN : 1;
		unsigned int                                 : 2;
		unsigned int                 BLND_ALPHA_MODE : 2;
		unsigned int                                 : 2;
		unsigned int            BLND_MULTIPLIED_MODE : 1;
		unsigned int                                 : 3;
		unsigned int               BLND_GLOBAL_ALPHA : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BLND_CONTROL2__VI {
	struct {
		unsigned int                      PTI_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               PTI_NEW_PIXEL_GAP : 2;
		unsigned int             BLND_NEW_PIXEL_MODE : 1;
		unsigned int         BLND_SUPERAA_DEGAMMA_EN : 1;
		unsigned int         BLND_SUPERAA_REGAMMA_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BLND_DEBUG__VI {
	struct {
		unsigned int             BLND_CNV_MUX_SELECT : 1;
		unsigned int                      BLND_DEBUG : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BLND_REG_UPDATE_STATUS__VI {
	struct {
		unsigned int   DCP_BLNDC_GRPH_UPDATE_PENDING : 1;
		unsigned int   DCP_BLNDO_GRPH_UPDATE_PENDING : 1;
		unsigned int DCP_BLNDC_GRPH_SURF_UPDATE_PENDING : 1;
		unsigned int DCP_BLNDO_GRPH_SURF_UPDATE_PENDING : 1;
		unsigned int    DCP_BLNDC_OVL_UPDATE_PENDING : 1;
		unsigned int    DCP_BLNDO_OVL_UPDATE_PENDING : 1;
		unsigned int    DCP_BLNDC_CUR_UPDATE_PENDING : 1;
		unsigned int    DCP_BLNDO_CUR_UPDATE_PENDING : 1;
		unsigned int        SCL_BLNDC_UPDATE_PENDING : 1;
		unsigned int        SCL_BLNDO_UPDATE_PENDING : 1;
		unsigned int       BLND_BLNDC_UPDATE_PENDING : 1;
		unsigned int       BLND_BLNDO_UPDATE_PENDING : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BLND_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int            BLND_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BLND_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int           BLND_TEST_DEBUG_INDEX : 8;
		unsigned int        BLND_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BLND_UNDERFLOW_INTERRUPT__VI {
	struct {
		unsigned int      BLND_UNDERFLOW_INT_OCCURED : 1;
		unsigned int                                 : 7;
		unsigned int          BLND_UNDERFLOW_INT_ACK : 1;
		unsigned int                                 : 3;
		unsigned int         BLND_UNDERFLOW_INT_MASK : 1;
		unsigned int                                 : 3;
		unsigned int   BLND_UNDERFLOW_INT_PIPE_INDEX : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BLND_UPDATE__VI {
	struct {
		unsigned int             BLND_UPDATE_PENDING : 1;
		unsigned int                                 : 7;
		unsigned int               BLND_UPDATE_TAKEN : 1;
		unsigned int                                 : 7;
		unsigned int                BLND_UPDATE_LOCK : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BLND_V_UPDATE_LOCK__VI {
	struct {
		unsigned int     BLND_DCP_GRPH_V_UPDATE_LOCK : 1;
		unsigned int BLND_DCP_GRPH_SURF_V_UPDATE_LOCK : 1;
		unsigned int                                 : 6;
		unsigned int      BLND_DCP_OVL_V_UPDATE_LOCK : 1;
		unsigned int                                 : 7;
		unsigned int      BLND_DCP_CUR_V_UPDATE_LOCK : 1;
		unsigned int                                 : 7;
		unsigned int     BLND_DCP_CUR2_V_UPDATE_LOCK : 1;
		unsigned int                                 : 3;
		unsigned int          BLND_SCL_V_UPDATE_LOCK : 1;
		unsigned int         BLND_BLND_V_UPDATE_LOCK : 1;
		unsigned int                                 : 1;
		unsigned int         BLND_V_UPDATE_LOCK_MODE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BPHYC_DAC_AUTO_CALIB_CONTROL__VI {
	struct {
		unsigned int             BPHYC_DAC_CAL_INITB : 1;
		unsigned int                BPHYC_DAC_CAL_EN : 1;
		unsigned int         BPHYC_DAC_CAL_DACADJ_EN : 1;
		unsigned int                                 : 1;
		unsigned int       BPHYC_DAC_CAL_WAIT_ADJUST : 10;
		unsigned int                                 : 6;
		unsigned int              BPHYC_DAC_CAL_MASK : 3;
		unsigned int                                 : 5;
		unsigned int          BPHYC_DAC_CAL_COMPLETE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BPHYC_DAC_MACRO_CNTL__VI {
	struct {
		unsigned int           BPHYC_DAC_WHITE_LEVEL : 2;
		unsigned int                                 : 6;
		unsigned int    BPHYC_DAC_WHITE_FINE_CONTROL : 6;
		unsigned int                                 : 2;
		unsigned int    BPHYC_DAC_BANDGAP_ADJUSTMENT : 6;
		unsigned int                                 : 2;
		unsigned int        BPHYC_DAC_ANALOG_MONITOR : 4;
		unsigned int               BPHYC_DAC_COREMON : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union BX_RESET_CNTL__VI {
	struct {
		unsigned int                   LINK_TRAIN_EN : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_DCC_BASE__VI {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR0_DCC_CONTROL__VI {
	struct {
		unsigned int      OVERWRITE_COMBINER_DISABLE : 1;
		unsigned int                KEY_CLEAR_ENABLE : 1;
		unsigned int     MAX_UNCOMPRESSED_BLOCK_SIZE : 2;
		unsigned int       MIN_COMPRESSED_BLOCK_SIZE : 1;
		unsigned int       MAX_COMPRESSED_BLOCK_SIZE : 2;
		unsigned int                 COLOR_TRANSFORM : 2;
		unsigned int          INDEPENDENT_64B_BLOCKS : 1;
		unsigned int             LOSSY_RGB_PRECISION : 4;
		unsigned int           LOSSY_ALPHA_PRECISION : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_DCC_BASE__VI {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR1_DCC_CONTROL__VI {
	struct {
		unsigned int      OVERWRITE_COMBINER_DISABLE : 1;
		unsigned int                KEY_CLEAR_ENABLE : 1;
		unsigned int     MAX_UNCOMPRESSED_BLOCK_SIZE : 2;
		unsigned int       MIN_COMPRESSED_BLOCK_SIZE : 1;
		unsigned int       MAX_COMPRESSED_BLOCK_SIZE : 2;
		unsigned int                 COLOR_TRANSFORM : 2;
		unsigned int          INDEPENDENT_64B_BLOCKS : 1;
		unsigned int             LOSSY_RGB_PRECISION : 4;
		unsigned int           LOSSY_ALPHA_PRECISION : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_DCC_BASE__VI {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR2_DCC_CONTROL__VI {
	struct {
		unsigned int      OVERWRITE_COMBINER_DISABLE : 1;
		unsigned int                KEY_CLEAR_ENABLE : 1;
		unsigned int     MAX_UNCOMPRESSED_BLOCK_SIZE : 2;
		unsigned int       MIN_COMPRESSED_BLOCK_SIZE : 1;
		unsigned int       MAX_COMPRESSED_BLOCK_SIZE : 2;
		unsigned int                 COLOR_TRANSFORM : 2;
		unsigned int          INDEPENDENT_64B_BLOCKS : 1;
		unsigned int             LOSSY_RGB_PRECISION : 4;
		unsigned int           LOSSY_ALPHA_PRECISION : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_DCC_BASE__VI {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR3_DCC_CONTROL__VI {
	struct {
		unsigned int      OVERWRITE_COMBINER_DISABLE : 1;
		unsigned int                KEY_CLEAR_ENABLE : 1;
		unsigned int     MAX_UNCOMPRESSED_BLOCK_SIZE : 2;
		unsigned int       MIN_COMPRESSED_BLOCK_SIZE : 1;
		unsigned int       MAX_COMPRESSED_BLOCK_SIZE : 2;
		unsigned int                 COLOR_TRANSFORM : 2;
		unsigned int          INDEPENDENT_64B_BLOCKS : 1;
		unsigned int             LOSSY_RGB_PRECISION : 4;
		unsigned int           LOSSY_ALPHA_PRECISION : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_DCC_BASE__VI {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR4_DCC_CONTROL__VI {
	struct {
		unsigned int      OVERWRITE_COMBINER_DISABLE : 1;
		unsigned int                KEY_CLEAR_ENABLE : 1;
		unsigned int     MAX_UNCOMPRESSED_BLOCK_SIZE : 2;
		unsigned int       MIN_COMPRESSED_BLOCK_SIZE : 1;
		unsigned int       MAX_COMPRESSED_BLOCK_SIZE : 2;
		unsigned int                 COLOR_TRANSFORM : 2;
		unsigned int          INDEPENDENT_64B_BLOCKS : 1;
		unsigned int             LOSSY_RGB_PRECISION : 4;
		unsigned int           LOSSY_ALPHA_PRECISION : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_DCC_BASE__VI {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR5_DCC_CONTROL__VI {
	struct {
		unsigned int      OVERWRITE_COMBINER_DISABLE : 1;
		unsigned int                KEY_CLEAR_ENABLE : 1;
		unsigned int     MAX_UNCOMPRESSED_BLOCK_SIZE : 2;
		unsigned int       MIN_COMPRESSED_BLOCK_SIZE : 1;
		unsigned int       MAX_COMPRESSED_BLOCK_SIZE : 2;
		unsigned int                 COLOR_TRANSFORM : 2;
		unsigned int          INDEPENDENT_64B_BLOCKS : 1;
		unsigned int             LOSSY_RGB_PRECISION : 4;
		unsigned int           LOSSY_ALPHA_PRECISION : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_DCC_BASE__VI {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR6_DCC_CONTROL__VI {
	struct {
		unsigned int      OVERWRITE_COMBINER_DISABLE : 1;
		unsigned int                KEY_CLEAR_ENABLE : 1;
		unsigned int     MAX_UNCOMPRESSED_BLOCK_SIZE : 2;
		unsigned int       MIN_COMPRESSED_BLOCK_SIZE : 1;
		unsigned int       MAX_COMPRESSED_BLOCK_SIZE : 2;
		unsigned int                 COLOR_TRANSFORM : 2;
		unsigned int          INDEPENDENT_64B_BLOCKS : 1;
		unsigned int             LOSSY_RGB_PRECISION : 4;
		unsigned int           LOSSY_ALPHA_PRECISION : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_DCC_BASE__VI {
	struct {
		unsigned int                       BASE_256B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_COLOR7_DCC_CONTROL__VI {
	struct {
		unsigned int      OVERWRITE_COMBINER_DISABLE : 1;
		unsigned int                KEY_CLEAR_ENABLE : 1;
		unsigned int     MAX_UNCOMPRESSED_BLOCK_SIZE : 2;
		unsigned int       MIN_COMPRESSED_BLOCK_SIZE : 1;
		unsigned int       MAX_COMPRESSED_BLOCK_SIZE : 2;
		unsigned int                 COLOR_TRANSFORM : 2;
		unsigned int          INDEPENDENT_64B_BLOCKS : 1;
		unsigned int             LOSSY_RGB_PRECISION : 4;
		unsigned int           LOSSY_ALPHA_PRECISION : 4;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DCC_CONFIG__VI {
	struct {
		unsigned int        OVERWRITE_COMBINER_DEPTH : 5;
		unsigned int      OVERWRITE_COMBINER_DISABLE : 1;
		unsigned int OVERWRITE_COMBINER_CC_POP_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int       FC_RDLAT_KEYID_FIFO_DEPTH : 8;
		unsigned int     READ_RETURN_SKID_FIFO_DEPTH : 7;
		unsigned int                                 : 1;
		unsigned int           DCC_CACHE_EVICT_POINT : 4;
		unsigned int              DCC_CACHE_NUM_TAGS : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DCC_CONTROL__VI {
	struct {
		unsigned int      OVERWRITE_COMBINER_DISABLE : 1;
		unsigned int OVERWRITE_COMBINER_MRT_SHARING_DISABLE : 1;
		unsigned int    OVERWRITE_COMBINER_WATERMARK : 5;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_19__VI {
	struct {
		unsigned int                 SURF_SYNC_STATE : 2;
		unsigned int                 SURF_SYNC_START : 1;
		unsigned int                         SF_BUSY : 1;
		unsigned int                         CS_BUSY : 1;
		unsigned int                         RB_BUSY : 1;
		unsigned int                         DS_BUSY : 1;
		unsigned int                         TB_BUSY : 1;
		unsigned int                         IB_BUSY : 1;
		unsigned int                        DRR_BUSY : 1;
		unsigned int                         DF_BUSY : 1;
		unsigned int                         DD_BUSY : 1;
		unsigned int                         DC_BUSY : 1;
		unsigned int                         DK_BUSY : 1;
		unsigned int              DF_SKID_FIFO_EMPTY : 1;
		unsigned int             DF_CLEAR_FIFO_EMPTY : 1;
		unsigned int                        DD_READY : 1;
		unsigned int                    DC_FIFO_FULL : 1;
		unsigned int                        DC_READY : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_20__VI {
	struct {
		unsigned int                MC_RDREQ_CREDITS : 6;
		unsigned int                MC_WRREQ_CREDITS : 6;
		unsigned int           CC_RDREQ_HAD_ITS_TURN : 1;
		unsigned int           FC_RDREQ_HAD_ITS_TURN : 1;
		unsigned int           CM_RDREQ_HAD_ITS_TURN : 1;
		unsigned int                                 : 1;
		unsigned int           CC_WRREQ_HAD_ITS_TURN : 1;
		unsigned int           FC_WRREQ_HAD_ITS_TURN : 1;
		unsigned int           CM_WRREQ_HAD_ITS_TURN : 1;
		unsigned int                                 : 1;
		unsigned int             CC_WRREQ_FIFO_EMPTY : 1;
		unsigned int             FC_WRREQ_FIFO_EMPTY : 1;
		unsigned int             CM_WRREQ_FIFO_EMPTY : 1;
		unsigned int            DCC_WRREQ_FIFO_EMPTY : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_21__VI {
	struct {
		unsigned int                         CM_BUSY : 1;
		unsigned int                         FC_BUSY : 1;
		unsigned int                         CC_BUSY : 1;
		unsigned int                         BB_BUSY : 1;
		unsigned int                         MA_BUSY : 1;
		unsigned int                   CORE_SCLK_VLD : 1;
		unsigned int                   REG_SCLK1_VLD : 1;
		unsigned int                   REG_SCLK0_VLD : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CB_DEBUG_BUS_22__VI {
	struct {
		unsigned int            OUTSTANDING_MC_READS : 12;
		unsigned int           OUTSTANDING_MC_WRITES : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_DC_PIPE_DIS__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                     DC_PIPE_DIS : 6;
		unsigned int                                 : 1;
		unsigned int                MCIF_WB_URG_OVRD : 1;
		unsigned int                 MCIF_WB_URG_LVL : 4;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_FCTRL_FUSES__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int         EXT_EFUSE_MACRO_PRESENT : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_GC_SHADER_RATE_CONFIG__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                       DPFP_RATE : 2;
		unsigned int             SQC_BALANCE_DISABLE : 1;
		unsigned int                        HALF_LDS : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_HARVEST_FUSES__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                     VCE_DISABLE : 2;
		unsigned int                                 : 1;
		unsigned int                     UVD_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int                      ACP_EXISTS : 1;
		unsigned int                                 : 1;
		unsigned int                      DC_DISABLE : 6;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__VI {
	struct {
		unsigned int         INPUT_PORT_CONNECTIVITY : 3;
		unsigned int                                 : 1;
		unsigned int INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__VI {
	struct {
		unsigned int               PORT_CONNECTIVITY : 3;
		unsigned int                                 : 1;
		unsigned int PORT_CONNECTIVITY_OVERRIDE_ENABLE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CFG_LNC_WINDOW__VI {
	struct {
		unsigned int                 CFG_LNC_WINDOW0 : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_CLKPIN_CNTL_DC__VI {
	struct {
		unsigned int                          OSC_EN : 1;
		unsigned int                    XTL_LOW_GAIN : 2;
		unsigned int                                 : 6;
		unsigned int              XTL_XOCLK_DRV_R_EN : 1;
		unsigned int                      XTALIN_SEL : 3;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_MCLK_CNTL__VI {
	struct {
		unsigned int                    MCLK_DIVIDER : 7;
		unsigned int                                 : 1;
		unsigned int                MCLK_DIR_CNTL_EN : 1;
		unsigned int               MCLK_DIR_CNTL_TOG : 1;
		unsigned int           MCLK_DIR_CNTL_DIVIDER : 7;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_MCLK_STATUS__VI {
	struct {
		unsigned int                     MCLK_STATUS : 1;
		unsigned int           MCLK_DIR_CNTL_DONETOG : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CG_SPLL_FUNC_CNTL_7__VI {
	struct {
		unsigned int                   SPLL_BW_CNTRL : 12;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT0_OFFSET_HI__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT1_OFFSET_HI__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT2_OFFSET_HI__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_BM__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_CD0__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_CD1__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_CD2__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_CD3__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_CK0__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_CK1__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_CK2__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_CK3__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_K0__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_K1__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_K2__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_K3__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_OFFSET__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_OFFSET_HI__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT3_STATUS__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_BM__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_CD0__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_CD1__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_CD2__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_CD3__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_CK0__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_CK1__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_CK2__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_CK3__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_K0__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_K1__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_K2__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_K3__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_OFFSET__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_OFFSET_HI__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLIENT4_STATUS__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CLKREQB_PERF_COUNTER__VI {
	struct {
		unsigned int      CLKREQB_PERF_COUNTER_LOWER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_C11_C12__VI {
	struct {
		unsigned int                     CNV_CSC_C11 : 13;
		unsigned int                                 : 3;
		unsigned int                     CNV_CSC_C12 : 13;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_C13_C14__VI {
	struct {
		unsigned int                     CNV_CSC_C13 : 13;
		unsigned int                                 : 3;
		unsigned int                     CNV_CSC_C14 : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_C21_C22__VI {
	struct {
		unsigned int                     CNV_CSC_C21 : 13;
		unsigned int                                 : 3;
		unsigned int                     CNV_CSC_C22 : 13;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_C23_C24__VI {
	struct {
		unsigned int                     CNV_CSC_C23 : 13;
		unsigned int                                 : 3;
		unsigned int                     CNV_CSC_C24 : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_C31_C32__VI {
	struct {
		unsigned int                     CNV_CSC_C31 : 13;
		unsigned int                                 : 3;
		unsigned int                     CNV_CSC_C32 : 13;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_C33_C34__VI {
	struct {
		unsigned int                     CNV_CSC_C33 : 13;
		unsigned int                                 : 3;
		unsigned int                     CNV_CSC_C34 : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_CLAMP_B__VI {
	struct {
		unsigned int           CNV_CSC_CLAMP_UPPER_B : 16;
		unsigned int           CNV_CSC_CLAMP_LOWER_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_CLAMP_G__VI {
	struct {
		unsigned int           CNV_CSC_CLAMP_UPPER_G : 16;
		unsigned int           CNV_CSC_CLAMP_LOWER_G : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_CLAMP_R__VI {
	struct {
		unsigned int           CNV_CSC_CLAMP_UPPER_R : 16;
		unsigned int           CNV_CSC_CLAMP_LOWER_R : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_CONTROL__VI {
	struct {
		unsigned int                  CNV_CSC_BYPASS : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_ROUND_OFFSET_B__VI {
	struct {
		unsigned int          CNV_CSC_ROUND_OFFSET_B : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_ROUND_OFFSET_G__VI {
	struct {
		unsigned int          CNV_CSC_ROUND_OFFSET_G : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_CSC_ROUND_OFFSET_R__VI {
	struct {
		unsigned int          CNV_CSC_ROUND_OFFSET_R : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_INPUT_SELECT__VI {
	struct {
		unsigned int            CNV_INPUT_SRC_SELECT : 2;
		unsigned int           CNV_INPUT_PIPE_SELECT : 3;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_MODE__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int          CNV_FRAME_CAPTURE_RATE : 2;
		unsigned int                                 : 2;
		unsigned int              CNV_WINDOW_CROP_EN : 1;
		unsigned int                 CNV_STEREO_TYPE : 2;
		unsigned int             CNV_INTERLACED_MODE : 1;
		unsigned int               CNV_EYE_SELECTION : 2;
		unsigned int             CNV_STEREO_POLARITY : 1;
		unsigned int      CNV_INTERLACED_FIELD_ORDER : 1;
		unsigned int                CNV_STEREO_SPLIT : 1;
		unsigned int                                 : 3;
		unsigned int                 CNV_NEW_CONTENT : 1;
		unsigned int                                 : 6;
		unsigned int            CNV_FRAME_CAPTURE_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_SOURCE_SIZE__VI {
	struct {
		unsigned int                CNV_SOURCE_WIDTH : 15;
		unsigned int                                 : 1;
		unsigned int               CNV_SOURCE_HEIGHT : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_TEST_CNTL__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                 CNV_TEST_CRC_EN : 1;
		unsigned int                                 : 3;
		unsigned int            CNV_TEST_CRC_CONT_EN : 1;
		unsigned int                                 : 7;
		unsigned int            CNV_TEST_CRC_DE_ONLY : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_TEST_CRC_BLUE__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int          CNV_TEST_CRC_BLUE_MASK : 12;
		unsigned int           CNV_TEST_CRC_SIG_BLUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_TEST_CRC_GREEN__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int         CNV_TEST_CRC_GREEN_MASK : 12;
		unsigned int          CNV_TEST_CRC_SIG_GREEN : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_TEST_CRC_RED__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int           CNV_TEST_CRC_RED_MASK : 12;
		unsigned int            CNV_TEST_CRC_SIG_RED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int             CNV_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int            CNV_TEST_DEBUG_INDEX : 8;
		unsigned int         CNV_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_UPDATE__VI {
	struct {
		unsigned int              CNV_UPDATE_PENDING : 1;
		unsigned int                                 : 7;
		unsigned int                CNV_UPDATE_TAKEN : 1;
		unsigned int                                 : 7;
		unsigned int                 CNV_UPDATE_LOCK : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_WINDOW_SIZE__VI {
	struct {
		unsigned int                CNV_WINDOW_WIDTH : 12;
		unsigned int                                 : 4;
		unsigned int               CNV_WINDOW_HEIGHT : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CNV_WINDOW_START__VI {
	struct {
		unsigned int              CNV_WINDOW_START_X : 12;
		unsigned int                                 : 4;
		unsigned int              CNV_WINDOW_START_Y : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COL_MAN_DEBUG_CONTROL__VI {
	struct {
		unsigned int COL_MAN_GLOBAL_PASSTHROUGH_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COL_MAN_FP_CONVERTED_FIELD__VI {
	struct {
		unsigned int COL_MAN_FP_CONVERTED_FIELD_DATA : 18;
		unsigned int                                 : 2;
		unsigned int COL_MAN_FP_CONVERTED_FIELD_INDEX : 6;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COL_MAN_INPUT_CSC_CONTROL__VI {
	struct {
		unsigned int                  INPUT_CSC_MODE : 2;
		unsigned int            INPUT_CSC_INPUT_TYPE : 2;
		unsigned int       INPUT_CSC_CONVERSION_MODE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COL_MAN_OUTPUT_CSC_CONTROL__VI {
	struct {
		unsigned int                 OUTPUT_CSC_MODE : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COL_MAN_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int         COL_MAN_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COL_MAN_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int        COL_MAN_TEST_DEBUG_INDEX : 8;
		unsigned int     COL_MAN_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COL_MAN_UPDATE__VI {
	struct {
		unsigned int          COL_MAN_UPDATE_PENDING : 1;
		unsigned int            COL_MAN_UPDATE_TAKEN : 1;
		unsigned int                                 : 14;
		unsigned int             COL_MAN_UPDATE_LOCK : 1;
		unsigned int                                 : 7;
		unsigned int COL_MAN_DISABLE_MULTIPLE_UPDATE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXA_TRANS_C11_C12__VI {
	struct {
		unsigned int          COMM_MATRIXA_TRANS_C11 : 16;
		unsigned int          COMM_MATRIXA_TRANS_C12 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXA_TRANS_C13_C14__VI {
	struct {
		unsigned int          COMM_MATRIXA_TRANS_C13 : 16;
		unsigned int          COMM_MATRIXA_TRANS_C14 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXA_TRANS_C21_C22__VI {
	struct {
		unsigned int          COMM_MATRIXA_TRANS_C21 : 16;
		unsigned int          COMM_MATRIXA_TRANS_C22 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXA_TRANS_C23_C24__VI {
	struct {
		unsigned int          COMM_MATRIXA_TRANS_C23 : 16;
		unsigned int          COMM_MATRIXA_TRANS_C24 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXA_TRANS_C31_C32__VI {
	struct {
		unsigned int          COMM_MATRIXA_TRANS_C31 : 16;
		unsigned int          COMM_MATRIXA_TRANS_C32 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXA_TRANS_C33_C34__VI {
	struct {
		unsigned int          COMM_MATRIXA_TRANS_C33 : 16;
		unsigned int          COMM_MATRIXA_TRANS_C34 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXB_TRANS_C11_C12__VI {
	struct {
		unsigned int          COMM_MATRIXB_TRANS_C11 : 16;
		unsigned int          COMM_MATRIXB_TRANS_C12 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXB_TRANS_C13_C14__VI {
	struct {
		unsigned int          COMM_MATRIXB_TRANS_C13 : 16;
		unsigned int          COMM_MATRIXB_TRANS_C14 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXB_TRANS_C21_C22__VI {
	struct {
		unsigned int          COMM_MATRIXB_TRANS_C21 : 16;
		unsigned int          COMM_MATRIXB_TRANS_C22 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXB_TRANS_C23_C24__VI {
	struct {
		unsigned int          COMM_MATRIXB_TRANS_C23 : 16;
		unsigned int          COMM_MATRIXB_TRANS_C24 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXB_TRANS_C31_C32__VI {
	struct {
		unsigned int          COMM_MATRIXB_TRANS_C31 : 16;
		unsigned int          COMM_MATRIXB_TRANS_C32 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMM_MATRIXB_TRANS_C33_C34__VI {
	struct {
		unsigned int          COMM_MATRIXB_TRANS_C33 : 16;
		unsigned int          COMM_MATRIXB_TRANS_C34 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_DISPATCH_ID__VI {
	struct {
		unsigned int                     DISPATCH_ID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_NOWHERE__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_RELAUNCH__VI {
	struct {
		unsigned int                         PAYLOAD : 30;
		unsigned int                        IS_EVENT : 1;
		unsigned int                        IS_STATE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_THREADGROUP_ID__VI {
	struct {
		unsigned int                  THREADGROUP_ID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_WAVE_RESTORE_ADDR_HI__VI {
	struct {
		unsigned int                            ADDR : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_WAVE_RESTORE_ADDR_LO__VI {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union COMPUTE_WAVE_RESTORE_CONTROL__VI {
	struct {
		unsigned int                             ATC : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CONFIG_RESERVED__VI {
	struct {
		unsigned int                 CONFIG_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED0__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED1__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED10__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED11__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED2__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED3__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED4__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED5__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED6__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED7__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED8__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPLL_MACRO_CNTL_RESERVED9__VI {
	struct {
		unsigned int        CPLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CPM_CONTROL__VI {
	struct {
		unsigned int            LCLK_DYN_GATE_ENABLE : 1;
		unsigned int           TXCLK_DYN_GATE_ENABLE : 1;
		unsigned int          TXCLK_PERM_GATE_ENABLE : 1;
		unsigned int           TXCLK_PIF_GATE_ENABLE : 1;
		unsigned int          TXCLK_GSKT_GATE_ENABLE : 1;
		unsigned int          TXCLK_LCNT_GATE_ENABLE : 1;
		unsigned int          TXCLK_REGS_GATE_ENABLE : 1;
		unsigned int          TXCLK_PRBS_GATE_ENABLE : 1;
		unsigned int         REFCLK_REGS_GATE_ENABLE : 1;
		unsigned int           LCLK_DYN_GATE_LATENCY : 1;
		unsigned int          TXCLK_DYN_GATE_LATENCY : 1;
		unsigned int         TXCLK_PERM_GATE_LATENCY : 1;
		unsigned int         TXCLK_REGS_GATE_LATENCY : 1;
		unsigned int        REFCLK_REGS_GATE_LATENCY : 1;
		unsigned int            LCLK_GATE_TXCLK_FREE : 1;
		unsigned int             RCVR_DET_CLK_ENABLE : 1;
		unsigned int         TXCLK_PERM_GATE_PLL_PDN : 1;
		unsigned int              FAST_TXCLK_LATENCY : 3;
		unsigned int          MASTER_PCIE_PLL_SELECT : 1;
		unsigned int            MASTER_PCIE_PLL_AUTO : 1;
		unsigned int            REFCLK_XSTCLK_ENABLE : 1;
		unsigned int           REFCLK_XSTCLK_LATENCY : 1;
		unsigned int                      SPARE_REGS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_COMPLETION_STATUS__VI {
	struct {
		unsigned int                          STATUS : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_METADATA_BASE_ADDR__VI {
	struct {
		unsigned int                         ADDR_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_METADATA_BASE_ADDR_HI__VI {
	struct {
		unsigned int                         ADDR_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CE_RB_OFFSET__VI {
	struct {
		unsigned int                       RB_OFFSET : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_IC_BASE_CNTL__VI {
	struct {
		unsigned int                            VMID : 4;
		unsigned int                                 : 19;
		unsigned int                             ATC : 1;
		unsigned int                    CACHE_POLICY : 1;
		unsigned int                                 : 2;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_IC_BASE_HI__VI {
	struct {
		unsigned int                      IC_BASE_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_IC_BASE_LO__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                      IC_BASE_LO : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_IC_OP_CNTL__VI {
	struct {
		unsigned int                INVALIDATE_CACHE : 1;
		unsigned int                                 : 3;
		unsigned int                    PRIME_ICACHE : 1;
		unsigned int                   ICACHE_PRIMED : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_CPC_MGCG_SYNC_CNTL__VI {
	struct {
		unsigned int                 COOLDOWN_PERIOD : 8;
		unsigned int                   WARMUP_PERIOD : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DFY_CMD__VI {
	struct {
		unsigned int                          OFFSET : 9;
		unsigned int                                 : 7;
		unsigned int                            SIZE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DISPATCH_INDR_ADDR__VI {
	struct {
		unsigned int                         ADDR_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DISPATCH_INDR_ADDR_HI__VI {
	struct {
		unsigned int                         ADDR_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DRAW_INDX_INDR_ADDR__VI {
	struct {
		unsigned int                         ADDR_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DRAW_INDX_INDR_ADDR_HI__VI {
	struct {
		unsigned int                         ADDR_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DRAW_OBJECT__VI {
	struct {
		unsigned int                          OBJECT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DRAW_OBJECT_COUNTER__VI {
	struct {
		unsigned int                           COUNT : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DRAW_WINDOW_CNTL__VI {
	struct {
		unsigned int      DISABLE_DRAW_WINDOW_LO_MAX : 1;
		unsigned int      DISABLE_DRAW_WINDOW_LO_MIN : 1;
		unsigned int          DISABLE_DRAW_WINDOW_HI : 1;
		unsigned int                                 : 5;
		unsigned int                            MODE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DRAW_WINDOW_HI__VI {
	struct {
		unsigned int                       WINDOW_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DRAW_WINDOW_LO__VI {
	struct {
		unsigned int                             MIN : 16;
		unsigned int                             MAX : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_DRAW_WINDOW_MASK_HI__VI {
	struct {
		unsigned int                  WINDOW_MASK_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_EOP_DONE_CNTX_ID__VI {
	struct {
		unsigned int                         CNTX_ID : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_GDS_BKUP_ADDR__VI {
	struct {
		unsigned int                         ADDR_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_GDS_BKUP_ADDR_HI__VI {
	struct {
		unsigned int                         ADDR_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HPD_STATUS0__VI {
	struct {
		unsigned int                     QUEUE_STATE : 5;
		unsigned int                    MAPPED_QUEUE : 3;
		unsigned int                 QUEUE_AVAILABLE : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_CNTL_STACK_OFFSET__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                          OFFSET : 13;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_CNTL_STACK_SIZE__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                            SIZE : 3;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_CTX_SAVE_BASE_ADDR_HI__VI {
	struct {
		unsigned int                         ADDR_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_CTX_SAVE_BASE_ADDR_LO__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                            ADDR : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_CTX_SAVE_CONTROL__VI {
	struct {
		unsigned int                             ATC : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                          POLICY : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_CTX_SAVE_SIZE__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                            SIZE : 13;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_EOP_BASE_ADDR__VI {
	struct {
		unsigned int                       BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_EOP_BASE_ADDR_HI__VI {
	struct {
		unsigned int                    BASE_ADDR_HI : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_EOP_CONTROL__VI {
	struct {
		unsigned int                        EOP_SIZE : 6;
		unsigned int                                 : 2;
		unsigned int                  PROCESSING_EOP : 1;
		unsigned int                                 : 3;
		unsigned int                  PROCESS_EOP_EN : 1;
		unsigned int                PROCESSING_EOPIB : 1;
		unsigned int                PROCESS_EOPIB_EN : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 6;
		unsigned int                         EOP_ATC : 1;
		unsigned int                    CACHE_POLICY : 1;
		unsigned int                                 : 4;
		unsigned int                  SIG_SEM_RESULT : 2;
		unsigned int                    PEND_SIG_SEM : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_EOP_DONES__VI {
	struct {
		unsigned int                      DONE_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_EOP_EVENTS__VI {
	struct {
		unsigned int                     EVENT_COUNT : 12;
		unsigned int                                 : 4;
		unsigned int           CS_PARTIAL_FLUSH_PEND : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_EOP_RPTR__VI {
	struct {
		unsigned int                            RPTR : 13;
		unsigned int                                 : 17;
		unsigned int               RPTR_EQ_CSMD_WPTR : 1;
		unsigned int                    INIT_FETCHER : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_EOP_WPTR__VI {
	struct {
		unsigned int                            WPTR : 13;
		unsigned int                                 : 3;
		unsigned int                       EOP_AVAIL : 13;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_EOP_WPTR_MEM__VI {
	struct {
		unsigned int                            WPTR : 13;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_ERROR__VI {
	struct {
		unsigned int                    EDC_ERROR_ID : 4;
		unsigned int                       SUA_ERROR : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_GDS_RESOURCE_STATE__VI {
	struct {
		unsigned int                     OA_REQUIRED : 1;
		unsigned int                     OA_ACQUIRED : 1;
		unsigned int                                 : 2;
		unsigned int                        GWS_SIZE : 6;
		unsigned int                                 : 2;
		unsigned int                        GWS_PNTR : 6;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_HQ_CONTROL0__VI {
	struct {
		unsigned int                         CONTROL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_HQ_CONTROL1__VI {
	struct {
		unsigned int                         CONTROL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_HQ_STATUS0__VI {
	struct {
		unsigned int                  DEQUEUE_STATUS : 2;
		unsigned int               DEQUEUE_RETRY_CNT : 2;
		unsigned int                         RSV_6_4 : 3;
		unsigned int                SCRATCH_RAM_INIT : 1;
		unsigned int                      TCL2_DIRTY : 1;
		unsigned int                    PG_ACTIVATED : 1;
		unsigned int                      RSVR_31_10 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_HQ_STATUS1__VI {
	struct {
		unsigned int                          STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_OFFLOAD__VI {
	struct {
		unsigned int                     DMA_OFFLOAD : 1;
		unsigned int                  DMA_OFFLOAD_EN : 1;
		unsigned int                                 : 2;
		unsigned int                     EOP_OFFLOAD : 1;
		unsigned int                  EOP_OFFLOAD_EN : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_HQD_WG_STATE_OFFSET__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                          OFFSET : 23;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INDEX_BASE_ADDR__VI {
	struct {
		unsigned int                         ADDR_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INDEX_BASE_ADDR_HI__VI {
	struct {
		unsigned int                         ADDR_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_INDEX_TYPE__VI {
	struct {
		unsigned int                      INDEX_TYPE : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC1_F32_INT_DIS__VI {
	struct {
		unsigned int                 EDC_ROQ_FED_INT : 1;
		unsigned int                    PRIV_REG_INT : 1;
		unsigned int            RESERVED_BIT_ERR_INT : 1;
		unsigned int                  EDC_TC_FED_INT : 1;
		unsigned int                 EDC_GDS_FED_INT : 1;
		unsigned int             EDC_SCRATCH_FED_INT : 1;
		unsigned int                WAVE_RESTORE_INT : 1;
		unsigned int               SUA_VIOLATION_INT : 1;
		unsigned int                 EDC_DMA_FED_INT : 1;
		unsigned int                    IQ_TIMER_INT : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC2_F32_INT_DIS__VI {
	struct {
		unsigned int                 EDC_ROQ_FED_INT : 1;
		unsigned int                    PRIV_REG_INT : 1;
		unsigned int            RESERVED_BIT_ERR_INT : 1;
		unsigned int                  EDC_TC_FED_INT : 1;
		unsigned int                 EDC_GDS_FED_INT : 1;
		unsigned int             EDC_SCRATCH_FED_INT : 1;
		unsigned int                WAVE_RESTORE_INT : 1;
		unsigned int               SUA_VIOLATION_INT : 1;
		unsigned int                 EDC_DMA_FED_INT : 1;
		unsigned int                    IQ_TIMER_INT : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC_DOORBELL_RANGE_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int            DOORBELL_RANGE_LOWER : 21;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_MEC_DOORBELL_RANGE_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int            DOORBELL_RANGE_UPPER : 21;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_COMPLETION_STATUS__VI {
	struct {
		unsigned int                          STATUS : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_METADATA_BASE_ADDR__VI {
	struct {
		unsigned int                         ADDR_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PFP_METADATA_BASE_ADDR_HI__VI {
	struct {
		unsigned int                         ADDR_HI : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PIPE_STATS_CONTROL__VI {
	struct {
		unsigned int                                 : 25;
		unsigned int                   CACHE_CONTROL : 1;
		unsigned int                                 : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PQ_STATUS__VI {
	struct {
		unsigned int                DOORBELL_UPDATED : 1;
		unsigned int                 DOORBELL_ENABLE : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_PRED_NOT_VISIBLE__VI {
	struct {
		unsigned int                     NOT_VISIBLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_DOORBELL_CONTROL__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                 DOORBELL_OFFSET : 21;
		unsigned int                                 : 7;
		unsigned int                     DOORBELL_EN : 1;
		unsigned int                    DOORBELL_HIT : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_DOORBELL_RANGE_LOWER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int            DOORBELL_RANGE_LOWER : 21;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_RB_DOORBELL_RANGE_UPPER__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int            DOORBELL_RANGE_UPPER : 21;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_SAMPLE_STATUS__VI {
	struct {
		unsigned int                   Z_PASS_ACITVE : 1;
		unsigned int                STREAMOUT_ACTIVE : 1;
		unsigned int                 PIPELINE_ACTIVE : 1;
		unsigned int                  STIPPLE_ACTIVE : 1;
		unsigned int              VGT_BUFFERS_ACTIVE : 1;
		unsigned int               SCREEN_EXT_ACTIVE : 1;
		unsigned int            DRAW_INDIRECT_ACTIVE : 1;
		unsigned int            DISP_INDIRECT_ACTIVE : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_STREAM_OUT_CONTROL__VI {
	struct {
		unsigned int                                 : 25;
		unsigned int                   CACHE_CONTROL : 1;
		unsigned int                                 : 1;
		unsigned int                           MTYPE : 2;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VIRT_STATUS__VI {
	struct {
		unsigned int                     VIRT_STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CP_VMID_STATUS__VI {
	struct {
		unsigned int               PREEMPT_DE_STATUS : 16;
		unsigned int               PREEMPT_CE_STATUS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_3D_STRUCTURE_CONTROL__VI {
	struct {
		unsigned int            CRTC_3D_STRUCTURE_EN : 1;
		unsigned int                                 : 3;
		unsigned int         CRTC_3D_STRUCTURE_EN_DB : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_3D_STRUCTURE_V_UPDATE_MODE : 2;
		unsigned int                                 : 2;
		unsigned int CRTC_3D_STRUCTURE_STEREO_SEL_OVR : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_3D_STRUCTURE_F_COUNT_RESET : 1;
		unsigned int CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING : 1;
		unsigned int       CRTC_3D_STRUCTURE_F_COUNT : 2;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_AVSYNC_COUNTER__VI {
	struct {
		unsigned int             CRTC_AVSYNC_COUNTER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_BLACK_COLOR_EXT__VI {
	struct {
		unsigned int       CRTC_BLACK_COLOR_B_CB_EXT : 2;
		unsigned int                                 : 6;
		unsigned int        CRTC_BLACK_COLOR_G_Y_EXT : 2;
		unsigned int                                 : 6;
		unsigned int       CRTC_BLACK_COLOR_R_CR_EXT : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_BLANK_DATA_COLOR_EXT__VI {
	struct {
		unsigned int CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT : 2;
		unsigned int                                 : 6;
		unsigned int CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT : 2;
		unsigned int                                 : 6;
		unsigned int CRTC_BLANK_DATA_COLOR_RED_CR_EXT : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC0_DATA_B__VI {
	struct {
		unsigned int                       CRC0_B_CB : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC0_DATA_RG__VI {
	struct {
		unsigned int                       CRC0_R_CR : 16;
		unsigned int                        CRC0_G_Y : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC0_WINDOWA_X_CONTROL__VI {
	struct {
		unsigned int       CRTC_CRC0_WINDOWA_X_START : 14;
		unsigned int                                 : 2;
		unsigned int         CRTC_CRC0_WINDOWA_X_END : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC0_WINDOWA_Y_CONTROL__VI {
	struct {
		unsigned int       CRTC_CRC0_WINDOWA_Y_START : 14;
		unsigned int                                 : 2;
		unsigned int         CRTC_CRC0_WINDOWA_Y_END : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC0_WINDOWB_X_CONTROL__VI {
	struct {
		unsigned int       CRTC_CRC0_WINDOWB_X_START : 14;
		unsigned int                                 : 2;
		unsigned int         CRTC_CRC0_WINDOWB_X_END : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC0_WINDOWB_Y_CONTROL__VI {
	struct {
		unsigned int       CRTC_CRC0_WINDOWB_Y_START : 14;
		unsigned int                                 : 2;
		unsigned int         CRTC_CRC0_WINDOWB_Y_END : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC1_DATA_B__VI {
	struct {
		unsigned int                       CRC1_B_CB : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC1_DATA_RG__VI {
	struct {
		unsigned int                       CRC1_R_CR : 16;
		unsigned int                        CRC1_G_Y : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC1_WINDOWA_X_CONTROL__VI {
	struct {
		unsigned int       CRTC_CRC1_WINDOWA_X_START : 14;
		unsigned int                                 : 2;
		unsigned int         CRTC_CRC1_WINDOWA_X_END : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC1_WINDOWA_Y_CONTROL__VI {
	struct {
		unsigned int       CRTC_CRC1_WINDOWA_Y_START : 14;
		unsigned int                                 : 2;
		unsigned int         CRTC_CRC1_WINDOWA_Y_END : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC1_WINDOWB_X_CONTROL__VI {
	struct {
		unsigned int       CRTC_CRC1_WINDOWB_X_START : 14;
		unsigned int                                 : 2;
		unsigned int         CRTC_CRC1_WINDOWB_X_END : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC1_WINDOWB_Y_CONTROL__VI {
	struct {
		unsigned int       CRTC_CRC1_WINDOWB_Y_START : 14;
		unsigned int                                 : 2;
		unsigned int         CRTC_CRC1_WINDOWB_Y_END : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_CRC_CNTL__VI {
	struct {
		unsigned int                     CRTC_CRC_EN : 1;
		unsigned int                                 : 3;
		unsigned int                CRTC_CRC_CONT_EN : 1;
		unsigned int                                 : 3;
		unsigned int            CRTC_CRC_STEREO_MODE : 2;
		unsigned int                                 : 2;
		unsigned int         CRTC_CRC_INTERLACE_MODE : 2;
		unsigned int                                 : 2;
		unsigned int CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS : 1;
		unsigned int                                 : 3;
		unsigned int                CRTC_CRC0_SELECT : 3;
		unsigned int                                 : 1;
		unsigned int                CRTC_CRC1_SELECT : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_DCFE_CLOCK_CONTROL__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int CRTC_DISPCLK_R_DCFE_GATE_DISABLE : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_DISPCLK_G_DCP_GATE_DISABLE : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_DISPCLK_G_SCL_GATE_DISABLE : 1;
		unsigned int                                 : 11;
		unsigned int          CRTC_DCFE_TEST_CLK_SEL : 5;
		unsigned int                                 : 2;
		unsigned int          CRTC_DCFE_CLOCK_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_EXT_TIMING_SYNC_CONTROL__VI {
	struct {
		unsigned int     CRTC_EXT_TIMING_SYNC_ENABLE : 2;
		unsigned int                                 : 1;
		unsigned int CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE : 1;
		unsigned int CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE : 1;
		unsigned int CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW : 2;
		unsigned int                                 : 1;
		unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE : 1;
		unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE : 1;
		unsigned int                                 : 2;
		unsigned int CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY : 1;
		unsigned int CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY : 1;
		unsigned int CRTC_EXT_TIMING_SYNC_INTERLACE_MODE : 1;
		unsigned int                                 : 9;
		unsigned int CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE : 3;
		unsigned int                                 : 1;
		unsigned int CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI {
	struct {
		unsigned int CRTC_EXT_TIMING_SYNC_INT_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int     CRTC_EXT_TIMING_SYNC_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_EXT_TIMING_SYNC_INT_STATUS : 1;
		unsigned int                                 : 7;
		unsigned int      CRTC_EXT_TIMING_SYNC_CLEAR : 1;
		unsigned int                                 : 3;
		unsigned int   CRTC_EXT_TIMING_SYNC_INT_TYPE : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI {
	struct {
		unsigned int CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_EXT_TIMING_SYNC_LOSS_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS : 1;
		unsigned int                                 : 7;
		unsigned int CRTC_EXT_TIMING_SYNC_LOSS_CLEAR : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE : 1;
		unsigned int                                 : 8;
		unsigned int CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI {
	struct {
		unsigned int CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS : 1;
		unsigned int                                 : 7;
		unsigned int CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_EXT_TIMING_SYNC_WINDOW_END__VI {
	struct {
		unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_END_X : 14;
		unsigned int                                 : 2;
		unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_END_Y : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_EXT_TIMING_SYNC_WINDOW_START__VI {
	struct {
		unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_START_X : 14;
		unsigned int                                 : 2;
		unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_START_Y : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_FIELD_INDICATION_CONTROL__VI {
	struct {
		unsigned int CRTC_FIELD_INDICATION_OUTPUT_POLARITY : 1;
		unsigned int            CRTC_FIELD_ALIGNMENT : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_GSL_CONTROL__VI {
	struct {
		unsigned int         CRTC_GSL_CHECK_LINE_NUM : 14;
		unsigned int                                 : 2;
		unsigned int            CRTC_GSL_FORCE_DELAY : 5;
		unsigned int                                 : 7;
		unsigned int       CRTC_GSL_CHECK_ALL_FIELDS : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_GSL_VSYNC_GAP__VI {
	struct {
		unsigned int        CRTC_GSL_VSYNC_GAP_LIMIT : 8;
		unsigned int        CRTC_GSL_VSYNC_GAP_DELAY : 8;
		unsigned int   CRTC_GSL_VSYNC_GAP_SOURCE_SEL : 1;
		unsigned int         CRTC_GSL_VSYNC_GAP_MODE : 2;
		unsigned int        CRTC_GSL_VSYNC_GAP_CLEAR : 1;
		unsigned int     CRTC_GSL_VSYNC_GAP_OCCURRED : 1;
		unsigned int                                 : 2;
		unsigned int CRTC_GSL_VSYNC_GAP_MASTER_FASTER : 1;
		unsigned int              CRTC_GSL_VSYNC_GAP : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_GSL_WINDOW__VI {
	struct {
		unsigned int           CRTC_GSL_WINDOW_START : 14;
		unsigned int                                 : 2;
		unsigned int             CRTC_GSL_WINDOW_END : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_H_BLANK_EARLY_NUM__VI {
	struct {
		unsigned int          CRTC_H_BLANK_EARLY_NUM : 10;
		unsigned int                                 : 6;
		unsigned int      CRTC_H_BLANK_EARLY_NUM_DIS : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_OVERSCAN_COLOR_EXT__VI {
	struct {
		unsigned int    CRTC_OVERSCAN_COLOR_BLUE_EXT : 2;
		unsigned int                                 : 6;
		unsigned int   CRTC_OVERSCAN_COLOR_GREEN_EXT : 2;
		unsigned int                                 : 6;
		unsigned int     CRTC_OVERSCAN_COLOR_RED_EXT : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_PIXEL_DATA_READBACK0__VI {
	struct {
		unsigned int         CRTC_PIXEL_DATA_BLUE_CB : 12;
		unsigned int                                 : 4;
		unsigned int         CRTC_PIXEL_DATA_GREEN_Y : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_PIXEL_DATA_READBACK1__VI {
	struct {
		unsigned int          CRTC_PIXEL_DATA_RED_CR : 12;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_STATIC_SCREEN_CONTROL__VI {
	struct {
		unsigned int   CRTC_STATIC_SCREEN_EVENT_MASK : 16;
		unsigned int  CRTC_STATIC_SCREEN_FRAME_COUNT : 8;
		unsigned int          CRTC_CPU_SS_INT_ENABLE : 1;
		unsigned int                  CRTC_SS_STATUS : 1;
		unsigned int          CRTC_CPU_SS_INT_STATUS : 1;
		unsigned int           CRTC_CPU_SS_INT_CLEAR : 1;
		unsigned int            CRTC_CPU_SS_INT_TYPE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_VERTICAL_INTERRUPT0_CONTROL__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_VERTICAL_INTERRUPT0_INT_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_VERTICAL_INTERRUPT0_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_VERTICAL_INTERRUPT0_INT_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int  CRTC_VERTICAL_INTERRUPT0_CLEAR : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_VERTICAL_INTERRUPT0_INT_TYPE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_VERTICAL_INTERRUPT0_POSITION__VI {
	struct {
		unsigned int CRTC_VERTICAL_INTERRUPT0_LINE_START : 14;
		unsigned int                                 : 2;
		unsigned int CRTC_VERTICAL_INTERRUPT0_LINE_END : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_VERTICAL_INTERRUPT1_CONTROL__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int CRTC_VERTICAL_INTERRUPT1_INT_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_VERTICAL_INTERRUPT1_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_VERTICAL_INTERRUPT1_INT_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int  CRTC_VERTICAL_INTERRUPT1_CLEAR : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_VERTICAL_INTERRUPT1_INT_TYPE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_VERTICAL_INTERRUPT1_POSITION__VI {
	struct {
		unsigned int CRTC_VERTICAL_INTERRUPT1_LINE_START : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_VERTICAL_INTERRUPT2_CONTROL__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int CRTC_VERTICAL_INTERRUPT2_INT_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_VERTICAL_INTERRUPT2_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_VERTICAL_INTERRUPT2_INT_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int  CRTC_VERTICAL_INTERRUPT2_CLEAR : 1;
		unsigned int                                 : 3;
		unsigned int CRTC_VERTICAL_INTERRUPT2_INT_TYPE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CRTC_VERTICAL_INTERRUPT2_POSITION__VI {
	struct {
		unsigned int CRTC_VERTICAL_INTERRUPT2_LINE_START : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR2_COLOR1__VI {
	struct {
		unsigned int                CUR2_COLOR1_BLUE : 8;
		unsigned int               CUR2_COLOR1_GREEN : 8;
		unsigned int                 CUR2_COLOR1_RED : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR2_COLOR2__VI {
	struct {
		unsigned int                CUR2_COLOR2_BLUE : 8;
		unsigned int               CUR2_COLOR2_GREEN : 8;
		unsigned int                 CUR2_COLOR2_RED : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR2_CONTROL__VI {
	struct {
		unsigned int                      CURSOR2_EN : 1;
		unsigned int                                 : 3;
		unsigned int            CUR2_INV_TRANS_CLAMP : 1;
		unsigned int                                 : 3;
		unsigned int                    CURSOR2_MODE : 2;
		unsigned int                                 : 6;
		unsigned int              CURSOR2_2X_MAGNIFY : 1;
		unsigned int                                 : 3;
		unsigned int             CURSOR2_FORCE_MC_ON : 1;
		unsigned int                                 : 3;
		unsigned int          CURSOR2_URGENT_CONTROL : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR2_HOT_SPOT__VI {
	struct {
		unsigned int              CURSOR2_HOT_SPOT_Y : 7;
		unsigned int                                 : 9;
		unsigned int              CURSOR2_HOT_SPOT_X : 7;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR2_POSITION__VI {
	struct {
		unsigned int              CURSOR2_Y_POSITION : 14;
		unsigned int                                 : 2;
		unsigned int              CURSOR2_X_POSITION : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR2_SIZE__VI {
	struct {
		unsigned int                  CURSOR2_HEIGHT : 7;
		unsigned int                                 : 9;
		unsigned int                   CURSOR2_WIDTH : 7;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR2_STEREO_CONTROL__VI {
	struct {
		unsigned int               CURSOR2_STEREO_EN : 1;
		unsigned int       CURSOR2_STEREO_OFFSET_YNX : 1;
		unsigned int                                 : 2;
		unsigned int          CURSOR2_PRIMARY_OFFSET : 10;
		unsigned int                                 : 2;
		unsigned int        CURSOR2_SECONDARY_OFFSET : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR2_SURFACE_ADDRESS__VI {
	struct {
		unsigned int         CURSOR2_SURFACE_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR2_SURFACE_ADDRESS_HIGH__VI {
	struct {
		unsigned int    CURSOR2_SURFACE_ADDRESS_HIGH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR2_UPDATE__VI {
	struct {
		unsigned int          CURSOR2_UPDATE_PENDING : 1;
		unsigned int            CURSOR2_UPDATE_TAKEN : 1;
		unsigned int                                 : 14;
		unsigned int             CURSOR2_UPDATE_LOCK : 1;
		unsigned int                                 : 7;
		unsigned int CURSOR2_DISABLE_MULTIPLE_UPDATE : 1;
		unsigned int      CURSOR2_UPDATE_STEREO_MODE : 2;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_REQUEST_FILTER_CNTL__VI {
	struct {
		unsigned int          CUR_REQUEST_FILTER_DIS : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union CUR_STEREO_CONTROL__VI {
	struct {
		unsigned int                CURSOR_STEREO_EN : 1;
		unsigned int        CURSOR_STEREO_OFFSET_YNX : 1;
		unsigned int                                 : 2;
		unsigned int           CURSOR_PRIMARY_OFFSET : 10;
		unsigned int                                 : 2;
		unsigned int         CURSOR_SECONDARY_OFFSET : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_CLK_ENABLE__VI {
	struct {
		unsigned int                 DACA_CLK_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int                 DACB_CLK_ENABLE : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_FIFO_STATUS__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int    DAC_FIFO_USE_OVERWRITE_LEVEL : 1;
		unsigned int        DAC_FIFO_OVERWRITE_LEVEL : 6;
		unsigned int                                 : 2;
		unsigned int      DAC_FIFO_CAL_AVERAGE_LEVEL : 6;
		unsigned int          DAC_FIFO_MAXIMUM_LEVEL : 4;
		unsigned int                                 : 2;
		unsigned int          DAC_FIFO_MINIMUM_LEVEL : 4;
		unsigned int                                 : 3;
		unsigned int             DAC_FIFO_CALIBRATED : 1;
		unsigned int    DAC_FIFO_FORCE_RECAL_AVERAGE : 1;
		unsigned int    DAC_FIFO_FORCE_RECOMP_MINMAX : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_MACRO_CNTL_RESERVED0__VI {
	struct {
		unsigned int         DAC_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_MACRO_CNTL_RESERVED1__VI {
	struct {
		unsigned int         DAC_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_MACRO_CNTL_RESERVED2__VI {
	struct {
		unsigned int         DAC_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_MACRO_CNTL_RESERVED3__VI {
	struct {
		unsigned int         DAC_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int             DAC_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DAC_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int            DAC_TEST_DEBUG_INDEX : 8;
		unsigned int         DAC_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DBG_OUT_CNTL__VI {
	struct {
		unsigned int                  DBG_OUT_PIN_EN : 1;
		unsigned int                                 : 3;
		unsigned int                 DBG_OUT_PIN_SEL : 1;
		unsigned int                                 : 3;
		unsigned int               DBG_OUT_12BIT_SEL : 2;
		unsigned int                                 : 2;
		unsigned int               DBG_OUT_TEST_DATA : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DBG_SMB_BYPASS_SRBM_ACCESS__VI {
	struct {
                unsigned int          DBG_SMB_BYPASS_SRBM_EN : 1;
                unsigned int                                 : 4;
                unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_AUDIO_DTO1_MODULE__VI {
	struct {
		unsigned int          DCCG_AUDIO_DTO1_MODULE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_AUDIO_DTO1_PHASE__VI {
	struct {
		unsigned int           DCCG_AUDIO_DTO1_PHASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_AUDIO_DTO_SOURCE__VI {
	struct {
		unsigned int      DCCG_AUDIO_DTO0_SOURCE_SEL : 3;
		unsigned int                                 : 1;
		unsigned int              DCCG_AUDIO_DTO_SEL : 2;
		unsigned int                                 : 6;
		unsigned int      DCCG_AUDIO_DTO2_SOURCE_SEL : 2;
		unsigned int                                 : 2;
		unsigned int        DCCG_AUDIO_DTO2_CLOCK_EN : 1;
		unsigned int                                 : 3;
		unsigned int  DCCG_AUDIO_DTO2_USE_512FBR_DTO : 1;
		unsigned int                                 : 3;
		unsigned int  DCCG_AUDIO_DTO0_USE_512FBR_DTO : 1;
		unsigned int                                 : 3;
		unsigned int  DCCG_AUDIO_DTO1_USE_512FBR_DTO : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_CAC_STATUS__VI {
	struct {
		unsigned int               CAC_STATUS_RDDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_CBUS_WRCMD_DELAY__VI {
	struct {
		unsigned int            CBUS_PLL_WRCMD_DELAY : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_DISP_CNTL_REG__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int           ALLOW_SR_ON_TRANS_REQ : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_DS_CNTL__VI {
	struct {
		unsigned int                  DCCG_DS_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int           DCCG_DS_HW_CAL_ENABLE : 1;
		unsigned int          DCCG_DS_ENABLED_STATUS : 1;
		unsigned int                                 : 6;
		unsigned int         DCCG_DS_XTALIN_RATE_DIV : 2;
		unsigned int                                 : 6;
		unsigned int       DCCG_DS_JITTER_REMOVE_DIS : 1;
		unsigned int          DCCG_DS_DELAY_XTAL_SEL : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_DS_DEBUG_CNTL__VI {
	struct {
		unsigned int      DCCG_DS_DEBUG_COUNT_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int  DCCG_DS_DEBUG_COUNT_TRIG_VALUE : 9;
		unsigned int                                 : 3;
		unsigned int DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED : 1;
		unsigned int  DCCG_DS_DEBUG_COUNT_TRIG_CLEAR : 1;
		unsigned int                                 : 2;
		unsigned int     DCCG_DS_JITTER_COUNT_ENABLE : 1;
		unsigned int    DCCG_DS_JITTER_COUNT_SRC_SEL : 1;
		unsigned int                                 : 2;
		unsigned int            DCCG_DS_JITTER_COUNT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_DS_DTO_INCR__VI {
	struct {
		unsigned int                DCCG_DS_DTO_INCR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_DS_DTO_MODULO__VI {
	struct {
		unsigned int              DCCG_DS_DTO_MODULO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_DS_HW_CAL_INTERVAL__VI {
	struct {
		unsigned int         DCCG_DS_HW_CAL_INTERVAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_GTC_CNTL__VI {
	struct {
		unsigned int                 DCCG_GTC_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_GTC_CURRENT__VI {
	struct {
		unsigned int                DCCG_GTC_CURRENT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_GTC_DTO_INCR__VI {
	struct {
		unsigned int               DCCG_GTC_DTO_INCR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_GTC_DTO_MODULO__VI {
	struct {
		unsigned int             DCCG_GTC_DTO_MODULO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_PERFMON_CNTL__VI {
	struct {
		unsigned int        DCCG_PERF_DISPCLK_ENABLE : 1;
		unsigned int       DCCG_PERF_DPREFCLK_ENABLE : 1;
		unsigned int        DCCG_PERF_PIXCLK1_ENABLE : 1;
		unsigned int        DCCG_PERF_PIXCLK2_ENABLE : 1;
		unsigned int        DCCG_PERF_PIXCLK0_ENABLE : 1;
		unsigned int                   DCCG_PERF_RUN : 1;
		unsigned int            DCCG_PERF_MODE_VSYNC : 1;
		unsigned int            DCCG_PERF_MODE_HSYNC : 1;
		unsigned int              DCCG_PERF_CRTC_SEL : 3;
		unsigned int      DCCG_PERF_XTALIN_PULSE_DIV : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_PERFMON_CNTL2__VI {
	struct {
		unsigned int         DCCG_PERF_DSICLK_ENABLE : 1;
		unsigned int         DCCG_PERF_REFCLK_ENABLE : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCCG_SOFT_RESET__VI {
	struct {
		unsigned int               REFCLK_SOFT_RESET : 1;
		unsigned int          PCIE_REFCLK_SOFT_RESET : 1;
		unsigned int                  SOFT_RESET_DVO : 1;
		unsigned int                  DVO_ENABLE_RST : 1;
		unsigned int       AUDIO_DTO2_CLK_SOFT_RESET : 1;
		unsigned int                                 : 3;
		unsigned int             DPREFCLK_SOFT_RESET : 1;
		unsigned int                                 : 3;
		unsigned int               AMCLK0_SOFT_RESET : 1;
		unsigned int               AMCLK1_SOFT_RESET : 1;
		unsigned int         P0PLL_CFG_IF_SOFT_RESET : 1;
		unsigned int         P1PLL_CFG_IF_SOFT_RESET : 1;
		unsigned int         P2PLL_CFG_IF_SOFT_RESET : 1;
		unsigned int         A0PLL_CFG_IF_SOFT_RESET : 1;
		unsigned int         A1PLL_CFG_IF_SOFT_RESET : 1;
		unsigned int         C0PLL_CFG_IF_SOFT_RESET : 1;
		unsigned int         C1PLL_CFG_IF_SOFT_RESET : 1;
		unsigned int         C2PLL_CFG_IF_SOFT_RESET : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCDEBUG_BUS_CLK5_SEL__VI {
	struct {
		unsigned int            DCDEBUG_BUS_CLK5_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCDEBUG_OUT_DATA__VI {
	struct {
		unsigned int                DCDEBUG_OUT_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCE_VCE_CONTROL__VI {
	struct {
		unsigned int        DC_VCE_VIDEO_PIPE_SELECT : 3;
		unsigned int                                 : 1;
		unsigned int      DC_VCE_AUDIO_STREAM_SELECT : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFEV0_CRTC_PIXEL_RATE_CNTL__VI {
	struct {
		unsigned int   DCFEV0_CRTC_PIXEL_RATE_SOURCE : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFEV0_PG_CONFIG__VI {
	struct {
		unsigned int            DCFEV0_POWER_FORCEON : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFEV0_PG_ENABLE__VI {
	struct {
		unsigned int               DCFEV0_POWER_GATE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFEV0_PG_STATUS__VI {
	struct {
		unsigned int          DCFEV0_PGFSM_READ_DATA : 24;
		unsigned int         DCFEV0_DEBUG_PWR_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int        DCFEV0_DESIRED_PWR_STATE : 1;
		unsigned int      DCFEV0_REQUESTED_PWR_STATE : 1;
		unsigned int         DCFEV0_PGFSM_PWR_STATUS : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFEV_CLOCK_CONTROL__VI {
	struct {
		unsigned int                                 : 3;
		unsigned int    DISPCLK_R_DCFEV_GATE_DISABLE : 1;
		unsigned int                                 : 3;
		unsigned int      DISPCLK_G_UNP_GATE_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int     DISPCLK_G_SCLV_GATE_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int  DISPCLK_G_COL_MAN_GATE_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int    DISPCLK_G_PSCLV_GATE_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int     DISPCLK_G_CRTC_GATE_DISABLE : 1;
		unsigned int                                 : 8;
		unsigned int              DCFEV_TEST_CLK_SEL : 5;
		unsigned int                                 : 2;
		unsigned int              DCFEV_CLOCK_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFEV_DBG_CONFIG__VI {
	struct {
		unsigned int                    DCFEV_DBG_EN : 1;
		unsigned int                                 : 3;
		unsigned int                   DCFEV_DBG_SEL : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFEV_DMIFV_CLOCK_CONTROL__VI {
	struct {
		unsigned int                                 : 3;
		unsigned int   DMIFV_SCLK_G_DMIFTRK_GATE_DIS : 1;
		unsigned int DMIFV_DISPCLK_G_DMIFVL_GATE_DIS : 1;
		unsigned int DMIFV_DISPCLK_G_DMIFVC_GATE_DIS : 1;
		unsigned int                DMIFV_SOFT_RESET : 1;
		unsigned int                                 : 17;
		unsigned int              DMIFV_TEST_CLK_SEL : 5;
		unsigned int                                 : 2;
		unsigned int               DMIFV_BUFFER_MODE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFEV_DMIFV_MEM_PWR_CTRL__VI {
	struct {
		unsigned int               DMIFV_MEM_PWR_SEL : 2;
		unsigned int      DMIFV_MEM_PWR_LUMA_0_FORCE : 1;
		unsigned int      DMIFV_MEM_PWR_LUMA_1_FORCE : 1;
		unsigned int      DMIFV_MEM_PWR_LUMA_2_FORCE : 1;
		unsigned int      DMIFV_MEM_PWR_LUMA_3_FORCE : 1;
		unsigned int      DMIFV_MEM_PWR_LUMA_4_FORCE : 1;
		unsigned int    DMIFV_MEM_PWR_CHROMA_0_FORCE : 1;
		unsigned int    DMIFV_MEM_PWR_CHROMA_1_FORCE : 1;
		unsigned int    DMIFV_MEM_PWR_CHROMA_2_FORCE : 1;
		unsigned int    DMIFV_MEM_PWR_CHROMA_3_FORCE : 1;
		unsigned int    DMIFV_MEM_PWR_CHROMA_4_FORCE : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFEV_DMIFV_MEM_PWR_STATUS__VI {
	struct {
		unsigned int      DMIFV_MEM_PWR_LUMA_0_STATE : 2;
		unsigned int      DMIFV_MEM_PWR_LUMA_1_STATE : 2;
		unsigned int      DMIFV_MEM_PWR_LUMA_2_STATE : 2;
		unsigned int      DMIFV_MEM_PWR_LUMA_3_STATE : 2;
		unsigned int      DMIFV_MEM_PWR_LUMA_4_STATE : 2;
		unsigned int    DMIFV_MEM_PWR_CHROMA_0_STATE : 2;
		unsigned int    DMIFV_MEM_PWR_CHROMA_1_STATE : 2;
		unsigned int    DMIFV_MEM_PWR_CHROMA_2_STATE : 2;
		unsigned int    DMIFV_MEM_PWR_CHROMA_3_STATE : 2;
		unsigned int    DMIFV_MEM_PWR_CHROMA_4_STATE : 2;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFEV_SOFT_RESET__VI {
	struct {
		unsigned int          UNP_PIXPIPE_SOFT_RESET : 1;
		unsigned int              UNP_REQ_SOFT_RESET : 1;
		unsigned int             SCLV_ALU_SOFT_RESET : 1;
		unsigned int                 SCLV_SOFT_RESET : 1;
		unsigned int                 CRTC_SOFT_RESET : 1;
		unsigned int                PSCLV_SOFT_RESET : 1;
		unsigned int              COL_MAN_SOFT_RESET : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFE_CLOCK_CONTROL__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int     DISPCLK_R_DCFE_GATE_DISABLE : 1;
		unsigned int                                 : 3;
		unsigned int      DISPCLK_G_DCP_GATE_DISABLE : 1;
		unsigned int                                 : 3;
		unsigned int      DISPCLK_G_SCL_GATE_DISABLE : 1;
		unsigned int                                 : 11;
		unsigned int               DCFE_TEST_CLK_SEL : 5;
		unsigned int                                 : 2;
		unsigned int               DCFE_CLOCK_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFE_DBG_CONFIG__VI {
	struct {
		unsigned int                     DCFE_DBG_EN : 1;
		unsigned int                                 : 3;
		unsigned int                    DCFE_DBG_SEL : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFE_DBG_SEL__VI {
	struct {
		unsigned int                    DCFE_DBG_SEL : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFE_MEM_PWR_CTRL__VI {
	struct {
		unsigned int           DCP_LUT_MEM_PWR_FORCE : 2;
		unsigned int             DCP_LUT_MEM_PWR_DIS : 1;
		unsigned int       DCP_REGAMMA_MEM_PWR_FORCE : 2;
		unsigned int         DCP_REGAMMA_MEM_PWR_DIS : 1;
		unsigned int         SCL_COEFF_MEM_PWR_FORCE : 2;
		unsigned int           SCL_COEFF_MEM_PWR_DIS : 1;
		unsigned int        DCP_CURSOR_MEM_PWR_FORCE : 2;
		unsigned int          DCP_CURSOR_MEM_PWR_DIS : 1;
		unsigned int         LB0_ALPHA_MEM_PWR_FORCE : 2;
		unsigned int           LB0_ALPHA_MEM_PWR_DIS : 1;
		unsigned int         LB1_ALPHA_MEM_PWR_FORCE : 2;
		unsigned int           LB1_ALPHA_MEM_PWR_DIS : 1;
		unsigned int         LB2_ALPHA_MEM_PWR_FORCE : 2;
		unsigned int           LB2_ALPHA_MEM_PWR_DIS : 1;
		unsigned int               LB0_MEM_PWR_FORCE : 2;
		unsigned int                 LB0_MEM_PWR_DIS : 1;
		unsigned int               LB1_MEM_PWR_FORCE : 2;
		unsigned int                 LB1_MEM_PWR_DIS : 1;
		unsigned int               LB2_MEM_PWR_FORCE : 2;
		unsigned int                 LB2_MEM_PWR_DIS : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFE_MEM_PWR_CTRL2__VI {
	struct {
		unsigned int        DCP_LUT_MEM_PWR_MODE_SEL : 2;
		unsigned int    DCP_REGAMMA_MEM_PWR_MODE_SEL : 2;
		unsigned int      SCL_COEFF_MEM_PWR_MODE_SEL : 2;
		unsigned int     DCP_CURSOR_MEM_PWR_MODE_SEL : 2;
		unsigned int       LB_ALPHA_MEM_PWR_MODE_SEL : 2;
		unsigned int             LB_MEM_PWR_MODE_SEL : 2;
		unsigned int    DCP_CURSOR2_MEM_PWR_MODE_SEL : 2;
		unsigned int           BLND_MEM_PWR_MODE_SEL : 2;
		unsigned int              BLND_MEM_PWR_FORCE : 2;
		unsigned int                BLND_MEM_PWR_DIS : 1;
		unsigned int            OVLSCL_MEM_PWR_FORCE : 1;
		unsigned int              OVLSCL_MEM_PWR_DIS : 1;
		unsigned int       DCP_CURSOR2_MEM_PWR_FORCE : 2;
		unsigned int         DCP_CURSOR2_MEM_PWR_DIS : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFE_MEM_PWR_STATUS__VI {
	struct {
		unsigned int           DCP_LUT_MEM_PWR_STATE : 2;
		unsigned int       DCP_REGAMMA_MEM_PWR_STATE : 2;
		unsigned int         SCL_COEFF_MEM_PWR_STATE : 2;
		unsigned int        DCP_CURSOR_MEM_PWR_STATE : 2;
		unsigned int       DCP_CURSOR2_MEM_PWR_STATE : 2;
		unsigned int         LB0_ALPHA_MEM_PWR_STATE : 2;
		unsigned int         LB1_ALPHA_MEM_PWR_STATE : 2;
		unsigned int         LB2_ALPHA_MEM_PWR_STATE : 2;
		unsigned int               LB0_MEM_PWR_STATE : 2;
		unsigned int               LB1_MEM_PWR_STATE : 2;
		unsigned int               LB2_MEM_PWR_STATE : 2;
		unsigned int              BLND_MEM_PWR_STATE : 2;
		unsigned int            OVLSCL_MEM_PWR_STATE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCFE_SOFT_RESET__VI {
	struct {
		unsigned int          DCP_PIXPIPE_SOFT_RESET : 1;
		unsigned int              DCP_REQ_SOFT_RESET : 1;
		unsigned int              SCL_ALU_SOFT_RESET : 1;
		unsigned int                  SCL_SOFT_RESET : 1;
		unsigned int                 CRTC_SOFT_RESET : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_CLOCK_CNTL__VI {
	struct {
		unsigned int               DCIO_TEST_CLK_SEL : 5;
		unsigned int         DISPCLK_R_DCIO_GATE_DIS : 1;
		unsigned int                                 : 2;
		unsigned int         DISPCLK_R_DCIO_RAMP_DIS : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG10__VI {
	struct {
		unsigned int                 DCIO_DIGC_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG11__VI {
	struct {
		unsigned int                 DCIO_DIGD_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG12__VI {
	struct {
		unsigned int                 DCIO_DIGE_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG13__VI {
	struct {
		unsigned int                 DCIO_DIGF_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG14__VI {
	struct {
		unsigned int                 DCIO_DIGG_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG15__VI {
	struct {
		unsigned int                    DCIO_DEBUG15 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG16__VI {
	struct {
		unsigned int                    DCIO_DEBUG16 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG8__VI {
	struct {
		unsigned int                     DCIO_DEBUG8 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG9__VI {
	struct {
		unsigned int                     DCIO_DEBUG9 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUGA__VI {
	struct {
		unsigned int                     DCIO_DEBUGA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUGB__VI {
	struct {
		unsigned int                     DCIO_DEBUGB : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUGC__VI {
	struct {
		unsigned int                     DCIO_DEBUGC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUGD__VI {
	struct {
		unsigned int                     DCIO_DEBUGD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUGE__VI {
	struct {
		unsigned int                 DCIO_DIGA_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUGF__VI {
	struct {
		unsigned int                 DCIO_DIGB_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG_CONFIG__VI {
	struct {
		unsigned int                     DCIO_DBG_EN : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DEBUG_ID__VI {
	struct {
		unsigned int                   DCIO_DEBUG_ID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_DPHY_SEL__VI {
	struct {
		unsigned int                  DPHY_LANE0_SEL : 2;
		unsigned int                  DPHY_LANE1_SEL : 2;
		unsigned int                  DPHY_LANE2_SEL : 2;
		unsigned int                  DPHY_LANE3_SEL : 2;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_GSL0_CNTL__VI {
	struct {
		unsigned int             DCIO_GSL0_VSYNC_SEL : 3;
		unsigned int                                 : 5;
		unsigned int       DCIO_GSL0_TIMING_SYNC_SEL : 3;
		unsigned int                                 : 5;
		unsigned int     DCIO_GSL0_GLOBAL_UNLOCK_SEL : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_GSL1_CNTL__VI {
	struct {
		unsigned int             DCIO_GSL1_VSYNC_SEL : 3;
		unsigned int                                 : 5;
		unsigned int       DCIO_GSL1_TIMING_SYNC_SEL : 3;
		unsigned int                                 : 5;
		unsigned int     DCIO_GSL1_GLOBAL_UNLOCK_SEL : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_GSL2_CNTL__VI {
	struct {
		unsigned int             DCIO_GSL2_VSYNC_SEL : 3;
		unsigned int                                 : 5;
		unsigned int       DCIO_GSL2_TIMING_SYNC_SEL : 3;
		unsigned int                                 : 5;
		unsigned int     DCIO_GSL2_GLOBAL_UNLOCK_SEL : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_GSL_GENLK_PAD_CNTL__VI {
	struct {
		unsigned int DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL : 2;
		unsigned int                                 : 2;
		unsigned int DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL : 2;
		unsigned int                                 : 2;
		unsigned int         DCIO_GENLK_CLK_GSL_MASK : 2;
		unsigned int                                 : 6;
		unsigned int DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL : 2;
		unsigned int                                 : 2;
		unsigned int DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL : 2;
		unsigned int                                 : 2;
		unsigned int       DCIO_GENLK_VSYNC_GSL_MASK : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_GSL_SWAPLOCK_PAD_CNTL__VI {
	struct {
		unsigned int DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL : 2;
		unsigned int                                 : 2;
		unsigned int DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL : 2;
		unsigned int                                 : 2;
		unsigned int        DCIO_SWAPLOCK_A_GSL_MASK : 2;
		unsigned int                                 : 6;
		unsigned int DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL : 2;
		unsigned int                                 : 2;
		unsigned int DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL : 2;
		unsigned int                                 : 2;
		unsigned int        DCIO_SWAPLOCK_B_GSL_MASK : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_IMPCAL_CNTL__VI {
	struct {
		unsigned int              CALR_CNTL_OVERRIDE : 4;
		unsigned int                                 : 1;
		unsigned int               IMPCAL_SOFT_RESET : 1;
		unsigned int                                 : 2;
		unsigned int                   IMPCAL_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int                IMPCAL_ARB_STATE : 3;
		unsigned int             AUX_IMPCAL_INTERVAL : 4;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_SOFT_RESET__VI {
	struct {
		unsigned int              UNIPHYA_SOFT_RESET : 1;
		unsigned int               DSYNCA_SOFT_RESET : 1;
		unsigned int              UNIPHYB_SOFT_RESET : 1;
		unsigned int               DSYNCB_SOFT_RESET : 1;
		unsigned int              UNIPHYC_SOFT_RESET : 1;
		unsigned int               DSYNCC_SOFT_RESET : 1;
		unsigned int              UNIPHYD_SOFT_RESET : 1;
		unsigned int               DSYNCD_SOFT_RESET : 1;
		unsigned int              UNIPHYE_SOFT_RESET : 1;
		unsigned int               DSYNCE_SOFT_RESET : 1;
		unsigned int              UNIPHYF_SOFT_RESET : 1;
		unsigned int               DSYNCF_SOFT_RESET : 1;
		unsigned int              UNIPHYG_SOFT_RESET : 1;
		unsigned int               DSYNCG_SOFT_RESET : 1;
		unsigned int                                 : 2;
		unsigned int                 DACA_SOFT_RESET : 1;
		unsigned int                                 : 3;
		unsigned int              DCRXPHY_SOFT_RESET : 1;
		unsigned int                                 : 3;
		unsigned int                 DPHY_SOFT_RESET : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int            DCIO_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int           DCIO_TEST_DEBUG_INDEX : 8;
		unsigned int        DCIO_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCIO_WRCMD_DELAY__VI {
	struct {
		unsigned int                    UNIPHY_DELAY : 4;
		unsigned int                       DAC_DELAY : 4;
		unsigned int                      DPHY_DELAY : 4;
		unsigned int                   DCRXPHY_DELAY : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_CLK_CNTL__VI {
	struct {
		unsigned int                DCI_TEST_CLK_SEL : 5;
		unsigned int          DISPCLK_R_DCI_GATE_DIS : 1;
		unsigned int              DISPCLK_M_GATE_DIS : 1;
		unsigned int       SCLK_G_STREAM_AZ_GATE_DIS : 1;
		unsigned int              SCLK_R_AZ_GATE_DIS : 1;
		unsigned int          DISPCLK_G_FBC_GATE_DIS : 1;
		unsigned int                                 : 1;
		unsigned int          DISPCLK_G_VGA_GATE_DIS : 1;
		unsigned int                                 : 1;
		unsigned int          DISPCLK_G_VIP_GATE_DIS : 1;
		unsigned int                       VPCLK_POL : 1;
		unsigned int         DISPCLK_G_DMCU_GATE_DIS : 1;
		unsigned int        DISPCLK_G_DMIF0_GATE_DIS : 1;
		unsigned int        DISPCLK_G_DMIF1_GATE_DIS : 1;
		unsigned int        DISPCLK_G_DMIF2_GATE_DIS : 1;
		unsigned int        DISPCLK_G_DMIF3_GATE_DIS : 1;
		unsigned int        DISPCLK_G_DMIF4_GATE_DIS : 1;
		unsigned int        DISPCLK_G_DMIF5_GATE_DIS : 1;
		unsigned int            SCLK_G_DMIF_GATE_DIS : 1;
		unsigned int         SCLK_G_DMIFTRK_GATE_DIS : 1;
		unsigned int         SCLK_G_CNTL_AZ_GATE_DIS : 1;
		unsigned int      DISPCLK_G_DMIFV_L_GATE_DIS : 1;
		unsigned int      DISPCLK_G_DMIFV_C_GATE_DIS : 1;
		unsigned int             DCI_PG_TEST_CLK_SEL : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_CLK_RAMP_CNTL__VI {
	struct {
		unsigned int     DISPCLK_G_MCIF_DWB_GATE_DIS : 1;
		unsigned int        SCLK_G_MCIF_DWB_GATE_DIS : 1;
		unsigned int    DISPCLK_G_MCIF_CWB0_GATE_DIS : 1;
		unsigned int       SCLK_G_MCIF_CWB0_GATE_DIS : 1;
		unsigned int    DISPCLK_G_MCIF_CWB1_GATE_DIS : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int       SCLK_G_MCIF_CWB1_GATE_DIS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_DEBUG_CONFIG__VI {
	struct {
		unsigned int                      DCI_DBG_EN : 1;
		unsigned int                                 : 3;
		unsigned int               DCI_DBG_BLOCK_SEL : 4;
		unsigned int               DCI_DBG_CLOCK_SEL : 4;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_MEM_PWR_CNTL__VI {
	struct {
		unsigned int        DMIF_RDREQ_MEM_PWR_FORCE : 2;
		unsigned int          DMIF_RDREQ_MEM_PWR_DIS : 1;
		unsigned int        MCIF_RDREQ_MEM_PWR_FORCE : 1;
		unsigned int          MCIF_RDREQ_MEM_PWR_DIS : 1;
		unsigned int        MCIF_WRREQ_MEM_PWR_FORCE : 1;
		unsigned int          MCIF_WRREQ_MEM_PWR_DIS : 1;
		unsigned int               VGA_MEM_PWR_FORCE : 1;
		unsigned int                 VGA_MEM_PWR_DIS : 1;
		unsigned int         DMCU_ERAM_MEM_PWR_FORCE : 2;
		unsigned int           DMCU_ERAM_MEM_PWR_DIS : 1;
		unsigned int         DMCU_IRAM_MEM_PWR_FORCE : 1;
		unsigned int           DMCU_IRAM_MEM_PWR_DIS : 1;
		unsigned int               FBC_MEM_PWR_FORCE : 2;
		unsigned int                 FBC_MEM_PWR_DIS : 1;
		unsigned int              MCIF_MEM_PWR_FORCE : 2;
		unsigned int                MCIF_MEM_PWR_DIS : 1;
		unsigned int          MCIF_DWB_MEM_PWR_FORCE : 2;
		unsigned int            MCIF_DWB_MEM_PWR_DIS : 1;
		unsigned int         MCIF_CWB0_MEM_PWR_FORCE : 2;
		unsigned int           MCIF_CWB0_MEM_PWR_DIS : 1;
		unsigned int         MCIF_CWB1_MEM_PWR_FORCE : 2;
		unsigned int           MCIF_CWB1_MEM_PWR_DIS : 1;
		unsigned int               VIP_MEM_PWR_FORCE : 1;
		unsigned int                 VIP_MEM_PWR_DIS : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_MEM_PWR_CNTL2__VI {
	struct {
		unsigned int       DMIF0_ASYNC_MEM_PWR_FORCE : 2;
		unsigned int         DMIF0_ASYNC_MEM_PWR_DIS : 1;
		unsigned int        DMIF0_DATA_MEM_PWR_FORCE : 2;
		unsigned int          DMIF0_DATA_MEM_PWR_DIS : 1;
		unsigned int       DMIF0_CHUNK_MEM_PWR_FORCE : 1;
		unsigned int         DMIF0_CHUNK_MEM_PWR_DIS : 1;
		unsigned int       DMIF1_ASYNC_MEM_PWR_FORCE : 2;
		unsigned int         DMIF1_ASYNC_MEM_PWR_DIS : 1;
		unsigned int        DMIF1_DATA_MEM_PWR_FORCE : 2;
		unsigned int          DMIF1_DATA_MEM_PWR_DIS : 1;
		unsigned int       DMIF1_CHUNK_MEM_PWR_FORCE : 1;
		unsigned int         DMIF1_CHUNK_MEM_PWR_DIS : 1;
		unsigned int       DMIF2_ASYNC_MEM_PWR_FORCE : 2;
		unsigned int         DMIF2_ASYNC_MEM_PWR_DIS : 1;
		unsigned int        DMIF2_DATA_MEM_PWR_FORCE : 2;
		unsigned int          DMIF2_DATA_MEM_PWR_DIS : 1;
		unsigned int       DMIF2_CHUNK_MEM_PWR_FORCE : 1;
		unsigned int         DMIF2_CHUNK_MEM_PWR_DIS : 1;
		unsigned int       DMIF3_ASYNC_MEM_PWR_FORCE : 2;
		unsigned int         DMIF3_ASYNC_MEM_PWR_DIS : 1;
		unsigned int        DMIF3_DATA_MEM_PWR_FORCE : 2;
		unsigned int          DMIF3_DATA_MEM_PWR_DIS : 1;
		unsigned int       DMIF3_CHUNK_MEM_PWR_FORCE : 1;
		unsigned int         DMIF3_CHUNK_MEM_PWR_DIS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_MEM_PWR_CNTL3__VI {
	struct {
		unsigned int       DMIF4_ASYNC_MEM_PWR_FORCE : 2;
		unsigned int         DMIF4_ASYNC_MEM_PWR_DIS : 1;
		unsigned int        DMIF4_DATA_MEM_PWR_FORCE : 2;
		unsigned int          DMIF4_DATA_MEM_PWR_DIS : 1;
		unsigned int       DMIF4_CHUNK_MEM_PWR_FORCE : 1;
		unsigned int         DMIF4_CHUNK_MEM_PWR_DIS : 1;
		unsigned int       DMIF5_ASYNC_MEM_PWR_FORCE : 2;
		unsigned int         DMIF5_ASYNC_MEM_PWR_DIS : 1;
		unsigned int        DMIF5_DATA_MEM_PWR_FORCE : 2;
		unsigned int          DMIF5_DATA_MEM_PWR_DIS : 1;
		unsigned int       DMIF5_CHUNK_MEM_PWR_FORCE : 1;
		unsigned int         DMIF5_CHUNK_MEM_PWR_DIS : 1;
		unsigned int     DMIF_RDREQ_MEM_PWR_MODE_SEL : 2;
		unsigned int     DMIF_ASYNC_MEM_PWR_MODE_SEL : 2;
		unsigned int      DMIF_DATA_MEM_PWR_MODE_SEL : 2;
		unsigned int      DMCU_ERAM_MEM_PWR_MODE_SEL : 1;
		unsigned int            FBC_MEM_PWR_MODE_SEL : 2;
		unsigned int      MCIF_CWB0_MEM_PWR_MODE_SEL : 2;
		unsigned int      MCIF_CWB1_MEM_PWR_MODE_SEL : 2;
		unsigned int       MCIF_DWB_MEM_PWR_MODE_SEL : 2;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_MEM_PWR_STATUS__VI {
	struct {
		unsigned int       DMIF_RDREQ_MEM1_PWR_STATE : 2;
		unsigned int       DMIF_RDREQ_MEM2_PWR_STATE : 2;
		unsigned int        MCIF_RDREQ_MEM_PWR_STATE : 1;
		unsigned int                                 : 1;
		unsigned int        MCIF_WRREQ_MEM_PWR_STATE : 1;
		unsigned int                                 : 1;
		unsigned int               VGA_MEM_PWR_STATE : 1;
		unsigned int         DMCU_ERAM_MEM_PWR_STATE : 2;
		unsigned int         DMCU_IRAM_MEM_PWR_STATE : 1;
		unsigned int               FBC_MEM_PWR_STATE : 2;
		unsigned int              MCIF_MEM_PWR_STATE : 2;
		unsigned int          MCIF_DWB_MEM_PWR_STATE : 2;
		unsigned int         MCIF_CWB0_MEM_PWR_STATE : 2;
		unsigned int         MCIF_CWB1_MEM_PWR_STATE : 2;
		unsigned int               VIP_MEM_PWR_STATE : 1;
		unsigned int                                 : 1;
		unsigned int       DMIF0_ASYNC_MEM_PWR_STATE : 2;
		unsigned int        DMIF0_DATA_MEM_PWR_STATE : 2;
		unsigned int       DMIF0_CHUNK_MEM_PWR_STATE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_MEM_PWR_STATUS2__VI {
	struct {
		unsigned int       DMIF1_ASYNC_MEM_PWR_STATE : 2;
		unsigned int        DMIF1_DATA_MEM_PWR_STATE : 2;
		unsigned int       DMIF1_CHUNK_MEM_PWR_STATE : 1;
		unsigned int       DMIF2_ASYNC_MEM_PWR_STATE : 2;
		unsigned int        DMIF2_DATA_MEM_PWR_STATE : 2;
		unsigned int       DMIF2_CHUNK_MEM_PWR_STATE : 1;
		unsigned int       DMIF3_ASYNC_MEM_PWR_STATE : 2;
		unsigned int        DMIF3_DATA_MEM_PWR_STATE : 2;
		unsigned int       DMIF3_CHUNK_MEM_PWR_STATE : 1;
		unsigned int       DMIF4_ASYNC_MEM_PWR_STATE : 2;
		unsigned int        DMIF4_DATA_MEM_PWR_STATE : 2;
		unsigned int       DMIF4_CHUNK_MEM_PWR_STATE : 1;
		unsigned int       DMIF5_ASYNC_MEM_PWR_STATE : 2;
		unsigned int        DMIF5_DATA_MEM_PWR_STATE : 2;
		unsigned int       DMIF5_CHUNK_MEM_PWR_STATE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_PG_DEBUG_CONFIG__VI {
	struct {
		unsigned int                   DCI_PG_DBG_EN : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCI_SOFT_RESET__VI {
	struct {
		unsigned int                  VGA_SOFT_RESET : 1;
		unsigned int                  VIP_SOFT_RESET : 1;
		unsigned int                 MCIF_SOFT_RESET : 1;
		unsigned int                  FBC_SOFT_RESET : 1;
		unsigned int                DMIF0_SOFT_RESET : 1;
		unsigned int                DMIF1_SOFT_RESET : 1;
		unsigned int                DMIF2_SOFT_RESET : 1;
		unsigned int                DMIF3_SOFT_RESET : 1;
		unsigned int                DMIF4_SOFT_RESET : 1;
		unsigned int                DMIF5_SOFT_RESET : 1;
		unsigned int             DCFEV0_L_SOFT_RESET : 1;
		unsigned int             DCFEV0_C_SOFT_RESET : 1;
		unsigned int              DMIFARB_SOFT_RESET : 1;
		unsigned int                                 : 3;
		unsigned int             MCIF_DWB_SOFT_RESET : 1;
		unsigned int            MCIF_CWB0_SOFT_RESET : 1;
		unsigned int            MCIF_CWB1_SOFT_RESET : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_CLK_CNTL__VI {
	struct {
		unsigned int                DCO_TEST_CLK_SEL : 5;
		unsigned int          DISPCLK_R_DCO_GATE_DIS : 1;
		unsigned int          DISPCLK_G_ABM_GATE_DIS : 1;
		unsigned int          DISPCLK_G_DVO_GATE_DIS : 1;
		unsigned int         DISPCLK_G_DACA_GATE_DIS : 1;
		unsigned int         DISPCLK_G_DACB_GATE_DIS : 1;
		unsigned int           REFCLK_R_DCO_GATE_DIS : 1;
		unsigned int                                 : 5;
		unsigned int         DISPCLK_G_FMT0_GATE_DIS : 1;
		unsigned int         DISPCLK_G_FMT1_GATE_DIS : 1;
		unsigned int         DISPCLK_G_FMT2_GATE_DIS : 1;
		unsigned int         DISPCLK_G_FMT3_GATE_DIS : 1;
		unsigned int         DISPCLK_G_FMT4_GATE_DIS : 1;
		unsigned int         DISPCLK_G_FMT5_GATE_DIS : 1;
		unsigned int                                 : 2;
		unsigned int         DISPCLK_G_DIGA_GATE_DIS : 1;
		unsigned int         DISPCLK_G_DIGB_GATE_DIS : 1;
		unsigned int         DISPCLK_G_DIGC_GATE_DIS : 1;
		unsigned int         DISPCLK_G_DIGD_GATE_DIS : 1;
		unsigned int         DISPCLK_G_DIGE_GATE_DIS : 1;
		unsigned int         DISPCLK_G_DIGF_GATE_DIS : 1;
		unsigned int         DISPCLK_G_DIGG_GATE_DIS : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_CLK_RAMP_CNTL__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int           REFCLK_R_DCO_RAMP_DIS : 1;
		unsigned int          DISPCLK_R_DCO_RAMP_DIS : 1;
		unsigned int          DISPCLK_G_ABM_RAMP_DIS : 1;
		unsigned int          DISPCLK_G_DVO_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_DACA_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_DACB_RAMP_DIS : 1;
		unsigned int                                 : 6;
		unsigned int         DISPCLK_G_FMT0_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_FMT1_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_FMT2_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_FMT3_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_FMT4_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_FMT5_RAMP_DIS : 1;
		unsigned int                                 : 2;
		unsigned int         DISPCLK_G_DIGA_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_DIGB_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_DIGC_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_DIGD_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_DIGE_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_DIGF_RAMP_DIS : 1;
		unsigned int         DISPCLK_G_DIGG_RAMP_DIS : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_DCFE_EXT_VSYNC_CNTL__VI {
	struct {
		unsigned int         DCO_DCFE0_EXT_VSYNC_MUX : 3;
		unsigned int                                 : 1;
		unsigned int         DCO_DCFE1_EXT_VSYNC_MUX : 3;
		unsigned int                                 : 1;
		unsigned int         DCO_DCFE2_EXT_VSYNC_MUX : 3;
		unsigned int                                 : 1;
		unsigned int         DCO_DCFE3_EXT_VSYNC_MUX : 3;
		unsigned int                                 : 1;
		unsigned int         DCO_DCFE4_EXT_VSYNC_MUX : 3;
		unsigned int                                 : 1;
		unsigned int         DCO_DCFE5_EXT_VSYNC_MUX : 3;
		unsigned int                                 : 1;
		unsigned int    DCO_SWAPLOCKB_EXT_VSYNC_MASK : 3;
		unsigned int                                 : 1;
		unsigned int     DCO_GENERICB_EXT_VSYNC_MASK : 3;
		unsigned int    DCO_CRTC_MANUAL_FLOW_CONTROL : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_MEM_PWR_CTRL__VI {
	struct {
		unsigned int           I2C_LIGHT_SLEEP_FORCE : 1;
		unsigned int             I2C_LIGHT_SLEEP_DIS : 1;
		unsigned int           TVOUT_LIGHT_SLEEP_DIS : 1;
		unsigned int             MVP_LIGHT_SLEEP_DIS : 1;
		unsigned int             DPA_LIGHT_SLEEP_DIS : 1;
		unsigned int             DPB_LIGHT_SLEEP_DIS : 1;
		unsigned int             DPC_LIGHT_SLEEP_DIS : 1;
		unsigned int             DPD_LIGHT_SLEEP_DIS : 1;
		unsigned int             DPE_LIGHT_SLEEP_DIS : 1;
		unsigned int             DPF_LIGHT_SLEEP_DIS : 1;
		unsigned int             DPG_LIGHT_SLEEP_DIS : 1;
		unsigned int             HDMI0_MEM_PWR_FORCE : 2;
		unsigned int               HDMI0_MEM_PWR_DIS : 1;
		unsigned int             HDMI1_MEM_PWR_FORCE : 2;
		unsigned int               HDMI1_MEM_PWR_DIS : 1;
		unsigned int             HDMI2_MEM_PWR_FORCE : 2;
		unsigned int               HDMI2_MEM_PWR_DIS : 1;
		unsigned int             HDMI3_MEM_PWR_FORCE : 2;
		unsigned int               HDMI3_MEM_PWR_DIS : 1;
		unsigned int             HDMI4_MEM_PWR_FORCE : 2;
		unsigned int               HDMI4_MEM_PWR_DIS : 1;
		unsigned int             HDMI5_MEM_PWR_FORCE : 2;
		unsigned int               HDMI5_MEM_PWR_DIS : 1;
		unsigned int             HDMI6_MEM_PWR_FORCE : 2;
		unsigned int               HDMI6_MEM_PWR_DIS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_MEM_PWR_CTRL2__VI {
	struct {
		unsigned int           HDMI_MEM_PWR_MODE_SEL : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_MEM_PWR_STATUS__VI {
	struct {
		unsigned int               I2C_MEM_PWR_STATE : 1;
		unsigned int             TVOUT_MEM_PWR_STATE : 1;
		unsigned int               MVP_MEM_PWR_STATE : 1;
		unsigned int               DPA_MEM_PWR_STATE : 1;
		unsigned int               DPB_MEM_PWR_STATE : 1;
		unsigned int               DPC_MEM_PWR_STATE : 1;
		unsigned int               DPD_MEM_PWR_STATE : 1;
		unsigned int               DPE_MEM_PWR_STATE : 1;
		unsigned int               DPF_MEM_PWR_STATE : 1;
		unsigned int               DPG_MEM_PWR_STATE : 1;
		unsigned int             HDMI0_MEM_PWR_STATE : 2;
		unsigned int             HDMI1_MEM_PWR_STATE : 2;
		unsigned int             HDMI2_MEM_PWR_STATE : 2;
		unsigned int             HDMI3_MEM_PWR_STATE : 2;
		unsigned int             HDMI4_MEM_PWR_STATE : 2;
		unsigned int             HDMI5_MEM_PWR_STATE : 2;
		unsigned int             HDMI6_MEM_PWR_STATE : 2;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_POWER_MANAGEMENT_CNTL__VI {
	struct {
		unsigned int                 PM_ASSERT_RESET : 1;
		unsigned int                                 : 7;
		unsigned int                 PM_ALL_BUSY_OFF : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_SCRATCH0__VI {
	struct {
		unsigned int                    DCO_SCRATCH0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_SCRATCH1__VI {
	struct {
		unsigned int                    DCO_SCRATCH1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_SCRATCH2__VI {
	struct {
		unsigned int                    DCO_SCRATCH2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_SCRATCH3__VI {
	struct {
		unsigned int                    DCO_SCRATCH3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_SCRATCH4__VI {
	struct {
		unsigned int                    DCO_SCRATCH4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_SCRATCH5__VI {
	struct {
		unsigned int                    DCO_SCRATCH5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_SCRATCH6__VI {
	struct {
		unsigned int                    DCO_SCRATCH6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_SCRATCH7__VI {
	struct {
		unsigned int                    DCO_SCRATCH7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_SOFT_RESET__VI {
	struct {
		unsigned int                 DACA_SOFT_RESET : 1;
		unsigned int                                 : 3;
		unsigned int          I2S0_SPDIF0_SOFT_RESET : 1;
		unsigned int                 I2S1_SOFT_RESET : 1;
		unsigned int               SPDIF1_SOFT_RESET : 1;
		unsigned int                                 : 5;
		unsigned int               DB_CLK_SOFT_RESET : 1;
		unsigned int                                 : 3;
		unsigned int                 FMT0_SOFT_RESET : 1;
		unsigned int                 FMT1_SOFT_RESET : 1;
		unsigned int                 FMT2_SOFT_RESET : 1;
		unsigned int                 FMT3_SOFT_RESET : 1;
		unsigned int                 FMT4_SOFT_RESET : 1;
		unsigned int                 FMT5_SOFT_RESET : 1;
		unsigned int                                 : 2;
		unsigned int                  MVP_SOFT_RESET : 1;
		unsigned int                  ABM_SOFT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                  DVO_SOFT_RESET : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_STEREOSYNC_SEL__VI {
	struct {
		unsigned int         GENERICA_STEREOSYNC_SEL : 3;
		unsigned int                                 : 13;
		unsigned int         GENERICB_STEREOSYNC_SEL : 3;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int             DCO_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCO_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int            DCO_TEST_DEBUG_INDEX : 8;
		unsigned int         DCO_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCPG_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int            DCPG_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCPG_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int           DCPG_TEST_DEBUG_INDEX : 8;
		unsigned int        DCPG_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_DEBUG2__VI {
	struct {
		unsigned int                      DCP_DEBUG2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_FP_CONVERTED_FIELD__VI {
	struct {
		unsigned int     DCP_FP_CONVERTED_FIELD_DATA : 18;
		unsigned int                                 : 2;
		unsigned int    DCP_FP_CONVERTED_FIELD_INDEX : 7;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_GSL_CONTROL__VI {
	struct {
		unsigned int                     DCP_GSL0_EN : 1;
		unsigned int                     DCP_GSL1_EN : 1;
		unsigned int                     DCP_GSL2_EN : 1;
		unsigned int                                 : 5;
		unsigned int                    DCP_GSL_MODE : 2;
		unsigned int                                 : 2;
		unsigned int  DCP_GSL_HSYNC_FLIP_FORCE_DELAY : 4;
		unsigned int               DCP_GSL_MASTER_EN : 1;
		unsigned int              DCP_GSL_XDMA_GROUP : 2;
		unsigned int DCP_GSL_XDMA_GROUP_UNDERFLOW_EN : 1;
		unsigned int                                 : 4;
		unsigned int             DCP_GSL_SYNC_SOURCE : 2;
		unsigned int                                 : 1;
		unsigned int DCP_GSL_DELAY_SURFACE_UPDATE_PENDING : 1;
		unsigned int  DCP_GSL_HSYNC_FLIP_CHECK_DELAY : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_RANDOM_SEEDS__VI {
	struct {
		unsigned int                 DCP_RAND_R_SEED : 8;
		unsigned int                 DCP_RAND_G_SEED : 8;
		unsigned int                 DCP_RAND_B_SEED : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCP_SPATIAL_DITHER_CNTL__VI {
	struct {
		unsigned int           DCP_SPATIAL_DITHER_EN : 1;
		unsigned int                                 : 3;
		unsigned int         DCP_SPATIAL_DITHER_MODE : 2;
		unsigned int        DCP_SPATIAL_DITHER_DEPTH : 2;
		unsigned int         DCP_FRAME_RANDOM_ENABLE : 1;
		unsigned int           DCP_RGB_RANDOM_ENABLE : 1;
		unsigned int      DCP_HIGHPASS_RANDOM_ENABLE : 1;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED0__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED1__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED10__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED100__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED101__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED102__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED103__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED104__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED105__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED106__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED107__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED108__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED109__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED11__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED110__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED111__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED112__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED113__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED114__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED115__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED116__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED117__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED118__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED119__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED12__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED120__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED121__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED122__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED123__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED124__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED125__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED126__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED127__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED128__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED129__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED13__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED130__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED131__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED132__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED133__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED134__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED135__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED136__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED137__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED138__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED139__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED14__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED140__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED141__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED142__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED143__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED144__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED145__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED146__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED147__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED148__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED149__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED15__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED150__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED151__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED152__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED153__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED154__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED155__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED156__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED157__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED158__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED159__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED16__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED160__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED161__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED162__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED163__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED164__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED165__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED166__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED167__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED168__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED169__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED17__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED170__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED171__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED172__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED173__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED174__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED175__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED176__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED177__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED178__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED179__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED18__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED180__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED181__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED182__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED183__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED184__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED185__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED186__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED187__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED188__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED189__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED19__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED190__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED191__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED192__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED193__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED194__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED195__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED196__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED197__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED198__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED199__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED2__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED20__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED200__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED201__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED202__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED203__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED204__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED205__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED206__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED207__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED208__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED209__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED21__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED210__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED211__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED212__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED213__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED214__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED215__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED216__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED217__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED218__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED219__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED22__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED220__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED221__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED222__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED223__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED224__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED225__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED226__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED227__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED228__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED229__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED23__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED230__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED231__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED232__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED233__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED234__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED235__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED236__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED237__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED238__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED239__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED24__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED240__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED241__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED242__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED243__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED244__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED245__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED246__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED247__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED248__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED249__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED25__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED250__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED251__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED252__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED253__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED254__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED255__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED256__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED257__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED258__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED259__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED26__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED260__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED261__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED262__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED263__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED264__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED265__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED266__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED267__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED268__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED269__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED27__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED270__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED271__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED272__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED273__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED274__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED275__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED276__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED277__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED278__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED279__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED28__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED280__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED281__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED282__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED283__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED284__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED285__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED286__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED287__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED288__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED289__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED29__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED290__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED291__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED292__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED293__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED294__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED295__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED296__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED297__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED298__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED299__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED3__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED30__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED300__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED301__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED302__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED303__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED304__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED305__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED306__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED307__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED308__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED309__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED31__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED310__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED311__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED312__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED313__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED314__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED315__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED316__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED317__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED318__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED319__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED32__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED320__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED321__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED322__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED323__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED324__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED325__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED326__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED327__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED328__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED329__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED33__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED330__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED331__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED332__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED333__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED334__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED335__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED336__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED337__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED338__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED339__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED34__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED340__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED341__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED342__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED343__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED344__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED345__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED346__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED347__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED348__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED349__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED35__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED350__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED351__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED352__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED353__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED354__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED355__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED356__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED357__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED358__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED359__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED36__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED360__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED361__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED362__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED363__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED364__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED365__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED366__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED367__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED368__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED369__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED37__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED370__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED371__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED372__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED373__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED374__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED375__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED376__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED377__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED378__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED379__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED38__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED39__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED4__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED40__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED41__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED42__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED43__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED44__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED45__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED46__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED47__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED48__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED49__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED5__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED50__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED51__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED52__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED53__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED54__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED55__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED56__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED57__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED58__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED59__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED6__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED60__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED61__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED62__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED63__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED64__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED65__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED66__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED67__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED68__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED69__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED7__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED70__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED71__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED72__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED73__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED74__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED75__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED76__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED77__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED78__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED79__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED8__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED80__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED81__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED82__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED83__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED84__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED85__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED86__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED87__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED88__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED89__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED9__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED90__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED91__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED92__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED93__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED94__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED95__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED96__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED97__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED98__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DCRX_PHY_MACRO_CNTL_RESERVED99__VI {
	struct {
		unsigned int    DCRX_PHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_ABM1_OVERSCAN_PIXEL_VALUE__VI {
	struct {
		unsigned int     ABM1_OVERSCAN_R_PIXEL_VALUE : 10;
		unsigned int     ABM1_OVERSCAN_G_PIXEL_VALUE : 10;
		unsigned int     ABM1_OVERSCAN_B_PIXEL_VALUE : 10;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_DVODATA_CONFIG__VI {
	struct {
		unsigned int                                 : 19;
		unsigned int                      VIP_MUX_EN : 1;
		unsigned int            VIP_ALTER_MAPPING_EN : 1;
		unsigned int            DVO_ALTER_MAPPING_EN : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDCVGA_A__VI {
	struct {
		unsigned int             DC_GPIO_DDCVGACLK_A : 1;
		unsigned int                                 : 7;
		unsigned int            DC_GPIO_DDCVGADATA_A : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDCVGA_EN__VI {
	struct {
		unsigned int            DC_GPIO_DDCVGACLK_EN : 1;
		unsigned int                                 : 7;
		unsigned int           DC_GPIO_DDCVGADATA_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDCVGA_MASK__VI {
	struct {
		unsigned int          DC_GPIO_DDCVGACLK_MASK : 1;
		unsigned int                                 : 5;
		unsigned int          DC_GPIO_DDCVGACLK_RECV : 1;
		unsigned int                                 : 1;
		unsigned int         DC_GPIO_DDCVGADATA_MASK : 1;
		unsigned int                                 : 3;
		unsigned int        DC_GPIO_DDCVGADATA_PD_EN : 1;
		unsigned int                                 : 1;
		unsigned int         DC_GPIO_DDCVGADATA_RECV : 1;
		unsigned int                                 : 1;
		unsigned int                 AUX_PADVGA_MODE : 1;
		unsigned int                                 : 3;
		unsigned int                      AUXVGA_POL : 1;
		unsigned int                                 : 1;
		unsigned int           ALLOW_HW_DDCVGA_PD_EN : 1;
		unsigned int                                 : 1;
		unsigned int           DC_GPIO_DDCVGACLK_STR : 4;
		unsigned int          DC_GPIO_DDCVGADATA_STR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_DDCVGA_Y__VI {
	struct {
		unsigned int             DC_GPIO_DDCVGACLK_Y : 1;
		unsigned int                                 : 7;
		unsigned int            DC_GPIO_DDCVGADATA_Y : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_GENLK_A__VI {
	struct {
		unsigned int             DC_GPIO_GENLK_CLK_A : 1;
		unsigned int                                 : 7;
		unsigned int           DC_GPIO_GENLK_VSYNC_A : 1;
		unsigned int                                 : 7;
		unsigned int            DC_GPIO_SWAPLOCK_A_A : 1;
		unsigned int                                 : 7;
		unsigned int            DC_GPIO_SWAPLOCK_B_A : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_GENLK_EN__VI {
	struct {
		unsigned int            DC_GPIO_GENLK_CLK_EN : 1;
		unsigned int                                 : 7;
		unsigned int          DC_GPIO_GENLK_VSYNC_EN : 1;
		unsigned int                                 : 7;
		unsigned int           DC_GPIO_SWAPLOCK_A_EN : 1;
		unsigned int                                 : 7;
		unsigned int           DC_GPIO_SWAPLOCK_B_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_GENLK_MASK__VI {
	struct {
		unsigned int          DC_GPIO_GENLK_CLK_MASK : 1;
		unsigned int        DC_GPIO_GENLK_CLK_PD_DIS : 1;
		unsigned int          DC_GPIO_GENLK_CLK_RECV : 1;
		unsigned int         DC_GPIO_GENLK_CLK_PU_EN : 1;
		unsigned int                                 : 4;
		unsigned int        DC_GPIO_GENLK_VSYNC_MASK : 1;
		unsigned int      DC_GPIO_GENLK_VSYNC_PD_DIS : 1;
		unsigned int        DC_GPIO_GENLK_VSYNC_RECV : 1;
		unsigned int       DC_GPIO_GENLK_VSYNC_PU_EN : 1;
		unsigned int                                 : 4;
		unsigned int         DC_GPIO_SWAPLOCK_A_MASK : 1;
		unsigned int       DC_GPIO_SWAPLOCK_A_PD_DIS : 1;
		unsigned int         DC_GPIO_SWAPLOCK_A_RECV : 1;
		unsigned int        DC_GPIO_SWAPLOCK_A_PU_EN : 1;
		unsigned int                                 : 4;
		unsigned int         DC_GPIO_SWAPLOCK_B_MASK : 1;
		unsigned int       DC_GPIO_SWAPLOCK_B_PD_DIS : 1;
		unsigned int         DC_GPIO_SWAPLOCK_B_RECV : 1;
		unsigned int        DC_GPIO_SWAPLOCK_B_PU_EN : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_GENLK_Y__VI {
	struct {
		unsigned int             DC_GPIO_GENLK_CLK_Y : 1;
		unsigned int                                 : 7;
		unsigned int           DC_GPIO_GENLK_VSYNC_Y : 1;
		unsigned int                                 : 7;
		unsigned int            DC_GPIO_SWAPLOCK_A_Y : 1;
		unsigned int                                 : 7;
		unsigned int            DC_GPIO_SWAPLOCK_B_Y : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_I2CPAD_A__VI {
	struct {
		unsigned int                   DC_GPIO_SCL_A : 1;
		unsigned int                   DC_GPIO_SDA_A : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_I2CPAD_EN__VI {
	struct {
		unsigned int                  DC_GPIO_SCL_EN : 1;
		unsigned int                  DC_GPIO_SDA_EN : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_I2CPAD_MASK__VI {
	struct {
		unsigned int                DC_GPIO_SCL_MASK : 1;
		unsigned int              DC_GPIO_SCL_PD_DIS : 1;
		unsigned int                DC_GPIO_SCL_RECV : 1;
		unsigned int                                 : 1;
		unsigned int                DC_GPIO_SDA_MASK : 1;
		unsigned int              DC_GPIO_SDA_PD_DIS : 1;
		unsigned int                DC_GPIO_SDA_RECV : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_I2CPAD_STRENGTH__VI {
	struct {
		unsigned int                 I2C_STRENGTH_SN : 4;
		unsigned int                 I2C_STRENGTH_SP : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPIO_I2CPAD_Y__VI {
	struct {
		unsigned int                   DC_GPIO_SCL_Y : 1;
		unsigned int                   DC_GPIO_SDA_Y : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPU_TIMER_START_POSITION_P_FLIP__VI {
	struct {
		unsigned int DC_GPU_TIMER_START_POSITION_D1_P_FLIP : 3;
		unsigned int                                 : 1;
		unsigned int DC_GPU_TIMER_START_POSITION_D2_P_FLIP : 3;
		unsigned int                                 : 1;
		unsigned int DC_GPU_TIMER_START_POSITION_D3_P_FLIP : 3;
		unsigned int                                 : 1;
		unsigned int DC_GPU_TIMER_START_POSITION_D4_P_FLIP : 3;
		unsigned int                                 : 1;
		unsigned int DC_GPU_TIMER_START_POSITION_D5_P_FLIP : 3;
		unsigned int                                 : 1;
		unsigned int DC_GPU_TIMER_START_POSITION_D6_P_FLIP : 3;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_GPU_TIMER_START_POSITION_V_UPDATE__VI {
	struct {
		unsigned int DC_GPU_TIMER_START_POSITION_D1_V_UPDATE : 3;
		unsigned int                                 : 1;
		unsigned int DC_GPU_TIMER_START_POSITION_D2_V_UPDATE : 3;
		unsigned int                                 : 1;
		unsigned int DC_GPU_TIMER_START_POSITION_D3_V_UPDATE : 3;
		unsigned int                                 : 1;
		unsigned int DC_GPU_TIMER_START_POSITION_D4_V_UPDATE : 3;
		unsigned int                                 : 1;
		unsigned int DC_GPU_TIMER_START_POSITION_D5_V_UPDATE : 3;
		unsigned int                                 : 1;
		unsigned int DC_GPU_TIMER_START_POSITION_D6_V_UPDATE : 3;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD_CONTROL__VI {
	struct {
		unsigned int         DC_HPD_CONNECTION_TIMER : 13;
		unsigned int                                 : 3;
		unsigned int             DC_HPD_RX_INT_TIMER : 10;
		unsigned int                                 : 2;
		unsigned int                       DC_HPD_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD_FAST_TRAIN_CNTL__VI {
	struct {
		unsigned int     DC_HPD_CONNECT_AUX_TX_DELAY : 8;
		unsigned int                                 : 4;
		unsigned int DC_HPD_CONNECT_FAST_TRAIN_DELAY : 8;
		unsigned int                                 : 4;
		unsigned int        DC_HPD_CONNECT_AUX_TX_EN : 1;
		unsigned int                                 : 3;
		unsigned int    DC_HPD_CONNECT_FAST_TRAIN_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD_INT_CONTROL__VI {
	struct {
		unsigned int                  DC_HPD_INT_ACK : 1;
		unsigned int                                 : 7;
		unsigned int             DC_HPD_INT_POLARITY : 1;
		unsigned int                                 : 7;
		unsigned int                   DC_HPD_INT_EN : 1;
		unsigned int                                 : 3;
		unsigned int               DC_HPD_RX_INT_ACK : 1;
		unsigned int                                 : 3;
		unsigned int                DC_HPD_RX_INT_EN : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD_INT_STATUS__VI {
	struct {
		unsigned int               DC_HPD_INT_STATUS : 1;
		unsigned int                    DC_HPD_SENSE : 1;
		unsigned int                                 : 2;
		unsigned int            DC_HPD_SENSE_DELAYED : 1;
		unsigned int                                 : 3;
		unsigned int            DC_HPD_RX_INT_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int DC_HPD_TOGGLE_FILT_CON_TIMER_VAL : 8;
		unsigned int                                 : 4;
		unsigned int DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_HPD_TOGGLE_FILT_CNTL__VI {
	struct {
		unsigned int        DC_HPD_CONNECT_INT_DELAY : 8;
		unsigned int                                 : 12;
		unsigned int     DC_HPD_DISCONNECT_INT_DELAY : 8;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDCVGA_HW_STATUS__VI {
	struct {
		unsigned int         DC_I2C_DDCVGA_HW_STATUS : 2;
		unsigned int                                 : 1;
		unsigned int           DC_I2C_DDCVGA_HW_DONE : 1;
		unsigned int                                 : 12;
		unsigned int            DC_I2C_DDCVGA_HW_REQ : 1;
		unsigned int            DC_I2C_DDCVGA_HW_URG : 1;
		unsigned int                                 : 2;
		unsigned int DC_I2C_DDCVGA_EDID_DETECT_STATUS : 1;
		unsigned int                                 : 3;
		unsigned int DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES : 4;
		unsigned int DC_I2C_DDCVGA_EDID_DETECT_STATE : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDCVGA_SETUP__VI {
	struct {
		unsigned int     DC_I2C_DDCVGA_DATA_DRIVE_EN : 1;
		unsigned int    DC_I2C_DDCVGA_DATA_DRIVE_SEL : 1;
		unsigned int                                 : 2;
		unsigned int DC_I2C_DDCVGA_EDID_DETECT_ENABLE : 1;
		unsigned int  DC_I2C_DDCVGA_EDID_DETECT_MODE : 1;
		unsigned int            DC_I2C_DDCVGA_ENABLE : 1;
		unsigned int      DC_I2C_DDCVGA_CLK_DRIVE_EN : 1;
		unsigned int  DC_I2C_DDCVGA_INTRA_BYTE_DELAY : 8;
		unsigned int DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY : 8;
		unsigned int        DC_I2C_DDCVGA_TIME_LIMIT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_DDCVGA_SPEED__VI {
	struct {
		unsigned int         DC_I2C_DDCVGA_THRESHOLD : 2;
		unsigned int                                 : 2;
		unsigned int DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL : 1;
		unsigned int                                 : 11;
		unsigned int          DC_I2C_DDCVGA_PRESCALE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_I2C_EDID_DETECT_CTRL__VI {
	struct {
		unsigned int    DC_I2C_EDID_DETECT_WAIT_TIME : 16;
		unsigned int                                 : 4;
		unsigned int DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID : 4;
		unsigned int                                 : 4;
		unsigned int   DC_I2C_EDID_DETECT_SEND_RESET : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_IP_REQUEST_CNTL__VI {
	struct {
		unsigned int                   IP_REQUEST_EN : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_LUT_VGA_ACCESS_ENABLE__VI {
	struct {
		unsigned int        DC_LUT_VGA_ACCESS_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_MEM_GLOBAL_PWR_REQ_CNTL__VI {
	struct {
		unsigned int       DC_MEM_GLOBAL_PWR_REQ_DIS : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_PGCNTL_STATUS_REG__VI {
	struct {
		unsigned int                 SWREQ_RWOP_BUSY : 1;
		unsigned int                SWREQ_RWOP_FORCE : 1;
		unsigned int             IPREQ_IGNORE_STATUS : 1;
		unsigned int                                 : 13;
		unsigned int                  DCPG_ECO_DEBUG : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_PGFSM_CONFIG_REG__VI {
	struct {
		unsigned int                PGFSM_CONFIG_REG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DC_PGFSM_WRITE_REG__VI {
	struct {
		unsigned int                 PGFSM_WRITE_REG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DEGAMMA_CONTROL__VI {
	struct {
		unsigned int               GRPH_DEGAMMA_MODE : 2;
		unsigned int                                 : 2;
		unsigned int                OVL_DEGAMMA_MODE : 2;
		unsigned int                                 : 2;
		unsigned int            CURSOR2_DEGAMMA_MODE : 2;
		unsigned int                                 : 2;
		unsigned int             CURSOR_DEGAMMA_MODE : 2;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DENORM_CLAMP_CONTROL__VI {
	struct {
		unsigned int                   DENORM_FACTOR : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DENORM_CLAMP_RANGE_B_CB__VI {
	struct {
		unsigned int            RANGE_CLAMP_MAX_B_CB : 12;
		unsigned int            RANGE_CLAMP_MIN_B_CB : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DENORM_CLAMP_RANGE_G_Y__VI {
	struct {
		unsigned int             RANGE_CLAMP_MAX_G_Y : 12;
		unsigned int             RANGE_CLAMP_MIN_G_Y : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DENORM_CLAMP_RANGE_R_CR__VI {
	struct {
		unsigned int            RANGE_CLAMP_MAX_R_CR : 12;
		unsigned int            RANGE_CLAMP_MIN_R_CR : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DENORM_CONTROL__VI {
	struct {
		unsigned int                     DENORM_MODE : 3;
		unsigned int                                 : 1;
		unsigned int                DENORM_14BIT_OUT : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DBR_CTRL0__VI {
	struct {
                unsigned int                    DIDT_CTRL_EN : 1;
                unsigned int                   USE_REF_CLOCK : 1;
                unsigned int                    PHASE_OFFSET : 2;
                unsigned int                   DIDT_CTRL_RST : 1;
                unsigned int            DIDT_CLK_EN_OVERRIDE : 1;
                unsigned int                                 : 6;
                unsigned int                                 : 6;
                unsigned int                        UNUSED_0 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DBR_CTRL1__VI {
	struct {
		unsigned int                       MIN_POWER : 16;
		unsigned int                       MAX_POWER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DBR_CTRL2__VI {
	struct {
		unsigned int                 MAX_POWER_DELTA : 14;
		unsigned int                        UNUSED_0 : 2;
		unsigned int        SHORT_TERM_INTERVAL_SIZE : 10;
		unsigned int                        UNUSED_1 : 1;
		unsigned int        LONG_TERM_INTERVAL_RATIO : 4;
		unsigned int                        UNUSED_2 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DBR_CTRL_OCP__VI {
	struct {
		unsigned int                        UNUSED_0 : 16;
		unsigned int                   OCP_MAX_POWER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DBR_WEIGHT0_3__VI {
	struct {
		unsigned int                         WEIGHT0 : 8;
		unsigned int                         WEIGHT1 : 8;
		unsigned int                         WEIGHT2 : 8;
		unsigned int                         WEIGHT3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DBR_WEIGHT4_7__VI {
	struct {
		unsigned int                         WEIGHT4 : 8;
		unsigned int                         WEIGHT5 : 8;
		unsigned int                         WEIGHT6 : 8;
		unsigned int                         WEIGHT7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DBR_WEIGHT8_11__VI {
	struct {
		unsigned int                         WEIGHT8 : 8;
		unsigned int                         WEIGHT9 : 8;
		unsigned int                        WEIGHT10 : 8;
		unsigned int                        WEIGHT11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_DB_CTRL_OCP__VI {
	struct {
		unsigned int                        UNUSED_0 : 16;
		unsigned int                   OCP_MAX_POWER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_SQ_CTRL_OCP__VI {
	struct {
		unsigned int                        UNUSED_0 : 16;
		unsigned int                   OCP_MAX_POWER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TCP_CTRL_OCP__VI {
	struct {
		unsigned int                        UNUSED_0 : 16;
		unsigned int                   OCP_MAX_POWER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIDT_TD_CTRL_OCP__VI {
	struct {
		unsigned int                        UNUSED_0 : 16;
		unsigned int                   OCP_MAX_POWER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_BE_CNTL__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int            DIG_FE_SOURCE_SELECT : 7;
		unsigned int                                 : 1;
		unsigned int                        DIG_MODE : 3;
		unsigned int                                 : 9;
		unsigned int                  DIG_HPD_SELECT : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_BE_EN_CNTL__VI {
	struct {
		unsigned int                      DIG_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int                DIG_SYMCLK_BE_ON : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_DISPCLK_SWITCH_CNTL__VI {
	struct {
		unsigned int        DIG_DISPCLK_SWITCH_POINT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_DISPCLK_SWITCH_STATUS__VI {
	struct {
		unsigned int      DIG_DISPCLK_SWITCH_ALLOWED : 1;
		unsigned int                                 : 3;
		unsigned int  DIG_DISPCLK_SWITCH_ALLOWED_INT : 1;
		unsigned int                                 : 3;
		unsigned int DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK : 1;
		unsigned int                                 : 3;
		unsigned int DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_FE_CNTL__VI {
	struct {
		unsigned int               DIG_SOURCE_SELECT : 3;
		unsigned int                                 : 1;
		unsigned int           DIG_STEREOSYNC_SELECT : 3;
		unsigned int                                 : 1;
		unsigned int          DIG_STEREOSYNC_GATE_EN : 1;
		unsigned int                                 : 1;
		unsigned int                       DIG_START : 1;
		unsigned int                                 : 5;
		unsigned int            DIG_DUAL_LINK_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                        DIG_SWAP : 1;
		unsigned int                                 : 1;
		unsigned int                DIG_RB_SWITCH_EN : 1;
		unsigned int                                 : 3;
		unsigned int                DIG_SYMCLK_FE_ON : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_FE_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int          DIG_FE_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_FE_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int         DIG_FE_TEST_DEBUG_INDEX : 8;
		unsigned int      DIG_FE_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_FIFO_STATUS__VI {
	struct {
		unsigned int            DIG_FIFO_LEVEL_ERROR : 1;
		unsigned int    DIG_FIFO_USE_OVERWRITE_LEVEL : 1;
		unsigned int        DIG_FIFO_OVERWRITE_LEVEL : 6;
		unsigned int              DIG_FIFO_ERROR_ACK : 1;
		unsigned int                                 : 1;
		unsigned int      DIG_FIFO_CAL_AVERAGE_LEVEL : 6;
		unsigned int          DIG_FIFO_MAXIMUM_LEVEL : 5;
		unsigned int                                 : 1;
		unsigned int          DIG_FIFO_MINIMUM_LEVEL : 4;
		unsigned int                                 : 3;
		unsigned int             DIG_FIFO_CALIBRATED : 1;
		unsigned int    DIG_FIFO_FORCE_RECAL_AVERAGE : 1;
		unsigned int    DIG_FIFO_FORCE_RECOMP_MINMAX : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_LANE_ENABLE__VI {
	struct {
		unsigned int                     DIG_LANE0EN : 1;
		unsigned int                     DIG_LANE1EN : 1;
		unsigned int                     DIG_LANE2EN : 1;
		unsigned int                     DIG_LANE3EN : 1;
		unsigned int                                 : 4;
		unsigned int                      DIG_CLK_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_SOFT_RESET__VI {
	struct {
		unsigned int              DIGA_FE_SOFT_RESET : 1;
		unsigned int              DIGA_BE_SOFT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int              DIGB_FE_SOFT_RESET : 1;
		unsigned int              DIGB_BE_SOFT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int              DIGC_FE_SOFT_RESET : 1;
		unsigned int              DIGC_BE_SOFT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int              DIGD_FE_SOFT_RESET : 1;
		unsigned int              DIGD_BE_SOFT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int              DIGE_FE_SOFT_RESET : 1;
		unsigned int              DIGE_BE_SOFT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int              DIGF_FE_SOFT_RESET : 1;
		unsigned int              DIGF_BE_SOFT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int              DIGG_FE_SOFT_RESET : 1;
		unsigned int              DIGG_BE_SOFT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                DPDBG_SOFT_RESET : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int             DIG_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DIG_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int            DIG_TEST_DEBUG_INDEX : 8;
		unsigned int         DIG_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISPCLK_FREQ_CHANGE_CNTL__VI {
	struct {
		unsigned int              DISPCLK_STEP_DELAY : 14;
		unsigned int                                 : 2;
		unsigned int               DISPCLK_STEP_SIZE : 4;
		unsigned int          DISPCLK_FREQ_RAMP_DONE : 1;
		unsigned int                                 : 4;
		unsigned int       DISPCLK_MAX_ERRDET_CYCLES : 3;
		unsigned int          DCCG_FIFO_ERRDET_RESET : 1;
		unsigned int          DCCG_FIFO_ERRDET_STATE : 1;
		unsigned int         DCCG_FIFO_ERRDET_OVR_EN : 1;
		unsigned int    DISPCLK_CHG_FWD_CORR_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISPPLL_BG_CNTL__VI {
	struct {
		unsigned int                  DISPPLL_BG_PDN : 1;
		unsigned int                                 : 3;
		unsigned int                  DISPPLL_BG_ADJ : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE3__VI {
	struct {
		unsigned int SCL_DISP4_MODE_CHANGE_INTERRUPT : 1;
		unsigned int D4BLND_DATA_UNDERFLOW_INTERRUPT : 1;
		unsigned int           LB_D4_VLINE_INTERRUPT : 1;
		unsigned int          LB_D4_VBLANK_INTERRUPT : 1;
		unsigned int        CRTC4_SNAPSHOT_INTERRUPT : 1;
		unsigned int CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1;
		unsigned int CRTC4_FORCE_COUNT_NOW_INTERRUPT : 1;
		unsigned int           CRTC4_TRIGA_INTERRUPT : 1;
		unsigned int           CRTC4_TRIGB_INTERRUPT : 1;
		unsigned int       CRTC4_VSYNC_NOM_INTERRUPT : 1;
		unsigned int CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1;
		unsigned int DIGD_DP_VID_STREAM_DISABLE_INTERRUPT : 1;
		unsigned int               DC_HPD4_INTERRUPT : 1;
		unsigned int            DC_HPD4_RX_INTERRUPT : 1;
		unsigned int          AUX4_SW_DONE_INTERRUPT : 1;
		unsigned int          AUX4_LS_DONE_INTERRUPT : 1;
		unsigned int           BUFMGR_IHIF_INTERRUPT : 1;
		unsigned int   WBSCL_HOST_CONFLICT_INTERRUPT : 1;
		unsigned int   WBSCL_DATA_OVERFLOW_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1;
		unsigned int CRTC3_EXT_TIMING_SYNC_INTERRUPT : 1;
		unsigned int CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1;
		unsigned int       CRTC3_VERTICAL_INTERRUPT0 : 1;
		unsigned int       CRTC3_VERTICAL_INTERRUPT1 : 1;
		unsigned int       CRTC3_VERTICAL_INTERRUPT2 : 1;
		unsigned int DISP_INTERRUPT_STATUS_CONTINUE4 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE4__VI {
	struct {
		unsigned int SCL_DISP5_MODE_CHANGE_INTERRUPT : 1;
		unsigned int D5BLND_DATA_UNDERFLOW_INTERRUPT : 1;
		unsigned int           LB_D5_VLINE_INTERRUPT : 1;
		unsigned int          LB_D5_VBLANK_INTERRUPT : 1;
		unsigned int        CRTC5_SNAPSHOT_INTERRUPT : 1;
		unsigned int CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1;
		unsigned int CRTC5_FORCE_COUNT_NOW_INTERRUPT : 1;
		unsigned int           CRTC5_TRIGA_INTERRUPT : 1;
		unsigned int           CRTC5_TRIGB_INTERRUPT : 1;
		unsigned int       CRTC5_VSYNC_NOM_INTERRUPT : 1;
		unsigned int CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1;
		unsigned int DIGE_DP_VID_STREAM_DISABLE_INTERRUPT : 1;
		unsigned int               DC_HPD5_INTERRUPT : 1;
		unsigned int            DC_HPD5_RX_INTERRUPT : 1;
		unsigned int          AUX5_SW_DONE_INTERRUPT : 1;
		unsigned int          AUX5_LS_DONE_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1;
		unsigned int CRTC4_EXT_TIMING_SYNC_INTERRUPT : 1;
		unsigned int CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1;
		unsigned int CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1;
		unsigned int CRTC5_EXT_TIMING_SYNC_INTERRUPT : 1;
		unsigned int CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1;
		unsigned int       CRTC4_VERTICAL_INTERRUPT0 : 1;
		unsigned int       CRTC4_VERTICAL_INTERRUPT1 : 1;
		unsigned int       CRTC4_VERTICAL_INTERRUPT2 : 1;
		unsigned int DISP_INTERRUPT_STATUS_CONTINUE5 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE5__VI {
	struct {
		unsigned int SCL_DISP6_MODE_CHANGE_INTERRUPT : 1;
		unsigned int D6BLND_DATA_UNDERFLOW_INTERRUPT : 1;
		unsigned int           LB_D6_VLINE_INTERRUPT : 1;
		unsigned int          LB_D6_VBLANK_INTERRUPT : 1;
		unsigned int        CRTC6_SNAPSHOT_INTERRUPT : 1;
		unsigned int CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1;
		unsigned int CRTC6_FORCE_COUNT_NOW_INTERRUPT : 1;
		unsigned int           CRTC6_TRIGA_INTERRUPT : 1;
		unsigned int           CRTC6_TRIGB_INTERRUPT : 1;
		unsigned int       CRTC6_VSYNC_NOM_INTERRUPT : 1;
		unsigned int CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1;
		unsigned int DIGF_DP_VID_STREAM_DISABLE_INTERRUPT : 1;
		unsigned int               DC_HPD6_INTERRUPT : 1;
		unsigned int            DC_HPD6_RX_INTERRUPT : 1;
		unsigned int          AUX6_SW_DONE_INTERRUPT : 1;
		unsigned int          AUX6_LS_DONE_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1;
		unsigned int CRTC6_EXT_TIMING_SYNC_INTERRUPT : 1;
		unsigned int CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1;
		unsigned int       CRTC5_VERTICAL_INTERRUPT0 : 1;
		unsigned int       CRTC5_VERTICAL_INTERRUPT1 : 1;
		unsigned int       CRTC5_VERTICAL_INTERRUPT2 : 1;
		unsigned int       CRTC6_VERTICAL_INTERRUPT0 : 1;
		unsigned int       CRTC6_VERTICAL_INTERRUPT1 : 1;
		unsigned int       CRTC6_VERTICAL_INTERRUPT2 : 1;
		unsigned int DISP_INTERRUPT_STATUS_CONTINUE6 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE6__VI {
	struct {
		unsigned int DCRX_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int DCRX_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int DCRX_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int DCRX_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int DCRX_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int DCRX_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int DCRX_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int DCRX_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DCRX_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int      BUFMGR_CWB0_IHIF_INTERRUPT : 1;
		unsigned int      BUFMGR_CWB1_IHIF_INTERRUPT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1;
		unsigned int DIGG_DP_VID_STREAM_DISABLE_INTERRUPT : 1;
		unsigned int AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT : 1;
		unsigned int   AUX1_GTC_SYNC_ERROR_INTERRUPT : 1;
		unsigned int AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT : 1;
		unsigned int   AUX2_GTC_SYNC_ERROR_INTERRUPT : 1;
		unsigned int AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT : 1;
		unsigned int   AUX3_GTC_SYNC_ERROR_INTERRUPT : 1;
		unsigned int AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT : 1;
		unsigned int   AUX4_GTC_SYNC_ERROR_INTERRUPT : 1;
		unsigned int AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT : 1;
		unsigned int   AUX5_GTC_SYNC_ERROR_INTERRUPT : 1;
		unsigned int AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT : 1;
		unsigned int   AUX6_GTC_SYNC_ERROR_INTERRUPT : 1;
		unsigned int                                 : 2;
		unsigned int DISP_INTERRUPT_STATUS_CONTINUE7 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE7__VI {
	struct {
		unsigned int DCCG_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int DCCG_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int DCCG_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int DCCG_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int DCCG_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int DCCG_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int DCCG_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int DCCG_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DCCG_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int  DCI_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int  DCI_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int  DCI_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int  DCI_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int  DCI_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int  DCI_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int  DCI_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int  DCI_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DCI_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int  DCO_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int  DCO_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int  DCO_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int  DCO_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int  DCO_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int  DCO_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int  DCO_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int  DCO_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DCO_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int   WB_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int   WB_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int   WB_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int   WB_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int DISP_INTERRUPT_STATUS_CONTINUE8 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE8__VI {
	struct {
		unsigned int DCFE0_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int DCFE0_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int DCFE0_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int DCFE0_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int DCFE0_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int DCFE0_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int DCFE0_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int DCFE0_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DCFE0_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int DCFE1_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int DCFE1_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int DCFE1_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int DCFE1_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int DCFE1_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int DCFE1_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int DCFE1_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int DCFE1_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DCFE1_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int DCFE2_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int DCFE2_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int DCFE2_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int DCFE2_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int DCFE2_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int DCFE2_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int DCFE2_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int DCFE2_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DCFE2_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int   WB_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int   WB_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int   WB_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int   WB_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DISP_INTERRUPT_STATUS_CONTINUE9 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DISP_INTERRUPT_STATUS_CONTINUE9__VI {
	struct {
		unsigned int DCFE3_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int DCFE3_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int DCFE3_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int DCFE3_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int DCFE3_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int DCFE3_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int DCFE3_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int DCFE3_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DCFE3_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int DCFE4_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int DCFE4_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int DCFE4_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int DCFE4_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int DCFE4_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int DCFE4_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int DCFE4_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int DCFE4_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DCFE4_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int DCFE5_PERFMON_COUNTER0_INTERRUPT : 1;
		unsigned int DCFE5_PERFMON_COUNTER1_INTERRUPT : 1;
		unsigned int DCFE5_PERFMON_COUNTER2_INTERRUPT : 1;
		unsigned int DCFE5_PERFMON_COUNTER3_INTERRUPT : 1;
		unsigned int DCFE5_PERFMON_COUNTER4_INTERRUPT : 1;
		unsigned int DCFE5_PERFMON_COUNTER5_INTERRUPT : 1;
		unsigned int DCFE5_PERFMON_COUNTER6_INTERRUPT : 1;
		unsigned int DCFE5_PERFMON_COUNTER7_INTERRUPT : 1;
		unsigned int DCFE5_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int WB_PERFMON_COUNTER_OFF_INTERRUPT : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_DPRX_INTERRUPT_STATUS1__VI {
	struct {
		unsigned int DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED : 1;
		unsigned int DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED : 1;
		unsigned int DPRX_SD0P0_VERTICAL_INT0_OCCURRED : 1;
		unsigned int DPRX_SD0P0_VERTICAL_INT1_OCCURRED : 1;
		unsigned int DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED : 1;
		unsigned int DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED : 1;
		unsigned int DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED : 1;
		unsigned int DPRX_SD1P0_VERTICAL_INT0_OCCURRED : 1;
		unsigned int DPRX_SD1P0_VERTICAL_INT1_OCCURRED : 1;
		unsigned int DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED : 1;
		unsigned int DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED : 1;
		unsigned int    DPRX_AUX_P0_AUX_INT_OCCURRED : 1;
		unsigned int    DPRX_AUX_P0_I2C_INT_OCCURRED : 1;
		unsigned int    DPRX_AUX_P0_CPU_INT_OCCURRED : 1;
		unsigned int DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED : 1;
		unsigned int DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED : 1;
		unsigned int DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED : 1;
		unsigned int DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__VI {
	struct {
		unsigned int DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN : 1;
		unsigned int DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN : 1;
		unsigned int DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN : 1;
		unsigned int DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN : 1;
		unsigned int DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN : 1;
		unsigned int DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN : 1;
		unsigned int DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN : 1;
		unsigned int DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN : 1;
		unsigned int DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN : 1;
		unsigned int DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN : 1;
		unsigned int DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN : 1;
		unsigned int    DPRX_AUX_P0_AUX_INT_TO_UC_EN : 1;
		unsigned int    DPRX_AUX_P0_I2C_INT_TO_UC_EN : 1;
		unsigned int    DPRX_AUX_P0_CPU_INT_TO_UC_EN : 1;
		unsigned int DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN : 1;
		unsigned int DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN : 1;
		unsigned int DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN : 1;
		unsigned int DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI {
	struct {
		unsigned int DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_STATUS1__VI {
	struct {
		unsigned int DCI_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCI_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCI_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCI_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCI_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCI_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCI_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCI_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCO_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCO_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCO_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCO_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCO_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCO_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCO_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCO_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCCG_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCCG_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCCG_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCCG_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCCG_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCCG_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCCG_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCCG_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCI_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int DCO_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_STATUS2__VI {
	struct {
		unsigned int DCFE0_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCFE0_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCFE0_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCFE0_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCFE0_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCFE0_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCFE0_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCFE0_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCFE1_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCFE1_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCFE1_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCFE1_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCFE1_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCFE1_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCFE1_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCFE1_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCFE2_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCFE2_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCFE2_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCFE2_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCFE2_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCFE2_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCFE2_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCFE2_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_STATUS3__VI {
	struct {
		unsigned int DCFE3_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCFE3_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCFE3_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCFE3_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCFE3_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCFE3_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCFE3_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCFE3_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCFE4_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCFE4_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCFE4_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCFE4_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCFE4_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCFE4_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCFE4_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCFE4_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCFE5_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCFE5_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCFE5_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCFE5_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCFE5_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCFE5_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCFE5_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCFE5_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_STATUS4__VI {
	struct {
		unsigned int WB_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int WB_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int WB_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int WB_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int WB_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int WB_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int WB_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int WB_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCRX_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCRX_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCRX_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCRX_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCRX_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCRX_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCRX_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCRX_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int                                 : 8;
		unsigned int WB_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_STATUS5__VI {
	struct {
		unsigned int DCFEV_PERFMON_COUNTER0_INT_OCCURRED : 1;
		unsigned int DCFEV_PERFMON_COUNTER1_INT_OCCURRED : 1;
		unsigned int DCFEV_PERFMON_COUNTER2_INT_OCCURRED : 1;
		unsigned int DCFEV_PERFMON_COUNTER3_INT_OCCURRED : 1;
		unsigned int DCFEV_PERFMON_COUNTER4_INT_OCCURRED : 1;
		unsigned int DCFEV_PERFMON_COUNTER5_INT_OCCURRED : 1;
		unsigned int DCFEV_PERFMON_COUNTER6_INT_OCCURRED : 1;
		unsigned int DCFEV_PERFMON_COUNTER7_INT_OCCURRED : 1;
		unsigned int DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__VI {
	struct {
		unsigned int   DCI_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int   DCI_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int   DCI_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int   DCI_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int   DCI_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int   DCI_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int   DCI_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int   DCI_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int   DCO_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int   DCO_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int   DCO_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int   DCO_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int   DCO_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int   DCO_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int   DCO_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int   DCO_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int  DCCG_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int  DCCG_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int  DCCG_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int  DCCG_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int  DCCG_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int  DCCG_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int  DCCG_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int  DCCG_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int DCI_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int DCO_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int DCCG_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__VI {
	struct {
		unsigned int DCFE0_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int DCFE0_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int DCFE0_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int DCFE0_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int DCFE0_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int DCFE0_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int DCFE0_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int DCFE0_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int DCFE1_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int DCFE1_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int DCFE1_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int DCFE1_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int DCFE1_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int DCFE1_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int DCFE1_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int DCFE1_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int DCFE2_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int DCFE2_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int DCFE2_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int DCFE2_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int DCFE2_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int DCFE2_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int DCFE2_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int DCFE2_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int DCFE0_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int DCFE1_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int DCFE2_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__VI {
	struct {
		unsigned int DCFE3_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int DCFE3_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int DCFE3_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int DCFE3_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int DCFE3_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int DCFE3_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int DCFE3_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int DCFE3_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int DCFE4_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int DCFE4_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int DCFE4_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int DCFE4_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int DCFE4_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int DCFE4_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int DCFE4_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int DCFE4_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int DCFE5_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int DCFE5_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int DCFE5_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int DCFE5_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int DCFE5_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int DCFE5_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int DCFE5_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int DCFE5_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int DCFE3_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int DCFE4_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int DCFE5_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__VI {
	struct {
		unsigned int    WB_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int    WB_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int    WB_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int    WB_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int    WB_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int    WB_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int    WB_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int    WB_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int  DCRX_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int  DCRX_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int  DCRX_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int  DCRX_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int  DCRX_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int  DCRX_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int  DCRX_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int  DCRX_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int                                 : 8;
		unsigned int WB_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int DCRX_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__VI {
	struct {
		unsigned int DCFEV_PERFMON_COUNTER0_INT_MASK : 1;
		unsigned int DCFEV_PERFMON_COUNTER1_INT_MASK : 1;
		unsigned int DCFEV_PERFMON_COUNTER2_INT_MASK : 1;
		unsigned int DCFEV_PERFMON_COUNTER3_INT_MASK : 1;
		unsigned int DCFEV_PERFMON_COUNTER4_INT_MASK : 1;
		unsigned int DCFEV_PERFMON_COUNTER5_INT_MASK : 1;
		unsigned int DCFEV_PERFMON_COUNTER6_INT_MASK : 1;
		unsigned int DCFEV_PERFMON_COUNTER7_INT_MASK : 1;
		unsigned int DCFEV_PERFMON_COUNTER_OFF_INT_MASK : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__VI {
	struct {
		unsigned int DCI_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCI_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCI_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCI_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCI_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCI_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCI_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCI_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCO_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCO_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCO_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCO_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCO_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCO_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCO_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCO_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCCG_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCCG_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCCG_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCCG_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCCG_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCCG_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCCG_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCCG_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__VI {
	struct {
		unsigned int DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__VI {
	struct {
		unsigned int DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__VI {
	struct {
		unsigned int WB_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int WB_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int WB_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int WB_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int WB_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int WB_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int WB_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int WB_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCRX_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCRX_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCRX_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCRX_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCRX_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCRX_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCRX_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCRX_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int                                 : 8;
		unsigned int WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__VI {
	struct {
		unsigned int DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN : 1;
		unsigned int DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN : 1;
		unsigned int DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN : 1;
		unsigned int DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN : 1;
		unsigned int DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN : 1;
		unsigned int DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN : 1;
		unsigned int DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN : 1;
		unsigned int DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN : 1;
		unsigned int DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI {
	struct {
		unsigned int DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__VI {
	struct {
		unsigned int DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__VI {
	struct {
		unsigned int DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__VI {
	struct {
		unsigned int WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int                                 : 8;
		unsigned int WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__VI {
	struct {
		unsigned int DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1;
		unsigned int DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_SMU_INTERRUPT_CNTL__VI {
	struct {
		unsigned int      DMCU_SMU_STATIC_SCREEN_INT : 1;
		unsigned int                                 : 15;
		unsigned int   DMCU_SMU_STATIC_SCREEN_STATUS : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_SS_INTERRUPT_CNTL_STATUS__VI {
	struct {
		unsigned int                                 : 13;
		unsigned int       STATIC_SCREEN1_INT_STATUS : 1;
		unsigned int     STATIC_SCREEN1_INT_OCCURRED : 1;
		unsigned int       STATIC_SCREEN2_INT_STATUS : 1;
		unsigned int     STATIC_SCREEN2_INT_OCCURRED : 1;
		unsigned int       STATIC_SCREEN3_INT_STATUS : 1;
		unsigned int     STATIC_SCREEN3_INT_OCCURRED : 1;
		unsigned int       STATIC_SCREEN4_INT_STATUS : 1;
		unsigned int     STATIC_SCREEN4_INT_OCCURRED : 1;
		unsigned int       STATIC_SCREEN5_INT_STATUS : 1;
		unsigned int     STATIC_SCREEN5_INT_OCCURRED : 1;
		unsigned int       STATIC_SCREEN6_INT_STATUS : 1;
		unsigned int     STATIC_SCREEN6_INT_OCCURRED : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMCU_UC_CLK_GATING_CNTL__VI {
	struct {
		unsigned int                UC_IRAM_RD_DELAY : 3;
		unsigned int                                 : 5;
		unsigned int                UC_ERAM_RD_DELAY : 3;
		unsigned int                                 : 5;
		unsigned int        UC_RBBM_RD_CLK_GATING_EN : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_ADDR_CALC__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int ADDR_CONFIG_PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 21;
		unsigned int            ADDR_CONFIG_ROW_SIZE : 2;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_ADDR_CONFIG__VI {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 9;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_DEBUG02_CORE0__VI {
	struct {
		unsigned int                         DB_DATA : 16;
		unsigned int               MC_RDRET_COUNT_EN : 1;
		unsigned int                MC_RDRET_COUNTER : 11;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_DEBUG02_CORE1__VI {
	struct {
		unsigned int                         DB_DATA : 16;
		unsigned int               MC_RDRET_COUNT_EN : 1;
		unsigned int                MC_RDRET_COUNTER : 11;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_P_VMID__VI {
	struct {
		unsigned int                    P_VMID_PIPE0 : 4;
		unsigned int                    P_VMID_PIPE1 : 4;
		unsigned int                    P_VMID_PIPE2 : 4;
		unsigned int                    P_VMID_PIPE3 : 4;
		unsigned int                    P_VMID_PIPE4 : 4;
		unsigned int                    P_VMID_PIPE5 : 4;
		unsigned int                    P_VMID_PIPE6 : 4;
		unsigned int                    P_VMID_PIPE7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_STATUS2__VI {
	struct {
		unsigned int       DMIF_PIPE0_DISPCLK_STATUS : 1;
		unsigned int       DMIF_PIPE1_DISPCLK_STATUS : 1;
		unsigned int       DMIF_PIPE2_DISPCLK_STATUS : 1;
		unsigned int       DMIF_PIPE3_DISPCLK_STATUS : 1;
		unsigned int       DMIF_PIPE4_DISPCLK_STATUS : 1;
		unsigned int       DMIF_PIPE5_DISPCLK_STATUS : 1;
		unsigned int                                 : 2;
		unsigned int  DMIF_CHUNK_TRACKER_SCLK_STATUS : 1;
		unsigned int    DMIF_FBC_TRACKER_SCLK_STATUS : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DMIF_URG_OVERRIDE__VI {
	struct {
		unsigned int            DMIF_URG_OVERRIDE_EN : 1;
		unsigned int                                 : 3;
		unsigned int         DMIF_URG_OVERRIDE_LEVEL : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPDBG_CLK_FORCE_CONTROL__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int              DPDBG_CLK_FORCE_EN : 1;
		unsigned int                                 : 3;
		unsigned int             DPDBG_CLK_FORCE_SRC : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPDBG_CNTL__VI {
	struct {
		unsigned int                    DPDBG_ENABLE : 1;
		unsigned int              DPDBG_INPUT_ENABLE : 1;
		unsigned int                                 : 2;
		unsigned int                 DPDBG_SYMCLK_ON : 1;
		unsigned int                                 : 3;
		unsigned int      DPDBG_ERROR_DETECTION_MODE : 1;
		unsigned int                                 : 7;
		unsigned int               DPDBG_LINE_LENGTH : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPDBG_INTERRUPT__VI {
	struct {
		unsigned int    DPDBG_FIFO_OVERFLOW_INT_MASK : 1;
		unsigned int    DPDBG_FIFO_OVERFLOW_INT_TYPE : 1;
		unsigned int                                 : 6;
		unsigned int     DPDBG_FIFO_OVERFLOW_INT_ACK : 1;
		unsigned int                                 : 7;
		unsigned int    DPDBG_FIFO_OVERFLOW_OCCURRED : 1;
		unsigned int                                 : 7;
		unsigned int  DPDBG_FIFO_OVERFLOW_INT_STATUS : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_HW_DEBUG_11__VI {
	struct {
		unsigned int                 DPG_HW_DEBUG_11 : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_HW_DEBUG_A__VI {
	struct {
		unsigned int                  DPG_HW_DEBUG_A : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_HW_DEBUG_B__VI {
	struct {
		unsigned int                  DPG_HW_DEBUG_B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_PIPE_ARBITRATION_CONTROL1__VI {
	struct {
		unsigned int                  PIXEL_DURATION : 16;
		unsigned int                     BASE_WEIGHT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_PIPE_ARBITRATION_CONTROL2__VI {
	struct {
		unsigned int                     TIME_WEIGHT : 16;
		unsigned int                  URGENCY_WEIGHT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_PIPE_DPM_CONTROL__VI {
	struct {
		unsigned int                      DPM_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int              MCLK_CHANGE_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int            MCLK_CHANGE_FORCE_ON : 1;
		unsigned int                                 : 3;
		unsigned int      MCLK_CHANGE_WATERMARK_MASK : 2;
		unsigned int                                 : 2;
		unsigned int           MCLK_CHANGE_WATERMARK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI {
	struct {
		unsigned int         NB_PSTATE_CHANGE_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int NB_PSTATE_CHANGE_URGENT_DURING_REQUEST : 1;
		unsigned int                                 : 3;
		unsigned int NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST : 1;
		unsigned int       NB_PSTATE_CHANGE_FORCE_ON : 1;
		unsigned int      NB_PSTATE_ALLOW_FOR_URGENT : 1;
		unsigned int                                 : 5;
		unsigned int      NB_PSTATE_CHANGE_WATERMARK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_PIPE_STUTTER_CONTROL__VI {
	struct {
		unsigned int                  STUTTER_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int           STUTTER_IGNORE_CURSOR : 1;
		unsigned int             STUTTER_IGNORE_ICON : 1;
		unsigned int              STUTTER_IGNORE_VGA : 1;
		unsigned int              STUTTER_IGNORE_FBC : 1;
		unsigned int        STUTTER_WM_HIGH_FORCE_ON : 1;
		unsigned int STUTTER_WM_HIGH_EXCLUDES_VBLANK : 1;
		unsigned int STUTTER_URGENT_IN_NOT_SELF_REFRESH : 1;
		unsigned int   STUTTER_SELF_REFRESH_FORCE_ON : 1;
		unsigned int                                 : 4;
		unsigned int STUTTER_EXIT_SELF_REFRESH_WATERMARK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI {
	struct {
		unsigned int         STUTTER_ENABLE_NONLPTCH : 1;
		unsigned int                                 : 3;
		unsigned int  STUTTER_IGNORE_CURSOR_NONLPTCH : 1;
		unsigned int    STUTTER_IGNORE_ICON_NONLPTCH : 1;
		unsigned int     STUTTER_IGNORE_VGA_NONLPTCH : 1;
		unsigned int     STUTTER_IGNORE_FBC_NONLPTCH : 1;
		unsigned int STUTTER_WM_HIGH_FORCE_ON_NONLPTCH : 1;
		unsigned int STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH : 1;
		unsigned int STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH : 1;
		unsigned int STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_PIPE_URGENCY_CONTROL__VI {
	struct {
		unsigned int           URGENCY_LOW_WATERMARK : 16;
		unsigned int          URGENCY_HIGH_WATERMARK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_REPEATER_PROGRAM__VI {
	struct {
		unsigned int         REG_DPG_DMIFRC_REPEATER : 3;
		unsigned int                                 : 1;
		unsigned int         REG_DMIFRC_DPG_REPEATER : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int             DPG_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int            DPG_TEST_DEBUG_INDEX : 8;
		unsigned int         DPG_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPG_WATERMARK_MASK_CONTROL__VI {
	struct {
		unsigned int STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK : 2;
		unsigned int                                 : 6;
		unsigned int          URGENCY_WATERMARK_MASK : 2;
		unsigned int                                 : 6;
		unsigned int NB_PSTATE_CHANGE_WATERMARK_MASK : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED0__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED1__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED10__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED11__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED12__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED13__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED14__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED15__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED16__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED17__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED18__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED19__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED2__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED20__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED21__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED22__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED23__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED24__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED25__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED26__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED27__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED28__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED29__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED3__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED30__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED31__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED32__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED33__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED34__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED35__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED36__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED37__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED38__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED39__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED4__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED40__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED41__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED42__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED43__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED44__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED45__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED46__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED47__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED48__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED49__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED5__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED50__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED51__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED52__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED53__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED54__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED55__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED56__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED57__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED58__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED59__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED6__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED60__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED61__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED62__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED63__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED7__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED8__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPHY_MACRO_CNTL_RESERVED9__VI {
	struct {
		unsigned int        DPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_1__VI {
	struct {
		unsigned int        GraphicsPIDController_Ki : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_10__VI {
	struct {
		unsigned int          MemoryPIDController_Ki : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_100__VI {
	struct {
		unsigned int GraphicsLevel_0_SpllSpreadSpectrum : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_101__VI {
	struct {
		unsigned int GraphicsLevel_0_SpllSpreadSpectrum2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_102__VI {
	struct {
		unsigned int      GraphicsLevel_0_CcPwrDynRm : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_103__VI {
	struct {
		unsigned int     GraphicsLevel_0_CcPwrDynRm1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_104__VI {
	struct {
		unsigned int GraphicsLevel_0_EnabledForThrottle : 8;
		unsigned int GraphicsLevel_0_EnabledForActivity : 8;
		unsigned int GraphicsLevel_0_DisplayWatermark : 8;
		unsigned int         GraphicsLevel_0_SclkDid : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_105__VI {
	struct {
		unsigned int   GraphicsLevel_0_PowerThrottle : 8;
		unsigned int GraphicsLevel_0_VoltageDownHyst : 8;
		unsigned int        GraphicsLevel_0_DownHyst : 8;
		unsigned int          GraphicsLevel_0_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_106__VI {
	struct {
		unsigned int GraphicsLevel_1_MinVoltage_Phases : 8;
		unsigned int GraphicsLevel_1_MinVoltage_VddGfx : 8;
		unsigned int GraphicsLevel_1_MinVoltage_Vddci : 8;
		unsigned int GraphicsLevel_1_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_107__VI {
	struct {
		unsigned int   GraphicsLevel_1_SclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_108__VI {
	struct {
		unsigned int   GraphicsLevel_1_ActivityLevel : 16;
		unsigned int  GraphicsLevel_1_DeepSleepDivId : 8;
		unsigned int    GraphicsLevel_1_pcieDpmLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_109__VI {
	struct {
		unsigned int GraphicsLevel_1_CgSpllFuncCntl3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_11__VI {
	struct {
		unsigned int MemoryPIDController_LFWindupUpperLim : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_110__VI {
	struct {
		unsigned int GraphicsLevel_1_CgSpllFuncCntl4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_111__VI {
	struct {
		unsigned int GraphicsLevel_1_SpllSpreadSpectrum : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_112__VI {
	struct {
		unsigned int GraphicsLevel_1_SpllSpreadSpectrum2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_113__VI {
	struct {
		unsigned int      GraphicsLevel_1_CcPwrDynRm : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_114__VI {
	struct {
		unsigned int     GraphicsLevel_1_CcPwrDynRm1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_115__VI {
	struct {
		unsigned int GraphicsLevel_1_EnabledForThrottle : 8;
		unsigned int GraphicsLevel_1_EnabledForActivity : 8;
		unsigned int GraphicsLevel_1_DisplayWatermark : 8;
		unsigned int         GraphicsLevel_1_SclkDid : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_116__VI {
	struct {
		unsigned int   GraphicsLevel_1_PowerThrottle : 8;
		unsigned int GraphicsLevel_1_VoltageDownHyst : 8;
		unsigned int        GraphicsLevel_1_DownHyst : 8;
		unsigned int          GraphicsLevel_1_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_117__VI {
	struct {
		unsigned int GraphicsLevel_2_MinVoltage_Phases : 8;
		unsigned int GraphicsLevel_2_MinVoltage_VddGfx : 8;
		unsigned int GraphicsLevel_2_MinVoltage_Vddci : 8;
		unsigned int GraphicsLevel_2_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_118__VI {
	struct {
		unsigned int   GraphicsLevel_2_SclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_119__VI {
	struct {
		unsigned int   GraphicsLevel_2_ActivityLevel : 16;
		unsigned int  GraphicsLevel_2_DeepSleepDivId : 8;
		unsigned int    GraphicsLevel_2_pcieDpmLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_12__VI {
	struct {
		unsigned int MemoryPIDController_LFWindupLowerLim : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_120__VI {
	struct {
		unsigned int GraphicsLevel_2_CgSpllFuncCntl3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_121__VI {
	struct {
		unsigned int GraphicsLevel_2_CgSpllFuncCntl4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_122__VI {
	struct {
		unsigned int GraphicsLevel_2_SpllSpreadSpectrum : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_123__VI {
	struct {
		unsigned int GraphicsLevel_2_SpllSpreadSpectrum2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_124__VI {
	struct {
		unsigned int      GraphicsLevel_2_CcPwrDynRm : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_125__VI {
	struct {
		unsigned int     GraphicsLevel_2_CcPwrDynRm1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_126__VI {
	struct {
		unsigned int GraphicsLevel_2_EnabledForThrottle : 8;
		unsigned int GraphicsLevel_2_EnabledForActivity : 8;
		unsigned int GraphicsLevel_2_DisplayWatermark : 8;
		unsigned int         GraphicsLevel_2_SclkDid : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_127__VI {
	struct {
		unsigned int   GraphicsLevel_2_PowerThrottle : 8;
		unsigned int GraphicsLevel_2_VoltageDownHyst : 8;
		unsigned int        GraphicsLevel_2_DownHyst : 8;
		unsigned int          GraphicsLevel_2_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_128__VI {
	struct {
		unsigned int GraphicsLevel_3_MinVoltage_Phases : 8;
		unsigned int GraphicsLevel_3_MinVoltage_VddGfx : 8;
		unsigned int GraphicsLevel_3_MinVoltage_Vddci : 8;
		unsigned int GraphicsLevel_3_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_129__VI {
	struct {
		unsigned int   GraphicsLevel_3_SclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_13__VI {
	struct {
		unsigned int MemoryPIDController_StatePrecision : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_130__VI {
	struct {
		unsigned int   GraphicsLevel_3_ActivityLevel : 16;
		unsigned int  GraphicsLevel_3_DeepSleepDivId : 8;
		unsigned int    GraphicsLevel_3_pcieDpmLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_131__VI {
	struct {
		unsigned int GraphicsLevel_3_CgSpllFuncCntl3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_132__VI {
	struct {
		unsigned int GraphicsLevel_3_CgSpllFuncCntl4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_133__VI {
	struct {
		unsigned int GraphicsLevel_3_SpllSpreadSpectrum : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_134__VI {
	struct {
		unsigned int GraphicsLevel_3_SpllSpreadSpectrum2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_135__VI {
	struct {
		unsigned int      GraphicsLevel_3_CcPwrDynRm : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_136__VI {
	struct {
		unsigned int     GraphicsLevel_3_CcPwrDynRm1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_137__VI {
	struct {
		unsigned int GraphicsLevel_3_EnabledForThrottle : 8;
		unsigned int GraphicsLevel_3_EnabledForActivity : 8;
		unsigned int GraphicsLevel_3_DisplayWatermark : 8;
		unsigned int         GraphicsLevel_3_SclkDid : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_138__VI {
	struct {
		unsigned int   GraphicsLevel_3_PowerThrottle : 8;
		unsigned int GraphicsLevel_3_VoltageDownHyst : 8;
		unsigned int        GraphicsLevel_3_DownHyst : 8;
		unsigned int          GraphicsLevel_3_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_139__VI {
	struct {
		unsigned int GraphicsLevel_4_MinVoltage_Phases : 8;
		unsigned int GraphicsLevel_4_MinVoltage_VddGfx : 8;
		unsigned int GraphicsLevel_4_MinVoltage_Vddci : 8;
		unsigned int GraphicsLevel_4_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_14__VI {
	struct {
		unsigned int MemoryPIDController_LfPrecision : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_140__VI {
	struct {
		unsigned int   GraphicsLevel_4_SclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_141__VI {
	struct {
		unsigned int   GraphicsLevel_4_ActivityLevel : 16;
		unsigned int  GraphicsLevel_4_DeepSleepDivId : 8;
		unsigned int    GraphicsLevel_4_pcieDpmLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_142__VI {
	struct {
		unsigned int GraphicsLevel_4_CgSpllFuncCntl3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_143__VI {
	struct {
		unsigned int GraphicsLevel_4_CgSpllFuncCntl4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_144__VI {
	struct {
		unsigned int GraphicsLevel_4_SpllSpreadSpectrum : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_145__VI {
	struct {
		unsigned int GraphicsLevel_4_SpllSpreadSpectrum2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_146__VI {
	struct {
		unsigned int      GraphicsLevel_4_CcPwrDynRm : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_147__VI {
	struct {
		unsigned int     GraphicsLevel_4_CcPwrDynRm1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_148__VI {
	struct {
		unsigned int GraphicsLevel_4_EnabledForThrottle : 8;
		unsigned int GraphicsLevel_4_EnabledForActivity : 8;
		unsigned int GraphicsLevel_4_DisplayWatermark : 8;
		unsigned int         GraphicsLevel_4_SclkDid : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_149__VI {
	struct {
		unsigned int   GraphicsLevel_4_PowerThrottle : 8;
		unsigned int GraphicsLevel_4_VoltageDownHyst : 8;
		unsigned int        GraphicsLevel_4_DownHyst : 8;
		unsigned int          GraphicsLevel_4_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_15__VI {
	struct {
		unsigned int    MemoryPIDController_LfOffset : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_150__VI {
	struct {
		unsigned int GraphicsLevel_5_MinVoltage_Phases : 8;
		unsigned int GraphicsLevel_5_MinVoltage_VddGfx : 8;
		unsigned int GraphicsLevel_5_MinVoltage_Vddci : 8;
		unsigned int GraphicsLevel_5_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_151__VI {
	struct {
		unsigned int   GraphicsLevel_5_SclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_152__VI {
	struct {
		unsigned int   GraphicsLevel_5_ActivityLevel : 16;
		unsigned int  GraphicsLevel_5_DeepSleepDivId : 8;
		unsigned int    GraphicsLevel_5_pcieDpmLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_153__VI {
	struct {
		unsigned int GraphicsLevel_5_CgSpllFuncCntl3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_154__VI {
	struct {
		unsigned int GraphicsLevel_5_CgSpllFuncCntl4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_155__VI {
	struct {
		unsigned int GraphicsLevel_5_SpllSpreadSpectrum : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_156__VI {
	struct {
		unsigned int GraphicsLevel_5_SpllSpreadSpectrum2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_157__VI {
	struct {
		unsigned int      GraphicsLevel_5_CcPwrDynRm : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_158__VI {
	struct {
		unsigned int     GraphicsLevel_5_CcPwrDynRm1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_159__VI {
	struct {
		unsigned int GraphicsLevel_5_EnabledForThrottle : 8;
		unsigned int GraphicsLevel_5_EnabledForActivity : 8;
		unsigned int GraphicsLevel_5_DisplayWatermark : 8;
		unsigned int         GraphicsLevel_5_SclkDid : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_16__VI {
	struct {
		unsigned int    MemoryPIDController_MaxState : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_160__VI {
	struct {
		unsigned int   GraphicsLevel_5_PowerThrottle : 8;
		unsigned int GraphicsLevel_5_VoltageDownHyst : 8;
		unsigned int        GraphicsLevel_5_DownHyst : 8;
		unsigned int          GraphicsLevel_5_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_161__VI {
	struct {
		unsigned int GraphicsLevel_6_MinVoltage_Phases : 8;
		unsigned int GraphicsLevel_6_MinVoltage_VddGfx : 8;
		unsigned int GraphicsLevel_6_MinVoltage_Vddci : 8;
		unsigned int GraphicsLevel_6_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_162__VI {
	struct {
		unsigned int   GraphicsLevel_6_SclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_163__VI {
	struct {
		unsigned int   GraphicsLevel_6_ActivityLevel : 16;
		unsigned int  GraphicsLevel_6_DeepSleepDivId : 8;
		unsigned int    GraphicsLevel_6_pcieDpmLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_164__VI {
	struct {
		unsigned int GraphicsLevel_6_CgSpllFuncCntl3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_165__VI {
	struct {
		unsigned int GraphicsLevel_6_CgSpllFuncCntl4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_166__VI {
	struct {
		unsigned int GraphicsLevel_6_SpllSpreadSpectrum : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_167__VI {
	struct {
		unsigned int GraphicsLevel_6_SpllSpreadSpectrum2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_168__VI {
	struct {
		unsigned int      GraphicsLevel_6_CcPwrDynRm : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_169__VI {
	struct {
		unsigned int     GraphicsLevel_6_CcPwrDynRm1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_17__VI {
	struct {
		unsigned int MemoryPIDController_MaxLfFraction : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_170__VI {
	struct {
		unsigned int GraphicsLevel_6_EnabledForThrottle : 8;
		unsigned int GraphicsLevel_6_EnabledForActivity : 8;
		unsigned int GraphicsLevel_6_DisplayWatermark : 8;
		unsigned int         GraphicsLevel_6_SclkDid : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_171__VI {
	struct {
		unsigned int   GraphicsLevel_6_PowerThrottle : 8;
		unsigned int GraphicsLevel_6_VoltageDownHyst : 8;
		unsigned int        GraphicsLevel_6_DownHyst : 8;
		unsigned int          GraphicsLevel_6_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_172__VI {
	struct {
		unsigned int GraphicsLevel_7_MinVoltage_Phases : 8;
		unsigned int GraphicsLevel_7_MinVoltage_VddGfx : 8;
		unsigned int GraphicsLevel_7_MinVoltage_Vddci : 8;
		unsigned int GraphicsLevel_7_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_173__VI {
	struct {
		unsigned int   GraphicsLevel_7_SclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_174__VI {
	struct {
		unsigned int   GraphicsLevel_7_ActivityLevel : 16;
		unsigned int  GraphicsLevel_7_DeepSleepDivId : 8;
		unsigned int    GraphicsLevel_7_pcieDpmLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_175__VI {
	struct {
		unsigned int GraphicsLevel_7_CgSpllFuncCntl3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_176__VI {
	struct {
		unsigned int GraphicsLevel_7_CgSpllFuncCntl4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_177__VI {
	struct {
		unsigned int GraphicsLevel_7_SpllSpreadSpectrum : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_178__VI {
	struct {
		unsigned int GraphicsLevel_7_SpllSpreadSpectrum2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_179__VI {
	struct {
		unsigned int      GraphicsLevel_7_CcPwrDynRm : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_18__VI {
	struct {
		unsigned int  MemoryPIDController_StateShift : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_180__VI {
	struct {
		unsigned int     GraphicsLevel_7_CcPwrDynRm1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_181__VI {
	struct {
		unsigned int GraphicsLevel_7_EnabledForThrottle : 8;
		unsigned int GraphicsLevel_7_EnabledForActivity : 8;
		unsigned int GraphicsLevel_7_DisplayWatermark : 8;
		unsigned int         GraphicsLevel_7_SclkDid : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_182__VI {
	struct {
		unsigned int   GraphicsLevel_7_PowerThrottle : 8;
		unsigned int GraphicsLevel_7_VoltageDownHyst : 8;
		unsigned int        GraphicsLevel_7_DownHyst : 8;
		unsigned int          GraphicsLevel_7_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_183__VI {
	struct {
		unsigned int MemoryACPILevel_MinVoltage_Phases : 8;
		unsigned int MemoryACPILevel_MinVoltage_VddGfx : 8;
		unsigned int MemoryACPILevel_MinVoltage_Vddci : 8;
		unsigned int MemoryACPILevel_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_184__VI {
	struct {
		unsigned int         MemoryACPILevel_MinMvdd : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_185__VI {
	struct {
		unsigned int   MemoryACPILevel_MclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_186__VI {
	struct {
		unsigned int MemoryACPILevel_EnabledForActivity : 8;
		unsigned int MemoryACPILevel_EnabledForThrottle : 8;
		unsigned int       MemoryACPILevel_FreqRange : 8;
		unsigned int   MemoryACPILevel_StutterEnable : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_187__VI {
	struct {
		unsigned int         MemoryACPILevel_padding : 8;
		unsigned int MemoryACPILevel_VoltageDownHyst : 8;
		unsigned int        MemoryACPILevel_DownHyst : 8;
		unsigned int          MemoryACPILevel_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_188__VI {
	struct {
		unsigned int     MemoryACPILevel_MclkDivider : 8;
		unsigned int MemoryACPILevel_DisplayWatermark : 8;
		unsigned int   MemoryACPILevel_ActivityLevel : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_189__VI {
	struct {
		unsigned int MemoryLevel_0_MinVoltage_Phases : 8;
		unsigned int MemoryLevel_0_MinVoltage_VddGfx : 8;
		unsigned int  MemoryLevel_0_MinVoltage_Vddci : 8;
		unsigned int   MemoryLevel_0_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_19__VI {
	struct {
		unsigned int            LinkPIDController_Ki : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_190__VI {
	struct {
		unsigned int           MemoryLevel_0_MinMvdd : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_191__VI {
	struct {
		unsigned int     MemoryLevel_0_MclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_192__VI {
	struct {
		unsigned int MemoryLevel_0_EnabledForActivity : 8;
		unsigned int MemoryLevel_0_EnabledForThrottle : 8;
		unsigned int         MemoryLevel_0_FreqRange : 8;
		unsigned int     MemoryLevel_0_StutterEnable : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_193__VI {
	struct {
		unsigned int           MemoryLevel_0_padding : 8;
		unsigned int   MemoryLevel_0_VoltageDownHyst : 8;
		unsigned int          MemoryLevel_0_DownHyst : 8;
		unsigned int            MemoryLevel_0_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_194__VI {
	struct {
		unsigned int       MemoryLevel_0_MclkDivider : 8;
		unsigned int  MemoryLevel_0_DisplayWatermark : 8;
		unsigned int     MemoryLevel_0_ActivityLevel : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_195__VI {
	struct {
		unsigned int MemoryLevel_1_MinVoltage_Phases : 8;
		unsigned int MemoryLevel_1_MinVoltage_VddGfx : 8;
		unsigned int  MemoryLevel_1_MinVoltage_Vddci : 8;
		unsigned int   MemoryLevel_1_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_196__VI {
	struct {
		unsigned int           MemoryLevel_1_MinMvdd : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_197__VI {
	struct {
		unsigned int     MemoryLevel_1_MclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_198__VI {
	struct {
		unsigned int MemoryLevel_1_EnabledForActivity : 8;
		unsigned int MemoryLevel_1_EnabledForThrottle : 8;
		unsigned int         MemoryLevel_1_FreqRange : 8;
		unsigned int     MemoryLevel_1_StutterEnable : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_199__VI {
	struct {
		unsigned int           MemoryLevel_1_padding : 8;
		unsigned int   MemoryLevel_1_VoltageDownHyst : 8;
		unsigned int          MemoryLevel_1_DownHyst : 8;
		unsigned int            MemoryLevel_1_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_2__VI {
	struct {
		unsigned int GraphicsPIDController_LFWindupUpperLim : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_20__VI {
	struct {
		unsigned int LinkPIDController_LFWindupUpperLim : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_200__VI {
	struct {
		unsigned int       MemoryLevel_1_MclkDivider : 8;
		unsigned int  MemoryLevel_1_DisplayWatermark : 8;
		unsigned int     MemoryLevel_1_ActivityLevel : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_201__VI {
	struct {
		unsigned int MemoryLevel_2_MinVoltage_Phases : 8;
		unsigned int MemoryLevel_2_MinVoltage_VddGfx : 8;
		unsigned int  MemoryLevel_2_MinVoltage_Vddci : 8;
		unsigned int   MemoryLevel_2_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_202__VI {
	struct {
		unsigned int           MemoryLevel_2_MinMvdd : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_203__VI {
	struct {
		unsigned int     MemoryLevel_2_MclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_204__VI {
	struct {
		unsigned int MemoryLevel_2_EnabledForActivity : 8;
		unsigned int MemoryLevel_2_EnabledForThrottle : 8;
		unsigned int         MemoryLevel_2_FreqRange : 8;
		unsigned int     MemoryLevel_2_StutterEnable : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_205__VI {
	struct {
		unsigned int           MemoryLevel_2_padding : 8;
		unsigned int   MemoryLevel_2_VoltageDownHyst : 8;
		unsigned int          MemoryLevel_2_DownHyst : 8;
		unsigned int            MemoryLevel_2_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_206__VI {
	struct {
		unsigned int       MemoryLevel_2_MclkDivider : 8;
		unsigned int  MemoryLevel_2_DisplayWatermark : 8;
		unsigned int     MemoryLevel_2_ActivityLevel : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_207__VI {
	struct {
		unsigned int MemoryLevel_3_MinVoltage_Phases : 8;
		unsigned int MemoryLevel_3_MinVoltage_VddGfx : 8;
		unsigned int  MemoryLevel_3_MinVoltage_Vddci : 8;
		unsigned int   MemoryLevel_3_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_208__VI {
	struct {
		unsigned int           MemoryLevel_3_MinMvdd : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_209__VI {
	struct {
		unsigned int     MemoryLevel_3_MclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_21__VI {
	struct {
		unsigned int LinkPIDController_LFWindupLowerLim : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_210__VI {
	struct {
		unsigned int MemoryLevel_3_EnabledForActivity : 8;
		unsigned int MemoryLevel_3_EnabledForThrottle : 8;
		unsigned int         MemoryLevel_3_FreqRange : 8;
		unsigned int     MemoryLevel_3_StutterEnable : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_211__VI {
	struct {
		unsigned int           MemoryLevel_3_padding : 8;
		unsigned int   MemoryLevel_3_VoltageDownHyst : 8;
		unsigned int          MemoryLevel_3_DownHyst : 8;
		unsigned int            MemoryLevel_3_UpHyst : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_212__VI {
	struct {
		unsigned int       MemoryLevel_3_MclkDivider : 8;
		unsigned int  MemoryLevel_3_DisplayWatermark : 8;
		unsigned int     MemoryLevel_3_ActivityLevel : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_213__VI {
	struct {
		unsigned int                 LinkLevel_0_SPC : 8;
		unsigned int  LinkLevel_0_EnabledForActivity : 8;
		unsigned int       LinkLevel_0_PcieLaneCount : 8;
		unsigned int        LinkLevel_0_PcieGenSpeed : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_214__VI {
	struct {
		unsigned int       LinkLevel_0_DownThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_215__VI {
	struct {
		unsigned int         LinkLevel_0_UpThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_216__VI {
	struct {
		unsigned int            LinkLevel_0_Reserved : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_217__VI {
	struct {
		unsigned int                 LinkLevel_1_SPC : 8;
		unsigned int  LinkLevel_1_EnabledForActivity : 8;
		unsigned int       LinkLevel_1_PcieLaneCount : 8;
		unsigned int        LinkLevel_1_PcieGenSpeed : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_218__VI {
	struct {
		unsigned int       LinkLevel_1_DownThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_219__VI {
	struct {
		unsigned int         LinkLevel_1_UpThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_22__VI {
	struct {
		unsigned int LinkPIDController_StatePrecision : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_220__VI {
	struct {
		unsigned int            LinkLevel_1_Reserved : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_221__VI {
	struct {
		unsigned int                 LinkLevel_2_SPC : 8;
		unsigned int  LinkLevel_2_EnabledForActivity : 8;
		unsigned int       LinkLevel_2_PcieLaneCount : 8;
		unsigned int        LinkLevel_2_PcieGenSpeed : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_222__VI {
	struct {
		unsigned int       LinkLevel_2_DownThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_223__VI {
	struct {
		unsigned int         LinkLevel_2_UpThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_224__VI {
	struct {
		unsigned int            LinkLevel_2_Reserved : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_225__VI {
	struct {
		unsigned int                 LinkLevel_3_SPC : 8;
		unsigned int  LinkLevel_3_EnabledForActivity : 8;
		unsigned int       LinkLevel_3_PcieLaneCount : 8;
		unsigned int        LinkLevel_3_PcieGenSpeed : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_226__VI {
	struct {
		unsigned int       LinkLevel_3_DownThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_227__VI {
	struct {
		unsigned int         LinkLevel_3_UpThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_228__VI {
	struct {
		unsigned int            LinkLevel_3_Reserved : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_229__VI {
	struct {
		unsigned int                 LinkLevel_4_SPC : 8;
		unsigned int  LinkLevel_4_EnabledForActivity : 8;
		unsigned int       LinkLevel_4_PcieLaneCount : 8;
		unsigned int        LinkLevel_4_PcieGenSpeed : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_23__VI {
	struct {
		unsigned int   LinkPIDController_LfPrecision : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_230__VI {
	struct {
		unsigned int       LinkLevel_4_DownThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_231__VI {
	struct {
		unsigned int         LinkLevel_4_UpThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_232__VI {
	struct {
		unsigned int            LinkLevel_4_Reserved : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_233__VI {
	struct {
		unsigned int                 LinkLevel_5_SPC : 8;
		unsigned int  LinkLevel_5_EnabledForActivity : 8;
		unsigned int       LinkLevel_5_PcieLaneCount : 8;
		unsigned int        LinkLevel_5_PcieGenSpeed : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_234__VI {
	struct {
		unsigned int       LinkLevel_5_DownThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_235__VI {
	struct {
		unsigned int         LinkLevel_5_UpThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_236__VI {
	struct {
		unsigned int            LinkLevel_5_Reserved : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_237__VI {
	struct {
		unsigned int                 LinkLevel_6_SPC : 8;
		unsigned int  LinkLevel_6_EnabledForActivity : 8;
		unsigned int       LinkLevel_6_PcieLaneCount : 8;
		unsigned int        LinkLevel_6_PcieGenSpeed : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_238__VI {
	struct {
		unsigned int       LinkLevel_6_DownThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_239__VI {
	struct {
		unsigned int         LinkLevel_6_UpThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_24__VI {
	struct {
		unsigned int      LinkPIDController_LfOffset : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_240__VI {
	struct {
		unsigned int            LinkLevel_6_Reserved : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_241__VI {
	struct {
		unsigned int                 LinkLevel_7_SPC : 8;
		unsigned int  LinkLevel_7_EnabledForActivity : 8;
		unsigned int       LinkLevel_7_PcieLaneCount : 8;
		unsigned int        LinkLevel_7_PcieGenSpeed : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_242__VI {
	struct {
		unsigned int       LinkLevel_7_DownThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_243__VI {
	struct {
		unsigned int         LinkLevel_7_UpThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_244__VI {
	struct {
		unsigned int            LinkLevel_7_Reserved : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_245__VI {
	struct {
		unsigned int                 ACPILevel_Flags : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_246__VI {
	struct {
		unsigned int     ACPILevel_MinVoltage_Phases : 8;
		unsigned int     ACPILevel_MinVoltage_VddGfx : 8;
		unsigned int      ACPILevel_MinVoltage_Vddci : 8;
		unsigned int       ACPILevel_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_247__VI {
	struct {
		unsigned int         ACPILevel_SclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_248__VI {
	struct {
		unsigned int               ACPILevel_padding : 8;
		unsigned int        ACPILevel_DeepSleepDivId : 8;
		unsigned int      ACPILevel_DisplayWatermark : 8;
		unsigned int               ACPILevel_SclkDid : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_249__VI {
	struct {
		unsigned int        ACPILevel_CgSpllFuncCntl : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_25__VI {
	struct {
		unsigned int      LinkPIDController_MaxState : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_250__VI {
	struct {
		unsigned int       ACPILevel_CgSpllFuncCntl2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_251__VI {
	struct {
		unsigned int       ACPILevel_CgSpllFuncCntl3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_252__VI {
	struct {
		unsigned int       ACPILevel_CgSpllFuncCntl4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_253__VI {
	struct {
		unsigned int    ACPILevel_SpllSpreadSpectrum : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_254__VI {
	struct {
		unsigned int   ACPILevel_SpllSpreadSpectrum2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_255__VI {
	struct {
		unsigned int            ACPILevel_CcPwrDynRm : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_256__VI {
	struct {
		unsigned int           ACPILevel_CcPwrDynRm1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_257__VI {
	struct {
		unsigned int        UvdLevel_0_VclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_258__VI {
	struct {
		unsigned int        UvdLevel_0_DclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_259__VI {
	struct {
		unsigned int    UvdLevel_0_MinVoltage_Phases : 8;
		unsigned int    UvdLevel_0_MinVoltage_VddGfx : 8;
		unsigned int     UvdLevel_0_MinVoltage_Vddci : 8;
		unsigned int      UvdLevel_0_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_26__VI {
	struct {
		unsigned int LinkPIDController_MaxLfFraction : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_260__VI {
	struct {
		unsigned int            UvdLevel_0_padding_1 : 8;
		unsigned int            UvdLevel_0_padding_0 : 8;
		unsigned int          UvdLevel_0_DclkDivider : 8;
		unsigned int          UvdLevel_0_VclkDivider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_261__VI {
	struct {
		unsigned int        UvdLevel_1_VclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_262__VI {
	struct {
		unsigned int        UvdLevel_1_DclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_263__VI {
	struct {
		unsigned int    UvdLevel_1_MinVoltage_Phases : 8;
		unsigned int    UvdLevel_1_MinVoltage_VddGfx : 8;
		unsigned int     UvdLevel_1_MinVoltage_Vddci : 8;
		unsigned int      UvdLevel_1_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_264__VI {
	struct {
		unsigned int            UvdLevel_1_padding_1 : 8;
		unsigned int            UvdLevel_1_padding_0 : 8;
		unsigned int          UvdLevel_1_DclkDivider : 8;
		unsigned int          UvdLevel_1_VclkDivider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_265__VI {
	struct {
		unsigned int        UvdLevel_2_VclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_266__VI {
	struct {
		unsigned int        UvdLevel_2_DclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_267__VI {
	struct {
		unsigned int    UvdLevel_2_MinVoltage_Phases : 8;
		unsigned int    UvdLevel_2_MinVoltage_VddGfx : 8;
		unsigned int     UvdLevel_2_MinVoltage_Vddci : 8;
		unsigned int      UvdLevel_2_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_268__VI {
	struct {
		unsigned int            UvdLevel_2_padding_1 : 8;
		unsigned int            UvdLevel_2_padding_0 : 8;
		unsigned int          UvdLevel_2_DclkDivider : 8;
		unsigned int          UvdLevel_2_VclkDivider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_269__VI {
	struct {
		unsigned int        UvdLevel_3_VclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_27__VI {
	struct {
		unsigned int    LinkPIDController_StateShift : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_270__VI {
	struct {
		unsigned int        UvdLevel_3_DclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_271__VI {
	struct {
		unsigned int    UvdLevel_3_MinVoltage_Phases : 8;
		unsigned int    UvdLevel_3_MinVoltage_VddGfx : 8;
		unsigned int     UvdLevel_3_MinVoltage_Vddci : 8;
		unsigned int      UvdLevel_3_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_272__VI {
	struct {
		unsigned int            UvdLevel_3_padding_1 : 8;
		unsigned int            UvdLevel_3_padding_0 : 8;
		unsigned int          UvdLevel_3_DclkDivider : 8;
		unsigned int          UvdLevel_3_VclkDivider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_273__VI {
	struct {
		unsigned int        UvdLevel_4_VclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_274__VI {
	struct {
		unsigned int        UvdLevel_4_DclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_275__VI {
	struct {
		unsigned int    UvdLevel_4_MinVoltage_Phases : 8;
		unsigned int    UvdLevel_4_MinVoltage_VddGfx : 8;
		unsigned int     UvdLevel_4_MinVoltage_Vddci : 8;
		unsigned int      UvdLevel_4_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_276__VI {
	struct {
		unsigned int            UvdLevel_4_padding_1 : 8;
		unsigned int            UvdLevel_4_padding_0 : 8;
		unsigned int          UvdLevel_4_DclkDivider : 8;
		unsigned int          UvdLevel_4_VclkDivider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_277__VI {
	struct {
		unsigned int        UvdLevel_5_VclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_278__VI {
	struct {
		unsigned int        UvdLevel_5_DclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_279__VI {
	struct {
		unsigned int    UvdLevel_5_MinVoltage_Phases : 8;
		unsigned int    UvdLevel_5_MinVoltage_VddGfx : 8;
		unsigned int     UvdLevel_5_MinVoltage_Vddci : 8;
		unsigned int      UvdLevel_5_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_28__VI {
	struct {
		unsigned int                     SystemFlags : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_280__VI {
	struct {
		unsigned int            UvdLevel_5_padding_1 : 8;
		unsigned int            UvdLevel_5_padding_0 : 8;
		unsigned int          UvdLevel_5_DclkDivider : 8;
		unsigned int          UvdLevel_5_VclkDivider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_281__VI {
	struct {
		unsigned int        UvdLevel_6_VclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_282__VI {
	struct {
		unsigned int        UvdLevel_6_DclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_283__VI {
	struct {
		unsigned int    UvdLevel_6_MinVoltage_Phases : 8;
		unsigned int    UvdLevel_6_MinVoltage_VddGfx : 8;
		unsigned int     UvdLevel_6_MinVoltage_Vddci : 8;
		unsigned int      UvdLevel_6_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_284__VI {
	struct {
		unsigned int            UvdLevel_6_padding_1 : 8;
		unsigned int            UvdLevel_6_padding_0 : 8;
		unsigned int          UvdLevel_6_DclkDivider : 8;
		unsigned int          UvdLevel_6_VclkDivider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_285__VI {
	struct {
		unsigned int        UvdLevel_7_VclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_286__VI {
	struct {
		unsigned int        UvdLevel_7_DclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_287__VI {
	struct {
		unsigned int    UvdLevel_7_MinVoltage_Phases : 8;
		unsigned int    UvdLevel_7_MinVoltage_VddGfx : 8;
		unsigned int     UvdLevel_7_MinVoltage_Vddci : 8;
		unsigned int      UvdLevel_7_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_288__VI {
	struct {
		unsigned int            UvdLevel_7_padding_1 : 8;
		unsigned int            UvdLevel_7_padding_0 : 8;
		unsigned int          UvdLevel_7_DclkDivider : 8;
		unsigned int          UvdLevel_7_VclkDivider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_289__VI {
	struct {
		unsigned int            VceLevel_0_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_29__VI {
	struct {
		unsigned int                        VRConfig : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_290__VI {
	struct {
		unsigned int    VceLevel_0_MinVoltage_Phases : 8;
		unsigned int    VceLevel_0_MinVoltage_VddGfx : 8;
		unsigned int     VceLevel_0_MinVoltage_Vddci : 8;
		unsigned int      VceLevel_0_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_291__VI {
	struct {
		unsigned int            VceLevel_0_padding_2 : 8;
		unsigned int            VceLevel_0_padding_1 : 8;
		unsigned int            VceLevel_0_padding_0 : 8;
		unsigned int              VceLevel_0_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_292__VI {
	struct {
		unsigned int            VceLevel_1_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_293__VI {
	struct {
		unsigned int    VceLevel_1_MinVoltage_Phases : 8;
		unsigned int    VceLevel_1_MinVoltage_VddGfx : 8;
		unsigned int     VceLevel_1_MinVoltage_Vddci : 8;
		unsigned int      VceLevel_1_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_294__VI {
	struct {
		unsigned int            VceLevel_1_padding_2 : 8;
		unsigned int            VceLevel_1_padding_1 : 8;
		unsigned int            VceLevel_1_padding_0 : 8;
		unsigned int              VceLevel_1_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_295__VI {
	struct {
		unsigned int            VceLevel_2_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_296__VI {
	struct {
		unsigned int    VceLevel_2_MinVoltage_Phases : 8;
		unsigned int    VceLevel_2_MinVoltage_VddGfx : 8;
		unsigned int     VceLevel_2_MinVoltage_Vddci : 8;
		unsigned int      VceLevel_2_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_297__VI {
	struct {
		unsigned int            VceLevel_2_padding_2 : 8;
		unsigned int            VceLevel_2_padding_1 : 8;
		unsigned int            VceLevel_2_padding_0 : 8;
		unsigned int              VceLevel_2_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_298__VI {
	struct {
		unsigned int            VceLevel_3_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_299__VI {
	struct {
		unsigned int    VceLevel_3_MinVoltage_Phases : 8;
		unsigned int    VceLevel_3_MinVoltage_VddGfx : 8;
		unsigned int     VceLevel_3_MinVoltage_Vddci : 8;
		unsigned int      VceLevel_3_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_3__VI {
	struct {
		unsigned int GraphicsPIDController_LFWindupLowerLim : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_30__VI {
	struct {
		unsigned int                       SmioMask1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_300__VI {
	struct {
		unsigned int            VceLevel_3_padding_2 : 8;
		unsigned int            VceLevel_3_padding_1 : 8;
		unsigned int            VceLevel_3_padding_0 : 8;
		unsigned int              VceLevel_3_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_301__VI {
	struct {
		unsigned int            VceLevel_4_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_302__VI {
	struct {
		unsigned int    VceLevel_4_MinVoltage_Phases : 8;
		unsigned int    VceLevel_4_MinVoltage_VddGfx : 8;
		unsigned int     VceLevel_4_MinVoltage_Vddci : 8;
		unsigned int      VceLevel_4_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_303__VI {
	struct {
		unsigned int            VceLevel_4_padding_2 : 8;
		unsigned int            VceLevel_4_padding_1 : 8;
		unsigned int            VceLevel_4_padding_0 : 8;
		unsigned int              VceLevel_4_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_304__VI {
	struct {
		unsigned int            VceLevel_5_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_305__VI {
	struct {
		unsigned int    VceLevel_5_MinVoltage_Phases : 8;
		unsigned int    VceLevel_5_MinVoltage_VddGfx : 8;
		unsigned int     VceLevel_5_MinVoltage_Vddci : 8;
		unsigned int      VceLevel_5_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_306__VI {
	struct {
		unsigned int            VceLevel_5_padding_2 : 8;
		unsigned int            VceLevel_5_padding_1 : 8;
		unsigned int            VceLevel_5_padding_0 : 8;
		unsigned int              VceLevel_5_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_307__VI {
	struct {
		unsigned int            VceLevel_6_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_308__VI {
	struct {
		unsigned int    VceLevel_6_MinVoltage_Phases : 8;
		unsigned int    VceLevel_6_MinVoltage_VddGfx : 8;
		unsigned int     VceLevel_6_MinVoltage_Vddci : 8;
		unsigned int      VceLevel_6_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_309__VI {
	struct {
		unsigned int            VceLevel_6_padding_2 : 8;
		unsigned int            VceLevel_6_padding_1 : 8;
		unsigned int            VceLevel_6_padding_0 : 8;
		unsigned int              VceLevel_6_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_31__VI {
	struct {
		unsigned int                       SmioMask2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_310__VI {
	struct {
		unsigned int            VceLevel_7_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_311__VI {
	struct {
		unsigned int    VceLevel_7_MinVoltage_Phases : 8;
		unsigned int    VceLevel_7_MinVoltage_VddGfx : 8;
		unsigned int     VceLevel_7_MinVoltage_Vddci : 8;
		unsigned int      VceLevel_7_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_312__VI {
	struct {
		unsigned int            VceLevel_7_padding_2 : 8;
		unsigned int            VceLevel_7_padding_1 : 8;
		unsigned int            VceLevel_7_padding_0 : 8;
		unsigned int              VceLevel_7_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_313__VI {
	struct {
		unsigned int            AcpLevel_0_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_314__VI {
	struct {
		unsigned int    AcpLevel_0_MinVoltage_Phases : 8;
		unsigned int    AcpLevel_0_MinVoltage_VddGfx : 8;
		unsigned int     AcpLevel_0_MinVoltage_Vddci : 8;
		unsigned int      AcpLevel_0_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_315__VI {
	struct {
		unsigned int            AcpLevel_0_padding_2 : 8;
		unsigned int            AcpLevel_0_padding_1 : 8;
		unsigned int            AcpLevel_0_padding_0 : 8;
		unsigned int              AcpLevel_0_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_316__VI {
	struct {
		unsigned int            AcpLevel_1_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_317__VI {
	struct {
		unsigned int    AcpLevel_1_MinVoltage_Phases : 8;
		unsigned int    AcpLevel_1_MinVoltage_VddGfx : 8;
		unsigned int     AcpLevel_1_MinVoltage_Vddci : 8;
		unsigned int      AcpLevel_1_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_318__VI {
	struct {
		unsigned int            AcpLevel_1_padding_2 : 8;
		unsigned int            AcpLevel_1_padding_1 : 8;
		unsigned int            AcpLevel_1_padding_0 : 8;
		unsigned int              AcpLevel_1_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_319__VI {
	struct {
		unsigned int            AcpLevel_2_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_32__VI {
	struct {
		unsigned int    SmioTable1_Pattern_0_padding : 8;
		unsigned int       SmioTable1_Pattern_0_Smio : 8;
		unsigned int    SmioTable1_Pattern_0_Voltage : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_320__VI {
	struct {
		unsigned int    AcpLevel_2_MinVoltage_Phases : 8;
		unsigned int    AcpLevel_2_MinVoltage_VddGfx : 8;
		unsigned int     AcpLevel_2_MinVoltage_Vddci : 8;
		unsigned int      AcpLevel_2_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_321__VI {
	struct {
		unsigned int            AcpLevel_2_padding_2 : 8;
		unsigned int            AcpLevel_2_padding_1 : 8;
		unsigned int            AcpLevel_2_padding_0 : 8;
		unsigned int              AcpLevel_2_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_322__VI {
	struct {
		unsigned int            AcpLevel_3_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_323__VI {
	struct {
		unsigned int    AcpLevel_3_MinVoltage_Phases : 8;
		unsigned int    AcpLevel_3_MinVoltage_VddGfx : 8;
		unsigned int     AcpLevel_3_MinVoltage_Vddci : 8;
		unsigned int      AcpLevel_3_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_324__VI {
	struct {
		unsigned int            AcpLevel_3_padding_2 : 8;
		unsigned int            AcpLevel_3_padding_1 : 8;
		unsigned int            AcpLevel_3_padding_0 : 8;
		unsigned int              AcpLevel_3_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_325__VI {
	struct {
		unsigned int            AcpLevel_4_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_326__VI {
	struct {
		unsigned int    AcpLevel_4_MinVoltage_Phases : 8;
		unsigned int    AcpLevel_4_MinVoltage_VddGfx : 8;
		unsigned int     AcpLevel_4_MinVoltage_Vddci : 8;
		unsigned int      AcpLevel_4_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_327__VI {
	struct {
		unsigned int            AcpLevel_4_padding_2 : 8;
		unsigned int            AcpLevel_4_padding_1 : 8;
		unsigned int            AcpLevel_4_padding_0 : 8;
		unsigned int              AcpLevel_4_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_328__VI {
	struct {
		unsigned int            AcpLevel_5_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_329__VI {
	struct {
		unsigned int    AcpLevel_5_MinVoltage_Phases : 8;
		unsigned int    AcpLevel_5_MinVoltage_VddGfx : 8;
		unsigned int     AcpLevel_5_MinVoltage_Vddci : 8;
		unsigned int      AcpLevel_5_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_33__VI {
	struct {
		unsigned int    SmioTable1_Pattern_1_padding : 8;
		unsigned int       SmioTable1_Pattern_1_Smio : 8;
		unsigned int    SmioTable1_Pattern_1_Voltage : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_330__VI {
	struct {
		unsigned int            AcpLevel_5_padding_2 : 8;
		unsigned int            AcpLevel_5_padding_1 : 8;
		unsigned int            AcpLevel_5_padding_0 : 8;
		unsigned int              AcpLevel_5_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_331__VI {
	struct {
		unsigned int            AcpLevel_6_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_332__VI {
	struct {
		unsigned int    AcpLevel_6_MinVoltage_Phases : 8;
		unsigned int    AcpLevel_6_MinVoltage_VddGfx : 8;
		unsigned int     AcpLevel_6_MinVoltage_Vddci : 8;
		unsigned int      AcpLevel_6_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_333__VI {
	struct {
		unsigned int            AcpLevel_6_padding_2 : 8;
		unsigned int            AcpLevel_6_padding_1 : 8;
		unsigned int            AcpLevel_6_padding_0 : 8;
		unsigned int              AcpLevel_6_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_334__VI {
	struct {
		unsigned int            AcpLevel_7_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_335__VI {
	struct {
		unsigned int    AcpLevel_7_MinVoltage_Phases : 8;
		unsigned int    AcpLevel_7_MinVoltage_VddGfx : 8;
		unsigned int     AcpLevel_7_MinVoltage_Vddci : 8;
		unsigned int      AcpLevel_7_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_336__VI {
	struct {
		unsigned int            AcpLevel_7_padding_2 : 8;
		unsigned int            AcpLevel_7_padding_1 : 8;
		unsigned int            AcpLevel_7_padding_0 : 8;
		unsigned int              AcpLevel_7_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_337__VI {
	struct {
		unsigned int           SamuLevel_0_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_338__VI {
	struct {
		unsigned int   SamuLevel_0_MinVoltage_Phases : 8;
		unsigned int   SamuLevel_0_MinVoltage_VddGfx : 8;
		unsigned int    SamuLevel_0_MinVoltage_Vddci : 8;
		unsigned int     SamuLevel_0_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_339__VI {
	struct {
		unsigned int           SamuLevel_0_padding_2 : 8;
		unsigned int           SamuLevel_0_padding_1 : 8;
		unsigned int           SamuLevel_0_padding_0 : 8;
		unsigned int             SamuLevel_0_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_34__VI {
	struct {
		unsigned int    SmioTable1_Pattern_2_padding : 8;
		unsigned int       SmioTable1_Pattern_2_Smio : 8;
		unsigned int    SmioTable1_Pattern_2_Voltage : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_340__VI {
	struct {
		unsigned int           SamuLevel_1_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_341__VI {
	struct {
		unsigned int   SamuLevel_1_MinVoltage_Phases : 8;
		unsigned int   SamuLevel_1_MinVoltage_VddGfx : 8;
		unsigned int    SamuLevel_1_MinVoltage_Vddci : 8;
		unsigned int     SamuLevel_1_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_342__VI {
	struct {
		unsigned int           SamuLevel_1_padding_2 : 8;
		unsigned int           SamuLevel_1_padding_1 : 8;
		unsigned int           SamuLevel_1_padding_0 : 8;
		unsigned int             SamuLevel_1_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_343__VI {
	struct {
		unsigned int           SamuLevel_2_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_344__VI {
	struct {
		unsigned int   SamuLevel_2_MinVoltage_Phases : 8;
		unsigned int   SamuLevel_2_MinVoltage_VddGfx : 8;
		unsigned int    SamuLevel_2_MinVoltage_Vddci : 8;
		unsigned int     SamuLevel_2_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_345__VI {
	struct {
		unsigned int           SamuLevel_2_padding_2 : 8;
		unsigned int           SamuLevel_2_padding_1 : 8;
		unsigned int           SamuLevel_2_padding_0 : 8;
		unsigned int             SamuLevel_2_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_346__VI {
	struct {
		unsigned int           SamuLevel_3_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_347__VI {
	struct {
		unsigned int   SamuLevel_3_MinVoltage_Phases : 8;
		unsigned int   SamuLevel_3_MinVoltage_VddGfx : 8;
		unsigned int    SamuLevel_3_MinVoltage_Vddci : 8;
		unsigned int     SamuLevel_3_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_348__VI {
	struct {
		unsigned int           SamuLevel_3_padding_2 : 8;
		unsigned int           SamuLevel_3_padding_1 : 8;
		unsigned int           SamuLevel_3_padding_0 : 8;
		unsigned int             SamuLevel_3_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_349__VI {
	struct {
		unsigned int           SamuLevel_4_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_35__VI {
	struct {
		unsigned int    SmioTable1_Pattern_3_padding : 8;
		unsigned int       SmioTable1_Pattern_3_Smio : 8;
		unsigned int    SmioTable1_Pattern_3_Voltage : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_350__VI {
	struct {
		unsigned int   SamuLevel_4_MinVoltage_Phases : 8;
		unsigned int   SamuLevel_4_MinVoltage_VddGfx : 8;
		unsigned int    SamuLevel_4_MinVoltage_Vddci : 8;
		unsigned int     SamuLevel_4_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_351__VI {
	struct {
		unsigned int           SamuLevel_4_padding_2 : 8;
		unsigned int           SamuLevel_4_padding_1 : 8;
		unsigned int           SamuLevel_4_padding_0 : 8;
		unsigned int             SamuLevel_4_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_352__VI {
	struct {
		unsigned int           SamuLevel_5_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_353__VI {
	struct {
		unsigned int   SamuLevel_5_MinVoltage_Phases : 8;
		unsigned int   SamuLevel_5_MinVoltage_VddGfx : 8;
		unsigned int    SamuLevel_5_MinVoltage_Vddci : 8;
		unsigned int     SamuLevel_5_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_354__VI {
	struct {
		unsigned int           SamuLevel_5_padding_2 : 8;
		unsigned int           SamuLevel_5_padding_1 : 8;
		unsigned int           SamuLevel_5_padding_0 : 8;
		unsigned int             SamuLevel_5_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_355__VI {
	struct {
		unsigned int           SamuLevel_6_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_356__VI {
	struct {
		unsigned int   SamuLevel_6_MinVoltage_Phases : 8;
		unsigned int   SamuLevel_6_MinVoltage_VddGfx : 8;
		unsigned int    SamuLevel_6_MinVoltage_Vddci : 8;
		unsigned int     SamuLevel_6_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_357__VI {
	struct {
		unsigned int           SamuLevel_6_padding_2 : 8;
		unsigned int           SamuLevel_6_padding_1 : 8;
		unsigned int           SamuLevel_6_padding_0 : 8;
		unsigned int             SamuLevel_6_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_358__VI {
	struct {
		unsigned int           SamuLevel_7_Frequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_359__VI {
	struct {
		unsigned int   SamuLevel_7_MinVoltage_Phases : 8;
		unsigned int   SamuLevel_7_MinVoltage_VddGfx : 8;
		unsigned int    SamuLevel_7_MinVoltage_Vddci : 8;
		unsigned int     SamuLevel_7_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_36__VI {
	struct {
		unsigned int    SmioTable2_Pattern_0_padding : 8;
		unsigned int       SmioTable2_Pattern_0_Smio : 8;
		unsigned int    SmioTable2_Pattern_0_Voltage : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_360__VI {
	struct {
		unsigned int           SamuLevel_7_padding_2 : 8;
		unsigned int           SamuLevel_7_padding_1 : 8;
		unsigned int           SamuLevel_7_padding_0 : 8;
		unsigned int             SamuLevel_7_Divider : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_361__VI {
	struct {
		unsigned int                  Ulv_CcPwrDynRm : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_362__VI {
	struct {
		unsigned int                 Ulv_CcPwrDynRm1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_363__VI {
	struct {
		unsigned int                   Ulv_VddcPhase : 8;
		unsigned int               Ulv_VddcOffsetVid : 8;
		unsigned int                  Ulv_VddcOffset : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_364__VI {
	struct {
		unsigned int                    Ulv_Reserved : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_365__VI {
	struct {
		unsigned int                    SclkStepSize : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_366__VI {
	struct {
		unsigned int                          Smio_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_367__VI {
	struct {
		unsigned int                          Smio_1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_368__VI {
	struct {
		unsigned int                          Smio_2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_369__VI {
	struct {
		unsigned int                          Smio_3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_37__VI {
	struct {
		unsigned int    SmioTable2_Pattern_1_padding : 8;
		unsigned int       SmioTable2_Pattern_1_Smio : 8;
		unsigned int    SmioTable2_Pattern_1_Voltage : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_370__VI {
	struct {
		unsigned int                          Smio_4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_371__VI {
	struct {
		unsigned int                          Smio_5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_372__VI {
	struct {
		unsigned int                          Smio_6 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_373__VI {
	struct {
		unsigned int                          Smio_7 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_374__VI {
	struct {
		unsigned int                          Smio_8 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_375__VI {
	struct {
		unsigned int                          Smio_9 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_376__VI {
	struct {
		unsigned int                         Smio_10 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_377__VI {
	struct {
		unsigned int                         Smio_11 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_378__VI {
	struct {
		unsigned int                         Smio_12 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_379__VI {
	struct {
		unsigned int                         Smio_13 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_38__VI {
	struct {
		unsigned int    SmioTable2_Pattern_2_padding : 8;
		unsigned int       SmioTable2_Pattern_2_Smio : 8;
		unsigned int    SmioTable2_Pattern_2_Voltage : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_380__VI {
	struct {
		unsigned int                         Smio_14 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_381__VI {
	struct {
		unsigned int                         Smio_15 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_382__VI {
	struct {
		unsigned int                         Smio_16 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_383__VI {
	struct {
		unsigned int                         Smio_17 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_384__VI {
	struct {
		unsigned int                         Smio_18 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_385__VI {
	struct {
		unsigned int                         Smio_19 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_386__VI {
	struct {
		unsigned int                         Smio_20 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_387__VI {
	struct {
		unsigned int                         Smio_21 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_388__VI {
	struct {
		unsigned int                         Smio_22 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_389__VI {
	struct {
		unsigned int                         Smio_23 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_39__VI {
	struct {
		unsigned int    SmioTable2_Pattern_3_padding : 8;
		unsigned int       SmioTable2_Pattern_3_Smio : 8;
		unsigned int    SmioTable2_Pattern_3_Voltage : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_390__VI {
	struct {
		unsigned int                         Smio_24 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_391__VI {
	struct {
		unsigned int                         Smio_25 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_392__VI {
	struct {
		unsigned int                         Smio_26 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_393__VI {
	struct {
		unsigned int                         Smio_27 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_394__VI {
	struct {
		unsigned int                         Smio_28 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_395__VI {
	struct {
		unsigned int                         Smio_29 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_396__VI {
	struct {
		unsigned int                         Smio_30 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_397__VI {
	struct {
		unsigned int                         Smio_31 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_398__VI {
	struct {
		unsigned int                   SamuBootLevel : 8;
		unsigned int                    AcpBootLevel : 8;
		unsigned int                    VceBootLevel : 8;
		unsigned int                    UvdBootLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_399__VI {
	struct {
		unsigned int                GraphicsInterval : 8;
		unsigned int     GraphicsThermThrottleEnable : 8;
		unsigned int     GraphicsVoltageChangeEnable : 8;
		unsigned int               GraphicsBootLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_4__VI {
	struct {
		unsigned int GraphicsPIDController_StatePrecision : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_40__VI {
	struct {
		unsigned int                  VddcLevelCount : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_400__VI {
	struct {
		unsigned int            TemperatureLimitHigh : 16;
		unsigned int                 ThermalInterval : 8;
		unsigned int                 VoltageInterval : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_401__VI {
	struct {
		unsigned int       MemoryVoltageChangeEnable : 8;
		unsigned int                 MemoryBootLevel : 8;
		unsigned int             TemperatureLimitLow : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_402__VI {
	struct {
		unsigned int       MemoryThermThrottleEnable : 8;
		unsigned int                  MemoryInterval : 8;
		unsigned int                        BootMVdd : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_403__VI {
	struct {
		unsigned int               PhaseResponseTime : 16;
		unsigned int             VoltageResponseTime : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_404__VI {
	struct {
		unsigned int                         DTEMode : 8;
		unsigned int                     DTEInterval : 8;
		unsigned int                 PCIeGenInterval : 8;
		unsigned int               PCIeBootLinkLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_405__VI {
	struct {
		unsigned int                       ThermGpio : 8;
		unsigned int                        AcDcGpio : 8;
		unsigned int                       VRHotGpio : 8;
		unsigned int                      SVI2Enable : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_406__VI {
	struct {
		unsigned int            PPM_TemperatureLimit : 16;
		unsigned int                 PPM_PkgPwrLimit : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_407__VI {
	struct {
		unsigned int                       TargetTdp : 16;
		unsigned int                      DefaultTdp : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_408__VI {
	struct {
		unsigned int                 FpsLowThreshold : 16;
		unsigned int                FpsHighThreshold : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_409__VI {
	struct {
		unsigned int                  BAPMTI_R_0_1_0 : 16;
		unsigned int                  BAPMTI_R_0_0_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_41__VI {
	struct {
		unsigned int                 VddciLevelCount : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_410__VI {
	struct {
		unsigned int                  BAPMTI_R_1_0_0 : 16;
		unsigned int                  BAPMTI_R_0_2_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_411__VI {
	struct {
		unsigned int                  BAPMTI_R_1_2_0 : 16;
		unsigned int                  BAPMTI_R_1_1_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_412__VI {
	struct {
		unsigned int                  BAPMTI_R_2_1_0 : 16;
		unsigned int                  BAPMTI_R_2_0_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_413__VI {
	struct {
		unsigned int                  BAPMTI_R_3_0_0 : 16;
		unsigned int                  BAPMTI_R_2_2_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_414__VI {
	struct {
		unsigned int                  BAPMTI_R_3_2_0 : 16;
		unsigned int                  BAPMTI_R_3_1_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_415__VI {
	struct {
		unsigned int                  BAPMTI_R_4_1_0 : 16;
		unsigned int                  BAPMTI_R_4_0_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_416__VI {
	struct {
		unsigned int                 BAPMTI_RC_0_0_0 : 16;
		unsigned int                  BAPMTI_R_4_2_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_417__VI {
	struct {
		unsigned int                 BAPMTI_RC_0_2_0 : 16;
		unsigned int                 BAPMTI_RC_0_1_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_418__VI {
	struct {
		unsigned int                 BAPMTI_RC_1_1_0 : 16;
		unsigned int                 BAPMTI_RC_1_0_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_419__VI {
	struct {
		unsigned int                 BAPMTI_RC_2_0_0 : 16;
		unsigned int                 BAPMTI_RC_1_2_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_42__VI {
	struct {
		unsigned int                VddGfxLevelCount : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_420__VI {
	struct {
		unsigned int                 BAPMTI_RC_2_2_0 : 16;
		unsigned int                 BAPMTI_RC_2_1_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_421__VI {
	struct {
		unsigned int                 BAPMTI_RC_3_1_0 : 16;
		unsigned int                 BAPMTI_RC_3_0_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_422__VI {
	struct {
		unsigned int                 BAPMTI_RC_4_0_0 : 16;
		unsigned int                 BAPMTI_RC_3_2_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_423__VI {
	struct {
		unsigned int                 BAPMTI_RC_4_2_0 : 16;
		unsigned int                 BAPMTI_RC_4_1_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_424__VI {
	struct {
		unsigned int                       GpuTjHyst : 8;
		unsigned int                        GpuTjMax : 8;
		unsigned int                     DTETjOffset : 8;
		unsigned int              DTEAmbientTempBase : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_425__VI {
	struct {
		unsigned int              BootVoltage_Phases : 8;
		unsigned int              BootVoltage_VddGfx : 8;
		unsigned int               BootVoltage_Vddci : 8;
		unsigned int                BootVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_426__VI {
	struct {
		unsigned int              BAPM_TEMP_GRADIENT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_427__VI {
	struct {
		unsigned int       LowSclkInterruptThreshold : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_428__VI {
	struct {
		unsigned int                 VddGfxReChkWait : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_429__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_43__VI {
	struct {
		unsigned int                  MvddLevelCount : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_430__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_431__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_432__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_433__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_434__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_435__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_436__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_437__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_438__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_439__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_44__VI {
	struct {
		unsigned int                     VddcTable_1 : 16;
		unsigned int                     VddcTable_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_440__VI {
	struct {
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5 : 8;
		unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_45__VI {
	struct {
		unsigned int                     VddcTable_3 : 16;
		unsigned int                     VddcTable_2 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_46__VI {
	struct {
		unsigned int                     VddcTable_5 : 16;
		unsigned int                     VddcTable_4 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_47__VI {
	struct {
		unsigned int                     VddcTable_7 : 16;
		unsigned int                     VddcTable_6 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_48__VI {
	struct {
		unsigned int                     VddcTable_9 : 16;
		unsigned int                     VddcTable_8 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_49__VI {
	struct {
		unsigned int                    VddcTable_11 : 16;
		unsigned int                    VddcTable_10 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_5__VI {
	struct {
		unsigned int GraphicsPIDController_LfPrecision : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_50__VI {
	struct {
		unsigned int                    VddcTable_13 : 16;
		unsigned int                    VddcTable_12 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_51__VI {
	struct {
		unsigned int                    VddcTable_15 : 16;
		unsigned int                    VddcTable_14 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_52__VI {
	struct {
		unsigned int                   VddGfxTable_1 : 16;
		unsigned int                   VddGfxTable_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_53__VI {
	struct {
		unsigned int                   VddGfxTable_3 : 16;
		unsigned int                   VddGfxTable_2 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_54__VI {
	struct {
		unsigned int                   VddGfxTable_5 : 16;
		unsigned int                   VddGfxTable_4 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_55__VI {
	struct {
		unsigned int                   VddGfxTable_7 : 16;
		unsigned int                   VddGfxTable_6 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_56__VI {
	struct {
		unsigned int                   VddGfxTable_9 : 16;
		unsigned int                   VddGfxTable_8 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_57__VI {
	struct {
		unsigned int                  VddGfxTable_11 : 16;
		unsigned int                  VddGfxTable_10 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_58__VI {
	struct {
		unsigned int                  VddGfxTable_13 : 16;
		unsigned int                  VddGfxTable_12 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_59__VI {
	struct {
		unsigned int                  VddGfxTable_15 : 16;
		unsigned int                  VddGfxTable_14 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_6__VI {
	struct {
		unsigned int  GraphicsPIDController_LfOffset : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_60__VI {
	struct {
		unsigned int                    VddciTable_1 : 16;
		unsigned int                    VddciTable_0 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_61__VI {
	struct {
		unsigned int                    VddciTable_3 : 16;
		unsigned int                    VddciTable_2 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_62__VI {
	struct {
		unsigned int                    VddciTable_5 : 16;
		unsigned int                    VddciTable_4 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_63__VI {
	struct {
		unsigned int                    VddciTable_7 : 16;
		unsigned int                    VddciTable_6 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_64__VI {
	struct {
		unsigned int           BapmVddGfxVidHiSidd_3 : 8;
		unsigned int           BapmVddGfxVidHiSidd_2 : 8;
		unsigned int           BapmVddGfxVidHiSidd_1 : 8;
		unsigned int           BapmVddGfxVidHiSidd_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_65__VI {
	struct {
		unsigned int           BapmVddGfxVidHiSidd_7 : 8;
		unsigned int           BapmVddGfxVidHiSidd_6 : 8;
		unsigned int           BapmVddGfxVidHiSidd_5 : 8;
		unsigned int           BapmVddGfxVidHiSidd_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_66__VI {
	struct {
		unsigned int          BapmVddGfxVidHiSidd_11 : 8;
		unsigned int          BapmVddGfxVidHiSidd_10 : 8;
		unsigned int           BapmVddGfxVidHiSidd_9 : 8;
		unsigned int           BapmVddGfxVidHiSidd_8 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_67__VI {
	struct {
		unsigned int          BapmVddGfxVidHiSidd_15 : 8;
		unsigned int          BapmVddGfxVidHiSidd_14 : 8;
		unsigned int          BapmVddGfxVidHiSidd_13 : 8;
		unsigned int          BapmVddGfxVidHiSidd_12 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_68__VI {
	struct {
		unsigned int           BapmVddGfxVidLoSidd_3 : 8;
		unsigned int           BapmVddGfxVidLoSidd_2 : 8;
		unsigned int           BapmVddGfxVidLoSidd_1 : 8;
		unsigned int           BapmVddGfxVidLoSidd_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_69__VI {
	struct {
		unsigned int           BapmVddGfxVidLoSidd_7 : 8;
		unsigned int           BapmVddGfxVidLoSidd_6 : 8;
		unsigned int           BapmVddGfxVidLoSidd_5 : 8;
		unsigned int           BapmVddGfxVidLoSidd_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_7__VI {
	struct {
		unsigned int  GraphicsPIDController_MaxState : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_70__VI {
	struct {
		unsigned int          BapmVddGfxVidLoSidd_11 : 8;
		unsigned int          BapmVddGfxVidLoSidd_10 : 8;
		unsigned int           BapmVddGfxVidLoSidd_9 : 8;
		unsigned int           BapmVddGfxVidLoSidd_8 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_71__VI {
	struct {
		unsigned int          BapmVddGfxVidLoSidd_15 : 8;
		unsigned int          BapmVddGfxVidLoSidd_14 : 8;
		unsigned int          BapmVddGfxVidLoSidd_13 : 8;
		unsigned int          BapmVddGfxVidLoSidd_12 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_72__VI {
	struct {
		unsigned int          BapmVddGfxVidHiSidd2_3 : 8;
		unsigned int          BapmVddGfxVidHiSidd2_2 : 8;
		unsigned int          BapmVddGfxVidHiSidd2_1 : 8;
		unsigned int          BapmVddGfxVidHiSidd2_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_73__VI {
	struct {
		unsigned int          BapmVddGfxVidHiSidd2_7 : 8;
		unsigned int          BapmVddGfxVidHiSidd2_6 : 8;
		unsigned int          BapmVddGfxVidHiSidd2_5 : 8;
		unsigned int          BapmVddGfxVidHiSidd2_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_74__VI {
	struct {
		unsigned int         BapmVddGfxVidHiSidd2_11 : 8;
		unsigned int         BapmVddGfxVidHiSidd2_10 : 8;
		unsigned int          BapmVddGfxVidHiSidd2_9 : 8;
		unsigned int          BapmVddGfxVidHiSidd2_8 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_75__VI {
	struct {
		unsigned int         BapmVddGfxVidHiSidd2_15 : 8;
		unsigned int         BapmVddGfxVidHiSidd2_14 : 8;
		unsigned int         BapmVddGfxVidHiSidd2_13 : 8;
		unsigned int         BapmVddGfxVidHiSidd2_12 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_76__VI {
	struct {
		unsigned int             BapmVddcVidHiSidd_3 : 8;
		unsigned int             BapmVddcVidHiSidd_2 : 8;
		unsigned int             BapmVddcVidHiSidd_1 : 8;
		unsigned int             BapmVddcVidHiSidd_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_77__VI {
	struct {
		unsigned int             BapmVddcVidHiSidd_7 : 8;
		unsigned int             BapmVddcVidHiSidd_6 : 8;
		unsigned int             BapmVddcVidHiSidd_5 : 8;
		unsigned int             BapmVddcVidHiSidd_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_78__VI {
	struct {
		unsigned int            BapmVddcVidHiSidd_11 : 8;
		unsigned int            BapmVddcVidHiSidd_10 : 8;
		unsigned int             BapmVddcVidHiSidd_9 : 8;
		unsigned int             BapmVddcVidHiSidd_8 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_79__VI {
	struct {
		unsigned int            BapmVddcVidHiSidd_15 : 8;
		unsigned int            BapmVddcVidHiSidd_14 : 8;
		unsigned int            BapmVddcVidHiSidd_13 : 8;
		unsigned int            BapmVddcVidHiSidd_12 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_8__VI {
	struct {
		unsigned int GraphicsPIDController_MaxLfFraction : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_80__VI {
	struct {
		unsigned int             BapmVddcVidLoSidd_3 : 8;
		unsigned int             BapmVddcVidLoSidd_2 : 8;
		unsigned int             BapmVddcVidLoSidd_1 : 8;
		unsigned int             BapmVddcVidLoSidd_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_81__VI {
	struct {
		unsigned int             BapmVddcVidLoSidd_7 : 8;
		unsigned int             BapmVddcVidLoSidd_6 : 8;
		unsigned int             BapmVddcVidLoSidd_5 : 8;
		unsigned int             BapmVddcVidLoSidd_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_82__VI {
	struct {
		unsigned int            BapmVddcVidLoSidd_11 : 8;
		unsigned int            BapmVddcVidLoSidd_10 : 8;
		unsigned int             BapmVddcVidLoSidd_9 : 8;
		unsigned int             BapmVddcVidLoSidd_8 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_83__VI {
	struct {
		unsigned int            BapmVddcVidLoSidd_15 : 8;
		unsigned int            BapmVddcVidLoSidd_14 : 8;
		unsigned int            BapmVddcVidLoSidd_13 : 8;
		unsigned int            BapmVddcVidLoSidd_12 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_84__VI {
	struct {
		unsigned int            BapmVddcVidHiSidd2_3 : 8;
		unsigned int            BapmVddcVidHiSidd2_2 : 8;
		unsigned int            BapmVddcVidHiSidd2_1 : 8;
		unsigned int            BapmVddcVidHiSidd2_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_85__VI {
	struct {
		unsigned int            BapmVddcVidHiSidd2_7 : 8;
		unsigned int            BapmVddcVidHiSidd2_6 : 8;
		unsigned int            BapmVddcVidHiSidd2_5 : 8;
		unsigned int            BapmVddcVidHiSidd2_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_86__VI {
	struct {
		unsigned int           BapmVddcVidHiSidd2_11 : 8;
		unsigned int           BapmVddcVidHiSidd2_10 : 8;
		unsigned int            BapmVddcVidHiSidd2_9 : 8;
		unsigned int            BapmVddcVidHiSidd2_8 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_87__VI {
	struct {
		unsigned int           BapmVddcVidHiSidd2_15 : 8;
		unsigned int           BapmVddcVidHiSidd2_14 : 8;
		unsigned int           BapmVddcVidHiSidd2_13 : 8;
		unsigned int           BapmVddcVidHiSidd2_12 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_88__VI {
	struct {
		unsigned int          MasterDeepSleepControl : 8;
		unsigned int                  LinkLevelCount : 8;
		unsigned int             MemoryDpmLevelCount : 8;
		unsigned int           GraphicsDpmLevelCount : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_89__VI {
	struct {
		unsigned int                  SamuLevelCount : 8;
		unsigned int                   AcpLevelCount : 8;
		unsigned int                   VceLevelCount : 8;
		unsigned int                   UvdLevelCount : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_9__VI {
	struct {
		unsigned int GraphicsPIDController_StateShift : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_90__VI {
	struct {
		unsigned int                      Reserved_0 : 8;
		unsigned int                    ThermOutMode : 8;
		unsigned int                ThermOutPolarity : 8;
		unsigned int                    ThermOutGpio : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_91__VI {
	struct {
		unsigned int                      Reserved_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_92__VI {
	struct {
		unsigned int                      Reserved_1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_93__VI {
	struct {
		unsigned int                      Reserved_2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_94__VI {
	struct {
		unsigned int                      Reserved_3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_95__VI {
	struct {
		unsigned int GraphicsLevel_0_MinVoltage_Phases : 8;
		unsigned int GraphicsLevel_0_MinVoltage_VddGfx : 8;
		unsigned int GraphicsLevel_0_MinVoltage_Vddci : 8;
		unsigned int GraphicsLevel_0_MinVoltage_Vddc : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_96__VI {
	struct {
		unsigned int   GraphicsLevel_0_SclkFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_97__VI {
	struct {
		unsigned int   GraphicsLevel_0_ActivityLevel : 16;
		unsigned int  GraphicsLevel_0_DeepSleepDivId : 8;
		unsigned int    GraphicsLevel_0_pcieDpmLevel : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_98__VI {
	struct {
		unsigned int GraphicsLevel_0_CgSpllFuncCntl3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPM_TABLE_99__VI {
	struct {
		unsigned int GraphicsLevel_0_CgSpllFuncCntl4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPREFCLK_CGTT_BLK_CTRL_REG__VI {
	struct {
		unsigned int          DPREFCLK_TURN_ON_DELAY : 4;
		unsigned int         DPREFCLK_TURN_OFF_DELAY : 8;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DPREFCLK_CNTL__VI {
	struct {
		unsigned int                DPREFCLK_SRC_SEL : 3;
		unsigned int                                 : 5;
		unsigned int               UNB_DB_CLK_ENABLE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_A__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_A : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_B__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_B : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_C__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_D__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_D : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_E__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_E : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_F__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_F : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_G__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_G : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_H__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_H : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_I__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_I : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_J__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_J : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_K__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_K : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_L__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_L : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_M__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_M : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_N__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_N : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_O__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_O : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_P__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_P : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_AUX_DEBUG_Q__VI {
	struct {
		unsigned int                  DP_AUX_DEBUG_Q : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_CRC_MST_CNTL__VI {
	struct {
		unsigned int         DPHY_CRC_MST_FIRST_SLOT : 6;
		unsigned int                                 : 2;
		unsigned int          DPHY_CRC_MST_LAST_SLOT : 6;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_CRC_MST_STATUS__VI {
	struct {
		unsigned int         DPHY_CRC_MST_PHASE_LOCK : 1;
		unsigned int                                 : 7;
		unsigned int        DPHY_CRC_MST_PHASE_ERROR : 1;
		unsigned int                                 : 7;
		unsigned int    DPHY_CRC_MST_PHASE_ERROR_ACK : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_FAST_TRAINING_STATUS__VI {
	struct {
		unsigned int        DPHY_FAST_TRAINING_STATE : 3;
		unsigned int                                 : 1;
		unsigned int DPHY_FAST_TRAINING_COMPLETE_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int DPHY_FAST_TRAINING_COMPLETE_MASK : 1;
		unsigned int                                 : 3;
		unsigned int DPHY_FAST_TRAINING_COMPLETE_ACK : 1;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_SYM0__VI {
	struct {
		unsigned int                       DPHY_SYM1 : 10;
		unsigned int                       DPHY_SYM2 : 10;
		unsigned int                       DPHY_SYM3 : 10;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_SYM1__VI {
	struct {
		unsigned int                       DPHY_SYM4 : 10;
		unsigned int                       DPHY_SYM5 : 10;
		unsigned int                       DPHY_SYM6 : 10;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_DPHY_SYM2__VI {
	struct {
		unsigned int                       DPHY_SYM7 : 10;
		unsigned int                       DPHY_SYM8 : 10;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_FE_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int           DP_FE_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_FE_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int          DP_FE_TEST_DEBUG_INDEX : 8;
		unsigned int       DP_FE_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_HBR2_EYE_PATTERN__VI {
	struct {
		unsigned int      DP_HBR2_EYE_PATTERN_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_LINK_FRAMING_CNTL__VI {
	struct {
		unsigned int             DP_IDLE_BS_INTERVAL : 18;
		unsigned int                                 : 6;
		unsigned int                 DP_VBID_DISABLE : 1;
		unsigned int                                 : 3;
		unsigned int      DP_VID_ENHANCED_FRAME_MODE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSA_COLORIMETRY__VI {
	struct {
		unsigned int           DP_MSA_MISC0_OVERRIDE : 8;
		unsigned int    DP_MSA_MISC0_OVERRIDE_ENABLE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSA_MISC__VI {
	struct {
		unsigned int                                 : 3;
		unsigned int                    DP_MSA_MISC1 : 4;
		unsigned int                                 : 1;
		unsigned int                    DP_MSA_MISC2 : 8;
		unsigned int                    DP_MSA_MISC3 : 8;
		unsigned int                    DP_MSA_MISC4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSA_V_TIMING_OVERRIDE1__VI {
	struct {
		unsigned int     DP_MSA_V_TIMING_OVERRIDE_EN : 1;
		unsigned int                                 : 3;
		unsigned int         DP_MSA_V_TOTAL_OVERRIDE : 14;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSA_V_TIMING_OVERRIDE2__VI {
	struct {
		unsigned int   DP_MSA_V_BLANK_START_OVERRIDE : 14;
		unsigned int                                 : 2;
		unsigned int     DP_MSA_V_BLANK_END_OVERRIDE : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSE_LINK_TIMING__VI {
	struct {
		unsigned int               DP_MSE_LINK_FRAME : 10;
		unsigned int                                 : 6;
		unsigned int                DP_MSE_LINK_LINE : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSE_MISC_CNTL__VI {
	struct {
		unsigned int               DP_MSE_BLANK_CODE : 1;
		unsigned int                                 : 3;
		unsigned int           DP_MSE_TIMESTAMP_MODE : 1;
		unsigned int                                 : 3;
		unsigned int             DP_MSE_ZERO_ENCODER : 1;
		unsigned int                                 : 7;
		unsigned int        DP_MSE_OUTPUT_DPDBG_DATA : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSE_RATE_CNTL__VI {
	struct {
		unsigned int                   DP_MSE_RATE_Y : 26;
		unsigned int                   DP_MSE_RATE_X : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSE_RATE_UPDATE__VI {
	struct {
		unsigned int      DP_MSE_RATE_UPDATE_PENDING : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSE_SAT0__VI {
	struct {
		unsigned int                 DP_MSE_SAT_SRC0 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int          DP_MSE_SAT_SLOT_COUNT0 : 6;
		unsigned int                                 : 2;
		unsigned int                 DP_MSE_SAT_SRC1 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int          DP_MSE_SAT_SLOT_COUNT1 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSE_SAT1__VI {
	struct {
		unsigned int                 DP_MSE_SAT_SRC2 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int          DP_MSE_SAT_SLOT_COUNT2 : 6;
		unsigned int                                 : 2;
		unsigned int                 DP_MSE_SAT_SRC3 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int          DP_MSE_SAT_SLOT_COUNT3 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSE_SAT2__VI {
	struct {
		unsigned int                 DP_MSE_SAT_SRC4 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int          DP_MSE_SAT_SLOT_COUNT4 : 6;
		unsigned int                                 : 2;
		unsigned int                 DP_MSE_SAT_SRC5 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int          DP_MSE_SAT_SLOT_COUNT5 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_MSE_SAT_UPDATE__VI {
	struct {
		unsigned int               DP_MSE_SAT_UPDATE : 2;
		unsigned int                                 : 6;
		unsigned int           DP_MSE_16_MTP_KEEPOUT : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DP_SEC_CNTL1__VI {
	struct {
		unsigned int              DP_SEC_ISRC_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_CLK_ENABLE__VI {
	struct {
		unsigned int                  DVO_CLK_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_FIFO_ERROR_STATUS__VI {
	struct {
		unsigned int            DVO_FIFO_LEVEL_ERROR : 1;
		unsigned int    DVO_FIFO_USE_OVERWRITE_LEVEL : 1;
		unsigned int        DVO_FIFO_OVERWRITE_LEVEL : 6;
		unsigned int              DVO_FIFO_ERROR_ACK : 1;
		unsigned int                                 : 1;
		unsigned int      DVO_FIFO_CAL_AVERAGE_LEVEL : 6;
		unsigned int          DVO_FIFO_MAXIMUM_LEVEL : 4;
		unsigned int                                 : 2;
		unsigned int          DVO_FIFO_MINIMUM_LEVEL : 4;
		unsigned int                                 : 3;
		unsigned int             DVO_FIFO_CALIBRATED : 1;
		unsigned int    DVO_FIFO_FORCE_RECAL_AVERAGE : 1;
		unsigned int    DVO_FIFO_FORCE_RECOMP_MINMAX : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_SKEW_ADJUST__VI {
	struct {
		unsigned int                 DVO_SKEW_ADJUST : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int             DVO_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int            DVO_TEST_DEBUG_INDEX : 8;
		unsigned int         DVO_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union DVO_VREF_CONTROL__VI {
	struct {
		unsigned int                     DVO_VREFPON : 1;
		unsigned int                     DVO_VREFSEL : 1;
		unsigned int                                 : 2;
		unsigned int                     DVO_VREFCAL : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union ENTITY_TEMPERATURES_1__VI {
	struct {
		unsigned int                             GPU : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_DEBUG_CSR_RDATA_HI__VI {
	struct {
		unsigned int          FBC_DEBUG_CSR_RDATA_HI : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_DEBUG_CSR_WDATA_HI__VI {
	struct {
		unsigned int          FBC_DEBUG_CSR_WDATA_HI : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FBC_STATUS__VI {
	struct {
		unsigned int               FBC_ENABLE_STATUS : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FEATURE_STATUS__VI {
	struct {
		unsigned int                     SCLK_DPM_ON : 1;
		unsigned int                     MCLK_DPM_ON : 1;
		unsigned int                     LCLK_DPM_ON : 1;
		unsigned int                      UVD_DPM_ON : 1;
		unsigned int                      VCE_DPM_ON : 1;
		unsigned int                     SAMU_DPM_ON : 1;
		unsigned int                      ACP_DPM_ON : 1;
		unsigned int                     PCIE_DPM_ON : 1;
		unsigned int                         BAPM_ON : 1;
		unsigned int                         LPMX_ON : 1;
		unsigned int                        NBDPM_ON : 1;
		unsigned int                         LHTC_ON : 1;
		unsigned int                          VPC_ON : 1;
		unsigned int           VOLTAGE_CONTROLLER_ON : 1;
		unsigned int                    TDC_LIMIT_ON : 1;
		unsigned int                      GPU_CAC_ON : 1;
		unsigned int                          AVS_ON : 1;
		unsigned int                         SPMI_ON : 1;
		unsigned int                 SCLK_DPM_FORCED : 1;
		unsigned int                 MCLK_DPM_FORCED : 1;
		unsigned int                 LCLK_DPM_FORCED : 1;
		unsigned int                 PCIE_DPM_FORCED : 1;
		unsigned int                        RESERVED : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CLAMP_COMPONENT_B__VI {
	struct {
		unsigned int               FMT_CLAMP_LOWER_B : 16;
		unsigned int               FMT_CLAMP_UPPER_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CLAMP_COMPONENT_G__VI {
	struct {
		unsigned int               FMT_CLAMP_LOWER_G : 16;
		unsigned int               FMT_CLAMP_UPPER_G : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_CLAMP_COMPONENT_R__VI {
	struct {
		unsigned int               FMT_CLAMP_LOWER_R : 16;
		unsigned int               FMT_CLAMP_UPPER_R : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_DEBUG0__VI {
	struct {
		unsigned int                      FMT_DEBUG0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_DEBUG1__VI {
	struct {
		unsigned int                      FMT_DEBUG1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_DEBUG2__VI {
	struct {
		unsigned int                      FMT_DEBUG2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_DEBUG_ID__VI {
	struct {
		unsigned int                    FMT_DEBUG_ID : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int             FMT_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union FMT_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int            FMT_TEST_DEBUG_INDEX : 8;
		unsigned int         FMT_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_END_CNTL1__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION_END : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_END_CNTL2__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE : 16;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION_END_BASE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_REGION_0_1__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_REGION_10_11__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_REGION_12_13__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_REGION_14_15__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_REGION_2_3__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_REGION_4_5__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_REGION_6_7__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_REGION_8_9__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_SLOPE_CNTL__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLA_START_CNTL__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION_START : 18;
		unsigned int                                 : 2;
		unsigned int GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT : 7;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_END_CNTL1__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION_END : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_END_CNTL2__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE : 16;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION_END_BASE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_REGION_0_1__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_REGION_10_11__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_REGION_12_13__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_REGION_14_15__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_REGION_2_3__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_REGION_4_5__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_REGION_6_7__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_REGION_8_9__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET : 8;
		unsigned int                                 : 3;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET : 8;
		unsigned int                                 : 4;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_SLOPE_CNTL__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CNTLB_START_CNTL__VI {
	struct {
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION_START : 18;
		unsigned int                                 : 2;
		unsigned int GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT : 7;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_CONTROL__VI {
	struct {
		unsigned int                 GAMMA_CORR_MODE : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_LUT_DATA__VI {
	struct {
		unsigned int             GAMMA_CORR_LUT_DATA : 19;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_LUT_INDEX__VI {
	struct {
		unsigned int            GAMMA_CORR_LUT_INDEX : 9;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMMA_CORR_LUT_WRITE_EN_MASK__VI {
	struct {
		unsigned int    GAMMA_CORR_LUT_WRITE_EN_MASK : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMUT_REMAP_C11_C12__VI {
	struct {
		unsigned int                 GAMUT_REMAP_C11 : 16;
		unsigned int                 GAMUT_REMAP_C12 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMUT_REMAP_C13_C14__VI {
	struct {
		unsigned int                 GAMUT_REMAP_C13 : 16;
		unsigned int                 GAMUT_REMAP_C14 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMUT_REMAP_C21_C22__VI {
	struct {
		unsigned int                 GAMUT_REMAP_C21 : 16;
		unsigned int                 GAMUT_REMAP_C22 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMUT_REMAP_C23_C24__VI {
	struct {
		unsigned int                 GAMUT_REMAP_C23 : 16;
		unsigned int                 GAMUT_REMAP_C24 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMUT_REMAP_C31_C32__VI {
	struct {
		unsigned int                 GAMUT_REMAP_C31 : 16;
		unsigned int                 GAMUT_REMAP_C32 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMUT_REMAP_C33_C34__VI {
	struct {
		unsigned int                 GAMUT_REMAP_C33 : 16;
		unsigned int                 GAMUT_REMAP_C34 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GAMUT_REMAP_CONTROL__VI {
	struct {
		unsigned int           GRPH_GAMUT_REMAP_MODE : 2;
		unsigned int                                 : 2;
		unsigned int            OVL_GAMUT_REMAP_MODE : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_CP_DMA_ME_COMMAND__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_CP_DMA_PFP_COMMAND__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_CP_DMA_PIO_COMMAND__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_CP_RB0_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_CP_RB1_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_CP_RB2_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_GARLIC_FLUSH_REQ__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_SAM_SAB_RBI_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_SAM_SAB_RBO_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_SDMA0_GFX_RB_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_SDMA1_GFX_RB_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_SDMA2_GFX_RB_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_SDMA3_GFX_RB_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_UVD_RBC_RB_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_VCE_OUT_RB_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_VCE_RB_WPTR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GARLIC_COHE_VCE_RB_WPTR2__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GCK_ADFS_CLK_BYPASS_CNTL1__VI {
	struct {
		unsigned int                ECLK_BYPASS_CNTL : 3;
		unsigned int                SCLK_BYPASS_CNTL : 3;
		unsigned int                LCLK_BYPASS_CNTL : 3;
		unsigned int                DCLK_BYPASS_CNTL : 3;
		unsigned int                VCLK_BYPASS_CNTL : 3;
		unsigned int             DISPCLK_BYPASS_CNTL : 3;
		unsigned int            DRREFCLK_BYPASS_CNTL : 3;
		unsigned int                ACLK_BYPASS_CNTL : 3;
		unsigned int              SAMCLK_BYPASS_CNTL : 3;
		unsigned int            ACLK_DIV_BYPASS_CNTL : 3;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GCK_DFS_BYPASS_CNTL__VI {
	struct {
                unsigned int                      BYPASSECLK : 1;
                unsigned int                      BYPASSLCLK : 1;
                unsigned int                     BYPASSEVCLK : 1;
                unsigned int                      BYPASSDCLK : 1;
                unsigned int                      BYPASSVCLK : 1;
                unsigned int                   BYPASSDISPCLK : 1;
                unsigned int                  BYPASSDPREFCLK : 1;
                unsigned int                      BYPASSACLK : 1;
                unsigned int                   BYPASSADIVCLK : 1;
                unsigned int                    BYPASSPSPCLK : 1;
                unsigned int                    BYPASSSAMCLK : 1;
                unsigned int                      BYPASSSCLK : 1;
                unsigned int              USE_SPLL_BYPASS_EN : 1;
                unsigned int                      BYPASSMCLK : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GCK_MCLK_FUSES__VI {
	struct {
		unsigned int                  StartupMClkDid : 7;
		unsigned int                        MClkADCA : 4;
		unsigned int                        MClkDDCA : 2;
		unsigned int                    MClkDiDtWait : 3;
		unsigned int                   MClkDiDtFloor : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GCK_PLL_TEST_CNTL_2__VI {
	struct {
		unsigned int                                 : 17;
		unsigned int                      TEST_COUNT : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU0__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU1__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU10__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU11__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU12__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU13__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU14__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU15__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU2__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU3__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU4__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU5__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU6__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU7__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU8__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_ACC_CU9__VI {
	struct {
		unsigned int                ACCUMULATOR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_CGTT_CLK_CTRL__VI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 18;
		unsigned int               SOFT_OVERRIDE_DYN : 1;
		unsigned int               SOFT_OVERRIDE_REG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_LKG_AGGR_LOWER__VI {
	struct {
		unsigned int                   LKG_AGGR_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_LKG_AGGR_UPPER__VI {
	struct {
		unsigned int                  LKG_AGGR_63_32 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_OVRD_CU__VI {
	struct {
		unsigned int                    OVRRD_SELECT : 16;
		unsigned int                     OVRRD_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_WEIGHT_CU_0__VI {
	struct {
		unsigned int                  WEIGHT_CU_SIG0 : 16;
		unsigned int                  WEIGHT_CU_SIG1 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_WEIGHT_CU_1__VI {
	struct {
		unsigned int                  WEIGHT_CU_SIG2 : 16;
		unsigned int                  WEIGHT_CU_SIG3 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_WEIGHT_CU_2__VI {
	struct {
		unsigned int                  WEIGHT_CU_SIG4 : 16;
		unsigned int                  WEIGHT_CU_SIG5 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_WEIGHT_CU_3__VI {
	struct {
		unsigned int                  WEIGHT_CU_SIG6 : 16;
		unsigned int                  WEIGHT_CU_SIG7 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_WEIGHT_CU_4__VI {
	struct {
		unsigned int                  WEIGHT_CU_SIG8 : 16;
		unsigned int                  WEIGHT_CU_SIG9 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_WEIGHT_CU_5__VI {
	struct {
		unsigned int                 WEIGHT_CU_SIG10 : 16;
		unsigned int                 WEIGHT_CU_SIG11 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_WEIGHT_CU_6__VI {
	struct {
		unsigned int                 WEIGHT_CU_SIG12 : 16;
		unsigned int                 WEIGHT_CU_SIG13 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_CAC_WEIGHT_CU_7__VI {
	struct {
		unsigned int                 WEIGHT_CU_SIG14 : 16;
		unsigned int                 WEIGHT_CU_SIG15 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GC_USER_SHADER_RATE_CONFIG__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                       DPFP_RATE : 2;
		unsigned int             SQC_BALANCE_DISABLE : 1;
		unsigned int                        HALF_LDS : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_CS_CTXSW_CNT0__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_CS_CTXSW_CNT1__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_CS_CTXSW_CNT2__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_CS_CTXSW_CNT3__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_CS_CTXSW_STATUS__VI {
	struct {
		unsigned int                               R : 1;
		unsigned int                               W : 1;
		unsigned int                          UNUSED : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_DSM_CNTL__VI {
	struct {
		unsigned int  SEL_DSM_GDS_IRRITATOR_DATA_A_0 : 1;
		unsigned int  SEL_DSM_GDS_IRRITATOR_DATA_A_1 : 1;
		unsigned int       GDS_ENABLE_SINGLE_WRITE_A : 1;
		unsigned int  SEL_DSM_GDS_IRRITATOR_DATA_B_0 : 1;
		unsigned int  SEL_DSM_GDS_IRRITATOR_DATA_B_1 : 1;
		unsigned int       GDS_ENABLE_SINGLE_WRITE_B : 1;
		unsigned int                          UNUSED : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_EDC_CNT__VI {
	struct {
		unsigned int                             DED : 8;
		unsigned int                             SED : 8;
		unsigned int                             SEC : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_EDC_GRBM_CNT__VI {
	struct {
		unsigned int                             DED : 8;
		unsigned int                                 : 8;
		unsigned int                             SEC : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_EDC_OA_DED__VI {
	struct {
		unsigned int             ME0_GFXHP3D_PIX_DED : 1;
		unsigned int             ME0_GFXHP3D_VTX_DED : 1;
		unsigned int                      ME0_CS_DED : 1;
		unsigned int                         UNUSED0 : 1;
		unsigned int                   ME1_PIPE0_DED : 1;
		unsigned int                   ME1_PIPE1_DED : 1;
		unsigned int                   ME1_PIPE2_DED : 1;
		unsigned int                   ME1_PIPE3_DED : 1;
		unsigned int                   ME2_PIPE0_DED : 1;
		unsigned int                   ME2_PIPE1_DED : 1;
		unsigned int                   ME2_PIPE2_DED : 1;
		unsigned int                   ME2_PIPE3_DED : 1;
		unsigned int                         UNUSED1 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_GFX_CTXSW_STATUS__VI {
	struct {
		unsigned int                               R : 1;
		unsigned int                               W : 1;
		unsigned int                          UNUSED : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS0_CTXSW_CNT0__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS0_CTXSW_CNT1__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS0_CTXSW_CNT2__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS0_CTXSW_CNT3__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS1_CTXSW_CNT0__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS1_CTXSW_CNT1__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS1_CTXSW_CNT2__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS1_CTXSW_CNT3__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS2_CTXSW_CNT0__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS2_CTXSW_CNT1__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS2_CTXSW_CNT2__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS2_CTXSW_CNT3__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS3_CTXSW_CNT0__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS3_CTXSW_CNT1__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS3_CTXSW_CNT2__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS3_CTXSW_CNT3__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS4_CTXSW_CNT0__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS4_CTXSW_CNT1__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS4_CTXSW_CNT2__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS4_CTXSW_CNT3__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS5_CTXSW_CNT0__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS5_CTXSW_CNT1__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS5_CTXSW_CNT2__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS5_CTXSW_CNT3__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS6_CTXSW_CNT0__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS6_CTXSW_CNT1__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS6_CTXSW_CNT2__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS6_CTXSW_CNT3__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS7_CTXSW_CNT0__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS7_CTXSW_CNT1__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS7_CTXSW_CNT2__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_PS7_CTXSW_CNT3__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VS_CTXSW_CNT0__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VS_CTXSW_CNT1__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VS_CTXSW_CNT2__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GDS_VS_CTXSW_CNT3__VI {
	struct {
		unsigned int                            UPDN : 16;
		unsigned int                             PTR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GMCON_LPT_TARGET__VI {
	struct {
		unsigned int               STCTRL_LPT_TARGET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GPU_BIST_CONTROL__VI {
	struct {
		unsigned int                 STOP_ON_FAIL_HW : 1;
		unsigned int            STOP_ON_FAIL_CU_HARV : 1;
		unsigned int              CU_HARV_LOOP_COUNT : 4;
		unsigned int                                 : 1;
		unsigned int                        RESERVED : 17;
		unsigned int               GLOBAL_LOOP_COUNT : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_DSM_BYPASS__VI {
	struct {
		unsigned int                     BYPASS_BITS : 2;
		unsigned int                       BYPASS_EN : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_HYP_CAM_DATA__VI {
	struct {
		unsigned int                        CAM_ADDR : 16;
		unsigned int                   CAM_REMAPADDR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_HYP_CAM_INDEX__VI {
	struct {
		unsigned int                       CAM_INDEX : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_TRAP_ADDR__VI {
	struct {
		unsigned int                            DATA : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_TRAP_ADDR_MSK__VI {
	struct {
		unsigned int                            DATA : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_TRAP_OP__VI {
	struct {
		unsigned int                              RW : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_TRAP_WD__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_TRAP_WD_MSK__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRBM_WRITE_ERROR__VI {
	struct {
		unsigned int             WRITE_REQUESTER_RLC : 1;
		unsigned int            WRITE_REQUESTER_SRBM : 1;
		unsigned int                    WRITE_SSRCID : 3;
		unsigned int                      WRITE_VFID : 4;
		unsigned int                                 : 3;
		unsigned int                        WRITE_VF : 1;
		unsigned int                      WRITE_VMID : 4;
		unsigned int                                 : 3;
		unsigned int                    WRITE_PIPEID : 2;
		unsigned int                      WRITE_MEID : 2;
		unsigned int                                 : 7;
		unsigned int                     WRITE_ERROR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_FLIP_RATE_CNTL__VI {
	struct {
		unsigned int                  GRPH_FLIP_RATE : 3;
		unsigned int           GRPH_FLIP_RATE_ENABLE : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_STEREOSYNC_FLIP__VI {
	struct {
		unsigned int         GRPH_STEREOSYNC_FLIP_EN : 1;
		unsigned int                                 : 7;
		unsigned int       GRPH_STEREOSYNC_FLIP_MODE : 2;
		unsigned int                                 : 6;
		unsigned int    GRPH_PRIMARY_SURFACE_PENDING : 1;
		unsigned int  GRPH_SECONDARY_SURFACE_PENDING : 1;
		unsigned int                                 : 10;
		unsigned int  GRPH_STEREOSYNC_SELECT_DISABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI {
	struct {
		unsigned int GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN : 1;
		unsigned int GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE : 1;
		unsigned int                                 : 2;
		unsigned int GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT : 13;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI {
	struct {
		unsigned int   GRPH_XDMA_CACHE_UNDERFLOW_CNT : 20;
		unsigned int                                 : 4;
		unsigned int GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS : 1;
		unsigned int GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK : 1;
		unsigned int GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK : 1;
		unsigned int                                 : 1;
		unsigned int   GRPH_XDMA_CACHE_UNDERFLOW_INT : 1;
		unsigned int GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK : 1;
		unsigned int GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int GRPH_XDMA_RECOVERY_SURFACE_ADDRESS : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI {
	struct {
		unsigned int GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union GSKT_CONTROL__VI {
	struct {
		unsigned int               GSKT_TxFifoBypass : 1;
		unsigned int                GSKT_TxFifoDelay : 1;
		unsigned int               GSKT_TxFifoDelay2 : 1;
		unsigned int                  GSKT_SpareRegs : 5;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_GENERIC_PACKET_CONTROL0__VI {
	struct {
		unsigned int              HDMI_GENERIC0_SEND : 1;
		unsigned int              HDMI_GENERIC0_CONT : 1;
		unsigned int                                 : 2;
		unsigned int              HDMI_GENERIC1_SEND : 1;
		unsigned int              HDMI_GENERIC1_CONT : 1;
		unsigned int                                 : 10;
		unsigned int              HDMI_GENERIC0_LINE : 6;
		unsigned int                                 : 2;
		unsigned int              HDMI_GENERIC1_LINE : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDMI_GENERIC_PACKET_CONTROL1__VI {
	struct {
		unsigned int              HDMI_GENERIC2_SEND : 1;
		unsigned int              HDMI_GENERIC2_CONT : 1;
		unsigned int                                 : 2;
		unsigned int              HDMI_GENERIC3_SEND : 1;
		unsigned int              HDMI_GENERIC3_CONT : 1;
		unsigned int                                 : 10;
		unsigned int              HDMI_GENERIC2_LINE : 6;
		unsigned int                                 : 2;
		unsigned int              HDMI_GENERIC3_LINE : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_ADDR_CONFIG__VI {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                        NUM_GPUS : 3;
		unsigned int                                 : 1;
		unsigned int             MULTI_GPU_TILE_SIZE : 2;
		unsigned int                                 : 2;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_MEMIO_ADDR__VI {
	struct {
		unsigned int                MEMIO_ADDR_LOWER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_MEMIO_CNTL__VI {
	struct {
		unsigned int                      MEMIO_SEND : 1;
		unsigned int                        MEMIO_OP : 1;
		unsigned int                        MEMIO_BE : 4;
		unsigned int                 MEMIO_WR_STROBE : 1;
		unsigned int                 MEMIO_RD_STROBE : 1;
		unsigned int                MEMIO_ADDR_UPPER : 6;
		unsigned int              MEMIO_CLR_WR_ERROR : 1;
		unsigned int              MEMIO_CLR_RD_ERROR : 1;
		unsigned int                        MEMIO_VF : 1;
		unsigned int                      MEMIO_VFID : 4;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_MEMIO_RD_DATA__VI {
	struct {
		unsigned int                   MEMIO_RD_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_MEMIO_STATUS__VI {
	struct {
		unsigned int                 MEMIO_WR_STATUS : 1;
		unsigned int                 MEMIO_RD_STATUS : 1;
		unsigned int                  MEMIO_WR_ERROR : 1;
		unsigned int                  MEMIO_RD_ERROR : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_MEMIO_WR_DATA__VI {
	struct {
		unsigned int                   MEMIO_WR_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_MEM_POWER_LS__VI {
	struct {
		unsigned int                       LS_ENABLE : 1;
		unsigned int                        LS_SETUP : 6;
		unsigned int                         LS_HOLD : 6;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_MISC_CNTL__VI {
	struct {
		unsigned int          FLUSH_INVALIDATE_CACHE : 1;
		unsigned int                           VM_ID : 4;
		unsigned int    OUTSTANDING_WRITE_COUNT_1024 : 1;
		unsigned int                  MULTIPLE_READS : 1;
		unsigned int            HDP_BIF_RDRET_CREDIT : 4;
		unsigned int       SIMULTANEOUS_READS_WRITES : 1;
		unsigned int           NO_SPLIT_ARRAY_LINEAR : 1;
		unsigned int                 MC_RDREQ_CREDIT : 6;
		unsigned int           READ_CACHE_INVALIDATE : 1;
		unsigned int           ADDRLIB_LINEAR_BYPASS : 1;
		unsigned int                      FED_ENABLE : 1;
		unsigned int            LEGACY_TILING_ENABLE : 1;
		unsigned int          LEGACY_SURFACES_ENABLE : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_NONSURFACE_PREFETCH__VI {
	struct {
		unsigned int            NONSURF_PREFETCH_PRI : 3;
		unsigned int            NONSURF_PREFETCH_DIR : 3;
		unsigned int            NONSURF_PREFETCH_NUM : 3;
		unsigned int          NONSURF_PREFETCH_MAX_Z : 11;
		unsigned int                                 : 7;
		unsigned int             NONSURF_PIPE_CONFIG : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_VF_ENABLE__VI {
	struct {
		unsigned int                           VF_EN : 1;
		unsigned int                                 : 15;
		unsigned int                          VF_NUM : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HDP_XDP_BARS_ADDR_39_36__VI {
	struct {
		unsigned int                 BAR0_ADDR_39_36 : 4;
		unsigned int                 BAR1_ADDR_39_36 : 4;
		unsigned int                 BAR2_ADDR_39_36 : 4;
		unsigned int                 BAR3_ADDR_39_36 : 4;
		unsigned int                 BAR4_ADDR_39_36 : 4;
		unsigned int                 BAR5_ADDR_39_36 : 4;
		unsigned int                 BAR6_ADDR_39_36 : 4;
		unsigned int                 BAR7_ADDR_39_36 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union HW_ROTATION__VI {
	struct {
		unsigned int             GRPH_ROTATION_ANGLE : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_ACTIVE_FCN_ID__VI {
	struct {
		unsigned int                           VF_ID : 4;
		unsigned int                        RESERVED : 27;
		unsigned int                           PF_VF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VI {
	struct {
		unsigned int                              CG : 1;
		unsigned int                              DC : 1;
		unsigned int                                 : 1;
		unsigned int                          SAMMSP : 1;
		unsigned int                             RLC : 1;
		unsigned int                             ROM : 1;
		unsigned int                            SRBM : 1;
		unsigned int                             VMC : 1;
		unsigned int                             UVD : 1;
		unsigned int                             BIF : 1;
		unsigned int                           SDMA0 : 1;
		unsigned int                           SDMA1 : 1;
		unsigned int                             ISP : 1;
		unsigned int                            VCE0 : 1;
		unsigned int                            VCE1 : 1;
		unsigned int                             ATC : 1;
		unsigned int                            XDMA : 1;
		unsigned int                             ACP : 1;
		unsigned int                              SH : 1;
		unsigned int                             SH1 : 1;
		unsigned int                             SH2 : 1;
		unsigned int                             SH3 : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_DEBUG__VI {
	struct {
		unsigned int            RB_FULL_DRAIN_ENABLE : 1;
		unsigned int            WPTR_OVERFLOW_ENABLE : 1;
		unsigned int         MC_WR_FIFO_BLOCK_ENABLE : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_DOORBELL_RPTR__VI {
	struct {
		unsigned int                          OFFSET : 21;
		unsigned int                                 : 7;
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                        CAPTURED : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_DSM_MATCH_DATA_CONTROL__VI {
	struct {
		unsigned int                           VALUE : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_DSM_MATCH_FIELD_CONTROL__VI {
	struct {
                unsigned int                          SRC_EN : 1;
                unsigned int                        FCNID_EN : 1;
                unsigned int                    TIMESTAMP_EN : 1;
                unsigned int                       RINGID_EN : 1;
                unsigned int                         VMID_EN : 1;
                unsigned int                        PASID_EN : 1;
                unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_DSM_MATCH_VALUE_BIT_31_0__VI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_DSM_MATCH_VALUE_BIT_63_32__VI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_DSM_MATCH_VALUE_BIT_95_64__VI {
	struct {
		unsigned int                           VALUE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_LEVEL_INTR_MASK__VI {
	struct {
		unsigned int                            MASK : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_RESET_INCOMPLETE_INT_CNTL__VI {
	struct {
		unsigned int                              CG : 1;
		unsigned int                              DC : 1;
		unsigned int                                 : 1;
		unsigned int                          SAMMSP : 1;
		unsigned int                             RLC : 1;
		unsigned int                             ROM : 1;
		unsigned int                            SRBM : 1;
		unsigned int                             VMC : 1;
		unsigned int                             UVD : 1;
		unsigned int                             BIF : 1;
		unsigned int                           SDMA0 : 1;
		unsigned int                           SDMA1 : 1;
		unsigned int                             ISP : 1;
		unsigned int                            VCE0 : 1;
		unsigned int                            VCE1 : 1;
		unsigned int                             ATC : 1;
		unsigned int                            XDMA : 1;
		unsigned int                             ACP : 1;
		unsigned int                              SH : 1;
		unsigned int                             SH1 : 1;
		unsigned int                             SH2 : 1;
		unsigned int                             SH3 : 1;
		unsigned int                    RESET_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                  INCOMPLETE_CNT : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VERSION__VI {
	struct {
		unsigned int                           VALUE : 12;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VF_ENABLE__VI {
	struct {
		unsigned int                           VALUE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VF_RB_BIF_STATUS__VI {
	struct {
		unsigned int                      RB_FULL_VF : 16;
		unsigned int           BIF_INTERRUPT_LINE_VF : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VF_RB_STATUS__VI {
	struct {
		unsigned int                RB_FULL_DRAIN_VF : 16;
		unsigned int                  RB_OVERFLOW_VF : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union IH_VIRT_RESET_REQ__VI {
	struct {
		unsigned int                              VF : 16;
		unsigned int                                 : 15;
		unsigned int                              PF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C11_C12__VI {
	struct {
		unsigned int                   INPUT_CSC_C11 : 16;
		unsigned int                   INPUT_CSC_C12 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C11_C12_A__VI {
	struct {
		unsigned int                 INPUT_CSC_C11_A : 16;
		unsigned int                 INPUT_CSC_C12_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C11_C12_B__VI {
	struct {
		unsigned int                 INPUT_CSC_C11_B : 16;
		unsigned int                 INPUT_CSC_C12_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C13_C14__VI {
	struct {
		unsigned int                   INPUT_CSC_C13 : 16;
		unsigned int                   INPUT_CSC_C14 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C13_C14_A__VI {
	struct {
		unsigned int                 INPUT_CSC_C13_A : 16;
		unsigned int                 INPUT_CSC_C14_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C13_C14_B__VI {
	struct {
		unsigned int                 INPUT_CSC_C13_B : 16;
		unsigned int                 INPUT_CSC_C14_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C21_C22__VI {
	struct {
		unsigned int                   INPUT_CSC_C21 : 16;
		unsigned int                   INPUT_CSC_C22 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C21_C22_A__VI {
	struct {
		unsigned int                 INPUT_CSC_C21_A : 16;
		unsigned int                 INPUT_CSC_C22_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C21_C22_B__VI {
	struct {
		unsigned int                 INPUT_CSC_C21_B : 16;
		unsigned int                 INPUT_CSC_C22_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C23_C24__VI {
	struct {
		unsigned int                   INPUT_CSC_C23 : 16;
		unsigned int                   INPUT_CSC_C24 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C23_C24_A__VI {
	struct {
		unsigned int                 INPUT_CSC_C23_A : 16;
		unsigned int                 INPUT_CSC_C24_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C23_C24_B__VI {
	struct {
		unsigned int                 INPUT_CSC_C23_B : 16;
		unsigned int                 INPUT_CSC_C24_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C31_C32__VI {
	struct {
		unsigned int                   INPUT_CSC_C31 : 16;
		unsigned int                   INPUT_CSC_C32 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C31_C32_A__VI {
	struct {
		unsigned int                 INPUT_CSC_C31_A : 16;
		unsigned int                 INPUT_CSC_C32_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C31_C32_B__VI {
	struct {
		unsigned int                 INPUT_CSC_C31_B : 16;
		unsigned int                 INPUT_CSC_C32_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C33_C34__VI {
	struct {
		unsigned int                   INPUT_CSC_C33 : 16;
		unsigned int                   INPUT_CSC_C34 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C33_C34_A__VI {
	struct {
		unsigned int                 INPUT_CSC_C33_A : 16;
		unsigned int                 INPUT_CSC_C34_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_C33_C34_B__VI {
	struct {
		unsigned int                 INPUT_CSC_C33_B : 16;
		unsigned int                 INPUT_CSC_C34_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_CSC_CONTROL__VI {
	struct {
		unsigned int             INPUT_CSC_GRPH_MODE : 2;
		unsigned int                                 : 2;
		unsigned int              INPUT_CSC_OVL_MODE : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_GAMMA_CONTROL__VI {
	struct {
		unsigned int           GRPH_INPUT_GAMMA_MODE : 2;
		unsigned int                                 : 2;
		unsigned int            OVL_INPUT_GAMMA_MODE : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union INPUT_STREAM_PAYLOAD_CAPABILITY__VI {
	struct {
		unsigned int                       INSTRMPAY : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KEY_CONTROL__VI {
	struct {
		unsigned int                      KEY_SELECT : 1;
		unsigned int                        KEY_MODE : 2;
		unsigned int                                 : 25;
		unsigned int             GRPH_OVL_HALF_BLEND : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KEY_RANGE_ALPHA__VI {
	struct {
		unsigned int                   KEY_ALPHA_LOW : 16;
		unsigned int                  KEY_ALPHA_HIGH : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KEY_RANGE_BLUE__VI {
	struct {
		unsigned int                    KEY_BLUE_LOW : 16;
		unsigned int                   KEY_BLUE_HIGH : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KEY_RANGE_GREEN__VI {
	struct {
		unsigned int                   KEY_GREEN_LOW : 16;
		unsigned int                  KEY_GREEN_HIGH : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union KEY_RANGE_RED__VI {
	struct {
		unsigned int                     KEY_RED_LOW : 16;
		unsigned int                    KEY_RED_HIGH : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_BLACK_KEYER_B_CB__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int             LB_BLACK_KEYER_B_CB : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_BLACK_KEYER_G_Y__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int              LB_BLACK_KEYER_G_Y : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_BLACK_KEYER_R_CR__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int             LB_BLACK_KEYER_R_CR : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_BUFFER_LEVEL_STATUS__VI {
	struct {
		unsigned int                  REQ_FIFO_LEVEL : 6;
		unsigned int                                 : 4;
		unsigned int              REQ_FIFO_FULL_CNTL : 6;
		unsigned int               DATA_BUFFER_LEVEL : 12;
		unsigned int             DATA_FIFO_FULL_CNTL : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_BUFFER_STATUS__VI {
	struct {
		unsigned int          LB_BUFFER_EMPTY_MARGIN : 4;
		unsigned int            LB_BUFFER_EMPTY_STAT : 1;
		unsigned int                                 : 3;
		unsigned int        LB_BUFFER_EMPTY_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int             LB_BUFFER_EMPTY_ACK : 1;
		unsigned int                                 : 3;
		unsigned int             LB_BUFFER_FULL_STAT : 1;
		unsigned int                                 : 3;
		unsigned int         LB_BUFFER_FULL_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int              LB_BUFFER_FULL_ACK : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_BUFFER_URGENCY_CTRL__VI {
	struct {
		unsigned int       LB_BUFFER_URGENCY_MARK_ON : 12;
		unsigned int                                 : 4;
		unsigned int      LB_BUFFER_URGENCY_MARK_OFF : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_BUFFER_URGENCY_STATUS__VI {
	struct {
		unsigned int         LB_BUFFER_URGENCY_LEVEL : 12;
		unsigned int                                 : 4;
		unsigned int          LB_BUFFER_URGENCY_STAT : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_DATA_FORMAT__VI {
	struct {
		unsigned int                     PIXEL_DEPTH : 2;
		unsigned int                PIXEL_EXPAN_MODE : 1;
		unsigned int                   INTERLEAVE_EN : 1;
		unsigned int               PIXEL_REDUCE_MODE : 1;
		unsigned int             DYNAMIC_PIXEL_DEPTH : 1;
		unsigned int                       DITHER_EN : 1;
		unsigned int           DOWNSCALE_PREFETCH_EN : 1;
		unsigned int                                 : 4;
		unsigned int                        PREFETCH : 1;
		unsigned int                                 : 11;
		unsigned int                    REQUEST_MODE : 1;
		unsigned int                                 : 6;
		unsigned int                        ALPHA_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_DEBUG__VI {
	struct {
		unsigned int                        LB_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_DEBUG2__VI {
	struct {
		unsigned int                       LB_DEBUG2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_DEBUG3__VI {
	struct {
		unsigned int                       LB_DEBUG3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_DESKTOP_HEIGHT__VI {
	struct {
		unsigned int                  DESKTOP_HEIGHT : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_INTERRUPT_MASK__VI {
	struct {
		unsigned int           VBLANK_INTERRUPT_MASK : 1;
		unsigned int                                 : 3;
		unsigned int            VLINE_INTERRUPT_MASK : 1;
		unsigned int                                 : 3;
		unsigned int           VLINE2_INTERRUPT_MASK : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_KEYER_COLOR_B_CB__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int             LB_KEYER_COLOR_B_CB : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_KEYER_COLOR_CTRL__VI {
	struct {
		unsigned int               LB_KEYER_COLOR_EN : 1;
		unsigned int                                 : 7;
		unsigned int           LB_KEYER_COLOR_REP_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_KEYER_COLOR_G_Y__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int              LB_KEYER_COLOR_G_Y : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_KEYER_COLOR_REP_B_CB__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int         LB_KEYER_COLOR_REP_B_CB : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_KEYER_COLOR_REP_G_Y__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int          LB_KEYER_COLOR_REP_G_Y : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_KEYER_COLOR_REP_R_CR__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int         LB_KEYER_COLOR_REP_R_CR : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_KEYER_COLOR_R_CR__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int             LB_KEYER_COLOR_R_CR : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_MEMORY_CTRL__VI {
	struct {
		unsigned int                  LB_MEMORY_SIZE : 12;
		unsigned int                                 : 4;
		unsigned int               LB_NUM_PARTITIONS : 4;
		unsigned int                LB_MEMORY_CONFIG : 2;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_MEMORY_SIZE_STATUS__VI {
	struct {
		unsigned int           LB_MEMORY_SIZE_STATUS : 12;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_NO_OUTSTANDING_REQ_STATUS__VI {
	struct {
		unsigned int      LB_NO_OUTSTANDING_REQ_STAT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_SNAPSHOT_V_COUNTER__VI {
	struct {
		unsigned int              SNAPSHOT_V_COUNTER : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_SNAPSHOT_V_COUNTER_CHROMA__VI {
	struct {
		unsigned int       SNAPSHOT_V_COUNTER_CHROMA : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_SYNC_RESET_SEL__VI {
	struct {
		unsigned int               LB_SYNC_RESET_SEL : 2;
		unsigned int                                 : 2;
		unsigned int              LB_SYNC_RESET_SEL2 : 1;
		unsigned int                                 : 3;
		unsigned int             LB_SYNC_RESET_DELAY : 8;
		unsigned int                                 : 6;
		unsigned int                LB_SYNC_DURATION : 2;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int              LB_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int             LB_TEST_DEBUG_INDEX : 8;
		unsigned int          LB_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_VBLANK_STATUS__VI {
	struct {
		unsigned int                 VBLANK_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int                      VBLANK_ACK : 1;
		unsigned int                                 : 7;
		unsigned int                     VBLANK_STAT : 1;
		unsigned int                                 : 3;
		unsigned int                VBLANK_INTERRUPT : 1;
		unsigned int           VBLANK_INTERRUPT_TYPE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_VLINE2_START_END__VI {
	struct {
		unsigned int                    VLINE2_START : 14;
		unsigned int                                 : 2;
		unsigned int                      VLINE2_END : 15;
		unsigned int                      VLINE2_INV : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_VLINE2_STATUS__VI {
	struct {
		unsigned int                 VLINE2_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int                      VLINE2_ACK : 1;
		unsigned int                                 : 7;
		unsigned int                     VLINE2_STAT : 1;
		unsigned int                                 : 3;
		unsigned int                VLINE2_INTERRUPT : 1;
		unsigned int           VLINE2_INTERRUPT_TYPE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_VLINE_START_END__VI {
	struct {
		unsigned int                     VLINE_START : 14;
		unsigned int                                 : 2;
		unsigned int                       VLINE_END : 15;
		unsigned int                       VLINE_INV : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_VLINE_STATUS__VI {
	struct {
		unsigned int                  VLINE_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int                       VLINE_ACK : 1;
		unsigned int                                 : 7;
		unsigned int                      VLINE_STAT : 1;
		unsigned int                                 : 3;
		unsigned int                 VLINE_INTERRUPT : 1;
		unsigned int            VLINE_INTERRUPT_TYPE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_V_COUNTER__VI {
	struct {
		unsigned int                       V_COUNTER : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LBV_V_COUNTER_CHROMA__VI {
	struct {
		unsigned int                V_COUNTER_CHROMA : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_BLACK_KEYER_B_CB__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int             LB_BLACK_KEYER_B_CB : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_BLACK_KEYER_G_Y__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int              LB_BLACK_KEYER_G_Y : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_BLACK_KEYER_R_CR__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int             LB_BLACK_KEYER_R_CR : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_BUFFER_LEVEL_STATUS__VI {
	struct {
		unsigned int                  REQ_FIFO_LEVEL : 6;
		unsigned int                                 : 4;
		unsigned int              REQ_FIFO_FULL_CNTL : 6;
		unsigned int               DATA_BUFFER_LEVEL : 12;
		unsigned int             DATA_FIFO_FULL_CNTL : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_BUFFER_STATUS__VI {
	struct {
		unsigned int          LB_BUFFER_EMPTY_MARGIN : 4;
		unsigned int            LB_BUFFER_EMPTY_STAT : 1;
		unsigned int                                 : 3;
		unsigned int        LB_BUFFER_EMPTY_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int             LB_BUFFER_EMPTY_ACK : 1;
		unsigned int                                 : 3;
		unsigned int             LB_BUFFER_FULL_STAT : 1;
		unsigned int                                 : 3;
		unsigned int         LB_BUFFER_FULL_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int              LB_BUFFER_FULL_ACK : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_BUFFER_URGENCY_CTRL__VI {
	struct {
		unsigned int       LB_BUFFER_URGENCY_MARK_ON : 12;
		unsigned int                                 : 4;
		unsigned int      LB_BUFFER_URGENCY_MARK_OFF : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_BUFFER_URGENCY_STATUS__VI {
	struct {
		unsigned int         LB_BUFFER_URGENCY_LEVEL : 12;
		unsigned int                                 : 4;
		unsigned int          LB_BUFFER_URGENCY_STAT : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_DATA_FORMAT__VI {
	struct {
		unsigned int                     PIXEL_DEPTH : 2;
		unsigned int                PIXEL_EXPAN_MODE : 1;
		unsigned int                   INTERLEAVE_EN : 1;
		unsigned int               PIXEL_REDUCE_MODE : 1;
		unsigned int             DYNAMIC_PIXEL_DEPTH : 1;
		unsigned int                                 : 6;
		unsigned int                        PREFETCH : 1;
		unsigned int                                 : 11;
		unsigned int                    REQUEST_MODE : 1;
		unsigned int                                 : 6;
		unsigned int                        ALPHA_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_DEBUG2__VI {
	struct {
		unsigned int                       LB_DEBUG2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_DEBUG3__VI {
	struct {
		unsigned int                       LB_DEBUG3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_DESKTOP_HEIGHT__VI {
	struct {
		unsigned int                  DESKTOP_HEIGHT : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_INTERRUPT_MASK__VI {
	struct {
		unsigned int           VBLANK_INTERRUPT_MASK : 1;
		unsigned int                                 : 3;
		unsigned int            VLINE_INTERRUPT_MASK : 1;
		unsigned int                                 : 3;
		unsigned int           VLINE2_INTERRUPT_MASK : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_KEYER_COLOR_B_CB__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int             LB_KEYER_COLOR_B_CB : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_KEYER_COLOR_CTRL__VI {
	struct {
		unsigned int               LB_KEYER_COLOR_EN : 1;
		unsigned int                                 : 7;
		unsigned int           LB_KEYER_COLOR_REP_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_KEYER_COLOR_G_Y__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int              LB_KEYER_COLOR_G_Y : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_KEYER_COLOR_REP_B_CB__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int         LB_KEYER_COLOR_REP_B_CB : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_KEYER_COLOR_REP_G_Y__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int          LB_KEYER_COLOR_REP_G_Y : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_KEYER_COLOR_REP_R_CR__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int         LB_KEYER_COLOR_REP_R_CR : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_KEYER_COLOR_R_CR__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int             LB_KEYER_COLOR_R_CR : 12;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_MEMORY_CTRL__VI {
	struct {
		unsigned int                  LB_MEMORY_SIZE : 12;
		unsigned int                                 : 4;
		unsigned int               LB_NUM_PARTITIONS : 4;
		unsigned int                LB_MEMORY_CONFIG : 2;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_MEMORY_SIZE_STATUS__VI {
	struct {
		unsigned int           LB_MEMORY_SIZE_STATUS : 12;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_NO_OUTSTANDING_REQ_STATUS__VI {
	struct {
		unsigned int      LB_NO_OUTSTANDING_REQ_STAT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_SNAPSHOT_V_COUNTER__VI {
	struct {
		unsigned int              SNAPSHOT_V_COUNTER : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_VBLANK_STATUS__VI {
	struct {
		unsigned int                 VBLANK_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int                      VBLANK_ACK : 1;
		unsigned int                                 : 7;
		unsigned int                     VBLANK_STAT : 1;
		unsigned int                                 : 3;
		unsigned int                VBLANK_INTERRUPT : 1;
		unsigned int           VBLANK_INTERRUPT_TYPE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_VLINE2_START_END__VI {
	struct {
		unsigned int                    VLINE2_START : 14;
		unsigned int                                 : 2;
		unsigned int                      VLINE2_END : 15;
		unsigned int                      VLINE2_INV : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_VLINE2_STATUS__VI {
	struct {
		unsigned int                 VLINE2_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int                      VLINE2_ACK : 1;
		unsigned int                                 : 7;
		unsigned int                     VLINE2_STAT : 1;
		unsigned int                                 : 3;
		unsigned int                VLINE2_INTERRUPT : 1;
		unsigned int           VLINE2_INTERRUPT_TYPE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_VLINE_START_END__VI {
	struct {
		unsigned int                     VLINE_START : 14;
		unsigned int                                 : 2;
		unsigned int                       VLINE_END : 15;
		unsigned int                       VLINE_INV : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_VLINE_STATUS__VI {
	struct {
		unsigned int                  VLINE_OCCURRED : 1;
		unsigned int                                 : 3;
		unsigned int                       VLINE_ACK : 1;
		unsigned int                                 : 7;
		unsigned int                      VLINE_STAT : 1;
		unsigned int                                 : 3;
		unsigned int                 VLINE_INTERRUPT : 1;
		unsigned int            VLINE_INTERRUPT_TYPE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LB_V_COUNTER__VI {
	struct {
		unsigned int                       V_COUNTER : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC6_CNTL__VI {
	struct {
		unsigned int                      MC6_ENABLE : 1;
		unsigned int                   MC6_THRESHOLD : 16;
		unsigned int                    MC6_BLOCK_ID : 5;
		unsigned int                   MC6_SIGNAL_ID : 8;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC6_OVR_SEL__VI {
	struct {
		unsigned int                     MC6_OVR_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC6_OVR_VAL__VI {
	struct {
		unsigned int                     MC6_OVR_VAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC7_CNTL__VI {
	struct {
		unsigned int                      MC7_ENABLE : 1;
		unsigned int                   MC7_THRESHOLD : 16;
		unsigned int                    MC7_BLOCK_ID : 5;
		unsigned int                   MC7_SIGNAL_ID : 8;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC7_OVR_SEL__VI {
	struct {
		unsigned int                     MC7_OVR_SEL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LCAC_MC7_OVR_VAL__VI {
	struct {
		unsigned int                     MC7_OVR_VAL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_CONTROL__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                  LoopbackSelect : 4;
		unsigned int                PRBSPCIeLbSelect : 1;
		unsigned int                LoopbackHalfRate : 2;
		unsigned int                 LoopbackFifoPtr : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_LANEENABLE__VI {
	struct {
		unsigned int                     LANE_enable : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_PCIERXMUX0__VI {
	struct {
		unsigned int                         RXLANE0 : 8;
		unsigned int                         RXLANE1 : 8;
		unsigned int                         RXLANE2 : 8;
		unsigned int                         RXLANE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_PCIERXMUX1__VI {
	struct {
		unsigned int                         RXLANE4 : 8;
		unsigned int                         RXLANE5 : 8;
		unsigned int                         RXLANE6 : 8;
		unsigned int                         RXLANE7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_PCIERXMUX2__VI {
	struct {
		unsigned int                         RXLANE8 : 8;
		unsigned int                         RXLANE9 : 8;
		unsigned int                        RXLANE10 : 8;
		unsigned int                        RXLANE11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_PCIERXMUX3__VI {
	struct {
		unsigned int                        RXLANE12 : 8;
		unsigned int                        RXLANE13 : 8;
		unsigned int                        RXLANE14 : 8;
		unsigned int                        RXLANE15 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_PCIETXMUX0__VI {
	struct {
		unsigned int                         TXLANE0 : 8;
		unsigned int                         TXLANE1 : 8;
		unsigned int                         TXLANE2 : 8;
		unsigned int                         TXLANE3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_PCIETXMUX1__VI {
	struct {
		unsigned int                         TXLANE4 : 8;
		unsigned int                         TXLANE5 : 8;
		unsigned int                         TXLANE6 : 8;
		unsigned int                         TXLANE7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_PCIETXMUX2__VI {
	struct {
		unsigned int                         TXLANE8 : 8;
		unsigned int                         TXLANE9 : 8;
		unsigned int                        TXLANE10 : 8;
		unsigned int                        TXLANE11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_PCIETXMUX3__VI {
	struct {
		unsigned int                        TXLANE12 : 8;
		unsigned int                        TXLANE13 : 8;
		unsigned int                        TXLANE14 : 8;
		unsigned int                        TXLANE15 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_POWERCONTROL__VI {
	struct {
		unsigned int                     LMTxPhyCmd0 : 3;
		unsigned int                     LMRxPhyCmd0 : 3;
		unsigned int                    LMLinkSpeed0 : 2;
		unsigned int                     LMTxPhyCmd1 : 3;
		unsigned int                     LMRxPhyCmd1 : 3;
		unsigned int                    LMLinkSpeed1 : 2;
		unsigned int                     LMTxPhyCmd2 : 3;
		unsigned int                     LMRxPhyCmd2 : 3;
		unsigned int                    LMLinkSpeed2 : 2;
		unsigned int                     LMTxPhyCmd3 : 3;
		unsigned int                     LMRxPhyCmd3 : 3;
		unsigned int                    LMLinkSpeed3 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_POWERCONTROL1__VI {
	struct {
		unsigned int                         LMTxEn0 : 1;
		unsigned int                      LMTxClkEn0 : 1;
		unsigned int                     LMTxMargin0 : 3;
		unsigned int                      LMSkipBit0 : 1;
		unsigned int                   LMLaneUnused0 : 1;
		unsigned int                   LMTxMarginEn0 : 1;
		unsigned int                       LMDeemph0 : 1;
		unsigned int                         LMTxEn1 : 1;
		unsigned int                      LMTxClkEn1 : 1;
		unsigned int                     LMTxMargin1 : 3;
		unsigned int                      LMSkipBit1 : 1;
		unsigned int                   LMLaneUnused1 : 1;
		unsigned int                   LMTxMarginEn1 : 1;
		unsigned int                       LMDeemph1 : 1;
		unsigned int                         LMTxEn2 : 1;
		unsigned int                      LMTxClkEn2 : 1;
		unsigned int                     LMTxMargin2 : 3;
		unsigned int                      LMSkipBit2 : 1;
		unsigned int                   LMLaneUnused2 : 1;
		unsigned int                   LMTxMarginEn2 : 1;
		unsigned int                       LMDeemph2 : 1;
		unsigned int                      TxCoeffID0 : 2;
		unsigned int                      TxCoeffID1 : 2;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_POWERCONTROL2__VI {
	struct {
		unsigned int                         LMTxEn3 : 1;
		unsigned int                      LMTxClkEn3 : 1;
		unsigned int                     LMTxMargin3 : 3;
		unsigned int                      LMSkipBit3 : 1;
		unsigned int                   LMLaneUnused3 : 1;
		unsigned int                   LMTxMarginEn3 : 1;
		unsigned int                       LMDeemph3 : 1;
		unsigned int                      TxCoeffID2 : 2;
		unsigned int                      TxCoeffID3 : 2;
		unsigned int                        TxCoeff0 : 6;
		unsigned int                        TxCoeff1 : 6;
		unsigned int                        TxCoeff2 : 6;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_POWERCONTROL3__VI {
	struct {
		unsigned int                        TxCoeff3 : 6;
		unsigned int                        RxEqCtl0 : 6;
		unsigned int                        RxEqCtl1 : 6;
		unsigned int                        RxEqCtl2 : 6;
		unsigned int                        RxEqCtl3 : 6;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_POWERCONTROL4__VI {
	struct {
		unsigned int                        LinkNum0 : 3;
		unsigned int                        LinkNum1 : 3;
		unsigned int                        LinkNum2 : 3;
		unsigned int                        LinkNum3 : 3;
		unsigned int                        LaneNum0 : 4;
		unsigned int                        LaneNum1 : 4;
		unsigned int                        LaneNum2 : 4;
		unsigned int                        LaneNum3 : 4;
		unsigned int                        SpcMode0 : 1;
		unsigned int                        SpcMode1 : 1;
		unsigned int                        SpcMode2 : 1;
		unsigned int                        SpcMode3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LM_PRBSCONTROL__VI {
	struct {
		unsigned int                  PRBSPCIeSelect : 16;
		unsigned int                                 : 12;
		unsigned int                  LMLaneDegrade0 : 1;
		unsigned int                  LMLaneDegrade1 : 1;
		unsigned int                  LMLaneDegrade2 : 1;
		unsigned int                  LMLaneDegrade3 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LNCNT_QUAN_THRD__VI {
	struct {
		unsigned int           CFG_LNC_BW_QUAN_THRD0 : 3;
		unsigned int                                 : 1;
		unsigned int          CFG_LNC_CMN_QUAN_THRD4 : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LNCNT_WEIGHT__VI {
	struct {
		unsigned int              CFG_LNC_BW_WEIGHT0 : 16;
		unsigned int            CFG_LNC_CMN_WEIGHT16 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LNC_BW_WACC__VI {
	struct {
		unsigned int                     LNC_BW_WACC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LNC_CMN_WACC__VI {
	struct {
		unsigned int                    LNC_CMN_WACC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LNC_TOTAL_WACC__VI {
	struct {
		unsigned int                  LNC_TOTAL_WACC : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union LOW_POWER_TILING_CONTROL__VI {
	struct {
		unsigned int         LOW_POWER_TILING_ENABLE : 1;
		unsigned int                                 : 2;
		unsigned int           LOW_POWER_TILING_MODE : 2;
		unsigned int      LOW_POWER_TILING_NUM_PIPES : 3;
		unsigned int      LOW_POWER_TILING_NUM_BANKS : 3;
		unsigned int LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE : 1;
		unsigned int       LOW_POWER_TILING_ROW_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int  LOW_POWER_TILING_ROWS_PER_CHAN : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_CONTROL__VI {
	struct {
		unsigned int                   TRN_MSG_VALID : 1;
		unsigned int                     TRN_MSG_ACK : 1;
		unsigned int                   RCV_MSG_VALID : 1;
		unsigned int                     RCV_MSG_ACK : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_INDEX__VI {
	struct {
		unsigned int                   MAILBOX_INDEX : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_INT_CNTL__VI {
	struct {
		unsigned int                    VALID_INT_EN : 1;
		unsigned int                      ACK_INT_EN : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_MSGBUF_RCV_DW0__VI {
	struct {
		unsigned int                     MSGBUF_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_MSGBUF_RCV_DW1__VI {
	struct {
		unsigned int                     MSGBUF_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_MSGBUF_RCV_DW2__VI {
	struct {
		unsigned int                     MSGBUF_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_MSGBUF_RCV_DW3__VI {
	struct {
		unsigned int                     MSGBUF_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_MSGBUF_TRN_DW0__VI {
	struct {
		unsigned int                     MSGBUF_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_MSGBUF_TRN_DW1__VI {
	struct {
		unsigned int                     MSGBUF_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_MSGBUF_TRN_DW2__VI {
	struct {
		unsigned int                     MSGBUF_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MAILBOX_MSGBUF_TRN_DW3__VI {
	struct {
		unsigned int                     MSGBUF_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_1__VI {
	struct {
		unsigned int     entries_0_0_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_10__VI {
	struct {
		unsigned int     entries_0_3_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_11__VI {
	struct {
		unsigned int    entries_0_3_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_12__VI {
	struct {
		unsigned int           entries_0_3_padding_2 : 8;
		unsigned int           entries_0_3_padding_1 : 8;
		unsigned int           entries_0_3_padding_0 : 8;
		unsigned int      entries_0_3_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_13__VI {
	struct {
		unsigned int     entries_1_0_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_14__VI {
	struct {
		unsigned int    entries_1_0_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_15__VI {
	struct {
		unsigned int           entries_1_0_padding_2 : 8;
		unsigned int           entries_1_0_padding_1 : 8;
		unsigned int           entries_1_0_padding_0 : 8;
		unsigned int      entries_1_0_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_16__VI {
	struct {
		unsigned int     entries_1_1_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_17__VI {
	struct {
		unsigned int    entries_1_1_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_18__VI {
	struct {
		unsigned int           entries_1_1_padding_2 : 8;
		unsigned int           entries_1_1_padding_1 : 8;
		unsigned int           entries_1_1_padding_0 : 8;
		unsigned int      entries_1_1_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_19__VI {
	struct {
		unsigned int     entries_1_2_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_2__VI {
	struct {
		unsigned int    entries_0_0_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_20__VI {
	struct {
		unsigned int    entries_1_2_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_21__VI {
	struct {
		unsigned int           entries_1_2_padding_2 : 8;
		unsigned int           entries_1_2_padding_1 : 8;
		unsigned int           entries_1_2_padding_0 : 8;
		unsigned int      entries_1_2_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_22__VI {
	struct {
		unsigned int     entries_1_3_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_23__VI {
	struct {
		unsigned int    entries_1_3_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_24__VI {
	struct {
		unsigned int           entries_1_3_padding_2 : 8;
		unsigned int           entries_1_3_padding_1 : 8;
		unsigned int           entries_1_3_padding_0 : 8;
		unsigned int      entries_1_3_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_25__VI {
	struct {
		unsigned int     entries_2_0_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_26__VI {
	struct {
		unsigned int    entries_2_0_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_27__VI {
	struct {
		unsigned int           entries_2_0_padding_2 : 8;
		unsigned int           entries_2_0_padding_1 : 8;
		unsigned int           entries_2_0_padding_0 : 8;
		unsigned int      entries_2_0_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_28__VI {
	struct {
		unsigned int     entries_2_1_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_29__VI {
	struct {
		unsigned int    entries_2_1_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_3__VI {
	struct {
		unsigned int           entries_0_0_padding_2 : 8;
		unsigned int           entries_0_0_padding_1 : 8;
		unsigned int           entries_0_0_padding_0 : 8;
		unsigned int      entries_0_0_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_30__VI {
	struct {
		unsigned int           entries_2_1_padding_2 : 8;
		unsigned int           entries_2_1_padding_1 : 8;
		unsigned int           entries_2_1_padding_0 : 8;
		unsigned int      entries_2_1_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_31__VI {
	struct {
		unsigned int     entries_2_2_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_32__VI {
	struct {
		unsigned int    entries_2_2_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_33__VI {
	struct {
		unsigned int           entries_2_2_padding_2 : 8;
		unsigned int           entries_2_2_padding_1 : 8;
		unsigned int           entries_2_2_padding_0 : 8;
		unsigned int      entries_2_2_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_34__VI {
	struct {
		unsigned int     entries_2_3_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_35__VI {
	struct {
		unsigned int    entries_2_3_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_36__VI {
	struct {
		unsigned int           entries_2_3_padding_2 : 8;
		unsigned int           entries_2_3_padding_1 : 8;
		unsigned int           entries_2_3_padding_0 : 8;
		unsigned int      entries_2_3_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_37__VI {
	struct {
		unsigned int     entries_3_0_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_38__VI {
	struct {
		unsigned int    entries_3_0_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_39__VI {
	struct {
		unsigned int           entries_3_0_padding_2 : 8;
		unsigned int           entries_3_0_padding_1 : 8;
		unsigned int           entries_3_0_padding_0 : 8;
		unsigned int      entries_3_0_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_4__VI {
	struct {
		unsigned int     entries_0_1_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_40__VI {
	struct {
		unsigned int     entries_3_1_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_41__VI {
	struct {
		unsigned int    entries_3_1_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_42__VI {
	struct {
		unsigned int           entries_3_1_padding_2 : 8;
		unsigned int           entries_3_1_padding_1 : 8;
		unsigned int           entries_3_1_padding_0 : 8;
		unsigned int      entries_3_1_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_43__VI {
	struct {
		unsigned int     entries_3_2_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_44__VI {
	struct {
		unsigned int    entries_3_2_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_45__VI {
	struct {
		unsigned int           entries_3_2_padding_2 : 8;
		unsigned int           entries_3_2_padding_1 : 8;
		unsigned int           entries_3_2_padding_0 : 8;
		unsigned int      entries_3_2_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_46__VI {
	struct {
		unsigned int     entries_3_3_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_47__VI {
	struct {
		unsigned int    entries_3_3_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_48__VI {
	struct {
		unsigned int           entries_3_3_padding_2 : 8;
		unsigned int           entries_3_3_padding_1 : 8;
		unsigned int           entries_3_3_padding_0 : 8;
		unsigned int      entries_3_3_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_49__VI {
	struct {
		unsigned int     entries_4_0_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_5__VI {
	struct {
		unsigned int    entries_0_1_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_50__VI {
	struct {
		unsigned int    entries_4_0_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_51__VI {
	struct {
		unsigned int           entries_4_0_padding_2 : 8;
		unsigned int           entries_4_0_padding_1 : 8;
		unsigned int           entries_4_0_padding_0 : 8;
		unsigned int      entries_4_0_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_52__VI {
	struct {
		unsigned int     entries_4_1_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_53__VI {
	struct {
		unsigned int    entries_4_1_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_54__VI {
	struct {
		unsigned int           entries_4_1_padding_2 : 8;
		unsigned int           entries_4_1_padding_1 : 8;
		unsigned int           entries_4_1_padding_0 : 8;
		unsigned int      entries_4_1_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_55__VI {
	struct {
		unsigned int     entries_4_2_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_56__VI {
	struct {
		unsigned int    entries_4_2_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_57__VI {
	struct {
		unsigned int           entries_4_2_padding_2 : 8;
		unsigned int           entries_4_2_padding_1 : 8;
		unsigned int           entries_4_2_padding_0 : 8;
		unsigned int      entries_4_2_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_58__VI {
	struct {
		unsigned int     entries_4_3_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_59__VI {
	struct {
		unsigned int    entries_4_3_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_6__VI {
	struct {
		unsigned int           entries_0_1_padding_2 : 8;
		unsigned int           entries_0_1_padding_1 : 8;
		unsigned int           entries_0_1_padding_0 : 8;
		unsigned int      entries_0_1_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_60__VI {
	struct {
		unsigned int           entries_4_3_padding_2 : 8;
		unsigned int           entries_4_3_padding_1 : 8;
		unsigned int           entries_4_3_padding_0 : 8;
		unsigned int      entries_4_3_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_61__VI {
	struct {
		unsigned int     entries_5_0_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_62__VI {
	struct {
		unsigned int    entries_5_0_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_63__VI {
	struct {
		unsigned int           entries_5_0_padding_2 : 8;
		unsigned int           entries_5_0_padding_1 : 8;
		unsigned int           entries_5_0_padding_0 : 8;
		unsigned int      entries_5_0_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_64__VI {
	struct {
		unsigned int     entries_5_1_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_65__VI {
	struct {
		unsigned int    entries_5_1_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_66__VI {
	struct {
		unsigned int           entries_5_1_padding_2 : 8;
		unsigned int           entries_5_1_padding_1 : 8;
		unsigned int           entries_5_1_padding_0 : 8;
		unsigned int      entries_5_1_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_67__VI {
	struct {
		unsigned int     entries_5_2_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_68__VI {
	struct {
		unsigned int    entries_5_2_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_69__VI {
	struct {
		unsigned int           entries_5_2_padding_2 : 8;
		unsigned int           entries_5_2_padding_1 : 8;
		unsigned int           entries_5_2_padding_0 : 8;
		unsigned int      entries_5_2_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_7__VI {
	struct {
		unsigned int     entries_0_2_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_70__VI {
	struct {
		unsigned int     entries_5_3_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_71__VI {
	struct {
		unsigned int    entries_5_3_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_72__VI {
	struct {
		unsigned int           entries_5_3_padding_2 : 8;
		unsigned int           entries_5_3_padding_1 : 8;
		unsigned int           entries_5_3_padding_0 : 8;
		unsigned int      entries_5_3_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_73__VI {
	struct {
		unsigned int     entries_6_0_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_74__VI {
	struct {
		unsigned int    entries_6_0_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_75__VI {
	struct {
		unsigned int           entries_6_0_padding_2 : 8;
		unsigned int           entries_6_0_padding_1 : 8;
		unsigned int           entries_6_0_padding_0 : 8;
		unsigned int      entries_6_0_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_76__VI {
	struct {
		unsigned int     entries_6_1_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_77__VI {
	struct {
		unsigned int    entries_6_1_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_78__VI {
	struct {
		unsigned int           entries_6_1_padding_2 : 8;
		unsigned int           entries_6_1_padding_1 : 8;
		unsigned int           entries_6_1_padding_0 : 8;
		unsigned int      entries_6_1_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_79__VI {
	struct {
		unsigned int     entries_6_2_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_8__VI {
	struct {
		unsigned int    entries_0_2_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_80__VI {
	struct {
		unsigned int    entries_6_2_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_81__VI {
	struct {
		unsigned int           entries_6_2_padding_2 : 8;
		unsigned int           entries_6_2_padding_1 : 8;
		unsigned int           entries_6_2_padding_0 : 8;
		unsigned int      entries_6_2_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_82__VI {
	struct {
		unsigned int     entries_6_3_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_83__VI {
	struct {
		unsigned int    entries_6_3_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_84__VI {
	struct {
		unsigned int           entries_6_3_padding_2 : 8;
		unsigned int           entries_6_3_padding_1 : 8;
		unsigned int           entries_6_3_padding_0 : 8;
		unsigned int      entries_6_3_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_85__VI {
	struct {
		unsigned int     entries_7_0_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_86__VI {
	struct {
		unsigned int    entries_7_0_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_87__VI {
	struct {
		unsigned int           entries_7_0_padding_2 : 8;
		unsigned int           entries_7_0_padding_1 : 8;
		unsigned int           entries_7_0_padding_0 : 8;
		unsigned int      entries_7_0_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_88__VI {
	struct {
		unsigned int     entries_7_1_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_89__VI {
	struct {
		unsigned int    entries_7_1_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_9__VI {
	struct {
		unsigned int           entries_0_2_padding_2 : 8;
		unsigned int           entries_0_2_padding_1 : 8;
		unsigned int           entries_0_2_padding_0 : 8;
		unsigned int      entries_0_2_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_90__VI {
	struct {
		unsigned int           entries_7_1_padding_2 : 8;
		unsigned int           entries_7_1_padding_1 : 8;
		unsigned int           entries_7_1_padding_0 : 8;
		unsigned int      entries_7_1_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_91__VI {
	struct {
		unsigned int     entries_7_2_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_92__VI {
	struct {
		unsigned int    entries_7_2_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_93__VI {
	struct {
		unsigned int           entries_7_2_padding_2 : 8;
		unsigned int           entries_7_2_padding_1 : 8;
		unsigned int           entries_7_2_padding_0 : 8;
		unsigned int      entries_7_2_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_94__VI {
	struct {
		unsigned int     entries_7_3_McArbDramTiming : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_95__VI {
	struct {
		unsigned int    entries_7_3_McArbDramTiming2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCARB_DRAM_TIMING_TABLE_96__VI {
	struct {
		unsigned int           entries_7_3_padding_2 : 8;
		unsigned int           entries_7_3_padding_1 : 8;
		unsigned int           entries_7_3_padding_0 : 8;
		unsigned int      entries_7_3_McArbBurstTime : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_MEM_CONTROL__VI {
	struct {
		unsigned int          MCIFMEM_CACHE_MODE_DIS : 1;
		unsigned int                                 : 3;
		unsigned int              MCIFMEM_CACHE_MODE : 2;
		unsigned int                                 : 2;
		unsigned int              MCIFMEM_CACHE_SIZE : 8;
		unsigned int              MCIFMEM_CACHE_PIPE : 3;
		unsigned int              MCIFMEM_CACHE_TYPE : 2;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_VMID__VI {
	struct {
		unsigned int                    MCIF_WR_VMID : 4;
		unsigned int                     VIP_WR_VMID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_ARBITRATION_CONTROL__VI {
	struct {
		unsigned int MCIF_WB_CLIENT_ARBITRATION_SLICE : 2;
		unsigned int                                 : 24;
		unsigned int          MCIF_WB_TIME_PER_PIXEL : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUFMGR_CUR_LINE_R__VI {
	struct {
		unsigned int       MCIF_WB_BUFMGR_CUR_LINE_R : 13;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUFMGR_STATUS__VI {
	struct {
		unsigned int   MCIF_WB_BUFMGR_VCE_INT_STATUS : 1;
		unsigned int    MCIF_WB_BUFMGR_SW_INT_STATUS : 1;
		unsigned int                                 : 2;
		unsigned int          MCIF_WB_BUFMGR_CUR_BUF : 3;
		unsigned int     MCIF_WB_BUF_DUALSIZE_STATUS : 1;
		unsigned int           MCIF_WB_BUFMGR_BUFTAG : 4;
		unsigned int       MCIF_WB_BUFMGR_CUR_LINE_L : 13;
		unsigned int                                 : 3;
		unsigned int         MCIF_WB_BUFMGR_NEXT_BUF : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUFMGR_SW_CONTROL__VI {
	struct {
		unsigned int           MCIF_WB_BUFMGR_ENABLE : 1;
		unsigned int        MCIF_WB_BUF_DUALSIZE_REQ : 1;
		unsigned int                                 : 2;
		unsigned int        MCIF_WB_BUFMGR_SW_INT_EN : 1;
		unsigned int       MCIF_WB_BUFMGR_SW_INT_ACK : 1;
		unsigned int  MCIF_WB_BUFMGR_SW_SLICE_INT_EN : 1;
		unsigned int                                 : 1;
		unsigned int          MCIF_WB_BUFMGR_SW_LOCK : 4;
		unsigned int                                 : 4;
		unsigned int                  MCIF_WB_P_VMID : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUFMGR_VCE_CONTROL__VI {
	struct {
		unsigned int  MCIF_WB_BUFMGR_VCE_LOCK_IGNORE : 1;
		unsigned int                                 : 3;
		unsigned int       MCIF_WB_BUFMGR_VCE_INT_EN : 1;
		unsigned int      MCIF_WB_BUFMGR_VCE_INT_ACK : 1;
		unsigned int MCIF_WB_BUFMGR_VCE_SLICE_INT_EN : 1;
		unsigned int                                 : 1;
		unsigned int         MCIF_WB_BUFMGR_VCE_LOCK : 4;
		unsigned int                                 : 4;
		unsigned int       MCIF_WB_BUFMGR_SLICE_SIZE : 13;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_1_ADDR_C__VI {
	struct {
		unsigned int            MCIF_WB_BUF_1_ADDR_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_1_ADDR_C_OFFSET__VI {
	struct {
		unsigned int     MCIF_WB_BUF_1_ADDR_C_OFFSET : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_1_ADDR_Y__VI {
	struct {
		unsigned int            MCIF_WB_BUF_1_ADDR_Y : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_1_ADDR_Y_OFFSET__VI {
	struct {
		unsigned int     MCIF_WB_BUF_1_ADDR_Y_OFFSET : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_1_STATUS__VI {
	struct {
		unsigned int            MCIF_WB_BUF_1_ACTIVE : 1;
		unsigned int         MCIF_WB_BUF_1_SW_LOCKED : 1;
		unsigned int        MCIF_WB_BUF_1_VCE_LOCKED : 1;
		unsigned int          MCIF_WB_BUF_1_OVERFLOW : 1;
		unsigned int           MCIF_WB_BUF_1_DISABLE : 1;
		unsigned int              MCIF_WB_BUF_1_MODE : 3;
		unsigned int            MCIF_WB_BUF_1_BUFTAG : 4;
		unsigned int           MCIF_WB_BUF_1_NXT_BUF : 3;
		unsigned int             MCIF_WB_BUF_1_FIELD : 1;
		unsigned int        MCIF_WB_BUF_1_CUR_LINE_L : 13;
		unsigned int   MCIF_WB_BUF_1_LONG_LINE_ERROR : 1;
		unsigned int  MCIF_WB_BUF_1_SHORT_LINE_ERROR : 1;
		unsigned int MCIF_WB_BUF_1_FRAME_LENGTH_ERROR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_1_STATUS2__VI {
	struct {
		unsigned int        MCIF_WB_BUF_1_CUR_LINE_R : 13;
		unsigned int       MCIF_WB_BUF_1_NEW_CONTENT : 1;
		unsigned int       MCIF_WB_BUF_1_COLOR_DEPTH : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_2_ADDR_C__VI {
	struct {
		unsigned int            MCIF_WB_BUF_2_ADDR_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_2_ADDR_C_OFFSET__VI {
	struct {
		unsigned int     MCIF_WB_BUF_2_ADDR_C_OFFSET : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_2_ADDR_Y__VI {
	struct {
		unsigned int            MCIF_WB_BUF_2_ADDR_Y : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_2_ADDR_Y_OFFSET__VI {
	struct {
		unsigned int     MCIF_WB_BUF_2_ADDR_Y_OFFSET : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_2_STATUS__VI {
	struct {
		unsigned int            MCIF_WB_BUF_2_ACTIVE : 1;
		unsigned int         MCIF_WB_BUF_2_SW_LOCKED : 1;
		unsigned int        MCIF_WB_BUF_2_VCE_LOCKED : 1;
		unsigned int          MCIF_WB_BUF_2_OVERFLOW : 1;
		unsigned int           MCIF_WB_BUF_2_DISABLE : 1;
		unsigned int              MCIF_WB_BUF_2_MODE : 3;
		unsigned int            MCIF_WB_BUF_2_BUFTAG : 4;
		unsigned int           MCIF_WB_BUF_2_NXT_BUF : 3;
		unsigned int             MCIF_WB_BUF_2_FIELD : 1;
		unsigned int        MCIF_WB_BUF_2_CUR_LINE_L : 13;
		unsigned int   MCIF_WB_BUF_2_LONG_LINE_ERROR : 1;
		unsigned int  MCIF_WB_BUF_2_SHORT_LINE_ERROR : 1;
		unsigned int MCIF_WB_BUF_2_FRAME_LENGTH_ERROR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_2_STATUS2__VI {
	struct {
		unsigned int        MCIF_WB_BUF_2_CUR_LINE_R : 13;
		unsigned int       MCIF_WB_BUF_2_NEW_CONTENT : 1;
		unsigned int       MCIF_WB_BUF_2_COLOR_DEPTH : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_3_ADDR_C__VI {
	struct {
		unsigned int            MCIF_WB_BUF_3_ADDR_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_3_ADDR_C_OFFSET__VI {
	struct {
		unsigned int     MCIF_WB_BUF_3_ADDR_C_OFFSET : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_3_ADDR_Y__VI {
	struct {
		unsigned int            MCIF_WB_BUF_3_ADDR_Y : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_3_ADDR_Y_OFFSET__VI {
	struct {
		unsigned int     MCIF_WB_BUF_3_ADDR_Y_OFFSET : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_3_STATUS__VI {
	struct {
		unsigned int            MCIF_WB_BUF_3_ACTIVE : 1;
		unsigned int         MCIF_WB_BUF_3_SW_LOCKED : 1;
		unsigned int        MCIF_WB_BUF_3_VCE_LOCKED : 1;
		unsigned int          MCIF_WB_BUF_3_OVERFLOW : 1;
		unsigned int           MCIF_WB_BUF_3_DISABLE : 1;
		unsigned int              MCIF_WB_BUF_3_MODE : 3;
		unsigned int            MCIF_WB_BUF_3_BUFTAG : 4;
		unsigned int           MCIF_WB_BUF_3_NXT_BUF : 3;
		unsigned int             MCIF_WB_BUF_3_FIELD : 1;
		unsigned int        MCIF_WB_BUF_3_CUR_LINE_L : 13;
		unsigned int   MCIF_WB_BUF_3_LONG_LINE_ERROR : 1;
		unsigned int  MCIF_WB_BUF_3_SHORT_LINE_ERROR : 1;
		unsigned int MCIF_WB_BUF_3_FRAME_LENGTH_ERROR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_3_STATUS2__VI {
	struct {
		unsigned int        MCIF_WB_BUF_3_CUR_LINE_R : 13;
		unsigned int       MCIF_WB_BUF_3_NEW_CONTENT : 1;
		unsigned int       MCIF_WB_BUF_3_COLOR_DEPTH : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_4_ADDR_C__VI {
	struct {
		unsigned int            MCIF_WB_BUF_4_ADDR_C : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_4_ADDR_C_OFFSET__VI {
	struct {
		unsigned int     MCIF_WB_BUF_4_ADDR_C_OFFSET : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_4_ADDR_Y__VI {
	struct {
		unsigned int            MCIF_WB_BUF_4_ADDR_Y : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_4_ADDR_Y_OFFSET__VI {
	struct {
		unsigned int     MCIF_WB_BUF_4_ADDR_Y_OFFSET : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_4_STATUS__VI {
	struct {
		unsigned int            MCIF_WB_BUF_4_ACTIVE : 1;
		unsigned int         MCIF_WB_BUF_4_SW_LOCKED : 1;
		unsigned int        MCIF_WB_BUF_4_VCE_LOCKED : 1;
		unsigned int          MCIF_WB_BUF_4_OVERFLOW : 1;
		unsigned int           MCIF_WB_BUF_4_DISABLE : 1;
		unsigned int              MCIF_WB_BUF_4_MODE : 3;
		unsigned int            MCIF_WB_BUF_4_BUFTAG : 4;
		unsigned int           MCIF_WB_BUF_4_NXT_BUF : 3;
		unsigned int             MCIF_WB_BUF_4_FIELD : 1;
		unsigned int        MCIF_WB_BUF_4_CUR_LINE_L : 13;
		unsigned int   MCIF_WB_BUF_4_LONG_LINE_ERROR : 1;
		unsigned int  MCIF_WB_BUF_4_SHORT_LINE_ERROR : 1;
		unsigned int MCIF_WB_BUF_4_FRAME_LENGTH_ERROR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_4_STATUS2__VI {
	struct {
		unsigned int        MCIF_WB_BUF_4_CUR_LINE_R : 13;
		unsigned int       MCIF_WB_BUF_4_NEW_CONTENT : 1;
		unsigned int       MCIF_WB_BUF_4_COLOR_DEPTH : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_BUF_PITCH__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int          MCIF_WB_BUF_LUMA_PITCH : 8;
		unsigned int                                 : 8;
		unsigned int        MCIF_WB_BUF_CHROMA_PITCH : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_HVVMID_CONTROL__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int            MCIF_WB_DEFAULT_VMID : 4;
		unsigned int                                 : 4;
		unsigned int       MCIF_WB_ALLOWED_VMID_MASK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int         MCIF_WB_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int        MCIF_WB_TEST_DEBUG_INDEX : 8;
		unsigned int     MCIF_WB_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MCIF_WB_URGENCY_WATERMARK__VI {
	struct {
		unsigned int MCIF_WB_CLIENT0_URGENCY_WATERMARK : 16;
		unsigned int MCIF_WB_CLIENT1_URGENCY_WATERMARK : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_ATOMIC__VI {
	struct {
                unsigned int                          TC_GRP : 3;
                unsigned int                       TC_GRP_EN : 1;
                unsigned int                        SDMA_GRP : 3;
                unsigned int                     SDMA_GRP_EN : 1;
                unsigned int                     OUTSTANDING : 8;
                unsigned int                  ATOMIC_RTN_GRP : 8;
                unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GRUB__VI {
	struct {
		unsigned int                  GRUB_WATERMARK : 8;
		unsigned int              GRUB_WATERMARK_PRI : 8;
		unsigned int              GRUB_WATERMARK_MED : 8;
		unsigned int                       REG_WR_EN : 2;
		unsigned int                      REG_RD_SEL : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GRUB2__VI {
	struct {
                unsigned int                 REALTIME_GRP_RD : 8;
                unsigned int                 REALTIME_GRP_WR : 8;
                unsigned int                DISP_RD_STALL_EN : 1;
                unsigned int                 ACP_RD_STALL_EN : 1;
                unsigned int                 UVD_RD_STALL_EN : 1;
                unsigned int                VCE0_RD_STALL_EN : 1;
                unsigned int                VCE1_RD_STALL_EN : 1;
                unsigned int                 REALTIME_RD_WTS : 1;
                unsigned int                 REALTIME_WR_WTS : 1;
                unsigned int            URGENT_BY_DISP_STALL : 1;
                unsigned int             PROMOTE_BY_DMIF_URG : 1;
                unsigned int PRIORITY_URGENT_OUTSTANDING_ONLY_RD : 1;
                unsigned int PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD : 1;
                unsigned int PRIORITY_URGENT_OUTSTANDING_ONLY_WR : 1;
                unsigned int PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR : 1;
                unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GRUB_PRIORITY1_RD__VI {
	struct {
		unsigned int                             CB0 : 2;
		unsigned int                        CBCMASK0 : 2;
		unsigned int                        CBFMASK0 : 2;
		unsigned int                             DB0 : 2;
		unsigned int                        DBHTILE0 : 2;
		unsigned int                         DBSTEN0 : 2;
		unsigned int                             TC0 : 2;
		unsigned int                            ACPG : 2;
		unsigned int                            ACPO : 2;
		unsigned int                            DMIF : 2;
		unsigned int                       DMIF_EXT0 : 2;
		unsigned int                       DMIF_EXT1 : 2;
		unsigned int                         DMIF_TW : 2;
		unsigned int                            MCIF : 2;
		unsigned int                             RLC : 2;
		unsigned int                             VMC : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GRUB_PRIORITY1_WR__VI {
	struct {
		unsigned int                             CB0 : 2;
		unsigned int                        CBCMASK0 : 2;
		unsigned int                        CBFMASK0 : 2;
		unsigned int                        CBIMMED0 : 2;
		unsigned int                             DB0 : 2;
		unsigned int                        DBHTILE0 : 2;
		unsigned int                         DBSTEN0 : 2;
		unsigned int                             TC0 : 2;
		unsigned int                              SH : 2;
		unsigned int                            ACPG : 2;
		unsigned int                            ACPO : 2;
		unsigned int                            MCIF : 2;
		unsigned int                             RLC : 2;
		unsigned int                           SDMA1 : 2;
		unsigned int                             SMU : 2;
		unsigned int                             VCE : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GRUB_PRIORITY2_RD__VI {
	struct {
		unsigned int                           SDMA1 : 2;
		unsigned int                             SMU : 2;
		unsigned int                             VCE : 2;
		unsigned int                                 : 2;
		unsigned int                           XDMAM : 2;
		unsigned int                           SDMA0 : 2;
		unsigned int                             HDP : 2;
		unsigned int                             UMC : 2;
		unsigned int                             UVD : 2;
		unsigned int                        UVD_EXT0 : 2;
		unsigned int                        UVD_EXT1 : 2;
		unsigned int                             SEM : 2;
		unsigned int                          SAMMSP : 2;
		unsigned int                             VP8 : 2;
		unsigned int                             ISP : 2;
		unsigned int                            RSV2 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GRUB_PRIORITY2_WR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                          SAMMSP : 2;
		unsigned int                            XDMA : 2;
		unsigned int                           XDMAM : 2;
		unsigned int                           SDMA0 : 2;
		unsigned int                             HDP : 2;
		unsigned int                             UMC : 2;
		unsigned int                             UVD : 2;
		unsigned int                        UVD_EXT0 : 2;
		unsigned int                        UVD_EXT1 : 2;
		unsigned int                             XDP : 2;
		unsigned int                             SEM : 2;
		unsigned int                              IH : 2;
		unsigned int                             VP8 : 2;
		unsigned int                             ISP : 2;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GRUB_PROMOTE__VI {
	struct {
		unsigned int                       URGENT_RD : 8;
		unsigned int                       URGENT_WR : 8;
		unsigned int                      PROMOTE_RD : 8;
		unsigned int                      PROMOTE_WR : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GRUB_REALTIME_RD__VI {
	struct {
		unsigned int                             CB0 : 1;
		unsigned int                        CBCMASK0 : 1;
		unsigned int                        CBFMASK0 : 1;
		unsigned int                             DB0 : 1;
		unsigned int                        DBHTILE0 : 1;
		unsigned int                         DBSTEN0 : 1;
		unsigned int                             TC0 : 1;
		unsigned int                              IA : 1;
		unsigned int                            ACPG : 1;
		unsigned int                            ACPO : 1;
		unsigned int                            DMIF : 1;
		unsigned int                       DMIF_EXT0 : 1;
		unsigned int                       DMIF_EXT1 : 1;
		unsigned int                         DMIF_TW : 1;
		unsigned int                            MCIF : 1;
		unsigned int                             RLC : 1;
		unsigned int                             VMC : 1;
		unsigned int                           SDMA1 : 1;
		unsigned int                             SMU : 1;
		unsigned int                             VCE : 1;
		unsigned int                                 : 1;
		unsigned int                           XDMAM : 1;
		unsigned int                           SDMA0 : 1;
		unsigned int                             HDP : 1;
		unsigned int                             UMC : 1;
		unsigned int                             UVD : 1;
		unsigned int                        UVD_EXT0 : 1;
		unsigned int                        UVD_EXT1 : 1;
		unsigned int                             SEM : 1;
		unsigned int                          SAMMSP : 1;
		unsigned int                             VP8 : 1;
		unsigned int                             ISP : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_GRUB_REALTIME_WR__VI {
	struct {
		unsigned int                             CB0 : 1;
		unsigned int                        CBCMASK0 : 1;
		unsigned int                        CBFMASK0 : 1;
		unsigned int                        CBIMMED0 : 1;
		unsigned int                             DB0 : 1;
		unsigned int                        DBHTILE0 : 1;
		unsigned int                         DBSTEN0 : 1;
		unsigned int                             TC0 : 1;
		unsigned int                              SH : 1;
		unsigned int                            ACPG : 1;
		unsigned int                            ACPO : 1;
		unsigned int                            MCIF : 1;
		unsigned int                             RLC : 1;
		unsigned int                           SDMA1 : 1;
		unsigned int                             SMU : 1;
		unsigned int                             VCE : 1;
		unsigned int                                 : 1;
		unsigned int                          SAMMSP : 1;
		unsigned int                            XDMA : 1;
		unsigned int                           XDMAM : 1;
		unsigned int                           SDMA0 : 1;
		unsigned int                             HDP : 1;
		unsigned int                             UMC : 1;
		unsigned int                             UVD : 1;
		unsigned int                        UVD_EXT0 : 1;
		unsigned int                        UVD_EXT1 : 1;
		unsigned int                             XDP : 1;
		unsigned int                             SEM : 1;
		unsigned int                              IH : 1;
		unsigned int                             VP8 : 1;
		unsigned int                             ISP : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_PERF_CID__VI {
	struct {
		unsigned int                             CH0 : 8;
		unsigned int                             CH1 : 8;
		unsigned int                          CH0_EN : 1;
		unsigned int                          CH1_EN : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_ARB_SNOOP__VI {
	struct {
		unsigned int                       TC_GRP_RD : 3;
		unsigned int                    TC_GRP_RD_EN : 1;
		unsigned int                       TC_GRP_WR : 3;
		unsigned int                    TC_GRP_WR_EN : 1;
		unsigned int                     SDMA_GRP_RD : 3;
		unsigned int                  SDMA_GRP_RD_EN : 1;
		unsigned int                     SDMA_GRP_WR : 3;
		unsigned int                  SDMA_GRP_WR_EN : 1;
		unsigned int                  OUTSTANDING_RD : 8;
		unsigned int                  OUTSTANDING_WR : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_CMD__VI {
	struct {
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_BIST_DAT__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 12;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_CITF_CREDITS_ARB_RD2__VI {
	struct {
		unsigned int                        READ_MED : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_ARB_GARLIC_CNTL__VI {
	struct {
		unsigned int   RX_RDRESP_FIFO_PTR_INIT_VALUE : 8;
		unsigned int   RX_WRRESP_FIFO_PTR_INIT_VALUE : 7;
		unsigned int                EN_64_BYTE_WRITE : 1;
		unsigned int             EDC_RESPONSE_ENABLE : 1;
		unsigned int        OUTSTANDING_RDRESP_LIMIT : 9;
		unsigned int        OUTSTANDING_WRRESP_LIMIT : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_ARB_GARLIC_ISOC_PRI__VI {
	struct {
		unsigned int               DMIF_RD_TOKURG_EN : 1;
		unsigned int                UVD_RD_TOKURG_EN : 1;
		unsigned int                VCE_RD_TOKURG_EN : 1;
		unsigned int                ACP_RD_TOKURG_EN : 1;
		unsigned int               DMIF_RD_PRIURG_EN : 1;
		unsigned int                UVD_RD_PRIURG_EN : 1;
		unsigned int                VCE_RD_PRIURG_EN : 1;
		unsigned int                ACP_RD_PRIURG_EN : 1;
		unsigned int                 DMIF_RD_ISOC_EN : 1;
		unsigned int                  UVD_RD_ISOC_EN : 1;
		unsigned int                  VCE_RD_ISOC_EN : 1;
		unsigned int                 MCIF_RD_ISOC_EN : 1;
		unsigned int                  UMC_RD_ISOC_EN : 1;
		unsigned int                 VCEU_RD_ISOC_EN : 1;
		unsigned int                  ACP_RD_ISOC_EN : 1;
		unsigned int              REQPRI_OVERRIDE_EN : 1;
		unsigned int             REQPRI_OVERRIDE_VAL : 2;
		unsigned int            PRIPRMTE_OVERRIDE_EN : 1;
		unsigned int              TOKURG_OVERRIDE_EN : 1;
		unsigned int              PRIURG_OVERRIDE_EN : 1;
		unsigned int           PRIPRMTE_OVERRIDE_VAL : 1;
		unsigned int             TOKURG_OVERRIDE_VAL : 1;
		unsigned int             PRIURG_OVERRIDE_VAL : 1;
		unsigned int              GARLIC_REQ_CREDITS : 5;
		unsigned int                     MM_REL_LATE : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_ARB_GARLIC_WR_PRI__VI {
	struct {
		unsigned int                       CB_WR_PRI : 2;
		unsigned int                       DB_WR_PRI : 2;
		unsigned int                       TC_WR_PRI : 2;
		unsigned int                       CP_WR_PRI : 2;
		unsigned int                      HDP_WR_PRI : 2;
		unsigned int                      XDP_WR_PRI : 2;
		unsigned int                      UMC_WR_PRI : 2;
		unsigned int                      UVD_WR_PRI : 2;
		unsigned int                      RLC_WR_PRI : 2;
		unsigned int                       IH_WR_PRI : 2;
		unsigned int                     SDMA_WR_PRI : 2;
		unsigned int                      SEM_WR_PRI : 2;
		unsigned int                       SH_WR_PRI : 2;
		unsigned int                     MCIF_WR_PRI : 2;
		unsigned int                      VCE_WR_PRI : 2;
		unsigned int                     VCEU_WR_PRI : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_ARB_GARLIC_WR_PRI2__VI {
	struct {
		unsigned int                      SMU_WR_PRI : 2;
		unsigned int                      SAM_WR_PRI : 2;
		unsigned int                      ACP_WR_PRI : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM0_BANK_ADDR_MAPPING__VI {
	struct {
		unsigned int                    DIMM0ADDRMAP : 4;
		unsigned int                    DIMM1ADDRMAP : 4;
		unsigned int                 BANKSWIZZLEMODE : 1;
		unsigned int                        BANKSWAP : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM0_CS0_BASE__VI {
	struct {
		unsigned int                        CSENABLE : 1;
		unsigned int                                 : 4;
		unsigned int                   BASEADDR21_11 : 11;
		unsigned int                                 : 3;
		unsigned int                   BASEADDR38_27 : 12;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM0_CS1_BASE__VI {
	struct {
		unsigned int                        CSENABLE : 1;
		unsigned int                                 : 4;
		unsigned int                   BASEADDR21_11 : 11;
		unsigned int                                 : 3;
		unsigned int                   BASEADDR38_27 : 12;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM0_CS2_BASE__VI {
	struct {
		unsigned int                        CSENABLE : 1;
		unsigned int                                 : 4;
		unsigned int                   BASEADDR21_11 : 11;
		unsigned int                                 : 3;
		unsigned int                   BASEADDR38_27 : 12;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM0_CS3_BASE__VI {
	struct {
		unsigned int                        CSENABLE : 1;
		unsigned int                                 : 4;
		unsigned int                   BASEADDR21_11 : 11;
		unsigned int                                 : 3;
		unsigned int                   BASEADDR38_27 : 12;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM0_CTL_BASE__VI {
	struct {
		unsigned int                          DCTSEL : 3;
		unsigned int                      DCTINTLVEN : 4;
		unsigned int                     DCTBASEADDR : 21;
		unsigned int                     DCTOFFSETEN : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM0_CTL_LIMIT__VI {
	struct {
		unsigned int                    DCTLIMITADDR : 21;
		unsigned int                   DRAMHOLEVALID : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM1_BANK_ADDR_MAPPING__VI {
	struct {
		unsigned int                    DIMM0ADDRMAP : 4;
		unsigned int                    DIMM1ADDRMAP : 4;
		unsigned int                 BANKSWIZZLEMODE : 1;
		unsigned int                        BANKSWAP : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM1_CS0_BASE__VI {
	struct {
		unsigned int                        CSENABLE : 1;
		unsigned int                                 : 4;
		unsigned int                   BASEADDR21_11 : 11;
		unsigned int                                 : 3;
		unsigned int                   BASEADDR38_27 : 12;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM1_CS1_BASE__VI {
	struct {
		unsigned int                        CSENABLE : 1;
		unsigned int                                 : 4;
		unsigned int                   BASEADDR21_11 : 11;
		unsigned int                                 : 3;
		unsigned int                   BASEADDR38_27 : 12;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM1_CS2_BASE__VI {
	struct {
		unsigned int                        CSENABLE : 1;
		unsigned int                                 : 4;
		unsigned int                   BASEADDR21_11 : 11;
		unsigned int                                 : 3;
		unsigned int                   BASEADDR38_27 : 12;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM1_CS3_BASE__VI {
	struct {
		unsigned int                        CSENABLE : 1;
		unsigned int                                 : 4;
		unsigned int                   BASEADDR21_11 : 11;
		unsigned int                                 : 3;
		unsigned int                   BASEADDR38_27 : 12;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM1_CTL_BASE__VI {
	struct {
		unsigned int                          DCTSEL : 3;
		unsigned int                      DCTINTLVEN : 4;
		unsigned int                     DCTBASEADDR : 21;
		unsigned int                     DCTOFFSETEN : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM1_CTL_LIMIT__VI {
	struct {
		unsigned int                    DCTLIMITADDR : 21;
		unsigned int                   DRAMHOLEVALID : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM_APER_BASE__VI {
	struct {
		unsigned int                            BASE : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM_APER_DEF__VI {
	struct {
		unsigned int                             DEF : 28;
		unsigned int           LOCK_MC_FUS_DRAM_REGS : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM_APER_TOP__VI {
	struct {
		unsigned int                             TOP : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM_CTL_HIGH_01__VI {
	struct {
		unsigned int                 DCTHIGHADDROFF0 : 12;
		unsigned int                 DCTHIGHADDROFF1 : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM_CTL_HIGH_23__VI {
	struct {
		unsigned int                 DCTHIGHADDROFF2 : 12;
		unsigned int                 DCTHIGHADDROFF3 : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_FUS_DRAM_MODE__VI {
	struct {
		unsigned int                 DCTSELINTLVADDR : 3;
		unsigned int                        DRAMTYPE : 3;
		unsigned int                  DRAMHOLEOFFSET : 9;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_FEATURES__VI {
	struct {
		unsigned int                  WR_COMBINE_OFF : 1;
		unsigned int                 SCLK_CG_DISABLE : 1;
		unsigned int              PRB_FILTER_DISABLE : 1;
		unsigned int           ARB_NRT_STACK_DISABLE : 1;
		unsigned int              ARB_FIXED_PRIORITY : 1;
		unsigned int         PRIORITY_UPDATE_DISABLE : 1;
		unsigned int                   RT_BYPASS_OFF : 1;
		unsigned int           SYNC_ON_ERROR_DISABLE : 1;
		unsigned int            SYNC_REFLECT_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int                    ARB_STALL_EN : 1;
		unsigned int                 CREDIT_STALL_EN : 1;
		unsigned int               ARB_STALL_SET_SEL : 2;
		unsigned int               ARB_STALL_CLR_SEL : 2;
		unsigned int            CREDIT_STALL_SET_SEL : 2;
		unsigned int            CREDIT_STALL_CLR_SEL : 2;
		unsigned int                  WR_REORDER_OFF : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_PERFCOUNTER0_CFG__VI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                    PERF_SEL_END : 8;
		unsigned int                                 : 8;
		unsigned int                       PERF_MODE : 4;
		unsigned int                          ENABLE : 1;
		unsigned int                           CLEAR : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_PERFCOUNTER1_CFG__VI {
	struct {
		unsigned int                        PERF_SEL : 8;
		unsigned int                    PERF_SEL_END : 8;
		unsigned int                                 : 8;
		unsigned int                       PERF_MODE : 4;
		unsigned int                          ENABLE : 1;
		unsigned int                           CLEAR : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_PERFCOUNTER_HI__VI {
	struct {
		unsigned int                      COUNTER_HI : 16;
		unsigned int                   COMPARE_VALUE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_PERFCOUNTER_LO__VI {
	struct {
		unsigned int                      COUNTER_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_PERFCOUNTER_RSLT_CNTL__VI {
	struct {
		unsigned int             PERF_COUNTER_SELECT : 4;
		unsigned int                                 : 4;
		unsigned int                   START_TRIGGER : 8;
		unsigned int                    STOP_TRIGGER : 8;
		unsigned int                      ENABLE_ANY : 1;
		unsigned int                       CLEAR_ALL : 1;
		unsigned int            STOP_ALL_ON_SATURATE : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_POST_PROBE_DELAY__VI {
	struct {
		unsigned int                REQ_TO_RSP_DELAY : 5;
		unsigned int                                 : 3;
		unsigned int             REQLCL_TO_RET_DELAY : 5;
		unsigned int                                 : 3;
		unsigned int             REQREM_TO_RET_DELAY : 5;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_PROBE_CREDITS__VI {
	struct {
		unsigned int                CREDITS_LIMIT_LO : 6;
		unsigned int                                 : 2;
		unsigned int                CREDITS_LIMIT_HI : 6;
		unsigned int                                 : 1;
		unsigned int               INTPRB_FIFO_LEVEL : 1;
		unsigned int           INTPRB_TIMEOUT_THRESH : 3;
		unsigned int                                 : 1;
		unsigned int              MEM_TIMEOUT_THRESH : 3;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_PROBE_MAP__VI {
	struct {
		unsigned int                 ADDR0_TO_TC_MAP : 2;
		unsigned int                 ADDR1_TO_TC_MAP : 2;
		unsigned int                 ADDR2_TO_TC_MAP : 2;
		unsigned int                 ADDR3_TO_TC_MAP : 2;
		unsigned int               ADDR0_TO_GRUB_MAP : 1;
		unsigned int               ADDR1_TO_GRUB_MAP : 1;
		unsigned int               ADDR2_TO_GRUB_MAP : 1;
		unsigned int               ADDR3_TO_GRUB_MAP : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_TCB_DATA_HI__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_TCB_DATA_LO__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_TCB_INDEX__VI {
	struct {
		unsigned int                           INDEX : 7;
		unsigned int                                 : 1;
		unsigned int                      TCB0_WR_EN : 1;
		unsigned int                      TCB1_WR_EN : 1;
		unsigned int                           RD_EN : 1;
		unsigned int                         TCB_SEL : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_GRUB_TX_CREDITS__VI {
	struct {
		unsigned int                    SRCTAG_LIMIT : 6;
		unsigned int                                 : 2;
		unsigned int               SRCTAG_RT_RESERVE : 4;
		unsigned int                  NPC_RT_RESERVE : 4;
		unsigned int                  NPD_RT_RESERVE : 4;
		unsigned int                   TX_FIFO_DEPTH : 5;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_MISC_ATOMIC_IDLE_STATUS__VI {
	struct {
                unsigned int          OUTSTANDING_GFX_ATOMIC : 1;
                unsigned int          OUTSTANDING_RLC_ATOMIC : 1;
                unsigned int        OUTSTANDING_SDMA0_ATOMIC : 1;
                unsigned int        OUTSTANDING_SDMA1_ATOMIC : 1;
                unsigned int         OUTSTANDING_DISP_ATOMIC : 1;
                unsigned int          OUTSTANDING_UVD_ATOMIC : 1;
                unsigned int          OUTSTANDING_SMU_ATOMIC : 1;
                unsigned int          OUTSTANDING_HDP_ATOMIC : 1;
                unsigned int          OUTSTANDING_OTH_ATOMIC : 1;
                unsigned int          OUTSTANDING_VMC_ATOMIC : 1;
                unsigned int          OUTSTANDING_VCE_ATOMIC : 1;
                unsigned int          OUTSTANDING_ACP_ATOMIC : 1;
                unsigned int       OUTSTANDING_SAMMSP_ATOMIC : 1;
                unsigned int         OUTSTANDING_XDMA_ATOMIC : 1;
                unsigned int          OUTSTANDING_ISP_ATOMIC : 1;
                unsigned int          OUTSTANDING_VP8_ATOMIC : 1;
                unsigned int           OUTSTANDING_VIN0_READ : 1;
                unsigned int          OUTSTANDING_VIN0_WRITE : 1;
                unsigned int         OUTSTANDING_VIN0_ATOMIC : 1;
                unsigned int            OUTSTANDING_TLS_READ : 1;
                unsigned int           OUTSTANDING_TLS_WRITE : 1;
                unsigned int          OUTSTANDING_TLS_ATOMIC : 1;
                unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_BYPASS_GBL0__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                            CID1 : 8;
		unsigned int                            CID2 : 8;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_ISP_CCPU__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                PRIORITY_DISABLE : 1;
		unsigned int             STALL_FILTER_ENABLE : 1;
		unsigned int                 STALL_THRESHOLD : 6;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_ISP_MPM__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                PRIORITY_DISABLE : 1;
		unsigned int             STALL_FILTER_ENABLE : 1;
		unsigned int                 STALL_THRESHOLD : 6;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_ISP_SPM__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                PRIORITY_DISABLE : 1;
		unsigned int             STALL_FILTER_ENABLE : 1;
		unsigned int                 STALL_THRESHOLD : 6;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDS__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                 STALL_THRESHOLD : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDT__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                 STALL_THRESHOLD : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDU__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                 STALL_THRESHOLD : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_MCDV__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                             BUS : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                     ASK_CREDITS : 7;
		unsigned int                 DISPLAY_CREDITS : 7;
		unsigned int                 STALL_THRESHOLD : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_SAMMSP__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_TLS__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_VCE0__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                       VM_BYPASS : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_VCE1__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int                       VM_BYPASS : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_VCEU0__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_VCEU1__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_VP8__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_RDREQ_VP8U__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_BP2__VI {
	struct {
		unsigned int                           RDRET : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_BYPASS_GBL0__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                            CID1 : 8;
		unsigned int                            CID2 : 8;
		unsigned int               HDP_PRIORITY_TIME : 7;
		unsigned int               OTH_PRIORITY_TIME : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_BYPASS_GBL1__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                            CID1 : 8;
		unsigned int                            CID2 : 8;
		unsigned int               HDP_PRIORITY_TIME : 7;
		unsigned int               OTH_PRIORITY_TIME : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS2__VI {
	struct {
                unsigned int                       STOR0_PRI : 8;
                unsigned int                       STOR1_PRI : 8;
                unsigned int                             VM2 : 8;
                unsigned int                             VM3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS3__VI {
	struct {
		unsigned int                       STOR0_URG : 8;
		unsigned int                       STOR1_URG : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS_MCDS__VI {
	struct {
                unsigned int                          WR_PRI : 7;
                unsigned int          WR_PRI_STALL_THRESHOLD : 7;
                unsigned int                          WR_URG : 7;
                unsigned int          WR_URG_STALL_THRESHOLD : 7;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS_MCDT__VI {
	struct {
                unsigned int                          WR_PRI : 7;
                unsigned int          WR_PRI_STALL_THRESHOLD : 7;
                unsigned int                          WR_URG : 7;
                unsigned int          WR_URG_STALL_THRESHOLD : 7;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS_MCDU__VI {
	struct {
                unsigned int                          WR_PRI : 7;
                unsigned int          WR_PRI_STALL_THRESHOLD : 7;
                unsigned int                          WR_URG : 7;
                unsigned int          WR_URG_STALL_THRESHOLD : 7;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS_MCDV__VI {
	struct {
                unsigned int                          WR_PRI : 7;
                unsigned int          WR_PRI_STALL_THRESHOLD : 7;
                unsigned int                          WR_URG : 7;
                unsigned int          WR_URG_STALL_THRESHOLD : 7;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS_MCDW__VI {
	struct {
                unsigned int                          WR_PRI : 7;
                unsigned int          WR_PRI_STALL_THRESHOLD : 7;
                unsigned int                          WR_URG : 7;
                unsigned int          WR_URG_STALL_THRESHOLD : 7;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS_MCDX__VI {
	struct {
                unsigned int                          WR_PRI : 7;
                unsigned int          WR_PRI_STALL_THRESHOLD : 7;
                unsigned int                          WR_URG : 7;
                unsigned int          WR_URG_STALL_THRESHOLD : 7;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS_MCDY__VI {
	struct {
                unsigned int                          WR_PRI : 7;
                unsigned int          WR_PRI_STALL_THRESHOLD : 7;
                unsigned int                          WR_URG : 7;
                unsigned int          WR_URG_STALL_THRESHOLD : 7;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_CREDITS_MCDZ__VI {
	struct {
                unsigned int                          WR_PRI : 7;
                unsigned int          WR_PRI_STALL_THRESHOLD : 7;
                unsigned int                          WR_URG : 7;
                unsigned int          WR_URG_STALL_THRESHOLD : 7;
                unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_ISP_CCPU__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                PRIORITY_DISABLE : 1;
		unsigned int             STALL_FILTER_ENABLE : 1;
		unsigned int                 STALL_THRESHOLD : 6;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_ISP_MPM__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                PRIORITY_DISABLE : 1;
		unsigned int             STALL_FILTER_ENABLE : 1;
		unsigned int                 STALL_THRESHOLD : 6;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_ISP_MPS__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                PRIORITY_DISABLE : 1;
		unsigned int             STALL_FILTER_ENABLE : 1;
		unsigned int                 STALL_THRESHOLD : 6;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_ISP_SPM__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                PRIORITY_DISABLE : 1;
		unsigned int             STALL_FILTER_ENABLE : 1;
		unsigned int                 STALL_THRESHOLD : 6;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MCDS__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                     ASK_CREDITS : 6;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                 STALL_THRESHOLD : 7;
		unsigned int                   ASK_CREDITS_W : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MCDT__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                     ASK_CREDITS : 6;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                 STALL_THRESHOLD : 7;
		unsigned int                   ASK_CREDITS_W : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MCDU__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                     ASK_CREDITS : 6;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                 STALL_THRESHOLD : 7;
		unsigned int                   ASK_CREDITS_W : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_MCDV__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                     ASK_CREDITS : 6;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int                 STALL_THRESHOLD : 7;
		unsigned int                   ASK_CREDITS_W : 7;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_SAMMSP__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int       URG_BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_VCE0__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                       VM_BYPASS : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int       URG_BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_VCE1__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int                       VM_BYPASS : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int       URG_BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_VCEU0__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int       URG_BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_VCEU1__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int       URG_BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_VIN0__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int       URG_BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_VP8__VI {
	struct {
                unsigned int                          ENABLE : 1;
                unsigned int                        PRESCALE : 2;
                unsigned int                 BLACKOUT_EXEMPT : 1;
                unsigned int                      STALL_MODE : 2;
                unsigned int                  STALL_OVERRIDE : 1;
                unsigned int                        MAXBURST : 4;
                unsigned int                      LAZY_TIMER : 4;
                unsigned int              STALL_OVERRIDE_WTM : 1;
                unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int       URG_BYPASS_AVAIL_OVERRIDE : 1;
                unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WDP_VP8U__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        PRESCALE : 2;
		unsigned int                 BLACKOUT_EXEMPT : 1;
		unsigned int                      STALL_MODE : 2;
		unsigned int                  STALL_OVERRIDE : 1;
		unsigned int                        MAXBURST : 4;
		unsigned int                      LAZY_TIMER : 4;
		unsigned int              STALL_OVERRIDE_WTM : 1;
		unsigned int           BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int       URG_BYPASS_AVAIL_OVERRIDE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WRRET_MCDS__VI {
	struct {
		unsigned int                      STALL_MODE : 1;
		unsigned int                    CREDIT_COUNT : 7;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WRRET_MCDT__VI {
	struct {
		unsigned int                      STALL_MODE : 1;
		unsigned int                    CREDIT_COUNT : 7;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WRRET_MCDU__VI {
	struct {
		unsigned int                      STALL_MODE : 1;
		unsigned int                    CREDIT_COUNT : 7;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_HUB_WRRET_MCDV__VI {
	struct {
		unsigned int                      STALL_MODE : 1;
		unsigned int                    CREDIT_COUNT : 7;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_TCI_CNTL__VI {
	struct {
		unsigned int                      TCI_ENABLE : 1;
		unsigned int                      TCI_POLICY : 2;
		unsigned int                         TCI_VOL : 1;
		unsigned int                        TCI_VMID : 4;
		unsigned int                 TCI_REQ_CREDITS : 8;
		unsigned int                  TCI_MAX_WRITES : 8;
		unsigned int                   TCI_MAX_READS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_RPB_TCI_CNTL2__VI {
	struct {
		unsigned int                      TCI_POLICY : 1;
		unsigned int                       TCI_MTYPE : 2;
		unsigned int                       TCI_SNOOP : 1;
		unsigned int                    TCI_PHYSICAL : 1;
		unsigned int                TCI_PERF_CNTR_EN : 1;
		unsigned int                         TCI_EXE : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SEQ_IO_RESERVE__VI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SHARED_ACTIVE_FCN_ID__VI {
	struct {
		unsigned int                            VFID : 4;
		unsigned int                                 : 27;
		unsigned int                              VF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SHARED_CHREMAP2__VI {
	struct {
		unsigned int                           CHAN8 : 4;
		unsigned int                           CHAN9 : 4;
		unsigned int                          CHAN10 : 4;
		unsigned int                          CHAN11 : 4;
		unsigned int                          CHAN12 : 4;
		unsigned int                          CHAN13 : 4;
		unsigned int                          CHAN14 : 4;
		unsigned int                          CHAN15 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SHARED_VF_ENABLE__VI {
	struct {
		unsigned int                       VF_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_SHARED_VIRT_RESET_REQ__VI {
	struct {
		unsigned int                              VF : 16;
		unsigned int                                 : 15;
		unsigned int                              PF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF0__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF1__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF10__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF11__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF12__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF13__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF14__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF15__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF2__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF3__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF4__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF5__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF6__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF7__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF8__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_FB_SIZE_OFFSET_VF9__VI {
	struct {
		unsigned int                      VF_FB_SIZE : 16;
		unsigned int                    VF_FB_OFFSET : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_BASE_HI_0__VI {
	struct {
		unsigned int                  MARC_BASE_HI_0 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_BASE_HI_1__VI {
	struct {
		unsigned int                  MARC_BASE_HI_1 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_BASE_HI_2__VI {
	struct {
		unsigned int                  MARC_BASE_HI_2 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_BASE_HI_3__VI {
	struct {
		unsigned int                  MARC_BASE_HI_3 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_BASE_LO_0__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                  MARC_BASE_LO_0 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_BASE_LO_1__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                  MARC_BASE_LO_1 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_BASE_LO_2__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                  MARC_BASE_LO_2 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_BASE_LO_3__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                  MARC_BASE_LO_3 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_CNTL__VI {
	struct {
		unsigned int              ENABLE_ALL_CLIENTS : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_LEN_HI_0__VI {
	struct {
		unsigned int                   MARC_LEN_HI_0 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_LEN_HI_1__VI {
	struct {
		unsigned int                   MARC_LEN_HI_1 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_LEN_HI_2__VI {
	struct {
		unsigned int                   MARC_LEN_HI_2 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_LEN_HI_3__VI {
	struct {
		unsigned int                   MARC_LEN_HI_3 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_LEN_LO_0__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                   MARC_LEN_LO_0 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_LEN_LO_1__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                   MARC_LEN_LO_1 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_LEN_LO_2__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                   MARC_LEN_LO_2 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_LEN_LO_3__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                   MARC_LEN_LO_3 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_RELOC_HI_0__VI {
	struct {
		unsigned int                 MARC_RELOC_HI_0 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_RELOC_HI_1__VI {
	struct {
		unsigned int                 MARC_RELOC_HI_1 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_RELOC_HI_2__VI {
	struct {
		unsigned int                 MARC_RELOC_HI_2 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_RELOC_HI_3__VI {
	struct {
		unsigned int                 MARC_RELOC_HI_3 : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_RELOC_LO_0__VI {
	struct {
		unsigned int                   MARC_ENABLE_0 : 1;
		unsigned int                 MARC_READONLY_0 : 1;
		unsigned int                                 : 10;
		unsigned int                 MARC_RELOC_LO_0 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_RELOC_LO_1__VI {
	struct {
		unsigned int                   MARC_ENABLE_1 : 1;
		unsigned int                 MARC_READONLY_1 : 1;
		unsigned int                                 : 10;
		unsigned int                 MARC_RELOC_LO_1 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_RELOC_LO_2__VI {
	struct {
		unsigned int                   MARC_ENABLE_2 : 1;
		unsigned int                 MARC_READONLY_2 : 1;
		unsigned int                                 : 10;
		unsigned int                 MARC_RELOC_LO_2 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MARC_RELOC_LO_3__VI {
	struct {
		unsigned int                   MARC_ENABLE_3 : 1;
		unsigned int                 MARC_READONLY_3 : 1;
		unsigned int                                 : 10;
		unsigned int                 MARC_RELOC_LO_3 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLB1_DEBUG__VI {
	struct {
		unsigned int               INVALIDATE_L1_TLB : 1;
		unsigned int                                 : 7;
		unsigned int                SEND_FREE_AT_RTN : 1;
		unsigned int           EFFECTIVE_L1_TLB_SIZE : 3;
		unsigned int         EFFECTIVE_L1_QUEUE_SIZE : 3;
		unsigned int                    L1_TLB_DEBUG : 4;
		unsigned int               L1_TLB_FORCE_MISS : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_CNTL0__VI {
	struct {
		unsigned int                   REQ_STREAM_ID : 9;
		unsigned int                                 : 3;
		unsigned int                              EN : 1;
		unsigned int                   PREFETCH_DONE : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_CNTL1__VI {
	struct {
		unsigned int                   REQ_STREAM_ID : 9;
		unsigned int                                 : 3;
		unsigned int                              EN : 1;
		unsigned int                   PREFETCH_DONE : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_CNTL2__VI {
	struct {
		unsigned int                   REQ_STREAM_ID : 9;
		unsigned int                                 : 3;
		unsigned int                              EN : 1;
		unsigned int                   PREFETCH_DONE : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_CNTL3__VI {
	struct {
		unsigned int                   REQ_STREAM_ID : 9;
		unsigned int                                 : 3;
		unsigned int                              EN : 1;
		unsigned int                   PREFETCH_DONE : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_CNTL4__VI {
	struct {
		unsigned int                   REQ_STREAM_ID : 9;
		unsigned int                                 : 3;
		unsigned int                              EN : 1;
		unsigned int                   PREFETCH_DONE : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_CNTL5__VI {
	struct {
		unsigned int                   REQ_STREAM_ID : 9;
		unsigned int                                 : 3;
		unsigned int                              EN : 1;
		unsigned int                   PREFETCH_DONE : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_CNTL6__VI {
	struct {
		unsigned int                   REQ_STREAM_ID : 9;
		unsigned int                                 : 3;
		unsigned int                              EN : 1;
		unsigned int                   PREFETCH_DONE : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_CNTL7__VI {
	struct {
		unsigned int                   REQ_STREAM_ID : 9;
		unsigned int                                 : 3;
		unsigned int                              EN : 1;
		unsigned int                   PREFETCH_DONE : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_CNTL8__VI {
	struct {
		unsigned int                   REQ_STREAM_ID : 9;
		unsigned int                                 : 3;
		unsigned int                              EN : 1;
		unsigned int                   PREFETCH_DONE : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_END_ADDR0__VI {
	struct {
		unsigned int                        END_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_END_ADDR1__VI {
	struct {
		unsigned int                        END_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_END_ADDR2__VI {
	struct {
		unsigned int                        END_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_END_ADDR3__VI {
	struct {
		unsigned int                        END_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_END_ADDR4__VI {
	struct {
		unsigned int                        END_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_END_ADDR5__VI {
	struct {
		unsigned int                        END_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_END_ADDR6__VI {
	struct {
		unsigned int                        END_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_END_ADDR7__VI {
	struct {
		unsigned int                        END_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_END_ADDR8__VI {
	struct {
		unsigned int                        END_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__VI {
	struct {
		unsigned int               LOGICAL_PAGE_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VI {
	struct {
		unsigned int                     PROTECTIONS : 8;
		unsigned int                                 : 4;
		unsigned int                MEMORY_CLIENT_ID : 9;
		unsigned int                                 : 3;
		unsigned int                MEMORY_CLIENT_RW : 1;
		unsigned int                            VMID : 4;
		unsigned int                          ATOMIC : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_START_ADDR0__VI {
	struct {
		unsigned int                      START_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_START_ADDR1__VI {
	struct {
		unsigned int                      START_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_START_ADDR2__VI {
	struct {
		unsigned int                      START_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_START_ADDR3__VI {
	struct {
		unsigned int                      START_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_START_ADDR4__VI {
	struct {
		unsigned int                      START_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_START_ADDR5__VI {
	struct {
		unsigned int                      START_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_START_ADDR6__VI {
	struct {
		unsigned int                      START_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_START_ADDR7__VI {
	struct {
		unsigned int                      START_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_MB_L1_TLS0_START_ADDR8__VI {
	struct {
		unsigned int                      START_ADDR : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_NB_LOWER_TOP_OF_DRAM2__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 22;
		unsigned int                      LOWER_TOM2 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_NB_MMIOBASE__VI {
	struct {
		unsigned int                        MMIOBASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_NB_MMIOLIMIT__VI {
	struct {
		unsigned int                       MMIOLIMIT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_NB_PCI_ARB__VI {
	struct {
		unsigned int                                 : 3;
		unsigned int                        VGA_HOLE : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_NB_PCI_CTRL__VI {
	struct {
		unsigned int                                 : 23;
		unsigned int                      MMIOENABLE : 1;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_NB_TOP_OF_DRAM3__VI {
	struct {
		unsigned int                      TOM3_LIMIT : 30;
		unsigned int                                 : 1;
		unsigned int                     TOM3_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_NB_TOP_OF_DRAM_SLOT1__VI {
	struct {
		unsigned int                                 : 23;
		unsigned int                     TOP_OF_DRAM : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_VM_NB_UPPER_TOP_OF_DRAM2__VI {
	struct {
		unsigned int                      UPPER_TOM2 : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_FIFO_MON_CNTL0__VI {
	struct {
		unsigned int                    START_THRESH : 12;
		unsigned int                     STOP_THRESH : 12;
		unsigned int                      START_MODE : 2;
		unsigned int                       STOP_MODE : 2;
		unsigned int                      ALLOW_WRAP : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_FIFO_MON_CNTL1__VI {
	struct {
		unsigned int                  THRESH_CNTR_ID : 8;
		unsigned int                   START_TRIG_ID : 8;
		unsigned int                    STOP_TRIG_ID : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_FIFO_MON_CNTL2__VI {
	struct {
		unsigned int                         MON0_ID : 8;
		unsigned int                         MON1_ID : 8;
		unsigned int                         MON2_ID : 8;
		unsigned int                         MON3_ID : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_FIFO_MON_MAX_THSH__VI {
	struct {
		unsigned int                            MON0 : 8;
		unsigned int                            MON1 : 8;
		unsigned int                            MON2 : 8;
		unsigned int                            MON3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_FIFO_MON_RSLT0__VI {
	struct {
		unsigned int                           COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_FIFO_MON_RSLT1__VI {
	struct {
		unsigned int                           COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_FIFO_MON_RSLT2__VI {
	struct {
		unsigned int                           COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MC_XBAR_FIFO_MON_RSLT3__VI {
	struct {
		unsigned int                           COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MILLISECOND_TIME_BASE_DIV__VI {
	struct {
		unsigned int       MILLISECOND_TIME_BASE_DIV : 17;
		unsigned int                                 : 3;
		unsigned int MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MP_FPS_CNT__VI {
	struct {
		unsigned int                         FPS_CNT : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MSI_MASK__VI {
	struct {
		unsigned int                        MSI_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MSI_MASK_64__VI {
	struct {
		unsigned int                     MSI_MASK_64 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MSI_PENDING__VI {
	struct {
		unsigned int                     MSI_PENDING : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MSI_PENDING_64__VI {
	struct {
		unsigned int                  MSI_PENDING_64 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union MVP_DEBUG__VI {
	struct {
		unsigned int             MVP_SWAP_LOCK_IN_EN : 1;
		unsigned int          MVP_FLOW_CONTROL_IN_EN : 1;
		unsigned int            MVP_SWAP_LOCK_IN_SEL : 1;
		unsigned int         MVP_FLOW_CONTROL_IN_SEL : 1;
		unsigned int MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP : 1;
		unsigned int MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP : 1;
		unsigned int MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR : 1;
		unsigned int MVP_DIS_READ_POINTER_RESET_DELAY : 1;
		unsigned int                  MVP_DEBUG_BITS : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C11_C12__VI {
	struct {
		unsigned int                  OUTPUT_CSC_C11 : 16;
		unsigned int                  OUTPUT_CSC_C12 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C11_C12_A__VI {
	struct {
		unsigned int                OUTPUT_CSC_C11_A : 16;
		unsigned int                OUTPUT_CSC_C12_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C11_C12_B__VI {
	struct {
		unsigned int                OUTPUT_CSC_C11_B : 16;
		unsigned int                OUTPUT_CSC_C12_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C13_C14__VI {
	struct {
		unsigned int                  OUTPUT_CSC_C13 : 16;
		unsigned int                  OUTPUT_CSC_C14 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C13_C14_A__VI {
	struct {
		unsigned int                OUTPUT_CSC_C13_A : 16;
		unsigned int                OUTPUT_CSC_C14_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C13_C14_B__VI {
	struct {
		unsigned int                OUTPUT_CSC_C13_B : 16;
		unsigned int                OUTPUT_CSC_C14_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C21_C22__VI {
	struct {
		unsigned int                  OUTPUT_CSC_C21 : 16;
		unsigned int                  OUTPUT_CSC_C22 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C21_C22_A__VI {
	struct {
		unsigned int                OUTPUT_CSC_C21_A : 16;
		unsigned int                OUTPUT_CSC_C22_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C21_C22_B__VI {
	struct {
		unsigned int                OUTPUT_CSC_C21_B : 16;
		unsigned int                OUTPUT_CSC_C22_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C23_C24__VI {
	struct {
		unsigned int                  OUTPUT_CSC_C23 : 16;
		unsigned int                  OUTPUT_CSC_C24 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C23_C24_A__VI {
	struct {
		unsigned int                OUTPUT_CSC_C23_A : 16;
		unsigned int                OUTPUT_CSC_C24_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C23_C24_B__VI {
	struct {
		unsigned int                OUTPUT_CSC_C23_B : 16;
		unsigned int                OUTPUT_CSC_C24_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C31_C32__VI {
	struct {
		unsigned int                  OUTPUT_CSC_C31 : 16;
		unsigned int                  OUTPUT_CSC_C32 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C31_C32_A__VI {
	struct {
		unsigned int                OUTPUT_CSC_C31_A : 16;
		unsigned int                OUTPUT_CSC_C32_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C31_C32_B__VI {
	struct {
		unsigned int                OUTPUT_CSC_C31_B : 16;
		unsigned int                OUTPUT_CSC_C32_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C33_C34__VI {
	struct {
		unsigned int                  OUTPUT_CSC_C33 : 16;
		unsigned int                  OUTPUT_CSC_C34 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C33_C34_A__VI {
	struct {
		unsigned int                OUTPUT_CSC_C33_A : 16;
		unsigned int                OUTPUT_CSC_C34_A : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_C33_C34_B__VI {
	struct {
		unsigned int                OUTPUT_CSC_C33_B : 16;
		unsigned int                OUTPUT_CSC_C34_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_CSC_CONTROL__VI {
	struct {
		unsigned int            OUTPUT_CSC_GRPH_MODE : 3;
		unsigned int                                 : 1;
		unsigned int             OUTPUT_CSC_OVL_MODE : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__VI {
	struct {
		unsigned int BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS : 7;
		unsigned int BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__VI {
	struct {
		unsigned int BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__VI {
	struct {
		unsigned int                    STREAM_RESET : 1;
		unsigned int                      STREAM_RUN : 1;
		unsigned int  INTERRUPT_ON_COMPLETION_ENABLE : 1;
		unsigned int     FIFO_ERROR_INTERRUPT_ENABLE : 1;
		unsigned int DESCRIPTOR_ERROR_INTERRUPT_ENABLE : 1;
		unsigned int                                 : 11;
		unsigned int                  STRIPE_CONTROL : 2;
		unsigned int                TRAFFIC_PRIORITY : 1;
		unsigned int                                 : 1;
		unsigned int                   STREAM_NUMBER : 4;
		unsigned int                                 : 2;
		unsigned int BUFFER_COMPLETION_INTERRUPT_STATUS : 1;
		unsigned int                      FIFO_ERROR : 1;
		unsigned int                DESCRIPTOR_ERROR : 1;
		unsigned int                      FIFO_READY : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__VI {
	struct {
		unsigned int            CYCLIC_BUFFER_LENGTH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__VI {
	struct {
		unsigned int                       FIFO_SIZE : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_STREAM_DESCRIPTOR_FORMAT__VI {
	struct {
		unsigned int              NUMBER_OF_CHANNELS : 4;
		unsigned int                 BITS_PER_SAMPLE : 3;
		unsigned int                                 : 1;
		unsigned int             SAMPLE_BASE_DIVISOR : 3;
		unsigned int            SAMPLE_BASE_MULTIPLE : 3;
		unsigned int                SAMPLE_BASE_RATE : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__VI {
	struct {
		unsigned int                LAST_VALID_INDEX : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__VI {
	struct {
		unsigned int         LINK_POSITION_IN_BUFFER : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__VI {
	struct {
		unsigned int   LINK_POSITION_IN_BUFFER_ALIAS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUTPUT_STREAM_PAYLOAD_CAPABILITY__VI {
	struct {
		unsigned int                      OUTSTRMPAY : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUT_CLAMP_CONTROL_B_CB__VI {
	struct {
		unsigned int              OUT_CLAMP_MAX_B_CB : 14;
		unsigned int                                 : 2;
		unsigned int              OUT_CLAMP_MIN_B_CB : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUT_CLAMP_CONTROL_G_Y__VI {
	struct {
		unsigned int               OUT_CLAMP_MAX_G_Y : 14;
		unsigned int                                 : 2;
		unsigned int               OUT_CLAMP_MIN_G_Y : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUT_CLAMP_CONTROL_R_CR__VI {
	struct {
		unsigned int              OUT_CLAMP_MAX_R_CR : 14;
		unsigned int                                 : 2;
		unsigned int              OUT_CLAMP_MIN_R_CR : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OUT_ROUND_CONTROL__VI {
	struct {
		unsigned int            OUT_ROUND_TRUNC_MODE : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_SECONDARY_SURFACE_ADDRESS__VI {
	struct {
		unsigned int        OVL_SECONDARY_DFQ_ENABLE : 1;
		unsigned int                                 : 7;
		unsigned int   OVL_SECONDARY_SURFACE_ADDRESS : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI {
	struct {
		unsigned int OVL_SECONDARY_SURFACE_ADDRESS_HIGH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union OVL_STEREOSYNC_FLIP__VI {
	struct {
		unsigned int          OVL_STEREOSYNC_FLIP_EN : 1;
		unsigned int                                 : 7;
		unsigned int        OVL_STEREOSYNC_FLIP_MODE : 2;
		unsigned int                                 : 6;
		unsigned int     OVL_PRIMARY_SURFACE_PENDING : 1;
		unsigned int   OVL_SECONDARY_SURFACE_PENDING : 1;
		unsigned int                                 : 10;
		unsigned int   OVL_STEREOSYNC_SELECT_DISABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_BIF_CMD_STATUS__VI {
	struct {
		unsigned int                   TXPHYSTATUS_0 : 1;
		unsigned int                   TXPHYSTATUS_1 : 1;
		unsigned int                   TXPHYSTATUS_2 : 1;
		unsigned int                   TXPHYSTATUS_3 : 1;
		unsigned int                   TXPHYSTATUS_4 : 1;
		unsigned int                   TXPHYSTATUS_5 : 1;
		unsigned int                   TXPHYSTATUS_6 : 1;
		unsigned int                   TXPHYSTATUS_7 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                   RXPHYSTATUS_0 : 1;
		unsigned int                   RXPHYSTATUS_1 : 1;
		unsigned int                   RXPHYSTATUS_2 : 1;
		unsigned int                   RXPHYSTATUS_3 : 1;
		unsigned int                   RXPHYSTATUS_4 : 1;
		unsigned int                   RXPHYSTATUS_5 : 1;
		unsigned int                   RXPHYSTATUS_6 : 1;
		unsigned int                   RXPHYSTATUS_7 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_CMD_BUS_CTRL__VI {
	struct {
                unsigned int               CMD_BUS_SCHL_MODE : 2;
                unsigned int               CMD_BUS_STAG_MODE : 2;
                unsigned int                CMD_BUS_STAG_DIS : 1;
                unsigned int            CMD_BUS_SCH_REQ_MODE : 2;
                unsigned int           CMD_BUS_IGNR_PEND_PWR : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_CMD_BUS_GLB_OVRD__VI {
	struct {
		unsigned int                  TXMARG_OVRD_EN : 1;
		unsigned int                  DEEMPH_OVRD_EN : 1;
		unsigned int                 PLLFREQ_OVRD_EN : 1;
		unsigned int                          TXMARG : 3;
		unsigned int                          DEEMPH : 1;
		unsigned int                         PLLFREQ : 2;
		unsigned int           RESPONSEMODE_PIF_OVRD : 1;
		unsigned int                                 : 6;
		unsigned int              CMD_BUS_LANE_DIS_0 : 1;
		unsigned int              CMD_BUS_LANE_DIS_1 : 1;
		unsigned int              CMD_BUS_LANE_DIS_2 : 1;
		unsigned int              CMD_BUS_LANE_DIS_3 : 1;
		unsigned int              CMD_BUS_LANE_DIS_4 : 1;
		unsigned int              CMD_BUS_LANE_DIS_5 : 1;
		unsigned int              CMD_BUS_LANE_DIS_6 : 1;
		unsigned int              CMD_BUS_LANE_DIS_7 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_CTRL__VI {
	struct {
                unsigned int                PIF_PLL_PWRDN_EN : 1;
                unsigned int            DTM_FORCE_FREQDIV_X1 : 1;
                unsigned int      PIF_PLL_HNDSHK_EARLY_ABORT : 1;
                unsigned int        PIF_PLL_PWRDN_EARLY_EXIT : 1;
                unsigned int               PHY_RST_PWROK_VDD : 1;
                unsigned int                                 : 1;
                unsigned int                  PIF_PLL_STATUS : 2;
                unsigned int        PIF_PLL_DEGRADE_OFF_VOTE : 1;
                unsigned int         PIF_PLL_UNUSED_OFF_VOTE : 1;
                unsigned int         PIF_PLL_DEGRADE_S2_VOTE : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_GLB_OVRD__VI {
	struct {
		unsigned int         RXDETECT_OVERRIDE_VAL_0 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_1 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_2 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_3 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_4 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_5 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_6 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_7 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int            RXDETECT_OVERRIDE_EN : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_GLB_OVRD2__VI {
	struct {
		unsigned int                X2_LANE_1_0_OVRD : 1;
		unsigned int                X2_LANE_3_2_OVRD : 1;
		unsigned int                X2_LANE_5_4_OVRD : 1;
		unsigned int                X2_LANE_7_6_OVRD : 1;
		unsigned int                X2_LANE_9_8_OVRD : 1;
		unsigned int              X2_LANE_11_10_OVRD : 1;
		unsigned int              X2_LANE_13_12_OVRD : 1;
		unsigned int              X2_LANE_15_14_OVRD : 1;
		unsigned int                X4_LANE_3_0_OVRD : 1;
		unsigned int                X4_LANE_7_4_OVRD : 1;
		unsigned int               X4_LANE_11_8_OVRD : 1;
		unsigned int              X4_LANE_15_12_OVRD : 1;
		unsigned int                                 : 4;
		unsigned int                X8_LANE_7_0_OVRD : 1;
		unsigned int               X8_LANE_15_8_OVRD : 1;
		unsigned int                                 : 2;
		unsigned int              X16_LANE_15_0_OVRD : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE0_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_0 : 1;
		unsigned int               FREQDIV_OVRD_EN_0 : 1;
		unsigned int             LINKSPEED_OVRD_EN_0 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_0 : 1;
		unsigned int                 TXPWR_OVRD_EN_0 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_0 : 1;
		unsigned int                 RXPWR_OVRD_EN_0 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_0 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_0 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_0 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_0 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_0 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_0 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_0 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_0 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_0 : 1;
		unsigned int                 CDREN_OVRD_EN_0 : 1;
		unsigned int                CDREN_OVRD_VAL_0 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE0_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_0 : 3;
		unsigned int                       FREQDIV_0 : 2;
		unsigned int                     LINKSPEED_0 : 2;
		unsigned int                  TWOSYMENABLE_0 : 1;
		unsigned int                         TXPWR_0 : 3;
		unsigned int                    TXPGENABLE_0 : 2;
		unsigned int                         RXPWR_0 : 3;
		unsigned int                    RXPGENABLE_0 : 2;
		unsigned int                 ELECIDLEDETEN_0 : 1;
		unsigned int                     ENABLEFOM_0 : 1;
		unsigned int                    REQUESTFOM_0 : 1;
		unsigned int                  RESPONSEMODE_0 : 1;
		unsigned int                    REQUESTTRK_0 : 1;
		unsigned int                    REQUESTTRN_0 : 1;
		unsigned int                 COEFFICIENTID_0 : 2;
		unsigned int                   COEFFICIENT_0 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE1_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_1 : 1;
		unsigned int               FREQDIV_OVRD_EN_1 : 1;
		unsigned int             LINKSPEED_OVRD_EN_1 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_1 : 1;
		unsigned int                 TXPWR_OVRD_EN_1 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_1 : 1;
		unsigned int                 RXPWR_OVRD_EN_1 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_1 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_1 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_1 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_1 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_1 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_1 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_1 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_1 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_1 : 1;
		unsigned int                 CDREN_OVRD_EN_1 : 1;
		unsigned int                CDREN_OVRD_VAL_1 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE1_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_1 : 3;
		unsigned int                       FREQDIV_1 : 2;
		unsigned int                     LINKSPEED_1 : 2;
		unsigned int                  TWOSYMENABLE_1 : 1;
		unsigned int                         TXPWR_1 : 3;
		unsigned int                    TXPGENABLE_1 : 2;
		unsigned int                         RXPWR_1 : 3;
		unsigned int                    RXPGENABLE_1 : 2;
		unsigned int                 ELECIDLEDETEN_1 : 1;
		unsigned int                     ENABLEFOM_1 : 1;
		unsigned int                    REQUESTFOM_1 : 1;
		unsigned int                  RESPONSEMODE_1 : 1;
		unsigned int                    REQUESTTRK_1 : 1;
		unsigned int                    REQUESTTRN_1 : 1;
		unsigned int                 COEFFICIENTID_1 : 2;
		unsigned int                   COEFFICIENT_1 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE2_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_2 : 1;
		unsigned int               FREQDIV_OVRD_EN_2 : 1;
		unsigned int             LINKSPEED_OVRD_EN_2 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_2 : 1;
		unsigned int                 TXPWR_OVRD_EN_2 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_2 : 1;
		unsigned int                 RXPWR_OVRD_EN_2 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_2 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_2 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_2 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_2 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_2 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_2 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_2 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_2 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_2 : 1;
		unsigned int                 CDREN_OVRD_EN_2 : 1;
		unsigned int                CDREN_OVRD_VAL_2 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE2_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_2 : 3;
		unsigned int                       FREQDIV_2 : 2;
		unsigned int                     LINKSPEED_2 : 2;
		unsigned int                  TWOSYMENABLE_2 : 1;
		unsigned int                         TXPWR_2 : 3;
		unsigned int                    TXPGENABLE_2 : 2;
		unsigned int                         RXPWR_2 : 3;
		unsigned int                    RXPGENABLE_2 : 2;
		unsigned int                 ELECIDLEDETEN_2 : 1;
		unsigned int                     ENABLEFOM_2 : 1;
		unsigned int                    REQUESTFOM_2 : 1;
		unsigned int                  RESPONSEMODE_2 : 1;
		unsigned int                    REQUESTTRK_2 : 1;
		unsigned int                    REQUESTTRN_2 : 1;
		unsigned int                 COEFFICIENTID_2 : 2;
		unsigned int                   COEFFICIENT_2 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE3_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_3 : 1;
		unsigned int               FREQDIV_OVRD_EN_3 : 1;
		unsigned int             LINKSPEED_OVRD_EN_3 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_3 : 1;
		unsigned int                 TXPWR_OVRD_EN_3 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_3 : 1;
		unsigned int                 RXPWR_OVRD_EN_3 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_3 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_3 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_3 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_3 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_3 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_3 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_3 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_3 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_3 : 1;
		unsigned int                 CDREN_OVRD_EN_3 : 1;
		unsigned int                CDREN_OVRD_VAL_3 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE3_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_3 : 3;
		unsigned int                       FREQDIV_3 : 2;
		unsigned int                     LINKSPEED_3 : 2;
		unsigned int                  TWOSYMENABLE_3 : 1;
		unsigned int                         TXPWR_3 : 3;
		unsigned int                    TXPGENABLE_3 : 2;
		unsigned int                         RXPWR_3 : 3;
		unsigned int                    RXPGENABLE_3 : 2;
		unsigned int                 ELECIDLEDETEN_3 : 1;
		unsigned int                     ENABLEFOM_3 : 1;
		unsigned int                    REQUESTFOM_3 : 1;
		unsigned int                  RESPONSEMODE_3 : 1;
		unsigned int                    REQUESTTRK_3 : 1;
		unsigned int                    REQUESTTRN_3 : 1;
		unsigned int                 COEFFICIENTID_3 : 2;
		unsigned int                   COEFFICIENT_3 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE4_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_4 : 1;
		unsigned int               FREQDIV_OVRD_EN_4 : 1;
		unsigned int             LINKSPEED_OVRD_EN_4 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_4 : 1;
		unsigned int                 TXPWR_OVRD_EN_4 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_4 : 1;
		unsigned int                 RXPWR_OVRD_EN_4 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_4 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_4 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_4 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_4 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_4 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_4 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_4 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_4 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_4 : 1;
		unsigned int                 CDREN_OVRD_EN_4 : 1;
		unsigned int                CDREN_OVRD_VAL_4 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE4_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_4 : 3;
		unsigned int                       FREQDIV_4 : 2;
		unsigned int                     LINKSPEED_4 : 2;
		unsigned int                  TWOSYMENABLE_4 : 1;
		unsigned int                         TXPWR_4 : 3;
		unsigned int                    TXPGENABLE_4 : 2;
		unsigned int                         RXPWR_4 : 3;
		unsigned int                    RXPGENABLE_4 : 2;
		unsigned int                 ELECIDLEDETEN_4 : 1;
		unsigned int                     ENABLEFOM_4 : 1;
		unsigned int                    REQUESTFOM_4 : 1;
		unsigned int                  RESPONSEMODE_4 : 1;
		unsigned int                    REQUESTTRK_4 : 1;
		unsigned int                    REQUESTTRN_4 : 1;
		unsigned int                 COEFFICIENTID_4 : 2;
		unsigned int                   COEFFICIENT_4 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE5_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_5 : 1;
		unsigned int               FREQDIV_OVRD_EN_5 : 1;
		unsigned int             LINKSPEED_OVRD_EN_5 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_5 : 1;
		unsigned int                 TXPWR_OVRD_EN_5 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_5 : 1;
		unsigned int                 RXPWR_OVRD_EN_5 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_5 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_5 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_5 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_5 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_5 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_5 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_5 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_5 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_5 : 1;
		unsigned int                 CDREN_OVRD_EN_5 : 1;
		unsigned int                CDREN_OVRD_VAL_5 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE5_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_5 : 3;
		unsigned int                       FREQDIV_5 : 2;
		unsigned int                     LINKSPEED_5 : 2;
		unsigned int                  TWOSYMENABLE_5 : 1;
		unsigned int                         TXPWR_5 : 3;
		unsigned int                    TXPGENABLE_5 : 2;
		unsigned int                         RXPWR_5 : 3;
		unsigned int                    RXPGENABLE_5 : 2;
		unsigned int                 ELECIDLEDETEN_5 : 1;
		unsigned int                     ENABLEFOM_5 : 1;
		unsigned int                    REQUESTFOM_5 : 1;
		unsigned int                  RESPONSEMODE_5 : 1;
		unsigned int                    REQUESTTRK_5 : 1;
		unsigned int                    REQUESTTRN_5 : 1;
		unsigned int                 COEFFICIENTID_5 : 2;
		unsigned int                   COEFFICIENT_5 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE6_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_6 : 1;
		unsigned int               FREQDIV_OVRD_EN_6 : 1;
		unsigned int             LINKSPEED_OVRD_EN_6 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_6 : 1;
		unsigned int                 TXPWR_OVRD_EN_6 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_6 : 1;
		unsigned int                 RXPWR_OVRD_EN_6 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_6 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_6 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_6 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_6 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_6 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_6 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_6 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_6 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_6 : 1;
		unsigned int                 CDREN_OVRD_EN_6 : 1;
		unsigned int                CDREN_OVRD_VAL_6 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE6_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_6 : 3;
		unsigned int                       FREQDIV_6 : 2;
		unsigned int                     LINKSPEED_6 : 2;
		unsigned int                  TWOSYMENABLE_6 : 1;
		unsigned int                         TXPWR_6 : 3;
		unsigned int                    TXPGENABLE_6 : 2;
		unsigned int                         RXPWR_6 : 3;
		unsigned int                    RXPGENABLE_6 : 2;
		unsigned int                 ELECIDLEDETEN_6 : 1;
		unsigned int                     ENABLEFOM_6 : 1;
		unsigned int                    REQUESTFOM_6 : 1;
		unsigned int                  RESPONSEMODE_6 : 1;
		unsigned int                    REQUESTTRK_6 : 1;
		unsigned int                    REQUESTTRN_6 : 1;
		unsigned int                 COEFFICIENTID_6 : 2;
		unsigned int                   COEFFICIENT_6 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE7_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_7 : 1;
		unsigned int               FREQDIV_OVRD_EN_7 : 1;
		unsigned int             LINKSPEED_OVRD_EN_7 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_7 : 1;
		unsigned int                 TXPWR_OVRD_EN_7 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_7 : 1;
		unsigned int                 RXPWR_OVRD_EN_7 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_7 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_7 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_7 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_7 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_7 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_7 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_7 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_7 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_7 : 1;
		unsigned int                 CDREN_OVRD_EN_7 : 1;
		unsigned int                CDREN_OVRD_VAL_7 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_LANE7_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_7 : 3;
		unsigned int                       FREQDIV_7 : 2;
		unsigned int                     LINKSPEED_7 : 2;
		unsigned int                  TWOSYMENABLE_7 : 1;
		unsigned int                         TXPWR_7 : 3;
		unsigned int                    TXPGENABLE_7 : 2;
		unsigned int                         RXPWR_7 : 3;
		unsigned int                    RXPGENABLE_7 : 2;
		unsigned int                 ELECIDLEDETEN_7 : 1;
		unsigned int                     ENABLEFOM_7 : 1;
		unsigned int                    REQUESTFOM_7 : 1;
		unsigned int                  RESPONSEMODE_7 : 1;
		unsigned int                    REQUESTTRK_7 : 1;
		unsigned int                    REQUESTTRN_7 : 1;
		unsigned int                 COEFFICIENTID_7 : 2;
		unsigned int                   COEFFICIENT_7 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_RX_CTRL__VI {
	struct {
                unsigned int                     RXPWR_IN_S2 : 3;
                unsigned int                RXPWR_IN_SPDCHNG : 3;
                unsigned int                    RXPWR_IN_OFF : 3;
                unsigned int                RXPWR_IN_DEGRADE : 3;
                unsigned int                 RXPWR_IN_UNUSED : 3;
                unsigned int                   RXPWR_IN_INIT : 3;
                unsigned int                RXPWR_IN_PLL_OFF : 3;
                unsigned int           RXPWR_IN_DEGRADE_MODE : 1;
                unsigned int            RXPWR_IN_UNUSED_MODE : 1;
                unsigned int              RXPWR_GATING_IN_L1 : 1;
                unsigned int          RXPWR_GATING_IN_UNUSED : 1;
                unsigned int                RX_HLD_EIE_COUNT : 1;
                unsigned int        RX_EI_DET_IN_PS2_DEGRADE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_RX_CTRL2__VI {
	struct {
		unsigned int              RX_RDY_DASRT_COUNT : 3;
		unsigned int           RX_STATUS_DASRT_COUNT : 3;
		unsigned int               RXPHYSTATUS_DELAY : 3;
		unsigned int                                 : 7;
		unsigned int              FORCE_CDREN_IN_L0S : 1;
		unsigned int               EI_DET_CYCLE_MODE : 2;
		unsigned int                  EI_DET_ON_TIME : 2;
		unsigned int                 EI_DET_OFF_TIME : 3;
		unsigned int         EI_DET_CYCLE_DIS_IN_PS1 : 1;
		unsigned int                RX_CDR_XTND_MODE : 2;
		unsigned int          RX_L0S_TO_L0_DETECT_EI : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_STRAP_0__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int           STRAP_TX_RDY_XTND_DIS : 1;
		unsigned int           STRAP_RX_RDY_XTND_DIS : 1;
		unsigned int        STRAP_TX_STATUS_XTND_DIS : 1;
		unsigned int        STRAP_RX_STATUS_XTND_DIS : 1;
		unsigned int            STRAP_FORCE_OWN_MSTR : 1;
		unsigned int           STRAP_PIF_CDR_EN_MODE : 2;
		unsigned int              STRAP_RX_EI_FILTER : 2;
		unsigned int     STRAP_RX_DIS_HLD_EIE_IN_PS1 : 1;
		unsigned int     STRAP_RX_DIS_HLD_EIE_IN_PS2 : 1;
		unsigned int                STRAP_PIF_BIT_12 : 1;
		unsigned int                STRAP_PIF_BIT_13 : 1;
		unsigned int                STRAP_PIF_BIT_14 : 1;
		unsigned int                STRAP_PIF_BIT_15 : 1;
		unsigned int                STRAP_PIF_BIT_16 : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_TX_CTRL__VI {
	struct {
		unsigned int                     TXPWR_IN_S2 : 3;
		unsigned int                TXPWR_IN_SPDCHNG : 3;
		unsigned int                    TXPWR_IN_OFF : 3;
		unsigned int                TXPWR_IN_DEGRADE : 3;
		unsigned int                 TXPWR_IN_UNUSED : 3;
		unsigned int                   TXPWR_IN_INIT : 3;
		unsigned int                TXPWR_IN_PLL_OFF : 3;
		unsigned int           TXPWR_IN_DEGRADE_MODE : 1;
		unsigned int            TXPWR_IN_UNUSED_MODE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_PIF_TX_CTRL2__VI {
	struct {
                unsigned int              TX_RDY_DASRT_COUNT : 3;
                unsigned int           TX_STATUS_DASRT_COUNT : 3;
                unsigned int               TXPHYSTATUS_DELAY : 3;
                unsigned int                                 : 7;
                unsigned int             TX_HIGH_IMP_STAG_MP : 1;
                unsigned int           TX_HIGH_IMP_STAG_MODE : 2;
                unsigned int                                 : 2;
                unsigned int             TX_FORCE_DATA_VALID : 1;
                unsigned int                TX_L0_TO_HIZ_DLY : 3;
                unsigned int           TX_FIFO_INIT_UPCONFIG : 1;
                unsigned int                TX_HIZ_TO_L0_DLY : 3;
                unsigned int          TX_LINKSPEED_ACK_IN_S2 : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_STRAP_GLB_REG1__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int         STRAP_RX_ADAPT_RST_MODE : 2;
                unsigned int          STRAP_RX_L0_ENTRY_MODE : 2;
                unsigned int              STRAP_RX_EI_FILTER : 2;
                unsigned int    STRAP_RX_ADAPT_RST_SUB_ENTRY : 1;
                unsigned int       STRAP_RX_PS0_RDY_GEN_MODE : 2;
                unsigned int    STRAP_RX_DLL_RESET_IN_SPDCHG : 1;
                unsigned int         STRAP_RX_ADAPT_TIME_OUT : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB0_STRAP_GLB_REG2__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int    STRAP_BPHYC_PLL_RAMP_UP_TIME : 3;
		unsigned int        STRAP_IMPCAL_SETTLE_TIME : 2;
		unsigned int            STRAP_BG_SETTLE_TIME : 2;
		unsigned int             STRAP_TX_CMDET_TIME : 2;
		unsigned int           STRAP_TX_STARTUP_TIME : 2;
		unsigned int                                 : 15;
		unsigned int                STRAP_B_PCB_DIS0 : 1;
		unsigned int                STRAP_B_PCB_DIS1 : 1;
		unsigned int             STRAP_B_PCB_DRV_STR : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_BIF_CMD_STATUS__VI {
	struct {
		unsigned int                   TXPHYSTATUS_0 : 1;
		unsigned int                   TXPHYSTATUS_1 : 1;
		unsigned int                   TXPHYSTATUS_2 : 1;
		unsigned int                   TXPHYSTATUS_3 : 1;
		unsigned int                   TXPHYSTATUS_4 : 1;
		unsigned int                   TXPHYSTATUS_5 : 1;
		unsigned int                   TXPHYSTATUS_6 : 1;
		unsigned int                   TXPHYSTATUS_7 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                   RXPHYSTATUS_0 : 1;
		unsigned int                   RXPHYSTATUS_1 : 1;
		unsigned int                   RXPHYSTATUS_2 : 1;
		unsigned int                   RXPHYSTATUS_3 : 1;
		unsigned int                   RXPHYSTATUS_4 : 1;
		unsigned int                   RXPHYSTATUS_5 : 1;
		unsigned int                   RXPHYSTATUS_6 : 1;
		unsigned int                   RXPHYSTATUS_7 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_CMD_BUS_CTRL__VI {
	struct {
                unsigned int               CMD_BUS_SCHL_MODE : 2;
                unsigned int               CMD_BUS_STAG_MODE : 2;
                unsigned int                CMD_BUS_STAG_DIS : 1;
                unsigned int            CMD_BUS_SCH_REQ_MODE : 2;
                unsigned int           CMD_BUS_IGNR_PEND_PWR : 1;
                unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_CMD_BUS_GLB_OVRD__VI {
	struct {
		unsigned int                  TXMARG_OVRD_EN : 1;
		unsigned int                  DEEMPH_OVRD_EN : 1;
		unsigned int                 PLLFREQ_OVRD_EN : 1;
		unsigned int                          TXMARG : 3;
		unsigned int                          DEEMPH : 1;
		unsigned int                         PLLFREQ : 2;
		unsigned int           RESPONSEMODE_PIF_OVRD : 1;
		unsigned int                                 : 6;
		unsigned int              CMD_BUS_LANE_DIS_0 : 1;
		unsigned int              CMD_BUS_LANE_DIS_1 : 1;
		unsigned int              CMD_BUS_LANE_DIS_2 : 1;
		unsigned int              CMD_BUS_LANE_DIS_3 : 1;
		unsigned int              CMD_BUS_LANE_DIS_4 : 1;
		unsigned int              CMD_BUS_LANE_DIS_5 : 1;
		unsigned int              CMD_BUS_LANE_DIS_6 : 1;
		unsigned int              CMD_BUS_LANE_DIS_7 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_CTRL__VI {
	struct {
                unsigned int                PIF_PLL_PWRDN_EN : 1;
                unsigned int            DTM_FORCE_FREQDIV_X1 : 1;
                unsigned int      PIF_PLL_HNDSHK_EARLY_ABORT : 1;
                unsigned int        PIF_PLL_PWRDN_EARLY_EXIT : 1;
                unsigned int               PHY_RST_PWROK_VDD : 1;
                unsigned int                                 : 1;
                unsigned int                  PIF_PLL_STATUS : 2;
                unsigned int        PIF_PLL_DEGRADE_OFF_VOTE : 1;
                unsigned int         PIF_PLL_UNUSED_OFF_VOTE : 1;
                unsigned int         PIF_PLL_DEGRADE_S2_VOTE : 1;
                unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_GLB_OVRD__VI {
	struct {
		unsigned int         RXDETECT_OVERRIDE_VAL_0 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_1 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_2 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_3 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_4 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_5 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_6 : 1;
		unsigned int         RXDETECT_OVERRIDE_VAL_7 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int            RXDETECT_OVERRIDE_EN : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_GLB_OVRD2__VI {
	struct {
		unsigned int                X2_LANE_1_0_OVRD : 1;
		unsigned int                X2_LANE_3_2_OVRD : 1;
		unsigned int                X2_LANE_5_4_OVRD : 1;
		unsigned int                X2_LANE_7_6_OVRD : 1;
		unsigned int                X2_LANE_9_8_OVRD : 1;
		unsigned int              X2_LANE_11_10_OVRD : 1;
		unsigned int              X2_LANE_13_12_OVRD : 1;
		unsigned int              X2_LANE_15_14_OVRD : 1;
		unsigned int                X4_LANE_3_0_OVRD : 1;
		unsigned int                X4_LANE_7_4_OVRD : 1;
		unsigned int               X4_LANE_11_8_OVRD : 1;
		unsigned int              X4_LANE_15_12_OVRD : 1;
		unsigned int                                 : 4;
		unsigned int                X8_LANE_7_0_OVRD : 1;
		unsigned int               X8_LANE_15_8_OVRD : 1;
		unsigned int                                 : 2;
		unsigned int              X16_LANE_15_0_OVRD : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE0_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_0 : 1;
		unsigned int               FREQDIV_OVRD_EN_0 : 1;
		unsigned int             LINKSPEED_OVRD_EN_0 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_0 : 1;
		unsigned int                 TXPWR_OVRD_EN_0 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_0 : 1;
		unsigned int                 RXPWR_OVRD_EN_0 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_0 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_0 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_0 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_0 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_0 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_0 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_0 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_0 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_0 : 1;
		unsigned int                 CDREN_OVRD_EN_0 : 1;
		unsigned int                CDREN_OVRD_VAL_0 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE0_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_0 : 3;
		unsigned int                       FREQDIV_0 : 2;
		unsigned int                     LINKSPEED_0 : 2;
		unsigned int                  TWOSYMENABLE_0 : 1;
		unsigned int                         TXPWR_0 : 3;
		unsigned int                    TXPGENABLE_0 : 2;
		unsigned int                         RXPWR_0 : 3;
		unsigned int                    RXPGENABLE_0 : 2;
		unsigned int                 ELECIDLEDETEN_0 : 1;
		unsigned int                     ENABLEFOM_0 : 1;
		unsigned int                    REQUESTFOM_0 : 1;
		unsigned int                  RESPONSEMODE_0 : 1;
		unsigned int                    REQUESTTRK_0 : 1;
		unsigned int                    REQUESTTRN_0 : 1;
		unsigned int                 COEFFICIENTID_0 : 2;
		unsigned int                   COEFFICIENT_0 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE1_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_1 : 1;
		unsigned int               FREQDIV_OVRD_EN_1 : 1;
		unsigned int             LINKSPEED_OVRD_EN_1 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_1 : 1;
		unsigned int                 TXPWR_OVRD_EN_1 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_1 : 1;
		unsigned int                 RXPWR_OVRD_EN_1 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_1 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_1 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_1 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_1 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_1 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_1 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_1 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_1 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_1 : 1;
		unsigned int                 CDREN_OVRD_EN_1 : 1;
		unsigned int                CDREN_OVRD_VAL_1 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE1_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_1 : 3;
		unsigned int                       FREQDIV_1 : 2;
		unsigned int                     LINKSPEED_1 : 2;
		unsigned int                  TWOSYMENABLE_1 : 1;
		unsigned int                         TXPWR_1 : 3;
		unsigned int                    TXPGENABLE_1 : 2;
		unsigned int                         RXPWR_1 : 3;
		unsigned int                    RXPGENABLE_1 : 2;
		unsigned int                 ELECIDLEDETEN_1 : 1;
		unsigned int                     ENABLEFOM_1 : 1;
		unsigned int                    REQUESTFOM_1 : 1;
		unsigned int                  RESPONSEMODE_1 : 1;
		unsigned int                    REQUESTTRK_1 : 1;
		unsigned int                    REQUESTTRN_1 : 1;
		unsigned int                 COEFFICIENTID_1 : 2;
		unsigned int                   COEFFICIENT_1 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE2_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_2 : 1;
		unsigned int               FREQDIV_OVRD_EN_2 : 1;
		unsigned int             LINKSPEED_OVRD_EN_2 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_2 : 1;
		unsigned int                 TXPWR_OVRD_EN_2 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_2 : 1;
		unsigned int                 RXPWR_OVRD_EN_2 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_2 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_2 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_2 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_2 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_2 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_2 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_2 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_2 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_2 : 1;
		unsigned int                 CDREN_OVRD_EN_2 : 1;
		unsigned int                CDREN_OVRD_VAL_2 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE2_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_2 : 3;
		unsigned int                       FREQDIV_2 : 2;
		unsigned int                     LINKSPEED_2 : 2;
		unsigned int                  TWOSYMENABLE_2 : 1;
		unsigned int                         TXPWR_2 : 3;
		unsigned int                    TXPGENABLE_2 : 2;
		unsigned int                         RXPWR_2 : 3;
		unsigned int                    RXPGENABLE_2 : 2;
		unsigned int                 ELECIDLEDETEN_2 : 1;
		unsigned int                     ENABLEFOM_2 : 1;
		unsigned int                    REQUESTFOM_2 : 1;
		unsigned int                  RESPONSEMODE_2 : 1;
		unsigned int                    REQUESTTRK_2 : 1;
		unsigned int                    REQUESTTRN_2 : 1;
		unsigned int                 COEFFICIENTID_2 : 2;
		unsigned int                   COEFFICIENT_2 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE3_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_3 : 1;
		unsigned int               FREQDIV_OVRD_EN_3 : 1;
		unsigned int             LINKSPEED_OVRD_EN_3 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_3 : 1;
		unsigned int                 TXPWR_OVRD_EN_3 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_3 : 1;
		unsigned int                 RXPWR_OVRD_EN_3 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_3 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_3 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_3 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_3 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_3 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_3 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_3 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_3 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_3 : 1;
		unsigned int                 CDREN_OVRD_EN_3 : 1;
		unsigned int                CDREN_OVRD_VAL_3 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE3_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_3 : 3;
		unsigned int                       FREQDIV_3 : 2;
		unsigned int                     LINKSPEED_3 : 2;
		unsigned int                  TWOSYMENABLE_3 : 1;
		unsigned int                         TXPWR_3 : 3;
		unsigned int                    TXPGENABLE_3 : 2;
		unsigned int                         RXPWR_3 : 3;
		unsigned int                    RXPGENABLE_3 : 2;
		unsigned int                 ELECIDLEDETEN_3 : 1;
		unsigned int                     ENABLEFOM_3 : 1;
		unsigned int                    REQUESTFOM_3 : 1;
		unsigned int                  RESPONSEMODE_3 : 1;
		unsigned int                    REQUESTTRK_3 : 1;
		unsigned int                    REQUESTTRN_3 : 1;
		unsigned int                 COEFFICIENTID_3 : 2;
		unsigned int                   COEFFICIENT_3 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE4_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_4 : 1;
		unsigned int               FREQDIV_OVRD_EN_4 : 1;
		unsigned int             LINKSPEED_OVRD_EN_4 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_4 : 1;
		unsigned int                 TXPWR_OVRD_EN_4 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_4 : 1;
		unsigned int                 RXPWR_OVRD_EN_4 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_4 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_4 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_4 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_4 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_4 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_4 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_4 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_4 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_4 : 1;
		unsigned int                 CDREN_OVRD_EN_4 : 1;
		unsigned int                CDREN_OVRD_VAL_4 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE4_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_4 : 3;
		unsigned int                       FREQDIV_4 : 2;
		unsigned int                     LINKSPEED_4 : 2;
		unsigned int                  TWOSYMENABLE_4 : 1;
		unsigned int                         TXPWR_4 : 3;
		unsigned int                    TXPGENABLE_4 : 2;
		unsigned int                         RXPWR_4 : 3;
		unsigned int                    RXPGENABLE_4 : 2;
		unsigned int                 ELECIDLEDETEN_4 : 1;
		unsigned int                     ENABLEFOM_4 : 1;
		unsigned int                    REQUESTFOM_4 : 1;
		unsigned int                  RESPONSEMODE_4 : 1;
		unsigned int                    REQUESTTRK_4 : 1;
		unsigned int                    REQUESTTRN_4 : 1;
		unsigned int                 COEFFICIENTID_4 : 2;
		unsigned int                   COEFFICIENT_4 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE5_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_5 : 1;
		unsigned int               FREQDIV_OVRD_EN_5 : 1;
		unsigned int             LINKSPEED_OVRD_EN_5 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_5 : 1;
		unsigned int                 TXPWR_OVRD_EN_5 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_5 : 1;
		unsigned int                 RXPWR_OVRD_EN_5 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_5 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_5 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_5 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_5 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_5 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_5 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_5 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_5 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_5 : 1;
		unsigned int                 CDREN_OVRD_EN_5 : 1;
		unsigned int                CDREN_OVRD_VAL_5 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE5_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_5 : 3;
		unsigned int                       FREQDIV_5 : 2;
		unsigned int                     LINKSPEED_5 : 2;
		unsigned int                  TWOSYMENABLE_5 : 1;
		unsigned int                         TXPWR_5 : 3;
		unsigned int                    TXPGENABLE_5 : 2;
		unsigned int                         RXPWR_5 : 3;
		unsigned int                    RXPGENABLE_5 : 2;
		unsigned int                 ELECIDLEDETEN_5 : 1;
		unsigned int                     ENABLEFOM_5 : 1;
		unsigned int                    REQUESTFOM_5 : 1;
		unsigned int                  RESPONSEMODE_5 : 1;
		unsigned int                    REQUESTTRK_5 : 1;
		unsigned int                    REQUESTTRN_5 : 1;
		unsigned int                 COEFFICIENTID_5 : 2;
		unsigned int                   COEFFICIENT_5 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE6_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_6 : 1;
		unsigned int               FREQDIV_OVRD_EN_6 : 1;
		unsigned int             LINKSPEED_OVRD_EN_6 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_6 : 1;
		unsigned int                 TXPWR_OVRD_EN_6 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_6 : 1;
		unsigned int                 RXPWR_OVRD_EN_6 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_6 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_6 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_6 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_6 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_6 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_6 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_6 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_6 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_6 : 1;
		unsigned int                 CDREN_OVRD_EN_6 : 1;
		unsigned int                CDREN_OVRD_VAL_6 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE6_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_6 : 3;
		unsigned int                       FREQDIV_6 : 2;
		unsigned int                     LINKSPEED_6 : 2;
		unsigned int                  TWOSYMENABLE_6 : 1;
		unsigned int                         TXPWR_6 : 3;
		unsigned int                    TXPGENABLE_6 : 2;
		unsigned int                         RXPWR_6 : 3;
		unsigned int                    RXPGENABLE_6 : 2;
		unsigned int                 ELECIDLEDETEN_6 : 1;
		unsigned int                     ENABLEFOM_6 : 1;
		unsigned int                    REQUESTFOM_6 : 1;
		unsigned int                  RESPONSEMODE_6 : 1;
		unsigned int                    REQUESTTRK_6 : 1;
		unsigned int                    REQUESTTRN_6 : 1;
		unsigned int                 COEFFICIENTID_6 : 2;
		unsigned int                   COEFFICIENT_6 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE7_OVRD__VI {
	struct {
		unsigned int              GANGMODE_OVRD_EN_7 : 1;
		unsigned int               FREQDIV_OVRD_EN_7 : 1;
		unsigned int             LINKSPEED_OVRD_EN_7 : 1;
		unsigned int          TWOSYMENABLE_OVRD_EN_7 : 1;
		unsigned int                 TXPWR_OVRD_EN_7 : 1;
		unsigned int            TXPGENABLE_OVRD_EN_7 : 1;
		unsigned int                 RXPWR_OVRD_EN_7 : 1;
		unsigned int            RXPGENABLE_OVRD_EN_7 : 1;
		unsigned int         ELECIDLEDETEN_OVRD_EN_7 : 1;
		unsigned int             ENABLEFOM_OVRD_EN_7 : 1;
		unsigned int            REQUESTFOM_OVRD_EN_7 : 1;
		unsigned int          RESPONSEMODE_OVRD_EN_7 : 1;
		unsigned int            REQUESTTRK_OVRD_EN_7 : 1;
		unsigned int            REQUESTTRN_OVRD_EN_7 : 1;
		unsigned int         COEFFICIENTID_OVRD_EN_7 : 1;
		unsigned int           COEFFICIENT_OVRD_EN_7 : 1;
		unsigned int                 CDREN_OVRD_EN_7 : 1;
		unsigned int                CDREN_OVRD_VAL_7 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_LANE7_OVRD2__VI {
	struct {
		unsigned int                      GANGMODE_7 : 3;
		unsigned int                       FREQDIV_7 : 2;
		unsigned int                     LINKSPEED_7 : 2;
		unsigned int                  TWOSYMENABLE_7 : 1;
		unsigned int                         TXPWR_7 : 3;
		unsigned int                    TXPGENABLE_7 : 2;
		unsigned int                         RXPWR_7 : 3;
		unsigned int                    RXPGENABLE_7 : 2;
		unsigned int                 ELECIDLEDETEN_7 : 1;
		unsigned int                     ENABLEFOM_7 : 1;
		unsigned int                    REQUESTFOM_7 : 1;
		unsigned int                  RESPONSEMODE_7 : 1;
		unsigned int                    REQUESTTRK_7 : 1;
		unsigned int                    REQUESTTRN_7 : 1;
		unsigned int                 COEFFICIENTID_7 : 2;
		unsigned int                   COEFFICIENT_7 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_RX_CTRL__VI {
	struct {
                unsigned int                     RXPWR_IN_S2 : 3;
                unsigned int                RXPWR_IN_SPDCHNG : 3;
                unsigned int                    RXPWR_IN_OFF : 3;
                unsigned int                RXPWR_IN_DEGRADE : 3;
                unsigned int                 RXPWR_IN_UNUSED : 3;
                unsigned int                   RXPWR_IN_INIT : 3;
                unsigned int                RXPWR_IN_PLL_OFF : 3;
                unsigned int           RXPWR_IN_DEGRADE_MODE : 1;
                unsigned int            RXPWR_IN_UNUSED_MODE : 1;
                unsigned int              RXPWR_GATING_IN_L1 : 1;
                unsigned int          RXPWR_GATING_IN_UNUSED : 1;
                unsigned int                RX_HLD_EIE_COUNT : 1;
                unsigned int        RX_EI_DET_IN_PS2_DEGRADE : 1;
                unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_RX_CTRL2__VI {
	struct {
		unsigned int              RX_RDY_DASRT_COUNT : 3;
		unsigned int           RX_STATUS_DASRT_COUNT : 3;
		unsigned int               RXPHYSTATUS_DELAY : 3;
		unsigned int                                 : 7;
		unsigned int              FORCE_CDREN_IN_L0S : 1;
		unsigned int               EI_DET_CYCLE_MODE : 2;
		unsigned int                  EI_DET_ON_TIME : 2;
		unsigned int                 EI_DET_OFF_TIME : 3;
		unsigned int         EI_DET_CYCLE_DIS_IN_PS1 : 1;
		unsigned int                RX_CDR_XTND_MODE : 2;
		unsigned int          RX_L0S_TO_L0_DETECT_EI : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_STRAP_0__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int           STRAP_TX_RDY_XTND_DIS : 1;
		unsigned int           STRAP_RX_RDY_XTND_DIS : 1;
		unsigned int        STRAP_TX_STATUS_XTND_DIS : 1;
		unsigned int        STRAP_RX_STATUS_XTND_DIS : 1;
		unsigned int            STRAP_FORCE_OWN_MSTR : 1;
		unsigned int           STRAP_PIF_CDR_EN_MODE : 2;
		unsigned int              STRAP_RX_EI_FILTER : 2;
		unsigned int     STRAP_RX_DIS_HLD_EIE_IN_PS1 : 1;
		unsigned int     STRAP_RX_DIS_HLD_EIE_IN_PS2 : 1;
		unsigned int                STRAP_PIF_BIT_12 : 1;
		unsigned int                STRAP_PIF_BIT_13 : 1;
		unsigned int                STRAP_PIF_BIT_14 : 1;
		unsigned int                STRAP_PIF_BIT_15 : 1;
		unsigned int                STRAP_PIF_BIT_16 : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_TX_CTRL__VI {
	struct {
		unsigned int                     TXPWR_IN_S2 : 3;
		unsigned int                TXPWR_IN_SPDCHNG : 3;
		unsigned int                    TXPWR_IN_OFF : 3;
		unsigned int                TXPWR_IN_DEGRADE : 3;
		unsigned int                 TXPWR_IN_UNUSED : 3;
		unsigned int                   TXPWR_IN_INIT : 3;
		unsigned int                TXPWR_IN_PLL_OFF : 3;
		unsigned int           TXPWR_IN_DEGRADE_MODE : 1;
		unsigned int            TXPWR_IN_UNUSED_MODE : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_PIF_TX_CTRL2__VI {
	struct {
                unsigned int              TX_RDY_DASRT_COUNT : 3;
                unsigned int           TX_STATUS_DASRT_COUNT : 3;
                unsigned int               TXPHYSTATUS_DELAY : 3;
                unsigned int                                 : 7;
                unsigned int             TX_HIGH_IMP_STAG_MP : 1;
                unsigned int           TX_HIGH_IMP_STAG_MODE : 2;
                unsigned int                                 : 2;
                unsigned int             TX_FORCE_DATA_VALID : 1;
                unsigned int                TX_L0_TO_HIZ_DLY : 3;
                unsigned int           TX_FIFO_INIT_UPCONFIG : 1;
                unsigned int                TX_HIZ_TO_L0_DLY : 3;
                unsigned int          TX_LINKSPEED_ACK_IN_S2 : 1;
                unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_STRAP_GLB_REG1__VI {
	struct {
                unsigned int                                 : 1;
                unsigned int         STRAP_RX_ADAPT_RST_MODE : 2;
                unsigned int          STRAP_RX_L0_ENTRY_MODE : 2;
                unsigned int              STRAP_RX_EI_FILTER : 2;
                unsigned int    STRAP_RX_ADAPT_RST_SUB_ENTRY : 1;
                unsigned int       STRAP_RX_PS0_RDY_GEN_MODE : 2;
                unsigned int    STRAP_RX_DLL_RESET_IN_SPDCHG : 1;
                unsigned int         STRAP_RX_ADAPT_TIME_OUT : 2;
                unsigned int                                 : 1;
                unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PB1_STRAP_GLB_REG2__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int    STRAP_BPHYC_PLL_RAMP_UP_TIME : 3;
		unsigned int        STRAP_IMPCAL_SETTLE_TIME : 2;
		unsigned int            STRAP_BG_SETTLE_TIME : 2;
		unsigned int             STRAP_TX_CMDET_TIME : 2;
		unsigned int           STRAP_TX_STARTUP_TIME : 2;
		unsigned int                                 : 15;
		unsigned int                STRAP_B_PCB_DIS0 : 1;
		unsigned int                STRAP_B_PCB_DIS1 : 1;
		unsigned int             STRAP_B_PCB_DRV_STR : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_ERROR_INJECT_PHYSICAL__VI {
	struct {
		unsigned int        ERROR_INJECT_PL_LANE_ERR : 2;
		unsigned int     ERROR_INJECT_PL_FRAMING_ERR : 2;
		unsigned int ERROR_INJECT_PL_BAD_PARITY_IN_SKP : 2;
		unsigned int ERROR_INJECT_PL_BAD_LFSR_IN_SKP : 2;
		unsigned int  ERROR_INJECT_PL_LOOPBACK_UFLOW : 2;
		unsigned int  ERROR_INJECT_PL_LOOPBACK_OFLOW : 2;
		unsigned int      ERROR_INJECT_PL_DESKEW_ERR : 2;
		unsigned int ERROR_INJECT_PL_8B10B_DISPARITY_ERR : 2;
		unsigned int ERROR_INJECT_PL_8B10B_DECODE_ERR : 2;
		unsigned int    ERROR_INJECT_PL_SKP_OS_ERROR : 2;
		unsigned int ERROR_INJECT_PL_INV_OS_IDENTIFIER : 2;
		unsigned int ERROR_INJECT_PL_BAD_SYNC_HEADER : 2;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_ERROR_INJECT_TRANSACTION__VI {
	struct {
		unsigned int    ERROR_INJECT_TL_FLOW_CTL_ERR : 2;
		unsigned int ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER : 2;
		unsigned int        ERROR_INJECT_TL_BAD_DLLP : 2;
		unsigned int         ERROR_INJECT_TL_BAD_TLP : 2;
		unsigned int ERROR_INJECT_TL_UNSUPPORTED_REQ : 2;
		unsigned int      ERROR_INJECT_TL_ECRC_ERROR : 2;
		unsigned int   ERROR_INJECT_TL_MALFORMED_TLP : 2;
		unsigned int ERROR_INJECT_TL_UNEXPECTED_CMPLT : 2;
		unsigned int ERROR_INJECT_TL_COMPLETER_ABORT : 2;
		unsigned int ERROR_INJECT_TL_COMPLETION_TIMEOUT : 2;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIEP_SRIOV_PRIV_CTRL__VI {
	struct {
                unsigned int        RX_SRIOV_VF_MAPPING_MODE : 2;
                unsigned int  SRIOV_SAVE_VFS_ON_VFENABLE_CLR : 2;
                unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ARI_CAP__VI {
	struct {
		unsigned int        ARI_MFVC_FUNC_GROUPS_CAP : 1;
		unsigned int         ARI_ACS_FUNC_GROUPS_CAP : 1;
		unsigned int                                 : 6;
		unsigned int               ARI_NEXT_FUNC_NUM : 8;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ARI_CNTL__VI {
	struct {
		unsigned int         ARI_MFVC_FUNC_GROUPS_EN : 1;
		unsigned int          ARI_ACS_FUNC_GROUPS_EN : 1;
		unsigned int                                 : 2;
		unsigned int              ARI_FUNCTION_GROUP : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_ARI_ENH_CAP_LIST__VI {
	struct {
		unsigned int                          CAP_ID : 16;
		unsigned int                         CAP_VER : 4;
		unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_EFUSE__VI {
	struct {
		unsigned int                      PCIE_EFUSE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_EFUSE2__VI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_EFUSE3__VI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_EFUSE4__VI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_EFUSE5__VI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_EFUSE6__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int STRAP_BIF_F0_SUPPORTED_PAGE_SIZES : 16;
		unsigned int              SPARE_15_PCIEFUSE6 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_EFUSE7__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int STRAP_BIF_F0_SRIOV_VF_DEVICE_ID : 16;
		unsigned int              SPARE_15_PCIEFUSE7 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_HOLD_TRAINING_A__VI {
	struct {
		unsigned int                 HOLD_TRAINING_A : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_BEST_EQ_SETTINGS__VI {
	struct {
		unsigned int                  LC_BEST_PRESET : 4;
		unsigned int               LC_BEST_PRECURSOR : 6;
		unsigned int                  LC_BEST_CURSOR : 6;
		unsigned int              LC_BEST_POSTCURSOR : 6;
		unsigned int                     LC_BEST_FOM : 8;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_CNTL6__VI {
	struct {
		unsigned int               LC_SPC_MODE_2P5GT : 1;
		unsigned int                                 : 1;
		unsigned int                 LC_SPC_MODE_5GT : 1;
		unsigned int                                 : 1;
		unsigned int                 LC_SPC_MODE_8GT : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LC_FORCE_EQ_REQ_COEFF__VI {
	struct {
		unsigned int  LC_FORCE_COEFF_IN_EQ_REQ_PHASE : 1;
		unsigned int         LC_FORCE_PRE_CURSOR_REQ : 6;
		unsigned int             LC_FORCE_CURSOR_REQ : 6;
		unsigned int        LC_FORCE_POST_CURSOR_REQ : 6;
		unsigned int                 LC_FS_OTHER_END : 6;
		unsigned int                 LC_LF_OTHER_END : 6;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LTR_CAP__VI {
	struct {
		unsigned int         LTR_MAX_S_LATENCY_VALUE : 10;
		unsigned int         LTR_MAX_S_LATENCY_SCALE : 3;
		unsigned int                                 : 3;
		unsigned int        LTR_MAX_NS_LATENCY_VALUE : 10;
		unsigned int        LTR_MAX_NS_LATENCY_SCALE : 3;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_LTR_ENH_CAP_LIST__VI {
	struct {
		unsigned int                          CAP_ID : 16;
		unsigned int                         CAP_VER : 4;
		unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_ADDR0__VI {
	struct {
		unsigned int                    MC_INDEX_POS : 6;
		unsigned int                                 : 6;
		unsigned int                  MC_BASE_ADDR_0 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_ADDR1__VI {
	struct {
		unsigned int                  MC_BASE_ADDR_1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_BLOCK_ALL0__VI {
	struct {
		unsigned int                  MC_BLOCK_ALL_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_BLOCK_ALL1__VI {
	struct {
		unsigned int                  MC_BLOCK_ALL_1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_BLOCK_UNTRANSLATED_0__VI {
	struct {
		unsigned int         MC_BLOCK_UNTRANSLATED_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_BLOCK_UNTRANSLATED_1__VI {
	struct {
		unsigned int         MC_BLOCK_UNTRANSLATED_1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_CAP__VI {
	struct {
		unsigned int                    MC_MAX_GROUP : 6;
		unsigned int                                 : 2;
		unsigned int                 MC_WIN_SIZE_REQ : 6;
		unsigned int                                 : 1;
		unsigned int              MC_ECRC_REGEN_SUPP : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_CNTL__VI {
	struct {
		unsigned int                    MC_NUM_GROUP : 6;
		unsigned int                                 : 9;
		unsigned int                       MC_ENABLE : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_ENH_CAP_LIST__VI {
	struct {
		unsigned int                          CAP_ID : 16;
		unsigned int                         CAP_VER : 4;
		unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_RCV0__VI {
	struct {
		unsigned int                    MC_RECEIVE_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_MC_RCV1__VI {
	struct {
		unsigned int                    MC_RECEIVE_1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_OBFF_CNTL__VI {
	struct {
		unsigned int            TX_OBFF_PRIV_DISABLE : 1;
		unsigned int     TX_OBFF_WAKE_SIMPLE_MODE_EN : 1;
		unsigned int       TX_OBFF_HOSTMEM_TO_ACTIVE : 1;
		unsigned int        TX_OBFF_SLVCPL_TO_ACTIVE : 1;
		unsigned int    TX_OBFF_WAKE_MAX_PULSE_WIDTH : 4;
		unsigned int TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH : 4;
		unsigned int    TX_OBFF_WAKE_SAMPLING_PERIOD : 4;
		unsigned int          TX_OBFF_INTR_TO_ACTIVE : 1;
		unsigned int           TX_OBFF_ERR_TO_ACTIVE : 1;
		unsigned int       TX_OBFF_ANY_MSG_TO_ACTIVE : 1;
		unsigned int         TX_OBFF_ACCEPT_IN_NOND0 : 1;
		unsigned int   TX_OBFF_PENDING_REQ_TO_ACTIVE : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_RXDET_OVERRIDE__VI {
	struct {
		unsigned int                     RxDetOvrVal : 16;
		unsigned int                      RxDetOvrEn : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_CAP__VI {
	struct {
		unsigned int          SRIOV_VF_MIGRATION_CAP : 1;
		unsigned int SRIOV_ARI_CAP_HIERARCHY_PRESERVED : 1;
		unsigned int                                 : 19;
		unsigned int SRIOV_VF_MIGRATION_INTR_MSG_NUM : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_CONTROL__VI {
	struct {
		unsigned int                 SRIOV_VF_ENABLE : 1;
		unsigned int       SRIOV_VF_MIGRATION_ENABLE : 1;
		unsigned int  SRIOV_VF_MIGRATION_INTR_ENABLE : 1;
		unsigned int                    SRIOV_VF_MSE : 1;
		unsigned int         SRIOV_ARI_CAP_HIERARCHY : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_ENH_CAP_LIST__VI {
	struct {
		unsigned int                          CAP_ID : 16;
		unsigned int                         CAP_VER : 4;
		unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_FIRST_VF_OFFSET__VI {
	struct {
		unsigned int           SRIOV_FIRST_VF_OFFSET : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_FUNC_DEP_LINK__VI {
	struct {
		unsigned int             SRIOV_FUNC_DEP_LINK : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_INITIAL_VFS__VI {
	struct {
		unsigned int               SRIOV_INITIAL_VFS : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_NUM_VFS__VI {
	struct {
		unsigned int                   SRIOV_NUM_VFS : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_STATUS__VI {
	struct {
		unsigned int       SRIOV_VF_MIGRATION_STATUS : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI {
	struct {
		unsigned int       SRIOV_SUPPORTED_PAGE_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_SYSTEM_PAGE_SIZE__VI {
	struct {
		unsigned int          SRIOV_SYSTEM_PAGE_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_TOTAL_VFS__VI {
	struct {
		unsigned int                 SRIOV_TOTAL_VFS : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_VF_BASE_ADDR_0__VI {
	struct {
		unsigned int                    VF_BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_VF_BASE_ADDR_1__VI {
	struct {
		unsigned int                    VF_BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_VF_BASE_ADDR_2__VI {
	struct {
		unsigned int                    VF_BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_VF_BASE_ADDR_3__VI {
	struct {
		unsigned int                    VF_BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_VF_BASE_ADDR_4__VI {
	struct {
		unsigned int                    VF_BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_VF_BASE_ADDR_5__VI {
	struct {
		unsigned int                    VF_BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_VF_DEVICE_ID__VI {
	struct {
		unsigned int              SRIOV_VF_DEVICE_ID : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI {
	struct {
		unsigned int SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_SRIOV_VF_STRIDE__VI {
	struct {
		unsigned int                 SRIOV_VF_STRIDE : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TPH_REQR_CAP__VI {
	struct {
		unsigned int   TPH_REQR_NO_ST_MODE_SUPPORTED : 1;
		unsigned int TPH_REQR_INT_VEC_MODE_SUPPORTED : 1;
		unsigned int TPH_REQR_DEV_SPC_MODE_SUPPORTED : 1;
		unsigned int                                 : 5;
		unsigned int TPH_REQR_EXTND_TPH_REQR_SUPPORED : 1;
		unsigned int      TPH_REQR_ST_TABLE_LOCATION : 2;
		unsigned int                                 : 5;
		unsigned int          TPH_REQR_ST_TABLE_SIZE : 11;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TPH_REQR_CNTL__VI {
	struct {
		unsigned int            TPH_REQR_ST_MODE_SEL : 3;
		unsigned int                                 : 5;
		unsigned int                     TPH_REQR_EN : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TPH_REQR_ENH_CAP_LIST__VI {
	struct {
		unsigned int                          CAP_ID : 16;
		unsigned int                         CAP_VER : 4;
		unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_TX_LTR_CNTL__VI {
	struct {
		unsigned int          LTR_PRIV_S_SHORT_VALUE : 3;
		unsigned int           LTR_PRIV_S_LONG_VALUE : 3;
		unsigned int          LTR_PRIV_S_REQUIREMENT : 1;
		unsigned int         LTR_PRIV_NS_SHORT_VALUE : 3;
		unsigned int          LTR_PRIV_NS_LONG_VALUE : 3;
		unsigned int         LTR_PRIV_NS_REQUIREMENT : 1;
		unsigned int   LTR_PRIV_MSG_DIS_IN_PM_NON_D0 : 1;
		unsigned int     LTR_PRIV_RST_LTR_IN_DL_DOWN : 1;
		unsigned int                TX_CHK_FC_FOR_L1 : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI {
	struct {
		unsigned int                          CAP_ID : 16;
		unsigned int                         CAP_VER : 4;
		unsigned int                        NEXT_PTR : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI {
	struct {
		unsigned int                         VSEC_ID : 16;
		unsigned int                        VSEC_REV : 4;
		unsigned int                     VSEC_LENGTH : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI {
	struct {
		unsigned int                     SOFT_PF_FLR : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_WRAP_DTM_MISC__VI {
	struct {
		unsigned int    DTM_BULKPHY_FREQDIV_OVERRIDE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_WRAP_MISC__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int  STRAP_BIF_HOLD_TRAINING_STICKY : 1;
		unsigned int        STRAP_BIF_QUICKSIM_START : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_WRAP_PIF_MISC__VI {
	struct {
		unsigned int                DTM_PIF_DELAY_FI : 3;
		unsigned int                                 : 1;
		unsigned int                DTM_PIF_DELAY_DI : 3;
		unsigned int                DTM_PIF_ATSEL_FI : 1;
		unsigned int                DTM_PIF_ATSEL_DI : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_WRAP_REG_TARG_MISC__VI {
	struct {
		unsigned int                      CLKEN_MASK : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_WRAP_SCRATCH1__VI {
	struct {
		unsigned int              PCIE_WRAP_SCRATCH1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_WRAP_SCRATCH2__VI {
	struct {
		unsigned int              PCIE_WRAP_SCRATCH2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PCIE_WRAP_TURNAROUND_DAISYCHAIN__VI {
	struct {
		unsigned int END_BIFCORE_REGISTER_DAISYCHAIN : 1;
		unsigned int END_WRAPPER_REGISTER_DAISYCHAIN : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PERFCOUNTER_CNTL__VI {
	struct {
		unsigned int           PERFCOUNTER_EVENT_SEL : 9;
		unsigned int          PERFCOUNTER_CVALUE_SEL : 3;
		unsigned int            PERFCOUNTER_INC_MODE : 2;
		unsigned int         PERFCOUNTER_HW_CNTL_SEL : 1;
		unsigned int          PERFCOUNTER_RUNEN_MODE : 1;
		unsigned int          PERFCOUNTER_CNTOFF_SEL : 5;
		unsigned int    PERFCOUNTER_CNTOFF_START_DIS : 1;
		unsigned int          PERFCOUNTER_RESTART_EN : 1;
		unsigned int              PERFCOUNTER_INT_EN : 1;
		unsigned int            PERFCOUNTER_OFF_MASK : 1;
		unsigned int              PERFCOUNTER_ACTIVE : 1;
		unsigned int            PERFCOUNTER_INT_TYPE : 1;
		unsigned int  PERFCOUNTER_COUNTED_VALUE_TYPE : 1;
		unsigned int                                 : 1;
		unsigned int            PERFCOUNTER_CNTL_SEL : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PERFCOUNTER_STATE__VI {
	struct {
		unsigned int          PERFCOUNTER_CNT0_STATE : 2;
		unsigned int          PERFCOUNTER_STATE_SEL0 : 1;
		unsigned int                                 : 1;
		unsigned int          PERFCOUNTER_CNT1_STATE : 2;
		unsigned int          PERFCOUNTER_STATE_SEL1 : 1;
		unsigned int                                 : 1;
		unsigned int          PERFCOUNTER_CNT2_STATE : 2;
		unsigned int          PERFCOUNTER_STATE_SEL2 : 1;
		unsigned int                                 : 1;
		unsigned int          PERFCOUNTER_CNT3_STATE : 2;
		unsigned int          PERFCOUNTER_STATE_SEL3 : 1;
		unsigned int                                 : 1;
		unsigned int          PERFCOUNTER_CNT4_STATE : 2;
		unsigned int          PERFCOUNTER_STATE_SEL4 : 1;
		unsigned int                                 : 1;
		unsigned int          PERFCOUNTER_CNT5_STATE : 2;
		unsigned int          PERFCOUNTER_STATE_SEL5 : 1;
		unsigned int                                 : 1;
		unsigned int          PERFCOUNTER_CNT6_STATE : 2;
		unsigned int          PERFCOUNTER_STATE_SEL6 : 1;
		unsigned int                                 : 1;
		unsigned int          PERFCOUNTER_CNT7_STATE : 2;
		unsigned int          PERFCOUNTER_STATE_SEL7 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PERFMON_CNTL__VI {
	struct {
		unsigned int                   PERFMON_STATE : 2;
		unsigned int          PERFMON_RUN_ENABLE_SEL : 6;
		unsigned int               PERFMON_RPT_COUNT : 20;
		unsigned int           PERFMON_CNTOFF_AND_OR : 1;
		unsigned int           PERFMON_CNTOFF_INT_EN : 1;
		unsigned int       PERFMON_CNTOFF_INT_STATUS : 1;
		unsigned int          PERFMON_CNTOFF_INT_ACK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PERFMON_CNTL2__VI {
	struct {
		unsigned int         PERFMON_CNTOFF_INT_TYPE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PERFMON_CVALUE_INT_MISC__VI {
	struct {
		unsigned int         PERFCOUNTER_INT0_STATUS : 1;
		unsigned int         PERFCOUNTER_INT1_STATUS : 1;
		unsigned int         PERFCOUNTER_INT2_STATUS : 1;
		unsigned int         PERFCOUNTER_INT3_STATUS : 1;
		unsigned int         PERFCOUNTER_INT4_STATUS : 1;
		unsigned int         PERFCOUNTER_INT5_STATUS : 1;
		unsigned int         PERFCOUNTER_INT6_STATUS : 1;
		unsigned int         PERFCOUNTER_INT7_STATUS : 1;
		unsigned int            PERFCOUNTER_INT0_ACK : 1;
		unsigned int            PERFCOUNTER_INT1_ACK : 1;
		unsigned int            PERFCOUNTER_INT2_ACK : 1;
		unsigned int            PERFCOUNTER_INT3_ACK : 1;
		unsigned int            PERFCOUNTER_INT4_ACK : 1;
		unsigned int            PERFCOUNTER_INT5_ACK : 1;
		unsigned int            PERFCOUNTER_INT6_ACK : 1;
		unsigned int            PERFCOUNTER_INT7_ACK : 1;
		unsigned int               PERFMON_CVALUE_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PERFMON_CVALUE_LOW__VI {
	struct {
		unsigned int              PERFMON_CVALUE_LOW : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PERFMON_HI__VI {
	struct {
		unsigned int                      PERFMON_HI : 16;
		unsigned int                                 : 13;
		unsigned int                PERFMON_READ_SEL : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PERFMON_LOW__VI {
	struct {
		unsigned int                     PERFMON_LOW : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PERFMON_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int         PERFMON_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PERFMON_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int        PERFMON_TEST_DEBUG_INDEX : 8;
		unsigned int     PERFMON_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE0_DMIF_BUFFER_CONTROL__VI {
	struct {
		unsigned int          DMIF_BUFFERS_ALLOCATED : 3;
		unsigned int                                 : 1;
		unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE0_MAX_REQUESTS__VI {
	struct {
		unsigned int                    MAX_REQUESTS : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE0_PG_CONFIG__VI {
	struct {
		unsigned int             PIPE0_POWER_FORCEON : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE0_PG_ENABLE__VI {
	struct {
		unsigned int                PIPE0_POWER_GATE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE0_PG_STATUS__VI {
	struct {
		unsigned int           PIPE0_PGFSM_READ_DATA : 24;
		unsigned int          PIPE0_DEBUG_PWR_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int         PIPE0_DESIRED_PWR_STATE : 1;
		unsigned int       PIPE0_REQUESTED_PWR_STATE : 1;
		unsigned int          PIPE0_PGFSM_PWR_STATUS : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE1_DMIF_BUFFER_CONTROL__VI {
	struct {
		unsigned int          DMIF_BUFFERS_ALLOCATED : 3;
		unsigned int                                 : 1;
		unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE1_MAX_REQUESTS__VI {
	struct {
		unsigned int                    MAX_REQUESTS : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE1_PG_CONFIG__VI {
	struct {
		unsigned int             PIPE1_POWER_FORCEON : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE1_PG_ENABLE__VI {
	struct {
		unsigned int                PIPE1_POWER_GATE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE1_PG_STATUS__VI {
	struct {
		unsigned int           PIPE1_PGFSM_READ_DATA : 24;
		unsigned int          PIPE1_DEBUG_PWR_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int         PIPE1_DESIRED_PWR_STATE : 1;
		unsigned int       PIPE1_REQUESTED_PWR_STATE : 1;
		unsigned int          PIPE1_PGFSM_PWR_STATUS : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE2_DMIF_BUFFER_CONTROL__VI {
	struct {
		unsigned int          DMIF_BUFFERS_ALLOCATED : 3;
		unsigned int                                 : 1;
		unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE2_MAX_REQUESTS__VI {
	struct {
		unsigned int                    MAX_REQUESTS : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE2_PG_CONFIG__VI {
	struct {
		unsigned int             PIPE2_POWER_FORCEON : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE2_PG_ENABLE__VI {
	struct {
		unsigned int                PIPE2_POWER_GATE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE2_PG_STATUS__VI {
	struct {
		unsigned int           PIPE2_PGFSM_READ_DATA : 24;
		unsigned int          PIPE2_DEBUG_PWR_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int         PIPE2_DESIRED_PWR_STATE : 1;
		unsigned int       PIPE2_REQUESTED_PWR_STATE : 1;
		unsigned int          PIPE2_PGFSM_PWR_STATUS : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE3_DMIF_BUFFER_CONTROL__VI {
	struct {
		unsigned int          DMIF_BUFFERS_ALLOCATED : 3;
		unsigned int                                 : 1;
		unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE3_MAX_REQUESTS__VI {
	struct {
		unsigned int                    MAX_REQUESTS : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE3_PG_CONFIG__VI {
	struct {
		unsigned int             PIPE3_POWER_FORCEON : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE3_PG_ENABLE__VI {
	struct {
		unsigned int                PIPE3_POWER_GATE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE3_PG_STATUS__VI {
	struct {
		unsigned int           PIPE3_PGFSM_READ_DATA : 24;
		unsigned int          PIPE3_DEBUG_PWR_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int         PIPE3_DESIRED_PWR_STATE : 1;
		unsigned int       PIPE3_REQUESTED_PWR_STATE : 1;
		unsigned int          PIPE3_PGFSM_PWR_STATUS : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE4_DMIF_BUFFER_CONTROL__VI {
	struct {
		unsigned int          DMIF_BUFFERS_ALLOCATED : 3;
		unsigned int                                 : 1;
		unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE4_MAX_REQUESTS__VI {
	struct {
		unsigned int                    MAX_REQUESTS : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE4_PG_CONFIG__VI {
	struct {
		unsigned int             PIPE4_POWER_FORCEON : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE4_PG_ENABLE__VI {
	struct {
		unsigned int                PIPE4_POWER_GATE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE4_PG_STATUS__VI {
	struct {
		unsigned int           PIPE4_PGFSM_READ_DATA : 24;
		unsigned int          PIPE4_DEBUG_PWR_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int         PIPE4_DESIRED_PWR_STATE : 1;
		unsigned int       PIPE4_REQUESTED_PWR_STATE : 1;
		unsigned int          PIPE4_PGFSM_PWR_STATUS : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE5_DMIF_BUFFER_CONTROL__VI {
	struct {
		unsigned int          DMIF_BUFFERS_ALLOCATED : 3;
		unsigned int                                 : 1;
		unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE5_MAX_REQUESTS__VI {
	struct {
		unsigned int                    MAX_REQUESTS : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE5_PG_CONFIG__VI {
	struct {
		unsigned int             PIPE5_POWER_FORCEON : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE5_PG_ENABLE__VI {
	struct {
		unsigned int                PIPE5_POWER_GATE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE5_PG_STATUS__VI {
	struct {
		unsigned int           PIPE5_PGFSM_READ_DATA : 24;
		unsigned int          PIPE5_DEBUG_PWR_STATUS : 2;
		unsigned int                                 : 2;
		unsigned int         PIPE5_DESIRED_PWR_STATE : 1;
		unsigned int       PIPE5_REQUESTED_PWR_STATE : 1;
		unsigned int          PIPE5_PGFSM_PWR_STATUS : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE6_ARBITRATION_CONTROL3__VI {
	struct {
		unsigned int               EFFICIENCY_WEIGHT : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE6_MAX_REQUESTS__VI {
	struct {
		unsigned int                    MAX_REQUESTS : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE7_ARBITRATION_CONTROL3__VI {
	struct {
		unsigned int               EFFICIENCY_WEIGHT : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIPE7_MAX_REQUESTS__VI {
	struct {
		unsigned int                    MAX_REQUESTS : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PIXCLK0_RESYNC_CNTL__VI {
	struct {
		unsigned int           PIXCLK0_RESYNC_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int           DCCG_DEEP_COLOR_CNTL0 : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_ANALOG__VI {
	struct {
		unsigned int                    PLL_CAL_MODE : 5;
		unsigned int               PLL_PFD_PULSE_SEL : 2;
		unsigned int                                 : 1;
		unsigned int                          PLL_CP : 4;
		unsigned int                     PLL_LF_MODE : 9;
		unsigned int                PLL_VREG_FB_TRIM : 3;
		unsigned int                       PLL_IBIAS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_ANALOG_CNTL__VI {
	struct {
		unsigned int              PLL_ANALOG_TEST_EN : 1;
		unsigned int             PLL_ANALOG_MUX_CNTL : 4;
		unsigned int          PLL_ANALOGOUT_MUX_CNTL : 4;
		unsigned int                 PLL_REGREF_TRIM : 5;
		unsigned int                 PLL_CALIB_FBDIV : 3;
		unsigned int               PLL_CALIB_FASTCAL : 1;
		unsigned int               PLL_TEST_SSAMP_EN : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_CNTL__VI {
	struct {
		unsigned int                       PLL_RESET : 1;
		unsigned int                  PLL_POWER_DOWN : 1;
		unsigned int                  PLL_BYPASS_CAL : 1;
		unsigned int                PLL_POST_DIV_SRC : 1;
		unsigned int                      PLL_VCOREF : 2;
		unsigned int             PLL_PCIE_REFCLK_SEL : 1;
		unsigned int           PLL_ANTIGLITCH_RESETB : 1;
		unsigned int                      PLL_CALREF : 2;
		unsigned int           PLL_CAL_BYPASS_REFDIV : 1;
		unsigned int                  PLL_REFCLK_SEL : 2;
		unsigned int           PLL_ANTI_GLITCH_RESET : 1;
		unsigned int              PLL_XOCLK_DRV_R_EN : 1;
		unsigned int                                 : 1;
		unsigned int                 PLL_REF_DIV_SRC : 3;
		unsigned int               PLL_LOCK_FREQ_SEL : 1;
		unsigned int                  PLL_CALIB_DONE : 1;
		unsigned int                      PLL_LOCKED : 1;
		unsigned int              PLL_REFCLK_RECV_EN : 1;
		unsigned int             PLL_REFCLK_RECV_SEL : 1;
		unsigned int          PLL_TIMING_MODE_STATUS : 2;
		unsigned int                   PLL_DIG_SPARE : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_DEBUG_CNTL__VI {
	struct {
		unsigned int        PLL_DEBUG_SIGNALS_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int            PLL_DEBUG_MUXOUT_SEL : 4;
		unsigned int               PLL_DEBUG_CLK_SEL : 5;
		unsigned int                                 : 3;
		unsigned int              PLL_DEBUG_ADC_CNTL : 8;
		unsigned int          PLL_DEBUG_ADC_READBACK : 3;
		unsigned int                PLL_DEBUG_ADC_EN : 1;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_DS_CNTL__VI {
	struct {
		unsigned int                     PLL_DS_FRAC : 16;
		unsigned int                    PLL_DS_ORDER : 2;
		unsigned int                     PLL_DS_MODE : 1;
		unsigned int                  PLL_DS_PRBS_EN : 1;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_FB_DIV__VI {
	struct {
		unsigned int             PLL_FB_DIV_FRACTION : 4;
		unsigned int        PLL_FB_DIV_FRACTION_CNTL : 2;
		unsigned int                                 : 10;
		unsigned int                      PLL_FB_DIV : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_IDCLK_CNTL__VI {
	struct {
		unsigned int               PLL_LTDP_IDCLK_EN : 1;
		unsigned int          PLL_LTDP_IDCLK_DIFF_EN : 1;
		unsigned int               PLL_TMDP_IDCLK_EN : 1;
		unsigned int          PLL_TMDP_IDCLK_DIFF_EN : 1;
		unsigned int                    PLL_IDCLK_EN : 1;
		unsigned int                                 : 3;
		unsigned int         PLL_DIFF_POST_DIV_RESET : 1;
		unsigned int                                 : 3;
		unsigned int        PLL_DIFF_POST_DIV_SELECT : 1;
		unsigned int                                 : 3;
		unsigned int               PLL_DIFF_POST_DIV : 4;
		unsigned int                    PLL_CUR_LTDP : 2;
		unsigned int                  PLL_CUR_PREDRV : 2;
		unsigned int                    PLL_CUR_TMDP : 2;
		unsigned int                PLL_CML_A_DRVSTR : 2;
		unsigned int                PLL_CML_B_DRVSTR : 2;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED0__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED1__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED10__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED11__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED12__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED13__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED14__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED15__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED16__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED17__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED18__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED19__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED2__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED20__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED21__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED22__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED23__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED24__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED25__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED26__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED27__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED28__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED29__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED3__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED30__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED31__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED32__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED33__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED34__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED35__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED36__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED37__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED38__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED39__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED4__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED40__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED41__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED5__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED6__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED7__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED8__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_MACRO_CNTL_RESERVED9__VI {
	struct {
		unsigned int         PLL_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_POST_DIV__VI {
	struct {
		unsigned int             PLL_POST_DIV_PIXCLK : 7;
		unsigned int         PLL_POST_DIV1P5_DISPCLK : 1;
		unsigned int             PLL_POST_DIV_DVOCLK : 7;
		unsigned int        PLL_POST_DIV1P5_DPREFCLK : 1;
		unsigned int              PLL_POST_DIV_IDCLK : 7;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_REF_DIV__VI {
	struct {
		unsigned int                     PLL_REF_DIV : 10;
		unsigned int                                 : 2;
		unsigned int         PLL_CALIBRATION_REF_DIV : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_SS_AMOUNT_DSFRAC__VI {
	struct {
		unsigned int            PLL_SS_AMOUNT_DSFRAC : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_SS_CNTL__VI {
	struct {
		unsigned int             PLL_SS_AMOUNT_FBDIV : 8;
		unsigned int        PLL_SS_AMOUNT_NFRAC_SLIP : 4;
		unsigned int                       PLL_SS_EN : 1;
		unsigned int                     PLL_SS_MODE : 1;
		unsigned int                                 : 2;
		unsigned int         PLL_SS_STEP_SIZE_DSFRAC : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_UNLOCK_DETECT_CNTL__VI {
	struct {
		unsigned int        PLL_UNLOCK_DETECT_ENABLE : 1;
		unsigned int    PLL_UNLOCK_DET_RES100_SELECT : 1;
		unsigned int        PLL_UNLOCK_STICKY_STATUS : 1;
		unsigned int                                 : 1;
		unsigned int            PLL_UNLOCK_DET_COUNT : 3;
		unsigned int    PLL_UNLOCKED_STICKY_RST_TEST : 1;
		unsigned int PLL_UNLOCKED_STICKY_TEST_READBACK : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_UPDATE_CNTL__VI {
	struct {
		unsigned int              PLL_UPDATE_PENDING : 1;
		unsigned int                                 : 7;
		unsigned int                PLL_UPDATE_POINT : 1;
		unsigned int                                 : 7;
		unsigned int          PLL_AUTO_RESET_DISABLE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_UPDATE_LOCK__VI {
	struct {
		unsigned int                 PLL_UPDATE_LOCK : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_VREG_CNTL__VI {
	struct {
		unsigned int                   PLL_VREG_CNTL : 20;
		unsigned int                PLL_BG_VREG_BIAS : 2;
		unsigned int                                 : 4;
		unsigned int                    PLL_VREF_SEL : 1;
		unsigned int                                 : 1;
		unsigned int                   PLL_VREG_BIAS : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PLL_XOR_LOCK__VI {
	struct {
		unsigned int                    PLL_XOR_LOCK : 1;
		unsigned int           PLL_XOR_LOCK_READBACK : 1;
		unsigned int                                 : 6;
		unsigned int                       PLL_SPARE : 6;
		unsigned int                                 : 2;
		unsigned int              PLL_LOCK_COUNT_SEL : 4;
		unsigned int PLL_LOCK_DETECTOR_RESOLUTION_FREF : 3;
		unsigned int PLL_LOCK_DETECTOR_RESOLUTION_FFB : 3;
		unsigned int    PLL_LOCK_DETECTOR_OPAMP_BIAS : 2;
		unsigned int           PLL_FAST_LOCK_MODE_EN : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_1__VI {
	struct {
		unsigned int           SviLoadLineOffsetVddC : 8;
		unsigned int             SviLoadLineTrimVddC : 8;
		unsigned int                 SviLoadLineVddC : 8;
		unsigned int                   SviLoadLineEn : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_10__VI {
	struct {
		unsigned int                       GnbLPML_3 : 8;
		unsigned int                       GnbLPML_2 : 8;
		unsigned int                       GnbLPML_1 : 8;
		unsigned int                       GnbLPML_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_11__VI {
	struct {
		unsigned int                       GnbLPML_7 : 8;
		unsigned int                       GnbLPML_6 : 8;
		unsigned int                       GnbLPML_5 : 8;
		unsigned int                       GnbLPML_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_12__VI {
	struct {
		unsigned int                      GnbLPML_11 : 8;
		unsigned int                      GnbLPML_10 : 8;
		unsigned int                       GnbLPML_9 : 8;
		unsigned int                       GnbLPML_8 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_13__VI {
	struct {
		unsigned int                      GnbLPML_15 : 8;
		unsigned int                      GnbLPML_14 : 8;
		unsigned int                      GnbLPML_13 : 8;
		unsigned int                      GnbLPML_12 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_14__VI {
	struct {
		unsigned int                     Reserved1_1 : 8;
		unsigned int                     Reserved1_0 : 8;
		unsigned int                   GnbLPMLMinVid : 8;
		unsigned int                   GnbLPMLMaxVid : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_15__VI {
	struct {
		unsigned int       BapmVddCBaseLeakageLoSidd : 16;
		unsigned int       BapmVddCBaseLeakageHiSidd : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_2__VI {
	struct {
		unsigned int                        TDC_MAWt : 8;
		unsigned int TDC_VDDC_ThrottleReleaseLimitPerc : 8;
		unsigned int               TDC_VDDC_PkgLimit : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_3__VI {
	struct {
		unsigned int                        Reserved : 8;
		unsigned int              LPMLTemperatureMax : 8;
		unsigned int              LPMLTemperatureMin : 8;
		unsigned int                 TdcWaterfallCtl : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_4__VI {
	struct {
		unsigned int         LPMLTemperatureScaler_3 : 8;
		unsigned int         LPMLTemperatureScaler_2 : 8;
		unsigned int         LPMLTemperatureScaler_1 : 8;
		unsigned int         LPMLTemperatureScaler_0 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_5__VI {
	struct {
		unsigned int         LPMLTemperatureScaler_7 : 8;
		unsigned int         LPMLTemperatureScaler_6 : 8;
		unsigned int         LPMLTemperatureScaler_5 : 8;
		unsigned int         LPMLTemperatureScaler_4 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_6__VI {
	struct {
		unsigned int        LPMLTemperatureScaler_11 : 8;
		unsigned int        LPMLTemperatureScaler_10 : 8;
		unsigned int         LPMLTemperatureScaler_9 : 8;
		unsigned int         LPMLTemperatureScaler_8 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_7__VI {
	struct {
		unsigned int        LPMLTemperatureScaler_15 : 8;
		unsigned int        LPMLTemperatureScaler_14 : 8;
		unsigned int        LPMLTemperatureScaler_13 : 8;
		unsigned int        LPMLTemperatureScaler_12 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_8__VI {
	struct {
		unsigned int      FuzzyFan_ErrorRateSetDelta : 16;
		unsigned int          FuzzyFan_ErrorSetDelta : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PM_FUSES_9__VI {
	struct {
		unsigned int                       Reserved6 : 16;
		unsigned int            FuzzyFan_PwmSetDelta : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PPLL_DEBUG_MUX_CNTL__VI {
	struct {
		unsigned int               DEBUG_BUS_MUX_SEL : 5;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PPLL_DIV_UPDATE_DEBUG__VI {
	struct {
		unsigned int             PLL_REF_DIV_CHANGED : 1;
		unsigned int              PLL_FB_DIV_CHANGED : 1;
		unsigned int              PLL_UPDATE_PENDING : 1;
		unsigned int        PLL_UPDATE_CURRENT_STATE : 2;
		unsigned int               PLL_UPDATE_ENABLE : 1;
		unsigned int                  PLL_UPDATE_REQ : 1;
		unsigned int                  PLL_UPDATE_ACK : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PPLL_SPARE0__VI {
	struct {
		unsigned int                      PLL_SPARE0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PPLL_SPARE1__VI {
	struct {
		unsigned int                      PLL_SPARE1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PPLL_STATUS_DEBUG__VI {
	struct {
		unsigned int                   PLL_DEBUG_BUS : 16;
		unsigned int                      PLL_UNLOCK : 1;
		unsigned int                  PLL_CAL_RESULT : 4;
		unsigned int                                 : 3;
		unsigned int           PLL_POWERGOOD_ISO_ENB : 1;
		unsigned int                 PLL_POWERGOOD_S : 1;
		unsigned int                 PLL_POWERGOOD_V : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_CONTROL__VI {
	struct {
		unsigned int                   PRESCALE_MODE : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_GRPH_CONTROL__VI {
	struct {
		unsigned int            GRPH_PRESCALE_SELECT : 1;
		unsigned int            GRPH_PRESCALE_R_SIGN : 1;
		unsigned int            GRPH_PRESCALE_G_SIGN : 1;
		unsigned int            GRPH_PRESCALE_B_SIGN : 1;
		unsigned int            GRPH_PRESCALE_BYPASS : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_OVL_CONTROL__VI {
	struct {
		unsigned int             OVL_PRESCALE_SELECT : 1;
		unsigned int            OVL_PRESCALE_CB_SIGN : 1;
		unsigned int             OVL_PRESCALE_Y_SIGN : 1;
		unsigned int            OVL_PRESCALE_CR_SIGN : 1;
		unsigned int             OVL_PRESCALE_BYPASS : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_VALUES_B__VI {
	struct {
		unsigned int                 PRESCALE_BIAS_B : 16;
		unsigned int                PRESCALE_SCALE_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_VALUES_G__VI {
	struct {
		unsigned int                 PRESCALE_BIAS_G : 16;
		unsigned int                PRESCALE_SCALE_G : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_VALUES_GRPH_B__VI {
	struct {
		unsigned int            GRPH_PRESCALE_BIAS_B : 16;
		unsigned int           GRPH_PRESCALE_SCALE_B : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_VALUES_GRPH_G__VI {
	struct {
		unsigned int            GRPH_PRESCALE_BIAS_G : 16;
		unsigned int           GRPH_PRESCALE_SCALE_G : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_VALUES_GRPH_R__VI {
	struct {
		unsigned int            GRPH_PRESCALE_BIAS_R : 16;
		unsigned int           GRPH_PRESCALE_SCALE_R : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_VALUES_OVL_CB__VI {
	struct {
		unsigned int            OVL_PRESCALE_BIAS_CB : 16;
		unsigned int           OVL_PRESCALE_SCALE_CB : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_VALUES_OVL_CR__VI {
	struct {
		unsigned int            OVL_PRESCALE_BIAS_CR : 16;
		unsigned int           OVL_PRESCALE_SCALE_CR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_VALUES_OVL_Y__VI {
	struct {
		unsigned int             OVL_PRESCALE_BIAS_Y : 16;
		unsigned int            OVL_PRESCALE_SCALE_Y : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PRESCALE_VALUES_R__VI {
	struct {
		unsigned int                 PRESCALE_BIAS_R : 16;
		unsigned int                PRESCALE_SCALE_R : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS0_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS10_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS11_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS12_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS13_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS14_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS15_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS16_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS17_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS18_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS19_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS1_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS20_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS21_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS22_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS23_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS24_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS25_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS26_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS27_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS2_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS3_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS4_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS5_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS6_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS7_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS8_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS9_CNTL_STATUS__VI {
	struct {
		unsigned int                        MmDatOut : 8;
		unsigned int                          PsmTdo : 1;
		unsigned int                       AlarmFlag : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS_CNTL__VI {
	struct {
		unsigned int                         MmBusIn : 8;
		unsigned int                       MmLclRdEn : 1;
		unsigned int                       MmLclWrEn : 1;
		unsigned int                         MmLclSz : 2;
		unsigned int                         MmState : 6;
		unsigned int                     PsmScanMode : 1;
		unsigned int                        PsmGater : 1;
		unsigned int                         PsmTrst : 1;
		unsigned int                           PsmEn : 1;
		unsigned int                     SkipPhaseEn : 1;
		unsigned int                         Isolate : 1;
		unsigned int                         AvfsRst : 1;
		unsigned int                    PccIsolateEn : 1;
		unsigned int              DeepSleepIsolateEn : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_AVFS_SEL__VI {
	struct {
		unsigned int                         AvfsSel : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_CKS_CNTL__VI {
	struct {
		unsigned int                      CKS_BYPASS : 1;
		unsigned int                   CKS_PCCEnable : 1;
		unsigned int                   CKS_TEMP_COMP : 1;
		unsigned int              CKS_STRETCH_AMOUNT : 4;
		unsigned int           CKS_SKIP_PHASE_BYPASS : 1;
		unsigned int                 CKS_SAMPLE_SIZE : 4;
		unsigned int             CKS_FSM_WAIT_CYCLES : 4;
		unsigned int            CKS_USE_FOR_LOW_FREQ : 1;
		unsigned int        CKS_NO_EXTRA_COARSE_STEP : 1;
		unsigned int                  CKS_LDO_REFSEL : 4;
		unsigned int                   DDT_DEBUS_SEL : 1;
		unsigned int         CKS_LDO_READY_COUNT_VAL : 8;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_CKS_ENABLE__VI {
	struct {
		unsigned int                  STRETCH_ENABLE : 1;
		unsigned int                     masterReset : 1;
		unsigned int                    staticEnable : 1;
		unsigned int             IGNORE_DROOP_DETECT : 1;
		unsigned int               PCC_HAND_SHAKE_EN : 1;
		unsigned int                    MET_CTRL_SEL : 2;
		unsigned int                DS_HAND_SHAKE_EN : 1;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_DISP_TIMER2_CONTROL__VI {
	struct {
		unsigned int            DISP_TIMER_INT_COUNT : 25;
		unsigned int           DISP_TIMER_INT_ENABLE : 1;
		unsigned int          DISP_TIMER_INT_DISABLE : 1;
		unsigned int             DISP_TIMER_INT_MASK : 1;
		unsigned int          DISP_TIMER_INT_STAT_AK : 1;
		unsigned int             DISP_TIMER_INT_TYPE : 1;
		unsigned int             DISP_TIMER_INT_MODE : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_DISP_TIMER2_DEBUG__VI {
	struct {
		unsigned int          DISP_TIMER_INT_RUNNING : 1;
		unsigned int             DISP_TIMER_INT_STAT : 1;
		unsigned int                  DISP_TIMER_INT : 1;
		unsigned int                                 : 4;
		unsigned int              DISP_TIMER_RUN_VAL : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_DISP_TIMER_CONTROL__VI {
	struct {
		unsigned int            DISP_TIMER_INT_COUNT : 25;
		unsigned int           DISP_TIMER_INT_ENABLE : 1;
		unsigned int          DISP_TIMER_INT_DISABLE : 1;
		unsigned int             DISP_TIMER_INT_MASK : 1;
		unsigned int          DISP_TIMER_INT_STAT_AK : 1;
		unsigned int             DISP_TIMER_INT_TYPE : 1;
		unsigned int             DISP_TIMER_INT_MODE : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_DISP_TIMER_CONTROL2__VI {
	struct {
		unsigned int          DISP_TIMER_PULSE_WIDTH : 10;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_DISP_TIMER_DEBUG__VI {
	struct {
		unsigned int          DISP_TIMER_INT_RUNNING : 1;
		unsigned int             DISP_TIMER_INT_STAT : 1;
		unsigned int                  DISP_TIMER_INT : 1;
		unsigned int                                 : 4;
		unsigned int              DISP_TIMER_RUN_VAL : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_PCC_CONTROL__VI {
	struct {
		unsigned int                    PCC_POLARITY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union PWR_PCC_GPIO_SELECT__VI {
	struct {
		unsigned int                            GPIO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RAS_TA_SIGNATURE1__VI {
	struct {
		unsigned int                       SIGNATURE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RBBMIF_STATUS__VI {
	struct {
		unsigned int      RBBMIF_TIMEOUT_CLIENTS_DEC : 15;
		unsigned int                                 : 13;
		unsigned int               RBBMIF_TIMEOUT_OP : 1;
		unsigned int      RBBMIF_TIMEOUT_RDWR_STATUS : 1;
		unsigned int              RBBMIF_TIMEOUT_ACK : 1;
		unsigned int             RBBMIF_TIMEOUT_MASK : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RBBMIF_STATUS_FLAG__VI {
	struct {
		unsigned int                    RBBMIF_STATE : 3;
		unsigned int              RBBMIF_ACK_TIMEOUT : 1;
		unsigned int             RBBMIF_READ_TIMEOUT : 1;
		unsigned int               RBBMIF_FIFO_EMPTY : 1;
		unsigned int                RBBMIF_FIFO_FULL : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RBBMIF_TIMEOUT__VI {
	struct {
		unsigned int            RBBMIF_TIMEOUT_DELAY : 20;
		unsigned int                 RBBMIF_ACK_HOLD : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RBBMIF_TIMEOUT_DIS__VI {
	struct {
		unsigned int             CLIENT0_TIMEOUT_DIS : 1;
		unsigned int             CLIENT1_TIMEOUT_DIS : 1;
		unsigned int             CLIENT2_TIMEOUT_DIS : 1;
		unsigned int             CLIENT3_TIMEOUT_DIS : 1;
		unsigned int             CLIENT4_TIMEOUT_DIS : 1;
		unsigned int             CLIENT5_TIMEOUT_DIS : 1;
		unsigned int             CLIENT6_TIMEOUT_DIS : 1;
		unsigned int             CLIENT7_TIMEOUT_DIS : 1;
		unsigned int             CLIENT8_TIMEOUT_DIS : 1;
		unsigned int             CLIENT9_TIMEOUT_DIS : 1;
		unsigned int            CLIENT10_TIMEOUT_DIS : 1;
		unsigned int            CLIENT11_TIMEOUT_DIS : 1;
		unsigned int            CLIENT12_TIMEOUT_DIS : 1;
		unsigned int            CLIENT13_TIMEOUT_DIS : 1;
		unsigned int            CLIENT14_TIMEOUT_DIS : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RCU_VIRT_RESET_REQ__VI {
	struct {
		unsigned int                              VF : 16;
		unsigned int                                 : 15;
		unsigned int                              PF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REFCLK_CGTT_BLK_CTRL_REG__VI {
	struct {
		unsigned int            REFCLK_TURN_ON_DELAY : 4;
		unsigned int           REFCLK_TURN_OFF_DELAY : 8;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REFCLK_CNTL__VI {
	struct {
		unsigned int                 REFCLK_CLOCK_EN : 1;
		unsigned int                  REFCLK_SRC_SEL : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_END_CNTL1__VI {
	struct {
		unsigned int    REGAMMA_CNTLA_EXP_REGION_END : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_END_CNTL2__VI {
	struct {
		unsigned int REGAMMA_CNTLA_EXP_REGION_END_SLOPE : 16;
		unsigned int REGAMMA_CNTLA_EXP_REGION_END_BASE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_REGION_0_1__VI {
	struct {
		unsigned int REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_REGION_10_11__VI {
	struct {
		unsigned int REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_REGION_12_13__VI {
	struct {
		unsigned int REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_REGION_14_15__VI {
	struct {
		unsigned int REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_REGION_2_3__VI {
	struct {
		unsigned int REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_REGION_4_5__VI {
	struct {
		unsigned int REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_REGION_6_7__VI {
	struct {
		unsigned int REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_REGION_8_9__VI {
	struct {
		unsigned int REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_SLOPE_CNTL__VI {
	struct {
		unsigned int REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLA_START_CNTL__VI {
	struct {
		unsigned int  REGAMMA_CNTLA_EXP_REGION_START : 18;
		unsigned int                                 : 2;
		unsigned int REGAMMA_CNTLA_EXP_REGION_START_SEGMENT : 7;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_END_CNTL1__VI {
	struct {
		unsigned int    REGAMMA_CNTLB_EXP_REGION_END : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_END_CNTL2__VI {
	struct {
		unsigned int REGAMMA_CNTLB_EXP_REGION_END_SLOPE : 16;
		unsigned int REGAMMA_CNTLB_EXP_REGION_END_BASE : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_REGION_0_1__VI {
	struct {
		unsigned int REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_REGION_10_11__VI {
	struct {
		unsigned int REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_REGION_12_13__VI {
	struct {
		unsigned int REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_REGION_14_15__VI {
	struct {
		unsigned int REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_REGION_2_3__VI {
	struct {
		unsigned int REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_REGION_4_5__VI {
	struct {
		unsigned int REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_REGION_6_7__VI {
	struct {
		unsigned int REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_REGION_8_9__VI {
	struct {
		unsigned int REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
		unsigned int REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET : 9;
		unsigned int                                 : 3;
		unsigned int REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_SLOPE_CNTL__VI {
	struct {
		unsigned int REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE : 18;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CNTLB_START_CNTL__VI {
	struct {
		unsigned int  REGAMMA_CNTLB_EXP_REGION_START : 18;
		unsigned int                                 : 2;
		unsigned int REGAMMA_CNTLB_EXP_REGION_START_SEGMENT : 7;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_CONTROL__VI {
	struct {
		unsigned int               GRPH_REGAMMA_MODE : 3;
		unsigned int                                 : 1;
		unsigned int                OVL_REGAMMA_MODE : 3;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_LUT_DATA__VI {
	struct {
		unsigned int                REGAMMA_LUT_DATA : 19;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_LUT_INDEX__VI {
	struct {
		unsigned int               REGAMMA_LUT_INDEX : 9;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REGAMMA_LUT_WRITE_EN_MASK__VI {
	struct {
		unsigned int       REGAMMA_LUT_WRITE_EN_MASK : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REG_ADAPT_pciecore0_CONTROL__VI {
	struct {
		unsigned int           ACCESS_MODE_pciecore0 : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REG_ADAPT_pif0_CONTROL__VI {
	struct {
		unsigned int                ACCESS_MODE_pif0 : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REG_ADAPT_pwregr_CONTROL__VI {
	struct {
		unsigned int              ACCESS_MODE_pwregr : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REG_ADAPT_pwregt_CONTROL__VI {
	struct {
		unsigned int              ACCESS_MODE_pwregt : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REMAP_HDP_MEM_FLUSH_CNTL__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union REMAP_HDP_REG_FLUSH_CNTL__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                         ADDRESS : 17;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CP_RESPONSE0__VI {
	struct {
		unsigned int                        RESPONSE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CP_RESPONSE1__VI {
	struct {
		unsigned int                        RESPONSE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CP_RESPONSE2__VI {
	struct {
		unsigned int                        RESPONSE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CP_RESPONSE3__VI {
	struct {
		unsigned int                        RESPONSE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CP_SCHEDULERS__VI {
	struct {
		unsigned int                      scheduler0 : 8;
		unsigned int                      scheduler1 : 8;
		unsigned int                      scheduler2 : 8;
		unsigned int                      scheduler3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CSIB_ADDR_HI__VI {
	struct {
		unsigned int                         ADDRESS : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CSIB_ADDR_LO__VI {
	struct {
		unsigned int                         ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_CSIB_LENGTH__VI {
	struct {
		unsigned int                          LENGTH : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_INT_DISABLE_TH0__VI {
	struct {
		unsigned int                         DISABLE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_INT_DISABLE_TH1__VI {
	struct {
		unsigned int                         DISABLE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_INT_FORCE_TH0__VI {
	struct {
		unsigned int                           FORCE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_INT_FORCE_TH1__VI {
	struct {
		unsigned int                           FORCE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_THREAD_RESET__VI {
	struct {
		unsigned int                   THREAD0_RESET : 1;
		unsigned int                   THREAD1_RESET : 1;
		unsigned int                   THREAD2_RESET : 1;
		unsigned int                   THREAD3_RESET : 1;
		unsigned int                        RESERVED : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPM_VMID_THREAD2__VI {
	struct {
		unsigned int                        RLC_VMID : 4;
		unsigned int                       RESERVED0 : 4;
		unsigned int                     RLC_QUEUEID : 3;
		unsigned int                       RESERVED1 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_ACTIVE_FCN_ID__VI {
	struct {
		unsigned int                           VF_ID : 4;
		unsigned int                        RESERVED : 27;
		unsigned int                           PF_VF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG1__VI {
	struct {
		unsigned int                        CMD_TYPE : 4;
		unsigned int                     CMD_EXECUTE : 1;
		unsigned int             CMD_EXECUTE_INTR_EN : 1;
		unsigned int                        RESERVED : 2;
		unsigned int                          FCN_ID : 8;
		unsigned int                     NEXT_FCN_ID : 8;
		unsigned int                       RESERVED1 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG10__VI {
	struct {
		unsigned int                  TIME_QUANTA_PF : 16;
		unsigned int                        RESERVED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG11__VI {
	struct {
		unsigned int                           YIELD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG12__VI {
	struct {
		unsigned int                 TIME_QUANTA_VF0 : 8;
		unsigned int                 TIME_QUANTA_VF1 : 8;
		unsigned int                 TIME_QUANTA_VF2 : 8;
		unsigned int                 TIME_QUANTA_VF3 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG13__VI {
	struct {
		unsigned int                 TIME_QUANTA_VF4 : 8;
		unsigned int                 TIME_QUANTA_VF5 : 8;
		unsigned int                 TIME_QUANTA_VF6 : 8;
		unsigned int                 TIME_QUANTA_VF7 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG14__VI {
	struct {
		unsigned int                 TIME_QUANTA_VF8 : 8;
		unsigned int                 TIME_QUANTA_VF9 : 8;
		unsigned int                TIME_QUANTA_VF10 : 8;
		unsigned int                TIME_QUANTA_VF11 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG15__VI {
	struct {
		unsigned int                TIME_QUANTA_VF12 : 8;
		unsigned int                TIME_QUANTA_VF13 : 8;
		unsigned int                TIME_QUANTA_VF14 : 8;
		unsigned int                TIME_QUANTA_VF15 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG2__VI {
	struct {
		unsigned int                      CMD_STATUS : 4;
		unsigned int                        RESERVED : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG6__VI {
	struct {
		unsigned int                      CNTXT_SIZE : 7;
		unsigned int                  CNTXT_LOCATION : 1;
		unsigned int                        RESERVED : 2;
		unsigned int                    CNTXT_OFFSET : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG8__VI {
	struct {
		unsigned int                  VM_BUSY_STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_CFG_REG9__VI {
	struct {
		unsigned int                   ACTIVE_FCN_ID : 8;
		unsigned int            ACTIVE_FCN_ID_STATUS : 4;
		unsigned int                        RESERVED : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_F32_CNTL__VI {
	struct {
		unsigned int                          ENABLE : 1;
		unsigned int                        RESERVED : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_F32_RESET__VI {
	struct {
		unsigned int                           RESET : 1;
		unsigned int                        RESERVED : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_INT_DISABLE__VI {
	struct {
		unsigned int                         DISABLE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_INT_FORCE__VI {
	struct {
		unsigned int                           FORCE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_RLC_RESPONSE__VI {
	struct {
		unsigned int                            RESP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SCH_0__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SCH_1__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SCH_2__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SCH_3__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SCH_INT__VI {
	struct {
		unsigned int                       interrupt : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SCRATCH_ADDR__VI {
	struct {
		unsigned int                            ADDR : 9;
		unsigned int                        RESERVED : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SCRATCH_DATA__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SDMA0_BUSY_STATUS__VI {
	struct {
		unsigned int                  VM_BUSY_STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SDMA0_STATUS__VI {
	struct {
		unsigned int                       PREEMPTED : 1;
		unsigned int                        RESERVED : 7;
		unsigned int                           SAVED : 1;
		unsigned int                       RESERVED1 : 3;
		unsigned int                        RESTORED : 1;
		unsigned int                       RESERVED2 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SDMA1_BUSY_STATUS__VI {
	struct {
		unsigned int                  VM_BUSY_STATUS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SDMA1_STATUS__VI {
	struct {
		unsigned int                       PREEMPTED : 1;
		unsigned int                        RESERVED : 7;
		unsigned int                           SAVED : 1;
		unsigned int                       RESERVED1 : 3;
		unsigned int                        RESTORED : 1;
		unsigned int                       RESERVED2 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_SMU_RESPONSE__VI {
	struct {
		unsigned int                            RESP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_UCODE_ADDR__VI {
	struct {
		unsigned int                      UCODE_ADDR : 12;
		unsigned int                        RESERVED : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_UCODE_DATA__VI {
	struct {
		unsigned int                      UCODE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_VF_ENABLE__VI {
	struct {
		unsigned int                       VF_ENABLE : 1;
		unsigned int                        RESERVED : 15;
		unsigned int                          VF_NUM : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_GPU_IOV_VIRT_RESET_REQ__VI {
	struct {
		unsigned int                          VF_FLR : 16;
		unsigned int                        RESERVED : 15;
		unsigned int                     SOFT_PF_FLR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_HYP_GPM_UCODE_ADDR__VI {
	struct {
		unsigned int                      UCODE_ADDR : 12;
		unsigned int                        RESERVED : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_HYP_GPM_UCODE_DATA__VI {
	struct {
		unsigned int                      UCODE_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_MGCG_CTRL__VI {
	struct {
		unsigned int                         MGCG_EN : 1;
		unsigned int                      SILICON_EN : 1;
		unsigned int                   SIMULATION_EN : 1;
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int            GC_CAC_MGCG_CLK_CNTL : 1;
		unsigned int            SE_CAC_MGCG_CLK_CNTL : 1;
		unsigned int                           SPARE : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PERFMON_CLK_CNTL__VI {
	struct {
		unsigned int             PERFMON_CLOCK_STATE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_PG_DELAY_3__VI {
	struct {
		unsigned int         CGCG_ACTIVE_BEFORE_CGPG : 8;
		unsigned int                        RESERVED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_RLCV_COMMAND__VI {
	struct {
		unsigned int                             CMD : 4;
		unsigned int                        RESERVED : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_RLCV_SAFE_MODE__VI {
	struct {
		unsigned int                             CMD : 1;
		unsigned int                         MESSAGE : 4;
		unsigned int                       RESERVED1 : 3;
		unsigned int                        RESPONSE : 4;
		unsigned int                        RESERVED : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_ROM_CNTL__VI {
	struct {
		unsigned int                         USE_ROM : 1;
		unsigned int                     SLP_MODE_EN : 1;
		unsigned int                EFUSE_DISTRIB_EN : 1;
		unsigned int                   HELLOWORLD_EN : 1;
		unsigned int                   CU_HARVEST_EN : 1;
		unsigned int                        RESERVED : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SMU_COMMAND__VI {
	struct {
		unsigned int                             CMD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SMU_MESSAGE__VI {
	struct {
		unsigned int                             CMD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SMU_SAFE_MODE__VI {
	struct {
		unsigned int                             CMD : 1;
		unsigned int                         MESSAGE : 4;
		unsigned int                       RESERVED1 : 3;
		unsigned int                        RESPONSE : 4;
		unsigned int                        RESERVED : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__VI {
	struct {
		unsigned int            PERFMON_SAMPLE_DELAY : 8;
		unsigned int                        RESERVED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__VI {
	struct {
		unsigned int            PERFMON_SAMPLE_DELAY : 8;
		unsigned int                        RESERVED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__VI {
	struct {
		unsigned int            PERFMON_SAMPLE_DELAY : 8;
		unsigned int                        RESERVED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__VI {
	struct {
		unsigned int            PERFMON_SAMPLE_DELAY : 8;
		unsigned int                        RESERVED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_ARAM_ADDR__VI {
	struct {
		unsigned int                            ADDR : 10;
		unsigned int                        RESERVED : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_ARAM_DATA__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_CNTL__VI {
	struct {
		unsigned int                      SRM_ENABLE : 1;
		unsigned int                  AUTO_INCR_ADDR : 1;
		unsigned int                        RESERVED : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_DEBUG__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_DEBUG_SELECT__VI {
	struct {
		unsigned int                          SELECT : 8;
		unsigned int                        RESERVED : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_DRAM_ADDR__VI {
	struct {
		unsigned int                            ADDR : 10;
		unsigned int                        RESERVED : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_DRAM_DATA__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_GPM_ABORT__VI {
	struct {
		unsigned int                           ABORT : 1;
		unsigned int                        RESERVED : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_GPM_COMMAND__VI {
	struct {
		unsigned int                              OP : 1;
		unsigned int                      INDEX_CNTL : 1;
		unsigned int                  INDEX_CNTL_NUM : 3;
		unsigned int                            SIZE : 12;
		unsigned int                    START_OFFSET : 12;
		unsigned int                       RESERVED1 : 2;
		unsigned int                     DEST_MEMORY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_GPM_COMMAND_STATUS__VI {
	struct {
		unsigned int                      FIFO_EMPTY : 1;
		unsigned int                       FIFO_FULL : 1;
		unsigned int                        RESERVED : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_ADDR_0__VI {
	struct {
		unsigned int                         ADDRESS : 16;
		unsigned int                        RESERVED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_ADDR_1__VI {
	struct {
		unsigned int                         ADDRESS : 16;
		unsigned int                        RESERVED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_ADDR_2__VI {
	struct {
		unsigned int                         ADDRESS : 16;
		unsigned int                        RESERVED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_ADDR_3__VI {
	struct {
		unsigned int                         ADDRESS : 16;
		unsigned int                        RESERVED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_ADDR_4__VI {
	struct {
		unsigned int                         ADDRESS : 16;
		unsigned int                        RESERVED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_ADDR_5__VI {
	struct {
		unsigned int                         ADDRESS : 16;
		unsigned int                        RESERVED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_ADDR_6__VI {
	struct {
		unsigned int                         ADDRESS : 16;
		unsigned int                        RESERVED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_ADDR_7__VI {
	struct {
		unsigned int                         ADDRESS : 16;
		unsigned int                        RESERVED : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_DATA_0__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_DATA_1__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_DATA_2__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_DATA_3__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_DATA_4__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_DATA_5__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_DATA_6__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_INDEX_CNTL_DATA_7__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_RLCV_COMMAND__VI {
	struct {
		unsigned int                              OP : 1;
		unsigned int                        RESERVED : 3;
		unsigned int                            SIZE : 12;
		unsigned int                    START_OFFSET : 12;
		unsigned int                       RESERVED1 : 3;
		unsigned int                     DEST_MEMORY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_RLCV_COMMAND_STATUS__VI {
	struct {
		unsigned int                      FIFO_EMPTY : 1;
		unsigned int                       FIFO_FULL : 1;
		unsigned int                        RESERVED : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union RLC_SRM_STAT__VI {
	struct {
		unsigned int                      SRM_STATUS : 1;
		unsigned int                        RESERVED : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SAM_IH_EXT_ERR_INTR__VI {
	struct {
		unsigned int                             UVD : 1;
		unsigned int                             VCE : 1;
		unsigned int                             ISP : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SAM_IH_EXT_ERR_INTR_STATUS__VI {
	struct {
		unsigned int                             UVD : 1;
		unsigned int                             VCE : 1;
		unsigned int                             ISP : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SAM_SAB_RBI_WPTR__VI {
	struct {
		unsigned int                                 : 26;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SAM_SAB_RBO_WPTR__VI {
	struct {
		unsigned int                                 : 30;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_ALU_CONTROL__VI {
	struct {
		unsigned int                 SCL_ALU_DISABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_AUTOMATIC_MODE_CONTROL__VI {
	struct {
		unsigned int        SCL_V_CALC_AUTO_RATIO_EN : 1;
		unsigned int                                 : 15;
		unsigned int        SCL_H_CALC_AUTO_RATIO_EN : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_COEF_RAM_SELECT__VI {
	struct {
		unsigned int          SCL_C_RAM_TAP_PAIR_IDX : 2;
		unsigned int                                 : 6;
		unsigned int                 SCL_C_RAM_PHASE : 7;
		unsigned int                                 : 1;
		unsigned int           SCL_C_RAM_FILTER_TYPE : 2;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_COEF_RAM_TAP_DATA__VI {
	struct {
		unsigned int         SCL_C_RAM_EVEN_TAP_COEF : 14;
		unsigned int                                 : 1;
		unsigned int      SCL_C_RAM_EVEN_TAP_COEF_EN : 1;
		unsigned int          SCL_C_RAM_ODD_TAP_COEF : 14;
		unsigned int                                 : 1;
		unsigned int       SCL_C_RAM_ODD_TAP_COEF_EN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_CONTROL__VI {
	struct {
		unsigned int               SCL_BOUNDARY_MODE : 1;
		unsigned int                                 : 3;
		unsigned int              SCL_EARLY_EOL_MODE : 1;
		unsigned int                                 : 3;
		unsigned int                 SCL_TOTAL_PHASE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_DEBUG__VI {
	struct {
		unsigned int                       SCL_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_DEBUG2__VI {
	struct {
		unsigned int              SCL_DEBUG_REQ_MODE : 1;
		unsigned int              SCL_DEBUG_EOF_MODE : 2;
		unsigned int                      SCL_DEBUG2 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_EXT_OVERSCAN_LEFT_RIGHT__VI {
	struct {
		unsigned int              EXT_OVERSCAN_RIGHT : 13;
		unsigned int                                 : 3;
		unsigned int               EXT_OVERSCAN_LEFT : 13;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_EXT_OVERSCAN_TOP_BOTTOM__VI {
	struct {
		unsigned int             EXT_OVERSCAN_BOTTOM : 13;
		unsigned int                                 : 3;
		unsigned int                EXT_OVERSCAN_TOP : 13;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_HORZ_FILTER_CONTROL__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int     SCL_H_2TAP_HARDCODE_COEF_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_HORZ_FILTER_INIT__VI {
	struct {
		unsigned int                 SCL_H_INIT_FRAC : 24;
		unsigned int                  SCL_H_INIT_INT : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_HORZ_FILTER_INIT_C__VI {
	struct {
		unsigned int               SCL_H_INIT_FRAC_C : 24;
		unsigned int                SCL_H_INIT_INT_C : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_HORZ_FILTER_SCALE_RATIO__VI {
	struct {
		unsigned int               SCL_H_SCALE_RATIO : 26;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_HORZ_FILTER_SCALE_RATIO_C__VI {
	struct {
		unsigned int             SCL_H_SCALE_RATIO_C : 26;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_MANUAL_REPLICATE_CONTROL__VI {
	struct {
		unsigned int   SCL_V_MANUAL_REPLICATE_FACTOR : 4;
		unsigned int                                 : 4;
		unsigned int   SCL_H_MANUAL_REPLICATE_FACTOR : 4;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_MODE__VI {
	struct {
		unsigned int                        SCL_MODE : 1;
		unsigned int                                 : 3;
		unsigned int                     SCL_PSCL_EN : 1;
		unsigned int                                 : 3;
		unsigned int            SCL_INTERLACE_SOURCE : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_MODE_CHANGE_DET1__VI {
	struct {
		unsigned int                 SCL_MODE_CHANGE : 1;
		unsigned int                                 : 3;
		unsigned int             SCL_MODE_CHANGE_ACK : 1;
		unsigned int                                 : 2;
		unsigned int           SCL_ALU_H_SCALE_RATIO : 21;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_MODE_CHANGE_DET2__VI {
	struct {
		unsigned int           SCL_ALU_V_SCALE_RATIO : 21;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_MODE_CHANGE_DET3__VI {
	struct {
		unsigned int           SCL_ALU_SOURCE_HEIGHT : 14;
		unsigned int                                 : 2;
		unsigned int            SCL_ALU_SOURCE_WIDTH : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_MODE_CHANGE_MASK__VI {
	struct {
		unsigned int            SCL_MODE_CHANGE_MASK : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_ROUND_OFFSET__VI {
	struct {
		unsigned int          SCL_ROUND_OFFSET_RGB_Y : 16;
		unsigned int           SCL_ROUND_OFFSET_CBCR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_TAP_CONTROL__VI {
	struct {
		unsigned int               SCL_V_NUM_OF_TAPS : 3;
		unsigned int                                 : 1;
		unsigned int               SCL_H_NUM_OF_TAPS : 3;
		unsigned int                                 : 1;
		unsigned int             SCL_V_NUM_OF_TAPS_C : 3;
		unsigned int                                 : 1;
		unsigned int             SCL_H_NUM_OF_TAPS_C : 3;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int             SCL_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int            SCL_TEST_DEBUG_INDEX : 8;
		unsigned int         SCL_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_UPDATE__VI {
	struct {
		unsigned int              SCL_UPDATE_PENDING : 1;
		unsigned int                                 : 7;
		unsigned int                SCL_UPDATE_TAKEN : 1;
		unsigned int                                 : 7;
		unsigned int                 SCL_UPDATE_LOCK : 1;
		unsigned int                                 : 7;
		unsigned int        SCL_COEF_UPDATE_COMPLETE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VERT_FILTER_CONTROL__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int     SCL_V_2TAP_HARDCODE_COEF_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VERT_FILTER_INIT__VI {
	struct {
		unsigned int                 SCL_V_INIT_FRAC : 24;
		unsigned int                  SCL_V_INIT_INT : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VERT_FILTER_INIT_BOT__VI {
	struct {
		unsigned int             SCL_V_INIT_FRAC_BOT : 24;
		unsigned int              SCL_V_INIT_INT_BOT : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VERT_FILTER_INIT_BOT_C__VI {
	struct {
		unsigned int           SCL_V_INIT_FRAC_BOT_C : 24;
		unsigned int            SCL_V_INIT_INT_BOT_C : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VERT_FILTER_INIT_C__VI {
	struct {
		unsigned int               SCL_V_INIT_FRAC_C : 24;
		unsigned int                SCL_V_INIT_INT_C : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VERT_FILTER_SCALE_RATIO__VI {
	struct {
		unsigned int               SCL_V_SCALE_RATIO : 26;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VERT_FILTER_SCALE_RATIO_C__VI {
	struct {
		unsigned int             SCL_V_SCALE_RATIO_C : 26;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VIEWPORT_SIZE__VI {
	struct {
		unsigned int                 VIEWPORT_HEIGHT : 13;
		unsigned int                                 : 3;
		unsigned int                  VIEWPORT_WIDTH : 13;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VIEWPORT_SIZE_C__VI {
	struct {
		unsigned int               VIEWPORT_HEIGHT_C : 13;
		unsigned int                                 : 3;
		unsigned int                VIEWPORT_WIDTH_C : 13;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VIEWPORT_START__VI {
	struct {
		unsigned int                VIEWPORT_Y_START : 14;
		unsigned int                                 : 2;
		unsigned int                VIEWPORT_X_START : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VIEWPORT_START_C__VI {
	struct {
		unsigned int              VIEWPORT_Y_START_C : 14;
		unsigned int                                 : 2;
		unsigned int              VIEWPORT_X_START_C : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VIEWPORT_START_SECONDARY__VI {
	struct {
		unsigned int      VIEWPORT_Y_START_SECONDARY : 14;
		unsigned int                                 : 2;
		unsigned int      VIEWPORT_X_START_SECONDARY : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCLV_VIEWPORT_START_SECONDARY_C__VI {
	struct {
		unsigned int    VIEWPORT_Y_START_SECONDARY_C : 14;
		unsigned int                                 : 2;
		unsigned int    VIEWPORT_X_START_SECONDARY_C : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_DEBUG2__VI {
	struct {
		unsigned int              SCL_DEBUG_REQ_MODE : 1;
		unsigned int              SCL_DEBUG_EOF_MODE : 2;
		unsigned int                      SCL_DEBUG2 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_HORZ_FILTER_INIT__VI {
	struct {
		unsigned int                 SCL_H_INIT_FRAC : 24;
		unsigned int                  SCL_H_INIT_INT : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_MODE__VI {
	struct {
		unsigned int                        SCL_MODE : 2;
		unsigned int                                 : 2;
		unsigned int                     SCL_PSCL_EN : 1;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SCL_ROUND_OFFSET__VI {
	struct {
		unsigned int          SCL_ROUND_OFFSET_RGB_Y : 16;
		unsigned int           SCL_ROUND_OFFSET_CBCR : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_ACTIVE_FCN_ID__VI {
	struct {
		unsigned int                            VFID : 4;
		unsigned int                                 : 27;
		unsigned int                              VF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_ATOMIC_CNTL__VI {
	struct {
		unsigned int                      LOOP_TIMER : 31;
		unsigned int           ATOMIC_RTN_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_ATOMIC_PREOP_HI__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_ATOMIC_PREOP_LO__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_BA_THRESHOLD__VI {
	struct {
		unsigned int                      READ_THRES : 10;
		unsigned int                                 : 6;
		unsigned int                     WRITE_THRES : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_CONTEXT_REG_TYPE0__VI {
	struct {
		unsigned int               SDMA0_GFX_RB_CNTL : 1;
		unsigned int               SDMA0_GFX_RB_BASE : 1;
		unsigned int            SDMA0_GFX_RB_BASE_HI : 1;
		unsigned int               SDMA0_GFX_RB_RPTR : 1;
		unsigned int               SDMA0_GFX_RB_WPTR : 1;
		unsigned int     SDMA0_GFX_RB_WPTR_POLL_CNTL : 1;
		unsigned int  SDMA0_GFX_RB_WPTR_POLL_ADDR_HI : 1;
		unsigned int  SDMA0_GFX_RB_WPTR_POLL_ADDR_LO : 1;
		unsigned int       SDMA0_GFX_RB_RPTR_ADDR_HI : 1;
		unsigned int       SDMA0_GFX_RB_RPTR_ADDR_LO : 1;
		unsigned int               SDMA0_GFX_IB_CNTL : 1;
		unsigned int               SDMA0_GFX_IB_RPTR : 1;
		unsigned int             SDMA0_GFX_IB_OFFSET : 1;
		unsigned int            SDMA0_GFX_IB_BASE_LO : 1;
		unsigned int            SDMA0_GFX_IB_BASE_HI : 1;
		unsigned int               SDMA0_GFX_IB_SIZE : 1;
		unsigned int             SDMA0_GFX_SKIP_CNTL : 1;
		unsigned int        SDMA0_GFX_CONTEXT_STATUS : 1;
		unsigned int              SDMA0_GFX_DOORBELL : 1;
		unsigned int          SDMA0_GFX_CONTEXT_CNTL : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_CONTEXT_REG_TYPE1__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int          SDMA0_GFX_VIRTUAL_ADDR : 1;
		unsigned int             SDMA0_GFX_APE1_CNTL : 1;
		unsigned int          SDMA0_GFX_DOORBELL_LOG : 1;
		unsigned int             SDMA0_GFX_WATERMARK : 1;
		unsigned int                       VOID_REG1 : 1;
		unsigned int           SDMA0_GFX_CSA_ADDR_LO : 1;
		unsigned int           SDMA0_GFX_CSA_ADDR_HI : 1;
		unsigned int                       VOID_REG2 : 1;
		unsigned int         SDMA0_GFX_IB_SUB_REMAIN : 1;
		unsigned int               SDMA0_GFX_PREEMPT : 1;
		unsigned int             SDMA0_GFX_DUMMY_REG : 1;
		unsigned int                        RESERVED : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_CONTEXT_REG_TYPE2__VI {
	struct {
		unsigned int          SDMA0_GFX_MIDCMD_DATA0 : 1;
		unsigned int          SDMA0_GFX_MIDCMD_DATA1 : 1;
		unsigned int          SDMA0_GFX_MIDCMD_DATA2 : 1;
		unsigned int          SDMA0_GFX_MIDCMD_DATA3 : 1;
		unsigned int          SDMA0_GFX_MIDCMD_DATA4 : 1;
		unsigned int          SDMA0_GFX_MIDCMD_DATA5 : 1;
		unsigned int           SDMA0_GFX_MIDCMD_CNTL : 1;
		unsigned int                        RESERVED : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_EDC_CONFIG__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                         DIS_EDC : 1;
		unsigned int                  ECC_INT_ENABLE : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_CSA_ADDR_HI__VI {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_CSA_ADDR_LO__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_DOORBELL__VI {
	struct {
		unsigned int                          OFFSET : 21;
		unsigned int                                 : 7;
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                        CAPTURED : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_DOORBELL_LOG__VI {
	struct {
		unsigned int                        BE_ERROR : 1;
		unsigned int                                 : 1;
		unsigned int                            DATA : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_DUMMY_REG__VI {
	struct {
		unsigned int                           DUMMY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_IB_SUB_REMAIN__VI {
	struct {
		unsigned int                            SIZE : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_MIDCMD_CNTL__VI {
	struct {
		unsigned int                      DATA_VALID : 1;
		unsigned int                       COPY_MODE : 1;
		unsigned int                                 : 2;
		unsigned int                     SPLIT_STATE : 4;
		unsigned int                   ALLOW_PREEMPT : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_MIDCMD_DATA0__VI {
	struct {
		unsigned int                           DATA0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_MIDCMD_DATA1__VI {
	struct {
		unsigned int                           DATA1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_MIDCMD_DATA2__VI {
	struct {
		unsigned int                           DATA2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_MIDCMD_DATA3__VI {
	struct {
		unsigned int                           DATA3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_MIDCMD_DATA4__VI {
	struct {
		unsigned int                           DATA4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_MIDCMD_DATA5__VI {
	struct {
		unsigned int                           DATA5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_PREEMPT__VI {
	struct {
		unsigned int                      IB_PREEMPT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_GFX_WATERMARK__VI {
	struct {
		unsigned int                  RD_OUTSTANDING : 12;
		unsigned int                                 : 4;
		unsigned int                  WR_OUTSTANDING : 9;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_ID__VI {
	struct {
		unsigned int                       DEVICE_ID : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_PERF_REG_TYPE0__VI {
	struct {
		unsigned int              SDMA0_PERFMON_CNTL : 1;
		unsigned int       SDMA0_PERFCOUNTER0_RESULT : 1;
		unsigned int       SDMA0_PERFCOUNTER1_RESULT : 1;
		unsigned int                   RESERVED_31_3 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_POWER_CNTL_IDLE__VI {
	struct {
		unsigned int                          DELAY1 : 16;
		unsigned int                          DELAY2 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_PUB_REG_TYPE0__VI {
	struct {
		unsigned int                SDMA0_UCODE_ADDR : 1;
		unsigned int                SDMA0_UCODE_DATA : 1;
		unsigned int                SDMA0_POWER_CNTL : 1;
		unsigned int                  SDMA0_CLK_CTRL : 1;
		unsigned int                      SDMA0_CNTL : 1;
		unsigned int              SDMA0_CHICKEN_BITS : 1;
		unsigned int             SDMA0_TILING_CONFIG : 1;
		unsigned int                      SDMA0_HASH : 1;
		unsigned int                                 : 1;
		unsigned int  SDMA0_SEM_WAIT_FAIL_TIMER_CNTL : 1;
		unsigned int             SDMA0_RB_RPTR_FETCH : 1;
		unsigned int           SDMA0_IB_OFFSET_FETCH : 1;
		unsigned int                   SDMA0_PROGRAM : 1;
		unsigned int                SDMA0_STATUS_REG : 1;
		unsigned int               SDMA0_STATUS1_REG : 1;
		unsigned int             SDMA0_RD_BURST_CNTL : 1;
		unsigned int                     RESERVED_16 : 1;
		unsigned int                     RESERVED_17 : 1;
		unsigned int                  SDMA0_F32_CNTL : 1;
		unsigned int                    SDMA0_FREEZE : 1;
		unsigned int            SDMA0_PHASE0_QUANTUM : 1;
		unsigned int            SDMA0_PHASE1_QUANTUM : 1;
		unsigned int               SDMA_POWER_GATING : 1;
		unsigned int               SDMA_PGFSM_CONFIG : 1;
		unsigned int                SDMA_PGFSM_WRITE : 1;
		unsigned int                 SDMA_PGFSM_READ : 1;
		unsigned int                SDMA0_EDC_CONFIG : 1;
		unsigned int              SDMA0_BA_THRESHOLD : 1;
		unsigned int                 SDMA0_DEVICE_ID : 1;
		unsigned int                                 : 1;
		unsigned int                        RESERVED : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_PUB_REG_TYPE1__VI {
	struct {
		unsigned int                   SDMA0_VM_CNTL : 1;
		unsigned int                 SDMA0_VM_CTX_LO : 1;
		unsigned int                 SDMA0_VM_CTX_HI : 1;
		unsigned int               SDMA0_STATUS2_REG : 1;
		unsigned int               SDMA0_VM_CTX_CNTL : 1;
		unsigned int                        RESERVED : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RD_BURST_CNTL__VI {
	struct {
		unsigned int                        RD_BURST : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_CSA_ADDR_HI__VI {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_CSA_ADDR_LO__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_DUMMY_REG__VI {
	struct {
		unsigned int                           DUMMY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_IB_SUB_REMAIN__VI {
	struct {
		unsigned int                            SIZE : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_MIDCMD_CNTL__VI {
	struct {
		unsigned int                      DATA_VALID : 1;
		unsigned int                       COPY_MODE : 1;
		unsigned int                                 : 2;
		unsigned int                     SPLIT_STATE : 4;
		unsigned int                   ALLOW_PREEMPT : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_MIDCMD_DATA0__VI {
	struct {
		unsigned int                           DATA0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_MIDCMD_DATA1__VI {
	struct {
		unsigned int                           DATA1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_MIDCMD_DATA2__VI {
	struct {
		unsigned int                           DATA2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_MIDCMD_DATA3__VI {
	struct {
		unsigned int                           DATA3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_MIDCMD_DATA4__VI {
	struct {
		unsigned int                           DATA4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_MIDCMD_DATA5__VI {
	struct {
		unsigned int                           DATA5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_PREEMPT__VI {
	struct {
		unsigned int                      IB_PREEMPT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC0_WATERMARK__VI {
	struct {
		unsigned int                  RD_OUTSTANDING : 12;
		unsigned int                                 : 4;
		unsigned int                  WR_OUTSTANDING : 9;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_CSA_ADDR_HI__VI {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_CSA_ADDR_LO__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_DUMMY_REG__VI {
	struct {
		unsigned int                           DUMMY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_IB_SUB_REMAIN__VI {
	struct {
		unsigned int                            SIZE : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_MIDCMD_CNTL__VI {
	struct {
		unsigned int                      DATA_VALID : 1;
		unsigned int                       COPY_MODE : 1;
		unsigned int                                 : 2;
		unsigned int                     SPLIT_STATE : 4;
		unsigned int                   ALLOW_PREEMPT : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_MIDCMD_DATA0__VI {
	struct {
		unsigned int                           DATA0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_MIDCMD_DATA1__VI {
	struct {
		unsigned int                           DATA1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_MIDCMD_DATA2__VI {
	struct {
		unsigned int                           DATA2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_MIDCMD_DATA3__VI {
	struct {
		unsigned int                           DATA3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_MIDCMD_DATA4__VI {
	struct {
		unsigned int                           DATA4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_MIDCMD_DATA5__VI {
	struct {
		unsigned int                           DATA5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_PREEMPT__VI {
	struct {
		unsigned int                      IB_PREEMPT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_RLC1_WATERMARK__VI {
	struct {
		unsigned int                  RD_OUTSTANDING : 12;
		unsigned int                                 : 4;
		unsigned int                  WR_OUTSTANDING : 9;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_STATUS2_REG__VI {
	struct {
		unsigned int                              ID : 2;
		unsigned int                   F32_INSTR_PTR : 14;
		unsigned int                          CMD_OP : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_VERSION__VI {
	struct {
		unsigned int                           VALUE : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_VF_ENABLE__VI {
	struct {
		unsigned int                       VF_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_VIRT_RESET_REQ__VI {
	struct {
		unsigned int                              VF : 16;
		unsigned int                                 : 15;
		unsigned int                              PF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_VM_CNTL__VI {
	struct {
		unsigned int                             CMD : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_VM_CTX_CNTL__VI {
	struct {
		unsigned int                            PRIV : 1;
		unsigned int                                 : 3;
		unsigned int                            VMID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_VM_CTX_HI__VI {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA0_VM_CTX_LO__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_ACTIVE_FCN_ID__VI {
	struct {
		unsigned int                            VFID : 4;
		unsigned int                                 : 27;
		unsigned int                              VF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_ATOMIC_CNTL__VI {
	struct {
		unsigned int                      LOOP_TIMER : 31;
		unsigned int           ATOMIC_RTN_INT_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_ATOMIC_PREOP_HI__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_ATOMIC_PREOP_LO__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_BA_THRESHOLD__VI {
	struct {
		unsigned int                      READ_THRES : 10;
		unsigned int                                 : 6;
		unsigned int                     WRITE_THRES : 10;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_CONTEXT_REG_TYPE0__VI {
	struct {
		unsigned int               SDMA1_GFX_RB_CNTL : 1;
		unsigned int               SDMA1_GFX_RB_BASE : 1;
		unsigned int            SDMA1_GFX_RB_BASE_HI : 1;
		unsigned int               SDMA1_GFX_RB_RPTR : 1;
		unsigned int               SDMA1_GFX_RB_WPTR : 1;
		unsigned int     SDMA1_GFX_RB_WPTR_POLL_CNTL : 1;
		unsigned int  SDMA1_GFX_RB_WPTR_POLL_ADDR_HI : 1;
		unsigned int  SDMA1_GFX_RB_WPTR_POLL_ADDR_LO : 1;
		unsigned int       SDMA1_GFX_RB_RPTR_ADDR_HI : 1;
		unsigned int       SDMA1_GFX_RB_RPTR_ADDR_LO : 1;
		unsigned int               SDMA1_GFX_IB_CNTL : 1;
		unsigned int               SDMA1_GFX_IB_RPTR : 1;
		unsigned int             SDMA1_GFX_IB_OFFSET : 1;
		unsigned int            SDMA1_GFX_IB_BASE_LO : 1;
		unsigned int            SDMA1_GFX_IB_BASE_HI : 1;
		unsigned int               SDMA1_GFX_IB_SIZE : 1;
		unsigned int             SDMA1_GFX_SKIP_CNTL : 1;
		unsigned int        SDMA1_GFX_CONTEXT_STATUS : 1;
		unsigned int              SDMA1_GFX_DOORBELL : 1;
		unsigned int          SDMA1_GFX_CONTEXT_CNTL : 1;
		unsigned int                        RESERVED : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_CONTEXT_REG_TYPE1__VI {
	struct {
		unsigned int                       VOID_REG0 : 7;
		unsigned int          SDMA1_GFX_VIRTUAL_ADDR : 1;
		unsigned int             SDMA1_GFX_APE1_CNTL : 1;
		unsigned int          SDMA1_GFX_DOORBELL_LOG : 1;
		unsigned int             SDMA1_GFX_WATERMARK : 1;
		unsigned int                       VOID_REG2 : 1;
		unsigned int           SDMA1_GFX_CSA_ADDR_LO : 1;
		unsigned int           SDMA1_GFX_CSA_ADDR_HI : 1;
		unsigned int                       VOID_REG3 : 1;
		unsigned int         SDMA1_GFX_IB_SUB_REMAIN : 1;
		unsigned int               SDMA1_GFX_PREEMPT : 1;
		unsigned int             SDMA1_GFX_DUMMY_REG : 1;
		unsigned int                        RESERVED : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_CONTEXT_REG_TYPE2__VI {
	struct {
		unsigned int          SDMA1_GFX_MIDCMD_DATA0 : 1;
		unsigned int          SDMA1_GFX_MIDCMD_DATA1 : 1;
		unsigned int          SDMA1_GFX_MIDCMD_DATA2 : 1;
		unsigned int          SDMA1_GFX_MIDCMD_DATA3 : 1;
		unsigned int          SDMA1_GFX_MIDCMD_DATA4 : 1;
		unsigned int          SDMA1_GFX_MIDCMD_DATA5 : 1;
		unsigned int           SDMA1_GFX_MIDCMD_CNTL : 1;
		unsigned int                        RESERVED : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_EDC_CONFIG__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                         DIS_EDC : 1;
		unsigned int                  ECC_INT_ENABLE : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_CSA_ADDR_HI__VI {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_CSA_ADDR_LO__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_DOORBELL__VI {
	struct {
		unsigned int                          OFFSET : 21;
		unsigned int                                 : 7;
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int                        CAPTURED : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_DOORBELL_LOG__VI {
	struct {
		unsigned int                        BE_ERROR : 1;
		unsigned int                                 : 1;
		unsigned int                            DATA : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_DUMMY_REG__VI {
	struct {
		unsigned int                           DUMMY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_IB_SUB_REMAIN__VI {
	struct {
		unsigned int                            SIZE : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_MIDCMD_CNTL__VI {
	struct {
		unsigned int                      DATA_VALID : 1;
		unsigned int                       COPY_MODE : 1;
		unsigned int                                 : 2;
		unsigned int                     SPLIT_STATE : 4;
		unsigned int                   ALLOW_PREEMPT : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_MIDCMD_DATA0__VI {
	struct {
		unsigned int                           DATA0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_MIDCMD_DATA1__VI {
	struct {
		unsigned int                           DATA1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_MIDCMD_DATA2__VI {
	struct {
		unsigned int                           DATA2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_MIDCMD_DATA3__VI {
	struct {
		unsigned int                           DATA3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_MIDCMD_DATA4__VI {
	struct {
		unsigned int                           DATA4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_MIDCMD_DATA5__VI {
	struct {
		unsigned int                           DATA5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_PREEMPT__VI {
	struct {
		unsigned int                      IB_PREEMPT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_GFX_WATERMARK__VI {
	struct {
		unsigned int                  RD_OUTSTANDING : 12;
		unsigned int                                 : 4;
		unsigned int                  WR_OUTSTANDING : 9;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_ID__VI {
	struct {
		unsigned int                       DEVICE_ID : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_PERF_REG_TYPE0__VI {
	struct {
		unsigned int              SDMA1_PERFMON_CNTL : 1;
		unsigned int       SDMA1_PERFCOUNTER0_RESULT : 1;
		unsigned int       SDMA1_PERFCOUNTER1_RESULT : 1;
		unsigned int                   RESERVED_31_3 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_POWER_CNTL_IDLE__VI {
	struct {
		unsigned int                          DELAY1 : 16;
		unsigned int                          DELAY2 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_PUB_REG_TYPE0__VI {
	struct {
		unsigned int                SDMA1_UCODE_ADDR : 1;
		unsigned int                SDMA1_UCODE_DATA : 1;
		unsigned int                SDMA1_POWER_CNTL : 1;
		unsigned int                  SDMA1_CLK_CTRL : 1;
		unsigned int                      SDMA1_CNTL : 1;
		unsigned int              SDMA1_CHICKEN_BITS : 1;
		unsigned int             SDMA1_TILING_CONFIG : 1;
		unsigned int                      SDMA1_HASH : 1;
		unsigned int                                 : 1;
		unsigned int  SDMA1_SEM_WAIT_FAIL_TIMER_CNTL : 1;
		unsigned int             SDMA1_RB_RPTR_FETCH : 1;
		unsigned int           SDMA1_IB_OFFSET_FETCH : 1;
		unsigned int                   SDMA1_PROGRAM : 1;
		unsigned int                SDMA1_STATUS_REG : 1;
		unsigned int               SDMA1_STATUS1_REG : 1;
		unsigned int             SDMA1_RD_BURST_CNTL : 1;
		unsigned int                     RESERVED_16 : 1;
		unsigned int                     RESERVED_17 : 1;
		unsigned int                  SDMA1_F32_CNTL : 1;
		unsigned int                    SDMA1_FREEZE : 1;
		unsigned int            SDMA1_PHASE0_QUANTUM : 1;
		unsigned int            SDMA1_PHASE1_QUANTUM : 1;
		unsigned int                       VOID_REG0 : 4;
		unsigned int                SDMA1_EDC_CONFIG : 1;
		unsigned int              SDMA1_BA_THRESHOLD : 1;
		unsigned int                 SDMA1_DEVICE_ID : 1;
		unsigned int                                 : 1;
		unsigned int                        RESERVED : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_PUB_REG_TYPE1__VI {
	struct {
		unsigned int                   SDMA1_VM_CNTL : 1;
		unsigned int                 SDMA1_VM_CTX_LO : 1;
		unsigned int                 SDMA1_VM_CTX_HI : 1;
		unsigned int               SDMA1_STATUS2_REG : 1;
		unsigned int               SDMA1_VM_CTX_CNTL : 1;
		unsigned int                        RESERVED : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RD_BURST_CNTL__VI {
	struct {
		unsigned int                        RD_BURST : 2;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_CSA_ADDR_HI__VI {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_CSA_ADDR_LO__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_DUMMY_REG__VI {
	struct {
		unsigned int                           DUMMY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_IB_SUB_REMAIN__VI {
	struct {
		unsigned int                            SIZE : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_MIDCMD_CNTL__VI {
	struct {
		unsigned int                      DATA_VALID : 1;
		unsigned int                       COPY_MODE : 1;
		unsigned int                                 : 2;
		unsigned int                     SPLIT_STATE : 4;
		unsigned int                   ALLOW_PREEMPT : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_MIDCMD_DATA0__VI {
	struct {
		unsigned int                           DATA0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_MIDCMD_DATA1__VI {
	struct {
		unsigned int                           DATA1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_MIDCMD_DATA2__VI {
	struct {
		unsigned int                           DATA2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_MIDCMD_DATA3__VI {
	struct {
		unsigned int                           DATA3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_MIDCMD_DATA4__VI {
	struct {
		unsigned int                           DATA4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_MIDCMD_DATA5__VI {
	struct {
		unsigned int                           DATA5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_PREEMPT__VI {
	struct {
		unsigned int                      IB_PREEMPT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC0_WATERMARK__VI {
	struct {
		unsigned int                  RD_OUTSTANDING : 12;
		unsigned int                                 : 4;
		unsigned int                  WR_OUTSTANDING : 9;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_CSA_ADDR_HI__VI {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_CSA_ADDR_LO__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_DUMMY_REG__VI {
	struct {
		unsigned int                           DUMMY : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_IB_SUB_REMAIN__VI {
	struct {
		unsigned int                            SIZE : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_MIDCMD_CNTL__VI {
	struct {
		unsigned int                      DATA_VALID : 1;
		unsigned int                       COPY_MODE : 1;
		unsigned int                                 : 2;
		unsigned int                     SPLIT_STATE : 4;
		unsigned int                   ALLOW_PREEMPT : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_MIDCMD_DATA0__VI {
	struct {
		unsigned int                           DATA0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_MIDCMD_DATA1__VI {
	struct {
		unsigned int                           DATA1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_MIDCMD_DATA2__VI {
	struct {
		unsigned int                           DATA2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_MIDCMD_DATA3__VI {
	struct {
		unsigned int                           DATA3 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_MIDCMD_DATA4__VI {
	struct {
		unsigned int                           DATA4 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_MIDCMD_DATA5__VI {
	struct {
		unsigned int                           DATA5 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_PREEMPT__VI {
	struct {
		unsigned int                      IB_PREEMPT : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_RLC1_WATERMARK__VI {
	struct {
		unsigned int                  RD_OUTSTANDING : 12;
		unsigned int                                 : 4;
		unsigned int                  WR_OUTSTANDING : 9;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_STATUS2_REG__VI {
	struct {
		unsigned int                              ID : 2;
		unsigned int                   F32_INSTR_PTR : 14;
		unsigned int                          CMD_OP : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_VERSION__VI {
	struct {
		unsigned int                           VALUE : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_VF_ENABLE__VI {
	struct {
		unsigned int                       VF_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_VIRT_RESET_REQ__VI {
	struct {
		unsigned int                              VF : 16;
		unsigned int                                 : 15;
		unsigned int                              PF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_VM_CNTL__VI {
	struct {
		unsigned int                             CMD : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_VM_CTX_CNTL__VI {
	struct {
		unsigned int                            PRIV : 1;
		unsigned int                                 : 3;
		unsigned int                            VMID : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_VM_CTX_HI__VI {
	struct {
		unsigned int                            ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SDMA1_VM_CTX_LO__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                            ADDR : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_ACTIVE_FCN_ID__VI {
	struct {
		unsigned int                            VFID : 4;
		unsigned int                                 : 27;
		unsigned int                              VF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_MAILBOX_CLIENTCONFIG_EXTRA__VI {
	struct {
		unsigned int                    VCE1_CLIENT0 : 5;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_PERFCOUNTER0_RESULT__VI {
	struct {
		unsigned int                      PERF_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_PERFCOUNTER1_RESULT__VI {
	struct {
		unsigned int                      PERF_COUNT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_PERFMON_CNTL__VI {
	struct {
		unsigned int                    PERF_ENABLE0 : 1;
		unsigned int                     PERF_CLEAR0 : 1;
		unsigned int                       PERF_SEL0 : 8;
		unsigned int                    PERF_ENABLE1 : 1;
		unsigned int                     PERF_CLEAR1 : 1;
		unsigned int                       PERF_SEL1 : 8;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_VF_ENABLE__VI {
	struct {
		unsigned int                           VALUE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SEM_VIRT_RESET_REQ__VI {
	struct {
		unsigned int                              VF : 16;
		unsigned int                                 : 15;
		unsigned int                              PF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SE_CAC_CGTT_CLK_CTRL__VI {
	struct {
		unsigned int                        ON_DELAY : 4;
		unsigned int                  OFF_HYSTERESIS : 8;
		unsigned int                                 : 18;
		unsigned int               SOFT_OVERRIDE_DYN : 1;
		unsigned int               SOFT_OVERRIDE_REG : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION0__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION1__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION10__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION11__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION12__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION13__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION14__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION15__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION16__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION17__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION2__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION3__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION4__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION5__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION6__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION7__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION8__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SINK_DESCRIPTION9__VI {
	struct {
		unsigned int                     DESCRIPTION : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMBUS_BACO_DUMMY__VI {
	struct {
		unsigned int           SMBUS_BACO_DUMMY_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_BIF_VDDGFX_PWR_STATUS__VI {
	struct {
		unsigned int              VDDGFX_GFX_PWR_OFF : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_CONTROL__VI {
	struct {
		unsigned int              DISPLAY0_FORCE_VBI : 1;
		unsigned int              DISPLAY1_FORCE_VBI : 1;
		unsigned int              DISPLAY2_FORCE_VBI : 1;
		unsigned int              DISPLAY3_FORCE_VBI : 1;
		unsigned int              DISPLAY4_FORCE_VBI : 1;
		unsigned int              DISPLAY5_FORCE_VBI : 1;
		unsigned int            DISPLAY_V0_FORCE_VBI : 1;
		unsigned int                                 : 9;
		unsigned int                SMU_DC_INT_CLEAR : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_DATA_0__VI {
	struct {
		unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_DATA_1__VI {
	struct {
		unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_DATA_2__VI {
	struct {
		unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_DATA_3__VI {
	struct {
		unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_DATA_4__VI {
	struct {
		unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_DATA_5__VI {
	struct {
		unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_DATA_6__VI {
	struct {
		unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_DATA_7__VI {
	struct {
		unsigned int                    SMC_IND_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_INDEX_0__VI {
	struct {
		unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_INDEX_1__VI {
	struct {
		unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_INDEX_2__VI {
	struct {
		unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_INDEX_3__VI {
	struct {
		unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_INDEX_4__VI {
	struct {
		unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_INDEX_5__VI {
	struct {
		unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_INDEX_6__VI {
	struct {
		unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_IND_INDEX_7__VI {
	struct {
		unsigned int                    SMC_IND_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_INTERRUPT_CONTROL__VI {
	struct {
		unsigned int               DC_SMU_INT_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int               DC_SMU_INT_STATUS : 1;
		unsigned int                                 : 11;
		unsigned int                DC_SMU_INT_EVENT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_MP1_RLC2MP_RESP__VI {
	struct {
		unsigned int                         CONTENT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_MP1_SRBM2P_MSG_5__VI {
	struct {
		unsigned int                         CONTENT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_0__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_1__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_10__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_100__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_101__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_102__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_103__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_104__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_105__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_106__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_107__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_108__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_109__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_11__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_110__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_111__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_112__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_113__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_114__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_115__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_116__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_117__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_118__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_119__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_12__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_120__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_121__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_122__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_123__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_124__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_125__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_126__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_127__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_13__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_14__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_15__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_16__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_17__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_18__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_19__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_2__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_20__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_21__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_22__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_23__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_24__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_25__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_26__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_27__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_28__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_29__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_3__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_30__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_31__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_32__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_33__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_34__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_35__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_36__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_37__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_38__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_39__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_4__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_40__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_41__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_42__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_43__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_44__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_45__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_46__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_47__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_48__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_49__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_5__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_50__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_51__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_52__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_53__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_54__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_55__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_56__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_57__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_58__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_59__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_6__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_60__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_61__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_62__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_63__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_64__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_65__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_66__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_67__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_68__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_69__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_7__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_70__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_71__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_72__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_73__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_74__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_75__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_76__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_77__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_78__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_79__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_8__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_80__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_81__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_82__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_83__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_84__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_85__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_86__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_87__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_88__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_89__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_9__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_90__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_91__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_92__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_93__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_94__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_95__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_96__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_97__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_98__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_PM_STATUS_99__VI {
	struct {
		unsigned int                            DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SMU_RLC_RESPONSE__VI {
	struct {
		unsigned int                            RESP : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SM_CONTROL2__VI {
	struct {
		unsigned int                         SM_MODE : 3;
		unsigned int                                 : 1;
		unsigned int              SM_FRAME_ALTERNATE : 1;
		unsigned int              SM_FIELD_ALTERNATE : 1;
		unsigned int                                 : 2;
		unsigned int         SM_FORCE_NEXT_FRAME_POL : 2;
		unsigned int                                 : 6;
		unsigned int           SM_FORCE_NEXT_TOP_POL : 2;
		unsigned int                                 : 6;
		unsigned int            SM_CURRENT_FRAME_POL : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_1__VI {
	struct {
		unsigned int               RefClockFrequency : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_10__VI {
	struct {
		unsigned int                     G5TrainTime : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_11__VI {
	struct {
		unsigned int                  DelayMpllPwron : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_12__VI {
	struct {
		unsigned int            VoltageChangeTimeout : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_13__VI {
	struct {
		unsigned int               HandshakeDisables : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_14__VI {
	struct {
		unsigned int               DisplayPhy4Config : 8;
		unsigned int               DisplayPhy3Config : 8;
		unsigned int               DisplayPhy2Config : 8;
		unsigned int               DisplayPhy1Config : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_15__VI {
	struct {
		unsigned int               DisplayPhy8Config : 8;
		unsigned int               DisplayPhy7Config : 8;
		unsigned int               DisplayPhy6Config : 8;
		unsigned int               DisplayPhy5Config : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_16__VI {
	struct {
		unsigned int         AverageGraphicsActivity : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_17__VI {
	struct {
		unsigned int           AverageMemoryActivity : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_18__VI {
	struct {
		unsigned int              AverageGioActivity : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_19__VI {
	struct {
		unsigned int            PCIeDpmEnabledLevels : 8;
		unsigned int            LClkDpmEnabledLevels : 8;
		unsigned int            MClkDpmEnabledLevels : 8;
		unsigned int            SClkDpmEnabledLevels : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_2__VI {
	struct {
		unsigned int                   PmTimerPeriod : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_20__VI {
	struct {
		unsigned int             VCEDpmEnabledLevels : 8;
		unsigned int             ACPDpmEnabledLevels : 8;
		unsigned int            SAMUDpmEnabledLevels : 8;
		unsigned int             UVDDpmEnabledLevels : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_21__VI {
	struct {
		unsigned int                 DRAM_LOG_ADDR_H : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_22__VI {
	struct {
		unsigned int                 DRAM_LOG_ADDR_L : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_23__VI {
	struct {
		unsigned int             DRAM_LOG_PHY_ADDR_H : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_24__VI {
	struct {
		unsigned int             DRAM_LOG_PHY_ADDR_L : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_25__VI {
	struct {
		unsigned int              DRAM_LOG_BUFF_SIZE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_26__VI {
	struct {
		unsigned int                   UlvEnterCount : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_27__VI {
	struct {
		unsigned int                         UlvTime : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_28__VI {
	struct {
		unsigned int                 UcodeLoadStatus : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_29__VI {
	struct {
		unsigned int                      Reserved_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_3__VI {
	struct {
		unsigned int                  FeatureEnables : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_30__VI {
	struct {
		unsigned int                      Reserved_1 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_4__VI {
	struct {
		unsigned int                    PreVBlankGap : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_5__VI {
	struct {
		unsigned int                   VBlankTimeout : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_6__VI {
	struct {
		unsigned int                    TrainTimeGap : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_7__VI {
	struct {
		unsigned int                  MvddSwitchTime : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_8__VI {
	struct {
		unsigned int            LongestAcpiTrainTime : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SOFT_REGISTERS_TABLE_9__VI {
	struct {
		unsigned int                       AcpiDelay : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_COMPUTE_WF_CTX_SAVE__VI {
	struct {
		unsigned int                        INITIATE : 1;
		unsigned int                GDS_INTERRUPT_EN : 1;
		unsigned int               DONE_INTERRUPT_EN : 1;
		unsigned int                                 : 27;
		unsigned int                    GDS_REQ_BUSY : 1;
		unsigned int                       SAVE_BUSY : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_CONFIG_CNTL_2__VI {
	struct {
		unsigned int CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD : 4;
		unsigned int CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD : 4;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_DSM_CNTL__VI {
	struct {
		unsigned int     Sel_DSM_SPI_Irritator_data0 : 1;
		unsigned int     Sel_DSM_SPI_Irritator_data1 : 1;
		unsigned int         SPI_Enable_Single_Write : 1;
		unsigned int                          UNUSED : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_EDC_CNT__VI {
	struct {
		unsigned int                             SED : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_GFX_CNTL__VI {
	struct {
		unsigned int                    RESET_COUNTS : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_12__VI {
	struct {
		unsigned int                            VGPR : 4;
		unsigned int                            SGPR : 4;
		unsigned int                             LDS : 4;
		unsigned int                           WAVES : 3;
		unsigned int                        BARRIERS : 4;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_13__VI {
	struct {
		unsigned int                            VGPR : 4;
		unsigned int                            SGPR : 4;
		unsigned int                             LDS : 4;
		unsigned int                           WAVES : 3;
		unsigned int                        BARRIERS : 4;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_14__VI {
	struct {
		unsigned int                            VGPR : 4;
		unsigned int                            SGPR : 4;
		unsigned int                             LDS : 4;
		unsigned int                           WAVES : 3;
		unsigned int                        BARRIERS : 4;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_CU_15__VI {
	struct {
		unsigned int                            VGPR : 4;
		unsigned int                            SGPR : 4;
		unsigned int                             LDS : 4;
		unsigned int                           WAVES : 3;
		unsigned int                        BARRIERS : 4;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_12__VI {
	struct {
		unsigned int                              EN : 1;
		unsigned int                       TYPE_MASK : 15;
		unsigned int                      QUEUE_MASK : 8;
		unsigned int              RESERVE_SPACE_ONLY : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_13__VI {
	struct {
		unsigned int                              EN : 1;
		unsigned int                       TYPE_MASK : 15;
		unsigned int                      QUEUE_MASK : 8;
		unsigned int              RESERVE_SPACE_ONLY : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_14__VI {
	struct {
		unsigned int                              EN : 1;
		unsigned int                       TYPE_MASK : 15;
		unsigned int                      QUEUE_MASK : 8;
		unsigned int              RESERVE_SPACE_ONLY : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_RESOURCE_RESERVE_EN_CU_15__VI {
	struct {
		unsigned int                              EN : 1;
		unsigned int                       TYPE_MASK : 15;
		unsigned int                      QUEUE_MASK : 8;
		unsigned int              RESERVE_SPACE_ONLY : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPI_START_PHASE__VI {
	struct {
		unsigned int                VGPR_START_PHASE : 2;
		unsigned int                SGPR_START_PHASE : 2;
		unsigned int                WAVE_START_PHASE : 2;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_CONFIG0_0__VI {
	struct {
		unsigned int                     SPMI_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int      SPMI_PATH_NUM_TIMING_FLOPS : 5;
		unsigned int     SPMI_SIGNALING_DELAY_CYCLES : 5;
		unsigned int      SPMI_SIGNALING_HOLD_CYCLES : 5;
		unsigned int   SPMI_PATH_ENABLE_DELAY_CYCLES : 5;
		unsigned int  SPMI_PATH_DISABLE_DELAY_CYCLES : 5;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_CONFIG1_0__VI {
	struct {
		unsigned int SPMI_SIGNALING_RESET_HOLD_CYCLES : 5;
		unsigned int                 SPMI_CHAIN_SIZE : 11;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_FORCE_CLOCK_GATERS__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 7;
		unsigned int                                 : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_SPARE__VI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_SPARE_EX__VI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPMI_SRAM_CLK_GATER__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 10;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SPU_PORT_STATUS__VI {
	struct {
		unsigned int                        RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_ATC_EDC_GATCL1_CNT__VI {
	struct {
		unsigned int                 ICACHE_DATA_SEC : 8;
		unsigned int                                 : 8;
		unsigned int                 DCACHE_DATA_SEC : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_DSM_CNTL__VI {
	struct {
		unsigned int           SEL_DATA_ICACHE_BANKA : 2;
		unsigned int       EN_SINGLE_WR_ICACHE_BANKA : 1;
		unsigned int           SEL_DATA_ICACHE_BANKB : 2;
		unsigned int       EN_SINGLE_WR_ICACHE_BANKB : 1;
		unsigned int           SEL_DATA_ICACHE_BANKC : 2;
		unsigned int       EN_SINGLE_WR_ICACHE_BANKC : 1;
		unsigned int           SEL_DATA_ICACHE_BANKD : 2;
		unsigned int       EN_SINGLE_WR_ICACHE_BANKD : 1;
		unsigned int          SEL_DATA_ICACHE_GATCL1 : 2;
		unsigned int      EN_SINGLE_WR_ICACHE_GATCL1 : 1;
		unsigned int           SEL_DATA_DCACHE_BANKA : 2;
		unsigned int       EN_SINGLE_WR_DCACHE_BANKA : 1;
		unsigned int           SEL_DATA_DCACHE_BANKB : 2;
		unsigned int       EN_SINGLE_WR_DCACHE_BANKB : 1;
		unsigned int           SEL_DATA_DCACHE_BANKC : 2;
		unsigned int       EN_SINGLE_WR_DCACHE_BANKC : 1;
		unsigned int           SEL_DATA_DCACHE_BANKD : 2;
		unsigned int       EN_SINGLE_WR_DCACHE_BANKD : 1;
		unsigned int          SEL_DATA_DCACHE_GATCL1 : 2;
		unsigned int      EN_SINGLE_WR_DCACHE_GATCL1 : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_EDC_CNT__VI {
	struct {
		unsigned int                        INST_SEC : 8;
		unsigned int                        INST_DED : 8;
		unsigned int                        DATA_SEC : 8;
		unsigned int                        DATA_DED : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_GATCL1_CNTL__VI {
	struct {
		unsigned int                        RESERVED : 18;
		unsigned int      DCACHE_INVALIDATE_ALL_VMID : 1;
		unsigned int               DCACHE_FORCE_MISS : 1;
		unsigned int           DCACHE_FORCE_IN_ORDER : 1;
		unsigned int   DCACHE_REDUCE_FIFO_DEPTH_BY_2 : 2;
		unsigned int   DCACHE_REDUCE_CACHE_SIZE_BY_2 : 2;
		unsigned int      ICACHE_INVALIDATE_ALL_VMID : 1;
		unsigned int               ICACHE_FORCE_MISS : 1;
		unsigned int           ICACHE_FORCE_IN_ORDER : 1;
		unsigned int   ICACHE_REDUCE_FIFO_DEPTH_BY_2 : 2;
		unsigned int   ICACHE_REDUCE_CACHE_SIZE_BY_2 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQC_WRITEBACK__VI {
	struct {
		unsigned int                             DWB : 1;
		unsigned int                           DIRTY : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_DSM_CNTL__VI {
	struct {
		unsigned int               WAVEFRONT_STALL_0 : 1;
		unsigned int               WAVEFRONT_STALL_1 : 1;
		unsigned int              SPI_BACKPRESSURE_0 : 1;
		unsigned int              SPI_BACKPRESSURE_1 : 1;
		unsigned int                                 : 4;
		unsigned int    SEL_DSM_SGPR_IRRITATOR_DATA0 : 1;
		unsigned int    SEL_DSM_SGPR_IRRITATOR_DATA1 : 1;
		unsigned int        SGPR_ENABLE_SINGLE_WRITE : 1;
		unsigned int                                 : 5;
		unsigned int     SEL_DSM_LDS_IRRITATOR_DATA0 : 1;
		unsigned int     SEL_DSM_LDS_IRRITATOR_DATA1 : 1;
		unsigned int       LDS_ENABLE_SINGLE_WRITE01 : 1;
		unsigned int     SEL_DSM_LDS_IRRITATOR_DATA2 : 1;
		unsigned int     SEL_DSM_LDS_IRRITATOR_DATA3 : 1;
		unsigned int       LDS_ENABLE_SINGLE_WRITE23 : 1;
		unsigned int                                 : 2;
		unsigned int      SEL_DSM_SP_IRRITATOR_DATA0 : 1;
		unsigned int      SEL_DSM_SP_IRRITATOR_DATA1 : 1;
		unsigned int          SP_ENABLE_SINGLE_WRITE : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_EDC_DED_CNT__VI {
	struct {
		unsigned int                         LDS_DED : 8;
		unsigned int                        SGPR_DED : 8;
		unsigned int                        VGPR_DED : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_EDC_INFO__VI {
	struct {
		unsigned int                         WAVE_ID : 4;
		unsigned int                         SIMD_ID : 2;
		unsigned int                          SOURCE : 3;
		unsigned int                           VM_ID : 4;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_EDC_SEC_CNT__VI {
	struct {
		unsigned int                         LDS_SEC : 8;
		unsigned int                        SGPR_SEC : 8;
		unsigned int                        VGPR_SEC : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_M0_GPR_IDX_WORD__VI {
	struct {
		unsigned int                           INDEX : 8;
		unsigned int                                 : 4;
		unsigned int                       VSRC0_REL : 1;
		unsigned int                       VSRC1_REL : 1;
		unsigned int                       VSRC2_REL : 1;
		unsigned int                        VDST_REL : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_SMEM_0__VI {
	struct {
		unsigned int                           SBASE : 6;
		unsigned int                           SDATA : 7;
		unsigned int                                 : 3;
		unsigned int                             GLC : 1;
		unsigned int                             IMM : 1;
		unsigned int                              OP : 8;
		unsigned int                        ENCODING : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_SMEM_1__VI {
	struct {
		unsigned int                          OFFSET : 20;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VOP_DPP__VI {
	struct {
		unsigned int                            SRC0 : 8;
		unsigned int                        DPP_CTRL : 9;
		unsigned int                                 : 2;
		unsigned int                      BOUND_CTRL : 1;
		unsigned int                        SRC0_NEG : 1;
		unsigned int                        SRC0_ABS : 1;
		unsigned int                        SRC1_NEG : 1;
		unsigned int                        SRC1_ABS : 1;
		unsigned int                       BANK_MASK : 4;
		unsigned int                        ROW_MASK : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_VOP_SDWA__VI {
	struct {
		unsigned int                            SRC0 : 8;
		unsigned int                         DST_SEL : 3;
		unsigned int                      DST_UNUSED : 2;
		unsigned int                           CLAMP : 1;
		unsigned int                                 : 2;
		unsigned int                        SRC0_SEL : 3;
		unsigned int                       SRC0_SEXT : 1;
		unsigned int                        SRC0_NEG : 1;
		unsigned int                        SRC0_ABS : 1;
		unsigned int                                 : 2;
		unsigned int                        SRC1_SEL : 3;
		unsigned int                       SRC1_SEXT : 1;
		unsigned int                        SRC1_NEG : 1;
		unsigned int                        SRC1_ABS : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WAVE_IB_DBG1__VI {
	struct {
		unsigned int                          IXNACK : 1;
		unsigned int                           XNACK : 1;
		unsigned int                   TA_NEED_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                            XCNT : 4;
		unsigned int                            QCNT : 4;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WREXEC_EXEC_HI__VI {
	struct {
		unsigned int                         ADDR_HI : 16;
		unsigned int                                 : 10;
		unsigned int                      FIRST_WAVE : 1;
		unsigned int                             ATC : 1;
		unsigned int                           MTYPE : 3;
		unsigned int                             MSB : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SQ_WREXEC_EXEC_LO__VI {
	struct {
		unsigned int                         ADDR_LO : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_CREDIT_RECOVER__VI {
	struct {
		unsigned int              CREDIT_RECOVER_BIF : 1;
		unsigned int              CREDIT_RECOVER_SMU : 1;
		unsigned int               CREDIT_RECOVER_DC : 1;
		unsigned int            CREDIT_RECOVER_GIONB : 1;
		unsigned int              CREDIT_RECOVER_ACP : 1;
		unsigned int             CREDIT_RECOVER_XDMA : 1;
		unsigned int              CREDIT_RECOVER_ODE : 1;
		unsigned int            CREDIT_RECOVER_REGBB : 1;
		unsigned int              CREDIT_RECOVER_VP8 : 1;
		unsigned int             CREDIT_RECOVER_GRBM : 1;
		unsigned int              CREDIT_RECOVER_UVD : 1;
		unsigned int             CREDIT_RECOVER_VCE0 : 1;
		unsigned int             CREDIT_RECOVER_VCE1 : 1;
		unsigned int              CREDIT_RECOVER_ISP : 1;
		unsigned int              CREDIT_RECOVER_SAM : 1;
		unsigned int              CREDIT_RECOVER_MCB : 1;
		unsigned int             CREDIT_RECOVER_MCC0 : 1;
		unsigned int             CREDIT_RECOVER_MCC1 : 1;
		unsigned int             CREDIT_RECOVER_MCC2 : 1;
		unsigned int             CREDIT_RECOVER_MCC3 : 1;
		unsigned int             CREDIT_RECOVER_MCC4 : 1;
		unsigned int             CREDIT_RECOVER_MCC5 : 1;
		unsigned int             CREDIT_RECOVER_MCC6 : 1;
		unsigned int             CREDIT_RECOVER_MCC7 : 1;
		unsigned int             CREDIT_RECOVER_MCD0 : 1;
		unsigned int             CREDIT_RECOVER_MCD1 : 1;
		unsigned int             CREDIT_RECOVER_MCD2 : 1;
		unsigned int             CREDIT_RECOVER_MCD3 : 1;
		unsigned int             CREDIT_RECOVER_MCD4 : 1;
		unsigned int             CREDIT_RECOVER_MCD5 : 1;
		unsigned int             CREDIT_RECOVER_MCD6 : 1;
		unsigned int             CREDIT_RECOVER_MCD7 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_CREDIT_RECOVER_CNTL__VI {
	struct {
		unsigned int             CREDIT_RECOVER_TIME : 12;
		unsigned int                                 : 19;
		unsigned int           CREDIT_RECOVER_ENABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_CREDIT_RESET__VI {
	struct {
		unsigned int                CREDIT_RESET_BIF : 1;
		unsigned int                CREDIT_RESET_SMU : 1;
		unsigned int                 CREDIT_RESET_DC : 1;
		unsigned int              CREDIT_RESET_GIONB : 1;
		unsigned int                CREDIT_RESET_ACP : 1;
		unsigned int               CREDIT_RESET_XDMA : 1;
		unsigned int                CREDIT_RESET_ODE : 1;
		unsigned int              CREDIT_RESET_REGBB : 1;
		unsigned int                CREDIT_RESET_VP8 : 1;
		unsigned int               CREDIT_RESET_GRBM : 1;
		unsigned int                CREDIT_RESET_UVD : 1;
		unsigned int               CREDIT_RESET_VCE0 : 1;
		unsigned int               CREDIT_RESET_VCE1 : 1;
		unsigned int                CREDIT_RESET_ISP : 1;
		unsigned int                CREDIT_RESET_SAM : 1;
		unsigned int                CREDIT_RESET_MCB : 1;
		unsigned int               CREDIT_RESET_MCC0 : 1;
		unsigned int               CREDIT_RESET_MCC1 : 1;
		unsigned int               CREDIT_RESET_MCC2 : 1;
		unsigned int               CREDIT_RESET_MCC3 : 1;
		unsigned int               CREDIT_RESET_MCC4 : 1;
		unsigned int               CREDIT_RESET_MCC5 : 1;
		unsigned int               CREDIT_RESET_MCC6 : 1;
		unsigned int               CREDIT_RESET_MCC7 : 1;
		unsigned int               CREDIT_RESET_MCD0 : 1;
		unsigned int               CREDIT_RESET_MCD1 : 1;
		unsigned int               CREDIT_RESET_MCD2 : 1;
		unsigned int               CREDIT_RESET_MCD3 : 1;
		unsigned int               CREDIT_RESET_MCD4 : 1;
		unsigned int               CREDIT_RESET_MCD5 : 1;
		unsigned int               CREDIT_RESET_MCD6 : 1;
		unsigned int               CREDIT_RESET_MCD7 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DEBUG_SNAPSHOT2__VI {
	struct {
		unsigned int                        VCE1_RDY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DSM_TRIG_CNTL0__VI {
	struct {
		unsigned int                   DSM_TRIG_ADDR : 16;
		unsigned int                     DSM_TRIG_OP : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DSM_TRIG_CNTL1__VI {
	struct {
		unsigned int                     DSM_TRIG_WD : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DSM_TRIG_MASK0__VI {
	struct {
		unsigned int              DSM_TRIG_ADDR_MASK : 16;
		unsigned int                DSM_TRIG_OP_MASK : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_DSM_TRIG_MASK1__VI {
	struct {
		unsigned int                DSM_TRIG_WD_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_FIREWALL_ERROR_ADDR__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int                  ACCESS_ADDRESS : 16;
		unsigned int                                 : 1;
		unsigned int                       ACCESS_VF : 1;
		unsigned int                     ACCESS_VFID : 4;
		unsigned int                                 : 7;
		unsigned int              FIREWALL_VIOLATION : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_FIREWALL_ERROR_SRC__VI {
	struct {
		unsigned int            ACCESS_REQUESTER_BIF : 1;
		unsigned int            ACCESS_REQUESTER_ACP : 1;
		unsigned int         ACCESS_REQUESTER_SAMSCP : 1;
		unsigned int         ACCESS_REQUESTER_SAMMSP : 1;
		unsigned int                                 : 1;
		unsigned int            ACCESS_REQUESTER_TST : 1;
		unsigned int          ACCESS_REQUESTER_SDMA3 : 1;
		unsigned int          ACCESS_REQUESTER_SDMA2 : 1;
		unsigned int          ACCESS_REQUESTER_SDMA1 : 1;
		unsigned int          ACCESS_REQUESTER_SDMA0 : 1;
		unsigned int            ACCESS_REQUESTER_UVD : 1;
		unsigned int           ACCESS_REQUESTER_VCE0 : 1;
		unsigned int           ACCESS_REQUESTER_GRBM : 1;
		unsigned int            ACCESS_REQUESTER_SMU : 1;
		unsigned int           ACCESS_REQUESTER_PEER : 1;
		unsigned int            ACCESS_REQUESTER_CPU : 1;
		unsigned int            ACCESS_REQUESTER_ISP : 1;
		unsigned int           ACCESS_REQUESTER_VCE1 : 1;
		unsigned int         ACCESS_REQUESTER_RLCHYP : 1;
		unsigned int         ACCESS_REQUESTER_SMUHYP : 1;
		unsigned int         ACCESS_REQUESTER_BIFHYP : 1;
		unsigned int                                 : 3;
		unsigned int        RAERR_FIREWALL_VIOLATION : 1;
		unsigned int   RAERR_HAR_REGIONSIZE_OVERFLOW : 1;
		unsigned int         RAERR_BIF_ADDR_OVERFLOW : 1;
		unsigned int RAERR_P2SRP_REGIONSIZE_OVERFLOW : 1;
		unsigned int  RAERR_P2SRP_FIREWALL_VIOLATION : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_GFX_CNTL_DATA__VI {
	struct {
		unsigned int                          PIPEID : 2;
		unsigned int                            MEID : 2;
		unsigned int                            VMID : 4;
		unsigned int                         QUEUEID : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_GFX_CNTL_SELECT__VI {
	struct {
		unsigned int               SRBM_GFX_CNTL_SEL : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_ISP_CLKEN_CNTL__VI {
	struct {
		unsigned int                PREFIX_DELAY_CNT : 4;
		unsigned int                                 : 4;
		unsigned int                  POST_DELAY_CNT : 5;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_ISP_DOMAIN_ADDR0__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_ISP_DOMAIN_ADDR1__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_ISP_DOMAIN_ADDR2__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_MC_DOMAIN_ADDR0__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_MC_DOMAIN_ADDR1__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_MC_DOMAIN_ADDR2__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_MC_DOMAIN_ADDR3__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_MC_DOMAIN_ADDR4__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_MC_DOMAIN_ADDR5__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_MC_DOMAIN_ADDR6__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_READ_CNTL__VI {
	struct {
		unsigned int                    READ_TIMEOUT : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_READ_ERROR2__VI {
	struct {
		unsigned int              READ_REQUESTER_ACP : 1;
		unsigned int              READ_REQUESTER_ISP : 1;
		unsigned int             READ_REQUESTER_VCE1 : 1;
		unsigned int                                 : 20;
		unsigned int                         READ_VF : 1;
		unsigned int                       READ_VFID : 4;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SAM_DOMAIN_ADDR0__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SAM_DOMAIN_ADDR1__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SAM_DOMAIN_ADDR2__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SDMA_DOMAIN_ADDR0__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SDMA_DOMAIN_ADDR1__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SDMA_DOMAIN_ADDR2__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SDMA_DOMAIN_ADDR3__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_STATUS3__VI {
	struct {
		unsigned int                       MCC0_BUSY : 1;
		unsigned int                       MCC1_BUSY : 1;
		unsigned int                       MCC2_BUSY : 1;
		unsigned int                       MCC3_BUSY : 1;
		unsigned int                       MCC4_BUSY : 1;
		unsigned int                       MCC5_BUSY : 1;
		unsigned int                       MCC6_BUSY : 1;
		unsigned int                       MCC7_BUSY : 1;
		unsigned int                       MCD0_BUSY : 1;
		unsigned int                       MCD1_BUSY : 1;
		unsigned int                       MCD2_BUSY : 1;
		unsigned int                       MCD3_BUSY : 1;
		unsigned int                       MCD4_BUSY : 1;
		unsigned int                       MCD5_BUSY : 1;
		unsigned int                       MCD6_BUSY : 1;
		unsigned int                       MCD7_BUSY : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SYS_DOMAIN_ADDR0__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SYS_DOMAIN_ADDR1__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SYS_DOMAIN_ADDR2__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SYS_DOMAIN_ADDR3__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SYS_DOMAIN_ADDR4__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SYS_DOMAIN_ADDR5__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_SYS_DOMAIN_ADDR6__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_UVD_DOMAIN_ADDR0__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_UVD_DOMAIN_ADDR1__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_UVD_DOMAIN_ADDR2__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_VCE_DOMAIN_ADDR0__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_VCE_DOMAIN_ADDR1__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_VCE_DOMAIN_ADDR2__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_VF_ENABLE__VI {
	struct {
		unsigned int                       VF_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_VIRT_CNTL__VI {
	struct {
		unsigned int                 VF_WRITE_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_VIRT_RESET_REQ__VI {
	struct {
		unsigned int                              VF : 16;
		unsigned int                                 : 15;
		unsigned int                              PF : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_VP8_CLKEN_CNTL__VI {
	struct {
		unsigned int                PREFIX_DELAY_CNT : 4;
		unsigned int                                 : 4;
		unsigned int                  POST_DELAY_CNT : 5;
		unsigned int                                 : 19;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SRBM_VP8_DOMAIN_ADDR0__VI {
	struct {
		unsigned int                         ADDR_LO : 16;
		unsigned int                         ADDR_HI : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_COMMAND_0__VI {
	struct {
		unsigned int                                 : 15;
		unsigned int              BIF_STRAPREG_RESET : 1;
		unsigned int               BIF0_GLOBAL_RESET : 1;
		unsigned int                BIF0_CALIB_RESET : 1;
		unsigned int                 BIF0_CORE_RESET : 1;
		unsigned int             BIF0_REGISTER_RESET : 1;
		unsigned int                  BIF0_PHY_RESET : 1;
		unsigned int               BIF0_STICKY_RESET : 1;
		unsigned int               BIF0_CONFIG_RESET : 1;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_COMMAND_1__VI {
	struct {
		unsigned int                       SWITCHCLK : 1;
		unsigned int                                 : 1;
		unsigned int                    RESETLANEMUX : 1;
		unsigned int                   RESETWRAPREGS : 1;
		unsigned int                      RESETSRBM0 : 1;
		unsigned int                      RESETSRBM1 : 1;
		unsigned int                         RESETLC : 1;
		unsigned int                                 : 1;
		unsigned int                    SYNCIDLEPIF0 : 1;
		unsigned int                    SYNCIDLEPIF1 : 1;
		unsigned int                                 : 3;
		unsigned int                       RESETMNTR : 1;
		unsigned int                       RESETHLTR : 1;
		unsigned int                        RESETCPM : 1;
		unsigned int                       RESETPIF0 : 1;
		unsigned int                       RESETPIF1 : 1;
		unsigned int                                 : 2;
		unsigned int                    RESETIMPARB0 : 1;
		unsigned int                    RESETIMPARB1 : 1;
		unsigned int                                 : 2;
		unsigned int                       RESETPHY0 : 1;
		unsigned int                       RESETPHY1 : 1;
		unsigned int                                 : 2;
		unsigned int                     TOGGLESTRAP : 1;
		unsigned int                        CMDCFGEN : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_COMMAND_STATUS__VI {
	struct {
		unsigned int                     RECONFIGURE : 1;
		unsigned int                    ATOMIC_RESET : 1;
		unsigned int                                 : 14;
		unsigned int                  RESET_COMPLETE : 1;
		unsigned int                      WAIT_STATE : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_CONTROL_0__VI {
	struct {
		unsigned int                                 : 15;
		unsigned int          BIF_STRAPREG_RESETRCEN : 1;
		unsigned int           BIF0_GLOBAL_RESETRCEN : 1;
		unsigned int            BIF0_CALIB_RESETRCEN : 1;
		unsigned int             BIF0_CORE_RESETRCEN : 1;
		unsigned int         BIF0_REGISTER_RESETRCEN : 1;
		unsigned int              BIF0_PHY_RESETRCEN : 1;
		unsigned int           BIF0_STICKY_RESETRCEN : 1;
		unsigned int           BIF0_CONFIG_RESETRCEN : 1;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_CONTROL_1__VI {
	struct {
		unsigned int                  SWITCHCLK_RCEN : 1;
		unsigned int                                 : 1;
		unsigned int               RESETLANEMUX_RCEN : 1;
		unsigned int              RESETWRAPREGS_RCEN : 1;
		unsigned int                 RESETSRBM0_RCEN : 1;
		unsigned int                 RESETSRBM1_RCEN : 1;
		unsigned int                    RESETLC_RCEN : 1;
		unsigned int                                 : 1;
		unsigned int               SYNCIDLEPIF0_RCEN : 1;
		unsigned int               SYNCIDLEPIF1_RCEN : 1;
		unsigned int                                 : 3;
		unsigned int                  RESETMNTR_RCEN : 1;
		unsigned int                  RESETHLTR_RCEN : 1;
		unsigned int                   RESETCPM_RCEN : 1;
		unsigned int                  RESETPIF0_RCEN : 1;
		unsigned int                  RESETPIF1_RCEN : 1;
		unsigned int                                 : 2;
		unsigned int               RESETIMPARB0_RCEN : 1;
		unsigned int               RESETIMPARB1_RCEN : 1;
		unsigned int                                 : 2;
		unsigned int                  RESETPHY0_RCEN : 1;
		unsigned int                  RESETPHY1_RCEN : 1;
		unsigned int                                 : 2;
		unsigned int                   STRAPVLD_RCEN : 1;
		unsigned int                     CMDCFG_RCEN : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_CONTROL_2__VI {
	struct {
		unsigned int                                 : 15;
		unsigned int          BIF_STRAPREG_RESETATEN : 1;
		unsigned int           BIF0_GLOBAL_RESETATEN : 1;
		unsigned int            BIF0_CALIB_RESETATEN : 1;
		unsigned int             BIF0_CORE_RESETATEN : 1;
		unsigned int         BIF0_REGISTER_RESETATEN : 1;
		unsigned int              BIF0_PHY_RESETATEN : 1;
		unsigned int           BIF0_STICKY_RESETATEN : 1;
		unsigned int           BIF0_CONFIG_RESETATEN : 1;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_CONTROL_3__VI {
	struct {
		unsigned int                  SWITCHCLK_ATEN : 1;
		unsigned int                                 : 1;
		unsigned int               RESETLANEMUX_ATEN : 1;
		unsigned int              RESETWRAPREGS_ATEN : 1;
		unsigned int                 RESETSRBM0_ATEN : 1;
		unsigned int                 RESETSRBM1_ATEN : 1;
		unsigned int                    RESETLC_ATEN : 1;
		unsigned int                                 : 1;
		unsigned int               SYNCIDLEPIF0_ATEN : 1;
		unsigned int               SYNCIDLEPIF1_ATEN : 1;
		unsigned int                                 : 3;
		unsigned int                  RESETMNTR_ATEN : 1;
		unsigned int                  RESETHLTR_ATEN : 1;
		unsigned int                   RESETCPM_ATEN : 1;
		unsigned int                  RESETPIF0_ATEN : 1;
		unsigned int                  RESETPIF1_ATEN : 1;
		unsigned int                                 : 2;
		unsigned int               RESETIMPARB0_ATEN : 1;
		unsigned int               RESETIMPARB1_ATEN : 1;
		unsigned int                                 : 2;
		unsigned int                  RESETPHY0_ATEN : 1;
		unsigned int                  RESETPHY1_ATEN : 1;
		unsigned int                                 : 2;
		unsigned int                   STRAPVLD_ATEN : 1;
		unsigned int                     CMDCFG_ATEN : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_CONTROL_4__VI {
	struct {
		unsigned int                                 : 14;
		unsigned int          BIF_STRAPREG_WRRESETEN : 1;
		unsigned int                                 : 1;
		unsigned int           BIF0_GLOBAL_WRRESETEN : 1;
		unsigned int            BIF0_CALIB_WRRESETEN : 1;
		unsigned int             BIF0_CORE_WRRESETEN : 1;
		unsigned int         BIF0_REGISTER_WRRESETEN : 1;
		unsigned int              BIF0_PHY_WRRESETEN : 1;
		unsigned int           BIF0_STICKY_WRRESETEN : 1;
		unsigned int           BIF0_CONFIG_WRRESETEN : 1;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_CONTROL_5__VI {
	struct {
		unsigned int                  WRSWITCHCLK_EN : 1;
		unsigned int                                 : 1;
		unsigned int               WRRESETLANEMUX_EN : 1;
		unsigned int              WRRESETWRAPREGS_EN : 1;
		unsigned int                 WRRESETSRBM0_EN : 1;
		unsigned int                 WRRESETSRBM1_EN : 1;
		unsigned int                    WRRESETLC_EN : 1;
		unsigned int                                 : 1;
		unsigned int               WRSYNCIDLEPIF0_EN : 1;
		unsigned int               WRSYNCIDLEPIF1_EN : 1;
		unsigned int                                 : 3;
		unsigned int                  WRRESETMNTR_EN : 1;
		unsigned int                  WRRESETHLTR_EN : 1;
		unsigned int                   WRRESETCPM_EN : 1;
		unsigned int                  WRRESETPIF0_EN : 1;
		unsigned int                  WRRESETPIF1_EN : 1;
		unsigned int                                 : 2;
		unsigned int               WRRESETIMPARB0_EN : 1;
		unsigned int               WRRESETIMPARB1_EN : 1;
		unsigned int                                 : 2;
		unsigned int                  WRRESETPHY0_EN : 1;
		unsigned int                  WRRESETPHY1_EN : 1;
		unsigned int                                 : 2;
		unsigned int                   WRSTRAPVLD_EN : 1;
		unsigned int                     WRCMDCFG_EN : 1;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_CONTROL_6__VI {
	struct {
		unsigned int                    WARMRESET_EN : 1;
		unsigned int                                 : 7;
		unsigned int          CONNECTWITHWRAPREGS_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_EP_COMMAND_0__VI {
	struct {
		unsigned int               EP_CFG_RESET_ONLY : 1;
		unsigned int                   EP_SOFT_RESET : 1;
		unsigned int                    EP_DRV_RESET : 1;
		unsigned int                                 : 5;
		unsigned int                    EP_HOT_RESET : 1;
		unsigned int                 EP_LNKDWN_RESET : 1;
		unsigned int                 EP_LNKDIS_RESET : 1;
		unsigned int                                 : 5;
		unsigned int                   EP_FLR0_RESET : 1;
		unsigned int                   EP_FLR1_RESET : 1;
		unsigned int                   EP_FLR2_RESET : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_EP_CONTROL_0__VI {
	struct {
		unsigned int            EP_CFG_RESET_ONLY_EN : 1;
		unsigned int                EP_SOFT_RESET_EN : 1;
		unsigned int                 EP_DRV_RESET_EN : 1;
		unsigned int                                 : 5;
		unsigned int                 EP_HOT_RESET_EN : 1;
		unsigned int              EP_LNKDWN_RESET_EN : 1;
		unsigned int              EP_LNKDIS_RESET_EN : 1;
		unsigned int                                 : 5;
		unsigned int                EP_FLR0_RESET_EN : 1;
		unsigned int                EP_FLR1_RESET_EN : 1;
		unsigned int                EP_FLR2_RESET_EN : 1;
		unsigned int              EP_CFG_WR_RESET_EN : 1;
		unsigned int          EP_FLR_DISABLE_CFG_RST : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SWRST_GENERAL_CONTROL__VI {
	struct {
		unsigned int                  RECONFIGURE_EN : 1;
		unsigned int                 ATOMIC_RESET_EN : 1;
		unsigned int                    RESET_PERIOD : 3;
		unsigned int                                 : 3;
		unsigned int                     WAIT_LINKUP : 1;
		unsigned int                   FORCE_REGIDLE : 1;
		unsigned int                   BLOCK_ON_IDLE : 1;
		unsigned int                                 : 1;
		unsigned int                CONFIG_XFER_MODE : 1;
		unsigned int                MUXSEL_XFER_MODE : 1;
		unsigned int              HLDTRAIN_XFER_MODE : 1;
		unsigned int                                 : 1;
		unsigned int                     BYPASS_HOLD : 1;
		unsigned int                 BYPASS_PIF_HOLD : 1;
		unsigned int                                 : 10;
		unsigned int                EP_COMPLT_CHK_EN : 1;
		unsigned int              EP_COMPLT_WAIT_TMR : 2;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_BLEND_OPT_CONTROL__VI {
	struct {
		unsigned int          MRT0_COLOR_OPT_DISABLE : 1;
		unsigned int          MRT0_ALPHA_OPT_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int          MRT1_COLOR_OPT_DISABLE : 1;
		unsigned int          MRT1_ALPHA_OPT_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int          MRT2_COLOR_OPT_DISABLE : 1;
		unsigned int          MRT2_ALPHA_OPT_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int          MRT3_COLOR_OPT_DISABLE : 1;
		unsigned int          MRT3_ALPHA_OPT_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int          MRT4_COLOR_OPT_DISABLE : 1;
		unsigned int          MRT4_ALPHA_OPT_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int          MRT5_COLOR_OPT_DISABLE : 1;
		unsigned int          MRT5_ALPHA_OPT_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int          MRT6_COLOR_OPT_DISABLE : 1;
		unsigned int          MRT6_ALPHA_OPT_DISABLE : 1;
		unsigned int                                 : 2;
		unsigned int          MRT7_COLOR_OPT_DISABLE : 1;
		unsigned int          MRT7_ALPHA_OPT_DISABLE : 1;
		unsigned int                                 : 1;
		unsigned int          PIXEN_ZERO_OPT_DISABLE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_BLEND_OPT_EPSILON__VI {
	struct {
		unsigned int                    MRT0_EPSILON : 4;
		unsigned int                    MRT1_EPSILON : 4;
		unsigned int                    MRT2_EPSILON : 4;
		unsigned int                    MRT3_EPSILON : 4;
		unsigned int                    MRT4_EPSILON : 4;
		unsigned int                    MRT5_EPSILON : 4;
		unsigned int                    MRT6_EPSILON : 4;
		unsigned int                    MRT7_EPSILON : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_MRT0_BLEND_OPT__VI {
	struct {
		unsigned int                   COLOR_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   COLOR_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                                 : 5;
		unsigned int                   ALPHA_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   ALPHA_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_MRT1_BLEND_OPT__VI {
	struct {
		unsigned int                   COLOR_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   COLOR_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                                 : 5;
		unsigned int                   ALPHA_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   ALPHA_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_MRT2_BLEND_OPT__VI {
	struct {
		unsigned int                   COLOR_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   COLOR_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                                 : 5;
		unsigned int                   ALPHA_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   ALPHA_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_MRT3_BLEND_OPT__VI {
	struct {
		unsigned int                   COLOR_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   COLOR_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                                 : 5;
		unsigned int                   ALPHA_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   ALPHA_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_MRT4_BLEND_OPT__VI {
	struct {
		unsigned int                   COLOR_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   COLOR_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                                 : 5;
		unsigned int                   ALPHA_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   ALPHA_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_MRT5_BLEND_OPT__VI {
	struct {
		unsigned int                   COLOR_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   COLOR_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                                 : 5;
		unsigned int                   ALPHA_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   ALPHA_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_MRT6_BLEND_OPT__VI {
	struct {
		unsigned int                   COLOR_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   COLOR_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                                 : 5;
		unsigned int                   ALPHA_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   ALPHA_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_MRT7_BLEND_OPT__VI {
	struct {
		unsigned int                   COLOR_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   COLOR_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  COLOR_COMB_FCN : 3;
		unsigned int                                 : 5;
		unsigned int                   ALPHA_SRC_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                   ALPHA_DST_OPT : 3;
		unsigned int                                 : 1;
		unsigned int                  ALPHA_COMB_FCN : 3;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SX_PS_DOWNCONVERT__VI {
	struct {
		unsigned int                            MRT0 : 4;
		unsigned int                            MRT1 : 4;
		unsigned int                            MRT2 : 4;
		unsigned int                            MRT3 : 4;
		unsigned int                            MRT4 : 4;
		unsigned int                            MRT5 : 4;
		unsigned int                            MRT6 : 4;
		unsigned int                            MRT7 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SYMCLKA_CLOCK_ENABLE__VI {
	struct {
		unsigned int            SYMCLKA_CLOCK_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int             SYMCLKA_FE_FORCE_EN : 1;
		unsigned int                                 : 3;
		unsigned int            SYMCLKA_FE_FORCE_SRC : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SYMCLKB_CLOCK_ENABLE__VI {
	struct {
		unsigned int            SYMCLKB_CLOCK_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int             SYMCLKB_FE_FORCE_EN : 1;
		unsigned int                                 : 3;
		unsigned int            SYMCLKB_FE_FORCE_SRC : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SYMCLKC_CLOCK_ENABLE__VI {
	struct {
		unsigned int            SYMCLKC_CLOCK_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int             SYMCLKC_FE_FORCE_EN : 1;
		unsigned int                                 : 3;
		unsigned int            SYMCLKC_FE_FORCE_SRC : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SYMCLKD_CLOCK_ENABLE__VI {
	struct {
		unsigned int            SYMCLKD_CLOCK_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int             SYMCLKD_FE_FORCE_EN : 1;
		unsigned int                                 : 3;
		unsigned int            SYMCLKD_FE_FORCE_SRC : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SYMCLKE_CLOCK_ENABLE__VI {
	struct {
		unsigned int            SYMCLKE_CLOCK_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int             SYMCLKE_FE_FORCE_EN : 1;
		unsigned int                                 : 3;
		unsigned int            SYMCLKE_FE_FORCE_SRC : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SYMCLKF_CLOCK_ENABLE__VI {
	struct {
		unsigned int            SYMCLKF_CLOCK_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int             SYMCLKF_FE_FORCE_EN : 1;
		unsigned int                                 : 3;
		unsigned int            SYMCLKF_FE_FORCE_SRC : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SYMCLKG_CLOCK_ENABLE__VI {
	struct {
		unsigned int            SYMCLKG_CLOCK_ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int             SYMCLKG_FE_FORCE_EN : 1;
		unsigned int                                 : 3;
		unsigned int            SYMCLKG_FE_FORCE_SRC : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SYS_GRBM_GFX_INDEX_DATA__VI {
	struct {
		unsigned int                  INSTANCE_INDEX : 8;
		unsigned int                        SH_INDEX : 8;
		unsigned int                        SE_INDEX : 8;
		unsigned int                                 : 5;
		unsigned int             SH_BROADCAST_WRITES : 1;
		unsigned int       INSTANCE_BROADCAST_WRITES : 1;
		unsigned int             SE_BROADCAST_WRITES : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union SYS_GRBM_GFX_INDEX_SELECT__VI {
	struct {
		unsigned int          SYS_GRBM_GFX_INDEX_SEL : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_DSM_CNTL__VI {
	struct {
		unsigned int    CACHE_RAM_IRRITATOR_DATA_SEL : 2;
		unsigned int CACHE_RAM_IRRITATOR_SINGLE_WRITE : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_EDC_CNT__VI {
	struct {
		unsigned int                       SEC_COUNT : 8;
		unsigned int                                 : 8;
		unsigned int                       DED_COUNT : 8;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCC_EXE_DISABLE__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                     EXE_DISABLE : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_ATC_EDC_GATCL1_CNT__VI {
	struct {
		unsigned int                        DATA_SEC : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_CNTL2__VI {
	struct {
		unsigned int               LS_DISABLE_CLOCKS : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_DSM_CNTL__VI {
	struct {
		unsigned int    CACHE_RAM_IRRITATOR_DATA_SEL : 2;
		unsigned int CACHE_RAM_IRRITATOR_SINGLE_WRITE : 1;
		unsigned int    LFIFO_RAM_IRRITATOR_DATA_SEL : 2;
		unsigned int LFIFO_RAM_IRRITATOR_SINGLE_WRITE : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_EDC_CNT__VI {
	struct {
		unsigned int                       SEC_COUNT : 8;
		unsigned int                 LFIFO_SED_COUNT : 8;
		unsigned int                       DED_COUNT : 8;
		unsigned int                          UNUSED : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_GATCL1_CNTL__VI {
	struct {
		unsigned int                                 : 25;
		unsigned int             INVALIDATE_ALL_VMID : 1;
		unsigned int                      FORCE_MISS : 1;
		unsigned int                  FORCE_IN_ORDER : 1;
		unsigned int          REDUCE_FIFO_DEPTH_BY_2 : 2;
		unsigned int          REDUCE_CACHE_SIZE_BY_2 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TCP_GATCL1_DSM_CNTL__VI {
	struct {
		unsigned int SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0 : 1;
		unsigned int SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1 : 1;
		unsigned int TCP_GATCL1_ENABLE_SINGLE_WRITE_A : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TDC_MV_AVERAGE__VI {
	struct {
		unsigned int                             IDD : 16;
		unsigned int                            IDDC : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TDC_STATUS__VI {
	struct {
		unsigned int                       VDD_Boost : 8;
		unsigned int                    VDD_Throttle : 8;
		unsigned int                      VDDC_Boost : 8;
		unsigned int                   VDDC_Throttle : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TDC_VRM_LIMIT__VI {
	struct {
		unsigned int                             IDD : 16;
		unsigned int                            IDDC : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union TD_DSM_CNTL__VI {
	struct {
		unsigned int                    FORCE_SEDB_0 : 1;
		unsigned int                    FORCE_SEDB_1 : 1;
		unsigned int               EN_SINGLE_WR_SEDB : 1;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON0_STATUS__VI {
	struct {
		unsigned int                     CURRENT_RDI : 5;
		unsigned int                       MEAS_DONE : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON1_STATUS__VI {
	struct {
		unsigned int                     CURRENT_RDI : 5;
		unsigned int                       MEAS_DONE : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_CSR_RD__VI {
	struct {
		unsigned int                       READ_DATA : 12;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_CSR_WR__VI {
	struct {
		unsigned int                       CSR_WRITE : 1;
		unsigned int                        CSR_READ : 1;
		unsigned int                        CSR_ADDR : 10;
		unsigned int                      WRITE_DATA : 12;
		unsigned int                           SPARE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_CTRL__VI {
	struct {
		unsigned int                      POWER_DOWN : 1;
		unsigned int                           BGADJ : 8;
		unsigned int                      BGADJ_MODE : 1;
		unsigned int                      TMON_PAUSE : 1;
		unsigned int                     INT_MEAS_EN : 1;
		unsigned int                      DEBUG_MODE : 1;
		unsigned int                   EN_CFG_SERDES : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_CTRL2__VI {
	struct {
		unsigned int                    RDIL_PRESENT : 16;
		unsigned int                    RDIR_PRESENT : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_DEBUG__VI {
	struct {
		unsigned int                       DEBUG_RDI : 5;
		unsigned int                         DEBUG_Z : 11;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_INT_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL0_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL10_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL11_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL12_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL13_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL14_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL15_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL1_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL2_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL3_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL4_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL5_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL6_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL7_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL8_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIL9_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR0_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR10_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR11_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR12_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR13_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR14_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR15_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR1_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR2_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR3_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR4_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR5_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR6_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR7_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR8_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_RDIR9_DATA__VI {
	struct {
		unsigned int                               Z : 11;
		unsigned int                           VALID : 1;
		unsigned int                            TEMP : 12;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union THM_TMON2_STATUS__VI {
	struct {
		unsigned int                     CURRENT_RDI : 5;
		unsigned int                       MEAS_DONE : 1;
		unsigned int                                 : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYA_CHANNEL_XBAR_CNTL__VI {
	struct {
		unsigned int     UNIPHY_CHANNEL0_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL1_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL2_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL3_XBAR_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int              UNIPHY_LINK_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYA_LINK_CNTL__VI {
	struct {
		unsigned int                 UNIPHY_PFREQCHG : 1;
		unsigned int                                 : 3;
		unsigned int             UNIPHY_PIXVLD_RESET : 1;
		unsigned int                                 : 3;
		unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3;
		unsigned int                                 : 1;
		unsigned int          UNIPHY_CHANNEL0_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL1_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL2_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL3_INVERT : 1;
		unsigned int                                 : 4;
		unsigned int       UNIPHY_LANE_STAGGER_DELAY : 3;
		unsigned int                                 : 1;
		unsigned int     UNIPHY_LINK_ENABLE_HPD_MASK : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYB_CHANNEL_XBAR_CNTL__VI {
	struct {
		unsigned int     UNIPHY_CHANNEL0_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL1_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL2_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL3_XBAR_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int              UNIPHY_LINK_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYB_LINK_CNTL__VI {
	struct {
		unsigned int                 UNIPHY_PFREQCHG : 1;
		unsigned int                                 : 3;
		unsigned int             UNIPHY_PIXVLD_RESET : 1;
		unsigned int                                 : 3;
		unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3;
		unsigned int                                 : 1;
		unsigned int          UNIPHY_CHANNEL0_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL1_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL2_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL3_INVERT : 1;
		unsigned int                                 : 4;
		unsigned int       UNIPHY_LANE_STAGGER_DELAY : 3;
		unsigned int                                 : 1;
		unsigned int     UNIPHY_LINK_ENABLE_HPD_MASK : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYC_CHANNEL_XBAR_CNTL__VI {
	struct {
		unsigned int     UNIPHY_CHANNEL0_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL1_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL2_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL3_XBAR_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int              UNIPHY_LINK_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYC_LINK_CNTL__VI {
	struct {
		unsigned int                 UNIPHY_PFREQCHG : 1;
		unsigned int                                 : 3;
		unsigned int             UNIPHY_PIXVLD_RESET : 1;
		unsigned int                                 : 3;
		unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3;
		unsigned int                                 : 1;
		unsigned int          UNIPHY_CHANNEL0_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL1_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL2_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL3_INVERT : 1;
		unsigned int                                 : 4;
		unsigned int       UNIPHY_LANE_STAGGER_DELAY : 3;
		unsigned int                                 : 1;
		unsigned int     UNIPHY_LINK_ENABLE_HPD_MASK : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYD_CHANNEL_XBAR_CNTL__VI {
	struct {
		unsigned int     UNIPHY_CHANNEL0_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL1_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL2_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL3_XBAR_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int              UNIPHY_LINK_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYD_LINK_CNTL__VI {
	struct {
		unsigned int                 UNIPHY_PFREQCHG : 1;
		unsigned int                                 : 3;
		unsigned int             UNIPHY_PIXVLD_RESET : 1;
		unsigned int                                 : 3;
		unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3;
		unsigned int                                 : 1;
		unsigned int          UNIPHY_CHANNEL0_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL1_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL2_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL3_INVERT : 1;
		unsigned int                                 : 4;
		unsigned int       UNIPHY_LANE_STAGGER_DELAY : 3;
		unsigned int                                 : 1;
		unsigned int     UNIPHY_LINK_ENABLE_HPD_MASK : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYE_CHANNEL_XBAR_CNTL__VI {
	struct {
		unsigned int     UNIPHY_CHANNEL0_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL1_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL2_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL3_XBAR_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int              UNIPHY_LINK_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYE_LINK_CNTL__VI {
	struct {
		unsigned int                 UNIPHY_PFREQCHG : 1;
		unsigned int                                 : 3;
		unsigned int             UNIPHY_PIXVLD_RESET : 1;
		unsigned int                                 : 3;
		unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3;
		unsigned int                                 : 1;
		unsigned int          UNIPHY_CHANNEL0_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL1_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL2_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL3_INVERT : 1;
		unsigned int                                 : 4;
		unsigned int       UNIPHY_LANE_STAGGER_DELAY : 3;
		unsigned int                                 : 1;
		unsigned int     UNIPHY_LINK_ENABLE_HPD_MASK : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYF_CHANNEL_XBAR_CNTL__VI {
	struct {
		unsigned int     UNIPHY_CHANNEL0_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL1_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL2_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL3_XBAR_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int              UNIPHY_LINK_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYF_LINK_CNTL__VI {
	struct {
		unsigned int                 UNIPHY_PFREQCHG : 1;
		unsigned int                                 : 3;
		unsigned int             UNIPHY_PIXVLD_RESET : 1;
		unsigned int                                 : 3;
		unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3;
		unsigned int                                 : 1;
		unsigned int          UNIPHY_CHANNEL0_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL1_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL2_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL3_INVERT : 1;
		unsigned int                                 : 4;
		unsigned int       UNIPHY_LANE_STAGGER_DELAY : 3;
		unsigned int                                 : 1;
		unsigned int     UNIPHY_LINK_ENABLE_HPD_MASK : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYG_CHANNEL_XBAR_CNTL__VI {
	struct {
		unsigned int     UNIPHY_CHANNEL0_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL1_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL2_XBAR_SOURCE : 2;
		unsigned int                                 : 6;
		unsigned int     UNIPHY_CHANNEL3_XBAR_SOURCE : 2;
		unsigned int                                 : 2;
		unsigned int              UNIPHY_LINK_ENABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHYG_LINK_CNTL__VI {
	struct {
		unsigned int                 UNIPHY_PFREQCHG : 1;
		unsigned int                                 : 3;
		unsigned int             UNIPHY_PIXVLD_RESET : 1;
		unsigned int                                 : 3;
		unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3;
		unsigned int                                 : 1;
		unsigned int          UNIPHY_CHANNEL0_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL1_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL2_INVERT : 1;
		unsigned int          UNIPHY_CHANNEL3_INVERT : 1;
		unsigned int                                 : 4;
		unsigned int       UNIPHY_LANE_STAGGER_DELAY : 3;
		unsigned int                                 : 1;
		unsigned int     UNIPHY_LINK_ENABLE_HPD_MASK : 2;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_ANG_BIST_CNTL__VI {
	struct {
		unsigned int               UNIPHY_TEST_RX_EN : 1;
		unsigned int           UNIPHY_ANG_BIST_RESET : 1;
		unsigned int                                 : 6;
		unsigned int                  UNIPHY_RX_BIAS : 4;
		unsigned int                                 : 4;
		unsigned int           UNIPHY_ANG_BIST_ERROR : 5;
		unsigned int                                 : 3;
		unsigned int                  UNIPHY_PRESETB : 1;
		unsigned int                  UNIPHY_BIST_EN : 1;
		unsigned int           UNIPHY_CLK_CH_EN4_DFT : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_DEBUG__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int                          DEBUG0 : 10;
		unsigned int                          DEBUG1 : 3;
		unsigned int                         DBG_SEL : 2;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_PSW_AB__VI {
	struct {
		unsigned int         UNIPHY_IMPCAL_PSW_LINKA : 15;
		unsigned int                                 : 1;
		unsigned int         UNIPHY_IMPCAL_PSW_LINKB : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_PSW_CD__VI {
	struct {
		unsigned int         UNIPHY_IMPCAL_PSW_LINKC : 15;
		unsigned int                                 : 1;
		unsigned int         UNIPHY_IMPCAL_PSW_LINKD : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_IMPCAL_PSW_EF__VI {
	struct {
		unsigned int         UNIPHY_IMPCAL_PSW_LINKE : 15;
		unsigned int                                 : 1;
		unsigned int         UNIPHY_IMPCAL_PSW_LINKF : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED0__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED1__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED10__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED11__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED12__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED13__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED14__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED15__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED16__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED17__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED18__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED19__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED2__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED20__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED21__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED22__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED23__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED24__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED25__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED26__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED27__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED28__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED29__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED3__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED30__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED31__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED4__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED5__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED6__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED7__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED8__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_MACRO_CNTL_RESERVED9__VI {
	struct {
		unsigned int      UNIPHY_MACRO_CNTL_RESERVED : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_PLL_CONTROL1__VI {
	struct {
		unsigned int               UNIPHY_PLL_ENABLE : 1;
		unsigned int                UNIPHY_PLL_RESET : 1;
		unsigned int         UNIPHY_PLL_EXT_RESET_EN : 1;
		unsigned int               UNIPHY_PLL_CLK_EN : 1;
		unsigned int             UNIPHY_PLL_CLKPH_EN : 4;
		unsigned int              UNIPHY_PLL_LF_CNTL : 7;
		unsigned int                                 : 1;
		unsigned int              UNIPHY_PLL_BW_CNTL : 8;
		unsigned int      UNIPHY_PLL_TEST_BYPCLK_SRC : 1;
		unsigned int       UNIPHY_PLL_TEST_BYPCLK_EN : 1;
		unsigned int     UNIPHY_PLL_TEST_VCTL_ADC_EN : 1;
		unsigned int                                 : 1;
		unsigned int                 UNIPHY_VCO_MODE : 2;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_PLL_CONTROL2__VI {
	struct {
		unsigned int         UNIPHY_PLL_DISPCLK_MODE : 2;
		unsigned int                  UNIPHY_DPLLSEL : 2;
		unsigned int                UNIPHY_IDCLK_SEL : 1;
		unsigned int         UNIPHY_IPCIE_REFCLK_SEL : 1;
		unsigned int              UNIPHY_IXTALIN_SEL : 1;
		unsigned int                                 : 1;
		unsigned int           UNIPHY_PLL_REFCLK_SRC : 3;
		unsigned int           UNIPHY_PCIEREF_CLK_EN : 1;
		unsigned int                 UNIPHY_IDCLK_EN : 1;
		unsigned int                   UNIPHY_CLKINV : 1;
		unsigned int                                 : 2;
		unsigned int       UNIPHY_PLL_VTOI_BIAS_CNTL : 1;
		unsigned int                                 : 2;
		unsigned int UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS : 1;
		unsigned int             UNIPHY_PDIVFRAC_SEL : 1;
		unsigned int                                 : 3;
		unsigned int               UNIPHY_PLL_REFDIV : 5;
		unsigned int                 UNIPHY_PDIV_SEL : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_PLL_FBDIV__VI {
	struct {
		unsigned int                                 : 2;
		unsigned int       UNIPHY_PLL_FBDIV_FRACTION : 14;
		unsigned int                UNIPHY_PLL_FBDIV : 12;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_PLL_SS_CNTL__VI {
	struct {
		unsigned int          UNIPHY_PLL_SS_STEP_NUM : 12;
		unsigned int             UNIPHY_PLL_DSMOD_EN : 1;
		unsigned int                UNIPHY_PLL_SS_EN : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_PLL_SS_STEP_SIZE__VI {
	struct {
		unsigned int         UNIPHY_PLL_SS_STEP_SIZE : 26;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_POWER_CONTROL__VI {
	struct {
		unsigned int                    UNIPHY_BGPDN : 1;
		unsigned int                UNIPHY_RST_LOGIC : 1;
		unsigned int              UNIPHY_BIASREF_SEL : 1;
		unsigned int                                 : 5;
		unsigned int                UNIPHY_BGADJ1P00 : 4;
		unsigned int                UNIPHY_BGADJ1P25 : 4;
		unsigned int                UNIPHY_BGADJ0P45 : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_REG_TEST_OUTPUT2__VI {
	struct {
		unsigned int                       UNIPHY_TX : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_TPG_CONTROL__VI {
	struct {
		unsigned int      UNIPHY_STATIC_TEST_PATTERN : 10;
		unsigned int                                 : 6;
		unsigned int                   UNIPHY_TPG_EN : 1;
		unsigned int                  UNIPHY_TPG_SEL : 3;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_TPG_SEED__VI {
	struct {
		unsigned int                 UNIPHY_TPG_SEED : 23;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_TX_CONTROL1__VI {
	struct {
		unsigned int              UNIPHY_PREMPH_STR0 : 3;
		unsigned int                                 : 1;
		unsigned int              UNIPHY_PREMPH_STR1 : 3;
		unsigned int                                 : 1;
		unsigned int              UNIPHY_PREMPH_STR2 : 3;
		unsigned int                                 : 1;
		unsigned int              UNIPHY_PREMPH_STR3 : 3;
		unsigned int                                 : 1;
		unsigned int              UNIPHY_PREMPH_STR4 : 3;
		unsigned int                                 : 1;
		unsigned int                   UNIPHY_TX_VS0 : 2;
		unsigned int                   UNIPHY_TX_VS1 : 2;
		unsigned int                   UNIPHY_TX_VS2 : 2;
		unsigned int                   UNIPHY_TX_VS3 : 2;
		unsigned int                   UNIPHY_TX_VS4 : 2;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_TX_CONTROL2__VI {
	struct {
		unsigned int               UNIPHY_PREMPH0_PC : 2;
		unsigned int                                 : 2;
		unsigned int               UNIPHY_PREMPH1_PC : 2;
		unsigned int                                 : 2;
		unsigned int               UNIPHY_PREMPH2_PC : 2;
		unsigned int                                 : 2;
		unsigned int               UNIPHY_PREMPH3_PC : 2;
		unsigned int                                 : 2;
		unsigned int               UNIPHY_PREMPH4_PC : 2;
		unsigned int                                 : 2;
		unsigned int               UNIPHY_PREMPH_SEL : 1;
		unsigned int                UNIPHY_RT0_CPSEL : 2;
		unsigned int                UNIPHY_RT1_CPSEL : 2;
		unsigned int                UNIPHY_RT2_CPSEL : 2;
		unsigned int                UNIPHY_RT3_CPSEL : 2;
		unsigned int                UNIPHY_RT4_CPSEL : 2;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_TX_CONTROL3__VI {
	struct {
		unsigned int            UNIPHY_PREMPH_PW_CLK : 2;
		unsigned int            UNIPHY_PREMPH_PW_DAT : 2;
		unsigned int            UNIPHY_PREMPH_CS_CLK : 4;
		unsigned int            UNIPHY_PREMPH_CS_DAT : 4;
		unsigned int           UNIPHY_PREMPH_STR_CLK : 3;
		unsigned int                                 : 1;
		unsigned int           UNIPHY_PREMPH_STR_DAT : 3;
		unsigned int                                 : 1;
		unsigned int                   UNIPHY_PESEL0 : 1;
		unsigned int                   UNIPHY_PESEL1 : 1;
		unsigned int                   UNIPHY_PESEL2 : 1;
		unsigned int                   UNIPHY_PESEL3 : 1;
		unsigned int                UNIPHY_TX_VS_ADJ : 5;
		unsigned int                                 : 2;
		unsigned int             UNIPHY_LVDS_PULLDWN : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNIPHY_TX_CONTROL4__VI {
	struct {
		unsigned int               UNIPHY_TX_NVS_CLK : 5;
		unsigned int               UNIPHY_TX_NVS_DAT : 5;
		unsigned int                                 : 2;
		unsigned int               UNIPHY_TX_PVS_CLK : 5;
		unsigned int               UNIPHY_TX_PVS_DAT : 5;
		unsigned int                                 : 2;
		unsigned int                UNIPHY_TX_OP_CLK : 3;
		unsigned int                                 : 1;
		unsigned int                UNIPHY_TX_OP_DAT : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_CRC_CONTROL__VI {
	struct {
		unsigned int                  UNP_CRC_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int              UNP_CRC_SOURCE_SEL : 3;
		unsigned int                                 : 3;
		unsigned int                UNP_CRC_LINE_SEL : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_CRC_CURRENT__VI {
	struct {
		unsigned int                 UNP_CRC_CURRENT : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_CRC_LAST__VI {
	struct {
		unsigned int                    UNP_CRC_LAST : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_CRC_MASK__VI {
	struct {
		unsigned int                    UNP_CRC_MASK : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_DEBUG__VI {
	struct {
		unsigned int                       UNP_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_DEBUG2__VI {
	struct {
		unsigned int                      UNP_DEBUG2 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_CONTROL__VI {
	struct {
		unsigned int                      GRPH_DEPTH : 2;
		unsigned int                  GRPH_NUM_BANKS : 2;
		unsigned int                          GRPH_Z : 2;
		unsigned int                 GRPH_BANK_WIDTH : 2;
		unsigned int                     GRPH_FORMAT : 3;
		unsigned int                GRPH_BANK_HEIGHT : 2;
		unsigned int                 GRPH_TILE_SPLIT : 3;
		unsigned int GRPH_ADDRESS_TRANSLATION_ENABLE : 1;
		unsigned int   GRPH_PRIVILEGED_ACCESS_ENABLE : 1;
		unsigned int          GRPH_MACRO_TILE_ASPECT : 2;
		unsigned int                 GRPH_ARRAY_MODE : 4;
		unsigned int                GRPH_PIPE_CONFIG : 5;
		unsigned int            GRPH_MICRO_TILE_MODE : 2;
		unsigned int       GRPH_COLOR_EXPANSION_MODE : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_CONTROL_EXP__VI {
	struct {
		unsigned int                    VIDEO_FORMAT : 3;
		unsigned int                                 : 29;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_DFQ_CONTROL__VI {
	struct {
		unsigned int                  GRPH_DFQ_RESET : 1;
		unsigned int                                 : 3;
		unsigned int                   GRPH_DFQ_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int       GRPH_DFQ_MIN_FREE_ENTRIES : 3;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_DFQ_STATUS__VI {
	struct {
		unsigned int    GRPH_PRIMARY_DFQ_NUM_ENTRIES : 4;
		unsigned int  GRPH_SECONDARY_DFQ_NUM_ENTRIES : 4;
		unsigned int             GRPH_DFQ_RESET_FLAG : 1;
		unsigned int              GRPH_DFQ_RESET_ACK : 1;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_ENABLE__VI {
	struct {
		unsigned int                     GRPH_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_FLIP_RATE_CNTL__VI {
	struct {
		unsigned int                  GRPH_FLIP_RATE : 3;
		unsigned int           GRPH_FLIP_RATE_ENABLE : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_INTERRUPT_CONTROL__VI {
	struct {
		unsigned int             GRPH_PFLIP_INT_MASK : 1;
		unsigned int                                 : 7;
		unsigned int             GRPH_PFLIP_INT_TYPE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_INTERRUPT_STATUS__VI {
	struct {
		unsigned int         GRPH_PFLIP_INT_OCCURRED : 1;
		unsigned int                                 : 7;
		unsigned int            GRPH_PFLIP_INT_CLEAR : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_PITCH_C__VI {
	struct {
		unsigned int                    GRPH_PITCH_C : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_PITCH_L__VI {
	struct {
		unsigned int                    GRPH_PITCH_L : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__VI {
	struct {
		unsigned int GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C : 1;
		unsigned int                                 : 7;
		unsigned int GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI {
	struct {
		unsigned int GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI {
	struct {
		unsigned int GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__VI {
	struct {
		unsigned int GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L : 1;
		unsigned int                                 : 7;
		unsigned int GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__VI {
	struct {
		unsigned int       GRPH_PRIMARY_DFQ_ENABLE_C : 1;
		unsigned int                                 : 7;
		unsigned int  GRPH_PRIMARY_SURFACE_ADDRESS_C : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__VI {
	struct {
		unsigned int GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__VI {
	struct {
		unsigned int GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__VI {
	struct {
		unsigned int       GRPH_PRIMARY_DFQ_ENABLE_L : 1;
		unsigned int                                 : 7;
		unsigned int  GRPH_PRIMARY_SURFACE_ADDRESS_L : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__VI {
	struct {
		unsigned int GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C : 1;
		unsigned int                                 : 7;
		unsigned int GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI {
	struct {
		unsigned int GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI {
	struct {
		unsigned int GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__VI {
	struct {
		unsigned int GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L : 1;
		unsigned int                                 : 7;
		unsigned int GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__VI {
	struct {
		unsigned int     GRPH_SECONDARY_DFQ_ENABLE_C : 1;
		unsigned int                                 : 7;
		unsigned int GRPH_SECONDARY_SURFACE_ADDRESS_C : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__VI {
	struct {
		unsigned int GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__VI {
	struct {
		unsigned int GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__VI {
	struct {
		unsigned int     GRPH_SECONDARY_DFQ_ENABLE_L : 1;
		unsigned int                                 : 7;
		unsigned int GRPH_SECONDARY_SURFACE_ADDRESS_L : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_STEREOSYNC_FLIP__VI {
	struct {
		unsigned int         GRPH_STEREOSYNC_FLIP_EN : 1;
		unsigned int                                 : 3;
		unsigned int       GRPH_STEREOSYNC_FLIP_MODE : 2;
		unsigned int                                 : 2;
		unsigned int    GRPH_STACK_INTERLACE_FLIP_EN : 1;
		unsigned int                                 : 3;
		unsigned int  GRPH_STACK_INTERLACE_FLIP_MODE : 2;
		unsigned int                                 : 2;
		unsigned int    GRPH_PRIMARY_SURFACE_PENDING : 1;
		unsigned int  GRPH_SECONDARY_SURFACE_PENDING : 1;
		unsigned int GRPH_PRIMARY_BOTTOM_SURFACE_PENDING : 1;
		unsigned int GRPH_SECONDARY_BOTTOM_SURFACE_PENDING : 1;
		unsigned int                                 : 8;
		unsigned int  GRPH_STEREOSYNC_SELECT_DISABLE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__VI {
	struct {
		unsigned int GRPH_SURFACE_ADDRESS_HIGH_INUSE_C : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__VI {
	struct {
		unsigned int GRPH_SURFACE_ADDRESS_HIGH_INUSE_L : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SURFACE_ADDRESS_INUSE_C__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int    GRPH_SURFACE_ADDRESS_INUSE_C : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SURFACE_ADDRESS_INUSE_L__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int    GRPH_SURFACE_ADDRESS_INUSE_L : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SURFACE_OFFSET_X_C__VI {
	struct {
		unsigned int         GRPH_SURFACE_OFFSET_X_C : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SURFACE_OFFSET_X_L__VI {
	struct {
		unsigned int         GRPH_SURFACE_OFFSET_X_L : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SURFACE_OFFSET_Y_C__VI {
	struct {
		unsigned int         GRPH_SURFACE_OFFSET_Y_C : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SURFACE_OFFSET_Y_L__VI {
	struct {
		unsigned int         GRPH_SURFACE_OFFSET_Y_L : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_SWAP_CNTL__VI {
	struct {
		unsigned int                GRPH_ENDIAN_SWAP : 2;
		unsigned int                                 : 2;
		unsigned int               GRPH_RED_CROSSBAR : 2;
		unsigned int             GRPH_GREEN_CROSSBAR : 2;
		unsigned int              GRPH_BLUE_CROSSBAR : 2;
		unsigned int                                 : 22;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_UPDATE__VI {
	struct {
		unsigned int        GRPH_MODE_UPDATE_PENDING : 1;
		unsigned int          GRPH_MODE_UPDATE_TAKEN : 1;
		unsigned int     GRPH_SURFACE_UPDATE_PENDING : 1;
		unsigned int       GRPH_SURFACE_UPDATE_TAKEN : 1;
		unsigned int                                 : 12;
		unsigned int                GRPH_UPDATE_LOCK : 1;
		unsigned int                                 : 3;
		unsigned int GRPH_SURFACE_IGNORE_UPDATE_LOCK : 1;
		unsigned int                                 : 3;
		unsigned int GRPH_MODE_DISABLE_MULTIPLE_UPDATE : 1;
		unsigned int                                 : 3;
		unsigned int GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE : 1;
		unsigned int                                 : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_X_END_C__VI {
	struct {
		unsigned int                    GRPH_X_END_C : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_X_END_L__VI {
	struct {
		unsigned int                    GRPH_X_END_L : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_X_START_C__VI {
	struct {
		unsigned int                  GRPH_X_START_C : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_X_START_L__VI {
	struct {
		unsigned int                  GRPH_X_START_L : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_Y_END_C__VI {
	struct {
		unsigned int                    GRPH_Y_END_C : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_Y_END_L__VI {
	struct {
		unsigned int                    GRPH_Y_END_L : 15;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_Y_START_C__VI {
	struct {
		unsigned int                  GRPH_Y_START_C : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_GRPH_Y_START_L__VI {
	struct {
		unsigned int                  GRPH_Y_START_L : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_HW_ROTATION__VI {
	struct {
		unsigned int                  ROTATION_ANGLE : 3;
		unsigned int                                 : 1;
		unsigned int                      PIXEL_DROP : 1;
		unsigned int                                 : 3;
		unsigned int                     BUFFER_MODE : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_LB_DATA_GAP_BETWEEN_CHUNK__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int        UNP_LB_GAP_BETWEEN_CHUNK : 5;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int             UNP_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UNP_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int            UNP_TEST_DEBUG_INDEX : 8;
		unsigned int         UNP_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CGC_CTRL2__VI {
	struct {
		unsigned int                DYN_OCLK_RAMP_EN : 1;
		unsigned int                DYN_RCLK_RAMP_EN : 1;
		unsigned int                    GATER_DIV_ID : 3;
		unsigned int                                 : 27;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CGC_MEM_CTRL__VI {
	struct {
		unsigned int                    LMI_MC_LS_EN : 1;
		unsigned int                       MPC_LS_EN : 1;
		unsigned int                      MPRD_LS_EN : 1;
		unsigned int                       WCB_LS_EN : 1;
		unsigned int                   UDEC_RE_LS_EN : 1;
		unsigned int                   UDEC_CM_LS_EN : 1;
		unsigned int                   UDEC_IT_LS_EN : 1;
		unsigned int                   UDEC_DB_LS_EN : 1;
		unsigned int                   UDEC_MP_LS_EN : 1;
		unsigned int                       SYS_LS_EN : 1;
		unsigned int                      VCPU_LS_EN : 1;
		unsigned int                      SCPU_LS_EN : 1;
		unsigned int                       MIF_LS_EN : 1;
		unsigned int                       LCM_LS_EN : 1;
		unsigned int                      JPEG_LS_EN : 1;
		unsigned int                     JPEG2_LS_EN : 1;
		unsigned int                    LS_SET_DELAY : 4;
		unsigned int                  LS_CLEAR_DELAY : 4;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_CGC_UDEC_STATUS__VI {
	struct {
		unsigned int                         RE_SCLK : 1;
		unsigned int                         RE_DCLK : 1;
		unsigned int                         RE_VCLK : 1;
		unsigned int                         CM_SCLK : 1;
		unsigned int                         CM_DCLK : 1;
		unsigned int                         CM_VCLK : 1;
		unsigned int                         IT_SCLK : 1;
		unsigned int                         IT_DCLK : 1;
		unsigned int                         IT_VCLK : 1;
		unsigned int                         DB_SCLK : 1;
		unsigned int                         DB_DCLK : 1;
		unsigned int                         DB_VCLK : 1;
		unsigned int                         MP_SCLK : 1;
		unsigned int                         MP_DCLK : 1;
		unsigned int                         MP_VCLK : 1;
		unsigned int                       JPEG_VCLK : 1;
		unsigned int                       JPEG_SCLK : 1;
		unsigned int                      JPEG2_VCLK : 1;
		unsigned int                      JPEG2_SCLK : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_JPEG_ADDR_CONFIG__VI {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                        NUM_GPUS : 3;
		unsigned int                                 : 1;
		unsigned int             MULTI_GPU_TILE_SIZE : 2;
		unsigned int                                 : 2;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_ADDR_EXT2__VI {
	struct {
		unsigned int                   SCPU_ADDR_EXT : 4;
		unsigned int                SCPU_VM_ADDR_EXT : 4;
		unsigned int               SCPU_NC0_ADDR_EXT : 4;
		unsigned int               SCPU_NC1_ADDR_EXT : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_RBC_IB_64BIT_BAR_HIGH__VI {
	struct {
		unsigned int                      BITS_63_32 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_RBC_IB_64BIT_BAR_LOW__VI {
	struct {
		unsigned int                       BITS_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_RBC_IB_VMID__VI {
	struct {
		unsigned int                         IB_VMID : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_RBC_RB_64BIT_BAR_HIGH__VI {
	struct {
		unsigned int                      BITS_63_32 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_RBC_RB_64BIT_BAR_LOW__VI {
	struct {
		unsigned int                       BITS_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_RBC_RB_VMID__VI {
	struct {
		unsigned int                         RB_VMID : 4;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_SWAP_CNTL2__VI {
	struct {
		unsigned int                  SCPU_R_MC_SWAP : 2;
		unsigned int                  SCPU_W_MC_SWAP : 2;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__VI {
	struct {
		unsigned int                      BITS_63_32 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__VI {
	struct {
		unsigned int                       BITS_31_0 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_VMID_INTERNAL__VI {
	struct {
		unsigned int                   VCPU_NC0_VMID : 4;
		unsigned int                   VCPU_NC1_VMID : 4;
		unsigned int                        DPB_VMID : 4;
		unsigned int                        DBW_VMID : 4;
		unsigned int                       LBSI_VMID : 4;
		unsigned int                       IDCT_VMID : 4;
		unsigned int                       JPEG_VMID : 4;
		unsigned int                      JPEG2_VMID : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_VMID_INTERNAL2__VI {
	struct {
		unsigned int                  MIF_GPGPU_VMID : 4;
		unsigned int                   MIF_CURR_VMID : 4;
		unsigned int                    MIF_REF_VMID : 4;
		unsigned int                    MIF_DBW_VMID : 4;
		unsigned int               MIF_CM_COLOC_VMID : 4;
		unsigned int                    MIF_BSD_VMID : 4;
		unsigned int                    MIF_BSP_VMID : 4;
		unsigned int                       VDMA_VMID : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_LMI_VMID_INTERNAL3__VI {
	struct {
		unsigned int                MIF_GEN_RD0_VMID : 4;
		unsigned int                MIF_GEN_RD1_VMID : 4;
		unsigned int                MIF_GEN_WR0_VMID : 4;
		unsigned int                MIF_GEN_WR1_VMID : 4;
		unsigned int                   MIF_SCLR_VMID : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MIF_CURR_ADDR_CONFIG__VI {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                        NUM_GPUS : 3;
		unsigned int                                 : 1;
		unsigned int             MULTI_GPU_TILE_SIZE : 2;
		unsigned int                                 : 2;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MIF_RECON1_ADDR_CONFIG__VI {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                        NUM_GPUS : 3;
		unsigned int                                 : 1;
		unsigned int             MULTI_GPU_TILE_SIZE : 2;
		unsigned int                                 : 2;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MIF_REF_ADDR_CONFIG__VI {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                        NUM_GPUS : 3;
		unsigned int                                 : 1;
		unsigned int             MULTI_GPU_TILE_SIZE : 2;
		unsigned int                                 : 2;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_MIF_SCLR_ADDR_CONFIG__VI {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                        NUM_GPUS : 3;
		unsigned int                                 : 1;
		unsigned int             MULTI_GPU_TILE_SIZE : 2;
		unsigned int                                 : 2;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_PGFSM_CONFIG__VI {
	struct {
		unsigned int              UVD_PGFSM_FSM_ADDR : 8;
		unsigned int            UVD_PGFSM_POWER_DOWN : 1;
		unsigned int              UVD_PGFSM_POWER_UP : 1;
		unsigned int             UVD_PGFSM_P1_SELECT : 1;
		unsigned int             UVD_PGFSM_P2_SELECT : 1;
		unsigned int                 UVD_PGFSM_WRITE : 1;
		unsigned int                  UVD_PGFSM_READ : 1;
		unsigned int                                 : 14;
		unsigned int              UVD_PGFSM_REG_ADDR : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_PGFSM_READ_TILE1__VI {
	struct {
		unsigned int      UVD_PGFSM_READ_TILE1_VALUE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_PGFSM_READ_TILE2__VI {
	struct {
		unsigned int      UVD_PGFSM_READ_TILE2_VALUE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_PGFSM_READ_TILE3__VI {
	struct {
		unsigned int      UVD_PGFSM_READ_TILE3_VALUE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_PGFSM_READ_TILE4__VI {
	struct {
		unsigned int      UVD_PGFSM_READ_TILE4_VALUE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_PGFSM_READ_TILE5__VI {
	struct {
		unsigned int      UVD_PGFSM_READ_TILE5_VALUE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_PGFSM_READ_TILE6__VI {
	struct {
		unsigned int      UVD_PGFSM_READ_TILE6_VALUE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_PGFSM_READ_TILE7__VI {
	struct {
		unsigned int      UVD_PGFSM_READ_TILE7_VALUE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_PGFSM_WRITE__VI {
	struct {
		unsigned int                                 : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_POWER_STATUS__VI {
	struct {
		unsigned int                UVD_POWER_STATUS : 2;
		unsigned int                     UVD_PG_MODE : 1;
		unsigned int        UVD_STATUS_CHECK_TIMEOUT : 1;
		unsigned int            PWR_ON_CHECK_TIMEOUT : 1;
		unsigned int           PWR_OFF_CHECK_TIMEOUT : 1;
		unsigned int          UVD_PGFSM_TIMEOUT_MODE : 2;
		unsigned int                       UVD_PG_EN : 1;
		unsigned int                   PAUSE_DPG_REQ : 1;
		unsigned int                   PAUSE_DPG_ACK : 1;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SUVD_CGC_CTRL__VI {
	struct {
		unsigned int                        SRE_MODE : 1;
		unsigned int                        SIT_MODE : 1;
		unsigned int                        SMP_MODE : 1;
		unsigned int                        SCM_MODE : 1;
		unsigned int                        SDB_MODE : 1;
		unsigned int                       SCLR_MODE : 1;
		unsigned int                     UVD_SC_MODE : 1;
		unsigned int                                 : 25;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SUVD_CGC_GATE__VI {
	struct {
		unsigned int                             SRE : 1;
		unsigned int                             SIT : 1;
		unsigned int                             SMP : 1;
		unsigned int                             SCM : 1;
		unsigned int                             SDB : 1;
		unsigned int                        SRE_H264 : 1;
		unsigned int                        SRE_HEVC : 1;
		unsigned int                        SIT_H264 : 1;
		unsigned int                        SIT_HEVC : 1;
		unsigned int                        SCM_H264 : 1;
		unsigned int                        SCM_HEVC : 1;
		unsigned int                        SDB_H264 : 1;
		unsigned int                        SDB_HEVC : 1;
		unsigned int                            SCLR : 1;
		unsigned int                          UVD_SC : 1;
		unsigned int                                 : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_SUVD_CGC_STATUS__VI {
	struct {
		unsigned int                        SRE_VCLK : 1;
		unsigned int                        SRE_DCLK : 1;
		unsigned int                        SIT_DCLK : 1;
		unsigned int                        SMP_DCLK : 1;
		unsigned int                        SCM_DCLK : 1;
		unsigned int                        SDB_DCLK : 1;
		unsigned int                   SRE_H264_VCLK : 1;
		unsigned int                   SRE_HEVC_VCLK : 1;
		unsigned int                   SIT_H264_DCLK : 1;
		unsigned int                   SIT_HEVC_DCLK : 1;
		unsigned int                   SCM_H264_DCLK : 1;
		unsigned int                   SCM_HEVC_DCLK : 1;
		unsigned int                   SDB_H264_DCLK : 1;
		unsigned int                   SDB_HEVC_DCLK : 1;
		unsigned int                       SCLR_DCLK : 1;
		unsigned int                          UVD_SC : 1;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_UDEC_ADDR_CONFIG__VI {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                        NUM_GPUS : 3;
		unsigned int                                 : 1;
		unsigned int             MULTI_GPU_TILE_SIZE : 2;
		unsigned int                                 : 2;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_UDEC_DBW_ADDR_CONFIG__VI {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                        NUM_GPUS : 3;
		unsigned int                                 : 1;
		unsigned int             MULTI_GPU_TILE_SIZE : 2;
		unsigned int                                 : 2;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union UVD_UDEC_DB_ADDR_CONFIG__VI {
	struct {
		unsigned int                       NUM_PIPES : 3;
		unsigned int                                 : 1;
		unsigned int            PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int            BANK_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int              NUM_SHADER_ENGINES : 2;
		unsigned int                                 : 2;
		unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
		unsigned int                                 : 1;
		unsigned int                        NUM_GPUS : 3;
		unsigned int                                 : 1;
		unsigned int             MULTI_GPU_TILE_SIZE : 2;
		unsigned int                                 : 2;
		unsigned int                        ROW_SIZE : 2;
		unsigned int                 NUM_LOWER_PIPES : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_INT_STATUS__VI {
	struct {
		unsigned int                                 : 16;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 13;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_LMI_CACHE_CTRL__VI {
	struct {
		unsigned int                         VCPU_EN : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 30;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_LMI_CTRL__VI {
	struct {
		unsigned int                                 : 11;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 1;
		unsigned int          VCPU_DATA_COHERENCY_EN : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_LMI_CTRL2__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                       STALL_ARB : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 3;
		unsigned int                                 : 1;
		unsigned int                   STALL_ARB_UMC : 1;
		unsigned int                                 : 2;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_LMI_SWAP_CNTL__VI {
	struct {
		unsigned int                  VCPU_W_MC_SWAP : 2;
		unsigned int                  WR_MC_CID_SWAP : 12;
		unsigned int                                 : 6;
		unsigned int                                 : 6;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_LMI_SWAP_CNTL1__VI {
	struct {
		unsigned int                  VCPU_R_MC_SWAP : 2;
		unsigned int                  RD_MC_CID_SWAP : 12;
		unsigned int                                 : 6;
		unsigned int                                 : 6;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_LMI_SWAP_CNTL2__VI {
	struct {
		unsigned int                  WR_MC_CID_SWAP : 8;
		unsigned int                                 : 6;
		unsigned int                                 : 4;
		unsigned int                                 : 2;
		unsigned int                                 : 4;
		unsigned int                                 : 2;
		unsigned int                                 : 4;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_LMI_SWAP_CNTL3__VI {
	struct {
		unsigned int                  RD_MC_CID_SWAP : 2;
		unsigned int                                 : 12;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
		unsigned int                                 : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_LMI_VCPU_CACHE_40BIT_BAR__VI {
	struct {
		unsigned int                             BAR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_OUT_RB_WPTR__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                                 : 19;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_ARB_CTRL__VI {
	struct {
		unsigned int                                 : 9;
		unsigned int                                 : 7;
		unsigned int               VCE_CGTT_OVERRIDE : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_BASE_HI__VI {
	struct {
		unsigned int                      RB_BASE_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_BASE_HI2__VI {
	struct {
		unsigned int                      RB_BASE_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_BASE_HI3__VI {
	struct {
		unsigned int                      RB_BASE_HI : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_BASE_LO__VI {
	struct {
		unsigned int                                 : 6;
		unsigned int                      RB_BASE_LO : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_BASE_LO2__VI {
	struct {
		unsigned int                                 : 6;
		unsigned int                      RB_BASE_LO : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_BASE_LO3__VI {
	struct {
		unsigned int                                 : 6;
		unsigned int                      RB_BASE_LO : 26;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_RPTR__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                         RB_RPTR : 19;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_RPTR2__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                         RB_RPTR : 19;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_RPTR3__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                         RB_RPTR : 19;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_SIZE__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                         RB_SIZE : 19;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_SIZE2__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                         RB_SIZE : 19;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_SIZE3__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                         RB_SIZE : 19;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_WPTR__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                         RB_WPTR : 19;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_WPTR2__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                         RB_WPTR : 19;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_RB_WPTR3__VI {
	struct {
		unsigned int                                 : 4;
		unsigned int                         RB_WPTR : 19;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_SOFT_RESET__VI {
	struct {
		unsigned int                 ECPU_SOFT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_STATUS__VI {
	struct {
		unsigned int                        JOB_BUSY : 1;
		unsigned int                     VCPU_REPORT : 7;
		unsigned int                       UENC_BUSY : 1;
		unsigned int                                 : 13;
		unsigned int               VCE_CONFIGURATION : 2;
		unsigned int                 VCE_INSTANCE_ID : 2;
		unsigned int                                 : 4;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_SYS_INT_ACK__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int  VCE_SYS_INT_TRAP_INTERRUPT_ACK : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_SYS_INT_EN__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int   VCE_SYS_INT_TRAP_INTERRUPT_EN : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_SYS_INT_STATUS__VI {
	struct {
		unsigned int                                 : 1;
		unsigned int                                 : 2;
		unsigned int  VCE_SYS_INT_TRAP_INTERRUPT_INT : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 14;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_UENC_DMA_DCLK_CTRL__VI {
	struct {
		unsigned int                 WRDMCLK_FORCEON : 1;
		unsigned int                 RDDMCLK_FORCEON : 1;
		unsigned int                  REGCLK_FORCEON : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_VCPU_CACHE_OFFSET0__VI {
	struct {
		unsigned int                          OFFSET : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_VCPU_CACHE_OFFSET1__VI {
	struct {
		unsigned int                          OFFSET : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_VCPU_CACHE_OFFSET2__VI {
	struct {
		unsigned int                          OFFSET : 28;
		unsigned int                                 : 4;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_VCPU_CACHE_SIZE0__VI {
	struct {
		unsigned int                            SIZE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_VCPU_CACHE_SIZE1__VI {
	struct {
		unsigned int                            SIZE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_VCPU_CACHE_SIZE2__VI {
	struct {
		unsigned int                            SIZE : 24;
		unsigned int                                 : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VCE_VCPU_CNTL__VI {
	struct {
		unsigned int                          CLK_EN : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 14;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                 RBBM_SOFT_RESET : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 11;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VDDGFX_IDLE_CONTROL__VI {
	struct {
		unsigned int                  VDDGFX_IDLE_EN : 1;
		unsigned int              VDDGFX_IDLE_DETECT : 1;
		unsigned int          FORCE_VDDGFX_IDLE_EXIT : 1;
		unsigned int           SMC_VDDGFX_IDLE_STATE : 1;
		unsigned int                                 : 28;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VDDGFX_IDLE_EXIT__VI {
	struct {
		unsigned int                    BIF_EXIT_REQ : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VDDGFX_IDLE_PARAMETER__VI {
	struct {
		unsigned int           VDDGFX_IDLE_THRESHOLD : 16;
		unsigned int      VDDGFX_IDLE_THRESHOLD_UNIT : 4;
		unsigned int                                 : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA25_PPLL_ANALOG__VI {
	struct {
		unsigned int                  VGA25_CAL_MODE : 5;
		unsigned int        VGA25_PPLL_PFD_PULSE_SEL : 2;
		unsigned int                                 : 1;
		unsigned int                   VGA25_PPLL_CP : 4;
		unsigned int              VGA25_PPLL_LF_MODE : 9;
		unsigned int                                 : 3;
		unsigned int                VGA25_PPLL_IBIAS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA28_PPLL_ANALOG__VI {
	struct {
		unsigned int                  VGA28_CAL_MODE : 5;
		unsigned int        VGA28_PPLL_PFD_PULSE_SEL : 2;
		unsigned int                                 : 1;
		unsigned int                   VGA28_PPLL_CP : 4;
		unsigned int              VGA28_PPLL_LF_MODE : 9;
		unsigned int                                 : 3;
		unsigned int                VGA28_PPLL_IBIAS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGA41_PPLL_ANALOG__VI {
	struct {
		unsigned int                  VGA41_CAL_MODE : 5;
		unsigned int        VGA41_PPLL_PFD_PULSE_SEL : 2;
		unsigned int                                 : 1;
		unsigned int                   VGA41_PPLL_CP : 4;
		unsigned int              VGA41_PPLL_LF_MODE : 9;
		unsigned int                                 : 3;
		unsigned int                VGA41_PPLL_IBIAS : 8;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_DISPATCH_DRAW_INDEX__VI {
	struct {
		unsigned int                     MATCH_INDEX : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VGT_TESS_DISTRIBUTION__VI {
	struct {
		unsigned int                   ACCUM_ISOLINE : 8;
		unsigned int                       ACCUM_TRI : 8;
		unsigned int                      ACCUM_QUAD : 8;
		unsigned int                     DONUT_SPLIT : 5;
		unsigned int                      TRAP_SPLIT : 3;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VIEWPORT_START_SECONDARY__VI {
	struct {
		unsigned int      VIEWPORT_Y_START_SECONDARY : 14;
		unsigned int                                 : 2;
		unsigned int      VIEWPORT_X_START_SECONDARY : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_INIT_STATUS__VI {
	struct {
		unsigned int                  VM_INIT_STATUS : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_BANK_SELECT_RESERVED_CID__VI {
	struct {
		unsigned int         RESERVED_READ_CLIENT_ID : 9;
		unsigned int                                 : 1;
		unsigned int        RESERVED_WRITE_CLIENT_ID : 9;
		unsigned int                                 : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int RESERVED_CACHE_INVALIDATION_MODE : 1;
		unsigned int RESERVED_CACHE_PRIVATE_INVALIDATION : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_BANK_SELECT_RESERVED_CID2__VI {
	struct {
		unsigned int         RESERVED_READ_CLIENT_ID : 9;
		unsigned int                                 : 1;
		unsigned int        RESERVED_WRITE_CLIENT_ID : 9;
		unsigned int                                 : 1;
		unsigned int                          ENABLE : 1;
		unsigned int                                 : 3;
		unsigned int RESERVED_CACHE_INVALIDATION_MODE : 1;
		unsigned int RESERVED_CACHE_PRIVATE_INVALIDATION : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union VM_L2_CNTL4__VI {
	struct {
		unsigned int     L2_CACHE_4K_PARTITION_COUNT : 6;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 1;
		unsigned int                                 : 20;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WB_DBG_MODE__VI {
	struct {
		unsigned int                  WB_DBG_MODE_EN : 1;
		unsigned int                  WB_DBG_DIN_FMT : 1;
		unsigned int                   WB_DBG_36MODE : 1;
		unsigned int                     WB_DBG_CMAP : 1;
		unsigned int                                 : 4;
		unsigned int            WB_DBG_PXLRATE_ERROR : 1;
		unsigned int                                 : 7;
		unsigned int             WB_DBG_SOURCE_WIDTH : 15;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WB_DEBUG_CTRL__VI {
	struct {
		unsigned int                     WB_DEBUG_EN : 1;
		unsigned int                                 : 5;
		unsigned int                    WB_DEBUG_SEL : 2;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WB_EC_CONFIG__VI {
	struct {
		unsigned int           DISPCLK_R_WB_GATE_DIS : 1;
		unsigned int           DISPCLK_G_WB_GATE_DIS : 1;
		unsigned int        DISPCLK_G_WBSCL_GATE_DIS : 1;
		unsigned int           DISPCLK_R_WB_RAMP_DIS : 1;
		unsigned int           DISPCLK_G_WB_RAMP_DIS : 1;
		unsigned int        DISPCLK_G_WBSCL_RAMP_DIS : 1;
		unsigned int                    WB_LB_LS_DIS : 1;
		unsigned int                    WB_LB_SD_DIS : 1;
		unsigned int                   WB_LUT_LS_DIS : 1;
		unsigned int       WBSCL_LB_MEM_PWR_MODE_SEL : 2;
		unsigned int                                 : 1;
		unsigned int                 WB_TEST_CLK_SEL : 4;
		unsigned int            WBSCL_LB_MEM_PWR_DIS : 1;
		unsigned int          WBSCL_LB_MEM_PWR_FORCE : 2;
		unsigned int          WBSCL_LB_MEM_PWR_STATE : 2;
		unsigned int                                 : 2;
		unsigned int             WB_RAM_PW_SAVE_MODE : 1;
		unsigned int                                 : 4;
		unsigned int                LB_MEM_PWR_STATE : 2;
		unsigned int               LUT_MEM_PWR_STATE : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WB_ENABLE__VI {
	struct {
		unsigned int                       WB_ENABLE : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WB_HW_DEBUG__VI {
	struct {
		unsigned int                     WB_HW_DEBUG : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WB_SOFT_RESET__VI {
	struct {
		unsigned int                   WB_SOFT_RESET : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG10__VI {
	struct {
		unsigned int                ttp_pd_patch_rts : 1;
		unsigned int                 ttp_pd_is_event : 1;
		unsigned int                     ttp_pd_eopg : 1;
		unsigned int                      ttp_pd_eop : 1;
		unsigned int                        pipe0_dr : 1;
		unsigned int                        pipe1_dr : 1;
		unsigned int                       pipe0_rtr : 1;
		unsigned int                       pipe1_rtr : 1;
		unsigned int                   donut_en_p1_q : 1;
		unsigned int              donut_se_switch_p2 : 1;
		unsigned int              patch_se_switch_p2 : 1;
		unsigned int            last_donut_switch_p2 : 1;
		unsigned int          last_donut_of_patch_p2 : 1;
		unsigned int                   is_event_p1_q : 1;
		unsigned int                       eopg_p1_q : 1;
		unsigned int                        eop_p1_q : 1;
		unsigned int                   patch_accum_q : 8;
		unsigned int       wd_te11_out_se0_fifo_full : 1;
		unsigned int      wd_te11_out_se0_fifo_empty : 1;
		unsigned int       wd_te11_out_se1_fifo_full : 1;
		unsigned int      wd_te11_out_se1_fifo_empty : 1;
		unsigned int       wd_te11_out_se2_fifo_full : 1;
		unsigned int      wd_te11_out_se2_fifo_empty : 1;
		unsigned int       wd_te11_out_se3_fifo_full : 1;
		unsigned int      wd_te11_out_se3_fifo_empty : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG6__VI {
	struct {
		unsigned int                  WD_IA_draw_eop : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG7__VI {
	struct {
		unsigned int        SE0VGT_WD_thdgrp_send_in : 1;
		unsigned int        wd_arb_se0_input_fifo_re : 1;
		unsigned int     wd_arb_se0_input_fifo_empty : 1;
		unsigned int      wd_arb_se0_input_fifo_full : 1;
		unsigned int        SE1VGT_WD_thdgrp_send_in : 1;
		unsigned int        wd_arb_se1_input_fifo_re : 1;
		unsigned int     wd_arb_se1_input_fifo_empty : 1;
		unsigned int      wd_arb_se1_input_fifo_full : 1;
		unsigned int                          SPARE1 : 4;
		unsigned int                          SPARE2 : 4;
		unsigned int                te11_arb_state_q : 3;
		unsigned int                          SPARE5 : 1;
		unsigned int             se0_thdgrp_is_event : 1;
		unsigned int                  se0_thdgrp_eop : 1;
		unsigned int             se1_thdgrp_is_event : 1;
		unsigned int                  se1_thdgrp_eop : 1;
		unsigned int                          SPARE6 : 4;
		unsigned int            tfreq_arb_tgroup_rtr : 1;
		unsigned int            arb_tfreq_tgroup_rts : 1;
		unsigned int          arb_tfreq_tgroup_event : 1;
		unsigned int                   te11_arb_busy : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG8__VI {
	struct {
		unsigned int                        pipe0_dr : 1;
		unsigned int                        pipe1_dr : 1;
		unsigned int                       pipe0_rtr : 1;
		unsigned int                       pipe1_rtr : 1;
		unsigned int             tfreq_tg_fifo_empty : 1;
		unsigned int              tfreq_tg_fifo_full : 1;
		unsigned int             tf_data_fifo_busy_q : 1;
		unsigned int              tf_data_fifo_rtr_q : 1;
		unsigned int              tf_skid_fifo_empty : 1;
		unsigned int               tf_skid_fifo_full : 1;
		unsigned int               wd_tc_rdreq_rtr_q : 1;
		unsigned int               last_req_of_tg_p2 : 1;
		unsigned int         se0spi_wd_hs_done_cnt_q : 6;
		unsigned int                 event_flag_p1_q : 1;
		unsigned int                  null_flag_p1_q : 1;
		unsigned int              tf_data_fifo_cnt_q : 7;
		unsigned int            second_tf_ret_data_q : 1;
		unsigned int            first_req_of_tg_p1_q : 1;
		unsigned int            WD_TC_rdreq_send_out : 1;
		unsigned int           WD_TC_rdnfo_stall_out : 1;
		unsigned int            TC_WD_rdret_valid_in : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_DEBUG_REG9__VI {
	struct {
		unsigned int                        pipe0_dr : 1;
		unsigned int                     pipec_tf_dr : 1;
		unsigned int                        pipe2_dr : 1;
		unsigned int        event_or_null_flags_p0_q : 1;
		unsigned int                       pipe0_rtr : 1;
		unsigned int                       pipe1_rtr : 1;
		unsigned int                    pipec_tf_rtr : 1;
		unsigned int                       pipe2_rtr : 1;
		unsigned int             ttp_patch_fifo_full : 1;
		unsigned int            ttp_patch_fifo_empty : 1;
		unsigned int               ttp_tf_fifo_empty : 1;
		unsigned int                          SPARE0 : 5;
		unsigned int                tf_fetch_state_q : 3;
		unsigned int                last_patch_of_tg : 1;
		unsigned int                 tf_pointer_p0_q : 4;
		unsigned int                 dynamic_hs_p0_q : 1;
		unsigned int          first_fetch_of_tg_p0_q : 1;
		unsigned int                     mem_is_even : 1;
		unsigned int                          SPARE1 : 1;
		unsigned int                          SPARE2 : 2;
		unsigned int                        pipe4_dr : 1;
		unsigned int                       pipe4_rtr : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union WD_QOS__VI {
	struct {
		unsigned int                      DRAW_STALL : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_AON_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int        XDMA_AON_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_AON_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int       XDMA_AON_TEST_DEBUG_INDEX : 8;
		unsigned int    XDMA_AON_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                  XDMA_DEBUG_SEL : 1;
		unsigned int               XDMA_DEBUG_OUT_EN : 1;
		unsigned int                                 : 21;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_CLOCK_GATING_CNTL__VI {
	struct {
		unsigned int         XDMA_SCLK_TURN_ON_DELAY : 4;
		unsigned int        XDMA_SCLK_TURN_OFF_DELAY : 8;
		unsigned int                                 : 3;
		unsigned int              XDMA_SCLK_GATE_DIS : 1;
		unsigned int          XDMA_SCLK_REG_GATE_DIS : 1;
		unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0 : 1;
		unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1 : 1;
		unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2 : 1;
		unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3 : 1;
		unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4 : 1;
		unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5 : 1;
		unsigned int       XDMA_SCLK_G_SDYN_GATE_DIS : 1;
		unsigned int      XDMA_SCLK_G_MSTAT_GATE_DIS : 1;
		unsigned int      XDMA_SCLK_G_SSTAT_GATE_DIS : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_IF_BIF_STATUS__VI {
	struct {
		unsigned int        XDMA_IF_BIF_ERROR_STATUS : 4;
		unsigned int                                 : 4;
		unsigned int         XDMA_IF_BIF_ERROR_CLEAR : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_IF_STATUS__VI {
	struct {
		unsigned int             XDMA_MC_PCIEWR_BUSY : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_INTERRUPT__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int       XDMA_MSTR_MEM_URGENT_STAT : 1;
		unsigned int       XDMA_MSTR_MEM_URGENT_MASK : 1;
		unsigned int        XDMA_MSTR_MEM_URGENT_ACK : 1;
		unsigned int                                 : 5;
		unsigned int       XDMA_SLV_READ_URGENT_STAT : 1;
		unsigned int       XDMA_SLV_READ_URGENT_MASK : 1;
		unsigned int        XDMA_SLV_READ_URGENT_ACK : 1;
		unsigned int                                 : 1;
		unsigned int             XDMA_PERF_MEAS_STAT : 1;
		unsigned int             XDMA_PERF_MEAS_MASK : 1;
		unsigned int              XDMA_PERF_MEAS_ACK : 1;
		unsigned int                                 : 9;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_LOCAL_SURFACE_TILING1__VI {
	struct {
		unsigned int           XDMA_LOCAL_ARRAY_MODE : 4;
		unsigned int           XDMA_LOCAL_TILE_SPLIT : 3;
		unsigned int                                 : 1;
		unsigned int           XDMA_LOCAL_BANK_WIDTH : 2;
		unsigned int          XDMA_LOCAL_BANK_HEIGHT : 2;
		unsigned int    XDMA_LOCAL_MACRO_TILE_ASPECT : 2;
		unsigned int                                 : 6;
		unsigned int            XDMA_LOCAL_NUM_BANKS : 2;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_LOCAL_SURFACE_TILING2__VI {
	struct {
		unsigned int XDMA_LOCAL_PIPE_INTERLEAVE_SIZE : 3;
		unsigned int                                 : 17;
		unsigned int      XDMA_LOCAL_MICRO_TILE_MODE : 3;
		unsigned int                                 : 4;
		unsigned int          XDMA_LOCAL_PIPE_CONFIG : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MC_PCIE_CLIENT_CONFIG__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int               XDMA_MC_PCIE_SWAP : 2;
		unsigned int                                 : 2;
		unsigned int               XDMA_MC_PCIE_VMID : 4;
		unsigned int               XDMA_MC_PCIE_PRIV : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MEM_POWER_CNTL__VI {
	struct {
		unsigned int        XDMA_MEM_CORE_IDLE_STATE : 2;
		unsigned int          XDMA_MEM_IF_IDLE_STATE : 2;
		unsigned int                                 : 15;
		unsigned int          XDMA_MEM_IF_PCIE_STATE : 2;
		unsigned int          XDMA_MEM_IF_PCIE_TRANS : 1;
		unsigned int            XDMA_MEM_IF_RD_STATE : 2;
		unsigned int                                 : 1;
		unsigned int            XDMA_MEM_IF_RD_TRANS : 1;
		unsigned int            XDMA_MEM_IF_WR_STATE : 2;
		unsigned int            XDMA_MEM_IF_WR_TRANS : 1;
		unsigned int           XDMA_MEM_IF_BIF_STATE : 2;
		unsigned int           XDMA_MEM_IF_BIF_TRANS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_CACHE__VI {
	struct {
		unsigned int           XDMA_MSTR_CACHE_PITCH : 14;
		unsigned int                                 : 15;
		unsigned int    XDMA_MSTR_CACHE_TLB_PG_STATE : 2;
		unsigned int    XDMA_MSTR_CACHE_TLB_PG_TRANS : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_CACHE_BASE_ADDR__VI {
	struct {
		unsigned int       XDMA_MSTR_CACHE_BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI {
	struct {
		unsigned int  XDMA_MSTR_CACHE_BASE_ADDR_HIGH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_CHANNEL_DIM__VI {
	struct {
		unsigned int         XDMA_MSTR_CHANNEL_WIDTH : 14;
		unsigned int                                 : 2;
		unsigned int        XDMA_MSTR_CHANNEL_HEIGHT : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_CHANNEL_START__VI {
	struct {
		unsigned int       XDMA_MSTR_CHANNEL_START_X : 14;
		unsigned int                                 : 2;
		unsigned int       XDMA_MSTR_CHANNEL_START_Y : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_CMD_URGENT_CNTL__VI {
	struct {
		unsigned int      XDMA_MSTR_CMD_CLIENT_STALL : 1;
		unsigned int                                 : 7;
		unsigned int      XDMA_MSTR_CMD_URGENT_LEVEL : 4;
		unsigned int       XDMA_MSTR_CMD_STALL_DELAY : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_CNTL__VI {
	struct {
		unsigned int                                 : 12;
		unsigned int        XDMA_MSTR_ALPHA_POSITION : 2;
		unsigned int             XDMA_MSTR_MEM_READY : 1;
		unsigned int                                 : 1;
		unsigned int                XDMA_MSTR_ENABLE : 1;
		unsigned int                                 : 1;
		unsigned int            XDMA_MSTR_DEBUG_MODE : 1;
		unsigned int                                 : 1;
		unsigned int            XDMA_MSTR_SOFT_RESET : 1;
		unsigned int          XDMA_MSTR_BIF_STALL_EN : 1;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_HEIGHT__VI {
	struct {
		unsigned int         XDMA_MSTR_ACTIVE_HEIGHT : 14;
		unsigned int                                 : 2;
		unsigned int          XDMA_MSTR_FRAME_HEIGHT : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__VI {
	struct {
		unsigned int XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__VI {
	struct {
		unsigned int XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_LOCAL_SURFACE_PITCH__VI {
	struct {
		unsigned int   XDMA_MSTR_LOCAL_SURFACE_PITCH : 14;
		unsigned int                                 : 18;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_MEM_CLIENT_CONFIG__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int       XDMA_MSTR_MEM_CLIENT_SWAP : 2;
		unsigned int                                 : 2;
		unsigned int       XDMA_MSTR_MEM_CLIENT_VMID : 4;
		unsigned int       XDMA_MSTR_MEM_CLIENT_PRIV : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_MEM_NACK_STATUS__VI {
	struct {
		unsigned int          XDMA_MSTR_MEM_NACK_TAG : 10;
		unsigned int                                 : 2;
		unsigned int              XDMA_MSTR_MEM_NACK : 2;
		unsigned int                                 : 2;
		unsigned int          XDMA_MSTR_MEM_NACK_CLR : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_MEM_URGENT_CNTL__VI {
	struct {
		unsigned int      XDMA_MSTR_MEM_CLIENT_STALL : 1;
		unsigned int                                 : 3;
		unsigned int      XDMA_MSTR_MEM_URGENT_LIMIT : 4;
		unsigned int      XDMA_MSTR_MEM_URGENT_LEVEL : 4;
		unsigned int       XDMA_MSTR_MEM_STALL_DELAY : 4;
		unsigned int      XDMA_MSTR_MEM_URGENT_TIMER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_PCIE_NACK_STATUS__VI {
	struct {
		unsigned int         XDMA_MSTR_PCIE_NACK_TAG : 10;
		unsigned int                                 : 2;
		unsigned int             XDMA_MSTR_PCIE_NACK : 2;
		unsigned int                                 : 2;
		unsigned int         XDMA_MSTR_PCIE_NACK_CLR : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_PERFMEAS_CNTL__VI {
	struct {
		unsigned int    XDMA_MSTR_CACHE_BW_MEAS_ITER : 12;
		unsigned int    XDMA_MSTR_CACHE_BW_SEGID_SEL : 5;
		unsigned int  XDMA_MSTR_CACHE_BW_COUNTER_RST : 1;
		unsigned int                                 : 1;
		unsigned int          XDMA_MSTR_LT_MEAS_ITER : 12;
		unsigned int        XDMA_MSTR_LT_COUNTER_RST : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_PERFMEAS_STATUS__VI {
	struct {
		unsigned int         XDMA_MSTR_PERFMEAS_DATA : 24;
		unsigned int        XDMA_MSTR_PERFMEAS_INDEX : 3;
		unsigned int                                 : 3;
		unsigned int   XDMA_MSTR_PERFMEAS_INDEX_MODE : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_PIPE_CNTL__VI {
	struct {
		unsigned int           XDMA_MSTR_CACHE_LINES : 8;
		unsigned int          XDMA_MSTR_READ_REQUEST : 1;
		unsigned int       XDMA_MSTR_PIPE_FRAME_MODE : 1;
		unsigned int       XDMA_MSTR_PIPE_SOFT_RESET : 1;
		unsigned int      XDMA_MSTR_CACHE_INVALIDATE : 1;
		unsigned int    XDMA_MSTR_REQUEST_CHANNEL_ID : 3;
		unsigned int             XDMA_MSTR_FLIP_MODE : 1;
		unsigned int           XDMA_MSTR_REQUEST_MIN : 8;
		unsigned int           XDMA_MSTR_PIPE_ACTIVE : 1;
		unsigned int         XDMA_MSTR_PIPE_FLUSHING : 1;
		unsigned int     XDMA_MSTR_PIPE_FLIP_PENDING : 1;
		unsigned int      XDMA_MSTR_VSYNC_GSL_ENABLE : 1;
		unsigned int        XDMA_MSTR_SUPERAA_ENABLE : 1;
		unsigned int       XDMA_MSTR_HSYNC_GSL_GROUP : 2;
		unsigned int      XDMA_MSTR_GSL_GROUP_MASTER : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_READ_COMMAND__VI {
	struct {
		unsigned int          XDMA_MSTR_REQUEST_SIZE : 14;
		unsigned int                                 : 2;
		unsigned int      XDMA_MSTR_REQUEST_PREFETCH : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_REMOTE_GPU_ADDRESS__VI {
	struct {
		unsigned int    XDMA_MSTR_REMOTE_GPU_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI {
	struct {
		unsigned int XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_REMOTE_SURFACE_BASE__VI {
	struct {
		unsigned int   XDMA_MSTR_REMOTE_SURFACE_BASE : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI {
	struct {
		unsigned int XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_STATUS__VI {
	struct {
		unsigned int        XDMA_MSTR_VCOUNT_CURRENT : 14;
		unsigned int                                 : 2;
		unsigned int    XDMA_MSTR_WRITE_LINE_CURRENT : 12;
		unsigned int         XDMA_MSTR_STATUS_SELECT : 3;
		unsigned int                                 : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_MSTR_VSYNC_GSL_CHECK__VI {
	struct {
		unsigned int   XDMA_MSTR_VSYNC_GSL_CHECK_SEL : 3;
		unsigned int                                 : 5;
		unsigned int XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT : 14;
		unsigned int                                 : 10;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_PERF_MEAS_STATUS__VI {
	struct {
		unsigned int           XDMA_PERF_MEAS_STATUS : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_PG_CONTROL__VI {
	struct {
		unsigned int                 XDMA_PG_CONTROL : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_PG_STATUS__VI {
	struct {
		unsigned int               XDMA_SERDES_RDATA : 24;
		unsigned int           XDMA_PGFSM_READ_READY : 1;
		unsigned int                XDMA_SERDES_BUSY : 1;
		unsigned int    XDMA_SERDES_SMU_POWER_STATUS : 1;
		unsigned int                                 : 5;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_PG_WDATA__VI {
	struct {
		unsigned int                   XDMA_PG_WDATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_RBBMIF_RDWR_CNTL__VI {
	struct {
		unsigned int          XDMA_RBBMIF_RDWR_DELAY : 3;
		unsigned int    XDMA_RBBMIF_RDWR_TIMEOUT_DIS : 1;
		unsigned int                                 : 11;
		unsigned int       XDMA_RBBMIF_TIMEOUT_DELAY : 17;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_CHANNEL_CNTL__VI {
	struct {
		unsigned int         XDMA_SLV_CHANNEL_WEIGHT : 9;
		unsigned int                                 : 7;
		unsigned int          XDMA_SLV_STOP_TRANSFER : 1;
		unsigned int     XDMA_SLV_CHANNEL_SOFT_RESET : 1;
		unsigned int                                 : 6;
		unsigned int         XDMA_SLV_CHANNEL_ACTIVE : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_CNTL__VI {
	struct {
		unsigned int             XDMA_SLV_READ_LINES : 1;
		unsigned int                                 : 8;
		unsigned int              XDMA_SLV_MEM_READY : 1;
		unsigned int                 XDMA_SLV_ACTIVE : 1;
		unsigned int                                 : 1;
		unsigned int         XDMA_SLV_ALPHA_POSITION : 2;
		unsigned int                                 : 2;
		unsigned int                 XDMA_SLV_ENABLE : 1;
		unsigned int                                 : 2;
		unsigned int       XDMA_SLV_READ_LAT_TEST_EN : 1;
		unsigned int             XDMA_SLV_SOFT_RESET : 1;
		unsigned int                                 : 3;
		unsigned int          XDMA_SLV_REQ_MAXED_OUT : 1;
		unsigned int         XDMA_SLV_WB_BURST_RESET : 1;
		unsigned int                                 : 6;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_FLIP_PENDING__VI {
	struct {
		unsigned int           XDMA_SLV_FLIP_PENDING : 1;
		unsigned int                                 : 31;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_MEM_CLIENT_CONFIG__VI {
	struct {
		unsigned int                                 : 8;
		unsigned int        XDMA_SLV_MEM_CLIENT_SWAP : 2;
		unsigned int                                 : 2;
		unsigned int        XDMA_SLV_MEM_CLIENT_VMID : 4;
		unsigned int        XDMA_SLV_MEM_CLIENT_PRIV : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_MEM_NACK_STATUS__VI {
	struct {
		unsigned int           XDMA_SLV_MEM_NACK_TAG : 16;
		unsigned int               XDMA_SLV_MEM_NACK : 2;
		unsigned int                                 : 13;
		unsigned int           XDMA_SLV_MEM_NACK_CLR : 1;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_PCIE_NACK_STATUS__VI {
	struct {
		unsigned int          XDMA_SLV_PCIE_NACK_TAG : 10;
		unsigned int                                 : 2;
		unsigned int              XDMA_SLV_PCIE_NACK : 2;
		unsigned int                                 : 2;
		unsigned int          XDMA_SLV_PCIE_NACK_CLR : 1;
		unsigned int                                 : 15;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_RDRET_BUF_STATUS__VI {
	struct {
		unsigned int     XDMA_SLV_RDRET_FREE_ENTRIES : 10;
		unsigned int                                 : 2;
		unsigned int         XDMA_SLV_RDRET_BUF_SIZE : 10;
		unsigned int         XDMA_SLV_RDRET_PG_STATE : 2;
		unsigned int         XDMA_SLV_RDRET_PG_TRANS : 1;
		unsigned int                                 : 7;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_READ_LATENCY_AVE__VI {
	struct {
		unsigned int       XDMA_SLV_READ_LATENCY_ACC : 20;
		unsigned int     XDMA_SLV_READ_LATENCY_COUNT : 12;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_READ_LATENCY_MINMAX__VI {
	struct {
		unsigned int       XDMA_SLV_READ_LATENCY_MIN : 16;
		unsigned int       XDMA_SLV_READ_LATENCY_MAX : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_READ_LATENCY_TIMER__VI {
	struct {
		unsigned int     XDMA_SLV_READ_LATENCY_TIMER : 16;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_READ_URGENT_CNTL__VI {
	struct {
		unsigned int      XDMA_SLV_READ_CLIENT_STALL : 1;
		unsigned int                                 : 3;
		unsigned int      XDMA_SLV_READ_URGENT_LIMIT : 4;
		unsigned int      XDMA_SLV_READ_URGENT_LEVEL : 4;
		unsigned int       XDMA_SLV_READ_STALL_DELAY : 4;
		unsigned int      XDMA_SLV_READ_URGENT_TIMER : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_REMOTE_GPU_ADDRESS__VI {
	struct {
		unsigned int     XDMA_SLV_REMOTE_GPU_ADDRESS : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI {
	struct {
		unsigned int XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH : 8;
		unsigned int                                 : 24;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_SLS_PITCH__VI {
	struct {
		unsigned int              XDMA_SLV_SLS_PITCH : 14;
		unsigned int                                 : 2;
		unsigned int              XDMA_SLV_SLS_WIDTH : 14;
		unsigned int                                 : 2;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_WB_RATE_CNTL__VI {
	struct {
		unsigned int          XDMA_SLV_WB_BURST_SIZE : 9;
		unsigned int                                 : 7;
		unsigned int        XDMA_SLV_WB_BURST_PERIOD : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_SLV_WRITE_URGENT_CNTL__VI {
	struct {
		unsigned int            XDMA_SLV_WRITE_STALL : 1;
		unsigned int                                 : 7;
		unsigned int     XDMA_SLV_WRITE_URGENT_LEVEL : 4;
		unsigned int      XDMA_SLV_WRITE_STALL_DELAY : 4;
		unsigned int                                 : 16;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_TEST_DEBUG_DATA__VI {
	struct {
		unsigned int            XDMA_TEST_DEBUG_DATA : 32;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

	union XDMA_TEST_DEBUG_INDEX__VI {
	struct {
		unsigned int           XDMA_TEST_DEBUG_INDEX : 8;
		unsigned int        XDMA_TEST_DEBUG_WRITE_EN : 1;
		unsigned int                                 : 23;
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
	};

} // inline namespace Chip
} // namespace Gfx6
} // namespace Pal

#endif
