/*
 ***********************************************************************************************************************
 *
 *  Copyright (c) 2014-2021 Advanced Micro Devices, Inc. All Rights Reserved.
 *
 *  Permission is hereby granted, free of charge, to any person obtaining a copy
 *  of this software and associated documentation files (the "Software"), to deal
 *  in the Software without restriction, including without limitation the rights
 *  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 *  copies of the Software, and to permit persons to whom the Software is
 *  furnished to do so, subject to the following conditions:
 *
 *  The above copyright notice and this permission notice shall be included in all
 *  copies or substantial portions of the Software.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 *  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 *  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 *  SOFTWARE.
 *
 **********************************************************************************************************************/

#if !defined (__SI__CI__VI_MERGED_ENUM_HEADER)
#define __SI__CI__VI_MERGED_ENUM_HEADER

namespace Pal
{
namespace Gfx6
{
inline namespace Chip
{

typedef enum ArrayMode {
ARRAY_LINEAR_GENERAL                     = 0x00000000,
ARRAY_LINEAR_ALIGNED                     = 0x00000001,
ARRAY_1D_TILED_THIN1                     = 0x00000002,
ARRAY_1D_TILED_THICK                     = 0x00000003,
ARRAY_2D_TILED_THIN1                     = 0x00000004,
ARRAY_2D_TILED_THIN2__SI                 = 0x00000005,
ARRAY_PRT_TILED_THIN1__CI__VI            = 0x00000005,
ARRAY_2D_TILED_THIN4__SI                 = 0x00000006,
ARRAY_PRT_2D_TILED_THIN1__CI__VI         = 0x00000006,
ARRAY_2D_TILED_THICK                     = 0x00000007,
ARRAY_2D_TILED_XTHICK                    = 0x00000008,
ARRAY_2B_TILED_THIN2__SI                 = 0x00000009,
ARRAY_PRT_TILED_THICK__CI__VI            = 0x00000009,
ARRAY_2B_TILED_THIN4__SI                 = 0x0000000a,
ARRAY_PRT_2D_TILED_THICK__CI__VI         = 0x0000000a,
ARRAY_2B_TILED_THICK__SI                 = 0x0000000b,
ARRAY_PRT_3D_TILED_THIN1__CI__VI         = 0x0000000b,
ARRAY_3D_TILED_THIN1                     = 0x0000000c,
ARRAY_3D_TILED_THICK                     = 0x0000000d,
ARRAY_3D_TILED_XTHICK                    = 0x0000000e,
ARRAY_POWER_SAVE__SI                     = 0x0000000f,
ARRAY_PRT_3D_TILED_THICK__CI__VI         = 0x0000000f,
} ArrayMode;

typedef enum BUF_DATA_FORMAT {
BUF_DATA_FORMAT_INVALID                  = 0x00000000,
BUF_DATA_FORMAT_8                        = 0x00000001,
BUF_DATA_FORMAT_16                       = 0x00000002,
BUF_DATA_FORMAT_8_8                      = 0x00000003,
BUF_DATA_FORMAT_32                       = 0x00000004,
BUF_DATA_FORMAT_16_16                    = 0x00000005,
BUF_DATA_FORMAT_10_11_11                 = 0x00000006,
BUF_DATA_FORMAT_11_11_10                 = 0x00000007,
BUF_DATA_FORMAT_10_10_10_2               = 0x00000008,
BUF_DATA_FORMAT_2_10_10_10               = 0x00000009,
BUF_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
BUF_DATA_FORMAT_32_32                    = 0x0000000b,
BUF_DATA_FORMAT_16_16_16_16              = 0x0000000c,
BUF_DATA_FORMAT_32_32_32                 = 0x0000000d,
BUF_DATA_FORMAT_32_32_32_32              = 0x0000000e,
BUF_DATA_FORMAT_RESERVED_15              = 0x0000000f,
} BUF_DATA_FORMAT;

typedef enum BUF_NUM_FORMAT {
BUF_NUM_FORMAT_UNORM                     = 0x00000000,
BUF_NUM_FORMAT_SNORM                     = 0x00000001,
BUF_NUM_FORMAT_USCALED                   = 0x00000002,
BUF_NUM_FORMAT_SSCALED                   = 0x00000003,
BUF_NUM_FORMAT_UINT                      = 0x00000004,
BUF_NUM_FORMAT_SINT                      = 0x00000005,
BUF_NUM_FORMAT_SNORM_OGL__SI__CI         = 0x00000006,
BUF_NUM_FORMAT_RESERVED_6__VI            = 0x00000006,
BUF_NUM_FORMAT_FLOAT                     = 0x00000007,
} BUF_NUM_FORMAT;

typedef enum BankHeight {
ADDR_SURF_BANK_HEIGHT_1                  = 0x00000000,
ADDR_SURF_BANK_HEIGHT_2                  = 0x00000001,
ADDR_SURF_BANK_HEIGHT_4                  = 0x00000002,
ADDR_SURF_BANK_HEIGHT_8                  = 0x00000003,
} BankHeight;

typedef enum BankInterleaveSize {
ADDR_CONFIG_BANK_INTERLEAVE_1            = 0x00000000,
ADDR_CONFIG_BANK_INTERLEAVE_2            = 0x00000001,
ADDR_CONFIG_BANK_INTERLEAVE_4            = 0x00000002,
ADDR_CONFIG_BANK_INTERLEAVE_8            = 0x00000003,
} BankInterleaveSize;

typedef enum BankSwapBytes {
CONFIG_128B_SWAPS                        = 0x00000000,
CONFIG_256B_SWAPS                        = 0x00000001,
CONFIG_512B_SWAPS                        = 0x00000002,
CONFIG_1KB_SWAPS                         = 0x00000003,
} BankSwapBytes;

typedef enum BankTiling {
CONFIG_4_BANK                            = 0x00000000,
CONFIG_8_BANK                            = 0x00000001,
} BankTiling;

typedef enum BankWidth {
ADDR_SURF_BANK_WIDTH_1                   = 0x00000000,
ADDR_SURF_BANK_WIDTH_2                   = 0x00000001,
ADDR_SURF_BANK_WIDTH_4                   = 0x00000002,
ADDR_SURF_BANK_WIDTH_8                   = 0x00000003,
} BankWidth;

typedef enum BankWidthHeight {
ADDR_SURF_BANK_WH_1                      = 0x00000000,
ADDR_SURF_BANK_WH_2                      = 0x00000001,
ADDR_SURF_BANK_WH_4                      = 0x00000002,
ADDR_SURF_BANK_WH_8                      = 0x00000003,
} BankWidthHeight;

typedef enum BlendOp {
BLEND_ZERO                               = 0x00000000,
BLEND_ONE                                = 0x00000001,
BLEND_SRC_COLOR                          = 0x00000002,
BLEND_ONE_MINUS_SRC_COLOR                = 0x00000003,
BLEND_SRC_ALPHA                          = 0x00000004,
BLEND_ONE_MINUS_SRC_ALPHA                = 0x00000005,
BLEND_DST_ALPHA                          = 0x00000006,
BLEND_ONE_MINUS_DST_ALPHA                = 0x00000007,
BLEND_DST_COLOR                          = 0x00000008,
BLEND_ONE_MINUS_DST_COLOR                = 0x00000009,
BLEND_SRC_ALPHA_SATURATE                 = 0x0000000a,
BLEND_BOTH_SRC_ALPHA                     = 0x0000000b,
BLEND_BOTH_INV_SRC_ALPHA                 = 0x0000000c,
BLEND_CONSTANT_COLOR                     = 0x0000000d,
BLEND_ONE_MINUS_CONSTANT_COLOR           = 0x0000000e,
BLEND_SRC1_COLOR                         = 0x0000000f,
BLEND_INV_SRC1_COLOR                     = 0x00000010,
BLEND_SRC1_ALPHA                         = 0x00000011,
BLEND_INV_SRC1_ALPHA                     = 0x00000012,
BLEND_CONSTANT_ALPHA                     = 0x00000013,
BLEND_ONE_MINUS_CONSTANT_ALPHA           = 0x00000014,
} BlendOp;

typedef enum BlendOpt {
FORCE_OPT_AUTO                           = 0x00000000,
FORCE_OPT_DISABLE                        = 0x00000001,
FORCE_OPT_ENABLE_IF_SRC_A_0              = 0x00000002,
FORCE_OPT_ENABLE_IF_SRC_RGB_0            = 0x00000003,
FORCE_OPT_ENABLE_IF_SRC_ARGB_0           = 0x00000004,
FORCE_OPT_ENABLE_IF_SRC_A_1              = 0x00000005,
FORCE_OPT_ENABLE_IF_SRC_RGB_1            = 0x00000006,
FORCE_OPT_ENABLE_IF_SRC_ARGB_1           = 0x00000007,
} BlendOpt;

typedef enum CBMode {
CB_DISABLE                               = 0x00000000,
CB_NORMAL                                = 0x00000001,
CB_ELIMINATE_FAST_CLEAR                  = 0x00000002,
CB_RESOLVE                               = 0x00000003,
CB_DECOMPRESS                            = 0x00000004,
CB_FMASK_DECOMPRESS                      = 0x00000005,
CB_DCC_DECOMPRESS__VI                    = 0x00000006,
} CBMode;

typedef enum CBPerfClearFilterSel {
CB_PERF_CLEAR_FILTER_SEL_NONCLEAR        = 0x00000000,
CB_PERF_CLEAR_FILTER_SEL_CLEAR           = 0x00000001,
} CBPerfClearFilterSel;

typedef enum CBPerfOpFilterSel {
CB_PERF_OP_FILTER_SEL_WRITE_ONLY         = 0x00000000,
CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION  = 0x00000001,
CB_PERF_OP_FILTER_SEL_RESOLVE            = 0x00000002,
CB_PERF_OP_FILTER_SEL_DECOMPRESS         = 0x00000003,
CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS   = 0x00000004,
CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005,
} CBPerfOpFilterSel;

typedef enum CBPerfSel {
CB_PERF_SEL_NONE                         = 0x00000000,
CB_PERF_SEL_BUSY                         = 0x00000001,
CB_PERF_SEL_CORE_SCLK_VLD                = 0x00000002,
CB_PERF_SEL_REG_SCLK0_VLD                = 0x00000003,
CB_PERF_SEL_REG_SCLK1_VLD                = 0x00000004,
CB_PERF_SEL_DRAWN_QUAD                   = 0x00000005,
CB_PERF_SEL_DRAWN_PIXEL                  = 0x00000006,
CB_PERF_SEL_DRAWN_QUAD_FRAGMENT          = 0x00000007,
CB_PERF_SEL_DRAWN_TILE                   = 0x00000008,
CB_PERF_SEL_DB_CB_TILE_VALID_READY       = 0x00000009,
CB_PERF_SEL_DB_CB_TILE_VALID_READYB      = 0x0000000a,
CB_PERF_SEL_DB_CB_TILE_VALIDB_READY      = 0x0000000b,
CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB     = 0x0000000c,
CB_PERF_SEL_CM_FC_TILE_VALID_READY       = 0x0000000d,
CB_PERF_SEL_CM_FC_TILE_VALID_READYB      = 0x0000000e,
CB_PERF_SEL_CM_FC_TILE_VALIDB_READY      = 0x0000000f,
CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB     = 0x00000010,
CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY  = 0x00000011,
CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012,
CB_PERF_SEL_DB_CB_LQUAD_VALID_READY      = 0x00000013,
CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB     = 0x00000014,
CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY     = 0x00000015,
CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB    = 0x00000016,
CB_PERF_SEL_LQUAD_NO_TILE                = 0x00000017,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R  = 0x00000018,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d,
CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f,
CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020,
CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022,
CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023,
CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY    = 0x00000024,
CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB   = 0x00000025,
CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY   = 0x00000026,
CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB  = 0x00000027,
CB_PERF_SEL_FOP_IN_VALID_READY           = 0x00000028,
CB_PERF_SEL_FOP_IN_VALID_READYB          = 0x00000029,
CB_PERF_SEL_FOP_IN_VALIDB_READY          = 0x0000002a,
CB_PERF_SEL_FOP_IN_VALIDB_READYB         = 0x0000002b,
CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY   = 0x0000002c,
CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB  = 0x0000002d,
CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY  = 0x0000002e,
CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f,
CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY    = 0x00000030,
CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB   = 0x00000031,
CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY   = 0x00000032,
CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB  = 0x00000033,
CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY    = 0x00000034,
CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB   = 0x00000035,
CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY   = 0x00000036,
CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB  = 0x00000037,
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038,
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039,
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a,
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b,
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c,
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d,
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e,
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f,
CB_PERF_SEL_CC_BC_CS_FRAG_VALID          = 0x00000040,
CB_PERF_SEL_CM_CACHE_HIT                 = 0x00000041,
CB_PERF_SEL_CM_CACHE_TAG_MISS            = 0x00000042,
CB_PERF_SEL_CM_CACHE_SECTOR_MISS         = 0x00000043,
CB_PERF_SEL_CM_CACHE_REEVICTION_STALL    = 0x00000044,
CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046,
CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL   = 0x00000048,
CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL  = 0x00000049,
CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL    = 0x0000004a,
CB_PERF_SEL_CM_CACHE_STALL               = 0x0000004b,
CB_PERF_SEL_CM_CACHE_FLUSH               = 0x0000004c,
CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED        = 0x0000004d,
CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED     = 0x0000004e,
CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f,
CB_PERF_SEL_FC_CACHE_HIT                 = 0x00000050,
CB_PERF_SEL_FC_CACHE_TAG_MISS            = 0x00000051,
CB_PERF_SEL_FC_CACHE_SECTOR_MISS         = 0x00000052,
CB_PERF_SEL_FC_CACHE_REEVICTION_STALL    = 0x00000053,
CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055,
CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL   = 0x00000057,
CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL  = 0x00000058,
CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL    = 0x00000059,
CB_PERF_SEL_FC_CACHE_STALL               = 0x0000005a,
CB_PERF_SEL_FC_CACHE_FLUSH               = 0x0000005b,
CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED        = 0x0000005c,
CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED     = 0x0000005d,
CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e,
CB_PERF_SEL_CC_CACHE_HIT                 = 0x0000005f,
CB_PERF_SEL_CC_CACHE_TAG_MISS            = 0x00000060,
CB_PERF_SEL_CC_CACHE_SECTOR_MISS         = 0x00000061,
CB_PERF_SEL_CC_CACHE_REEVICTION_STALL    = 0x00000062,
CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064,
CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL   = 0x00000066,
CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL  = 0x00000067,
CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL    = 0x00000068,
CB_PERF_SEL_CC_CACHE_STALL               = 0x00000069,
CB_PERF_SEL_CC_CACHE_FLUSH               = 0x0000006a,
CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED        = 0x0000006b,
CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED     = 0x0000006c,
CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d,
CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e,
CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY__SI__CI = 0x0000006f,
CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC__VI = 0x0000006f,
CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB__SI__CI = 0x00000070,
CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY__VI = 0x00000070,
CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY__SI__CI = 0x00000071,
CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB__VI = 0x00000071,
CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB__SI__CI = 0x00000072,
CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY__VI = 0x00000072,
CB_PERF_SEL_CM_MC_WRITE_REQUEST__SI__CI  = 0x00000073,
CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB__VI = 0x00000073,
CB_PERF_SEL_FC_MC_WRITE_REQUEST__SI__CI  = 0x00000074,
CB_PERF_SEL_CM_MC_WRITE_REQUEST__VI      = 0x00000074,
CB_PERF_SEL_CC_MC_WRITE_REQUEST__SI__CI  = 0x00000075,
CB_PERF_SEL_FC_MC_WRITE_REQUEST__VI      = 0x00000075,
CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT__SI__CI = 0x00000076,
CB_PERF_SEL_CC_MC_WRITE_REQUEST__VI      = 0x00000076,
CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT__SI__CI = 0x00000077,
CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000077,
CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT__SI__CI = 0x00000078,
CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000078,
CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY__SI__CI = 0x00000079,
CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000079,
CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB__SI__CI = 0x0000007a,
CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY__VI = 0x0000007a,
CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY__SI__CI = 0x0000007b,
CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB__VI = 0x0000007b,
CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB__SI__CI = 0x0000007c,
CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY__VI = 0x0000007c,
CB_PERF_SEL_CM_MC_READ_REQUEST__SI__CI   = 0x0000007d,
CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB__VI = 0x0000007d,
CB_PERF_SEL_FC_MC_READ_REQUEST__SI__CI   = 0x0000007e,
CB_PERF_SEL_CM_MC_READ_REQUEST__VI       = 0x0000007e,
CB_PERF_SEL_CC_MC_READ_REQUEST__SI__CI   = 0x0000007f,
CB_PERF_SEL_FC_MC_READ_REQUEST__VI       = 0x0000007f,
CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT__SI__CI = 0x00000080,
CB_PERF_SEL_CC_MC_READ_REQUEST__VI       = 0x00000080,
CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT__SI__CI = 0x00000081,
CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000081,
CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT__SI__CI = 0x00000082,
CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000082,
CB_PERF_SEL_CM_TQ_FULL__SI__CI           = 0x00000083,
CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000083,
CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL__SI__CI = 0x00000084,
CB_PERF_SEL_CM_TQ_FULL__VI               = 0x00000084,
CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL__SI__CI = 0x00000085,
CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL__VI = 0x00000085,
CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL__SI__CI = 0x00000086,
CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL__VI  = 0x00000086,
CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL__SI__CI = 0x00000087,
CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL__VI  = 0x00000087,
CB_PERF_SEL_FOP_FMASK_RAW_STALL__SI__CI  = 0x00000088,
CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL__VI = 0x00000088,
CB_PERF_SEL_FOP_FMASK_BYPASS_STALL__SI__CI = 0x00000089,
CB_PERF_SEL_FOP_FMASK_RAW_STALL__VI      = 0x00000089,
CB_PERF_SEL_CC_SF_FULL__SI__CI           = 0x0000008a,
CB_PERF_SEL_FOP_FMASK_BYPASS_STALL__VI   = 0x0000008a,
CB_PERF_SEL_CC_RB_FULL__SI__CI           = 0x0000008b,
CB_PERF_SEL_CC_SF_FULL__VI               = 0x0000008b,
CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL__SI__CI = 0x0000008c,
CB_PERF_SEL_CC_RB_FULL__VI               = 0x0000008c,
CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL__SI__CI = 0x0000008d,
CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL__VI = 0x0000008d,
CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL__SI__CI = 0x0000008e,
CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL__VI = 0x0000008e,
CB_PERF_SEL_EVENT__SI__CI                = 0x0000008f,
CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL__VI = 0x0000008f,
CB_PERF_SEL_EVENT_CACHE_FLUSH_TS__SI__CI = 0x00000090,
CB_PERF_SEL_EVENT__VI                    = 0x00000090,
CB_PERF_SEL_EVENT_CONTEXT_DONE__SI__CI   = 0x00000091,
CB_PERF_SEL_EVENT_CACHE_FLUSH_TS__VI     = 0x00000091,
CB_PERF_SEL_EVENT_CACHE_FLUSH__SI__CI    = 0x00000092,
CB_PERF_SEL_EVENT_CONTEXT_DONE__VI       = 0x00000092,
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__SI__CI = 0x00000093,
CB_PERF_SEL_EVENT_CACHE_FLUSH__VI        = 0x00000093,
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT__SI__CI = 0x00000094,
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__VI = 0x00000094,
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS__SI__CI = 0x00000095,
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT__VI = 0x00000095,
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META__SI__CI = 0x00000096,
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS__VI = 0x00000096,
CB_PERF_SEL_CC_SURFACE_SYNC__SI__CI      = 0x00000097,
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META__VI = 0x00000097,
CB_PERF_SEL_CMASK_READ_DATA_0xC__SI__CI  = 0x00000098,
CB_PERF_SEL_CC_SURFACE_SYNC__VI          = 0x00000098,
CB_PERF_SEL_CMASK_READ_DATA_0xD__SI__CI  = 0x00000099,
CB_PERF_SEL_CMASK_READ_DATA_0xC__VI      = 0x00000099,
CB_PERF_SEL_CMASK_READ_DATA_0xE__SI__CI  = 0x0000009a,
CB_PERF_SEL_CMASK_READ_DATA_0xD__VI      = 0x0000009a,
CB_PERF_SEL_CMASK_READ_DATA_0xF__SI__CI  = 0x0000009b,
CB_PERF_SEL_CMASK_READ_DATA_0xE__VI      = 0x0000009b,
CB_PERF_SEL_CMASK_WRITE_DATA_0xC__SI__CI = 0x0000009c,
CB_PERF_SEL_CMASK_READ_DATA_0xF__VI      = 0x0000009c,
CB_PERF_SEL_CMASK_WRITE_DATA_0xD__SI__CI = 0x0000009d,
CB_PERF_SEL_CMASK_WRITE_DATA_0xC__VI     = 0x0000009d,
CB_PERF_SEL_CMASK_WRITE_DATA_0xE__SI__CI = 0x0000009e,
CB_PERF_SEL_CMASK_WRITE_DATA_0xD__VI     = 0x0000009e,
CB_PERF_SEL_CMASK_WRITE_DATA_0xF__SI__CI = 0x0000009f,
CB_PERF_SEL_CMASK_WRITE_DATA_0xE__VI     = 0x0000009f,
CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT__SI__CI = 0x000000a0,
CB_PERF_SEL_CMASK_WRITE_DATA_0xF__VI     = 0x000000a0,
CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT__SI__CI = 0x000000a1,
CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT__VI  = 0x000000a1,
CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT__SI__CI = 0x000000a2,
CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT__VI = 0x000000a2,
CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__SI__CI = 0x000000a3,
CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT__VI = 0x000000a3,
CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a4,
CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__VI = 0x000000a4,
CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a5,
CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a5,
CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a6,
CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a6,
CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a7,
CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a7,
CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a8,
CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a8,
CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a9,
CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a9,
CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000aa,
CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000aa,
CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__SI__CI = 0x000000ab,
CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000ab,
CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000ac,
CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__VI = 0x000000ac,
CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000ad,
CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__VI = 0x000000ad,
CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000ae,
CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__VI = 0x000000ae,
CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000af,
CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__VI = 0x000000af,
CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000b0,
CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b0,
CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000b1,
CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b1,
CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000b2,
CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b2,
CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT__SI__CI = 0x000000b3,
CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b3,
CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS__SI__CI = 0x000000b4,
CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT__VI    = 0x000000b4,
CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS__SI__CI = 0x000000b5,
CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS__VI   = 0x000000b5,
CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS__SI__CI = 0x000000b6,
CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS__VI   = 0x000000b6,
CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS__SI__CI = 0x000000b7,
CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS__VI   = 0x000000b7,
CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS__SI__CI = 0x000000b8,
CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS__VI   = 0x000000b8,
CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS__SI__CI = 0x000000b9,
CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS__VI   = 0x000000b9,
CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT__SI__CI = 0x000000ba,
CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS__VI   = 0x000000ba,
CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS__SI__CI = 0x000000bb,
CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT__VI  = 0x000000bb,
CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS__SI__CI = 0x000000bc,
CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS__VI = 0x000000bc,
CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS__SI__CI = 0x000000bd,
CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS__VI = 0x000000bd,
CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS__SI__CI = 0x000000be,
CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS__VI = 0x000000be,
CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS__SI__CI = 0x000000bf,
CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS__VI = 0x000000bf,
CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS__SI__CI = 0x000000c0,
CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS__VI = 0x000000c0,
CB_PERF_SEL_QUAD_READS_FRAGMENT_0__SI__CI = 0x000000c1,
CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS__VI = 0x000000c1,
CB_PERF_SEL_QUAD_READS_FRAGMENT_1__SI__CI = 0x000000c2,
CB_PERF_SEL_QUAD_READS_FRAGMENT_0__VI    = 0x000000c2,
CB_PERF_SEL_QUAD_READS_FRAGMENT_2__SI__CI = 0x000000c3,
CB_PERF_SEL_QUAD_READS_FRAGMENT_1__VI    = 0x000000c3,
CB_PERF_SEL_QUAD_READS_FRAGMENT_3__SI__CI = 0x000000c4,
CB_PERF_SEL_QUAD_READS_FRAGMENT_2__VI    = 0x000000c4,
CB_PERF_SEL_QUAD_READS_FRAGMENT_4__SI__CI = 0x000000c5,
CB_PERF_SEL_QUAD_READS_FRAGMENT_3__VI    = 0x000000c5,
CB_PERF_SEL_QUAD_READS_FRAGMENT_5__SI__CI = 0x000000c6,
CB_PERF_SEL_QUAD_READS_FRAGMENT_4__VI    = 0x000000c6,
CB_PERF_SEL_QUAD_READS_FRAGMENT_6__SI__CI = 0x000000c7,
CB_PERF_SEL_QUAD_READS_FRAGMENT_5__VI    = 0x000000c7,
CB_PERF_SEL_QUAD_READS_FRAGMENT_7__SI__CI = 0x000000c8,
CB_PERF_SEL_QUAD_READS_FRAGMENT_6__VI    = 0x000000c8,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0__SI__CI = 0x000000c9,
CB_PERF_SEL_QUAD_READS_FRAGMENT_7__VI    = 0x000000c9,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1__SI__CI = 0x000000ca,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0__VI   = 0x000000ca,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2__SI__CI = 0x000000cb,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1__VI   = 0x000000cb,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3__SI__CI = 0x000000cc,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2__VI   = 0x000000cc,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4__SI__CI = 0x000000cd,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3__VI   = 0x000000cd,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5__SI__CI = 0x000000ce,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4__VI   = 0x000000ce,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6__SI__CI = 0x000000cf,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5__VI   = 0x000000cf,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7__SI__CI = 0x000000d0,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6__VI   = 0x000000d0,
CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST__SI__CI = 0x000000d1,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7__VI   = 0x000000d1,
CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS__SI__CI = 0x000000d2,
CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST__VI = 0x000000d2,
CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS__SI__CI = 0x000000d3,
CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS__VI = 0x000000d3,
CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS__VI = 0x000000d4,
CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED__SI__CI = 0x000000d6,
CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST__CI = 0x000000d7,
CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED__VI = 0x000000d7,
CB_PERF_SEL_DRAWN_BUSY__CI               = 0x000000d8,
CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST__VI = 0x000000d8,
CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY__CI  = 0x000000d9,
CB_PERF_SEL_DRAWN_BUSY__VI               = 0x000000d9,
CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY__CI   = 0x000000da,
CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY__VI  = 0x000000da,
CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY__CI   = 0x000000db,
CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY__VI   = 0x000000db,
CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY__CI   = 0x000000dc,
CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY__VI   = 0x000000dc,
CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY__VI   = 0x000000dd,
CB_PERF_SEL_FC_SEQUENCER_CLEAR__CI       = 0x000000de,
CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR__CI = 0x000000df,
CB_PERF_SEL_FC_SEQUENCER_CLEAR__VI       = 0x000000df,
CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS__CI = 0x000000e0,
CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR__VI = 0x000000e0,
CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS__VI = 0x000000e1,
CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL__VI = 0x000000e3,
CB_PERF_SEL_FC_DOC_IS_STALLED__VI        = 0x000000e4,
CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED__VI = 0x000000e5,
CB_PERF_SEL_FC_DOC_MRTS_COMBINED__VI     = 0x000000e6,
CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS__VI    = 0x000000e7,
CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT__VI     = 0x000000e8,
CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS__VI    = 0x000000e9,
CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT__VI     = 0x000000ea,
CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL__VI = 0x000000eb,
CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR__VI = 0x000000ec,
CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS__VI = 0x000000ed,
CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS__VI = 0x000000ee,
CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS__VI = 0x000000ef,
CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS__VI = 0x000000f0,
CB_PERF_SEL_FC_DCC_CACHE_HIT__VI         = 0x000000f1,
CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS__VI    = 0x000000f2,
CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS__VI = 0x000000f3,
CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL__VI = 0x000000f4,
CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL__VI = 0x000000f8,
CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL__VI = 0x000000f9,
CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL__VI = 0x000000fa,
CB_PERF_SEL_FC_DCC_CACHE_STALL__VI       = 0x000000fb,
CB_PERF_SEL_FC_DCC_CACHE_FLUSH__VI       = 0x000000fc,
CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED__VI = 0x000000fd,
CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED__VI = 0x000000fe,
CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED__VI = 0x000000ff,
CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT__VI = 0x00000100,
CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST__VI  = 0x00000101,
CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000102,
CB_PERF_SEL_FC_MC_DCC_READ_REQUEST__VI   = 0x00000103,
CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000104,
CB_PERF_SEL_CC_DCC_RDREQ_STALL__VI       = 0x00000105,
CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN__VI = 0x00000106,
CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT__VI = 0x00000107,
CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN__VI  = 0x00000108,
CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT__VI = 0x00000109,
CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR__VI  = 0x0000010a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1__VI = 0x0000010b,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1__VI = 0x0000011a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2__VI = 0x0000011f,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3__VI = 0x00000124,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0__VI = 0x0000015c,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1__VI = 0x0000015d,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0__VI = 0x00000163,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1__VI = 0x00000164,
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1__VI = 0x0000016b,
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1__VI = 0x0000016c,
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2__VI = 0x00000172,
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2__VI = 0x00000173,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1__VI = 0x00000174,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2__VI = 0x00000175,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3__VI = 0x00000176,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4__VI = 0x00000177,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5__VI = 0x00000178,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6__VI = 0x00000179,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7__VI = 0x0000017a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED__VI = 0x0000017b,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1__VI = 0x0000017c,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1__VI = 0x0000017d,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2__VI = 0x0000017e,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3__VI = 0x0000017f,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1__VI = 0x00000180,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2__VI = 0x00000181,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3__VI = 0x00000182,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4__VI = 0x00000183,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5__VI = 0x00000184,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1__VI = 0x00000185,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2__VI = 0x00000186,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3__VI = 0x00000187,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4__VI = 0x00000188,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5__VI = 0x00000189,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6__VI = 0x0000018a,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7__VI = 0x0000018b,
} CBPerfSel;

typedef enum CHUB_TC_RET_CREDITS_ENUM {
CHUB_TC_RET_CREDITS                      = 0x00000020,
} CHUB_TC_RET_CREDITS_ENUM;

typedef enum CLKGATE_BASE_MODE {
MULT_8                                   = 0x00000000,
MULT_16                                  = 0x00000001,
} CLKGATE_BASE_MODE;

typedef enum CLKGATE_SM_MODE {
ON_SEQ                                   = 0x00000000,
OFF_SEQ                                  = 0x00000001,
PROG_SEQ                                 = 0x00000002,
READ_SEQ                                 = 0x00000003,
SM_MODE_RESERVED                         = 0x00000004,
} CLKGATE_SM_MODE;

typedef enum CPC_PERFCOUNT_SEL {
CPC_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000001,
CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION   = 0x00000002,
CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE     = 0x00000003,
CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE     = 0x00000004,
CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x00000005,
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006,
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007,
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008,
CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ  = 0x00000009,
CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0x0000000a,
CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ  = 0x0000000b,
CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c,
CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE  = 0x0000000d,
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e,
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f,
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010,
CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ  = 0x00000011,
CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x00000012,
CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ  = 0x00000013,
CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014,
CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE  = 0x00000015,
CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE__VI = 0x00000016,
CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS__VI = 0x00000017,
CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION__VI = 0x00000018,
} CPC_PERFCOUNT_SEL;

typedef enum CPF_PERFCOUNT_SEL {
CPF_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001,
CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002,
CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003,
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING  = 0x00000004,
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1   = 0x00000005,
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2   = 0x00000006,
CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007,
CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008,
CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR         = 0x00000009,
CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR      = 0x0000000a,
CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x0000000b,
CPF_PERF_SEL_GRBM_DWORDS_SENT            = 0x0000000c,
CPF_PERF_SEL_DYNAMIC_CLOCK_VALID         = 0x0000000d,
CPF_PERF_SEL_REGISTER_CLOCK_VALID        = 0x0000000e,
CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND      = 0x0000000f,
CPF_PERF_SEL_MIU_READ_REQUEST_SEND       = 0x00000010,
CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE__VI = 0x00000011,
CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS__VI = 0x00000012,
CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION__VI = 0x00000013,
} CPF_PERFCOUNT_SEL;

typedef enum CPG_PERFCOUNT_SEL {
CPG_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
CPG_PERF_SEL_RBIU_FIFO_FULL              = 0x00000001,
CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR     = 0x00000002,
CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL  = 0x00000003,
CPG_PERF_SEL_CP_GRBM_DWORDS_SENT         = 0x00000004,
CPG_PERF_SEL_ME_PARSER_BUSY              = 0x00000005,
CPG_PERF_SEL_COUNT_TYPE0_PACKETS         = 0x00000006,
CPG_PERF_SEL_COUNT_TYPE3_PACKETS         = 0x00000007,
CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x00000008,
CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS      = 0x00000009,
CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS  = 0x0000000a,
CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS  = 0x0000000b,
CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ     = 0x0000000c,
CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ    = 0x0000000d,
CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX  = 0x0000000e,
CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f,
CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010,
CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011,
CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY    = 0x00000012,
CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY    = 0x00000013,
CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY   = 0x00000014,
CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015,
CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016,
CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017,
CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018,
CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU  = 0x00000019,
CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a,
CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b,
CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER       = 0x0000001c,
CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER     = 0x0000001d,
CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e,
CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f,
CPG_PERF_SEL_DYNAMIC_CLK_VALID           = 0x00000020,
CPG_PERF_SEL_REGISTER_CLK_VALID          = 0x00000021,
CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT      = 0x00000022,
CPG_PERF_SEL_MIU_READ_REQUEST_SENT       = 0x00000023,
CPG_PERF_SEL_CE_STALL_RAM_DUMP           = 0x00000024,
CPG_PERF_SEL_CE_STALL_RAM_WRITE          = 0x00000025,
CPG_PERF_SEL_CE_STALL_ON_INC_FIFO        = 0x00000026,
CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO     = 0x00000027,
CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU   = 0x00000028,
CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ   = 0x00000029,
CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG  = 0x0000002a,
CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER      = 0x0000002b,
CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x0000002c,
CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS     = 0x0000002d,
CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE__VI = 0x0000002e,
CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS__VI = 0x0000002f,
CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION__VI = 0x00000030,
} CPG_PERFCOUNT_SEL;

typedef enum CP_ALPHA_TAG_RAM_SEL {
CPG_TAG_RAM                              = 0x00000000,
CPC_TAG_RAM                              = 0x00000001,
CPF_TAG_RAM                              = 0x00000002,
RSV_TAG_RAM                              = 0x00000003,
} CP_ALPHA_TAG_RAM_SEL;

typedef enum CP_ME_ID {
ME_ID0                                   = 0x00000000,
ME_ID1                                   = 0x00000001,
ME_ID2                                   = 0x00000002,
ME_ID3                                   = 0x00000003,
} CP_ME_ID;

typedef enum CP_PERFMON_ENABLE_MODE {
CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT      = 0x00000000,
CP_PERFMON_ENABLE_MODE_RESERVED_1        = 0x00000001,
CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
} CP_PERFMON_ENABLE_MODE;

typedef enum CP_PERFMON_STATE {
CP_PERFMON_STATE_DISABLE_AND_RESET       = 0x00000000,
CP_PERFMON_STATE_START_COUNTING          = 0x00000001,
CP_PERFMON_STATE_STOP_COUNTING           = 0x00000002,
CP_PERFMON_STATE_RESERVED_3              = 0x00000003,
CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
} CP_PERFMON_STATE;

typedef enum CP_PIPE_ID {
PIPE_ID0                                 = 0x00000000,
PIPE_ID1                                 = 0x00000001,
PIPE_ID2                                 = 0x00000002,
PIPE_ID3                                 = 0x00000003,
} CP_PIPE_ID;

typedef enum CP_RING_ID {
RINGID0                                  = 0x00000000,
RINGID1                                  = 0x00000001,
RINGID2                                  = 0x00000002,
RINGID3__CI__VI                          = 0x00000003,
} CP_RING_ID;

typedef enum CSDATA_TYPE {
CSDATA_TYPE_TG                           = 0x00000000,
CSDATA_TYPE_STATE                        = 0x00000001,
CSDATA_TYPE_EVENT                        = 0x00000002,
CSDATA_TYPE_PRIVATE                      = 0x00000003,
} CSDATA_TYPE;

typedef enum CmaskCode {
CMASK_CLR00_F0                           = 0x00000000,
CMASK_CLR00_F1                           = 0x00000001,
CMASK_CLR00_F2                           = 0x00000002,
CMASK_CLR00_FX                           = 0x00000003,
CMASK_CLR01_F0                           = 0x00000004,
CMASK_CLR01_F1                           = 0x00000005,
CMASK_CLR01_F2                           = 0x00000006,
CMASK_CLR01_FX                           = 0x00000007,
CMASK_CLR10_F0                           = 0x00000008,
CMASK_CLR10_F1                           = 0x00000009,
CMASK_CLR10_F2                           = 0x0000000a,
CMASK_CLR10_FX                           = 0x0000000b,
CMASK_CLR11_F0                           = 0x0000000c,
CMASK_CLR11_F1                           = 0x0000000d,
CMASK_CLR11_F2                           = 0x0000000e,
CMASK_CLR11_FX                           = 0x0000000f,
} CmaskCode;

typedef enum CmaskMode {
CMASK_CLEAR_NONE                         = 0x00000000,
CMASK_CLEAR_ONE                          = 0x00000001,
CMASK_CLEAR_ALL                          = 0x00000002,
CMASK_ANY_EXPANDED                       = 0x00000003,
CMASK_ALPHA0_FRAG1                       = 0x00000004,
CMASK_ALPHA0_FRAG2                       = 0x00000005,
CMASK_ALPHA0_FRAG4                       = 0x00000006,
CMASK_ALPHA0_FRAGS                       = 0x00000007,
CMASK_ALPHA1_FRAG1                       = 0x00000008,
CMASK_ALPHA1_FRAG2                       = 0x00000009,
CMASK_ALPHA1_FRAG4                       = 0x0000000a,
CMASK_ALPHA1_FRAGS                       = 0x0000000b,
CMASK_ALPHAX_FRAG1                       = 0x0000000c,
CMASK_ALPHAX_FRAG2                       = 0x0000000d,
CMASK_ALPHAX_FRAG4                       = 0x0000000e,
CMASK_ALPHAX_FRAGS                       = 0x0000000f,
} CmaskMode;

typedef enum ColorArray {
ARRAY_2D_ALT_COLOR                       = 0x00000000,
ARRAY_2D_COLOR                           = 0x00000001,
ARRAY_3D_SLICE_COLOR                     = 0x00000003,
} ColorArray;

typedef enum ColorFormat {
COLOR_INVALID                            = 0x00000000,
COLOR_8                                  = 0x00000001,
COLOR_16                                 = 0x00000002,
COLOR_8_8                                = 0x00000003,
COLOR_32                                 = 0x00000004,
COLOR_16_16                              = 0x00000005,
COLOR_10_11_11                           = 0x00000006,
COLOR_11_11_10                           = 0x00000007,
COLOR_10_10_10_2                         = 0x00000008,
COLOR_2_10_10_10                         = 0x00000009,
COLOR_8_8_8_8                            = 0x0000000a,
COLOR_32_32                              = 0x0000000b,
COLOR_16_16_16_16                        = 0x0000000c,
COLOR_RESERVED_13                        = 0x0000000d,
COLOR_32_32_32_32                        = 0x0000000e,
COLOR_RESERVED_15                        = 0x0000000f,
COLOR_5_6_5                              = 0x00000010,
COLOR_1_5_5_5                            = 0x00000011,
COLOR_5_5_5_1                            = 0x00000012,
COLOR_4_4_4_4                            = 0x00000013,
COLOR_8_24                               = 0x00000014,
COLOR_24_8                               = 0x00000015,
COLOR_X24_8_32_FLOAT                     = 0x00000016,
COLOR_RESERVED_23                        = 0x00000017,
} ColorFormat;

typedef enum CombFunc {
COMB_DST_PLUS_SRC                        = 0x00000000,
COMB_SRC_MINUS_DST                       = 0x00000001,
COMB_MIN_DST_SRC                         = 0x00000002,
COMB_MAX_DST_SRC                         = 0x00000003,
COMB_DST_MINUS_SRC                       = 0x00000004,
} CombFunc;

typedef enum CompareFrag {
FRAG_NEVER                               = 0x00000000,
FRAG_LESS                                = 0x00000001,
FRAG_EQUAL                               = 0x00000002,
FRAG_LEQUAL                              = 0x00000003,
FRAG_GREATER                             = 0x00000004,
FRAG_NOTEQUAL                            = 0x00000005,
FRAG_GEQUAL                              = 0x00000006,
FRAG_ALWAYS                              = 0x00000007,
} CompareFrag;

typedef enum CompareRef {
REF_NEVER                                = 0x00000000,
REF_LESS                                 = 0x00000001,
REF_EQUAL                                = 0x00000002,
REF_LEQUAL                               = 0x00000003,
REF_GREATER                              = 0x00000004,
REF_NOTEQUAL                             = 0x00000005,
REF_GEQUAL                               = 0x00000006,
REF_ALWAYS                               = 0x00000007,
} CompareRef;

typedef enum ConservativeZExport {
EXPORT_ANY_Z                             = 0x00000000,
EXPORT_LESS_THAN_Z                       = 0x00000001,
EXPORT_GREATER_THAN_Z                    = 0x00000002,
EXPORT_RESERVED                          = 0x00000003,
} ConservativeZExport;

typedef enum DbPSLControl {
PSLC_AUTO                                = 0x00000000,
PSLC_ON_HANG_ONLY                        = 0x00000001,
PSLC_ASAP                                = 0x00000002,
PSLC_COUNTDOWN                           = 0x00000003,
} DbPSLControl;

typedef enum DebugBlockId {
DBG_BLOCK_ID_RESERVED__SI__CI            = 0x00000000,
DBG_CLIENT_BLKID_RESERVED__VI            = 0x00000000,
DBG_BLOCK_ID_RESERVED__VI                = 0x00000000,
DBG_BLOCK_ID_DBG__SI__CI                 = 0x00000001,
DBG_CLIENT_BLKID_dbg__VI                 = 0x00000001,
DBG_BLOCK_ID_DBG__VI                     = 0x00000001,
DBG_BLOCK_ID_VMC__SI__CI                 = 0x00000002,
DBG_CLIENT_BLKID_scf2__VI                = 0x00000002,
DBG_BLOCK_ID_VMC__VI                     = 0x00000002,
DBG_BLOCK_ID_PDMA__SI__CI                = 0x00000003,
DBG_CLIENT_BLKID_mcd5_0__VI              = 0x00000003,
DBG_BLOCK_ID_PDMA__VI                    = 0x00000003,
DBG_BLOCK_ID_CG__SI__CI                  = 0x00000004,
DBG_CLIENT_BLKID_mcd5_1__VI              = 0x00000004,
DBG_BLOCK_ID_CG__VI                      = 0x00000004,
DBG_BLOCK_ID_SRBM__SI__CI                = 0x00000005,
DBG_CLIENT_BLKID_mcd6_0__VI              = 0x00000005,
DBG_BLOCK_ID_SRBM__VI                    = 0x00000005,
DBG_BLOCK_ID_GRBM__SI__CI                = 0x00000006,
DBG_CLIENT_BLKID_mcd6_1__VI              = 0x00000006,
DBG_BLOCK_ID_GRBM__VI                    = 0x00000006,
DBG_BLOCK_ID_RLC__SI__CI                 = 0x00000007,
DBG_CLIENT_BLKID_mcd7_0__VI              = 0x00000007,
DBG_BLOCK_ID_RLC__VI                     = 0x00000007,
DBG_BLOCK_ID_CSC__SI__CI                 = 0x00000008,
DBG_CLIENT_BLKID_mcd7_1__VI              = 0x00000008,
DBG_BLOCK_ID_CSC__VI                     = 0x00000008,
DBG_BLOCK_ID_SEM__SI__CI                 = 0x00000009,
DBG_CLIENT_BLKID_vmc__VI                 = 0x00000009,
DBG_BLOCK_ID_SEM__VI                     = 0x00000009,
DBG_BLOCK_ID_IH__SI__CI                  = 0x0000000a,
DBG_CLIENT_BLKID_sx30__VI                = 0x0000000a,
DBG_BLOCK_ID_IH__VI                      = 0x0000000a,
DBG_BLOCK_ID_SC__SI__CI                  = 0x0000000b,
DBG_CLIENT_BLKID_mcd2_0__VI              = 0x0000000b,
DBG_BLOCK_ID_SC__VI                      = 0x0000000b,
DBG_BLOCK_ID_SQ__SI__CI                  = 0x0000000c,
DBG_CLIENT_BLKID_mcd2_1__VI              = 0x0000000c,
DBG_BLOCK_ID_SQ__VI                      = 0x0000000c,
DBG_BLOCK_ID_AVP__SI__CI                 = 0x0000000d,
DBG_CLIENT_BLKID_bci1__VI                = 0x0000000d,
DBG_BLOCK_ID_AVP__VI                     = 0x0000000d,
DBG_BLOCK_ID_GMCON__SI__CI               = 0x0000000e,
DBG_CLIENT_BLKID_xdma_dbg_client_wrapper__VI = 0x0000000e,
DBG_BLOCK_ID_GMCON__VI                   = 0x0000000e,
DBG_BLOCK_ID_SMU__SI__CI                 = 0x0000000f,
DBG_CLIENT_BLKID_mcc0__VI                = 0x0000000f,
DBG_BLOCK_ID_SMU__VI                     = 0x0000000f,
DBG_CLIENT_BLKID_uvdf_0__VI              = 0x00000010,
DBG_CLIENT_BLKID_uvdf_1__VI              = 0x00000011,
DBG_BLOCK_ID_SPIM__SI__CI                = 0x00000012,
DBG_CLIENT_BLKID_uvdf_2__VI              = 0x00000012,
DBG_BLOCK_ID_SPIM__VI                    = 0x00000012,
DBG_BLOCK_ID_GDS__SI__CI                 = 0x00000013,
DBG_CLIENT_BLKID_bci0__VI                = 0x00000013,
DBG_BLOCK_ID_GDS__VI                     = 0x00000013,
DBG_BLOCK_ID_SPIS__SI__CI                = 0x00000014,
DBG_CLIENT_BLKID_vcec0_0__VI             = 0x00000014,
DBG_BLOCK_ID_SPIS__VI                    = 0x00000014,
DBG_BLOCK_ID_UNUSED0__SI__CI             = 0x00000015,
DBG_CLIENT_BLKID_cb100__VI               = 0x00000015,
DBG_BLOCK_ID_UNUSED0__VI                 = 0x00000015,
DBG_BLOCK_ID_PA0__SI__CI                 = 0x00000016,
DBG_CLIENT_BLKID_cb001__VI               = 0x00000016,
DBG_BLOCK_ID_PA0__VI                     = 0x00000016,
DBG_BLOCK_ID_PA1__SI__CI                 = 0x00000017,
DBG_CLIENT_BLKID_cb002__VI               = 0x00000017,
DBG_BLOCK_ID_PA1__VI                     = 0x00000017,
DBG_BLOCK_ID_CP0__SI__CI                 = 0x00000018,
DBG_CLIENT_BLKID_cb003__VI               = 0x00000018,
DBG_BLOCK_ID_CP0__VI                     = 0x00000018,
DBG_BLOCK_ID_CP1__SI__CI                 = 0x00000019,
DBG_CLIENT_BLKID_mcd4_0__VI              = 0x00000019,
DBG_BLOCK_ID_CP1__VI                     = 0x00000019,
DBG_BLOCK_ID_CP2__SI__CI                 = 0x0000001a,
DBG_CLIENT_BLKID_mcd4_1__VI              = 0x0000001a,
DBG_BLOCK_ID_CP2__VI                     = 0x0000001a,
DBG_BLOCK_ID_UNUSED1__SI__CI             = 0x0000001b,
DBG_CLIENT_BLKID_tmonw00__VI             = 0x0000001b,
DBG_BLOCK_ID_UNUSED1__VI                 = 0x0000001b,
DBG_BLOCK_ID_UVDU__SI__CI                = 0x0000001c,
DBG_CLIENT_BLKID_cb101__VI               = 0x0000001c,
DBG_BLOCK_ID_UVDU__VI                    = 0x0000001c,
DBG_BLOCK_ID_UVDM__SI__CI                = 0x0000001d,
DBG_CLIENT_BLKID_cb102__VI               = 0x0000001d,
DBG_BLOCK_ID_UVDM__VI                    = 0x0000001d,
DBG_BLOCK_ID_VCE__SI__CI                 = 0x0000001e,
DBG_CLIENT_BLKID_cb103__VI               = 0x0000001e,
DBG_BLOCK_ID_VCE__VI                     = 0x0000001e,
DBG_BLOCK_ID_UNUSED2__SI__CI             = 0x0000001f,
DBG_CLIENT_BLKID_sx10__VI                = 0x0000001f,
DBG_BLOCK_ID_UNUSED2__VI                 = 0x0000001f,
DBG_BLOCK_ID_VGT0__SI__CI                = 0x00000020,
DBG_CLIENT_BLKID_cb301__VI               = 0x00000020,
DBG_BLOCK_ID_VGT0__VI                    = 0x00000020,
DBG_BLOCK_ID_VGT1__SI__CI                = 0x00000021,
DBG_CLIENT_BLKID_cb302__VI               = 0x00000021,
DBG_BLOCK_ID_VGT1__VI                    = 0x00000021,
DBG_BLOCK_ID_IA__SI__CI                  = 0x00000022,
DBG_CLIENT_BLKID_cb303__VI               = 0x00000022,
DBG_BLOCK_ID_IA__VI                      = 0x00000022,
DBG_BLOCK_ID_UNUSED3__SI__CI             = 0x00000023,
DBG_CLIENT_BLKID_tmonw01__VI             = 0x00000023,
DBG_BLOCK_ID_UNUSED3__VI                 = 0x00000023,
DBG_BLOCK_ID_SCT0__SI__CI                = 0x00000024,
DBG_CLIENT_BLKID_tmonw02__VI             = 0x00000024,
DBG_BLOCK_ID_SCT0__VI                    = 0x00000024,
DBG_BLOCK_ID_SCT1__SI__CI                = 0x00000025,
DBG_CLIENT_BLKID_vcea0_0__VI             = 0x00000025,
DBG_BLOCK_ID_SCT1__VI                    = 0x00000025,
DBG_BLOCK_ID_SPM0__SI__CI                = 0x00000026,
DBG_CLIENT_BLKID_vcea0_1__VI             = 0x00000026,
DBG_BLOCK_ID_SPM0__VI                    = 0x00000026,
DBG_BLOCK_ID_SPM1__SI__CI                = 0x00000027,
DBG_CLIENT_BLKID_vcea0_2__VI             = 0x00000027,
DBG_BLOCK_ID_SPM1__VI                    = 0x00000027,
DBG_BLOCK_ID_TCAA__SI__CI                = 0x00000028,
DBG_CLIENT_BLKID_vcea0_3__VI             = 0x00000028,
DBG_BLOCK_ID_TCAA__VI                    = 0x00000028,
DBG_BLOCK_ID_TCAB__SI__CI                = 0x00000029,
DBG_CLIENT_BLKID_scf1__VI                = 0x00000029,
DBG_BLOCK_ID_TCAB__VI                    = 0x00000029,
DBG_BLOCK_ID_TCCA__SI__CI                = 0x0000002a,
DBG_CLIENT_BLKID_sx20__VI                = 0x0000002a,
DBG_BLOCK_ID_TCCA__VI                    = 0x0000002a,
DBG_BLOCK_ID_TCCB__SI__CI                = 0x0000002b,
DBG_CLIENT_BLKID_spim1__VI               = 0x0000002b,
DBG_BLOCK_ID_TCCB__VI                    = 0x0000002b,
DBG_BLOCK_ID_MCC0__SI__CI                = 0x0000002c,
DBG_CLIENT_BLKID_scb1__VI                = 0x0000002c,
DBG_BLOCK_ID_MCC0__VI                    = 0x0000002c,
DBG_BLOCK_ID_MCC1__SI__CI                = 0x0000002d,
DBG_CLIENT_BLKID_pa10__VI                = 0x0000002d,
DBG_BLOCK_ID_MCC1__VI                    = 0x0000002d,
DBG_BLOCK_ID_MCC2__SI__CI                = 0x0000002e,
DBG_CLIENT_BLKID_pa00__VI                = 0x0000002e,
DBG_BLOCK_ID_MCC2__VI                    = 0x0000002e,
DBG_BLOCK_ID_MCC3__SI__CI                = 0x0000002f,
DBG_CLIENT_BLKID_gmcon__VI               = 0x0000002f,
DBG_BLOCK_ID_MCC3__VI                    = 0x0000002f,
DBG_BLOCK_ID_SX0__SI__CI                 = 0x00000030,
DBG_CLIENT_BLKID_mcb__VI                 = 0x00000030,
DBG_BLOCK_ID_SX0__VI                     = 0x00000030,
DBG_BLOCK_ID_SX1__SI__CI                 = 0x00000031,
DBG_CLIENT_BLKID_vgt0__VI                = 0x00000031,
DBG_BLOCK_ID_SX1__VI                     = 0x00000031,
DBG_BLOCK_ID_SX2__SI__CI                 = 0x00000032,
DBG_CLIENT_BLKID_pc0__VI                 = 0x00000032,
DBG_BLOCK_ID_SX2__VI                     = 0x00000032,
DBG_BLOCK_ID_SX3__SI__CI                 = 0x00000033,
DBG_CLIENT_BLKID_bci2__VI                = 0x00000033,
DBG_BLOCK_ID_SX3__VI                     = 0x00000033,
DBG_BLOCK_ID_UNUSED4__SI__CI             = 0x00000034,
DBG_CLIENT_BLKID_uvdb_0__VI              = 0x00000034,
DBG_BLOCK_ID_UNUSED4__VI                 = 0x00000034,
DBG_BLOCK_ID_UNUSED5__SI__CI             = 0x00000035,
DBG_CLIENT_BLKID_spim3__VI               = 0x00000035,
DBG_BLOCK_ID_UNUSED5__VI                 = 0x00000035,
DBG_BLOCK_ID_UNUSED6__SI__CI             = 0x00000036,
DBG_CLIENT_BLKID_scb3__VI                = 0x00000036,
DBG_BLOCK_ID_UNUSED6__VI                 = 0x00000036,
DBG_BLOCK_ID_UNUSED7__SI__CI             = 0x00000037,
DBG_CLIENT_BLKID_cpc_0__VI               = 0x00000037,
DBG_BLOCK_ID_UNUSED7__VI                 = 0x00000037,
DBG_BLOCK_ID_PC0__SI__CI                 = 0x00000038,
DBG_CLIENT_BLKID_cpc_1__VI               = 0x00000038,
DBG_BLOCK_ID_PC0__VI                     = 0x00000038,
DBG_BLOCK_ID_PC1__SI__CI                 = 0x00000039,
DBG_CLIENT_BLKID_uvdm_0__VI              = 0x00000039,
DBG_BLOCK_ID_PC1__VI                     = 0x00000039,
DBG_BLOCK_ID_UNUSED8__SI__CI             = 0x0000003a,
DBG_CLIENT_BLKID_uvdm_1__VI              = 0x0000003a,
DBG_BLOCK_ID_UNUSED8__VI                 = 0x0000003a,
DBG_BLOCK_ID_UNUSED9__SI__CI             = 0x0000003b,
DBG_CLIENT_BLKID_uvdm_2__VI              = 0x0000003b,
DBG_BLOCK_ID_UNUSED9__VI                 = 0x0000003b,
DBG_BLOCK_ID_UNUSED10__SI__CI            = 0x0000003c,
DBG_CLIENT_BLKID_uvdm_3__VI              = 0x0000003c,
DBG_BLOCK_ID_UNUSED10__VI                = 0x0000003c,
DBG_BLOCK_ID_UNUSED11__SI__CI            = 0x0000003d,
DBG_CLIENT_BLKID_cb000__VI               = 0x0000003d,
DBG_BLOCK_ID_UNUSED11__VI                = 0x0000003d,
DBG_BLOCK_ID_MCB__SI__CI                 = 0x0000003e,
DBG_CLIENT_BLKID_spim0__VI               = 0x0000003e,
DBG_BLOCK_ID_MCB__VI                     = 0x0000003e,
DBG_BLOCK_ID_UNUSED12__SI__CI            = 0x0000003f,
DBG_CLIENT_BLKID_scb0__VI                = 0x0000003f,
DBG_BLOCK_ID_UNUSED12__VI                = 0x0000003f,
DBG_BLOCK_ID_SCB0__SI__CI                = 0x00000040,
DBG_CLIENT_BLKID_mcc2__VI                = 0x00000040,
DBG_BLOCK_ID_SCB0__VI                    = 0x00000040,
DBG_BLOCK_ID_SCB1__SI__CI                = 0x00000041,
DBG_CLIENT_BLKID_ds0__VI                 = 0x00000041,
DBG_BLOCK_ID_SCB1__VI                    = 0x00000041,
DBG_BLOCK_ID_UNUSED13__SI__CI            = 0x00000042,
DBG_CLIENT_BLKID_srbm__VI                = 0x00000042,
DBG_BLOCK_ID_UNUSED13__VI                = 0x00000042,
DBG_BLOCK_ID_UNUSED14__SI__CI            = 0x00000043,
DBG_CLIENT_BLKID_ih__VI                  = 0x00000043,
DBG_BLOCK_ID_UNUSED14__VI                = 0x00000043,
DBG_BLOCK_ID_SCF0__SI__CI                = 0x00000044,
DBG_CLIENT_BLKID_sem__VI                 = 0x00000044,
DBG_BLOCK_ID_SCF0__VI                    = 0x00000044,
DBG_BLOCK_ID_SCF1__SI__CI                = 0x00000045,
DBG_CLIENT_BLKID_sdma_0__VI              = 0x00000045,
DBG_BLOCK_ID_SCF1__VI                    = 0x00000045,
DBG_BLOCK_ID_UNUSED15__SI__CI            = 0x00000046,
DBG_CLIENT_BLKID_sdma_1__VI              = 0x00000046,
DBG_BLOCK_ID_UNUSED15__VI                = 0x00000046,
DBG_BLOCK_ID_UNUSED16__SI__CI            = 0x00000047,
DBG_CLIENT_BLKID_hdp__VI                 = 0x00000047,
DBG_BLOCK_ID_UNUSED16__VI                = 0x00000047,
DBG_BLOCK_ID_BCI0__SI__CI                = 0x00000048,
DBG_CLIENT_BLKID_acp_0__VI               = 0x00000048,
DBG_BLOCK_ID_BCI0__VI                    = 0x00000048,
DBG_BLOCK_ID_BCI1__SI__CI                = 0x00000049,
DBG_CLIENT_BLKID_acp_1__VI               = 0x00000049,
DBG_BLOCK_ID_BCI1__VI                    = 0x00000049,
DBG_BLOCK_ID_BCI2__SI__CI                = 0x0000004a,
DBG_CLIENT_BLKID_cb200__VI               = 0x0000004a,
DBG_BLOCK_ID_BCI2__VI                    = 0x0000004a,
DBG_BLOCK_ID_BCI3__SI__CI                = 0x0000004b,
DBG_CLIENT_BLKID_scf3__VI                = 0x0000004b,
DBG_BLOCK_ID_BCI3__VI                    = 0x0000004b,
DBG_BLOCK_ID_UNUSED17__SI__CI            = 0x0000004c,
DBG_CLIENT_BLKID_bci3__VI                = 0x0000004c,
DBG_BLOCK_ID_UNUSED17__VI                = 0x0000004c,
DBG_BLOCK_ID_UNUSED18__SI__CI            = 0x0000004d,
DBG_CLIENT_BLKID_mcd0_0__VI              = 0x0000004d,
DBG_BLOCK_ID_UNUSED18__VI                = 0x0000004d,
DBG_BLOCK_ID_UNUSED19__SI__CI            = 0x0000004e,
DBG_CLIENT_BLKID_mcd0_1__VI              = 0x0000004e,
DBG_BLOCK_ID_UNUSED19__VI                = 0x0000004e,
DBG_BLOCK_ID_UNUSED20__SI__CI            = 0x0000004f,
DBG_CLIENT_BLKID_pa11__VI                = 0x0000004f,
DBG_BLOCK_ID_UNUSED20__VI                = 0x0000004f,
DBG_BLOCK_ID_CB00__SI__CI                = 0x00000050,
DBG_CLIENT_BLKID_pa01__VI                = 0x00000050,
DBG_BLOCK_ID_CB00__VI                    = 0x00000050,
DBG_BLOCK_ID_CB01__SI__CI                = 0x00000051,
DBG_CLIENT_BLKID_cb201__VI               = 0x00000051,
DBG_BLOCK_ID_CB01__VI                    = 0x00000051,
DBG_BLOCK_ID_CB02__SI__CI                = 0x00000052,
DBG_CLIENT_BLKID_cb202__VI               = 0x00000052,
DBG_BLOCK_ID_CB02__VI                    = 0x00000052,
DBG_BLOCK_ID_CB03__SI__CI                = 0x00000053,
DBG_CLIENT_BLKID_cb203__VI               = 0x00000053,
DBG_BLOCK_ID_CB03__VI                    = 0x00000053,
DBG_BLOCK_ID_CB04__SI__CI                = 0x00000054,
DBG_CLIENT_BLKID_spim2__VI               = 0x00000054,
DBG_BLOCK_ID_CB04__VI                    = 0x00000054,
DBG_BLOCK_ID_UNUSED21__SI__CI            = 0x00000055,
DBG_CLIENT_BLKID_scb2__VI                = 0x00000055,
DBG_BLOCK_ID_UNUSED21__VI                = 0x00000055,
DBG_BLOCK_ID_UNUSED22__SI__CI            = 0x00000056,
DBG_CLIENT_BLKID_vgt2__VI                = 0x00000056,
DBG_BLOCK_ID_UNUSED22__VI                = 0x00000056,
DBG_BLOCK_ID_UNUSED23__SI__CI            = 0x00000057,
DBG_CLIENT_BLKID_pc2__VI                 = 0x00000057,
DBG_BLOCK_ID_UNUSED23__VI                = 0x00000057,
DBG_BLOCK_ID_CB10__SI__CI                = 0x00000058,
DBG_CLIENT_BLKID_smu_0__VI               = 0x00000058,
DBG_BLOCK_ID_CB10__VI                    = 0x00000058,
DBG_BLOCK_ID_CB11__SI__CI                = 0x00000059,
DBG_CLIENT_BLKID_smu_1__VI               = 0x00000059,
DBG_BLOCK_ID_CB11__VI                    = 0x00000059,
DBG_BLOCK_ID_CB12__SI__CI                = 0x0000005a,
DBG_CLIENT_BLKID_smu_2__VI               = 0x0000005a,
DBG_BLOCK_ID_CB12__VI                    = 0x0000005a,
DBG_BLOCK_ID_CB13__SI__CI                = 0x0000005b,
DBG_CLIENT_BLKID_cb1__VI                 = 0x0000005b,
DBG_BLOCK_ID_CB13__VI                    = 0x0000005b,
DBG_BLOCK_ID_CB14__SI__CI                = 0x0000005c,
DBG_CLIENT_BLKID_ia0__VI                 = 0x0000005c,
DBG_BLOCK_ID_CB14__VI                    = 0x0000005c,
DBG_BLOCK_ID_UNUSED24__SI__CI            = 0x0000005d,
DBG_CLIENT_BLKID_wd__VI                  = 0x0000005d,
DBG_BLOCK_ID_UNUSED24__VI                = 0x0000005d,
DBG_BLOCK_ID_UNUSED25__SI__CI            = 0x0000005e,
DBG_CLIENT_BLKID_ia1__VI                 = 0x0000005e,
DBG_BLOCK_ID_UNUSED25__VI                = 0x0000005e,
DBG_BLOCK_ID_UNUSED26__SI__CI            = 0x0000005f,
DBG_CLIENT_BLKID_scf0__VI                = 0x0000005f,
DBG_BLOCK_ID_UNUSED26__VI                = 0x0000005f,
DBG_BLOCK_ID_TCP0__SI__CI                = 0x00000060,
DBG_CLIENT_BLKID_vgt1__VI                = 0x00000060,
DBG_BLOCK_ID_TCP0__VI                    = 0x00000060,
DBG_BLOCK_ID_TCP1__SI__CI                = 0x00000061,
DBG_CLIENT_BLKID_pc1__VI                 = 0x00000061,
DBG_BLOCK_ID_TCP1__VI                    = 0x00000061,
DBG_BLOCK_ID_TCP2__SI__CI                = 0x00000062,
DBG_CLIENT_BLKID_cb0__VI                 = 0x00000062,
DBG_BLOCK_ID_TCP2__VI                    = 0x00000062,
DBG_BLOCK_ID_TCP3__SI__CI                = 0x00000063,
DBG_CLIENT_BLKID_gdc_one_0__VI           = 0x00000063,
DBG_BLOCK_ID_TCP3__VI                    = 0x00000063,
DBG_BLOCK_ID_TCP4__SI__CI                = 0x00000064,
DBG_CLIENT_BLKID_gdc_one_1__VI           = 0x00000064,
DBG_BLOCK_ID_TCP4__VI                    = 0x00000064,
DBG_BLOCK_ID_TCP5__SI__CI                = 0x00000065,
DBG_CLIENT_BLKID_gdc_one_2__VI           = 0x00000065,
DBG_BLOCK_ID_TCP5__VI                    = 0x00000065,
DBG_BLOCK_ID_TCP6__SI__CI                = 0x00000066,
DBG_CLIENT_BLKID_gdc_one_3__VI           = 0x00000066,
DBG_BLOCK_ID_TCP6__VI                    = 0x00000066,
DBG_BLOCK_ID_TCP7__SI__CI                = 0x00000067,
DBG_CLIENT_BLKID_gdc_one_4__VI           = 0x00000067,
DBG_BLOCK_ID_TCP7__VI                    = 0x00000067,
DBG_BLOCK_ID_TCP8__SI__CI                = 0x00000068,
DBG_CLIENT_BLKID_gdc_one_5__VI           = 0x00000068,
DBG_BLOCK_ID_TCP8__VI                    = 0x00000068,
DBG_BLOCK_ID_TCP9__SI__CI                = 0x00000069,
DBG_CLIENT_BLKID_gdc_one_6__VI           = 0x00000069,
DBG_BLOCK_ID_TCP9__VI                    = 0x00000069,
DBG_BLOCK_ID_TCP10__SI__CI               = 0x0000006a,
DBG_CLIENT_BLKID_gdc_one_7__VI           = 0x0000006a,
DBG_BLOCK_ID_TCP10__VI                   = 0x0000006a,
DBG_BLOCK_ID_TCP11__SI__CI               = 0x0000006b,
DBG_CLIENT_BLKID_gdc_one_8__VI           = 0x0000006b,
DBG_BLOCK_ID_TCP11__VI                   = 0x0000006b,
DBG_BLOCK_ID_TCP12__SI__CI               = 0x0000006c,
DBG_CLIENT_BLKID_gdc_one_9__VI           = 0x0000006c,
DBG_BLOCK_ID_TCP12__VI                   = 0x0000006c,
DBG_BLOCK_ID_TCP13__SI__CI               = 0x0000006d,
DBG_CLIENT_BLKID_gdc_one_10__VI          = 0x0000006d,
DBG_BLOCK_ID_TCP13__VI                   = 0x0000006d,
DBG_BLOCK_ID_TCP14__SI__CI               = 0x0000006e,
DBG_CLIENT_BLKID_gdc_one_11__VI          = 0x0000006e,
DBG_BLOCK_ID_TCP14__VI                   = 0x0000006e,
DBG_BLOCK_ID_TCP15__SI__CI               = 0x0000006f,
DBG_CLIENT_BLKID_gdc_one_12__VI          = 0x0000006f,
DBG_BLOCK_ID_TCP15__VI                   = 0x0000006f,
DBG_BLOCK_ID_TCP16__SI__CI               = 0x00000070,
DBG_CLIENT_BLKID_gdc_one_13__VI          = 0x00000070,
DBG_BLOCK_ID_TCP16__VI                   = 0x00000070,
DBG_BLOCK_ID_TCP17__SI__CI               = 0x00000071,
DBG_CLIENT_BLKID_gdc_one_14__VI          = 0x00000071,
DBG_BLOCK_ID_TCP17__VI                   = 0x00000071,
DBG_BLOCK_ID_TCP18__SI__CI               = 0x00000072,
DBG_CLIENT_BLKID_gdc_one_15__VI          = 0x00000072,
DBG_BLOCK_ID_TCP18__VI                   = 0x00000072,
DBG_BLOCK_ID_TCP19__SI__CI               = 0x00000073,
DBG_CLIENT_BLKID_gdc_one_16__VI          = 0x00000073,
DBG_BLOCK_ID_TCP19__VI                   = 0x00000073,
DBG_BLOCK_ID_TCP20__SI__CI               = 0x00000074,
DBG_CLIENT_BLKID_gdc_one_17__VI          = 0x00000074,
DBG_BLOCK_ID_TCP20__VI                   = 0x00000074,
DBG_BLOCK_ID_TCP21__SI__CI               = 0x00000075,
DBG_CLIENT_BLKID_gdc_one_18__VI          = 0x00000075,
DBG_BLOCK_ID_TCP21__VI                   = 0x00000075,
DBG_BLOCK_ID_TCP22__SI__CI               = 0x00000076,
DBG_CLIENT_BLKID_gdc_one_19__VI          = 0x00000076,
DBG_BLOCK_ID_TCP22__VI                   = 0x00000076,
DBG_BLOCK_ID_TCP23__SI__CI               = 0x00000077,
DBG_CLIENT_BLKID_gdc_one_20__VI          = 0x00000077,
DBG_BLOCK_ID_TCP23__VI                   = 0x00000077,
DBG_BLOCK_ID_TCP_RESERVED0__SI__CI       = 0x00000078,
DBG_CLIENT_BLKID_gdc_one_21__VI          = 0x00000078,
DBG_BLOCK_ID_TCP_RESERVED0__VI           = 0x00000078,
DBG_BLOCK_ID_TCP_RESERVED1__SI__CI       = 0x00000079,
DBG_CLIENT_BLKID_gdc_one_22__VI          = 0x00000079,
DBG_BLOCK_ID_TCP_RESERVED1__VI           = 0x00000079,
DBG_BLOCK_ID_TCP_RESERVED2__SI__CI       = 0x0000007a,
DBG_CLIENT_BLKID_gdc_one_23__VI          = 0x0000007a,
DBG_BLOCK_ID_TCP_RESERVED2__VI           = 0x0000007a,
DBG_BLOCK_ID_TCP_RESERVED3__SI__CI       = 0x0000007b,
DBG_CLIENT_BLKID_gdc_one_24__VI          = 0x0000007b,
DBG_BLOCK_ID_TCP_RESERVED3__VI           = 0x0000007b,
DBG_BLOCK_ID_TCP_RESERVED4__SI__CI       = 0x0000007c,
DBG_CLIENT_BLKID_gdc_one_25__VI          = 0x0000007c,
DBG_BLOCK_ID_TCP_RESERVED4__VI           = 0x0000007c,
DBG_BLOCK_ID_TCP_RESERVED5__SI__CI       = 0x0000007d,
DBG_CLIENT_BLKID_gdc_one_26__VI          = 0x0000007d,
DBG_BLOCK_ID_TCP_RESERVED5__VI           = 0x0000007d,
DBG_BLOCK_ID_TCP_RESERVED6__SI__CI       = 0x0000007e,
DBG_CLIENT_BLKID_gdc_one_27__VI          = 0x0000007e,
DBG_BLOCK_ID_TCP_RESERVED6__VI           = 0x0000007e,
DBG_BLOCK_ID_TCP_RESERVED7__SI__CI       = 0x0000007f,
DBG_CLIENT_BLKID_gdc_one_28__VI          = 0x0000007f,
DBG_BLOCK_ID_TCP_RESERVED7__VI           = 0x0000007f,
DBG_BLOCK_ID_DB00__SI__CI                = 0x00000080,
DBG_CLIENT_BLKID_gdc_one_29__VI          = 0x00000080,
DBG_BLOCK_ID_DB00__VI                    = 0x00000080,
DBG_BLOCK_ID_DB01__SI__CI                = 0x00000081,
DBG_CLIENT_BLKID_gdc_one_30__VI          = 0x00000081,
DBG_BLOCK_ID_DB01__VI                    = 0x00000081,
DBG_BLOCK_ID_DB02__SI__CI                = 0x00000082,
DBG_CLIENT_BLKID_gdc_one_31__VI          = 0x00000082,
DBG_BLOCK_ID_DB02__VI                    = 0x00000082,
DBG_BLOCK_ID_DB03__SI__CI                = 0x00000083,
DBG_CLIENT_BLKID_gdc_one_32__VI          = 0x00000083,
DBG_BLOCK_ID_DB03__VI                    = 0x00000083,
DBG_BLOCK_ID_DB04__SI__CI                = 0x00000084,
DBG_CLIENT_BLKID_gdc_one_33__VI          = 0x00000084,
DBG_BLOCK_ID_DB04__VI                    = 0x00000084,
DBG_BLOCK_ID_UNUSED27__SI__CI            = 0x00000085,
DBG_CLIENT_BLKID_gdc_one_34__VI          = 0x00000085,
DBG_BLOCK_ID_UNUSED27__VI                = 0x00000085,
DBG_BLOCK_ID_UNUSED28__SI__CI            = 0x00000086,
DBG_CLIENT_BLKID_gdc_one_35__VI          = 0x00000086,
DBG_BLOCK_ID_UNUSED28__VI                = 0x00000086,
DBG_BLOCK_ID_UNUSED29__SI__CI            = 0x00000087,
DBG_CLIENT_BLKID_vceb0_0__VI             = 0x00000087,
DBG_BLOCK_ID_UNUSED29__VI                = 0x00000087,
DBG_BLOCK_ID_DB10__SI__CI                = 0x00000088,
DBG_CLIENT_BLKID_vgt3__VI                = 0x00000088,
DBG_BLOCK_ID_DB10__VI                    = 0x00000088,
DBG_BLOCK_ID_DB11__SI__CI                = 0x00000089,
DBG_CLIENT_BLKID_pc3__VI                 = 0x00000089,
DBG_BLOCK_ID_DB11__VI                    = 0x00000089,
DBG_BLOCK_ID_DB12__SI__CI                = 0x0000008a,
DBG_CLIENT_BLKID_mcd3_0__VI              = 0x0000008a,
DBG_BLOCK_ID_DB12__VI                    = 0x0000008a,
DBG_BLOCK_ID_DB13__SI__CI                = 0x0000008b,
DBG_CLIENT_BLKID_mcd3_1__VI              = 0x0000008b,
DBG_BLOCK_ID_DB13__VI                    = 0x0000008b,
DBG_BLOCK_ID_DB14__SI__CI                = 0x0000008c,
DBG_CLIENT_BLKID_uvdu_0__VI              = 0x0000008c,
DBG_BLOCK_ID_DB14__VI                    = 0x0000008c,
DBG_BLOCK_ID_UNUSED30__SI__CI            = 0x0000008d,
DBG_CLIENT_BLKID_uvdu_1__VI              = 0x0000008d,
DBG_BLOCK_ID_UNUSED30__VI                = 0x0000008d,
DBG_BLOCK_ID_UNUSED31__SI__CI            = 0x0000008e,
DBG_CLIENT_BLKID_uvdu_2__VI              = 0x0000008e,
DBG_BLOCK_ID_UNUSED31__VI                = 0x0000008e,
DBG_BLOCK_ID_UNUSED32__SI__CI            = 0x0000008f,
DBG_CLIENT_BLKID_uvdu_3__VI              = 0x0000008f,
DBG_BLOCK_ID_UNUSED32__VI                = 0x0000008f,
DBG_BLOCK_ID_TCC0__SI__CI                = 0x00000090,
DBG_CLIENT_BLKID_uvdu_4__VI              = 0x00000090,
DBG_BLOCK_ID_TCC0__VI                    = 0x00000090,
DBG_BLOCK_ID_TCC1__SI__CI                = 0x00000091,
DBG_CLIENT_BLKID_uvdu_5__VI              = 0x00000091,
DBG_BLOCK_ID_TCC1__VI                    = 0x00000091,
DBG_BLOCK_ID_TCC2__SI__CI                = 0x00000092,
DBG_CLIENT_BLKID_uvdu_6__VI              = 0x00000092,
DBG_BLOCK_ID_TCC2__VI                    = 0x00000092,
DBG_BLOCK_ID_TCC3__SI__CI                = 0x00000093,
DBG_CLIENT_BLKID_cb300__VI               = 0x00000093,
DBG_BLOCK_ID_TCC3__VI                    = 0x00000093,
DBG_BLOCK_ID_TCC4__SI__CI                = 0x00000094,
DBG_CLIENT_BLKID_mcd1_0__VI              = 0x00000094,
DBG_BLOCK_ID_TCC4__VI                    = 0x00000094,
DBG_BLOCK_ID_TCC5__SI__CI                = 0x00000095,
DBG_CLIENT_BLKID_mcd1_1__VI              = 0x00000095,
DBG_BLOCK_ID_TCC5__VI                    = 0x00000095,
DBG_BLOCK_ID_TCC6__SI__CI                = 0x00000096,
DBG_CLIENT_BLKID_sx00__VI                = 0x00000096,
DBG_BLOCK_ID_TCC6__VI                    = 0x00000096,
DBG_BLOCK_ID_TCC7__SI__CI                = 0x00000097,
DBG_CLIENT_BLKID_uvdc_0__VI              = 0x00000097,
DBG_BLOCK_ID_TCC7__VI                    = 0x00000097,
DBG_BLOCK_ID_SPS00__SI__CI               = 0x00000098,
DBG_CLIENT_BLKID_uvdc_1__VI              = 0x00000098,
DBG_BLOCK_ID_SPS00__VI                   = 0x00000098,
DBG_BLOCK_ID_SPS01__SI__CI               = 0x00000099,
DBG_CLIENT_BLKID_mcc3__VI                = 0x00000099,
DBG_BLOCK_ID_SPS01__VI                   = 0x00000099,
DBG_BLOCK_ID_SPS02__SI__CI               = 0x0000009a,
DBG_CLIENT_BLKID_mcc4__VI                = 0x0000009a,
DBG_BLOCK_ID_SPS02__VI                   = 0x0000009a,
DBG_BLOCK_ID_SPS10__SI__CI               = 0x0000009b,
DBG_CLIENT_BLKID_mcc5__VI                = 0x0000009b,
DBG_BLOCK_ID_SPS10__VI                   = 0x0000009b,
DBG_BLOCK_ID_SPS11__SI__CI               = 0x0000009c,
DBG_CLIENT_BLKID_mcc6__VI                = 0x0000009c,
DBG_BLOCK_ID_SPS11__VI                   = 0x0000009c,
DBG_BLOCK_ID_SPS12__SI__CI               = 0x0000009d,
DBG_CLIENT_BLKID_mcc7__VI                = 0x0000009d,
DBG_BLOCK_ID_SPS12__VI                   = 0x0000009d,
DBG_BLOCK_ID_UNUSED33__SI__CI            = 0x0000009e,
DBG_CLIENT_BLKID_cpg_0__VI               = 0x0000009e,
DBG_BLOCK_ID_UNUSED33__VI                = 0x0000009e,
DBG_BLOCK_ID_UNUSED34__SI__CI            = 0x0000009f,
DBG_CLIENT_BLKID_cpg_1__VI               = 0x0000009f,
DBG_BLOCK_ID_UNUSED34__VI                = 0x0000009f,
DBG_BLOCK_ID_TA00__SI__CI                = 0x000000a0,
DBG_CLIENT_BLKID_gck__VI                 = 0x000000a0,
DBG_BLOCK_ID_TA00__VI                    = 0x000000a0,
DBG_BLOCK_ID_TA01__SI__CI                = 0x000000a1,
DBG_CLIENT_BLKID_mcc1__VI                = 0x000000a1,
DBG_BLOCK_ID_TA01__VI                    = 0x000000a1,
DBG_BLOCK_ID_TA02__SI__CI                = 0x000000a2,
DBG_CLIENT_BLKID_cpf_0__VI               = 0x000000a2,
DBG_BLOCK_ID_TA02__VI                    = 0x000000a2,
DBG_BLOCK_ID_TA03__SI__CI                = 0x000000a3,
DBG_CLIENT_BLKID_cpf_1__VI               = 0x000000a3,
DBG_BLOCK_ID_TA03__VI                    = 0x000000a3,
DBG_BLOCK_ID_TA04__SI__CI                = 0x000000a4,
DBG_CLIENT_BLKID_rlc__VI                 = 0x000000a4,
DBG_BLOCK_ID_TA04__VI                    = 0x000000a4,
DBG_BLOCK_ID_TA05__SI__CI                = 0x000000a5,
DBG_CLIENT_BLKID_grbm__VI                = 0x000000a5,
DBG_BLOCK_ID_TA05__VI                    = 0x000000a5,
DBG_BLOCK_ID_TA06__SI__CI                = 0x000000a6,
DBG_CLIENT_BLKID_sammsp__VI              = 0x000000a6,
DBG_BLOCK_ID_TA06__VI                    = 0x000000a6,
DBG_BLOCK_ID_TA07__SI__CI                = 0x000000a7,
DBG_CLIENT_BLKID_dci_pg__VI              = 0x000000a7,
DBG_BLOCK_ID_TA07__VI                    = 0x000000a7,
DBG_BLOCK_ID_TA08__SI__CI                = 0x000000a8,
DBG_CLIENT_BLKID_dci_0__VI               = 0x000000a8,
DBG_BLOCK_ID_TA08__VI                    = 0x000000a8,
DBG_BLOCK_ID_TA09__SI__CI                = 0x000000a9,
DBG_CLIENT_BLKID_dccg0_0__VI             = 0x000000a9,
DBG_BLOCK_ID_TA09__VI                    = 0x000000a9,
DBG_BLOCK_ID_TA0A__SI__CI                = 0x000000aa,
DBG_CLIENT_BLKID_dccg0_1__VI             = 0x000000aa,
DBG_BLOCK_ID_TA0A__VI                    = 0x000000aa,
DBG_BLOCK_ID_TA0B__SI__CI                = 0x000000ab,
DBG_CLIENT_BLKID_dcfe01_0__VI            = 0x000000ab,
DBG_BLOCK_ID_TA0B__VI                    = 0x000000ab,
DBG_BLOCK_ID_UNUSED35__SI__CI            = 0x000000ac,
DBG_CLIENT_BLKID_dcfe02_0__VI            = 0x000000ac,
DBG_BLOCK_ID_UNUSED35__VI                = 0x000000ac,
DBG_BLOCK_ID_UNUSED36__SI__CI            = 0x000000ad,
DBG_CLIENT_BLKID_dcfe03_0__VI            = 0x000000ad,
DBG_BLOCK_ID_UNUSED36__VI                = 0x000000ad,
DBG_BLOCK_ID_UNUSED37__SI__CI            = 0x000000ae,
DBG_CLIENT_BLKID_dcfe04_0__VI            = 0x000000ae,
DBG_BLOCK_ID_UNUSED37__VI                = 0x000000ae,
DBG_BLOCK_ID_UNUSED38__SI__CI            = 0x000000af,
DBG_CLIENT_BLKID_dcfe05_0__VI            = 0x000000af,
DBG_BLOCK_ID_UNUSED38__VI                = 0x000000af,
DBG_BLOCK_ID_TA10__SI__CI                = 0x000000b0,
DBG_CLIENT_BLKID_dcfe06_0__VI            = 0x000000b0,
DBG_BLOCK_ID_TA10__VI                    = 0x000000b0,
DBG_BLOCK_ID_TA11__SI__CI                = 0x000000b1,
DBG_CLIENT_BLKID_mcq0_0__VI              = 0x000000b1,
DBG_BLOCK_ID_TA11__VI                    = 0x000000b1,
DBG_BLOCK_ID_TA12__SI__CI                = 0x000000b2,
DBG_CLIENT_BLKID_mcq0_1__VI              = 0x000000b2,
DBG_BLOCK_ID_TA12__VI                    = 0x000000b2,
DBG_BLOCK_ID_TA13__SI__CI                = 0x000000b3,
DBG_CLIENT_BLKID_mcq1_0__VI              = 0x000000b3,
DBG_BLOCK_ID_TA13__VI                    = 0x000000b3,
DBG_BLOCK_ID_TA14__SI__CI                = 0x000000b4,
DBG_CLIENT_BLKID_mcq1_1__VI              = 0x000000b4,
DBG_BLOCK_ID_TA14__VI                    = 0x000000b4,
DBG_BLOCK_ID_TA15__SI__CI                = 0x000000b5,
DBG_CLIENT_BLKID_mcq2_0__VI              = 0x000000b5,
DBG_BLOCK_ID_TA15__VI                    = 0x000000b5,
DBG_BLOCK_ID_TA16__SI__CI                = 0x000000b6,
DBG_CLIENT_BLKID_mcq2_1__VI              = 0x000000b6,
DBG_BLOCK_ID_TA16__VI                    = 0x000000b6,
DBG_BLOCK_ID_TA17__SI__CI                = 0x000000b7,
DBG_CLIENT_BLKID_mcq3_0__VI              = 0x000000b7,
DBG_BLOCK_ID_TA17__VI                    = 0x000000b7,
DBG_BLOCK_ID_TA18__SI__CI                = 0x000000b8,
DBG_CLIENT_BLKID_mcq3_1__VI              = 0x000000b8,
DBG_BLOCK_ID_TA18__VI                    = 0x000000b8,
DBG_BLOCK_ID_TA19__SI__CI                = 0x000000b9,
DBG_CLIENT_BLKID_mcq4_0__VI              = 0x000000b9,
DBG_BLOCK_ID_TA19__VI                    = 0x000000b9,
DBG_BLOCK_ID_TA1A__SI__CI                = 0x000000ba,
DBG_CLIENT_BLKID_mcq4_1__VI              = 0x000000ba,
DBG_BLOCK_ID_TA1A__VI                    = 0x000000ba,
DBG_BLOCK_ID_TA1B__SI__CI                = 0x000000bb,
DBG_CLIENT_BLKID_mcq5_0__VI              = 0x000000bb,
DBG_BLOCK_ID_TA1B__VI                    = 0x000000bb,
DBG_BLOCK_ID_UNUSED39__SI__CI            = 0x000000bc,
DBG_CLIENT_BLKID_mcq5_1__VI              = 0x000000bc,
DBG_BLOCK_ID_UNUSED39__VI                = 0x000000bc,
DBG_BLOCK_ID_UNUSED40__SI__CI            = 0x000000bd,
DBG_CLIENT_BLKID_mcq6_0__VI              = 0x000000bd,
DBG_BLOCK_ID_UNUSED40__VI                = 0x000000bd,
DBG_BLOCK_ID_UNUSED41__SI__CI            = 0x000000be,
DBG_CLIENT_BLKID_mcq6_1__VI              = 0x000000be,
DBG_BLOCK_ID_UNUSED41__VI                = 0x000000be,
DBG_BLOCK_ID_UNUSED42__SI__CI            = 0x000000bf,
DBG_CLIENT_BLKID_mcq7_0__VI              = 0x000000bf,
DBG_BLOCK_ID_UNUSED42__VI                = 0x000000bf,
DBG_BLOCK_ID_TD00__SI__CI                = 0x000000c0,
DBG_CLIENT_BLKID_mcq7_1__VI              = 0x000000c0,
DBG_BLOCK_ID_TD00__VI                    = 0x000000c0,
DBG_BLOCK_ID_TD01__SI__CI                = 0x000000c1,
DBG_CLIENT_BLKID_uvdi_0__VI              = 0x000000c1,
DBG_BLOCK_ID_TD01__VI                    = 0x000000c1,
DBG_BLOCK_ID_TD02__SI__CI                = 0x000000c2,
DBG_CLIENT_BLKID_RESERVED_LAST__VI       = 0x000000c2,
DBG_BLOCK_ID_TD02__VI                    = 0x000000c2,
DBG_BLOCK_ID_TD03                        = 0x000000c3,
DBG_BLOCK_ID_TD04                        = 0x000000c4,
DBG_BLOCK_ID_TD05                        = 0x000000c5,
DBG_BLOCK_ID_TD06                        = 0x000000c6,
DBG_BLOCK_ID_TD07                        = 0x000000c7,
DBG_BLOCK_ID_TD08                        = 0x000000c8,
DBG_BLOCK_ID_TD09                        = 0x000000c9,
DBG_BLOCK_ID_TD0A                        = 0x000000ca,
DBG_BLOCK_ID_TD0B                        = 0x000000cb,
DBG_BLOCK_ID_UNUSED43                    = 0x000000cc,
DBG_BLOCK_ID_UNUSED44                    = 0x000000cd,
DBG_BLOCK_ID_UNUSED45                    = 0x000000ce,
DBG_BLOCK_ID_UNUSED46                    = 0x000000cf,
DBG_BLOCK_ID_TD10                        = 0x000000d0,
DBG_BLOCK_ID_TD11                        = 0x000000d1,
DBG_BLOCK_ID_TD12                        = 0x000000d2,
DBG_BLOCK_ID_TD13                        = 0x000000d3,
DBG_BLOCK_ID_TD14                        = 0x000000d4,
DBG_BLOCK_ID_TD15                        = 0x000000d5,
DBG_BLOCK_ID_TD16                        = 0x000000d6,
DBG_BLOCK_ID_TD17                        = 0x000000d7,
DBG_BLOCK_ID_TD18                        = 0x000000d8,
DBG_BLOCK_ID_TD19                        = 0x000000d9,
DBG_BLOCK_ID_TD1A                        = 0x000000da,
DBG_BLOCK_ID_TD1B                        = 0x000000db,
DBG_BLOCK_ID_UNUSED47                    = 0x000000dc,
DBG_BLOCK_ID_UNUSED48                    = 0x000000dd,
DBG_BLOCK_ID_UNUSED49                    = 0x000000de,
DBG_BLOCK_ID_UNUSED50                    = 0x000000df,
DBG_BLOCK_ID_MCD0                        = 0x000000e0,
DBG_BLOCK_ID_MCD1                        = 0x000000e1,
DBG_BLOCK_ID_MCD2                        = 0x000000e2,
DBG_BLOCK_ID_MCD3                        = 0x000000e3,
DBG_BLOCK_ID_MCD4                        = 0x000000e4,
DBG_BLOCK_ID_MCD5                        = 0x000000e5,
DBG_BLOCK_ID_UNUSED51                    = 0x000000e6,
DBG_BLOCK_ID_UNUSED52                    = 0x000000e7,
} DebugBlockId;

typedef enum DebugBlockId_BY16 {
DBG_BLOCK_ID_RESERVED_BY16               = 0x00000000,
DBG_BLOCK_ID_VGT0_BY16                   = 0x00000002,
DBG_BLOCK_ID_SX0_BY16                    = 0x00000003,
DBG_BLOCK_ID_SCB0_BY16                   = 0x00000004,
DBG_BLOCK_ID_CB00_BY16                   = 0x00000005,
DBG_BLOCK_ID_TCP0_BY16                   = 0x00000006,
DBG_BLOCK_ID_TCP16_BY16                  = 0x00000007,
DBG_BLOCK_ID_DB00_BY16                   = 0x00000008,
DBG_BLOCK_ID_TCC0_BY16                   = 0x00000009,
DBG_BLOCK_ID_TA00_BY16                   = 0x0000000a,
DBG_BLOCK_ID_TA10_BY16                   = 0x0000000b,
DBG_BLOCK_ID_TD00_BY16                   = 0x0000000c,
DBG_BLOCK_ID_TD10_BY16                   = 0x0000000d,
DBG_BLOCK_ID_MCD0_BY16                   = 0x0000000e,
} DebugBlockId_BY16;

typedef enum DebugBlockId_BY2 {
DBG_BLOCK_ID_RESERVED_BY2                = 0x00000000,
DBG_BLOCK_ID_VMC_BY2                     = 0x00000001,
DBG_BLOCK_ID_CG_BY2                      = 0x00000002,
DBG_BLOCK_ID_GRBM_BY2                    = 0x00000003,
DBG_BLOCK_ID_CSC_BY2                     = 0x00000004,
DBG_BLOCK_ID_IH_BY2                      = 0x00000005,
DBG_BLOCK_ID_SQ_BY2                      = 0x00000006,
DBG_BLOCK_ID_GMCON_BY2                   = 0x00000007,
DBG_BLOCK_ID_SPIM_BY2                    = 0x00000009,
DBG_BLOCK_ID_SPIS_BY2                    = 0x0000000a,
DBG_BLOCK_ID_PA0_BY2                     = 0x0000000b,
DBG_BLOCK_ID_CP0_BY2                     = 0x0000000c,
DBG_BLOCK_ID_CP2_BY2                     = 0x0000000d,
DBG_BLOCK_ID_UVDU_BY2                    = 0x0000000e,
DBG_BLOCK_ID_VCE_BY2                     = 0x0000000f,
DBG_BLOCK_ID_VGT0_BY2                    = 0x00000010,
DBG_BLOCK_ID_IA_BY2                      = 0x00000011,
DBG_BLOCK_ID_SCT0_BY2                    = 0x00000012,
DBG_BLOCK_ID_SPM0_BY2                    = 0x00000013,
DBG_BLOCK_ID_TCAA_BY2                    = 0x00000014,
DBG_BLOCK_ID_TCCA_BY2                    = 0x00000015,
DBG_BLOCK_ID_MCC0_BY2                    = 0x00000016,
DBG_BLOCK_ID_MCC2_BY2                    = 0x00000017,
DBG_BLOCK_ID_SX0_BY2                     = 0x00000018,
DBG_BLOCK_ID_SX2_BY2                     = 0x00000019,
DBG_BLOCK_ID_UNUSED4_BY2                 = 0x0000001a,
DBG_BLOCK_ID_UNUSED6_BY2                 = 0x0000001b,
DBG_BLOCK_ID_PC0_BY2                     = 0x0000001c,
DBG_BLOCK_ID_UNUSED8_BY2                 = 0x0000001d,
DBG_BLOCK_ID_UNUSED10_BY2                = 0x0000001e,
DBG_BLOCK_ID_MCB_BY2                     = 0x0000001f,
DBG_BLOCK_ID_SCB0_BY2                    = 0x00000020,
DBG_BLOCK_ID_UNUSED13_BY2                = 0x00000021,
DBG_BLOCK_ID_SCF0_BY2                    = 0x00000022,
DBG_BLOCK_ID_UNUSED15_BY2                = 0x00000023,
DBG_BLOCK_ID_BCI0_BY2                    = 0x00000024,
DBG_BLOCK_ID_BCI2_BY2                    = 0x00000025,
DBG_BLOCK_ID_UNUSED17_BY2                = 0x00000026,
DBG_BLOCK_ID_UNUSED19_BY2                = 0x00000027,
DBG_BLOCK_ID_CB00_BY2                    = 0x00000028,
DBG_BLOCK_ID_CB02_BY2                    = 0x00000029,
DBG_BLOCK_ID_CB04_BY2                    = 0x0000002a,
DBG_BLOCK_ID_UNUSED22_BY2                = 0x0000002b,
DBG_BLOCK_ID_CB10_BY2                    = 0x0000002c,
DBG_BLOCK_ID_CB12_BY2                    = 0x0000002d,
DBG_BLOCK_ID_CB14_BY2                    = 0x0000002e,
DBG_BLOCK_ID_UNUSED25_BY2                = 0x0000002f,
DBG_BLOCK_ID_TCP0_BY2                    = 0x00000030,
DBG_BLOCK_ID_TCP2_BY2                    = 0x00000031,
DBG_BLOCK_ID_TCP4_BY2                    = 0x00000032,
DBG_BLOCK_ID_TCP6_BY2                    = 0x00000033,
DBG_BLOCK_ID_TCP8_BY2                    = 0x00000034,
DBG_BLOCK_ID_TCP10_BY2                   = 0x00000035,
DBG_BLOCK_ID_TCP12_BY2                   = 0x00000036,
DBG_BLOCK_ID_TCP14_BY2                   = 0x00000037,
DBG_BLOCK_ID_TCP16_BY2                   = 0x00000038,
DBG_BLOCK_ID_TCP18_BY2                   = 0x00000039,
DBG_BLOCK_ID_TCP20_BY2                   = 0x0000003a,
DBG_BLOCK_ID_TCP22_BY2                   = 0x0000003b,
DBG_BLOCK_ID_TCP_RESERVED0_BY2           = 0x0000003c,
DBG_BLOCK_ID_TCP_RESERVED2_BY2           = 0x0000003d,
DBG_BLOCK_ID_TCP_RESERVED4_BY2           = 0x0000003e,
DBG_BLOCK_ID_TCP_RESERVED6_BY2           = 0x0000003f,
DBG_BLOCK_ID_DB00_BY2                    = 0x00000040,
DBG_BLOCK_ID_DB02_BY2                    = 0x00000041,
DBG_BLOCK_ID_DB04_BY2                    = 0x00000042,
DBG_BLOCK_ID_UNUSED28_BY2                = 0x00000043,
DBG_BLOCK_ID_DB10_BY2                    = 0x00000044,
DBG_BLOCK_ID_DB12_BY2                    = 0x00000045,
DBG_BLOCK_ID_DB14_BY2                    = 0x00000046,
DBG_BLOCK_ID_UNUSED31_BY2                = 0x00000047,
DBG_BLOCK_ID_TCC0_BY2                    = 0x00000048,
DBG_BLOCK_ID_TCC2_BY2                    = 0x00000049,
DBG_BLOCK_ID_TCC4_BY2                    = 0x0000004a,
DBG_BLOCK_ID_TCC6_BY2                    = 0x0000004b,
DBG_BLOCK_ID_SPS00_BY2                   = 0x0000004c,
DBG_BLOCK_ID_SPS02_BY2                   = 0x0000004d,
DBG_BLOCK_ID_SPS11_BY2                   = 0x0000004e,
DBG_BLOCK_ID_UNUSED33_BY2                = 0x0000004f,
DBG_BLOCK_ID_TA00_BY2                    = 0x00000050,
DBG_BLOCK_ID_TA02_BY2                    = 0x00000051,
DBG_BLOCK_ID_TA04_BY2                    = 0x00000052,
DBG_BLOCK_ID_TA06_BY2                    = 0x00000053,
DBG_BLOCK_ID_TA08_BY2                    = 0x00000054,
DBG_BLOCK_ID_TA0A_BY2                    = 0x00000055,
DBG_BLOCK_ID_UNUSED35_BY2                = 0x00000056,
DBG_BLOCK_ID_UNUSED37_BY2                = 0x00000057,
DBG_BLOCK_ID_TA10_BY2                    = 0x00000058,
DBG_BLOCK_ID_TA12_BY2                    = 0x00000059,
DBG_BLOCK_ID_TA14_BY2                    = 0x0000005a,
DBG_BLOCK_ID_TA16_BY2                    = 0x0000005b,
DBG_BLOCK_ID_TA18_BY2                    = 0x0000005c,
DBG_BLOCK_ID_TA1A_BY2                    = 0x0000005d,
DBG_BLOCK_ID_UNUSED39_BY2                = 0x0000005e,
DBG_BLOCK_ID_UNUSED41_BY2                = 0x0000005f,
DBG_BLOCK_ID_TD00_BY2                    = 0x00000060,
DBG_BLOCK_ID_TD02_BY2                    = 0x00000061,
DBG_BLOCK_ID_TD04_BY2                    = 0x00000062,
DBG_BLOCK_ID_TD06_BY2                    = 0x00000063,
DBG_BLOCK_ID_TD08_BY2                    = 0x00000064,
DBG_BLOCK_ID_TD0A_BY2                    = 0x00000065,
DBG_BLOCK_ID_UNUSED43_BY2                = 0x00000066,
DBG_BLOCK_ID_UNUSED45_BY2                = 0x00000067,
DBG_BLOCK_ID_TD10_BY2                    = 0x00000068,
DBG_BLOCK_ID_TD12_BY2                    = 0x00000069,
DBG_BLOCK_ID_TD14_BY2                    = 0x0000006a,
DBG_BLOCK_ID_TD16_BY2                    = 0x0000006b,
DBG_BLOCK_ID_TD18_BY2                    = 0x0000006c,
DBG_BLOCK_ID_TD1A_BY2                    = 0x0000006d,
DBG_BLOCK_ID_UNUSED47_BY2                = 0x0000006e,
DBG_BLOCK_ID_UNUSED49_BY2                = 0x0000006f,
DBG_BLOCK_ID_MCD0_BY2                    = 0x00000070,
DBG_BLOCK_ID_MCD2_BY2                    = 0x00000071,
DBG_BLOCK_ID_MCD4_BY2                    = 0x00000072,
DBG_BLOCK_ID_UNUSED51_BY2                = 0x00000073,
} DebugBlockId_BY2;

typedef enum DebugBlockId_BY4 {
DBG_BLOCK_ID_RESERVED_BY4                = 0x00000000,
DBG_BLOCK_ID_CG_BY4                      = 0x00000001,
DBG_BLOCK_ID_CSC_BY4                     = 0x00000002,
DBG_BLOCK_ID_SQ_BY4                      = 0x00000003,
DBG_BLOCK_ID_SPIS_BY4                    = 0x00000005,
DBG_BLOCK_ID_CP0_BY4                     = 0x00000006,
DBG_BLOCK_ID_UVDU_BY4                    = 0x00000007,
DBG_BLOCK_ID_VGT0_BY4                    = 0x00000008,
DBG_BLOCK_ID_SCT0_BY4                    = 0x00000009,
DBG_BLOCK_ID_TCAA_BY4                    = 0x0000000a,
DBG_BLOCK_ID_MCC0_BY4                    = 0x0000000b,
DBG_BLOCK_ID_SX0_BY4                     = 0x0000000c,
DBG_BLOCK_ID_UNUSED4_BY4                 = 0x0000000d,
DBG_BLOCK_ID_PC0_BY4                     = 0x0000000e,
DBG_BLOCK_ID_UNUSED10_BY4                = 0x0000000f,
DBG_BLOCK_ID_SCB0_BY4                    = 0x00000010,
DBG_BLOCK_ID_SCF0_BY4                    = 0x00000011,
DBG_BLOCK_ID_BCI0_BY4                    = 0x00000012,
DBG_BLOCK_ID_UNUSED17_BY4                = 0x00000013,
DBG_BLOCK_ID_CB00_BY4                    = 0x00000014,
DBG_BLOCK_ID_CB04_BY4                    = 0x00000015,
DBG_BLOCK_ID_CB10_BY4                    = 0x00000016,
DBG_BLOCK_ID_CB14_BY4                    = 0x00000017,
DBG_BLOCK_ID_TCP0_BY4                    = 0x00000018,
DBG_BLOCK_ID_TCP4_BY4                    = 0x00000019,
DBG_BLOCK_ID_TCP8_BY4                    = 0x0000001a,
DBG_BLOCK_ID_TCP12_BY4                   = 0x0000001b,
DBG_BLOCK_ID_TCP16_BY4                   = 0x0000001c,
DBG_BLOCK_ID_TCP20_BY4                   = 0x0000001d,
DBG_BLOCK_ID_TCP_RESERVED0_BY4           = 0x0000001e,
DBG_BLOCK_ID_TCP_RESERVED4_BY4           = 0x0000001f,
DBG_BLOCK_ID_DB_BY4                      = 0x00000020,
DBG_BLOCK_ID_DB04_BY4                    = 0x00000021,
DBG_BLOCK_ID_DB10_BY4                    = 0x00000022,
DBG_BLOCK_ID_DB14_BY4                    = 0x00000023,
DBG_BLOCK_ID_TCC0_BY4                    = 0x00000024,
DBG_BLOCK_ID_TCC4_BY4                    = 0x00000025,
DBG_BLOCK_ID_SPS00_BY4                   = 0x00000026,
DBG_BLOCK_ID_SPS11_BY4                   = 0x00000027,
DBG_BLOCK_ID_TA00_BY4                    = 0x00000028,
DBG_BLOCK_ID_TA04_BY4                    = 0x00000029,
DBG_BLOCK_ID_TA08_BY4                    = 0x0000002a,
DBG_BLOCK_ID_UNUSED35_BY4                = 0x0000002b,
DBG_BLOCK_ID_TA10_BY4                    = 0x0000002c,
DBG_BLOCK_ID_TA14_BY4                    = 0x0000002d,
DBG_BLOCK_ID_TA18_BY4                    = 0x0000002e,
DBG_BLOCK_ID_UNUSED39_BY4                = 0x0000002f,
DBG_BLOCK_ID_TD00_BY4                    = 0x00000030,
DBG_BLOCK_ID_TD04_BY4                    = 0x00000031,
DBG_BLOCK_ID_TD08_BY4                    = 0x00000032,
DBG_BLOCK_ID_UNUSED43_BY4                = 0x00000033,
DBG_BLOCK_ID_TD10_BY4                    = 0x00000034,
DBG_BLOCK_ID_TD14_BY4                    = 0x00000035,
DBG_BLOCK_ID_TD18_BY4                    = 0x00000036,
DBG_BLOCK_ID_UNUSED47_BY4                = 0x00000037,
DBG_BLOCK_ID_MCD0_BY4                    = 0x00000038,
DBG_BLOCK_ID_MCD4_BY4                    = 0x00000039,
} DebugBlockId_BY4;

typedef enum DebugBlockId_BY8 {
DBG_BLOCK_ID_RESERVED_BY8                = 0x00000000,
DBG_BLOCK_ID_CSC_BY8                     = 0x00000001,
DBG_BLOCK_ID_CP0_BY8                     = 0x00000003,
DBG_BLOCK_ID_VGT0_BY8                    = 0x00000004,
DBG_BLOCK_ID_TCAA_BY8                    = 0x00000005,
DBG_BLOCK_ID_SX0_BY8                     = 0x00000006,
DBG_BLOCK_ID_PC0_BY8                     = 0x00000007,
DBG_BLOCK_ID_SCB0_BY8                    = 0x00000008,
DBG_BLOCK_ID_BCI0_BY8                    = 0x00000009,
DBG_BLOCK_ID_CB00_BY8                    = 0x0000000a,
DBG_BLOCK_ID_CB10_BY8                    = 0x0000000b,
DBG_BLOCK_ID_TCP0_BY8                    = 0x0000000c,
DBG_BLOCK_ID_TCP8_BY8                    = 0x0000000d,
DBG_BLOCK_ID_TCP16_BY8                   = 0x0000000e,
DBG_BLOCK_ID_TCP_RESERVED0_BY8           = 0x0000000f,
DBG_BLOCK_ID_DB00_BY8                    = 0x00000010,
DBG_BLOCK_ID_DB10_BY8                    = 0x00000011,
DBG_BLOCK_ID_TCC0_BY8                    = 0x00000012,
DBG_BLOCK_ID_SPS00_BY8                   = 0x00000013,
DBG_BLOCK_ID_TA00_BY8                    = 0x00000014,
DBG_BLOCK_ID_TA08_BY8                    = 0x00000015,
DBG_BLOCK_ID_TA10_BY8                    = 0x00000016,
DBG_BLOCK_ID_TA18_BY8                    = 0x00000017,
DBG_BLOCK_ID_TD00_BY8                    = 0x00000018,
DBG_BLOCK_ID_TD08_BY8                    = 0x00000019,
DBG_BLOCK_ID_TD10_BY8                    = 0x0000001a,
DBG_BLOCK_ID_TD18_BY8                    = 0x0000001b,
DBG_BLOCK_ID_MCD0_BY8                    = 0x0000001c,
} DebugBlockId_BY8;

typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH                       = 0x00000000,
ARRAY_2D_DEPTH                           = 0x00000001,
} DepthArray;

typedef enum DepthFormat {
DEPTH_INVALID                            = 0x00000000,
DEPTH_16                                 = 0x00000001,
DEPTH_X8_24                              = 0x00000002,
DEPTH_8_24                               = 0x00000003,
DEPTH_X8_24_FLOAT                        = 0x00000004,
DEPTH_8_24_FLOAT                         = 0x00000005,
DEPTH_32_FLOAT                           = 0x00000006,
DEPTH_X24_8_32_FLOAT                     = 0x00000007,
} DepthFormat;

typedef enum ENUM_SQ_EXPORT_RAT_INST {
SQ_EXPORT_RAT_INST_NOP                   = 0x00000000,
SQ_EXPORT_RAT_INST_STORE_TYPED           = 0x00000001,
SQ_EXPORT_RAT_INST_STORE_RAW             = 0x00000002,
SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM     = 0x00000003,
SQ_EXPORT_RAT_INST_CMPXCHG_INT           = 0x00000004,
SQ_EXPORT_RAT_INST_CMPXCHG_FLT           = 0x00000005,
SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM       = 0x00000006,
SQ_EXPORT_RAT_INST_ADD                   = 0x00000007,
SQ_EXPORT_RAT_INST_SUB                   = 0x00000008,
SQ_EXPORT_RAT_INST_RSUB                  = 0x00000009,
SQ_EXPORT_RAT_INST_MIN_INT               = 0x0000000a,
SQ_EXPORT_RAT_INST_MIN_UINT              = 0x0000000b,
SQ_EXPORT_RAT_INST_MAX_INT               = 0x0000000c,
SQ_EXPORT_RAT_INST_MAX_UINT              = 0x0000000d,
SQ_EXPORT_RAT_INST_AND                   = 0x0000000e,
SQ_EXPORT_RAT_INST_OR                    = 0x0000000f,
SQ_EXPORT_RAT_INST_XOR                   = 0x00000010,
SQ_EXPORT_RAT_INST_MSKOR                 = 0x00000011,
SQ_EXPORT_RAT_INST_INC_UINT              = 0x00000012,
SQ_EXPORT_RAT_INST_DEC_UINT              = 0x00000013,
SQ_EXPORT_RAT_INST_STORE_DWORD           = 0x00000014,
SQ_EXPORT_RAT_INST_STORE_SHORT           = 0x00000015,
SQ_EXPORT_RAT_INST_STORE_BYTE            = 0x00000016,
SQ_EXPORT_RAT_INST_NOP_RTN               = 0x00000020,
SQ_EXPORT_RAT_INST_XCHG_RTN              = 0x00000022,
SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN      = 0x00000023,
SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN       = 0x00000024,
SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN       = 0x00000025,
SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN   = 0x00000026,
SQ_EXPORT_RAT_INST_ADD_RTN               = 0x00000027,
SQ_EXPORT_RAT_INST_SUB_RTN               = 0x00000028,
SQ_EXPORT_RAT_INST_RSUB_RTN              = 0x00000029,
SQ_EXPORT_RAT_INST_MIN_INT_RTN           = 0x0000002a,
SQ_EXPORT_RAT_INST_MIN_UINT_RTN          = 0x0000002b,
SQ_EXPORT_RAT_INST_MAX_INT_RTN           = 0x0000002c,
SQ_EXPORT_RAT_INST_MAX_UINT_RTN          = 0x0000002d,
SQ_EXPORT_RAT_INST_AND_RTN               = 0x0000002e,
SQ_EXPORT_RAT_INST_OR_RTN                = 0x0000002f,
SQ_EXPORT_RAT_INST_XOR_RTN               = 0x00000030,
SQ_EXPORT_RAT_INST_MSKOR_RTN             = 0x00000031,
SQ_EXPORT_RAT_INST_INC_UINT_RTN          = 0x00000032,
SQ_EXPORT_RAT_INST_DEC_UINT_RTN          = 0x00000033,
} ENUM_SQ_EXPORT_RAT_INST;

typedef enum ForceControl {
FORCE_OFF                                = 0x00000000,
FORCE_ENABLE                             = 0x00000001,
FORCE_DISABLE                            = 0x00000002,
FORCE_RESERVED                           = 0x00000003,
} ForceControl;

typedef enum GB_EDC_DED_MODE {
GB_EDC_DED_MODE_LOG                      = 0x00000000,
GB_EDC_DED_MODE_HALT                     = 0x00000001,
GB_EDC_DED_MODE_INT_HALT                 = 0x00000002,
} GB_EDC_DED_MODE;

typedef enum GRBM_PERF_SEL {
GRBM_PERF_SEL_COUNT                      = 0x00000000,
GRBM_PERF_SEL_USER_DEFINED               = 0x00000001,
GRBM_PERF_SEL_GUI_ACTIVE                 = 0x00000002,
GRBM_PERF_SEL_CP_BUSY                    = 0x00000003,
GRBM_PERF_SEL_CP_COHER_BUSY              = 0x00000004,
GRBM_PERF_SEL_CP_DMA_BUSY                = 0x00000005,
GRBM_PERF_SEL_CB_BUSY                    = 0x00000006,
GRBM_PERF_SEL_DB_BUSY                    = 0x00000007,
GRBM_PERF_SEL_PA_BUSY                    = 0x00000008,
GRBM_PERF_SEL_SC_BUSY                    = 0x00000009,
GRBM_PERF_SEL_RESERVED_2__SI             = 0x0000000a,
GRBM_PERF_SEL_RESERVED_6__CI__VI         = 0x0000000a,
GRBM_PERF_SEL_SPI_BUSY                   = 0x0000000b,
GRBM_PERF_SEL_SX_BUSY                    = 0x0000000c,
GRBM_PERF_SEL_TA_BUSY                    = 0x0000000d,
GRBM_PERF_SEL_CB_CLEAN                   = 0x0000000e,
GRBM_PERF_SEL_DB_CLEAN                   = 0x0000000f,
GRBM_PERF_SEL_RESERVED_1__SI             = 0x00000010,
GRBM_PERF_SEL_RESERVED_5__CI__VI         = 0x00000010,
GRBM_PERF_SEL_VGT_BUSY                   = 0x00000011,
GRBM_PERF_SEL_RESERVED_0__SI             = 0x00000012,
GRBM_PERF_SEL_RESERVED_4__CI__VI         = 0x00000012,
GRBM_PERF_SEL_RESERVED_3__CI__VI         = 0x00000013,
GRBM_PERF_SEL_RESERVED_2__CI__VI         = 0x00000014,
GRBM_PERF_SEL_RESERVED_1__CI__VI         = 0x00000015,
GRBM_PERF_SEL_RESERVED_0__CI__VI         = 0x00000016,
GRBM_PERF_SEL_IA_BUSY                    = 0x00000017,
GRBM_PERF_SEL_IA_NO_DMA_BUSY             = 0x00000018,
GRBM_PERF_SEL_GDS_BUSY                   = 0x00000019,
GRBM_PERF_SEL_BCI_BUSY                   = 0x0000001a,
GRBM_PERF_SEL_RLC_BUSY                   = 0x0000001b,
GRBM_PERF_SEL_TC_BUSY                    = 0x0000001c,
GRBM_PERF_SEL_CPG_BUSY__CI__VI           = 0x0000001d,
GRBM_PERF_SEL_CPC_BUSY__CI__VI           = 0x0000001e,
GRBM_PERF_SEL_CPF_BUSY__CI__VI           = 0x0000001f,
GRBM_PERF_SEL_WD_BUSY__CI__VI            = 0x00000020,
GRBM_PERF_SEL_WD_NO_DMA_BUSY__CI__VI     = 0x00000021,
} GRBM_PERF_SEL;

typedef enum GRBM_SE0_PERF_SEL {
GRBM_SE0_PERF_SEL_COUNT                  = 0x00000000,
GRBM_SE0_PERF_SEL_USER_DEFINED           = 0x00000001,
GRBM_SE0_PERF_SEL_CB_BUSY                = 0x00000002,
GRBM_SE0_PERF_SEL_DB_BUSY                = 0x00000003,
GRBM_SE0_PERF_SEL_SC_BUSY                = 0x00000004,
GRBM_SE0_PERF_SEL_RESERVED_1             = 0x00000005,
GRBM_SE0_PERF_SEL_SPI_BUSY               = 0x00000006,
GRBM_SE0_PERF_SEL_SX_BUSY                = 0x00000007,
GRBM_SE0_PERF_SEL_TA_BUSY                = 0x00000008,
GRBM_SE0_PERF_SEL_CB_CLEAN               = 0x00000009,
GRBM_SE0_PERF_SEL_DB_CLEAN               = 0x0000000a,
GRBM_SE0_PERF_SEL_RESERVED_0             = 0x0000000b,
GRBM_SE0_PERF_SEL_PA_BUSY                = 0x0000000c,
GRBM_SE0_PERF_SEL_VGT_BUSY               = 0x0000000d,
GRBM_SE0_PERF_SEL_BCI_BUSY               = 0x0000000e,
} GRBM_SE0_PERF_SEL;

typedef enum GRBM_SE1_PERF_SEL {
GRBM_SE1_PERF_SEL_COUNT                  = 0x00000000,
GRBM_SE1_PERF_SEL_USER_DEFINED           = 0x00000001,
GRBM_SE1_PERF_SEL_CB_BUSY                = 0x00000002,
GRBM_SE1_PERF_SEL_DB_BUSY                = 0x00000003,
GRBM_SE1_PERF_SEL_SC_BUSY                = 0x00000004,
GRBM_SE1_PERF_SEL_RESERVED_1             = 0x00000005,
GRBM_SE1_PERF_SEL_SPI_BUSY               = 0x00000006,
GRBM_SE1_PERF_SEL_SX_BUSY                = 0x00000007,
GRBM_SE1_PERF_SEL_TA_BUSY                = 0x00000008,
GRBM_SE1_PERF_SEL_CB_CLEAN               = 0x00000009,
GRBM_SE1_PERF_SEL_DB_CLEAN               = 0x0000000a,
GRBM_SE1_PERF_SEL_RESERVED_0             = 0x0000000b,
GRBM_SE1_PERF_SEL_PA_BUSY                = 0x0000000c,
GRBM_SE1_PERF_SEL_VGT_BUSY               = 0x0000000d,
GRBM_SE1_PERF_SEL_BCI_BUSY               = 0x0000000e,
} GRBM_SE1_PERF_SEL;

typedef enum GRBM_SE2_PERF_SEL {
GRBM_SE2_PERF_SEL_COUNT                  = 0x00000000,
GRBM_SE2_PERF_SEL_USER_DEFINED           = 0x00000001,
GRBM_SE2_PERF_SEL_CB_BUSY                = 0x00000002,
GRBM_SE2_PERF_SEL_DB_BUSY                = 0x00000003,
GRBM_SE2_PERF_SEL_SC_BUSY                = 0x00000004,
GRBM_SE2_PERF_SEL_RESERVED_1             = 0x00000005,
GRBM_SE2_PERF_SEL_SPI_BUSY               = 0x00000006,
GRBM_SE2_PERF_SEL_SX_BUSY                = 0x00000007,
GRBM_SE2_PERF_SEL_TA_BUSY                = 0x00000008,
GRBM_SE2_PERF_SEL_CB_CLEAN               = 0x00000009,
GRBM_SE2_PERF_SEL_DB_CLEAN               = 0x0000000a,
GRBM_SE2_PERF_SEL_RESERVED_0             = 0x0000000b,
GRBM_SE2_PERF_SEL_PA_BUSY                = 0x0000000c,
GRBM_SE2_PERF_SEL_VGT_BUSY               = 0x0000000d,
GRBM_SE2_PERF_SEL_BCI_BUSY               = 0x0000000e,
} GRBM_SE2_PERF_SEL;

typedef enum GRBM_SE3_PERF_SEL {
GRBM_SE3_PERF_SEL_COUNT                  = 0x00000000,
GRBM_SE3_PERF_SEL_USER_DEFINED           = 0x00000001,
GRBM_SE3_PERF_SEL_CB_BUSY                = 0x00000002,
GRBM_SE3_PERF_SEL_DB_BUSY                = 0x00000003,
GRBM_SE3_PERF_SEL_SC_BUSY                = 0x00000004,
GRBM_SE3_PERF_SEL_RESERVED_1             = 0x00000005,
GRBM_SE3_PERF_SEL_SPI_BUSY               = 0x00000006,
GRBM_SE3_PERF_SEL_SX_BUSY                = 0x00000007,
GRBM_SE3_PERF_SEL_TA_BUSY                = 0x00000008,
GRBM_SE3_PERF_SEL_CB_CLEAN               = 0x00000009,
GRBM_SE3_PERF_SEL_DB_CLEAN               = 0x0000000a,
GRBM_SE3_PERF_SEL_RESERVED_0             = 0x0000000b,
GRBM_SE3_PERF_SEL_PA_BUSY                = 0x0000000c,
GRBM_SE3_PERF_SEL_VGT_BUSY               = 0x0000000d,
GRBM_SE3_PERF_SEL_BCI_BUSY               = 0x0000000e,
} GRBM_SE3_PERF_SEL;

typedef enum GroupInterleave {
CONFIG_256B_GROUP                        = 0x00000000,
CONFIG_512B_GROUP                        = 0x00000001,
} GroupInterleave;

typedef enum IA_PERFCOUNT_SELECT {
ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE__CI__VI = 0x00000000,
ia_perf_MC_LAT_BIN_0__CI                 = 0x00000001,
ia_perf_dma_data_fifo_full__VI           = 0x00000001,
ia_perf_MC_LAT_BIN_1__CI                 = 0x00000002,
ia_perf_RESERVED1__VI                    = 0x00000002,
ia_perf_MC_LAT_BIN_2__CI                 = 0x00000003,
ia_perf_RESERVED2__VI                    = 0x00000003,
ia_perf_MC_LAT_BIN_3__CI                 = 0x00000004,
ia_perf_RESERVED3__VI                    = 0x00000004,
ia_perf_MC_LAT_BIN_4__CI                 = 0x00000005,
ia_perf_RESERVED4__VI                    = 0x00000005,
ia_perf_MC_LAT_BIN_5__CI                 = 0x00000006,
ia_perf_RESERVED5__VI                    = 0x00000006,
ia_perf_MC_LAT_BIN_0__SI__VI             = 0x00000007,
ia_perf_MC_LAT_BIN_6__CI                 = 0x00000007,
ia_perf_MC_LAT_BIN_1__SI__VI             = 0x00000008,
ia_perf_MC_LAT_BIN_7__CI                 = 0x00000008,
ia_perf_MC_LAT_BIN_2__SI__VI             = 0x00000009,
ia_perf_ia_busy__CI                      = 0x00000009,
ia_perf_MC_LAT_BIN_3__SI__VI             = 0x0000000a,
ia_perf_ia_sclk_reg_vld_event__CI        = 0x0000000a,
ia_perf_MC_LAT_BIN_4__SI__VI             = 0x0000000b,
ia_perf_RESERVED0__CI                    = 0x0000000b,
ia_perf_MC_LAT_BIN_5__SI__VI             = 0x0000000c,
ia_perf_ia_sclk_core_vld_event__CI       = 0x0000000c,
ia_perf_MC_LAT_BIN_6__SI__VI             = 0x0000000d,
ia_perf_RESERVED1__CI                    = 0x0000000d,
ia_perf_MC_LAT_BIN_7__SI__VI             = 0x0000000e,
ia_perf_ia_dma_return__CI                = 0x0000000e,
ia_perf_ia_busy__SI__VI                  = 0x0000000f,
ia_perf_shift_starved_pipe1_event__CI    = 0x0000000f,
ia_perf_ia_sclk_reg_vld_event__SI__VI    = 0x00000010,
ia_perf_shift_starved_pipe0_event__CI    = 0x00000010,
ia_perf_ia_stalled__CI                   = 0x00000011,
ia_perf_RESERVED6__VI                    = 0x00000011,
ia_perf_ia_sclk_core_vld_event__SI__VI   = 0x00000012,
ia_perf_RESERVED7__VI                    = 0x00000013,
ia_perf_ia_dma_return__SI__VI            = 0x00000014,
ia_perf_ia_stalled__SI__VI               = 0x00000015,
ia_perf_shift_starved_pipe0_event__VI    = 0x00000016,
ia_perf_shift_starved_pipe1_event__VI    = 0x00000017,
} IA_PERFCOUNT_SELECT;

typedef enum IH_CLIENT_ID {
DC_IH_SRC_ID_START                       = 0x00000001,
DC_IH_SRC_ID_END                         = 0x0000001f,
VGA_IH_SRC_ID_START                      = 0x00000020,
VGA_IH_SRC_ID_END                        = 0x00000027,
CAP_IH_SRC_ID_START                      = 0x00000028,
CAP_IH_SRC_ID_END                        = 0x0000002f,
VIP_IH_SRC_ID_START                      = 0x00000030,
VIP_IH_SRC_ID_END                        = 0x0000003f,
ROM_IH_SRC_ID_START                      = 0x00000040,
ROM_IH_SRC_ID_END                        = 0x0000005d,
BIF_IH_SRC_ID_START                      = 0x0000005e,
SAM_IH_SRC_ID_START__CI__VI              = 0x0000005f,
SRBM_IH_SRC_ID_START                     = 0x00000060,
SRBM_IH_SRC_ID_END                       = 0x00000067,
UVD_IH_SRC_ID_START                      = 0x00000072,
UVD_IH_SRC_ID_END                        = 0x00000085,
VMC_IH_SRC_ID_START                      = 0x00000086,
VMC_IH_SRC_ID_END                        = 0x0000008f,
RLC_IH_SRC_ID_START                      = 0x00000090,
RLC_IH_SRC_ID_END                        = 0x000000f3,
PDMA_IH_SRC_ID_START                     = 0x000000f4,
PDMA_IH_SRC_ID_END                       = 0x000000f7,
CG_IH_SRC_ID_START                       = 0x000000f8,
CG_IH_SRC_ID_END                         = 0x000000ff,
} IH_CLIENT_ID;

typedef enum IH_PERF_SEL {
IH_PERF_SEL_CYCLE__CI__VI                = 0x00000000,
IH_PERF_SEL_IDLE__CI__VI                 = 0x00000001,
IH_PERF_SEL_INPUT_IDLE__CI__VI           = 0x00000002,
IH_PERF_SEL_CLIENT0_IH_STALL__CI__VI     = 0x00000003,
IH_PERF_SEL_CLIENT1_IH_STALL__CI__VI     = 0x00000004,
IH_PERF_SEL_CLIENT2_IH_STALL__CI__VI     = 0x00000005,
IH_PERF_SEL_CLIENT3_IH_STALL__CI__VI     = 0x00000006,
IH_PERF_SEL_CLIENT4_IH_STALL__CI__VI     = 0x00000007,
IH_PERF_SEL_CLIENT5_IH_STALL__CI__VI     = 0x00000008,
IH_PERF_SEL_CLIENT6_IH_STALL__CI__VI     = 0x00000009,
IH_PERF_SEL_CLIENT7_IH_STALL__CI__VI     = 0x0000000a,
IH_PERF_SEL_RB_IDLE__CI__VI              = 0x0000000b,
IH_PERF_SEL_RB_FULL__CI__VI              = 0x0000000c,
IH_PERF_SEL_RB_OVERFLOW__CI__VI          = 0x0000000d,
IH_PERF_SEL_RB_WPTR_WRITEBACK__CI__VI    = 0x0000000e,
IH_PERF_SEL_RB_WPTR_WRAP__CI__VI         = 0x0000000f,
IH_PERF_SEL_RB_RPTR_WRAP__CI__VI         = 0x00000010,
IH_PERF_SEL_MC_WR_IDLE__CI__VI           = 0x00000011,
IH_PERF_SEL_MC_WR_COUNT__CI__VI          = 0x00000012,
IH_PERF_SEL_MC_WR_STALL__CI__VI          = 0x00000013,
IH_PERF_SEL_MC_WR_CLEAN_PENDING__CI__VI  = 0x00000014,
IH_PERF_SEL_MC_WR_CLEAN_STALL__CI__VI    = 0x00000015,
IH_PERF_SEL_BIF_RISING__CI__VI           = 0x00000016,
IH_PERF_SEL_BIF_FALLING__CI__VI          = 0x00000017,
IH_PERF_SEL_CLIENT8_IH_STALL__CI__VI     = 0x00000018,
IH_PERF_SEL_CLIENT9_IH_STALL__CI__VI     = 0x00000019,
IH_PERF_SEL_CLIENT10_IH_STALL__CI__VI    = 0x0000001a,
IH_PERF_SEL_CLIENT11_IH_STALL__CI__VI    = 0x0000001b,
IH_PERF_SEL_CLIENT12_IH_STALL__CI__VI    = 0x0000001c,
IH_PERF_SEL_CLIENT13_IH_STALL__CI__VI    = 0x0000001d,
IH_PERF_SEL_CLIENT14_IH_STALL__CI__VI    = 0x0000001e,
IH_PERF_SEL_CLIENT15_IH_STALL__CI__VI    = 0x0000001f,
IH_PERF_SEL_CLIENT16_IH_STALL__CI__VI    = 0x00000020,
IH_PERF_SEL_CLIENT17_IH_STALL__CI__VI    = 0x00000021,
IH_PERF_SEL_CLIENT18_IH_STALL__CI__VI    = 0x00000022,
IH_PERF_SEL_CLIENT19_IH_STALL__CI__VI    = 0x00000023,
IH_PERF_SEL_CLIENT20_IH_STALL__VI        = 0x00000024,
IH_PERF_SEL_CLIENT21_IH_STALL__VI        = 0x00000025,
IH_PERF_SEL_CLIENT22_IH_STALL__VI        = 0x00000026,
IH_PERF_SEL_RB_FULL_VF0__VI              = 0x00000027,
IH_PERF_SEL_RB_FULL_VF1__VI              = 0x00000028,
IH_PERF_SEL_RB_FULL_VF2__VI              = 0x00000029,
IH_PERF_SEL_RB_FULL_VF3__VI              = 0x0000002a,
IH_PERF_SEL_RB_FULL_VF4__VI              = 0x0000002b,
IH_PERF_SEL_RB_FULL_VF5__VI              = 0x0000002c,
IH_PERF_SEL_RB_FULL_VF6__VI              = 0x0000002d,
IH_PERF_SEL_RB_FULL_VF7__VI              = 0x0000002e,
IH_PERF_SEL_RB_FULL_VF8__VI              = 0x0000002f,
IH_PERF_SEL_RB_FULL_VF9__VI              = 0x00000030,
IH_PERF_SEL_RB_FULL_VF10__VI             = 0x00000031,
IH_PERF_SEL_RB_FULL_VF11__VI             = 0x00000032,
IH_PERF_SEL_RB_FULL_VF12__VI             = 0x00000033,
IH_PERF_SEL_RB_FULL_VF13__VI             = 0x00000034,
IH_PERF_SEL_RB_FULL_VF14__VI             = 0x00000035,
IH_PERF_SEL_RB_FULL_VF15__VI             = 0x00000036,
IH_PERF_SEL_RB_OVERFLOW_VF0__VI          = 0x00000037,
IH_PERF_SEL_RB_OVERFLOW_VF1__VI          = 0x00000038,
IH_PERF_SEL_RB_OVERFLOW_VF2__VI          = 0x00000039,
IH_PERF_SEL_RB_OVERFLOW_VF3__VI          = 0x0000003a,
IH_PERF_SEL_RB_OVERFLOW_VF4__VI          = 0x0000003b,
IH_PERF_SEL_RB_OVERFLOW_VF5__VI          = 0x0000003c,
IH_PERF_SEL_RB_OVERFLOW_VF6__VI          = 0x0000003d,
IH_PERF_SEL_RB_OVERFLOW_VF7__VI          = 0x0000003e,
IH_PERF_SEL_RB_OVERFLOW_VF8__VI          = 0x0000003f,
IH_PERF_SEL_RB_OVERFLOW_VF9__VI          = 0x00000040,
IH_PERF_SEL_RB_OVERFLOW_VF10__VI         = 0x00000041,
IH_PERF_SEL_RB_OVERFLOW_VF11__VI         = 0x00000042,
IH_PERF_SEL_RB_OVERFLOW_VF12__VI         = 0x00000043,
IH_PERF_SEL_RB_OVERFLOW_VF13__VI         = 0x00000044,
IH_PERF_SEL_RB_OVERFLOW_VF14__VI         = 0x00000045,
IH_PERF_SEL_RB_OVERFLOW_VF15__VI         = 0x00000046,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF0__VI    = 0x00000047,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF1__VI    = 0x00000048,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF2__VI    = 0x00000049,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF3__VI    = 0x0000004a,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF4__VI    = 0x0000004b,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF5__VI    = 0x0000004c,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF6__VI    = 0x0000004d,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF7__VI    = 0x0000004e,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF8__VI    = 0x0000004f,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF9__VI    = 0x00000050,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF10__VI   = 0x00000051,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF11__VI   = 0x00000052,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF12__VI   = 0x00000053,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF13__VI   = 0x00000054,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF14__VI   = 0x00000055,
IH_PERF_SEL_RB_WPTR_WRITEBACK_VF15__VI   = 0x00000056,
IH_PERF_SEL_RB_WPTR_WRAP_VF0__VI         = 0x00000057,
IH_PERF_SEL_RB_WPTR_WRAP_VF1__VI         = 0x00000058,
IH_PERF_SEL_RB_WPTR_WRAP_VF2__VI         = 0x00000059,
IH_PERF_SEL_RB_WPTR_WRAP_VF3__VI         = 0x0000005a,
IH_PERF_SEL_RB_WPTR_WRAP_VF4__VI         = 0x0000005b,
IH_PERF_SEL_RB_WPTR_WRAP_VF5__VI         = 0x0000005c,
IH_PERF_SEL_RB_WPTR_WRAP_VF6__VI         = 0x0000005d,
IH_PERF_SEL_RB_WPTR_WRAP_VF7__VI         = 0x0000005e,
IH_PERF_SEL_RB_WPTR_WRAP_VF8__VI         = 0x0000005f,
IH_PERF_SEL_RB_WPTR_WRAP_VF9__VI         = 0x00000060,
IH_PERF_SEL_RB_WPTR_WRAP_VF10__VI        = 0x00000061,
IH_PERF_SEL_RB_WPTR_WRAP_VF11__VI        = 0x00000062,
IH_PERF_SEL_RB_WPTR_WRAP_VF12__VI        = 0x00000063,
IH_PERF_SEL_RB_WPTR_WRAP_VF13__VI        = 0x00000064,
IH_PERF_SEL_RB_WPTR_WRAP_VF14__VI        = 0x00000065,
IH_PERF_SEL_RB_WPTR_WRAP_VF15__VI        = 0x00000066,
IH_PERF_SEL_RB_RPTR_WRAP_VF0__VI         = 0x00000067,
IH_PERF_SEL_RB_RPTR_WRAP_VF1__VI         = 0x00000068,
IH_PERF_SEL_RB_RPTR_WRAP_VF2__VI         = 0x00000069,
IH_PERF_SEL_RB_RPTR_WRAP_VF3__VI         = 0x0000006a,
IH_PERF_SEL_RB_RPTR_WRAP_VF4__VI         = 0x0000006b,
IH_PERF_SEL_RB_RPTR_WRAP_VF5__VI         = 0x0000006c,
IH_PERF_SEL_RB_RPTR_WRAP_VF6__VI         = 0x0000006d,
IH_PERF_SEL_RB_RPTR_WRAP_VF7__VI         = 0x0000006e,
IH_PERF_SEL_RB_RPTR_WRAP_VF8__VI         = 0x0000006f,
IH_PERF_SEL_RB_RPTR_WRAP_VF9__VI         = 0x00000070,
IH_PERF_SEL_RB_RPTR_WRAP_VF10__VI        = 0x00000071,
IH_PERF_SEL_RB_RPTR_WRAP_VF11__VI        = 0x00000072,
IH_PERF_SEL_RB_RPTR_WRAP_VF12__VI        = 0x00000073,
IH_PERF_SEL_RB_RPTR_WRAP_VF13__VI        = 0x00000074,
IH_PERF_SEL_RB_RPTR_WRAP_VF14__VI        = 0x00000075,
IH_PERF_SEL_RB_RPTR_WRAP_VF15__VI        = 0x00000076,
IH_PERF_SEL_BIF_RISING_VF0__VI           = 0x00000077,
IH_PERF_SEL_BIF_RISING_VF1__VI           = 0x00000078,
IH_PERF_SEL_BIF_RISING_VF2__VI           = 0x00000079,
IH_PERF_SEL_BIF_RISING_VF3__VI           = 0x0000007a,
IH_PERF_SEL_BIF_RISING_VF4__VI           = 0x0000007b,
IH_PERF_SEL_BIF_RISING_VF5__VI           = 0x0000007c,
IH_PERF_SEL_BIF_RISING_VF6__VI           = 0x0000007d,
IH_PERF_SEL_BIF_RISING_VF7__VI           = 0x0000007e,
IH_PERF_SEL_BIF_RISING_VF8__VI           = 0x0000007f,
IH_PERF_SEL_BIF_RISING_VF9__VI           = 0x00000080,
IH_PERF_SEL_BIF_RISING_VF10__VI          = 0x00000081,
IH_PERF_SEL_BIF_RISING_VF11__VI          = 0x00000082,
IH_PERF_SEL_BIF_RISING_VF12__VI          = 0x00000083,
IH_PERF_SEL_BIF_RISING_VF13__VI          = 0x00000084,
IH_PERF_SEL_BIF_RISING_VF14__VI          = 0x00000085,
IH_PERF_SEL_BIF_RISING_VF15__VI          = 0x00000086,
IH_PERF_SEL_BIF_FALLING_VF0__VI          = 0x00000087,
IH_PERF_SEL_BIF_FALLING_VF1__VI          = 0x00000088,
IH_PERF_SEL_BIF_FALLING_VF2__VI          = 0x00000089,
IH_PERF_SEL_BIF_FALLING_VF3__VI          = 0x0000008a,
IH_PERF_SEL_BIF_FALLING_VF4__VI          = 0x0000008b,
IH_PERF_SEL_BIF_FALLING_VF5__VI          = 0x0000008c,
IH_PERF_SEL_BIF_FALLING_VF6__VI          = 0x0000008d,
IH_PERF_SEL_BIF_FALLING_VF7__VI          = 0x0000008e,
IH_PERF_SEL_BIF_FALLING_VF8__VI          = 0x0000008f,
IH_PERF_SEL_BIF_FALLING_VF9__VI          = 0x00000090,
IH_PERF_SEL_BIF_FALLING_VF10__VI         = 0x00000091,
IH_PERF_SEL_BIF_FALLING_VF11__VI         = 0x00000092,
IH_PERF_SEL_BIF_FALLING_VF12__VI         = 0x00000093,
IH_PERF_SEL_BIF_FALLING_VF13__VI         = 0x00000094,
IH_PERF_SEL_BIF_FALLING_VF14__VI         = 0x00000095,
IH_PERF_SEL_BIF_FALLING_VF15__VI         = 0x00000096,
} IH_PERF_SEL;

typedef enum IMG_DATA_FORMAT {
IMG_DATA_FORMAT_INVALID                  = 0x00000000,
IMG_DATA_FORMAT_8                        = 0x00000001,
IMG_DATA_FORMAT_16                       = 0x00000002,
IMG_DATA_FORMAT_8_8                      = 0x00000003,
IMG_DATA_FORMAT_32                       = 0x00000004,
IMG_DATA_FORMAT_16_16                    = 0x00000005,
IMG_DATA_FORMAT_10_11_11                 = 0x00000006,
IMG_DATA_FORMAT_11_11_10                 = 0x00000007,
IMG_DATA_FORMAT_10_10_10_2               = 0x00000008,
IMG_DATA_FORMAT_2_10_10_10               = 0x00000009,
IMG_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
IMG_DATA_FORMAT_32_32                    = 0x0000000b,
IMG_DATA_FORMAT_16_16_16_16              = 0x0000000c,
IMG_DATA_FORMAT_32_32_32                 = 0x0000000d,
IMG_DATA_FORMAT_32_32_32_32              = 0x0000000e,
IMG_DATA_FORMAT_RESERVED_15              = 0x0000000f,
IMG_DATA_FORMAT_5_6_5                    = 0x00000010,
IMG_DATA_FORMAT_1_5_5_5                  = 0x00000011,
IMG_DATA_FORMAT_5_5_5_1                  = 0x00000012,
IMG_DATA_FORMAT_4_4_4_4                  = 0x00000013,
IMG_DATA_FORMAT_8_24                     = 0x00000014,
IMG_DATA_FORMAT_24_8                     = 0x00000015,
IMG_DATA_FORMAT_X24_8_32                 = 0x00000016,
IMG_DATA_FORMAT_RESERVED_23              = 0x00000017,
IMG_DATA_FORMAT_RESERVED_24              = 0x00000018,
IMG_DATA_FORMAT_ETC2_RGB__VI             = 0x00000018,
IMG_DATA_FORMAT_RESERVED_25              = 0x00000019,
IMG_DATA_FORMAT_ETC2_RGBA__VI            = 0x00000019,
IMG_DATA_FORMAT_RESERVED_26              = 0x0000001a,
IMG_DATA_FORMAT_ETC2_R__VI               = 0x0000001a,
IMG_DATA_FORMAT_RESERVED_27              = 0x0000001b,
IMG_DATA_FORMAT_ETC2_RG__VI              = 0x0000001b,
IMG_DATA_FORMAT_RESERVED_28              = 0x0000001c,
IMG_DATA_FORMAT_ETC2_RGBA1__VI           = 0x0000001c,
IMG_DATA_FORMAT_RESERVED_29              = 0x0000001d,
IMG_DATA_FORMAT_RESERVED_30              = 0x0000001e,
IMG_DATA_FORMAT_RESERVED_31              = 0x0000001f,
IMG_DATA_FORMAT_GB_GR                    = 0x00000020,
IMG_DATA_FORMAT_BG_RG                    = 0x00000021,
IMG_DATA_FORMAT_5_9_9_9                  = 0x00000022,
IMG_DATA_FORMAT_BC1                      = 0x00000023,
IMG_DATA_FORMAT_BC2                      = 0x00000024,
IMG_DATA_FORMAT_BC3                      = 0x00000025,
IMG_DATA_FORMAT_BC4                      = 0x00000026,
IMG_DATA_FORMAT_BC5                      = 0x00000027,
IMG_DATA_FORMAT_BC6                      = 0x00000028,
IMG_DATA_FORMAT_BC7                      = 0x00000029,
IMG_DATA_FORMAT_RESERVED_42              = 0x0000002a,
IMG_DATA_FORMAT_RESERVED_43              = 0x0000002b,
IMG_DATA_FORMAT_FMASK8_S2_F1             = 0x0000002c,
IMG_DATA_FORMAT_FMASK8_S4_F1             = 0x0000002d,
IMG_DATA_FORMAT_FMASK8_S8_F1             = 0x0000002e,
IMG_DATA_FORMAT_FMASK8_S2_F2             = 0x0000002f,
IMG_DATA_FORMAT_FMASK8_S4_F2             = 0x00000030,
IMG_DATA_FORMAT_FMASK8_S4_F4             = 0x00000031,
IMG_DATA_FORMAT_FMASK16_S16_F1           = 0x00000032,
IMG_DATA_FORMAT_FMASK16_S8_F2            = 0x00000033,
IMG_DATA_FORMAT_FMASK32_S16_F2           = 0x00000034,
IMG_DATA_FORMAT_FMASK32_S8_F4            = 0x00000035,
IMG_DATA_FORMAT_FMASK32_S8_F8            = 0x00000036,
IMG_DATA_FORMAT_FMASK64_S16_F4           = 0x00000037,
IMG_DATA_FORMAT_FMASK64_S16_F8           = 0x00000038,
IMG_DATA_FORMAT_4_4                      = 0x00000039,
IMG_DATA_FORMAT_6_5_5                    = 0x0000003a,
IMG_DATA_FORMAT_1                        = 0x0000003b,
IMG_DATA_FORMAT_1_REVERSED               = 0x0000003c,
IMG_DATA_FORMAT_32_AS_8                  = 0x0000003d,
IMG_DATA_FORMAT_32_AS_8_8                = 0x0000003e,
IMG_DATA_FORMAT_32_AS_32_32_32_32        = 0x0000003f,
} IMG_DATA_FORMAT;

typedef enum IMG_NUM_FORMAT {
IMG_NUM_FORMAT_UNORM                     = 0x00000000,
IMG_NUM_FORMAT_SNORM                     = 0x00000001,
IMG_NUM_FORMAT_USCALED                   = 0x00000002,
IMG_NUM_FORMAT_SSCALED                   = 0x00000003,
IMG_NUM_FORMAT_UINT                      = 0x00000004,
IMG_NUM_FORMAT_SINT                      = 0x00000005,
IMG_NUM_FORMAT_SNORM_OGL__SI__CI         = 0x00000006,
IMG_NUM_FORMAT_RESERVED_6__VI            = 0x00000006,
IMG_NUM_FORMAT_FLOAT                     = 0x00000007,
IMG_NUM_FORMAT_RESERVED_8                = 0x00000008,
IMG_NUM_FORMAT_SRGB                      = 0x00000009,
IMG_NUM_FORMAT_UBNORM__SI__CI            = 0x0000000a,
IMG_NUM_FORMAT_RESERVED_10__VI           = 0x0000000a,
IMG_NUM_FORMAT_UBNORM_OGL__SI__CI        = 0x0000000b,
IMG_NUM_FORMAT_RESERVED_11__VI           = 0x0000000b,
IMG_NUM_FORMAT_UBINT__SI__CI             = 0x0000000c,
IMG_NUM_FORMAT_RESERVED_12__VI           = 0x0000000c,
IMG_NUM_FORMAT_UBSCALED__SI__CI          = 0x0000000d,
IMG_NUM_FORMAT_RESERVED_13__VI           = 0x0000000d,
IMG_NUM_FORMAT_RESERVED_14               = 0x0000000e,
IMG_NUM_FORMAT_RESERVED_15               = 0x0000000f,
} IMG_NUM_FORMAT;

typedef enum MacroTileAspect {
ADDR_SURF_MACRO_ASPECT_1                 = 0x00000000,
ADDR_SURF_MACRO_ASPECT_2                 = 0x00000001,
ADDR_SURF_MACRO_ASPECT_4                 = 0x00000002,
ADDR_SURF_MACRO_ASPECT_8                 = 0x00000003,
} MacroTileAspect;

typedef enum MicroTileMode {
ADDR_SURF_DISPLAY_MICRO_TILING           = 0x00000000,
ADDR_SURF_THIN_MICRO_TILING              = 0x00000001,
ADDR_SURF_DEPTH_MICRO_TILING             = 0x00000002,
ADDR_SURF_THICK_MICRO_TILING__SI         = 0x00000003,
ADDR_SURF_ROTATED_MICRO_TILING__CI__VI   = 0x00000003,
ADDR_SURF_THICK_MICRO_TILING__CI__VI     = 0x00000004,
} MicroTileMode;

typedef enum MultiGPUTileSize {
ADDR_CONFIG_GPU_TILE_16                  = 0x00000000,
ADDR_CONFIG_GPU_TILE_32                  = 0x00000001,
ADDR_CONFIG_GPU_TILE_64                  = 0x00000002,
ADDR_CONFIG_GPU_TILE_128                 = 0x00000003,
} MultiGPUTileSize;

typedef enum NonDispTilingOrder {
ADDR_SURF_MICRO_TILING_DISPLAY           = 0x00000000,
ADDR_SURF_MICRO_TILING_NON_DISPLAY       = 0x00000001,
} NonDispTilingOrder;

typedef enum NumBanks {
ADDR_SURF_2_BANK                         = 0x00000000,
ADDR_SURF_4_BANK                         = 0x00000001,
ADDR_SURF_8_BANK                         = 0x00000002,
ADDR_SURF_16_BANK                        = 0x00000003,
} NumBanks;

typedef enum NumGPUs {
ADDR_CONFIG_1_GPU                        = 0x00000000,
ADDR_CONFIG_2_GPU                        = 0x00000001,
ADDR_CONFIG_4_GPU                        = 0x00000002,
} NumGPUs;

typedef enum NumLowerPipes {
ADDR_CONFIG_1_LOWER_PIPES                = 0x00000000,
ADDR_CONFIG_2_LOWER_PIPES                = 0x00000001,
} NumLowerPipes;

typedef enum NumPipes {
ADDR_CONFIG_1_PIPE                       = 0x00000000,
ADDR_CONFIG_2_PIPE                       = 0x00000001,
ADDR_CONFIG_4_PIPE                       = 0x00000002,
ADDR_CONFIG_8_PIPE                       = 0x00000003,
} NumPipes;

typedef enum NumShaderEngines {
ADDR_CONFIG_1_SHADER_ENGINE              = 0x00000000,
ADDR_CONFIG_2_SHADER_ENGINE              = 0x00000001,
} NumShaderEngines;

typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES__CI__VI = 0x00000009,
PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
} PERFMON_COUNTER_MODE;

typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF                     = 0x00000000,
PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
} PERFMON_SPM_MODE;

typedef enum PerfCounter_Vals {
DB_PERF_SEL_SC_DB_tile_sends             = 0x00000000,
DB_PERF_SEL_SC_DB_tile_busy              = 0x00000001,
DB_PERF_SEL_SC_DB_tile_stalls            = 0x00000002,
DB_PERF_SEL_SC_DB_tile_events            = 0x00000003,
DB_PERF_SEL_SC_DB_tile_tiles             = 0x00000004,
DB_PERF_SEL_SC_DB_tile_covered           = 0x00000005,
DB_PERF_SEL_hiz_tc_read_starved          = 0x00000006,
DB_PERF_SEL_hiz_tc_write_stall           = 0x00000007,
DB_PERF_SEL_hiz_qtiles_culled            = 0x00000008,
DB_PERF_SEL_his_qtiles_culled            = 0x00000009,
DB_PERF_SEL_DB_SC_tile_sends             = 0x0000000a,
DB_PERF_SEL_DB_SC_tile_busy              = 0x0000000b,
DB_PERF_SEL_DB_SC_tile_stalls            = 0x0000000c,
DB_PERF_SEL_DB_SC_tile_df_stalls         = 0x0000000d,
DB_PERF_SEL_DB_SC_tile_tiles             = 0x0000000e,
DB_PERF_SEL_DB_SC_tile_culled            = 0x0000000f,
DB_PERF_SEL_DB_SC_tile_hier_kill         = 0x00000010,
DB_PERF_SEL_DB_SC_tile_fast_ops          = 0x00000011,
DB_PERF_SEL_DB_SC_tile_no_ops            = 0x00000012,
DB_PERF_SEL_DB_SC_tile_tile_rate         = 0x00000013,
DB_PERF_SEL_DB_SC_tile_ssaa_kill         = 0x00000014,
DB_PERF_SEL_DB_SC_tile_fast_z_ops        = 0x00000015,
DB_PERF_SEL_DB_SC_tile_fast_stencil_ops  = 0x00000016,
DB_PERF_SEL_SC_DB_quad_sends             = 0x00000017,
DB_PERF_SEL_SC_DB_quad_busy              = 0x00000018,
DB_PERF_SEL_SC_DB_quad_squads            = 0x00000019,
DB_PERF_SEL_SC_DB_quad_tiles             = 0x0000001a,
DB_PERF_SEL_SC_DB_quad_pixels            = 0x0000001b,
DB_PERF_SEL_SC_DB_quad_killed_tiles      = 0x0000001c,
DB_PERF_SEL_DB_SC_quad_sends             = 0x0000001d,
DB_PERF_SEL_DB_SC_quad_busy              = 0x0000001e,
DB_PERF_SEL_DB_SC_quad_stalls            = 0x0000001f,
DB_PERF_SEL_DB_SC_quad_tiles__CI__VI     = 0x00000020,
DB_PERF_SEL_DB_SC_quad_tiles__SI         = 0x00000021,
DB_PERF_SEL_DB_SC_quad_lit_quad__CI__VI  = 0x00000021,
DB_PERF_SEL_DB_SC_quad_lit_quad__SI      = 0x00000022,
DB_PERF_SEL_DB_CB_tile_sends__CI__VI     = 0x00000022,
DB_PERF_SEL_DB_CB_tile_sends__SI         = 0x00000023,
DB_PERF_SEL_DB_CB_tile_busy__CI__VI      = 0x00000023,
DB_PERF_SEL_DB_CB_tile_busy__SI          = 0x00000024,
DB_PERF_SEL_DB_CB_tile_stalls__CI__VI    = 0x00000024,
DB_PERF_SEL_DB_CB_tile_stalls__SI        = 0x00000025,
DB_PERF_SEL_SX_DB_quad_sends__CI__VI     = 0x00000025,
DB_PERF_SEL_SX_DB_quad_sends__SI         = 0x00000026,
DB_PERF_SEL_SX_DB_quad_busy__CI__VI      = 0x00000026,
DB_PERF_SEL_SX_DB_quad_busy__SI          = 0x00000027,
DB_PERF_SEL_SX_DB_quad_stalls__CI__VI    = 0x00000027,
DB_PERF_SEL_SX_DB_quad_stalls__SI        = 0x00000028,
DB_PERF_SEL_SX_DB_quad_quads__CI__VI     = 0x00000028,
DB_PERF_SEL_SX_DB_quad_quads__SI         = 0x00000029,
DB_PERF_SEL_SX_DB_quad_pixels__CI__VI    = 0x00000029,
DB_PERF_SEL_SX_DB_quad_pixels__SI        = 0x0000002a,
DB_PERF_SEL_SX_DB_quad_exports__CI__VI   = 0x0000002a,
DB_PERF_SEL_SX_DB_quad_exports__SI       = 0x0000002b,
DB_PERF_SEL_SH_quads_outstanding_sum__CI__VI = 0x0000002b,
DB_PERF_SEL_SH_quads_outstanding_sum__SI = 0x0000002c,
DB_PERF_SEL_DB_CB_lquad_sends__CI__VI    = 0x0000002c,
DB_PERF_SEL_DB_CB_lquad_sends__SI        = 0x0000002d,
DB_PERF_SEL_DB_CB_lquad_busy__CI__VI     = 0x0000002d,
DB_PERF_SEL_DB_CB_lquad_busy__SI         = 0x0000002e,
DB_PERF_SEL_DB_CB_lquad_stalls__CI__VI   = 0x0000002e,
DB_PERF_SEL_DB_CB_lquad_stalls__SI       = 0x0000002f,
DB_PERF_SEL_DB_CB_lquad_quads__CI__VI    = 0x0000002f,
DB_PERF_SEL_DB_CB_lquad_quads__SI        = 0x00000030,
DB_PERF_SEL_tile_rd_sends__CI__VI        = 0x00000030,
DB_PERF_SEL_tile_rd_sends__SI            = 0x00000031,
DB_PERF_SEL_mi_tile_rd_outstanding_sum__CI__VI = 0x00000031,
DB_PERF_SEL_mi_tile_rd_outstanding_sum__SI = 0x00000032,
DB_PERF_SEL_quad_rd_sends__CI__VI        = 0x00000032,
DB_PERF_SEL_quad_rd_sends__SI            = 0x00000033,
DB_PERF_SEL_quad_rd_busy__CI__VI         = 0x00000033,
DB_PERF_SEL_quad_rd_busy__SI             = 0x00000034,
DB_PERF_SEL_quad_rd_mi_stall__CI__VI     = 0x00000034,
DB_PERF_SEL_quad_rd_mi_stall__SI         = 0x00000035,
DB_PERF_SEL_quad_rd_rw_collision__CI__VI = 0x00000035,
DB_PERF_SEL_quad_rd_rw_collision__SI     = 0x00000036,
DB_PERF_SEL_quad_rd_tag_stall__CI__VI    = 0x00000036,
DB_PERF_SEL_quad_rd_tag_stall__SI        = 0x00000037,
DB_PERF_SEL_quad_rd_32byte_reqs__CI__VI  = 0x00000037,
DB_PERF_SEL_quad_rd_32byte_reqs__SI      = 0x00000038,
DB_PERF_SEL_quad_rd_panic__CI__VI        = 0x00000038,
DB_PERF_SEL_quad_rd_panic__SI            = 0x00000039,
DB_PERF_SEL_mi_quad_rd_outstanding_sum__CI__VI = 0x00000039,
DB_PERF_SEL_mi_quad_rd_outstanding_sum__SI = 0x0000003a,
DB_PERF_SEL_quad_rdret_sends__CI__VI     = 0x0000003a,
DB_PERF_SEL_quad_rdret_sends__SI         = 0x0000003b,
DB_PERF_SEL_quad_rdret_busy__CI__VI      = 0x0000003b,
DB_PERF_SEL_quad_rdret_busy__SI          = 0x0000003c,
DB_PERF_SEL_tile_wr_sends__CI__VI        = 0x0000003c,
DB_PERF_SEL_tile_wr_sends__SI            = 0x0000003d,
DB_PERF_SEL_tile_wr_acks__CI__VI         = 0x0000003d,
DB_PERF_SEL_tile_wr_acks__SI             = 0x0000003e,
DB_PERF_SEL_mi_tile_wr_outstanding_sum__CI__VI = 0x0000003e,
DB_PERF_SEL_mi_tile_wr_outstanding_sum__SI = 0x0000003f,
DB_PERF_SEL_quad_wr_sends__CI__VI        = 0x0000003f,
DB_PERF_SEL_quad_wr_sends__SI            = 0x00000040,
DB_PERF_SEL_quad_wr_busy__CI__VI         = 0x00000040,
DB_PERF_SEL_quad_wr_busy__SI             = 0x00000041,
DB_PERF_SEL_quad_wr_mi_stall__CI__VI     = 0x00000041,
DB_PERF_SEL_quad_wr_mi_stall__SI         = 0x00000042,
DB_PERF_SEL_quad_wr_coherency_stall__CI__VI = 0x00000042,
DB_PERF_SEL_quad_wr_coherency_stall__SI  = 0x00000043,
DB_PERF_SEL_quad_wr_acks__CI__VI         = 0x00000043,
DB_PERF_SEL_quad_wr_acks__SI             = 0x00000044,
DB_PERF_SEL_mi_quad_wr_outstanding_sum__CI__VI = 0x00000044,
DB_PERF_SEL_mi_quad_wr_outstanding_sum__SI = 0x00000045,
DB_PERF_SEL_Tile_Cache_misses__CI__VI    = 0x00000045,
DB_PERF_SEL_Tile_Cache_misses__SI        = 0x00000046,
DB_PERF_SEL_Tile_Cache_hits__CI__VI      = 0x00000046,
DB_PERF_SEL_Tile_Cache_hits__SI          = 0x00000047,
DB_PERF_SEL_Tile_Cache_flushes__CI__VI   = 0x00000047,
DB_PERF_SEL_Tile_Cache_flushes__SI       = 0x00000048,
DB_PERF_SEL_Tile_Cache_surface_stall__CI__VI = 0x00000048,
DB_PERF_SEL_Tile_Cache_surface_stall__SI = 0x00000049,
DB_PERF_SEL_Tile_Cache_starves__CI__VI   = 0x00000049,
DB_PERF_SEL_Tile_Cache_starves__SI       = 0x0000004a,
DB_PERF_SEL_Tile_Cache_mem_return_starve__CI__VI = 0x0000004a,
DB_PERF_SEL_Tile_Cache_mem_return_starve__SI = 0x0000004b,
DB_PERF_SEL_tcp_dispatcher_reads__CI__VI = 0x0000004b,
DB_PERF_SEL_tcp_dispatcher_reads__SI     = 0x0000004c,
DB_PERF_SEL_tcp_prefetcher_reads__CI__VI = 0x0000004c,
DB_PERF_SEL_tcp_prefetcher_reads__SI     = 0x0000004d,
DB_PERF_SEL_tcp_preloader_reads__CI__VI  = 0x0000004d,
DB_PERF_SEL_tcp_preloader_reads__SI      = 0x0000004e,
DB_PERF_SEL_tcp_dispatcher_flushes__CI__VI = 0x0000004e,
DB_PERF_SEL_tcp_dispatcher_flushes__SI   = 0x0000004f,
DB_PERF_SEL_tcp_prefetcher_flushes__CI__VI = 0x0000004f,
DB_PERF_SEL_tcp_prefetcher_flushes__SI   = 0x00000050,
DB_PERF_SEL_tcp_preloader_flushes__CI__VI = 0x00000050,
DB_PERF_SEL_tcp_preloader_flushes__SI    = 0x00000051,
DB_PERF_SEL_Depth_Tile_Cache_sends__CI__VI = 0x00000051,
DB_PERF_SEL_Depth_Tile_Cache_sends__SI   = 0x00000052,
DB_PERF_SEL_Depth_Tile_Cache_busy__CI__VI = 0x00000052,
DB_PERF_SEL_Depth_Tile_Cache_busy__SI    = 0x00000053,
DB_PERF_SEL_Depth_Tile_Cache_starves__CI__VI = 0x00000053,
DB_PERF_SEL_Depth_Tile_Cache_starves__SI = 0x00000054,
DB_PERF_SEL_Depth_Tile_Cache_dtile_locked__CI__VI = 0x00000054,
DB_PERF_SEL_Depth_Tile_Cache_dtile_locked__SI = 0x00000055,
DB_PERF_SEL_Depth_Tile_Cache_alloc_stall__CI__VI = 0x00000055,
DB_PERF_SEL_Depth_Tile_Cache_alloc_stall__SI = 0x00000056,
DB_PERF_SEL_Depth_Tile_Cache_misses__CI__VI = 0x00000056,
DB_PERF_SEL_Depth_Tile_Cache_misses__SI  = 0x00000057,
DB_PERF_SEL_Depth_Tile_Cache_hits__CI__VI = 0x00000057,
DB_PERF_SEL_Depth_Tile_Cache_hits__SI    = 0x00000058,
DB_PERF_SEL_Depth_Tile_Cache_flushes__CI__VI = 0x00000058,
DB_PERF_SEL_Depth_Tile_Cache_flushes__SI = 0x00000059,
DB_PERF_SEL_Depth_Tile_Cache_noop_tile__CI__VI = 0x00000059,
DB_PERF_SEL_Depth_Tile_Cache_noop_tile__SI = 0x0000005a,
DB_PERF_SEL_Depth_Tile_Cache_detailed_noop__CI__VI = 0x0000005a,
DB_PERF_SEL_Depth_Tile_Cache_detailed_noop__SI = 0x0000005b,
DB_PERF_SEL_Depth_Tile_Cache_event__CI__VI = 0x0000005b,
DB_PERF_SEL_Depth_Tile_Cache_event__SI   = 0x0000005c,
DB_PERF_SEL_Depth_Tile_Cache_tile_frees__CI__VI = 0x0000005c,
DB_PERF_SEL_Depth_Tile_Cache_tile_frees__SI = 0x0000005d,
DB_PERF_SEL_Depth_Tile_Cache_data_frees__CI__VI = 0x0000005d,
DB_PERF_SEL_Depth_Tile_Cache_data_frees__SI = 0x0000005e,
DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve__CI__VI = 0x0000005e,
DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve__SI = 0x0000005f,
DB_PERF_SEL_Stencil_Cache_misses__CI__VI = 0x0000005f,
DB_PERF_SEL_Stencil_Cache_misses__SI     = 0x00000060,
DB_PERF_SEL_Stencil_Cache_hits__CI__VI   = 0x00000060,
DB_PERF_SEL_Stencil_Cache_hits__SI       = 0x00000061,
DB_PERF_SEL_Stencil_Cache_flushes__CI__VI = 0x00000061,
DB_PERF_SEL_Stencil_Cache_flushes__SI    = 0x00000062,
DB_PERF_SEL_Stencil_Cache_starves__CI__VI = 0x00000062,
DB_PERF_SEL_Stencil_Cache_starves__SI    = 0x00000063,
DB_PERF_SEL_Stencil_Cache_frees__CI__VI  = 0x00000063,
DB_PERF_SEL_Stencil_Cache_frees__SI      = 0x00000064,
DB_PERF_SEL_Z_Cache_separate_Z_misses__CI__VI = 0x00000064,
DB_PERF_SEL_Z_Cache_separate_Z_misses__SI = 0x00000065,
DB_PERF_SEL_Z_Cache_separate_Z_hits__CI__VI = 0x00000065,
DB_PERF_SEL_Z_Cache_separate_Z_hits__SI  = 0x00000066,
DB_PERF_SEL_Z_Cache_separate_Z_flushes__CI__VI = 0x00000066,
DB_PERF_SEL_Z_Cache_separate_Z_flushes__SI = 0x00000067,
DB_PERF_SEL_Z_Cache_separate_Z_starves__CI__VI = 0x00000067,
DB_PERF_SEL_Z_Cache_separate_Z_starves__SI = 0x00000068,
DB_PERF_SEL_Z_Cache_pmask_misses__CI__VI = 0x00000068,
DB_PERF_SEL_Z_Cache_pmask_misses__SI     = 0x00000069,
DB_PERF_SEL_Z_Cache_pmask_hits__CI__VI   = 0x00000069,
DB_PERF_SEL_Z_Cache_pmask_hits__SI       = 0x0000006a,
DB_PERF_SEL_Z_Cache_pmask_flushes__CI__VI = 0x0000006a,
DB_PERF_SEL_Z_Cache_pmask_flushes__SI    = 0x0000006b,
DB_PERF_SEL_Z_Cache_pmask_starves__CI__VI = 0x0000006b,
DB_PERF_SEL_Z_Cache_pmask_starves__SI    = 0x0000006c,
DB_PERF_SEL_Z_Cache_frees__CI__VI        = 0x0000006c,
DB_PERF_SEL_Z_Cache_frees__SI            = 0x0000006d,
DB_PERF_SEL_Plane_Cache_misses__CI__VI   = 0x0000006d,
DB_PERF_SEL_Plane_Cache_misses__SI       = 0x0000006e,
DB_PERF_SEL_Plane_Cache_hits__CI__VI     = 0x0000006e,
DB_PERF_SEL_Plane_Cache_hits__SI         = 0x0000006f,
DB_PERF_SEL_Plane_Cache_flushes__CI__VI  = 0x0000006f,
DB_PERF_SEL_Plane_Cache_flushes__SI      = 0x00000070,
DB_PERF_SEL_Plane_Cache_starves__CI__VI  = 0x00000070,
DB_PERF_SEL_Plane_Cache_starves__SI      = 0x00000071,
DB_PERF_SEL_Plane_Cache_frees__CI__VI    = 0x00000071,
DB_PERF_SEL_Plane_Cache_frees__SI        = 0x00000072,
DB_PERF_SEL_flush_expanded_stencil__CI__VI = 0x00000072,
DB_PERF_SEL_flush_expanded_stencil__SI   = 0x00000073,
DB_PERF_SEL_flush_compressed_stencil__CI__VI = 0x00000073,
DB_PERF_SEL_flush_compressed_stencil__SI = 0x00000074,
DB_PERF_SEL_flush_single_stencil__CI__VI = 0x00000074,
DB_PERF_SEL_flush_single_stencil__SI     = 0x00000075,
DB_PERF_SEL_planes_flushed__CI__VI       = 0x00000075,
DB_PERF_SEL_planes_flushed__SI           = 0x00000076,
DB_PERF_SEL_flush_1plane__CI__VI         = 0x00000076,
DB_PERF_SEL_flush_1plane__SI             = 0x00000077,
DB_PERF_SEL_flush_2plane__CI__VI         = 0x00000077,
DB_PERF_SEL_flush_2plane__SI             = 0x00000078,
DB_PERF_SEL_flush_3plane__CI__VI         = 0x00000078,
DB_PERF_SEL_flush_3plane__SI             = 0x00000079,
DB_PERF_SEL_flush_4plane__CI__VI         = 0x00000079,
DB_PERF_SEL_flush_4plane__SI             = 0x0000007a,
DB_PERF_SEL_flush_5plane__CI__VI         = 0x0000007a,
DB_PERF_SEL_flush_5plane__SI             = 0x0000007b,
DB_PERF_SEL_flush_6plane__CI__VI         = 0x0000007b,
DB_PERF_SEL_flush_6plane__SI             = 0x0000007c,
DB_PERF_SEL_flush_7plane__CI__VI         = 0x0000007c,
DB_PERF_SEL_flush_7plane__SI             = 0x0000007d,
DB_PERF_SEL_flush_8plane__CI__VI         = 0x0000007d,
DB_PERF_SEL_flush_8plane__SI             = 0x0000007e,
DB_PERF_SEL_flush_9plane__CI__VI         = 0x0000007e,
DB_PERF_SEL_flush_9plane__SI             = 0x0000007f,
DB_PERF_SEL_flush_10plane__CI__VI        = 0x0000007f,
DB_PERF_SEL_flush_10plane__SI            = 0x00000080,
DB_PERF_SEL_flush_11plane__CI__VI        = 0x00000080,
DB_PERF_SEL_flush_11plane__SI            = 0x00000081,
DB_PERF_SEL_flush_12plane__CI__VI        = 0x00000081,
DB_PERF_SEL_flush_12plane__SI            = 0x00000082,
DB_PERF_SEL_flush_13plane__CI__VI        = 0x00000082,
DB_PERF_SEL_flush_13plane__SI            = 0x00000083,
DB_PERF_SEL_flush_14plane__CI__VI        = 0x00000083,
DB_PERF_SEL_flush_14plane__SI            = 0x00000084,
DB_PERF_SEL_flush_15plane__CI__VI        = 0x00000084,
DB_PERF_SEL_flush_15plane__SI            = 0x00000085,
DB_PERF_SEL_flush_16plane__CI__VI        = 0x00000085,
DB_PERF_SEL_flush_16plane__SI            = 0x00000086,
DB_PERF_SEL_flush_expanded_z__CI__VI     = 0x00000086,
DB_PERF_SEL_flush_expanded_z__SI         = 0x00000087,
DB_PERF_SEL_earlyZ_waiting_for_postZ_done__CI__VI = 0x00000087,
DB_PERF_SEL_earlyZ_waiting_for_postZ_done__SI = 0x00000088,
DB_PERF_SEL_reZ_waiting_for_postZ_done__CI__VI = 0x00000088,
DB_PERF_SEL_reZ_waiting_for_postZ_done__SI = 0x00000089,
DB_PERF_SEL_dk_tile_sends__CI__VI        = 0x00000089,
DB_PERF_SEL_dk_tile_sends__SI            = 0x0000008a,
DB_PERF_SEL_dk_tile_busy__CI__VI         = 0x0000008a,
DB_PERF_SEL_dk_tile_busy__SI             = 0x0000008b,
DB_PERF_SEL_dk_tile_quad_starves__CI__VI = 0x0000008b,
DB_PERF_SEL_dk_tile_quad_starves__SI     = 0x0000008c,
DB_PERF_SEL_dk_tile_stalls__CI__VI       = 0x0000008c,
DB_PERF_SEL_dk_tile_stalls__SI           = 0x0000008d,
DB_PERF_SEL_dk_squad_sends__CI__VI       = 0x0000008d,
DB_PERF_SEL_dk_squad_sends__SI           = 0x0000008e,
DB_PERF_SEL_dk_squad_busy__CI__VI        = 0x0000008e,
DB_PERF_SEL_dk_squad_busy__SI            = 0x0000008f,
DB_PERF_SEL_dk_squad_stalls__CI__VI      = 0x0000008f,
DB_PERF_SEL_dk_squad_stalls__SI          = 0x00000090,
DB_PERF_SEL_Op_Pipe_Busy__CI__VI         = 0x00000090,
DB_PERF_SEL_Op_Pipe_Busy__SI             = 0x00000091,
DB_PERF_SEL_Op_Pipe_MC_Read_stall__CI__VI = 0x00000091,
DB_PERF_SEL_Op_Pipe_MC_Read_stall__SI    = 0x00000092,
DB_PERF_SEL_qc_busy__CI__VI              = 0x00000092,
DB_PERF_SEL_qc_busy__SI                  = 0x00000093,
DB_PERF_SEL_qc_xfc__CI__VI               = 0x00000093,
DB_PERF_SEL_qc_xfc__SI                   = 0x00000094,
DB_PERF_SEL_qc_conflicts__CI__VI         = 0x00000094,
DB_PERF_SEL_qc_conflicts__SI             = 0x00000095,
DB_PERF_SEL_qc_full_stall__CI__VI        = 0x00000095,
DB_PERF_SEL_qc_full_stall__SI            = 0x00000096,
DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ__CI__VI = 0x00000096,
DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ__SI = 0x00000097,
DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ__CI__VI = 0x00000097,
DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ__SI = 0x00000098,
DB_PERF_SEL_tsc_insert_summarize_stall__CI__VI = 0x00000098,
DB_PERF_SEL_tsc_insert_summarize_stall__SI = 0x00000099,
DB_PERF_SEL_tl_busy__CI__VI              = 0x00000099,
DB_PERF_SEL_tl_busy__SI                  = 0x0000009a,
DB_PERF_SEL_tl_dtc_read_starved__CI__VI  = 0x0000009a,
DB_PERF_SEL_tl_dtc_read_starved__SI      = 0x0000009b,
DB_PERF_SEL_tl_z_fetch_stall__CI__VI     = 0x0000009b,
DB_PERF_SEL_tl_z_fetch_stall__SI         = 0x0000009c,
DB_PERF_SEL_tl_stencil_stall__CI__VI     = 0x0000009c,
DB_PERF_SEL_tl_stencil_stall__SI         = 0x0000009d,
DB_PERF_SEL_tl_z_decompress_stall__CI__VI = 0x0000009d,
DB_PERF_SEL_tl_z_decompress_stall__SI    = 0x0000009e,
DB_PERF_SEL_tl_stencil_locked_stall__CI__VI = 0x0000009e,
DB_PERF_SEL_tl_stencil_locked_stall__SI  = 0x0000009f,
DB_PERF_SEL_tl_events__CI__VI            = 0x0000009f,
DB_PERF_SEL_tl_events__SI                = 0x000000a0,
DB_PERF_SEL_tl_summarize_squads__CI__VI  = 0x000000a0,
DB_PERF_SEL_tl_summarize_squads__SI      = 0x000000a1,
DB_PERF_SEL_tl_flush_expand_squads__CI__VI = 0x000000a1,
DB_PERF_SEL_tl_flush_expand_squads__SI   = 0x000000a2,
DB_PERF_SEL_tl_expand_squads__CI__VI     = 0x000000a2,
DB_PERF_SEL_tl_expand_squads__SI         = 0x000000a3,
DB_PERF_SEL_tl_preZ_squads__CI__VI       = 0x000000a3,
DB_PERF_SEL_tl_preZ_squads__SI           = 0x000000a4,
DB_PERF_SEL_tl_postZ_squads__CI__VI      = 0x000000a4,
DB_PERF_SEL_tl_postZ_squads__SI          = 0x000000a5,
DB_PERF_SEL_tl_preZ_noop_squads__CI__VI  = 0x000000a5,
DB_PERF_SEL_tl_preZ_noop_squads__SI      = 0x000000a6,
DB_PERF_SEL_tl_postZ_noop_squads__CI__VI = 0x000000a6,
DB_PERF_SEL_tl_postZ_noop_squads__SI     = 0x000000a7,
DB_PERF_SEL_tl_tile_ops__CI__VI          = 0x000000a7,
DB_PERF_SEL_tl_in_xfc__CI__VI            = 0x000000a8,
DB_PERF_SEL_tl_tile_ops__SI              = 0x000000a9,
DB_PERF_SEL_tl_in_single_stencil_expand_stall__CI__VI = 0x000000a9,
DB_PERF_SEL_tl_in_xfc__SI                = 0x000000aa,
DB_PERF_SEL_tl_in_fast_z_stall__CI__VI   = 0x000000aa,
DB_PERF_SEL_tl_in_single_stencil_expand_stall__SI = 0x000000ab,
DB_PERF_SEL_tl_out_xfc__CI__VI           = 0x000000ab,
DB_PERF_SEL_tl_out_squads__CI__VI        = 0x000000ac,
DB_PERF_SEL_tl_in_fast_z_stall__SI       = 0x000000ad,
DB_PERF_SEL_zf_plane_multicycle__CI__VI  = 0x000000ad,
DB_PERF_SEL_tl_out_xfc__SI               = 0x000000ae,
DB_PERF_SEL_PostZ_Samples_passing_Z__CI__VI = 0x000000ae,
DB_PERF_SEL_tl_out_squads__SI            = 0x000000af,
DB_PERF_SEL_PostZ_Samples_failing_Z__CI__VI = 0x000000af,
DB_PERF_SEL_zf_plane_multicycle__SI      = 0x000000b0,
DB_PERF_SEL_PostZ_Samples_failing_S__CI__VI = 0x000000b0,
DB_PERF_SEL_PostZ_Samples_passing_Z__SI  = 0x000000b1,
DB_PERF_SEL_PreZ_Samples_passing_Z__CI__VI = 0x000000b1,
DB_PERF_SEL_PostZ_Samples_failing_Z__SI  = 0x000000b2,
DB_PERF_SEL_PreZ_Samples_failing_Z__CI__VI = 0x000000b2,
DB_PERF_SEL_PostZ_Samples_failing_S__SI  = 0x000000b3,
DB_PERF_SEL_PreZ_Samples_failing_S__CI__VI = 0x000000b3,
DB_PERF_SEL_PreZ_Samples_passing_Z__SI   = 0x000000b4,
DB_PERF_SEL_ts_tc_update_stall__CI__VI   = 0x000000b4,
DB_PERF_SEL_PreZ_Samples_failing_Z__SI   = 0x000000b5,
DB_PERF_SEL_sc_kick_start__CI__VI        = 0x000000b5,
DB_PERF_SEL_PreZ_Samples_failing_S__SI   = 0x000000b6,
DB_PERF_SEL_sc_kick_end__CI__VI          = 0x000000b6,
DB_PERF_SEL_ts_tc_update_stall__SI       = 0x000000b7,
DB_PERF_SEL_clock_reg_active__CI__VI     = 0x000000b7,
DB_PERF_SEL_sc_kick_start__SI            = 0x000000b8,
DB_PERF_SEL_clock_main_active__CI__VI    = 0x000000b8,
DB_PERF_SEL_sc_kick_end__SI              = 0x000000b9,
DB_PERF_SEL_clock_mem_export_active__CI__VI = 0x000000b9,
DB_PERF_SEL_clock_reg_active__SI         = 0x000000ba,
DB_PERF_SEL_esr_ps_out_busy__CI__VI      = 0x000000ba,
DB_PERF_SEL_clock_main_active__SI        = 0x000000bb,
DB_PERF_SEL_esr_ps_lqf_busy__CI__VI      = 0x000000bb,
DB_PERF_SEL_clock_mem_export_active__SI  = 0x000000bc,
DB_PERF_SEL_esr_ps_lqf_stall__CI__VI     = 0x000000bc,
DB_PERF_SEL_esr_ps_out_busy__SI          = 0x000000bd,
DB_PERF_SEL_etr_out_send__CI__VI         = 0x000000bd,
DB_PERF_SEL_esr_ps_lqf_busy__SI          = 0x000000be,
DB_PERF_SEL_etr_out_busy__CI__VI         = 0x000000be,
DB_PERF_SEL_esr_ps_lqf_stall__SI         = 0x000000bf,
DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall__CI__VI = 0x000000bf,
DB_PERF_SEL_etr_out_send__SI             = 0x000000c0,
DB_PERF_SEL_etr_out_cb_tile_stall__CI__VI = 0x000000c0,
DB_PERF_SEL_etr_out_busy__SI             = 0x000000c1,
DB_PERF_SEL_etr_out_esr_stall__CI__VI    = 0x000000c1,
DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall__SI = 0x000000c2,
DB_PERF_SEL_esr_ps_sqq_busy__CI__VI      = 0x000000c2,
DB_PERF_SEL_etr_out_cb_tile_stall__SI    = 0x000000c3,
DB_PERF_SEL_esr_ps_sqq_stall__CI__VI     = 0x000000c3,
DB_PERF_SEL_etr_out_esr_stall__SI        = 0x000000c4,
DB_PERF_SEL_esr_eot_fwd_busy__CI__VI     = 0x000000c4,
DB_PERF_SEL_esr_ps_sqq_busy__SI          = 0x000000c5,
DB_PERF_SEL_esr_eot_fwd_holding_squad__CI__VI = 0x000000c5,
DB_PERF_SEL_esr_ps_sqq_stall__SI         = 0x000000c6,
DB_PERF_SEL_esr_eot_fwd_forward__CI__VI  = 0x000000c6,
DB_PERF_SEL_esr_eot_fwd_busy__SI         = 0x000000c7,
DB_PERF_SEL_esr_sqq_zi_busy__CI__VI      = 0x000000c7,
DB_PERF_SEL_esr_eot_fwd_holding_squad__SI = 0x000000c8,
DB_PERF_SEL_esr_sqq_zi_stall__CI__VI     = 0x000000c8,
DB_PERF_SEL_esr_eot_fwd_forward__SI      = 0x000000c9,
DB_PERF_SEL_postzl_sq_pt_busy__CI__VI    = 0x000000c9,
DB_PERF_SEL_esr_sqq_zi_busy__SI          = 0x000000ca,
DB_PERF_SEL_postzl_sq_pt_stall__CI__VI   = 0x000000ca,
DB_PERF_SEL_esr_sqq_zi_stall__SI         = 0x000000cb,
DB_PERF_SEL_postzl_se_busy__CI__VI       = 0x000000cb,
DB_PERF_SEL_postzl_sq_pt_busy__SI        = 0x000000cc,
DB_PERF_SEL_postzl_se_stall__CI__VI      = 0x000000cc,
DB_PERF_SEL_postzl_sq_pt_stall__SI       = 0x000000cd,
DB_PERF_SEL_postzl_partial_launch__CI__VI = 0x000000cd,
DB_PERF_SEL_postzl_se_busy__SI           = 0x000000ce,
DB_PERF_SEL_postzl_full_launch__CI__VI   = 0x000000ce,
DB_PERF_SEL_postzl_se_stall__SI          = 0x000000cf,
DB_PERF_SEL_postzl_partial_waiting__CI__VI = 0x000000cf,
DB_PERF_SEL_postzl_partial_launch__SI    = 0x000000d0,
DB_PERF_SEL_postzl_tile_mem_stall__CI__VI = 0x000000d0,
DB_PERF_SEL_postzl_full_launch__SI       = 0x000000d1,
DB_PERF_SEL_postzl_tile_init_stall__CI__VI = 0x000000d1,
DB_PERF_SEL_postzl_partial_waiting__SI   = 0x000000d2,
DB_PEFF_SEL_prezl_tile_mem_stall__CI__VI = 0x000000d2,
DB_PERF_SEL_postzl_tile_mem_stall__SI    = 0x000000d3,
DB_PERF_SEL_prezl_tile_init_stall__CI__VI = 0x000000d3,
DB_PERF_SEL_postzl_tile_init_stall__SI   = 0x000000d4,
DB_PERF_SEL_dtt_sm_clash_stall__CI__VI   = 0x000000d4,
DB_PEFF_SEL_prezl_tile_mem_stall__SI     = 0x000000d5,
DB_PERF_SEL_dtt_sm_slot_stall__CI__VI    = 0x000000d5,
DB_PERF_SEL_prezl_tile_init_stall__SI    = 0x000000d6,
DB_PERF_SEL_dtt_sm_miss_stall__CI__VI    = 0x000000d6,
DB_PERF_SEL_dtt_sm_clash_stall__SI       = 0x000000d7,
DB_PERF_SEL_mi_rdreq_busy__CI__VI        = 0x000000d7,
DB_PERF_SEL_dtt_sm_slot_stall__SI        = 0x000000d8,
DB_PERF_SEL_mi_rdreq_stall__CI__VI       = 0x000000d8,
DB_PERF_SEL_dtt_sm_miss_stall__SI        = 0x000000d9,
DB_PERF_SEL_mi_wrreq_busy__CI__VI        = 0x000000d9,
DB_PERF_SEL_mi_rdreq_busy__SI            = 0x000000da,
DB_PERF_SEL_mi_wrreq_stall__CI__VI       = 0x000000da,
DB_PERF_SEL_mi_rdreq_stall__SI           = 0x000000db,
DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop__CI__VI = 0x000000db,
DB_PERF_SEL_mi_wrreq_busy__SI            = 0x000000dc,
DB_PERF_SEL_dkg_tile_rate_tile__CI__VI   = 0x000000dc,
DB_PERF_SEL_mi_wrreq_stall__SI           = 0x000000dd,
DB_PERF_SEL_prezl_src_in_sends__CI__VI   = 0x000000dd,
DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop__SI = 0x000000de,
DB_PERF_SEL_prezl_src_in_stall__CI__VI   = 0x000000de,
DB_PERF_SEL_dkg_tile_rate_tile__SI       = 0x000000df,
DB_PERF_SEL_prezl_src_in_squads__CI__VI  = 0x000000df,
DB_PERF_SEL_prezl_src_in_sends__SI       = 0x000000e0,
DB_PERF_SEL_prezl_src_in_squads_unrolled__CI__VI = 0x000000e0,
DB_PERF_SEL_prezl_src_in_stall__SI       = 0x000000e1,
DB_PERF_SEL_prezl_src_in_tile_rate__CI__VI = 0x000000e1,
DB_PERF_SEL_prezl_src_in_squads__SI      = 0x000000e2,
DB_PERF_SEL_prezl_src_in_tile_rate_unrolled__CI__VI = 0x000000e2,
DB_PERF_SEL_prezl_src_in_squads_unrolled__SI = 0x000000e3,
DB_PERF_SEL_prezl_src_out_stall__CI__VI  = 0x000000e3,
DB_PERF_SEL_prezl_src_in_tile_rate__SI   = 0x000000e4,
DB_PERF_SEL_postzl_src_in_sends__CI__VI  = 0x000000e4,
DB_PERF_SEL_prezl_src_in_tile_rate_unrolled__SI = 0x000000e5,
DB_PERF_SEL_postzl_src_in_stall__CI__VI  = 0x000000e5,
DB_PERF_SEL_prezl_src_out_stall__SI      = 0x000000e6,
DB_PERF_SEL_postzl_src_in_squads__CI__VI = 0x000000e6,
DB_PERF_SEL_postzl_src_in_sends__SI      = 0x000000e7,
DB_PERF_SEL_postzl_src_in_squads_unrolled__CI__VI = 0x000000e7,
DB_PERF_SEL_postzl_src_in_stall__SI      = 0x000000e8,
DB_PERF_SEL_postzl_src_in_tile_rate__CI__VI = 0x000000e8,
DB_PERF_SEL_postzl_src_in_squads__SI     = 0x000000e9,
DB_PERF_SEL_postzl_src_in_tile_rate_unrolled__CI__VI = 0x000000e9,
DB_PERF_SEL_postzl_src_in_squads_unrolled__SI = 0x000000ea,
DB_PERF_SEL_postzl_src_out_stall__CI__VI = 0x000000ea,
DB_PERF_SEL_postzl_src_in_tile_rate__SI  = 0x000000eb,
DB_PERF_SEL_esr_ps_src_in_sends__CI__VI  = 0x000000eb,
DB_PERF_SEL_postzl_src_in_tile_rate_unrolled__SI = 0x000000ec,
DB_PERF_SEL_esr_ps_src_in_stall__CI__VI  = 0x000000ec,
DB_PERF_SEL_postzl_src_out_stall__SI     = 0x000000ed,
DB_PERF_SEL_esr_ps_src_in_squads__CI__VI = 0x000000ed,
DB_PERF_SEL_esr_ps_src_in_sends__SI      = 0x000000ee,
DB_PERF_SEL_esr_ps_src_in_squads_unrolled__CI__VI = 0x000000ee,
DB_PERF_SEL_esr_ps_src_in_stall__SI      = 0x000000ef,
DB_PERF_SEL_esr_ps_src_in_tile_rate__CI__VI = 0x000000ef,
DB_PERF_SEL_esr_ps_src_in_squads__SI     = 0x000000f0,
DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled__CI__VI = 0x000000f0,
DB_PERF_SEL_esr_ps_src_in_squads_unrolled__SI = 0x000000f1,
DB_PERF_SEL_esr_ps_src_in_tile_rate__SI  = 0x000000f2,
DB_PERF_SEL_esr_ps_src_out_stall__CI__VI = 0x000000f2,
DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled__SI = 0x000000f3,
DB_PERF_SEL_depth_bounds_qtiles_culled__CI__VI = 0x000000f3,
DB_PERF_SEL_PreZ_Samples_failing_DB__CI__VI = 0x000000f4,
DB_PERF_SEL_esr_ps_src_out_stall__SI     = 0x000000f5,
DB_PERF_SEL_PostZ_Samples_failing_DB__CI__VI = 0x000000f5,
DB_PERF_SEL_depth_bounds_qtiles_culled__SI = 0x000000f6,
DB_PERF_SEL_flush_compressed__CI__VI     = 0x000000f6,
DB_PERF_SEL_PreZ_Samples_failing_DB__SI  = 0x000000f7,
DB_PERF_SEL_flush_plane_le4__CI__VI      = 0x000000f7,
DB_PERF_SEL_PostZ_Samples_failing_DB__SI = 0x000000f8,
DB_PERF_SEL_tiles_z_fully_summarized__CI__VI = 0x000000f8,
DB_PERF_SEL_tiles_stencil_fully_summarized__CI__VI = 0x000000f9,
DB_PERF_SEL_tiles_z_clear_on_expclear__CI__VI = 0x000000fa,
DB_PERF_SEL_tiles_s_clear_on_expclear__CI__VI = 0x000000fb,
DB_PERF_SEL_tiles_decomp_on_expclear__CI__VI = 0x000000fc,
DB_PERF_SEL_tiles_compressed_to_decompressed__CI__VI = 0x000000fd,
DB_PERF_SEL_Op_Pipe_Prez_Busy__CI__VI    = 0x000000fe,
DB_PERF_SEL_Op_Pipe_Postz_Busy__CI__VI   = 0x000000ff,
DB_PERF_SEL_di_dt_stall__CI__VI          = 0x00000100,
} PerfCounter_Vals;

typedef enum PipeConfig {
ADDR_SURF_P2                             = 0x00000000,
ADDR_SURF_P2_RESERVED0                   = 0x00000001,
ADDR_SURF_P2_RESERVED1                   = 0x00000002,
ADDR_SURF_P2_RESERVED2                   = 0x00000003,
ADDR_SURF_P4_8x16                        = 0x00000004,
ADDR_SURF_P4_16x16                       = 0x00000005,
ADDR_SURF_P4_16x32                       = 0x00000006,
ADDR_SURF_P4_32x32                       = 0x00000007,
ADDR_SURF_P8_16x16_8x16                  = 0x00000008,
ADDR_SURF_P8_16x32_8x16                  = 0x00000009,
ADDR_SURF_P8_32x32_8x16                  = 0x0000000a,
ADDR_SURF_P8_16x32_16x16                 = 0x0000000b,
ADDR_SURF_P8_32x32_16x16                 = 0x0000000c,
ADDR_SURF_P8_32x32_16x32                 = 0x0000000d,
ADDR_SURF_P8_32x64_32x32                 = 0x0000000e,
ADDR_SURF_P8_RESERVED0__CI__VI           = 0x0000000f,
ADDR_SURF_P16_32x32_8x16__CI__VI         = 0x00000010,
ADDR_SURF_P16_32x32_16x16__CI__VI        = 0x00000011,
} PipeConfig;

typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
} PipeInterleaveSize;

typedef enum PipeTiling {
CONFIG_1_PIPE                            = 0x00000000,
CONFIG_2_PIPE                            = 0x00000001,
CONFIG_4_PIPE                            = 0x00000002,
CONFIG_8_PIPE                            = 0x00000003,
} PipeTiling;

typedef enum PixelPipeCounterId {
PIXEL_PIPE_OCCLUSION_COUNT_0             = 0x00000000,
PIXEL_PIPE_OCCLUSION_COUNT_1             = 0x00000001,
PIXEL_PIPE_OCCLUSION_COUNT_2             = 0x00000002,
PIXEL_PIPE_OCCLUSION_COUNT_3             = 0x00000003,
PIXEL_PIPE_SCREEN_MIN_EXTENTS_0__VI      = 0x00000004,
PIXEL_PIPE_SCREEN_MAX_EXTENTS_0__VI      = 0x00000005,
PIXEL_PIPE_SCREEN_MIN_EXTENTS_1__VI      = 0x00000006,
PIXEL_PIPE_SCREEN_MAX_EXTENTS_1__VI      = 0x00000007,
} PixelPipeCounterId;

typedef enum PixelPipeStride {
PIXEL_PIPE_STRIDE_32_BITS                = 0x00000000,
PIXEL_PIPE_STRIDE_64_BITS                = 0x00000001,
PIXEL_PIPE_STRIDE_128_BITS               = 0x00000002,
PIXEL_PIPE_STRIDE_256_BITS               = 0x00000003,
} PixelPipeStride;

typedef enum PkrMap {
RASTER_CONFIG_PKR_MAP_0                  = 0x00000000,
RASTER_CONFIG_PKR_MAP_1                  = 0x00000001,
RASTER_CONFIG_PKR_MAP_2                  = 0x00000002,
RASTER_CONFIG_PKR_MAP_3                  = 0x00000003,
} PkrMap;

typedef enum PkrXsel {
RASTER_CONFIG_PKR_XSEL_0                 = 0x00000000,
RASTER_CONFIG_PKR_XSEL_1                 = 0x00000001,
RASTER_CONFIG_PKR_XSEL_2                 = 0x00000002,
RASTER_CONFIG_PKR_XSEL_3                 = 0x00000003,
} PkrXsel;

typedef enum PkrXsel2 {
RASTER_CONFIG_PKR_XSEL2_0                = 0x00000000,
RASTER_CONFIG_PKR_XSEL2_1                = 0x00000001,
RASTER_CONFIG_PKR_XSEL2_2                = 0x00000002,
RASTER_CONFIG_PKR_XSEL2_3                = 0x00000003,
} PkrXsel2;

typedef enum PkrYsel {
RASTER_CONFIG_PKR_YSEL_0                 = 0x00000000,
RASTER_CONFIG_PKR_YSEL_1                 = 0x00000001,
RASTER_CONFIG_PKR_YSEL_2                 = 0x00000002,
RASTER_CONFIG_PKR_YSEL_3                 = 0x00000003,
} PkrYsel;

typedef enum QuadExportFormat {
EXPORT_UNUSED                            = 0x00000000,
EXPORT_32_R                              = 0x00000001,
EXPORT_32_GR                             = 0x00000002,
EXPORT_32_AR                             = 0x00000003,
EXPORT_FP16_ABGR                         = 0x00000004,
EXPORT_UNSIGNED16_ABGR                   = 0x00000005,
EXPORT_SIGNED16_ABGR                     = 0x00000006,
EXPORT_32_ABGR                           = 0x00000007,
} QuadExportFormat;

typedef enum QuadExportFormatOld {
EXPORT_4P_32BPC_ABGR                     = 0x00000000,
EXPORT_4P_16BPC_ABGR                     = 0x00000001,
EXPORT_4P_32BPC_GR                       = 0x00000002,
EXPORT_4P_32BPC_AR                       = 0x00000003,
EXPORT_2P_32BPC_ABGR                     = 0x00000004,
EXPORT_8P_32BPC_R                        = 0x00000005,
} QuadExportFormatOld;

typedef enum RbMap {
RASTER_CONFIG_RB_MAP_0                   = 0x00000000,
RASTER_CONFIG_RB_MAP_1                   = 0x00000001,
RASTER_CONFIG_RB_MAP_2                   = 0x00000002,
RASTER_CONFIG_RB_MAP_3                   = 0x00000003,
} RbMap;

typedef enum RbXsel {
RASTER_CONFIG_RB_XSEL_0                  = 0x00000000,
RASTER_CONFIG_RB_XSEL_1                  = 0x00000001,
} RbXsel;

typedef enum RbXsel2 {
RASTER_CONFIG_RB_XSEL2_0                 = 0x00000000,
RASTER_CONFIG_RB_XSEL2_1                 = 0x00000001,
RASTER_CONFIG_RB_XSEL2_2                 = 0x00000002,
RASTER_CONFIG_RB_XSEL2_3                 = 0x00000003,
} RbXsel2;

typedef enum RbYsel {
RASTER_CONFIG_RB_YSEL_0                  = 0x00000000,
RASTER_CONFIG_RB_YSEL_1                  = 0x00000001,
} RbYsel;

typedef enum ReadSize {
READ_256_BITS                            = 0x00000000,
READ_512_BITS                            = 0x00000001,
} ReadSize;

typedef enum RingCounterControl {
COUNTER_RING_SPLIT                       = 0x00000000,
COUNTER_RING_0                           = 0x00000001,
COUNTER_RING_1                           = 0x00000002,
} RingCounterControl;

typedef enum RoundMode {
ROUND_BY_HALF                            = 0x00000000,
ROUND_TRUNCATE                           = 0x00000001,
} RoundMode;

typedef enum RowSize {
ADDR_CONFIG_1KB_ROW                      = 0x00000000,
ADDR_CONFIG_2KB_ROW                      = 0x00000001,
ADDR_CONFIG_4KB_ROW                      = 0x00000002,
} RowSize;

typedef enum RowTiling {
CONFIG_1KB_ROW                           = 0x00000000,
CONFIG_2KB_ROW                           = 0x00000001,
CONFIG_4KB_ROW                           = 0x00000002,
CONFIG_8KB_ROW                           = 0x00000003,
CONFIG_1KB_ROW_OPT                       = 0x00000004,
CONFIG_2KB_ROW_OPT                       = 0x00000005,
CONFIG_4KB_ROW_OPT                       = 0x00000006,
CONFIG_8KB_ROW_OPT                       = 0x00000007,
} RowTiling;

typedef enum SC_PERFCNT_SEL {
SC_SRPS_WINDOW_VALID                     = 0x00000000,
SC_PSSW_WINDOW_VALID                     = 0x00000001,
SC_TPQZ_WINDOW_VALID                     = 0x00000002,
SC_QZQP_WINDOW_VALID                     = 0x00000003,
SC_TRPK_WINDOW_VALID                     = 0x00000004,
SC_SRPS_WINDOW_VALID_BUSY                = 0x00000005,
SC_PSSW_WINDOW_VALID_BUSY                = 0x00000006,
SC_TPQZ_WINDOW_VALID_BUSY                = 0x00000007,
SC_QZQP_WINDOW_VALID_BUSY                = 0x00000008,
SC_TRPK_WINDOW_VALID_BUSY                = 0x00000009,
SC_STARVED_BY_PA                         = 0x0000000a,
SC_STALLED_BY_PRIMFIFO                   = 0x0000000b,
SC_STALLED_BY_DB_TILE                    = 0x0000000c,
SC_STARVED_BY_DB_TILE                    = 0x0000000d,
SC_STALLED_BY_TILEORDERFIFO              = 0x0000000e,
SC_STALLED_BY_TILEFIFO                   = 0x0000000f,
SC_STALLED_BY_DB_QUAD                    = 0x00000010,
SC_STARVED_BY_DB_QUAD                    = 0x00000011,
SC_STALLED_BY_QUADFIFO                   = 0x00000012,
SC_STALLED_BY_BCI                        = 0x00000013,
SC_STALLED_BY_SPI                        = 0x00000014,
SC_SCISSOR_DISCARD                       = 0x00000015,
SC_BB_DISCARD                            = 0x00000016,
SC_SUPERTILE_COUNT                       = 0x00000017,
SC_SUPERTILE_PER_PRIM_H0                 = 0x00000018,
SC_SUPERTILE_PER_PRIM_H1                 = 0x00000019,
SC_SUPERTILE_PER_PRIM_H2                 = 0x0000001a,
SC_SUPERTILE_PER_PRIM_H3                 = 0x0000001b,
SC_SUPERTILE_PER_PRIM_H4                 = 0x0000001c,
SC_SUPERTILE_PER_PRIM_H5                 = 0x0000001d,
SC_SUPERTILE_PER_PRIM_H6                 = 0x0000001e,
SC_SUPERTILE_PER_PRIM_H7                 = 0x0000001f,
SC_SUPERTILE_PER_PRIM_H8                 = 0x00000020,
SC_SUPERTILE_PER_PRIM_H9                 = 0x00000021,
SC_SUPERTILE_PER_PRIM_H10                = 0x00000022,
SC_SUPERTILE_PER_PRIM_H11                = 0x00000023,
SC_SUPERTILE_PER_PRIM_H12                = 0x00000024,
SC_SUPERTILE_PER_PRIM_H13                = 0x00000025,
SC_SUPERTILE_PER_PRIM_H14                = 0x00000026,
SC_SUPERTILE_PER_PRIM_H15                = 0x00000027,
SC_SUPERTILE_PER_PRIM_H16                = 0x00000028,
SC_TILE_PER_PRIM_H0                      = 0x00000029,
SC_TILE_PER_PRIM_H1                      = 0x0000002a,
SC_TILE_PER_PRIM_H2                      = 0x0000002b,
SC_TILE_PER_PRIM_H3                      = 0x0000002c,
SC_TILE_PER_PRIM_H4                      = 0x0000002d,
SC_TILE_PER_PRIM_H5                      = 0x0000002e,
SC_TILE_PER_PRIM_H6                      = 0x0000002f,
SC_TILE_PER_PRIM_H7                      = 0x00000030,
SC_TILE_PER_PRIM_H8                      = 0x00000031,
SC_TILE_PER_PRIM_H9                      = 0x00000032,
SC_TILE_PER_PRIM_H10                     = 0x00000033,
SC_TILE_PER_PRIM_H11                     = 0x00000034,
SC_TILE_PER_PRIM_H12                     = 0x00000035,
SC_TILE_PER_PRIM_H13                     = 0x00000036,
SC_TILE_PER_PRIM_H14                     = 0x00000037,
SC_TILE_PER_PRIM_H15                     = 0x00000038,
SC_TILE_PER_PRIM_H16                     = 0x00000039,
SC_TILE_PER_SUPERTILE_H0                 = 0x0000003a,
SC_TILE_PER_SUPERTILE_H1                 = 0x0000003b,
SC_TILE_PER_SUPERTILE_H2                 = 0x0000003c,
SC_TILE_PER_SUPERTILE_H3                 = 0x0000003d,
SC_TILE_PER_SUPERTILE_H4                 = 0x0000003e,
SC_TILE_PER_SUPERTILE_H5                 = 0x0000003f,
SC_TILE_PER_SUPERTILE_H6                 = 0x00000040,
SC_TILE_PER_SUPERTILE_H7                 = 0x00000041,
SC_TILE_PER_SUPERTILE_H8                 = 0x00000042,
SC_TILE_PER_SUPERTILE_H9                 = 0x00000043,
SC_TILE_PER_SUPERTILE_H10                = 0x00000044,
SC_TILE_PER_SUPERTILE_H11                = 0x00000045,
SC_TILE_PER_SUPERTILE_H12                = 0x00000046,
SC_TILE_PER_SUPERTILE_H13                = 0x00000047,
SC_TILE_PER_SUPERTILE_H14                = 0x00000048,
SC_TILE_PER_SUPERTILE_H15                = 0x00000049,
SC_TILE_PER_SUPERTILE_H16                = 0x0000004a,
SC_TILE_PICKED_H1                        = 0x0000004b,
SC_TILE_PICKED_H2                        = 0x0000004c,
SC_TILE_PICKED_H3                        = 0x0000004d,
SC_TILE_PICKED_H4                        = 0x0000004e,
SC_QZ0_MULTI_GPU_TILE_DISCARD            = 0x0000004f,
SC_QZ1_MULTI_GPU_TILE_DISCARD            = 0x00000050,
SC_QZ2_MULTI_GPU_TILE_DISCARD            = 0x00000051,
SC_QZ3_MULTI_GPU_TILE_DISCARD            = 0x00000052,
SC_QZ0_TILE_COUNT                        = 0x00000053,
SC_QZ1_TILE_COUNT                        = 0x00000054,
SC_QZ2_TILE_COUNT                        = 0x00000055,
SC_QZ3_TILE_COUNT                        = 0x00000056,
SC_QZ0_TILE_COVERED_COUNT                = 0x00000057,
SC_QZ1_TILE_COVERED_COUNT                = 0x00000058,
SC_QZ2_TILE_COVERED_COUNT                = 0x00000059,
SC_QZ3_TILE_COVERED_COUNT                = 0x0000005a,
SC_QZ0_TILE_NOT_COVERED_COUNT            = 0x0000005b,
SC_QZ1_TILE_NOT_COVERED_COUNT            = 0x0000005c,
SC_QZ2_TILE_NOT_COVERED_COUNT            = 0x0000005d,
SC_QZ3_TILE_NOT_COVERED_COUNT            = 0x0000005e,
SC_QZ0_QUAD_PER_TILE_H0                  = 0x0000005f,
SC_QZ0_QUAD_PER_TILE_H1                  = 0x00000060,
SC_QZ0_QUAD_PER_TILE_H2                  = 0x00000061,
SC_QZ0_QUAD_PER_TILE_H3                  = 0x00000062,
SC_QZ0_QUAD_PER_TILE_H4                  = 0x00000063,
SC_QZ0_QUAD_PER_TILE_H5                  = 0x00000064,
SC_QZ0_QUAD_PER_TILE_H6                  = 0x00000065,
SC_QZ0_QUAD_PER_TILE_H7                  = 0x00000066,
SC_QZ0_QUAD_PER_TILE_H8                  = 0x00000067,
SC_QZ0_QUAD_PER_TILE_H9                  = 0x00000068,
SC_QZ0_QUAD_PER_TILE_H10                 = 0x00000069,
SC_QZ0_QUAD_PER_TILE_H11                 = 0x0000006a,
SC_QZ0_QUAD_PER_TILE_H12                 = 0x0000006b,
SC_QZ0_QUAD_PER_TILE_H13                 = 0x0000006c,
SC_QZ0_QUAD_PER_TILE_H14                 = 0x0000006d,
SC_QZ0_QUAD_PER_TILE_H15                 = 0x0000006e,
SC_QZ0_QUAD_PER_TILE_H16                 = 0x0000006f,
SC_QZ1_QUAD_PER_TILE_H0                  = 0x00000070,
SC_QZ1_QUAD_PER_TILE_H1                  = 0x00000071,
SC_QZ1_QUAD_PER_TILE_H2                  = 0x00000072,
SC_QZ1_QUAD_PER_TILE_H3                  = 0x00000073,
SC_QZ1_QUAD_PER_TILE_H4                  = 0x00000074,
SC_QZ1_QUAD_PER_TILE_H5                  = 0x00000075,
SC_QZ1_QUAD_PER_TILE_H6                  = 0x00000076,
SC_QZ1_QUAD_PER_TILE_H7                  = 0x00000077,
SC_QZ1_QUAD_PER_TILE_H8                  = 0x00000078,
SC_QZ1_QUAD_PER_TILE_H9                  = 0x00000079,
SC_QZ1_QUAD_PER_TILE_H10                 = 0x0000007a,
SC_QZ1_QUAD_PER_TILE_H11                 = 0x0000007b,
SC_QZ1_QUAD_PER_TILE_H12                 = 0x0000007c,
SC_QZ1_QUAD_PER_TILE_H13                 = 0x0000007d,
SC_QZ1_QUAD_PER_TILE_H14                 = 0x0000007e,
SC_QZ1_QUAD_PER_TILE_H15                 = 0x0000007f,
SC_QZ1_QUAD_PER_TILE_H16                 = 0x00000080,
SC_QZ2_QUAD_PER_TILE_H0                  = 0x00000081,
SC_QZ2_QUAD_PER_TILE_H1                  = 0x00000082,
SC_QZ2_QUAD_PER_TILE_H2                  = 0x00000083,
SC_QZ2_QUAD_PER_TILE_H3                  = 0x00000084,
SC_QZ2_QUAD_PER_TILE_H4                  = 0x00000085,
SC_QZ2_QUAD_PER_TILE_H5                  = 0x00000086,
SC_QZ2_QUAD_PER_TILE_H6                  = 0x00000087,
SC_QZ2_QUAD_PER_TILE_H7                  = 0x00000088,
SC_QZ2_QUAD_PER_TILE_H8                  = 0x00000089,
SC_QZ2_QUAD_PER_TILE_H9                  = 0x0000008a,
SC_QZ2_QUAD_PER_TILE_H10                 = 0x0000008b,
SC_QZ2_QUAD_PER_TILE_H11                 = 0x0000008c,
SC_QZ2_QUAD_PER_TILE_H12                 = 0x0000008d,
SC_QZ2_QUAD_PER_TILE_H13                 = 0x0000008e,
SC_QZ2_QUAD_PER_TILE_H14                 = 0x0000008f,
SC_QZ2_QUAD_PER_TILE_H15                 = 0x00000090,
SC_QZ2_QUAD_PER_TILE_H16                 = 0x00000091,
SC_QZ3_QUAD_PER_TILE_H0                  = 0x00000092,
SC_QZ3_QUAD_PER_TILE_H1                  = 0x00000093,
SC_QZ3_QUAD_PER_TILE_H2                  = 0x00000094,
SC_QZ3_QUAD_PER_TILE_H3                  = 0x00000095,
SC_QZ3_QUAD_PER_TILE_H4                  = 0x00000096,
SC_QZ3_QUAD_PER_TILE_H5                  = 0x00000097,
SC_QZ3_QUAD_PER_TILE_H6                  = 0x00000098,
SC_QZ3_QUAD_PER_TILE_H7                  = 0x00000099,
SC_QZ3_QUAD_PER_TILE_H8                  = 0x0000009a,
SC_QZ3_QUAD_PER_TILE_H9                  = 0x0000009b,
SC_QZ3_QUAD_PER_TILE_H10                 = 0x0000009c,
SC_QZ3_QUAD_PER_TILE_H11                 = 0x0000009d,
SC_QZ3_QUAD_PER_TILE_H12                 = 0x0000009e,
SC_QZ3_QUAD_PER_TILE_H13                 = 0x0000009f,
SC_QZ3_QUAD_PER_TILE_H14                 = 0x000000a0,
SC_QZ3_QUAD_PER_TILE_H15                 = 0x000000a1,
SC_QZ3_QUAD_PER_TILE_H16                 = 0x000000a2,
SC_QZ0_QUAD_COUNT                        = 0x000000a3,
SC_QZ1_QUAD_COUNT                        = 0x000000a4,
SC_QZ2_QUAD_COUNT                        = 0x000000a5,
SC_QZ3_QUAD_COUNT                        = 0x000000a6,
SC_P0_HIZ_TILE_COUNT                     = 0x000000a7,
SC_P1_HIZ_TILE_COUNT                     = 0x000000a8,
SC_P2_HIZ_TILE_COUNT                     = 0x000000a9,
SC_P3_HIZ_TILE_COUNT                     = 0x000000aa,
SC_P0_HIZ_QUAD_PER_TILE_H0               = 0x000000ab,
SC_P0_HIZ_QUAD_PER_TILE_H1               = 0x000000ac,
SC_P0_HIZ_QUAD_PER_TILE_H2               = 0x000000ad,
SC_P0_HIZ_QUAD_PER_TILE_H3               = 0x000000ae,
SC_P0_HIZ_QUAD_PER_TILE_H4               = 0x000000af,
SC_P0_HIZ_QUAD_PER_TILE_H5               = 0x000000b0,
SC_P0_HIZ_QUAD_PER_TILE_H6               = 0x000000b1,
SC_P0_HIZ_QUAD_PER_TILE_H7               = 0x000000b2,
SC_P0_HIZ_QUAD_PER_TILE_H8               = 0x000000b3,
SC_P0_HIZ_QUAD_PER_TILE_H9               = 0x000000b4,
SC_P0_HIZ_QUAD_PER_TILE_H10              = 0x000000b5,
SC_P0_HIZ_QUAD_PER_TILE_H11              = 0x000000b6,
SC_P0_HIZ_QUAD_PER_TILE_H12              = 0x000000b7,
SC_P0_HIZ_QUAD_PER_TILE_H13              = 0x000000b8,
SC_P0_HIZ_QUAD_PER_TILE_H14              = 0x000000b9,
SC_P0_HIZ_QUAD_PER_TILE_H15              = 0x000000ba,
SC_P0_HIZ_QUAD_PER_TILE_H16              = 0x000000bb,
SC_P1_HIZ_QUAD_PER_TILE_H0               = 0x000000bc,
SC_P1_HIZ_QUAD_PER_TILE_H1               = 0x000000bd,
SC_P1_HIZ_QUAD_PER_TILE_H2               = 0x000000be,
SC_P1_HIZ_QUAD_PER_TILE_H3               = 0x000000bf,
SC_P1_HIZ_QUAD_PER_TILE_H4               = 0x000000c0,
SC_P1_HIZ_QUAD_PER_TILE_H5               = 0x000000c1,
SC_P1_HIZ_QUAD_PER_TILE_H6               = 0x000000c2,
SC_P1_HIZ_QUAD_PER_TILE_H7               = 0x000000c3,
SC_P1_HIZ_QUAD_PER_TILE_H8               = 0x000000c4,
SC_P1_HIZ_QUAD_PER_TILE_H9               = 0x000000c5,
SC_P1_HIZ_QUAD_PER_TILE_H10              = 0x000000c6,
SC_P1_HIZ_QUAD_PER_TILE_H11              = 0x000000c7,
SC_P1_HIZ_QUAD_PER_TILE_H12              = 0x000000c8,
SC_P1_HIZ_QUAD_PER_TILE_H13              = 0x000000c9,
SC_P1_HIZ_QUAD_PER_TILE_H14              = 0x000000ca,
SC_P1_HIZ_QUAD_PER_TILE_H15              = 0x000000cb,
SC_P1_HIZ_QUAD_PER_TILE_H16              = 0x000000cc,
SC_P2_HIZ_QUAD_PER_TILE_H0               = 0x000000cd,
SC_P2_HIZ_QUAD_PER_TILE_H1               = 0x000000ce,
SC_P2_HIZ_QUAD_PER_TILE_H2               = 0x000000cf,
SC_P2_HIZ_QUAD_PER_TILE_H3               = 0x000000d0,
SC_P2_HIZ_QUAD_PER_TILE_H4               = 0x000000d1,
SC_P2_HIZ_QUAD_PER_TILE_H5               = 0x000000d2,
SC_P2_HIZ_QUAD_PER_TILE_H6               = 0x000000d3,
SC_P2_HIZ_QUAD_PER_TILE_H7               = 0x000000d4,
SC_P2_HIZ_QUAD_PER_TILE_H8               = 0x000000d5,
SC_P2_HIZ_QUAD_PER_TILE_H9               = 0x000000d6,
SC_P2_HIZ_QUAD_PER_TILE_H10              = 0x000000d7,
SC_P2_HIZ_QUAD_PER_TILE_H11              = 0x000000d8,
SC_P2_HIZ_QUAD_PER_TILE_H12              = 0x000000d9,
SC_P2_HIZ_QUAD_PER_TILE_H13              = 0x000000da,
SC_P2_HIZ_QUAD_PER_TILE_H14              = 0x000000db,
SC_P2_HIZ_QUAD_PER_TILE_H15              = 0x000000dc,
SC_P2_HIZ_QUAD_PER_TILE_H16              = 0x000000dd,
SC_P3_HIZ_QUAD_PER_TILE_H0               = 0x000000de,
SC_P3_HIZ_QUAD_PER_TILE_H1               = 0x000000df,
SC_P3_HIZ_QUAD_PER_TILE_H2               = 0x000000e0,
SC_P3_HIZ_QUAD_PER_TILE_H3               = 0x000000e1,
SC_P3_HIZ_QUAD_PER_TILE_H4               = 0x000000e2,
SC_P3_HIZ_QUAD_PER_TILE_H5               = 0x000000e3,
SC_P3_HIZ_QUAD_PER_TILE_H6               = 0x000000e4,
SC_P3_HIZ_QUAD_PER_TILE_H7               = 0x000000e5,
SC_P3_HIZ_QUAD_PER_TILE_H8               = 0x000000e6,
SC_P3_HIZ_QUAD_PER_TILE_H9               = 0x000000e7,
SC_P3_HIZ_QUAD_PER_TILE_H10              = 0x000000e8,
SC_P3_HIZ_QUAD_PER_TILE_H11              = 0x000000e9,
SC_P3_HIZ_QUAD_PER_TILE_H12              = 0x000000ea,
SC_P3_HIZ_QUAD_PER_TILE_H13              = 0x000000eb,
SC_P3_HIZ_QUAD_PER_TILE_H14              = 0x000000ec,
SC_P3_HIZ_QUAD_PER_TILE_H15              = 0x000000ed,
SC_P3_HIZ_QUAD_PER_TILE_H16              = 0x000000ee,
SC_P0_HIZ_QUAD_COUNT                     = 0x000000ef,
SC_P1_HIZ_QUAD_COUNT                     = 0x000000f0,
SC_P2_HIZ_QUAD_COUNT                     = 0x000000f1,
SC_P3_HIZ_QUAD_COUNT                     = 0x000000f2,
SC_P0_DETAIL_QUAD_COUNT                  = 0x000000f3,
SC_P1_DETAIL_QUAD_COUNT                  = 0x000000f4,
SC_P2_DETAIL_QUAD_COUNT                  = 0x000000f5,
SC_P3_DETAIL_QUAD_COUNT                  = 0x000000f6,
SC_P0_DETAIL_QUAD_WITH_1_PIX             = 0x000000f7,
SC_P0_DETAIL_QUAD_WITH_2_PIX             = 0x000000f8,
SC_P0_DETAIL_QUAD_WITH_3_PIX             = 0x000000f9,
SC_P0_DETAIL_QUAD_WITH_4_PIX             = 0x000000fa,
SC_P1_DETAIL_QUAD_WITH_1_PIX             = 0x000000fb,
SC_P1_DETAIL_QUAD_WITH_2_PIX             = 0x000000fc,
SC_P1_DETAIL_QUAD_WITH_3_PIX             = 0x000000fd,
SC_P1_DETAIL_QUAD_WITH_4_PIX             = 0x000000fe,
SC_P2_DETAIL_QUAD_WITH_1_PIX             = 0x000000ff,
SC_P2_DETAIL_QUAD_WITH_2_PIX             = 0x00000100,
SC_P2_DETAIL_QUAD_WITH_3_PIX             = 0x00000101,
SC_P2_DETAIL_QUAD_WITH_4_PIX             = 0x00000102,
SC_P3_DETAIL_QUAD_WITH_1_PIX             = 0x00000103,
SC_P3_DETAIL_QUAD_WITH_2_PIX             = 0x00000104,
SC_P3_DETAIL_QUAD_WITH_3_PIX             = 0x00000105,
SC_P3_DETAIL_QUAD_WITH_4_PIX             = 0x00000106,
SC_EARLYZ_QUAD_COUNT                     = 0x00000107,
SC_EARLYZ_QUAD_WITH_1_PIX                = 0x00000108,
SC_EARLYZ_QUAD_WITH_2_PIX                = 0x00000109,
SC_EARLYZ_QUAD_WITH_3_PIX                = 0x0000010a,
SC_EARLYZ_QUAD_WITH_4_PIX                = 0x0000010b,
SC_PKR_QUAD_PER_ROW_H1                   = 0x0000010c,
SC_PKR_QUAD_PER_ROW_H2                   = 0x0000010d,
SC_PKR_QUAD_PER_ROW_H3                   = 0x0000010e,
SC_PKR_QUAD_PER_ROW_H4                   = 0x0000010f,
SC_PKR_END_OF_VECTOR                     = 0x00000110,
SC_PKR_CONTROL_XFER                      = 0x00000111,
SC_PKR_DBHANG_FORCE_EOV                  = 0x00000112,
SC_REG_SCLK_BUSY                         = 0x00000113,
SC_GRP0_DYN_SCLK_BUSY                    = 0x00000114,
SC_GRP1_DYN_SCLK_BUSY                    = 0x00000115,
SC_GRP2_DYN_SCLK_BUSY                    = 0x00000116,
SC_GRP3_DYN_SCLK_BUSY                    = 0x00000117,
SC_GRP4_DYN_SCLK_BUSY                    = 0x00000118,
SC_PA0_SC_DATA_FIFO_RD                   = 0x00000119,
SC_PA0_SC_DATA_FIFO_WE                   = 0x0000011a,
SC_PA1_SC_DATA_FIFO_RD                   = 0x0000011b,
SC_PA1_SC_DATA_FIFO_WE                   = 0x0000011c,
SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES   = 0x0000011d,
SC_PS_ARB_XFC_ONLY_PRIM_CYCLES           = 0x0000011e,
SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM      = 0x0000011f,
SC_PS_ARB_STALLED_FROM_BELOW             = 0x00000120,
SC_PS_ARB_STARVED_FROM_ABOVE             = 0x00000121,
SC_PS_ARB_SC_BUSY                        = 0x00000122,
SC_PS_ARB_PA_SC_BUSY                     = 0x00000123,
SC_PA2_SC_DATA_FIFO_RD__CI__VI           = 0x00000124,
SC_PA2_SC_DATA_FIFO_WE__CI__VI           = 0x00000125,
SC_PA3_SC_DATA_FIFO_RD__CI__VI           = 0x00000126,
SC_PA3_SC_DATA_FIFO_WE__CI__VI           = 0x00000127,
SC_PA_SC_DEALLOC_0_0_WE__CI__VI          = 0x00000128,
SC_PA_SC_DEALLOC_0_1_WE__CI__VI          = 0x00000129,
SC_PA_SC_DEALLOC_1_0_WE__CI__VI          = 0x0000012a,
SC_PA_SC_DEALLOC_1_1_WE__CI__VI          = 0x0000012b,
SC_PA_SC_DEALLOC_2_0_WE__CI__VI          = 0x0000012c,
SC_PA_SC_DEALLOC_2_1_WE__CI__VI          = 0x0000012d,
SC_PA_SC_DEALLOC_3_0_WE__CI__VI          = 0x0000012e,
SC_PA_SC_DEALLOC_3_1_WE__CI__VI          = 0x0000012f,
SC_PA0_SC_EOP_WE__CI__VI                 = 0x00000130,
SC_PA0_SC_EOPG_WE__CI__VI                = 0x00000131,
SC_PA0_SC_EVENT_WE__CI__VI               = 0x00000132,
SC_PA1_SC_EOP_WE__CI__VI                 = 0x00000133,
SC_PA1_SC_EOPG_WE__CI__VI                = 0x00000134,
SC_PA1_SC_EVENT_WE__CI__VI               = 0x00000135,
SC_PA2_SC_EOP_WE__CI__VI                 = 0x00000136,
SC_PA2_SC_EOPG_WE__CI__VI                = 0x00000137,
SC_PA2_SC_EVENT_WE__CI__VI               = 0x00000138,
SC_PA3_SC_EOP_WE__CI__VI                 = 0x00000139,
SC_PA3_SC_EOPG_WE__CI__VI                = 0x0000013a,
SC_PA3_SC_EVENT_WE__CI__VI               = 0x0000013b,
SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO__CI__VI = 0x0000013c,
SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH__CI__VI  = 0x0000013d,
SC_PS_ARB_NULL_PRIM_BUBBLE_POP__CI__VI   = 0x0000013e,
SC_PS_ARB_EOP_POP_SYNC_POP__CI__VI       = 0x0000013f,
SC_PS_ARB_EVENT_SYNC_POP__CI__VI         = 0x00000140,
SC_SC_PS_ENG_MULTICYCLE_BUBBLE__CI__VI   = 0x00000141,
SC_PA0_SC_FPOV_WE__CI__VI                = 0x00000142,
SC_PA1_SC_FPOV_WE__CI__VI                = 0x00000143,
SC_PA2_SC_FPOV_WE__CI__VI                = 0x00000144,
SC_PA3_SC_FPOV_WE__CI__VI                = 0x00000145,
SC_PA0_SC_LPOV_WE__CI__VI                = 0x00000146,
SC_PA1_SC_LPOV_WE__CI__VI                = 0x00000147,
SC_PA2_SC_LPOV_WE__CI__VI                = 0x00000148,
SC_PA3_SC_LPOV_WE__CI__VI                = 0x00000149,
SC_SC_SPI_DEALLOC_0_0__CI__VI            = 0x0000014a,
SC_SC_SPI_DEALLOC_0_1__CI__VI            = 0x0000014b,
SC_SC_SPI_DEALLOC_0_2__CI__VI            = 0x0000014c,
SC_SC_SPI_DEALLOC_1_0__CI__VI            = 0x0000014d,
SC_SC_SPI_DEALLOC_1_1__CI__VI            = 0x0000014e,
SC_SC_SPI_DEALLOC_1_2__CI__VI            = 0x0000014f,
SC_SC_SPI_DEALLOC_2_0__CI__VI            = 0x00000150,
SC_SC_SPI_DEALLOC_2_1__CI__VI            = 0x00000151,
SC_SC_SPI_DEALLOC_2_2__CI__VI            = 0x00000152,
SC_SC_SPI_DEALLOC_3_0__CI__VI            = 0x00000153,
SC_SC_SPI_DEALLOC_3_1__CI__VI            = 0x00000154,
SC_SC_SPI_DEALLOC_3_2__CI__VI            = 0x00000155,
SC_SC_SPI_FPOV_0__CI__VI                 = 0x00000156,
SC_SC_SPI_FPOV_1__CI__VI                 = 0x00000157,
SC_SC_SPI_FPOV_2__CI__VI                 = 0x00000158,
SC_SC_SPI_FPOV_3__CI__VI                 = 0x00000159,
SC_SC_SPI_EVENT__CI__VI                  = 0x0000015a,
SC_PS_TS_EVENT_FIFO_PUSH__CI__VI         = 0x0000015b,
SC_PS_TS_EVENT_FIFO_POP__CI__VI          = 0x0000015c,
SC_PS_CTX_DONE_FIFO_PUSH__CI__VI         = 0x0000015d,
SC_PS_CTX_DONE_FIFO_POP__CI__VI          = 0x0000015e,
SC_MULTICYCLE_BUBBLE_FREEZE__CI__VI      = 0x0000015f,
SC_EOP_SYNC_WINDOW__CI__VI               = 0x00000160,
SC_PA0_SC_NULL_WE__CI__VI                = 0x00000161,
SC_PA0_SC_NULL_DEALLOC_WE__CI__VI        = 0x00000162,
SC_PA0_SC_DATA_FIFO_EOPG_RD__CI__VI      = 0x00000163,
SC_PA0_SC_DATA_FIFO_EOP_RD__CI__VI       = 0x00000164,
SC_PA0_SC_DEALLOC_0_RD__CI__VI           = 0x00000165,
SC_PA0_SC_DEALLOC_1_RD__CI__VI           = 0x00000166,
SC_PA1_SC_DATA_FIFO_EOPG_RD__CI__VI      = 0x00000167,
SC_PA1_SC_DATA_FIFO_EOP_RD__CI__VI       = 0x00000168,
SC_PA1_SC_DEALLOC_0_RD__CI__VI           = 0x00000169,
SC_PA1_SC_DEALLOC_1_RD__CI__VI           = 0x0000016a,
SC_PA1_SC_NULL_WE__CI__VI                = 0x0000016b,
SC_PA1_SC_NULL_DEALLOC_WE__CI__VI        = 0x0000016c,
SC_PA2_SC_DATA_FIFO_EOPG_RD__CI__VI      = 0x0000016d,
SC_PA2_SC_DATA_FIFO_EOP_RD__CI__VI       = 0x0000016e,
SC_PA2_SC_DEALLOC_0_RD__CI__VI           = 0x0000016f,
SC_PA2_SC_DEALLOC_1_RD__CI__VI           = 0x00000170,
SC_PA2_SC_NULL_WE__CI__VI                = 0x00000171,
SC_PA2_SC_NULL_DEALLOC_WE__CI__VI        = 0x00000172,
SC_PA3_SC_DATA_FIFO_EOPG_RD__CI__VI      = 0x00000173,
SC_PA3_SC_DATA_FIFO_EOP_RD__CI__VI       = 0x00000174,
SC_PA3_SC_DEALLOC_0_RD__CI__VI           = 0x00000175,
SC_PA3_SC_DEALLOC_1_RD__CI__VI           = 0x00000176,
SC_PA3_SC_NULL_WE__CI__VI                = 0x00000177,
SC_PA3_SC_NULL_DEALLOC_WE__CI__VI        = 0x00000178,
SC_PS_PA0_SC_FIFO_EMPTY__CI__VI          = 0x00000179,
SC_PS_PA0_SC_FIFO_FULL__CI__VI           = 0x0000017a,
SC_PA0_PS_DATA_SEND__CI__VI              = 0x0000017b,
SC_PS_PA1_SC_FIFO_EMPTY__CI__VI          = 0x0000017c,
SC_PS_PA1_SC_FIFO_FULL__CI__VI           = 0x0000017d,
SC_PA1_PS_DATA_SEND__CI__VI              = 0x0000017e,
SC_PS_PA2_SC_FIFO_EMPTY__CI__VI          = 0x0000017f,
SC_PS_PA2_SC_FIFO_FULL__CI__VI           = 0x00000180,
SC_PA2_PS_DATA_SEND__CI__VI              = 0x00000181,
SC_PS_PA3_SC_FIFO_EMPTY__CI__VI          = 0x00000182,
SC_PS_PA3_SC_FIFO_FULL__CI__VI           = 0x00000183,
SC_PA3_PS_DATA_SEND__CI__VI              = 0x00000184,
SC_BUSY_PROCESSING_MULTICYCLE_PRIM__CI__VI = 0x00000185,
SC_BUSY_CNT_NOT_ZERO__CI__VI             = 0x00000186,
SC_BM_BUSY__CI__VI                       = 0x00000187,
SC_BACKEND_BUSY__CI__VI                  = 0x00000188,
SC_SCF_SCB_INTERFACE_BUSY__CI__VI        = 0x00000189,
SC_SCB_BUSY__CI__VI                      = 0x0000018a,
SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY__VI = 0x0000018b,
SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL__VI = 0x0000018c,
} SC_PERFCNT_SEL;

typedef enum SDMA_PERF_SEL {
SDMA_PERF_SEL_CYCLE                      = 0x00000000,
SDMA_PERF_SEL_IDLE                       = 0x00000001,
SDMA_PERF_SEL_REG_IDLE                   = 0x00000002,
SDMA_PERF_SEL_RB_EMPTY                   = 0x00000003,
SDMA_PERF_SEL_RB_FULL                    = 0x00000004,
SDMA_PERF_SEL_RB_WPTR_WRAP               = 0x00000005,
SDMA_PERF_SEL_RB_RPTR_WRAP               = 0x00000006,
SDMA_PERF_SEL_RB_WPTR_POLL_READ          = 0x00000007,
SDMA_PERF_SEL_RB_RPTR_WB                 = 0x00000008,
SDMA_PERF_SEL_RB_CMD_IDLE                = 0x00000009,
SDMA_PERF_SEL_RB_CMD_FULL                = 0x0000000a,
SDMA_PERF_SEL_IB_CMD_IDLE                = 0x0000000b,
SDMA_PERF_SEL_IB_CMD_FULL                = 0x0000000c,
SDMA_PERF_SEL_EX_IDLE                    = 0x0000000d,
SDMA_PERF_SEL_SRBM_REG_SEND              = 0x0000000e,
SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE  = 0x0000000f,
SDMA_PERF_SEL_MC_WR_IDLE                 = 0x00000010,
SDMA_PERF_SEL_MC_WR_COUNT                = 0x00000011,
SDMA_PERF_SEL_MC_RD_IDLE                 = 0x00000012,
SDMA_PERF_SEL_MC_RD_COUNT                = 0x00000013,
SDMA_PERF_SEL_MC_RD_RET_STALL            = 0x00000014,
SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE         = 0x00000015,
SDMA_PERF_SEL_SEM_IDLE                   = 0x00000018,
SDMA_PERF_SEL_SEM_REQ_STALL              = 0x00000019,
SDMA_PERF_SEL_SEM_REQ_COUNT              = 0x0000001a,
SDMA_PERF_SEL_SEM_RESP_INCOMPLETE        = 0x0000001b,
SDMA_PERF_SEL_SEM_RESP_FAIL              = 0x0000001c,
SDMA_PERF_SEL_SEM_RESP_PASS              = 0x0000001d,
SDMA_PERF_SEL_INT_IDLE                   = 0x0000001e,
SDMA_PERF_SEL_INT_REQ_STALL              = 0x0000001f,
SDMA_PERF_SEL_INT_REQ_COUNT              = 0x00000020,
SDMA_PERF_SEL_INT_RESP_ACCEPTED          = 0x00000021,
SDMA_PERF_SEL_INT_RESP_RETRY             = 0x00000022,
SDMA_PERF_SEL_NUM_PACKET                 = 0x00000023,
SDMA_PERF_SEL_CE_WREQ_IDLE               = 0x00000025,
SDMA_PERF_SEL_CE_WR_IDLE                 = 0x00000026,
SDMA_PERF_SEL_CE_SPLIT_IDLE              = 0x00000027,
SDMA_PERF_SEL_CE_RREQ_IDLE               = 0x00000028,
SDMA_PERF_SEL_CE_OUT_IDLE                = 0x00000029,
SDMA_PERF_SEL_CE_IN_IDLE                 = 0x0000002a,
SDMA_PERF_SEL_CE_DST_IDLE                = 0x0000002b,
SDMA_PERF_SEL_CE_AFIFO_FULL              = 0x0000002e,
SDMA_PERF_SEL_CE_INFO_FULL               = 0x00000031,
SDMA_PERF_SEL_CE_INFO1_FULL              = 0x00000032,
SDMA_PERF_SEL_CE_RD_STALL                = 0x00000033,
SDMA_PERF_SEL_CE_WR_STALL                = 0x00000034,
SDMA_PERF_SEL_GFX_SELECT__VI             = 0x00000035,
SDMA_PERF_SEL_RLC0_SELECT__VI            = 0x00000036,
SDMA_PERF_SEL_RLC1_SELECT__VI            = 0x00000037,
SDMA_PERF_SEL_CTX_CHANGE__VI             = 0x00000038,
SDMA_PERF_SEL_CTX_CHANGE_EXPIRED__VI     = 0x00000039,
SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION__VI   = 0x0000003a,
SDMA_PERF_SEL_DOORBELL__VI               = 0x0000003b,
SDMA_PERF_SEL_RD_BA_RTR__VI              = 0x0000003c,
SDMA_PERF_SEL_WR_BA_RTR__VI              = 0x0000003d,
} SDMA_PERF_SEL;

typedef enum SH_MEM_ALIGNMENT_MODE {
SH_MEM_ALIGNMENT_MODE_DWORD              = 0x00000000,
SH_MEM_ALIGNMENT_MODE_DWORD_STRICT       = 0x00000001,
SH_MEM_ALIGNMENT_MODE_STRICT             = 0x00000002,
SH_MEM_ALIGNMENT_MODE_UNALIGNED          = 0x00000003,
} SH_MEM_ALIGNMENT_MODE;

typedef enum SPI_FOG_MODE {
SPI_FOG_NONE                             = 0x00000000,
SPI_FOG_EXP                              = 0x00000001,
SPI_FOG_EXP2                             = 0x00000002,
SPI_FOG_LINEAR                           = 0x00000003,
} SPI_FOG_MODE;

typedef enum SPI_PERFCNT_SEL {
SPI_PERF_VS_WINDOW_VALID                 = 0x00000000,
SPI_PERF_VS_BUSY                         = 0x00000001,
SPI_PERF_VS_FIRST_WAVE                   = 0x00000002,
SPI_PERF_VS_LAST_WAVE                    = 0x00000003,
SPI_PERF_VS_LSHS_DEALLOC                 = 0x00000004,
SPI_PERF_VS_PC_STALL                     = 0x00000005,
SPI_PERF_VS_POS0_STALL                   = 0x00000006,
SPI_PERF_VS_POS1_STALL                   = 0x00000007,
SPI_PERF_VS_CRAWLER_STALL                = 0x00000008,
SPI_PERF_VS_EVENT_WAVE                   = 0x00000009,
SPI_PERF_VS_WAVE                         = 0x0000000a,
SPI_PERF_VS_PERS_UPD_FULL0__CI__VI       = 0x0000000b,
SPI_PERF_GS_WINDOW_VALID__SI             = 0x0000000c,
SPI_PERF_VS_PERS_UPD_FULL1__CI__VI       = 0x0000000c,
SPI_PERF_GS_BUSY__SI                     = 0x0000000d,
SPI_PERF_VS_LATE_ALLOC_FULL__CI__VI      = 0x0000000d,
SPI_PERF_GS_CRAWLER_STALL__SI            = 0x0000000e,
SPI_PERF_VS_FIRST_SUBGRP__CI__VI         = 0x0000000e,
SPI_PERF_GS_EVENT_WAVE__SI               = 0x0000000f,
SPI_PERF_VS_LAST_SUBGRP__CI__VI          = 0x0000000f,
SPI_PERF_GS_WAVE__SI                     = 0x00000010,
SPI_PERF_GS_WINDOW_VALID__CI__VI         = 0x00000010,
SPI_PERF_GS_BUSY__CI__VI                 = 0x00000011,
SPI_PERF_ES_WINDOW_VALID__SI             = 0x00000012,
SPI_PERF_GS_CRAWLER_STALL__CI__VI        = 0x00000012,
SPI_PERF_ES_BUSY__SI                     = 0x00000013,
SPI_PERF_GS_EVENT_WAVE__CI__VI           = 0x00000013,
SPI_PERF_ES_CRAWLER_STALL__SI            = 0x00000014,
SPI_PERF_GS_WAVE__CI__VI                 = 0x00000014,
SPI_PERF_ES_FIRST_WAVE__SI               = 0x00000015,
SPI_PERF_GS_PERS_UPD_FULL0__CI__VI       = 0x00000015,
SPI_PERF_ES_LAST_WAVE__SI                = 0x00000016,
SPI_PERF_GS_PERS_UPD_FULL1__CI__VI       = 0x00000016,
SPI_PERF_ES_LSHS_DEALLOC__SI             = 0x00000017,
SPI_PERF_GS_FIRST_SUBGRP__CI__VI         = 0x00000017,
SPI_PERF_ES_EVENT_WAVE__SI               = 0x00000018,
SPI_PERF_GS_LAST_SUBGRP__CI__VI          = 0x00000018,
SPI_PERF_ES_WAVE__SI                     = 0x00000019,
SPI_PERF_ES_WINDOW_VALID__CI__VI         = 0x00000019,
SPI_PERF_ES_BUSY__CI__VI                 = 0x0000001a,
SPI_PERF_HS_WINDOW_VALID__SI             = 0x0000001b,
SPI_PERF_ES_CRAWLER_STALL__CI__VI        = 0x0000001b,
SPI_PERF_HS_BUSY__SI                     = 0x0000001c,
SPI_PERF_ES_FIRST_WAVE__CI__VI           = 0x0000001c,
SPI_PERF_HS_CRAWLER_STALL__SI            = 0x0000001d,
SPI_PERF_ES_LAST_WAVE__CI__VI            = 0x0000001d,
SPI_PERF_HS_FIRST_WAVE__SI               = 0x0000001e,
SPI_PERF_ES_LSHS_DEALLOC__CI__VI         = 0x0000001e,
SPI_PERF_HS_LAST_WAVE__SI                = 0x0000001f,
SPI_PERF_ES_EVENT_WAVE__CI__VI           = 0x0000001f,
SPI_PERF_HS_LSHS_DEALLOC__SI             = 0x00000020,
SPI_PERF_ES_WAVE__CI__VI                 = 0x00000020,
SPI_PERF_HS_EVENT_WAVE__SI               = 0x00000021,
SPI_PERF_ES_PERS_UPD_FULL0__CI__VI       = 0x00000021,
SPI_PERF_HS_WAVE__SI                     = 0x00000022,
SPI_PERF_ES_PERS_UPD_FULL1__CI__VI       = 0x00000022,
SPI_PERF_ES_FIRST_SUBGRP__CI__VI         = 0x00000023,
SPI_PERF_LS_WINDOW_VALID__SI             = 0x00000024,
SPI_PERF_ES_LAST_SUBGRP__CI__VI          = 0x00000024,
SPI_PERF_LS_BUSY__SI                     = 0x00000025,
SPI_PERF_HS_WINDOW_VALID__CI__VI         = 0x00000025,
SPI_PERF_LS_CRAWLER_STALL__SI            = 0x00000026,
SPI_PERF_HS_BUSY__CI__VI                 = 0x00000026,
SPI_PERF_LS_FIRST_WAVE__SI               = 0x00000027,
SPI_PERF_HS_CRAWLER_STALL__CI__VI        = 0x00000027,
SPI_PERF_LS_LAST_WAVE__SI                = 0x00000028,
SPI_PERF_HS_FIRST_WAVE__CI__VI           = 0x00000028,
SPI_PERF_OFFCHIP_LDS_STALL_LS__SI        = 0x00000029,
SPI_PERF_HS_LAST_WAVE__CI__VI            = 0x00000029,
SPI_PERF_LS_EVENT_WAVE__SI               = 0x0000002a,
SPI_PERF_HS_LSHS_DEALLOC__CI__VI         = 0x0000002a,
SPI_PERF_LS_WAVE__SI                     = 0x0000002b,
SPI_PERF_HS_EVENT_WAVE__CI__VI           = 0x0000002b,
SPI_PERF_HS_WAVE__CI__VI                 = 0x0000002c,
SPI_PERF_HS_PERS_UPD_FULL0__CI__VI       = 0x0000002d,
SPI_PERF_HS_PERS_UPD_FULL1__CI__VI       = 0x0000002e,
SPI_PERF_LS_WINDOW_VALID__CI__VI         = 0x0000002f,
SPI_PERF_LS_BUSY__CI__VI                 = 0x00000030,
SPI_PERF_LS_CRAWLER_STALL__CI__VI        = 0x00000031,
SPI_PERF_LS_FIRST_WAVE__CI__VI           = 0x00000032,
SPI_PERF_LS_LAST_WAVE__CI__VI            = 0x00000033,
SPI_PERF_OFFCHIP_LDS_STALL_LS__CI__VI    = 0x00000034,
SPI_PERF_LS_EVENT_WAVE__CI__VI           = 0x00000035,
SPI_PERF_LS_WAVE__CI__VI                 = 0x00000036,
SPI_PERF_LS_PERS_UPD_FULL0__CI__VI       = 0x00000037,
SPI_PERF_LS_PERS_UPD_FULL1__CI__VI       = 0x00000038,
SPI_PERF_CSG_WINDOW_VALID__CI__VI        = 0x00000039,
SPI_PERF_CSG_BUSY__CI__VI                = 0x0000003a,
SPI_PERF_CSG_NUM_THREADGROUPS__CI__VI    = 0x0000003b,
SPI_PERF_CSG_CRAWLER_STALL__CI__VI       = 0x0000003c,
SPI_PERF_CSG_EVENT_WAVE__CI__VI          = 0x0000003d,
SPI_PERF_CSG_WAVE__CI__VI                = 0x0000003e,
SPI_PERF_CSN_WINDOW_VALID__CI__VI        = 0x0000003f,
SPI_PERF_CSN_BUSY__CI__VI                = 0x00000040,
SPI_PERF_CSN_NUM_THREADGROUPS__CI__VI    = 0x00000041,
SPI_PERF_PS_CTL_WINDOW_VALID__SI         = 0x00000042,
SPI_PERF_CSN_CRAWLER_STALL__CI__VI       = 0x00000042,
SPI_PERF_PS_CTL_BUSY__SI                 = 0x00000043,
SPI_PERF_CSN_EVENT_WAVE__CI__VI          = 0x00000043,
SPI_PERF_PS_CTL_ACTIVE__SI               = 0x00000044,
SPI_PERF_CSN_WAVE__CI__VI                = 0x00000044,
SPI_PERF_PS_CTL_WINDOW_VALID__CI__VI     = 0x00000045,
SPI_PERF_PS_CTL_BUSY__CI__VI             = 0x00000046,
SPI_PERF_PS_CTL_ACTIVE__CI__VI           = 0x00000047,
SPI_PERF_PS_CTL_DEALLOC_BIN0__CI__VI     = 0x00000048,
SPI_PERF_PS_CTL_EVENT_WAVE__SI           = 0x00000049,
SPI_PERF_PS_CTL_FPOS_BIN1_STALL__CI__VI  = 0x00000049,
SPI_PERF_PS_CTL_WAVE__SI                 = 0x0000004a,
SPI_PERF_PS_CTL_EVENT_WAVE__CI__VI       = 0x0000004a,
SPI_PERF_PS_CTL_OPT_WAVE__SI             = 0x0000004b,
SPI_PERF_PS_CTL_WAVE__CI__VI             = 0x0000004b,
SPI_PERF_PS_CTL_PASS_BIN0__SI            = 0x0000004c,
SPI_PERF_PS_CTL_OPT_WAVE__CI__VI         = 0x0000004c,
SPI_PERF_PS_CTL_PASS_BIN1__SI            = 0x0000004d,
SPI_PERF_PS_CTL_PASS_BIN0__CI__VI        = 0x0000004d,
SPI_PERF_PS_CTL_PASS_BIN1__CI__VI        = 0x0000004e,
SPI_PERF_PS_CTL_FPOS_BIN2__CI__VI        = 0x0000004f,
SPI_PERF_PS_CTL_PRIM_BIN0                = 0x00000050,
SPI_PERF_PS_CTL_PRIM_BIN1                = 0x00000051,
SPI_PERF_PS_CTL_CNF_BIN2                 = 0x00000052,
SPI_PERF_PS_CTL_CNF_BIN3                 = 0x00000053,
SPI_PERF_PS_CTL_CRAWLER_STALL            = 0x00000054,
SPI_PERF_PS_CTL_LDS_RES_FULL             = 0x00000055,
SPI_PERF_PS_PERS_UPD_FULL0__CI__VI       = 0x00000056,
SPI_PERF_PIX_ALLOC_PEND_CNT__SI          = 0x00000057,
SPI_PERF_PS_PERS_UPD_FULL1__CI__VI       = 0x00000057,
SPI_PERF_PIX_ALLOC_SCB_STALL__SI         = 0x00000058,
SPI_PERF_PIX_ALLOC_PEND_CNT__CI__VI      = 0x00000058,
SPI_PERF_PIX_ALLOC_DB0_STALL__SI         = 0x00000059,
SPI_PERF_PIX_ALLOC_SCB_STALL__CI__VI     = 0x00000059,
SPI_PERF_PIX_ALLOC_DB1_STALL__SI         = 0x0000005a,
SPI_PERF_PIX_ALLOC_DB0_STALL__CI__VI     = 0x0000005a,
SPI_PERF_PIX_ALLOC_DB1_STALL__CI__VI     = 0x0000005b,
SPI_PERF_PIX_ALLOC_DB2_STALL__CI__VI     = 0x0000005c,
SPI_PERF_PIX_ALLOC_DB3_STALL__CI__VI     = 0x0000005d,
SPI_PERF_RA_TASK_REQ_BIN3__SI            = 0x0000005e,
SPI_PERF_LDS0_PC_VALID__CI__VI           = 0x0000005e,
SPI_PERF_RA_WR_CTL_FULL__SI              = 0x0000005f,
SPI_PERF_LDS1_PC_VALID__CI__VI           = 0x0000005f,
SPI_PERF_RA_REQ_NO_ALLOC__SI             = 0x00000060,
SPI_PERF_RA_PIPE_REQ_BIN2__CI__VI        = 0x00000060,
SPI_PERF_RA_REQ_NO_ALLOC_PS__SI          = 0x00000061,
SPI_PERF_RA_TASK_REQ_BIN3__CI__VI        = 0x00000061,
SPI_PERF_RA_REQ_NO_ALLOC_VS__SI          = 0x00000062,
SPI_PERF_RA_WR_CTL_FULL__CI__VI          = 0x00000062,
SPI_PERF_RA_REQ_NO_ALLOC_GS__SI          = 0x00000063,
SPI_PERF_RA_REQ_NO_ALLOC__CI__VI         = 0x00000063,
SPI_PERF_RA_REQ_NO_ALLOC_ES__SI          = 0x00000064,
SPI_PERF_RA_REQ_NO_ALLOC_PS__CI__VI      = 0x00000064,
SPI_PERF_RA_REQ_NO_ALLOC_HS__SI          = 0x00000065,
SPI_PERF_RA_REQ_NO_ALLOC_VS__CI__VI      = 0x00000065,
SPI_PERF_RA_REQ_NO_ALLOC_LS__SI          = 0x00000066,
SPI_PERF_RA_REQ_NO_ALLOC_GS__CI__VI      = 0x00000066,
SPI_PERF_RA_REQ_NO_ALLOC_ES__CI__VI      = 0x00000067,
SPI_PERF_RA_REQ_NO_ALLOC_HS__CI__VI      = 0x00000068,
SPI_PERF_RA_REQ_NO_ALLOC_LS__CI__VI      = 0x00000069,
SPI_PERF_RA_RES_STALL_PS__SI             = 0x0000006a,
SPI_PERF_RA_REQ_NO_ALLOC_CSG__CI__VI     = 0x0000006a,
SPI_PERF_RA_RES_STALL_VS__SI             = 0x0000006b,
SPI_PERF_RA_REQ_NO_ALLOC_CSN__CI__VI     = 0x0000006b,
SPI_PERF_RA_RES_STALL_GS__SI             = 0x0000006c,
SPI_PERF_RA_RES_STALL_PS__CI__VI         = 0x0000006c,
SPI_PERF_RA_RES_STALL_ES__SI             = 0x0000006d,
SPI_PERF_RA_RES_STALL_VS__CI__VI         = 0x0000006d,
SPI_PERF_RA_RES_STALL_HS__SI             = 0x0000006e,
SPI_PERF_RA_RES_STALL_GS__CI__VI         = 0x0000006e,
SPI_PERF_RA_RES_STALL_LS__SI             = 0x0000006f,
SPI_PERF_RA_RES_STALL_ES__CI__VI         = 0x0000006f,
SPI_PERF_RA_RES_STALL_HS__CI__VI         = 0x00000070,
SPI_PERF_RA_RES_STALL_LS__CI__VI         = 0x00000071,
SPI_PERF_RA_RES_STALL_CSG__CI__VI        = 0x00000072,
SPI_PERF_RA_TMP_STALL_PS__SI             = 0x00000073,
SPI_PERF_RA_RES_STALL_CSN__CI__VI        = 0x00000073,
SPI_PERF_RA_TMP_STALL_VS__SI             = 0x00000074,
SPI_PERF_RA_TMP_STALL_PS__CI__VI         = 0x00000074,
SPI_PERF_RA_TMP_STALL_GS__SI             = 0x00000075,
SPI_PERF_RA_TMP_STALL_VS__CI__VI         = 0x00000075,
SPI_PERF_RA_TMP_STALL_ES__SI             = 0x00000076,
SPI_PERF_RA_TMP_STALL_GS__CI__VI         = 0x00000076,
SPI_PERF_RA_TMP_STALL_HS__SI             = 0x00000077,
SPI_PERF_RA_TMP_STALL_ES__CI__VI         = 0x00000077,
SPI_PERF_RA_TMP_STALL_LS__SI             = 0x00000078,
SPI_PERF_RA_TMP_STALL_HS__CI__VI         = 0x00000078,
SPI_PERF_RA_TMP_STALL_LS__CI__VI         = 0x00000079,
SPI_PERF_RA_TMP_STALL_CSG__CI__VI        = 0x0000007a,
SPI_PERF_RA_TMP_STALL_CSN__CI__VI        = 0x0000007b,
SPI_PERF_RA_WAVE_SIMD_FULL_PS            = 0x0000007c,
SPI_PERF_RA_WAVE_SIMD_FULL_VS            = 0x0000007d,
SPI_PERF_RA_WAVE_SIMD_FULL_GS            = 0x0000007e,
SPI_PERF_RA_WAVE_SIMD_FULL_ES            = 0x0000007f,
SPI_PERF_RA_WAVE_SIMD_FULL_HS            = 0x00000080,
SPI_PERF_RA_WAVE_SIMD_FULL_LS            = 0x00000081,
SPI_PERF_RA_WAVE_SIMD_FULL_CSG__CI__VI   = 0x00000082,
SPI_PERF_RA_WAVE_SIMD_FULL_CSN__CI__VI   = 0x00000083,
SPI_PERF_RA_VGPR_SIMD_FULL_PS__CI__VI    = 0x00000084,
SPI_PERF_RA_VGPR_SIMD_FULL_PS__SI        = 0x00000085,
SPI_PERF_RA_VGPR_SIMD_FULL_VS__CI__VI    = 0x00000085,
SPI_PERF_RA_VGPR_SIMD_FULL_VS__SI        = 0x00000086,
SPI_PERF_RA_VGPR_SIMD_FULL_GS__CI__VI    = 0x00000086,
SPI_PERF_RA_VGPR_SIMD_FULL_GS__SI        = 0x00000087,
SPI_PERF_RA_VGPR_SIMD_FULL_ES__CI__VI    = 0x00000087,
SPI_PERF_RA_VGPR_SIMD_FULL_ES__SI        = 0x00000088,
SPI_PERF_RA_VGPR_SIMD_FULL_HS__CI__VI    = 0x00000088,
SPI_PERF_RA_VGPR_SIMD_FULL_HS__SI        = 0x00000089,
SPI_PERF_RA_VGPR_SIMD_FULL_LS__CI__VI    = 0x00000089,
SPI_PERF_RA_VGPR_SIMD_FULL_LS__SI        = 0x0000008a,
SPI_PERF_RA_VGPR_SIMD_FULL_CSG__CI__VI   = 0x0000008a,
SPI_PERF_RA_VGPR_SIMD_FULL_CSN__CI__VI   = 0x0000008b,
SPI_PERF_RA_SGPR_SIMD_FULL_PS__CI__VI    = 0x0000008c,
SPI_PERF_RA_SGPR_SIMD_FULL_VS__CI__VI    = 0x0000008d,
SPI_PERF_RA_SGPR_SIMD_FULL_PS__SI        = 0x0000008e,
SPI_PERF_RA_SGPR_SIMD_FULL_GS__CI__VI    = 0x0000008e,
SPI_PERF_RA_SGPR_SIMD_FULL_VS__SI        = 0x0000008f,
SPI_PERF_RA_SGPR_SIMD_FULL_ES__CI__VI    = 0x0000008f,
SPI_PERF_RA_SGPR_SIMD_FULL_GS__SI        = 0x00000090,
SPI_PERF_RA_SGPR_SIMD_FULL_HS__CI__VI    = 0x00000090,
SPI_PERF_RA_SGPR_SIMD_FULL_ES__SI        = 0x00000091,
SPI_PERF_RA_SGPR_SIMD_FULL_LS__CI__VI    = 0x00000091,
SPI_PERF_RA_SGPR_SIMD_FULL_HS__SI        = 0x00000092,
SPI_PERF_RA_SGPR_SIMD_FULL_CSG__CI__VI   = 0x00000092,
SPI_PERF_RA_SGPR_SIMD_FULL_LS__SI        = 0x00000093,
SPI_PERF_RA_SGPR_SIMD_FULL_CSN__CI__VI   = 0x00000093,
SPI_PERF_RA_LDS_CU_FULL_PS__CI__VI       = 0x00000094,
SPI_PERF_RA_LDS_CU_FULL_LS__CI__VI       = 0x00000095,
SPI_PERF_RA_LDS_CU_FULL_ES__CI__VI       = 0x00000096,
SPI_PERF_RA_LDS_CU_FULL_PS__SI           = 0x00000097,
SPI_PERF_RA_LDS_CU_FULL_CSG__CI__VI      = 0x00000097,
SPI_PERF_RA_LDS_CU_FULL_LS__SI           = 0x00000098,
SPI_PERF_RA_LDS_CU_FULL_CSN__CI__VI      = 0x00000098,
SPI_PERF_RA_BAR_CU_FULL_HS__CI__VI       = 0x00000099,
SPI_PERF_RA_BAR_CU_FULL_CSG__CI__VI      = 0x0000009a,
SPI_PERF_RA_BAR_CU_FULL_CSN__CI__VI      = 0x0000009b,
SPI_PERF_RA_BAR_CU_FULL_HS__SI           = 0x0000009c,
SPI_PERF_RA_BULKY_CU_FULL_CSG__CI__VI    = 0x0000009c,
SPI_PERF_RA_BULKY_CU_FULL_CSN__CI__VI    = 0x0000009d,
SPI_PERF_RA_TGLIM_CU_FULL_CSG__CI__VI    = 0x0000009e,
SPI_PERF_RA_TGLIM_CU_FULL_CSN__CI__VI    = 0x0000009f,
SPI_PERF_RA_WVLIM_STALL_PS__CI__VI       = 0x000000a0,
SPI_PERF_RA_WVLIM_STALL_VS__CI__VI       = 0x000000a1,
SPI_PERF_RA_WVLIM_STALL_GS__CI__VI       = 0x000000a2,
SPI_PERF_RA_WVLIM_STALL_PS__SI           = 0x000000a3,
SPI_PERF_RA_WVLIM_STALL_ES__CI__VI       = 0x000000a3,
SPI_PERF_RA_WVLIM_STALL_VS__SI           = 0x000000a4,
SPI_PERF_RA_WVLIM_STALL_HS__CI__VI       = 0x000000a4,
SPI_PERF_RA_WVLIM_STALL_GS__SI           = 0x000000a5,
SPI_PERF_RA_WVLIM_STALL_LS__CI__VI       = 0x000000a5,
SPI_PERF_RA_WVLIM_STALL_ES__SI           = 0x000000a6,
SPI_PERF_RA_WVLIM_STALL_CSG__CI__VI      = 0x000000a6,
SPI_PERF_RA_WVLIM_STALL_HS__SI           = 0x000000a7,
SPI_PERF_RA_WVLIM_STALL_CSN__CI__VI      = 0x000000a7,
SPI_PERF_RA_WVLIM_STALL_LS__SI           = 0x000000a8,
SPI_PERF_RA_PS_LOCK__CI                  = 0x000000a8,
SPI_PERF_RA_PS_LOCK_NA__VI               = 0x000000a8,
SPI_PERF_RA_VS_LOCK__CI__VI              = 0x000000a9,
SPI_PERF_RA_GS_LOCK__CI__VI              = 0x000000aa,
SPI_PERF_RA_ES_LOCK__CI__VI              = 0x000000ab,
SPI_PERF_RA_VS_LOCK__SI                  = 0x000000ac,
SPI_PERF_RA_HS_LOCK__CI__VI              = 0x000000ac,
SPI_PERF_RA_GS_LOCK__SI                  = 0x000000ad,
SPI_PERF_RA_LS_LOCK__CI__VI              = 0x000000ad,
SPI_PERF_RA_ES_LOCK__SI                  = 0x000000ae,
SPI_PERF_RA_CSG_LOCK__CI__VI             = 0x000000ae,
SPI_PERF_RA_HS_LOCK__SI                  = 0x000000af,
SPI_PERF_RA_CSN_LOCK__CI__VI             = 0x000000af,
SPI_PERF_RA_LS_LOCK__SI                  = 0x000000b0,
SPI_PERF_RA_RSV_UPD__CI__VI              = 0x000000b0,
SPI_PERF_EXP_ARB_COL_CNT__CI__VI         = 0x000000b1,
SPI_PERF_EXP_ARB_PAR_CNT__CI__VI         = 0x000000b2,
SPI_PERF_EXP_ARB_POS_CNT__CI__VI         = 0x000000b3,
SPI_PERF_EXP_ARB_COL_CNT__SI             = 0x000000b4,
SPI_PERF_EXP_ARB_GDS_CNT__CI__VI         = 0x000000b4,
SPI_PERF_EXP_ARB_PAR_CNT__SI             = 0x000000b5,
SPI_PERF_CLKGATE_BUSY_STALL__CI__VI      = 0x000000b5,
SPI_PERF_EXP_ARB_POS_CNT__SI             = 0x000000b6,
SPI_PERF_CLKGATE_ACTIVE_STALL__CI__VI    = 0x000000b6,
SPI_PERF_EXP_ARB_GDS_CNT__SI             = 0x000000b7,
SPI_PERF_CLKGATE_ALL_CLOCKS_ON__CI__VI   = 0x000000b7,
SPI_PERF_CLKGATE_BUSY_STALL__SI          = 0x000000b8,
SPI_PERF_CLKGATE_CGTT_DYN_ON__CI__VI     = 0x000000b8,
SPI_PERF_CLKGATE_ACTIVE_STALL__SI        = 0x000000b9,
SPI_PERF_CLKGATE_CGTT_REG_ON__CI__VI     = 0x000000b9,
SPI_PERF_CLKGATE_ALL_CLOCKS_ON__SI       = 0x000000ba,
SPI_PERF_NUM_VS_POS_EXPORTS__VI          = 0x000000ba,
SPI_PERF_CLKGATE_CGTT_DYN_ON__SI         = 0x000000bb,
SPI_PERF_NUM_VS_PARAM_EXPORTS__VI        = 0x000000bb,
SPI_PERF_CLKGATE_CGTT_REG_ON__SI         = 0x000000bc,
SPI_PERF_NUM_PS_COL_EXPORTS__VI          = 0x000000bc,
SPI_PERF_ES_GRP_FIFO_FULL__VI            = 0x000000bd,
SPI_PERF_GS_GRP_FIFO_FULL__VI            = 0x000000be,
SPI_PERF_HS_GRP_FIFO_FULL__VI            = 0x000000bf,
SPI_PERF_LS_GRP_FIFO_FULL__VI            = 0x000000c0,
SPI_PERF_VS_ALLOC_CNT__VI                = 0x000000c1,
SPI_PERF_VS_LATE_ALLOC_ACCUM__VI         = 0x000000c2,
SPI_PERF_PC_ALLOC_CNT__VI                = 0x000000c3,
SPI_PERF_PC_ALLOC_ACCUM__VI              = 0x000000c4,
} SPI_PERFCNT_SEL;

typedef enum SPI_PNT_SPRITE_OVERRIDE {
SPI_PNT_SPRITE_SEL_0                     = 0x00000000,
SPI_PNT_SPRITE_SEL_1                     = 0x00000001,
SPI_PNT_SPRITE_SEL_S                     = 0x00000002,
SPI_PNT_SPRITE_SEL_T                     = 0x00000003,
SPI_PNT_SPRITE_SEL_NONE                  = 0x00000004,
} SPI_PNT_SPRITE_OVERRIDE;

typedef enum SPI_SAMPLE_CNTL {
CENTROIDS_ONLY                           = 0x00000000,
CENTERS_ONLY                             = 0x00000001,
CENTROIDS_AND_CENTERS                    = 0x00000002,
UNDEF                                    = 0x00000003,
} SPI_SAMPLE_CNTL;

typedef enum SPI_SHADER_EX_FORMAT {
SPI_SHADER_ZERO                          = 0x00000000,
SPI_SHADER_32_R                          = 0x00000001,
SPI_SHADER_32_GR                         = 0x00000002,
SPI_SHADER_32_AR                         = 0x00000003,
SPI_SHADER_FP16_ABGR                     = 0x00000004,
SPI_SHADER_UNORM16_ABGR                  = 0x00000005,
SPI_SHADER_SNORM16_ABGR                  = 0x00000006,
SPI_SHADER_UINT16_ABGR                   = 0x00000007,
SPI_SHADER_SINT16_ABGR                   = 0x00000008,
SPI_SHADER_32_ABGR                       = 0x00000009,
} SPI_SHADER_EX_FORMAT;

typedef enum SPI_SHADER_FORMAT {
SPI_SHADER_NONE                          = 0x00000000,
SPI_SHADER_1COMP                         = 0x00000001,
SPI_SHADER_2COMP                         = 0x00000002,
SPI_SHADER_4COMPRESS                     = 0x00000003,
SPI_SHADER_4COMP                         = 0x00000004,
} SPI_SHADER_FORMAT;

typedef enum SPM_PERFMON_STATE {
STRM_PERFMON_STATE_DISABLE_AND_RESET     = 0x00000000,
STRM_PERFMON_STATE_START_COUNTING        = 0x00000001,
STRM_PERFMON_STATE_STOP_COUNTING         = 0x00000002,
STRM_PERFMON_STATE_RESERVED_3            = 0x00000003,
STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
} SPM_PERFMON_STATE;

typedef enum SQC_DATA_CACHE_POLICIES {
SQC_DATA_CACHE_POLICY_HIT_LRU            = 0x00000000,
SQC_DATA_CACHE_POLICY_MISS_EVICT         = 0x00000001,
} SQC_DATA_CACHE_POLICIES;

typedef enum SQ_CAC_POWER_SEL {
SQ_CAC_POWER_VALU                        = 0x00000000,
SQ_CAC_POWER_VALU0                       = 0x00000001,
SQ_CAC_POWER_VALU1                       = 0x00000002,
SQ_CAC_POWER_VALU2                       = 0x00000003,
SQ_CAC_POWER_GPR_RD                      = 0x00000004,
SQ_CAC_POWER_GPR_WR                      = 0x00000005,
SQ_CAC_POWER_LDS_BUSY                    = 0x00000006,
SQ_CAC_POWER_ALU_BUSY                    = 0x00000007,
SQ_CAC_POWER_TEX_BUSY                    = 0x00000008,
} SQ_CAC_POWER_SEL;

typedef enum SQ_DED_INFO_SOURCE {
SQ_DED_INFO_SOURCE_INVALID               = 0x00000000,
SQ_DED_INFO_SOURCE_INST                  = 0x00000001,
SQ_DED_INFO_SOURCE_SGPR                  = 0x00000002,
SQ_DED_INFO_SOURCE_VGPR                  = 0x00000003,
SQ_DED_INFO_SOURCE_LDS                   = 0x00000004,
SQ_DED_INFO_SOURCE_GDS                   = 0x00000005,
SQ_DED_INFO_SOURCE_TA                    = 0x00000006,
} SQ_DED_INFO_SOURCE;

typedef enum SQ_IBUF_ST {
SQ_IBUF_IB_IDLE                          = 0x00000000,
SQ_IBUF_IB_INI_WAIT_GNT                  = 0x00000001,
SQ_IBUF_IB_INI_WAIT_DRET                 = 0x00000002,
SQ_IBUF_IB_LE_4DW                        = 0x00000003,
SQ_IBUF_IB_WAIT_DRET                     = 0x00000004,
SQ_IBUF_IB_EMPTY_WAIT_DRET               = 0x00000005,
SQ_IBUF_IB_DRET                          = 0x00000006,
SQ_IBUF_IB_EMPTY_WAIT_GNT                = 0x00000007,
} SQ_IBUF_ST;

typedef enum SQ_IMG_FILTER_TYPE {
SQ_IMG_FILTER_MODE_BLEND                 = 0x00000000,
SQ_IMG_FILTER_MODE_MIN                   = 0x00000001,
SQ_IMG_FILTER_MODE_MAX                   = 0x00000002,
} SQ_IMG_FILTER_TYPE;

typedef enum SQ_IND_CMD_CMD {
SQ_IND_CMD_CMD_NULL                      = 0x00000000,
SQ_IND_CMD_CMD_HALT__SI__CI              = 0x00000001,
SQ_IND_CMD_CMD_SETHALT__VI               = 0x00000001,
SQ_IND_CMD_CMD_RESUME__SI__CI            = 0x00000002,
SQ_IND_CMD_CMD_SAVECTX__VI               = 0x00000002,
SQ_IND_CMD_CMD_KILL                      = 0x00000003,
SQ_IND_CMD_CMD_DEBUG                     = 0x00000004,
SQ_IND_CMD_CMD_TRAP                      = 0x00000005,
SQ_IND_CMD_CMD_SET_SPI_PRIO__VI          = 0x00000006,
} SQ_IND_CMD_CMD;

typedef enum SQ_IND_CMD_MODE {
SQ_IND_CMD_MODE_SINGLE                   = 0x00000000,
SQ_IND_CMD_MODE_BROADCAST                = 0x00000001,
SQ_IND_CMD_MODE_BROADCAST_QUEUE__CI__VI  = 0x00000002,
SQ_IND_CMD_MODE_BROADCAST_PIPE__CI__VI   = 0x00000003,
SQ_IND_CMD_MODE_BROADCAST_ME__CI__VI     = 0x00000004,
} SQ_IND_CMD_MODE;

typedef enum SQ_INST_STR_ST {
SQ_INST_STR_IB_WAVE_NORML                = 0x00000000,
SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV    = 0x00000001,
SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV     = 0x00000002,
SQ_INST_STR_IB_WAVE_INST_SKIP_AV         = 0x00000003,
SQ_INST_STR_IB_WAVE_SETVSKIP_ST0         = 0x00000004,
SQ_INST_STR_IB_WAVE_SETVSKIP_ST1         = 0x00000005,
SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT       = 0x00000006,
SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007,
} SQ_INST_STR_ST;

typedef enum SQ_INTERRUPT_WORD_ENCODING {
SQ_INTERRUPT_WORD_ENCODING_AUTO          = 0x00000000,
SQ_INTERRUPT_WORD_ENCODING_INST          = 0x00000001,
SQ_INTERRUPT_WORD_ENCODING_ERROR         = 0x00000002,
} SQ_INTERRUPT_WORD_ENCODING;

typedef enum SQ_PERF_SEL {
SQ_PERF_SEL_NONE                         = 0x00000000,
SQ_PERF_SEL_ACCUM_PREV                   = 0x00000001,
SQ_PERF_SEL_CYCLES                       = 0x00000002,
SQ_PERF_SEL_BUSY_CYCLES                  = 0x00000003,
SQ_PERF_SEL_WAVES                        = 0x00000004,
SQ_PERF_SEL_LEVEL_WAVES                  = 0x00000005,
SQ_PERF_SEL_WAVES_CU__SI                 = 0x00000006,
SQ_PERF_SEL_WAVES_EQ_64__CI__VI          = 0x00000006,
SQ_PERF_SEL_LEVEL_WAVES_CU__SI           = 0x00000007,
SQ_PERF_SEL_WAVES_LT_64__CI__VI          = 0x00000007,
SQ_PERF_SEL_BUSY_CU_CYCLES__SI           = 0x00000008,
SQ_PERF_SEL_WAVES_LT_48__CI__VI          = 0x00000008,
SQ_PERF_SEL_ITEMS__SI                    = 0x00000009,
SQ_PERF_SEL_WAVES_LT_32__CI__VI          = 0x00000009,
SQ_PERF_SEL_QUADS__SI                    = 0x0000000a,
SQ_PERF_SEL_WAVES_LT_16__CI__VI          = 0x0000000a,
SQ_PERF_SEL_EVENTS__SI                   = 0x0000000b,
SQ_PERF_SEL_WAVES_CU__CI__VI             = 0x0000000b,
SQ_PERF_SEL_SURF_SYNCS__SI               = 0x0000000c,
SQ_PERF_SEL_LEVEL_WAVES_CU__CI__VI       = 0x0000000c,
SQ_PERF_SEL_INSTS__SI                    = 0x0000000d,
SQ_PERF_SEL_BUSY_CU_CYCLES__CI__VI       = 0x0000000d,
SQ_PERF_SEL_INSTS_VALU__SI               = 0x0000000e,
SQ_PERF_SEL_ITEMS__CI__VI                = 0x0000000e,
SQ_PERF_SEL_INSTS_VMEM_WR__SI            = 0x0000000f,
SQ_PERF_SEL_QUADS__CI__VI                = 0x0000000f,
SQ_PERF_SEL_INSTS_VMEM_RD__SI            = 0x00000010,
SQ_PERF_SEL_EVENTS__CI__VI               = 0x00000010,
SQ_PERF_SEL_INSTS_VMEM__SI               = 0x00000011,
SQ_PERF_SEL_SURF_SYNCS__CI__VI           = 0x00000011,
SQ_PERF_SEL_INSTS_SALU__SI               = 0x00000012,
SQ_PERF_SEL_TTRACE_REQS__CI__VI          = 0x00000012,
SQ_PERF_SEL_INSTS_SMEM__SI               = 0x00000013,
SQ_PERF_SEL_TTRACE_INFLIGHT_REQS__CI__VI = 0x00000013,
SQ_PERF_SEL_INSTS_LDS__SI                = 0x00000014,
SQ_PERF_SEL_TTRACE_STALL__CI__VI         = 0x00000014,
SQ_PERF_SEL_INSTS_GDS__SI                = 0x00000015,
SQ_PERF_SEL_MSG_CNTR__CI__VI             = 0x00000015,
SQ_PERF_SEL_INSTS_EXP__SI                = 0x00000016,
SQ_PERF_SEL_MSG_PERF__CI__VI             = 0x00000016,
SQ_PERF_SEL_INSTS_BRANCH__SI             = 0x00000017,
SQ_PERF_SEL_MSG_GSCNT__CI__VI            = 0x00000017,
SQ_PERF_SEL_INSTS_SENDMSG__SI            = 0x00000018,
SQ_PERF_SEL_MSG_INTERRUPT__CI__VI        = 0x00000018,
SQ_PERF_SEL_INST_LEVEL_VMEM__SI          = 0x00000019,
SQ_PERF_SEL_INSTS__CI__VI                = 0x00000019,
SQ_PERF_SEL_INST_LEVEL_SMEM__SI          = 0x0000001a,
SQ_PERF_SEL_INSTS_VALU__CI__VI           = 0x0000001a,
SQ_PERF_SEL_INST_LEVEL_LDS__SI           = 0x0000001b,
SQ_PERF_SEL_INSTS_VMEM_WR__CI__VI        = 0x0000001b,
SQ_PERF_SEL_INST_LEVEL_GDS__SI           = 0x0000001c,
SQ_PERF_SEL_INSTS_VMEM_RD__CI__VI        = 0x0000001c,
SQ_PERF_SEL_INST_LEVEL_EXP__SI           = 0x0000001d,
SQ_PERF_SEL_INSTS_VMEM__CI__VI           = 0x0000001d,
SQ_PERF_SEL_WAIT_CNT_VM__SI              = 0x0000001e,
SQ_PERF_SEL_INSTS_SALU__CI__VI           = 0x0000001e,
SQ_PERF_SEL_WAIT_CNT_LGKM__SI            = 0x0000001f,
SQ_PERF_SEL_INSTS_SMEM__CI__VI           = 0x0000001f,
SQ_PERF_SEL_WAIT_CNT_EXP__SI             = 0x00000020,
SQ_PERF_SEL_INSTS_FLAT__CI__VI           = 0x00000020,
SQ_PERF_SEL_WAIT_CNT_ANY__SI             = 0x00000021,
SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY__CI__VI  = 0x00000021,
SQ_PERF_SEL_WAIT_BARRIER__SI             = 0x00000022,
SQ_PERF_SEL_INSTS_LDS__CI__VI            = 0x00000022,
SQ_PERF_SEL_WAIT_EXP_ALLOC__SI           = 0x00000023,
SQ_PERF_SEL_INSTS_GDS__CI__VI            = 0x00000023,
SQ_PERF_SEL_WAIT_SLEEP__SI               = 0x00000024,
SQ_PERF_SEL_INSTS_EXP__CI__VI            = 0x00000024,
SQ_PERF_SEL_WAIT_INST_VMEM__SI           = 0x00000025,
SQ_PERF_SEL_INSTS_EXP_GDS__CI__VI        = 0x00000025,
SQ_PERF_SEL_WAIT_INST_SCA__SI            = 0x00000026,
SQ_PERF_SEL_INSTS_BRANCH__CI__VI         = 0x00000026,
SQ_PERF_SEL_WAIT_INST_LDS__SI            = 0x00000027,
SQ_PERF_SEL_INSTS_SENDMSG__CI__VI        = 0x00000027,
SQ_PERF_SEL_WAIT_INST_VALU__SI           = 0x00000028,
SQ_PERF_SEL_INSTS_VSKIPPED__CI__VI       = 0x00000028,
SQ_PERF_SEL_WAIT_INST_EXP_GDS__SI        = 0x00000029,
SQ_PERF_SEL_INST_LEVEL_VMEM__CI__VI      = 0x00000029,
SQ_PERF_SEL_WAIT_INST_MISC__SI           = 0x0000002a,
SQ_PERF_SEL_INST_LEVEL_SMEM__CI__VI      = 0x0000002a,
SQ_PERF_SEL_INST_CYCLES_VMEM_WR__SI      = 0x0000002b,
SQ_PERF_SEL_INST_LEVEL_LDS__CI__VI       = 0x0000002b,
SQ_PERF_SEL_INST_CYCLES_VMEM_RD__SI      = 0x0000002c,
SQ_PERF_SEL_INST_LEVEL_GDS__CI__VI       = 0x0000002c,
SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR__SI    = 0x0000002d,
SQ_PERF_SEL_INST_LEVEL_EXP__CI__VI       = 0x0000002d,
SQ_PERF_SEL_INST_CYCLES_VMEM_DATA__SI    = 0x0000002e,
SQ_PERF_SEL_WAVE_CYCLES__CI__VI          = 0x0000002e,
SQ_PERF_SEL_INST_CYCLES_VMEM_CMD__SI     = 0x0000002f,
SQ_PERF_SEL_WAVE_READY__CI__VI           = 0x0000002f,
SQ_PERF_SEL_INST_CYCLES_VMEM__SI         = 0x00000030,
SQ_PERF_SEL_WAIT_CNT_VM__CI__VI          = 0x00000030,
SQ_PERF_SEL_INST_CYCLES_LDS__SI          = 0x00000031,
SQ_PERF_SEL_WAIT_CNT_LGKM__CI__VI        = 0x00000031,
SQ_PERF_SEL_INST_CYCLES_VALU__SI         = 0x00000032,
SQ_PERF_SEL_WAIT_CNT_EXP__CI__VI         = 0x00000032,
SQ_PERF_SEL_INST_CYCLES_EXP__SI          = 0x00000033,
SQ_PERF_SEL_WAIT_CNT_ANY__CI__VI         = 0x00000033,
SQ_PERF_SEL_INST_CYCLES_GDS__SI          = 0x00000034,
SQ_PERF_SEL_WAIT_BARRIER__CI__VI         = 0x00000034,
SQ_PERF_SEL_INST_CYCLES_SCA__SI          = 0x00000035,
SQ_PERF_SEL_WAIT_EXP_ALLOC__CI__VI       = 0x00000035,
SQ_PERF_SEL_INST_CYCLES_SMEM__SI         = 0x00000036,
SQ_PERF_SEL_WAIT_SLEEP__CI__VI           = 0x00000036,
SQ_PERF_SEL_INST_CYCLES_SALU__SI         = 0x00000037,
SQ_PERF_SEL_WAIT_OTHER__CI__VI           = 0x00000037,
SQ_PERF_SEL_INST_CYCLES_EXP_GDS__SI      = 0x00000038,
SQ_PERF_SEL_WAIT_ANY__CI__VI             = 0x00000038,
SQ_PERF_SEL_INST_CYCLES_MISC__SI         = 0x00000039,
SQ_PERF_SEL_WAIT_TTRACE__CI__VI          = 0x00000039,
SQ_PERF_SEL_THREAD_CYCLES_VALU__SI       = 0x0000003a,
SQ_PERF_SEL_WAIT_IFETCH__CI__VI          = 0x0000003a,
SQ_PERF_SEL_WAIT_INST_VMEM__CI__VI       = 0x0000003b,
SQ_PERF_SEL_VALU_LDS_DIRECT_RD__SI       = 0x0000003c,
SQ_PERF_SEL_WAIT_INST_SCA__CI__VI        = 0x0000003c,
SQ_PERF_SEL_VALU_LDS_INTERP_OP__SI       = 0x0000003d,
SQ_PERF_SEL_WAIT_INST_LDS__CI__VI        = 0x0000003d,
SQ_PERF_SEL_LDS_BANK_CONFLICT__SI        = 0x0000003e,
SQ_PERF_SEL_WAIT_INST_VALU__CI__VI       = 0x0000003e,
SQ_PERF_SEL_LDS_ADDR_CONFLICT__SI        = 0x0000003f,
SQ_PERF_SEL_WAIT_INST_EXP_GDS__CI__VI    = 0x0000003f,
SQ_PERF_SEL_VALU_DEP_STALL__SI           = 0x00000040,
SQ_PERF_SEL_WAIT_INST_MISC__CI__VI       = 0x00000040,
SQ_PERF_SEL_EXP_REQ_FIFO_FULL__SI        = 0x00000041,
SQ_PERF_SEL_WAIT_INST_FLAT__CI__VI       = 0x00000041,
SQ_PERF_SEL_LDS_BACK2BACK_STALL__SI      = 0x00000042,
SQ_PERF_SEL_ACTIVE_INST_ANY__CI__VI      = 0x00000042,
SQ_PERF_SEL_LDS_DATA_FIFO_FULL__SI       = 0x00000043,
SQ_PERF_SEL_ACTIVE_INST_VMEM__CI__VI     = 0x00000043,
SQ_PERF_SEL_LDS_CMD_FIFO_FULL__SI        = 0x00000044,
SQ_PERF_SEL_ACTIVE_INST_LDS__CI__VI      = 0x00000044,
SQ_PERF_SEL_VMEM_BACK2BACK_STALL__SI     = 0x00000045,
SQ_PERF_SEL_ACTIVE_INST_VALU__CI__VI     = 0x00000045,
SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL__SI   = 0x00000046,
SQ_PERF_SEL_ACTIVE_INST_SCA__CI__VI      = 0x00000046,
SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL__SI    = 0x00000047,
SQ_PERF_SEL_ACTIVE_INST_EXP_GDS__CI__VI  = 0x00000047,
SQ_PERF_SEL_ACTIVE_INST_MISC__CI__VI     = 0x00000048,
SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL__SI  = 0x00000049,
SQ_PERF_SEL_ACTIVE_INST_FLAT__CI__VI     = 0x00000049,
SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL__SI = 0x0000004a,
SQ_PERF_SEL_INST_CYCLES_VMEM_WR__CI__VI  = 0x0000004a,
SQ_PERF_SEL_VALU_SRC_C_CONFLICT__SI      = 0x0000004b,
SQ_PERF_SEL_INST_CYCLES_VMEM_RD__CI__VI  = 0x0000004b,
SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT__SI  = 0x0000004c,
SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR__CI__VI = 0x0000004c,
SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT__SI  = 0x0000004d,
SQ_PERF_SEL_INST_CYCLES_VMEM_DATA__CI__VI = 0x0000004d,
SQ_PERF_SEL_LDS_SRC_CD_CONFLICT__SI      = 0x0000004e,
SQ_PERF_SEL_INST_CYCLES_VMEM_CMD__CI__VI = 0x0000004e,
SQ_PERF_SEL_PT_POWER_STALL__SI           = 0x0000004f,
SQ_PERF_SEL_INST_CYCLES_VMEM__CI__VI     = 0x0000004f,
SQ_PERF_SEL_INST_CYCLES_LDS__CI__VI      = 0x00000050,
SQ_PERF_SEL_TTRACE_STALL__SI             = 0x00000051,
SQ_PERF_SEL_INST_CYCLES_VALU__CI__VI     = 0x00000051,
SQ_PERF_SEL_USER0__SI                    = 0x00000052,
SQ_PERF_SEL_INST_CYCLES_EXP__CI__VI      = 0x00000052,
SQ_PERF_SEL_USER1__SI                    = 0x00000053,
SQ_PERF_SEL_INST_CYCLES_GDS__CI__VI      = 0x00000053,
SQ_PERF_SEL_USER2__SI                    = 0x00000054,
SQ_PERF_SEL_INST_CYCLES_SCA__CI__VI      = 0x00000054,
SQ_PERF_SEL_USER3__SI                    = 0x00000055,
SQ_PERF_SEL_INST_CYCLES_SMEM__CI__VI     = 0x00000055,
SQ_PERF_SEL_USER4__SI                    = 0x00000056,
SQ_PERF_SEL_INST_CYCLES_SALU__CI__VI     = 0x00000056,
SQ_PERF_SEL_USER5__SI                    = 0x00000057,
SQ_PERF_SEL_INST_CYCLES_EXP_GDS__CI__VI  = 0x00000057,
SQ_PERF_SEL_USER6__SI                    = 0x00000058,
SQ_PERF_SEL_INST_CYCLES_MISC__CI__VI     = 0x00000058,
SQ_PERF_SEL_USER7__SI                    = 0x00000059,
SQ_PERF_SEL_THREAD_CYCLES_VALU__CI__VI   = 0x00000059,
SQ_PERF_SEL_USER8__SI                    = 0x0000005a,
SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX__CI__VI = 0x0000005a,
SQ_PERF_SEL_USER9__SI                    = 0x0000005b,
SQ_PERF_SEL_IFETCH__CI__VI               = 0x0000005b,
SQ_PERF_SEL_USER10__SI                   = 0x0000005c,
SQ_PERF_SEL_IFETCH_LEVEL__CI__VI         = 0x0000005c,
SQ_PERF_SEL_USER11__SI                   = 0x0000005d,
SQ_PERF_SEL_CBRANCH_FORK__CI__VI         = 0x0000005d,
SQ_PERF_SEL_USER12__SI                   = 0x0000005e,
SQ_PERF_SEL_CBRANCH_FORK_SPLIT__CI__VI   = 0x0000005e,
SQ_PERF_SEL_USER13__SI                   = 0x0000005f,
SQ_PERF_SEL_VALU_LDS_DIRECT_RD__CI__VI   = 0x0000005f,
SQ_PERF_SEL_USER14__SI                   = 0x00000060,
SQ_PERF_SEL_VALU_LDS_INTERP_OP__CI__VI   = 0x00000060,
SQ_PERF_SEL_USER15__SI                   = 0x00000061,
SQ_PERF_SEL_LDS_BANK_CONFLICT__CI__VI    = 0x00000061,
SQ_PERF_SEL_USER_LEVEL0__SI              = 0x00000062,
SQ_PERF_SEL_LDS_ADDR_CONFLICT__CI__VI    = 0x00000062,
SQ_PERF_SEL_USER_LEVEL1__SI              = 0x00000063,
SQ_PERF_SEL_LDS_UNALIGNED_STALL__CI__VI  = 0x00000063,
SQ_PERF_SEL_USER_LEVEL2__SI              = 0x00000064,
SQ_PERF_SEL_LDS_MEM_VIOLATIONS__CI__VI   = 0x00000064,
SQ_PERF_SEL_USER_LEVEL3__SI              = 0x00000065,
SQ_PERF_SEL_LDS_ATOMIC_RETURN__CI__VI    = 0x00000065,
SQ_PERF_SEL_USER_LEVEL4__SI              = 0x00000066,
SQ_PERF_SEL_LDS_IDX_ACTIVE__CI__VI       = 0x00000066,
SQ_PERF_SEL_USER_LEVEL5__SI              = 0x00000067,
SQ_PERF_SEL_VALU_DEP_STALL__CI__VI       = 0x00000067,
SQ_PERF_SEL_USER_LEVEL6__SI              = 0x00000068,
SQ_PERF_SEL_VALU_STARVE__CI__VI          = 0x00000068,
SQ_PERF_SEL_USER_LEVEL7__SI              = 0x00000069,
SQ_PERF_SEL_EXP_REQ_FIFO_FULL__CI__VI    = 0x00000069,
SQ_PERF_SEL_USER_LEVEL8__SI              = 0x0000006a,
SQ_PERF_SEL_LDS_BACK2BACK_STALL__CI__VI  = 0x0000006a,
SQ_PERF_SEL_USER_LEVEL9__SI              = 0x0000006b,
SQ_PERF_SEL_LDS_DATA_FIFO_FULL__CI__VI   = 0x0000006b,
SQ_PERF_SEL_USER_LEVEL10__SI             = 0x0000006c,
SQ_PERF_SEL_LDS_CMD_FIFO_FULL__CI__VI    = 0x0000006c,
SQ_PERF_SEL_USER_LEVEL11__SI             = 0x0000006d,
SQ_PERF_SEL_VMEM_BACK2BACK_STALL__CI__VI = 0x0000006d,
SQ_PERF_SEL_USER_LEVEL12__SI             = 0x0000006e,
SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL__CI__VI = 0x0000006e,
SQ_PERF_SEL_USER_LEVEL13__SI             = 0x0000006f,
SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL__CI__VI = 0x0000006f,
SQ_PERF_SEL_USER_LEVEL14__SI             = 0x00000070,
SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY__CI__VI = 0x00000070,
SQ_PERF_SEL_USER_LEVEL15__SI             = 0x00000071,
SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL__CI__VI = 0x00000071,
SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL__CI__VI = 0x00000072,
SQ_PERF_SEL_VALU_SRC_C_CONFLICT__CI__VI  = 0x00000073,
SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT__CI__VI = 0x00000074,
SQ_PERF_SEL_MSG_CNTR__SI                 = 0x00000075,
SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT__CI__VI = 0x00000075,
SQ_PERF_SEL_MSG_PERF__SI                 = 0x00000076,
SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT__CI__VI = 0x00000076,
SQ_PERF_SEL_MSG_GSCNT__SI                = 0x00000077,
SQ_PERF_SEL_LDS_SRC_CD_CONFLICT__CI__VI  = 0x00000077,
SQ_PERF_SEL_MSG_INTERRUPT__SI            = 0x00000078,
SQ_PERF_SEL_SRC_CD_BUSY__CI__VI          = 0x00000078,
SQ_PERF_SEL_PT_POWER_STALL__CI__VI       = 0x00000079,
SQ_PERF_SEL_USER0__CI__VI                = 0x0000007a,
SQ_PERF_SEL_USER1__CI__VI                = 0x0000007b,
SQ_PERF_SEL_USER2__CI__VI                = 0x0000007c,
SQ_PERF_SEL_USER3__CI__VI                = 0x0000007d,
SQ_PERF_SEL_USER4__CI__VI                = 0x0000007e,
SQ_PERF_SEL_USER5__CI__VI                = 0x0000007f,
SQ_PERF_SEL_USER6__CI__VI                = 0x00000080,
SQ_PERF_SEL_USER7__CI__VI                = 0x00000081,
SQ_PERF_SEL_USER8__CI__VI                = 0x00000082,
SQ_PERF_SEL_USER9__CI__VI                = 0x00000083,
SQ_PERF_SEL_USER10__CI__VI               = 0x00000084,
SQ_PERF_SEL_USER11__CI__VI               = 0x00000085,
SQ_PERF_SEL_USER12__CI__VI               = 0x00000086,
SQ_PERF_SEL_USER13__CI__VI               = 0x00000087,
SQ_PERF_SEL_USER14__CI__VI               = 0x00000088,
SQ_PERF_SEL_USER15__CI__VI               = 0x00000089,
SQ_PERF_SEL_USER_LEVEL0__CI__VI          = 0x0000008a,
SQ_PERF_SEL_USER_LEVEL1__CI__VI          = 0x0000008b,
SQ_PERF_SEL_USER_LEVEL2__CI__VI          = 0x0000008c,
SQ_PERF_SEL_USER_LEVEL3__CI__VI          = 0x0000008d,
SQ_PERF_SEL_USER_LEVEL4__CI__VI          = 0x0000008e,
SQ_PERF_SEL_USER_LEVEL5__CI__VI          = 0x0000008f,
SQ_PERF_SEL_USER_LEVEL6__CI__VI          = 0x00000090,
SQ_PERF_SEL_USER_LEVEL7__CI__VI          = 0x00000091,
SQ_PERF_SEL_USER_LEVEL8__CI__VI          = 0x00000092,
SQ_PERF_SEL_USER_LEVEL9__CI__VI          = 0x00000093,
SQ_PERF_SEL_USER_LEVEL10__CI__VI         = 0x00000094,
SQ_PERF_SEL_USER_LEVEL11__CI__VI         = 0x00000095,
SQ_PERF_SEL_USER_LEVEL12__CI__VI         = 0x00000096,
SQ_PERF_SEL_USER_LEVEL13__CI__VI         = 0x00000097,
SQC_PERF_SEL_TC_REQ__SI                  = 0x00000098,
SQ_PERF_SEL_USER_LEVEL14__CI__VI         = 0x00000098,
SQC_PERF_SEL_TC_STALL__SI                = 0x00000099,
SQ_PERF_SEL_USER_LEVEL15__CI__VI         = 0x00000099,
SQC_PERF_SEL_TC_STARVE__SI               = 0x0000009a,
SQ_PERF_SEL_POWER_VALU__CI__VI           = 0x0000009a,
SQC_PERF_SEL_ICACHE_BUSY_CYCLES__SI      = 0x0000009b,
SQ_PERF_SEL_POWER_VALU0__CI__VI          = 0x0000009b,
SQ_PERF_SEL_POWER_VALU1__CI__VI          = 0x0000009c,
SQC_PERF_SEL_ICACHE_REQ__SI              = 0x0000009d,
SQ_PERF_SEL_POWER_VALU2__CI__VI          = 0x0000009d,
SQ_PERF_SEL_POWER_GPR_RD__CI__VI         = 0x0000009e,
SQ_PERF_SEL_POWER_GPR_WR__CI__VI         = 0x0000009f,
SQ_PERF_SEL_POWER_LDS_BUSY__CI__VI       = 0x000000a0,
SQ_PERF_SEL_POWER_ALU_BUSY__CI__VI       = 0x000000a1,
SQ_PERF_SEL_POWER_TEX_BUSY__CI__VI       = 0x000000a2,
SQ_PERF_SEL_ACCUM_PREV_HIRES__CI__VI     = 0x000000a3,
SQ_PERF_SEL_WAVES_RESTORED__VI           = 0x000000a4,
SQ_PERF_SEL_WAVES_SAVED__VI              = 0x000000a5,
SQ_PERF_SEL_DUMMY_LAST__CI__VI           = 0x000000a7,
SQC_PERF_SEL_ICACHE_INPUT_VALID_READY__CI__VI = 0x000000a8,
SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB__CI__VI = 0x000000a9,
SQC_PERF_SEL_ICACHE_INPUT_VALIDB__CI__VI = 0x000000aa,
SQC_PERF_SEL_DCACHE_INPUT_VALID_READY__CI__VI = 0x000000ab,
SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB__CI__VI = 0x000000ac,
SQC_PERF_SEL_DCACHE_INPUT_VALIDB__CI__VI = 0x000000ad,
SQC_PERF_SEL_TC_REQ__CI__VI              = 0x000000ae,
SQC_PERF_SEL_TC_INST_REQ__CI__VI         = 0x000000af,
SQC_PERF_SEL_TC_DATA_REQ__CI             = 0x000000b0,
SQC_PERF_SEL_TC_DATA_READ_REQ__VI        = 0x000000b0,
SQC_PERF_SEL_TC_STALL__CI                = 0x000000b1,
SQC_PERF_SEL_TC_DATA_WRITE_REQ__VI       = 0x000000b1,
SQC_PERF_SEL_TC_STARVE__CI               = 0x000000b2,
SQC_PERF_SEL_TC_DATA_ATOMIC_REQ__VI      = 0x000000b2,
SQC_PERF_SEL_ICACHE_BUSY_CYCLES__CI      = 0x000000b3,
SQC_PERF_SEL_TC_STALL__VI                = 0x000000b3,
SQC_PERF_SEL_ICACHE_REQ__CI              = 0x000000b4,
SQC_PERF_SEL_TC_STARVE__VI               = 0x000000b4,
SQC_PERF_SEL_ICACHE_HITS__CI             = 0x000000b5,
SQC_PERF_SEL_ICACHE_BUSY_CYCLES__VI      = 0x000000b5,
SQC_PERF_SEL_ICACHE_HITS__SI             = 0x000000b6,
SQC_PERF_SEL_ICACHE_MISSES__CI           = 0x000000b6,
SQC_PERF_SEL_ICACHE_REQ__VI              = 0x000000b6,
SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE__CI = 0x000000b7,
SQC_PERF_SEL_ICACHE_HITS__VI             = 0x000000b7,
SQC_PERF_SEL_ICACHE_UNCACHED__CI         = 0x000000b8,
SQC_PERF_SEL_ICACHE_MISSES__VI           = 0x000000b8,
SQC_PERF_SEL_ICACHE_VOLATILE__CI         = 0x000000b9,
SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE__VI = 0x000000b9,
SQC_PERF_SEL_ICACHE_INVAL_INST__CI__VI   = 0x000000ba,
SQC_PERF_SEL_ICACHE_INVAL_ASYNC__CI__VI  = 0x000000bb,
SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_INST__CI = 0x000000bc,
SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT__VI = 0x000000bc,
SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_ASYNC__CI = 0x000000bd,
SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB__VI = 0x000000bd,
SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT__CI = 0x000000be,
SQC_PERF_SEL_ICACHE_CACHE_STALLED__VI    = 0x000000be,
SQC_PERF_SEL_ICACHE_MISSES__SI           = 0x000000bf,
SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB__CI = 0x000000bf,
SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO__VI = 0x000000bf,
SQC_PERF_SEL_ICACHE_CACHE_STALLED__CI    = 0x000000c0,
SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX__VI = 0x000000c0,
SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO__CI = 0x000000c1,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT__VI = 0x000000c1,
SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX__CI = 0x000000c2,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO__VI = 0x000000c2,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO__VI = 0x000000c3,
SQC_PERF_SEL_ICACHE_CACHE_STALL_UNCACHED_HIT__CI = 0x000000c4,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF__VI = 0x000000c4,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT__CI = 0x000000c5,
SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT__VI = 0x000000c5,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO__CI = 0x000000c6,
SQC_PERF_SEL_DCACHE_BUSY_CYCLES__VI      = 0x000000c6,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO__CI = 0x000000c7,
SQC_PERF_SEL_DCACHE_REQ__VI              = 0x000000c7,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF__CI = 0x000000c8,
SQC_PERF_SEL_DCACHE_HITS__VI             = 0x000000c8,
SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT__CI = 0x000000c9,
SQC_PERF_SEL_DCACHE_MISSES__VI           = 0x000000c9,
SQC_PERF_SEL_DCACHE_BUSY_CYCLES__CI      = 0x000000ca,
SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE__VI = 0x000000ca,
SQC_PERF_SEL_DCACHE_REQ__CI              = 0x000000cb,
SQC_PERF_SEL_DCACHE_HIT_LRU_READ__VI     = 0x000000cb,
SQC_PERF_SEL_DCACHE_HITS__CI             = 0x000000cc,
SQC_PERF_SEL_DCACHE_MISS_EVICT_READ__VI  = 0x000000cc,
SQC_PERF_SEL_DCACHE_MISSES__CI           = 0x000000cd,
SQC_PERF_SEL_DCACHE_WC_LRU_WRITE__VI     = 0x000000cd,
SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE__CI = 0x000000ce,
SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE__VI   = 0x000000ce,
SQC_PERF_SEL_DCACHE_UNCACHED__CI         = 0x000000cf,
SQC_PERF_SEL_DCACHE_ATOMIC__VI           = 0x000000cf,
SQC_PERF_SEL_DCACHE_VOLATILE__CI__VI     = 0x000000d0,
SQC_PERF_SEL_DCACHE_INVAL_INST__CI__VI   = 0x000000d1,
SQC_PERF_SEL_DCACHE_INVAL_ASYNC__CI__VI  = 0x000000d2,
SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST__CI__VI = 0x000000d3,
SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC__CI__VI = 0x000000d4,
SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT__CI = 0x000000d5,
SQC_PERF_SEL_DCACHE_WB_INST__VI          = 0x000000d5,
SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB__CI = 0x000000d6,
SQC_PERF_SEL_DCACHE_WB_ASYNC__VI         = 0x000000d6,
SQC_PERF_SEL_DCACHE_CACHE_STALLED__CI    = 0x000000d7,
SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST__VI = 0x000000d7,
SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO__CI = 0x000000d8,
SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC__VI = 0x000000d8,
SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX__CI = 0x000000d9,
SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT__VI = 0x000000d9,
SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB__VI = 0x000000da,
SQC_PERF_SEL_DCACHE_CACHE_STALL_UNCACHED_HIT__CI = 0x000000db,
SQC_PERF_SEL_DCACHE_CACHE_STALLED__VI    = 0x000000db,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT__CI = 0x000000dc,
SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX__VI = 0x000000dc,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO__CI = 0x000000dd,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT__VI = 0x000000dd,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO__CI = 0x000000de,
SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT__VI = 0x000000de,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF__CI = 0x000000df,
SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED__VI = 0x000000df,
SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT__CI = 0x000000e0,
SQC_PERF_SEL_DCACHE_REQ_1__CI            = 0x000000e1,
SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT__VI = 0x000000e1,
SQC_PERF_SEL_DCACHE_REQ_2__CI            = 0x000000e2,
SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH__VI = 0x000000e2,
SQC_PERF_SEL_DCACHE_REQ_4__CI            = 0x000000e3,
SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE__VI = 0x000000e3,
SQC_PERF_SEL_DCACHE_REQ_8__CI            = 0x000000e4,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO__VI = 0x000000e4,
SQC_PERF_SEL_DCACHE_REQ_16__CI           = 0x000000e5,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO__VI = 0x000000e5,
SQC_PERF_SEL_DCACHE_REQ_TIME__CI         = 0x000000e6,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF__VI = 0x000000e6,
SQC_PERF_SEL_SQ_DCACHE_REQS__CI          = 0x000000e7,
SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT__VI = 0x000000e7,
SQC_PERF_SEL_DCACHE_FLAT_REQ__CI         = 0x000000e8,
SQC_PERF_SEL_DCACHE_REQ_READ_1__VI       = 0x000000e8,
SQC_PERF_SEL_DCACHE_NONFLAT_REQ__CI      = 0x000000e9,
SQC_PERF_SEL_DCACHE_REQ_READ_2__VI       = 0x000000e9,
SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL__CI   = 0x000000ea,
SQC_PERF_SEL_DCACHE_REQ_READ_4__VI       = 0x000000ea,
SQC_PERF_SEL_ICACHE_PRE_CC_LEVEL__CI     = 0x000000eb,
SQC_PERF_SEL_DCACHE_REQ_READ_8__VI       = 0x000000eb,
SQC_PERF_SEL_ICACHE_POST_CC_LEVEL__CI    = 0x000000ec,
SQC_PERF_SEL_DCACHE_REQ_READ_16__VI      = 0x000000ec,
SQC_PERF_SEL_ICACHE_POST_CC_HIT_LEVEL__CI = 0x000000ed,
SQC_PERF_SEL_DCACHE_REQ_TIME__VI         = 0x000000ed,
SQC_PERF_SEL_ICACHE_POST_CC_MISS_LEVEL__CI = 0x000000ee,
SQC_PERF_SEL_DCACHE_REQ_WRITE_1__VI      = 0x000000ee,
SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL__CI   = 0x000000ef,
SQC_PERF_SEL_DCACHE_REQ_WRITE_2__VI      = 0x000000ef,
SQC_PERF_SEL_DCACHE_PRE_CC_LEVEL__CI     = 0x000000f0,
SQC_PERF_SEL_DCACHE_REQ_WRITE_4__VI      = 0x000000f0,
SQC_PERF_SEL_DCACHE_POST_CC_LEVEL__CI    = 0x000000f1,
SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE__VI    = 0x000000f1,
SQC_PERF_SEL_DCACHE_POST_CC_HIT_LEVEL__CI = 0x000000f2,
SQC_PERF_SEL_SQ_DCACHE_REQS__VI          = 0x000000f2,
SQC_PERF_SEL_DCACHE_POST_CC_MISS_LEVEL__CI = 0x000000f3,
SQC_PERF_SEL_DCACHE_FLAT_REQ__VI         = 0x000000f3,
SQC_PERF_SEL_TC_INFLIGHT_LEVEL__CI       = 0x000000f4,
SQC_PERF_SEL_DCACHE_NONFLAT_REQ__VI      = 0x000000f4,
SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL__CI = 0x000000f5,
SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL__VI   = 0x000000f5,
SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL__CI = 0x000000f6,
SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL__VI   = 0x000000f6,
SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED__CI = 0x000000f7,
SQC_PERF_SEL_TC_INFLIGHT_LEVEL__VI       = 0x000000f7,
SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED__CI = 0x000000f8,
SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL__VI = 0x000000f8,
SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED__CI = 0x000000f9,
SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL__VI = 0x000000f9,
SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS__VI = 0x000000fa,
SQC_PERF_SEL_DUMMY_LAST__CI              = 0x000000fb,
SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS__VI = 0x000000fb,
SQC_PERF_SEL_ICACHE_GATCL1_REQUEST__VI   = 0x000000fc,
SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX__VI = 0x000000fd,
SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT__VI = 0x000000fe,
SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL__VI = 0x000000ff,
SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES__VI = 0x00000100,
SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT__VI = 0x00000102,
SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL__VI = 0x00000103,
SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS__VI = 0x00000104,
SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS__VI = 0x00000105,
SQC_PERF_SEL_DCACHE_GATCL1_REQUEST__VI   = 0x00000106,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX__VI = 0x00000107,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT__VI = 0x00000108,
SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL__VI = 0x00000109,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES__VI = 0x0000010a,
SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT__VI = 0x0000010c,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL__VI = 0x0000010d,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS__VI = 0x0000010e,
SQC_PERF_SEL_DCACHE_BUSY_CYCLES__SI      = 0x0000010f,
SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL__VI = 0x0000010f,
SQC_PERF_SEL_DUMMY_LAST__VI              = 0x00000110,
SQC_PERF_SEL_DCACHE_REQ__SI              = 0x00000111,
SQ_PERF_SEL_INSTS_SMEM_NORM__VI          = 0x00000111,
SQ_PERF_SEL_ATC_INSTS_VMEM__VI           = 0x00000112,
SQ_PERF_SEL_ATC_INST_LEVEL_VMEM__VI      = 0x00000113,
SQ_PERF_SEL_ATC_XNACK_FIRST__VI          = 0x00000114,
SQ_PERF_SEL_ATC_XNACK_ALL__VI            = 0x00000115,
SQ_PERF_SEL_ATC_XNACK_FIFO_FULL__VI      = 0x00000116,
SQ_PERF_SEL_ATC_INSTS_SMEM__VI           = 0x00000117,
SQ_PERF_SEL_ATC_INST_LEVEL_SMEM__VI      = 0x00000118,
SQ_PERF_SEL_IFETCH_XNACK__VI             = 0x00000119,
SQ_PERF_SEL_TLB_SHOOTDOWN__VI            = 0x0000011a,
SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES__VI     = 0x0000011b,
SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY__VI     = 0x0000011c,
SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY__VI     = 0x0000011d,
SQ_PERF_SEL_INSTS_VMEM_REPLAY__VI        = 0x0000011e,
SQ_PERF_SEL_INSTS_SMEM_REPLAY__VI        = 0x0000011f,
SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY__VI   = 0x00000120,
SQ_PERF_SEL_INSTS_FLAT_REPLAY__VI        = 0x00000121,
SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY__VI    = 0x00000122,
SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY__VI    = 0x00000123,
SQC_PERF_SEL_DCACHE_REQ_1__SI            = 0x0000012a,
SQ_PERF_SEL_DUMMY_LAST1__VI              = 0x0000012a,
SQC_PERF_SEL_DCACHE_REQ_2__SI            = 0x0000012b,
SQC_PERF_SEL_DCACHE_REQ_4__SI            = 0x0000012c,
SQC_PERF_SEL_DCACHE_REQ_8__SI            = 0x0000012d,
SQC_PERF_SEL_DCACHE_REQ_16__SI           = 0x0000012e,
SQC_PERF_SEL_DCACHE_REQ_TIME__SI         = 0x0000012f,
SQC_PERF_SEL_DCACHE_HITS__SI             = 0x00000130,
SQC_PERF_SEL_DCACHE_MISSES__SI           = 0x00000139,
SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED__SI = 0x00000189,
SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED__SI = 0x0000018a,
SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED__SI = 0x0000018b,
} SQ_PERF_SEL;

typedef enum SQ_ROUND_MODE {
SQ_ROUND_NEAREST_EVEN                    = 0x00000000,
SQ_ROUND_PLUS_INFINITY                   = 0x00000001,
SQ_ROUND_MINUS_INFINITY                  = 0x00000002,
SQ_ROUND_TO_ZERO                         = 0x00000003,
} SQ_ROUND_MODE;

typedef enum SQ_RSRC_BUF_TYPE {
SQ_RSRC_BUF                              = 0x00000000,
SQ_RSRC_BUF_RSVD_1                       = 0x00000001,
SQ_RSRC_BUF_RSVD_2                       = 0x00000002,
SQ_RSRC_BUF_RSVD_3                       = 0x00000003,
} SQ_RSRC_BUF_TYPE;

typedef enum SQ_RSRC_FLAT_TYPE {
SQ_RSRC_FLAT_RSVD_0                      = 0x00000000,
SQ_RSRC_FLAT                             = 0x00000001,
SQ_RSRC_FLAT_RSVD_2                      = 0x00000002,
SQ_RSRC_FLAT_RSVD_3                      = 0x00000003,
} SQ_RSRC_FLAT_TYPE;

typedef enum SQ_RSRC_IMG_TYPE {
SQ_RSRC_IMG_RSVD_0                       = 0x00000000,
SQ_RSRC_IMG_RSVD_1                       = 0x00000001,
SQ_RSRC_IMG_RSVD_2                       = 0x00000002,
SQ_RSRC_IMG_RSVD_3                       = 0x00000003,
SQ_RSRC_IMG_RSVD_4                       = 0x00000004,
SQ_RSRC_IMG_RSVD_5                       = 0x00000005,
SQ_RSRC_IMG_RSVD_6                       = 0x00000006,
SQ_RSRC_IMG_RSVD_7                       = 0x00000007,
SQ_RSRC_IMG_1D                           = 0x00000008,
SQ_RSRC_IMG_2D                           = 0x00000009,
SQ_RSRC_IMG_3D                           = 0x0000000a,
SQ_RSRC_IMG_CUBE                         = 0x0000000b,
SQ_RSRC_IMG_1D_ARRAY                     = 0x0000000c,
SQ_RSRC_IMG_2D_ARRAY                     = 0x0000000d,
SQ_RSRC_IMG_2D_MSAA                      = 0x0000000e,
SQ_RSRC_IMG_2D_MSAA_ARRAY                = 0x0000000f,
} SQ_RSRC_IMG_TYPE;

typedef enum SQ_SEL_XYZW01 {
SQ_SEL_0                                 = 0x00000000,
SQ_SEL_1                                 = 0x00000001,
SQ_SEL_RESERVED_0                        = 0x00000002,
SQ_SEL_RESERVED_1                        = 0x00000003,
SQ_SEL_X                                 = 0x00000004,
SQ_SEL_Y                                 = 0x00000005,
SQ_SEL_Z                                 = 0x00000006,
SQ_SEL_W                                 = 0x00000007,
} SQ_SEL_XYZW01;

typedef enum SQ_TEX_ANISO_RATIO {
SQ_TEX_ANISO_RATIO_1                     = 0x00000000,
SQ_TEX_ANISO_RATIO_2                     = 0x00000001,
SQ_TEX_ANISO_RATIO_4                     = 0x00000002,
SQ_TEX_ANISO_RATIO_8                     = 0x00000003,
SQ_TEX_ANISO_RATIO_16                    = 0x00000004,
} SQ_TEX_ANISO_RATIO;

typedef enum SQ_TEX_BORDER_COLOR {
SQ_TEX_BORDER_COLOR_TRANS_BLACK          = 0x00000000,
SQ_TEX_BORDER_COLOR_OPAQUE_BLACK         = 0x00000001,
SQ_TEX_BORDER_COLOR_OPAQUE_WHITE         = 0x00000002,
SQ_TEX_BORDER_COLOR_REGISTER             = 0x00000003,
} SQ_TEX_BORDER_COLOR;

typedef enum SQ_TEX_CLAMP {
SQ_TEX_WRAP                              = 0x00000000,
SQ_TEX_MIRROR                            = 0x00000001,
SQ_TEX_CLAMP_LAST_TEXEL                  = 0x00000002,
SQ_TEX_MIRROR_ONCE_LAST_TEXEL            = 0x00000003,
SQ_TEX_CLAMP_HALF_BORDER                 = 0x00000004,
SQ_TEX_MIRROR_ONCE_HALF_BORDER           = 0x00000005,
SQ_TEX_CLAMP_BORDER                      = 0x00000006,
SQ_TEX_MIRROR_ONCE_BORDER                = 0x00000007,
} SQ_TEX_CLAMP;

typedef enum SQ_TEX_DEPTH_COMPARE {
SQ_TEX_DEPTH_COMPARE_NEVER               = 0x00000000,
SQ_TEX_DEPTH_COMPARE_LESS                = 0x00000001,
SQ_TEX_DEPTH_COMPARE_EQUAL               = 0x00000002,
SQ_TEX_DEPTH_COMPARE_LESSEQUAL           = 0x00000003,
SQ_TEX_DEPTH_COMPARE_GREATER             = 0x00000004,
SQ_TEX_DEPTH_COMPARE_NOTEQUAL            = 0x00000005,
SQ_TEX_DEPTH_COMPARE_GREATEREQUAL        = 0x00000006,
SQ_TEX_DEPTH_COMPARE_ALWAYS              = 0x00000007,
} SQ_TEX_DEPTH_COMPARE;

typedef enum SQ_TEX_MIP_FILTER {
SQ_TEX_MIP_FILTER_NONE                   = 0x00000000,
SQ_TEX_MIP_FILTER_POINT                  = 0x00000001,
SQ_TEX_MIP_FILTER_LINEAR                 = 0x00000002,
SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ__VI    = 0x00000003,
} SQ_TEX_MIP_FILTER;

typedef enum SQ_TEX_XY_FILTER {
SQ_TEX_XY_FILTER_POINT                   = 0x00000000,
SQ_TEX_XY_FILTER_BILINEAR                = 0x00000001,
SQ_TEX_XY_FILTER_ANISO_POINT             = 0x00000002,
SQ_TEX_XY_FILTER_ANISO_BILINEAR          = 0x00000003,
} SQ_TEX_XY_FILTER;

typedef enum SQ_TEX_Z_FILTER {
SQ_TEX_Z_FILTER_NONE                     = 0x00000000,
SQ_TEX_Z_FILTER_POINT                    = 0x00000001,
SQ_TEX_Z_FILTER_LINEAR                   = 0x00000002,
} SQ_TEX_Z_FILTER;

typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
SQ_THREAD_TRACE_CAPTURE_MODE_ALL         = 0x00000000,
SQ_THREAD_TRACE_CAPTURE_MODE_SELECT      = 0x00000001,
SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x00000002,
} SQ_THREAD_TRACE_CAPTURE_MODE;

typedef enum SQ_THREAD_TRACE_INST_TYPE {
SQ_THREAD_TRACE_INST_TYPE_SMEM__SI__CI   = 0x00000000,
SQ_THREAD_TRACE_INST_TYPE_SMEM_RD__VI    = 0x00000000,
SQ_THREAD_TRACE_INST_TYPE_SALU__SI__CI   = 0x00000001,
SQ_THREAD_TRACE_INST_TYPE_SALU_32__VI    = 0x00000001,
SQ_THREAD_TRACE_INST_TYPE_VMEM_RD__CI__VI = 0x00000002,
SQ_THREAD_TRACE_INST_TYPE_VMEM_WR__CI__VI = 0x00000003,
SQ_THREAD_TRACE_INST_TYPE_FLAT_WR__CI__VI = 0x00000004,
SQ_THREAD_TRACE_INST_TYPE_VALU__SI__CI   = 0x00000005,
SQ_THREAD_TRACE_INST_TYPE_VALU_32__VI    = 0x00000005,
SQ_THREAD_TRACE_INST_TYPE_LDS            = 0x00000006,
SQ_THREAD_TRACE_INST_TYPE_PC             = 0x00000007,
SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS     = 0x00000008,
SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX     = 0x00000009,
SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0x0000000a,
SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0x0000000b,
SQ_THREAD_TRACE_INST_TYPE_JUMP           = 0x0000000c,
SQ_THREAD_TRACE_INST_TYPE_NEXT           = 0x0000000d,
SQ_THREAD_TRACE_INST_TYPE_FLAT_RD__CI__VI = 0x0000000e,
SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG      = 0x0000000f,
SQ_THREAD_TRACE_INST_TYPE_SMEM_WR__VI    = 0x00000010,
SQ_THREAD_TRACE_INST_TYPE_SALU_64__VI    = 0x00000011,
SQ_THREAD_TRACE_INST_TYPE_VALU_64__VI    = 0x00000012,
SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY__VI = 0x00000013,
SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY__VI = 0x00000014,
SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY__VI = 0x00000015,
SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY__VI = 0x00000016,
SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY__VI = 0x00000017,
SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY__VI = 0x00000018,
} SQ_THREAD_TRACE_INST_TYPE;

typedef enum SQ_THREAD_TRACE_ISSUE {
SQ_THREAD_TRACE_ISSUE_NULL               = 0x00000000,
SQ_THREAD_TRACE_ISSUE_STALL              = 0x00000001,
SQ_THREAD_TRACE_ISSUE_INST               = 0x00000002,
SQ_THREAD_TRACE_ISSUE_IMMED              = 0x00000003,
} SQ_THREAD_TRACE_ISSUE;

typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
SQ_THREAD_TRACE_ISSUE_MASK_ALL           = 0x00000000,
SQ_THREAD_TRACE_ISSUE_MASK_STALLED       = 0x00000001,
SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x00000002,
SQ_THREAD_TRACE_ISSUE_MASK_IMMED__CI__VI = 0x00000003,
} SQ_THREAD_TRACE_ISSUE_MASK;

typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC__SI = 0x00000000,
SQ_THREAD_TRACE_MISC_TOKEN_TIME__CI__VI  = 0x00000000,
SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN__SI = 0x00000001,
SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET__CI__VI = 0x00000001,
SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END__SI = 0x00000002,
SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST__CI__VI = 0x00000002,
SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC__CI__VI = 0x00000003,
SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN__CI__VI = 0x00000004,
SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END__CI__VI = 0x00000005,
SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX__VI   = 0x00000006,
SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN__VI = 0x00000007,
} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;

typedef enum SQ_THREAD_TRACE_MODE_SEL {
SQ_THREAD_TRACE_MODE_OFF                 = 0x00000000,
SQ_THREAD_TRACE_MODE_ON                  = 0x00000001,
SQ_THREAD_TRACE_MODE_RANDOM__SI__CI      = 0x00000002,
} SQ_THREAD_TRACE_MODE_SEL;

typedef enum SQ_THREAD_TRACE_REG_OP {
SQ_THREAD_TRACE_REG_OP_READ              = 0x00000000,
SQ_THREAD_TRACE_REG_OP_WRITE             = 0x00000001,
} SQ_THREAD_TRACE_REG_OP;

typedef enum SQ_THREAD_TRACE_REG_TYPE {
SQ_THREAD_TRACE_REG_TYPE_EVENT           = 0x00000000,
SQ_THREAD_TRACE_REG_TYPE_DRAW            = 0x00000001,
SQ_THREAD_TRACE_REG_TYPE_DISPATCH        = 0x00000002,
SQ_THREAD_TRACE_REG_TYPE_USERDATA        = 0x00000003,
SQ_THREAD_TRACE_REG_TYPE_MARKER          = 0x00000004,
SQ_THREAD_TRACE_REG_TYPE_GFXDEC          = 0x00000005,
SQ_THREAD_TRACE_REG_TYPE_SHDEC           = 0x00000006,
SQ_THREAD_TRACE_REG_TYPE_OTHER           = 0x00000007,
} SQ_THREAD_TRACE_REG_TYPE;

typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
SQ_THREAD_TRACE_TOKEN_MISC__CI__VI       = 0x00000000,
SQ_THREAD_TRACE_TOKEN_TIMESTAMP          = 0x00000001,
SQ_THREAD_TRACE_TOKEN_REG                = 0x00000002,
SQ_THREAD_TRACE_TOKEN_WAVE_START         = 0x00000003,
SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC__CI__VI = 0x00000004,
SQ_THREAD_TRACE_TOKEN_REG_CSPRIV__CI__VI = 0x00000005,
SQ_THREAD_TRACE_TOKEN_WAVE_END           = 0x00000006,
SQ_THREAD_TRACE_TOKEN_EVENT              = 0x00000007,
SQ_THREAD_TRACE_TOKEN_EVENT_CS           = 0x00000008,
SQ_THREAD_TRACE_TOKEN_EVENT_GFX1         = 0x00000009,
SQ_THREAD_TRACE_TOKEN_INST               = 0x0000000a,
SQ_THREAD_TRACE_TOKEN_INST_PC            = 0x0000000b,
SQ_THREAD_TRACE_TOKEN_INST_USERDATA      = 0x0000000c,
SQ_THREAD_TRACE_TOKEN_ISSUE              = 0x0000000d,
SQ_THREAD_TRACE_TOKEN_PERF               = 0x0000000e,
SQ_THREAD_TRACE_TOKEN_MISC__SI           = 0x0000000f,
SQ_THREAD_TRACE_TOKEN_REG_CS__CI__VI     = 0x0000000f,
} SQ_THREAD_TRACE_TOKEN_TYPE;

typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
SQ_THREAD_TRACE_VM_ID_MASK_SINGLE        = 0x00000000,
SQ_THREAD_TRACE_VM_ID_MASK_ALL           = 0x00000001,
SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x00000002,
} SQ_THREAD_TRACE_VM_ID_MASK;

typedef enum SQ_THREAD_TRACE_WAVE_MASK {
SQ_THREAD_TRACE_WAVE_MASK_NONE           = 0x00000000,
SQ_THREAD_TRACE_WAVE_MASK_ALL            = 0x00000001,
SQ_THREAD_TRACE_WAVE_MASK_1_2__SI__CI    = 0x00000002,
SQ_THREAD_TRACE_WAVE_MASK_1_4__SI__CI    = 0x00000003,
SQ_THREAD_TRACE_WAVE_MASK_1_8__SI__CI    = 0x00000004,
SQ_THREAD_TRACE_WAVE_MASK_1_16__SI__CI   = 0x00000005,
SQ_THREAD_TRACE_WAVE_MASK_1_32__SI__CI   = 0x00000006,
SQ_THREAD_TRACE_WAVE_MASK_1_64__SI__CI   = 0x00000007,
} SQ_THREAD_TRACE_WAVE_MASK;

typedef enum SQ_WAVE_IB_ECC_ST {
SQ_WAVE_IB_ECC_CLEAN                     = 0x00000000,
SQ_WAVE_IB_ECC_ERR_CONTINUE              = 0x00000001,
SQ_WAVE_IB_ECC_ERR_HALT                  = 0x00000002,
SQ_WAVE_IB_ECC_WITH_ERR_MSG              = 0x00000003,
} SQ_WAVE_IB_ECC_ST;

typedef enum SQ_WAVE_TYPE {
SQ_WAVE_TYPE_PS                          = 0x00000000,
SQ_WAVE_TYPE_VS                          = 0x00000001,
SQ_WAVE_TYPE_GS                          = 0x00000002,
SQ_WAVE_TYPE_ES                          = 0x00000003,
SQ_WAVE_TYPE_HS                          = 0x00000004,
SQ_WAVE_TYPE_LS                          = 0x00000005,
SQ_WAVE_TYPE_CS                          = 0x00000006,
SQ_WAVE_TYPE_PS1                         = 0x00000007,
} SQ_WAVE_TYPE;

typedef enum SRBM_PERFCOUNT1_SEL {
SRBM_PERF_SEL_COUNT                      = 0x00000000,
SRBM_PERF_SEL_BIF_BUSY                   = 0x00000001,
SRBM_PERF_SEL_SDMA0_BUSY__CI__VI         = 0x00000003,
SRBM_PERF_SEL_IH_BUSY                    = 0x00000004,
SRBM_PERF_SEL_MCB_BUSY                   = 0x00000005,
SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY       = 0x00000006,
SRBM_PERF_SEL_MCC_BUSY                   = 0x00000007,
SRBM_PERF_SEL_MCD_BUSY                   = 0x00000008,
SRBM_PERF_SEL_CHUB_BUSY__CI__VI          = 0x00000009,
SRBM_PERF_SEL_SEM_BUSY                   = 0x0000000a,
SRBM_PERF_SEL_UVD_BUSY                   = 0x0000000b,
SRBM_PERF_SEL_VMC_BUSY                   = 0x0000000c,
SRBM_PERF_SEL_XSP_BUSY__SI__CI           = 0x0000000d,
SRBM_PERF_SEL_ODE_BUSY__VI               = 0x0000000d,
SRBM_PERF_SEL_SDMA1_BUSY__CI__VI         = 0x0000000e,
SRBM_PERF_SEL_SAMMSP_BUSY__VI            = 0x0000000f,
SRBM_PERF_SEL_VCE0_BUSY__VI              = 0x00000010,
SRBM_PERF_SEL_XDMA_BUSY                  = 0x00000011,
SRBM_PERF_SEL_ACP_BUSY__CI__VI           = 0x00000012,
SRBM_PERF_SEL_SDMA2_BUSY__VI             = 0x00000013,
SRBM_PERF_SEL_SDMA3_BUSY__VI             = 0x00000014,
SRBM_PERF_SEL_SAMSCP_BUSY__VI            = 0x00000015,
SRBM_PERF_SEL_VMC1_BUSY__VI              = 0x00000016,
SRBM_PERF_SEL_ISP_BUSY__VI               = 0x00000017,
SRBM_PERF_SEL_VCE1_BUSY__VI              = 0x00000018,
SRBM_PERF_SEL_GCATCL2_BUSY__VI           = 0x00000019,
SRBM_PERF_SEL_OSATCL2_BUSY__VI           = 0x0000001a,
SRBM_PERF_SEL_VP8_BUSY__VI               = 0x0000001b,
} SRBM_PERFCOUNT1_SEL;

typedef enum SU_PERFCNT_SEL {
PERF_PAPC_PASX_REQ                       = 0x00000000,
PERF_PAPC_PASX_DISABLE_PIPE              = 0x00000001,
PERF_PAPC_PASX_FIRST_VECTOR              = 0x00000002,
PERF_PAPC_PASX_SECOND_VECTOR             = 0x00000003,
PERF_PAPC_PASX_FIRST_DEAD                = 0x00000004,
PERF_PAPC_PASX_SECOND_DEAD               = 0x00000005,
PERF_PAPC_PASX_VTX_KILL_DISCARD          = 0x00000006,
PERF_PAPC_PASX_VTX_NAN_DISCARD           = 0x00000007,
PERF_PAPC_PA_INPUT_PRIM                  = 0x00000008,
PERF_PAPC_PA_INPUT_NULL_PRIM             = 0x00000009,
PERF_PAPC_PA_INPUT_EVENT_FLAG            = 0x0000000a,
PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT       = 0x0000000b,
PERF_PAPC_PA_INPUT_END_OF_PACKET         = 0x0000000c,
PERF_PAPC_PA_INPUT_EXTENDED_EVENT        = 0x0000000d,
PERF_PAPC_CLPR_CULL_PRIM                 = 0x0000000e,
PERF_PAPC_CLPR_VVUCP_CULL_PRIM           = 0x0000000f,
PERF_PAPC_CLPR_VV_CULL_PRIM              = 0x00000010,
PERF_PAPC_CLPR_UCP_CULL_PRIM             = 0x00000011,
PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM        = 0x00000012,
PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM         = 0x00000013,
PERF_PAPC_CLPR_CULL_TO_NULL_PRIM         = 0x00000014,
PERF_PAPC_CLPR_VVUCP_CLIP_PRIM           = 0x00000015,
PERF_PAPC_CLPR_VV_CLIP_PRIM              = 0x00000016,
PERF_PAPC_CLPR_UCP_CLIP_PRIM             = 0x00000017,
PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE      = 0x00000018,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_1          = 0x00000019,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_2          = 0x0000001a,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_3          = 0x0000001b,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_4          = 0x0000001c,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8        = 0x0000001d,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12       = 0x0000001e,
PERF_PAPC_CLPR_CLIP_PLANE_NEAR           = 0x0000001f,
PERF_PAPC_CLPR_CLIP_PLANE_FAR            = 0x00000020,
PERF_PAPC_CLPR_CLIP_PLANE_LEFT           = 0x00000021,
PERF_PAPC_CLPR_CLIP_PLANE_RIGHT          = 0x00000022,
PERF_PAPC_CLPR_CLIP_PLANE_TOP            = 0x00000023,
PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM         = 0x00000024,
PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM        = 0x00000025,
PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM     = 0x00000026,
PERF_PAPC_CLSM_NULL_PRIM                 = 0x00000027,
PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM      = 0x00000028,
PERF_PAPC_CLSM_CULL_TO_NULL_PRIM         = 0x00000029,
PERF_PAPC_CLSM_OUT_PRIM_CNT_1            = 0x0000002a,
PERF_PAPC_CLSM_OUT_PRIM_CNT_2            = 0x0000002b,
PERF_PAPC_CLSM_OUT_PRIM_CNT_3            = 0x0000002c,
PERF_PAPC_CLSM_OUT_PRIM_CNT_4            = 0x0000002d,
PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8          = 0x0000002e,
PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13         = 0x0000002f,
PERF_PAPC_CLIPGA_VTE_KILL_PRIM           = 0x00000030,
PERF_PAPC_SU_INPUT_PRIM                  = 0x00000031,
PERF_PAPC_SU_INPUT_CLIP_PRIM             = 0x00000032,
PERF_PAPC_SU_INPUT_NULL_PRIM             = 0x00000033,
PERF_PAPC_SU_INPUT_PRIM_DUAL             = 0x00000034,
PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL        = 0x00000035,
PERF_PAPC_SU_ZERO_AREA_CULL_PRIM         = 0x00000036,
PERF_PAPC_SU_BACK_FACE_CULL_PRIM         = 0x00000037,
PERF_PAPC_SU_FRONT_FACE_CULL_PRIM        = 0x00000038,
PERF_PAPC_SU_POLYMODE_FACE_CULL          = 0x00000039,
PERF_PAPC_SU_POLYMODE_BACK_CULL          = 0x0000003a,
PERF_PAPC_SU_POLYMODE_FRONT_CULL         = 0x0000003b,
PERF_PAPC_SU_POLYMODE_INVALID_FILL       = 0x0000003c,
PERF_PAPC_SU_OUTPUT_PRIM                 = 0x0000003d,
PERF_PAPC_SU_OUTPUT_CLIP_PRIM            = 0x0000003e,
PERF_PAPC_SU_OUTPUT_NULL_PRIM            = 0x0000003f,
PERF_PAPC_SU_OUTPUT_EVENT_FLAG           = 0x00000040,
PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT      = 0x00000041,
PERF_PAPC_SU_OUTPUT_END_OF_PACKET        = 0x00000042,
PERF_PAPC_SU_OUTPUT_POLYMODE_FACE        = 0x00000043,
PERF_PAPC_SU_OUTPUT_POLYMODE_BACK        = 0x00000044,
PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT       = 0x00000045,
PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE      = 0x00000046,
PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK      = 0x00000047,
PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT     = 0x00000048,
PERF_PAPC_SU_OUTPUT_PRIM_DUAL            = 0x00000049,
PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL       = 0x0000004a,
PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL        = 0x0000004b,
PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL   = 0x0000004c,
PERF_PAPC_PASX_REQ_IDLE                  = 0x0000004d,
PERF_PAPC_PASX_REQ_BUSY                  = 0x0000004e,
PERF_PAPC_PASX_REQ_STALLED               = 0x0000004f,
PERF_PAPC_PASX_REC_IDLE                  = 0x00000050,
PERF_PAPC_PASX_REC_BUSY                  = 0x00000051,
PERF_PAPC_PASX_REC_STARVED_SX            = 0x00000052,
PERF_PAPC_PASX_REC_STALLED               = 0x00000053,
PERF_PAPC_PASX_REC_STALLED_POS_MEM       = 0x00000054,
PERF_PAPC_PASX_REC_STALLED_CCGSM_IN      = 0x00000055,
PERF_PAPC_CCGSM_IDLE                     = 0x00000056,
PERF_PAPC_CCGSM_BUSY                     = 0x00000057,
PERF_PAPC_CCGSM_STALLED                  = 0x00000058,
PERF_PAPC_CLPRIM_IDLE                    = 0x00000059,
PERF_PAPC_CLPRIM_BUSY                    = 0x0000005a,
PERF_PAPC_CLPRIM_STALLED                 = 0x0000005b,
PERF_PAPC_CLPRIM_STARVED_CCGSM           = 0x0000005c,
PERF_PAPC_CLIPSM_IDLE                    = 0x0000005d,
PERF_PAPC_CLIPSM_BUSY                    = 0x0000005e,
PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH     = 0x0000005f,
PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ       = 0x00000060,
PERF_PAPC_CLIPSM_WAIT_CLIPGA             = 0x00000061,
PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP     = 0x00000062,
PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM         = 0x00000063,
PERF_PAPC_CLIPGA_IDLE                    = 0x00000064,
PERF_PAPC_CLIPGA_BUSY                    = 0x00000065,
PERF_PAPC_CLIPGA_STARVED_VTE_CLIP        = 0x00000066,
PERF_PAPC_CLIPGA_STALLED                 = 0x00000067,
PERF_PAPC_CLIP_IDLE                      = 0x00000068,
PERF_PAPC_CLIP_BUSY                      = 0x00000069,
PERF_PAPC_SU_IDLE                        = 0x0000006a,
PERF_PAPC_SU_BUSY                        = 0x0000006b,
PERF_PAPC_SU_STARVED_CLIP                = 0x0000006c,
PERF_PAPC_SU_STALLED_SC                  = 0x0000006d,
PERF_PAPC_CL_DYN_SCLK_VLD                = 0x0000006e,
PERF_PAPC_SU_DYN_SCLK_VLD                = 0x0000006f,
PERF_PAPC_PA_REG_SCLK_VLD                = 0x00000070,
PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL  = 0x00000071,
PERF_PAPC_PASX_SE0_REQ                   = 0x00000072,
PERF_PAPC_PASX_SE1_REQ                   = 0x00000073,
PERF_PAPC_PASX_SE0_FIRST_VECTOR          = 0x00000074,
PERF_PAPC_PASX_SE0_SECOND_VECTOR         = 0x00000075,
PERF_PAPC_PASX_SE1_FIRST_VECTOR          = 0x00000076,
PERF_PAPC_PASX_SE1_SECOND_VECTOR         = 0x00000077,
PERF_PAPC_SU_SE0_PRIM_FILTER_CULL        = 0x00000078,
PERF_PAPC_SU_SE1_PRIM_FILTER_CULL        = 0x00000079,
PERF_PAPC_SU_SE01_PRIM_FILTER_CULL       = 0x0000007a,
PERF_PAPC_SU_SE0_OUTPUT_PRIM             = 0x0000007b,
PERF_PAPC_SU_SE1_OUTPUT_PRIM             = 0x0000007c,
PERF_PAPC_SU_SE01_OUTPUT_PRIM            = 0x0000007d,
PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM        = 0x0000007e,
PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM        = 0x0000007f,
PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM       = 0x00000080,
PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT  = 0x00000081,
PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT  = 0x00000082,
PERF_PAPC_SU_SE0_STALLED_SC              = 0x00000083,
PERF_PAPC_SU_SE1_STALLED_SC              = 0x00000084,
PERF_PAPC_SU_SE01_STALLED_SC             = 0x00000085,
PERF_PAPC_CLSM_CLIPPING_PRIM             = 0x00000086,
PERF_PAPC_SU_CULLED_PRIM                 = 0x00000087,
PERF_PAPC_SU_OUTPUT_EOPG__CI__VI         = 0x00000088,
PERF_PAPC_SU_SE2_PRIM_FILTER_CULL__CI__VI = 0x00000089,
PERF_PAPC_SU_SE3_PRIM_FILTER_CULL__CI__VI = 0x0000008a,
PERF_PAPC_SU_SE2_OUTPUT_PRIM__CI__VI     = 0x0000008b,
PERF_PAPC_SU_SE3_OUTPUT_PRIM__CI__VI     = 0x0000008c,
PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM__CI__VI = 0x0000008d,
PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM__CI__VI = 0x0000008e,
PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET__CI__VI = 0x0000008f,
PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET__CI__VI = 0x00000090,
PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET__CI__VI = 0x00000091,
PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET__CI__VI = 0x00000092,
PERF_PAPC_SU_SE0_OUTPUT_EOPG__CI__VI     = 0x00000093,
PERF_PAPC_SU_SE1_OUTPUT_EOPG__CI__VI     = 0x00000094,
PERF_PAPC_SU_SE2_OUTPUT_EOPG__CI__VI     = 0x00000095,
PERF_PAPC_SU_SE3_OUTPUT_EOPG__CI__VI     = 0x00000096,
PERF_PAPC_SU_SE2_STALLED_SC__CI__VI      = 0x00000097,
PERF_PAPC_SU_SE3_STALLED_SC__CI__VI      = 0x00000098,
} SU_PERFCNT_SEL;

typedef enum SampleSplit {
ADDR_SURF_SAMPLE_SPLIT_1                 = 0x00000000,
ADDR_SURF_SAMPLE_SPLIT_2                 = 0x00000001,
ADDR_SURF_SAMPLE_SPLIT_4                 = 0x00000002,
ADDR_SURF_SAMPLE_SPLIT_8                 = 0x00000003,
} SampleSplit;

typedef enum SampleSplitBytes {
CONFIG_1KB_SPLIT                         = 0x00000000,
CONFIG_2KB_SPLIT                         = 0x00000001,
CONFIG_4KB_SPLIT                         = 0x00000002,
CONFIG_8KB_SPLIT                         = 0x00000003,
} SampleSplitBytes;

typedef enum ScMap {
RASTER_CONFIG_SC_MAP_0                   = 0x00000000,
RASTER_CONFIG_SC_MAP_1                   = 0x00000001,
RASTER_CONFIG_SC_MAP_2                   = 0x00000002,
RASTER_CONFIG_SC_MAP_3                   = 0x00000003,
} ScMap;

typedef enum ScXsel {
RASTER_CONFIG_SC_XSEL_8_WIDE_TILE        = 0x00000000,
RASTER_CONFIG_SC_XSEL_16_WIDE_TILE       = 0x00000001,
RASTER_CONFIG_SC_XSEL_32_WIDE_TILE       = 0x00000002,
RASTER_CONFIG_SC_XSEL_64_WIDE_TILE       = 0x00000003,
} ScXsel;

typedef enum ScYsel {
RASTER_CONFIG_SC_YSEL_8_WIDE_TILE        = 0x00000000,
RASTER_CONFIG_SC_YSEL_16_WIDE_TILE       = 0x00000001,
RASTER_CONFIG_SC_YSEL_32_WIDE_TILE       = 0x00000002,
RASTER_CONFIG_SC_YSEL_64_WIDE_TILE       = 0x00000003,
} ScYsel;

typedef enum SeMap {
RASTER_CONFIG_SE_MAP_0                   = 0x00000000,
RASTER_CONFIG_SE_MAP_1                   = 0x00000001,
RASTER_CONFIG_SE_MAP_2                   = 0x00000002,
RASTER_CONFIG_SE_MAP_3                   = 0x00000003,
} SeMap;

typedef enum SePairMap {
RASTER_CONFIG_SE_PAIR_MAP_0              = 0x00000000,
RASTER_CONFIG_SE_PAIR_MAP_1              = 0x00000001,
RASTER_CONFIG_SE_PAIR_MAP_2              = 0x00000002,
RASTER_CONFIG_SE_PAIR_MAP_3              = 0x00000003,
} SePairMap;

typedef enum SePairXsel {
RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE   = 0x00000000,
RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE  = 0x00000001,
RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE  = 0x00000002,
RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE  = 0x00000003,
} SePairXsel;

typedef enum SePairYsel {
RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE   = 0x00000000,
RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE  = 0x00000001,
RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE  = 0x00000002,
RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE  = 0x00000003,
} SePairYsel;

typedef enum SeXsel {
RASTER_CONFIG_SE_XSEL_8_WIDE_TILE        = 0x00000000,
RASTER_CONFIG_SE_XSEL_16_WIDE_TILE       = 0x00000001,
RASTER_CONFIG_SE_XSEL_32_WIDE_TILE       = 0x00000002,
RASTER_CONFIG_SE_XSEL_64_WIDE_TILE       = 0x00000003,
} SeXsel;

typedef enum SeYsel {
RASTER_CONFIG_SE_YSEL_8_WIDE_TILE        = 0x00000000,
RASTER_CONFIG_SE_YSEL_16_WIDE_TILE       = 0x00000001,
RASTER_CONFIG_SE_YSEL_32_WIDE_TILE       = 0x00000002,
RASTER_CONFIG_SE_YSEL_64_WIDE_TILE       = 0x00000003,
} SeYsel;

typedef enum ShaderEngineTileSize {
ADDR_CONFIG_SE_TILE_16                   = 0x00000000,
ADDR_CONFIG_SE_TILE_32                   = 0x00000001,
} ShaderEngineTileSize;

typedef enum SourceFormat {
EXPORT_4C_32BPC                          = 0x00000000,
EXPORT_4C_16BPC                          = 0x00000001,
EXPORT_2C_32BPC_GR                       = 0x00000002,
EXPORT_2C_32BPC_AR                       = 0x00000003,
} SourceFormat;

typedef enum StencilFormat {
STENCIL_INVALID                          = 0x00000000,
STENCIL_8                                = 0x00000001,
} StencilFormat;

typedef enum StencilOp {
STENCIL_KEEP                             = 0x00000000,
STENCIL_ZERO                             = 0x00000001,
STENCIL_ONES                             = 0x00000002,
STENCIL_REPLACE_TEST                     = 0x00000003,
STENCIL_REPLACE_OP                       = 0x00000004,
STENCIL_ADD_CLAMP                        = 0x00000005,
STENCIL_SUB_CLAMP                        = 0x00000006,
STENCIL_INVERT                           = 0x00000007,
STENCIL_ADD_WRAP                         = 0x00000008,
STENCIL_SUB_WRAP                         = 0x00000009,
STENCIL_AND                              = 0x0000000a,
STENCIL_OR                               = 0x0000000b,
STENCIL_XOR                              = 0x0000000c,
STENCIL_NAND                             = 0x0000000d,
STENCIL_NOR                              = 0x0000000e,
STENCIL_XNOR                             = 0x0000000f,
} StencilOp;

typedef enum SurfaceArray {
ARRAY_1D                                 = 0x00000000,
ARRAY_2D                                 = 0x00000001,
ARRAY_3D                                 = 0x00000002,
ARRAY_3D_SLICE                           = 0x00000003,
} SurfaceArray;

typedef enum SurfaceEndian {
ENDIAN_NONE                              = 0x00000000,
ENDIAN_8IN16                             = 0x00000001,
ENDIAN_8IN32                             = 0x00000002,
ENDIAN_8IN64                             = 0x00000003,
} SurfaceEndian;

typedef enum SurfaceFormat {
FMT_INVALID                              = 0x00000000,
FMT_8                                    = 0x00000001,
FMT_16                                   = 0x00000002,
FMT_8_8                                  = 0x00000003,
FMT_32                                   = 0x00000004,
FMT_16_16                                = 0x00000005,
FMT_10_11_11                             = 0x00000006,
FMT_11_11_10                             = 0x00000007,
FMT_10_10_10_2                           = 0x00000008,
FMT_2_10_10_10                           = 0x00000009,
FMT_8_8_8_8                              = 0x0000000a,
FMT_32_32                                = 0x0000000b,
FMT_16_16_16_16                          = 0x0000000c,
FMT_32_32_32                             = 0x0000000d,
FMT_32_32_32_32                          = 0x0000000e,
FMT_RESERVED_4                           = 0x0000000f,
FMT_5_6_5                                = 0x00000010,
FMT_1_5_5_5                              = 0x00000011,
FMT_5_5_5_1                              = 0x00000012,
FMT_4_4_4_4                              = 0x00000013,
FMT_8_24                                 = 0x00000014,
FMT_24_8                                 = 0x00000015,
FMT_X24_8_32_FLOAT                       = 0x00000016,
FMT_RESERVED_33                          = 0x00000017,
FMT_11_11_10_FLOAT                       = 0x00000018,
FMT_16_FLOAT                             = 0x00000019,
FMT_32_FLOAT                             = 0x0000001a,
FMT_16_16_FLOAT                          = 0x0000001b,
FMT_8_24_FLOAT                           = 0x0000001c,
FMT_24_8_FLOAT                           = 0x0000001d,
FMT_32_32_FLOAT                          = 0x0000001e,
FMT_10_11_11_FLOAT                       = 0x0000001f,
FMT_16_16_16_16_FLOAT                    = 0x00000020,
FMT_3_3_2                                = 0x00000021,
FMT_6_5_5                                = 0x00000022,
FMT_32_32_32_32_FLOAT                    = 0x00000023,
FMT_RESERVED_36                          = 0x00000024,
FMT_1                                    = 0x00000025,
FMT_1_REVERSED                           = 0x00000026,
FMT_GB_GR                                = 0x00000027,
FMT_BG_RG                                = 0x00000028,
FMT_32_AS_8                              = 0x00000029,
FMT_32_AS_8_8                            = 0x0000002a,
FMT_5_9_9_9_SHAREDEXP                    = 0x0000002b,
FMT_8_8_8                                = 0x0000002c,
FMT_16_16_16                             = 0x0000002d,
FMT_16_16_16_FLOAT                       = 0x0000002e,
FMT_4_4                                  = 0x0000002f,
FMT_32_32_32_FLOAT                       = 0x00000030,
FMT_BC1                                  = 0x00000031,
FMT_BC2                                  = 0x00000032,
FMT_BC3                                  = 0x00000033,
FMT_BC4                                  = 0x00000034,
FMT_BC5                                  = 0x00000035,
FMT_BC6                                  = 0x00000036,
FMT_BC7                                  = 0x00000037,
FMT_32_AS_32_32_32_32                    = 0x00000038,
FMT_APC3                                 = 0x00000039,
FMT_APC4                                 = 0x0000003a,
FMT_APC5                                 = 0x0000003b,
FMT_APC6                                 = 0x0000003c,
FMT_APC7                                 = 0x0000003d,
FMT_CTX1                                 = 0x0000003e,
FMT_RESERVED_63                          = 0x0000003f,
} SurfaceFormat;

typedef enum SurfaceNumber {
NUMBER_UNORM                             = 0x00000000,
NUMBER_SNORM                             = 0x00000001,
NUMBER_USCALED                           = 0x00000002,
NUMBER_SSCALED                           = 0x00000003,
NUMBER_UINT                              = 0x00000004,
NUMBER_SINT                              = 0x00000005,
NUMBER_SRGB                              = 0x00000006,
NUMBER_FLOAT                             = 0x00000007,
} SurfaceNumber;

typedef enum SurfaceSwap {
SWAP_STD                                 = 0x00000000,
SWAP_ALT                                 = 0x00000001,
SWAP_STD_REV                             = 0x00000002,
SWAP_ALT_REV                             = 0x00000003,
} SurfaceSwap;

typedef enum SurfaceTiling {
ARRAY_LINEAR                             = 0x00000000,
ARRAY_TILED                              = 0x00000001,
} SurfaceTiling;

typedef enum TA_PERFCOUNT_SEL {
TA_PERF_SEL_ta_busy__SI__CI              = 0x00000000,
TA_PERF_SEL_NULL__VI                     = 0x00000000,
TA_PERF_SEL_sh_fifo_busy                 = 0x00000001,
TA_PERF_SEL_sh_fifo_cmd_busy             = 0x00000002,
TA_PERF_SEL_sh_fifo_addr_busy            = 0x00000003,
TA_PERF_SEL_sh_fifo_data_busy            = 0x00000004,
TA_PERF_SEL_sh_fifo_data_sfifo_busy      = 0x00000005,
TA_PERF_SEL_sh_fifo_data_tfifo_busy      = 0x00000006,
TA_PERF_SEL_gradient_busy                = 0x00000007,
TA_PERF_SEL_gradient_fifo_busy           = 0x00000008,
TA_PERF_SEL_lod_busy                     = 0x00000009,
TA_PERF_SEL_lod_fifo_busy                = 0x0000000a,
TA_PERF_SEL_addresser_busy               = 0x0000000b,
TA_PERF_SEL_addresser_fifo_busy          = 0x0000000c,
TA_PERF_SEL_aligner_busy                 = 0x0000000d,
TA_PERF_SEL_write_path_busy              = 0x0000000e,
TA_PERF_SEL_RESERVED_15__SI__CI          = 0x0000000f,
TA_PERF_SEL_ta_busy__VI                  = 0x0000000f,
TA_PERF_SEL_sq_ta_cmd_cycles             = 0x00000010,
TA_PERF_SEL_sp_ta_addr_cycles            = 0x00000011,
TA_PERF_SEL_sp_ta_data_cycles            = 0x00000012,
TA_PERF_SEL_ta_fa_data_state_cycles      = 0x00000013,
TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014,
TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015,
TA_PERF_SEL_RESERVED_28                  = 0x0000001c,
TA_PERF_SEL_RESERVED_29                  = 0x0000001d,
TA_PERF_SEL_sh_fifo_addr_cycles          = 0x0000001e,
TA_PERF_SEL_sh_fifo_data_cycles          = 0x0000001f,
TA_PERF_SEL_total_wavefronts             = 0x00000020,
TA_PERF_SEL_gradient_cycles              = 0x00000021,
TA_PERF_SEL_walker_cycles                = 0x00000022,
TA_PERF_SEL_aligner_cycles               = 0x00000023,
TA_PERF_SEL_image_wavefronts             = 0x00000024,
TA_PERF_SEL_image_read_wavefronts        = 0x00000025,
TA_PERF_SEL_image_write_wavefronts       = 0x00000026,
TA_PERF_SEL_image_atomic_wavefronts      = 0x00000027,
TA_PERF_SEL_image_total_cycles           = 0x00000028,
TA_PERF_SEL_RESERVED_41                  = 0x00000029,
TA_PERF_SEL_RESERVED_42                  = 0x0000002a,
TA_PERF_SEL_RESERVED_43                  = 0x0000002b,
TA_PERF_SEL_buffer_wavefronts            = 0x0000002c,
TA_PERF_SEL_buffer_read_wavefronts       = 0x0000002d,
TA_PERF_SEL_buffer_write_wavefronts      = 0x0000002e,
TA_PERF_SEL_buffer_atomic_wavefronts     = 0x0000002f,
TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030,
TA_PERF_SEL_buffer_total_cycles          = 0x00000031,
TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034,
TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035,
TA_PERF_SEL_addr_stalled_by_tc_cycles    = 0x00000036,
TA_PERF_SEL_addr_stalled_by_td_cycles    = 0x00000037,
TA_PERF_SEL_data_stalled_by_tc_cycles    = 0x00000038,
TA_PERF_SEL_addresser_stalled_cycles     = 0x0000003a,
TA_PERF_SEL_aniso_stalled_cycles         = 0x0000003c,
TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d,
TA_PERF_SEL_deriv_stalled_cycles         = 0x0000003e,
TA_PERF_SEL_aniso_gt1_cycle_quads__CI__VI = 0x0000003f,
TA_PERF_SEL_color_1_cycle_pixels         = 0x00000040,
TA_PERF_SEL_color_2_cycle_pixels         = 0x00000041,
TA_PERF_SEL_color_3_cycle_pixels         = 0x00000042,
TA_PERF_SEL_color_4_cycle_pixels         = 0x00000043,
TA_PERF_SEL_mip_1_cycle_pixels           = 0x00000044,
TA_PERF_SEL_mip_2_cycle_pixels           = 0x00000045,
TA_PERF_SEL_vol_1_cycle_pixels           = 0x00000046,
TA_PERF_SEL_vol_2_cycle_pixels           = 0x00000047,
TA_PERF_SEL_bilin_point_1_cycle_pixels   = 0x00000048,
TA_PERF_SEL_mipmap_lod_0_samples         = 0x00000049,
TA_PERF_SEL_mipmap_lod_1_samples         = 0x0000004a,
TA_PERF_SEL_mipmap_lod_2_samples         = 0x0000004b,
TA_PERF_SEL_mipmap_lod_3_samples         = 0x0000004c,
TA_PERF_SEL_mipmap_lod_4_samples         = 0x0000004d,
TA_PERF_SEL_mipmap_lod_5_samples         = 0x0000004e,
TA_PERF_SEL_mipmap_lod_6_samples         = 0x0000004f,
TA_PERF_SEL_mipmap_lod_7_samples         = 0x00000050,
TA_PERF_SEL_mipmap_lod_8_samples         = 0x00000051,
TA_PERF_SEL_mipmap_lod_9_samples         = 0x00000052,
TA_PERF_SEL_mipmap_lod_10_samples        = 0x00000053,
TA_PERF_SEL_mipmap_lod_11_samples        = 0x00000054,
TA_PERF_SEL_mipmap_lod_12_samples        = 0x00000055,
TA_PERF_SEL_mipmap_lod_13_samples        = 0x00000056,
TA_PERF_SEL_mipmap_lod_14_samples        = 0x00000057,
TA_PERF_SEL_mipmap_invalid_samples       = 0x00000058,
TA_PERF_SEL_aniso_1_cycle_quads          = 0x00000059,
TA_PERF_SEL_aniso_2_cycle_quads          = 0x0000005a,
TA_PERF_SEL_aniso_4_cycle_quads          = 0x0000005b,
TA_PERF_SEL_aniso_6_cycle_quads          = 0x0000005c,
TA_PERF_SEL_aniso_8_cycle_quads          = 0x0000005d,
TA_PERF_SEL_aniso_10_cycle_quads         = 0x0000005e,
TA_PERF_SEL_aniso_12_cycle_quads         = 0x0000005f,
TA_PERF_SEL_aniso_14_cycle_quads         = 0x00000060,
TA_PERF_SEL_aniso_16_cycle_quads         = 0x00000061,
TA_PERF_SEL_write_path_input_cycles      = 0x00000062,
TA_PERF_SEL_write_path_output_cycles     = 0x00000063,
TA_PERF_SEL_reg_sclk_vld__SI             = 0x00000064,
TA_PERF_SEL_flat_wavefronts__CI__VI      = 0x00000064,
TA_PERF_SEL_local_cg_dyn_sclk_grp0_en__SI = 0x00000065,
TA_PERF_SEL_flat_read_wavefronts__CI__VI = 0x00000065,
TA_PERF_SEL_local_cg_dyn_sclk_grp1_en__SI = 0x00000066,
TA_PERF_SEL_flat_write_wavefronts__CI__VI = 0x00000066,
TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en__SI = 0x00000067,
TA_PERF_SEL_flat_atomic_wavefronts__CI__VI = 0x00000067,
TA_PERF_SEL_local_cg_dyn_sclk_grp4_en__SI = 0x00000068,
TA_PERF_SEL_flat_coalesceable_wavefronts__CI__VI = 0x00000068,
TA_PERF_SEL_local_cg_dyn_sclk_grp5_en__SI = 0x00000069,
TA_PERF_SEL_reg_sclk_vld__CI__VI         = 0x00000069,
TA_PERF_SEL_local_cg_dyn_sclk_grp0_en__CI__VI = 0x0000006a,
TA_PERF_SEL_local_cg_dyn_sclk_grp1_en__CI__VI = 0x0000006b,
TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en__CI__VI = 0x0000006c,
TA_PERF_SEL_local_cg_dyn_sclk_grp4_en__CI__VI = 0x0000006d,
TA_PERF_SEL_local_cg_dyn_sclk_grp5_en__CI__VI = 0x0000006e,
TA_PERF_SEL_xnack_on_phase0__VI          = 0x0000006f,
TA_PERF_SEL_xnack_on_phase1__VI          = 0x00000070,
TA_PERF_SEL_xnack_on_phase2__VI          = 0x00000071,
TA_PERF_SEL_xnack_on_phase3__VI          = 0x00000072,
TA_PERF_SEL_first_xnack_on_phase0__VI    = 0x00000073,
TA_PERF_SEL_first_xnack_on_phase1__VI    = 0x00000074,
TA_PERF_SEL_first_xnack_on_phase2__VI    = 0x00000075,
TA_PERF_SEL_first_xnack_on_phase3__VI    = 0x00000076,
} TA_PERFCOUNT_SEL;

typedef enum TA_TC_ADDR_MODES {
TA_TC_ADDR_MODE_DEFAULT                  = 0x00000000,
TA_TC_ADDR_MODE_COMP0                    = 0x00000001,
TA_TC_ADDR_MODE_COMP1                    = 0x00000002,
TA_TC_ADDR_MODE_COMP2                    = 0x00000003,
TA_TC_ADDR_MODE_COMP3                    = 0x00000004,
TA_TC_ADDR_MODE_UNALIGNED                = 0x00000005,
TA_TC_ADDR_MODE_BORDER_COLOR             = 0x00000006,
} TA_TC_ADDR_MODES;

typedef enum TCA_PERF_SEL {
TCA_PERF_SEL_NONE                        = 0x00000000,
TCA_PERF_SEL_CYCLE                       = 0x00000001,
TCA_PERF_SEL_BUSY                        = 0x00000002,
TCA_PERF_SEL_FORCED_HOLE_TCC0            = 0x00000003,
TCA_PERF_SEL_FORCED_HOLE_TCC1            = 0x00000004,
TCA_PERF_SEL_FORCED_HOLE_TCC2            = 0x00000005,
TCA_PERF_SEL_FORCED_HOLE_TCC3            = 0x00000006,
TCA_PERF_SEL_FORCED_HOLE_TCC4            = 0x00000007,
TCA_PERF_SEL_FORCED_HOLE_TCC5            = 0x00000008,
TCA_PERF_SEL_FORCED_HOLE_TCC6            = 0x00000009,
TCA_PERF_SEL_FORCED_HOLE_TCC7            = 0x0000000a,
TCA_PERF_SEL_REQ_TCC0                    = 0x0000000b,
TCA_PERF_SEL_REQ_TCC1                    = 0x0000000c,
TCA_PERF_SEL_REQ_TCC2                    = 0x0000000d,
TCA_PERF_SEL_REQ_TCC3                    = 0x0000000e,
TCA_PERF_SEL_REQ_TCC4                    = 0x0000000f,
TCA_PERF_SEL_REQ_TCC5                    = 0x00000010,
TCA_PERF_SEL_REQ_TCC6                    = 0x00000011,
TCA_PERF_SEL_REQ_TCC7                    = 0x00000012,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0    = 0x00000013,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1    = 0x00000014,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2    = 0x00000015,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3    = 0x00000016,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4    = 0x00000017,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5    = 0x00000018,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6    = 0x00000019,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7    = 0x0000001a,
TCA_PERF_SEL_CROSSBAR_STALL_TCC0         = 0x0000001b,
TCA_PERF_SEL_CROSSBAR_STALL_TCC1         = 0x0000001c,
TCA_PERF_SEL_CROSSBAR_STALL_TCC2         = 0x0000001d,
TCA_PERF_SEL_CROSSBAR_STALL_TCC3         = 0x0000001e,
TCA_PERF_SEL_CROSSBAR_STALL_TCC4         = 0x0000001f,
TCA_PERF_SEL_CROSSBAR_STALL_TCC5         = 0x00000020,
TCA_PERF_SEL_CROSSBAR_STALL_TCC6         = 0x00000021,
TCA_PERF_SEL_CROSSBAR_STALL_TCC7         = 0x00000022,
TCA_PERF_SEL_FORCED_HOLE_TCS__CI         = 0x00000023,
TCA_PERF_SEL_REQ_TCS__CI                 = 0x00000024,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCS__CI = 0x00000025,
TCA_PERF_SEL_CROSSBAR_STALL_TCS__CI      = 0x00000026,
} TCA_PERF_SEL;

typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU                     = 0x00000000,
TCC_CACHE_POLICY_STREAM                  = 0x00000001,
TCC_CACHE_POLICY_BYPASS__SI__CI          = 0x00000002,
} TCC_CACHE_POLICIES;

typedef enum TCC_PERF_SEL {
TCC_PERF_SEL_NONE                        = 0x00000000,
TCC_PERF_SEL_CYCLE                       = 0x00000001,
TCC_PERF_SEL_BUSY                        = 0x00000002,
TCC_PERF_SEL_REQ                         = 0x00000003,
TCC_PERF_SEL_STREAMING_REQ               = 0x00000004,
TCC_PERF_SEL_READ__SI__CI                = 0x00000005,
TCC_PERF_SEL_EXE_REQ__VI                 = 0x00000005,
TCC_PERF_SEL_WRITE__SI__CI               = 0x00000006,
TCC_PERF_SEL_COMPRESSED_REQ__VI          = 0x00000006,
TCC_PERF_SEL_ATOMIC__SI__CI              = 0x00000007,
TCC_PERF_SEL_COMPRESSED_0_REQ__VI        = 0x00000007,
TCC_PERF_SEL_WBINVL2__SI__CI             = 0x00000008,
TCC_PERF_SEL_METADATA_REQ__VI            = 0x00000008,
TCC_PERF_SEL_WBINVL2_CYCLE__SI__CI       = 0x00000009,
TCC_PERF_SEL_NC_VIRTUAL_REQ__VI          = 0x00000009,
TCC_PERF_SEL_HIT__SI__CI                 = 0x0000000a,
TCC_PERF_SEL_NC_PHYSICAL_REQ__VI         = 0x0000000a,
TCC_PERF_SEL_MISS__SI__CI                = 0x0000000b,
TCC_PERF_SEL_UC_VIRTUAL_REQ__VI          = 0x0000000b,
TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT__SI__CI = 0x0000000c,
TCC_PERF_SEL_UC_PHYSICAL_REQ__VI         = 0x0000000c,
TCC_PERF_SEL_FULLY_WRITTEN_HIT__SI__CI   = 0x0000000d,
TCC_PERF_SEL_CC_PHYSICAL_REQ__VI         = 0x0000000d,
TCC_PERF_SEL_WRITEBACK__SI__CI           = 0x0000000e,
TCC_PERF_SEL_PROBE__VI                   = 0x0000000e,
TCC_PERF_SEL_LATENCY_FIFO_FULL__SI__CI   = 0x0000000f,
TCC_PERF_SEL_READ__VI                    = 0x0000000f,
TCC_PERF_SEL_SRC_FIFO_FULL__SI__CI       = 0x00000010,
TCC_PERF_SEL_WRITE__VI                   = 0x00000010,
TCC_PERF_SEL_HOLE_FIFO_FULL__SI__CI      = 0x00000011,
TCC_PERF_SEL_ATOMIC__VI                  = 0x00000011,
TCC_PERF_SEL_MC_WRREQ__SI__CI            = 0x00000012,
TCC_PERF_SEL_HIT__VI                     = 0x00000012,
TCC_PERF_SEL_MC_WRREQ_STALL__SI__CI      = 0x00000013,
TCC_PERF_SEL_MISS__VI                    = 0x00000013,
TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL__SI__CI = 0x00000014,
TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT__VI    = 0x00000014,
TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL__SI__CI = 0x00000015,
TCC_PERF_SEL_FULLY_WRITTEN_HIT__VI       = 0x00000015,
TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL__SI__CI = 0x00000016,
TCC_PERF_SEL_WRITEBACK__VI               = 0x00000016,
TCC_PERF_SEL_MC_WRREQ_LEVEL__SI__CI      = 0x00000017,
TCC_PERF_SEL_LATENCY_FIFO_FULL__VI       = 0x00000017,
TCC_PERF_SEL_MC_RDREQ__SI__CI            = 0x00000018,
TCC_PERF_SEL_SRC_FIFO_FULL__VI           = 0x00000018,
TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL__SI__CI = 0x00000019,
TCC_PERF_SEL_HOLE_FIFO_FULL__VI          = 0x00000019,
TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL__SI__CI = 0x0000001a,
TCC_PERF_SEL_MC_WRREQ__VI                = 0x0000001a,
TCC_PERF_SEL_MC_RDREQ_LEVEL__SI__CI      = 0x0000001b,
TCC_PERF_SEL_MC_WRREQ_UNCACHED__VI       = 0x0000001b,
TCC_PERF_SEL_TAG_STALL__SI__CI           = 0x0000001c,
TCC_PERF_SEL_MC_WRREQ_STALL__VI          = 0x0000001c,
TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL__SI__CI = 0x0000001d,
TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL__VI   = 0x0000001d,
TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL__SI__CI = 0x0000001e,
TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL__VI  = 0x0000001e,
TCC_PERF_SEL_READ_RETURN_TIMEOUT__SI__CI = 0x0000001f,
TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL__VI = 0x0000001f,
TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT__SI__CI = 0x00000020,
TCC_PERF_SEL_MC_WRREQ_LEVEL__VI          = 0x00000020,
TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE__SI__CI = 0x00000021,
TCC_PERF_SEL_MC_ATOMIC__VI               = 0x00000021,
TCC_PERF_SEL_BUBBLE__SI__CI              = 0x00000022,
TCC_PERF_SEL_MC_ATOMIC_LEVEL__VI         = 0x00000022,
TCC_PERF_SEL_RETURN_ACK__SI__CI          = 0x00000023,
TCC_PERF_SEL_MC_RDREQ__VI                = 0x00000023,
TCC_PERF_SEL_RETURN_DATA__SI__CI         = 0x00000024,
TCC_PERF_SEL_MC_RDREQ_UNCACHED__VI       = 0x00000024,
TCC_PERF_SEL_RETURN_HOLE__SI__CI         = 0x00000025,
TCC_PERF_SEL_MC_RDREQ_MDC__VI            = 0x00000025,
TCC_PERF_SEL_RETURN_ACK_HOLE__SI__CI     = 0x00000026,
TCC_PERF_SEL_MC_RDREQ_COMPRESSED__VI     = 0x00000026,
TCC_PERF_SEL_IB_STALL__SI__CI            = 0x00000027,
TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL__VI   = 0x00000027,
TCC_PERF_SEL_TCA_LEVEL__SI__CI           = 0x00000028,
TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL__VI  = 0x00000028,
TCC_PERF_SEL_HOLE_LEVEL__SI__CI          = 0x00000029,
TCC_PERF_SEL_MC_RDREQ_LEVEL__VI          = 0x00000029,
TCC_PERF_SEL_MC_RDRET_NACK__CI           = 0x0000002a,
TCC_PERF_SEL_TAG_STALL__VI               = 0x0000002a,
TCC_PERF_SEL_MC_WRRET_NACK__CI           = 0x0000002b,
TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL__VI = 0x0000002b,
TCC_PERF_SEL_EXE_REQ__CI                 = 0x0000002c,
TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL__VI = 0x0000002c,
TCC_PERF_SEL_TAG_PROBE_STALL__VI         = 0x0000002f,
TCC_PERF_SEL_TAG_PROBE_FILTER_STALL__VI  = 0x00000030,
TCC_PERF_SEL_READ_RETURN_TIMEOUT__VI     = 0x00000031,
TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT__VI  = 0x00000032,
TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE__VI = 0x00000033,
TCC_PERF_SEL_BUBBLE__VI                  = 0x00000034,
TCC_PERF_SEL_RETURN_ACK__VI              = 0x00000035,
TCC_PERF_SEL_RETURN_DATA__VI             = 0x00000036,
TCC_PERF_SEL_RETURN_HOLE__VI             = 0x00000037,
TCC_PERF_SEL_RETURN_ACK_HOLE__VI         = 0x00000038,
TCC_PERF_SEL_IB_REQ__VI                  = 0x00000039,
TCC_PERF_SEL_IB_STALL__VI                = 0x0000003a,
TCC_PERF_SEL_IB_TAG_STALL__VI            = 0x0000003b,
TCC_PERF_SEL_IB_MDC_STALL__VI            = 0x0000003c,
TCC_PERF_SEL_TCA_LEVEL__VI               = 0x0000003d,
TCC_PERF_SEL_HOLE_LEVEL__VI              = 0x0000003e,
TCC_PERF_SEL_MC_RDRET_NACK__VI           = 0x0000003f,
TCC_PERF_SEL_CLIENT0_REQ__SI__CI         = 0x00000040,
TCC_PERF_SEL_MC_WRRET_NACK__VI           = 0x00000040,
TCC_PERF_SEL_CLIENT1_REQ__SI__CI         = 0x00000041,
TCC_PERF_SEL_NORMAL_WRITEBACK__VI        = 0x00000041,
TCC_PERF_SEL_CLIENT2_REQ__SI__CI         = 0x00000042,
TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK__VI = 0x00000042,
TCC_PERF_SEL_CLIENT3_REQ__SI__CI         = 0x00000043,
TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK__VI = 0x00000043,
TCC_PERF_SEL_CLIENT4_REQ__SI__CI         = 0x00000044,
TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK__VI = 0x00000044,
TCC_PERF_SEL_CLIENT5_REQ__SI__CI         = 0x00000045,
TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK__VI = 0x00000045,
TCC_PERF_SEL_CLIENT6_REQ__SI__CI         = 0x00000046,
TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK__VI  = 0x00000046,
TCC_PERF_SEL_CLIENT7_REQ__SI__CI         = 0x00000047,
TCC_PERF_SEL_NORMAL_EVICT__VI            = 0x00000047,
TCC_PERF_SEL_CLIENT8_REQ__SI__CI         = 0x00000048,
TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT__VI     = 0x00000048,
TCC_PERF_SEL_CLIENT9_REQ__SI__CI         = 0x00000049,
TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT__VI    = 0x00000049,
TCC_PERF_SEL_CLIENT10_REQ__SI__CI        = 0x0000004a,
TCC_PERF_SEL_TC_OP_WBINVL2_EVICT__VI     = 0x0000004a,
TCC_PERF_SEL_CLIENT11_REQ__SI__CI        = 0x0000004b,
TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT__VI  = 0x0000004b,
TCC_PERF_SEL_CLIENT12_REQ__SI__CI        = 0x0000004c,
TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT__VI  = 0x0000004c,
TCC_PERF_SEL_CLIENT13_REQ__SI__CI        = 0x0000004d,
TCC_PERF_SEL_ALL_TC_OP_INV_EVICT__VI     = 0x0000004d,
TCC_PERF_SEL_CLIENT14_REQ__SI__CI        = 0x0000004e,
TCC_PERF_SEL_PROBE_EVICT__VI             = 0x0000004e,
TCC_PERF_SEL_CLIENT15_REQ__SI__CI        = 0x0000004f,
TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE__VI     = 0x0000004f,
TCC_PERF_SEL_CLIENT16_REQ__SI__CI        = 0x00000050,
TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE__VI    = 0x00000050,
TCC_PERF_SEL_CLIENT17_REQ__SI__CI        = 0x00000051,
TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE__VI     = 0x00000051,
TCC_PERF_SEL_CLIENT18_REQ__SI__CI        = 0x00000052,
TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE__VI  = 0x00000052,
TCC_PERF_SEL_CLIENT19_REQ__SI__CI        = 0x00000053,
TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE__VI  = 0x00000053,
TCC_PERF_SEL_CLIENT20_REQ__SI__CI        = 0x00000054,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE__VI = 0x00000054,
TCC_PERF_SEL_CLIENT21_REQ__SI__CI        = 0x00000055,
TCC_PERF_SEL_TC_OP_WBL2_NC_START__VI     = 0x00000055,
TCC_PERF_SEL_CLIENT22_REQ__SI__CI        = 0x00000056,
TCC_PERF_SEL_TC_OP_INVL2_NC_START__VI    = 0x00000056,
TCC_PERF_SEL_CLIENT23_REQ__SI__CI        = 0x00000057,
TCC_PERF_SEL_TC_OP_WBINVL2_START__VI     = 0x00000057,
TCC_PERF_SEL_CLIENT24_REQ__SI__CI        = 0x00000058,
TCC_PERF_SEL_TC_OP_WBINVL2_NC_START__VI  = 0x00000058,
TCC_PERF_SEL_CLIENT25_REQ__SI__CI        = 0x00000059,
TCC_PERF_SEL_TC_OP_WBINVL2_SD_START__VI  = 0x00000059,
TCC_PERF_SEL_CLIENT26_REQ__SI__CI        = 0x0000005a,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START__VI = 0x0000005a,
TCC_PERF_SEL_CLIENT27_REQ__SI__CI        = 0x0000005b,
TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH__VI    = 0x0000005b,
TCC_PERF_SEL_CLIENT28_REQ__SI__CI        = 0x0000005c,
TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH__VI   = 0x0000005c,
TCC_PERF_SEL_CLIENT29_REQ__SI__CI        = 0x0000005d,
TCC_PERF_SEL_TC_OP_WBINVL2_FINISH__VI    = 0x0000005d,
TCC_PERF_SEL_CLIENT30_REQ__SI__CI        = 0x0000005e,
TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH__VI = 0x0000005e,
TCC_PERF_SEL_CLIENT31_REQ__SI__CI        = 0x0000005f,
TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH__VI = 0x0000005f,
TCC_PERF_SEL_CLIENT32_REQ__SI__CI        = 0x00000060,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH__VI = 0x00000060,
TCC_PERF_SEL_CLIENT33_REQ__SI__CI        = 0x00000061,
TCC_PERF_SEL_MDC_REQ__VI                 = 0x00000061,
TCC_PERF_SEL_CLIENT34_REQ__SI__CI        = 0x00000062,
TCC_PERF_SEL_MDC_LEVEL__VI               = 0x00000062,
TCC_PERF_SEL_CLIENT35_REQ__SI__CI        = 0x00000063,
TCC_PERF_SEL_MDC_TAG_HIT__VI             = 0x00000063,
TCC_PERF_SEL_CLIENT36_REQ__SI__CI        = 0x00000064,
TCC_PERF_SEL_MDC_SECTOR_HIT__VI          = 0x00000064,
TCC_PERF_SEL_CLIENT37_REQ__SI__CI        = 0x00000065,
TCC_PERF_SEL_MDC_SECTOR_MISS__VI         = 0x00000065,
TCC_PERF_SEL_CLIENT38_REQ__SI__CI        = 0x00000066,
TCC_PERF_SEL_MDC_TAG_STALL__VI           = 0x00000066,
TCC_PERF_SEL_CLIENT39_REQ__SI__CI        = 0x00000067,
TCC_PERF_SEL_CLIENT40_REQ__SI__CI        = 0x00000068,
TCC_PERF_SEL_CLIENT41_REQ__SI__CI        = 0x00000069,
TCC_PERF_SEL_CLIENT42_REQ__SI__CI        = 0x0000006a,
TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION__VI = 0x0000006a,
TCC_PERF_SEL_CLIENT43_REQ__SI__CI        = 0x0000006b,
TCC_PERF_SEL_PROBE_FILTER_DISABLED__VI   = 0x0000006b,
TCC_PERF_SEL_CLIENT44_REQ__SI__CI        = 0x0000006c,
TCC_PERF_SEL_CLIENT45_REQ__SI__CI        = 0x0000006d,
TCC_PERF_SEL_CLIENT46_REQ__SI__CI        = 0x0000006e,
TCC_PERF_SEL_CLIENT47_REQ__SI__CI        = 0x0000006f,
TCC_PERF_SEL_CLIENT48_REQ__SI__CI        = 0x00000070,
TCC_PERF_SEL_CLIENT49_REQ__SI__CI        = 0x00000071,
TCC_PERF_SEL_CLIENT50_REQ__SI__CI        = 0x00000072,
TCC_PERF_SEL_CLIENT51_REQ__SI__CI        = 0x00000073,
TCC_PERF_SEL_CLIENT52_REQ__SI__CI        = 0x00000074,
TCC_PERF_SEL_CLIENT53_REQ__SI__CI        = 0x00000075,
TCC_PERF_SEL_CLIENT54_REQ__SI__CI        = 0x00000076,
TCC_PERF_SEL_CLIENT55_REQ__SI__CI        = 0x00000077,
TCC_PERF_SEL_CLIENT56_REQ__SI__CI        = 0x00000078,
TCC_PERF_SEL_CLIENT57_REQ__SI__CI        = 0x00000079,
TCC_PERF_SEL_CLIENT58_REQ__SI__CI        = 0x0000007a,
TCC_PERF_SEL_CLIENT59_REQ__SI__CI        = 0x0000007b,
TCC_PERF_SEL_CLIENT60_REQ__SI__CI        = 0x0000007c,
TCC_PERF_SEL_CLIENT61_REQ__SI__CI        = 0x0000007d,
TCC_PERF_SEL_CLIENT62_REQ__SI__CI        = 0x0000007e,
TCC_PERF_SEL_CLIENT63_REQ__SI__CI        = 0x0000007f,
TCC_PERF_SEL_NORMAL_WRITEBACK__CI        = 0x00000080,
TCC_PERF_SEL_CLIENT0_REQ__VI             = 0x00000080,
TCC_PERF_SEL_TC_OP_WBL2_VOL_WRITEBACK__CI = 0x00000081,
TCC_PERF_SEL_CLIENT1_REQ__VI             = 0x00000081,
TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK__CI = 0x00000082,
TCC_PERF_SEL_CLIENT2_REQ__VI             = 0x00000082,
TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK__CI  = 0x00000083,
TCC_PERF_SEL_CLIENT3_REQ__VI             = 0x00000083,
TCC_PERF_SEL_NORMAL_EVICT__CI            = 0x00000084,
TCC_PERF_SEL_CLIENT4_REQ__VI             = 0x00000084,
TCC_PERF_SEL_TC_OP_INVL2_VOL_EVICT__CI   = 0x00000085,
TCC_PERF_SEL_CLIENT5_REQ__VI             = 0x00000085,
TCC_PERF_SEL_TC_OP_INVL1L2_VOL_EVICT__CI = 0x00000086,
TCC_PERF_SEL_CLIENT6_REQ__VI             = 0x00000086,
TCC_PERF_SEL_TC_OP_WBL2_VOL_EVICT__CI    = 0x00000087,
TCC_PERF_SEL_CLIENT7_REQ__VI             = 0x00000087,
TCC_PERF_SEL_TC_OP_WBINVL2_EVICT__CI     = 0x00000088,
TCC_PERF_SEL_CLIENT8_REQ__VI             = 0x00000088,
TCC_PERF_SEL_ALL_TC_OP_INV_EVICT__CI     = 0x00000089,
TCC_PERF_SEL_CLIENT9_REQ__VI             = 0x00000089,
TCC_PERF_SEL_ALL_TC_OP_INV_VOL_EVICT__CI = 0x0000008a,
TCC_PERF_SEL_CLIENT10_REQ__VI            = 0x0000008a,
TCC_PERF_SEL_TC_OP_WBL2_VOL_CYCLE__CI    = 0x0000008b,
TCC_PERF_SEL_CLIENT11_REQ__VI            = 0x0000008b,
TCC_PERF_SEL_TC_OP_INVL2_VOL_CYCLE__CI   = 0x0000008c,
TCC_PERF_SEL_CLIENT12_REQ__VI            = 0x0000008c,
TCC_PERF_SEL_TC_OP_INVL1L2_VOL_CYCLE__CI = 0x0000008d,
TCC_PERF_SEL_CLIENT13_REQ__VI            = 0x0000008d,
TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE__CI     = 0x0000008e,
TCC_PERF_SEL_CLIENT14_REQ__VI            = 0x0000008e,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE__CI = 0x0000008f,
TCC_PERF_SEL_CLIENT15_REQ__VI            = 0x0000008f,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_CYCLE__CI = 0x00000090,
TCC_PERF_SEL_CLIENT16_REQ__VI            = 0x00000090,
TCC_PERF_SEL_TC_OP_WBL2_VOL_START__CI    = 0x00000091,
TCC_PERF_SEL_CLIENT17_REQ__VI            = 0x00000091,
TCC_PERF_SEL_TC_OP_INVL2_VOL_START__CI   = 0x00000092,
TCC_PERF_SEL_CLIENT18_REQ__VI            = 0x00000092,
TCC_PERF_SEL_TC_OP_INVL1L2_VOL_START__CI = 0x00000093,
TCC_PERF_SEL_CLIENT19_REQ__VI            = 0x00000093,
TCC_PERF_SEL_TC_OP_WBINVL2_START__CI     = 0x00000094,
TCC_PERF_SEL_CLIENT20_REQ__VI            = 0x00000094,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START__CI = 0x00000095,
TCC_PERF_SEL_CLIENT21_REQ__VI            = 0x00000095,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START__CI = 0x00000096,
TCC_PERF_SEL_CLIENT22_REQ__VI            = 0x00000096,
TCC_PERF_SEL_TC_OP_WBL2_VOL_FINISH__CI   = 0x00000097,
TCC_PERF_SEL_CLIENT23_REQ__VI            = 0x00000097,
TCC_PERF_SEL_TC_OP_INVL2_VOL_FINISH__CI  = 0x00000098,
TCC_PERF_SEL_CLIENT24_REQ__VI            = 0x00000098,
TCC_PERF_SEL_TC_OP_INVL1L2_VOL_FINISH__CI = 0x00000099,
TCC_PERF_SEL_CLIENT25_REQ__VI            = 0x00000099,
TCC_PERF_SEL_TC_OP_WBINVL2_FINISH__CI    = 0x0000009a,
TCC_PERF_SEL_CLIENT26_REQ__VI            = 0x0000009a,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH__CI = 0x0000009b,
TCC_PERF_SEL_CLIENT27_REQ__VI            = 0x0000009b,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_FINISH__CI = 0x0000009c,
TCC_PERF_SEL_CLIENT28_REQ__VI            = 0x0000009c,
TCC_PERF_SEL_VOL_MC_WRREQ__CI            = 0x0000009d,
TCC_PERF_SEL_CLIENT29_REQ__VI            = 0x0000009d,
TCC_PERF_SEL_VOL_MC_RDREQ__CI            = 0x0000009e,
TCC_PERF_SEL_CLIENT30_REQ__VI            = 0x0000009e,
TCC_PERF_SEL_VOL_REQ__CI                 = 0x0000009f,
TCC_PERF_SEL_CLIENT31_REQ__VI            = 0x0000009f,
TCC_PERF_SEL_CLIENT32_REQ__VI            = 0x000000a0,
TCC_PERF_SEL_CLIENT33_REQ__VI            = 0x000000a1,
TCC_PERF_SEL_CLIENT34_REQ__VI            = 0x000000a2,
TCC_PERF_SEL_CLIENT35_REQ__VI            = 0x000000a3,
TCC_PERF_SEL_CLIENT36_REQ__VI            = 0x000000a4,
TCC_PERF_SEL_CLIENT37_REQ__VI            = 0x000000a5,
TCC_PERF_SEL_CLIENT38_REQ__VI            = 0x000000a6,
TCC_PERF_SEL_CLIENT39_REQ__VI            = 0x000000a7,
TCC_PERF_SEL_CLIENT40_REQ__VI            = 0x000000a8,
TCC_PERF_SEL_CLIENT41_REQ__VI            = 0x000000a9,
TCC_PERF_SEL_CLIENT42_REQ__VI            = 0x000000aa,
TCC_PERF_SEL_CLIENT43_REQ__VI            = 0x000000ab,
TCC_PERF_SEL_CLIENT44_REQ__VI            = 0x000000ac,
TCC_PERF_SEL_CLIENT45_REQ__VI            = 0x000000ad,
TCC_PERF_SEL_CLIENT46_REQ__VI            = 0x000000ae,
TCC_PERF_SEL_CLIENT47_REQ__VI            = 0x000000af,
TCC_PERF_SEL_CLIENT48_REQ__VI            = 0x000000b0,
TCC_PERF_SEL_CLIENT49_REQ__VI            = 0x000000b1,
TCC_PERF_SEL_CLIENT50_REQ__VI            = 0x000000b2,
TCC_PERF_SEL_CLIENT51_REQ__VI            = 0x000000b3,
TCC_PERF_SEL_CLIENT52_REQ__VI            = 0x000000b4,
TCC_PERF_SEL_CLIENT53_REQ__VI            = 0x000000b5,
TCC_PERF_SEL_CLIENT54_REQ__VI            = 0x000000b6,
TCC_PERF_SEL_CLIENT55_REQ__VI            = 0x000000b7,
TCC_PERF_SEL_CLIENT56_REQ__VI            = 0x000000b8,
TCC_PERF_SEL_CLIENT57_REQ__VI            = 0x000000b9,
TCC_PERF_SEL_CLIENT58_REQ__VI            = 0x000000ba,
TCC_PERF_SEL_CLIENT59_REQ__VI            = 0x000000bb,
TCC_PERF_SEL_CLIENT60_REQ__VI            = 0x000000bc,
TCC_PERF_SEL_CLIENT61_REQ__VI            = 0x000000bd,
TCC_PERF_SEL_CLIENT62_REQ__VI            = 0x000000be,
TCC_PERF_SEL_CLIENT63_REQ__VI            = 0x000000bf,
TCC_PERF_SEL_CLIENT64_REQ__VI            = 0x000000c0,
TCC_PERF_SEL_CLIENT65_REQ__VI            = 0x000000c1,
TCC_PERF_SEL_CLIENT66_REQ__VI            = 0x000000c2,
TCC_PERF_SEL_CLIENT67_REQ__VI            = 0x000000c3,
TCC_PERF_SEL_CLIENT68_REQ__VI            = 0x000000c4,
TCC_PERF_SEL_CLIENT69_REQ__VI            = 0x000000c5,
TCC_PERF_SEL_CLIENT70_REQ__VI            = 0x000000c6,
TCC_PERF_SEL_CLIENT71_REQ__VI            = 0x000000c7,
TCC_PERF_SEL_CLIENT72_REQ__VI            = 0x000000c8,
TCC_PERF_SEL_CLIENT73_REQ__VI            = 0x000000c9,
TCC_PERF_SEL_CLIENT74_REQ__VI            = 0x000000ca,
TCC_PERF_SEL_CLIENT75_REQ__VI            = 0x000000cb,
TCC_PERF_SEL_CLIENT76_REQ__VI            = 0x000000cc,
TCC_PERF_SEL_CLIENT77_REQ__VI            = 0x000000cd,
TCC_PERF_SEL_CLIENT78_REQ__VI            = 0x000000ce,
TCC_PERF_SEL_CLIENT79_REQ__VI            = 0x000000cf,
TCC_PERF_SEL_CLIENT80_REQ__VI            = 0x000000d0,
TCC_PERF_SEL_CLIENT81_REQ__VI            = 0x000000d1,
TCC_PERF_SEL_CLIENT82_REQ__VI            = 0x000000d2,
TCC_PERF_SEL_CLIENT83_REQ__VI            = 0x000000d3,
TCC_PERF_SEL_CLIENT84_REQ__VI            = 0x000000d4,
TCC_PERF_SEL_CLIENT85_REQ__VI            = 0x000000d5,
TCC_PERF_SEL_CLIENT86_REQ__VI            = 0x000000d6,
TCC_PERF_SEL_CLIENT87_REQ__VI            = 0x000000d7,
TCC_PERF_SEL_CLIENT88_REQ__VI            = 0x000000d8,
TCC_PERF_SEL_CLIENT89_REQ__VI            = 0x000000d9,
TCC_PERF_SEL_CLIENT90_REQ__VI            = 0x000000da,
TCC_PERF_SEL_CLIENT91_REQ__VI            = 0x000000db,
TCC_PERF_SEL_CLIENT92_REQ__VI            = 0x000000dc,
TCC_PERF_SEL_CLIENT93_REQ__VI            = 0x000000dd,
TCC_PERF_SEL_CLIENT94_REQ__VI            = 0x000000de,
TCC_PERF_SEL_CLIENT95_REQ__VI            = 0x000000df,
TCC_PERF_SEL_CLIENT96_REQ__VI            = 0x000000e0,
TCC_PERF_SEL_CLIENT97_REQ__VI            = 0x000000e1,
TCC_PERF_SEL_CLIENT98_REQ__VI            = 0x000000e2,
TCC_PERF_SEL_CLIENT99_REQ__VI            = 0x000000e3,
TCC_PERF_SEL_CLIENT100_REQ__VI           = 0x000000e4,
TCC_PERF_SEL_CLIENT101_REQ__VI           = 0x000000e5,
TCC_PERF_SEL_CLIENT102_REQ__VI           = 0x000000e6,
TCC_PERF_SEL_CLIENT103_REQ__VI           = 0x000000e7,
TCC_PERF_SEL_CLIENT104_REQ__VI           = 0x000000e8,
TCC_PERF_SEL_CLIENT105_REQ__VI           = 0x000000e9,
TCC_PERF_SEL_CLIENT106_REQ__VI           = 0x000000ea,
TCC_PERF_SEL_CLIENT107_REQ__VI           = 0x000000eb,
TCC_PERF_SEL_CLIENT108_REQ__VI           = 0x000000ec,
TCC_PERF_SEL_CLIENT109_REQ__VI           = 0x000000ed,
TCC_PERF_SEL_CLIENT110_REQ__VI           = 0x000000ee,
TCC_PERF_SEL_CLIENT111_REQ__VI           = 0x000000ef,
TCC_PERF_SEL_CLIENT112_REQ__VI           = 0x000000f0,
TCC_PERF_SEL_CLIENT113_REQ__VI           = 0x000000f1,
TCC_PERF_SEL_CLIENT114_REQ__VI           = 0x000000f2,
TCC_PERF_SEL_CLIENT115_REQ__VI           = 0x000000f3,
TCC_PERF_SEL_CLIENT116_REQ__VI           = 0x000000f4,
TCC_PERF_SEL_CLIENT117_REQ__VI           = 0x000000f5,
TCC_PERF_SEL_CLIENT118_REQ__VI           = 0x000000f6,
TCC_PERF_SEL_CLIENT119_REQ__VI           = 0x000000f7,
TCC_PERF_SEL_CLIENT120_REQ__VI           = 0x000000f8,
TCC_PERF_SEL_CLIENT121_REQ__VI           = 0x000000f9,
TCC_PERF_SEL_CLIENT122_REQ__VI           = 0x000000fa,
TCC_PERF_SEL_CLIENT123_REQ__VI           = 0x000000fb,
TCC_PERF_SEL_CLIENT124_REQ__VI           = 0x000000fc,
TCC_PERF_SEL_CLIENT125_REQ__VI           = 0x000000fd,
TCC_PERF_SEL_CLIENT126_REQ__VI           = 0x000000fe,
TCC_PERF_SEL_CLIENT127_REQ__VI           = 0x000000ff,
} TCC_PERF_SEL;

typedef enum TCP_CACHE_POLICIES {
TCP_CACHE_POLICY_MISS_LRU                = 0x00000000,
TCP_CACHE_POLICY_MISS_EVICT              = 0x00000001,
TCP_CACHE_POLICY_HIT_LRU                 = 0x00000002,
TCP_CACHE_POLICY_HIT_EVICT               = 0x00000003,
} TCP_CACHE_POLICIES;

typedef enum TCP_CACHE_STORE_POLICIES {
TCP_CACHE_STORE_POLICY_MISS_LRU__SI__CI  = 0x00000000,
TCP_CACHE_STORE_POLICY_WT_LRU__VI        = 0x00000000,
TCP_CACHE_STORE_POLICY_MISS_EVICT__SI__CI = 0x00000001,
TCP_CACHE_STORE_POLICY_WT_EVICT__VI      = 0x00000001,
} TCP_CACHE_STORE_POLICIES;

typedef enum TCP_PERFCOUNT_SELECT {
TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES__SI = 0,
TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES__CI__VI = 0x00000000,
TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES__CI__VI = 0x00000001,
TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES__CI__VI = 0x00000002,
TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES__CI__VI = 0x00000003,
TCP_PERF_SEL_TD_TCP_STALL_CYCLES__CI__VI = 0x00000004,
TCP_PERF_SEL_TCR_TCP_STALL_CYCLES__CI__VI = 0x00000005,
TCP_PERF_SEL_LOD_STALL_CYCLES__CI__VI    = 0x00000006,
TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES__CI__VI = 0x00000007,
TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES__CI__VI = 0x00000008,
TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES__CI__VI = 0x00000009,
TCP_PERF_SEL_ALLOC_STALL_CYCLES__CI__VI  = 0x0000000a,
TCP_PERF_SEL_LFIFO_STALL_CYCLES__CI__VI  = 0x0000000b,
TCP_PERF_SEL_RFIFO_STALL_CYCLES__CI__VI  = 0x0000000c,
TCP_PERF_SEL_TCR_RDRET_STALL__CI__VI     = 0x0000000d,
TCP_PERF_SEL_WRITE_CONFLICT_STALL__CI__VI = 0x0000000e,
TCP_PERF_SEL_HOLE_READ_STALL__CI__VI     = 0x0000000f,
TCP_PERF_SEL_READCONFLICT_STALL_CYCLES__CI__VI = 0x00000010,
TCP_PERF_SEL_PENDING_STALL_CYCLES__CI__VI = 0x00000011,
TCP_PERF_SEL_READFIFO_STALL_CYCLES__CI__VI = 0x00000012,
TCP_PERF_SEL_TCP_LATENCY__CI__VI         = 0x00000013,
TCP_PERF_SEL_TCC_READ_REQ_LATENCY__CI__VI = 0x00000014,
TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY__CI__VI = 0x00000015,
TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY__CI__VI = 0x00000016,
TCP_PERF_SEL_TCC_READ_REQ__CI__VI        = 0x00000017,
TCP_PERF_SEL_TCC_WRITE_REQ__CI__VI       = 0x00000018,
TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ__CI__VI = 0x00000019,
TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ__CI__VI = 0x0000001a,
TCP_PERF_SEL_TOTAL_LOCAL_READ__CI__VI    = 0x0000001b,
TCP_PERF_SEL_TOTAL_GLOBAL_READ__CI__VI   = 0x0000001c,
TCP_PERF_SEL_TOTAL_LOCAL_WRITE__CI__VI   = 0x0000001d,
TCP_PERF_SEL_TOTAL_GLOBAL_WRITE__CI__VI  = 0x0000001e,
TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET__CI__VI = 0x0000001f,
TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET__CI__VI = 0x00000020,
TCP_PERF_SEL_TOTAL_WBINVL1__CI__VI       = 0x00000021,
TCP_PERF_SEL_IMG_READ_FMT_1__CI__VI      = 0x00000022,
TCP_PERF_SEL_IMG_READ_FMT_8__CI__VI      = 0x00000023,
TCP_PERF_SEL_IMG_READ_FMT_16__CI__VI     = 0x00000024,
TCP_PERF_SEL_IMG_READ_FMT_32__CI__VI     = 0x00000025,
TCP_PERF_SEL_IMG_READ_FMT_32_AS_8__CI__VI = 0x00000026,
TCP_PERF_SEL_IMG_READ_FMT_32_AS_16__CI__VI = 0x00000027,
TCP_PERF_SEL_IMG_READ_FMT_32_AS_128__CI__VI = 0x00000028,
TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE__CI__VI = 0x00000029,
TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE__CI__VI = 0x0000002a,
TCP_PERF_SEL_IMG_READ_FMT_96__CI__VI     = 0x0000002b,
TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE__CI__VI = 0x0000002c,
TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE__CI__VI = 0x0000002d,
TCP_PERF_SEL_IMG_READ_FMT_BC1__CI__VI    = 0x0000002e,
TCP_PERF_SEL_IMG_READ_FMT_BC2__CI__VI    = 0x0000002f,
TCP_PERF_SEL_IMG_READ_FMT_BC3__CI__VI    = 0x00000030,
TCP_PERF_SEL_IMG_READ_FMT_BC4__CI__VI    = 0x00000031,
TCP_PERF_SEL_IMG_READ_FMT_BC5__CI__VI    = 0x00000032,
TCP_PERF_SEL_IMG_READ_FMT_BC6__CI__VI    = 0x00000033,
TCP_PERF_SEL_IMG_READ_FMT_BC7__CI__VI    = 0x00000034,
TCP_PERF_SEL_IMG_READ_FMT_I8__CI__VI     = 0x00000035,
TCP_PERF_SEL_IMG_READ_FMT_I16__CI__VI    = 0x00000036,
TCP_PERF_SEL_IMG_READ_FMT_I32__CI__VI    = 0x00000037,
TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8__CI__VI = 0x00000038,
TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16__CI__VI = 0x00000039,
TCP_PERF_SEL_IMG_READ_FMT_D8__CI__VI     = 0x0000003a,
TCP_PERF_SEL_IMG_READ_FMT_D16__CI__VI    = 0x0000003b,
TCP_PERF_SEL_IMG_READ_FMT_D32__CI__VI    = 0x0000003c,
TCP_PERF_SEL_IMG_WRITE_FMT_8__CI__VI     = 0x0000003d,
TCP_PERF_SEL_IMG_WRITE_FMT_16__CI__VI    = 0x0000003e,
TCP_PERF_SEL_IMG_WRITE_FMT_32__CI__VI    = 0x0000003f,
TCP_PERF_SEL_IMG_WRITE_FMT_64__CI__VI    = 0x00000040,
TCP_PERF_SEL_IMG_WRITE_FMT_128__CI__VI   = 0x00000041,
TCP_PERF_SEL_IMG_WRITE_FMT_D8__CI__VI    = 0x00000042,
TCP_PERF_SEL_IMG_WRITE_FMT_D16__CI__VI   = 0x00000043,
TCP_PERF_SEL_IMG_WRITE_FMT_D32__CI__VI   = 0x00000044,
TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32__CI__VI = 0x00000045,
TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32__CI__VI = 0x00000046,
TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64__CI__VI = 0x00000047,
TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64__CI__VI = 0x00000048,
TCP_PERF_SEL_BUF_READ_FMT_8__CI__VI      = 0x00000049,
TCP_PERF_SEL_BUF_READ_FMT_16__CI__VI     = 0x0000004a,
TCP_PERF_SEL_BUF_READ_FMT_32__CI__VI     = 0x0000004b,
TCP_PERF_SEL_BUF_WRITE_FMT_8__CI__VI     = 0x0000004c,
TCP_PERF_SEL_BUF_WRITE_FMT_16__CI__VI    = 0x0000004d,
TCP_PERF_SEL_BUF_WRITE_FMT_32__CI__VI    = 0x0000004e,
TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32__CI__VI = 0x0000004f,
TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32__CI__VI = 0x00000050,
TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64__CI__VI = 0x00000051,
TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64__CI__VI = 0x00000052,
TCP_PERF_SEL_ARR_LINEAR_GENERAL__CI__VI  = 0x00000053,
TCP_PERF_SEL_ARR_LINEAR_ALIGNED__CI__VI  = 0x00000054,
TCP_PERF_SEL_ARR_1D_THIN1__CI__VI        = 0x00000055,
TCP_PERF_SEL_ARR_1D_THICK__CI__VI        = 0x00000056,
TCP_PERF_SEL_ARR_2D_THIN1__CI__VI        = 0x00000057,
TCP_PERF_SEL_ARR_2D_THICK__CI__VI        = 0x00000058,
TCP_PERF_SEL_ARR_2D_XTHICK__CI__VI       = 0x00000059,
TCP_PERF_SEL_ARR_3D_THIN1__CI__VI        = 0x0000005a,
TCP_PERF_SEL_ARR_3D_THICK__CI__VI        = 0x0000005b,
TCP_PERF_SEL_ARR_3D_XTHICK__CI__VI       = 0x0000005c,
TCP_PERF_SEL_DIM_1D__CI__VI              = 0x0000005d,
TCP_PERF_SEL_DIM_2D__CI__VI              = 0x0000005e,
TCP_PERF_SEL_DIM_3D__CI__VI              = 0x0000005f,
TCP_PERF_SEL_DIM_1D_ARRAY__CI__VI        = 0x00000060,
TCP_PERF_SEL_DIM_2D_ARRAY__CI__VI        = 0x00000061,
TCP_PERF_SEL_DIM_2D_MSAA__CI__VI         = 0x00000062,
TCP_PERF_SEL_DIM_2D_ARRAY_MSAA__CI__VI   = 0x00000063,
TCP_PERF_SEL_DIM_CUBE_ARRAY__CI__VI      = 0x00000064,
TCP_PERF_SEL_CP_TCP_INVALIDATE__CI__VI   = 0x00000065,
TCP_PERF_SEL_TA_TCP_STATE_READ__CI__VI   = 0x00000066,
TCP_PERF_SEL_TAGRAM0_REQ__CI__VI         = 0x00000067,
TCP_PERF_SEL_TAGRAM1_REQ__CI__VI         = 0x00000068,
TCP_PERF_SEL_TAGRAM2_REQ__CI__VI         = 0x00000069,
TCP_PERF_SEL_TAGRAM3_REQ__CI__VI         = 0x0000006a,
TCP_PERF_SEL_GATE_EN1__CI__VI            = 0x0000006b,
TCP_PERF_SEL_GATE_EN2__CI__VI            = 0x0000006c,
TCP_PERF_SEL_CORE_REG_SCLK_VLD__CI__VI   = 0x0000006d,
TCP_PERF_SEL_TCC_REQ__CI__VI             = 0x0000006e,
TCP_PERF_SEL_TCC_NON_READ_REQ__CI__VI    = 0x0000006f,
TCP_PERF_SEL_TCC_BYPASS_READ_REQ__CI__VI = 0x00000070,
TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ__CI__VI = 0x00000071,
TCP_PERF_SEL_TCC_VOLATILE_READ_REQ__CI__VI = 0x00000072,
TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ__CI__VI = 0x00000073,
TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ__CI__VI = 0x00000074,
TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ__CI__VI = 0x00000075,
TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ__CI__VI = 0x00000076,
TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ__CI__VI = 0x00000077,
TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ__CI__VI = 0x00000078,
TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ__CI__VI = 0x00000079,
TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ__CI__VI = 0x0000007a,
TCP_PERF_SEL_TCC_ATOMIC_REQ__CI__VI      = 0x0000007b,
TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ__CI__VI = 0x0000007c,
TCP_PERF_SEL_TCC_DATA_BUS_BUSY__CI__VI   = 0x0000007d,
TCP_PERF_SEL_TOTAL_ACCESSES__CI__VI      = 0x0000007e,
TCP_PERF_SEL_TOTAL_READ__CI__VI          = 0x0000007f,
TCP_PERF_SEL_TOTAL_HIT_LRU_READ__CI__VI  = 0x00000080,
TCP_PERF_SEL_TOTAL_HIT_EVICT_READ__CI__VI = 0x00000081,
TCP_PERF_SEL_TOTAL_MISS_LRU_READ__CI__VI = 0x00000082,
TCP_PERF_SEL_TOTAL_MISS_EVICT_READ__CI__VI = 0x00000083,
TCP_PERF_SEL_TOTAL_NON_READ__CI__VI      = 0x00000084,
TCP_PERF_SEL_TOTAL_WRITE__CI__VI         = 0x00000085,
TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE__CI__VI = 0x00000086,
TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE__CI__VI = 0x00000087,
TCP_PERF_SEL_TOTAL_WBINVL1_VOL__CI__VI   = 0x00000088,
TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES__CI__VI = 0x00000089,
TCP_PERF_SEL_DISPLAY_MICROTILING__CI__VI = 0x0000008a,
TCP_PERF_SEL_THIN_MICROTILING__CI__VI    = 0x0000008b,
TCP_PERF_SEL_DEPTH_MICROTILING__CI__VI   = 0x0000008c,
TCP_PERF_SEL_ARR_PRT_THIN1__CI__VI       = 0x0000008d,
TCP_PERF_SEL_ARR_PRT_2D_THIN1__CI__VI    = 0x0000008e,
TCP_PERF_SEL_ARR_PRT_3D_THIN1__CI__VI    = 0x0000008f,
TCP_PERF_SEL_ARR_PRT_THICK__CI__VI       = 0x00000090,
TCP_PERF_SEL_ARR_PRT_2D_THICK__CI__VI    = 0x00000091,
TCP_PERF_SEL_ARR_PRT_3D_THICK__CI__VI    = 0x00000092,
TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL__CI__VI = 0x00000093,
TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL__CI__VI = 0x00000094,
TCP_PERF_SEL_UNALIGNED__CI__VI           = 0x00000095,
TCP_PERF_SEL_ROTATED_MICROTILING__CI__VI = 0x00000096,
TCP_PERF_SEL_THICK_MICROTILING__CI__VI   = 0x00000097,
TCP_PERF_SEL_ATC__CI__VI                 = 0x00000098,
TCP_PERF_SEL_POWER_STALL__CI__VI         = 0x00000099,
TCP_PERF_SEL_RESERVED_154__VI            = 0x0000009a,
TCP_PERF_SEL_TCC_LRU_REQ__VI             = 0x0000009b,
TCP_PERF_SEL_TCC_STREAM_REQ__VI          = 0x0000009c,
TCP_PERF_SEL_TCC_NC_READ_REQ__VI         = 0x0000009d,
TCP_PERF_SEL_TCC_NC_WRITE_REQ__VI        = 0x0000009e,
TCP_PERF_SEL_TCC_NC_ATOMIC_REQ__VI       = 0x0000009f,
TCP_PERF_SEL_TCC_UC_READ_REQ__VI         = 0x000000a0,
TCP_PERF_SEL_TCC_UC_WRITE_REQ__VI        = 0x000000a1,
TCP_PERF_SEL_TCC_UC_ATOMIC_REQ__VI       = 0x000000a2,
TCP_PERF_SEL_TCC_CC_READ_REQ__VI         = 0x000000a3,
TCP_PERF_SEL_TCC_CC_WRITE_REQ__VI        = 0x000000a4,
TCP_PERF_SEL_TCC_CC_ATOMIC_REQ__VI       = 0x000000a5,
TCP_PERF_SEL_TCC_DCC_REQ__VI             = 0x000000a6,
TCP_PERF_SEL_TCC_PHYSICAL_REQ__VI        = 0x000000a7,
TCP_PERF_SEL_UNORDERED_MTYPE_STALL__VI   = 0x000000a8,
TCP_PERF_SEL_VOLATILE__VI                = 0x000000a9,
TCP_PERF_SEL_TC_TA_XNACK_STALL__VI       = 0x000000aa,
TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL__VI = 0x000000ab,
TCP_PERF_SEL_SHOOTDOWN__VI               = 0x000000ac,
TCP_PERF_SEL_GATCL1_TRANSLATION_MISS__VI = 0x000000ad,
TCP_PERF_SEL_GATCL1_PERMISSION_MISS__VI  = 0x000000ae,
TCP_PERF_SEL_GATCL1_REQUEST__VI          = 0x000000af,
TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX__VI = 0x000000b0,
TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT__VI = 0x000000b1,
TCP_PERF_SEL_GATCL1_LFIFO_FULL__VI       = 0x000000b2,
TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES__VI = 0x000000b3,
TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT__VI   = 0x000000b5,
TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL__VI = 0x000000b6,
TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES__SI = 1,
TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES__SI = 2,
TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES__SI = 3,
TCP_PERF_SEL_TD_TCP_STALL_CYCLES__SI     = 4,
TCP_PERF_SEL_TCR_TCP_STALL_CYCLES__SI    = 5,
TCP_PERF_SEL_LOD_STALL_CYCLES__SI        = 6,
TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES__SI = 7,
TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES__SI = 8,
TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES__SI = 9,
TCP_PERF_SEL_ALLOC_STALL_CYCLES__SI      = 10,
TCP_PERF_SEL_LFIFO_STALL_CYCLES__SI      = 11,
TCP_PERF_SEL_RFIFO_STALL_CYCLES__SI      = 12,
TCP_PERF_SEL_TCR_RDRET_STALL__SI         = 13,
TCP_PERF_SEL_WRITE_CONFLICT_STALL__SI    = 14,
TCP_PERF_SEL_HOLE_READ_STALL__SI         = 15,
TCP_PERF_SEL_READCONFLICT_STALL_CYCLES__SI = 16,
TCP_PERF_SEL_PENDING_STALL_CYCLES__SI    = 17,
TCP_PERF_SEL_READFIFO_STALL_CYCLES__SI   = 18,
TCP_PERF_SEL_TCP_LATENCY__SI             = 19,
TCP_PERF_SEL_TCC_READ_REQ_LATENCY__SI    = 20,
TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY__SI   = 21,
TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY__SI = 22,
TCP_PERF_SEL_TCC_READ_REQ__SI            = 23,
TCP_PERF_SEL_TCC_WRITE_REQ__SI           = 24,
TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ__SI = 25,
TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ__SI = 26,
TCP_PERF_SEL_TOTAL_LOCAL_READ__SI        = 27,
TCP_PERF_SEL_TOTAL_GLOBAL_READ__SI       = 28,
TCP_PERF_SEL_TOTAL_LOCAL_WRITE__SI       = 29,
TCP_PERF_SEL_TOTAL_GLOBAL_WRITE__SI      = 30,
TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET__SI   = 31,
TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET__SI = 32,
TCP_PERF_SEL_TOTAL_WBINVL1__SI           = 33,
TCP_PERF_SEL_IMG_READ_FMT_1__SI          = 34,
TCP_PERF_SEL_IMG_READ_FMT_8__SI          = 35,
TCP_PERF_SEL_IMG_READ_FMT_16__SI         = 36,
TCP_PERF_SEL_IMG_READ_FMT_32__SI         = 37,
TCP_PERF_SEL_IMG_READ_FMT_32_AS_8__SI    = 38,
TCP_PERF_SEL_IMG_READ_FMT_32_AS_16__SI   = 39,
TCP_PERF_SEL_IMG_READ_FMT_32_AS_128__SI  = 40,
TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE__SI = 41,
TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE__SI = 42,
TCP_PERF_SEL_IMG_READ_FMT_96__SI         = 43,
TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE__SI = 44,
TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE__SI = 45,
TCP_PERF_SEL_IMG_READ_FMT_BC1__SI        = 46,
TCP_PERF_SEL_IMG_READ_FMT_BC2__SI        = 47,
TCP_PERF_SEL_IMG_READ_FMT_BC3__SI        = 48,
TCP_PERF_SEL_IMG_READ_FMT_BC4__SI        = 49,
TCP_PERF_SEL_IMG_READ_FMT_BC5__SI        = 50,
TCP_PERF_SEL_IMG_READ_FMT_BC6__SI        = 51,
TCP_PERF_SEL_IMG_READ_FMT_BC7__SI        = 52,
TCP_PERF_SEL_IMG_READ_FMT_I8__SI         = 53,
TCP_PERF_SEL_IMG_READ_FMT_I16__SI        = 54,
TCP_PERF_SEL_IMG_READ_FMT_I32__SI        = 55,
TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8__SI   = 56,
TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16__SI  = 57,
TCP_PERF_SEL_IMG_READ_FMT_D8__SI         = 58,
TCP_PERF_SEL_IMG_READ_FMT_D16__SI        = 59,
TCP_PERF_SEL_IMG_READ_FMT_D32__SI        = 60,
TCP_PERF_SEL_IMG_WRITE_FMT_8__SI         = 61,
TCP_PERF_SEL_IMG_WRITE_FMT_16__SI        = 62,
TCP_PERF_SEL_IMG_WRITE_FMT_32__SI        = 63,
TCP_PERF_SEL_IMG_WRITE_FMT_64__SI        = 64,
TCP_PERF_SEL_IMG_WRITE_FMT_128__SI       = 65,
TCP_PERF_SEL_IMG_WRITE_FMT_D8__SI        = 66,
TCP_PERF_SEL_IMG_WRITE_FMT_D16__SI       = 67,
TCP_PERF_SEL_IMG_WRITE_FMT_D32__SI       = 68,
TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32__SI = 69,
TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32__SI = 70,
TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64__SI = 71,
TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64__SI = 72,
TCP_PERF_SEL_BUF_READ_FMT_8__SI          = 73,
TCP_PERF_SEL_BUF_READ_FMT_16__SI         = 74,
TCP_PERF_SEL_BUF_READ_FMT_32__SI         = 75,
TCP_PERF_SEL_BUF_WRITE_FMT_8__SI         = 76,
TCP_PERF_SEL_BUF_WRITE_FMT_16__SI        = 77,
TCP_PERF_SEL_BUF_WRITE_FMT_32__SI        = 78,
TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32__SI = 79,
TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32__SI = 80,
TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64__SI = 81,
TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64__SI = 82,
TCP_PERF_SEL_ARR_LINEAR_GENERAL__SI      = 83,
TCP_PERF_SEL_ARR_LINEAR_ALIGNED__SI      = 84,
TCP_PERF_SEL_ARR_1D_THIN1__SI            = 85,
TCP_PERF_SEL_ARR_1D_THICK__SI            = 86,
TCP_PERF_SEL_ARR_2D_THIN1__SI            = 87,
TCP_PERF_SEL_ARR_2D_THICK__SI            = 88,
TCP_PERF_SEL_ARR_2D_XTHICK__SI           = 89,
TCP_PERF_SEL_ARR_3D_THIN1__SI            = 90,
TCP_PERF_SEL_ARR_3D_THICK__SI            = 91,
TCP_PERF_SEL_ARR_3D_XTHICK__SI           = 92,
TCP_PERF_SEL_DIM_1D__SI                  = 93,
TCP_PERF_SEL_DIM_2D__SI                  = 94,
TCP_PERF_SEL_DIM_3D__SI                  = 95,
TCP_PERF_SEL_DIM_1D_ARRAY__SI            = 96,
TCP_PERF_SEL_DIM_2D_ARRAY__SI            = 97,
TCP_PERF_SEL_DIM_2D_MSAA__SI             = 98,
TCP_PERF_SEL_DIM_2D_ARRAY_MSAA__SI       = 99,
TCP_PERF_SEL_DIM_CUBE_ARRAY__SI          = 100,
TCP_PERF_SEL_CP_TCP_INVALIDATE__SI       = 101,
TCP_PERF_SEL_TA_TCP_STATE_READ__SI       = 102,
TCP_PERF_SEL_TAGRAM0_REQ__SI             = 103,
TCP_PERF_SEL_TAGRAM1_REQ__SI             = 104,
TCP_PERF_SEL_TAGRAM2_REQ__SI             = 105,
TCP_PERF_SEL_TAGRAM3_REQ__SI             = 106,
TCP_PERF_SEL_GATE_EN1__SI                = 107,
TCP_PERF_SEL_GATE_EN2__SI                = 108,
TCP_PERF_SEL_CORE_REG_SCLK_VLD__SI       = 109,
} TCP_PERFCOUNT_SELECT;

typedef enum TCP_WATCH_MODES {
TCP_WATCH_MODE_READ                      = 0x00000000,
TCP_WATCH_MODE_NONREAD                   = 0x00000001,
TCP_WATCH_MODE_ATOMIC                    = 0x00000002,
TCP_WATCH_MODE_ALL                       = 0x00000003,
} TCP_WATCH_MODES;

typedef enum TCS_PERF_SEL {
TCS_PERF_SEL_NONE                        = 0x00000000,
TCS_PERF_SEL_CYCLE                       = 0x00000001,
TCS_PERF_SEL_BUSY                        = 0x00000002,
TCS_PERF_SEL_REQ                         = 0x00000003,
TCS_PERF_SEL_READ                        = 0x00000004,
TCS_PERF_SEL_WRITE                       = 0x00000005,
TCS_PERF_SEL_ATOMIC                      = 0x00000006,
TCS_PERF_SEL_HOLE_FIFO_FULL              = 0x00000007,
TCS_PERF_SEL_REQ_FIFO_FULL               = 0x00000008,
TCS_PERF_SEL_REQ_CREDIT_STALL            = 0x00000009,
TCS_PERF_SEL_REQ_NO_SRC_DATA_STALL       = 0x0000000a,
TCS_PERF_SEL_REQ_STALL                   = 0x0000000b,
TCS_PERF_SEL_TCS_CHUB_REQ_SEND           = 0x0000000c,
TCS_PERF_SEL_CHUB_TCS_RET_SEND           = 0x0000000d,
TCS_PERF_SEL_RETURN_ACK                  = 0x0000000e,
TCS_PERF_SEL_RETURN_DATA                 = 0x0000000f,
TCS_PERF_SEL_IB_TOTAL_REQUESTS_STALL     = 0x00000010,
TCS_PERF_SEL_IB_STALL                    = 0x00000011,
TCS_PERF_SEL_TCA_LEVEL                   = 0x00000012,
TCS_PERF_SEL_HOLE_LEVEL                  = 0x00000013,
TCS_PERF_SEL_CHUB_LEVEL                  = 0x00000014,
TCS_PERF_SEL_CLIENT0_REQ                 = 0x00000040,
TCS_PERF_SEL_CLIENT1_REQ                 = 0x00000041,
TCS_PERF_SEL_CLIENT2_REQ                 = 0x00000042,
TCS_PERF_SEL_CLIENT3_REQ                 = 0x00000043,
TCS_PERF_SEL_CLIENT4_REQ                 = 0x00000044,
TCS_PERF_SEL_CLIENT5_REQ                 = 0x00000045,
TCS_PERF_SEL_CLIENT6_REQ                 = 0x00000046,
TCS_PERF_SEL_CLIENT7_REQ                 = 0x00000047,
TCS_PERF_SEL_CLIENT8_REQ                 = 0x00000048,
TCS_PERF_SEL_CLIENT9_REQ                 = 0x00000049,
TCS_PERF_SEL_CLIENT10_REQ                = 0x0000004a,
TCS_PERF_SEL_CLIENT11_REQ                = 0x0000004b,
TCS_PERF_SEL_CLIENT12_REQ                = 0x0000004c,
TCS_PERF_SEL_CLIENT13_REQ                = 0x0000004d,
TCS_PERF_SEL_CLIENT14_REQ                = 0x0000004e,
TCS_PERF_SEL_CLIENT15_REQ                = 0x0000004f,
TCS_PERF_SEL_CLIENT16_REQ                = 0x00000050,
TCS_PERF_SEL_CLIENT17_REQ                = 0x00000051,
TCS_PERF_SEL_CLIENT18_REQ                = 0x00000052,
TCS_PERF_SEL_CLIENT19_REQ                = 0x00000053,
TCS_PERF_SEL_CLIENT20_REQ                = 0x00000054,
TCS_PERF_SEL_CLIENT21_REQ                = 0x00000055,
TCS_PERF_SEL_CLIENT22_REQ                = 0x00000056,
TCS_PERF_SEL_CLIENT23_REQ                = 0x00000057,
TCS_PERF_SEL_CLIENT24_REQ                = 0x00000058,
TCS_PERF_SEL_CLIENT25_REQ                = 0x00000059,
TCS_PERF_SEL_CLIENT26_REQ                = 0x0000005a,
TCS_PERF_SEL_CLIENT27_REQ                = 0x0000005b,
TCS_PERF_SEL_CLIENT28_REQ                = 0x0000005c,
TCS_PERF_SEL_CLIENT29_REQ                = 0x0000005d,
TCS_PERF_SEL_CLIENT30_REQ                = 0x0000005e,
TCS_PERF_SEL_CLIENT31_REQ                = 0x0000005f,
TCS_PERF_SEL_CLIENT32_REQ                = 0x00000060,
TCS_PERF_SEL_CLIENT33_REQ                = 0x00000061,
TCS_PERF_SEL_CLIENT34_REQ                = 0x00000062,
TCS_PERF_SEL_CLIENT35_REQ                = 0x00000063,
TCS_PERF_SEL_CLIENT36_REQ                = 0x00000064,
TCS_PERF_SEL_CLIENT37_REQ                = 0x00000065,
TCS_PERF_SEL_CLIENT38_REQ                = 0x00000066,
TCS_PERF_SEL_CLIENT39_REQ                = 0x00000067,
TCS_PERF_SEL_CLIENT40_REQ                = 0x00000068,
TCS_PERF_SEL_CLIENT41_REQ                = 0x00000069,
TCS_PERF_SEL_CLIENT42_REQ                = 0x0000006a,
TCS_PERF_SEL_CLIENT43_REQ                = 0x0000006b,
TCS_PERF_SEL_CLIENT44_REQ                = 0x0000006c,
TCS_PERF_SEL_CLIENT45_REQ                = 0x0000006d,
TCS_PERF_SEL_CLIENT46_REQ                = 0x0000006e,
TCS_PERF_SEL_CLIENT47_REQ                = 0x0000006f,
TCS_PERF_SEL_CLIENT48_REQ                = 0x00000070,
TCS_PERF_SEL_CLIENT49_REQ                = 0x00000071,
TCS_PERF_SEL_CLIENT50_REQ                = 0x00000072,
TCS_PERF_SEL_CLIENT51_REQ                = 0x00000073,
TCS_PERF_SEL_CLIENT52_REQ                = 0x00000074,
TCS_PERF_SEL_CLIENT53_REQ                = 0x00000075,
TCS_PERF_SEL_CLIENT54_REQ                = 0x00000076,
TCS_PERF_SEL_CLIENT55_REQ                = 0x00000077,
TCS_PERF_SEL_CLIENT56_REQ                = 0x00000078,
TCS_PERF_SEL_CLIENT57_REQ                = 0x00000079,
TCS_PERF_SEL_CLIENT58_REQ                = 0x0000007a,
TCS_PERF_SEL_CLIENT59_REQ                = 0x0000007b,
TCS_PERF_SEL_CLIENT60_REQ                = 0x0000007c,
TCS_PERF_SEL_CLIENT61_REQ                = 0x0000007d,
TCS_PERF_SEL_CLIENT62_REQ                = 0x0000007e,
TCS_PERF_SEL_CLIENT63_REQ                = 0x0000007f,
} TCS_PERF_SEL;

typedef enum TC_CHUB_REQ_CREDITS_ENUM {
TC_CHUB_REQ_CREDITS                      = 0x00000010,
} TC_CHUB_REQ_CREDITS_ENUM;

typedef enum TC_NACKS {
TC_NACK_NO_FAULT                         = 0x00000000,
TC_NACK_PAGE_FAULT                       = 0x00000001,
TC_NACK_PROTECTION_FAULT                 = 0x00000002,
TC_NACK_DATA_ERROR                       = 0x00000003,
} TC_NACKS;

typedef enum TC_OP {
TC_OP_READ                               = 0x00000000,
TC_OP_ATOMIC_FCMPSWAP_RTN_32             = 0x00000001,
TC_OP_ATOMIC_FMIN_RTN_32                 = 0x00000002,
TC_OP_ATOMIC_FMAX_RTN_32                 = 0x00000003,
TC_OP_RESERVED_FOP_RTN_32_0              = 0x00000004,
TC_OP_RESERVED_FOP_RTN_32_1              = 0x00000005,
TC_OP_RESERVED_FOP_RTN_32_2              = 0x00000006,
TC_OP_ATOMIC_SWAP_RTN_32                 = 0x00000007,
TC_OP_ATOMIC_CMPSWAP_RTN_32              = 0x00000008,
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32    = 0x0000000a,
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32    = 0x0000000b,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0x0000000c,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
TC_OP_ATOMIC_ADD_RTN_32                  = 0x0000000f,
TC_OP_ATOMIC_SUB_RTN_32                  = 0x00000010,
TC_OP_ATOMIC_SMIN_RTN_32__CI__VI         = 0x00000011,
TC_OP_ATOMIC_SMIN_RTN_32__SI             = 0x00000012,
TC_OP_ATOMIC_UMIN_RTN_32__CI__VI         = 0x00000012,
TC_OP_ATOMIC_UMIN_RTN_32__SI             = 0x00000013,
TC_OP_ATOMIC_SMAX_RTN_32__CI__VI         = 0x00000013,
TC_OP_ATOMIC_SMAX_RTN_32__SI             = 0x00000014,
TC_OP_ATOMIC_UMAX_RTN_32__CI__VI         = 0x00000014,
TC_OP_ATOMIC_UMAX_RTN_32__SI             = 0x00000015,
TC_OP_ATOMIC_AND_RTN_32__CI__VI          = 0x00000015,
TC_OP_ATOMIC_AND_RTN_32__SI              = 0x00000016,
TC_OP_ATOMIC_OR_RTN_32__CI__VI           = 0x00000016,
TC_OP_ATOMIC_OR_RTN_32__SI               = 0x00000017,
TC_OP_ATOMIC_XOR_RTN_32__CI__VI          = 0x00000017,
TC_OP_ATOMIC_XOR_RTN_32__SI              = 0x00000018,
TC_OP_ATOMIC_INC_RTN_32__CI__VI          = 0x00000018,
TC_OP_ATOMIC_INC_RTN_32__SI              = 0x00000019,
TC_OP_ATOMIC_DEC_RTN_32__CI__VI          = 0x00000019,
TC_OP_ATOMIC_DEC_RTN_32__SI              = 0x0000001a,
TC_OP_WBINVL1_VOL__CI__VI                = 0x0000001a,
TC_OP_RESERVED_NON_FLOAT_RTN_32_0__SI__CI = 0x0000001b,
TC_OP_WBINVL1_SD__VI                     = 0x0000001b,
TC_OP_RESERVED_NON_FLOAT_RTN_32_1__SI__CI = 0x0000001c,
TC_OP_RESERVED_NON_FLOAT_RTN_32_0__VI    = 0x0000001c,
TC_OP_RESERVED_NON_FLOAT_RTN_32_2__SI__CI = 0x0000001d,
TC_OP_RESERVED_NON_FLOAT_RTN_32_1__VI    = 0x0000001d,
TC_OP_RESERVED_NON_FLOAT_RTN_32_3__SI__CI = 0x0000001e,
TC_OP_RESERVED_NON_FLOAT_RTN_32_2__VI    = 0x0000001e,
TC_OP_RESERVED_NON_FLOAT_RTN_32_4__SI__CI = 0x0000001f,
TC_OP_RESERVED_NON_FLOAT_RTN_32_3__VI    = 0x0000001f,
TC_OP_WRITE                              = 0x00000020,
TC_OP_ATOMIC_FCMPSWAP_RTN_64             = 0x00000021,
TC_OP_ATOMIC_FMIN_RTN_64                 = 0x00000022,
TC_OP_ATOMIC_FMAX_RTN_64                 = 0x00000023,
TC_OP_RESERVED_FOP_RTN_64_0              = 0x00000024,
TC_OP_RESERVED_FOP_RTN_64_1              = 0x00000025,
TC_OP_RESERVED_FOP_RTN_64_2              = 0x00000026,
TC_OP_ATOMIC_SWAP_RTN_64                 = 0x00000027,
TC_OP_ATOMIC_CMPSWAP_RTN_64              = 0x00000028,
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64    = 0x0000002a,
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64    = 0x0000002b,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0__SI__CI = 0x0000002c,
TC_OP_WBINVL2_SD__VI                     = 0x0000002c,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1__SI__CI = 0x0000002d,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0__VI = 0x0000002d,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_2__SI__CI = 0x0000002e,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1__VI = 0x0000002e,
TC_OP_ATOMIC_ADD_RTN_64                  = 0x0000002f,
TC_OP_ATOMIC_SUB_RTN_64                  = 0x00000030,
TC_OP_ATOMIC_SMIN_RTN_64__CI__VI         = 0x00000031,
TC_OP_ATOMIC_SMIN_RTN_64__SI             = 0x00000032,
TC_OP_ATOMIC_UMIN_RTN_64__CI__VI         = 0x00000032,
TC_OP_ATOMIC_UMIN_RTN_64__SI             = 0x00000033,
TC_OP_ATOMIC_SMAX_RTN_64__CI__VI         = 0x00000033,
TC_OP_ATOMIC_SMAX_RTN_64__SI             = 0x00000034,
TC_OP_ATOMIC_UMAX_RTN_64__CI__VI         = 0x00000034,
TC_OP_ATOMIC_UMAX_RTN_64__SI             = 0x00000035,
TC_OP_ATOMIC_AND_RTN_64__CI__VI          = 0x00000035,
TC_OP_ATOMIC_AND_RTN_64__SI              = 0x00000036,
TC_OP_ATOMIC_OR_RTN_64__CI__VI           = 0x00000036,
TC_OP_ATOMIC_OR_RTN_64__SI               = 0x00000037,
TC_OP_ATOMIC_XOR_RTN_64__CI__VI          = 0x00000037,
TC_OP_ATOMIC_XOR_RTN_64__SI              = 0x00000038,
TC_OP_ATOMIC_INC_RTN_64__CI__VI          = 0x00000038,
TC_OP_ATOMIC_INC_RTN_64__SI              = 0x00000039,
TC_OP_ATOMIC_DEC_RTN_64__CI__VI          = 0x00000039,
TC_OP_ATOMIC_DEC_RTN_64__SI              = 0x0000003a,
TC_OP_WBL2_VOL__CI                       = 0x0000003a,
TC_OP_WBL2_NC__VI                        = 0x0000003a,
TC_OP_RESERVED_NON_FLOAT_RTN_64_0        = 0x0000003b,
TC_OP_RESERVED_NON_FLOAT_RTN_64_1        = 0x0000003c,
TC_OP_RESERVED_NON_FLOAT_RTN_64_2        = 0x0000003d,
TC_OP_RESERVED_NON_FLOAT_RTN_64_3        = 0x0000003e,
TC_OP_RESERVED_NON_FLOAT_RTN_64_4        = 0x0000003f,
TC_OP_WBINVL1                            = 0x00000040,
TC_OP_ATOMIC_FCMPSWAP_32                 = 0x00000041,
TC_OP_ATOMIC_FMIN_32                     = 0x00000042,
TC_OP_ATOMIC_FMAX_32                     = 0x00000043,
TC_OP_RESERVED_FOP_32_0                  = 0x00000044,
TC_OP_RESERVED_FOP_32_1                  = 0x00000045,
TC_OP_RESERVED_FOP_32_2                  = 0x00000046,
TC_OP_ATOMIC_SWAP_32                     = 0x00000047,
TC_OP_ATOMIC_CMPSWAP_32                  = 0x00000048,
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32    = 0x00000049,
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32        = 0x0000004a,
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32        = 0x0000004b,
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0     = 0x0000004c,
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1     = 0x0000004d,
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2     = 0x0000004e,
TC_OP_ATOMIC_ADD_32                      = 0x0000004f,
TC_OP_ATOMIC_SUB_32                      = 0x00000050,
TC_OP_ATOMIC_SMIN_32__CI__VI             = 0x00000051,
TC_OP_ATOMIC_SMIN_32__SI                 = 0x00000052,
TC_OP_ATOMIC_UMIN_32__CI__VI             = 0x00000052,
TC_OP_ATOMIC_UMIN_32__SI                 = 0x00000053,
TC_OP_ATOMIC_SMAX_32__CI__VI             = 0x00000053,
TC_OP_ATOMIC_SMAX_32__SI                 = 0x00000054,
TC_OP_ATOMIC_UMAX_32__CI__VI             = 0x00000054,
TC_OP_ATOMIC_UMAX_32__SI                 = 0x00000055,
TC_OP_ATOMIC_AND_32__CI__VI              = 0x00000055,
TC_OP_ATOMIC_AND_32__SI                  = 0x00000056,
TC_OP_ATOMIC_OR_32__CI__VI               = 0x00000056,
TC_OP_ATOMIC_OR_32__SI                   = 0x00000057,
TC_OP_ATOMIC_XOR_32__CI__VI              = 0x00000057,
TC_OP_ATOMIC_XOR_32__SI                  = 0x00000058,
TC_OP_ATOMIC_INC_32__CI__VI              = 0x00000058,
TC_OP_ATOMIC_INC_32__SI                  = 0x00000059,
TC_OP_ATOMIC_DEC_32__CI__VI              = 0x00000059,
TC_OP_ATOMIC_DEC_32__SI                  = 0x0000005a,
TC_OP_INVL2_VOL__CI                      = 0x0000005a,
TC_OP_INVL2_NC__VI                       = 0x0000005a,
TC_OP_RESERVED_NON_FLOAT_32_0            = 0x0000005b,
TC_OP_RESERVED_NON_FLOAT_32_1            = 0x0000005c,
TC_OP_RESERVED_NON_FLOAT_32_2            = 0x0000005d,
TC_OP_RESERVED_NON_FLOAT_32_3            = 0x0000005e,
TC_OP_RESERVED_NON_FLOAT_32_4            = 0x0000005f,
TC_OP_WBINVL2                            = 0x00000060,
TC_OP_ATOMIC_FCMPSWAP_64                 = 0x00000061,
TC_OP_ATOMIC_FMIN_64                     = 0x00000062,
TC_OP_ATOMIC_FMAX_64                     = 0x00000063,
TC_OP_RESERVED_FOP_64_0                  = 0x00000064,
TC_OP_RESERVED_FOP_64_1                  = 0x00000065,
TC_OP_RESERVED_FOP_64_2                  = 0x00000066,
TC_OP_ATOMIC_SWAP_64                     = 0x00000067,
TC_OP_ATOMIC_CMPSWAP_64                  = 0x00000068,
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64    = 0x00000069,
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64        = 0x0000006a,
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64        = 0x0000006b,
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0     = 0x0000006c,
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1     = 0x0000006d,
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2     = 0x0000006e,
TC_OP_ATOMIC_ADD_64                      = 0x0000006f,
TC_OP_ATOMIC_SUB_64                      = 0x00000070,
TC_OP_ATOMIC_SMIN_64__CI__VI             = 0x00000071,
TC_OP_ATOMIC_SMIN_64__SI                 = 0x00000072,
TC_OP_ATOMIC_UMIN_64__CI__VI             = 0x00000072,
TC_OP_ATOMIC_UMIN_64__SI                 = 0x00000073,
TC_OP_ATOMIC_SMAX_64__CI__VI             = 0x00000073,
TC_OP_ATOMIC_SMAX_64__SI                 = 0x00000074,
TC_OP_ATOMIC_UMAX_64__CI__VI             = 0x00000074,
TC_OP_ATOMIC_UMAX_64__SI                 = 0x00000075,
TC_OP_ATOMIC_AND_64__CI__VI              = 0x00000075,
TC_OP_ATOMIC_AND_64__SI                  = 0x00000076,
TC_OP_ATOMIC_OR_64__CI__VI               = 0x00000076,
TC_OP_ATOMIC_OR_64__SI                   = 0x00000077,
TC_OP_ATOMIC_XOR_64__CI__VI              = 0x00000077,
TC_OP_ATOMIC_XOR_64__SI                  = 0x00000078,
TC_OP_ATOMIC_INC_64__CI__VI              = 0x00000078,
TC_OP_ATOMIC_INC_64__SI                  = 0x00000079,
TC_OP_ATOMIC_DEC_64__CI__VI              = 0x00000079,
TC_OP_ATOMIC_DEC_64__SI                  = 0x0000007a,
TC_OP_INVL1L2_VOL__CI                    = 0x0000007a,
TC_OP_WBINVL2_NC__VI                     = 0x0000007a,
TC_OP_RESERVED_NON_FLOAT_64_0            = 0x0000007b,
TC_OP_RESERVED_NON_FLOAT_64_1            = 0x0000007c,
TC_OP_RESERVED_NON_FLOAT_64_2            = 0x0000007d,
TC_OP_RESERVED_NON_FLOAT_64_3            = 0x0000007e,
TC_OP_RESERVED_NON_FLOAT_64_4            = 0x0000007f,
} TC_OP;

typedef enum TC_OP_MASKS {
TC_OP_MASK_FLUSH_DENROM                  = 0x00000008,
TC_OP_MASK_64                            = 0x00000020,
TC_OP_MASK_NO_RTN                        = 0x00000040,
} TC_OP_MASKS;

typedef enum TD_PERFCOUNT_SEL {
TD_PERF_SEL_td_busy__SI__CI              = 0x00000000,
TD_PERF_SEL_none__VI                     = 0x00000000,
TD_PERF_SEL_input_busy__SI__CI           = 0x00000001,
TD_PERF_SEL_td_busy__VI                  = 0x00000001,
TD_PERF_SEL_output_busy__SI__CI          = 0x00000002,
TD_PERF_SEL_input_busy__VI               = 0x00000002,
TD_PERF_SEL_lerp_busy__SI__CI            = 0x00000003,
TD_PERF_SEL_output_busy__VI              = 0x00000003,
TD_PERF_SEL_RESERVED_4__SI__CI           = 0x00000004,
TD_PERF_SEL_lerp_busy__VI                = 0x00000004,
TD_PERF_SEL_reg_sclk_vld                 = 0x00000005,
TD_PERF_SEL_local_cg_dyn_sclk_grp0_en    = 0x00000006,
TD_PERF_SEL_local_cg_dyn_sclk_grp1_en    = 0x00000007,
TD_PERF_SEL_local_cg_dyn_sclk_grp4_en    = 0x00000008,
TD_PERF_SEL_local_cg_dyn_sclk_grp5_en    = 0x00000009,
TD_PERF_SEL_tc_td_fifo_full              = 0x0000000a,
TD_PERF_SEL_constant_state_full          = 0x0000000b,
TD_PERF_SEL_sample_state_full            = 0x0000000c,
TD_PERF_SEL_output_fifo_full             = 0x0000000d,
TD_PERF_SEL_RESERVED_14                  = 0x0000000e,
TD_PERF_SEL_tc_stall                     = 0x0000000f,
TD_PERF_SEL_pc_stall                     = 0x00000010,
TD_PERF_SEL_gds_stall                    = 0x00000011,
TD_PERF_SEL_RESERVED_18                  = 0x00000012,
TD_PERF_SEL_RESERVED_19                  = 0x00000013,
TD_PERF_SEL_gather4_wavefront            = 0x00000014,
TD_PERF_SEL_sample_c_wavefront           = 0x00000015,
TD_PERF_SEL_load_wavefront               = 0x00000016,
TD_PERF_SEL_atomic_wavefront             = 0x00000017,
TD_PERF_SEL_store_wavefront              = 0x00000018,
TD_PERF_SEL_ldfptr_wavefront             = 0x00000019,
TD_PERF_SEL_RESERVED_26                  = 0x0000001a,
TD_PERF_SEL_RESERVED_27                  = 0x0000001b,
TD_PERF_SEL_RESERVED_28__SI__CI          = 0x0000001c,
TD_PERF_SEL_d16_en_wavefront__VI         = 0x0000001c,
TD_PERF_SEL_RESERVED_29__SI__CI          = 0x0000001d,
TD_PERF_SEL_bicubic_filter_wavefront__VI = 0x0000001d,
TD_PERF_SEL_bypass_filter_wavefront      = 0x0000001e,
TD_PERF_SEL_min_max_filter_wavefront     = 0x0000001f,
TD_PERF_SEL_coalescable_wavefront        = 0x00000020,
TD_PERF_SEL_coalesced_phase              = 0x00000021,
TD_PERF_SEL_four_phase_wavefront         = 0x00000022,
TD_PERF_SEL_eight_phase_wavefront        = 0x00000023,
TD_PERF_SEL_sixteen_phase_wavefront      = 0x00000024,
TD_PERF_SEL_four_phase_forward_wavefront = 0x00000025,
TD_PERF_SEL_write_ack_wavefront          = 0x00000026,
TD_PERF_SEL_RESERVED_39                  = 0x00000027,
TD_PERF_SEL_user_defined_border          = 0x00000028,
TD_PERF_SEL_white_border                 = 0x00000029,
TD_PERF_SEL_opaque_black_border          = 0x0000002a,
TD_PERF_SEL_RESERVED_43                  = 0x0000002b,
TD_PERF_SEL_RESERVED_44                  = 0x0000002c,
TD_PERF_SEL_nack                         = 0x0000002d,
TD_PERF_SEL_consume_gds_traffic__SI      = 0x0000002e,
TD_PERF_SEL_td_sp_traffic__CI__VI        = 0x0000002e,
TD_PERF_SEL_addresscmd_poison__SI        = 0x0000002f,
TD_PERF_SEL_consume_gds_traffic__CI__VI  = 0x0000002f,
TD_PERF_SEL_data_poison__SI              = 0x00000030,
TD_PERF_SEL_addresscmd_poison__CI__VI    = 0x00000030,
TD_PERF_SEL_data_poison__CI__VI          = 0x00000031,
TD_PERF_SEL_start_cycle_0__CI__VI        = 0x00000032,
TD_PERF_SEL_start_cycle_1__CI__VI        = 0x00000033,
TD_PERF_SEL_start_cycle_2__CI__VI        = 0x00000034,
TD_PERF_SEL_start_cycle_3__CI__VI        = 0x00000035,
TD_PERF_SEL_null_cycle_output__CI__VI    = 0x00000036,
} TD_PERFCOUNT_SEL;

typedef enum TEX_BORDER_COLOR_TYPE {
TEX_BorderColor_TransparentBlack         = 0x00000000,
TEX_BorderColor_OpaqueBlack              = 0x00000001,
TEX_BorderColor_OpaqueWhite              = 0x00000002,
TEX_BorderColor_Register                 = 0x00000003,
} TEX_BORDER_COLOR_TYPE;

typedef enum TEX_CHROMA_KEY {
TEX_ChromaKey_Disabled                   = 0x00000000,
TEX_ChromaKey_Kill                       = 0x00000001,
TEX_ChromaKey_Blend                      = 0x00000002,
TEX_ChromaKey_RESERVED_3                 = 0x00000003,
} TEX_CHROMA_KEY;

typedef enum TEX_CLAMP {
TEX_Clamp_Repeat                         = 0x00000000,
TEX_Clamp_Mirror                         = 0x00000001,
TEX_Clamp_ClampToLast                    = 0x00000002,
TEX_Clamp_MirrorOnceToLast               = 0x00000003,
TEX_Clamp_ClampHalfToBorder              = 0x00000004,
TEX_Clamp_MirrorOnceHalfToBorder         = 0x00000005,
TEX_Clamp_ClampToBorder                  = 0x00000006,
TEX_Clamp_MirrorOnceToBorder             = 0x00000007,
} TEX_CLAMP;

typedef enum TEX_COORD_TYPE {
TEX_CoordType_Unnormalized               = 0x00000000,
TEX_CoordType_Normalized                 = 0x00000001,
} TEX_COORD_TYPE;

typedef enum TEX_DEPTH_COMPARE_FUNCTION {
TEX_DepthCompareFunction_Never           = 0x00000000,
TEX_DepthCompareFunction_Less            = 0x00000001,
TEX_DepthCompareFunction_Equal           = 0x00000002,
TEX_DepthCompareFunction_LessEqual       = 0x00000003,
TEX_DepthCompareFunction_Greater         = 0x00000004,
TEX_DepthCompareFunction_NotEqual        = 0x00000005,
TEX_DepthCompareFunction_GreaterEqual    = 0x00000006,
TEX_DepthCompareFunction_Always          = 0x00000007,
} TEX_DEPTH_COMPARE_FUNCTION;

typedef enum TEX_DIM {
TEX_Dim_1D                               = 0x00000000,
TEX_Dim_2D                               = 0x00000001,
TEX_Dim_3D                               = 0x00000002,
TEX_Dim_CubeMap                          = 0x00000003,
TEX_Dim_1DArray                          = 0x00000004,
TEX_Dim_2DArray                          = 0x00000005,
TEX_Dim_2D_MSAA                          = 0x00000006,
TEX_Dim_2DArray_MSAA                     = 0x00000007,
} TEX_DIM;

typedef enum TEX_FORMAT_COMP {
TEX_FormatComp_Unsigned                  = 0x00000000,
TEX_FormatComp_Signed                    = 0x00000001,
TEX_FormatComp_UnsignedBiased            = 0x00000002,
TEX_FormatComp_RESERVED_3                = 0x00000003,
} TEX_FORMAT_COMP;

typedef enum TEX_MAX_ANISO_RATIO {
TEX_MaxAnisoRatio_1to1                   = 0x00000000,
TEX_MaxAnisoRatio_2to1                   = 0x00000001,
TEX_MaxAnisoRatio_4to1                   = 0x00000002,
TEX_MaxAnisoRatio_8to1                   = 0x00000003,
TEX_MaxAnisoRatio_16to1                  = 0x00000004,
TEX_MaxAnisoRatio_RESERVED_5             = 0x00000005,
TEX_MaxAnisoRatio_RESERVED_6             = 0x00000006,
TEX_MaxAnisoRatio_RESERVED_7             = 0x00000007,
} TEX_MAX_ANISO_RATIO;

typedef enum TEX_MIP_FILTER {
TEX_MipFilter_None                       = 0x00000000,
TEX_MipFilter_Point                      = 0x00000001,
TEX_MipFilter_Linear                     = 0x00000002,
TEX_MipFilter_RESERVED_3__SI__CI         = 0x00000003,
TEX_MipFilter_Point_Aniso_Adj__VI        = 0x00000003,
} TEX_MIP_FILTER;

typedef enum TEX_REQUEST_SIZE {
TEX_RequestSize_32B                      = 0x00000000,
TEX_RequestSize_64B                      = 0x00000001,
TEX_RequestSize_128B                     = 0x00000002,
TEX_RequestSize_2X64B                    = 0x00000003,
} TEX_REQUEST_SIZE;

typedef enum TEX_SAMPLER_TYPE {
TEX_SamplerType_Invalid                  = 0x00000000,
TEX_SamplerType_Valid                    = 0x00000001,
} TEX_SAMPLER_TYPE;

typedef enum TEX_XY_FILTER {
TEX_XYFilter_Point                       = 0x00000000,
TEX_XYFilter_Linear                      = 0x00000001,
TEX_XYFilter_AnisoPoint                  = 0x00000002,
TEX_XYFilter_AnisoLinear                 = 0x00000003,
} TEX_XY_FILTER;

typedef enum TEX_Z_FILTER {
TEX_ZFilter_None                         = 0x00000000,
TEX_ZFilter_Point                        = 0x00000001,
TEX_ZFilter_Linear                       = 0x00000002,
TEX_ZFilter_RESERVED_3                   = 0x00000003,
} TEX_Z_FILTER;

typedef enum TVX_DATA_FORMAT {
TVX_FMT_INVALID                          = 0x00000000,
TVX_FMT_8                                = 0x00000001,
TVX_FMT_4_4                              = 0x00000002,
TVX_FMT_3_3_2                            = 0x00000003,
TVX_FMT_RESERVED_4                       = 0x00000004,
TVX_FMT_16                               = 0x00000005,
TVX_FMT_16_FLOAT                         = 0x00000006,
TVX_FMT_8_8                              = 0x00000007,
TVX_FMT_5_6_5                            = 0x00000008,
TVX_FMT_6_5_5                            = 0x00000009,
TVX_FMT_1_5_5_5                          = 0x0000000a,
TVX_FMT_4_4_4_4                          = 0x0000000b,
TVX_FMT_5_5_5_1                          = 0x0000000c,
TVX_FMT_32                               = 0x0000000d,
TVX_FMT_32_FLOAT                         = 0x0000000e,
TVX_FMT_16_16                            = 0x0000000f,
TVX_FMT_16_16_FLOAT                      = 0x00000010,
TVX_FMT_8_24                             = 0x00000011,
TVX_FMT_8_24_FLOAT                       = 0x00000012,
TVX_FMT_24_8                             = 0x00000013,
TVX_FMT_24_8_FLOAT                       = 0x00000014,
TVX_FMT_10_11_11                         = 0x00000015,
TVX_FMT_10_11_11_FLOAT                   = 0x00000016,
TVX_FMT_11_11_10                         = 0x00000017,
TVX_FMT_11_11_10_FLOAT                   = 0x00000018,
TVX_FMT_2_10_10_10                       = 0x00000019,
TVX_FMT_8_8_8_8                          = 0x0000001a,
TVX_FMT_10_10_10_2                       = 0x0000001b,
TVX_FMT_X24_8_32_FLOAT                   = 0x0000001c,
TVX_FMT_32_32                            = 0x0000001d,
TVX_FMT_32_32_FLOAT                      = 0x0000001e,
TVX_FMT_16_16_16_16                      = 0x0000001f,
TVX_FMT_16_16_16_16_FLOAT                = 0x00000020,
TVX_FMT_RESERVED_33                      = 0x00000021,
TVX_FMT_32_32_32_32                      = 0x00000022,
TVX_FMT_32_32_32_32_FLOAT                = 0x00000023,
TVX_FMT_RESERVED_36                      = 0x00000024,
TVX_FMT_1                                = 0x00000025,
TVX_FMT_1_REVERSED                       = 0x00000026,
TVX_FMT_GB_GR                            = 0x00000027,
TVX_FMT_BG_RG                            = 0x00000028,
TVX_FMT_32_AS_8                          = 0x00000029,
TVX_FMT_32_AS_8_8                        = 0x0000002a,
TVX_FMT_5_9_9_9_SHAREDEXP                = 0x0000002b,
TVX_FMT_8_8_8                            = 0x0000002c,
TVX_FMT_16_16_16                         = 0x0000002d,
TVX_FMT_16_16_16_FLOAT                   = 0x0000002e,
TVX_FMT_32_32_32                         = 0x0000002f,
TVX_FMT_32_32_32_FLOAT                   = 0x00000030,
TVX_FMT_BC1                              = 0x00000031,
TVX_FMT_BC2                              = 0x00000032,
TVX_FMT_BC3                              = 0x00000033,
TVX_FMT_BC4                              = 0x00000034,
TVX_FMT_BC5                              = 0x00000035,
TVX_FMT_APC0                             = 0x00000036,
TVX_FMT_APC1                             = 0x00000037,
TVX_FMT_APC2                             = 0x00000038,
TVX_FMT_APC3                             = 0x00000039,
TVX_FMT_APC4                             = 0x0000003a,
TVX_FMT_APC5                             = 0x0000003b,
TVX_FMT_APC6                             = 0x0000003c,
TVX_FMT_APC7                             = 0x0000003d,
TVX_FMT_CTX1                             = 0x0000003e,
TVX_FMT_RESERVED_63                      = 0x0000003f,
} TVX_DATA_FORMAT;

typedef enum TVX_DST_SEL {
TVX_DstSel_X                             = 0x00000000,
TVX_DstSel_Y                             = 0x00000001,
TVX_DstSel_Z                             = 0x00000002,
TVX_DstSel_W                             = 0x00000003,
TVX_DstSel_0f                            = 0x00000004,
TVX_DstSel_1f                            = 0x00000005,
TVX_DstSel_RESERVED_6                    = 0x00000006,
TVX_DstSel_Mask                          = 0x00000007,
} TVX_DST_SEL;

typedef enum TVX_ENDIAN_SWAP {
TVX_EndianSwap_None                      = 0x00000000,
TVX_EndianSwap_8in16                     = 0x00000001,
TVX_EndianSwap_8in32                     = 0x00000002,
TVX_EndianSwap_8in64                     = 0x00000003,
} TVX_ENDIAN_SWAP;

typedef enum TVX_INST {
TVX_Inst_NormalVertexFetch               = 0x00000000,
TVX_Inst_SemanticVertexFetch             = 0x00000001,
TVX_Inst_RESERVED_2                      = 0x00000002,
TVX_Inst_LD                              = 0x00000003,
TVX_Inst_GetTextureResInfo               = 0x00000004,
TVX_Inst_GetNumberOfSamples              = 0x00000005,
TVX_Inst_GetLOD                          = 0x00000006,
TVX_Inst_GetGradientsH                   = 0x00000007,
TVX_Inst_GetGradientsV                   = 0x00000008,
TVX_Inst_SetTextureOffsets               = 0x00000009,
TVX_Inst_KeepGradients                   = 0x0000000a,
TVX_Inst_SetGradientsH                   = 0x0000000b,
TVX_Inst_SetGradientsV                   = 0x0000000c,
TVX_Inst_Pass                            = 0x0000000d,
TVX_Inst_GetBufferResInfo                = 0x0000000e,
TVX_Inst_RESERVED_15                     = 0x0000000f,
TVX_Inst_Sample                          = 0x00000010,
TVX_Inst_Sample_L                        = 0x00000011,
TVX_Inst_Sample_LB                       = 0x00000012,
TVX_Inst_Sample_LZ                       = 0x00000013,
TVX_Inst_Sample_G                        = 0x00000014,
TVX_Inst_Gather4                         = 0x00000015,
TVX_Inst_Sample_G_LB                     = 0x00000016,
TVX_Inst_Gather4_O                       = 0x00000017,
TVX_Inst_Sample_C                        = 0x00000018,
TVX_Inst_Sample_C_L                      = 0x00000019,
TVX_Inst_Sample_C_LB                     = 0x0000001a,
TVX_Inst_Sample_C_LZ                     = 0x0000001b,
TVX_Inst_Sample_C_G                      = 0x0000001c,
TVX_Inst_Gather4_C                       = 0x0000001d,
TVX_Inst_Sample_C_G_LB                   = 0x0000001e,
TVX_Inst_Gather4_C_O                     = 0x0000001f,
} TVX_INST;

typedef enum TVX_NUM_FORMAT_ALL {
TVX_NumFormatAll_Norm                    = 0x00000000,
TVX_NumFormatAll_Int                     = 0x00000001,
TVX_NumFormatAll_Scaled                  = 0x00000002,
TVX_NumFormatAll_RESERVED_3              = 0x00000003,
} TVX_NUM_FORMAT_ALL;

typedef enum TVX_SRC_SEL {
TVX_SrcSel_X                             = 0x00000000,
TVX_SrcSel_Y                             = 0x00000001,
TVX_SrcSel_Z                             = 0x00000002,
TVX_SrcSel_W                             = 0x00000003,
TVX_SrcSel_0f                            = 0x00000004,
TVX_SrcSel_1f                            = 0x00000005,
} TVX_SRC_SEL;

typedef enum TVX_SRF_MODE_ALL {
TVX_SRFModeAll_ZCMO                      = 0x00000000,
TVX_SRFModeAll_NZ                        = 0x00000001,
} TVX_SRF_MODE_ALL;

typedef enum TVX_TYPE {
TVX_Type_InvalidTextureResource          = 0x00000000,
TVX_Type_InvalidVertexBuffer             = 0x00000001,
TVX_Type_ValidTextureResource            = 0x00000002,
TVX_Type_ValidVertexBuffer               = 0x00000003,
} TVX_TYPE;

typedef enum TileSplit {
ADDR_SURF_TILE_SPLIT_64B                 = 0x00000000,
ADDR_SURF_TILE_SPLIT_128B                = 0x00000001,
ADDR_SURF_TILE_SPLIT_256B                = 0x00000002,
ADDR_SURF_TILE_SPLIT_512B                = 0x00000003,
ADDR_SURF_TILE_SPLIT_1KB                 = 0x00000004,
ADDR_SURF_TILE_SPLIT_2KB                 = 0x00000005,
ADDR_SURF_TILE_SPLIT_4KB                 = 0x00000006,
} TileSplit;

typedef enum TileType {
ARRAY_COLOR_TILE                         = 0x00000000,
ARRAY_DEPTH_TILE                         = 0x00000001,
} TileType;

typedef enum UVDFirmwareCommand {
UVDFC_FENCE                              = 0x00000000,
UVDFC_TRAP                               = 0x00000001,
UVDFC_DECODED_ADDR                       = 0x00000002,
UVDFC_MBLOCK_ADDR                        = 0x00000003,
UVDFC_ITBUF_ADDR                         = 0x00000004,
UVDFC_DISPLAY_ADDR                       = 0x00000005,
UVDFC_EOD                                = 0x00000006,
UVDFC_DISPLAY_PITCH                      = 0x00000007,
UVDFC_DISPLAY_TILING                     = 0x00000008,
UVDFC_BITSTREAM_ADDR                     = 0x00000009,
UVDFC_BITSTREAM_SIZE                     = 0x0000000a,
} UVDFirmwareCommand;

typedef enum VGT_CACHE_INVALID_MODE {
VC_ONLY                                  = 0x00000000,
TC_ONLY                                  = 0x00000001,
VC_AND_TC                                = 0x00000002,
} VGT_CACHE_INVALID_MODE;

typedef enum VGT_DI_INDEX_SIZE {
DI_INDEX_SIZE_16_BIT                     = 0x00000000,
DI_INDEX_SIZE_32_BIT                     = 0x00000001,
DI_INDEX_SIZE_8_BIT__VI                  = 0x00000002,
} VGT_DI_INDEX_SIZE;

typedef enum VGT_DI_MAJOR_MODE_SELECT {
DI_MAJOR_MODE_0                          = 0x00000000,
DI_MAJOR_MODE_1                          = 0x00000001,
} VGT_DI_MAJOR_MODE_SELECT;

typedef enum VGT_DI_PRIM_TYPE {
DI_PT_NONE                               = 0x00000000,
DI_PT_POINTLIST                          = 0x00000001,
DI_PT_LINELIST                           = 0x00000002,
DI_PT_LINESTRIP                          = 0x00000003,
DI_PT_TRILIST                            = 0x00000004,
DI_PT_TRIFAN                             = 0x00000005,
DI_PT_TRISTRIP                           = 0x00000006,
DI_PT_UNUSED_0                           = 0x00000007,
DI_PT_UNUSED_1                           = 0x00000008,
DI_PT_PATCH                              = 0x00000009,
DI_PT_LINELIST_ADJ                       = 0x0000000a,
DI_PT_LINESTRIP_ADJ                      = 0x0000000b,
DI_PT_TRILIST_ADJ                        = 0x0000000c,
DI_PT_TRISTRIP_ADJ                       = 0x0000000d,
DI_PT_UNUSED_3                           = 0x0000000e,
DI_PT_UNUSED_4                           = 0x0000000f,
DI_PT_TRI_WITH_WFLAGS                    = 0x00000010,
DI_PT_RECTLIST                           = 0x00000011,
DI_PT_LINELOOP                           = 0x00000012,
DI_PT_QUADLIST                           = 0x00000013,
DI_PT_QUADSTRIP                          = 0x00000014,
DI_PT_POLYGON                            = 0x00000015,
DI_PT_2D_COPY_RECT_LIST_V0               = 0x00000016,
DI_PT_2D_COPY_RECT_LIST_V1               = 0x00000017,
DI_PT_2D_COPY_RECT_LIST_V2               = 0x00000018,
DI_PT_2D_COPY_RECT_LIST_V3               = 0x00000019,
DI_PT_2D_FILL_RECT_LIST                  = 0x0000001a,
DI_PT_2D_LINE_STRIP                      = 0x0000001b,
DI_PT_2D_TRI_STRIP                       = 0x0000001c,
} VGT_DI_PRIM_TYPE;

typedef enum VGT_DI_SOURCE_SELECT {
DI_SRC_SEL_DMA                           = 0x00000000,
DI_SRC_SEL_IMMEDIATE                     = 0x00000001,
DI_SRC_SEL_AUTO_INDEX                    = 0x00000002,
DI_SRC_SEL_RESERVED                      = 0x00000003,
} VGT_DI_SOURCE_SELECT;

typedef enum VGT_DMA_BUF_TYPE {
VGT_DMA_BUF_MEM                          = 0x00000000,
VGT_DMA_BUF_RING                         = 0x00000001,
VGT_DMA_BUF_SETUP                        = 0x00000002,
VGT_DMA_PTR_UPDATE__VI                   = 0x00000003,
} VGT_DMA_BUF_TYPE;

typedef enum VGT_DMA_SWAP_MODE {
VGT_DMA_SWAP_NONE                        = 0x00000000,
VGT_DMA_SWAP_16_BIT                      = 0x00000001,
VGT_DMA_SWAP_32_BIT                      = 0x00000002,
VGT_DMA_SWAP_WORD                        = 0x00000003,
} VGT_DMA_SWAP_MODE;

typedef enum VGT_EVENT_TYPE {
Reserved_0x00                            = 0x00000000,
SAMPLE_STREAMOUTSTATS1                   = 0x00000001,
SAMPLE_STREAMOUTSTATS2                   = 0x00000002,
SAMPLE_STREAMOUTSTATS3                   = 0x00000003,
CACHE_FLUSH_TS                           = 0x00000004,
CONTEXT_DONE                             = 0x00000005,
CACHE_FLUSH                              = 0x00000006,
CS_PARTIAL_FLUSH                         = 0x00000007,
VGT_STREAMOUT_SYNC                       = 0x00000008,
Reserved_0x09                            = 0x00000009,
VGT_STREAMOUT_RESET                      = 0x0000000a,
END_OF_PIPE_INCR_DE                      = 0x0000000b,
END_OF_PIPE_IB_END                       = 0x0000000c,
RST_PIX_CNT                              = 0x0000000d,
Reserved_0x0E                            = 0x0000000e,
VS_PARTIAL_FLUSH                         = 0x0000000f,
PS_PARTIAL_FLUSH                         = 0x00000010,
FLUSH_HS_OUTPUT                          = 0x00000011,
FLUSH_LS_OUTPUT                          = 0x00000012,
Reserved_0x13                            = 0x00000013,
CACHE_FLUSH_AND_INV_TS_EVENT             = 0x00000014,
ZPASS_DONE                               = 0x00000015,
CACHE_FLUSH_AND_INV_EVENT                = 0x00000016,
PERFCOUNTER_START                        = 0x00000017,
PERFCOUNTER_STOP                         = 0x00000018,
PIPELINESTAT_START                       = 0x00000019,
PIPELINESTAT_STOP                        = 0x0000001a,
PERFCOUNTER_SAMPLE                       = 0x0000001b,
FLUSH_ES_OUTPUT                          = 0x0000001c,
FLUSH_GS_OUTPUT                          = 0x0000001d,
SAMPLE_PIPELINESTAT                      = 0x0000001e,
SO_VGTSTREAMOUT_FLUSH                    = 0x0000001f,
SAMPLE_STREAMOUTSTATS                    = 0x00000020,
RESET_VTX_CNT                            = 0x00000021,
BLOCK_CONTEXT_DONE                       = 0x00000022,
CS_CONTEXT_DONE                          = 0x00000023,
VGT_FLUSH                                = 0x00000024,
Reserved_0x25__SI__CI                    = 0x00000025,
TGID_ROLLOVER__VI                        = 0x00000025,
SQ_NON_EVENT                             = 0x00000026,
SC_SEND_DB_VPZ                           = 0x00000027,
BOTTOM_OF_PIPE_TS                        = 0x00000028,
FLUSH_SX_TS                              = 0x00000029,
DB_CACHE_FLUSH_AND_INV                   = 0x0000002a,
FLUSH_AND_INV_DB_DATA_TS                 = 0x0000002b,
FLUSH_AND_INV_DB_META                    = 0x0000002c,
FLUSH_AND_INV_CB_DATA_TS                 = 0x0000002d,
FLUSH_AND_INV_CB_META                    = 0x0000002e,
CS_DONE                                  = 0x0000002f,
PS_DONE                                  = 0x00000030,
FLUSH_AND_INV_CB_PIXEL_DATA              = 0x00000031,
SX_CB_RAT_ACK_REQUEST                    = 0x00000032,
THREAD_TRACE_START                       = 0x00000033,
THREAD_TRACE_STOP                        = 0x00000034,
THREAD_TRACE_MARKER                      = 0x00000035,
THREAD_TRACE_FLUSH                       = 0x00000036,
THREAD_TRACE_FINISH                      = 0x00000037,
PIXEL_PIPE_STAT_CONTROL__CI__VI          = 0x00000038,
PIXEL_PIPE_STAT_DUMP__CI__VI             = 0x00000039,
PIXEL_PIPE_STAT_RESET__CI__VI            = 0x0000003a,
CONTEXT_SUSPEND__CI__VI                  = 0x0000003b,
OFFCHIP_HS_DEALLOC__VI                   = 0x0000003c,
} VGT_EVENT_TYPE;

typedef enum VGT_GROUP_CONV_SEL {
VGT_GRP_INDEX_16                         = 0x00000000,
VGT_GRP_INDEX_32                         = 0x00000001,
VGT_GRP_UINT_16                          = 0x00000002,
VGT_GRP_UINT_32                          = 0x00000003,
VGT_GRP_SINT_16                          = 0x00000004,
VGT_GRP_SINT_32                          = 0x00000005,
VGT_GRP_FLOAT_32                         = 0x00000006,
VGT_GRP_AUTO_PRIM                        = 0x00000007,
VGT_GRP_FIX_1_23_TO_FLOAT                = 0x00000008,
} VGT_GROUP_CONV_SEL;

typedef enum VGT_GRP_PRIM_ORDER {
VGT_GRP_LIST                             = 0x00000000,
VGT_GRP_STRIP                            = 0x00000001,
VGT_GRP_FAN                              = 0x00000002,
VGT_GRP_LOOP                             = 0x00000003,
VGT_GRP_POLYGON                          = 0x00000004,
} VGT_GRP_PRIM_ORDER;

typedef enum VGT_GRP_PRIM_TYPE {
VGT_GRP_3D_POINT                         = 0x00000000,
VGT_GRP_3D_LINE                          = 0x00000001,
VGT_GRP_3D_TRI                           = 0x00000002,
VGT_GRP_3D_RECT                          = 0x00000003,
VGT_GRP_3D_QUAD                          = 0x00000004,
VGT_GRP_2D_COPY_RECT_V0                  = 0x00000005,
VGT_GRP_2D_COPY_RECT_V1                  = 0x00000006,
VGT_GRP_2D_COPY_RECT_V2                  = 0x00000007,
VGT_GRP_2D_COPY_RECT_V3                  = 0x00000008,
VGT_GRP_2D_FILL_RECT                     = 0x00000009,
VGT_GRP_2D_LINE                          = 0x0000000a,
VGT_GRP_2D_TRI                           = 0x0000000b,
VGT_GRP_PRIM_INDEX_LINE                  = 0x0000000c,
VGT_GRP_PRIM_INDEX_TRI                   = 0x0000000d,
VGT_GRP_PRIM_INDEX_QUAD                  = 0x0000000e,
VGT_GRP_3D_LINE_ADJ                      = 0x0000000f,
VGT_GRP_3D_TRI_ADJ                       = 0x00000010,
VGT_GRP_3D_PATCH                         = 0x00000011,
} VGT_GRP_PRIM_TYPE;

typedef enum VGT_GS_CUT_MODE {
GS_CUT_1024                              = 0x00000000,
GS_CUT_512                               = 0x00000001,
GS_CUT_256                               = 0x00000002,
GS_CUT_128                               = 0x00000003,
} VGT_GS_CUT_MODE;

typedef enum VGT_GS_MODE_TYPE {
GS_OFF                                   = 0x00000000,
GS_SCENARIO_A                            = 0x00000001,
GS_SCENARIO_B                            = 0x00000002,
GS_SCENARIO_G                            = 0x00000003,
GS_SCENARIO_C                            = 0x00000004,
SPRITE_EN                                = 0x00000005,
} VGT_GS_MODE_TYPE;

typedef enum VGT_GS_OUTPRIM_TYPE {
POINTLIST                                = 0x00000000,
LINESTRIP                                = 0x00000001,
TRISTRIP                                 = 0x00000002,
} VGT_GS_OUTPRIM_TYPE;

typedef enum VGT_INDEX_TYPE_MODE {
VGT_INDEX_16                             = 0x00000000,
VGT_INDEX_32                             = 0x00000001,
VGT_INDEX_8__VI                          = 0x00000002,
} VGT_INDEX_TYPE_MODE;

typedef enum VGT_OUTPATH_SELECT {
VGT_OUTPATH_VTX_REUSE                    = 0x00000000,
VGT_OUTPATH_TESS_EN                      = 0x00000001,
VGT_OUTPATH_PASSTHRU                     = 0x00000002,
VGT_OUTPATH_GS_BLOCK                     = 0x00000003,
VGT_OUTPATH_HS_BLOCK                     = 0x00000004,
} VGT_OUTPATH_SELECT;

typedef enum VGT_OUT_PRIM_TYPE {
VGT_OUT_POINT                            = 0x00000000,
VGT_OUT_LINE                             = 0x00000001,
VGT_OUT_TRI                              = 0x00000002,
VGT_OUT_RECT_V0                          = 0x00000003,
VGT_OUT_RECT_V1                          = 0x00000004,
VGT_OUT_RECT_V2                          = 0x00000005,
VGT_OUT_RECT_V3                          = 0x00000006,
VGT_OUT_RESERVED                         = 0x00000007,
VGT_TE_QUAD                              = 0x00000008,
VGT_TE_PRIM_INDEX_LINE                   = 0x00000009,
VGT_TE_PRIM_INDEX_TRI                    = 0x0000000a,
VGT_TE_PRIM_INDEX_QUAD                   = 0x0000000b,
VGT_OUT_LINE_ADJ                         = 0x0000000c,
VGT_OUT_TRI_ADJ                          = 0x0000000d,
VGT_OUT_PATCH                            = 0x0000000e,
} VGT_OUT_PRIM_TYPE;

typedef enum VGT_PERFCOUNT_SELECT {
vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x00000000,
vgt_perf_VGT_SPI_ESVERT_VALID            = 0x00000001,
vgt_perf_VGT_SPI_ESVERT_EOV              = 0x00000002,
vgt_perf_VGT_SPI_ESVERT_STALLED          = 0x00000003,
vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY     = 0x00000004,
vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE     = 0x00000005,
vgt_perf_VGT_SPI_ESVERT_STATIC           = 0x00000006,
vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT       = 0x00000007,
vgt_perf_VGT_SPI_ESTHREAD_SEND           = 0x00000008,
vgt_perf_VGT_SPI_GSPRIM_VALID            = 0x00000009,
vgt_perf_VGT_SPI_GSPRIM_EOV              = 0x0000000a,
vgt_perf_VGT_SPI_GSPRIM_CONT             = 0x0000000b,
vgt_perf_VGT_SPI_GSPRIM_STALLED          = 0x0000000c,
vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY     = 0x0000000d,
vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE     = 0x0000000e,
vgt_perf_VGT_SPI_GSPRIM_STATIC           = 0x0000000f,
vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000010,
vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT       = 0x00000011,
vgt_perf_VGT_SPI_GSTHREAD_SEND           = 0x00000012,
vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000013,
vgt_perf_VGT_SPI_VSVERT_SEND             = 0x00000014,
vgt_perf_VGT_SPI_VSVERT_EOV              = 0x00000015,
vgt_perf_VGT_SPI_VSVERT_STALLED          = 0x00000016,
vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY     = 0x00000017,
vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE     = 0x00000018,
vgt_perf_VGT_SPI_VSVERT_STATIC           = 0x00000019,
vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT       = 0x0000001a,
vgt_perf_VGT_SPI_VSTHREAD_SEND           = 0x0000001b,
vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE      = 0x0000001c,
vgt_perf_VGT_PA_CLIPV_SEND               = 0x0000001d,
vgt_perf_VGT_PA_CLIPV_FIRSTVERT          = 0x0000001e,
vgt_perf_VGT_PA_CLIPV_STALLED            = 0x0000001f,
vgt_perf_VGT_PA_CLIPV_STARVED_BUSY       = 0x00000020,
vgt_perf_VGT_PA_CLIPV_STARVED_IDLE       = 0x00000021,
vgt_perf_VGT_PA_CLIPV_STATIC             = 0x00000022,
vgt_perf_VGT_PA_CLIPP_SEND               = 0x00000023,
vgt_perf_VGT_PA_CLIPP_EOP                = 0x00000024,
vgt_perf_VGT_PA_CLIPP_IS_EVENT           = 0x00000025,
vgt_perf_VGT_PA_CLIPP_NULL_PRIM          = 0x00000026,
vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT       = 0x00000027,
vgt_perf_VGT_PA_CLIPP_STALLED            = 0x00000028,
vgt_perf_VGT_PA_CLIPP_STARVED_BUSY       = 0x00000029,
vgt_perf_VGT_PA_CLIPP_STARVED_IDLE       = 0x0000002a,
vgt_perf_VGT_PA_CLIPP_STATIC             = 0x0000002b,
vgt_perf_VGT_PA_CLIPS_SEND               = 0x0000002c,
vgt_perf_VGT_PA_CLIPS_STALLED            = 0x0000002d,
vgt_perf_VGT_PA_CLIPS_STARVED_BUSY       = 0x0000002e,
vgt_perf_VGT_PA_CLIPS_STARVED_IDLE       = 0x0000002f,
vgt_perf_VGT_PA_CLIPS_STATIC             = 0x00000030,
vgt_perf_vsvert_ds_send                  = 0x00000031,
vgt_perf_vsvert_api_send                 = 0x00000032,
vgt_perf_hs_tif_stall                    = 0x00000033,
vgt_perf_hs_input_stall                  = 0x00000034,
vgt_perf_hs_interface_stall              = 0x00000035,
vgt_perf_hs_tfm_stall                    = 0x00000036,
vgt_perf_te11_starved                    = 0x00000037,
vgt_perf_gs_event_stall                  = 0x00000038,
vgt_perf_RESERVED0__SI                   = 0x00000039,
vgt_perf_vgt_pa_clipp_send_not_event__CI__VI = 0x00000039,
vgt_perf_RESERVED1__SI                   = 0x0000003a,
vgt_perf_vgt_pa_clipp_valid_prim__CI__VI = 0x0000003a,
vgt_perf_RESERVED2__SI                   = 0x0000003b,
vgt_perf_reused_es_indices__CI__VI       = 0x0000003b,
vgt_perf_vs_cache_hits__CI__VI           = 0x0000003c,
vgt_perf_gs_cache_hits__CI__VI           = 0x0000003d,
vgt_perf_ds_cache_hits__CI__VI           = 0x0000003e,
vgt_perf_total_cache_hits__CI__VI        = 0x0000003f,
vgt_perf_vgt_busy                        = 0x00000040,
vgt_perf_vgt_gs_busy                     = 0x00000041,
vgt_perf_esvert_stalled_es_tbl           = 0x00000042,
vgt_perf_esvert_stalled_gs_tbl           = 0x00000043,
vgt_perf_esvert_stalled_gs_event         = 0x00000044,
vgt_perf_esvert_stalled_gsprim           = 0x00000045,
vgt_perf_gsprim_stalled_es_tbl           = 0x00000046,
vgt_perf_gsprim_stalled_gs_tbl           = 0x00000047,
vgt_perf_gsprim_stalled_gs_event         = 0x00000048,
vgt_perf_gsprim_stalled_esvert           = 0x00000049,
vgt_perf_esthread_stalled_es_rb_full     = 0x0000004a,
vgt_perf_esthread_stalled_spi_bp         = 0x0000004b,
vgt_perf_counters_avail_stalled          = 0x0000004c,
vgt_perf_gs_rb_space_avail_stalled       = 0x0000004d,
vgt_perf_gs_issue_rtr_stalled            = 0x0000004e,
vgt_perf_gsthread_stalled                = 0x0000004f,
vgt_perf_strmout_stalled__CI__VI         = 0x00000050,
vgt_perf_wait_for_es_done_stalled        = 0x00000051,
vgt_perf_cm_stalled_by_gog               = 0x00000052,
vgt_perf_cm_reading_stalled              = 0x00000053,
vgt_perf_cm_stalled_by_gsfetch_done      = 0x00000054,
vgt_perf_gog_vs_tbl_stalled              = 0x00000055,
vgt_perf_gog_out_indx_stalled            = 0x00000056,
vgt_perf_gog_out_prim_stalled            = 0x00000057,
vgt_perf_waveid_stalled__CI__VI          = 0x00000058,
vgt_perf_gog_busy                        = 0x00000059,
vgt_perf_reused_vs_indices               = 0x0000005a,
vgt_perf_sclk_reg_vld_event              = 0x0000005b,
vgt_perf_RESERVED0__CI                   = 0x0000005c,
vgt_perf_vs_conflicting_indices__VI      = 0x0000005c,
vgt_perf_sclk_core_vld_event             = 0x0000005d,
vgt_perf_RESERVED1__CI                   = 0x0000005e,
vgt_perf_hswave_stalled__VI              = 0x0000005e,
vgt_perf_sclk_gs_vld_event               = 0x0000005f,
vgt_perf_VGT_SPI_LSVERT_VALID            = 0x00000060,
vgt_perf_VGT_SPI_LSVERT_EOV              = 0x00000061,
vgt_perf_VGT_SPI_LSVERT_STALLED          = 0x00000062,
vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY     = 0x00000063,
vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE     = 0x00000064,
vgt_perf_VGT_SPI_LSVERT_STATIC           = 0x00000065,
vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x00000066,
vgt_perf_VGT_SPI_LSWAVE_IS_EVENT         = 0x00000067,
vgt_perf_VGT_SPI_LSWAVE_SEND             = 0x00000068,
vgt_perf_VGT_SPI_HSVERT_VALID            = 0x00000069,
vgt_perf_VGT_SPI_HSVERT_EOV              = 0x0000006a,
vgt_perf_VGT_SPI_HSVERT_STALLED          = 0x0000006b,
vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY     = 0x0000006c,
vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE     = 0x0000006d,
vgt_perf_VGT_SPI_HSVERT_STATIC           = 0x0000006e,
vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x0000006f,
vgt_perf_VGT_SPI_HSWAVE_IS_EVENT         = 0x00000070,
vgt_perf_VGT_SPI_HSWAVE_SEND             = 0x00000071,
vgt_perf_ds_prims__CI__VI                = 0x00000072,
vgt_perf_null_tess_patches__SI__CI       = 0x00000073,
vgt_perf_ls_thread_groups__VI            = 0x00000073,
vgt_perf_ls_thread_groups__SI__CI        = 0x00000074,
vgt_perf_hs_thread_groups__VI            = 0x00000074,
vgt_perf_hs_thread_groups__SI__CI        = 0x00000075,
vgt_perf_es_thread_groups__VI            = 0x00000075,
vgt_perf_es_thread_groups__SI__CI        = 0x00000076,
vgt_perf_vs_thread_groups__VI            = 0x00000076,
vgt_perf_vs_thread_groups__SI__CI        = 0x00000077,
vgt_perf_ls_done_latency__VI             = 0x00000077,
vgt_perf_ls_done_latency__SI__CI         = 0x00000078,
vgt_perf_hs_done_latency__VI             = 0x00000078,
vgt_perf_hs_done_latency__SI__CI         = 0x00000079,
vgt_perf_es_done_latency__VI             = 0x00000079,
vgt_perf_es_done_latency__SI__CI         = 0x0000007a,
vgt_perf_gs_done_latency__VI             = 0x0000007a,
vgt_perf_gs_done_latency__SI__CI         = 0x0000007b,
vgt_perf_vgt_hs_busy__VI                 = 0x0000007b,
vgt_perf_vgt_hs_busy__SI__CI             = 0x0000007c,
vgt_perf_vgt_te11_busy__VI               = 0x0000007c,
vgt_perf_vgt_te11_busy__SI__CI           = 0x0000007d,
vgt_perf_ls_flush__VI                    = 0x0000007d,
vgt_perf_ls_flush__SI__CI                = 0x0000007e,
vgt_perf_hs_flush__VI                    = 0x0000007e,
vgt_perf_hs_flush__SI__CI                = 0x0000007f,
vgt_perf_es_flush__VI                    = 0x0000007f,
vgt_perf_es_flush__SI__CI                = 0x00000080,
vgt_perf_vgt_pa_clipp_eopg__VI           = 0x00000080,
vgt_perf_gs_flush__SI__CI                = 0x00000081,
vgt_perf_ls_done__VI                     = 0x00000081,
vgt_perf_ls_done__SI__CI                 = 0x00000082,
vgt_perf_hs_done__VI                     = 0x00000082,
vgt_perf_hs_done__SI__CI                 = 0x00000083,
vgt_perf_es_done__VI                     = 0x00000083,
vgt_perf_es_done__SI__CI                 = 0x00000084,
vgt_perf_gs_done__VI                     = 0x00000084,
vgt_perf_gs_done__SI__CI                 = 0x00000085,
vgt_perf_vsfetch_done__VI                = 0x00000085,
vgt_perf_vsfetch_done__SI__CI            = 0x00000086,
vgt_perf_gs_done_received__VI            = 0x00000086,
vgt_perf_RESERVED2__CI                   = 0x00000087,
vgt_perf_es_ring_high_water_mark__VI     = 0x00000087,
vgt_perf_es_ring_high_water_mark__SI__CI = 0x00000088,
vgt_perf_gs_ring_high_water_mark__VI     = 0x00000088,
vgt_perf_gs_ring_high_water_mark__SI__CI = 0x00000089,
vgt_perf_vs_table_high_water_mark__VI    = 0x00000089,
vgt_perf_vs_table_high_water_mark__SI__CI = 0x0000008a,
vgt_perf_hs_tgs_active_high_water_mark__VI = 0x0000008a,
vgt_perf_hs_tgs_active_high_water_mark__SI__CI = 0x0000008b,
vgt_perf_pa_clipp_dealloc__VI            = 0x0000008b,
vgt_perf_cut_mem_flush_stalled__VI       = 0x0000008c,
vgt_perf_vsvert_work_received__VI        = 0x0000008d,
vgt_perf_vgt_pa_clipp_starved_after_work__VI = 0x0000008e,
vgt_perf_te11_con_starved_after_work__VI = 0x0000008f,
vgt_perf_hs_waiting_on_ls_done_stall__VI = 0x00000090,
vgt_spi_vsvert_valid__VI                 = 0x00000091,
} VGT_PERFCOUNT_SELECT;

typedef enum VGT_RDREQ_POLICY {
VGT_POLICY_LRU                           = 0x00000000,
VGT_POLICY_STREAM                        = 0x00000001,
VGT_POLICY_BYPASS__SI__CI                = 0x00000002,
VGT_POLICY_RESERVED__SI__CI              = 0x00000003,
} VGT_RDREQ_POLICY;

typedef enum VGT_STAGES_ES_EN {
ES_STAGE_OFF                             = 0x00000000,
ES_STAGE_DS                              = 0x00000001,
ES_STAGE_REAL                            = 0x00000002,
RESERVED_ES                              = 0x00000003,
} VGT_STAGES_ES_EN;

typedef enum VGT_STAGES_GS_EN {
GS_STAGE_OFF                             = 0x00000000,
GS_STAGE_ON                              = 0x00000001,
} VGT_STAGES_GS_EN;

typedef enum VGT_STAGES_HS_EN {
HS_STAGE_OFF                             = 0x00000000,
HS_STAGE_ON                              = 0x00000001,
} VGT_STAGES_HS_EN;

typedef enum VGT_STAGES_LS_EN {
LS_STAGE_OFF                             = 0x00000000,
LS_STAGE_ON                              = 0x00000001,
CS_STAGE_ON                              = 0x00000002,
RESERVED_LS                              = 0x00000003,
} VGT_STAGES_LS_EN;

typedef enum VGT_STAGES_VS_EN {
VS_STAGE_REAL                            = 0x00000000,
VS_STAGE_DS                              = 0x00000001,
VS_STAGE_COPY_SHADER                     = 0x00000002,
RESERVED_VS                              = 0x00000003,
} VGT_STAGES_VS_EN;

typedef enum VGT_TESS_PARTITION {
PART_INTEGER                             = 0x00000000,
PART_POW2                                = 0x00000001,
PART_FRAC_ODD                            = 0x00000002,
PART_FRAC_EVEN                           = 0x00000003,
} VGT_TESS_PARTITION;

typedef enum VGT_TESS_TOPOLOGY {
OUTPUT_POINT                             = 0x00000000,
OUTPUT_LINE                              = 0x00000001,
OUTPUT_TRIANGLE_CW                       = 0x00000002,
OUTPUT_TRIANGLE_CCW                      = 0x00000003,
} VGT_TESS_TOPOLOGY;

typedef enum VGT_TESS_TYPE {
TESS_ISOLINE                             = 0x00000000,
TESS_TRIANGLE                            = 0x00000001,
TESS_QUAD                                = 0x00000002,
} VGT_TESS_TYPE;

typedef enum VTX_CLAMP {
VTX_Clamp_ClampToZero                    = 0x00000000,
VTX_Clamp_ClampToNAN                     = 0x00000001,
} VTX_CLAMP;

typedef enum VTX_FETCH_TYPE {
VTX_FetchType_VertexData                 = 0x00000000,
VTX_FetchType_InstanceData               = 0x00000001,
VTX_FetchType_NoIndexOffset              = 0x00000002,
VTX_FetchType_RESERVED_3                 = 0x00000003,
} VTX_FETCH_TYPE;

typedef enum VTX_FORMAT_COMP_ALL {
VTX_FormatCompAll_Unsigned               = 0x00000000,
VTX_FormatCompAll_Signed                 = 0x00000001,
} VTX_FORMAT_COMP_ALL;

typedef enum VTX_MEM_REQUEST_SIZE {
VTX_MemRequestSize_32B                   = 0x00000000,
VTX_MemRequestSize_64B                   = 0x00000001,
} VTX_MEM_REQUEST_SIZE;

typedef enum WD_IA_DRAW_TYPE {
WD_IA_DRAW_TYPE_DI_MM0                   = 0x00000000,
WD_IA_DRAW_TYPE_DI_MM1                   = 0x00000001,
WD_IA_DRAW_TYPE_EVENT_INIT               = 0x00000002,
WD_IA_DRAW_TYPE_EVENT_ADDR               = 0x00000003,
WD_IA_DRAW_TYPE_MIN_INDX                 = 0x00000004,
WD_IA_DRAW_TYPE_MAX_INDX                 = 0x00000005,
WD_IA_DRAW_TYPE_INDX_OFF                 = 0x00000006,
WD_IA_DRAW_TYPE_IMM_DATA                 = 0x00000007,
} WD_IA_DRAW_TYPE;

typedef enum WD_PERFCOUNT_SELECT {
wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE   = 0x00000000,
wd_perf_RBIU_DR_FIFO_STARVED             = 0x00000001,
wd_perf_RBIU_DR_FIFO_STALLED             = 0x00000002,
wd_perf_RBIU_DI_FIFO_STARVED             = 0x00000003,
wd_perf_RBIU_DI_FIFO_STALLED             = 0x00000004,
wd_perf_wd_busy                          = 0x00000005,
wd_perf_wd_sclk_reg_vld_event            = 0x00000006,
wd_perf_wd_sclk_input_vld_event          = 0x00000007,
wd_perf_wd_sclk_core_vld_event           = 0x00000008,
wd_perf_wd_stalled                       = 0x00000009,
wd_perf_inside_tf_bin_0__VI              = 0x0000000a,
wd_perf_inside_tf_bin_1__VI              = 0x0000000b,
wd_perf_inside_tf_bin_2__VI              = 0x0000000c,
wd_perf_inside_tf_bin_3__VI              = 0x0000000d,
wd_perf_inside_tf_bin_4__VI              = 0x0000000e,
wd_perf_inside_tf_bin_5__VI              = 0x0000000f,
wd_perf_inside_tf_bin_6__VI              = 0x00000010,
wd_perf_inside_tf_bin_7__VI              = 0x00000011,
wd_perf_inside_tf_bin_8__VI              = 0x00000012,
wd_perf_tfreq_lat_bin_0__VI              = 0x00000013,
wd_perf_tfreq_lat_bin_1__VI              = 0x00000014,
wd_perf_tfreq_lat_bin_2__VI              = 0x00000015,
wd_perf_tfreq_lat_bin_3__VI              = 0x00000016,
wd_perf_tfreq_lat_bin_4__VI              = 0x00000017,
wd_perf_tfreq_lat_bin_5__VI              = 0x00000018,
wd_perf_tfreq_lat_bin_6__VI              = 0x00000019,
wd_perf_tfreq_lat_bin_7__VI              = 0x0000001a,
wd_starved_on_hs_done__VI                = 0x0000001b,
wd_perf_se0_hs_done_latency__VI          = 0x0000001c,
wd_perf_se1_hs_done_latency__VI          = 0x0000001d,
wd_perf_se2_hs_done_latency__VI          = 0x0000001e,
wd_perf_se3_hs_done_latency__VI          = 0x0000001f,
wd_perf_hs_done_se0__VI                  = 0x00000020,
wd_perf_hs_done_se1__VI                  = 0x00000021,
wd_perf_hs_done_se2__VI                  = 0x00000022,
wd_perf_hs_done_se3__VI                  = 0x00000023,
wd_perf_null_patches__VI                 = 0x00000024,
} WD_PERFCOUNT_SELECT;

typedef enum ZFormat {
Z_INVALID                                = 0x00000000,
Z_16                                     = 0x00000001,
Z_24                                     = 0x00000002,
Z_32_FLOAT                               = 0x00000003,
} ZFormat;

typedef enum ZLimitSumm {
FORCE_SUMM_OFF                           = 0x00000000,
FORCE_SUMM_MINZ                          = 0x00000001,
FORCE_SUMM_MAXZ                          = 0x00000002,
FORCE_SUMM_BOTH                          = 0x00000003,
} ZLimitSumm;

typedef enum ZModeForce {
NO_FORCE                                 = 0x00000000,
FORCE_EARLY_Z                            = 0x00000001,
FORCE_LATE_Z                             = 0x00000002,
FORCE_RE_Z                               = 0x00000003,
} ZModeForce;

typedef enum ZOrder {
LATE_Z                                   = 0x00000000,
EARLY_Z_THEN_LATE_Z                      = 0x00000001,
RE_Z                                     = 0x00000002,
EARLY_Z_THEN_RE_Z                        = 0x00000003,
} ZOrder;

typedef enum ZSamplePosition {
Z_SAMPLE_CENTER                          = 0x00000000,
Z_SAMPLE_CENTROID                        = 0x00000001,
} ZSamplePosition;

typedef enum ZpassControl {
ZPASS_DISABLE                            = 0x00000000,
ZPASS_SAMPLES                            = 0x00000001,
ZPASS_PIXELS                             = 0x00000002,
} ZpassControl;

//Merged Enumerations
typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
DENORM_CLAMP_CONTROL_UNITY               = 0x00000000,
DENORM_CLAMP_CONTROL_8                   = 0x00000001,
DENORM_CLAMP_CONTROL_10                  = 0x00000002,
DENORM_CLAMP_CONTROL_12                  = 0x00000003,
} COL_MAN_DENORM_CLAMP_CONTROL;

typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
COL_MAN_MULTIPLE_UPDATE                  = 0x00000000,
COL_MAN_MULTIPLE_UPDAT_EDISABLE          = 0x00000001,
} COL_MAN_DISABLE_MULTIPLE_UPDATE;

typedef enum COL_MAN_GAMMA_CORR_CONTROL {
GAMMA_CORR_CONTROL_BYPASS                = 0x00000000,
GAMMA_CORR_CONTROL_A                     = 0x00000001,
GAMMA_CORR_CONTROL_B                     = 0x00000002,
} COL_MAN_GAMMA_CORR_CONTROL;

typedef enum COL_MAN_INPUTCSC_CONVERT {
INPUTCSC_ROUND                           = 0x00000000,
INPUTCSC_TRUNCATE                        = 0x00000001,
} COL_MAN_INPUTCSC_CONVERT;

typedef enum COL_MAN_INPUTCSC_MODE {
INPUTCSC_MODE_BYPASS                     = 0x00000000,
INPUTCSC_MODE_A                          = 0x00000001,
INPUTCSC_MODE_B                          = 0x00000002,
INPUTCSC_MODE_UNITY                      = 0x00000003,
} COL_MAN_INPUTCSC_MODE;

typedef enum COL_MAN_INPUTCSC_TYPE {
INPUTCSC_TYPE_12_0                       = 0x00000000,
INPUTCSC_TYPE_10_2                       = 0x00000001,
INPUTCSC_TYPE_8_4                        = 0x00000002,
} COL_MAN_INPUTCSC_TYPE;

typedef enum COL_MAN_OUTPUT_CSC_MODE {
COL_MAN_OUTPUT_CSC_BYPASS                = 0x00000000,
COL_MAN_OUTPUT_CSC_RGB                   = 0x00000001,
COL_MAN_OUTPUT_CSC_YCrCb601              = 0x00000002,
COL_MAN_OUTPUT_CSC_YCrCb709              = 0x00000003,
COL_MAN_OUTPUT_CSC_A                     = 0x00000004,
COL_MAN_OUTPUT_CSC_B                     = 0x00000005,
} COL_MAN_OUTPUT_CSC_MODE;

typedef enum COL_MAN_PRESCALE_MODE {
PRESCALE_MODE_BYPASS                     = 0x00000000,
PRESCALE_MODE_PROGRAM                    = 0x00000001,
PRESCALE_MODE_UNITY                      = 0x00000002,
} COL_MAN_PRESCALE_MODE;

typedef enum COL_MAN_UPDATE_LOCK {
COL_MAN_UPDATE_UNLOCKED                  = 0x00000000,
COL_MAN_UPDATE_LOCKED                    = 0x00000001,
} COL_MAN_UPDATE_LOCK;

typedef enum CmaskAddr {
CMASK_ADDR_TILED                         = 0x00000000,
CMASK_ADDR_LINEAR                        = 0x00000001,
CMASK_ADDR_COMPATIBLE                    = 0x00000002,
} CmaskAddr;

typedef enum ColorTransform {
DCC_CT_AUTO                              = 0x00000000,
DCC_CT_NONE                              = 0x00000001,
ABGR_TO_A_BG_G_RB                        = 0x00000002,
BGRA_TO_BG_G_RB_A                        = 0x00000003,
} ColorTransform;

typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
DCIOCHIP_AUXSLAVE_PAD_MODE_I2C           = 0x00000000,
DCIOCHIP_AUXSLAVE_PAD_MODE_AUX           = 0x00000001,
} DCIOCHIP_AUXSLAVE_PAD_MODE;

typedef enum DCIOCHIP_DVO_VREFPON {
DCIOCHIP_DVO_VREFPON_DISABLE             = 0x00000000,
DCIOCHIP_DVO_VREFPON_ENABLE              = 0x00000001,
} DCIOCHIP_DVO_VREFPON;

typedef enum DCIOCHIP_DVO_VREFSEL {
DCIOCHIP_DVO_VREFSEL_ONCHIP              = 0x00000000,
DCIOCHIP_DVO_VREFSEL_EXTERNAL            = 0x00000001,
} DCIOCHIP_DVO_VREFSEL;

typedef enum DCIOCHIP_ENABLE_2BIT {
DCIOCHIP_2BIT_DISABLE                    = 0x00000000,
DCIOCHIP_2BIT_ENABLE                     = 0x00000003,
} DCIOCHIP_ENABLE_2BIT;

typedef enum DCIOCHIP_ENABLE_4BIT {
DCIOCHIP_4BIT_DISABLE                    = 0x00000000,
DCIOCHIP_4BIT_ENABLE                     = 0x0000000f,
} DCIOCHIP_ENABLE_4BIT;

typedef enum DCIOCHIP_ENABLE_5BIT {
DCIOCHIP_5BIT_DISABLE                    = 0x00000000,
DCIOCHIP_5BIT_ENABLE                     = 0x0000001f,
} DCIOCHIP_ENABLE_5BIT;

typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
DCIOCHIP_GPIO_I2C_DRIVE_LOW              = 0x00000000,
DCIOCHIP_GPIO_I2C_DRIVE_HIGH             = 0x00000001,
} DCIOCHIP_GPIO_I2C_DRIVE;

typedef enum DCIOCHIP_GPIO_I2C_EN {
DCIOCHIP_GPIO_I2C_DISABLE                = 0x00000000,
DCIOCHIP_GPIO_I2C_ENABLE                 = 0x00000001,
} DCIOCHIP_GPIO_I2C_EN;

typedef enum DCIOCHIP_GPIO_I2C_MASK {
DCIOCHIP_GPIO_I2C_MASK_DISABLE           = 0x00000000,
DCIOCHIP_GPIO_I2C_MASK_ENABLE            = 0x00000001,
} DCIOCHIP_GPIO_I2C_MASK;

typedef enum DCIOCHIP_GPIO_MASK_EN {
DCIOCHIP_GPIO_MASK_EN_HARDWARE           = 0x00000000,
DCIOCHIP_GPIO_MASK_EN_SOFTWARE           = 0x00000001,
} DCIOCHIP_GPIO_MASK_EN;

typedef enum DCIOCHIP_HPD_SEL {
DCIOCHIP_HPD_SEL_ASYNC                   = 0x00000000,
DCIOCHIP_HPD_SEL_CLOCKED                 = 0x00000001,
} DCIOCHIP_HPD_SEL;

typedef enum DCIOCHIP_INVERT {
DCIOCHIP_POL_NON_INVERT                  = 0x00000000,
DCIOCHIP_POL_INVERT                      = 0x00000001,
} DCIOCHIP_INVERT;

typedef enum DCIOCHIP_MASK {
DCIOCHIP_MASK_DISABLE                    = 0x00000000,
DCIOCHIP_MASK_ENABLE                     = 0x00000001,
} DCIOCHIP_MASK;

typedef enum DCIOCHIP_MASK_2BIT {
DCIOCHIP_MASK_2BIT_DISABLE               = 0x00000000,
DCIOCHIP_MASK_2BIT_ENABLE                = 0x00000003,
} DCIOCHIP_MASK_2BIT;

typedef enum DCIOCHIP_MASK_4BIT {
DCIOCHIP_MASK_4BIT_DISABLE               = 0x00000000,
DCIOCHIP_MASK_4BIT_ENABLE                = 0x0000000f,
} DCIOCHIP_MASK_4BIT;

typedef enum DCIOCHIP_MASK_5BIT {
DCIOCHIP_MASIK_5BIT_DISABLE              = 0x00000000,
DCIOCHIP_MASIK_5BIT_ENABLE               = 0x0000001f,
} DCIOCHIP_MASK_5BIT;

typedef enum DCIOCHIP_PAD_MODE {
DCIOCHIP_PAD_MODE_DDC                    = 0x00000000,
DCIOCHIP_PAD_MODE_DP                     = 0x00000001,
} DCIOCHIP_PAD_MODE;

typedef enum DCIOCHIP_PD_EN {
DCIOCHIP_PD_EN_NOTALLOW                  = 0x00000000,
DCIOCHIP_PD_EN_ALLOW                     = 0x00000001,
} DCIOCHIP_PD_EN;

typedef enum DCIOCHIP_REF_27_SRC_SEL {
DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER     = 0x00000000,
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001,
DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS      = 0x00000002,
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003,
} DCIOCHIP_REF_27_SRC_SEL;

typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE      = 0x00000000,
DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE       = 0x00000001,
} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;

typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x00000000,
DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x00000001,
} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;

typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000,
DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001,
DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002,
DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003,
} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;

typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
DCIO_BL_PWM_DISABLE                      = 0x00000000,
DCIO_BL_PWM_ENABLE                       = 0x00000001,
} DCIO_BL_PWM_CNTL_BL_PWM_EN;

typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
DCIO_BL_PWM_FRACTIONAL_DISABLE           = 0x00000000,
DCIO_BL_PWM_FRACTIONAL_ENABLE            = 0x00000001,
} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;

typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;

typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000,
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001,
} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;

typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000,
} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;

typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE        = 0x00000000,
DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE         = 0x00000001,
} DCIO_BL_PWM_GRP1_REG_LOCK;

typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000,
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001,
} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;

typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
DCIO_TEST_CLK_SEL_DISPCLK                = 0x00000000,
DCIO_TEST_CLK_SEL_GATED_DISPCLK          = 0x00000001,
DCIO_TEST_CLK_SEL_SCLK                   = 0x00000002,
} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;

typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
DCIO_DISPCLK_R_DCIO_GATE_DISABLE         = 0x00000000,
DCIO_DISPCLK_R_DCIO_GATE_ENABLE          = 0x00000001,
} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;

typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS {
DCIO_DISPCLK_R_DCIO_RAMP_DISABLE         = 0x00000000,
DCIO_DISPCLK_R_DCIO_RAMP_ENABLE          = 0x00000001,
} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS;

typedef enum DCIO_DACA_SOFT_RESET {
DCIO_DACA_SOFT_RESET_DEASSERT            = 0x00000000,
DCIO_DACA_SOFT_RESET_ASSERT              = 0x00000001,
} DCIO_DACA_SOFT_RESET;

typedef enum DCIO_DBG_OUT_12BIT_SEL {
DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT         = 0x00000000,
DCIO_DBG_OUT_12BIT_SEL_MID_12BIT         = 0x00000001,
DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT        = 0x00000002,
DCIO_DBG_OUT_12BIT_SEL_OVERRIDE          = 0x00000003,
} DCIO_DBG_OUT_12BIT_SEL;

typedef enum DCIO_DBG_OUT_PIN_SEL {
DCIO_DBG_OUT_PIN_SEL_LOW_12BIT           = 0x00000000,
DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT          = 0x00000001,
} DCIO_DBG_OUT_PIN_SEL;

typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
DCIO_EXT_VSYNC_MUX_SWAPLOCKB             = 0x00000000,
DCIO_EXT_VSYNC_MUX_CRTC0                 = 0x00000001,
DCIO_EXT_VSYNC_MUX_CRTC1                 = 0x00000002,
DCIO_EXT_VSYNC_MUX_CRTC2                 = 0x00000003,
DCIO_EXT_VSYNC_MUX_CRTC3                 = 0x00000004,
DCIO_EXT_VSYNC_MUX_CRTC4                 = 0x00000005,
DCIO_EXT_VSYNC_MUX_CRTC5                 = 0x00000006,
DCIO_EXT_VSYNC_MUX_GENERICB              = 0x00000007,
} DCIO_DCO_DCFE_EXT_VSYNC_MUX;

typedef enum DCIO_DCO_EXT_VSYNC_MASK {
DCIO_EXT_VSYNC_MASK_NONE                 = 0x00000000,
DCIO_EXT_VSYNC_MASK_PIPE0                = 0x00000001,
DCIO_EXT_VSYNC_MASK_PIPE1                = 0x00000002,
DCIO_EXT_VSYNC_MASK_PIPE2                = 0x00000003,
DCIO_EXT_VSYNC_MASK_PIPE3                = 0x00000004,
DCIO_EXT_VSYNC_MASK_PIPE4                = 0x00000005,
DCIO_EXT_VSYNC_MASK_PIPE5                = 0x00000006,
DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE       = 0x00000007,
} DCIO_DCO_EXT_VSYNC_MASK;

typedef enum DCIO_DCRXPHY_SOFT_RESET {
DCIO_DCRXPHY_SOFT_RESET_DEASSERT         = 0x00000000,
DCIO_DCRXPHY_SOFT_RESET_ASSERT           = 0x00000001,
} DCIO_DCRXPHY_SOFT_RESET;

typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
DCIO_DVO_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;

typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
DCIO_VIP_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;

typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
DCIO_VIP_MUX_EN_DVO                      = 0x00000000,
DCIO_VIP_MUX_EN_VIP                      = 0x00000001,
} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;

typedef enum DCIO_DC_GENERICA_SEL {
DCIO_GENERICA_SEL_DACA_STEREOSYNC        = 0x00000000,
DCIO_GENERICA_SEL_STEREOSYNC             = 0x00000001,
DCIO_GENERICA_SEL_DACA_PIXCLK            = 0x00000002,
DCIO_GENERICA_SEL_DACB_PIXCLK            = 0x00000003,
DCIO_GENERICA_SEL_DVOA_CTL3              = 0x00000004,
DCIO_GENERICA_SEL_P1_PLLCLK              = 0x00000005,
DCIO_GENERICA_SEL_P2_PLLCLK              = 0x00000006,
DCIO_GENERICA_SEL_DVOA_STEREOSYNC        = 0x00000007,
DCIO_GENERICA_SEL_DACA_FIELD_NUMBER      = 0x00000008,
DCIO_GENERICA_SEL_DACB_FIELD_NUMBER      = 0x00000009,
DCIO_GENERICA_SEL_GENERICA_DCCG          = 0x0000000a,
DCIO_GENERICA_SEL_SYNCEN                 = 0x0000000b,
DCIO_GENERICA_SEL_GENERICA_SCG           = 0x0000000c,
DCIO_GENERICA_SEL_RESERVED_VALUE13       = 0x0000000d,
DCIO_GENERICA_SEL_RESERVED_VALUE14       = 0x0000000e,
DCIO_GENERICA_SEL_RESERVED_VALUE15       = 0x0000000f,
DCIO_GENERICA_SEL_GENERICA_DPRX          = 0x00000010,
DCIO_GENERICA_SEL_GENERICB_DPRX          = 0x00000011,
} DCIO_DC_GENERICA_SEL;

typedef enum DCIO_DC_GENERICB_SEL {
DCIO_GENERICB_SEL_DACA_STEREOSYNC        = 0x00000000,
DCIO_GENERICB_SEL_STEREOSYNC             = 0x00000001,
DCIO_GENERICB_SEL_DACA_PIXCLK            = 0x00000002,
DCIO_GENERICB_SEL_DACB_PIXCLK            = 0x00000003,
DCIO_GENERICB_SEL_DVOA_CTL3              = 0x00000004,
DCIO_GENERICB_SEL_P1_PLLCLK              = 0x00000005,
DCIO_GENERICB_SEL_P2_PLLCLK              = 0x00000006,
DCIO_GENERICB_SEL_DVOA_STEREOSYNC        = 0x00000007,
DCIO_GENERICB_SEL_DACA_FIELD_NUMBER      = 0x00000008,
DCIO_GENERICB_SEL_DACB_FIELD_NUMBER      = 0x00000009,
DCIO_GENERICB_SEL_GENERICB_DCCG          = 0x0000000a,
DCIO_GENERICB_SEL_SYNCEN                 = 0x0000000b,
DCIO_GENERICB_SEL_GENERICA_SCG           = 0x0000000c,
DCIO_GENERICB_SEL_RESERVED_VALUE13       = 0x0000000d,
DCIO_GENERICB_SEL_RESERVED_VALUE14       = 0x0000000e,
DCIO_GENERICB_SEL_RESERVED_VALUE15       = 0x0000000f,
} DCIO_DC_GENERICB_SEL;

typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2         = 0x00000000,
DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2         = 0x00000001,
DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2         = 0x00000002,
DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2         = 0x00000003,
DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2         = 0x00000004,
DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2         = 0x00000005,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;

typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
DCIO_UNIPHYA_FBDIV_CLK                   = 0x00000000,
DCIO_UNIPHYB_FBDIV_CLK                   = 0x00000001,
DCIO_UNIPHYC_FBDIV_CLK                   = 0x00000002,
DCIO_UNIPHYD_FBDIV_CLK                   = 0x00000003,
DCIO_UNIPHYE_FBDIV_CLK                   = 0x00000004,
DCIO_UNIPHYF_FBDIV_CLK                   = 0x00000005,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;

typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
DCIO_UNIPHYA_FBDIV_SSC_CLK               = 0x00000000,
DCIO_UNIPHYB_FBDIV_SSC_CLK               = 0x00000001,
DCIO_UNIPHYC_FBDIV_SSC_CLK               = 0x00000002,
DCIO_UNIPHYD_FBDIV_SSC_CLK               = 0x00000003,
DCIO_UNIPHYE_FBDIV_SSC_CLK               = 0x00000004,
DCIO_UNIPHYF_FBDIV_SSC_CLK               = 0x00000005,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;

typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
DCIO_UNIPHYA_TEST_REFDIV_CLK             = 0x00000000,
DCIO_UNIPHYB_TEST_REFDIV_CLK             = 0x00000001,
DCIO_UNIPHYC_TEST_REFDIV_CLK             = 0x00000002,
DCIO_UNIPHYD_TEST_REFDIV_CLK             = 0x00000003,
DCIO_UNIPHYE_TEST_REFDIV_CLK             = 0x00000004,
DCIO_UNIPHYF_TEST_REFDIV_CLK             = 0x00000005,
} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;

typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x00000000,
DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x00000001,
} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;

typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS    = 0x00000000,
DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE    = 0x00000001,
} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;

typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
DCIO_DPRX_LOOPBACK_ENABLE_NORMAL         = 0x00000000,
DCIO_DPRX_LOOPBACK_ENABLE_LOOP           = 0x00000001,
} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;

typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
DCIO_DC_GPIO_MACRO_DEBUG_NORMAL          = 0x00000000,
DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF        = 0x00000001,
DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x00000002,
DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x00000003,
} DCIO_DC_GPIO_MACRO_DEBUG;

typedef enum DCIO_DC_GPIO_VIP_DEBUG {
DCIO_DC_GPIO_VIP_DEBUG_NORMAL            = 0x00000000,
DCIO_DC_GPIO_VIP_DEBUG_CG_BIG            = 0x00000001,
} DCIO_DC_GPIO_VIP_DEBUG;

typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x00000002,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x00000003,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x00000004,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x00000005,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x00000006,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x00000007,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x00000008,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x00000009,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0x0000000a,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0x0000000b,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x0000000c,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x0000000d,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0x0000000e,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0x0000000f,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x00000010,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x00000011,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x00000012,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x00000013,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x00000014,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x00000015,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x00000016,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x00000017,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000018,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000019,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x0000001a,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x0000001b,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x0000001c,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x0000001d,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x0000001e,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x0000001f,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x00000020,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x00000021,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x00000022,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x00000023,
} DCIO_DC_GPU_TIMER_READ_SELECT;

typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
DCIO_GPU_TIMER_START_0_END_27            = 0x00000000,
DCIO_GPU_TIMER_START_1_END_28            = 0x00000001,
DCIO_GPU_TIMER_START_2_END_29            = 0x00000002,
DCIO_GPU_TIMER_START_3_END_30            = 0x00000003,
DCIO_GPU_TIMER_START_4_END_31            = 0x00000004,
DCIO_GPU_TIMER_START_6_END_33            = 0x00000005,
DCIO_GPU_TIMER_START_8_END_35            = 0x00000006,
DCIO_GPU_TIMER_START_10_END_37           = 0x00000007,
} DCIO_DC_GPU_TIMER_START_POSITION;

typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA         = 0x00000000,
DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x00000001,
DCIO_MVP_PIXEL_SRC_STATUS_CRTC           = 0x00000002,
DCIO_MVP_PIXEL_SRC_STATUS_LB             = 0x00000003,
} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;

typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
DCIO_DC_PAD_EXTERN_SIG_SEL_MVP           = 0x00000000,
DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA        = 0x00000001,
DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK     = 0x00000002,
DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC   = 0x00000003,
DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA      = 0x00000004,
DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB      = 0x00000005,
DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC      = 0x00000006,
DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1          = 0x00000007,
DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2          = 0x00000008,
DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK       = 0x00000009,
DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA      = 0x0000000a,
DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK       = 0x0000000b,
DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA      = 0x0000000c,
DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1         = 0x0000000d,
DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0         = 0x0000000e,
DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL        = 0x0000000f,
} DCIO_DC_PAD_EXTERN_SIG_SEL;

typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE        = 0x00000000,
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1          = 0x00000001,
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2          = 0x00000002,
DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003,
} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;

typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
DCIO_HSYNCA_OUTPUT_SEL_DISABLE           = 0x00000000,
DCIO_HSYNCA_OUTPUT_SEL_PPLL1             = 0x00000001,
DCIO_HSYNCA_OUTPUT_SEL_PPLL2             = 0x00000002,
DCIO_HSYNCA_OUTPUT_SEL_RESERVED          = 0x00000003,
} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;

typedef enum DCIO_DPHY_LANE_SEL {
DCIO_DPHY_LANE_SEL_LANE0                 = 0x00000000,
DCIO_DPHY_LANE_SEL_LANE1                 = 0x00000001,
DCIO_DPHY_LANE_SEL_LANE2                 = 0x00000002,
DCIO_DPHY_LANE_SEL_LANE3                 = 0x00000003,
} DCIO_DPHY_LANE_SEL;

typedef enum DCIO_DSYNC_SOFT_RESET {
DCIO_DSYNC_SOFT_RESET_DEASSERT           = 0x00000000,
DCIO_DSYNC_SOFT_RESET_ASSERT             = 0x00000001,
} DCIO_DSYNC_SOFT_RESET;

typedef enum DCIO_GENLK_CLK_GSL_MASK {
DCIO_GENLK_CLK_GSL_MASK_NO               = 0x00000000,
DCIO_GENLK_CLK_GSL_MASK_TIMING           = 0x00000001,
DCIO_GENLK_CLK_GSL_MASK_STEREO           = 0x00000002,
} DCIO_GENLK_CLK_GSL_MASK;

typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
DCIO_GENLK_VSYNC_GSL_MASK_NO             = 0x00000000,
DCIO_GENLK_VSYNC_GSL_MASK_TIMING         = 0x00000001,
DCIO_GENLK_VSYNC_GSL_MASK_STEREO         = 0x00000002,
} DCIO_GENLK_VSYNC_GSL_MASK;

typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
} DCIO_GSL0_GLOBAL_UNLOCK_SEL;

typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
DCIO_GSL0_TIMING_SYNC_SEL_PIPE           = 0x00000000,
DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
} DCIO_GSL0_TIMING_SYNC_SEL;

typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
} DCIO_GSL1_GLOBAL_UNLOCK_SEL;

typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
DCIO_GSL1_TIMING_SYNC_SEL_PIPE           = 0x00000000,
DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
} DCIO_GSL1_TIMING_SYNC_SEL;

typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
} DCIO_GSL2_GLOBAL_UNLOCK_SEL;

typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
DCIO_GSL2_TIMING_SYNC_SEL_PIPE           = 0x00000000,
DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
} DCIO_GSL2_TIMING_SYNC_SEL;

typedef enum DCIO_GSL_SEL {
DCIO_GSL_SEL_GROUP_0                     = 0x00000000,
DCIO_GSL_SEL_GROUP_1                     = 0x00000001,
DCIO_GSL_SEL_GROUP_2                     = 0x00000002,
} DCIO_GSL_SEL;

typedef enum DCIO_GSL_VSYNC_SEL {
DCIO_GSL_VSYNC_SEL_PIPE0                 = 0x00000000,
DCIO_GSL_VSYNC_SEL_PIPE1                 = 0x00000001,
DCIO_GSL_VSYNC_SEL_PIPE2                 = 0x00000002,
DCIO_GSL_VSYNC_SEL_PIPE3                 = 0x00000003,
DCIO_GSL_VSYNC_SEL_PIPE4                 = 0x00000004,
DCIO_GSL_VSYNC_SEL_PIPE5                 = 0x00000005,
} DCIO_GSL_VSYNC_SEL;

typedef enum DCIO_IMPCAL_STEP_DELAY {
DCIO_IMPCAL_STEP_DELAY_1us               = 0x00000000,
DCIO_IMPCAL_STEP_DELAY_2us               = 0x00000001,
DCIO_IMPCAL_STEP_DELAY_3us               = 0x00000002,
DCIO_IMPCAL_STEP_DELAY_4us               = 0x00000003,
DCIO_IMPCAL_STEP_DELAY_5us               = 0x00000004,
DCIO_IMPCAL_STEP_DELAY_6us               = 0x00000005,
DCIO_IMPCAL_STEP_DELAY_7us               = 0x00000006,
DCIO_IMPCAL_STEP_DELAY_8us               = 0x00000007,
DCIO_IMPCAL_STEP_DELAY_9us               = 0x00000008,
DCIO_IMPCAL_STEP_DELAY_10us              = 0x00000009,
DCIO_IMPCAL_STEP_DELAY_11us              = 0x0000000a,
DCIO_IMPCAL_STEP_DELAY_12us              = 0x0000000b,
DCIO_IMPCAL_STEP_DELAY_13us              = 0x0000000c,
DCIO_IMPCAL_STEP_DELAY_14us              = 0x0000000d,
DCIO_IMPCAL_STEP_DELAY_15us              = 0x0000000e,
DCIO_IMPCAL_STEP_DELAY_16us              = 0x0000000f,
} DCIO_IMPCAL_STEP_DELAY;

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
DCIO_LVTMA_BLON_OFF                      = 0x00000000,
DCIO_LVTMA_BLON_ON                       = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
DCIO_LVTMA_BLON_POL_NON_INVERT           = 0x00000000,
DCIO_LVTMA_BLON_POL_INVERT               = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
DCIO_LVTMA_DIGON_OFF                     = 0x00000000,
DCIO_LVTMA_DIGON_ON                      = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
DCIO_LVTMA_DIGON_POL_NON_INVERT          = 0x00000000,
DCIO_LVTMA_DIGON_POL_INVERT              = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
DCIO_LVTMA_SYNCEN_POL_NON_INVERT         = 0x00000000,
DCIO_LVTMA_SYNCEN_POL_INVERT             = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;

typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF   = 0x00000000,
DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON    = 0x00000001,
} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;

typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON      = 0x00000000,
DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE  = 0x00000001,
} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;

typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
DCIO_SWAPLOCK_A_GSL_MASK_NO              = 0x00000000,
DCIO_SWAPLOCK_A_GSL_MASK_TIMING          = 0x00000001,
DCIO_SWAPLOCK_A_GSL_MASK_STEREO          = 0x00000002,
} DCIO_SWAPLOCK_A_GSL_MASK;

typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
DCIO_SWAPLOCK_B_GSL_MASK_NO              = 0x00000000,
DCIO_SWAPLOCK_B_GSL_MASK_TIMING          = 0x00000001,
DCIO_SWAPLOCK_B_GSL_MASK_STEREO          = 0x00000002,
} DCIO_SWAPLOCK_B_GSL_MASK;

typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0      = 0x00000000,
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1      = 0x00000001,
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2      = 0x00000002,
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3      = 0x00000003,
} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;

typedef enum DCIO_UNIPHY_IMPCAL_SEL {
DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE       = 0x00000000,
DCIO_UNIPHY_IMPCAL_SEL_BINARY            = 0x00000001,
} DCIO_UNIPHY_IMPCAL_SEL;

typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
DCIO_UNIPHY_CHANNEL_NO_INVERSION         = 0x00000000,
DCIO_UNIPHY_CHANNEL_INVERTED             = 0x00000001,
} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;

typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000,
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW   = 0x00000001,
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002,
} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;

typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001,
} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;

typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU                          = 0x00000004,
} ENUM_NUM_SIMD_PER_CU;

typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL                       = 0x00000000,
GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
GATCL1_TYPE_BYPASS                       = 0x00000002,
} GATCL1RequestType;

typedef enum MEM_PWR_DIS_CTRL {
ENABLE_MEM_PWR_CTRL                      = 0x00000000,
DISABLE_MEM_PWR_CTRL                     = 0x00000001,
} MEM_PWR_DIS_CTRL;

typedef enum MEM_PWR_FORCE_CTRL {
NO_FORCE_REQUEST                         = 0x00000000,
FORCE_LIGHT_SLEEP_REQUEST                = 0x00000001,
FORCE_DEEP_SLEEP_REQUEST                 = 0x00000002,
FORCE_SHUT_DOWN_REQUEST                  = 0x00000003,
} MEM_PWR_FORCE_CTRL;

typedef enum MEM_PWR_FORCE_CTRL2 {
NO_FORCE_REQ                             = 0x00000000,
FORCE_LIGHT_SLEEP_REQ                    = 0x00000001,
} MEM_PWR_FORCE_CTRL2;

typedef enum MEM_PWR_SEL_CTRL {
DYNAMIC_SHUT_DOWN_ENABLE                 = 0x00000000,
DYNAMIC_DEEP_SLEEP_ENABLE                = 0x00000001,
DYNAMIC_LIGHT_SLEEP_ENABLE               = 0x00000002,
} MEM_PWR_SEL_CTRL;

typedef enum MEM_PWR_SEL_CTRL2 {
DYNAMIC_DEEP_SLEEP_EN                    = 0x00000000,
DYNAMIC_LIGHT_SLEEP_EN                   = 0x00000001,
} MEM_PWR_SEL_CTRL2;

typedef enum MTYPE {
MTYPE_NC_NV                              = 0x00000000,
MTYPE_NC                                 = 0x00000001,
MTYPE_CC                                 = 0x00000002,
MTYPE_UC                                 = 0x00000003,
} MTYPE;

typedef enum SEM_PERF_SEL {
SEM_PERF_SEL_CYCLE                       = 0x00000000,
SEM_PERF_SEL_IDLE                        = 0x00000001,
SEM_PERF_SEL_SDMA0_REQ_SIGNAL            = 0x00000002,
SEM_PERF_SEL_SDMA1_REQ_SIGNAL            = 0x00000003,
SEM_PERF_SEL_UVD_REQ_SIGNAL              = 0x00000004,
SEM_PERF_SEL_VCE0_REQ_SIGNAL             = 0x00000005,
SEM_PERF_SEL_ACP_REQ_SIGNAL              = 0x00000006,
SEM_PERF_SEL_ISP_REQ_SIGNAL              = 0x00000007,
SEM_PERF_SEL_VCE1_REQ_SIGNAL             = 0x00000008,
SEM_PERF_SEL_VP8_REQ_SIGNAL              = 0x00000009,
SEM_PERF_SEL_CPG_E0_REQ_SIGNAL           = 0x0000000a,
SEM_PERF_SEL_CPG_E1_REQ_SIGNAL           = 0x0000000b,
SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL     = 0x0000000c,
SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL     = 0x0000000d,
SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL     = 0x0000000e,
SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL     = 0x0000000f,
SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL     = 0x00000010,
SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL     = 0x00000011,
SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL     = 0x00000012,
SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL     = 0x00000013,
SEM_PERF_SEL_SDMA0_REQ_WAIT              = 0x00000014,
SEM_PERF_SEL_SDMA1_REQ_WAIT              = 0x00000015,
SEM_PERF_SEL_UVD_REQ_WAIT                = 0x00000016,
SEM_PERF_SEL_VCE0_REQ_WAIT               = 0x00000017,
SEM_PERF_SEL_ACP_REQ_WAIT                = 0x00000018,
SEM_PERF_SEL_ISP_REQ_WAIT                = 0x00000019,
SEM_PERF_SEL_VCE1_REQ_WAIT               = 0x0000001a,
SEM_PERF_SEL_VP8_REQ_WAIT                = 0x0000001b,
SEM_PERF_SEL_CPG_E0_REQ_WAIT             = 0x0000001c,
SEM_PERF_SEL_CPG_E1_REQ_WAIT             = 0x0000001d,
SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT       = 0x0000001e,
SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT       = 0x0000001f,
SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT       = 0x00000020,
SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT       = 0x00000021,
SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT       = 0x00000022,
SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT       = 0x00000023,
SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT       = 0x00000024,
SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT       = 0x00000025,
SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT       = 0x00000026,
SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT       = 0x00000027,
SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT       = 0x00000028,
SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT       = 0x00000029,
SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT       = 0x0000002a,
SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT       = 0x0000002b,
SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT       = 0x0000002c,
SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT       = 0x0000002d,
SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT       = 0x0000002e,
SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT       = 0x0000002f,
SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT      = 0x00000030,
SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT      = 0x00000031,
SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT      = 0x00000032,
SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT      = 0x00000033,
SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT      = 0x00000034,
SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT      = 0x00000035,
SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT      = 0x00000036,
SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT      = 0x00000037,
SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT      = 0x00000038,
SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT      = 0x00000039,
SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT      = 0x0000003a,
SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT      = 0x0000003b,
SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT      = 0x0000003c,
SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT      = 0x0000003d,
SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT      = 0x0000003e,
SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT      = 0x0000003f,
SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT      = 0x00000040,
SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT      = 0x00000041,
SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT      = 0x00000042,
SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT      = 0x00000043,
SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT      = 0x00000044,
SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT      = 0x00000045,
SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT       = 0x00000046,
SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT       = 0x00000047,
SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT       = 0x00000048,
SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT       = 0x00000049,
SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT       = 0x0000004a,
SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT       = 0x0000004b,
SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT       = 0x0000004c,
SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT       = 0x0000004d,
SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT       = 0x0000004e,
SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT       = 0x0000004f,
SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT      = 0x00000050,
SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT      = 0x00000051,
SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT      = 0x00000052,
SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT      = 0x00000053,
SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT      = 0x00000054,
SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT      = 0x00000055,
SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT      = 0x00000056,
SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT      = 0x00000057,
SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT      = 0x00000058,
SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT      = 0x00000059,
SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT      = 0x0000005a,
SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT      = 0x0000005b,
SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT      = 0x0000005c,
SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT      = 0x0000005d,
SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT      = 0x0000005e,
SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT      = 0x0000005f,
SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT      = 0x00000060,
SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT      = 0x00000061,
SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT      = 0x00000062,
SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT      = 0x00000063,
SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT      = 0x00000064,
SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT      = 0x00000065,
SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT      = 0x00000066,
SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT      = 0x00000067,
SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT      = 0x00000068,
SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT      = 0x00000069,
SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT      = 0x0000006a,
SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT      = 0x0000006b,
SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT      = 0x0000006c,
SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT      = 0x0000006d,
SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT      = 0x0000006e,
SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT      = 0x0000006f,
SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT     = 0x00000070,
SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT     = 0x00000071,
SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT     = 0x00000072,
SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT     = 0x00000073,
SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT     = 0x00000074,
SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT     = 0x00000075,
SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT     = 0x00000076,
SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT     = 0x00000077,
SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT     = 0x00000078,
SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT     = 0x00000079,
SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT     = 0x0000007a,
SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT     = 0x0000007b,
SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT     = 0x0000007c,
SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT     = 0x0000007d,
SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT     = 0x0000007e,
SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT     = 0x0000007f,
SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT     = 0x00000080,
SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT     = 0x00000081,
SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT     = 0x00000082,
SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT     = 0x00000083,
SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT     = 0x00000084,
SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT     = 0x00000085,
SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT      = 0x00000086,
SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT      = 0x00000087,
SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT      = 0x00000088,
SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT      = 0x00000089,
SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT      = 0x0000008a,
SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT      = 0x0000008b,
SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT      = 0x0000008c,
SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT      = 0x0000008d,
SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT      = 0x0000008e,
SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT      = 0x0000008f,
SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT     = 0x00000090,
SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT     = 0x00000091,
SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT     = 0x00000092,
SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT     = 0x00000093,
SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT     = 0x00000094,
SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT     = 0x00000095,
SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT     = 0x00000096,
SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT     = 0x00000097,
SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT     = 0x00000098,
SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT     = 0x00000099,
SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT     = 0x0000009a,
SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT     = 0x0000009b,
SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT     = 0x0000009c,
SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT     = 0x0000009d,
SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT     = 0x0000009e,
SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT     = 0x0000009f,
SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT     = 0x000000a0,
SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT     = 0x000000a1,
SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT     = 0x000000a2,
SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT     = 0x000000a3,
SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT     = 0x000000a4,
SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT     = 0x000000a5,
SEM_PERF_SEL_MC_RD_REQ                   = 0x000000a6,
SEM_PERF_SEL_MC_RD_RET                   = 0x000000a7,
SEM_PERF_SEL_MC_WR_REQ                   = 0x000000a8,
SEM_PERF_SEL_MC_WR_RET                   = 0x000000a9,
SEM_PERF_SEL_ATC_REQ                     = 0x000000aa,
SEM_PERF_SEL_ATC_RET                     = 0x000000ab,
SEM_PERF_SEL_ATC_XNACK                   = 0x000000ac,
SEM_PERF_SEL_ATC_INVALIDATION            = 0x000000ad,
} SEM_PERF_SEL;

typedef enum SH_MEM_ADDRESS_MODE {
SH_MEM_ADDRESS_MODE_GPUVM64              = 0x00000000,
SH_MEM_ADDRESS_MODE_GPUVM32              = 0x00000001,
SH_MEM_ADDRESS_MODE_HSA64                = 0x00000002,
SH_MEM_ADDRESS_MODE_HSA32                = 0x00000003,
} SH_MEM_ADDRESS_MODE;

typedef enum SQ_EDC_INFO_SOURCE {
SQ_EDC_INFO_SOURCE_INVALID               = 0x00000000,
SQ_EDC_INFO_SOURCE_INST                  = 0x00000001,
SQ_EDC_INFO_SOURCE_SGPR                  = 0x00000002,
SQ_EDC_INFO_SOURCE_VGPR                  = 0x00000003,
SQ_EDC_INFO_SOURCE_LDS                   = 0x00000004,
SQ_EDC_INFO_SOURCE_GDS                   = 0x00000005,
SQ_EDC_INFO_SOURCE_TA                    = 0x00000006,
} SQ_EDC_INFO_SOURCE;

typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x00000018,
SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x00000019,
} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;

typedef enum SRBM_GFX_CNTL_SEL {
SRBM_GFX_CNTL_BIF                        = 0x00000000,
SRBM_GFX_CNTL_SDMA0                      = 0x00000001,
SRBM_GFX_CNTL_SDMA1                      = 0x00000002,
SRBM_GFX_CNTL_GRBM                       = 0x00000003,
SRBM_GFX_CNTL_UVD                        = 0x00000004,
SRBM_GFX_CNTL_VCE0                       = 0x00000005,
SRBM_GFX_CNTL_VCE1                       = 0x00000006,
SRBM_GFX_CNTL_ACP                        = 0x00000007,
SRBM_GFX_CNTL_SMU                        = 0x00000008,
SRBM_GFX_CNTL_SAMMSP                     = 0x00000009,
SRBM_GFX_CNTL_SAMSCP                     = 0x0000000a,
SRBM_GFX_CNTL_ISP                        = 0x0000000b,
SRBM_GFX_CNTL_TST                        = 0x0000000c,
SRBM_GFX_CNTL_SDMA2                      = 0x0000000d,
SRBM_GFX_CNTL_SDMA3                      = 0x0000000e,
} SRBM_GFX_CNTL_SEL;

typedef enum SX_BLEND_OPT {
BLEND_OPT_PRESERVE_NONE_IGNORE_ALL       = 0x00000000,
BLEND_OPT_PRESERVE_ALL_IGNORE_NONE       = 0x00000001,
BLEND_OPT_PRESERVE_C1_IGNORE_C0          = 0x00000002,
BLEND_OPT_PRESERVE_C0_IGNORE_C1          = 0x00000003,
BLEND_OPT_PRESERVE_A1_IGNORE_A0          = 0x00000004,
BLEND_OPT_PRESERVE_A0_IGNORE_A1          = 0x00000005,
BLEND_OPT_PRESERVE_NONE_IGNORE_A0        = 0x00000006,
BLEND_OPT_PRESERVE_NONE_IGNORE_NONE      = 0x00000007,
} SX_BLEND_OPT;

typedef enum SX_DOWNCONVERT_FORMAT {
SX_RT_EXPORT_NO_CONVERSION               = 0x00000000,
SX_RT_EXPORT_32_R                        = 0x00000001,
SX_RT_EXPORT_32_A                        = 0x00000002,
SX_RT_EXPORT_10_11_11                    = 0x00000003,
SX_RT_EXPORT_2_10_10_10                  = 0x00000004,
SX_RT_EXPORT_8_8_8_8                     = 0x00000005,
SX_RT_EXPORT_5_6_5                       = 0x00000006,
SX_RT_EXPORT_1_5_5_5                     = 0x00000007,
SX_RT_EXPORT_4_4_4_4                     = 0x00000008,
SX_RT_EXPORT_16_16_GR                    = 0x00000009,
SX_RT_EXPORT_16_16_AR                    = 0x0000000a,
} SX_DOWNCONVERT_FORMAT;

typedef enum SX_OPT_COMB_FCN {
OPT_COMB_NONE                            = 0x00000000,
OPT_COMB_ADD                             = 0x00000001,
OPT_COMB_SUBTRACT                        = 0x00000002,
OPT_COMB_MIN                             = 0x00000003,
OPT_COMB_MAX                             = 0x00000004,
OPT_COMB_REVSUBTRACT                     = 0x00000005,
OPT_COMB_BLEND_DISABLED                  = 0x00000006,
OPT_COMB_SAFE_ADD                        = 0x00000007,
} SX_OPT_COMB_FCN;

typedef enum SYS_GRBM_GFX_INDEX_SEL {
GRBM_GFX_INDEX_BIF                       = 0x00000000,
GRBM_GFX_INDEX_SDMA0                     = 0x00000001,
GRBM_GFX_INDEX_SDMA1                     = 0x00000002,
RESEVERED0                               = 0x00000003,
GRBM_GFX_INDEX_UVD                       = 0x00000004,
GRBM_GFX_INDEX_VCE0                      = 0x00000005,
GRBM_GFX_INDEX_VCE1                      = 0x00000006,
GRBM_GFX_INDEX_ACP                       = 0x00000007,
GRBM_GFX_INDEX_SMU                       = 0x00000008,
GRBM_GFX_INDEX_SAMMSP                    = 0x00000009,
GRBM_GFX_INDEX_SAMSCP                    = 0x0000000a,
GRBM_GFX_INDEX_ISP                       = 0x0000000b,
GRBM_GFX_INDEX_TST                       = 0x0000000c,
GRBM_GFX_INDEX_SDMA2                     = 0x0000000d,
GRBM_GFX_INDEX_SDMA3                     = 0x0000000e,
} SYS_GRBM_GFX_INDEX_SEL;

typedef enum TCP_DSM_DATA_SEL {
TCP_DSM_DISABLE                          = 0x00000000,
TCP_DSM_SEL0                             = 0x00000001,
TCP_DSM_SEL1                             = 0x00000002,
TCP_DSM_SEL_BOTH                         = 0x00000003,
} TCP_DSM_DATA_SEL;

typedef enum TCP_DSM_SINGLE_WRITE {
TCP_DSM_SINGLE_WRITE_EN                  = 0x00000001,
} TCP_DSM_SINGLE_WRITE;

typedef enum VGT_DIST_MODE {
NO_DIST                                  = 0x00000000,
PATCHES                                  = 0x00000001,
DONUTS                                   = 0x00000002,
TRAPEZOIDS                               = 0x00000003,
} VGT_DIST_MODE;

typedef enum WD_IA_DRAW_SOURCE {
WD_IA_DRAW_SOURCE_DMA                    = 0x00000000,
WD_IA_DRAW_SOURCE_IMMD                   = 0x00000001,
WD_IA_DRAW_SOURCE_AUTO                   = 0x00000002,
WD_IA_DRAW_SOURCE_OPAQ                   = 0x00000003,
} WD_IA_DRAW_SOURCE;

//Merged Defines
#define CG_SRBM_END_ADDR__CI__VI                        0x000008ff
#define CG_SRBM_END_ADDR__SI                            0x00000900
#define CG_SRBM_START_ADDR                              0x00000600
#define CONFIG_SPACE1_END__CI__VI                       0x00002bff
#define CONFIG_SPACE1_START__CI__VI                     0x00002000
#define CONFIG_SPACE2_END__CI__VI                       0x00009fff
#define CONFIG_SPACE2_START__CI__VI                     0x00003000
#define CONFIG_SPACE_END__CI__VI                        0x00009fff
#define CONFIG_SPACE_END__SI                            0x000033ff
#define CONFIG_SPACE_START                              0x00002000
#define CONTEXT_SPACE_END__CI__VI                       0x0000bfff
#define CONTEXT_SPACE_END__SI                           0x0000afff
#define CONTEXT_SPACE_START                             0x0000a000
#define CSDATA_ADDR_WIDTH__CI__VI                       0x00000007
#define CSDATA_DATA_WIDTH__CI__VI                       0x00000020
#define CSDATA_TYPE_WIDTH__CI__VI                       0x00000002
#define GB_TILING_CONFIG_MACROTABLE_SIZE__CI__VI        0x00000010
#define GB_TILING_CONFIG_TABLE_SIZE                     0x00000020
#define GSTHREADID_SIZE                                 0x00000002
#define INST_ID_ECC_INTERRUPT_MSG__CI__VI               0xfffffff0
#define INST_ID_HOST_REG_TRAP_MSG__CI__VI               0xfffffffe
#define INST_ID_HW_TRAP__CI__VI                         0xfffffff2
#define INST_ID_KILL_SEQ__CI__VI                        0xfffffff3
#define INST_ID_TTRACE_NEW_PC_MSG__CI__VI               0xfffffff1
#define IQ_DEQUEUE_RETRY__CI__VI                        0x00000004
#define IQ_INTR_TYPE_IB__CI__VI                         0x00000001
#define IQ_INTR_TYPE_MQD__CI__VI                        0x00000002
#define IQ_INTR_TYPE_PQ__CI__VI                         0x00000000
#define IQ_OFFLOAD_RETRY__CI__VI                        0x00000001
#define IQ_QUEUE_SLEEP__CI__VI                          0x00000000
#define IQ_SCH_WAVE_MSG__CI__VI                         0x00000002
#define IQ_SEM_REARM__CI__VI                            0x00000003
#define KEYS_CHAIN_ADR__CI                              0x00000000
#define PERSISTENT_SPACE_END                            0x00002fff
#define PERSISTENT_SPACE_START                          0x00002c00
#define RCU_CCF_BITS0__CI                               0x00000500
#define RCU_CCF_BITS1__CI                               0x00001000
#define RCU_CCF_BITS__SI                                0x00000508
#define RCU_CCF_DWORDS0__CI                             0x00000028
#define RCU_CCF_DWORDS1__CI                             0x0000007f
#define RCU_SAM_BYTES__CI                               0x00000040
#define RCU_SAM_RTL_BYTES__CI                           0x00000040
#define RCU_SMU_BYTES__CI__VI                           0x00000011
#define RCU_SMU_RTL_BYTES__CI__VI                       0x00000011
#define ROM_SIGNATURE                                   0x0000aa55
#define SAMU_KEY_EADR__CI                               0x000000e0
#define SAMU_KEY_SADR__CI                               0x000000a1
#define SEM_ECC_ERROR__CI__VI                           0x00000000
#define SEM_FAILED__CI__VI                              0x00000002
#define SEM_PASSED__CI__VI                              0x00000003
#define SEM_RESERVED__CI__VI                            0x00000001
#define SMC_HEADER_SIZE__CI__VI                         0x00000040
#define SMC_MSG_ADJUST_LOADLINE__CI__VI                 0x00000018
#define SMC_MSG_CASCADE_PLL_OFF__CI__VI                 0x00000006
#define SMC_MSG_CASCADE_PLL_ON__CI__VI                  0x00000007
#define SMC_MSG_CONFIG_BAPM__CI__VI                     0x0000000d
#define SMC_MSG_CONFIG_HTC_LIMIT__CI__VI                0x00000010
#define SMC_MSG_CONFIG_LCLK_DPM__CI__VI                 0x00000009
#define SMC_MSG_CONFIG_LOADLINE__CI__VI                 0x00000017
#define SMC_MSG_CONFIG_LPMx__CI__VI                     0x0000000f
#define SMC_MSG_CONFIG_NBDPM__CI__VI                    0x00000016
#define SMC_MSG_CONFIG_TDC_LIMIT__CI__VI                0x0000000e
#define SMC_MSG_CONFIG_TDP_CNTL__CI__VI                 0x00000013
#define SMC_MSG_CONFIG_THERMAL_CNTL__CI__VI             0x00000011
#define SMC_MSG_CONFIG_VOLTAGE_CNTL__CI__VI             0x00000012
#define SMC_MSG_CONFIG_VPC_ACCUMULATOR__CI__VI          0x0000000c
#define SMC_MSG_DDI_PHY_OFF__CI__VI                     0x00000004
#define SMC_MSG_DDI_PHY_ON__CI__VI                      0x00000005
#define SMC_MSG_DIS_PM_CNTL__CI__VI                     0x00000015
#define SMC_MSG_EN_PM_CNTL__CI__VI                      0x00000014
#define SMC_MSG_FLUSH_DATA_CACHE__CI__VI                0x0000000a
#define SMC_MSG_FLUSH_INSTRUCTION_CACHE__CI__VI         0x0000000b
#define SMC_MSG_PHY_LN_OFF__CI__VI                      0x00000002
#define SMC_MSG_PHY_LN_ON__CI__VI                       0x00000003
#define SMC_MSG_PWR_OFF_x16__CI__VI                     0x00000008
#define SMC_MSG_RESET__CI__VI                           0x00000020
#define SMC_MSG_TEST__CI__VI                            0x00000001
#define SMC_MSG_VOLTAGE__CI__VI                         0x00000025
#define SMC_VERSION_MAJOR__CI__VI                       0x00000007
#define SMC_VERSION_MINOR__CI__VI                       0x00000000
#define SQDEC_BEGIN                                     0x00002300
#define SQDEC_END                                       0x000023ff
#define SQGFXUDEC_BEGIN__CI                             0x0000c340
#define SQGFXUDEC_END__CI__VI                           0x0000c380
#define SQIND_GLOBAL_REGS_OFFSET                        0x00000000
#define SQIND_GLOBAL_REGS_SIZE                          0x00000008
#define SQIND_LOCAL_REGS_OFFSET                         0x00000008
#define SQIND_LOCAL_REGS_SIZE                           0x00000008
#define SQIND_WAVE_HWREGS_OFFSET                        0x00000010
#define SQIND_WAVE_HWREGS_SIZE                          0x000001f0
#define SQIND_WAVE_SGPRS_OFFSET                         0x00000200
#define SQIND_WAVE_SGPRS_SIZE                           0x00000200
#define SQPERFDDEC_BEGIN__CI__VI                        0x0000d1c0
#define SQPERFDDEC_END__CI__VI                          0x0000d240
#define SQPERFSDEC_BEGIN__CI__VI                        0x0000d9c0
#define SQPERFSDEC_END__CI__VI                          0x0000da40
#define SQPWRDEC_BEGIN__CI__VI                          0x0000f08c
#define SQPWRDEC_END__CI__VI                            0x0000f094
#define SQ_ATTR0                                        0x00000000
#define SQ_BUFFER_ATOMIC_FCMPSWAP__SI__CI               0x0000003e
#define SQ_BUFFER_ATOMIC_FCMPSWAP_X2__SI__CI            0x0000005e
#define SQ_BUFFER_ATOMIC_FMAX__SI__CI                   0x00000040
#define SQ_BUFFER_ATOMIC_FMAX_X2__SI__CI                0x00000060
#define SQ_BUFFER_ATOMIC_FMIN__SI__CI                   0x0000003f
#define SQ_BUFFER_ATOMIC_FMIN_X2__SI__CI                0x0000005f
#define SQ_BUFFER_LOAD_DWORDX3__CI                      0x0000000f
#define SQ_BUFFER_LOAD_FORMAT_X                         0x00000000
#define SQ_BUFFER_LOAD_FORMAT_XY                        0x00000001
#define SQ_BUFFER_LOAD_FORMAT_XYZ                       0x00000002
#define SQ_BUFFER_LOAD_FORMAT_XYZW                      0x00000003
#define SQ_BUFFER_STORE_BYTE                            0x00000018
#define SQ_BUFFER_STORE_DWORD                           0x0000001c
#define SQ_BUFFER_STORE_DWORDX2                         0x0000001d
#define SQ_BUFFER_STORE_DWORDX3__CI                     0x0000001f
#define SQ_BUFFER_STORE_FORMAT_X                        0x00000004
#define SQ_BUFFER_STORE_FORMAT_XY                       0x00000005
#define SQ_BUFFER_STORE_FORMAT_XYZ                      0x00000006
#define SQ_BUFFER_STORE_FORMAT_XYZW                     0x00000007
#define SQ_BUFFER_STORE_SHORT                           0x0000001a
#define SQ_BUFFER_WBINVL1_VOL__CI                       0x00000070
#define SQ_CHAN_W                                       0x00000003
#define SQ_CHAN_X                                       0x00000000
#define SQ_CHAN_Y                                       0x00000001
#define SQ_CHAN_Z                                       0x00000002
#define SQ_CNT1                                         0x00000000
#define SQ_CNT2                                         0x00000001
#define SQ_CNT3                                         0x00000002
#define SQ_CNT4                                         0x00000003
#define SQ_DFMT_10_10_10_2__SI__CI                      0x00000008
#define SQ_DFMT_10_11_11__SI__CI                        0x00000006
#define SQ_DFMT_11_11_10__SI__CI                        0x00000007
#define SQ_DFMT_16__SI__CI                              0x00000002
#define SQ_DFMT_16_16__SI__CI                           0x00000005
#define SQ_DFMT_16_16_16_16__SI__CI                     0x0000000c
#define SQ_DFMT_2_10_10_10__SI__CI                      0x00000009
#define SQ_DFMT_32__SI__CI                              0x00000004
#define SQ_DFMT_32_32__SI__CI                           0x0000000b
#define SQ_DFMT_32_32_32__SI__CI                        0x0000000d
#define SQ_DFMT_32_32_32_32__SI__CI                     0x0000000e
#define SQ_DFMT_8__SI__CI                               0x00000001
#define SQ_DFMT_8_8__SI__CI                             0x00000003
#define SQ_DFMT_8_8_8_8__SI__CI                         0x0000000a
#define SQ_DFMT_INVALID__SI__CI                         0x00000000
#define SQ_DISPATCHER_GFX_CNT_PER_RING                  0x00000008
#define SQ_DISPATCHER_GFX_MIN                           0x00000010
#define SQ_DS_ADD_RTN_U32                               0x00000020
#define SQ_DS_ADD_RTN_U64                               0x00000060
#define SQ_DS_ADD_SRC2_U32                              0x00000080
#define SQ_DS_ADD_SRC2_U64                              0x000000c0
#define SQ_DS_ADD_U32                                   0x00000000
#define SQ_DS_ADD_U64                                   0x00000040
#define SQ_DS_AND_B32                                   0x00000009
#define SQ_DS_AND_B64                                   0x00000049
#define SQ_DS_AND_RTN_B32                               0x00000029
#define SQ_DS_AND_RTN_B64                               0x00000069
#define SQ_DS_AND_SRC2_B32                              0x00000089
#define SQ_DS_AND_SRC2_B64                              0x000000c9
#define SQ_DS_CMPST_B32                                 0x00000010
#define SQ_DS_CMPST_B64                                 0x00000050
#define SQ_DS_CMPST_F32                                 0x00000011
#define SQ_DS_CMPST_F64                                 0x00000051
#define SQ_DS_CMPST_RTN_B32                             0x00000030
#define SQ_DS_CMPST_RTN_B64                             0x00000070
#define SQ_DS_CMPST_RTN_F32                             0x00000031
#define SQ_DS_CMPST_RTN_F64                             0x00000071
#define SQ_DS_CONDXCHG32_RTN_B128__CI__VI               0x000000fd
#define SQ_DS_CONDXCHG32_RTN_B64__CI__VI                0x0000007e
#define SQ_DS_DEC_RTN_U32                               0x00000024
#define SQ_DS_DEC_RTN_U64                               0x00000064
#define SQ_DS_DEC_SRC2_U32                              0x00000084
#define SQ_DS_DEC_SRC2_U64                              0x000000c4
#define SQ_DS_DEC_U32                                   0x00000004
#define SQ_DS_DEC_U64                                   0x00000044
#define SQ_DS_GWS_SEMA_RELEASE_ALL__CI                  0x00000018
#define SQ_DS_INC_RTN_U32                               0x00000023
#define SQ_DS_INC_RTN_U64                               0x00000063
#define SQ_DS_INC_SRC2_U32                              0x00000083
#define SQ_DS_INC_SRC2_U64                              0x000000c3
#define SQ_DS_INC_U32                                   0x00000003
#define SQ_DS_INC_U64                                   0x00000043
#define SQ_DS_MAX_F32                                   0x00000013
#define SQ_DS_MAX_F64                                   0x00000053
#define SQ_DS_MAX_I32                                   0x00000006
#define SQ_DS_MAX_I64                                   0x00000046
#define SQ_DS_MAX_RTN_F32                               0x00000033
#define SQ_DS_MAX_RTN_F64                               0x00000073
#define SQ_DS_MAX_RTN_I32                               0x00000026
#define SQ_DS_MAX_RTN_I64                               0x00000066
#define SQ_DS_MAX_RTN_U32                               0x00000028
#define SQ_DS_MAX_RTN_U64                               0x00000068
#define SQ_DS_MAX_SRC2_F32                              0x00000093
#define SQ_DS_MAX_SRC2_F64                              0x000000d3
#define SQ_DS_MAX_SRC2_I32                              0x00000086
#define SQ_DS_MAX_SRC2_I64                              0x000000c6
#define SQ_DS_MAX_SRC2_U32                              0x00000088
#define SQ_DS_MAX_SRC2_U64                              0x000000c8
#define SQ_DS_MAX_U32                                   0x00000008
#define SQ_DS_MAX_U64                                   0x00000048
#define SQ_DS_MIN_F32                                   0x00000012
#define SQ_DS_MIN_F64                                   0x00000052
#define SQ_DS_MIN_I32                                   0x00000005
#define SQ_DS_MIN_I64                                   0x00000045
#define SQ_DS_MIN_RTN_F32                               0x00000032
#define SQ_DS_MIN_RTN_F64                               0x00000072
#define SQ_DS_MIN_RTN_I32                               0x00000025
#define SQ_DS_MIN_RTN_I64                               0x00000065
#define SQ_DS_MIN_RTN_U32                               0x00000027
#define SQ_DS_MIN_RTN_U64                               0x00000067
#define SQ_DS_MIN_SRC2_F32                              0x00000092
#define SQ_DS_MIN_SRC2_F64                              0x000000d2
#define SQ_DS_MIN_SRC2_I32                              0x00000085
#define SQ_DS_MIN_SRC2_I64                              0x000000c5
#define SQ_DS_MIN_SRC2_U32                              0x00000087
#define SQ_DS_MIN_SRC2_U64                              0x000000c7
#define SQ_DS_MIN_U32                                   0x00000007
#define SQ_DS_MIN_U64                                   0x00000047
#define SQ_DS_MSKOR_B32                                 0x0000000c
#define SQ_DS_MSKOR_B64                                 0x0000004c
#define SQ_DS_MSKOR_RTN_B32                             0x0000002c
#define SQ_DS_MSKOR_RTN_B64                             0x0000006c
#define SQ_DS_NOP__CI__VI                               0x00000014
#define SQ_DS_OR_B32                                    0x0000000a
#define SQ_DS_OR_B64                                    0x0000004a
#define SQ_DS_OR_RTN_B32                                0x0000002a
#define SQ_DS_OR_RTN_B64                                0x0000006a
#define SQ_DS_OR_SRC2_B32                               0x0000008a
#define SQ_DS_OR_SRC2_B64                               0x000000ca
#define SQ_DS_READ2ST64_B32                             0x00000038
#define SQ_DS_READ2ST64_B64                             0x00000078
#define SQ_DS_READ2_B32                                 0x00000037
#define SQ_DS_READ2_B64                                 0x00000077
#define SQ_DS_READ_B128__CI__VI                         0x000000ff
#define SQ_DS_READ_B32                                  0x00000036
#define SQ_DS_READ_B64                                  0x00000076
#define SQ_DS_READ_B96__CI__VI                          0x000000fe
#define SQ_DS_READ_I16                                  0x0000003b
#define SQ_DS_READ_I8                                   0x00000039
#define SQ_DS_READ_U16                                  0x0000003c
#define SQ_DS_READ_U8                                   0x0000003a
#define SQ_DS_RSUB_RTN_U32                              0x00000022
#define SQ_DS_RSUB_RTN_U64                              0x00000062
#define SQ_DS_RSUB_SRC2_U32                             0x00000082
#define SQ_DS_RSUB_SRC2_U64                             0x000000c2
#define SQ_DS_RSUB_U32                                  0x00000002
#define SQ_DS_RSUB_U64                                  0x00000042
#define SQ_DS_SUB_RTN_U32                               0x00000021
#define SQ_DS_SUB_RTN_U64                               0x00000061
#define SQ_DS_SUB_SRC2_U32                              0x00000081
#define SQ_DS_SUB_SRC2_U64                              0x000000c1
#define SQ_DS_SUB_U32                                   0x00000001
#define SQ_DS_SUB_U64                                   0x00000041
#define SQ_DS_WRAP_RTN_B32__CI__VI                      0x00000034
#define SQ_DS_WRITE2ST64_B32                            0x0000000f
#define SQ_DS_WRITE2ST64_B64                            0x0000004f
#define SQ_DS_WRITE2_B32                                0x0000000e
#define SQ_DS_WRITE2_B64                                0x0000004e
#define SQ_DS_WRITE_B128__CI__VI                        0x000000df
#define SQ_DS_WRITE_B16                                 0x0000001f
#define SQ_DS_WRITE_B32                                 0x0000000d
#define SQ_DS_WRITE_B64                                 0x0000004d
#define SQ_DS_WRITE_B8                                  0x0000001e
#define SQ_DS_WRITE_B96__CI__VI                         0x000000de
#define SQ_DS_WRITE_SRC2_B32                            0x0000008d
#define SQ_DS_WRITE_SRC2_B64                            0x000000cd
#define SQ_DS_WRXCHG2ST64_RTN_B32                       0x0000002f
#define SQ_DS_WRXCHG2ST64_RTN_B64                       0x0000006f
#define SQ_DS_WRXCHG2_RTN_B32                           0x0000002e
#define SQ_DS_WRXCHG2_RTN_B64                           0x0000006e
#define SQ_DS_WRXCHG_RTN_B32                            0x0000002d
#define SQ_DS_WRXCHG_RTN_B64                            0x0000006d
#define SQ_DS_XOR_B32                                   0x0000000b
#define SQ_DS_XOR_B64                                   0x0000004b
#define SQ_DS_XOR_RTN_B32                               0x0000002b
#define SQ_DS_XOR_RTN_B64                               0x0000006b
#define SQ_DS_XOR_SRC2_B32                              0x0000008b
#define SQ_DS_XOR_SRC2_B64                              0x000000cb
#define SQ_ENC_DS_BITS                                  0xd8000000
#define SQ_ENC_DS_FIELD                                 0x00000036
#define SQ_ENC_DS_MASK                                  0xfc000000
#define SQ_ENC_EXP_MASK                                 0xfc000000
#define SQ_ENC_FLAT_BITS__CI__VI                        0xdc000000
#define SQ_ENC_FLAT_FIELD__CI__VI                       0x00000037
#define SQ_ENC_FLAT_MASK__CI__VI                        0xfc000000
#define SQ_ENC_MIMG_BITS                                0xf0000000
#define SQ_ENC_MIMG_FIELD                               0x0000003c
#define SQ_ENC_MIMG_MASK                                0xfc000000
#define SQ_ENC_MTBUF_BITS                               0xe8000000
#define SQ_ENC_MTBUF_FIELD                              0x0000003a
#define SQ_ENC_MTBUF_MASK                               0xfc000000
#define SQ_ENC_MUBUF_BITS                               0xe0000000
#define SQ_ENC_MUBUF_FIELD                              0x00000038
#define SQ_ENC_MUBUF_MASK                               0xfc000000
#define SQ_ENC_SMRD_BITS__SI__CI                        0xc0000000
#define SQ_ENC_SMRD_FIELD__SI__CI                       0x00000018
#define SQ_ENC_SMRD_MASK__SI__CI                        0xf8000000
#define SQ_ENC_SOP1_BITS                                0xbe800000
#define SQ_ENC_SOP1_FIELD                               0x0000017d
#define SQ_ENC_SOP1_MASK                                0xff800000
#define SQ_ENC_SOP2_BITS                                0x80000000
#define SQ_ENC_SOP2_FIELD                               0x00000002
#define SQ_ENC_SOP2_MASK                                0xc0000000
#define SQ_ENC_SOPC_BITS                                0xbf000000
#define SQ_ENC_SOPC_FIELD                               0x0000017e
#define SQ_ENC_SOPC_MASK                                0xff800000
#define SQ_ENC_SOPK_BITS                                0xb0000000
#define SQ_ENC_SOPK_FIELD                               0x0000000b
#define SQ_ENC_SOPK_MASK                                0xf0000000
#define SQ_ENC_SOPP_BITS                                0xbf800000
#define SQ_ENC_SOPP_FIELD                               0x0000017f
#define SQ_ENC_SOPP_MASK                                0xff800000
#define SQ_ENC_VINTRP_MASK                              0xfc000000
#define SQ_ENC_VOP1_BITS                                0x7e000000
#define SQ_ENC_VOP1_FIELD                               0x0000003f
#define SQ_ENC_VOP1_MASK                                0xfe000000
#define SQ_ENC_VOP2_BITS                                0x00000000
#define SQ_ENC_VOP2_FIELD                               0x00000000
#define SQ_ENC_VOP2_MASK                                0x80000000
#define SQ_ENC_VOP3_BITS                                0xd0000000
#define SQ_ENC_VOP3_FIELD                               0x00000034
#define SQ_ENC_VOP3_MASK                                0xfc000000
#define SQ_ENC_VOPC_BITS                                0x7c000000
#define SQ_ENC_VOPC_FIELD                               0x0000003e
#define SQ_ENC_VOPC_MASK                                0xfe000000
#define SQ_EQ                                           0x00000002
#define SQ_EXEC_HI                                      0x0000007f
#define SQ_EXEC_LO                                      0x0000007e
#define SQ_EXP                                          0x00000000
#define SQ_EXP_GDS0                                     0x00000018
#define SQ_EXP_MRT0                                     0x00000000
#define SQ_EXP_MRTZ                                     0x00000008
#define SQ_EXP_NULL                                     0x00000009
#define SQ_EXP_NUM_GDS                                  0x00000005
#define SQ_EXP_NUM_MRT                                  0x00000008
#define SQ_EXP_NUM_PARAM                                0x00000020
#define SQ_EXP_NUM_POS                                  0x00000004
#define SQ_EXP_PARAM0                                   0x00000020
#define SQ_EXP_POS0                                     0x0000000c
#define SQ_EX_MODE_EXCP_ADDR_WATCH__CI__VI              0x00000007
#define SQ_EX_MODE_EXCP_DIV0__CI__VI                    0x00000002
#define SQ_EX_MODE_EXCP_INEXACT__CI__VI                 0x00000005
#define SQ_EX_MODE_EXCP_INPUT_DENORM__CI__VI            0x00000001
#define SQ_EX_MODE_EXCP_INT_DIV0__CI__VI                0x00000006
#define SQ_EX_MODE_EXCP_INVALID__CI__VI                 0x00000000
#define SQ_EX_MODE_EXCP_MEM_VIOL__CI__VI                0x00000008
#define SQ_EX_MODE_EXCP_OVERFLOW__CI__VI                0x00000003
#define SQ_EX_MODE_EXCP_UNDERFLOW__CI__VI               0x00000004
#define SQ_EX_MODE_EXCP_VALU_BASE__CI__VI               0x00000000
#define SQ_EX_MODE_EXCP_VALU_SIZE__CI__VI               0x00000007
#define SQ_F                                            0x00000000
#define SQ_FLAT_ATOMIC_ADD_X2__CI                       0x00000052
#define SQ_FLAT_ATOMIC_ADD__CI                          0x00000032
#define SQ_FLAT_ATOMIC_AND_X2__CI                       0x00000059
#define SQ_FLAT_ATOMIC_AND__CI                          0x00000039
#define SQ_FLAT_ATOMIC_CMPSWAP_X2__CI                   0x00000051
#define SQ_FLAT_ATOMIC_CMPSWAP__CI                      0x00000031
#define SQ_FLAT_ATOMIC_DEC_X2__CI                       0x0000005d
#define SQ_FLAT_ATOMIC_DEC__CI                          0x0000003d
#define SQ_FLAT_ATOMIC_FCMPSWAP_X2__CI                  0x0000005e
#define SQ_FLAT_ATOMIC_FCMPSWAP__CI                     0x0000003e
#define SQ_FLAT_ATOMIC_FMAX_X2__CI                      0x00000060
#define SQ_FLAT_ATOMIC_FMAX__CI                         0x00000040
#define SQ_FLAT_ATOMIC_FMIN_X2__CI                      0x0000005f
#define SQ_FLAT_ATOMIC_FMIN__CI                         0x0000003f
#define SQ_FLAT_ATOMIC_INC_X2__CI                       0x0000005c
#define SQ_FLAT_ATOMIC_INC__CI                          0x0000003c
#define SQ_FLAT_ATOMIC_OR_X2__CI                        0x0000005a
#define SQ_FLAT_ATOMIC_OR__CI                           0x0000003a
#define SQ_FLAT_ATOMIC_SMAX_X2__CI                      0x00000057
#define SQ_FLAT_ATOMIC_SMAX__CI                         0x00000037
#define SQ_FLAT_ATOMIC_SMIN_X2__CI                      0x00000055
#define SQ_FLAT_ATOMIC_SMIN__CI                         0x00000035
#define SQ_FLAT_ATOMIC_SUB_X2__CI                       0x00000053
#define SQ_FLAT_ATOMIC_SUB__CI                          0x00000033
#define SQ_FLAT_ATOMIC_SWAP_X2__CI                      0x00000050
#define SQ_FLAT_ATOMIC_SWAP__CI                         0x00000030
#define SQ_FLAT_ATOMIC_UMAX_X2__CI                      0x00000058
#define SQ_FLAT_ATOMIC_UMAX__CI                         0x00000038
#define SQ_FLAT_ATOMIC_UMIN_X2__CI                      0x00000056
#define SQ_FLAT_ATOMIC_UMIN__CI                         0x00000036
#define SQ_FLAT_ATOMIC_XOR_X2__CI                       0x0000005b
#define SQ_FLAT_ATOMIC_XOR__CI                          0x0000003b
#define SQ_FLAT_LOAD_DWORDX2__CI                        0x0000000d
#define SQ_FLAT_LOAD_DWORDX3__CI                        0x0000000f
#define SQ_FLAT_LOAD_DWORDX4__CI                        0x0000000e
#define SQ_FLAT_LOAD_DWORD__CI                          0x0000000c
#define SQ_FLAT_LOAD_SBYTE__CI                          0x00000009
#define SQ_FLAT_LOAD_SSHORT__CI                         0x0000000b
#define SQ_FLAT_LOAD_UBYTE__CI                          0x00000008
#define SQ_FLAT_LOAD_USHORT__CI                         0x0000000a
#define SQ_FLAT_SCRATCH_HI__CI                          0x00000069
#define SQ_FLAT_SCRATCH_LO__CI                          0x00000068
#define SQ_FLAT_STORE_BYTE__CI__VI                      0x00000018
#define SQ_FLAT_STORE_DWORDX2__CI__VI                   0x0000001d
#define SQ_FLAT_STORE_DWORDX3__CI                       0x0000001f
#define SQ_FLAT_STORE_DWORDX4__CI                       0x0000001e
#define SQ_FLAT_STORE_DWORD__CI__VI                     0x0000001c
#define SQ_FLAT_STORE_SHORT__CI__VI                     0x0000001a
#define SQ_GE                                           0x00000006
#define SQ_GFXDEC_BEGIN                                 0x0000a000
#define SQ_GFXDEC_END                                   0x0000c000
#define SQ_GFXDEC_STATE_ID_SHIFT                        0x0000000a
#define SQ_GS_OP_CUT                                    0x00000001
#define SQ_GS_OP_EMIT                                   0x00000002
#define SQ_GS_OP_EMIT_CUT                               0x00000003
#define SQ_GS_OP_NOP                                    0x00000000
#define SQ_GT                                           0x00000004
#define SQ_HWREG_ID_SHIFT                               0x00000000
#define SQ_HWREG_ID_SIZE                                0x00000006
#define SQ_HWREG_OFFSET_SHIFT                           0x00000006
#define SQ_HWREG_OFFSET_SIZE                            0x00000005
#define SQ_HWREG_SIZE_SHIFT                             0x0000000b
#define SQ_HWREG_SIZE_SIZE                              0x00000005
#define SQ_HW_REG_GPR_ALLOC                             0x00000005
#define SQ_HW_REG_HW_ID                                 0x00000004
#define SQ_HW_REG_IB_DBG0                               0x0000000c
#define SQ_HW_REG_IB_STS                                0x00000007
#define SQ_HW_REG_INST_DW0                              0x0000000a
#define SQ_HW_REG_INST_DW1                              0x0000000b
#define SQ_HW_REG_LDS_ALLOC                             0x00000006
#define SQ_HW_REG_MODE                                  0x00000001
#define SQ_HW_REG_PC_HI                                 0x00000009
#define SQ_HW_REG_PC_LO                                 0x00000008
#define SQ_HW_REG_STATUS                                0x00000002
#define SQ_HW_REG_TRAPSTS                               0x00000003
#define SQ_IMAGE_ATOMIC_AND                             0x00000018
#define SQ_IMAGE_ATOMIC_DEC                             0x0000001c
#define SQ_IMAGE_ATOMIC_FCMPSWAP__SI__CI                0x0000001d
#define SQ_IMAGE_ATOMIC_FMAX__SI__CI                    0x0000001f
#define SQ_IMAGE_ATOMIC_FMIN__SI__CI                    0x0000001e
#define SQ_IMAGE_ATOMIC_INC                             0x0000001b
#define SQ_IMAGE_ATOMIC_OR                              0x00000019
#define SQ_IMAGE_ATOMIC_SMAX                            0x00000016
#define SQ_IMAGE_ATOMIC_SMIN                            0x00000014
#define SQ_IMAGE_ATOMIC_UMAX                            0x00000017
#define SQ_IMAGE_ATOMIC_UMIN                            0x00000015
#define SQ_IMAGE_ATOMIC_XOR                             0x0000001a
#define SQ_IMAGE_GATHER4                                0x00000040
#define SQ_IMAGE_GATHER4_B                              0x00000045
#define SQ_IMAGE_GATHER4_B_CL                           0x00000046
#define SQ_IMAGE_GATHER4_B_CL_O                         0x00000056
#define SQ_IMAGE_GATHER4_B_O                            0x00000055
#define SQ_IMAGE_GATHER4_C                              0x00000048
#define SQ_IMAGE_GATHER4_CL                             0x00000041
#define SQ_IMAGE_GATHER4_CL_O                           0x00000051
#define SQ_IMAGE_GATHER4_C_B                            0x0000004d
#define SQ_IMAGE_GATHER4_C_B_CL                         0x0000004e
#define SQ_IMAGE_GATHER4_C_B_CL_O                       0x0000005e
#define SQ_IMAGE_GATHER4_C_B_O                          0x0000005d
#define SQ_IMAGE_GATHER4_C_CL                           0x00000049
#define SQ_IMAGE_GATHER4_C_CL_O                         0x00000059
#define SQ_IMAGE_GATHER4_C_L                            0x0000004c
#define SQ_IMAGE_GATHER4_C_LZ                           0x0000004f
#define SQ_IMAGE_GATHER4_C_LZ_O                         0x0000005f
#define SQ_IMAGE_GATHER4_C_L_O                          0x0000005c
#define SQ_IMAGE_GATHER4_C_O                            0x00000058
#define SQ_IMAGE_GATHER4_L                              0x00000044
#define SQ_IMAGE_GATHER4_LZ                             0x00000047
#define SQ_IMAGE_GATHER4_LZ_O                           0x00000057
#define SQ_IMAGE_GATHER4_L_O                            0x00000054
#define SQ_IMAGE_GATHER4_O                              0x00000050
#define SQ_IMAGE_GET_LOD                                0x00000060
#define SQ_IMAGE_GET_RESINFO                            0x0000000e
#define SQ_IMAGE_LOAD                                   0x00000000
#define SQ_IMAGE_LOAD_MIP                               0x00000001
#define SQ_IMAGE_LOAD_MIP_PCK                           0x00000004
#define SQ_IMAGE_LOAD_MIP_PCK_SGN                       0x00000005
#define SQ_IMAGE_LOAD_PCK                               0x00000002
#define SQ_IMAGE_LOAD_PCK_SGN                           0x00000003
#define SQ_IMAGE_RSRC256                                0x0000007e
#define SQ_IMAGE_SAMPLE                                 0x00000020
#define SQ_IMAGE_SAMPLER                                0x0000007f
#define SQ_IMAGE_SAMPLE_B                               0x00000025
#define SQ_IMAGE_SAMPLE_B_CL                            0x00000026
#define SQ_IMAGE_SAMPLE_B_CL_O                          0x00000036
#define SQ_IMAGE_SAMPLE_B_O                             0x00000035
#define SQ_IMAGE_SAMPLE_C                               0x00000028
#define SQ_IMAGE_SAMPLE_CD                              0x00000068
#define SQ_IMAGE_SAMPLE_CD_CL                           0x00000069
#define SQ_IMAGE_SAMPLE_CD_CL_O                         0x0000006d
#define SQ_IMAGE_SAMPLE_CD_O                            0x0000006c
#define SQ_IMAGE_SAMPLE_CL                              0x00000021
#define SQ_IMAGE_SAMPLE_CL_O                            0x00000031
#define SQ_IMAGE_SAMPLE_C_B                             0x0000002d
#define SQ_IMAGE_SAMPLE_C_B_CL                          0x0000002e
#define SQ_IMAGE_SAMPLE_C_B_CL_O                        0x0000003e
#define SQ_IMAGE_SAMPLE_C_B_O                           0x0000003d
#define SQ_IMAGE_SAMPLE_C_CD                            0x0000006a
#define SQ_IMAGE_SAMPLE_C_CD_CL                         0x0000006b
#define SQ_IMAGE_SAMPLE_C_CD_CL_O                       0x0000006f
#define SQ_IMAGE_SAMPLE_C_CD_O                          0x0000006e
#define SQ_IMAGE_SAMPLE_C_CL                            0x00000029
#define SQ_IMAGE_SAMPLE_C_CL_O                          0x00000039
#define SQ_IMAGE_SAMPLE_C_D                             0x0000002a
#define SQ_IMAGE_SAMPLE_C_D_CL                          0x0000002b
#define SQ_IMAGE_SAMPLE_C_D_CL_O                        0x0000003b
#define SQ_IMAGE_SAMPLE_C_D_O                           0x0000003a
#define SQ_IMAGE_SAMPLE_C_L                             0x0000002c
#define SQ_IMAGE_SAMPLE_C_LZ                            0x0000002f
#define SQ_IMAGE_SAMPLE_C_LZ_O                          0x0000003f
#define SQ_IMAGE_SAMPLE_C_L_O                           0x0000003c
#define SQ_IMAGE_SAMPLE_C_O                             0x00000038
#define SQ_IMAGE_SAMPLE_D                               0x00000022
#define SQ_IMAGE_SAMPLE_D_CL                            0x00000023
#define SQ_IMAGE_SAMPLE_D_CL_O                          0x00000033
#define SQ_IMAGE_SAMPLE_D_O                             0x00000032
#define SQ_IMAGE_SAMPLE_L                               0x00000024
#define SQ_IMAGE_SAMPLE_LZ                              0x00000027
#define SQ_IMAGE_SAMPLE_LZ_O                            0x00000037
#define SQ_IMAGE_SAMPLE_L_O                             0x00000034
#define SQ_IMAGE_SAMPLE_O                               0x00000030
#define SQ_IMAGE_STORE                                  0x00000008
#define SQ_IMAGE_STORE_MIP                              0x00000009
#define SQ_IMAGE_STORE_MIP_PCK                          0x0000000b
#define SQ_IMAGE_STORE_PCK                              0x0000000a
#define SQ_INTERRUPT_ID__SI__CI                         0x000000ef
#define SQ_LE                                           0x00000003
#define SQ_LG                                           0x00000005
#define SQ_LT                                           0x00000001
#define SQ_M0                                           0x0000007c
#define SQ_MAX_PGM_SGPRS                                0x00000068
#define SQ_MAX_PGM_VGPRS                                0x00000100
#define SQ_MSG_GS                                       0x00000002
#define SQ_MSG_GS_DONE                                  0x00000003
#define SQ_MSG_INTERRUPT                                0x00000001
#define SQ_MSG_SYSMSG                                   0x0000000f
#define SQ_NE                                           0x00000005
#define SQ_NEQ                                          0x0000000d
#define SQ_NFMT_FLOAT__SI__CI                           0x00000007
#define SQ_NFMT_SINT__SI__CI                            0x00000005
#define SQ_NFMT_SNORM__SI__CI                           0x00000001
#define SQ_NFMT_SNORM_OGL__SI__CI                       0x00000006
#define SQ_NFMT_SSCALED__SI__CI                         0x00000003
#define SQ_NFMT_UINT__SI__CI                            0x00000004
#define SQ_NFMT_UNORM__SI__CI                           0x00000000
#define SQ_NFMT_USCALED__SI__CI                         0x00000002
#define SQ_NGE                                          0x00000009
#define SQ_NGT                                          0x0000000b
#define SQ_NLE                                          0x0000000c
#define SQ_NLG                                          0x0000000a
#define SQ_NLT                                          0x0000000e
#define SQ_NUM_ATTR                                     0x00000021
#define SQ_NUM_TTMP                                     0x0000000c
#define SQ_NUM_VGPR                                     0x00000100
#define SQ_O                                            0x00000007
#define SQ_OMOD_D2                                      0x00000003
#define SQ_OMOD_M2                                      0x00000001
#define SQ_OMOD_M4                                      0x00000002
#define SQ_OMOD_OFF                                     0x00000000
#define SQ_PARAM_P0                                     0x00000002
#define SQ_PARAM_P10                                    0x00000000
#define SQ_PARAM_P20                                    0x00000001
#define SQ_SENDMSG_GSOP_SHIFT                           0x00000004
#define SQ_SENDMSG_GSOP_SIZE                            0x00000002
#define SQ_SENDMSG_MSG_SHIFT                            0x00000000
#define SQ_SENDMSG_MSG_SIZE                             0x00000004
#define SQ_SENDMSG_STREAMID_SHIFT                       0x00000008
#define SQ_SENDMSG_STREAMID_SIZE                        0x00000002
#define SQ_SENDMSG_SYSTEM_SHIFT                         0x00000004
#define SQ_SENDMSG_SYSTEM_SIZE                          0x00000003
#define SQ_SGPR0                                        0x00000000
#define SQ_SRC_0                                        0x00000080
#define SQ_SRC_0_5                                      0x000000f0
#define SQ_SRC_1                                        0x000000f2
#define SQ_SRC_10_INT                                   0x0000008a
#define SQ_SRC_11_INT                                   0x0000008b
#define SQ_SRC_12_INT                                   0x0000008c
#define SQ_SRC_13_INT                                   0x0000008d
#define SQ_SRC_14_INT                                   0x0000008e
#define SQ_SRC_15_INT                                   0x0000008f
#define SQ_SRC_16_INT                                   0x00000090
#define SQ_SRC_17_INT                                   0x00000091
#define SQ_SRC_18_INT                                   0x00000092
#define SQ_SRC_19_INT                                   0x00000093
#define SQ_SRC_1_INT                                    0x00000081
#define SQ_SRC_2                                        0x000000f4
#define SQ_SRC_20_INT                                   0x00000094
#define SQ_SRC_21_INT                                   0x00000095
#define SQ_SRC_22_INT                                   0x00000096
#define SQ_SRC_23_INT                                   0x00000097
#define SQ_SRC_24_INT                                   0x00000098
#define SQ_SRC_25_INT                                   0x00000099
#define SQ_SRC_26_INT                                   0x0000009a
#define SQ_SRC_27_INT                                   0x0000009b
#define SQ_SRC_28_INT                                   0x0000009c
#define SQ_SRC_29_INT                                   0x0000009d
#define SQ_SRC_2_INT                                    0x00000082
#define SQ_SRC_30_INT                                   0x0000009e
#define SQ_SRC_31_INT                                   0x0000009f
#define SQ_SRC_32_INT                                   0x000000a0
#define SQ_SRC_33_INT                                   0x000000a1
#define SQ_SRC_34_INT                                   0x000000a2
#define SQ_SRC_35_INT                                   0x000000a3
#define SQ_SRC_36_INT                                   0x000000a4
#define SQ_SRC_37_INT                                   0x000000a5
#define SQ_SRC_38_INT                                   0x000000a6
#define SQ_SRC_39_INT                                   0x000000a7
#define SQ_SRC_3_INT                                    0x00000083
#define SQ_SRC_4                                        0x000000f6
#define SQ_SRC_40_INT                                   0x000000a8
#define SQ_SRC_41_INT                                   0x000000a9
#define SQ_SRC_42_INT                                   0x000000aa
#define SQ_SRC_43_INT                                   0x000000ab
#define SQ_SRC_44_INT                                   0x000000ac
#define SQ_SRC_45_INT                                   0x000000ad
#define SQ_SRC_46_INT                                   0x000000ae
#define SQ_SRC_47_INT                                   0x000000af
#define SQ_SRC_48_INT                                   0x000000b0
#define SQ_SRC_49_INT                                   0x000000b1
#define SQ_SRC_4_INT                                    0x00000084
#define SQ_SRC_50_INT                                   0x000000b2
#define SQ_SRC_51_INT                                   0x000000b3
#define SQ_SRC_52_INT                                   0x000000b4
#define SQ_SRC_53_INT                                   0x000000b5
#define SQ_SRC_54_INT                                   0x000000b6
#define SQ_SRC_55_INT                                   0x000000b7
#define SQ_SRC_56_INT                                   0x000000b8
#define SQ_SRC_57_INT                                   0x000000b9
#define SQ_SRC_58_INT                                   0x000000ba
#define SQ_SRC_59_INT                                   0x000000bb
#define SQ_SRC_5_INT                                    0x00000085
#define SQ_SRC_60_INT                                   0x000000bc
#define SQ_SRC_61_INT                                   0x000000bd
#define SQ_SRC_62_INT                                   0x000000be
#define SQ_SRC_63_INT                                   0x000000bf
#define SQ_SRC_64_INT                                   0x000000c0
#define SQ_SRC_6_INT                                    0x00000086
#define SQ_SRC_7_INT                                    0x00000087
#define SQ_SRC_8_INT                                    0x00000088
#define SQ_SRC_9_INT                                    0x00000089
#define SQ_SRC_EXECZ                                    0x000000fc
#define SQ_SRC_LDS_DIRECT                               0x000000fe
#define SQ_SRC_LITERAL                                  0x000000ff
#define SQ_SRC_M_0_5                                    0x000000f1
#define SQ_SRC_M_1                                      0x000000f3
#define SQ_SRC_M_10_INT                                 0x000000ca
#define SQ_SRC_M_11_INT                                 0x000000cb
#define SQ_SRC_M_12_INT                                 0x000000cc
#define SQ_SRC_M_13_INT                                 0x000000cd
#define SQ_SRC_M_14_INT                                 0x000000ce
#define SQ_SRC_M_15_INT                                 0x000000cf
#define SQ_SRC_M_16_INT                                 0x000000d0
#define SQ_SRC_M_1_INT                                  0x000000c1
#define SQ_SRC_M_2                                      0x000000f5
#define SQ_SRC_M_2_INT                                  0x000000c2
#define SQ_SRC_M_3_INT                                  0x000000c3
#define SQ_SRC_M_4                                      0x000000f7
#define SQ_SRC_M_4_INT                                  0x000000c4
#define SQ_SRC_M_5_INT                                  0x000000c5
#define SQ_SRC_M_6_INT                                  0x000000c6
#define SQ_SRC_M_7_INT                                  0x000000c7
#define SQ_SRC_M_8_INT                                  0x000000c8
#define SQ_SRC_M_9_INT                                  0x000000c9
#define SQ_SRC_SCC                                      0x000000fd
#define SQ_SRC_VCCZ                                     0x000000fb
#define SQ_SRC_VGPR0                                    0x00000100
#define SQ_SRC_VGPR_BIT                                 0x00000100
#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT                  0x00000001
#define SQ_SYSMSG_OP_HOST_TRAP_ACK                      0x00000003
#define SQ_SYSMSG_OP_REG_RD                             0x00000002
#define SQ_SYSMSG_OP_TTRACE_PC                          0x00000004
#define SQ_S_ADDC_U32                                   0x00000004
#define SQ_S_ADD_I32                                    0x00000002
#define SQ_S_ADD_U32                                    0x00000000
#define SQ_S_BARRIER                                    0x0000000a
#define SQ_S_BITCMP0_B32                                0x0000000c
#define SQ_S_BITCMP0_B64                                0x0000000e
#define SQ_S_BITCMP1_B32                                0x0000000d
#define SQ_S_BITCMP1_B64                                0x0000000f
#define SQ_S_BRANCH                                     0x00000002
#define SQ_S_BUFFER_LOAD_DWORD                          0x00000008
#define SQ_S_BUFFER_LOAD_DWORDX16                       0x0000000c
#define SQ_S_BUFFER_LOAD_DWORDX2                        0x00000009
#define SQ_S_BUFFER_LOAD_DWORDX4                        0x0000000a
#define SQ_S_BUFFER_LOAD_DWORDX8                        0x0000000b
#define SQ_S_CBRANCH_CDBGSYS_AND_USER__CI__VI           0x0000001a
#define SQ_S_CBRANCH_CDBGSYS_OR_USER__CI__VI            0x00000019
#define SQ_S_CBRANCH_CDBGSYS__CI__VI                    0x00000017
#define SQ_S_CBRANCH_CDBGUSER__CI__VI                   0x00000018
#define SQ_S_CBRANCH_EXECNZ                             0x00000009
#define SQ_S_CBRANCH_EXECZ                              0x00000008
#define SQ_S_CBRANCH_SCC0                               0x00000004
#define SQ_S_CBRANCH_SCC1                               0x00000005
#define SQ_S_CBRANCH_VCCNZ                              0x00000007
#define SQ_S_CBRANCH_VCCZ                               0x00000006
#define SQ_S_CMP_EQ_I32                                 0x00000000
#define SQ_S_CMP_EQ_U32                                 0x00000006
#define SQ_S_CMP_GE_I32                                 0x00000003
#define SQ_S_CMP_GE_U32                                 0x00000009
#define SQ_S_CMP_GT_I32                                 0x00000002
#define SQ_S_CMP_GT_U32                                 0x00000008
#define SQ_S_CMP_LE_I32                                 0x00000005
#define SQ_S_CMP_LE_U32                                 0x0000000b
#define SQ_S_CMP_LG_I32                                 0x00000001
#define SQ_S_CMP_LG_U32                                 0x00000007
#define SQ_S_CMP_LT_I32                                 0x00000004
#define SQ_S_CMP_LT_U32                                 0x0000000a
#define SQ_S_CSELECT_B32                                0x0000000a
#define SQ_S_CSELECT_B64                                0x0000000b
#define SQ_S_DCACHE_INV_VOL__CI                         0x0000001d
#define SQ_S_DECPERFLEVEL                               0x00000015
#define SQ_S_ENDPGM                                     0x00000001
#define SQ_S_ICACHE_INV                                 0x00000013
#define SQ_S_INCPERFLEVEL                               0x00000014
#define SQ_S_LOAD_DWORD                                 0x00000000
#define SQ_S_LOAD_DWORDX16                              0x00000004
#define SQ_S_LOAD_DWORDX2                               0x00000001
#define SQ_S_LOAD_DWORDX4                               0x00000002
#define SQ_S_LOAD_DWORDX8                               0x00000003
#define SQ_S_MAX_I32                                    0x00000008
#define SQ_S_MAX_U32                                    0x00000009
#define SQ_S_MIN_I32                                    0x00000006
#define SQ_S_MIN_U32                                    0x00000007
#define SQ_S_MOVK_I32                                   0x00000000
#define SQ_S_NOP                                        0x00000000
#define SQ_S_SENDMSG                                    0x00000010
#define SQ_S_SENDMSGHALT                                0x00000011
#define SQ_S_SETHALT                                    0x0000000d
#define SQ_S_SETKILL__CI__VI                            0x0000000b
#define SQ_S_SETPRIO                                    0x0000000f
#define SQ_S_SETVSKIP                                   0x00000010
#define SQ_S_SLEEP                                      0x0000000e
#define SQ_S_SUBB_U32                                   0x00000005
#define SQ_S_SUB_I32                                    0x00000003
#define SQ_S_SUB_U32                                    0x00000001
#define SQ_S_TRAP                                       0x00000012
#define SQ_S_TTRACEDATA                                 0x00000016
#define SQ_S_WAITCNT                                    0x0000000c
#define SQ_T                                            0x00000007
#define SQ_TBA_HI                                       0x0000006d
#define SQ_TBA_LO                                       0x0000006c
#define SQ_TBUFFER_LOAD_FORMAT_X                        0x00000000
#define SQ_TBUFFER_LOAD_FORMAT_XY                       0x00000001
#define SQ_TBUFFER_LOAD_FORMAT_XYZ                      0x00000002
#define SQ_TBUFFER_LOAD_FORMAT_XYZW                     0x00000003
#define SQ_TBUFFER_STORE_FORMAT_X                       0x00000004
#define SQ_TBUFFER_STORE_FORMAT_XY                      0x00000005
#define SQ_TBUFFER_STORE_FORMAT_XYZ                     0x00000006
#define SQ_TBUFFER_STORE_FORMAT_XYZW                    0x00000007
#define SQ_THREAD_TRACE_LFSR_CS__SI__CI                 0x00008097
#define SQ_THREAD_TRACE_LFSR_ES__SI__CI                 0x00008029
#define SQ_THREAD_TRACE_LFSR_GS__SI__CI                 0x0000801f
#define SQ_THREAD_TRACE_LFSR_HS__SI__CI                 0x0000805e
#define SQ_THREAD_TRACE_LFSR_LS__SI__CI                 0x0000806b
#define SQ_THREAD_TRACE_LFSR_PS__SI__CI                 0x00008016
#define SQ_THREAD_TRACE_LFSR_VS__SI__CI                 0x0000801c
#define SQ_THREAD_TRACE_TIME_UNIT                       0x00000004
#define SQ_TMA_HI                                       0x0000006f
#define SQ_TMA_LO                                       0x0000006e
#define SQ_TRU                                          0x0000000f
#define SQ_TTMP0                                        0x00000070
#define SQ_TTMP1                                        0x00000071
#define SQ_TTMP10                                       0x0000007a
#define SQ_TTMP11                                       0x0000007b
#define SQ_TTMP2                                        0x00000072
#define SQ_TTMP3                                        0x00000073
#define SQ_TTMP4                                        0x00000074
#define SQ_TTMP5                                        0x00000075
#define SQ_TTMP6                                        0x00000076
#define SQ_TTMP7                                        0x00000077
#define SQ_TTMP8                                        0x00000078
#define SQ_TTMP9                                        0x00000079
#define SQ_U                                            0x00000008
#define SQ_VCC_ALL                                      0x00000000
#define SQ_VCC_HI                                       0x0000006b
#define SQ_VCC_LO                                       0x0000006a
#define SQ_VGPR0                                        0x00000000
#define SQ_V_ADD_I32__SI__CI                            0x00000025
#define SQ_V_ASHR_I32__SI__CI                           0x00000017
#define SQ_V_ASHR_I64__SI__CI                           0x00000163
#define SQ_V_CEIL_F64__CI__VI                           0x00000018
#define SQ_V_CMPSX_EQ_F32__SI__CI                       0x00000052
#define SQ_V_CMPSX_EQ_F64__SI__CI                       0x00000072
#define SQ_V_CMPSX_F_F32__SI__CI                        0x00000050
#define SQ_V_CMPSX_F_F64__SI__CI                        0x00000070
#define SQ_V_CMPSX_GE_F32__SI__CI                       0x00000056
#define SQ_V_CMPSX_GE_F64__SI__CI                       0x00000076
#define SQ_V_CMPSX_GT_F32__SI__CI                       0x00000054
#define SQ_V_CMPSX_GT_F64__SI__CI                       0x00000074
#define SQ_V_CMPSX_LE_F32__SI__CI                       0x00000053
#define SQ_V_CMPSX_LE_F64__SI__CI                       0x00000073
#define SQ_V_CMPSX_LG_F32__SI__CI                       0x00000055
#define SQ_V_CMPSX_LG_F64__SI__CI                       0x00000075
#define SQ_V_CMPSX_LT_F32__SI__CI                       0x00000051
#define SQ_V_CMPSX_LT_F64__SI__CI                       0x00000071
#define SQ_V_CMPSX_NEQ_F32__SI__CI                      0x0000005d
#define SQ_V_CMPSX_NEQ_F64__SI__CI                      0x0000007d
#define SQ_V_CMPSX_NGE_F32__SI__CI                      0x00000059
#define SQ_V_CMPSX_NGE_F64__SI__CI                      0x00000079
#define SQ_V_CMPSX_NGT_F32__SI__CI                      0x0000005b
#define SQ_V_CMPSX_NGT_F64__SI__CI                      0x0000007b
#define SQ_V_CMPSX_NLE_F32__SI__CI                      0x0000005c
#define SQ_V_CMPSX_NLE_F64__SI__CI                      0x0000007c
#define SQ_V_CMPSX_NLG_F32__SI__CI                      0x0000005a
#define SQ_V_CMPSX_NLG_F64__SI__CI                      0x0000007a
#define SQ_V_CMPSX_NLT_F32__SI__CI                      0x0000005e
#define SQ_V_CMPSX_NLT_F64__SI__CI                      0x0000007e
#define SQ_V_CMPSX_O_F32__SI__CI                        0x00000057
#define SQ_V_CMPSX_O_F64__SI__CI                        0x00000077
#define SQ_V_CMPSX_TRU_F32__SI__CI                      0x0000005f
#define SQ_V_CMPSX_TRU_F64__SI__CI                      0x0000007f
#define SQ_V_CMPSX_U_F32__SI__CI                        0x00000058
#define SQ_V_CMPSX_U_F64__SI__CI                        0x00000078
#define SQ_V_CMPS_EQ_F32__SI__CI                        0x00000042
#define SQ_V_CMPS_EQ_F64__SI__CI                        0x00000062
#define SQ_V_CMPS_F_F32__SI__CI                         0x00000040
#define SQ_V_CMPS_F_F64__SI__CI                         0x00000060
#define SQ_V_CMPS_GE_F32__SI__CI                        0x00000046
#define SQ_V_CMPS_GE_F64__SI__CI                        0x00000066
#define SQ_V_CMPS_GT_F32__SI__CI                        0x00000044
#define SQ_V_CMPS_GT_F64__SI__CI                        0x00000064
#define SQ_V_CMPS_LE_F32__SI__CI                        0x00000043
#define SQ_V_CMPS_LE_F64__SI__CI                        0x00000063
#define SQ_V_CMPS_LG_F32__SI__CI                        0x00000045
#define SQ_V_CMPS_LG_F64__SI__CI                        0x00000065
#define SQ_V_CMPS_LT_F32__SI__CI                        0x00000041
#define SQ_V_CMPS_LT_F64__SI__CI                        0x00000061
#define SQ_V_CMPS_NEQ_F32__SI__CI                       0x0000004d
#define SQ_V_CMPS_NEQ_F64__SI__CI                       0x0000006d
#define SQ_V_CMPS_NGE_F32__SI__CI                       0x00000049
#define SQ_V_CMPS_NGE_F64__SI__CI                       0x00000069
#define SQ_V_CMPS_NGT_F32__SI__CI                       0x0000004b
#define SQ_V_CMPS_NGT_F64__SI__CI                       0x0000006b
#define SQ_V_CMPS_NLE_F32__SI__CI                       0x0000004c
#define SQ_V_CMPS_NLE_F64__SI__CI                       0x0000006c
#define SQ_V_CMPS_NLG_F32__SI__CI                       0x0000004a
#define SQ_V_CMPS_NLG_F64__SI__CI                       0x0000006a
#define SQ_V_CMPS_NLT_F32__SI__CI                       0x0000004e
#define SQ_V_CMPS_NLT_F64__SI__CI                       0x0000006e
#define SQ_V_CMPS_O_F32__SI__CI                         0x00000047
#define SQ_V_CMPS_O_F64__SI__CI                         0x00000067
#define SQ_V_CMPS_TRU_F32__SI__CI                       0x0000004f
#define SQ_V_CMPS_TRU_F64__SI__CI                       0x0000006f
#define SQ_V_CMPS_U_F32__SI__CI                         0x00000048
#define SQ_V_CMPS_U_F64__SI__CI                         0x00000068
#define SQ_V_CNDMASK_B32                                0x00000000
#define SQ_V_CVT_F16_F32                                0x0000000a
#define SQ_V_CVT_F32_F16                                0x0000000b
#define SQ_V_CVT_F32_F64                                0x0000000f
#define SQ_V_CVT_F32_I32                                0x00000005
#define SQ_V_CVT_F32_U32                                0x00000006
#define SQ_V_CVT_F32_UBYTE0                             0x00000011
#define SQ_V_CVT_F32_UBYTE1                             0x00000012
#define SQ_V_CVT_F32_UBYTE2                             0x00000013
#define SQ_V_CVT_F32_UBYTE3                             0x00000014
#define SQ_V_CVT_F64_F32                                0x00000010
#define SQ_V_CVT_F64_I32                                0x00000004
#define SQ_V_CVT_F64_U32                                0x00000016
#define SQ_V_CVT_FLR_I32_F32                            0x0000000d
#define SQ_V_CVT_I32_F32                                0x00000008
#define SQ_V_CVT_I32_F64                                0x00000003
#define SQ_V_CVT_OFF_F32_I4                             0x0000000e
#define SQ_V_CVT_RPI_I32_F32                            0x0000000c
#define SQ_V_CVT_U32_F32                                0x00000007
#define SQ_V_CVT_U32_F64                                0x00000015
#define SQ_V_EXP_LEGACY_F32__CI                         0x00000046
#define SQ_V_FLOOR_F64__CI__VI                          0x0000001a
#define SQ_V_INTERP_MOV_F32                             0x00000002
#define SQ_V_INTERP_P1_F32                              0x00000000
#define SQ_V_INTERP_P2_F32                              0x00000001
#define SQ_V_LOG_CLAMP_F32__SI__CI                      0x00000026
#define SQ_V_LOG_LEGACY_F32__CI                         0x00000045
#define SQ_V_LSHL_B32__SI__CI                           0x00000019
#define SQ_V_LSHL_B64__SI__CI                           0x00000161
#define SQ_V_LSHR_B32__SI__CI                           0x00000015
#define SQ_V_LSHR_B64__SI__CI                           0x00000162
#define SQ_V_MAD_I64_I32__CI                            0x00000177
#define SQ_V_MAD_U64_U32__CI                            0x00000176
#define SQ_V_MAX_LEGACY_F32__SI__CI                     0x0000000e
#define SQ_V_MIN_LEGACY_F32__SI__CI                     0x0000000d
#define SQ_V_MOV_B32                                    0x00000001
#define SQ_V_MOV_FED_B32                                0x00000009
#define SQ_V_MQSAD_PK_U16_U8__CI                        0x00000173
#define SQ_V_MQSAD_U32_U8__CI                           0x00000175
#define SQ_V_MULLIT_F32__SI__CI                         0x00000150
#define SQ_V_MUL_LO_I32__SI__CI                         0x0000016b
#define SQ_V_NOP                                        0x00000000
#define SQ_V_OP1_COUNT                                  0x00000080
#define SQ_V_OP2_COUNT                                  0x00000040
#define SQ_V_OP2_OFFSET                                 0x00000100
#define SQ_V_OPC_COUNT                                  0x00000100
#define SQ_V_OPC_OFFSET                                 0x00000000
#define SQ_V_QSAD_PK_U16_U8__CI                         0x00000172
#define SQ_V_RCP_CLAMP_F32__SI__CI                      0x00000028
#define SQ_V_RCP_CLAMP_F64__SI__CI                      0x00000030
#define SQ_V_RCP_LEGACY_F32__SI__CI                     0x00000029
#define SQ_V_READFIRSTLANE_B32                          0x00000002
#define SQ_V_RNDNE_F64__CI__VI                          0x00000019
#define SQ_V_RSQ_CLAMP_F32__SI__CI                      0x0000002c
#define SQ_V_RSQ_CLAMP_F64__SI__CI                      0x00000032
#define SQ_V_RSQ_LEGACY_F32__SI__CI                     0x0000002d
#define SQ_V_SUBREV_I32__SI__CI                         0x00000027
#define SQ_V_SUB_I32__SI__CI                            0x00000026
#define SQ_V_TRUNC_F64__CI__VI                          0x00000017
#define SQ_WAITCNT_EXP_SHIFT                            0x00000004
#define SQ_WAITCNT_EXP_SIZE                             0x00000003
#define SQ_WAITCNT_LGKM_SHIFT                           0x00000008
#define SQ_WAITCNT_LGKM_SIZE                            0x00000004
#define SQ_WAITCNT_VM_SHIFT                             0x00000000
#define SQ_WAITCNT_VM_SIZE                              0x00000004
#define SQ_WAVE_TYPE_PS0                                0x00000000
#define UCONFIG_SPACE_END__CI__VI                       0x0000ffff
#define UCONFIG_SPACE_START__CI__VI                     0x0000c000
#define VMID_SZ__CI__VI                                 0x00000004

//Merged Defines

#define INST_ID_PRIV_START__VI                          0x80000000
#define INST_ID_SPI_WREXEC__VI                          0xfffffff4
#define KEYS_CHAIN_ADR__VI                              0x00000002
#define RCU_CCF_BITS__VI                                0x000002a0
#define RCU_CCF_BITS0__VI                               0x00001400
#define RCU_CCF_DWORDS__VI                              0x00000015
#define RCU_CCF_DWORDS0__VI                             0x000000a0
#define RCU_SAM_BYTES__VI                               0x00000062
#define RCU_SAM_RTL_BYTES__VI                           0x00000062
#define SAMU_KEY_CHAIN_ADR__VI                          0x00000000
#define SAMU_KEY_EADR__VI                               0x00000061
#define SAMU_KEY_SADR__VI                               0x00000000
#define SFP_BYTES__VI                                   0x00000080
#define SFP_CHAIN_ADDR__VI                              0x00000003
#define SFP_EADR__VI                                    0x0000037f
#define SFP_SADR__VI                                    0x00000000
#define SMU_KEY_CHAIN_ADR__VI                           0x00000000
#define SMU_KEY_EADR__VI                                0x00000072
#define SMU_KEY_SADR__VI                                0x00000062
#define SQGFXUDEC_BEGIN__VI                             0x0000c330
#define SQ_BUFFER_ATOMIC_ADD__SI__CI                    0x00000032
#define SQ_BUFFER_ATOMIC_ADD__VI                        0x00000042
#define SQ_BUFFER_ATOMIC_ADD_X2__SI__CI                 0x00000052
#define SQ_BUFFER_ATOMIC_ADD_X2__VI                     0x00000062
#define SQ_BUFFER_ATOMIC_AND__SI__CI                    0x00000039
#define SQ_BUFFER_ATOMIC_AND__VI                        0x00000048
#define SQ_BUFFER_ATOMIC_AND_X2__SI__CI                 0x00000059
#define SQ_BUFFER_ATOMIC_AND_X2__VI                     0x00000068
#define SQ_BUFFER_ATOMIC_CMPSWAP__SI__CI                0x00000031
#define SQ_BUFFER_ATOMIC_CMPSWAP__VI                    0x00000041
#define SQ_BUFFER_ATOMIC_CMPSWAP_X2__SI__CI             0x00000051
#define SQ_BUFFER_ATOMIC_CMPSWAP_X2__VI                 0x00000061
#define SQ_BUFFER_ATOMIC_DEC__SI__CI                    0x0000003d
#define SQ_BUFFER_ATOMIC_DEC__VI                        0x0000004c
#define SQ_BUFFER_ATOMIC_DEC_X2__SI__CI                 0x0000005d
#define SQ_BUFFER_ATOMIC_DEC_X2__VI                     0x0000006c
#define SQ_BUFFER_ATOMIC_INC__SI__CI                    0x0000003c
#define SQ_BUFFER_ATOMIC_INC__VI                        0x0000004b
#define SQ_BUFFER_ATOMIC_INC_X2__SI__CI                 0x0000005c
#define SQ_BUFFER_ATOMIC_INC_X2__VI                     0x0000006b
#define SQ_BUFFER_ATOMIC_OR__SI__CI                     0x0000003a
#define SQ_BUFFER_ATOMIC_OR__VI                         0x00000049
#define SQ_BUFFER_ATOMIC_OR_X2__SI__CI                  0x0000005a
#define SQ_BUFFER_ATOMIC_OR_X2__VI                      0x00000069
#define SQ_BUFFER_ATOMIC_SMAX__SI__CI                   0x00000037
#define SQ_BUFFER_ATOMIC_SMAX__VI                       0x00000046
#define SQ_BUFFER_ATOMIC_SMAX_X2__SI__CI                0x00000057
#define SQ_BUFFER_ATOMIC_SMAX_X2__VI                    0x00000066
#define SQ_BUFFER_ATOMIC_SMIN__SI__CI                   0x00000035
#define SQ_BUFFER_ATOMIC_SMIN__VI                       0x00000044
#define SQ_BUFFER_ATOMIC_SMIN_X2__SI__CI                0x00000055
#define SQ_BUFFER_ATOMIC_SMIN_X2__VI                    0x00000064
#define SQ_BUFFER_ATOMIC_SUB__SI__CI                    0x00000033
#define SQ_BUFFER_ATOMIC_SUB__VI                        0x00000043
#define SQ_BUFFER_ATOMIC_SUB_X2__SI__CI                 0x00000053
#define SQ_BUFFER_ATOMIC_SUB_X2__VI                     0x00000063
#define SQ_BUFFER_ATOMIC_SWAP__SI__CI                   0x00000030
#define SQ_BUFFER_ATOMIC_SWAP__VI                       0x00000040
#define SQ_BUFFER_ATOMIC_SWAP_X2__SI__CI                0x00000050
#define SQ_BUFFER_ATOMIC_SWAP_X2__VI                    0x00000060
#define SQ_BUFFER_ATOMIC_UMAX__SI__CI                   0x00000038
#define SQ_BUFFER_ATOMIC_UMAX__VI                       0x00000047
#define SQ_BUFFER_ATOMIC_UMAX_X2__SI__CI                0x00000058
#define SQ_BUFFER_ATOMIC_UMAX_X2__VI                    0x00000067
#define SQ_BUFFER_ATOMIC_UMIN__SI__CI                   0x00000036
#define SQ_BUFFER_ATOMIC_UMIN__VI                       0x00000045
#define SQ_BUFFER_ATOMIC_UMIN_X2__SI__CI                0x00000056
#define SQ_BUFFER_ATOMIC_UMIN_X2__VI                    0x00000065
#define SQ_BUFFER_ATOMIC_XOR__SI__CI                    0x0000003b
#define SQ_BUFFER_ATOMIC_XOR__VI                        0x0000004a
#define SQ_BUFFER_ATOMIC_XOR_X2__SI__CI                 0x0000005b
#define SQ_BUFFER_ATOMIC_XOR_X2__VI                     0x0000006a
#define SQ_BUFFER_LOAD_DWORD__SI__CI                    0x0000000c
#define SQ_BUFFER_LOAD_DWORD__VI                        0x00000014
#define SQ_BUFFER_LOAD_DWORDX2__SI__CI                  0x0000000d
#define SQ_BUFFER_LOAD_DWORDX2__VI                      0x00000015
#define SQ_BUFFER_LOAD_DWORDX3__VI                      0x00000016
#define SQ_BUFFER_LOAD_DWORDX4__SI__CI                  0x0000000e
#define SQ_BUFFER_LOAD_DWORDX4__VI                      0x00000017
#define SQ_BUFFER_LOAD_FORMAT_D16_X__VI                 0x00000008
#define SQ_BUFFER_LOAD_FORMAT_D16_XY__VI                0x00000009
#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ__VI               0x0000000a
#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW__VI              0x0000000b
#define SQ_BUFFER_LOAD_SBYTE__SI__CI                    0x00000009
#define SQ_BUFFER_LOAD_SBYTE__VI                        0x00000011
#define SQ_BUFFER_LOAD_SSHORT__SI__CI                   0x0000000b
#define SQ_BUFFER_LOAD_SSHORT__VI                       0x00000013
#define SQ_BUFFER_LOAD_UBYTE__SI__CI                    0x00000008
#define SQ_BUFFER_LOAD_UBYTE__VI                        0x00000010
#define SQ_BUFFER_LOAD_USHORT__SI__CI                   0x0000000a
#define SQ_BUFFER_LOAD_USHORT__VI                       0x00000012
#define SQ_BUFFER_STORE_DWORDX3__VI                     0x0000001e
#define SQ_BUFFER_STORE_DWORDX4__SI__CI                 0x0000001e
#define SQ_BUFFER_STORE_DWORDX4__VI                     0x0000001f
#define SQ_BUFFER_STORE_FORMAT_D16_X__VI                0x0000000c
#define SQ_BUFFER_STORE_FORMAT_D16_XY__VI               0x0000000d
#define SQ_BUFFER_STORE_FORMAT_D16_XYZ__VI              0x0000000e
#define SQ_BUFFER_STORE_FORMAT_D16_XYZW__VI             0x0000000f
#define SQ_BUFFER_STORE_LDS_DWORD__VI                   0x0000003d
#define SQ_BUFFER_WBINVL1__SI__CI                       0x00000071
#define SQ_BUFFER_WBINVL1__VI                           0x0000003e
#define SQ_BUFFER_WBINVL1_VOL__VI                       0x0000003f
#define SQ_DPP_BOUND_OFF__VI                            0x00000000
#define SQ_DPP_BOUND_ZERO__VI                           0x00000001
#define SQ_DPP_QUAD_PERM__VI                            0x00000000
#define SQ_DPP_ROW_BCAST15__VI                          0x00000142
#define SQ_DPP_ROW_BCAST31__VI                          0x00000143
#define SQ_DPP_ROW_HALF_MIRROR__VI                      0x00000141
#define SQ_DPP_ROW_MIRROR__VI                           0x00000140
#define SQ_DPP_ROW_RR1__VI                              0x00000121
#define SQ_DPP_ROW_RR10__VI                             0x0000012a
#define SQ_DPP_ROW_RR11__VI                             0x0000012b
#define SQ_DPP_ROW_RR12__VI                             0x0000012c
#define SQ_DPP_ROW_RR13__VI                             0x0000012d
#define SQ_DPP_ROW_RR14__VI                             0x0000012e
#define SQ_DPP_ROW_RR15__VI                             0x0000012f
#define SQ_DPP_ROW_RR2__VI                              0x00000122
#define SQ_DPP_ROW_RR3__VI                              0x00000123
#define SQ_DPP_ROW_RR4__VI                              0x00000124
#define SQ_DPP_ROW_RR5__VI                              0x00000125
#define SQ_DPP_ROW_RR6__VI                              0x00000126
#define SQ_DPP_ROW_RR7__VI                              0x00000127
#define SQ_DPP_ROW_RR8__VI                              0x00000128
#define SQ_DPP_ROW_RR9__VI                              0x00000129
#define SQ_DPP_ROW_SL1__VI                              0x00000101
#define SQ_DPP_ROW_SL10__VI                             0x0000010a
#define SQ_DPP_ROW_SL11__VI                             0x0000010b
#define SQ_DPP_ROW_SL12__VI                             0x0000010c
#define SQ_DPP_ROW_SL13__VI                             0x0000010d
#define SQ_DPP_ROW_SL14__VI                             0x0000010e
#define SQ_DPP_ROW_SL15__VI                             0x0000010f
#define SQ_DPP_ROW_SL2__VI                              0x00000102
#define SQ_DPP_ROW_SL3__VI                              0x00000103
#define SQ_DPP_ROW_SL4__VI                              0x00000104
#define SQ_DPP_ROW_SL5__VI                              0x00000105
#define SQ_DPP_ROW_SL6__VI                              0x00000106
#define SQ_DPP_ROW_SL7__VI                              0x00000107
#define SQ_DPP_ROW_SL8__VI                              0x00000108
#define SQ_DPP_ROW_SL9__VI                              0x00000109
#define SQ_DPP_ROW_SR1__VI                              0x00000111
#define SQ_DPP_ROW_SR10__VI                             0x0000011a
#define SQ_DPP_ROW_SR11__VI                             0x0000011b
#define SQ_DPP_ROW_SR12__VI                             0x0000011c
#define SQ_DPP_ROW_SR13__VI                             0x0000011d
#define SQ_DPP_ROW_SR14__VI                             0x0000011e
#define SQ_DPP_ROW_SR15__VI                             0x0000011f
#define SQ_DPP_ROW_SR2__VI                              0x00000112
#define SQ_DPP_ROW_SR3__VI                              0x00000113
#define SQ_DPP_ROW_SR4__VI                              0x00000114
#define SQ_DPP_ROW_SR5__VI                              0x00000115
#define SQ_DPP_ROW_SR6__VI                              0x00000116
#define SQ_DPP_ROW_SR7__VI                              0x00000117
#define SQ_DPP_ROW_SR8__VI                              0x00000118
#define SQ_DPP_ROW_SR9__VI                              0x00000119
#define SQ_DPP_WF_RL1__VI                               0x00000134
#define SQ_DPP_WF_RR1__VI                               0x0000013c
#define SQ_DPP_WF_SL1__VI                               0x00000130
#define SQ_DPP_WF_SR1__VI                               0x00000138
#define SQ_DS_ADD_F32__VI                               0x00000015
#define SQ_DS_ADD_RTN_F32__VI                           0x00000035
#define SQ_DS_ADD_SRC2_F32__VI                          0x00000095
#define SQ_DS_APPEND__SI__CI                            0x0000003e
#define SQ_DS_APPEND__VI                                0x000000be
#define SQ_DS_BPERMUTE_B32__VI                          0x0000003f
#define SQ_DS_CONSUME__SI__CI                           0x0000003d
#define SQ_DS_CONSUME__VI                               0x000000bd
#define SQ_DS_GWS_BARRIER__SI__CI                       0x0000001d
#define SQ_DS_GWS_BARRIER__VI                           0x0000009d
#define SQ_DS_GWS_INIT__SI__CI                          0x00000019
#define SQ_DS_GWS_INIT__VI                              0x00000099
#define SQ_DS_GWS_SEMA_BR__SI__CI                       0x0000001b
#define SQ_DS_GWS_SEMA_BR__VI                           0x0000009b
#define SQ_DS_GWS_SEMA_P__SI__CI                        0x0000001c
#define SQ_DS_GWS_SEMA_P__VI                            0x0000009c
#define SQ_DS_GWS_SEMA_RELEASE_ALL__VI                  0x00000098
#define SQ_DS_GWS_SEMA_V__SI__CI                        0x0000001a
#define SQ_DS_GWS_SEMA_V__VI                            0x0000009a
#define SQ_DS_ORDERED_COUNT__SI__CI                     0x0000003f
#define SQ_DS_ORDERED_COUNT__VI                         0x000000bf
#define SQ_DS_PERMUTE_B32__VI                           0x0000003e
#define SQ_DS_SWIZZLE_B32__SI__CI                       0x00000035
#define SQ_DS_SWIZZLE_B32__VI                           0x0000003d
#define SQ_ENC_EXP_BITS__SI__CI                         0xf8000000
#define SQ_ENC_EXP_BITS__VI                             0xc4000000
#define SQ_ENC_EXP_FIELD__SI__CI                        0x0000003e
#define SQ_ENC_EXP_FIELD__VI                            0x00000031
#define SQ_ENC_SMEM_BITS__VI                            0xc0000000
#define SQ_ENC_SMEM_FIELD__VI                           0x00000030
#define SQ_ENC_SMEM_MASK__VI                            0xfc000000
#define SQ_ENC_VINTRP_BITS__SI__CI                      0xc8000000
#define SQ_ENC_VINTRP_BITS__VI                          0xd4000000
#define SQ_ENC_VINTRP_FIELD__SI__CI                     0x00000032
#define SQ_ENC_VINTRP_FIELD__VI                         0x00000035
#define SQ_FLAT_ATOMIC_ADD__VI                          0x00000042
#define SQ_FLAT_ATOMIC_ADD_X2__VI                       0x00000062
#define SQ_FLAT_ATOMIC_AND__VI                          0x00000048
#define SQ_FLAT_ATOMIC_AND_X2__VI                       0x00000068
#define SQ_FLAT_ATOMIC_CMPSWAP__VI                      0x00000041
#define SQ_FLAT_ATOMIC_CMPSWAP_X2__VI                   0x00000061
#define SQ_FLAT_ATOMIC_DEC__VI                          0x0000004c
#define SQ_FLAT_ATOMIC_DEC_X2__VI                       0x0000006c
#define SQ_FLAT_ATOMIC_INC__VI                          0x0000004b
#define SQ_FLAT_ATOMIC_INC_X2__VI                       0x0000006b
#define SQ_FLAT_ATOMIC_OR__VI                           0x00000049
#define SQ_FLAT_ATOMIC_OR_X2__VI                        0x00000069
#define SQ_FLAT_ATOMIC_SMAX__VI                         0x00000046
#define SQ_FLAT_ATOMIC_SMAX_X2__VI                      0x00000066
#define SQ_FLAT_ATOMIC_SMIN__VI                         0x00000044
#define SQ_FLAT_ATOMIC_SMIN_X2__VI                      0x00000064
#define SQ_FLAT_ATOMIC_SUB__VI                          0x00000043
#define SQ_FLAT_ATOMIC_SUB_X2__VI                       0x00000063
#define SQ_FLAT_ATOMIC_SWAP__VI                         0x00000040
#define SQ_FLAT_ATOMIC_SWAP_X2__VI                      0x00000060
#define SQ_FLAT_ATOMIC_UMAX__VI                         0x00000047
#define SQ_FLAT_ATOMIC_UMAX_X2__VI                      0x00000067
#define SQ_FLAT_ATOMIC_UMIN__VI                         0x00000045
#define SQ_FLAT_ATOMIC_UMIN_X2__VI                      0x00000065
#define SQ_FLAT_ATOMIC_XOR__VI                          0x0000004a
#define SQ_FLAT_ATOMIC_XOR_X2__VI                       0x0000006a
#define SQ_FLAT_LOAD_DWORD__VI                          0x00000014
#define SQ_FLAT_LOAD_DWORDX2__VI                        0x00000015
#define SQ_FLAT_LOAD_DWORDX3__VI                        0x00000016
#define SQ_FLAT_LOAD_DWORDX4__VI                        0x00000017
#define SQ_FLAT_LOAD_SBYTE__VI                          0x00000011
#define SQ_FLAT_LOAD_SSHORT__VI                         0x00000013
#define SQ_FLAT_LOAD_UBYTE__VI                          0x00000010
#define SQ_FLAT_LOAD_USHORT__VI                         0x00000012
#define SQ_FLAT_SCRATCH_HI__VI                          0x00000067
#define SQ_FLAT_SCRATCH_LO__VI                          0x00000066
#define SQ_FLAT_STORE_DWORDX3__VI                       0x0000001e
#define SQ_FLAT_STORE_DWORDX4__VI                       0x0000001f
#define SQ_HW_REG_IB_DBG1__VI                           0x0000000d
#define SQ_IMAGE_ATOMIC_ADD__SI__CI                     0x00000011
#define SQ_IMAGE_ATOMIC_ADD__VI                         0x00000012
#define SQ_IMAGE_ATOMIC_CMPSWAP__SI__CI                 0x00000010
#define SQ_IMAGE_ATOMIC_CMPSWAP__VI                     0x00000011
#define SQ_IMAGE_ATOMIC_SUB__SI__CI                     0x00000012
#define SQ_IMAGE_ATOMIC_SUB__VI                         0x00000013
#define SQ_IMAGE_ATOMIC_SWAP__SI__CI                    0x0000000f
#define SQ_IMAGE_ATOMIC_SWAP__VI                        0x00000010
#define SQ_L1__VI                                       0x00000001
#define SQ_L10__VI                                      0x0000000a
#define SQ_L11__VI                                      0x0000000b
#define SQ_L12__VI                                      0x0000000c
#define SQ_L13__VI                                      0x0000000d
#define SQ_L14__VI                                      0x0000000e
#define SQ_L15__VI                                      0x0000000f
#define SQ_L2__VI                                       0x00000002
#define SQ_L3__VI                                       0x00000003
#define SQ_L4__VI                                       0x00000004
#define SQ_L5__VI                                       0x00000005
#define SQ_L6__VI                                       0x00000006
#define SQ_L7__VI                                       0x00000007
#define SQ_L8__VI                                       0x00000008
#define SQ_L9__VI                                       0x00000009
#define SQ_MSG_SAVEWAVE__VI                             0x00000004
#define SQ_NUM_SGPR__SI__CI                             0x00000068
#define SQ_NUM_SGPR__VI                                 0x00000066
#define SQ_R1__VI                                       0x00000001
#define SQ_R10__VI                                      0x0000000a
#define SQ_R11__VI                                      0x0000000b
#define SQ_R12__VI                                      0x0000000c
#define SQ_R13__VI                                      0x0000000d
#define SQ_R14__VI                                      0x0000000e
#define SQ_R15__VI                                      0x0000000f
#define SQ_R2__VI                                       0x00000002
#define SQ_R3__VI                                       0x00000003
#define SQ_R4__VI                                       0x00000004
#define SQ_R5__VI                                       0x00000005
#define SQ_R6__VI                                       0x00000006
#define SQ_R7__VI                                       0x00000007
#define SQ_R8__VI                                       0x00000008
#define SQ_R9__VI                                       0x00000009
#define SQ_SDWA_BYTE_0__VI                              0x00000000
#define SQ_SDWA_BYTE_1__VI                              0x00000001
#define SQ_SDWA_BYTE_2__VI                              0x00000002
#define SQ_SDWA_BYTE_3__VI                              0x00000003
#define SQ_SDWA_DWORD__VI                               0x00000006
#define SQ_SDWA_UNUSED_PAD__VI                          0x00000000
#define SQ_SDWA_UNUSED_PRESERVE__VI                     0x00000002
#define SQ_SDWA_UNUSED_SEXT__VI                         0x00000001
#define SQ_SDWA_WORD_0__VI                              0x00000004
#define SQ_SDWA_WORD_1__VI                              0x00000005
#define SQ_SRC_DPP__VI                                  0x000000fa
#define SQ_SRC_INV_2PI__VI                              0x000000f8
#define SQ_SRC_SDWA__VI                                 0x000000f9
#define SQ_S_ABSDIFF_I32__SI__CI                        0x0000002c
#define SQ_S_ABSDIFF_I32__VI                            0x0000002a
#define SQ_S_ABS_I32__SI__CI                            0x00000034
#define SQ_S_ABS_I32__VI                                0x00000030
#define SQ_S_ADDK_I32__SI__CI                           0x0000000f
#define SQ_S_ADDK_I32__VI                               0x0000000e
#define SQ_S_ANDN2_B32__SI__CI                          0x00000014
#define SQ_S_ANDN2_B32__VI                              0x00000012
#define SQ_S_ANDN2_B64__SI__CI                          0x00000015
#define SQ_S_ANDN2_B64__VI                              0x00000013
#define SQ_S_ANDN2_SAVEEXEC_B64__SI__CI                 0x00000027
#define SQ_S_ANDN2_SAVEEXEC_B64__VI                     0x00000023
#define SQ_S_AND_B32__SI__CI                            0x0000000e
#define SQ_S_AND_B32__VI                                0x0000000c
#define SQ_S_AND_B64__SI__CI                            0x0000000f
#define SQ_S_AND_B64__VI                                0x0000000d
#define SQ_S_AND_SAVEEXEC_B64__SI__CI                   0x00000024
#define SQ_S_AND_SAVEEXEC_B64__VI                       0x00000020
#define SQ_S_ASHR_I32__SI__CI                           0x00000022
#define SQ_S_ASHR_I32__VI                               0x00000020
#define SQ_S_ASHR_I64__SI__CI                           0x00000023
#define SQ_S_ASHR_I64__VI                               0x00000021
#define SQ_S_ATC_PROBE__VI                              0x00000026
#define SQ_S_ATC_PROBE_BUFFER__VI                       0x00000027
#define SQ_S_BCNT0_I32_B32__SI__CI                      0x0000000d
#define SQ_S_BCNT0_I32_B32__VI                          0x0000000a
#define SQ_S_BCNT0_I32_B64__SI__CI                      0x0000000e
#define SQ_S_BCNT0_I32_B64__VI                          0x0000000b
#define SQ_S_BCNT1_I32_B32__SI__CI                      0x0000000f
#define SQ_S_BCNT1_I32_B32__VI                          0x0000000c
#define SQ_S_BCNT1_I32_B64__SI__CI                      0x00000010
#define SQ_S_BCNT1_I32_B64__VI                          0x0000000d
#define SQ_S_BFE_I32__SI__CI                            0x00000028
#define SQ_S_BFE_I32__VI                                0x00000026
#define SQ_S_BFE_I64__SI__CI                            0x0000002a
#define SQ_S_BFE_I64__VI                                0x00000028
#define SQ_S_BFE_U32__SI__CI                            0x00000027
#define SQ_S_BFE_U32__VI                                0x00000025
#define SQ_S_BFE_U64__SI__CI                            0x00000029
#define SQ_S_BFE_U64__VI                                0x00000027
#define SQ_S_BFM_B32__SI__CI                            0x00000024
#define SQ_S_BFM_B32__VI                                0x00000022
#define SQ_S_BFM_B64__SI__CI                            0x00000025
#define SQ_S_BFM_B64__VI                                0x00000023
#define SQ_S_BITSET0_B32__SI__CI                        0x0000001b
#define SQ_S_BITSET0_B32__VI                            0x00000018
#define SQ_S_BITSET0_B64__SI__CI                        0x0000001c
#define SQ_S_BITSET0_B64__VI                            0x00000019
#define SQ_S_BITSET1_B32__SI__CI                        0x0000001d
#define SQ_S_BITSET1_B32__VI                            0x0000001a
#define SQ_S_BITSET1_B64__SI__CI                        0x0000001e
#define SQ_S_BITSET1_B64__VI                            0x0000001b
#define SQ_S_BREV_B32__SI__CI                           0x0000000b
#define SQ_S_BREV_B32__VI                               0x00000008
#define SQ_S_BREV_B64__SI__CI                           0x0000000c
#define SQ_S_BREV_B64__VI                               0x00000009
#define SQ_S_BUFFER_ATOMIC_ADD__VI                      0x00000042
#define SQ_S_BUFFER_ATOMIC_ADD_X2__VI                   0x00000062
#define SQ_S_BUFFER_ATOMIC_AND__VI                      0x00000048
#define SQ_S_BUFFER_ATOMIC_AND_X2__VI                   0x00000068
#define SQ_S_BUFFER_ATOMIC_CMPSWAP__VI                  0x00000041
#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2__VI               0x00000061
#define SQ_S_BUFFER_ATOMIC_DEC__VI                      0x0000004c
#define SQ_S_BUFFER_ATOMIC_DEC_X2__VI                   0x0000006c
#define SQ_S_BUFFER_ATOMIC_INC__VI                      0x0000004b
#define SQ_S_BUFFER_ATOMIC_INC_X2__VI                   0x0000006b
#define SQ_S_BUFFER_ATOMIC_OR__VI                       0x00000049
#define SQ_S_BUFFER_ATOMIC_OR_X2__VI                    0x00000069
#define SQ_S_BUFFER_ATOMIC_SMAX__VI                     0x00000046
#define SQ_S_BUFFER_ATOMIC_SMAX_X2__VI                  0x00000066
#define SQ_S_BUFFER_ATOMIC_SMIN__VI                     0x00000044
#define SQ_S_BUFFER_ATOMIC_SMIN_X2__VI                  0x00000064
#define SQ_S_BUFFER_ATOMIC_SUB__VI                      0x00000043
#define SQ_S_BUFFER_ATOMIC_SUB_X2__VI                   0x00000063
#define SQ_S_BUFFER_ATOMIC_SWAP__VI                     0x00000040
#define SQ_S_BUFFER_ATOMIC_SWAP_X2__VI                  0x00000060
#define SQ_S_BUFFER_ATOMIC_UMAX__VI                     0x00000047
#define SQ_S_BUFFER_ATOMIC_UMAX_X2__VI                  0x00000067
#define SQ_S_BUFFER_ATOMIC_UMIN__VI                     0x00000045
#define SQ_S_BUFFER_ATOMIC_UMIN_X2__VI                  0x00000065
#define SQ_S_BUFFER_ATOMIC_XOR__VI                      0x0000004a
#define SQ_S_BUFFER_ATOMIC_XOR_X2__VI                   0x0000006a
#define SQ_S_BUFFER_STORE_DWORD__VI                     0x00000018
#define SQ_S_BUFFER_STORE_DWORDX2__VI                   0x00000019
#define SQ_S_BUFFER_STORE_DWORDX4__VI                   0x0000001a
#define SQ_S_CBRANCH_G_FORK__SI__CI                     0x0000002b
#define SQ_S_CBRANCH_G_FORK__VI                         0x00000029
#define SQ_S_CBRANCH_I_FORK__SI__CI                     0x00000011
#define SQ_S_CBRANCH_I_FORK__VI                         0x00000010
#define SQ_S_CBRANCH_JOIN__SI__CI                       0x00000032
#define SQ_S_CBRANCH_JOIN__VI                           0x0000002e
#define SQ_S_CMOVK_I32__SI__CI                          0x00000002
#define SQ_S_CMOVK_I32__VI                              0x00000001
#define SQ_S_CMOV_B32__SI__CI                           0x00000005
#define SQ_S_CMOV_B32__VI                               0x00000002
#define SQ_S_CMOV_B64__SI__CI                           0x00000006
#define SQ_S_CMOV_B64__VI                               0x00000003
#define SQ_S_CMPK_EQ_I32__SI__CI                        0x00000003
#define SQ_S_CMPK_EQ_I32__VI                            0x00000002
#define SQ_S_CMPK_EQ_U32__SI__CI                        0x00000009
#define SQ_S_CMPK_EQ_U32__VI                            0x00000008
#define SQ_S_CMPK_GE_I32__SI__CI                        0x00000006
#define SQ_S_CMPK_GE_I32__VI                            0x00000005
#define SQ_S_CMPK_GE_U32__SI__CI                        0x0000000c
#define SQ_S_CMPK_GE_U32__VI                            0x0000000b
#define SQ_S_CMPK_GT_I32__SI__CI                        0x00000005
#define SQ_S_CMPK_GT_I32__VI                            0x00000004
#define SQ_S_CMPK_GT_U32__SI__CI                        0x0000000b
#define SQ_S_CMPK_GT_U32__VI                            0x0000000a
#define SQ_S_CMPK_LE_I32__SI__CI                        0x00000008
#define SQ_S_CMPK_LE_I32__VI                            0x00000007
#define SQ_S_CMPK_LE_U32__SI__CI                        0x0000000e
#define SQ_S_CMPK_LE_U32__VI                            0x0000000d
#define SQ_S_CMPK_LG_I32__SI__CI                        0x00000004
#define SQ_S_CMPK_LG_I32__VI                            0x00000003
#define SQ_S_CMPK_LG_U32__SI__CI                        0x0000000a
#define SQ_S_CMPK_LG_U32__VI                            0x00000009
#define SQ_S_CMPK_LT_I32__SI__CI                        0x00000007
#define SQ_S_CMPK_LT_I32__VI                            0x00000006
#define SQ_S_CMPK_LT_U32__SI__CI                        0x0000000d
#define SQ_S_CMPK_LT_U32__VI                            0x0000000c
#define SQ_S_CMP_EQ_U64__VI                             0x00000012
#define SQ_S_CMP_LG_U64__VI                             0x00000013
#define SQ_S_DCACHE_INV__SI__CI                         0x0000001f
#define SQ_S_DCACHE_INV__VI                             0x00000020
#define SQ_S_DCACHE_INV_VOL__VI                         0x00000022
#define SQ_S_DCACHE_WB__VI                              0x00000021
#define SQ_S_DCACHE_WB_VOL__VI                          0x00000023
#define SQ_S_ENDPGM_SAVED__VI                           0x0000001b
#define SQ_S_FF0_I32_B32__SI__CI                        0x00000011
#define SQ_S_FF0_I32_B32__VI                            0x0000000e
#define SQ_S_FF0_I32_B64__SI__CI                        0x00000012
#define SQ_S_FF0_I32_B64__VI                            0x0000000f
#define SQ_S_FF1_I32_B32__SI__CI                        0x00000013
#define SQ_S_FF1_I32_B32__VI                            0x00000010
#define SQ_S_FF1_I32_B64__SI__CI                        0x00000014
#define SQ_S_FF1_I32_B64__VI                            0x00000011
#define SQ_S_FLBIT_I32__SI__CI                          0x00000017
#define SQ_S_FLBIT_I32__VI                              0x00000014
#define SQ_S_FLBIT_I32_B32__SI__CI                      0x00000015
#define SQ_S_FLBIT_I32_B32__VI                          0x00000012
#define SQ_S_FLBIT_I32_B64__SI__CI                      0x00000016
#define SQ_S_FLBIT_I32_B64__VI                          0x00000013
#define SQ_S_FLBIT_I32_I64__SI__CI                      0x00000018
#define SQ_S_FLBIT_I32_I64__VI                          0x00000015
#define SQ_S_GETPC_B64__SI__CI                          0x0000001f
#define SQ_S_GETPC_B64__VI                              0x0000001c
#define SQ_S_GETREG_B32__SI__CI                         0x00000012
#define SQ_S_GETREG_B32__VI                             0x00000011
#define SQ_S_GETREG_REGRD_B32__SI__CI                   0x00000014
#define SQ_S_GETREG_REGRD_B32__VI                       0x00000013
#define SQ_S_LSHL_B32__SI__CI                           0x0000001e
#define SQ_S_LSHL_B32__VI                               0x0000001c
#define SQ_S_LSHL_B64__SI__CI                           0x0000001f
#define SQ_S_LSHL_B64__VI                               0x0000001d
#define SQ_S_LSHR_B32__SI__CI                           0x00000020
#define SQ_S_LSHR_B32__VI                               0x0000001e
#define SQ_S_LSHR_B64__SI__CI                           0x00000021
#define SQ_S_LSHR_B64__VI                               0x0000001f
#define SQ_S_MEMREALTIME__VI                            0x00000025
#define SQ_S_MEMTIME__SI__CI                            0x0000001e
#define SQ_S_MEMTIME__VI                                0x00000024
#define SQ_S_MOVRELD_B32__SI__CI                        0x00000030
#define SQ_S_MOVRELD_B32__VI                            0x0000002c
#define SQ_S_MOVRELD_B64__SI__CI                        0x00000031
#define SQ_S_MOVRELD_B64__VI                            0x0000002d
#define SQ_S_MOVRELS_B32__SI__CI                        0x0000002e
#define SQ_S_MOVRELS_B32__VI                            0x0000002a
#define SQ_S_MOVRELS_B64__SI__CI                        0x0000002f
#define SQ_S_MOVRELS_B64__VI                            0x0000002b
#define SQ_S_MOV_B32__SI__CI                            0x00000003
#define SQ_S_MOV_B32__VI                                0x00000000
#define SQ_S_MOV_B64__SI__CI                            0x00000004
#define SQ_S_MOV_B64__VI                                0x00000001
#define SQ_S_MOV_FED_B32__SI__CI                        0x00000035
#define SQ_S_MOV_FED_B32__VI                            0x00000031
#define SQ_S_MOV_REGRD_B32__SI__CI                      0x00000033
#define SQ_S_MOV_REGRD_B32__VI                          0x0000002f
#define SQ_S_MULK_I32__SI__CI                           0x00000010
#define SQ_S_MULK_I32__VI                               0x0000000f
#define SQ_S_MUL_I32__SI__CI                            0x00000026
#define SQ_S_MUL_I32__VI                                0x00000024
#define SQ_S_NAND_B32__SI__CI                           0x00000018
#define SQ_S_NAND_B32__VI                               0x00000016
#define SQ_S_NAND_B64__SI__CI                           0x00000019
#define SQ_S_NAND_B64__VI                               0x00000017
#define SQ_S_NAND_SAVEEXEC_B64__SI__CI                  0x00000029
#define SQ_S_NAND_SAVEEXEC_B64__VI                      0x00000025
#define SQ_S_NOR_B32__SI__CI                            0x0000001a
#define SQ_S_NOR_B32__VI                                0x00000018
#define SQ_S_NOR_B64__SI__CI                            0x0000001b
#define SQ_S_NOR_B64__VI                                0x00000019
#define SQ_S_NOR_SAVEEXEC_B64__SI__CI                   0x0000002a
#define SQ_S_NOR_SAVEEXEC_B64__VI                       0x00000026
#define SQ_S_NOT_B32__SI__CI                            0x00000007
#define SQ_S_NOT_B32__VI                                0x00000004
#define SQ_S_NOT_B64__SI__CI                            0x00000008
#define SQ_S_NOT_B64__VI                                0x00000005
#define SQ_S_ORN2_B32__SI__CI                           0x00000016
#define SQ_S_ORN2_B32__VI                               0x00000014
#define SQ_S_ORN2_B64__SI__CI                           0x00000017
#define SQ_S_ORN2_B64__VI                               0x00000015
#define SQ_S_ORN2_SAVEEXEC_B64__SI__CI                  0x00000028
#define SQ_S_ORN2_SAVEEXEC_B64__VI                      0x00000024
#define SQ_S_OR_B32__SI__CI                             0x00000010
#define SQ_S_OR_B32__VI                                 0x0000000e
#define SQ_S_OR_B64__SI__CI                             0x00000011
#define SQ_S_OR_B64__VI                                 0x0000000f
#define SQ_S_OR_SAVEEXEC_B64__SI__CI                    0x00000025
#define SQ_S_OR_SAVEEXEC_B64__VI                        0x00000021
#define SQ_S_QUADMASK_B32__SI__CI                       0x0000002c
#define SQ_S_QUADMASK_B32__VI                           0x00000028
#define SQ_S_QUADMASK_B64__SI__CI                       0x0000002d
#define SQ_S_QUADMASK_B64__VI                           0x00000029
#define SQ_S_RFE_B64__SI__CI                            0x00000022
#define SQ_S_RFE_B64__VI                                0x0000001f
#define SQ_S_RFE_RESTORE_B64__VI                        0x0000002b
#define SQ_S_SETPC_B64__SI__CI                          0x00000020
#define SQ_S_SETPC_B64__VI                              0x0000001d
#define SQ_S_SETREG_B32__SI__CI                         0x00000013
#define SQ_S_SETREG_B32__VI                             0x00000012
#define SQ_S_SETREG_IMM32_B32__SI__CI                   0x00000015
#define SQ_S_SETREG_IMM32_B32__VI                       0x00000014
#define SQ_S_SET_GPR_IDX_IDX__VI                        0x00000032
#define SQ_S_SET_GPR_IDX_MODE__VI                       0x0000001d
#define SQ_S_SET_GPR_IDX_OFF__VI                        0x0000001c
#define SQ_S_SET_GPR_IDX_ON__VI                         0x00000011
#define SQ_S_SEXT_I32_I16__SI__CI                       0x0000001a
#define SQ_S_SEXT_I32_I16__VI                           0x00000017
#define SQ_S_SEXT_I32_I8__SI__CI                        0x00000019
#define SQ_S_SEXT_I32_I8__VI                            0x00000016
#define SQ_S_STORE_DWORD__VI                            0x00000010
#define SQ_S_STORE_DWORDX2__VI                          0x00000011
#define SQ_S_STORE_DWORDX4__VI                          0x00000012
#define SQ_S_SWAPPC_B64__SI__CI                         0x00000021
#define SQ_S_SWAPPC_B64__VI                             0x0000001e
#define SQ_S_WAKEUP__VI                                 0x00000003
#define SQ_S_WQM_B32__SI__CI                            0x00000009
#define SQ_S_WQM_B32__VI                                0x00000006
#define SQ_S_WQM_B64__SI__CI                            0x0000000a
#define SQ_S_WQM_B64__VI                                0x00000007
#define SQ_S_XNOR_B32__SI__CI                           0x0000001c
#define SQ_S_XNOR_B32__VI                               0x0000001a
#define SQ_S_XNOR_B64__SI__CI                           0x0000001d
#define SQ_S_XNOR_B64__VI                               0x0000001b
#define SQ_S_XNOR_SAVEEXEC_B64__SI__CI                  0x0000002b
#define SQ_S_XNOR_SAVEEXEC_B64__VI                      0x00000027
#define SQ_S_XOR_B32__SI__CI                            0x00000012
#define SQ_S_XOR_B32__VI                                0x00000010
#define SQ_S_XOR_B64__SI__CI                            0x00000013
#define SQ_S_XOR_B64__VI                                0x00000011
#define SQ_S_XOR_SAVEEXEC_B64__SI__CI                   0x00000026
#define SQ_S_XOR_SAVEEXEC_B64__VI                       0x00000022
#define SQ_TBUFFER_LOAD_FORMAT_D16_X__VI                0x00000008
#define SQ_TBUFFER_LOAD_FORMAT_D16_XY__VI               0x00000009
#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ__VI              0x0000000a
#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW__VI             0x0000000b
#define SQ_TBUFFER_STORE_FORMAT_D16_X__VI               0x0000000c
#define SQ_TBUFFER_STORE_FORMAT_D16_XY__VI              0x0000000d
#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ__VI             0x0000000e
#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW__VI            0x0000000f
#define SQ_V_ADDC_U32__SI__CI                           0x00000028
#define SQ_V_ADDC_U32__VI                               0x0000001c
#define SQ_V_ADD_F16__VI                                0x0000001f
#define SQ_V_ADD_F32__SI__CI                            0x00000003
#define SQ_V_ADD_F32__VI                                0x00000001
#define SQ_V_ADD_F64__SI__CI                            0x00000164
#define SQ_V_ADD_F64__VI                                0x00000280
#define SQ_V_ADD_U16__VI                                0x00000026
#define SQ_V_ADD_U32__VI                                0x00000019
#define SQ_V_ALIGNBIT_B32__SI__CI                       0x0000014e
#define SQ_V_ALIGNBIT_B32__VI                           0x000001ce
#define SQ_V_ALIGNBYTE_B32__SI__CI                      0x0000014f
#define SQ_V_ALIGNBYTE_B32__VI                          0x000001cf
#define SQ_V_AND_B32__SI__CI                            0x0000001b
#define SQ_V_AND_B32__VI                                0x00000013
#define SQ_V_ASHRREV_I16__VI                            0x0000002c
#define SQ_V_ASHRREV_I32__SI__CI                        0x00000018
#define SQ_V_ASHRREV_I32__VI                            0x00000011
#define SQ_V_ASHRREV_I64__VI                            0x00000291
#define SQ_V_BCNT_U32_B32__SI__CI                       0x00000022
#define SQ_V_BCNT_U32_B32__VI                           0x0000028b
#define SQ_V_BFE_I32__SI__CI                            0x00000149
#define SQ_V_BFE_I32__VI                                0x000001c9
#define SQ_V_BFE_U32__SI__CI                            0x00000148
#define SQ_V_BFE_U32__VI                                0x000001c8
#define SQ_V_BFI_B32__SI__CI                            0x0000014a
#define SQ_V_BFI_B32__VI                                0x000001ca
#define SQ_V_BFM_B32__SI__CI                            0x0000001e
#define SQ_V_BFM_B32__VI                                0x00000293
#define SQ_V_BFREV_B32__SI__CI                          0x00000038
#define SQ_V_BFREV_B32__VI                              0x0000002c
#define SQ_V_CEIL_F16__VI                               0x00000045
#define SQ_V_CEIL_F32__SI__CI                           0x00000022
#define SQ_V_CEIL_F32__VI                               0x0000001d
#define SQ_V_CLREXCP__SI__CI                            0x00000041
#define SQ_V_CLREXCP__VI                                0x00000035
#define SQ_V_CMPX_CLASS_F16__VI                         0x00000015
#define SQ_V_CMPX_CLASS_F32__SI__CI                     0x00000098
#define SQ_V_CMPX_CLASS_F32__VI                         0x00000011
#define SQ_V_CMPX_CLASS_F64__SI__CI                     0x000000b8
#define SQ_V_CMPX_CLASS_F64__VI                         0x00000013
#define SQ_V_CMPX_EQ_F16__VI                            0x00000032
#define SQ_V_CMPX_EQ_F32__SI__CI                        0x00000012
#define SQ_V_CMPX_EQ_F32__VI                            0x00000052
#define SQ_V_CMPX_EQ_F64__SI__CI                        0x00000032
#define SQ_V_CMPX_EQ_F64__VI                            0x00000072
#define SQ_V_CMPX_EQ_I16__VI                            0x000000b2
#define SQ_V_CMPX_EQ_I32__SI__CI                        0x00000092
#define SQ_V_CMPX_EQ_I32__VI                            0x000000d2
#define SQ_V_CMPX_EQ_I64__SI__CI                        0x000000b2
#define SQ_V_CMPX_EQ_I64__VI                            0x000000f2
#define SQ_V_CMPX_EQ_U16__VI                            0x000000ba
#define SQ_V_CMPX_EQ_U32__SI__CI                        0x000000d2
#define SQ_V_CMPX_EQ_U32__VI                            0x000000da
#define SQ_V_CMPX_EQ_U64__SI__CI                        0x000000f2
#define SQ_V_CMPX_EQ_U64__VI                            0x000000fa
#define SQ_V_CMPX_F_F16__VI                             0x00000030
#define SQ_V_CMPX_F_F32__SI__CI                         0x00000010
#define SQ_V_CMPX_F_F32__VI                             0x00000050
#define SQ_V_CMPX_F_F64__SI__CI                         0x00000030
#define SQ_V_CMPX_F_F64__VI                             0x00000070
#define SQ_V_CMPX_F_I16__VI                             0x000000b0
#define SQ_V_CMPX_F_I32__SI__CI                         0x00000090
#define SQ_V_CMPX_F_I32__VI                             0x000000d0
#define SQ_V_CMPX_F_I64__SI__CI                         0x000000b0
#define SQ_V_CMPX_F_I64__VI                             0x000000f0
#define SQ_V_CMPX_F_U16__VI                             0x000000b8
#define SQ_V_CMPX_F_U32__SI__CI                         0x000000d0
#define SQ_V_CMPX_F_U32__VI                             0x000000d8
#define SQ_V_CMPX_F_U64__SI__CI                         0x000000f0
#define SQ_V_CMPX_F_U64__VI                             0x000000f8
#define SQ_V_CMPX_GE_F16__VI                            0x00000036
#define SQ_V_CMPX_GE_F32__SI__CI                        0x00000016
#define SQ_V_CMPX_GE_F32__VI                            0x00000056
#define SQ_V_CMPX_GE_F64__SI__CI                        0x00000036
#define SQ_V_CMPX_GE_F64__VI                            0x00000076
#define SQ_V_CMPX_GE_I16__VI                            0x000000b6
#define SQ_V_CMPX_GE_I32__SI__CI                        0x00000096
#define SQ_V_CMPX_GE_I32__VI                            0x000000d6
#define SQ_V_CMPX_GE_I64__SI__CI                        0x000000b6
#define SQ_V_CMPX_GE_I64__VI                            0x000000f6
#define SQ_V_CMPX_GE_U16__VI                            0x000000be
#define SQ_V_CMPX_GE_U32__SI__CI                        0x000000d6
#define SQ_V_CMPX_GE_U32__VI                            0x000000de
#define SQ_V_CMPX_GE_U64__SI__CI                        0x000000f6
#define SQ_V_CMPX_GE_U64__VI                            0x000000fe
#define SQ_V_CMPX_GT_F16__VI                            0x00000034
#define SQ_V_CMPX_GT_F32__SI__CI                        0x00000014
#define SQ_V_CMPX_GT_F32__VI                            0x00000054
#define SQ_V_CMPX_GT_F64__SI__CI                        0x00000034
#define SQ_V_CMPX_GT_F64__VI                            0x00000074
#define SQ_V_CMPX_GT_I16__VI                            0x000000b4
#define SQ_V_CMPX_GT_I32__SI__CI                        0x00000094
#define SQ_V_CMPX_GT_I32__VI                            0x000000d4
#define SQ_V_CMPX_GT_I64__SI__CI                        0x000000b4
#define SQ_V_CMPX_GT_I64__VI                            0x000000f4
#define SQ_V_CMPX_GT_U16__VI                            0x000000bc
#define SQ_V_CMPX_GT_U32__SI__CI                        0x000000d4
#define SQ_V_CMPX_GT_U32__VI                            0x000000dc
#define SQ_V_CMPX_GT_U64__SI__CI                        0x000000f4
#define SQ_V_CMPX_GT_U64__VI                            0x000000fc
#define SQ_V_CMPX_LE_F16__VI                            0x00000033
#define SQ_V_CMPX_LE_F32__SI__CI                        0x00000013
#define SQ_V_CMPX_LE_F32__VI                            0x00000053
#define SQ_V_CMPX_LE_F64__SI__CI                        0x00000033
#define SQ_V_CMPX_LE_F64__VI                            0x00000073
#define SQ_V_CMPX_LE_I16__VI                            0x000000b3
#define SQ_V_CMPX_LE_I32__SI__CI                        0x00000093
#define SQ_V_CMPX_LE_I32__VI                            0x000000d3
#define SQ_V_CMPX_LE_I64__SI__CI                        0x000000b3
#define SQ_V_CMPX_LE_I64__VI                            0x000000f3
#define SQ_V_CMPX_LE_U16__VI                            0x000000bb
#define SQ_V_CMPX_LE_U32__SI__CI                        0x000000d3
#define SQ_V_CMPX_LE_U32__VI                            0x000000db
#define SQ_V_CMPX_LE_U64__SI__CI                        0x000000f3
#define SQ_V_CMPX_LE_U64__VI                            0x000000fb
#define SQ_V_CMPX_LG_F16__VI                            0x00000035
#define SQ_V_CMPX_LG_F32__SI__CI                        0x00000015
#define SQ_V_CMPX_LG_F32__VI                            0x00000055
#define SQ_V_CMPX_LG_F64__SI__CI                        0x00000035
#define SQ_V_CMPX_LG_F64__VI                            0x00000075
#define SQ_V_CMPX_LT_F16__VI                            0x00000031
#define SQ_V_CMPX_LT_F32__SI__CI                        0x00000011
#define SQ_V_CMPX_LT_F32__VI                            0x00000051
#define SQ_V_CMPX_LT_F64__SI__CI                        0x00000031
#define SQ_V_CMPX_LT_F64__VI                            0x00000071
#define SQ_V_CMPX_LT_I16__VI                            0x000000b1
#define SQ_V_CMPX_LT_I32__SI__CI                        0x00000091
#define SQ_V_CMPX_LT_I32__VI                            0x000000d1
#define SQ_V_CMPX_LT_I64__SI__CI                        0x000000b1
#define SQ_V_CMPX_LT_I64__VI                            0x000000f1
#define SQ_V_CMPX_LT_U16__VI                            0x000000b9
#define SQ_V_CMPX_LT_U32__SI__CI                        0x000000d1
#define SQ_V_CMPX_LT_U32__VI                            0x000000d9
#define SQ_V_CMPX_LT_U64__SI__CI                        0x000000f1
#define SQ_V_CMPX_LT_U64__VI                            0x000000f9
#define SQ_V_CMPX_NEQ_F16__VI                           0x0000003d
#define SQ_V_CMPX_NEQ_F32__SI__CI                       0x0000001d
#define SQ_V_CMPX_NEQ_F32__VI                           0x0000005d
#define SQ_V_CMPX_NEQ_F64__SI__CI                       0x0000003d
#define SQ_V_CMPX_NEQ_F64__VI                           0x0000007d
#define SQ_V_CMPX_NE_I16__VI                            0x000000b5
#define SQ_V_CMPX_NE_I32__SI__CI                        0x00000095
#define SQ_V_CMPX_NE_I32__VI                            0x000000d5
#define SQ_V_CMPX_NE_I64__SI__CI                        0x000000b5
#define SQ_V_CMPX_NE_I64__VI                            0x000000f5
#define SQ_V_CMPX_NE_U16__VI                            0x000000bd
#define SQ_V_CMPX_NE_U32__SI__CI                        0x000000d5
#define SQ_V_CMPX_NE_U32__VI                            0x000000dd
#define SQ_V_CMPX_NE_U64__SI__CI                        0x000000f5
#define SQ_V_CMPX_NE_U64__VI                            0x000000fd
#define SQ_V_CMPX_NGE_F16__VI                           0x00000039
#define SQ_V_CMPX_NGE_F32__SI__CI                       0x00000019
#define SQ_V_CMPX_NGE_F32__VI                           0x00000059
#define SQ_V_CMPX_NGE_F64__SI__CI                       0x00000039
#define SQ_V_CMPX_NGE_F64__VI                           0x00000079
#define SQ_V_CMPX_NGT_F16__VI                           0x0000003b
#define SQ_V_CMPX_NGT_F32__SI__CI                       0x0000001b
#define SQ_V_CMPX_NGT_F32__VI                           0x0000005b
#define SQ_V_CMPX_NGT_F64__SI__CI                       0x0000003b
#define SQ_V_CMPX_NGT_F64__VI                           0x0000007b
#define SQ_V_CMPX_NLE_F16__VI                           0x0000003c
#define SQ_V_CMPX_NLE_F32__SI__CI                       0x0000001c
#define SQ_V_CMPX_NLE_F32__VI                           0x0000005c
#define SQ_V_CMPX_NLE_F64__SI__CI                       0x0000003c
#define SQ_V_CMPX_NLE_F64__VI                           0x0000007c
#define SQ_V_CMPX_NLG_F16__VI                           0x0000003a
#define SQ_V_CMPX_NLG_F32__SI__CI                       0x0000001a
#define SQ_V_CMPX_NLG_F32__VI                           0x0000005a
#define SQ_V_CMPX_NLG_F64__SI__CI                       0x0000003a
#define SQ_V_CMPX_NLG_F64__VI                           0x0000007a
#define SQ_V_CMPX_NLT_F16__VI                           0x0000003e
#define SQ_V_CMPX_NLT_F32__SI__CI                       0x0000001e
#define SQ_V_CMPX_NLT_F32__VI                           0x0000005e
#define SQ_V_CMPX_NLT_F64__SI__CI                       0x0000003e
#define SQ_V_CMPX_NLT_F64__VI                           0x0000007e
#define SQ_V_CMPX_O_F16__VI                             0x00000037
#define SQ_V_CMPX_O_F32__SI__CI                         0x00000017
#define SQ_V_CMPX_O_F32__VI                             0x00000057
#define SQ_V_CMPX_O_F64__SI__CI                         0x00000037
#define SQ_V_CMPX_O_F64__VI                             0x00000077
#define SQ_V_CMPX_TRU_F16__VI                           0x0000003f
#define SQ_V_CMPX_TRU_F32__SI__CI                       0x0000001f
#define SQ_V_CMPX_TRU_F32__VI                           0x0000005f
#define SQ_V_CMPX_TRU_F64__SI__CI                       0x0000003f
#define SQ_V_CMPX_TRU_F64__VI                           0x0000007f
#define SQ_V_CMPX_T_I16__VI                             0x000000b7
#define SQ_V_CMPX_T_I32__SI__CI                         0x00000097
#define SQ_V_CMPX_T_I32__VI                             0x000000d7
#define SQ_V_CMPX_T_I64__SI__CI                         0x000000b7
#define SQ_V_CMPX_T_I64__VI                             0x000000f7
#define SQ_V_CMPX_T_U16__VI                             0x000000bf
#define SQ_V_CMPX_T_U32__SI__CI                         0x000000d7
#define SQ_V_CMPX_T_U32__VI                             0x000000df
#define SQ_V_CMPX_T_U64__SI__CI                         0x000000f7
#define SQ_V_CMPX_T_U64__VI                             0x000000ff
#define SQ_V_CMPX_U_F16__VI                             0x00000038
#define SQ_V_CMPX_U_F32__SI__CI                         0x00000018
#define SQ_V_CMPX_U_F32__VI                             0x00000058
#define SQ_V_CMPX_U_F64__SI__CI                         0x00000038
#define SQ_V_CMPX_U_F64__VI                             0x00000078
#define SQ_V_CMP_CLASS_F16__VI                          0x00000014
#define SQ_V_CMP_CLASS_F32__SI__CI                      0x00000088
#define SQ_V_CMP_CLASS_F32__VI                          0x00000010
#define SQ_V_CMP_CLASS_F64__SI__CI                      0x000000a8
#define SQ_V_CMP_CLASS_F64__VI                          0x00000012
#define SQ_V_CMP_EQ_F16__VI                             0x00000022
#define SQ_V_CMP_EQ_F32__SI__CI                         0x00000002
#define SQ_V_CMP_EQ_F32__VI                             0x00000042
#define SQ_V_CMP_EQ_F64__SI__CI                         0x00000022
#define SQ_V_CMP_EQ_F64__VI                             0x00000062
#define SQ_V_CMP_EQ_I16__VI                             0x000000a2
#define SQ_V_CMP_EQ_I32__SI__CI                         0x00000082
#define SQ_V_CMP_EQ_I32__VI                             0x000000c2
#define SQ_V_CMP_EQ_I64__SI__CI                         0x000000a2
#define SQ_V_CMP_EQ_I64__VI                             0x000000e2
#define SQ_V_CMP_EQ_U16__VI                             0x000000aa
#define SQ_V_CMP_EQ_U32__SI__CI                         0x000000c2
#define SQ_V_CMP_EQ_U32__VI                             0x000000ca
#define SQ_V_CMP_EQ_U64__SI__CI                         0x000000e2
#define SQ_V_CMP_EQ_U64__VI                             0x000000ea
#define SQ_V_CMP_F_F16__VI                              0x00000020
#define SQ_V_CMP_F_F32__SI__CI                          0x00000000
#define SQ_V_CMP_F_F32__VI                              0x00000040
#define SQ_V_CMP_F_F64__SI__CI                          0x00000020
#define SQ_V_CMP_F_F64__VI                              0x00000060
#define SQ_V_CMP_F_I16__VI                              0x000000a0
#define SQ_V_CMP_F_I32__SI__CI                          0x00000080
#define SQ_V_CMP_F_I32__VI                              0x000000c0
#define SQ_V_CMP_F_I64__SI__CI                          0x000000a0
#define SQ_V_CMP_F_I64__VI                              0x000000e0
#define SQ_V_CMP_F_U16__VI                              0x000000a8
#define SQ_V_CMP_F_U32__SI__CI                          0x000000c0
#define SQ_V_CMP_F_U32__VI                              0x000000c8
#define SQ_V_CMP_F_U64__SI__CI                          0x000000e0
#define SQ_V_CMP_F_U64__VI                              0x000000e8
#define SQ_V_CMP_GE_F16__VI                             0x00000026
#define SQ_V_CMP_GE_F32__SI__CI                         0x00000006
#define SQ_V_CMP_GE_F32__VI                             0x00000046
#define SQ_V_CMP_GE_F64__SI__CI                         0x00000026
#define SQ_V_CMP_GE_F64__VI                             0x00000066
#define SQ_V_CMP_GE_I16__VI                             0x000000a6
#define SQ_V_CMP_GE_I32__SI__CI                         0x00000086
#define SQ_V_CMP_GE_I32__VI                             0x000000c6
#define SQ_V_CMP_GE_I64__SI__CI                         0x000000a6
#define SQ_V_CMP_GE_I64__VI                             0x000000e6
#define SQ_V_CMP_GE_U16__VI                             0x000000ae
#define SQ_V_CMP_GE_U32__SI__CI                         0x000000c6
#define SQ_V_CMP_GE_U32__VI                             0x000000ce
#define SQ_V_CMP_GE_U64__SI__CI                         0x000000e6
#define SQ_V_CMP_GE_U64__VI                             0x000000ee
#define SQ_V_CMP_GT_F16__VI                             0x00000024
#define SQ_V_CMP_GT_F32__SI__CI                         0x00000004
#define SQ_V_CMP_GT_F32__VI                             0x00000044
#define SQ_V_CMP_GT_F64__SI__CI                         0x00000024
#define SQ_V_CMP_GT_F64__VI                             0x00000064
#define SQ_V_CMP_GT_I16__VI                             0x000000a4
#define SQ_V_CMP_GT_I32__SI__CI                         0x00000084
#define SQ_V_CMP_GT_I32__VI                             0x000000c4
#define SQ_V_CMP_GT_I64__SI__CI                         0x000000a4
#define SQ_V_CMP_GT_I64__VI                             0x000000e4
#define SQ_V_CMP_GT_U16__VI                             0x000000ac
#define SQ_V_CMP_GT_U32__SI__CI                         0x000000c4
#define SQ_V_CMP_GT_U32__VI                             0x000000cc
#define SQ_V_CMP_GT_U64__SI__CI                         0x000000e4
#define SQ_V_CMP_GT_U64__VI                             0x000000ec
#define SQ_V_CMP_LE_F16__VI                             0x00000023
#define SQ_V_CMP_LE_F32__SI__CI                         0x00000003
#define SQ_V_CMP_LE_F32__VI                             0x00000043
#define SQ_V_CMP_LE_F64__SI__CI                         0x00000023
#define SQ_V_CMP_LE_F64__VI                             0x00000063
#define SQ_V_CMP_LE_I16__VI                             0x000000a3
#define SQ_V_CMP_LE_I32__SI__CI                         0x00000083
#define SQ_V_CMP_LE_I32__VI                             0x000000c3
#define SQ_V_CMP_LE_I64__SI__CI                         0x000000a3
#define SQ_V_CMP_LE_I64__VI                             0x000000e3
#define SQ_V_CMP_LE_U16__VI                             0x000000ab
#define SQ_V_CMP_LE_U32__SI__CI                         0x000000c3
#define SQ_V_CMP_LE_U32__VI                             0x000000cb
#define SQ_V_CMP_LE_U64__SI__CI                         0x000000e3
#define SQ_V_CMP_LE_U64__VI                             0x000000eb
#define SQ_V_CMP_LG_F16__VI                             0x00000025
#define SQ_V_CMP_LG_F32__SI__CI                         0x00000005
#define SQ_V_CMP_LG_F32__VI                             0x00000045
#define SQ_V_CMP_LG_F64__SI__CI                         0x00000025
#define SQ_V_CMP_LG_F64__VI                             0x00000065
#define SQ_V_CMP_LT_F16__VI                             0x00000021
#define SQ_V_CMP_LT_F32__SI__CI                         0x00000001
#define SQ_V_CMP_LT_F32__VI                             0x00000041
#define SQ_V_CMP_LT_F64__SI__CI                         0x00000021
#define SQ_V_CMP_LT_F64__VI                             0x00000061
#define SQ_V_CMP_LT_I16__VI                             0x000000a1
#define SQ_V_CMP_LT_I32__SI__CI                         0x00000081
#define SQ_V_CMP_LT_I32__VI                             0x000000c1
#define SQ_V_CMP_LT_I64__SI__CI                         0x000000a1
#define SQ_V_CMP_LT_I64__VI                             0x000000e1
#define SQ_V_CMP_LT_U16__VI                             0x000000a9
#define SQ_V_CMP_LT_U32__SI__CI                         0x000000c1
#define SQ_V_CMP_LT_U32__VI                             0x000000c9
#define SQ_V_CMP_LT_U64__SI__CI                         0x000000e1
#define SQ_V_CMP_LT_U64__VI                             0x000000e9
#define SQ_V_CMP_NEQ_F16__VI                            0x0000002d
#define SQ_V_CMP_NEQ_F32__SI__CI                        0x0000000d
#define SQ_V_CMP_NEQ_F32__VI                            0x0000004d
#define SQ_V_CMP_NEQ_F64__SI__CI                        0x0000002d
#define SQ_V_CMP_NEQ_F64__VI                            0x0000006d
#define SQ_V_CMP_NE_I16__VI                             0x000000a5
#define SQ_V_CMP_NE_I32__SI__CI                         0x00000085
#define SQ_V_CMP_NE_I32__VI                             0x000000c5
#define SQ_V_CMP_NE_I64__SI__CI                         0x000000a5
#define SQ_V_CMP_NE_I64__VI                             0x000000e5
#define SQ_V_CMP_NE_U16__VI                             0x000000ad
#define SQ_V_CMP_NE_U32__SI__CI                         0x000000c5
#define SQ_V_CMP_NE_U32__VI                             0x000000cd
#define SQ_V_CMP_NE_U64__SI__CI                         0x000000e5
#define SQ_V_CMP_NE_U64__VI                             0x000000ed
#define SQ_V_CMP_NGE_F16__VI                            0x00000029
#define SQ_V_CMP_NGE_F32__SI__CI                        0x00000009
#define SQ_V_CMP_NGE_F32__VI                            0x00000049
#define SQ_V_CMP_NGE_F64__SI__CI                        0x00000029
#define SQ_V_CMP_NGE_F64__VI                            0x00000069
#define SQ_V_CMP_NGT_F16__VI                            0x0000002b
#define SQ_V_CMP_NGT_F32__SI__CI                        0x0000000b
#define SQ_V_CMP_NGT_F32__VI                            0x0000004b
#define SQ_V_CMP_NGT_F64__SI__CI                        0x0000002b
#define SQ_V_CMP_NGT_F64__VI                            0x0000006b
#define SQ_V_CMP_NLE_F16__VI                            0x0000002c
#define SQ_V_CMP_NLE_F32__SI__CI                        0x0000000c
#define SQ_V_CMP_NLE_F32__VI                            0x0000004c
#define SQ_V_CMP_NLE_F64__SI__CI                        0x0000002c
#define SQ_V_CMP_NLE_F64__VI                            0x0000006c
#define SQ_V_CMP_NLG_F16__VI                            0x0000002a
#define SQ_V_CMP_NLG_F32__SI__CI                        0x0000000a
#define SQ_V_CMP_NLG_F32__VI                            0x0000004a
#define SQ_V_CMP_NLG_F64__SI__CI                        0x0000002a
#define SQ_V_CMP_NLG_F64__VI                            0x0000006a
#define SQ_V_CMP_NLT_F16__VI                            0x0000002e
#define SQ_V_CMP_NLT_F32__SI__CI                        0x0000000e
#define SQ_V_CMP_NLT_F32__VI                            0x0000004e
#define SQ_V_CMP_NLT_F64__SI__CI                        0x0000002e
#define SQ_V_CMP_NLT_F64__VI                            0x0000006e
#define SQ_V_CMP_O_F16__VI                              0x00000027
#define SQ_V_CMP_O_F32__SI__CI                          0x00000007
#define SQ_V_CMP_O_F32__VI                              0x00000047
#define SQ_V_CMP_O_F64__SI__CI                          0x00000027
#define SQ_V_CMP_O_F64__VI                              0x00000067
#define SQ_V_CMP_TRU_F16__VI                            0x0000002f
#define SQ_V_CMP_TRU_F32__SI__CI                        0x0000000f
#define SQ_V_CMP_TRU_F32__VI                            0x0000004f
#define SQ_V_CMP_TRU_F64__SI__CI                        0x0000002f
#define SQ_V_CMP_TRU_F64__VI                            0x0000006f
#define SQ_V_CMP_T_I16__VI                              0x000000a7
#define SQ_V_CMP_T_I32__SI__CI                          0x00000087
#define SQ_V_CMP_T_I32__VI                              0x000000c7
#define SQ_V_CMP_T_I64__SI__CI                          0x000000a7
#define SQ_V_CMP_T_I64__VI                              0x000000e7
#define SQ_V_CMP_T_U16__VI                              0x000000af
#define SQ_V_CMP_T_U32__SI__CI                          0x000000c7
#define SQ_V_CMP_T_U32__VI                              0x000000cf
#define SQ_V_CMP_T_U64__SI__CI                          0x000000e7
#define SQ_V_CMP_T_U64__VI                              0x000000ef
#define SQ_V_CMP_U_F16__VI                              0x00000028
#define SQ_V_CMP_U_F32__SI__CI                          0x00000008
#define SQ_V_CMP_U_F32__VI                              0x00000048
#define SQ_V_CMP_U_F64__SI__CI                          0x00000028
#define SQ_V_CMP_U_F64__VI                              0x00000068
#define SQ_V_COS_F16__VI                                0x0000004a
#define SQ_V_COS_F32__SI__CI                            0x00000036
#define SQ_V_COS_F32__VI                                0x0000002a
#define SQ_V_CUBEID_F32__SI__CI                         0x00000144
#define SQ_V_CUBEID_F32__VI                             0x000001c4
#define SQ_V_CUBEMA_F32__SI__CI                         0x00000147
#define SQ_V_CUBEMA_F32__VI                             0x000001c7
#define SQ_V_CUBESC_F32__SI__CI                         0x00000145
#define SQ_V_CUBESC_F32__VI                             0x000001c5
#define SQ_V_CUBETC_F32__SI__CI                         0x00000146
#define SQ_V_CUBETC_F32__VI                             0x000001c6
#define SQ_V_CVT_F16_I16__VI                            0x0000003a
#define SQ_V_CVT_F16_U16__VI                            0x00000039
#define SQ_V_CVT_I16_F16__VI                            0x0000003c
#define SQ_V_CVT_NORM_I16_F16__VI                       0x0000004d
#define SQ_V_CVT_NORM_U16_F16__VI                       0x0000004e
#define SQ_V_CVT_PKACCUM_U8_F32__SI__CI                 0x0000002c
#define SQ_V_CVT_PKACCUM_U8_F32__VI                     0x000001f0
#define SQ_V_CVT_PKNORM_I16_F16__VI                     0x00000299
#define SQ_V_CVT_PKNORM_I16_F32__SI__CI                 0x0000002d
#define SQ_V_CVT_PKNORM_I16_F32__VI                     0x00000294
#define SQ_V_CVT_PKNORM_U16_F16__VI                     0x0000029a
#define SQ_V_CVT_PKNORM_U16_F32__SI__CI                 0x0000002e
#define SQ_V_CVT_PKNORM_U16_F32__VI                     0x00000295
#define SQ_V_CVT_PKRTZ_F16_F32__SI__CI                  0x0000002f
#define SQ_V_CVT_PKRTZ_F16_F32__VI                      0x00000296
#define SQ_V_CVT_PK_I16_I32__SI__CI                     0x00000031
#define SQ_V_CVT_PK_I16_I32__VI                         0x00000298
#define SQ_V_CVT_PK_U16_U32__SI__CI                     0x00000030
#define SQ_V_CVT_PK_U16_U32__VI                         0x00000297
#define SQ_V_CVT_PK_U8_F32__SI__CI                      0x0000015e
#define SQ_V_CVT_PK_U8_F32__VI                          0x000001dd
#define SQ_V_CVT_U16_F16__VI                            0x0000003b
#define SQ_V_DIV_FIXUP_F16__VI                          0x000001ef
#define SQ_V_DIV_FIXUP_F32__SI__CI                      0x0000015f
#define SQ_V_DIV_FIXUP_F32__VI                          0x000001de
#define SQ_V_DIV_FIXUP_F64__SI__CI                      0x00000160
#define SQ_V_DIV_FIXUP_F64__VI                          0x000001df
#define SQ_V_DIV_FMAS_F32__SI__CI                       0x0000016f
#define SQ_V_DIV_FMAS_F32__VI                           0x000001e2
#define SQ_V_DIV_FMAS_F64__SI__CI                       0x00000170
#define SQ_V_DIV_FMAS_F64__VI                           0x000001e3
#define SQ_V_DIV_SCALE_F32__SI__CI                      0x0000016d
#define SQ_V_DIV_SCALE_F32__VI                          0x000001e0
#define SQ_V_DIV_SCALE_F64__SI__CI                      0x0000016e
#define SQ_V_DIV_SCALE_F64__VI                          0x000001e1
#define SQ_V_EXP_F16__VI                                0x00000041
#define SQ_V_EXP_F32__SI__CI                            0x00000025
#define SQ_V_EXP_F32__VI                                0x00000020
#define SQ_V_EXP_LEGACY_F32__VI                         0x0000004b
#define SQ_V_FFBH_I32__SI__CI                           0x0000003b
#define SQ_V_FFBH_I32__VI                               0x0000002f
#define SQ_V_FFBH_U32__SI__CI                           0x00000039
#define SQ_V_FFBH_U32__VI                               0x0000002d
#define SQ_V_FFBL_B32__SI__CI                           0x0000003a
#define SQ_V_FFBL_B32__VI                               0x0000002e
#define SQ_V_FLOOR_F16__VI                              0x00000044
#define SQ_V_FLOOR_F32__SI__CI                          0x00000024
#define SQ_V_FLOOR_F32__VI                              0x0000001f
#define SQ_V_FMA_F16__VI                                0x000001ee
#define SQ_V_FMA_F32__SI__CI                            0x0000014b
#define SQ_V_FMA_F32__VI                                0x000001cb
#define SQ_V_FMA_F64__SI__CI                            0x0000014c
#define SQ_V_FMA_F64__VI                                0x000001cc
#define SQ_V_FRACT_F16__VI                              0x00000048
#define SQ_V_FRACT_F32__SI__CI                          0x00000020
#define SQ_V_FRACT_F32__VI                              0x0000001b
#define SQ_V_FRACT_F64__SI__CI                          0x0000003e
#define SQ_V_FRACT_F64__VI                              0x00000032
#define SQ_V_FREXP_EXP_I16_F16__VI                      0x00000043
#define SQ_V_FREXP_EXP_I32_F32__SI__CI                  0x0000003f
#define SQ_V_FREXP_EXP_I32_F32__VI                      0x00000033
#define SQ_V_FREXP_EXP_I32_F64__SI__CI                  0x0000003c
#define SQ_V_FREXP_EXP_I32_F64__VI                      0x00000030
#define SQ_V_FREXP_MANT_F16__VI                         0x00000042
#define SQ_V_FREXP_MANT_F32__SI__CI                     0x00000040
#define SQ_V_FREXP_MANT_F32__VI                         0x00000034
#define SQ_V_FREXP_MANT_F64__SI__CI                     0x0000003d
#define SQ_V_FREXP_MANT_F64__VI                         0x00000031
#define SQ_V_INTERP_P1LL_F16__VI                        0x00000274
#define SQ_V_INTERP_P1LV_F16__VI                        0x00000275
#define SQ_V_INTERP_P2_F16__VI                          0x00000276
#define SQ_V_INTRP_COUNT__VI                            0x00000004
#define SQ_V_INTRP_OFFSET__VI                           0x00000270
#define SQ_V_LDEXP_F16__VI                              0x00000033
#define SQ_V_LDEXP_F32__SI__CI                          0x0000002b
#define SQ_V_LDEXP_F32__VI                              0x00000288
#define SQ_V_LDEXP_F64__SI__CI                          0x00000168
#define SQ_V_LDEXP_F64__VI                              0x00000284
#define SQ_V_LERP_U8__SI__CI                            0x0000014d
#define SQ_V_LERP_U8__VI                                0x000001cd
#define SQ_V_LOG_F16__VI                                0x00000040
#define SQ_V_LOG_F32__SI__CI                            0x00000027
#define SQ_V_LOG_F32__VI                                0x00000021
#define SQ_V_LOG_LEGACY_F32__VI                         0x0000004c
#define SQ_V_LSHLREV_B16__VI                            0x0000002a
#define SQ_V_LSHLREV_B32__SI__CI                        0x0000001a
#define SQ_V_LSHLREV_B32__VI                            0x00000012
#define SQ_V_LSHLREV_B64__VI                            0x0000028f
#define SQ_V_LSHRREV_B16__VI                            0x0000002b
#define SQ_V_LSHRREV_B32__SI__CI                        0x00000016
#define SQ_V_LSHRREV_B32__VI                            0x00000010
#define SQ_V_LSHRREV_B64__VI                            0x00000290
#define SQ_V_MAC_F16__VI                                0x00000023
#define SQ_V_MAC_F32__SI__CI                            0x0000001f
#define SQ_V_MAC_F32__VI                                0x00000016
#define SQ_V_MAC_LEGACY_F32__SI__CI                     0x00000006
#define SQ_V_MAC_LEGACY_F32__VI                         0x0000028e
#define SQ_V_MADAK_F16__VI                              0x00000025
#define SQ_V_MADAK_F32__SI__CI                          0x00000021
#define SQ_V_MADAK_F32__VI                              0x00000018
#define SQ_V_MADMK_F16__VI                              0x00000024
#define SQ_V_MADMK_F32__SI__CI                          0x00000020
#define SQ_V_MADMK_F32__VI                              0x00000017
#define SQ_V_MAD_F16__VI                                0x000001ea
#define SQ_V_MAD_F32__SI__CI                            0x00000141
#define SQ_V_MAD_F32__VI                                0x000001c1
#define SQ_V_MAD_I16__VI                                0x000001ec
#define SQ_V_MAD_I32_I24__SI__CI                        0x00000142
#define SQ_V_MAD_I32_I24__VI                            0x000001c2
#define SQ_V_MAD_I64_I32__VI                            0x000001e9
#define SQ_V_MAD_LEGACY_F32__SI__CI                     0x00000140
#define SQ_V_MAD_LEGACY_F32__VI                         0x000001c0
#define SQ_V_MAD_U16__VI                                0x000001eb
#define SQ_V_MAD_U32_U24__SI__CI                        0x00000143
#define SQ_V_MAD_U32_U24__VI                            0x000001c3
#define SQ_V_MAD_U64_U32__VI                            0x000001e8
#define SQ_V_MAX3_F32__SI__CI                           0x00000154
#define SQ_V_MAX3_F32__VI                               0x000001d3
#define SQ_V_MAX3_I32__SI__CI                           0x00000155
#define SQ_V_MAX3_I32__VI                               0x000001d4
#define SQ_V_MAX3_U32__SI__CI                           0x00000156
#define SQ_V_MAX3_U32__VI                               0x000001d5
#define SQ_V_MAX_F16__VI                                0x0000002d
#define SQ_V_MAX_F32__SI__CI                            0x00000010
#define SQ_V_MAX_F32__VI                                0x0000000b
#define SQ_V_MAX_F64__SI__CI                            0x00000167
#define SQ_V_MAX_F64__VI                                0x00000283
#define SQ_V_MAX_I16__VI                                0x00000030
#define SQ_V_MAX_I32__SI__CI                            0x00000012
#define SQ_V_MAX_I32__VI                                0x0000000d
#define SQ_V_MAX_U16__VI                                0x0000002f
#define SQ_V_MAX_U32__SI__CI                            0x00000014
#define SQ_V_MAX_U32__VI                                0x0000000f
#define SQ_V_MBCNT_HI_U32_B32__SI__CI                   0x00000024
#define SQ_V_MBCNT_HI_U32_B32__VI                       0x0000028d
#define SQ_V_MBCNT_LO_U32_B32__SI__CI                   0x00000023
#define SQ_V_MBCNT_LO_U32_B32__VI                       0x0000028c
#define SQ_V_MED3_F32__SI__CI                           0x00000157
#define SQ_V_MED3_F32__VI                               0x000001d6
#define SQ_V_MED3_I32__SI__CI                           0x00000158
#define SQ_V_MED3_I32__VI                               0x000001d7
#define SQ_V_MED3_U32__SI__CI                           0x00000159
#define SQ_V_MED3_U32__VI                               0x000001d8
#define SQ_V_MIN3_F32__SI__CI                           0x00000151
#define SQ_V_MIN3_F32__VI                               0x000001d0
#define SQ_V_MIN3_I32__SI__CI                           0x00000152
#define SQ_V_MIN3_I32__VI                               0x000001d1
#define SQ_V_MIN3_U32__SI__CI                           0x00000153
#define SQ_V_MIN3_U32__VI                               0x000001d2
#define SQ_V_MIN_F16__VI                                0x0000002e
#define SQ_V_MIN_F32__SI__CI                            0x0000000f
#define SQ_V_MIN_F32__VI                                0x0000000a
#define SQ_V_MIN_F64__SI__CI                            0x00000166
#define SQ_V_MIN_F64__VI                                0x00000282
#define SQ_V_MIN_I16__VI                                0x00000032
#define SQ_V_MIN_I32__SI__CI                            0x00000011
#define SQ_V_MIN_I32__VI                                0x0000000c
#define SQ_V_MIN_U16__VI                                0x00000031
#define SQ_V_MIN_U32__SI__CI                            0x00000013
#define SQ_V_MIN_U32__VI                                0x0000000e
#define SQ_V_MOVRELD_B32__SI__CI                        0x00000042
#define SQ_V_MOVRELD_B32__VI                            0x00000036
#define SQ_V_MOVRELSD_B32__SI__CI                       0x00000044
#define SQ_V_MOVRELSD_B32__VI                           0x00000038
#define SQ_V_MOVRELS_B32__SI__CI                        0x00000043
#define SQ_V_MOVRELS_B32__VI                            0x00000037
#define SQ_V_MQSAD_PK_U16_U8__VI                        0x000001e6
#define SQ_V_MQSAD_U32_U8__VI                           0x000001e7
#define SQ_V_MSAD_U8__SI__CI                            0x00000171
#define SQ_V_MSAD_U8__VI                                0x000001e4
#define SQ_V_MUL_F16__VI                                0x00000022
#define SQ_V_MUL_F32__SI__CI                            0x00000008
#define SQ_V_MUL_F32__VI                                0x00000005
#define SQ_V_MUL_F64__SI__CI                            0x00000165
#define SQ_V_MUL_F64__VI                                0x00000281
#define SQ_V_MUL_HI_I32__SI__CI                         0x0000016c
#define SQ_V_MUL_HI_I32__VI                             0x00000287
#define SQ_V_MUL_HI_I32_I24__SI__CI                     0x0000000a
#define SQ_V_MUL_HI_I32_I24__VI                         0x00000007
#define SQ_V_MUL_HI_U32__SI__CI                         0x0000016a
#define SQ_V_MUL_HI_U32__VI                             0x00000286
#define SQ_V_MUL_HI_U32_U24__SI__CI                     0x0000000c
#define SQ_V_MUL_HI_U32_U24__VI                         0x00000009
#define SQ_V_MUL_I32_I24__SI__CI                        0x00000009
#define SQ_V_MUL_I32_I24__VI                            0x00000006
#define SQ_V_MUL_LEGACY_F32__SI__CI                     0x00000007
#define SQ_V_MUL_LEGACY_F32__VI                         0x00000004
#define SQ_V_MUL_LO_U16__VI                             0x00000029
#define SQ_V_MUL_LO_U32__SI__CI                         0x00000169
#define SQ_V_MUL_LO_U32__VI                             0x00000285
#define SQ_V_MUL_U32_U24__SI__CI                        0x0000000b
#define SQ_V_MUL_U32_U24__VI                            0x00000008
#define SQ_V_NOT_B32__SI__CI                            0x00000037
#define SQ_V_NOT_B32__VI                                0x0000002b
#define SQ_V_OP1_OFFSET__SI__CI                         0x00000180
#define SQ_V_OP1_OFFSET__VI                             0x00000140
#define SQ_V_OP3_2IN_COUNT__VI                          0x00000080
#define SQ_V_OP3_2IN_OFFSET__VI                         0x00000280
#define SQ_V_OP3_3IN_COUNT__VI                          0x000000b0
#define SQ_V_OP3_3IN_OFFSET__VI                         0x000001c0
#define SQ_V_OP3_INTRP_COUNT__VI                        0x0000000c
#define SQ_V_OP3_INTRP_OFFSET__VI                       0x00000274
#define SQ_V_OR_B32__SI__CI                             0x0000001c
#define SQ_V_OR_B32__VI                                 0x00000014
#define SQ_V_PERM_B32__VI                               0x000001ed
#define SQ_V_QSAD_PK_U16_U8__VI                         0x000001e5
#define SQ_V_RCP_F16__VI                                0x0000003d
#define SQ_V_RCP_F32__SI__CI                            0x0000002a
#define SQ_V_RCP_F32__VI                                0x00000022
#define SQ_V_RCP_F64__SI__CI                            0x0000002f
#define SQ_V_RCP_F64__VI                                0x00000025
#define SQ_V_RCP_IFLAG_F32__SI__CI                      0x0000002b
#define SQ_V_RCP_IFLAG_F32__VI                          0x00000023
#define SQ_V_READLANE_B32__SI__CI                       0x00000001
#define SQ_V_READLANE_B32__VI                           0x00000289
#define SQ_V_RNDNE_F16__VI                              0x00000047
#define SQ_V_RNDNE_F32__SI__CI                          0x00000023
#define SQ_V_RNDNE_F32__VI                              0x0000001e
#define SQ_V_RSQ_F16__VI                                0x0000003f
#define SQ_V_RSQ_F32__SI__CI                            0x0000002e
#define SQ_V_RSQ_F32__VI                                0x00000024
#define SQ_V_RSQ_F64__SI__CI                            0x00000031
#define SQ_V_RSQ_F64__VI                                0x00000026
#define SQ_V_SAD_HI_U8__SI__CI                          0x0000015b
#define SQ_V_SAD_HI_U8__VI                              0x000001da
#define SQ_V_SAD_U16__SI__CI                            0x0000015c
#define SQ_V_SAD_U16__VI                                0x000001db
#define SQ_V_SAD_U32__SI__CI                            0x0000015d
#define SQ_V_SAD_U32__VI                                0x000001dc
#define SQ_V_SAD_U8__SI__CI                             0x0000015a
#define SQ_V_SAD_U8__VI                                 0x000001d9
#define SQ_V_SIN_F16__VI                                0x00000049
#define SQ_V_SIN_F32__SI__CI                            0x00000035
#define SQ_V_SIN_F32__VI                                0x00000029
#define SQ_V_SQRT_F16__VI                               0x0000003e
#define SQ_V_SQRT_F32__SI__CI                           0x00000033
#define SQ_V_SQRT_F32__VI                               0x00000027
#define SQ_V_SQRT_F64__SI__CI                           0x00000034
#define SQ_V_SQRT_F64__VI                               0x00000028
#define SQ_V_SUBBREV_U32__SI__CI                        0x0000002a
#define SQ_V_SUBBREV_U32__VI                            0x0000001e
#define SQ_V_SUBB_U32__SI__CI                           0x00000029
#define SQ_V_SUBB_U32__VI                               0x0000001d
#define SQ_V_SUBREV_F16__VI                             0x00000021
#define SQ_V_SUBREV_F32__SI__CI                         0x00000005
#define SQ_V_SUBREV_F32__VI                             0x00000003
#define SQ_V_SUBREV_U16__VI                             0x00000028
#define SQ_V_SUBREV_U32__VI                             0x0000001b
#define SQ_V_SUB_F16__VI                                0x00000020
#define SQ_V_SUB_F32__SI__CI                            0x00000004
#define SQ_V_SUB_F32__VI                                0x00000002
#define SQ_V_SUB_U16__VI                                0x00000027
#define SQ_V_SUB_U32__VI                                0x0000001a
#define SQ_V_TRIG_PREOP_F64__SI__CI                     0x00000174
#define SQ_V_TRIG_PREOP_F64__VI                         0x00000292
#define SQ_V_TRUNC_F16__VI                              0x00000046
#define SQ_V_TRUNC_F32__SI__CI                          0x00000021
#define SQ_V_TRUNC_F32__VI                              0x0000001c
#define SQ_V_WRITELANE_B32__SI__CI                      0x00000002
#define SQ_V_WRITELANE_B32__VI                          0x0000028a
#define SQ_V_XOR_B32__SI__CI                            0x0000001d
#define SQ_V_XOR_B32__VI                                0x00000015
#define SQ_XLATE_VOP3_TO_VINTRP_COUNT__VI               0x00000004
#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET__VI              0x00000270
#define SQ_XLATE_VOP3_TO_VOP1_COUNT__VI                 0x00000080
#define SQ_XLATE_VOP3_TO_VOP1_OFFSET__VI                0x00000140
#define SQ_XLATE_VOP3_TO_VOP2_COUNT__VI                 0x00000040
#define SQ_XLATE_VOP3_TO_VOP2_OFFSET__VI                0x00000100
#define SQ_XLATE_VOP3_TO_VOPC_COUNT__VI                 0x00000100
#define SQ_XLATE_VOP3_TO_VOPC_OFFSET__VI                0x00000000
#define SQ_XNACK_MASK_HI__VI                            0x00000069
#define SQ_XNACK_MASK_LO__VI                            0x00000068

} // inline namespace Chip
} // namespace Gfx6
} // namespace Pal

#endif
