unit si_ci_vi_merged_offset;

interface

{$mode objfpc}{$H+}

const
 mmGRBM_CNTL                                              =$2000;
 mmGRBM_SKEW_CNTL                                         =$2001;
 mmGRBM_STATUS2                                           =$2002;
 mmGRBM_PWR_CNTL                                          =$2003;
 mmGRBM_STATUS                                            =$2004;
 mmGRBM_STATUS_SE0                                        =$2005;
 mmGRBM_STATUS_SE1                                        =$2006;
 mmGRBM_SOFT_RESET                                        =$2008;
 mmGRBM_DEBUG_CNTL                                        =$2009;
 mmGRBM_DEBUG_DATA                                        =$200A;
 mmGRBM_GFX_CLKEN_CNTL                                    =$200C;
 mmGRBM_WAIT_IDLE_CLOCKS                                  =$200D;
 mmGRBM_STATUS_SE2                                        =$200E;
 mmGRBM_STATUS_SE3                                        =$200F;
 mmGRBM_DEBUG                                             =$2014;
 mmGRBM_DEBUG_SNAPSHOT                                    =$2015;
 mmGRBM_READ_ERROR                                        =$2016;
 mmGRBM_READ_ERROR2                                       =$2017;
 mmGRBM_INT_CNTL                                          =$2018;
 mmGRBM_TRAP_OP                                           =$2019;
 mmGRBM_TRAP_ADDR                                         =$201A;
 mmGRBM_TRAP_ADDR_MSK                                     =$201B;
 mmGRBM_TRAP_WD                                           =$201C;
 mmGRBM_TRAP_WD_MSK                                       =$201D;
 mmGRBM_DSM_BYPASS                                        =$201E;
 mmGRBM_WRITE_ERROR                                       =$201F;
 mmDEBUG_INDEX                                            =$203C;
 mmDEBUG_DATA                                             =$203D;
 mmGRBM_NOWHERE                                           =$203F;
 mmGRBM_SCRATCH_REG0                                      =$2040;
 mmGRBM_SCRATCH_REG1                                      =$2041;
 mmGRBM_SCRATCH_REG2                                      =$2042;
 mmGRBM_SCRATCH_REG3                                      =$2043;
 mmGRBM_SCRATCH_REG4                                      =$2044;
 mmGRBM_SCRATCH_REG5                                      =$2045;
 mmGRBM_SCRATCH_REG6                                      =$2046;
 mmGRBM_SCRATCH_REG7                                      =$2047;
 mmCP_CPC_STATUS                                          =$2084;
 mmCP_CPC_BUSY_STAT                                       =$2085;
 mmCP_CPC_STALLED_STAT1                                   =$2086;
 mmCP_CPF_STATUS                                          =$2087;
 mmCP_CPF_BUSY_STAT                                       =$2088;
 mmCP_CPF_STALLED_STAT1                                   =$2089;
 mmCP_CPC_GRBM_FREE_COUNT                                 =$208B;
 mmCP_MEC_CNTL                                            =$208D;
 mmCP_MEC_ME1_HEADER_DUMP                                 =$208E;
 mmCP_MEC_ME2_HEADER_DUMP                                 =$208F;
 mmCP_CPC_SCRATCH_INDEX                                   =$2090;
 mmCP_CPC_SCRATCH_DATA                                    =$2091;
 mmCP_CPC_HALT_HYST_COUNT                                 =$20A7;
 mmCP_PRT_LOD_STATS_CNTL0                                 =$20AD;
 mmCP_PRT_LOD_STATS_CNTL1                                 =$20AE;
 mmCP_PRT_LOD_STATS_CNTL2                                 =$20AF;
 mmCP_CE_COMPARE_COUNT                                    =$20C0;
 mmCP_CE_DE_COUNT                                         =$20C1;
 mmCP_DE_CE_COUNT                                         =$20C2;
 mmCP_DE_LAST_INVAL_COUNT                                 =$20C3;
 mmCP_DE_DE_COUNT                                         =$20C4;
 mmCP_STALLED_STAT3                                       =$219C;
 mmCP_STALLED_STAT1                                       =$219D;
 mmCP_STALLED_STAT2                                       =$219E;
 mmCP_BUSY_STAT                                           =$219F;
 mmCP_STAT                                                =$21A0;
 mmCP_ME_HEADER_DUMP                                      =$21A1;
 mmCP_PFP_HEADER_DUMP                                     =$21A2;
 mmCP_GRBM_FREE_COUNT                                     =$21A3;
 mmCP_CE_HEADER_DUMP                                      =$21A4;
 mmCP_CSF_STAT                                            =$21B4;
 mmCP_CSF_CNTL                                            =$21B5;
 mmCP_ME_CNTL                                             =$21B6;
 mmCP_CNTX_STAT                                           =$21B8;
 mmCP_ME_PREEMPTION                                       =$21B9;
 mmCP_ROQ_THRESHOLDS                                      =$21BC;
 mmCP_MEQ_STQ_THRESHOLD                                   =$21BD;
 mmCP_RB2_RPTR                                            =$21BE;
 mmCP_RB1_RPTR                                            =$21BF;
 mmCP_RB0_RPTR                                            =$21C0;
 mmCP_RB_WPTR_DELAY                                       =$21C1;
 mmCP_RB_WPTR_POLL_CNTL                                   =$21C2;
 mmCP_ROQ1_THRESHOLDS                                     =$21D5;
 mmCP_ROQ2_THRESHOLDS                                     =$21D6;
 mmCP_STQ_THRESHOLDS                                      =$21D7;
 mmCP_QUEUE_THRESHOLDS                                    =$21D8;
 mmCP_MEQ_THRESHOLDS                                      =$21D9;
 mmCP_ROQ_AVAIL                                           =$21DA;
 mmCP_STQ_AVAIL                                           =$21DB;
 mmCP_ROQ2_AVAIL                                          =$21DC;
 mmCP_MEQ_AVAIL                                           =$21DD;
 mmCP_CMD_INDEX                                           =$21DE;
 mmCP_CMD_DATA                                            =$21DF;
 mmCP_ROQ_RB_STAT                                         =$21E0;
 mmCP_ROQ_IB1_STAT                                        =$21E1;
 mmCP_ROQ_IB2_STAT                                        =$21E2;
 mmCP_STQ_STAT                                            =$21E3;
 mmCP_STQ_WR_STAT                                         =$21E4;
 mmCP_MEQ_STAT                                            =$21E5;
 mmCP_CEQ1_AVAIL                                          =$21E6;
 mmCP_CEQ2_AVAIL                                          =$21E7;
 mmCP_CE_ROQ_RB_STAT                                      =$21E8;
 mmCP_CE_ROQ_IB1_STAT                                     =$21E9;
 mmCP_CE_ROQ_IB2_STAT                                     =$21EA;
 mmCP_INT_STAT_DEBUG                                      =$21F7;
 mmCP_PERFCOUNTER_SELECT                                  =$21FC;
 mmCP_PERFCOUNTER_LO                                      =$21FD;
 mmCP_PERFCOUNTER_HI                                      =$21FE;
 mmVGT_VTX_VECT_EJECT_REG                                 =$222C;
 mmVGT_DMA_DATA_FIFO_DEPTH                                =$222D;
 mmVGT_DMA_REQ_FIFO_DEPTH                                 =$222E;
 mmVGT_DRAW_INIT_FIFO_DEPTH                               =$222F;
 mmVGT_LAST_COPY_STATE                                    =$2230;
 mmVGT_CACHE_INVALIDATION                                 =$2231;
 mmVGT_RESET_DEBUG                                        =$2232;
 mmVGT_STRMOUT_DELAY                                      =$2233;
 mmVGT_FIFO_DEPTHS                                        =$2234;
 mmVGT_GS_VERTEX_REUSE                                    =$2235;
 mmVGT_MC_LAT_CNTL                                        =$2236;
 mmIA_CNTL_STATUS                                         =$2237;
 mmVGT_DEBUG_CNTL                                         =$2238;
 mmVGT_DEBUG_DATA                                         =$2239;
 mmIA_DEBUG_CNTL                                          =$223A;
 mmIA_DEBUG_DATA                                          =$223B;
 mmVGT_CNTL_STATUS                                        =$223C;
 mmWD_DEBUG_CNTL                                          =$223D;
 mmWD_DEBUG_DATA                                          =$223E;
 mmWD_CNTL_STATUS                                         =$223F;
 mmCC_GC_PRIM_CONFIG                                      =$2240;
 mmGC_USER_PRIM_CONFIG                                    =$2241;
 mmWD_QOS                                                 =$2242;
 mmCGTT_VGT_CLK_CTRL                                      =$225F;
 mmCGTT_IA_CLK_CTRL                                       =$2261;
 mmVGT_SYS_CONFIG                                         =$2263;
 mmVGT_VS_MAX_WAVE_ID                                     =$2268;
 mmGFX_PIPE_CONTROL                                       =$226D;
 mmCC_GC_SHADER_ARRAY_CONFIG                              =$226F;
 mmGC_USER_SHADER_ARRAY_CONFIG                            =$2270;
 mmVGT_DMA_PRIMITIVE_TYPE                                 =$2271;
 mmVGT_DMA_CONTROL                                        =$2272;
 mmVGT_DMA_LS_HS_CONFIG                                   =$2273;
 mmPA_SU_DEBUG_CNTL                                       =$2280;
 mmPA_SU_DEBUG_DATA                                       =$2281;
 mmPA_CL_CNTL_STATUS                                      =$2284;
 mmPA_CL_ENHANCE                                          =$2285;
 mmPA_CL_RESET_DEBUG                                      =$2286;
 mmPA_SU_CNTL_STATUS                                      =$2294;
 mmPA_SC_FIFO_DEPTH_CNTL                                  =$2295;
 mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK                          =$22C0;
 mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK                         =$22C1;
 mmPA_SC_TRAP_SCREEN_HV_LOCK                              =$22C2;
 mmPA_SC_FORCE_EOV_MAX_CNTS                               =$22C9;
 mmCGTT_SC_CLK_CTRL                                       =$22CA;
 mmPA_SC_FIFO_SIZE                                        =$22F3;
 mmPA_SC_IF_FIFO_SIZE                                     =$22F5;
 mmPA_SC_DEBUG_CNTL                                       =$22F6;
 mmPA_SC_DEBUG_DATA                                       =$22F7;
 mmPA_SC_ENHANCE                                          =$22FC;
 mmSQ_CONFIG                                              =$2300;
 mmSQC_CONFIG                                             =$2301;
 mmSQ_RANDOM_WAVE_PRI                                     =$2303;
 mmSQ_REG_CREDITS                                         =$2304;
 mmSQ_FIFO_SIZES                                          =$2305;
 mmSQ_DSM_CNTL                                            =$2306;
 mmCC_SQC_BANK_DISABLE                                    =$2307;
 mmUSER_SQC_BANK_DISABLE                                  =$2308;
 mmSQ_DEBUG_STS_GLOBAL                                    =$2309;
 mmSH_MEM_BASES                                           =$230A;
 mmSH_MEM_APE1_BASE                                       =$230B;
 mmSH_MEM_APE1_LIMIT                                      =$230C;
 mmSH_MEM_CONFIG                                          =$230D;
 mmSQC_DSM_CNTL                                           =$230F;
 mmSQ_DEBUG_STS_GLOBAL2                                   =$2310;
 mmSQ_DEBUG_STS_GLOBAL3                                   =$2311;
 mmCC_GC_SHADER_RATE_CONFIG                               =$2312;
 mmGC_USER_SHADER_RATE_CONFIG                             =$2313;
 mmSQ_INTERRUPT_AUTO_MASK                                 =$2314;
 mmSQ_INTERRUPT_MSG_CTRL                                  =$2315;
 mmSQ_ALU_CLK_CTRL                                        =$2360;
 mmSQ_TEX_CLK_CTRL                                        =$2361;
 mmCGTT_SQ_CLK_CTRL                                       =$2362;
 mmCGTT_SQG_CLK_CTRL                                      =$2363;
 mmSQ_REG_TIMESTAMP                                       =$2374;
 mmSQ_CMD_TIMESTAMP                                       =$2375;
 mmSQ_IND_INDEX                                           =$2378;
 mmSQ_IND_DATA                                            =$2379;
 mmSQ_CMD                                                 =$237B;
 mmSQ_TIME_HI                                             =$237C;
 mmSQ_TIME_LO                                             =$237D;
 mmSQ_DS_0                                                =$237F;
 mmSQ_THREAD_TRACE_CNTR                                   =$2390;
 mmSQ_POWER_THROTTLE                                      =$2396;
 mmSQ_POWER_THROTTLE2                                     =$2397;
 mmSQ_LB_CTR_CTRL                                         =$2398;
 mmSQ_LB_DATA_ALU_CYCLES                                  =$2399;
 mmSQ_LB_DATA_TEX_CYCLES                                  =$239A;
 mmSQ_LB_DATA_ALU_STALLS                                  =$239B;
 mmSQ_LB_DATA_TEX_STALLS                                  =$239C;
 mmSQC_EDC_CNT                                            =$23A0;
 mmSQ_EDC_SEC_CNT                                         =$23A1;
 mmSQ_EDC_DED_CNT                                         =$23A2;
 mmSQ_EDC_INFO                                            =$23A3;
 mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2                     =$23B0;
 mmSQ_WREXEC_EXEC_HI                                      =$23B1;
 mmSQC_GATCL1_CNTL                                        =$23B2;
 mmSQC_ATC_EDC_GATCL1_CNT                                 =$23B3;
 mmSQ_BUF_RSRC_WORD0                                      =$23C0;
 mmSQ_BUF_RSRC_WORD1                                      =$23C1;
 mmSQ_BUF_RSRC_WORD2                                      =$23C2;
 mmSQ_BUF_RSRC_WORD3                                      =$23C3;
 mmSQ_IMG_RSRC_WORD0                                      =$23C4;
 mmSQ_IMG_RSRC_WORD1                                      =$23C5;
 mmSQ_IMG_RSRC_WORD2                                      =$23C6;
 mmSQ_IMG_RSRC_WORD3                                      =$23C7;
 mmSQ_IMG_RSRC_WORD4                                      =$23C8;
 mmSQ_IMG_RSRC_WORD5                                      =$23C9;
 mmSQ_IMG_RSRC_WORD6                                      =$23CA;
 mmSQ_IMG_RSRC_WORD7                                      =$23CB;
 mmSQ_IMG_SAMP_WORD0                                      =$23CC;
 mmSQ_IMG_SAMP_WORD1                                      =$23CD;
 mmSQ_IMG_SAMP_WORD2                                      =$23CE;
 mmSQ_IMG_SAMP_WORD3                                      =$23CF;
 mmSQ_FLAT_SCRATCH_WORD0                                  =$23D0;
 mmSQ_FLAT_SCRATCH_WORD1                                  =$23D1;
 mmSQ_M0_GPR_IDX_WORD                                     =$23D2;
 mmCGTT_SX_CLK_CTRL0                                      =$240C;
 mmCGTT_SX_CLK_CTRL1                                      =$240D;
 mmCGTT_SX_CLK_CTRL2                                      =$240E;
 mmCGTT_SX_CLK_CTRL3                                      =$240F;
 mmCGTT_SX_CLK_CTRL4                                      =$2410;
 mmSX_DEBUG_BUSY                                          =$2414;
 mmSX_DEBUG_BUSY_2                                        =$2415;
 mmSX_DEBUG_BUSY_3                                        =$2416;
 mmSX_DEBUG_BUSY_4                                        =$2417;
 mmSX_DEBUG_1                                             =$2418;
 mmSPI_PS_MAX_WAVE_ID                                     =$243A;
 mmSPI_START_PHASE                                        =$243B;
 mmSPI_GFX_CNTL                                           =$243C;
 mmSPI_CONFIG_CNTL                                        =$2440;
 mmSPI_DEBUG_CNTL                                         =$2441;
 mmSPI_DEBUG_READ                                         =$2442;
 mmSPI_DSM_CNTL                                           =$2443;
 mmSPI_EDC_CNT                                            =$2444;
 mmSPI_CONFIG_CNTL_1                                      =$244F;
 mmSPI_DEBUG_BUSY                                         =$2450;
 mmSPI_CONFIG_CNTL_2                                      =$2451;
 mmCGTS_TCC_DISABLE                                       =$2452;
 mmCGTS_USER_TCC_DISABLE                                  =$2453;
 mmCGTS_SM_CTRL_REG                                       =$2454;
 mmCGTS_RD_CTRL_REG                                       =$2455;
 mmCGTS_RD_REG                                            =$2456;
 mmCGTT_PC_CLK_CTRL                                       =$24A8;
 mmCGTT_BCI_CLK_CTRL                                      =$24A9;
 mmSPI_WF_LIFETIME_CNTL                                   =$24AA;
 mmSPI_WF_LIFETIME_LIMIT_0                                =$24AB;
 mmSPI_WF_LIFETIME_LIMIT_1                                =$24AC;
 mmSPI_WF_LIFETIME_LIMIT_2                                =$24AD;
 mmSPI_WF_LIFETIME_LIMIT_3                                =$24AE;
 mmSPI_WF_LIFETIME_LIMIT_4                                =$24AF;
 mmSPI_WF_LIFETIME_LIMIT_5                                =$24B0;
 mmSPI_WF_LIFETIME_LIMIT_6                                =$24B1;
 mmSPI_WF_LIFETIME_LIMIT_7                                =$24B2;
 mmSPI_WF_LIFETIME_LIMIT_8                                =$24B3;
 mmSPI_WF_LIFETIME_LIMIT_9                                =$24B4;
 mmSPI_WF_LIFETIME_STATUS_0                               =$24B5;
 mmSPI_WF_LIFETIME_STATUS_1                               =$24B6;
 mmSPI_WF_LIFETIME_STATUS_2                               =$24B7;
 mmSPI_WF_LIFETIME_STATUS_3                               =$24B8;
 mmSPI_WF_LIFETIME_STATUS_4                               =$24B9;
 mmSPI_WF_LIFETIME_STATUS_5                               =$24BA;
 mmSPI_WF_LIFETIME_STATUS_6                               =$24BB;
 mmSPI_WF_LIFETIME_STATUS_7                               =$24BC;
 mmSPI_WF_LIFETIME_STATUS_8                               =$24BD;
 mmSPI_WF_LIFETIME_STATUS_9                               =$24BE;
 mmSPI_WF_LIFETIME_STATUS_10                              =$24BF;
 mmSPI_WF_LIFETIME_STATUS_11                              =$24C0;
 mmSPI_WF_LIFETIME_STATUS_12                              =$24C1;
 mmSPI_WF_LIFETIME_STATUS_13                              =$24C2;
 mmSPI_WF_LIFETIME_STATUS_14                              =$24C3;
 mmSPI_WF_LIFETIME_STATUS_15                              =$24C4;
 mmSPI_WF_LIFETIME_STATUS_16                              =$24C5;
 mmSPI_WF_LIFETIME_STATUS_17                              =$24C6;
 mmSPI_WF_LIFETIME_STATUS_18                              =$24C7;
 mmSPI_WF_LIFETIME_STATUS_19                              =$24C8;
 mmSPI_WF_LIFETIME_STATUS_20                              =$24C9;
 mmSPI_WF_LIFETIME_DEBUG                                  =$24CA;
 mmSPI_SLAVE_DEBUG_BUSY                                   =$24D3;
 mmSPI_LB_CTR_CTRL                                        =$24D4;
 mmSPI_LB_CU_MASK                                         =$24D5;
 mmSPI_LB_DATA_REG                                        =$24D6;
 mmSPI_PG_ENABLE_STATIC_CU_MASK                           =$24D7;
 mmSPI_GDS_CREDITS                                        =$24D8;
 mmSPI_SX_EXPORT_BUFFER_SIZES                             =$24D9;
 mmSPI_SX_SCOREBOARD_BUFFER_SIZES                         =$24DA;
 mmSPI_CSQ_WF_ACTIVE_STATUS                               =$24DB;
 mmSPI_CSQ_WF_ACTIVE_COUNT_0                              =$24DC;
 mmSPI_CSQ_WF_ACTIVE_COUNT_1                              =$24DD;
 mmSPI_CSQ_WF_ACTIVE_COUNT_2                              =$24DE;
 mmSPI_CSQ_WF_ACTIVE_COUNT_3                              =$24DF;
 mmSPI_CSQ_WF_ACTIVE_COUNT_4                              =$24E0;
 mmSPI_CSQ_WF_ACTIVE_COUNT_5                              =$24E1;
 mmSPI_CSQ_WF_ACTIVE_COUNT_6                              =$24E2;
 mmSPI_CSQ_WF_ACTIVE_COUNT_7                              =$24E3;
 mmBCI_DEBUG_READ                                         =$24EB;
 mmSPI_P0_TRAP_SCREEN_PSBA_LO                             =$24EC;
 mmSPI_P0_TRAP_SCREEN_PSBA_HI                             =$24ED;
 mmSPI_P0_TRAP_SCREEN_PSMA_LO                             =$24EE;
 mmSPI_P0_TRAP_SCREEN_PSMA_HI                             =$24EF;
 mmSPI_P0_TRAP_SCREEN_GPR_MIN                             =$24F0;
 mmSPI_P1_TRAP_SCREEN_PSBA_LO                             =$24F1;
 mmSPI_P1_TRAP_SCREEN_PSBA_HI                             =$24F2;
 mmSPI_P1_TRAP_SCREEN_PSMA_LO                             =$24F3;
 mmSPI_P1_TRAP_SCREEN_PSMA_HI                             =$24F4;
 mmSPI_P1_TRAP_SCREEN_GPR_MIN                             =$24F5;
 mmTD_CNTL                                                =$2525;
 mmTD_STATUS                                              =$2526;
 mmTD_CGTT_CTRL                                           =$2527;
 mmTD_DEBUG_INDEX                                         =$2528;
 mmTD_DEBUG_DATA                                          =$2529;
 mmTD_DSM_CNTL                                            =$252F;
 mmTD_SCRATCH                                             =$2533;
 mmTA_CNTL                                                =$2541;
 mmTA_CNTL_AUX                                            =$2542;
 mmTA_RESERVED_010C                                       =$2543;
 mmTA_CGTT_CTRL                                           =$2544;
 mmTA_STATUS                                              =$2548;
 mmTA_DEBUG_INDEX                                         =$254C;
 mmTA_DEBUG_DATA                                          =$254D;
 mmTA_SCRATCH                                             =$2564;
 mmSH_HIDDEN_PRIVATE_BASE_VMID                            =$2580;
 mmSH_STATIC_MEM_CONFIG                                   =$2581;
 mmGDS_CONFIG                                             =$25C0;
 mmGDS_CNTL_STATUS                                        =$25C1;
 mmGDS_ENHANCE2                                           =$25C2;
 mmGDS_PROTECTION_FAULT                                   =$25C3;
 mmGDS_VM_PROTECTION_FAULT                                =$25C4;
 mmGDS_EDC_CNT                                            =$25C5;
 mmGDS_EDC_GRBM_CNT                                       =$25C6;
 mmGDS_EDC_OA_DED                                         =$25C7;
 mmGDS_DEBUG_CNTL                                         =$25C8;
 mmGDS_DEBUG_DATA                                         =$25C9;
 mmGDS_DSM_CNTL                                           =$25CA;
 mmCGTT_GDS_CLK_CTRL                                      =$25DD;
 mmGDS_SECDED_CNT                                         =$25E2;
 mmGDS_GRBM_SECDED_CNT                                    =$25E3;
 mmGDS_OA_DED                                             =$25E4;
 mmDB_DEBUG                                               =$260C;
 mmDB_DEBUG2                                              =$260D;
 mmDB_DEBUG3                                              =$260E;
 mmDB_DEBUG4                                              =$260F;
 mmDB_CREDIT_LIMIT                                        =$2614;
 mmDB_WATERMARKS                                          =$2615;
 mmDB_SUBTILE_CONTROL                                     =$2616;
 mmDB_FREE_CACHELINES                                     =$2617;
 mmDB_FIFO_DEPTH1                                         =$2618;
 mmDB_FIFO_DEPTH2                                         =$2619;
 mmDB_CGTT_CLK_CTRL_0                                     =$261A;
 mmDB_RING_CONTROL                                        =$261B;
 mmDB_READ_DEBUG_0                                        =$2620;
 mmDB_READ_DEBUG_1                                        =$2621;
 mmDB_READ_DEBUG_2                                        =$2622;
 mmDB_READ_DEBUG_3                                        =$2623;
 mmDB_READ_DEBUG_4                                        =$2624;
 mmDB_READ_DEBUG_5                                        =$2625;
 mmDB_READ_DEBUG_6                                        =$2626;
 mmDB_READ_DEBUG_7                                        =$2627;
 mmDB_READ_DEBUG_8                                        =$2628;
 mmDB_READ_DEBUG_9                                        =$2629;
 mmDB_READ_DEBUG_A                                        =$262A;
 mmDB_READ_DEBUG_B                                        =$262B;
 mmDB_READ_DEBUG_C                                        =$262C;
 mmDB_READ_DEBUG_D                                        =$262D;
 mmDB_READ_DEBUG_E                                        =$262E;
 mmDB_READ_DEBUG_F                                        =$262F;
 mmCC_RB_REDUNDANCY                                       =$263C;
 mmCC_RB_BACKEND_DISABLE                                  =$263D;
 mmGB_ADDR_CONFIG                                         =$263E;
 mmGB_BACKEND_MAP                                         =$263F;
 mmGB_GPU_ID                                              =$2640;
 mmCC_RB_DAISY_CHAIN                                      =$2641;
 mmGB_TILE_MODE0                                          =$2644;
 mmGB_TILE_MODE1                                          =$2645;
 mmGB_TILE_MODE2                                          =$2646;
 mmGB_TILE_MODE3                                          =$2647;
 mmGB_TILE_MODE4                                          =$2648;
 mmGB_TILE_MODE5                                          =$2649;
 mmGB_TILE_MODE6                                          =$264A;
 mmGB_TILE_MODE7                                          =$264B;
 mmGB_TILE_MODE8                                          =$264C;
 mmGB_TILE_MODE9                                          =$264D;
 mmGB_TILE_MODE10                                         =$264E;
 mmGB_TILE_MODE11                                         =$264F;
 mmGB_TILE_MODE12                                         =$2650;
 mmGB_TILE_MODE13                                         =$2651;
 mmGB_TILE_MODE14                                         =$2652;
 mmGB_TILE_MODE15                                         =$2653;
 mmGB_TILE_MODE16                                         =$2654;
 mmGB_TILE_MODE17                                         =$2655;
 mmGB_TILE_MODE18                                         =$2656;
 mmGB_TILE_MODE19                                         =$2657;
 mmGB_TILE_MODE20                                         =$2658;
 mmGB_TILE_MODE21                                         =$2659;
 mmGB_TILE_MODE22                                         =$265A;
 mmGB_TILE_MODE23                                         =$265B;
 mmGB_TILE_MODE24                                         =$265C;
 mmGB_TILE_MODE25                                         =$265D;
 mmGB_TILE_MODE26                                         =$265E;
 mmGB_TILE_MODE27                                         =$265F;
 mmGB_TILE_MODE28                                         =$2660;
 mmGB_TILE_MODE29                                         =$2661;
 mmGB_TILE_MODE30                                         =$2662;
 mmGB_TILE_MODE31                                         =$2663;
 mmGB_MACROTILE_MODE0                                     =$2664;
 mmGB_MACROTILE_MODE1                                     =$2665;
 mmGB_MACROTILE_MODE2                                     =$2666;
 mmGB_MACROTILE_MODE3                                     =$2667;
 mmGB_MACROTILE_MODE4                                     =$2668;
 mmGB_MACROTILE_MODE5                                     =$2669;
 mmGB_MACROTILE_MODE6                                     =$266A;
 mmGB_MACROTILE_MODE7                                     =$266B;
 mmGB_MACROTILE_MODE8                                     =$266C;
 mmGB_MACROTILE_MODE9                                     =$266D;
 mmGB_MACROTILE_MODE10                                    =$266E;
 mmGB_MACROTILE_MODE11                                    =$266F;
 mmGB_MACROTILE_MODE12                                    =$2670;
 mmGB_MACROTILE_MODE13                                    =$2671;
 mmGB_MACROTILE_MODE14                                    =$2672;
 mmGB_MACROTILE_MODE15                                    =$2673;
 mmCB_HW_CONTROL_3                                        =$2683;
 mmCB_HW_CONTROL                                          =$2684;
 mmCB_HW_CONTROL_1                                        =$2685;
 mmCB_HW_CONTROL_2                                        =$2686;
 mmCB_DCC_CONFIG                                          =$2687;
 mmCB_PERFCOUNTER0_SELECT0                                =$2688;
 mmCB_PERFCOUNTER1_SELECT0                                =$268A;
 mmCB_PERFCOUNTER1_SELECT1                                =$268B;
 mmCB_PERFCOUNTER2_SELECT0                                =$268C;
 mmCB_PERFCOUNTER2_SELECT1                                =$268D;
 mmCB_PERFCOUNTER3_SELECT0                                =$268E;
 mmCB_PERFCOUNTER3_SELECT1                                =$268F;
 mmCB_CGTT_SCLK_CTRL                                      =$2698;
 mmCB_DEBUG_BUS_1                                         =$2699;
 mmCB_DEBUG_BUS_2                                         =$269A;
 mmCB_DEBUG_BUS_13                                        =$26A5;
 mmCB_DEBUG_BUS_14                                        =$26A6;
 mmCB_DEBUG_BUS_15                                        =$26A7;
 mmCB_DEBUG_BUS_16                                        =$26A8;
 mmCB_DEBUG_BUS_17                                        =$26A9;
 mmCB_DEBUG_BUS_18                                        =$26AA;
 mmCB_DEBUG_BUS_19                                        =$26AB;
 mmCB_DEBUG_BUS_20                                        =$26AC;
 mmCB_DEBUG_BUS_21                                        =$26AD;
 mmCB_DEBUG_BUS_22                                        =$26AE;
 mmGC_USER_RB_REDUNDANCY                                  =$26DE;
 mmGC_USER_RB_BACKEND_DISABLE                             =$26DF;
 mmTCP_INVALIDATE                                         =$2B00;
 mmTCP_STATUS                                             =$2B01;
 mmTCP_CNTL                                               =$2B02;
 mmTCP_CHAN_STEER_LO                                      =$2B03;
 mmTCP_CHAN_STEER_HI                                      =$2B04;
 mmTCP_ADDR_CONFIG                                        =$2B05;
 mmTCP_CREDIT                                             =$2B06;
 mmCGTT_TCP_CLK_CTRL                                      =$2B15;
 mmTCP_BUFFER_ADDR_HASH_CNTL                              =$2B16;
 mmTCP_EDC_CNT                                            =$2B17;
 mmTC_CFG_L1_LOAD_POLICY0                                 =$2B1A;
 mmTC_CFG_L1_LOAD_POLICY1                                 =$2B1B;
 mmTC_CFG_L1_STORE_POLICY                                 =$2B1C;
 mmTC_CFG_L2_LOAD_POLICY0                                 =$2B1D;
 mmTC_CFG_L2_LOAD_POLICY1                                 =$2B1E;
 mmTC_CFG_L2_STORE_POLICY0                                =$2B1F;
 mmTC_CFG_L2_STORE_POLICY1                                =$2B20;
 mmTC_CFG_L2_ATOMIC_POLICY                                =$2B21;
 mmTC_CFG_L1_VOLATILE                                     =$2B22;
 mmTC_CFG_L2_VOLATILE                                     =$2B23;
 mmCGTT_TCI_CLK_CTRL                                      =$2B60;
 mmTCI_STATUS                                             =$2B61;
 mmTCI_CNTL_1                                             =$2B62;
 mmTCI_CNTL_2                                             =$2B63;
 mmTCC_CTRL                                               =$2B80;
 mmTCC_CGTT_SCLK_CTRL                                     =$2B81;
 mmTCC_EDC_CNT                                            =$2B82;
 mmTCC_REDUNDANCY                                         =$2B83;
 mmTCC_EXE_DISABLE                                        =$2B84;
 mmTCC_DSM_CNTL                                           =$2B85;
 mmTCA_CTRL                                               =$2BC0;
 mmTCA_CGTT_SCLK_CTRL                                     =$2BC1;
 mmSPI_SHADER_TBA_LO_PS                                   =$2C00;
 mmSPI_SHADER_TBA_HI_PS                                   =$2C01;
 mmSPI_SHADER_TMA_LO_PS                                   =$2C02;
 mmSPI_SHADER_TMA_HI_PS                                   =$2C03;
 mmSPI_SHADER_PGM_RSRC3_PS                                =$2C07;
 mmSPI_SHADER_PGM_LO_PS                                   =$2C08;
 mmSPI_SHADER_PGM_HI_PS                                   =$2C09;
 mmSPI_SHADER_PGM_RSRC1_PS                                =$2C0A;
 mmSPI_SHADER_PGM_RSRC2_PS                                =$2C0B;
 mmSPI_SHADER_USER_DATA_PS_0                              =$2C0C;
 mmSPI_SHADER_USER_DATA_PS_1                              =$2C0D;
 mmSPI_SHADER_USER_DATA_PS_2                              =$2C0E;
 mmSPI_SHADER_USER_DATA_PS_3                              =$2C0F;
 mmSPI_SHADER_USER_DATA_PS_4                              =$2C10;
 mmSPI_SHADER_USER_DATA_PS_5                              =$2C11;
 mmSPI_SHADER_USER_DATA_PS_6                              =$2C12;
 mmSPI_SHADER_USER_DATA_PS_7                              =$2C13;
 mmSPI_SHADER_USER_DATA_PS_8                              =$2C14;
 mmSPI_SHADER_USER_DATA_PS_9                              =$2C15;
 mmSPI_SHADER_USER_DATA_PS_10                             =$2C16;
 mmSPI_SHADER_USER_DATA_PS_11                             =$2C17;
 mmSPI_SHADER_USER_DATA_PS_12                             =$2C18;
 mmSPI_SHADER_USER_DATA_PS_13                             =$2C19;
 mmSPI_SHADER_USER_DATA_PS_14                             =$2C1A;
 mmSPI_SHADER_USER_DATA_PS_15                             =$2C1B;
 mmSPI_SHADER_TBA_LO_VS                                   =$2C40;
 mmSPI_SHADER_TBA_HI_VS                                   =$2C41;
 mmSPI_SHADER_TMA_LO_VS                                   =$2C42;
 mmSPI_SHADER_TMA_HI_VS                                   =$2C43;
 mmSPI_SHADER_PGM_RSRC3_VS                                =$2C46;
 mmSPI_SHADER_LATE_ALLOC_VS                               =$2C47;
 mmSPI_SHADER_PGM_LO_VS                                   =$2C48;
 mmSPI_SHADER_PGM_HI_VS                                   =$2C49;
 mmSPI_SHADER_PGM_RSRC1_VS                                =$2C4A;
 mmSPI_SHADER_PGM_RSRC2_VS                                =$2C4B;
 mmSPI_SHADER_USER_DATA_VS_0                              =$2C4C;
 mmSPI_SHADER_USER_DATA_VS_1                              =$2C4D;
 mmSPI_SHADER_USER_DATA_VS_2                              =$2C4E;
 mmSPI_SHADER_USER_DATA_VS_3                              =$2C4F;
 mmSPI_SHADER_USER_DATA_VS_4                              =$2C50;
 mmSPI_SHADER_USER_DATA_VS_5                              =$2C51;
 mmSPI_SHADER_USER_DATA_VS_6                              =$2C52;
 mmSPI_SHADER_USER_DATA_VS_7                              =$2C53;
 mmSPI_SHADER_USER_DATA_VS_8                              =$2C54;
 mmSPI_SHADER_USER_DATA_VS_9                              =$2C55;
 mmSPI_SHADER_USER_DATA_VS_10                             =$2C56;
 mmSPI_SHADER_USER_DATA_VS_11                             =$2C57;
 mmSPI_SHADER_USER_DATA_VS_12                             =$2C58;
 mmSPI_SHADER_USER_DATA_VS_13                             =$2C59;
 mmSPI_SHADER_USER_DATA_VS_14                             =$2C5A;
 mmSPI_SHADER_USER_DATA_VS_15                             =$2C5B;
 mmSPI_SHADER_PGM_RSRC2_ES_VS                             =$2C7C;
 mmSPI_SHADER_PGM_RSRC2_LS_VS                             =$2C7D;
 mmSPI_SHADER_TBA_LO_GS                                   =$2C80;
 mmSPI_SHADER_TBA_HI_GS                                   =$2C81;
 mmSPI_SHADER_TMA_LO_GS                                   =$2C82;
 mmSPI_SHADER_TMA_HI_GS                                   =$2C83;
 mmSPI_SHADER_PGM_RSRC3_GS                                =$2C87;
 mmSPI_SHADER_PGM_LO_GS                                   =$2C88;
 mmSPI_SHADER_PGM_HI_GS                                   =$2C89;
 mmSPI_SHADER_PGM_RSRC1_GS                                =$2C8A;
 mmSPI_SHADER_PGM_RSRC2_GS                                =$2C8B;
 mmSPI_SHADER_USER_DATA_GS_0                              =$2C8C;
 mmSPI_SHADER_USER_DATA_GS_1                              =$2C8D;
 mmSPI_SHADER_USER_DATA_GS_2                              =$2C8E;
 mmSPI_SHADER_USER_DATA_GS_3                              =$2C8F;
 mmSPI_SHADER_USER_DATA_GS_4                              =$2C90;
 mmSPI_SHADER_USER_DATA_GS_5                              =$2C91;
 mmSPI_SHADER_USER_DATA_GS_6                              =$2C92;
 mmSPI_SHADER_USER_DATA_GS_7                              =$2C93;
 mmSPI_SHADER_USER_DATA_GS_8                              =$2C94;
 mmSPI_SHADER_USER_DATA_GS_9                              =$2C95;
 mmSPI_SHADER_USER_DATA_GS_10                             =$2C96;
 mmSPI_SHADER_USER_DATA_GS_11                             =$2C97;
 mmSPI_SHADER_USER_DATA_GS_12                             =$2C98;
 mmSPI_SHADER_USER_DATA_GS_13                             =$2C99;
 mmSPI_SHADER_USER_DATA_GS_14                             =$2C9A;
 mmSPI_SHADER_USER_DATA_GS_15                             =$2C9B;
 mmSPI_SHADER_PGM_RSRC2_ES_GS                             =$2CBC;
 mmSPI_SHADER_TBA_LO_ES                                   =$2CC0;
 mmSPI_SHADER_TBA_HI_ES                                   =$2CC1;
 mmSPI_SHADER_TMA_LO_ES                                   =$2CC2;
 mmSPI_SHADER_TMA_HI_ES                                   =$2CC3;
 mmSPI_SHADER_PGM_RSRC3_ES                                =$2CC7;
 mmSPI_SHADER_PGM_LO_ES                                   =$2CC8;
 mmSPI_SHADER_PGM_HI_ES                                   =$2CC9;
 mmSPI_SHADER_PGM_RSRC1_ES                                =$2CCA;
 mmSPI_SHADER_PGM_RSRC2_ES                                =$2CCB;
 mmSPI_SHADER_USER_DATA_ES_0                              =$2CCC;
 mmSPI_SHADER_USER_DATA_ES_1                              =$2CCD;
 mmSPI_SHADER_USER_DATA_ES_2                              =$2CCE;
 mmSPI_SHADER_USER_DATA_ES_3                              =$2CCF;
 mmSPI_SHADER_USER_DATA_ES_4                              =$2CD0;
 mmSPI_SHADER_USER_DATA_ES_5                              =$2CD1;
 mmSPI_SHADER_USER_DATA_ES_6                              =$2CD2;
 mmSPI_SHADER_USER_DATA_ES_7                              =$2CD3;
 mmSPI_SHADER_USER_DATA_ES_8                              =$2CD4;
 mmSPI_SHADER_USER_DATA_ES_9                              =$2CD5;
 mmSPI_SHADER_USER_DATA_ES_10                             =$2CD6;
 mmSPI_SHADER_USER_DATA_ES_11                             =$2CD7;
 mmSPI_SHADER_USER_DATA_ES_12                             =$2CD8;
 mmSPI_SHADER_USER_DATA_ES_13                             =$2CD9;
 mmSPI_SHADER_USER_DATA_ES_14                             =$2CDA;
 mmSPI_SHADER_USER_DATA_ES_15                             =$2CDB;
 mmSPI_SHADER_PGM_RSRC2_LS_ES                             =$2CFD;
 mmSPI_SHADER_TBA_LO_HS                                   =$2D00;
 mmSPI_SHADER_TBA_HI_HS                                   =$2D01;
 mmSPI_SHADER_TMA_LO_HS                                   =$2D02;
 mmSPI_SHADER_TMA_HI_HS                                   =$2D03;
 mmSPI_SHADER_PGM_RSRC3_HS                                =$2D07;
 mmSPI_SHADER_PGM_LO_HS                                   =$2D08;
 mmSPI_SHADER_PGM_HI_HS                                   =$2D09;
 mmSPI_SHADER_PGM_RSRC1_HS                                =$2D0A;
 mmSPI_SHADER_PGM_RSRC2_HS                                =$2D0B;
 mmSPI_SHADER_USER_DATA_HS_0                              =$2D0C;
 mmSPI_SHADER_USER_DATA_HS_1                              =$2D0D;
 mmSPI_SHADER_USER_DATA_HS_2                              =$2D0E;
 mmSPI_SHADER_USER_DATA_HS_3                              =$2D0F;
 mmSPI_SHADER_USER_DATA_HS_4                              =$2D10;
 mmSPI_SHADER_USER_DATA_HS_5                              =$2D11;
 mmSPI_SHADER_USER_DATA_HS_6                              =$2D12;
 mmSPI_SHADER_USER_DATA_HS_7                              =$2D13;
 mmSPI_SHADER_USER_DATA_HS_8                              =$2D14;
 mmSPI_SHADER_USER_DATA_HS_9                              =$2D15;
 mmSPI_SHADER_USER_DATA_HS_10                             =$2D16;
 mmSPI_SHADER_USER_DATA_HS_11                             =$2D17;
 mmSPI_SHADER_USER_DATA_HS_12                             =$2D18;
 mmSPI_SHADER_USER_DATA_HS_13                             =$2D19;
 mmSPI_SHADER_USER_DATA_HS_14                             =$2D1A;
 mmSPI_SHADER_USER_DATA_HS_15                             =$2D1B;
 mmSPI_SHADER_PGM_RSRC2_LS_HS                             =$2D3D;
 mmSPI_SHADER_TBA_LO_LS                                   =$2D40;
 mmSPI_SHADER_TBA_HI_LS                                   =$2D41;
 mmSPI_SHADER_TMA_LO_LS                                   =$2D42;
 mmSPI_SHADER_TMA_HI_LS                                   =$2D43;
 mmSPI_SHADER_PGM_RSRC3_LS                                =$2D47;
 mmSPI_SHADER_PGM_LO_LS                                   =$2D48;
 mmSPI_SHADER_PGM_HI_LS                                   =$2D49;
 mmSPI_SHADER_PGM_RSRC1_LS                                =$2D4A;
 mmSPI_SHADER_PGM_RSRC2_LS                                =$2D4B;
 mmSPI_SHADER_USER_DATA_LS_0                              =$2D4C;
 mmSPI_SHADER_USER_DATA_LS_1                              =$2D4D;
 mmSPI_SHADER_USER_DATA_LS_2                              =$2D4E;
 mmSPI_SHADER_USER_DATA_LS_3                              =$2D4F;
 mmSPI_SHADER_USER_DATA_LS_4                              =$2D50;
 mmSPI_SHADER_USER_DATA_LS_5                              =$2D51;
 mmSPI_SHADER_USER_DATA_LS_6                              =$2D52;
 mmSPI_SHADER_USER_DATA_LS_7                              =$2D53;
 mmSPI_SHADER_USER_DATA_LS_8                              =$2D54;
 mmSPI_SHADER_USER_DATA_LS_9                              =$2D55;
 mmSPI_SHADER_USER_DATA_LS_10                             =$2D56;
 mmSPI_SHADER_USER_DATA_LS_11                             =$2D57;
 mmSPI_SHADER_USER_DATA_LS_12                             =$2D58;
 mmSPI_SHADER_USER_DATA_LS_13                             =$2D59;
 mmSPI_SHADER_USER_DATA_LS_14                             =$2D5A;
 mmSPI_SHADER_USER_DATA_LS_15                             =$2D5B;
 mmCOMPUTE_DISPATCH_INITIATOR                             =$2E00;
 mmCOMPUTE_DIM_X                                          =$2E01;
 mmCOMPUTE_DIM_Y                                          =$2E02;
 mmCOMPUTE_DIM_Z                                          =$2E03;
 mmCOMPUTE_START_X                                        =$2E04;
 mmCOMPUTE_START_Y                                        =$2E05;
 mmCOMPUTE_START_Z                                        =$2E06;
 mmCOMPUTE_NUM_THREAD_X                                   =$2E07;
 mmCOMPUTE_NUM_THREAD_Y                                   =$2E08;
 mmCOMPUTE_NUM_THREAD_Z                                   =$2E09;
 mmCOMPUTE_PIPELINESTAT_ENABLE                            =$2E0A;
 mmCOMPUTE_PERFCOUNT_ENABLE                               =$2E0B;
 mmCOMPUTE_PGM_LO                                         =$2E0C;
 mmCOMPUTE_PGM_HI                                         =$2E0D;
 mmCOMPUTE_TBA_LO                                         =$2E0E;
 mmCOMPUTE_TBA_HI                                         =$2E0F;
 mmCOMPUTE_TMA_LO                                         =$2E10;
 mmCOMPUTE_TMA_HI                                         =$2E11;
 mmCOMPUTE_PGM_RSRC1                                      =$2E12;
 mmCOMPUTE_PGM_RSRC2                                      =$2E13;
 mmCOMPUTE_VMID                                           =$2E14;
 mmCOMPUTE_RESOURCE_LIMITS                                =$2E15;
 mmCOMPUTE_STATIC_THREAD_MGMT_SE0                         =$2E16;
 mmCOMPUTE_STATIC_THREAD_MGMT_SE1                         =$2E17;
 mmCOMPUTE_TMPRING_SIZE                                   =$2E18;
 mmCOMPUTE_STATIC_THREAD_MGMT_SE2                         =$2E19;
 mmCOMPUTE_STATIC_THREAD_MGMT_SE3                         =$2E1A;
 mmCOMPUTE_RESTART_X                                      =$2E1B;
 mmCOMPUTE_RESTART_Y                                      =$2E1C;
 mmCOMPUTE_RESTART_Z                                      =$2E1D;
 mmCOMPUTE_THREAD_TRACE_ENABLE                            =$2E1E;
 mmCOMPUTE_MISC_RESERVED                                  =$2E1F;
 mmCOMPUTE_DISPATCH_ID                                    =$2E20;
 mmCOMPUTE_THREADGROUP_ID                                 =$2E21;
 mmCOMPUTE_RELAUNCH                                       =$2E22;
 mmCOMPUTE_WAVE_RESTORE_ADDR_LO                           =$2E23;
 mmCOMPUTE_WAVE_RESTORE_ADDR_HI                           =$2E24;
 mmCOMPUTE_WAVE_RESTORE_CONTROL                           =$2E25;
 mmCOMPUTE_USER_DATA_0                                    =$2E40;
 mmCOMPUTE_USER_DATA_1                                    =$2E41;
 mmCOMPUTE_USER_DATA_2                                    =$2E42;
 mmCOMPUTE_USER_DATA_3                                    =$2E43;
 mmCOMPUTE_USER_DATA_4                                    =$2E44;
 mmCOMPUTE_USER_DATA_5                                    =$2E45;
 mmCOMPUTE_USER_DATA_6                                    =$2E46;
 mmCOMPUTE_USER_DATA_7                                    =$2E47;
 mmCOMPUTE_USER_DATA_8                                    =$2E48;
 mmCOMPUTE_USER_DATA_9                                    =$2E49;
 mmCOMPUTE_USER_DATA_10                                   =$2E4A;
 mmCOMPUTE_USER_DATA_11                                   =$2E4B;
 mmCOMPUTE_USER_DATA_12                                   =$2E4C;
 mmCOMPUTE_USER_DATA_13                                   =$2E4D;
 mmCOMPUTE_USER_DATA_14                                   =$2E4E;
 mmCOMPUTE_USER_DATA_15                                   =$2E4F;
 mmCOMPUTE_NOWHERE                                        =$2E7F;
 mmCP_DFY_CNTL                                            =$3020;
 mmCP_DFY_STAT                                            =$3021;
 mmCP_DFY_ADDR_HI                                         =$3022;
 mmCP_DFY_ADDR_LO                                         =$3023;
 mmCP_DFY_DATA_0                                          =$3024;
 mmCP_DFY_DATA_1                                          =$3025;
 mmCP_DFY_DATA_2                                          =$3026;
 mmCP_DFY_DATA_3                                          =$3027;
 mmCP_DFY_DATA_4                                          =$3028;
 mmCP_DFY_DATA_5                                          =$3029;
 mmCP_DFY_DATA_6                                          =$302A;
 mmCP_DFY_DATA_7                                          =$302B;
 mmCP_DFY_DATA_8                                          =$302C;
 mmCP_DFY_DATA_9                                          =$302D;
 mmCP_DFY_DATA_10                                         =$302E;
 mmCP_DFY_DATA_11                                         =$302F;
 mmCP_DFY_DATA_12                                         =$3030;
 mmCP_DFY_DATA_13                                         =$3031;
 mmCP_DFY_DATA_14                                         =$3032;
 mmCP_DFY_DATA_15                                         =$3033;
 mmCP_DFY_CMD                                             =$3034;
 mmCP_CPC_MGCG_SYNC_CNTL                                  =$3036;
 mmCP_VIRT_STATUS                                         =$3038;
 mmCP_RB0_BASE                                            =$3040;
 mmCP_RB0_CNTL                                            =$3041;
 mmCP_RB_RPTR_WR                                          =$3042;
 mmCP_RB0_RPTR_ADDR                                       =$3043;
 mmCP_RB0_RPTR_ADDR_HI                                    =$3044;
 mmCP_RB0_WPTR                                            =$3045;
 mmCP_RB_WPTR_POLL_ADDR_LO                                =$3046;
 mmCP_RB_WPTR_POLL_ADDR_HI                                =$3047;
 mmCP_INT_CNTL                                            =$3049;
 mmCP_INT_STATUS                                          =$304A;
 mmCP_DEVICE_ID                                           =$304B;
 mmCP_ME0_PIPE_PRIORITY_CNTS                              =$304C;
 mmCP_ME0_PIPE0_PRIORITY                                  =$304D;
 mmCP_ME0_PIPE1_PRIORITY                                  =$304E;
 mmCP_ME0_PIPE2_PRIORITY                                  =$304F;
 mmCP_ENDIAN_SWAP                                         =$3050;
 mmCP_RB_VMID                                             =$3051;
 mmCP_ME0_PIPE0_VMID                                      =$3052;
 mmCP_ME0_PIPE1_VMID                                      =$3053;
 mmCP_RB_DOORBELL_CONTROL                                 =$3059;
 mmCP_RB_DOORBELL_RANGE_LOWER                             =$305A;
 mmCP_RB_DOORBELL_RANGE_UPPER                             =$305B;
 mmCP_MEC_DOORBELL_RANGE_LOWER                            =$305C;
 mmCP_MEC_DOORBELL_RANGE_UPPER                            =$305D;
 mmCP_RB1_BASE                                            =$3060;
 mmCP_RB1_CNTL                                            =$3061;
 mmCP_RB1_RPTR_ADDR                                       =$3062;
 mmCP_RB1_RPTR_ADDR_HI                                    =$3063;
 mmCP_RB1_WPTR                                            =$3064;
 mmCP_RB2_BASE                                            =$3065;
 mmCP_RB2_CNTL                                            =$3066;
 mmCP_RB2_RPTR_ADDR                                       =$3067;
 mmCP_RB2_RPTR_ADDR_HI                                    =$3068;
 mmCP_RB2_WPTR                                            =$3069;
 mmCP_INT_CNTL_RING0                                      =$306A;
 mmCP_INT_CNTL_RING1                                      =$306B;
 mmCP_INT_CNTL_RING2                                      =$306C;
 mmCP_INT_STATUS_RING0                                    =$306D;
 mmCP_INT_STATUS_RING1                                    =$306E;
 mmCP_INT_STATUS_RING2                                    =$306F;
 mmCP_PWR_CNTL                                            =$3078;
 mmCP_MEM_SLP_CNTL                                        =$3079;
 mmCP_ECC_FIRSTOCCURRENCE                                 =$307A;
 mmCP_ECC_FIRSTOCCURRENCE_RING0                           =$307B;
 mmCP_ECC_FIRSTOCCURRENCE_RING1                           =$307C;
 mmCP_ECC_FIRSTOCCURRENCE_RING2                           =$307D;
 mmGB_EDC_MODE                                            =$307E;
 mmCP_DEBUG                                               =$307F;
 mmCP_PQ_WPTR_POLL_CNTL                                   =$3083;
 mmCP_PQ_WPTR_POLL_CNTL1                                  =$3084;
 mmCP_ME1_PIPE0_INT_CNTL                                  =$3085;
 mmCP_ME1_PIPE1_INT_CNTL                                  =$3086;
 mmCP_ME1_PIPE2_INT_CNTL                                  =$3087;
 mmCP_ME1_PIPE3_INT_CNTL                                  =$3088;
 mmCP_ME2_PIPE0_INT_CNTL                                  =$3089;
 mmCP_ME2_PIPE1_INT_CNTL                                  =$308A;
 mmCP_ME2_PIPE2_INT_CNTL                                  =$308B;
 mmCP_ME2_PIPE3_INT_CNTL                                  =$308C;
 mmCP_ME1_PIPE0_INT_STATUS                                =$308D;
 mmCP_ME1_PIPE1_INT_STATUS                                =$308E;
 mmCP_ME1_PIPE2_INT_STATUS                                =$308F;
 mmCP_ME1_PIPE3_INT_STATUS                                =$3090;
 mmCP_ME2_PIPE0_INT_STATUS                                =$3091;
 mmCP_ME2_PIPE1_INT_STATUS                                =$3092;
 mmCP_ME2_PIPE2_INT_STATUS                                =$3093;
 mmCP_ME2_PIPE3_INT_STATUS                                =$3094;
 mmCP_ME1_INT_STAT_DEBUG                                  =$3095;
 mmCP_ME2_INT_STAT_DEBUG                                  =$3096;
 mmCC_GC_EDC_CONFIG                                       =$3098;
 mmCP_ME1_PIPE_PRIORITY_CNTS                              =$3099;
 mmCP_ME1_PIPE0_PRIORITY                                  =$309A;
 mmCP_ME1_PIPE1_PRIORITY                                  =$309B;
 mmCP_ME1_PIPE2_PRIORITY                                  =$309C;
 mmCP_ME1_PIPE3_PRIORITY                                  =$309D;
 mmCP_ME2_PIPE_PRIORITY_CNTS                              =$309E;
 mmCP_ME2_PIPE0_PRIORITY                                  =$309F;
 mmCP_ME2_PIPE1_PRIORITY                                  =$30A0;
 mmCP_ME2_PIPE2_PRIORITY                                  =$30A1;
 mmCP_ME2_PIPE3_PRIORITY                                  =$30A2;
 mmCP_CE_PRGRM_CNTR_START                                 =$30A3;
 mmCP_PFP_PRGRM_CNTR_START                                =$30A4;
 mmCP_ME_PRGRM_CNTR_START                                 =$30A5;
 mmCP_MEC1_PRGRM_CNTR_START                               =$30A6;
 mmCP_MEC2_PRGRM_CNTR_START                               =$30A7;
 mmCP_CE_INTR_ROUTINE_START                               =$30A8;
 mmCP_PFP_INTR_ROUTINE_START                              =$30A9;
 mmCP_ME_INTR_ROUTINE_START                               =$30AA;
 mmCP_MEC1_INTR_ROUTINE_START                             =$30AB;
 mmCP_MEC2_INTR_ROUTINE_START                             =$30AC;
 mmCP_CONTEXT_CNTL                                        =$30AD;
 mmCP_MAX_CONTEXT                                         =$30AE;
 mmCP_IQ_WAIT_TIME1                                       =$30AF;
 mmCP_IQ_WAIT_TIME2                                       =$30B0;
 mmCP_RB0_BASE_HI                                         =$30B1;
 mmCP_RB1_BASE_HI                                         =$30B2;
 mmCP_VMID_RESET                                          =$30B3;
 mmCPC_INT_CNTL                                           =$30B4;
 mmCPC_INT_STATUS                                         =$30B5;
 mmCP_VMID_PREEMPT                                        =$30B6;
 mmCPC_INT_CNTX_ID                                        =$30B7;
 mmCP_PQ_STATUS                                           =$30B8;
 mmCP_CPC_IC_BASE_LO                                      =$30B9;
 mmCP_CPC_IC_BASE_HI                                      =$30BA;
 mmCP_CPC_IC_BASE_CNTL                                    =$30BB;
 mmCP_CPC_IC_OP_CNTL                                      =$30BC;
 mmCP_MEC1_F32_INT_DIS                                    =$30BD;
 mmCP_MEC2_F32_INT_DIS                                    =$30BE;
 mmCP_VMID_STATUS                                         =$30BF;
 mmRLC_LB_CNTL                                            =$30C3;
 mmRLC_SAVE_AND_RESTORE_BASE                              =$30C4;
 mmRLC_LB_CNTR_MAX                                        =$30C5;
 mmRLC_LB_CNTR_INIT                                       =$30C6;
 mmRLC_DRIVER_CPDMA_STATUS                                =$30C7;
 mmRLC_DEBUG_SELECT                                       =$30C9;
 mmRLC_DEBUG                                              =$30CA;
 mmRLC_GPU_CLOCK_COUNT_LSB                                =$30CE;
 mmRLC_GPU_CLOCK_COUNT_MSB                                =$30CF;
 mmRLC_CAPTURE_GPU_CLOCK_COUNT                            =$30D0;
 mmRLC_MC_CNTL                                            =$30D1;
 mmRLC_UCODE_CNTL                                         =$30D2;
 mmRLC_STAT                                               =$30D3;
 mmRLC_GPU_CLOCK_32_RES_SEL                               =$30D4;
 mmRLC_GPU_CLOCK_32                                       =$30D5;
 mmRLC_SOFT_RESET_GPU                                     =$30D6;
 mmRLC_PG_CNTL                                            =$30D7;
 mmRLC_MEM_SLP_CNTL                                       =$30D8;
 mmRLC_PERFMON_CNTL                                       =$30D9;
 mmRLC_PERFCOUNTER0_SELECT                                =$30DA;
 mmRLC_PERFCOUNTER1_SELECT                                =$30DD;
 mmCGTT_RLC_CLK_CTRL                                      =$30E0;
 mmRLC_LOAD_BALANCE_CNTR                                  =$30F6;
 mmRLC_CGTT_MGCG_OVERRIDE                                 =$3100;
 mmRLC_CGCG_CGLS_CTRL                                     =$3101;
 mmRLC_CGCG_RAMP_CTRL                                     =$3102;
 mmRLC_DYN_PG_STATUS                                      =$3103;
 mmRLC_DYN_PG_REQUEST                                     =$3104;
 mmRLC_CU_STATUS                                          =$3106;
 mmRLC_LB_INIT_CU_MASK                                    =$3107;
 mmRLC_LB_ALWAYS_ACTIVE_CU_MASK                           =$3108;
 mmRLC_LB_PARAMS                                          =$3109;
 mmRLC_THREAD1_DELAY                                      =$310A;
 mmRLC_PG_ALWAYS_ON_CU_MASK                               =$310B;
 mmRLC_MAX_PG_CU                                          =$310C;
 mmRLC_AUTO_PG_CTRL                                       =$310D;
 mmRLC_SMU_GRBM_REG_SAVE_CTRL                             =$310E;
 mmRLC_SMU_PG_CTRL                                        =$310F;
 mmRLC_SMU_PG_WAKE_UP_CTRL                                =$3110;
 mmRLC_SERDES_RD_MASTER_INDEX                             =$3111;
 mmRLC_SERDES_RD_DATA_0                                   =$3112;
 mmRLC_SERDES_RD_DATA_1                                   =$3113;
 mmRLC_SERDES_RD_DATA_2                                   =$3114;
 mmRLC_SERDES_WR_CTRL                                     =$3117;
 mmRLC_SERDES_WR_DATA                                     =$3118;
 mmSPI_ARB_PRIORITY                                       =$31C0;
 mmSPI_ARB_CYCLES_0                                       =$31C1;
 mmSPI_ARB_CYCLES_1                                       =$31C2;
 mmSPI_CDBG_SYS_GFX                                       =$31C3;
 mmSPI_CDBG_SYS_HP3D                                      =$31C4;
 mmSPI_CDBG_SYS_CS0                                       =$31C5;
 mmSPI_CDBG_SYS_CS1                                       =$31C6;
 mmSPI_WCL_PIPE_PERCENT_GFX                               =$31C7;
 mmSPI_WCL_PIPE_PERCENT_HP3D                              =$31C8;
 mmSPI_WCL_PIPE_PERCENT_CS0                               =$31C9;
 mmSPI_WCL_PIPE_PERCENT_CS1                               =$31CA;
 mmSPI_WCL_PIPE_PERCENT_CS2                               =$31CB;
 mmSPI_WCL_PIPE_PERCENT_CS3                               =$31CC;
 mmSPI_WCL_PIPE_PERCENT_CS4                               =$31CD;
 mmSPI_WCL_PIPE_PERCENT_CS5                               =$31CE;
 mmSPI_WCL_PIPE_PERCENT_CS6                               =$31CF;
 mmSPI_WCL_PIPE_PERCENT_CS7                               =$31D0;
 mmSPI_GDBG_WAVE_CNTL                                     =$31D1;
 mmSPI_GDBG_TRAP_CONFIG                                   =$31D2;
 mmSPI_GDBG_TRAP_MASK                                     =$31D3;
 mmSPI_GDBG_TBA_LO                                        =$31D4;
 mmSPI_GDBG_TBA_HI                                        =$31D5;
 mmSPI_GDBG_TMA_LO                                        =$31D6;
 mmSPI_GDBG_TMA_HI                                        =$31D7;
 mmSPI_GDBG_TRAP_DATA0                                    =$31D8;
 mmSPI_GDBG_TRAP_DATA1                                    =$31D9;
 mmSPI_RESET_DEBUG                                        =$31DA;
 mmSPI_COMPUTE_QUEUE_RESET                                =$31DB;
 mmSPI_RESOURCE_RESERVE_CU_0                              =$31DC;
 mmSPI_RESOURCE_RESERVE_CU_1                              =$31DD;
 mmSPI_RESOURCE_RESERVE_CU_2                              =$31DE;
 mmSPI_RESOURCE_RESERVE_CU_3                              =$31DF;
 mmSPI_RESOURCE_RESERVE_CU_4                              =$31E0;
 mmSPI_RESOURCE_RESERVE_CU_5                              =$31E1;
 mmSPI_RESOURCE_RESERVE_CU_6                              =$31E2;
 mmSPI_RESOURCE_RESERVE_CU_7                              =$31E3;
 mmSPI_RESOURCE_RESERVE_CU_8                              =$31E4;
 mmSPI_RESOURCE_RESERVE_CU_9                              =$31E5;
 mmSPI_RESOURCE_RESERVE_EN_CU_0                           =$31E6;
 mmSPI_RESOURCE_RESERVE_EN_CU_1                           =$31E7;
 mmSPI_RESOURCE_RESERVE_EN_CU_2                           =$31E8;
 mmSPI_RESOURCE_RESERVE_EN_CU_3                           =$31E9;
 mmSPI_RESOURCE_RESERVE_EN_CU_4                           =$31EA;
 mmSPI_RESOURCE_RESERVE_EN_CU_5                           =$31EB;
 mmSPI_RESOURCE_RESERVE_EN_CU_6                           =$31EC;
 mmSPI_RESOURCE_RESERVE_EN_CU_7                           =$31ED;
 mmSPI_RESOURCE_RESERVE_EN_CU_8                           =$31EE;
 mmSPI_RESOURCE_RESERVE_EN_CU_9                           =$31EF;
 mmSPI_RESOURCE_RESERVE_CU_10                             =$31F0;
 mmSPI_RESOURCE_RESERVE_CU_11                             =$31F1;
 mmSPI_RESOURCE_RESERVE_EN_CU_10                          =$31F2;
 mmSPI_RESOURCE_RESERVE_EN_CU_11                          =$31F3;
 mmSPI_RESOURCE_RESERVE_CU_12                             =$31F4;
 mmSPI_RESOURCE_RESERVE_CU_13                             =$31F5;
 mmSPI_RESOURCE_RESERVE_CU_14                             =$31F6;
 mmSPI_RESOURCE_RESERVE_CU_15                             =$31F7;
 mmSPI_RESOURCE_RESERVE_EN_CU_12                          =$31F8;
 mmSPI_RESOURCE_RESERVE_EN_CU_13                          =$31F9;
 mmSPI_RESOURCE_RESERVE_EN_CU_14                          =$31FA;
 mmSPI_RESOURCE_RESERVE_EN_CU_15                          =$31FB;
 mmSPI_COMPUTE_WF_CTX_SAVE                                =$31FC;
 mmCP_HPD_ROQ_OFFSETS                                     =$3240;
 mmCP_HPD_STATUS0                                         =$3241;
 mmCP_MQD_BASE_ADDR                                       =$3245;
 mmCP_MQD_BASE_ADDR_HI                                    =$3246;
 mmCP_HQD_ACTIVE                                          =$3247;
 mmCP_HQD_VMID                                            =$3248;
 mmCP_HQD_PERSISTENT_STATE                                =$3249;
 mmCP_HQD_PIPE_PRIORITY                                   =$324A;
 mmCP_HQD_QUEUE_PRIORITY                                  =$324B;
 mmCP_HQD_QUANTUM                                         =$324C;
 mmCP_HQD_PQ_BASE                                         =$324D;
 mmCP_HQD_PQ_BASE_HI                                      =$324E;
 mmCP_HQD_PQ_RPTR                                         =$324F;
 mmCP_HQD_PQ_RPTR_REPORT_ADDR                             =$3250;
 mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                          =$3251;
 mmCP_HQD_PQ_WPTR_POLL_ADDR                               =$3252;
 mmCP_HQD_PQ_WPTR_POLL_ADDR_HI                            =$3253;
 mmCP_HQD_PQ_DOORBELL_CONTROL                             =$3254;
 mmCP_HQD_PQ_WPTR                                         =$3255;
 mmCP_HQD_PQ_CONTROL                                      =$3256;
 mmCP_HQD_IB_BASE_ADDR                                    =$3257;
 mmCP_HQD_IB_BASE_ADDR_HI                                 =$3258;
 mmCP_HQD_IB_RPTR                                         =$3259;
 mmCP_HQD_IB_CONTROL                                      =$325A;
 mmCP_HQD_IQ_TIMER                                        =$325B;
 mmCP_HQD_IQ_RPTR                                         =$325C;
 mmCP_HQD_DEQUEUE_REQUEST                                 =$325D;
 mmCP_HQD_DMA_OFFLOAD                                     =$325E;
 mmCP_HQD_SEMA_CMD                                        =$325F;
 mmCP_HQD_MSG_TYPE                                        =$3260;
 mmCP_HQD_ATOMIC0_PREOP_LO                                =$3261;
 mmCP_HQD_ATOMIC0_PREOP_HI                                =$3262;
 mmCP_HQD_ATOMIC1_PREOP_LO                                =$3263;
 mmCP_HQD_ATOMIC1_PREOP_HI                                =$3264;
 mmCP_HQD_HQ_SCHEDULER0                                   =$3265;
 mmCP_HQD_HQ_SCHEDULER1                                   =$3266;
 mmCP_MQD_CONTROL                                         =$3267;
 mmCP_HQD_HQ_STATUS1                                      =$3268;
 mmCP_HQD_HQ_CONTROL1                                     =$3269;
 mmCP_HQD_EOP_BASE_ADDR                                   =$326A;
 mmCP_HQD_EOP_BASE_ADDR_HI                                =$326B;
 mmCP_HQD_EOP_CONTROL                                     =$326C;
 mmCP_HQD_EOP_RPTR                                        =$326D;
 mmCP_HQD_EOP_WPTR                                        =$326E;
 mmCP_HQD_EOP_EVENTS                                      =$326F;
 mmCP_HQD_CTX_SAVE_BASE_ADDR_LO                           =$3270;
 mmCP_HQD_CTX_SAVE_BASE_ADDR_HI                           =$3271;
 mmCP_HQD_CTX_SAVE_CONTROL                                =$3272;
 mmCP_HQD_CNTL_STACK_OFFSET                               =$3273;
 mmCP_HQD_CNTL_STACK_SIZE                                 =$3274;
 mmCP_HQD_WG_STATE_OFFSET                                 =$3275;
 mmCP_HQD_CTX_SAVE_SIZE                                   =$3276;
 mmCP_HQD_GDS_RESOURCE_STATE                              =$3277;
 mmCP_HQD_ERROR                                           =$3278;
 mmCP_HQD_EOP_WPTR_MEM                                    =$3279;
 mmCP_HQD_EOP_DONES                                       =$327A;
 mmDIDT_IND_INDEX                                         =$3280;
 mmDIDT_IND_DATA                                          =$3281;
 mmGC_CAC_CGTT_CLK_CTRL                                   =$3292;
 mmSE_CAC_CGTT_CLK_CTRL                                   =$3293;
 mmGC_CAC_LKG_AGGR_LOWER                                  =$3296;
 mmGC_CAC_LKG_AGGR_UPPER                                  =$3297;
 mmTCP_WATCH0_ADDR_H                                      =$32A0;
 mmTCP_WATCH0_ADDR_L                                      =$32A1;
 mmTCP_WATCH0_CNTL                                        =$32A2;
 mmTCP_WATCH1_ADDR_H                                      =$32A3;
 mmTCP_WATCH1_ADDR_L                                      =$32A4;
 mmTCP_WATCH1_CNTL                                        =$32A5;
 mmTCP_WATCH2_ADDR_H                                      =$32A6;
 mmTCP_WATCH2_ADDR_L                                      =$32A7;
 mmTCP_WATCH2_CNTL                                        =$32A8;
 mmTCP_WATCH3_ADDR_H                                      =$32A9;
 mmTCP_WATCH3_ADDR_L                                      =$32AA;
 mmTCP_WATCH3_CNTL                                        =$32AB;
 mmTCP_GATCL1_CNTL                                        =$32B0;
 mmTCP_ATC_EDC_GATCL1_CNT                                 =$32B1;
 mmTCP_GATCL1_DSM_CNTL                                    =$32B2;
 mmTCP_DSM_CNTL                                           =$32B3;
 mmTCP_CNTL2                                              =$32B4;
 mmGDS_VMID0_BASE                                         =$3300;
 mmGDS_VMID0_SIZE                                         =$3301;
 mmGDS_VMID1_BASE                                         =$3302;
 mmGDS_VMID1_SIZE                                         =$3303;
 mmGDS_VMID2_BASE                                         =$3304;
 mmGDS_VMID2_SIZE                                         =$3305;
 mmGDS_VMID3_BASE                                         =$3306;
 mmGDS_VMID3_SIZE                                         =$3307;
 mmGDS_VMID4_BASE                                         =$3308;
 mmGDS_VMID4_SIZE                                         =$3309;
 mmGDS_VMID5_BASE                                         =$330A;
 mmGDS_VMID5_SIZE                                         =$330B;
 mmGDS_VMID6_BASE                                         =$330C;
 mmGDS_VMID6_SIZE                                         =$330D;
 mmGDS_VMID7_BASE                                         =$330E;
 mmGDS_VMID7_SIZE                                         =$330F;
 mmGDS_VMID8_BASE                                         =$3310;
 mmGDS_VMID8_SIZE                                         =$3311;
 mmGDS_VMID9_BASE                                         =$3312;
 mmGDS_VMID9_SIZE                                         =$3313;
 mmGDS_VMID10_BASE                                        =$3314;
 mmGDS_VMID10_SIZE                                        =$3315;
 mmGDS_VMID11_BASE                                        =$3316;
 mmGDS_VMID11_SIZE                                        =$3317;
 mmGDS_VMID12_BASE                                        =$3318;
 mmGDS_VMID12_SIZE                                        =$3319;
 mmGDS_VMID13_BASE                                        =$331A;
 mmGDS_VMID13_SIZE                                        =$331B;
 mmGDS_VMID14_BASE                                        =$331C;
 mmGDS_VMID14_SIZE                                        =$331D;
 mmGDS_VMID15_BASE                                        =$331E;
 mmGDS_VMID15_SIZE                                        =$331F;
 mmGDS_GWS_VMID0                                          =$3320;
 mmGDS_GWS_VMID1                                          =$3321;
 mmGDS_GWS_VMID2                                          =$3322;
 mmGDS_GWS_VMID3                                          =$3323;
 mmGDS_GWS_VMID4                                          =$3324;
 mmGDS_GWS_VMID5                                          =$3325;
 mmGDS_GWS_VMID6                                          =$3326;
 mmGDS_GWS_VMID7                                          =$3327;
 mmGDS_GWS_VMID8                                          =$3328;
 mmGDS_GWS_VMID9                                          =$3329;
 mmGDS_GWS_VMID10                                         =$332A;
 mmGDS_GWS_VMID11                                         =$332B;
 mmGDS_GWS_VMID12                                         =$332C;
 mmGDS_GWS_VMID13                                         =$332D;
 mmGDS_GWS_VMID14                                         =$332E;
 mmGDS_GWS_VMID15                                         =$332F;
 mmGDS_OA_VMID0                                           =$3330;
 mmGDS_OA_VMID1                                           =$3331;
 mmGDS_OA_VMID2                                           =$3332;
 mmGDS_OA_VMID3                                           =$3333;
 mmGDS_OA_VMID4                                           =$3334;
 mmGDS_OA_VMID5                                           =$3335;
 mmGDS_OA_VMID6                                           =$3336;
 mmGDS_OA_VMID7                                           =$3337;
 mmGDS_OA_VMID8                                           =$3338;
 mmGDS_OA_VMID9                                           =$3339;
 mmGDS_OA_VMID10                                          =$333A;
 mmGDS_OA_VMID11                                          =$333B;
 mmGDS_OA_VMID12                                          =$333C;
 mmGDS_OA_VMID13                                          =$333D;
 mmGDS_OA_VMID14                                          =$333E;
 mmGDS_OA_VMID15                                          =$333F;
 mmGDS_GWS_RESET0                                         =$3344;
 mmGDS_GWS_RESET1                                         =$3345;
 mmGDS_GWS_RESOURCE_RESET                                 =$3346;
 mmGDS_COMPUTE_MAX_WAVE_ID                                =$3348;
 mmGDS_OA_RESET_MASK                                      =$3349;
 mmGDS_OA_RESET                                           =$334A;
 mmGDS_ENHANCE                                            =$334B;
 mmGDS_OA_CGPG_RESTORE                                    =$334C;
 mmGDS_CS_CTXSW_STATUS                                    =$334D;
 mmGDS_CS_CTXSW_CNT0                                      =$334E;
 mmGDS_CS_CTXSW_CNT1                                      =$334F;
 mmGDS_CS_CTXSW_CNT2                                      =$3350;
 mmGDS_CS_CTXSW_CNT3                                      =$3351;
 mmGDS_GFX_CTXSW_STATUS                                   =$3352;
 mmGDS_VS_CTXSW_CNT0                                      =$3353;
 mmGDS_VS_CTXSW_CNT1                                      =$3354;
 mmGDS_VS_CTXSW_CNT2                                      =$3355;
 mmGDS_VS_CTXSW_CNT3                                      =$3356;
 mmGDS_PS0_CTXSW_CNT0                                     =$3357;
 mmGDS_PS0_CTXSW_CNT1                                     =$3358;
 mmGDS_PS0_CTXSW_CNT2                                     =$3359;
 mmGDS_PS0_CTXSW_CNT3                                     =$335A;
 mmGDS_PS1_CTXSW_CNT0                                     =$335B;
 mmGDS_PS1_CTXSW_CNT1                                     =$335C;
 mmGDS_PS1_CTXSW_CNT2                                     =$335D;
 mmGDS_PS1_CTXSW_CNT3                                     =$335E;
 mmGDS_PS2_CTXSW_CNT0                                     =$335F;
 mmGDS_PS2_CTXSW_CNT1                                     =$3360;
 mmGDS_PS2_CTXSW_CNT2                                     =$3361;
 mmGDS_PS2_CTXSW_CNT3                                     =$3362;
 mmGDS_PS3_CTXSW_CNT0                                     =$3363;
 mmGDS_PS3_CTXSW_CNT1                                     =$3364;
 mmGDS_PS3_CTXSW_CNT2                                     =$3365;
 mmGDS_PS3_CTXSW_CNT3                                     =$3366;
 mmGDS_PS4_CTXSW_CNT0                                     =$3367;
 mmGDS_PS4_CTXSW_CNT1                                     =$3368;
 mmGDS_PS4_CTXSW_CNT2                                     =$3369;
 mmGDS_PS4_CTXSW_CNT3                                     =$336A;
 mmGDS_PS5_CTXSW_CNT0                                     =$336B;
 mmGDS_PS5_CTXSW_CNT1                                     =$336C;
 mmGDS_PS5_CTXSW_CNT2                                     =$336D;
 mmGDS_PS5_CTXSW_CNT3                                     =$336E;
 mmGDS_PS6_CTXSW_CNT0                                     =$336F;
 mmGDS_PS6_CTXSW_CNT1                                     =$3370;
 mmGDS_PS6_CTXSW_CNT2                                     =$3371;
 mmGDS_PS6_CTXSW_CNT3                                     =$3372;
 mmGDS_PS7_CTXSW_CNT0                                     =$3373;
 mmGDS_PS7_CTXSW_CNT1                                     =$3374;
 mmGDS_PS7_CTXSW_CNT2                                     =$3375;
 mmGDS_PS7_CTXSW_CNT3                                     =$3376;
 mmRAS_SIGNATURE_CONTROL                                  =$3380;
 mmRAS_SIGNATURE_MASK                                     =$3381;
 mmRAS_SX_SIGNATURE0                                      =$3382;
 mmRAS_SX_SIGNATURE1                                      =$3383;
 mmRAS_SX_SIGNATURE2                                      =$3384;
 mmRAS_SX_SIGNATURE3                                      =$3385;
 mmRAS_DB_SIGNATURE0                                      =$338B;
 mmRAS_PA_SIGNATURE0                                      =$338C;
 mmRAS_VGT_SIGNATURE0                                     =$338D;
 mmRAS_SQ_SIGNATURE0                                      =$338E;
 mmRAS_SC_SIGNATURE0                                      =$338F;
 mmRAS_SC_SIGNATURE1                                      =$3390;
 mmRAS_SC_SIGNATURE2                                      =$3391;
 mmRAS_SC_SIGNATURE3                                      =$3392;
 mmRAS_SC_SIGNATURE4                                      =$3393;
 mmRAS_SC_SIGNATURE5                                      =$3394;
 mmRAS_SC_SIGNATURE6                                      =$3395;
 mmRAS_SC_SIGNATURE7                                      =$3396;
 mmRAS_IA_SIGNATURE0                                      =$3397;
 mmRAS_IA_SIGNATURE1                                      =$3398;
 mmRAS_SPI_SIGNATURE0                                     =$3399;
 mmRAS_SPI_SIGNATURE1                                     =$339A;
 mmRAS_TA_SIGNATURE0                                      =$339B;
 mmRAS_TD_SIGNATURE0                                      =$339C;
 mmRAS_CB_SIGNATURE0                                      =$339D;
 mmRAS_BCI_SIGNATURE0                                     =$339E;
 mmRAS_BCI_SIGNATURE1                                     =$339F;
 mmRAS_TA_SIGNATURE1                                      =$33A0;
 mmSDMA0_UCODE_ADDR                                       =$3400;
 mmSDMA0_UCODE_DATA                                       =$3401;
 mmSDMA0_POWER_CNTL                                       =$3402;
 mmSDMA0_CLK_CTRL                                         =$3403;
 mmSDMA0_CNTL                                             =$3404;
 mmSDMA0_CHICKEN_BITS                                     =$3405;
 mmSDMA0_TILING_CONFIG                                    =$3406;
 mmSDMA0_HASH                                             =$3407;
 mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL                         =$3409;
 mmSDMA0_RB_RPTR_FETCH                                    =$340A;
 mmSDMA0_IB_OFFSET_FETCH                                  =$340B;
 mmSDMA0_PROGRAM                                          =$340C;
 mmSDMA0_STATUS_REG                                       =$340D;
 mmSDMA0_STATUS1_REG                                      =$340E;
 mmSDMA0_RD_BURST_CNTL                                    =$340F;
 mmSDMA0_F32_CNTL                                         =$3412;
 mmSDMA0_FREEZE                                           =$3413;
 mmSDMA0_PHASE0_QUANTUM                                   =$3414;
 mmSDMA0_PHASE1_QUANTUM                                   =$3415;
 mmSDMA_POWER_GATING                                      =$3416;
 mmSDMA_PGFSM_CONFIG                                      =$3417;
 mmSDMA_PGFSM_WRITE                                       =$3418;
 mmSDMA_PGFSM_READ                                        =$3419;
 mmSDMA0_EDC_CONFIG                                       =$341A;
 mmSDMA0_VM_CNTL                                          =$341B;
 mmSDMA0_VM_CTX_LO                                        =$341C;
 mmSDMA0_VM_CTX_HI                                        =$341D;
 mmSDMA0_STATUS2_REG                                      =$341E;
 mmSDMA0_ACTIVE_FCN_ID                                    =$341F;
 mmSDMA0_VM_CTX_CNTL                                      =$3420;
 mmSDMA0_VIRT_RESET_REQ                                   =$3421;
 mmSDMA0_VF_ENABLE                                        =$342A;
 mmSDMA0_BA_THRESHOLD                                     =$342B;
 mmSDMA0_ID                                               =$342C;
 mmSDMA0_VERSION                                          =$342D;
 mmSDMA0_ATOMIC_CNTL                                      =$342E;
 mmSDMA0_ATOMIC_PREOP_LO                                  =$342F;
 mmSDMA0_ATOMIC_PREOP_HI                                  =$3430;
 mmSDMA0_PERF_REG_TYPE0                                   =$3477;
 mmSDMA0_CONTEXT_REG_TYPE0                                =$3478;
 mmSDMA0_CONTEXT_REG_TYPE1                                =$3479;
 mmSDMA0_CONTEXT_REG_TYPE2                                =$347A;
 mmSDMA0_PUB_REG_TYPE0                                    =$347C;
 mmSDMA0_PUB_REG_TYPE1                                    =$347D;
 mmSDMA0_GFX_RB_CNTL                                      =$3480;
 mmSDMA0_GFX_RB_BASE                                      =$3481;
 mmSDMA0_GFX_RB_BASE_HI                                   =$3482;
 mmSDMA0_GFX_RB_RPTR                                      =$3483;
 mmSDMA0_GFX_RB_WPTR                                      =$3484;
 mmSDMA0_GFX_RB_WPTR_POLL_CNTL                            =$3485;
 mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI                         =$3486;
 mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO                         =$3487;
 mmSDMA0_GFX_RB_RPTR_ADDR_HI                              =$3488;
 mmSDMA0_GFX_RB_RPTR_ADDR_LO                              =$3489;
 mmSDMA0_GFX_IB_CNTL                                      =$348A;
 mmSDMA0_GFX_IB_RPTR                                      =$348B;
 mmSDMA0_GFX_IB_OFFSET                                    =$348C;
 mmSDMA0_GFX_IB_BASE_LO                                   =$348D;
 mmSDMA0_GFX_IB_BASE_HI                                   =$348E;
 mmSDMA0_GFX_IB_SIZE                                      =$348F;
 mmSDMA0_GFX_SKIP_CNTL                                    =$3490;
 mmSDMA0_GFX_CONTEXT_STATUS                               =$3491;
 mmSDMA0_GFX_DOORBELL                                     =$3492;
 mmSDMA0_GFX_CONTEXT_CNTL                                 =$3493;
 mmSDMA0_GFX_VIRTUAL_ADDR                                 =$34A7;
 mmSDMA0_GFX_APE1_CNTL                                    =$34A8;
 mmSDMA0_GFX_DOORBELL_LOG                                 =$34A9;
 mmSDMA0_GFX_WATERMARK                                    =$34AA;
 mmSDMA0_GFX_CSA_ADDR_LO                                  =$34AC;
 mmSDMA0_GFX_CSA_ADDR_HI                                  =$34AD;
 mmSDMA0_GFX_IB_SUB_REMAIN                                =$34AF;
 mmSDMA0_GFX_PREEMPT                                      =$34B0;
 mmSDMA0_GFX_DUMMY_REG                                    =$34B1;
 mmSDMA0_GFX_MIDCMD_DATA0                                 =$34C1;
 mmSDMA0_GFX_MIDCMD_DATA1                                 =$34C2;
 mmSDMA0_GFX_MIDCMD_DATA2                                 =$34C3;
 mmSDMA0_GFX_MIDCMD_DATA3                                 =$34C4;
 mmSDMA0_GFX_MIDCMD_DATA4                                 =$34C5;
 mmSDMA0_GFX_MIDCMD_DATA5                                 =$34C6;
 mmSDMA0_GFX_MIDCMD_CNTL                                  =$34C7;
 mmSDMA0_RLC0_RB_CNTL                                     =$3500;
 mmSDMA0_RLC0_RB_BASE                                     =$3501;
 mmSDMA0_RLC0_RB_BASE_HI                                  =$3502;
 mmSDMA0_RLC0_RB_RPTR                                     =$3503;
 mmSDMA0_RLC0_RB_WPTR                                     =$3504;
 mmSDMA0_RLC0_RB_WPTR_POLL_CNTL                           =$3505;
 mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI                        =$3506;
 mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO                        =$3507;
 mmSDMA0_RLC0_RB_RPTR_ADDR_HI                             =$3508;
 mmSDMA0_RLC0_RB_RPTR_ADDR_LO                             =$3509;
 mmSDMA0_RLC0_IB_CNTL                                     =$350A;
 mmSDMA0_RLC0_IB_RPTR                                     =$350B;
 mmSDMA0_RLC0_IB_OFFSET                                   =$350C;
 mmSDMA0_RLC0_IB_BASE_LO                                  =$350D;
 mmSDMA0_RLC0_IB_BASE_HI                                  =$350E;
 mmSDMA0_RLC0_IB_SIZE                                     =$350F;
 mmSDMA0_RLC0_SKIP_CNTL                                   =$3510;
 mmSDMA0_RLC0_CONTEXT_STATUS                              =$3511;
 mmSDMA0_RLC0_DOORBELL                                    =$3512;
 mmSDMA0_RLC0_VIRTUAL_ADDR                                =$3527;
 mmSDMA0_RLC0_APE1_CNTL                                   =$3528;
 mmSDMA0_RLC0_DOORBELL_LOG                                =$3529;
 mmSDMA0_RLC0_WATERMARK                                   =$352A;
 mmSDMA0_RLC0_CSA_ADDR_LO                                 =$352C;
 mmSDMA0_RLC0_CSA_ADDR_HI                                 =$352D;
 mmSDMA0_RLC0_IB_SUB_REMAIN                               =$352F;
 mmSDMA0_RLC0_PREEMPT                                     =$3530;
 mmSDMA0_RLC0_DUMMY_REG                                   =$3531;
 mmSDMA0_RLC0_MIDCMD_DATA0                                =$3541;
 mmSDMA0_RLC0_MIDCMD_DATA1                                =$3542;
 mmSDMA0_RLC0_MIDCMD_DATA2                                =$3543;
 mmSDMA0_RLC0_MIDCMD_DATA3                                =$3544;
 mmSDMA0_RLC0_MIDCMD_DATA4                                =$3545;
 mmSDMA0_RLC0_MIDCMD_DATA5                                =$3546;
 mmSDMA0_RLC0_MIDCMD_CNTL                                 =$3547;
 mmSDMA0_RLC1_RB_CNTL                                     =$3580;
 mmSDMA0_RLC1_RB_BASE                                     =$3581;
 mmSDMA0_RLC1_RB_BASE_HI                                  =$3582;
 mmSDMA0_RLC1_RB_RPTR                                     =$3583;
 mmSDMA0_RLC1_RB_WPTR                                     =$3584;
 mmSDMA0_RLC1_RB_WPTR_POLL_CNTL                           =$3585;
 mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI                        =$3586;
 mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO                        =$3587;
 mmSDMA0_RLC1_RB_RPTR_ADDR_HI                             =$3588;
 mmSDMA0_RLC1_RB_RPTR_ADDR_LO                             =$3589;
 mmSDMA0_RLC1_IB_CNTL                                     =$358A;
 mmSDMA0_RLC1_IB_RPTR                                     =$358B;
 mmSDMA0_RLC1_IB_OFFSET                                   =$358C;
 mmSDMA0_RLC1_IB_BASE_LO                                  =$358D;
 mmSDMA0_RLC1_IB_BASE_HI                                  =$358E;
 mmSDMA0_RLC1_IB_SIZE                                     =$358F;
 mmSDMA0_RLC1_SKIP_CNTL                                   =$3590;
 mmSDMA0_RLC1_CONTEXT_STATUS                              =$3591;
 mmSDMA0_RLC1_DOORBELL                                    =$3592;
 mmSDMA0_RLC1_VIRTUAL_ADDR                                =$35A7;
 mmSDMA0_RLC1_APE1_CNTL                                   =$35A8;
 mmSDMA0_RLC1_DOORBELL_LOG                                =$35A9;
 mmSDMA0_RLC1_WATERMARK                                   =$35AA;
 mmSDMA0_RLC1_CSA_ADDR_LO                                 =$35AC;
 mmSDMA0_RLC1_CSA_ADDR_HI                                 =$35AD;
 mmSDMA0_RLC1_IB_SUB_REMAIN                               =$35AF;
 mmSDMA0_RLC1_PREEMPT                                     =$35B0;
 mmSDMA0_RLC1_DUMMY_REG                                   =$35B1;
 mmSDMA0_RLC1_MIDCMD_DATA0                                =$35C1;
 mmSDMA0_RLC1_MIDCMD_DATA1                                =$35C2;
 mmSDMA0_RLC1_MIDCMD_DATA2                                =$35C3;
 mmSDMA0_RLC1_MIDCMD_DATA3                                =$35C4;
 mmSDMA0_RLC1_MIDCMD_DATA4                                =$35C5;
 mmSDMA0_RLC1_MIDCMD_DATA5                                =$35C6;
 mmSDMA0_RLC1_MIDCMD_CNTL                                 =$35C7;
 mmSDMA1_UCODE_ADDR                                       =$3600;
 mmSDMA1_UCODE_DATA                                       =$3601;
 mmSDMA1_POWER_CNTL                                       =$3602;
 mmSDMA1_CLK_CTRL                                         =$3603;
 mmSDMA1_CNTL                                             =$3604;
 mmSDMA1_CHICKEN_BITS                                     =$3605;
 mmSDMA1_TILING_CONFIG                                    =$3606;
 mmSDMA1_HASH                                             =$3607;
 mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                         =$3609;
 mmSDMA1_RB_RPTR_FETCH                                    =$360A;
 mmSDMA1_IB_OFFSET_FETCH                                  =$360B;
 mmSDMA1_PROGRAM                                          =$360C;
 mmSDMA1_STATUS_REG                                       =$360D;
 mmSDMA1_STATUS1_REG                                      =$360E;
 mmSDMA1_RD_BURST_CNTL                                    =$360F;
 mmSDMA1_F32_CNTL                                         =$3612;
 mmSDMA1_FREEZE                                           =$3613;
 mmSDMA1_PHASE0_QUANTUM                                   =$3614;
 mmSDMA1_PHASE1_QUANTUM                                   =$3615;
 mmSDMA1_EDC_CONFIG                                       =$361A;
 mmSDMA1_VM_CNTL                                          =$361B;
 mmSDMA1_VM_CTX_LO                                        =$361C;
 mmSDMA1_VM_CTX_HI                                        =$361D;
 mmSDMA1_STATUS2_REG                                      =$361E;
 mmSDMA1_ACTIVE_FCN_ID                                    =$361F;
 mmSDMA1_VM_CTX_CNTL                                      =$3620;
 mmSDMA1_VIRT_RESET_REQ                                   =$3621;
 mmSDMA1_VF_ENABLE                                        =$362A;
 mmSDMA1_BA_THRESHOLD                                     =$362B;
 mmSDMA1_ID                                               =$362C;
 mmSDMA1_VERSION                                          =$362D;
 mmSDMA1_ATOMIC_CNTL                                      =$362E;
 mmSDMA1_ATOMIC_PREOP_LO                                  =$362F;
 mmSDMA1_ATOMIC_PREOP_HI                                  =$3630;
 mmSDMA1_PERF_REG_TYPE0                                   =$3677;
 mmSDMA1_CONTEXT_REG_TYPE0                                =$3678;
 mmSDMA1_CONTEXT_REG_TYPE1                                =$3679;
 mmSDMA1_CONTEXT_REG_TYPE2                                =$367A;
 mmSDMA1_PUB_REG_TYPE0                                    =$367C;
 mmSDMA1_PUB_REG_TYPE1                                    =$367D;
 mmSDMA1_GFX_RB_CNTL                                      =$3680;
 mmSDMA1_GFX_RB_BASE                                      =$3681;
 mmSDMA1_GFX_RB_BASE_HI                                   =$3682;
 mmSDMA1_GFX_RB_RPTR                                      =$3683;
 mmSDMA1_GFX_RB_WPTR                                      =$3684;
 mmSDMA1_GFX_RB_WPTR_POLL_CNTL                            =$3685;
 mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI                         =$3686;
 mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO                         =$3687;
 mmSDMA1_GFX_RB_RPTR_ADDR_HI                              =$3688;
 mmSDMA1_GFX_RB_RPTR_ADDR_LO                              =$3689;
 mmSDMA1_GFX_IB_CNTL                                      =$368A;
 mmSDMA1_GFX_IB_RPTR                                      =$368B;
 mmSDMA1_GFX_IB_OFFSET                                    =$368C;
 mmSDMA1_GFX_IB_BASE_LO                                   =$368D;
 mmSDMA1_GFX_IB_BASE_HI                                   =$368E;
 mmSDMA1_GFX_IB_SIZE                                      =$368F;
 mmSDMA1_GFX_SKIP_CNTL                                    =$3690;
 mmSDMA1_GFX_CONTEXT_STATUS                               =$3691;
 mmSDMA1_GFX_DOORBELL                                     =$3692;
 mmSDMA1_GFX_CONTEXT_CNTL                                 =$3693;
 mmSDMA1_GFX_VIRTUAL_ADDR                                 =$36A7;
 mmSDMA1_GFX_APE1_CNTL                                    =$36A8;
 mmSDMA1_GFX_DOORBELL_LOG                                 =$36A9;
 mmSDMA1_GFX_WATERMARK                                    =$36AA;
 mmSDMA1_GFX_CSA_ADDR_LO                                  =$36AC;
 mmSDMA1_GFX_CSA_ADDR_HI                                  =$36AD;
 mmSDMA1_GFX_IB_SUB_REMAIN                                =$36AF;
 mmSDMA1_GFX_PREEMPT                                      =$36B0;
 mmSDMA1_GFX_DUMMY_REG                                    =$36B1;
 mmSDMA1_GFX_MIDCMD_DATA0                                 =$36C1;
 mmSDMA1_GFX_MIDCMD_DATA1                                 =$36C2;
 mmSDMA1_GFX_MIDCMD_DATA2                                 =$36C3;
 mmSDMA1_GFX_MIDCMD_DATA3                                 =$36C4;
 mmSDMA1_GFX_MIDCMD_DATA4                                 =$36C5;
 mmSDMA1_GFX_MIDCMD_DATA5                                 =$36C6;
 mmSDMA1_GFX_MIDCMD_CNTL                                  =$36C7;
 mmSDMA1_RLC0_RB_CNTL                                     =$3700;
 mmSDMA1_RLC0_RB_BASE                                     =$3701;
 mmSDMA1_RLC0_RB_BASE_HI                                  =$3702;
 mmSDMA1_RLC0_RB_RPTR                                     =$3703;
 mmSDMA1_RLC0_RB_WPTR                                     =$3704;
 mmSDMA1_RLC0_RB_WPTR_POLL_CNTL                           =$3705;
 mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                        =$3706;
 mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                        =$3707;
 mmSDMA1_RLC0_RB_RPTR_ADDR_HI                             =$3708;
 mmSDMA1_RLC0_RB_RPTR_ADDR_LO                             =$3709;
 mmSDMA1_RLC0_IB_CNTL                                     =$370A;
 mmSDMA1_RLC0_IB_RPTR                                     =$370B;
 mmSDMA1_RLC0_IB_OFFSET                                   =$370C;
 mmSDMA1_RLC0_IB_BASE_LO                                  =$370D;
 mmSDMA1_RLC0_IB_BASE_HI                                  =$370E;
 mmSDMA1_RLC0_IB_SIZE                                     =$370F;
 mmSDMA1_RLC0_SKIP_CNTL                                   =$3710;
 mmSDMA1_RLC0_CONTEXT_STATUS                              =$3711;
 mmSDMA1_RLC0_DOORBELL                                    =$3712;
 mmSDMA1_RLC0_VIRTUAL_ADDR                                =$3727;
 mmSDMA1_RLC0_APE1_CNTL                                   =$3728;
 mmSDMA1_RLC0_DOORBELL_LOG                                =$3729;
 mmSDMA1_RLC0_WATERMARK                                   =$372A;
 mmSDMA1_RLC0_CSA_ADDR_LO                                 =$372C;
 mmSDMA1_RLC0_CSA_ADDR_HI                                 =$372D;
 mmSDMA1_RLC0_IB_SUB_REMAIN                               =$372F;
 mmSDMA1_RLC0_PREEMPT                                     =$3730;
 mmSDMA1_RLC0_DUMMY_REG                                   =$3731;
 mmSDMA1_RLC0_MIDCMD_DATA0                                =$3741;
 mmSDMA1_RLC0_MIDCMD_DATA1                                =$3742;
 mmSDMA1_RLC0_MIDCMD_DATA2                                =$3743;
 mmSDMA1_RLC0_MIDCMD_DATA3                                =$3744;
 mmSDMA1_RLC0_MIDCMD_DATA4                                =$3745;
 mmSDMA1_RLC0_MIDCMD_DATA5                                =$3746;
 mmSDMA1_RLC0_MIDCMD_CNTL                                 =$3747;
 mmSDMA1_RLC1_RB_CNTL                                     =$3780;
 mmSDMA1_RLC1_RB_BASE                                     =$3781;
 mmSDMA1_RLC1_RB_BASE_HI                                  =$3782;
 mmSDMA1_RLC1_RB_RPTR                                     =$3783;
 mmSDMA1_RLC1_RB_WPTR                                     =$3784;
 mmSDMA1_RLC1_RB_WPTR_POLL_CNTL                           =$3785;
 mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                        =$3786;
 mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                        =$3787;
 mmSDMA1_RLC1_RB_RPTR_ADDR_HI                             =$3788;
 mmSDMA1_RLC1_RB_RPTR_ADDR_LO                             =$3789;
 mmSDMA1_RLC1_IB_CNTL                                     =$378A;
 mmSDMA1_RLC1_IB_RPTR                                     =$378B;
 mmSDMA1_RLC1_IB_OFFSET                                   =$378C;
 mmSDMA1_RLC1_IB_BASE_LO                                  =$378D;
 mmSDMA1_RLC1_IB_BASE_HI                                  =$378E;
 mmSDMA1_RLC1_IB_SIZE                                     =$378F;
 mmSDMA1_RLC1_SKIP_CNTL                                   =$3790;
 mmSDMA1_RLC1_CONTEXT_STATUS                              =$3791;
 mmSDMA1_RLC1_DOORBELL                                    =$3792;
 mmSDMA1_RLC1_VIRTUAL_ADDR                                =$37A7;
 mmSDMA1_RLC1_APE1_CNTL                                   =$37A8;
 mmSDMA1_RLC1_DOORBELL_LOG                                =$37A9;
 mmSDMA1_RLC1_WATERMARK                                   =$37AA;
 mmSDMA1_RLC1_CSA_ADDR_LO                                 =$37AC;
 mmSDMA1_RLC1_CSA_ADDR_HI                                 =$37AD;
 mmSDMA1_RLC1_IB_SUB_REMAIN                               =$37AF;
 mmSDMA1_RLC1_PREEMPT                                     =$37B0;
 mmSDMA1_RLC1_DUMMY_REG                                   =$37B1;
 mmSDMA1_RLC1_MIDCMD_DATA0                                =$37C1;
 mmSDMA1_RLC1_MIDCMD_DATA1                                =$37C2;
 mmSDMA1_RLC1_MIDCMD_DATA2                                =$37C3;
 mmSDMA1_RLC1_MIDCMD_DATA3                                =$37C4;
 mmSDMA1_RLC1_MIDCMD_DATA4                                =$37C5;
 mmSDMA1_RLC1_MIDCMD_DATA5                                =$37C6;
 mmSDMA1_RLC1_MIDCMD_CNTL                                 =$37C7;
 mmUVD_PGFSM_CONFIG                                       =$38C0;
 mmUVD_PGFSM_READ_TILE1                                   =$38C2;
 mmUVD_PGFSM_READ_TILE2                                   =$38C3;
 mmUVD_POWER_STATUS                                       =$38C4;
 mmUVD_PGFSM_READ_TILE3                                   =$38C5;
 mmUVD_PGFSM_READ_TILE4                                   =$38C6;
 mmUVD_PGFSM_READ_TILE5                                   =$38C8;
 mmUVD_PGFSM_READ_TILE6                                   =$38EE;
 mmUVD_PGFSM_READ_TILE7                                   =$38EF;
 mmUVD_MIF_CURR_ADDR_CONFIG                               =$3992;
 mmUVD_MIF_REF_ADDR_CONFIG                                =$3993;
 mmUVD_MIF_RECON1_ADDR_CONFIG                             =$39C5;
 mmUVD_JPEG_ADDR_CONFIG                                   =$3A1F;
 mmUVD_SEMA_ADDR_LOW                                      =$3BC0;
 mmUVD_SEMA_ADDR_HIGH                                     =$3BC1;
 mmUVD_SEMA_CMD                                           =$3BC2;
 mmUVD_GPCOM_VCPU_CMD                                     =$3BC3;
 mmUVD_GPCOM_VCPU_DATA0                                   =$3BC4;
 mmUVD_GPCOM_VCPU_DATA1                                   =$3BC5;
 mmUVD_ENGINE_CNTL                                        =$3BC6;
 mmUVD_UDEC_ADDR_CONFIG                                   =$3BD3;
 mmUVD_UDEC_DB_ADDR_CONFIG                                =$3BD4;
 mmUVD_UDEC_DBW_ADDR_CONFIG                               =$3BD5;
 mmUVD_SUVD_CGC_GATE                                      =$3BE4;
 mmUVD_SUVD_CGC_STATUS                                    =$3BE5;
 mmUVD_SUVD_CGC_CTRL                                      =$3BE6;
 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                      =$3C5E;
 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                       =$3C5F;
 mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH                          =$3C66;
 mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                           =$3C67;
 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                          =$3C68;
 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                           =$3C69;
 mmUVD_SEMA_CNTL                                          =$3D00;
 mmUVD_LMI_EXT40_ADDR                                     =$3D26;
 mmUVD_CTX_INDEX                                          =$3D28;
 mmUVD_CTX_DATA                                           =$3D29;
 mmUVD_CGC_GATE                                           =$3D2A;
 mmUVD_CGC_STATUS                                         =$3D2B;
 mmUVD_CGC_CTRL                                           =$3D2C;
 mmUVD_CGC_UDEC_STATUS                                    =$3D2D;
 mmUVD_LMI_CTRL2                                          =$3D3D;
 mmUVD_MASTINT_EN                                         =$3D40;
 mmUVD_LMI_ADDR_EXT                                       =$3D65;
 mmUVD_LMI_CTRL                                           =$3D66;
 mmUVD_LMI_STATUS                                         =$3D67;
 mmUVD_LMI_SWAP_CNTL                                      =$3D6D;
 mmUVD_MP_SWAP_CNTL                                       =$3D6F;
 mmUVD_MPC_CNTL                                           =$3D77;
 mmUVD_MPC_SET_MUXA0                                      =$3D79;
 mmUVD_MPC_SET_MUXA1                                      =$3D7A;
 mmUVD_MPC_SET_MUXB0                                      =$3D7B;
 mmUVD_MPC_SET_MUXB1                                      =$3D7C;
 mmUVD_MPC_SET_MUX                                        =$3D7D;
 mmUVD_MPC_SET_ALU                                        =$3D7E;
 mmUVD_VCPU_CACHE_OFFSET0                                 =$3D82;
 mmUVD_VCPU_CACHE_SIZE0                                   =$3D83;
 mmUVD_VCPU_CACHE_OFFSET1                                 =$3D84;
 mmUVD_VCPU_CACHE_SIZE1                                   =$3D85;
 mmUVD_VCPU_CACHE_OFFSET2                                 =$3D86;
 mmUVD_VCPU_CACHE_SIZE2                                   =$3D87;
 mmUVD_VCPU_CNTL                                          =$3D98;
 mmUVD_SOFT_RESET                                         =$3DA0;
 mmUVD_LMI_RBC_IB_VMID                                    =$3DA1;
 mmUVD_RBC_IB_SIZE                                        =$3DA2;
 mmUVD_LMI_RBC_RB_VMID                                    =$3DA3;
 mmUVD_RBC_RB_RPTR                                        =$3DA4;
 mmUVD_RBC_RB_WPTR                                        =$3DA5;
 mmUVD_RBC_RB_CNTL                                        =$3DA9;
 mmUVD_RBC_RB_RPTR_ADDR                                   =$3DAA;
 mmUVD_STATUS                                             =$3DAF;
 mmUVD_SEMA_TIMEOUT_STATUS                                =$3DB0;
 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                  =$3DB1;
 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                       =$3DB2;
 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                =$3DB3;
 mmUVD_CONTEXT_ID                                         =$3DBD;
 mmDCP3_GRPH_ENABLE                                       =$4000;
 mmDCP3_GRPH_CONTROL                                      =$4001;
 mmDCP3_GRPH_LUT_10BIT_BYPASS                             =$4002;
 mmDCP3_GRPH_SWAP_CNTL                                    =$4003;
 mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS                      =$4004;
 mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS                    =$4005;
 mmDCP3_GRPH_PITCH                                        =$4006;
 mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                 =$4007;
 mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH               =$4008;
 mmDCP3_GRPH_SURFACE_OFFSET_X                             =$4009;
 mmDCP3_GRPH_SURFACE_OFFSET_Y                             =$400A;
 mmDCP3_GRPH_X_START                                      =$400B;
 mmDCP3_GRPH_Y_START                                      =$400C;
 mmDCP3_GRPH_X_END                                        =$400D;
 mmDCP3_GRPH_Y_END                                        =$400E;
 mmDCP3_INPUT_GAMMA_CONTROL                               =$4010;
 mmDCP3_GRPH_UPDATE                                       =$4011;
 mmDCP3_GRPH_FLIP_CONTROL                                 =$4012;
 mmDCP3_GRPH_SURFACE_ADDRESS_INUSE                        =$4013;
 mmDCP3_GRPH_DFQ_CONTROL                                  =$4014;
 mmDCP3_GRPH_DFQ_STATUS                                   =$4015;
 mmDCP3_GRPH_INTERRUPT_STATUS                             =$4016;
 mmDCP3_GRPH_INTERRUPT_CONTROL                            =$4017;
 mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE                   =$4018;
 mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS                     =$4019;
 mmDCP3_GRPH_COMPRESS_PITCH                               =$401A;
 mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                =$401B;
 mmDCP3_OVL_ENABLE                                        =$401C;
 mmDCP3_OVL_CONTROL1                                      =$401D;
 mmDCP3_OVL_CONTROL2                                      =$401E;
 mmDCP3_OVL_SWAP_CNTL                                     =$401F;
 mmDCP3_OVL_SURFACE_ADDRESS                               =$4020;
 mmDCP3_OVL_PITCH                                         =$4021;
 mmDCP3_OVL_SURFACE_ADDRESS_HIGH                          =$4022;
 mmDCP3_OVL_SURFACE_OFFSET_X                              =$4023;
 mmDCP3_OVL_SURFACE_OFFSET_Y                              =$4024;
 mmDCP3_OVL_START                                         =$4025;
 mmDCP3_OVL_END                                           =$4026;
 mmDCP3_OVL_UPDATE                                        =$4027;
 mmDCP3_OVL_SURFACE_ADDRESS_INUSE                         =$4028;
 mmDCP3_OVL_DFQ_CONTROL                                   =$4029;
 mmDCP3_OVL_DFQ_STATUS                                    =$402A;
 mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE                    =$402B;
 mmDCP3_OVLSCL_EDGE_PIXEL_CNTL                            =$402C;
 mmDCP3_PRESCALE_GRPH_CONTROL                             =$402D;
 mmDCP3_PRESCALE_VALUES_GRPH_R                            =$402E;
 mmDCP3_PRESCALE_VALUES_GRPH_G                            =$402F;
 mmDCP3_PRESCALE_VALUES_GRPH_B                            =$4030;
 mmDCP3_PRESCALE_OVL_CONTROL                              =$4031;
 mmDCP3_PRESCALE_VALUES_OVL_CB                            =$4032;
 mmDCP3_PRESCALE_VALUES_OVL_Y                             =$4033;
 mmDCP3_PRESCALE_VALUES_OVL_CR                            =$4034;
 mmDCP3_INPUT_CSC_CONTROL                                 =$4035;
 mmDCP3_INPUT_CSC_C11_C12                                 =$4036;
 mmDCP3_INPUT_CSC_C13_C14                                 =$4037;
 mmDCP3_INPUT_CSC_C21_C22                                 =$4038;
 mmDCP3_INPUT_CSC_C23_C24                                 =$4039;
 mmDCP3_INPUT_CSC_C31_C32                                 =$403A;
 mmDCP3_INPUT_CSC_C33_C34                                 =$403B;
 mmDCP3_OUTPUT_CSC_CONTROL                                =$403C;
 mmDCP3_OUTPUT_CSC_C11_C12                                =$403D;
 mmDCP3_OUTPUT_CSC_C13_C14                                =$403E;
 mmDCP3_OUTPUT_CSC_C21_C22                                =$403F;
 mmDCP3_OUTPUT_CSC_C23_C24                                =$4040;
 mmDCP3_OUTPUT_CSC_C31_C32                                =$4041;
 mmDCP3_OUTPUT_CSC_C33_C34                                =$4042;
 mmDCP3_COMM_MATRIXA_TRANS_C11_C12                        =$4043;
 mmDCP3_COMM_MATRIXA_TRANS_C13_C14                        =$4044;
 mmDCP3_COMM_MATRIXA_TRANS_C21_C22                        =$4045;
 mmDCP3_COMM_MATRIXA_TRANS_C23_C24                        =$4046;
 mmDCP3_COMM_MATRIXA_TRANS_C31_C32                        =$4047;
 mmDCP3_COMM_MATRIXA_TRANS_C33_C34                        =$4048;
 mmDCP3_COMM_MATRIXB_TRANS_C11_C12                        =$4049;
 mmDCP3_COMM_MATRIXB_TRANS_C13_C14                        =$404A;
 mmDCP3_COMM_MATRIXB_TRANS_C21_C22                        =$404B;
 mmDCP3_COMM_MATRIXB_TRANS_C23_C24                        =$404C;
 mmDCP3_COMM_MATRIXB_TRANS_C31_C32                        =$404D;
 mmDCP3_COMM_MATRIXB_TRANS_C33_C34                        =$404E;
 mmDCP3_DENORM_CONTROL                                    =$4050;
 mmDCP3_OUT_ROUND_CONTROL                                 =$4051;
 mmDCP3_OUT_CLAMP_CONTROL_R_CR                            =$4052;
 mmDCP3_KEY_CONTROL                                       =$4053;
 mmDCP3_KEY_RANGE_ALPHA                                   =$4054;
 mmDCP3_KEY_RANGE_RED                                     =$4055;
 mmDCP3_KEY_RANGE_GREEN                                   =$4056;
 mmDCP3_KEY_RANGE_BLUE                                    =$4057;
 mmDCP3_DEGAMMA_CONTROL                                   =$4058;
 mmDCP3_GAMUT_REMAP_CONTROL                               =$4059;
 mmDCP3_GAMUT_REMAP_C11_C12                               =$405A;
 mmDCP3_GAMUT_REMAP_C13_C14                               =$405B;
 mmDCP3_GAMUT_REMAP_C21_C22                               =$405C;
 mmDCP3_GAMUT_REMAP_C23_C24                               =$405D;
 mmDCP3_GAMUT_REMAP_C31_C32                               =$405E;
 mmDCP3_GAMUT_REMAP_C33_C34                               =$405F;
 mmDCP3_DCP_SPATIAL_DITHER_CNTL                           =$4060;
 mmDCP3_DCP_RANDOM_SEEDS                                  =$4061;
 mmDCP3_DCP_FP_CONVERTED_FIELD                            =$4065;
 mmDCP3_CUR_CONTROL                                       =$4066;
 mmDCP3_CUR_SURFACE_ADDRESS                               =$4067;
 mmDCP3_CUR_SIZE                                          =$4068;
 mmDCP3_CUR_SURFACE_ADDRESS_HIGH                          =$4069;
 mmDCP3_CUR_POSITION                                      =$406A;
 mmDCP3_CUR_HOT_SPOT                                      =$406B;
 mmDCP3_CUR_COLOR1                                        =$406C;
 mmDCP3_CUR_COLOR2                                        =$406D;
 mmDCP3_CUR_UPDATE                                        =$406E;
 mmDCP3_CUR2_CONTROL                                      =$406F;
 mmDCP3_CUR2_SURFACE_ADDRESS                              =$4070;
 mmDCP3_CUR2_SIZE                                         =$4071;
 mmDCP3_CUR2_SURFACE_ADDRESS_HIGH                         =$4072;
 mmDCP3_CUR2_POSITION                                     =$4073;
 mmDCP3_CUR2_HOT_SPOT                                     =$4074;
 mmDCP3_CUR2_COLOR1                                       =$4075;
 mmDCP3_CUR2_COLOR2                                       =$4076;
 mmDCP3_CUR2_UPDATE                                       =$4077;
 mmDCP3_DC_LUT_RW_MODE                                    =$4078;
 mmDCP3_DC_LUT_RW_INDEX                                   =$4079;
 mmDCP3_DC_LUT_SEQ_COLOR                                  =$407A;
 mmDCP3_DC_LUT_PWL_DATA                                   =$407B;
 mmDCP3_DC_LUT_30_COLOR                                   =$407C;
 mmDCP3_DC_LUT_VGA_ACCESS_ENABLE                          =$407D;
 mmDCP3_DC_LUT_WRITE_EN_MASK                              =$407E;
 mmDCP3_DC_LUT_AUTOFILL                                   =$407F;
 mmDCP3_DC_LUT_CONTROL                                    =$4080;
 mmDCP3_DC_LUT_BLACK_OFFSET_BLUE                          =$4081;
 mmDCP3_DC_LUT_BLACK_OFFSET_GREEN                         =$4082;
 mmDCP3_DC_LUT_BLACK_OFFSET_RED                           =$4083;
 mmDCP3_DC_LUT_WHITE_OFFSET_BLUE                          =$4084;
 mmDCP3_DC_LUT_WHITE_OFFSET_GREEN                         =$4085;
 mmDCP3_DC_LUT_WHITE_OFFSET_RED                           =$4086;
 mmDCP3_DCP_CRC_CONTROL                                   =$4087;
 mmDCP3_DCP_CRC_MASK                                      =$4088;
 mmDCP3_DCP_CRC_CURRENT                                   =$4089;
 mmDCP3_DCP_CRC_LAST                                      =$408B;
 mmDCP3_DCP_DEBUG                                         =$408D;
 mmDCP3_GRPH_FLIP_RATE_CNTL                               =$408E;
 mmDCP3_DCP_GSL_CONTROL                                   =$4090;
 mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK                     =$4091;
 mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS                     =$4092;
 mmDCP3_OVL_STEREOSYNC_FLIP                               =$4093;
 mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                =$4094;
 mmDCP3_DCP_TEST_DEBUG_INDEX                              =$4095;
 mmDCP3_DCP_TEST_DEBUG_DATA                               =$4096;
 mmDCP3_GRPH_STEREOSYNC_FLIP                              =$4097;
 mmDCP3_DCP_DEBUG2                                        =$4098;
 mmDCP3_CUR_REQUEST_FILTER_CNTL                           =$4099;
 mmDCP3_CUR_STEREO_CONTROL                                =$409A;
 mmDCP3_CUR2_STEREO_CONTROL                               =$409B;
 mmDCP3_OUT_CLAMP_CONTROL_G_Y                             =$409C;
 mmDCP3_OUT_CLAMP_CONTROL_B_CB                            =$409D;
 mmDCP3_HW_ROTATION                                       =$409E;
 mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                =$409F;
 mmDCP3_REGAMMA_CONTROL                                   =$40A0;
 mmDCP3_REGAMMA_LUT_INDEX                                 =$40A1;
 mmDCP3_REGAMMA_LUT_DATA                                  =$40A2;
 mmDCP3_REGAMMA_LUT_WRITE_EN_MASK                         =$40A3;
 mmDCP3_REGAMMA_CNTLA_START_CNTL                          =$40A4;
 mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL                          =$40A5;
 mmDCP3_REGAMMA_CNTLA_END_CNTL1                           =$40A6;
 mmDCP3_REGAMMA_CNTLA_END_CNTL2                           =$40A7;
 mmDCP3_REGAMMA_CNTLA_REGION_0_1                          =$40A8;
 mmDCP3_REGAMMA_CNTLA_REGION_2_3                          =$40A9;
 mmDCP3_REGAMMA_CNTLA_REGION_4_5                          =$40AA;
 mmDCP3_REGAMMA_CNTLA_REGION_6_7                          =$40AB;
 mmDCP3_REGAMMA_CNTLA_REGION_8_9                          =$40AC;
 mmDCP3_REGAMMA_CNTLA_REGION_10_11                        =$40AD;
 mmDCP3_REGAMMA_CNTLA_REGION_12_13                        =$40AE;
 mmDCP3_REGAMMA_CNTLA_REGION_14_15                        =$40AF;
 mmDCP3_REGAMMA_CNTLB_START_CNTL                          =$40B0;
 mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL                          =$40B1;
 mmDCP3_REGAMMA_CNTLB_END_CNTL1                           =$40B2;
 mmDCP3_REGAMMA_CNTLB_END_CNTL2                           =$40B3;
 mmDCP3_REGAMMA_CNTLB_REGION_0_1                          =$40B4;
 mmDCP3_REGAMMA_CNTLB_REGION_2_3                          =$40B5;
 mmDCP3_REGAMMA_CNTLB_REGION_4_5                          =$40B6;
 mmDCP3_REGAMMA_CNTLB_REGION_6_7                          =$40B7;
 mmDCP3_REGAMMA_CNTLB_REGION_8_9                          =$40B8;
 mmDCP3_REGAMMA_CNTLB_REGION_10_11                        =$40B9;
 mmDCP3_REGAMMA_CNTLB_REGION_12_13                        =$40BA;
 mmDCP3_REGAMMA_CNTLB_REGION_14_15                        =$40BB;
 mmDCP3_ALPHA_CONTROL                                     =$40BC;
 mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                =$40BD;
 mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH           =$40BE;
 mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS              =$40BF;
 mmLB3_LB_DATA_FORMAT                                     =$40C0;
 mmLB3_LB_MEMORY_CTRL                                     =$40C1;
 mmLB3_LB_MEMORY_SIZE_STATUS                              =$40C2;
 mmLB3_LB_DESKTOP_HEIGHT                                  =$40C3;
 mmLB3_LB_VLINE_START_END                                 =$40C4;
 mmLB3_LB_VLINE2_START_END                                =$40C5;
 mmLB3_LB_V_COUNTER                                       =$40C6;
 mmLB3_LB_SNAPSHOT_V_COUNTER                              =$40C7;
 mmLB3_LB_INTERRUPT_MASK                                  =$40C8;
 mmLB3_LB_VLINE_STATUS                                    =$40C9;
 mmLB3_LB_VLINE2_STATUS                                   =$40CA;
 mmLB3_LB_VBLANK_STATUS                                   =$40CB;
 mmLB3_LB_SYNC_RESET_SEL                                  =$40CC;
 mmLB3_LB_BLACK_KEYER_R_CR                                =$40CD;
 mmLB3_LB_BLACK_KEYER_G_Y                                 =$40CE;
 mmLB3_LB_BLACK_KEYER_B_CB                                =$40CF;
 mmLB3_LB_KEYER_COLOR_CTRL                                =$40D0;
 mmLB3_LB_KEYER_COLOR_R_CR                                =$40D1;
 mmLB3_LB_KEYER_COLOR_G_Y                                 =$40D2;
 mmLB3_LB_KEYER_COLOR_B_CB                                =$40D3;
 mmLB3_LB_KEYER_COLOR_REP_R_CR                            =$40D4;
 mmLB3_LB_KEYER_COLOR_REP_G_Y                             =$40D5;
 mmLB3_LB_KEYER_COLOR_REP_B_CB                            =$40D6;
 mmLB3_LB_BUFFER_LEVEL_STATUS                             =$40D7;
 mmLB3_LB_BUFFER_URGENCY_CTRL                             =$40D8;
 mmLB3_LB_BUFFER_URGENCY_STATUS                           =$40D9;
 mmLB3_LB_BUFFER_STATUS                                   =$40DA;
 mmLB2_DC_MVP_LB_CONTROL                                  =$40DB;
 mmLB3_LB_NO_OUTSTANDING_REQ_STATUS                       =$40DC;
 mmLB3_MVP_AFR_FLIP_MODE                                  =$40E0;
 mmLB3_MVP_AFR_FLIP_FIFO_CNTL                             =$40E1;
 mmLB3_MVP_FLIP_LINE_NUM_INSERT                           =$40E2;
 mmLB3_DC_MVP_LB_CONTROL                                  =$40E3;
 mmLB3_LB_DEBUG                                           =$40E4;
 mmLB3_LB_DEBUG2                                          =$40E5;
 mmLB3_LB_DEBUG3                                          =$40E6;
 mmLB2_LB_DEBUG                                           =$40FC;
 mmLB3_LB_TEST_DEBUG_INDEX                                =$40FE;
 mmLB3_LB_TEST_DEBUG_DATA                                 =$40FF;
 mmDCFE3_DCFE_CLOCK_CONTROL                               =$4100;
 mmDCFE3_DCFE_SOFT_RESET                                  =$4101;
 mmDCFE3_DCFE_DBG_CONFIG                                  =$4102;
 mmDC_PERFMON6_PERFCOUNTER_CNTL                           =$4124;
 mmDC_PERFMON6_PERFCOUNTER_STATE                          =$4125;
 mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                    =$4126;
 mmDC_PERFMON6_PERFMON_CNTL                               =$4127;
 mmDC_PERFMON6_PERFMON_CVALUE_LOW                         =$4128;
 mmDC_PERFMON6_PERFMON_HI                                 =$4129;
 mmDC_PERFMON6_PERFMON_LOW                                =$412A;
 mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX                   =$412B;
 mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA                    =$412C;
 mmDC_PERFMON6_PERFMON_CNTL2                              =$412E;
 mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1                 =$4130;
 mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2                 =$4131;
 mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL                    =$4132;
 mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL                      =$4133;
 mmDMIF_PG3_DPG_PIPE_DPM_CONTROL                          =$4134;
 mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL                      =$4135;
 mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             =$4136;
 mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             =$4137;
 mmDMIF_PG3_DPG_TEST_DEBUG_INDEX                          =$4138;
 mmDMIF_PG3_DPG_TEST_DEBUG_DATA                           =$4139;
 mmDMIF_PG3_DPG_REPEATER_PROGRAM                          =$413A;
 mmDMIF_PG3_DPG_HW_DEBUG_A                                =$413B;
 mmDMIF_PG3_DPG_HW_DEBUG_B                                =$413C;
 mmDMIF_PG3_DPG_HW_DEBUG_11                               =$413D;
 mmSCL3_SCL_COEF_RAM_SELECT                               =$4140;
 mmSCL3_SCL_COEF_RAM_TAP_DATA                             =$4141;
 mmSCL3_SCL_MODE                                          =$4142;
 mmSCL3_SCL_TAP_CONTROL                                   =$4143;
 mmSCL3_SCL_CONTROL                                       =$4144;
 mmSCL3_SCL_BYPASS_CONTROL                                =$4145;
 mmSCL3_SCL_MANUAL_REPLICATE_CONTROL                      =$4146;
 mmSCL3_SCL_AUTOMATIC_MODE_CONTROL                        =$4147;
 mmSCL3_SCL_HORZ_FILTER_CONTROL                           =$4148;
 mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO                       =$4149;
 mmSCL3_SCL_HORZ_FILTER_INIT                              =$414A;
 mmSCL3_SCL_VERT_FILTER_CONTROL                           =$414B;
 mmSCL3_SCL_VERT_FILTER_SCALE_RATIO                       =$414C;
 mmSCL3_SCL_VERT_FILTER_INIT                              =$414D;
 mmSCL3_SCL_VERT_FILTER_INIT_BOT                          =$414E;
 mmSCL3_SCL_ROUND_OFFSET                                  =$414F;
 mmSCL2_SCL_VERT_FILTER_INIT                              =$4150;
 mmSCL3_SCL_UPDATE                                        =$4151;
 mmSCL3_SCL_F_SHARP_CONTROL                               =$4153;
 mmSCL3_SCL_ALU_CONTROL                                   =$4154;
 mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS                      =$4155;
 mmSCL2_SCL_VERT_FILTER_INIT_BOT                          =$4157;
 mmSCL3_VIEWPORT_START_SECONDARY                          =$415B;
 mmSCL3_VIEWPORT_START                                    =$415C;
 mmSCL3_VIEWPORT_SIZE                                     =$415D;
 mmSCL3_EXT_OVERSCAN_LEFT_RIGHT                           =$415E;
 mmSCL3_EXT_OVERSCAN_TOP_BOTTOM                           =$415F;
 mmSCL3_SCL_MODE_CHANGE_DET1                              =$4160;
 mmSCL3_SCL_MODE_CHANGE_DET2                              =$4161;
 mmSCL3_SCL_MODE_CHANGE_DET3                              =$4162;
 mmSCL3_SCL_MODE_CHANGE_MASK                              =$4163;
 mmSCL3_SCL_DEBUG2                                        =$4169;
 mmSCL3_SCL_DEBUG                                         =$416A;
 mmSCL3_SCL_TEST_DEBUG_INDEX                              =$416B;
 mmSCL3_SCL_TEST_DEBUG_DATA                               =$416C;
 mmBLND3_BLND_CONTROL                                     =$416D;
 mmBLND3_SM_CONTROL2                                      =$416E;
 mmBLND3_BLND_CONTROL2                                    =$416F;
 mmBLND3_BLND_UPDATE                                      =$4170;
 mmBLND3_BLND_UNDERFLOW_INTERRUPT                         =$4171;
 mmBLND3_BLND_V_UPDATE_LOCK                               =$4173;
 mmBLND3_BLND_DEBUG                                       =$4174;
 mmBLND3_BLND_TEST_DEBUG_INDEX                            =$4175;
 mmBLND3_BLND_TEST_DEBUG_DATA                             =$4176;
 mmBLND3_BLND_REG_UPDATE_STATUS                           =$4177;
 mmCRTC3_CRTC_3D_STRUCTURE_CONTROL                        =$4178;
 mmCRTC3_CRTC_GSL_VSYNC_GAP                               =$4179;
 mmCRTC3_CRTC_GSL_WINDOW                                  =$417A;
 mmCRTC3_CRTC_GSL_CONTROL                                 =$417B;
 mmCRTC3_CRTC_DCFE_CLOCK_CONTROL                          =$417C;
 mmCRTC3_CRTC_H_BLANK_EARLY_NUM                           =$417D;
 mmCRTC3_DCFE_DBG_SEL                                     =$417E;
 mmCRTC3_DCFE_MEM_PWR_CTRL                                =$417F;
 mmCRTC3_CRTC_H_TOTAL                                     =$4180;
 mmCRTC3_CRTC_H_BLANK_START_END                           =$4181;
 mmCRTC3_CRTC_H_SYNC_A                                    =$4182;
 mmCRTC3_CRTC_H_SYNC_A_CNTL                               =$4183;
 mmCRTC3_CRTC_H_SYNC_B                                    =$4184;
 mmCRTC3_CRTC_H_SYNC_B_CNTL                               =$4185;
 mmCRTC3_CRTC_VBI_END                                     =$4186;
 mmCRTC3_CRTC_V_TOTAL                                     =$4187;
 mmCRTC3_CRTC_V_TOTAL_MIN                                 =$4188;
 mmCRTC3_CRTC_V_TOTAL_MAX                                 =$4189;
 mmCRTC3_CRTC_V_TOTAL_CONTROL                             =$418A;
 mmCRTC3_CRTC_V_TOTAL_INT_STATUS                          =$418B;
 mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS                        =$418C;
 mmCRTC3_CRTC_V_BLANK_START_END                           =$418D;
 mmCRTC3_CRTC_V_SYNC_A                                    =$418E;
 mmCRTC3_CRTC_V_SYNC_A_CNTL                               =$418F;
 mmCRTC3_CRTC_V_SYNC_B                                    =$4190;
 mmCRTC3_CRTC_V_SYNC_B_CNTL                               =$4191;
 mmCRTC3_CRTC_DTMTEST_CNTL                                =$4192;
 mmCRTC3_CRTC_DTMTEST_STATUS_POSITION                     =$4193;
 mmCRTC3_CRTC_TRIGA_CNTL                                  =$4194;
 mmCRTC3_CRTC_TRIGA_MANUAL_TRIG                           =$4195;
 mmCRTC3_CRTC_TRIGB_CNTL                                  =$4196;
 mmCRTC3_CRTC_TRIGB_MANUAL_TRIG                           =$4197;
 mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL                        =$4198;
 mmCRTC3_CRTC_FLOW_CONTROL                                =$4199;
 mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE                       =$419A;
 mmCRTC3_CRTC_AVSYNC_COUNTER                              =$419B;
 mmCRTC3_CRTC_CONTROL                                     =$419C;
 mmCRTC3_CRTC_BLANK_CONTROL                               =$419D;
 mmCRTC3_CRTC_INTERLACE_CONTROL                           =$419E;
 mmCRTC3_CRTC_INTERLACE_STATUS                            =$419F;
 mmCRTC3_CRTC_FIELD_INDICATION_CONTROL                    =$41A0;
 mmCRTC3_CRTC_PIXEL_DATA_READBACK0                        =$41A1;
 mmCRTC3_CRTC_PIXEL_DATA_READBACK1                        =$41A2;
 mmCRTC3_CRTC_STATUS                                      =$41A3;
 mmCRTC3_CRTC_STATUS_POSITION                             =$41A4;
 mmCRTC3_CRTC_NOM_VERT_POSITION                           =$41A5;
 mmCRTC3_CRTC_STATUS_FRAME_COUNT                          =$41A6;
 mmCRTC3_CRTC_STATUS_VF_COUNT                             =$41A7;
 mmCRTC3_CRTC_STATUS_HV_COUNT                             =$41A8;
 mmCRTC3_CRTC_COUNT_CONTROL                               =$41A9;
 mmCRTC3_CRTC_COUNT_RESET                                 =$41AA;
 mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                =$41AB;
 mmCRTC3_CRTC_VERT_SYNC_CONTROL                           =$41AC;
 mmCRTC3_CRTC_STEREO_STATUS                               =$41AD;
 mmCRTC3_CRTC_STEREO_CONTROL                              =$41AE;
 mmCRTC3_CRTC_SNAPSHOT_STATUS                             =$41AF;
 mmCRTC3_CRTC_SNAPSHOT_CONTROL                            =$41B0;
 mmCRTC3_CRTC_SNAPSHOT_POSITION                           =$41B1;
 mmCRTC3_CRTC_SNAPSHOT_FRAME                              =$41B2;
 mmCRTC3_CRTC_START_LINE_CONTROL                          =$41B3;
 mmCRTC3_CRTC_INTERRUPT_CONTROL                           =$41B4;
 mmCRTC3_CRTC_UPDATE_LOCK                                 =$41B5;
 mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL                       =$41B6;
 mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE                  =$41B7;
 mmCRTC3_DCFE_MEM_PWR_CTRL2                               =$41B8;
 mmCRTC3_DCFE_MEM_PWR_STATUS                              =$41B9;
 mmCRTC3_CRTC_TEST_PATTERN_CONTROL                        =$41BA;
 mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS                     =$41BB;
 mmCRTC3_CRTC_TEST_PATTERN_COLOR                          =$41BC;
 mmCRTC3_MASTER_UPDATE_LOCK                               =$41BD;
 mmCRTC3_MASTER_UPDATE_MODE                               =$41BE;
 mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT                      =$41BF;
 mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                =$41C0;
 mmCRTC3_CRTC_MVP_STATUS                                  =$41C1;
 mmCRTC3_CRTC_MASTER_EN                                   =$41C2;
 mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT                        =$41C3;
 mmCRTC3_CRTC_V_UPDATE_INT_STATUS                         =$41C4;
 mmCRTC3_CRTC_TEST_DEBUG_INDEX                            =$41C6;
 mmCRTC3_CRTC_TEST_DEBUG_DATA                             =$41C7;
 mmCRTC3_CRTC_OVERSCAN_COLOR                              =$41C8;
 mmCRTC3_CRTC_OVERSCAN_COLOR_EXT                          =$41C9;
 mmCRTC3_CRTC_BLANK_DATA_COLOR                            =$41CA;
 mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT                        =$41CB;
 mmCRTC3_CRTC_BLACK_COLOR                                 =$41CC;
 mmCRTC3_CRTC_BLACK_COLOR_EXT                             =$41CD;
 mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION                =$41CE;
 mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL                 =$41CF;
 mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION                =$41D0;
 mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL                 =$41D1;
 mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION                =$41D2;
 mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL                 =$41D3;
 mmCRTC3_CRTC_CRC_CNTL                                    =$41D4;
 mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL                      =$41D5;
 mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL                      =$41D6;
 mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL                      =$41D7;
 mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL                      =$41D8;
 mmCRTC3_CRTC_CRC0_DATA_RG                                =$41D9;
 mmCRTC3_CRTC_CRC0_DATA_B                                 =$41DA;
 mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL                      =$41DB;
 mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL                      =$41DC;
 mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL                      =$41DD;
 mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL                      =$41DE;
 mmCRTC3_CRTC_CRC1_DATA_RG                                =$41DF;
 mmCRTC3_CRTC_CRC1_DATA_B                                 =$41E0;
 mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL                     =$41E1;
 mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START                =$41E2;
 mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END                  =$41E3;
 mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      =$41E4;
 mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           =$41E5;
 mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    =$41E6;
 mmCRTC3_CRTC_STATIC_SCREEN_CONTROL                       =$41E7;
 mmFMT3_FMT_CLAMP_COMPONENT_R                             =$41E8;
 mmFMT3_FMT_CLAMP_COMPONENT_G                             =$41E9;
 mmFMT3_FMT_CLAMP_COMPONENT_B                             =$41EA;
 mmFMT3_FMT_TEST_DEBUG_INDEX                              =$41EB;
 mmFMT3_FMT_TEST_DEBUG_DATA                               =$41EC;
 mmFMT3_FMT_DYNAMIC_EXP_CNTL                              =$41ED;
 mmFMT3_FMT_CONTROL                                       =$41EE;
 mmFMT3_FMT_FORCE_OUTPUT_CNTL                             =$41EF;
 mmFMT3_FMT_FORCE_DATA_0_1                                =$41F0;
 mmFMT3_FMT_FORCE_DATA_2_3                                =$41F1;
 mmFMT3_FMT_BIT_DEPTH_CONTROL                             =$41F2;
 mmFMT3_FMT_DITHER_RAND_R_SEED                            =$41F3;
 mmFMT3_FMT_DITHER_RAND_G_SEED                            =$41F4;
 mmFMT3_FMT_DITHER_RAND_B_SEED                            =$41F5;
 mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL               =$41F6;
 mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX =$41F7;
 mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX =$41F8;
 mmFMT3_FMT_CLAMP_CNTL                                    =$41F9;
 mmFMT3_FMT_CRC_CNTL                                      =$41FA;
 mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK                        =$41FB;
 mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK                     =$41FC;
 mmFMT3_FMT_CRC_SIG_RED_GREEN                             =$41FD;
 mmFMT3_FMT_CRC_SIG_BLUE_CONTROL                          =$41FE;
 mmFMT3_FMT_DEBUG_CNTL                                    =$41FF;
 mmDCP4_GRPH_ENABLE                                       =$4200;
 mmDCP4_GRPH_CONTROL                                      =$4201;
 mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS                      =$4204;
 mmDCP4_GRPH_PITCH                                        =$4206;
 mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                 =$4207;
 mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH               =$4208;
 mmDCP4_GRPH_SURFACE_OFFSET_X                             =$4209;
 mmDCP4_GRPH_SURFACE_OFFSET_Y                             =$420A;
 mmDCP4_GRPH_X_START                                      =$420B;
 mmDCP4_INPUT_GAMMA_CONTROL                               =$4210;
 mmDCP4_GRPH_UPDATE                                       =$4211;
 mmDCP4_GRPH_FLIP_CONTROL                                 =$4212;
 mmDCP4_GRPH_SURFACE_ADDRESS_INUSE                        =$4213;
 mmDCP4_GRPH_DFQ_CONTROL                                  =$4214;
 mmDCP4_GRPH_DFQ_STATUS                                   =$4215;
 mmDCP4_OVL_SURFACE_ADDRESS                               =$4220;
 mmDCP4_OVL_UPDATE                                        =$4227;
 mmDCP4_OVL_SURFACE_ADDRESS_INUSE                         =$4228;
 mmDCP4_OVL_DFQ_CONTROL                                   =$4229;
 mmDCP4_OVL_DFQ_STATUS                                    =$422A;
 mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE                    =$422B;
 mmDCP4_OVLSCL_EDGE_PIXEL_CNTL                            =$422C;
 mmDCP4_PRESCALE_GRPH_CONTROL                             =$422D;
 mmDCP4_PRESCALE_VALUES_GRPH_R                            =$422E;
 mmDCP4_PRESCALE_VALUES_GRPH_G                            =$422F;
 mmDCP4_PRESCALE_VALUES_GRPH_B                            =$4230;
 mmDCP4_PRESCALE_OVL_CONTROL                              =$4231;
 mmDCP4_PRESCALE_VALUES_OVL_CB                            =$4232;
 mmDCP4_PRESCALE_VALUES_OVL_Y                             =$4233;
 mmDCP4_PRESCALE_VALUES_OVL_CR                            =$4234;
 mmDCP4_INPUT_CSC_CONTROL                                 =$4235;
 mmDCP4_INPUT_CSC_C11_C12                                 =$4236;
 mmDCP4_INPUT_CSC_C13_C14                                 =$4237;
 mmDCP4_INPUT_CSC_C21_C22                                 =$4238;
 mmDCP4_INPUT_CSC_C23_C24                                 =$4239;
 mmDCP4_INPUT_CSC_C31_C32                                 =$423A;
 mmDCP4_INPUT_CSC_C33_C34                                 =$423B;
 mmDCP4_OUTPUT_CSC_CONTROL                                =$423C;
 mmDCP4_OUTPUT_CSC_C11_C12                                =$423D;
 mmDCP4_OUTPUT_CSC_C13_C14                                =$423E;
 mmDCP4_OUTPUT_CSC_C21_C22                                =$423F;
 mmDCP4_OUTPUT_CSC_C23_C24                                =$4240;
 mmDCP4_OUTPUT_CSC_C31_C32                                =$4241;
 mmDCP4_OUTPUT_CSC_C33_C34                                =$4242;
 mmDCP4_COMM_MATRIXA_TRANS_C11_C12                        =$4243;
 mmDCP4_COMM_MATRIXA_TRANS_C13_C14                        =$4244;
 mmDCP4_COMM_MATRIXA_TRANS_C21_C22                        =$4245;
 mmDCP4_COMM_MATRIXA_TRANS_C23_C24                        =$4246;
 mmDCP4_COMM_MATRIXA_TRANS_C31_C32                        =$4247;
 mmDCP4_COMM_MATRIXA_TRANS_C33_C34                        =$4248;
 mmDCP4_COMM_MATRIXB_TRANS_C11_C12                        =$4249;
 mmDCP4_COMM_MATRIXB_TRANS_C13_C14                        =$424A;
 mmDCP4_COMM_MATRIXB_TRANS_C21_C22                        =$424B;
 mmDCP4_COMM_MATRIXB_TRANS_C23_C24                        =$424C;
 mmDCP4_COMM_MATRIXB_TRANS_C31_C32                        =$424D;
 mmDCP4_COMM_MATRIXB_TRANS_C33_C34                        =$424E;
 mmDCP4_DENORM_CONTROL                                    =$4250;
 mmDCP4_OUT_ROUND_CONTROL                                 =$4251;
 mmDCP4_OUT_CLAMP_CONTROL_R_CR                            =$4252;
 mmDCP4_KEY_CONTROL                                       =$4253;
 mmDCP4_KEY_RANGE_ALPHA                                   =$4254;
 mmDCP4_KEY_RANGE_RED                                     =$4255;
 mmDCP4_KEY_RANGE_GREEN                                   =$4256;
 mmDCP4_KEY_RANGE_BLUE                                    =$4257;
 mmDCP4_DEGAMMA_CONTROL                                   =$4258;
 mmDCP4_GAMUT_REMAP_CONTROL                               =$4259;
 mmDCP4_GAMUT_REMAP_C11_C12                               =$425A;
 mmDCP4_GAMUT_REMAP_C13_C14                               =$425B;
 mmDCP4_GAMUT_REMAP_C21_C22                               =$425C;
 mmDCP4_GAMUT_REMAP_C23_C24                               =$425D;
 mmDCP4_GAMUT_REMAP_C31_C32                               =$425E;
 mmDCP4_GAMUT_REMAP_C33_C34                               =$425F;
 mmDCP4_DCP_SPATIAL_DITHER_CNTL                           =$4260;
 mmDCP4_DCP_RANDOM_SEEDS                                  =$4261;
 mmDCP4_DCP_FP_CONVERTED_FIELD                            =$4265;
 mmDCP4_CUR_CONTROL                                       =$4266;
 mmDCP4_CUR_SURFACE_ADDRESS                               =$4267;
 mmDCP4_CUR_SIZE                                          =$4268;
 mmDCP4_CUR_SURFACE_ADDRESS_HIGH                          =$4269;
 mmDCP4_CUR_POSITION                                      =$426A;
 mmDCP4_CUR_HOT_SPOT                                      =$426B;
 mmDCP4_CUR_COLOR1                                        =$426C;
 mmDCP4_CUR_COLOR2                                        =$426D;
 mmDCP4_CUR_UPDATE                                        =$426E;
 mmDCP4_CUR2_CONTROL                                      =$426F;
 mmDCP4_CUR2_SURFACE_ADDRESS                              =$4270;
 mmDCP4_CUR2_SIZE                                         =$4271;
 mmDCP4_CUR2_SURFACE_ADDRESS_HIGH                         =$4272;
 mmDCP4_CUR2_POSITION                                     =$4273;
 mmDCP4_CUR2_HOT_SPOT                                     =$4274;
 mmDCP4_CUR2_COLOR1                                       =$4275;
 mmDCP4_CUR2_COLOR2                                       =$4276;
 mmDCP4_CUR2_UPDATE                                       =$4277;
 mmDCP4_DC_LUT_RW_MODE                                    =$4278;
 mmDCP4_DC_LUT_RW_INDEX                                   =$4279;
 mmDCP4_DC_LUT_SEQ_COLOR                                  =$427A;
 mmDCP4_DC_LUT_PWL_DATA                                   =$427B;
 mmDCP4_DC_LUT_VGA_ACCESS_ENABLE                          =$427D;
 mmDCP4_DC_LUT_WHITE_OFFSET_GREEN                         =$4285;
 mmDCP4_DCP_CRC_MASK                                      =$4288;
 mmDCP4_DCP_CRC_CURRENT                                   =$4289;
 mmDCP4_DCP_CRC_LAST                                      =$428B;
 mmDCP4_DCP_DEBUG                                         =$428D;
 mmDCP4_GRPH_FLIP_RATE_CNTL                               =$428E;
 mmDCP4_DCP_GSL_CONTROL                                   =$4290;
 mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK                     =$4291;
 mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS                     =$4292;
 mmDCP4_OVL_STEREOSYNC_FLIP                               =$4293;
 mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                =$4294;
 mmDCP4_DCP_TEST_DEBUG_INDEX                              =$4295;
 mmDCP4_DCP_TEST_DEBUG_DATA                               =$4296;
 mmDCP4_GRPH_STEREOSYNC_FLIP                              =$4297;
 mmDCP4_DCP_DEBUG2                                        =$4298;
 mmDCP4_CUR_REQUEST_FILTER_CNTL                           =$4299;
 mmDCP4_CUR_STEREO_CONTROL                                =$429A;
 mmDCP4_CUR2_STEREO_CONTROL                               =$429B;
 mmDCP4_OUT_CLAMP_CONTROL_G_Y                             =$429C;
 mmDCP4_OUT_CLAMP_CONTROL_B_CB                            =$429D;
 mmDCP4_HW_ROTATION                                       =$429E;
 mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                =$429F;
 mmDCP4_REGAMMA_CONTROL                                   =$42A0;
 mmDCP4_REGAMMA_LUT_INDEX                                 =$42A1;
 mmDCP4_REGAMMA_LUT_DATA                                  =$42A2;
 mmDCP4_REGAMMA_LUT_WRITE_EN_MASK                         =$42A3;
 mmDCP4_REGAMMA_CNTLA_START_CNTL                          =$42A4;
 mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL                          =$42A5;
 mmDCP4_REGAMMA_CNTLA_END_CNTL1                           =$42A6;
 mmDCP4_REGAMMA_CNTLA_END_CNTL2                           =$42A7;
 mmDCP4_REGAMMA_CNTLA_REGION_0_1                          =$42A8;
 mmDCP4_REGAMMA_CNTLA_REGION_2_3                          =$42A9;
 mmDCP4_REGAMMA_CNTLA_REGION_4_5                          =$42AA;
 mmDCP4_REGAMMA_CNTLA_REGION_6_7                          =$42AB;
 mmDCP4_REGAMMA_CNTLA_REGION_8_9                          =$42AC;
 mmDCP4_REGAMMA_CNTLA_REGION_10_11                        =$42AD;
 mmDCP4_REGAMMA_CNTLA_REGION_12_13                        =$42AE;
 mmDCP4_REGAMMA_CNTLA_REGION_14_15                        =$42AF;
 mmDCP4_REGAMMA_CNTLB_START_CNTL                          =$42B0;
 mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL                          =$42B1;
 mmDCP4_REGAMMA_CNTLB_END_CNTL1                           =$42B2;
 mmDCP4_REGAMMA_CNTLB_END_CNTL2                           =$42B3;
 mmDCP4_REGAMMA_CNTLB_REGION_0_1                          =$42B4;
 mmDCP4_REGAMMA_CNTLB_REGION_2_3                          =$42B5;
 mmDCP4_REGAMMA_CNTLB_REGION_4_5                          =$42B6;
 mmDCP4_REGAMMA_CNTLB_REGION_6_7                          =$42B7;
 mmDCP4_REGAMMA_CNTLB_REGION_8_9                          =$42B8;
 mmDCP4_REGAMMA_CNTLB_REGION_10_11                        =$42B9;
 mmDCP4_REGAMMA_CNTLB_REGION_12_13                        =$42BA;
 mmDCP4_REGAMMA_CNTLB_REGION_14_15                        =$42BB;
 mmDCP4_ALPHA_CONTROL                                     =$42BC;
 mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                =$42BD;
 mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH           =$42BE;
 mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS              =$42BF;
 mmLB4_LB_DATA_FORMAT                                     =$42C0;
 mmLB4_LB_MEMORY_CTRL                                     =$42C1;
 mmLB4_LB_MEMORY_SIZE_STATUS                              =$42C2;
 mmLB4_LB_DESKTOP_HEIGHT                                  =$42C3;
 mmLB4_LB_VLINE_START_END                                 =$42C4;
 mmLB4_LB_VLINE2_START_END                                =$42C5;
 mmLB4_LB_V_COUNTER                                       =$42C6;
 mmLB4_LB_SNAPSHOT_V_COUNTER                              =$42C7;
 mmLB4_LB_INTERRUPT_MASK                                  =$42C8;
 mmLB4_LB_VLINE_STATUS                                    =$42C9;
 mmLB4_LB_VLINE2_STATUS                                   =$42CA;
 mmLB4_LB_VBLANK_STATUS                                   =$42CB;
 mmLB4_LB_SYNC_RESET_SEL                                  =$42CC;
 mmLB4_LB_BLACK_KEYER_R_CR                                =$42CD;
 mmLB4_LB_BLACK_KEYER_G_Y                                 =$42CE;
 mmLB4_LB_BLACK_KEYER_B_CB                                =$42CF;
 mmLB4_LB_KEYER_COLOR_CTRL                                =$42D0;
 mmLB4_LB_KEYER_COLOR_R_CR                                =$42D1;
 mmLB4_LB_KEYER_COLOR_G_Y                                 =$42D2;
 mmLB4_LB_KEYER_COLOR_B_CB                                =$42D3;
 mmLB4_LB_KEYER_COLOR_REP_R_CR                            =$42D4;
 mmLB4_LB_KEYER_COLOR_REP_G_Y                             =$42D5;
 mmLB4_LB_KEYER_COLOR_REP_B_CB                            =$42D6;
 mmLB4_LB_BUFFER_LEVEL_STATUS                             =$42D7;
 mmLB4_LB_BUFFER_URGENCY_CTRL                             =$42D8;
 mmLB4_LB_BUFFER_URGENCY_STATUS                           =$42D9;
 mmLB4_LB_BUFFER_STATUS                                   =$42DA;
 mmLB4_LB_NO_OUTSTANDING_REQ_STATUS                       =$42DC;
 mmLB4_MVP_AFR_FLIP_MODE                                  =$42E0;
 mmLB4_MVP_AFR_FLIP_FIFO_CNTL                             =$42E1;
 mmLB4_MVP_FLIP_LINE_NUM_INSERT                           =$42E2;
 mmLB4_DC_MVP_LB_CONTROL                                  =$42E3;
 mmLB4_LB_DEBUG                                           =$42E4;
 mmLB4_LB_DEBUG2                                          =$42E5;
 mmLB4_LB_DEBUG3                                          =$42E6;
 mmLB4_LB_TEST_DEBUG_INDEX                                =$42FE;
 mmLB4_LB_TEST_DEBUG_DATA                                 =$42FF;
 mmDCFE4_DCFE_CLOCK_CONTROL                               =$4300;
 mmDCFE4_DCFE_SOFT_RESET                                  =$4301;
 mmDCFE4_DCFE_DBG_CONFIG                                  =$4302;
 mmDC_PERFMON7_PERFCOUNTER_CNTL                           =$4324;
 mmDC_PERFMON7_PERFCOUNTER_STATE                          =$4325;
 mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                    =$4326;
 mmDC_PERFMON7_PERFMON_CNTL                               =$4327;
 mmDC_PERFMON7_PERFMON_CVALUE_LOW                         =$4328;
 mmDC_PERFMON7_PERFMON_HI                                 =$4329;
 mmDC_PERFMON7_PERFMON_LOW                                =$432A;
 mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX                   =$432B;
 mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA                    =$432C;
 mmDC_PERFMON7_PERFMON_CNTL2                              =$432E;
 mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1                 =$4330;
 mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2                 =$4331;
 mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL                    =$4332;
 mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL                      =$4333;
 mmDMIF_PG4_DPG_PIPE_DPM_CONTROL                          =$4334;
 mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL                      =$4335;
 mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             =$4336;
 mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             =$4337;
 mmDMIF_PG4_DPG_TEST_DEBUG_INDEX                          =$4338;
 mmDMIF_PG4_DPG_TEST_DEBUG_DATA                           =$4339;
 mmDMIF_PG4_DPG_REPEATER_PROGRAM                          =$433A;
 mmDMIF_PG4_DPG_HW_DEBUG_A                                =$433B;
 mmDMIF_PG4_DPG_HW_DEBUG_B                                =$433C;
 mmDMIF_PG4_DPG_HW_DEBUG_11                               =$433D;
 mmSCL4_SCL_COEF_RAM_SELECT                               =$4340;
 mmSCL4_SCL_COEF_RAM_TAP_DATA                             =$4341;
 mmSCL4_SCL_MODE                                          =$4342;
 mmSCL4_SCL_TAP_CONTROL                                   =$4343;
 mmSCL4_SCL_CONTROL                                       =$4344;
 mmSCL4_SCL_BYPASS_CONTROL                                =$4345;
 mmSCL4_SCL_MANUAL_REPLICATE_CONTROL                      =$4346;
 mmSCL4_SCL_AUTOMATIC_MODE_CONTROL                        =$4347;
 mmSCL4_SCL_HORZ_FILTER_CONTROL                           =$4348;
 mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO                       =$4349;
 mmSCL4_SCL_HORZ_FILTER_INIT                              =$434A;
 mmSCL4_SCL_VERT_FILTER_CONTROL                           =$434B;
 mmSCL4_SCL_VERT_FILTER_SCALE_RATIO                       =$434C;
 mmSCL4_SCL_VERT_FILTER_INIT                              =$434D;
 mmSCL4_SCL_VERT_FILTER_INIT_BOT                          =$434E;
 mmSCL4_SCL_ROUND_OFFSET                                  =$434F;
 mmSCL4_SCL_UPDATE                                        =$4351;
 mmSCL4_SCL_F_SHARP_CONTROL                               =$4353;
 mmSCL4_SCL_ALU_CONTROL                                   =$4354;
 mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS                      =$4355;
 mmSCL4_VIEWPORT_START_SECONDARY                          =$435B;
 mmSCL4_VIEWPORT_START                                    =$435C;
 mmSCL4_VIEWPORT_SIZE                                     =$435D;
 mmSCL4_EXT_OVERSCAN_LEFT_RIGHT                           =$435E;
 mmSCL4_EXT_OVERSCAN_TOP_BOTTOM                           =$435F;
 mmSCL4_SCL_MODE_CHANGE_DET1                              =$4360;
 mmSCL4_SCL_MODE_CHANGE_DET2                              =$4361;
 mmSCL4_SCL_MODE_CHANGE_DET3                              =$4362;
 mmSCL4_SCL_MODE_CHANGE_MASK                              =$4363;
 mmSCL4_SCL_DEBUG2                                        =$4369;
 mmSCL4_SCL_DEBUG                                         =$436A;
 mmSCL4_SCL_TEST_DEBUG_INDEX                              =$436B;
 mmSCL4_SCL_TEST_DEBUG_DATA                               =$436C;
 mmBLND4_BLND_CONTROL                                     =$436D;
 mmBLND4_SM_CONTROL2                                      =$436E;
 mmBLND4_BLND_CONTROL2                                    =$436F;
 mmBLND4_BLND_UPDATE                                      =$4370;
 mmBLND4_BLND_UNDERFLOW_INTERRUPT                         =$4371;
 mmBLND4_BLND_V_UPDATE_LOCK                               =$4373;
 mmBLND4_BLND_DEBUG                                       =$4374;
 mmBLND4_BLND_TEST_DEBUG_INDEX                            =$4375;
 mmBLND4_BLND_TEST_DEBUG_DATA                             =$4376;
 mmBLND4_BLND_REG_UPDATE_STATUS                           =$4377;
 mmCRTC4_CRTC_3D_STRUCTURE_CONTROL                        =$4378;
 mmCRTC4_CRTC_GSL_VSYNC_GAP                               =$4379;
 mmCRTC4_CRTC_GSL_WINDOW                                  =$437A;
 mmCRTC4_CRTC_GSL_CONTROL                                 =$437B;
 mmCRTC4_CRTC_DCFE_CLOCK_CONTROL                          =$437C;
 mmCRTC4_CRTC_H_BLANK_EARLY_NUM                           =$437D;
 mmCRTC4_DCFE_DBG_SEL                                     =$437E;
 mmCRTC4_DCFE_MEM_PWR_CTRL                                =$437F;
 mmCRTC4_CRTC_V_TOTAL_CONTROL                             =$438A;
 mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS                        =$438C;
 mmCRTC4_CRTC_V_SYNC_A                                    =$438E;
 mmCRTC4_CRTC_V_SYNC_A_CNTL                               =$438F;
 mmCRTC4_CRTC_V_SYNC_B                                    =$4390;
 mmCRTC4_CRTC_DTMTEST_CNTL                                =$4392;
 mmCRTC4_CRTC_DTMTEST_STATUS_POSITION                     =$4393;
 mmCRTC4_CRTC_TRIGA_CNTL                                  =$4394;
 mmCRTC4_CRTC_TRIGB_MANUAL_TRIG                           =$4397;
 mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL                        =$4398;
 mmCRTC4_CRTC_FLOW_CONTROL                                =$4399;
 mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE                       =$439A;
 mmCRTC4_CRTC_AVSYNC_COUNTER                              =$439B;
 mmCRTC4_CRTC_CONTROL                                     =$439C;
 mmCRTC4_CRTC_BLANK_CONTROL                               =$439D;
 mmCRTC4_CRTC_INTERLACE_CONTROL                           =$439E;
 mmCRTC4_CRTC_INTERLACE_STATUS                            =$439F;
 mmCRTC4_CRTC_FIELD_INDICATION_CONTROL                    =$43A0;
 mmCRTC4_CRTC_PIXEL_DATA_READBACK0                        =$43A1;
 mmCRTC4_CRTC_PIXEL_DATA_READBACK1                        =$43A2;
 mmCRTC4_CRTC_STATUS                                      =$43A3;
 mmCRTC4_CRTC_STATUS_POSITION                             =$43A4;
 mmCRTC4_CRTC_NOM_VERT_POSITION                           =$43A5;
 mmCRTC4_CRTC_STATUS_FRAME_COUNT                          =$43A6;
 mmCRTC4_CRTC_STATUS_VF_COUNT                             =$43A7;
 mmCRTC4_CRTC_STATUS_HV_COUNT                             =$43A8;
 mmCRTC4_CRTC_COUNT_CONTROL                               =$43A9;
 mmCRTC4_CRTC_COUNT_RESET                                 =$43AA;
 mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                =$43AB;
 mmCRTC4_CRTC_VERT_SYNC_CONTROL                           =$43AC;
 mmCRTC4_CRTC_STEREO_STATUS                               =$43AD;
 mmCRTC4_CRTC_STEREO_CONTROL                              =$43AE;
 mmCRTC4_CRTC_SNAPSHOT_STATUS                             =$43AF;
 mmCRTC4_CRTC_SNAPSHOT_CONTROL                            =$43B0;
 mmCRTC4_CRTC_SNAPSHOT_POSITION                           =$43B1;
 mmCRTC4_CRTC_SNAPSHOT_FRAME                              =$43B2;
 mmCRTC4_CRTC_START_LINE_CONTROL                          =$43B3;
 mmCRTC4_CRTC_INTERRUPT_CONTROL                           =$43B4;
 mmCRTC4_CRTC_UPDATE_LOCK                                 =$43B5;
 mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL                       =$43B6;
 mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE                  =$43B7;
 mmCRTC4_DCFE_MEM_PWR_CTRL2                               =$43B8;
 mmCRTC4_DCFE_MEM_PWR_STATUS                              =$43B9;
 mmCRTC4_CRTC_TEST_PATTERN_CONTROL                        =$43BA;
 mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS                     =$43BB;
 mmCRTC4_CRTC_TEST_PATTERN_COLOR                          =$43BC;
 mmCRTC4_MASTER_UPDATE_LOCK                               =$43BD;
 mmCRTC4_MASTER_UPDATE_MODE                               =$43BE;
 mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT                      =$43BF;
 mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                =$43C0;
 mmCRTC4_CRTC_MVP_STATUS                                  =$43C1;
 mmCRTC4_CRTC_MASTER_EN                                   =$43C2;
 mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT                        =$43C3;
 mmCRTC4_CRTC_V_UPDATE_INT_STATUS                         =$43C4;
 mmCRTC4_CRTC_TEST_DEBUG_INDEX                            =$43C6;
 mmCRTC4_CRTC_TEST_DEBUG_DATA                             =$43C7;
 mmCRTC4_CRTC_OVERSCAN_COLOR                              =$43C8;
 mmCRTC4_CRTC_OVERSCAN_COLOR_EXT                          =$43C9;
 mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT                        =$43CB;
 mmCRTC4_CRTC_BLACK_COLOR                                 =$43CC;
 mmCRTC4_CRTC_BLACK_COLOR_EXT                             =$43CD;
 mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION                =$43CE;
 mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL                 =$43CF;
 mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION                =$43D0;
 mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL                 =$43D1;
 mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION                =$43D2;
 mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL                 =$43D3;
 mmCRTC4_CRTC_CRC_CNTL                                    =$43D4;
 mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL                      =$43D5;
 mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL                      =$43D6;
 mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL                      =$43D7;
 mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL                      =$43D8;
 mmCRTC4_CRTC_CRC0_DATA_RG                                =$43D9;
 mmCRTC4_CRTC_CRC0_DATA_B                                 =$43DA;
 mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL                      =$43DB;
 mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL                      =$43DC;
 mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL                      =$43DD;
 mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL                      =$43DE;
 mmCRTC4_CRTC_CRC1_DATA_RG                                =$43DF;
 mmCRTC4_CRTC_CRC1_DATA_B                                 =$43E0;
 mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL                     =$43E1;
 mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START                =$43E2;
 mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END                  =$43E3;
 mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      =$43E4;
 mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           =$43E5;
 mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    =$43E6;
 mmCRTC4_CRTC_STATIC_SCREEN_CONTROL                       =$43E7;
 mmFMT4_FMT_CLAMP_COMPONENT_R                             =$43E8;
 mmFMT4_FMT_CLAMP_COMPONENT_G                             =$43E9;
 mmFMT4_FMT_CLAMP_COMPONENT_B                             =$43EA;
 mmFMT4_FMT_TEST_DEBUG_INDEX                              =$43EB;
 mmFMT4_FMT_TEST_DEBUG_DATA                               =$43EC;
 mmFMT4_FMT_DYNAMIC_EXP_CNTL                              =$43ED;
 mmFMT4_FMT_CONTROL                                       =$43EE;
 mmFMT4_FMT_FORCE_OUTPUT_CNTL                             =$43EF;
 mmFMT4_FMT_FORCE_DATA_0_1                                =$43F0;
 mmFMT4_FMT_FORCE_DATA_2_3                                =$43F1;
 mmFMT4_FMT_BIT_DEPTH_CONTROL                             =$43F2;
 mmFMT4_FMT_DITHER_RAND_R_SEED                            =$43F3;
 mmFMT4_FMT_DITHER_RAND_G_SEED                            =$43F4;
 mmFMT4_FMT_DITHER_RAND_B_SEED                            =$43F5;
 mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL               =$43F6;
 mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX =$43F7;
 mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX =$43F8;
 mmFMT4_FMT_CLAMP_CNTL                                    =$43F9;
 mmFMT4_FMT_CRC_CNTL                                      =$43FA;
 mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK                        =$43FB;
 mmFMT4_FMT_CRC_SIG_RED_GREEN                             =$43FD;
 mmDCP5_GRPH_ENABLE                                       =$4400;
 mmDCP5_GRPH_CONTROL                                      =$4401;
 mmDCP5_GRPH_LUT_10BIT_BYPASS                             =$4402;
 mmDCP5_GRPH_SWAP_CNTL                                    =$4403;
 mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS                      =$4404;
 mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS                    =$4405;
 mmDCP5_GRPH_PITCH                                        =$4406;
 mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                 =$4407;
 mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH               =$4408;
 mmDCP5_GRPH_SURFACE_OFFSET_X                             =$4409;
 mmDCP5_GRPH_SURFACE_OFFSET_Y                             =$440A;
 mmDCP5_GRPH_X_START                                      =$440B;
 mmDCP5_GRPH_Y_START                                      =$440C;
 mmDCP5_GRPH_X_END                                        =$440D;
 mmDCP5_GRPH_Y_END                                        =$440E;
 mmDCP5_INPUT_GAMMA_CONTROL                               =$4410;
 mmDCP5_GRPH_UPDATE                                       =$4411;
 mmDCP5_GRPH_FLIP_CONTROL                                 =$4412;
 mmDCP5_GRPH_SURFACE_ADDRESS_INUSE                        =$4413;
 mmDCP5_GRPH_DFQ_CONTROL                                  =$4414;
 mmDCP5_GRPH_DFQ_STATUS                                   =$4415;
 mmDCP5_GRPH_INTERRUPT_STATUS                             =$4416;
 mmDCP5_GRPH_INTERRUPT_CONTROL                            =$4417;
 mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE                   =$4418;
 mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS                     =$4419;
 mmDCP5_GRPH_COMPRESS_PITCH                               =$441A;
 mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                =$441B;
 mmDCP5_OVL_ENABLE                                        =$441C;
 mmDCP5_OVL_CONTROL1                                      =$441D;
 mmDCP5_OVL_CONTROL2                                      =$441E;
 mmDCP5_OVL_SWAP_CNTL                                     =$441F;
 mmDCP5_OVL_SURFACE_ADDRESS                               =$4420;
 mmDCP5_OVL_PITCH                                         =$4421;
 mmDCP5_OVL_SURFACE_ADDRESS_HIGH                          =$4422;
 mmDCP5_OVL_SURFACE_OFFSET_X                              =$4423;
 mmDCP5_OVL_SURFACE_OFFSET_Y                              =$4424;
 mmDCP5_OVL_START                                         =$4425;
 mmDCP5_OVL_END                                           =$4426;
 mmDCP5_OVL_UPDATE                                        =$4427;
 mmDCP5_OVL_SURFACE_ADDRESS_INUSE                         =$4428;
 mmDCP5_OVL_DFQ_CONTROL                                   =$4429;
 mmDCP5_OVL_DFQ_STATUS                                    =$442A;
 mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE                    =$442B;
 mmDCP5_OVLSCL_EDGE_PIXEL_CNTL                            =$442C;
 mmDCP5_PRESCALE_GRPH_CONTROL                             =$442D;
 mmDCP5_PRESCALE_VALUES_GRPH_R                            =$442E;
 mmDCP5_PRESCALE_VALUES_GRPH_G                            =$442F;
 mmDCP5_PRESCALE_VALUES_GRPH_B                            =$4430;
 mmDCP5_PRESCALE_OVL_CONTROL                              =$4431;
 mmDCP5_PRESCALE_VALUES_OVL_CB                            =$4432;
 mmDCP5_PRESCALE_VALUES_OVL_Y                             =$4433;
 mmDCP5_PRESCALE_VALUES_OVL_CR                            =$4434;
 mmDCP5_INPUT_CSC_CONTROL                                 =$4435;
 mmDCP5_INPUT_CSC_C11_C12                                 =$4436;
 mmDCP5_INPUT_CSC_C13_C14                                 =$4437;
 mmDCP5_INPUT_CSC_C21_C22                                 =$4438;
 mmDCP5_INPUT_CSC_C23_C24                                 =$4439;
 mmDCP5_INPUT_CSC_C31_C32                                 =$443A;
 mmDCP5_INPUT_CSC_C33_C34                                 =$443B;
 mmDCP5_OUTPUT_CSC_CONTROL                                =$443C;
 mmDCP5_OUTPUT_CSC_C11_C12                                =$443D;
 mmDCP5_OUTPUT_CSC_C13_C14                                =$443E;
 mmDCP5_OUTPUT_CSC_C21_C22                                =$443F;
 mmDCP5_OUTPUT_CSC_C23_C24                                =$4440;
 mmDCP5_OUTPUT_CSC_C31_C32                                =$4441;
 mmDCP5_OUTPUT_CSC_C33_C34                                =$4442;
 mmDCP5_COMM_MATRIXA_TRANS_C11_C12                        =$4443;
 mmDCP5_COMM_MATRIXA_TRANS_C13_C14                        =$4444;
 mmDCP5_COMM_MATRIXA_TRANS_C21_C22                        =$4445;
 mmDCP5_COMM_MATRIXA_TRANS_C23_C24                        =$4446;
 mmDCP5_COMM_MATRIXA_TRANS_C31_C32                        =$4447;
 mmDCP5_COMM_MATRIXA_TRANS_C33_C34                        =$4448;
 mmDCP5_COMM_MATRIXB_TRANS_C11_C12                        =$4449;
 mmDCP5_COMM_MATRIXB_TRANS_C13_C14                        =$444A;
 mmDCP5_COMM_MATRIXB_TRANS_C21_C22                        =$444B;
 mmDCP5_COMM_MATRIXB_TRANS_C23_C24                        =$444C;
 mmDCP5_COMM_MATRIXB_TRANS_C31_C32                        =$444D;
 mmDCP5_COMM_MATRIXB_TRANS_C33_C34                        =$444E;
 mmDCP5_DENORM_CONTROL                                    =$4450;
 mmDCP5_OUT_ROUND_CONTROL                                 =$4451;
 mmDCP5_OUT_CLAMP_CONTROL_R_CR                            =$4452;
 mmDCP5_KEY_CONTROL                                       =$4453;
 mmDCP5_KEY_RANGE_ALPHA                                   =$4454;
 mmDCP5_KEY_RANGE_RED                                     =$4455;
 mmDCP5_KEY_RANGE_GREEN                                   =$4456;
 mmDCP5_KEY_RANGE_BLUE                                    =$4457;
 mmDCP5_DEGAMMA_CONTROL                                   =$4458;
 mmDCP5_GAMUT_REMAP_CONTROL                               =$4459;
 mmDCP5_GAMUT_REMAP_C11_C12                               =$445A;
 mmDCP5_GAMUT_REMAP_C13_C14                               =$445B;
 mmDCP5_GAMUT_REMAP_C21_C22                               =$445C;
 mmDCP5_GAMUT_REMAP_C23_C24                               =$445D;
 mmDCP5_GAMUT_REMAP_C31_C32                               =$445E;
 mmDCP5_GAMUT_REMAP_C33_C34                               =$445F;
 mmDCP5_DCP_SPATIAL_DITHER_CNTL                           =$4460;
 mmDCP5_DCP_RANDOM_SEEDS                                  =$4461;
 mmDCP5_DCP_FP_CONVERTED_FIELD                            =$4465;
 mmDCP5_CUR_CONTROL                                       =$4466;
 mmDCP5_CUR_SURFACE_ADDRESS                               =$4467;
 mmDCP5_CUR_SIZE                                          =$4468;
 mmDCP5_CUR_SURFACE_ADDRESS_HIGH                          =$4469;
 mmDCP5_CUR_POSITION                                      =$446A;
 mmDCP5_CUR_HOT_SPOT                                      =$446B;
 mmDCP5_CUR_COLOR1                                        =$446C;
 mmDCP5_CUR_COLOR2                                        =$446D;
 mmDCP5_CUR_UPDATE                                        =$446E;
 mmDCP5_CUR2_CONTROL                                      =$446F;
 mmDCP5_CUR2_SURFACE_ADDRESS                              =$4470;
 mmDCP5_CUR2_SIZE                                         =$4471;
 mmDCP5_CUR2_SURFACE_ADDRESS_HIGH                         =$4472;
 mmDCP5_CUR2_POSITION                                     =$4473;
 mmDCP5_CUR2_HOT_SPOT                                     =$4474;
 mmDCP5_CUR2_COLOR1                                       =$4475;
 mmDCP5_CUR2_COLOR2                                       =$4476;
 mmDCP5_CUR2_UPDATE                                       =$4477;
 mmDCP5_DC_LUT_RW_MODE                                    =$4478;
 mmDCP5_DC_LUT_RW_INDEX                                   =$4479;
 mmDCP5_DC_LUT_SEQ_COLOR                                  =$447A;
 mmDCP5_DC_LUT_PWL_DATA                                   =$447B;
 mmDCP5_DC_LUT_30_COLOR                                   =$447C;
 mmDCP5_DC_LUT_VGA_ACCESS_ENABLE                          =$447D;
 mmDCP5_DC_LUT_WRITE_EN_MASK                              =$447E;
 mmDCP5_DC_LUT_AUTOFILL                                   =$447F;
 mmDCP5_DC_LUT_CONTROL                                    =$4480;
 mmDCP5_DC_LUT_BLACK_OFFSET_BLUE                          =$4481;
 mmDCP5_DC_LUT_BLACK_OFFSET_GREEN                         =$4482;
 mmDCP5_DC_LUT_BLACK_OFFSET_RED                           =$4483;
 mmDCP5_DC_LUT_WHITE_OFFSET_BLUE                          =$4484;
 mmDCP5_DC_LUT_WHITE_OFFSET_GREEN                         =$4485;
 mmDCP5_DC_LUT_WHITE_OFFSET_RED                           =$4486;
 mmDCP5_DCP_CRC_CONTROL                                   =$4487;
 mmDCP5_DCP_CRC_MASK                                      =$4488;
 mmDCP5_DCP_CRC_CURRENT                                   =$4489;
 mmDCP5_DCP_CRC_LAST                                      =$448B;
 mmDCP5_DCP_DEBUG                                         =$448D;
 mmDCP5_GRPH_FLIP_RATE_CNTL                               =$448E;
 mmDCP5_DCP_GSL_CONTROL                                   =$4490;
 mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK                     =$4491;
 mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS                     =$4492;
 mmDCP5_OVL_STEREOSYNC_FLIP                               =$4493;
 mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                =$4494;
 mmDCP5_DCP_TEST_DEBUG_INDEX                              =$4495;
 mmDCP5_DCP_TEST_DEBUG_DATA                               =$4496;
 mmDCP5_GRPH_STEREOSYNC_FLIP                              =$4497;
 mmDCP5_DCP_DEBUG2                                        =$4498;
 mmDCP5_CUR_REQUEST_FILTER_CNTL                           =$4499;
 mmDCP5_CUR_STEREO_CONTROL                                =$449A;
 mmDCP5_CUR2_STEREO_CONTROL                               =$449B;
 mmDCP5_OUT_CLAMP_CONTROL_G_Y                             =$449C;
 mmDCP5_OUT_CLAMP_CONTROL_B_CB                            =$449D;
 mmDCP5_HW_ROTATION                                       =$449E;
 mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                =$449F;
 mmDCP5_REGAMMA_CONTROL                                   =$44A0;
 mmDCP5_REGAMMA_LUT_INDEX                                 =$44A1;
 mmDCP5_REGAMMA_LUT_DATA                                  =$44A2;
 mmDCP5_REGAMMA_LUT_WRITE_EN_MASK                         =$44A3;
 mmDCP5_REGAMMA_CNTLA_START_CNTL                          =$44A4;
 mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL                          =$44A5;
 mmDCP5_REGAMMA_CNTLA_END_CNTL1                           =$44A6;
 mmDCP5_REGAMMA_CNTLA_END_CNTL2                           =$44A7;
 mmDCP5_REGAMMA_CNTLA_REGION_0_1                          =$44A8;
 mmDCP5_REGAMMA_CNTLA_REGION_2_3                          =$44A9;
 mmDCP5_REGAMMA_CNTLA_REGION_4_5                          =$44AA;
 mmDCP5_REGAMMA_CNTLA_REGION_6_7                          =$44AB;
 mmDCP5_REGAMMA_CNTLA_REGION_8_9                          =$44AC;
 mmDCP5_REGAMMA_CNTLA_REGION_10_11                        =$44AD;
 mmDCP5_REGAMMA_CNTLA_REGION_12_13                        =$44AE;
 mmDCP5_REGAMMA_CNTLA_REGION_14_15                        =$44AF;
 mmDCP5_REGAMMA_CNTLB_START_CNTL                          =$44B0;
 mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL                          =$44B1;
 mmDCP5_REGAMMA_CNTLB_END_CNTL1                           =$44B2;
 mmDCP5_REGAMMA_CNTLB_END_CNTL2                           =$44B3;
 mmDCP5_REGAMMA_CNTLB_REGION_0_1                          =$44B4;
 mmDCP5_REGAMMA_CNTLB_REGION_2_3                          =$44B5;
 mmDCP5_REGAMMA_CNTLB_REGION_4_5                          =$44B6;
 mmDCP5_REGAMMA_CNTLB_REGION_6_7                          =$44B7;
 mmDCP5_REGAMMA_CNTLB_REGION_8_9                          =$44B8;
 mmDCP5_REGAMMA_CNTLB_REGION_10_11                        =$44B9;
 mmDCP5_REGAMMA_CNTLB_REGION_12_13                        =$44BA;
 mmDCP5_REGAMMA_CNTLB_REGION_14_15                        =$44BB;
 mmDCP5_ALPHA_CONTROL                                     =$44BC;
 mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                =$44BD;
 mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH           =$44BE;
 mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS              =$44BF;
 mmLB5_LB_DATA_FORMAT                                     =$44C0;
 mmLB5_LB_MEMORY_CTRL                                     =$44C1;
 mmLB5_LB_MEMORY_SIZE_STATUS                              =$44C2;
 mmLB5_LB_DESKTOP_HEIGHT                                  =$44C3;
 mmLB5_LB_VLINE_START_END                                 =$44C4;
 mmLB5_LB_VLINE2_START_END                                =$44C5;
 mmLB5_LB_V_COUNTER                                       =$44C6;
 mmLB5_LB_SNAPSHOT_V_COUNTER                              =$44C7;
 mmLB5_LB_INTERRUPT_MASK                                  =$44C8;
 mmLB5_LB_VLINE_STATUS                                    =$44C9;
 mmLB5_LB_VLINE2_STATUS                                   =$44CA;
 mmLB5_LB_VBLANK_STATUS                                   =$44CB;
 mmLB5_LB_SYNC_RESET_SEL                                  =$44CC;
 mmLB5_LB_BLACK_KEYER_R_CR                                =$44CD;
 mmLB5_LB_BLACK_KEYER_G_Y                                 =$44CE;
 mmLB5_LB_BLACK_KEYER_B_CB                                =$44CF;
 mmLB5_LB_KEYER_COLOR_CTRL                                =$44D0;
 mmLB5_LB_KEYER_COLOR_R_CR                                =$44D1;
 mmLB5_LB_KEYER_COLOR_G_Y                                 =$44D2;
 mmLB5_LB_KEYER_COLOR_B_CB                                =$44D3;
 mmLB5_LB_KEYER_COLOR_REP_R_CR                            =$44D4;
 mmLB5_LB_KEYER_COLOR_REP_G_Y                             =$44D5;
 mmLB5_LB_KEYER_COLOR_REP_B_CB                            =$44D6;
 mmLB5_LB_BUFFER_LEVEL_STATUS                             =$44D7;
 mmLB5_LB_BUFFER_URGENCY_CTRL                             =$44D8;
 mmLB5_LB_BUFFER_URGENCY_STATUS                           =$44D9;
 mmLB5_LB_BUFFER_STATUS                                   =$44DA;
 mmLB5_LB_NO_OUTSTANDING_REQ_STATUS                       =$44DC;
 mmLB5_MVP_AFR_FLIP_MODE                                  =$44E0;
 mmLB5_MVP_AFR_FLIP_FIFO_CNTL                             =$44E1;
 mmLB5_MVP_FLIP_LINE_NUM_INSERT                           =$44E2;
 mmLB5_DC_MVP_LB_CONTROL                                  =$44E3;
 mmLB5_LB_DEBUG                                           =$44E4;
 mmLB5_LB_DEBUG2                                          =$44E5;
 mmLB5_LB_DEBUG3                                          =$44E6;
 mmLB5_LB_TEST_DEBUG_INDEX                                =$44FE;
 mmLB5_LB_TEST_DEBUG_DATA                                 =$44FF;
 mmDCFE5_DCFE_CLOCK_CONTROL                               =$4500;
 mmDCFE5_DCFE_SOFT_RESET                                  =$4501;
 mmDCFE5_DCFE_DBG_CONFIG                                  =$4502;
 mmDIG3_HDMI_GENERIC_PACKET_CONTROL                       =$4513;
 mmDC_PERFMON8_PERFCOUNTER_CNTL                           =$4524;
 mmDC_PERFMON8_PERFCOUNTER_STATE                          =$4525;
 mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                    =$4526;
 mmDC_PERFMON8_PERFMON_CNTL                               =$4527;
 mmDC_PERFMON8_PERFMON_CVALUE_LOW                         =$4528;
 mmDC_PERFMON8_PERFMON_HI                                 =$4529;
 mmDC_PERFMON8_PERFMON_LOW                                =$452A;
 mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX                   =$452B;
 mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA                    =$452C;
 mmDC_PERFMON8_PERFMON_CNTL2                              =$452E;
 mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1                 =$4530;
 mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2                 =$4531;
 mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL                    =$4532;
 mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL                      =$4533;
 mmDMIF_PG5_DPG_PIPE_DPM_CONTROL                          =$4534;
 mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL                      =$4535;
 mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             =$4536;
 mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             =$4537;
 mmDMIF_PG5_DPG_TEST_DEBUG_INDEX                          =$4538;
 mmDMIF_PG5_DPG_TEST_DEBUG_DATA                           =$4539;
 mmDMIF_PG5_DPG_REPEATER_PROGRAM                          =$453A;
 mmDMIF_PG5_DPG_HW_DEBUG_A                                =$453B;
 mmDMIF_PG5_DPG_HW_DEBUG_B                                =$453C;
 mmDMIF_PG5_DPG_HW_DEBUG_11                               =$453D;
 mmSCL5_SCL_COEF_RAM_SELECT                               =$4540;
 mmSCL5_SCL_COEF_RAM_TAP_DATA                             =$4541;
 mmSCL5_SCL_MODE                                          =$4542;
 mmSCL5_SCL_TAP_CONTROL                                   =$4543;
 mmSCL5_SCL_CONTROL                                       =$4544;
 mmSCL5_SCL_BYPASS_CONTROL                                =$4545;
 mmSCL5_SCL_MANUAL_REPLICATE_CONTROL                      =$4546;
 mmSCL5_SCL_AUTOMATIC_MODE_CONTROL                        =$4547;
 mmSCL5_SCL_HORZ_FILTER_CONTROL                           =$4548;
 mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO                       =$4549;
 mmSCL5_SCL_HORZ_FILTER_INIT                              =$454A;
 mmSCL5_SCL_VERT_FILTER_CONTROL                           =$454B;
 mmSCL5_SCL_VERT_FILTER_SCALE_RATIO                       =$454C;
 mmSCL5_SCL_VERT_FILTER_INIT                              =$454D;
 mmSCL5_SCL_VERT_FILTER_INIT_BOT                          =$454E;
 mmSCL5_SCL_ROUND_OFFSET                                  =$454F;
 mmSCL5_SCL_UPDATE                                        =$4551;
 mmSCL5_SCL_F_SHARP_CONTROL                               =$4553;
 mmSCL5_SCL_ALU_CONTROL                                   =$4554;
 mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS                      =$4555;
 mmSCL5_VIEWPORT_START_SECONDARY                          =$455B;
 mmSCL5_VIEWPORT_START                                    =$455C;
 mmSCL5_VIEWPORT_SIZE                                     =$455D;
 mmSCL5_EXT_OVERSCAN_LEFT_RIGHT                           =$455E;
 mmSCL5_EXT_OVERSCAN_TOP_BOTTOM                           =$455F;
 mmSCL5_SCL_MODE_CHANGE_DET1                              =$4560;
 mmSCL5_SCL_MODE_CHANGE_DET2                              =$4561;
 mmSCL5_SCL_MODE_CHANGE_DET3                              =$4562;
 mmSCL5_SCL_MODE_CHANGE_MASK                              =$4563;
 mmSCL5_SCL_DEBUG2                                        =$4569;
 mmSCL5_SCL_DEBUG                                         =$456A;
 mmSCL5_SCL_TEST_DEBUG_INDEX                              =$456B;
 mmSCL5_SCL_TEST_DEBUG_DATA                               =$456C;
 mmBLND5_BLND_CONTROL                                     =$456D;
 mmBLND5_SM_CONTROL2                                      =$456E;
 mmBLND5_BLND_CONTROL2                                    =$456F;
 mmBLND5_BLND_UPDATE                                      =$4570;
 mmBLND5_BLND_UNDERFLOW_INTERRUPT                         =$4571;
 mmBLND5_BLND_V_UPDATE_LOCK                               =$4573;
 mmBLND5_BLND_DEBUG                                       =$4574;
 mmBLND5_BLND_TEST_DEBUG_INDEX                            =$4575;
 mmBLND5_BLND_TEST_DEBUG_DATA                             =$4576;
 mmBLND5_BLND_REG_UPDATE_STATUS                           =$4577;
 mmCRTC5_CRTC_3D_STRUCTURE_CONTROL                        =$4578;
 mmCRTC5_CRTC_GSL_VSYNC_GAP                               =$4579;
 mmCRTC5_CRTC_GSL_WINDOW                                  =$457A;
 mmCRTC5_CRTC_GSL_CONTROL                                 =$457B;
 mmCRTC5_CRTC_DCFE_CLOCK_CONTROL                          =$457C;
 mmCRTC5_CRTC_H_BLANK_EARLY_NUM                           =$457D;
 mmCRTC5_DCFE_DBG_SEL                                     =$457E;
 mmCRTC5_DCFE_MEM_PWR_CTRL                                =$457F;
 mmCRTC5_CRTC_H_SYNC_B_CNTL                               =$4585;
 mmCRTC5_CRTC_V_TOTAL_MIN                                 =$4588;
 mmCRTC5_CRTC_V_TOTAL_MAX                                 =$4589;
 mmCRTC5_CRTC_V_TOTAL_CONTROL                             =$458A;
 mmCRTC5_CRTC_V_TOTAL_INT_STATUS                          =$458B;
 mmCRTC5_CRTC_V_BLANK_START_END                           =$458D;
 mmCRTC5_CRTC_V_SYNC_A                                    =$458E;
 mmCRTC5_CRTC_V_SYNC_A_CNTL                               =$458F;
 mmCRTC5_CRTC_V_SYNC_B                                    =$4590;
 mmCRTC5_CRTC_V_SYNC_B_CNTL                               =$4591;
 mmCRTC5_CRTC_DTMTEST_CNTL                                =$4592;
 mmCRTC5_CRTC_DTMTEST_STATUS_POSITION                     =$4593;
 mmCRTC5_CRTC_TRIGA_CNTL                                  =$4594;
 mmCRTC5_CRTC_TRIGA_MANUAL_TRIG                           =$4595;
 mmCRTC5_CRTC_TRIGB_CNTL                                  =$4596;
 mmCRTC5_CRTC_TRIGB_MANUAL_TRIG                           =$4597;
 mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL                        =$4598;
 mmCRTC5_CRTC_FLOW_CONTROL                                =$4599;
 mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE                       =$459A;
 mmCRTC5_CRTC_AVSYNC_COUNTER                              =$459B;
 mmCRTC5_CRTC_CONTROL                                     =$459C;
 mmCRTC5_CRTC_BLANK_CONTROL                               =$459D;
 mmCRTC5_CRTC_INTERLACE_CONTROL                           =$459E;
 mmCRTC5_CRTC_INTERLACE_STATUS                            =$459F;
 mmCRTC5_CRTC_FIELD_INDICATION_CONTROL                    =$45A0;
 mmCRTC5_CRTC_PIXEL_DATA_READBACK0                        =$45A1;
 mmCRTC5_CRTC_PIXEL_DATA_READBACK1                        =$45A2;
 mmCRTC5_CRTC_STATUS                                      =$45A3;
 mmCRTC5_CRTC_STATUS_POSITION                             =$45A4;
 mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                =$45AB;
 mmCRTC5_CRTC_VERT_SYNC_CONTROL                           =$45AC;
 mmCRTC5_CRTC_STEREO_STATUS                               =$45AD;
 mmCRTC5_CRTC_STEREO_CONTROL                              =$45AE;
 mmCRTC5_CRTC_SNAPSHOT_STATUS                             =$45AF;
 mmCRTC5_CRTC_SNAPSHOT_CONTROL                            =$45B0;
 mmCRTC5_CRTC_SNAPSHOT_POSITION                           =$45B1;
 mmCRTC5_CRTC_SNAPSHOT_FRAME                              =$45B2;
 mmCRTC5_CRTC_START_LINE_CONTROL                          =$45B3;
 mmCRTC5_CRTC_INTERRUPT_CONTROL                           =$45B4;
 mmCRTC5_CRTC_UPDATE_LOCK                                 =$45B5;
 mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL                       =$45B6;
 mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE                  =$45B7;
 mmCRTC5_DCFE_MEM_PWR_CTRL2                               =$45B8;
 mmCRTC5_DCFE_MEM_PWR_STATUS                              =$45B9;
 mmCRTC5_CRTC_TEST_PATTERN_CONTROL                        =$45BA;
 mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS                     =$45BB;
 mmCRTC5_CRTC_TEST_PATTERN_COLOR                          =$45BC;
 mmCRTC5_MASTER_UPDATE_LOCK                               =$45BD;
 mmCRTC5_MASTER_UPDATE_MODE                               =$45BE;
 mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT                      =$45BF;
 mmCRTC5_CRTC_TEST_DEBUG_INDEX                            =$45C6;
 mmCRTC5_CRTC_TEST_DEBUG_DATA                             =$45C7;
 mmCRTC5_CRTC_OVERSCAN_COLOR                              =$45C8;
 mmCRTC5_CRTC_OVERSCAN_COLOR_EXT                          =$45C9;
 mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT                        =$45CB;
 mmCRTC5_CRTC_BLACK_COLOR                                 =$45CC;
 mmCRTC5_CRTC_BLACK_COLOR_EXT                             =$45CD;
 mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION                =$45CE;
 mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL                 =$45CF;
 mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION                =$45D0;
 mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL                 =$45D1;
 mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION                =$45D2;
 mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL                 =$45D3;
 mmCRTC5_CRTC_CRC_CNTL                                    =$45D4;
 mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL                      =$45D5;
 mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL                      =$45D6;
 mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL                      =$45D7;
 mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL                      =$45D8;
 mmCRTC5_CRTC_CRC0_DATA_RG                                =$45D9;
 mmCRTC5_CRTC_CRC0_DATA_B                                 =$45DA;
 mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL                      =$45DB;
 mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL                      =$45DC;
 mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL                      =$45DD;
 mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL                      =$45DE;
 mmCRTC5_CRTC_CRC1_DATA_RG                                =$45DF;
 mmCRTC5_CRTC_CRC1_DATA_B                                 =$45E0;
 mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL                     =$45E1;
 mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START                =$45E2;
 mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END                  =$45E3;
 mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      =$45E4;
 mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           =$45E5;
 mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    =$45E6;
 mmCRTC5_CRTC_STATIC_SCREEN_CONTROL                       =$45E7;
 mmFMT5_FMT_CLAMP_COMPONENT_R                             =$45E8;
 mmFMT5_FMT_CLAMP_COMPONENT_G                             =$45E9;
 mmFMT5_FMT_CLAMP_COMPONENT_B                             =$45EA;
 mmFMT5_FMT_TEST_DEBUG_INDEX                              =$45EB;
 mmFMT5_FMT_TEST_DEBUG_DATA                               =$45EC;
 mmFMT5_FMT_DYNAMIC_EXP_CNTL                              =$45ED;
 mmFMT5_FMT_CONTROL                                       =$45EE;
 mmFMT5_FMT_FORCE_OUTPUT_CNTL                             =$45EF;
 mmFMT5_FMT_FORCE_DATA_0_1                                =$45F0;
 mmFMT5_FMT_FORCE_DATA_2_3                                =$45F1;
 mmFMT5_FMT_BIT_DEPTH_CONTROL                             =$45F2;
 mmFMT5_FMT_DITHER_RAND_R_SEED                            =$45F3;
 mmFMT5_FMT_DITHER_RAND_G_SEED                            =$45F4;
 mmFMT5_FMT_DITHER_RAND_B_SEED                            =$45F5;
 mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL               =$45F6;
 mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX =$45F7;
 mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX =$45F8;
 mmFMT5_FMT_CLAMP_CNTL                                    =$45F9;
 mmFMT5_FMT_CRC_CNTL                                      =$45FA;
 mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK                        =$45FB;
 mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK                     =$45FC;
 mmFMT5_FMT_CRC_SIG_RED_GREEN                             =$45FD;
 mmFMT5_FMT_CRC_SIG_BLUE_CONTROL                          =$45FE;
 mmFMT5_FMT_DEBUG_CNTL                                    =$45FF;
 mmUNP_GRPH_ENABLE                                        =$4600;
 mmUNP_GRPH_CONTROL                                       =$4601;
 mmUNP_GRPH_CONTROL_EXP                                   =$4603;
 mmUNP_GRPH_SWAP_CNTL                                     =$4605;
 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                     =$4606;
 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                     =$4607;
 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                =$4608;
 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                =$4609;
 mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L              =$460A;
 mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C              =$460B;
 mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L         =$460C;
 mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C         =$460D;
 mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                   =$460E;
 mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                   =$460F;
 mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L              =$4610;
 mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C              =$4611;
 mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L            =$4612;
 mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C            =$4613;
 mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L       =$4614;
 mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C       =$4615;
 mmUNP_GRPH_PITCH_L                                       =$4616;
 mmUNP_GRPH_PITCH_C                                       =$4617;
 mmUNP_GRPH_SURFACE_OFFSET_X_L                            =$4618;
 mmUNP_GRPH_SURFACE_OFFSET_X_C                            =$4619;
 mmUNP_GRPH_SURFACE_OFFSET_Y_L                            =$461A;
 mmUNP_GRPH_SURFACE_OFFSET_Y_C                            =$461B;
 mmUNP_GRPH_X_START_L                                     =$461C;
 mmUNP_GRPH_X_START_C                                     =$461D;
 mmUNP_GRPH_Y_START_L                                     =$461E;
 mmUNP_GRPH_Y_START_C                                     =$461F;
 mmUNP_GRPH_X_END_L                                       =$4620;
 mmUNP_GRPH_X_END_C                                       =$4621;
 mmUNP_GRPH_Y_END_L                                       =$4622;
 mmUNP_GRPH_Y_END_C                                       =$4623;
 mmUNP_GRPH_UPDATE                                        =$4624;
 mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L                       =$4625;
 mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C                       =$4626;
 mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                  =$4627;
 mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                  =$4628;
 mmUNP_GRPH_DFQ_CONTROL                                   =$4629;
 mmUNP_GRPH_DFQ_STATUS                                    =$462A;
 mmUNP_GRPH_INTERRUPT_STATUS                              =$462B;
 mmUNP_GRPH_INTERRUPT_CONTROL                             =$462C;
 mmUNP_GRPH_STEREOSYNC_FLIP                               =$462E;
 mmUNP_GRPH_FLIP_RATE_CNTL                                =$462F;
 mmUNP_CRC_CONTROL                                        =$4630;
 mmUNP_CRC_MASK                                           =$4631;
 mmUNP_CRC_CURRENT                                        =$4632;
 mmUNP_CRC_LAST                                           =$4633;
 mmUNP_LB_DATA_GAP_BETWEEN_CHUNK                          =$4634;
 mmUNP_HW_ROTATION                                        =$4635;
 mmUNP_DEBUG                                              =$4636;
 mmUNP_DEBUG2                                             =$4637;
 mmUNP_TEST_DEBUG_INDEX                                   =$4638;
 mmUNP_TEST_DEBUG_DATA                                    =$4639;
 mmLBV_DATA_FORMAT                                        =$463C;
 mmLBV_MEMORY_CTRL                                        =$463D;
 mmLBV_MEMORY_SIZE_STATUS                                 =$463E;
 mmLBV_DESKTOP_HEIGHT                                     =$463F;
 mmLBV_VLINE_START_END                                    =$4640;
 mmLBV_VLINE2_START_END                                   =$4641;
 mmLBV_V_COUNTER                                          =$4642;
 mmLBV_SNAPSHOT_V_COUNTER                                 =$4643;
 mmLBV_V_COUNTER_CHROMA                                   =$4644;
 mmLBV_SNAPSHOT_V_COUNTER_CHROMA                          =$4645;
 mmLBV_INTERRUPT_MASK                                     =$4646;
 mmLBV_VLINE_STATUS                                       =$4647;
 mmLBV_VLINE2_STATUS                                      =$4648;
 mmLBV_VBLANK_STATUS                                      =$4649;
 mmLBV_SYNC_RESET_SEL                                     =$464A;
 mmLBV_BLACK_KEYER_R_CR                                   =$464B;
 mmLBV_BLACK_KEYER_G_Y                                    =$464C;
 mmLBV_BLACK_KEYER_B_CB                                   =$464D;
 mmLBV_KEYER_COLOR_CTRL                                   =$464E;
 mmLBV_KEYER_COLOR_R_CR                                   =$464F;
 mmLBV_KEYER_COLOR_G_Y                                    =$4650;
 mmLBV_KEYER_COLOR_B_CB                                   =$4651;
 mmLBV_KEYER_COLOR_REP_R_CR                               =$4652;
 mmLBV_KEYER_COLOR_REP_G_Y                                =$4653;
 mmLBV_KEYER_COLOR_REP_B_CB                               =$4654;
 mmLBV_BUFFER_LEVEL_STATUS                                =$4655;
 mmLBV_BUFFER_URGENCY_CTRL                                =$4656;
 mmLBV_BUFFER_URGENCY_STATUS                              =$4657;
 mmLBV_BUFFER_STATUS                                      =$4658;
 mmLBV_NO_OUTSTANDING_REQ_STATUS                          =$4659;
 mmLBV_DEBUG                                              =$465A;
 mmLBV_DEBUG2                                             =$465B;
 mmLBV_DEBUG3                                             =$465C;
 mmLBV_TEST_DEBUG_INDEX                                   =$4666;
 mmLBV_TEST_DEBUG_DATA                                    =$4667;
 mmSCLV_COEF_RAM_SELECT                                   =$4670;
 mmSCLV_COEF_RAM_TAP_DATA                                 =$4671;
 mmSCLV_MODE                                              =$4672;
 mmSCLV_TAP_CONTROL                                       =$4673;
 mmSCLV_CONTROL                                           =$4674;
 mmSCLV_MANUAL_REPLICATE_CONTROL                          =$4675;
 mmSCLV_AUTOMATIC_MODE_CONTROL                            =$4676;
 mmSCLV_HORZ_FILTER_CONTROL                               =$4677;
 mmSCLV_HORZ_FILTER_SCALE_RATIO                           =$4678;
 mmSCLV_HORZ_FILTER_INIT                                  =$4679;
 mmSCLV_HORZ_FILTER_SCALE_RATIO_C                         =$467A;
 mmSCLV_HORZ_FILTER_INIT_C                                =$467B;
 mmSCLV_VERT_FILTER_CONTROL                               =$467C;
 mmSCLV_VERT_FILTER_SCALE_RATIO                           =$467D;
 mmSCLV_VERT_FILTER_INIT                                  =$467E;
 mmSCLV_VERT_FILTER_INIT_BOT                              =$467F;
 mmSCLV_VERT_FILTER_SCALE_RATIO_C                         =$4680;
 mmSCLV_VERT_FILTER_INIT_C                                =$4681;
 mmSCLV_VERT_FILTER_INIT_BOT_C                            =$4682;
 mmSCLV_ROUND_OFFSET                                      =$4683;
 mmSCLV_UPDATE                                            =$4684;
 mmSCLV_ALU_CONTROL                                       =$4685;
 mmSCLV_VIEWPORT_START                                    =$4686;
 mmSCLV_VIEWPORT_START_SECONDARY                          =$4687;
 mmSCLV_VIEWPORT_SIZE                                     =$4688;
 mmSCLV_VIEWPORT_START_C                                  =$4689;
 mmSCLV_VIEWPORT_START_SECONDARY_C                        =$468A;
 mmSCLV_VIEWPORT_SIZE_C                                   =$468B;
 mmSCLV_EXT_OVERSCAN_LEFT_RIGHT                           =$468C;
 mmSCLV_EXT_OVERSCAN_TOP_BOTTOM                           =$468D;
 mmSCLV_MODE_CHANGE_DET1                                  =$468E;
 mmSCLV_MODE_CHANGE_DET2                                  =$468F;
 mmSCLV_MODE_CHANGE_DET3                                  =$4690;
 mmSCLV_MODE_CHANGE_MASK                                  =$4691;
 mmSCLV_DEBUG2                                            =$4692;
 mmSCLV_DEBUG                                             =$4693;
 mmSCLV_TEST_DEBUG_INDEX                                  =$4694;
 mmSCLV_TEST_DEBUG_DATA                                   =$4695;
 mmCOL_MAN_UPDATE                                         =$46A4;
 mmCOL_MAN_INPUT_CSC_CONTROL                              =$46A5;
 mmINPUT_CSC_C11_C12_A                                    =$46A6;
 mmINPUT_CSC_C13_C14_A                                    =$46A7;
 mmINPUT_CSC_C21_C22_A                                    =$46A8;
 mmINPUT_CSC_C23_C24_A                                    =$46A9;
 mmINPUT_CSC_C31_C32_A                                    =$46AA;
 mmINPUT_CSC_C33_C34_A                                    =$46AB;
 mmINPUT_CSC_C11_C12_B                                    =$46AC;
 mmINPUT_CSC_C13_C14_B                                    =$46AD;
 mmINPUT_CSC_C21_C22_B                                    =$46AE;
 mmINPUT_CSC_C23_C24_B                                    =$46AF;
 mmINPUT_CSC_C31_C32_B                                    =$46B0;
 mmINPUT_CSC_C33_C34_B                                    =$46B1;
 mmPRESCALE_CONTROL                                       =$46B2;
 mmPRESCALE_VALUES_R                                      =$46B3;
 mmPRESCALE_VALUES_G                                      =$46B4;
 mmPRESCALE_VALUES_B                                      =$46B5;
 mmCOL_MAN_OUTPUT_CSC_CONTROL                             =$46B6;
 mmOUTPUT_CSC_C11_C12_A                                   =$46B7;
 mmOUTPUT_CSC_C13_C14_A                                   =$46B8;
 mmOUTPUT_CSC_C21_C22_A                                   =$46B9;
 mmOUTPUT_CSC_C23_C24_A                                   =$46BA;
 mmOUTPUT_CSC_C31_C32_A                                   =$46BB;
 mmOUTPUT_CSC_C33_C34_A                                   =$46BC;
 mmOUTPUT_CSC_C11_C12_B                                   =$46BD;
 mmOUTPUT_CSC_C13_C14_B                                   =$46BE;
 mmOUTPUT_CSC_C21_C22_B                                   =$46BF;
 mmOUTPUT_CSC_C23_C24_B                                   =$46C0;
 mmOUTPUT_CSC_C31_C32_B                                   =$46C1;
 mmOUTPUT_CSC_C33_C34_B                                   =$46C2;
 mmDENORM_CLAMP_CONTROL                                   =$46C3;
 mmDENORM_CLAMP_RANGE_R_CR                                =$46C4;
 mmDENORM_CLAMP_RANGE_G_Y                                 =$46C5;
 mmDENORM_CLAMP_RANGE_B_CB                                =$46C6;
 mmCOL_MAN_FP_CONVERTED_FIELD                             =$46C7;
 mmGAMMA_CORR_CONTROL                                     =$46C8;
 mmGAMMA_CORR_LUT_INDEX                                   =$46C9;
 mmGAMMA_CORR_LUT_DATA                                    =$46CA;
 mmGAMMA_CORR_LUT_WRITE_EN_MASK                           =$46CB;
 mmGAMMA_CORR_CNTLA_START_CNTL                            =$46CC;
 mmGAMMA_CORR_CNTLA_SLOPE_CNTL                            =$46CD;
 mmGAMMA_CORR_CNTLA_END_CNTL1                             =$46CE;
 mmGAMMA_CORR_CNTLA_END_CNTL2                             =$46CF;
 mmGAMMA_CORR_CNTLA_REGION_0_1                            =$46D0;
 mmGAMMA_CORR_CNTLA_REGION_2_3                            =$46D1;
 mmGAMMA_CORR_CNTLA_REGION_4_5                            =$46D2;
 mmGAMMA_CORR_CNTLA_REGION_6_7                            =$46D3;
 mmGAMMA_CORR_CNTLA_REGION_8_9                            =$46D4;
 mmGAMMA_CORR_CNTLA_REGION_10_11                          =$46D5;
 mmGAMMA_CORR_CNTLA_REGION_12_13                          =$46D6;
 mmGAMMA_CORR_CNTLA_REGION_14_15                          =$46D7;
 mmGAMMA_CORR_CNTLB_START_CNTL                            =$46D8;
 mmGAMMA_CORR_CNTLB_SLOPE_CNTL                            =$46D9;
 mmGAMMA_CORR_CNTLB_END_CNTL1                             =$46DA;
 mmGAMMA_CORR_CNTLB_END_CNTL2                             =$46DB;
 mmGAMMA_CORR_CNTLB_REGION_0_1                            =$46DC;
 mmGAMMA_CORR_CNTLB_REGION_2_3                            =$46DD;
 mmGAMMA_CORR_CNTLB_REGION_4_5                            =$46DE;
 mmGAMMA_CORR_CNTLB_REGION_6_7                            =$46DF;
 mmGAMMA_CORR_CNTLB_REGION_8_9                            =$46E0;
 mmGAMMA_CORR_CNTLB_REGION_10_11                          =$46E1;
 mmGAMMA_CORR_CNTLB_REGION_12_13                          =$46E2;
 mmGAMMA_CORR_CNTLB_REGION_14_15                          =$46E3;
 mmCOL_MAN_TEST_DEBUG_INDEX                               =$46E4;
 mmCOL_MAN_TEST_DEBUG_DATA                                =$46E5;
 mmCOL_MAN_DEBUG_CONTROL                                  =$46E6;
 mmDCFEV_CLOCK_CONTROL                                    =$46F4;
 mmDCFEV_SOFT_RESET                                       =$46F5;
 mmDCFEV_DMIFV_CLOCK_CONTROL                              =$46F6;
 mmDCFEV_DBG_CONFIG                                       =$46F7;
 mmDCFEV_DMIFV_MEM_PWR_CTRL                               =$46F8;
 mmDCFEV_DMIFV_MEM_PWR_STATUS                             =$46F9;
 mmDC_PERFMON11_PERFCOUNTER_CNTL                          =$4724;
 mmDC_PERFMON11_PERFCOUNTER_STATE                         =$4725;
 mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                   =$4726;
 mmDC_PERFMON11_PERFMON_CNTL                              =$4727;
 mmDC_PERFMON11_PERFMON_CVALUE_LOW                        =$4728;
 mmDC_PERFMON11_PERFMON_HI                                =$4729;
 mmDC_PERFMON11_PERFMON_LOW                               =$472A;
 mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX                  =$472B;
 mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA                   =$472C;
 mmDC_PERFMON11_PERFMON_CNTL2                             =$472E;
 mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1                 =$4730;
 mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2                 =$4731;
 mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL                    =$4732;
 mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL                      =$4733;
 mmDMIF_PG6_DPG_PIPE_DPM_CONTROL                          =$4734;
 mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL                      =$4735;
 mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             =$4736;
 mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             =$4737;
 mmDMIF_PG6_DPG_TEST_DEBUG_INDEX                          =$4738;
 mmDMIF_PG6_DPG_TEST_DEBUG_DATA                           =$4739;
 mmDMIF_PG6_DPG_REPEATER_PROGRAM                          =$473A;
 mmDMIF_PG6_DPG_HW_DEBUG_A                                =$473B;
 mmDMIF_PG6_DPG_HW_DEBUG_B                                =$473C;
 mmDMIF_PG6_DPG_HW_DEBUG_11                               =$473D;
 mmBLND6_BLND_CONTROL                                     =$476D;
 mmBLND6_SM_CONTROL2                                      =$476E;
 mmBLND6_BLND_CONTROL2                                    =$476F;
 mmBLND6_BLND_UPDATE                                      =$4770;
 mmBLND6_BLND_UNDERFLOW_INTERRUPT                         =$4771;
 mmBLND6_BLND_V_UPDATE_LOCK                               =$4773;
 mmBLND6_BLND_DEBUG                                       =$4774;
 mmBLND6_BLND_TEST_DEBUG_INDEX                            =$4775;
 mmBLND6_BLND_TEST_DEBUG_DATA                             =$4776;
 mmBLND6_BLND_REG_UPDATE_STATUS                           =$4777;
 mmCRTC6_CRTC_3D_STRUCTURE_CONTROL                        =$4778;
 mmCRTC6_CRTC_GSL_VSYNC_GAP                               =$4779;
 mmCRTC6_CRTC_GSL_WINDOW                                  =$477A;
 mmCRTC6_CRTC_GSL_CONTROL                                 =$477B;
 mmCRTC6_CRTC_DCFE_CLOCK_CONTROL                          =$477C;
 mmCRTC6_CRTC_H_BLANK_EARLY_NUM                           =$477D;
 mmCRTC6_DCFE_DBG_SEL                                     =$477E;
 mmCRTC6_DCFE_MEM_PWR_CTRL                                =$477F;
 mmCRTC6_CRTC_H_TOTAL                                     =$4780;
 mmCRTC6_CRTC_H_BLANK_START_END                           =$4781;
 mmCRTC6_CRTC_H_SYNC_A                                    =$4782;
 mmCRTC6_CRTC_H_SYNC_A_CNTL                               =$4783;
 mmCRTC6_CRTC_H_SYNC_B                                    =$4784;
 mmCRTC6_CRTC_H_SYNC_B_CNTL                               =$4785;
 mmCRTC6_CRTC_VBI_END                                     =$4786;
 mmCRTC6_CRTC_V_TOTAL                                     =$4787;
 mmCRTC6_CRTC_V_TOTAL_MIN                                 =$4788;
 mmCRTC6_CRTC_V_TOTAL_MAX                                 =$4789;
 mmCRTC6_CRTC_V_TOTAL_CONTROL                             =$478A;
 mmCRTC6_CRTC_V_TOTAL_INT_STATUS                          =$478B;
 mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS                        =$478C;
 mmCRTC6_CRTC_V_BLANK_START_END                           =$478D;
 mmCRTC6_CRTC_V_SYNC_A                                    =$478E;
 mmCRTC6_CRTC_V_SYNC_A_CNTL                               =$478F;
 mmCRTC6_CRTC_V_SYNC_B                                    =$4790;
 mmCRTC6_CRTC_V_SYNC_B_CNTL                               =$4791;
 mmCRTC6_CRTC_DTMTEST_CNTL                                =$4792;
 mmCRTC6_CRTC_DTMTEST_STATUS_POSITION                     =$4793;
 mmCRTC6_CRTC_TRIGA_CNTL                                  =$4794;
 mmCRTC6_CRTC_TRIGA_MANUAL_TRIG                           =$4795;
 mmCRTC6_CRTC_TRIGB_CNTL                                  =$4796;
 mmCRTC6_CRTC_TRIGB_MANUAL_TRIG                           =$4797;
 mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL                        =$4798;
 mmCRTC6_CRTC_FLOW_CONTROL                                =$4799;
 mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE                       =$479A;
 mmCRTC6_CRTC_AVSYNC_COUNTER                              =$479B;
 mmCRTC6_CRTC_CONTROL                                     =$479C;
 mmCRTC6_CRTC_BLANK_CONTROL                               =$479D;
 mmCRTC6_CRTC_INTERLACE_CONTROL                           =$479E;
 mmCRTC6_CRTC_INTERLACE_STATUS                            =$479F;
 mmCRTC6_CRTC_FIELD_INDICATION_CONTROL                    =$47A0;
 mmCRTC6_CRTC_PIXEL_DATA_READBACK0                        =$47A1;
 mmCRTC6_CRTC_PIXEL_DATA_READBACK1                        =$47A2;
 mmCRTC6_CRTC_STATUS                                      =$47A3;
 mmCRTC6_CRTC_STATUS_POSITION                             =$47A4;
 mmCRTC6_CRTC_NOM_VERT_POSITION                           =$47A5;
 mmCRTC6_CRTC_STATUS_FRAME_COUNT                          =$47A6;
 mmCRTC6_CRTC_STATUS_VF_COUNT                             =$47A7;
 mmCRTC6_CRTC_STATUS_HV_COUNT                             =$47A8;
 mmCRTC6_CRTC_COUNT_CONTROL                               =$47A9;
 mmCRTC6_CRTC_COUNT_RESET                                 =$47AA;
 mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                =$47AB;
 mmCRTC6_CRTC_VERT_SYNC_CONTROL                           =$47AC;
 mmCRTC6_CRTC_STEREO_STATUS                               =$47AD;
 mmCRTC6_CRTC_STEREO_CONTROL                              =$47AE;
 mmCRTC6_CRTC_SNAPSHOT_STATUS                             =$47AF;
 mmCRTC6_CRTC_SNAPSHOT_CONTROL                            =$47B0;
 mmCRTC6_CRTC_SNAPSHOT_POSITION                           =$47B1;
 mmCRTC6_CRTC_SNAPSHOT_FRAME                              =$47B2;
 mmCRTC6_CRTC_START_LINE_CONTROL                          =$47B3;
 mmCRTC6_CRTC_INTERRUPT_CONTROL                           =$47B4;
 mmCRTC6_CRTC_UPDATE_LOCK                                 =$47B5;
 mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL                       =$47B6;
 mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE                  =$47B7;
 mmCRTC6_DCFE_MEM_PWR_CTRL2                               =$47B8;
 mmCRTC6_DCFE_MEM_PWR_STATUS                              =$47B9;
 mmCRTC6_CRTC_TEST_PATTERN_CONTROL                        =$47BA;
 mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS                     =$47BB;
 mmCRTC6_CRTC_TEST_PATTERN_COLOR                          =$47BC;
 mmCRTC6_MASTER_UPDATE_LOCK                               =$47BD;
 mmCRTC6_MASTER_UPDATE_MODE                               =$47BE;
 mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT                      =$47BF;
 mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                =$47C0;
 mmCRTC6_CRTC_MVP_STATUS                                  =$47C1;
 mmCRTC6_CRTC_MASTER_EN                                   =$47C2;
 mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT                        =$47C3;
 mmCRTC6_CRTC_V_UPDATE_INT_STATUS                         =$47C4;
 mmCRTC6_CRTC_TEST_DEBUG_INDEX                            =$47C6;
 mmCRTC6_CRTC_TEST_DEBUG_DATA                             =$47C7;
 mmCRTC6_CRTC_OVERSCAN_COLOR                              =$47C8;
 mmCRTC6_CRTC_OVERSCAN_COLOR_EXT                          =$47C9;
 mmCRTC6_CRTC_BLANK_DATA_COLOR                            =$47CA;
 mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT                        =$47CB;
 mmCRTC6_CRTC_BLACK_COLOR                                 =$47CC;
 mmCRTC6_CRTC_BLACK_COLOR_EXT                             =$47CD;
 mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION                =$47CE;
 mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL                 =$47CF;
 mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION                =$47D0;
 mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL                 =$47D1;
 mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION                =$47D2;
 mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL                 =$47D3;
 mmCRTC6_CRTC_CRC_CNTL                                    =$47D4;
 mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL                      =$47D5;
 mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL                      =$47D6;
 mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL                      =$47D7;
 mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL                      =$47D8;
 mmCRTC6_CRTC_CRC0_DATA_RG                                =$47D9;
 mmCRTC6_CRTC_CRC0_DATA_B                                 =$47DA;
 mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL                      =$47DB;
 mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL                      =$47DC;
 mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL                      =$47DD;
 mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL                      =$47DE;
 mmCRTC6_CRTC_CRC1_DATA_RG                                =$47DF;
 mmCRTC6_CRTC_CRC1_DATA_B                                 =$47E0;
 mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL                     =$47E1;
 mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START                =$47E2;
 mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END                  =$47E3;
 mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      =$47E4;
 mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           =$47E5;
 mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    =$47E6;
 mmCRTC6_CRTC_STATIC_SCREEN_CONTROL                       =$47E7;
 mmDC_GENERICA                                            =$4800;
 mmDC_GENERICB                                            =$4801;
 mmDC_PAD_EXTERN_SIG                                      =$4802;
 mmDC_REF_CLK_CNTL                                        =$4803;
 mmDC_GPIO_DEBUG                                          =$4804;
 mmUNIPHYA_LINK_CNTL                                      =$4805;
 mmUNIPHYA_CHANNEL_XBAR_CNTL                              =$4806;
 mmUNIPHYB_LINK_CNTL                                      =$4807;
 mmUNIPHYB_CHANNEL_XBAR_CNTL                              =$4808;
 mmUNIPHYC_LINK_CNTL                                      =$4809;
 mmUNIPHYC_CHANNEL_XBAR_CNTL                              =$480A;
 mmUNIPHYD_LINK_CNTL                                      =$480B;
 mmUNIPHYD_CHANNEL_XBAR_CNTL                              =$480C;
 mmUNIPHYE_LINK_CNTL                                      =$480D;
 mmUNIPHYE_CHANNEL_XBAR_CNTL                              =$480E;
 mmUNIPHYF_LINK_CNTL                                      =$480F;
 mmUNIPHYF_CHANNEL_XBAR_CNTL                              =$4810;
 mmUNIPHYG_LINK_CNTL                                      =$4811;
 mmUNIPHYG_CHANNEL_XBAR_CNTL                              =$4812;
 mmDIG4_HDMI_GENERIC_PACKET_CONTROL                       =$4813;
 mmDCIO_WRCMD_DELAY                                       =$4816;
 mmDC_PINSTRAPS                                           =$4818;
 mmDC_DVODATA_CONFIG                                      =$481A;
 mmLVTMA_PWRSEQ_CNTL                                      =$481B;
 mmLVTMA_PWRSEQ_STATE                                     =$481C;
 mmLVTMA_PWRSEQ_REF_DIV                                   =$481D;
 mmLVTMA_PWRSEQ_DELAY1                                    =$481E;
 mmLVTMA_PWRSEQ_DELAY2                                    =$481F;
 mmBL_PWM_CNTL                                            =$4820;
 mmBL_PWM_CNTL2                                           =$4821;
 mmBL_PWM_PERIOD_CNTL                                     =$4822;
 mmBL_PWM_GRP1_REG_LOCK                                   =$4823;
 mmDCIO_GSL_GENLK_PAD_CNTL                                =$4824;
 mmDCIO_GSL_SWAPLOCK_PAD_CNTL                             =$4825;
 mmDCIO_GSL0_CNTL                                         =$4826;
 mmDCIO_GSL1_CNTL                                         =$4827;
 mmDCIO_GSL2_CNTL                                         =$4828;
 mmDC_GPU_TIMER_START_POSITION_V_UPDATE                   =$4829;
 mmDC_GPU_TIMER_START_POSITION_P_FLIP                     =$482A;
 mmDC_GPU_TIMER_READ                                      =$482B;
 mmDC_GPU_TIMER_READ_CNTL                                 =$482C;
 mmDCIO_CLOCK_CNTL                                        =$482D;
 mmDCIO_DEBUG                                             =$482F;
 mmDCO_DCFE_EXT_VSYNC_CNTL                                =$4830;
 mmDCIO_TEST_DEBUG_INDEX                                  =$4831;
 mmDCIO_TEST_DEBUG_DATA                                   =$4832;
 mmDBG_OUT_CNTL                                           =$4834;
 mmDCIO_DEBUG_CONFIG                                      =$4835;
 mmDCIO_SOFT_RESET                                        =$4836;
 mmDCIO_DPHY_SEL                                          =$4837;
 mmUNIPHY_IMPCAL_LINKA                                    =$4838;
 mmUNIPHY_IMPCAL_LINKB                                    =$4839;
 mmUNIPHY_IMPCAL_PERIOD                                   =$483A;
 mmAUXP_IMPCAL                                            =$483B;
 mmAUXN_IMPCAL                                            =$483C;
 mmDCIO_IMPCAL_CNTL                                       =$483D;
 mmUNIPHY_IMPCAL_PSW_AB                                   =$483E;
 mmUNIPHY_IMPCAL_LINKC                                    =$483F;
 mmUNIPHY_IMPCAL_LINKD                                    =$4840;
 mmDCIO_IMPCAL_CNTL_CD                                    =$4841;
 mmUNIPHY_IMPCAL_PSW_CD                                   =$4842;
 mmUNIPHY_IMPCAL_LINKE                                    =$4843;
 mmUNIPHY_IMPCAL_LINKF                                    =$4844;
 mmDCIO_IMPCAL_CNTL_EF                                    =$4845;
 mmUNIPHY_IMPCAL_PSW_EF                                   =$4846;
 mmDC_GPIO_GENERIC_MASK                                   =$4860;
 mmDC_GPIO_GENERIC_A                                      =$4861;
 mmDC_GPIO_GENERIC_EN                                     =$4862;
 mmDC_GPIO_GENERIC_Y                                      =$4863;
 mmDC_GPIO_DVODATA_MASK                                   =$4864;
 mmDC_GPIO_DVODATA_A                                      =$4865;
 mmDC_GPIO_DVODATA_EN                                     =$4866;
 mmDC_GPIO_DVODATA_Y                                      =$4867;
 mmDC_GPIO_DDC1_MASK                                      =$4868;
 mmDC_GPIO_DDC1_A                                         =$4869;
 mmDC_GPIO_DDC1_EN                                        =$486A;
 mmDC_GPIO_DDC1_Y                                         =$486B;
 mmDC_GPIO_DDC2_MASK                                      =$486C;
 mmDC_GPIO_DDC2_A                                         =$486D;
 mmDC_GPIO_DDC2_EN                                        =$486E;
 mmDC_GPIO_DDC2_Y                                         =$486F;
 mmDC_GPIO_DDC3_MASK                                      =$4870;
 mmDC_GPIO_DDC3_A                                         =$4871;
 mmDC_GPIO_DDC3_EN                                        =$4872;
 mmDC_GPIO_DDC3_Y                                         =$4873;
 mmDC_GPIO_DDC4_MASK                                      =$4874;
 mmDC_GPIO_DDC4_A                                         =$4875;
 mmDC_GPIO_DDC4_EN                                        =$4876;
 mmDC_GPIO_DDC4_Y                                         =$4877;
 mmDC_GPIO_DDC5_MASK                                      =$4878;
 mmDC_GPIO_DDC5_A                                         =$4879;
 mmDC_GPIO_DDC5_EN                                        =$487A;
 mmDC_GPIO_DDC5_Y                                         =$487B;
 mmDC_GPIO_DDC6_MASK                                      =$487C;
 mmDC_GPIO_DDC6_A                                         =$487D;
 mmDC_GPIO_DDC6_EN                                        =$487E;
 mmDC_GPIO_DDC6_Y                                         =$487F;
 mmDC_GPIO_DDCVGA_MASK                                    =$4880;
 mmDC_GPIO_DDCVGA_A                                       =$4881;
 mmDC_GPIO_DDCVGA_EN                                      =$4882;
 mmDC_GPIO_DDCVGA_Y                                       =$4883;
 mmDC_GPIO_SYNCA_MASK                                     =$4884;
 mmDC_GPIO_SYNCA_A                                        =$4885;
 mmDC_GPIO_SYNCA_EN                                       =$4886;
 mmDC_GPIO_SYNCA_Y                                        =$4887;
 mmDC_GPIO_GENLK_MASK                                     =$4888;
 mmDC_GPIO_GENLK_A                                        =$4889;
 mmDC_GPIO_GENLK_EN                                       =$488A;
 mmDC_GPIO_GENLK_Y                                        =$488B;
 mmDC_GPIO_HPD_MASK                                       =$488C;
 mmDC_GPIO_HPD_A                                          =$488D;
 mmDC_GPIO_HPD_EN                                         =$488E;
 mmDC_GPIO_HPD_Y                                          =$488F;
 mmDC_GPIO_PWRSEQ_MASK                                    =$4890;
 mmDC_GPIO_PWRSEQ_A                                       =$4891;
 mmDC_GPIO_PWRSEQ_EN                                      =$4892;
 mmDC_GPIO_PWRSEQ_Y                                       =$4893;
 mmDC_GPIO_PAD_STRENGTH_1                                 =$4894;
 mmDC_GPIO_PAD_STRENGTH_2                                 =$4895;
 mmPHY_AUX_CNTL                                           =$4897;
 mmDC_GPIO_I2CPAD_MASK                                    =$4898;
 mmDC_GPIO_I2CPAD_A                                       =$4899;
 mmDC_GPIO_I2CPAD_EN                                      =$489A;
 mmDC_GPIO_I2CPAD_Y                                       =$489B;
 mmDC_GPIO_I2CPAD_STRENGTH                                =$489C;
 mmDVO_STRENGTH_CONTROL                                   =$489D;
 mmDVO_VREF_CONTROL                                       =$489E;
 mmDVO_SKEW_ADJUST                                        =$489F;
 mmDAC_MACRO_CNTL_RESERVED0                               =$48B8;
 mmBPHYC_DAC_MACRO_CNTL                                   =$48B9;
 mmBPHYC_DAC_AUTO_CALIB_CONTROL                           =$48BA;
 mmDAC_MACRO_CNTL_RESERVED3                               =$48BB;
 mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1                       =$48C0;
 mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2                       =$48C1;
 mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3                       =$48C2;
 mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4                       =$48C3;
 mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL                     =$48C4;
 mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV                         =$48C5;
 mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1                      =$48C6;
 mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2                      =$48C7;
 mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE                  =$48C8;
 mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL                       =$48C9;
 mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION              =$48CA;
 mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT                   =$48CB;
 mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL                     =$48CC;
 mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2                  =$48CD;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14              =$48CE;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15              =$48CF;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16              =$48D0;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17              =$48D1;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18              =$48D2;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19              =$48D3;
 mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL                       =$48D4;
 mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED                          =$48D5;
 mmBPHYC_UNIPHY0_UNIPHY_DEBUG                             =$48D6;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23              =$48D7;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24              =$48D8;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25              =$48D9;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26              =$48DA;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27              =$48DB;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28              =$48DC;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29              =$48DD;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30              =$48DE;
 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31              =$48DF;
 mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1                       =$48E0;
 mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2                       =$48E1;
 mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3                       =$48E2;
 mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4                       =$48E3;
 mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL                     =$48E4;
 mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV                         =$48E5;
 mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1                      =$48E6;
 mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2                      =$48E7;
 mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE                  =$48E8;
 mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL                       =$48E9;
 mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION              =$48EA;
 mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT                   =$48EB;
 mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL                     =$48EC;
 mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2                  =$48ED;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14              =$48EE;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15              =$48EF;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16              =$48F0;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17              =$48F1;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18              =$48F2;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19              =$48F3;
 mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL                       =$48F4;
 mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED                          =$48F5;
 mmBPHYC_UNIPHY1_UNIPHY_DEBUG                             =$48F6;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23              =$48F7;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24              =$48F8;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25              =$48F9;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26              =$48FA;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27              =$48FB;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28              =$48FC;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29              =$48FD;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30              =$48FE;
 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31              =$48FF;
 mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1                       =$4900;
 mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2                       =$4901;
 mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3                       =$4902;
 mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4                       =$4903;
 mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL                     =$4904;
 mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV                         =$4905;
 mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1                      =$4906;
 mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2                      =$4907;
 mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE                  =$4908;
 mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL                       =$4909;
 mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION              =$490A;
 mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT                   =$490B;
 mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL                     =$490C;
 mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2                  =$490D;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14              =$490E;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15              =$490F;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16              =$4910;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17              =$4911;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18              =$4912;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19              =$4913;
 mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL                       =$4914;
 mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED                          =$4915;
 mmBPHYC_UNIPHY2_UNIPHY_DEBUG                             =$4916;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23              =$4917;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24              =$4918;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25              =$4919;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26              =$491A;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27              =$491B;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28              =$491C;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29              =$491D;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30              =$491E;
 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31              =$491F;
 mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1                       =$4920;
 mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2                       =$4921;
 mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3                       =$4922;
 mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4                       =$4923;
 mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL                     =$4924;
 mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV                         =$4925;
 mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1                      =$4926;
 mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2                      =$4927;
 mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE                  =$4928;
 mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL                       =$4929;
 mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION              =$492A;
 mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT                   =$492B;
 mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL                     =$492C;
 mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2                  =$492D;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14              =$492E;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15              =$492F;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16              =$4930;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17              =$4931;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18              =$4932;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19              =$4933;
 mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL                       =$4934;
 mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED                          =$4935;
 mmBPHYC_UNIPHY3_UNIPHY_DEBUG                             =$4936;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23              =$4937;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24              =$4938;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25              =$4939;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26              =$493A;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27              =$493B;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28              =$493C;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29              =$493D;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30              =$493E;
 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31              =$493F;
 mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1                       =$4940;
 mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2                       =$4941;
 mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3                       =$4942;
 mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4                       =$4943;
 mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL                     =$4944;
 mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV                         =$4945;
 mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1                      =$4946;
 mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2                      =$4947;
 mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE                  =$4948;
 mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL                       =$4949;
 mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION              =$494A;
 mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT                   =$494B;
 mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL                     =$494C;
 mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2                  =$494D;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14              =$494E;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15              =$494F;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16              =$4950;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17              =$4951;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18              =$4952;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19              =$4953;
 mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL                       =$4954;
 mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED                          =$4955;
 mmBPHYC_UNIPHY4_UNIPHY_DEBUG                             =$4956;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23              =$4957;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24              =$4958;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25              =$4959;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26              =$495A;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27              =$495B;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28              =$495C;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29              =$495D;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30              =$495E;
 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31              =$495F;
 mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1                       =$4960;
 mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2                       =$4961;
 mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3                       =$4962;
 mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4                       =$4963;
 mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL                     =$4964;
 mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV                         =$4965;
 mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1                      =$4966;
 mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2                      =$4967;
 mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE                  =$4968;
 mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL                       =$4969;
 mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION              =$496A;
 mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT                   =$496B;
 mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL                     =$496C;
 mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2                  =$496D;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14              =$496E;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15              =$496F;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16              =$4970;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17              =$4971;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18              =$4972;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19              =$4973;
 mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL                       =$4974;
 mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED                          =$4975;
 mmBPHYC_UNIPHY5_UNIPHY_DEBUG                             =$4976;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23              =$4977;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24              =$4978;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25              =$4979;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26              =$497A;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27              =$497B;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28              =$497C;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29              =$497D;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30              =$497E;
 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31              =$497F;
 mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1                       =$4980;
 mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2                       =$4981;
 mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3                       =$4982;
 mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4                       =$4983;
 mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL                     =$4984;
 mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV                         =$4985;
 mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1                      =$4986;
 mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2                      =$4987;
 mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE                  =$4988;
 mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL                       =$4989;
 mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION              =$498A;
 mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT                   =$498B;
 mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL                     =$498C;
 mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2                  =$498D;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14              =$498E;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15              =$498F;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16              =$4990;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17              =$4991;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18              =$4992;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19              =$4993;
 mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL                       =$4994;
 mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED                          =$4995;
 mmBPHYC_UNIPHY6_UNIPHY_DEBUG                             =$4996;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23              =$4997;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24              =$4998;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25              =$4999;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26              =$499A;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27              =$499B;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28              =$499C;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29              =$499D;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30              =$499E;
 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31              =$499F;
 mmDIG0_DIG_FE_CNTL                                       =$4A00;
 mmDIG0_DIG_OUTPUT_CRC_CNTL                               =$4A01;
 mmDIG0_DIG_OUTPUT_CRC_RESULT                             =$4A02;
 mmDIG0_DIG_CLOCK_PATTERN                                 =$4A03;
 mmDIG0_DIG_TEST_PATTERN                                  =$4A04;
 mmDIG0_DIG_RANDOM_PATTERN_SEED                           =$4A05;
 mmDIG0_DIG_FIFO_STATUS                                   =$4A06;
 mmDIG0_DIG_DISPCLK_SWITCH_CNTL                           =$4A07;
 mmDIG0_DIG_DISPCLK_SWITCH_STATUS                         =$4A08;
 mmDIG0_HDMI_CONTROL                                      =$4A09;
 mmDIG0_HDMI_STATUS                                       =$4A0A;
 mmDIG0_HDMI_AUDIO_PACKET_CONTROL                         =$4A0B;
 mmDIG0_HDMI_ACR_PACKET_CONTROL                           =$4A0C;
 mmDIG0_HDMI_VBI_PACKET_CONTROL                           =$4A0D;
 mmDIG0_HDMI_INFOFRAME_CONTROL0                           =$4A0E;
 mmDIG0_HDMI_INFOFRAME_CONTROL1                           =$4A0F;
 mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                      =$4A10;
 mmDIG0_HDMI_GC                                           =$4A13;
 mmAFMT_AUDIO_PACKET_CONTROL2                             =$4A14;
 mmAFMT_ISRC1_0                                           =$4A15;
 mmAFMT_ISRC1_1                                           =$4A16;
 mmAFMT_ISRC1_2                                           =$4A17;
 mmAFMT_ISRC1_3                                           =$4A18;
 mmAFMT_ISRC1_4                                           =$4A19;
 mmAFMT_ISRC2_0                                           =$4A1A;
 mmAFMT_ISRC2_1                                           =$4A1B;
 mmAFMT_ISRC2_2                                           =$4A1C;
 mmAFMT_ISRC2_3                                           =$4A1D;
 mmAFMT_AVI_INFO0                                         =$4A1E;
 mmAFMT_AVI_INFO1                                         =$4A1F;
 mmAFMT_AVI_INFO2                                         =$4A20;
 mmAFMT_AVI_INFO3                                         =$4A21;
 mmAFMT_MPEG_INFO0                                        =$4A22;
 mmAFMT_MPEG_INFO1                                        =$4A23;
 mmAFMT_GENERIC_HDR                                       =$4A24;
 mmAFMT_GENERIC_0                                         =$4A25;
 mmAFMT_GENERIC_1                                         =$4A26;
 mmAFMT_GENERIC_2                                         =$4A27;
 mmAFMT_GENERIC_3                                         =$4A28;
 mmAFMT_GENERIC_4                                         =$4A29;
 mmAFMT_GENERIC_5                                         =$4A2A;
 mmAFMT_GENERIC_6                                         =$4A2B;
 mmAFMT_GENERIC_7                                         =$4A2C;
 mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                      =$4A2D;
 mmDIG0_HDMI_ACR_32_0                                     =$4A2E;
 mmDIG0_HDMI_ACR_32_1                                     =$4A2F;
 mmDIG0_HDMI_ACR_44_0                                     =$4A30;
 mmDIG0_HDMI_ACR_44_1                                     =$4A31;
 mmDIG0_HDMI_ACR_48_0                                     =$4A32;
 mmDIG0_HDMI_ACR_48_1                                     =$4A33;
 mmDIG0_HDMI_ACR_STATUS_0                                 =$4A34;
 mmDIG0_HDMI_ACR_STATUS_1                                 =$4A35;
 mmAFMT_AUDIO_INFO0                                       =$4A36;
 mmAFMT_AUDIO_INFO1                                       =$4A37;
 mmAFMT_60958_0                                           =$4A38;
 mmAFMT_60958_1                                           =$4A39;
 mmAFMT_AUDIO_CRC_CONTROL                                 =$4A3A;
 mmAFMT_RAMP_CONTROL0                                     =$4A3B;
 mmAFMT_RAMP_CONTROL1                                     =$4A3C;
 mmAFMT_RAMP_CONTROL2                                     =$4A3D;
 mmAFMT_RAMP_CONTROL3                                     =$4A3E;
 mmAFMT_60958_2                                           =$4A3F;
 mmAFMT_AUDIO_CRC_RESULT                                  =$4A40;
 mmAFMT_STATUS                                            =$4A41;
 mmAFMT_AUDIO_PACKET_CONTROL                              =$4A42;
 mmAFMT_VBI_PACKET_CONTROL                                =$4A43;
 mmAFMT_INFOFRAME_CONTROL0                                =$4A44;
 mmAFMT_AUDIO_SRC_CONTROL                                 =$4A45;
 mmAFMT_AUDIO_DBG_DTO_CNTL                                =$4A46;
 mmDIG0_DIG_BE_CNTL                                       =$4A47;
 mmDIG0_DIG_BE_EN_CNTL                                    =$4A48;
 mmDIG0_TMDS_CNTL                                         =$4A6B;
 mmDIG0_TMDS_CONTROL_CHAR                                 =$4A6C;
 mmDIG0_TMDS_CONTROL0_FEEDBACK                            =$4A6D;
 mmDIG0_TMDS_STEREOSYNC_CTL_SEL                           =$4A6E;
 mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                        =$4A6F;
 mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                        =$4A70;
 mmDIG0_TMDS_DEBUG                                        =$4A71;
 mmDIG0_TMDS_CTL_BITS                                     =$4A72;
 mmDIG0_TMDS_DCBALANCER_CONTROL                           =$4A73;
 mmDIG0_TMDS_CTL0_1_GEN_CNTL                              =$4A75;
 mmDIG0_TMDS_CTL2_3_GEN_CNTL                              =$4A76;
 mmDIG0_LVDS_DATA_CNTL                                    =$4A78;
 mmDIG0_DIG_LANE_ENABLE                                   =$4A79;
 mmDIG0_DIG_TEST_DEBUG_INDEX                              =$4A7A;
 mmDIG0_DIG_TEST_DEBUG_DATA                               =$4A7B;
 mmDIG0_DIG_FE_TEST_DEBUG_INDEX                           =$4A7C;
 mmDIG0_DIG_FE_TEST_DEBUG_DATA                            =$4A7D;
 mmCRTC5_CRTC_PIXEL_DATA_READBACK                         =$4A9A;
 mmDP0_DP_LINK_CNTL                                       =$4AA0;
 mmDP0_DP_PIXEL_FORMAT                                    =$4AA1;
 mmDP0_DP_MSA_COLORIMETRY                                 =$4AA2;
 mmDP0_DP_CONFIG                                          =$4AA3;
 mmDP0_DP_VID_STREAM_CNTL                                 =$4AA4;
 mmDP0_DP_STEER_FIFO                                      =$4AA5;
 mmDP0_DP_MSA_MISC                                        =$4AA6;
 mmDP0_DP_VID_TIMING                                      =$4AA8;
 mmDP0_DP_VID_N                                           =$4AA9;
 mmDP0_DP_VID_M                                           =$4AAA;
 mmDP0_DP_LINK_FRAMING_CNTL                               =$4AAB;
 mmDP0_DP_HBR2_EYE_PATTERN                                =$4AAC;
 mmDP0_DP_VID_MSA_VBID                                    =$4AAD;
 mmDP0_DP_VID_INTERRUPT_CNTL                              =$4AAE;
 mmDP0_DP_DPHY_CNTL                                       =$4AAF;
 mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                       =$4AB0;
 mmDP0_DP_DPHY_SYM0                                       =$4AB1;
 mmDP0_DP_DPHY_SYM1                                       =$4AB2;
 mmDP0_DP_DPHY_SYM2                                       =$4AB3;
 mmDP0_DP_DPHY_8B10B_CNTL                                 =$4AB4;
 mmDP0_DP_DPHY_PRBS_CNTL                                  =$4AB5;
 mmDP0_DP_DPHY_CRC_EN                                     =$4AB7;
 mmDP0_DP_DPHY_CRC_CNTL                                   =$4AB8;
 mmDP0_DP_DPHY_CRC_RESULT                                 =$4AB9;
 mmDP0_DP_DPHY_CRC_MST_CNTL                               =$4ABA;
 mmDP0_DP_DPHY_CRC_MST_STATUS                             =$4ABB;
 mmDP0_DP_DPHY_FAST_TRAINING                              =$4ABC;
 mmDP0_DP_DPHY_FAST_TRAINING_STATUS                       =$4ABD;
 mmDP0_DP_MSA_V_TIMING_OVERRIDE1                          =$4ABE;
 mmDP0_DP_MSA_V_TIMING_OVERRIDE2                          =$4ABF;
 mmDP0_DP_SEC_CNTL                                        =$4AC3;
 mmDP0_DP_SEC_CNTL1                                       =$4AC4;
 mmDP0_DP_SEC_FRAMING1                                    =$4AC5;
 mmDP0_DP_SEC_FRAMING2                                    =$4AC6;
 mmDP0_DP_SEC_FRAMING3                                    =$4AC7;
 mmDP0_DP_SEC_FRAMING4                                    =$4AC8;
 mmDP0_DP_SEC_AUD_N                                       =$4AC9;
 mmDP0_DP_SEC_AUD_N_READBACK                              =$4ACA;
 mmDP0_DP_SEC_AUD_M                                       =$4ACB;
 mmDP0_DP_SEC_AUD_M_READBACK                              =$4ACC;
 mmDP0_DP_SEC_TIMESTAMP                                   =$4ACD;
 mmDP0_DP_SEC_PACKET_CNTL                                 =$4ACE;
 mmDP0_DP_MSE_RATE_CNTL                                   =$4ACF;
 mmDP0_DP_MSE_RATE_UPDATE                                 =$4AD1;
 mmDP0_DP_MSE_SAT0                                        =$4AD2;
 mmDP0_DP_MSE_SAT1                                        =$4AD3;
 mmDP0_DP_MSE_SAT2                                        =$4AD4;
 mmDP0_DP_MSE_SAT_UPDATE                                  =$4AD5;
 mmDP0_DP_MSE_LINK_TIMING                                 =$4AD6;
 mmDP0_DP_MSE_MISC_CNTL                                   =$4AD7;
 mmDP0_DP_TEST_DEBUG_INDEX                                =$4AD8;
 mmDP0_DP_TEST_DEBUG_DATA                                 =$4AD9;
 mmDP0_DP_FE_TEST_DEBUG_INDEX                             =$4ADA;
 mmDP0_DP_FE_TEST_DEBUG_DATA                              =$4ADB;
 mmDIG1_DIG_FE_CNTL                                       =$4B00;
 mmDIG1_DIG_OUTPUT_CRC_CNTL                               =$4B01;
 mmDIG1_DIG_OUTPUT_CRC_RESULT                             =$4B02;
 mmDIG1_DIG_CLOCK_PATTERN                                 =$4B03;
 mmDIG1_DIG_TEST_PATTERN                                  =$4B04;
 mmDIG1_DIG_RANDOM_PATTERN_SEED                           =$4B05;
 mmDIG1_DIG_FIFO_STATUS                                   =$4B06;
 mmDIG1_DIG_DISPCLK_SWITCH_CNTL                           =$4B07;
 mmDIG1_DIG_DISPCLK_SWITCH_STATUS                         =$4B08;
 mmDIG1_HDMI_CONTROL                                      =$4B09;
 mmDIG1_HDMI_STATUS                                       =$4B0A;
 mmDIG1_HDMI_AUDIO_PACKET_CONTROL                         =$4B0B;
 mmDIG1_HDMI_ACR_PACKET_CONTROL                           =$4B0C;
 mmDIG1_HDMI_VBI_PACKET_CONTROL                           =$4B0D;
 mmDIG1_HDMI_INFOFRAME_CONTROL0                           =$4B0E;
 mmDIG1_HDMI_INFOFRAME_CONTROL1                           =$4B0F;
 mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                      =$4B10;
 mmDIG1_HDMI_GC                                           =$4B13;
 mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                        =$4B14;
 mmDIG1_AFMT_ISRC1_0                                      =$4B15;
 mmDIG1_AFMT_ISRC1_1                                      =$4B16;
 mmDIG1_AFMT_ISRC1_2                                      =$4B17;
 mmDIG1_AFMT_ISRC1_3                                      =$4B18;
 mmDIG1_AFMT_ISRC1_4                                      =$4B19;
 mmDIG1_AFMT_ISRC2_0                                      =$4B1A;
 mmDIG1_AFMT_ISRC2_1                                      =$4B1B;
 mmDIG1_AFMT_ISRC2_2                                      =$4B1C;
 mmDIG1_AFMT_ISRC2_3                                      =$4B1D;
 mmDIG1_AFMT_AVI_INFO0                                    =$4B1E;
 mmDIG1_AFMT_AVI_INFO1                                    =$4B1F;
 mmDIG1_AFMT_AVI_INFO2                                    =$4B20;
 mmDIG1_AFMT_AVI_INFO3                                    =$4B21;
 mmDIG1_AFMT_MPEG_INFO0                                   =$4B22;
 mmDIG1_AFMT_MPEG_INFO1                                   =$4B23;
 mmDIG1_AFMT_GENERIC_HDR                                  =$4B24;
 mmDIG1_AFMT_GENERIC_0                                    =$4B25;
 mmDIG1_AFMT_GENERIC_1                                    =$4B26;
 mmDIG1_AFMT_GENERIC_2                                    =$4B27;
 mmDIG1_AFMT_GENERIC_3                                    =$4B28;
 mmDIG1_AFMT_GENERIC_4                                    =$4B29;
 mmDIG1_AFMT_GENERIC_5                                    =$4B2A;
 mmDIG1_AFMT_GENERIC_6                                    =$4B2B;
 mmDIG1_AFMT_GENERIC_7                                    =$4B2C;
 mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                      =$4B2D;
 mmDIG1_HDMI_ACR_32_0                                     =$4B2E;
 mmDIG1_HDMI_ACR_32_1                                     =$4B2F;
 mmDIG1_HDMI_ACR_44_0                                     =$4B30;
 mmDIG1_HDMI_ACR_44_1                                     =$4B31;
 mmDIG1_HDMI_ACR_48_0                                     =$4B32;
 mmDIG1_HDMI_ACR_48_1                                     =$4B33;
 mmDIG1_HDMI_ACR_STATUS_0                                 =$4B34;
 mmDIG1_HDMI_ACR_STATUS_1                                 =$4B35;
 mmDIG1_AFMT_AUDIO_INFO0                                  =$4B36;
 mmDIG1_AFMT_AUDIO_INFO1                                  =$4B37;
 mmDIG1_AFMT_60958_0                                      =$4B38;
 mmDIG1_AFMT_60958_1                                      =$4B39;
 mmDIG1_AFMT_AUDIO_CRC_CONTROL                            =$4B3A;
 mmDIG1_AFMT_RAMP_CONTROL0                                =$4B3B;
 mmDIG1_AFMT_RAMP_CONTROL1                                =$4B3C;
 mmDIG1_AFMT_RAMP_CONTROL2                                =$4B3D;
 mmDIG1_AFMT_RAMP_CONTROL3                                =$4B3E;
 mmDIG1_AFMT_60958_2                                      =$4B3F;
 mmDIG1_AFMT_AUDIO_CRC_RESULT                             =$4B40;
 mmDIG1_AFMT_STATUS                                       =$4B41;
 mmDIG1_AFMT_AUDIO_PACKET_CONTROL                         =$4B42;
 mmDIG1_AFMT_VBI_PACKET_CONTROL                           =$4B43;
 mmDIG1_AFMT_INFOFRAME_CONTROL0                           =$4B44;
 mmDIG1_AFMT_AUDIO_SRC_CONTROL                            =$4B45;
 mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL                           =$4B46;
 mmDIG1_DIG_BE_CNTL                                       =$4B47;
 mmDIG1_DIG_BE_EN_CNTL                                    =$4B48;
 mmDIG1_TMDS_CNTL                                         =$4B6B;
 mmDIG1_TMDS_CONTROL_CHAR                                 =$4B6C;
 mmDIG1_TMDS_CONTROL0_FEEDBACK                            =$4B6D;
 mmDIG1_TMDS_STEREOSYNC_CTL_SEL                           =$4B6E;
 mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                        =$4B6F;
 mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                        =$4B70;
 mmDIG1_TMDS_DEBUG                                        =$4B71;
 mmDIG1_TMDS_CTL_BITS                                     =$4B72;
 mmDIG1_TMDS_DCBALANCER_CONTROL                           =$4B73;
 mmDIG1_TMDS_CTL0_1_GEN_CNTL                              =$4B75;
 mmDIG1_TMDS_CTL2_3_GEN_CNTL                              =$4B76;
 mmDIG1_LVDS_DATA_CNTL                                    =$4B78;
 mmDIG1_DIG_LANE_ENABLE                                   =$4B79;
 mmDIG1_DIG_TEST_DEBUG_INDEX                              =$4B7A;
 mmDIG1_DIG_TEST_DEBUG_DATA                               =$4B7B;
 mmDIG1_DIG_FE_TEST_DEBUG_INDEX                           =$4B7C;
 mmDIG1_DIG_FE_TEST_DEBUG_DATA                            =$4B7D;
 mmDP1_DP_LINK_CNTL                                       =$4BA0;
 mmDP1_DP_PIXEL_FORMAT                                    =$4BA1;
 mmDP1_DP_MSA_COLORIMETRY                                 =$4BA2;
 mmDP1_DP_CONFIG                                          =$4BA3;
 mmDP1_DP_VID_STREAM_CNTL                                 =$4BA4;
 mmDP1_DP_STEER_FIFO                                      =$4BA5;
 mmDP1_DP_MSA_MISC                                        =$4BA6;
 mmDP1_DP_VID_TIMING                                      =$4BA8;
 mmDP1_DP_VID_N                                           =$4BA9;
 mmDP1_DP_VID_M                                           =$4BAA;
 mmDP1_DP_LINK_FRAMING_CNTL                               =$4BAB;
 mmDP1_DP_HBR2_EYE_PATTERN                                =$4BAC;
 mmDP1_DP_VID_MSA_VBID                                    =$4BAD;
 mmDP1_DP_VID_INTERRUPT_CNTL                              =$4BAE;
 mmDP1_DP_DPHY_CNTL                                       =$4BAF;
 mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                       =$4BB0;
 mmDP1_DP_DPHY_SYM0                                       =$4BB1;
 mmDP1_DP_DPHY_SYM1                                       =$4BB2;
 mmDP1_DP_DPHY_SYM2                                       =$4BB3;
 mmDP1_DP_DPHY_8B10B_CNTL                                 =$4BB4;
 mmDP1_DP_DPHY_PRBS_CNTL                                  =$4BB5;
 mmDP1_DP_DPHY_CRC_EN                                     =$4BB7;
 mmDP1_DP_DPHY_CRC_CNTL                                   =$4BB8;
 mmDP1_DP_DPHY_CRC_RESULT                                 =$4BB9;
 mmDP1_DP_DPHY_CRC_MST_CNTL                               =$4BBA;
 mmDP1_DP_DPHY_CRC_MST_STATUS                             =$4BBB;
 mmDP1_DP_DPHY_FAST_TRAINING                              =$4BBC;
 mmDP1_DP_DPHY_FAST_TRAINING_STATUS                       =$4BBD;
 mmDP1_DP_MSA_V_TIMING_OVERRIDE1                          =$4BBE;
 mmDP1_DP_MSA_V_TIMING_OVERRIDE2                          =$4BBF;
 mmDP1_DP_SEC_CNTL                                        =$4BC3;
 mmDP1_DP_SEC_CNTL1                                       =$4BC4;
 mmDP1_DP_SEC_FRAMING1                                    =$4BC5;
 mmDP1_DP_SEC_FRAMING2                                    =$4BC6;
 mmDP1_DP_SEC_FRAMING3                                    =$4BC7;
 mmDP1_DP_SEC_FRAMING4                                    =$4BC8;
 mmDP1_DP_SEC_AUD_N                                       =$4BC9;
 mmDP1_DP_SEC_AUD_N_READBACK                              =$4BCA;
 mmDP1_DP_SEC_AUD_M                                       =$4BCB;
 mmDP1_DP_SEC_AUD_M_READBACK                              =$4BCC;
 mmDP1_DP_SEC_TIMESTAMP                                   =$4BCD;
 mmDP1_DP_SEC_PACKET_CNTL                                 =$4BCE;
 mmDP1_DP_MSE_RATE_CNTL                                   =$4BCF;
 mmDP1_DP_MSE_RATE_UPDATE                                 =$4BD1;
 mmDP1_DP_MSE_SAT0                                        =$4BD2;
 mmDP1_DP_MSE_SAT1                                        =$4BD3;
 mmDP1_DP_MSE_SAT2                                        =$4BD4;
 mmDP1_DP_MSE_SAT_UPDATE                                  =$4BD5;
 mmDP1_DP_MSE_LINK_TIMING                                 =$4BD6;
 mmDP1_DP_MSE_MISC_CNTL                                   =$4BD7;
 mmDP1_DP_TEST_DEBUG_INDEX                                =$4BD8;
 mmDP1_DP_TEST_DEBUG_DATA                                 =$4BD9;
 mmDP1_DP_FE_TEST_DEBUG_INDEX                             =$4BDA;
 mmDP1_DP_FE_TEST_DEBUG_DATA                              =$4BDB;
 mmDIG2_DIG_FE_CNTL                                       =$4C00;
 mmDIG2_DIG_OUTPUT_CRC_CNTL                               =$4C01;
 mmDIG2_DIG_OUTPUT_CRC_RESULT                             =$4C02;
 mmDIG2_DIG_CLOCK_PATTERN                                 =$4C03;
 mmDIG2_DIG_TEST_PATTERN                                  =$4C04;
 mmDIG2_DIG_RANDOM_PATTERN_SEED                           =$4C05;
 mmDIG2_DIG_FIFO_STATUS                                   =$4C06;
 mmDIG2_DIG_DISPCLK_SWITCH_CNTL                           =$4C07;
 mmDIG2_DIG_DISPCLK_SWITCH_STATUS                         =$4C08;
 mmDIG2_HDMI_CONTROL                                      =$4C09;
 mmDIG2_HDMI_STATUS                                       =$4C0A;
 mmDIG2_HDMI_AUDIO_PACKET_CONTROL                         =$4C0B;
 mmDIG2_HDMI_ACR_PACKET_CONTROL                           =$4C0C;
 mmDIG2_HDMI_VBI_PACKET_CONTROL                           =$4C0D;
 mmDIG2_HDMI_INFOFRAME_CONTROL0                           =$4C0E;
 mmDIG2_HDMI_INFOFRAME_CONTROL1                           =$4C0F;
 mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                      =$4C10;
 mmDIG2_HDMI_GC                                           =$4C13;
 mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                        =$4C14;
 mmDIG2_AFMT_ISRC1_0                                      =$4C15;
 mmDIG2_AFMT_ISRC1_1                                      =$4C16;
 mmDIG2_AFMT_ISRC1_2                                      =$4C17;
 mmDIG2_AFMT_ISRC1_3                                      =$4C18;
 mmDIG2_AFMT_ISRC1_4                                      =$4C19;
 mmDIG2_AFMT_ISRC2_0                                      =$4C1A;
 mmDIG2_AFMT_ISRC2_1                                      =$4C1B;
 mmDIG2_AFMT_ISRC2_2                                      =$4C1C;
 mmDIG2_AFMT_ISRC2_3                                      =$4C1D;
 mmDIG2_AFMT_AVI_INFO0                                    =$4C1E;
 mmDIG2_AFMT_AVI_INFO1                                    =$4C1F;
 mmDIG2_AFMT_AVI_INFO2                                    =$4C20;
 mmDIG2_AFMT_AVI_INFO3                                    =$4C21;
 mmDIG2_AFMT_MPEG_INFO0                                   =$4C22;
 mmDIG2_AFMT_MPEG_INFO1                                   =$4C23;
 mmDIG2_AFMT_GENERIC_HDR                                  =$4C24;
 mmDIG2_AFMT_GENERIC_0                                    =$4C25;
 mmDIG2_AFMT_GENERIC_1                                    =$4C26;
 mmDIG2_AFMT_GENERIC_2                                    =$4C27;
 mmDIG2_AFMT_GENERIC_3                                    =$4C28;
 mmDIG2_AFMT_GENERIC_4                                    =$4C29;
 mmDIG2_AFMT_GENERIC_5                                    =$4C2A;
 mmDIG2_AFMT_GENERIC_6                                    =$4C2B;
 mmDIG2_AFMT_GENERIC_7                                    =$4C2C;
 mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                      =$4C2D;
 mmDIG2_HDMI_ACR_32_0                                     =$4C2E;
 mmDIG2_HDMI_ACR_32_1                                     =$4C2F;
 mmDIG2_HDMI_ACR_44_0                                     =$4C30;
 mmDIG2_HDMI_ACR_44_1                                     =$4C31;
 mmDIG2_HDMI_ACR_48_0                                     =$4C32;
 mmDIG2_HDMI_ACR_48_1                                     =$4C33;
 mmDIG2_HDMI_ACR_STATUS_0                                 =$4C34;
 mmDIG2_HDMI_ACR_STATUS_1                                 =$4C35;
 mmDIG2_AFMT_AUDIO_INFO0                                  =$4C36;
 mmDIG2_AFMT_AUDIO_INFO1                                  =$4C37;
 mmDIG2_AFMT_60958_0                                      =$4C38;
 mmDIG2_AFMT_60958_1                                      =$4C39;
 mmDIG2_AFMT_AUDIO_CRC_CONTROL                            =$4C3A;
 mmDIG2_AFMT_RAMP_CONTROL0                                =$4C3B;
 mmDIG2_AFMT_RAMP_CONTROL1                                =$4C3C;
 mmDIG2_AFMT_RAMP_CONTROL2                                =$4C3D;
 mmDIG2_AFMT_RAMP_CONTROL3                                =$4C3E;
 mmDIG2_AFMT_60958_2                                      =$4C3F;
 mmDIG2_AFMT_AUDIO_CRC_RESULT                             =$4C40;
 mmDIG2_AFMT_STATUS                                       =$4C41;
 mmDIG2_AFMT_AUDIO_PACKET_CONTROL                         =$4C42;
 mmDIG2_AFMT_VBI_PACKET_CONTROL                           =$4C43;
 mmDIG2_AFMT_INFOFRAME_CONTROL0                           =$4C44;
 mmDIG2_AFMT_AUDIO_SRC_CONTROL                            =$4C45;
 mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL                           =$4C46;
 mmDIG2_DIG_BE_CNTL                                       =$4C47;
 mmDIG2_DIG_BE_EN_CNTL                                    =$4C48;
 mmDIG2_TMDS_CNTL                                         =$4C6B;
 mmDIG2_TMDS_CONTROL_CHAR                                 =$4C6C;
 mmDIG2_TMDS_CONTROL0_FEEDBACK                            =$4C6D;
 mmDIG2_TMDS_STEREOSYNC_CTL_SEL                           =$4C6E;
 mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                        =$4C6F;
 mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                        =$4C70;
 mmDIG2_TMDS_DEBUG                                        =$4C71;
 mmDIG2_TMDS_CTL_BITS                                     =$4C72;
 mmDIG2_TMDS_DCBALANCER_CONTROL                           =$4C73;
 mmDIG2_TMDS_CTL0_1_GEN_CNTL                              =$4C75;
 mmDIG2_TMDS_CTL2_3_GEN_CNTL                              =$4C76;
 mmDIG2_LVDS_DATA_CNTL                                    =$4C78;
 mmDIG2_DIG_LANE_ENABLE                                   =$4C79;
 mmDIG2_DIG_TEST_DEBUG_INDEX                              =$4C7A;
 mmDIG2_DIG_TEST_DEBUG_DATA                               =$4C7B;
 mmDIG2_DIG_FE_TEST_DEBUG_INDEX                           =$4C7C;
 mmDIG2_DIG_FE_TEST_DEBUG_DATA                            =$4C7D;
 mmDP2_DP_LINK_CNTL                                       =$4CA0;
 mmDP2_DP_PIXEL_FORMAT                                    =$4CA1;
 mmDP2_DP_MSA_COLORIMETRY                                 =$4CA2;
 mmDP2_DP_CONFIG                                          =$4CA3;
 mmDP2_DP_VID_STREAM_CNTL                                 =$4CA4;
 mmDP2_DP_STEER_FIFO                                      =$4CA5;
 mmDP2_DP_MSA_MISC                                        =$4CA6;
 mmDP2_DP_VID_TIMING                                      =$4CA8;
 mmDP2_DP_VID_N                                           =$4CA9;
 mmDP2_DP_VID_M                                           =$4CAA;
 mmDP2_DP_LINK_FRAMING_CNTL                               =$4CAB;
 mmDP2_DP_HBR2_EYE_PATTERN                                =$4CAC;
 mmDP2_DP_VID_MSA_VBID                                    =$4CAD;
 mmDP2_DP_VID_INTERRUPT_CNTL                              =$4CAE;
 mmDP2_DP_DPHY_CNTL                                       =$4CAF;
 mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                       =$4CB0;
 mmDP2_DP_DPHY_SYM0                                       =$4CB1;
 mmDP2_DP_DPHY_SYM1                                       =$4CB2;
 mmDP2_DP_DPHY_SYM2                                       =$4CB3;
 mmDP2_DP_DPHY_8B10B_CNTL                                 =$4CB4;
 mmDP2_DP_DPHY_PRBS_CNTL                                  =$4CB5;
 mmDP2_DP_DPHY_CRC_EN                                     =$4CB7;
 mmDP2_DP_DPHY_CRC_CNTL                                   =$4CB8;
 mmDP2_DP_DPHY_CRC_RESULT                                 =$4CB9;
 mmDP2_DP_DPHY_CRC_MST_CNTL                               =$4CBA;
 mmDP2_DP_DPHY_CRC_MST_STATUS                             =$4CBB;
 mmDP2_DP_DPHY_FAST_TRAINING                              =$4CBC;
 mmDP2_DP_DPHY_FAST_TRAINING_STATUS                       =$4CBD;
 mmDP2_DP_MSA_V_TIMING_OVERRIDE1                          =$4CBE;
 mmDP2_DP_MSA_V_TIMING_OVERRIDE2                          =$4CBF;
 mmDP2_DP_SEC_CNTL                                        =$4CC3;
 mmDP2_DP_SEC_CNTL1                                       =$4CC4;
 mmDP2_DP_SEC_FRAMING1                                    =$4CC5;
 mmDP2_DP_SEC_FRAMING2                                    =$4CC6;
 mmDP2_DP_SEC_FRAMING3                                    =$4CC7;
 mmDP2_DP_SEC_FRAMING4                                    =$4CC8;
 mmDP2_DP_SEC_AUD_N                                       =$4CC9;
 mmDP2_DP_SEC_AUD_N_READBACK                              =$4CCA;
 mmDP2_DP_SEC_AUD_M                                       =$4CCB;
 mmDP2_DP_SEC_AUD_M_READBACK                              =$4CCC;
 mmDP2_DP_SEC_TIMESTAMP                                   =$4CCD;
 mmDP2_DP_SEC_PACKET_CNTL                                 =$4CCE;
 mmDP2_DP_MSE_RATE_CNTL                                   =$4CCF;
 mmDP2_DP_MSE_RATE_UPDATE                                 =$4CD1;
 mmDP2_DP_MSE_SAT0                                        =$4CD2;
 mmDP2_DP_MSE_SAT1                                        =$4CD3;
 mmDP2_DP_MSE_SAT2                                        =$4CD4;
 mmDP2_DP_MSE_SAT_UPDATE                                  =$4CD5;
 mmDP2_DP_MSE_LINK_TIMING                                 =$4CD6;
 mmDP2_DP_MSE_MISC_CNTL                                   =$4CD7;
 mmDP2_DP_TEST_DEBUG_INDEX                                =$4CD8;
 mmDP2_DP_TEST_DEBUG_DATA                                 =$4CD9;
 mmDP2_DP_FE_TEST_DEBUG_INDEX                             =$4CDA;
 mmDP2_DP_FE_TEST_DEBUG_DATA                              =$4CDB;
 mmDIG3_DIG_FE_CNTL                                       =$4D00;
 mmDIG3_DIG_OUTPUT_CRC_CNTL                               =$4D01;
 mmDIG3_DIG_OUTPUT_CRC_RESULT                             =$4D02;
 mmDIG3_DIG_CLOCK_PATTERN                                 =$4D03;
 mmDIG3_DIG_TEST_PATTERN                                  =$4D04;
 mmDIG3_DIG_RANDOM_PATTERN_SEED                           =$4D05;
 mmDIG3_DIG_FIFO_STATUS                                   =$4D06;
 mmDIG3_DIG_DISPCLK_SWITCH_CNTL                           =$4D07;
 mmDIG3_DIG_DISPCLK_SWITCH_STATUS                         =$4D08;
 mmDIG3_HDMI_CONTROL                                      =$4D09;
 mmDIG3_HDMI_STATUS                                       =$4D0A;
 mmDIG3_HDMI_AUDIO_PACKET_CONTROL                         =$4D0B;
 mmDIG3_HDMI_ACR_PACKET_CONTROL                           =$4D0C;
 mmDIG3_HDMI_VBI_PACKET_CONTROL                           =$4D0D;
 mmDIG3_HDMI_INFOFRAME_CONTROL0                           =$4D0E;
 mmDIG3_HDMI_INFOFRAME_CONTROL1                           =$4D0F;
 mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                      =$4D10;
 mmDIG3_HDMI_GC                                           =$4D13;
 mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                        =$4D14;
 mmDIG3_AFMT_ISRC1_0                                      =$4D15;
 mmDIG3_AFMT_ISRC1_1                                      =$4D16;
 mmDIG3_AFMT_ISRC1_2                                      =$4D17;
 mmDIG3_AFMT_ISRC1_3                                      =$4D18;
 mmDIG3_AFMT_ISRC1_4                                      =$4D19;
 mmDIG3_AFMT_ISRC2_0                                      =$4D1A;
 mmDIG3_AFMT_ISRC2_1                                      =$4D1B;
 mmDIG3_AFMT_ISRC2_2                                      =$4D1C;
 mmDIG3_AFMT_ISRC2_3                                      =$4D1D;
 mmDIG3_AFMT_AVI_INFO0                                    =$4D1E;
 mmDIG3_AFMT_AVI_INFO1                                    =$4D1F;
 mmDIG3_AFMT_AVI_INFO2                                    =$4D20;
 mmDIG3_AFMT_AVI_INFO3                                    =$4D21;
 mmDIG3_AFMT_MPEG_INFO0                                   =$4D22;
 mmDIG3_AFMT_MPEG_INFO1                                   =$4D23;
 mmDIG3_AFMT_GENERIC_HDR                                  =$4D24;
 mmDIG3_AFMT_GENERIC_0                                    =$4D25;
 mmDIG3_AFMT_GENERIC_1                                    =$4D26;
 mmDIG3_AFMT_GENERIC_2                                    =$4D27;
 mmDIG3_AFMT_GENERIC_3                                    =$4D28;
 mmDIG3_AFMT_GENERIC_4                                    =$4D29;
 mmDIG3_AFMT_GENERIC_5                                    =$4D2A;
 mmDIG3_AFMT_GENERIC_6                                    =$4D2B;
 mmDIG3_AFMT_GENERIC_7                                    =$4D2C;
 mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                      =$4D2D;
 mmDIG3_HDMI_ACR_32_0                                     =$4D2E;
 mmDIG3_HDMI_ACR_32_1                                     =$4D2F;
 mmDIG3_HDMI_ACR_44_0                                     =$4D30;
 mmDIG3_HDMI_ACR_44_1                                     =$4D31;
 mmDIG3_HDMI_ACR_48_0                                     =$4D32;
 mmDIG3_HDMI_ACR_48_1                                     =$4D33;
 mmDIG3_HDMI_ACR_STATUS_0                                 =$4D34;
 mmDIG3_HDMI_ACR_STATUS_1                                 =$4D35;
 mmDIG3_AFMT_AUDIO_INFO0                                  =$4D36;
 mmDIG3_AFMT_AUDIO_INFO1                                  =$4D37;
 mmDIG3_AFMT_60958_0                                      =$4D38;
 mmDIG3_AFMT_60958_1                                      =$4D39;
 mmDIG3_AFMT_AUDIO_CRC_CONTROL                            =$4D3A;
 mmDIG3_AFMT_RAMP_CONTROL0                                =$4D3B;
 mmDIG3_AFMT_RAMP_CONTROL1                                =$4D3C;
 mmDIG3_AFMT_RAMP_CONTROL2                                =$4D3D;
 mmDIG3_AFMT_RAMP_CONTROL3                                =$4D3E;
 mmDIG3_AFMT_60958_2                                      =$4D3F;
 mmDIG3_AFMT_AUDIO_CRC_RESULT                             =$4D40;
 mmDIG3_AFMT_STATUS                                       =$4D41;
 mmDIG3_AFMT_AUDIO_PACKET_CONTROL                         =$4D42;
 mmDIG3_AFMT_VBI_PACKET_CONTROL                           =$4D43;
 mmDIG3_AFMT_INFOFRAME_CONTROL0                           =$4D44;
 mmDIG3_AFMT_AUDIO_SRC_CONTROL                            =$4D45;
 mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL                           =$4D46;
 mmDIG3_DIG_BE_CNTL                                       =$4D47;
 mmDIG3_DIG_BE_EN_CNTL                                    =$4D48;
 mmDIG3_TMDS_CNTL                                         =$4D6B;
 mmDIG3_TMDS_CONTROL_CHAR                                 =$4D6C;
 mmDIG3_TMDS_CONTROL0_FEEDBACK                            =$4D6D;
 mmDIG3_TMDS_STEREOSYNC_CTL_SEL                           =$4D6E;
 mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                        =$4D6F;
 mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                        =$4D70;
 mmDIG3_TMDS_DEBUG                                        =$4D71;
 mmDIG3_TMDS_CTL_BITS                                     =$4D72;
 mmDIG3_TMDS_DCBALANCER_CONTROL                           =$4D73;
 mmDIG3_TMDS_CTL0_1_GEN_CNTL                              =$4D75;
 mmDIG3_TMDS_CTL2_3_GEN_CNTL                              =$4D76;
 mmDIG3_LVDS_DATA_CNTL                                    =$4D78;
 mmDIG3_DIG_LANE_ENABLE                                   =$4D79;
 mmDIG3_DIG_TEST_DEBUG_INDEX                              =$4D7A;
 mmDIG3_DIG_TEST_DEBUG_DATA                               =$4D7B;
 mmDIG3_DIG_FE_TEST_DEBUG_INDEX                           =$4D7C;
 mmDIG3_DIG_FE_TEST_DEBUG_DATA                            =$4D7D;
 mmDP3_DP_LINK_CNTL                                       =$4DA0;
 mmDP3_DP_PIXEL_FORMAT                                    =$4DA1;
 mmDP3_DP_MSA_COLORIMETRY                                 =$4DA2;
 mmDP3_DP_CONFIG                                          =$4DA3;
 mmDP3_DP_VID_STREAM_CNTL                                 =$4DA4;
 mmDP3_DP_STEER_FIFO                                      =$4DA5;
 mmDP3_DP_MSA_MISC                                        =$4DA6;
 mmDP3_DP_VID_TIMING                                      =$4DA8;
 mmDP3_DP_VID_N                                           =$4DA9;
 mmDP3_DP_VID_M                                           =$4DAA;
 mmDP3_DP_LINK_FRAMING_CNTL                               =$4DAB;
 mmDP3_DP_HBR2_EYE_PATTERN                                =$4DAC;
 mmDP3_DP_VID_MSA_VBID                                    =$4DAD;
 mmDP3_DP_VID_INTERRUPT_CNTL                              =$4DAE;
 mmDP3_DP_DPHY_CNTL                                       =$4DAF;
 mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                       =$4DB0;
 mmDP3_DP_DPHY_SYM0                                       =$4DB1;
 mmDP3_DP_DPHY_SYM1                                       =$4DB2;
 mmDP3_DP_DPHY_SYM2                                       =$4DB3;
 mmDP3_DP_DPHY_8B10B_CNTL                                 =$4DB4;
 mmDP3_DP_DPHY_PRBS_CNTL                                  =$4DB5;
 mmDP3_DP_DPHY_CRC_EN                                     =$4DB7;
 mmDP3_DP_DPHY_CRC_CNTL                                   =$4DB8;
 mmDP3_DP_DPHY_CRC_RESULT                                 =$4DB9;
 mmDP3_DP_DPHY_CRC_MST_CNTL                               =$4DBA;
 mmDP3_DP_DPHY_CRC_MST_STATUS                             =$4DBB;
 mmDP3_DP_DPHY_FAST_TRAINING                              =$4DBC;
 mmDP3_DP_DPHY_FAST_TRAINING_STATUS                       =$4DBD;
 mmDP3_DP_MSA_V_TIMING_OVERRIDE1                          =$4DBE;
 mmDP3_DP_MSA_V_TIMING_OVERRIDE2                          =$4DBF;
 mmDP3_DP_SEC_CNTL                                        =$4DC3;
 mmDP3_DP_SEC_CNTL1                                       =$4DC4;
 mmDP3_DP_SEC_FRAMING1                                    =$4DC5;
 mmDP3_DP_SEC_FRAMING2                                    =$4DC6;
 mmDP3_DP_SEC_FRAMING3                                    =$4DC7;
 mmDP3_DP_SEC_FRAMING4                                    =$4DC8;
 mmDP3_DP_SEC_AUD_N                                       =$4DC9;
 mmDP3_DP_SEC_AUD_N_READBACK                              =$4DCA;
 mmDP3_DP_SEC_AUD_M                                       =$4DCB;
 mmDP3_DP_SEC_AUD_M_READBACK                              =$4DCC;
 mmDP3_DP_SEC_TIMESTAMP                                   =$4DCD;
 mmDP3_DP_SEC_PACKET_CNTL                                 =$4DCE;
 mmDP3_DP_MSE_RATE_CNTL                                   =$4DCF;
 mmDP3_DP_MSE_RATE_UPDATE                                 =$4DD1;
 mmDP3_DP_MSE_SAT0                                        =$4DD2;
 mmDP3_DP_MSE_SAT1                                        =$4DD3;
 mmDP3_DP_MSE_SAT2                                        =$4DD4;
 mmDP3_DP_MSE_SAT_UPDATE                                  =$4DD5;
 mmDP3_DP_MSE_LINK_TIMING                                 =$4DD6;
 mmDP3_DP_MSE_MISC_CNTL                                   =$4DD7;
 mmDP3_DP_TEST_DEBUG_INDEX                                =$4DD8;
 mmDP3_DP_TEST_DEBUG_DATA                                 =$4DD9;
 mmDP3_DP_FE_TEST_DEBUG_INDEX                             =$4DDA;
 mmDP3_DP_FE_TEST_DEBUG_DATA                              =$4DDB;
 mmDIG4_DIG_FE_CNTL                                       =$4E00;
 mmDIG4_DIG_OUTPUT_CRC_CNTL                               =$4E01;
 mmDIG4_DIG_OUTPUT_CRC_RESULT                             =$4E02;
 mmDIG4_DIG_CLOCK_PATTERN                                 =$4E03;
 mmDIG4_DIG_TEST_PATTERN                                  =$4E04;
 mmDIG4_DIG_RANDOM_PATTERN_SEED                           =$4E05;
 mmDIG4_DIG_FIFO_STATUS                                   =$4E06;
 mmDIG4_DIG_DISPCLK_SWITCH_CNTL                           =$4E07;
 mmDIG4_DIG_DISPCLK_SWITCH_STATUS                         =$4E08;
 mmDIG4_HDMI_CONTROL                                      =$4E09;
 mmDIG4_HDMI_STATUS                                       =$4E0A;
 mmDIG4_HDMI_AUDIO_PACKET_CONTROL                         =$4E0B;
 mmDIG4_HDMI_ACR_PACKET_CONTROL                           =$4E0C;
 mmDIG4_HDMI_VBI_PACKET_CONTROL                           =$4E0D;
 mmDIG4_HDMI_INFOFRAME_CONTROL0                           =$4E0E;
 mmDIG4_HDMI_INFOFRAME_CONTROL1                           =$4E0F;
 mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                      =$4E10;
 mmDIG4_HDMI_GC                                           =$4E13;
 mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                        =$4E14;
 mmDIG4_AFMT_ISRC1_0                                      =$4E15;
 mmDIG4_AFMT_ISRC1_1                                      =$4E16;
 mmDIG4_AFMT_ISRC1_2                                      =$4E17;
 mmDIG4_AFMT_ISRC1_3                                      =$4E18;
 mmDIG4_AFMT_ISRC1_4                                      =$4E19;
 mmDIG4_AFMT_ISRC2_0                                      =$4E1A;
 mmDIG4_AFMT_ISRC2_1                                      =$4E1B;
 mmDIG4_AFMT_ISRC2_2                                      =$4E1C;
 mmDIG4_AFMT_ISRC2_3                                      =$4E1D;
 mmDIG4_AFMT_AVI_INFO0                                    =$4E1E;
 mmDIG4_AFMT_AVI_INFO1                                    =$4E1F;
 mmDIG4_AFMT_AVI_INFO2                                    =$4E20;
 mmDIG4_AFMT_AVI_INFO3                                    =$4E21;
 mmDIG4_AFMT_MPEG_INFO0                                   =$4E22;
 mmDIG4_AFMT_MPEG_INFO1                                   =$4E23;
 mmDIG4_AFMT_GENERIC_HDR                                  =$4E24;
 mmDIG4_AFMT_GENERIC_0                                    =$4E25;
 mmDIG4_AFMT_GENERIC_1                                    =$4E26;
 mmDIG4_AFMT_GENERIC_2                                    =$4E27;
 mmDIG4_AFMT_GENERIC_3                                    =$4E28;
 mmDIG4_AFMT_GENERIC_4                                    =$4E29;
 mmDIG4_AFMT_GENERIC_5                                    =$4E2A;
 mmDIG4_AFMT_GENERIC_6                                    =$4E2B;
 mmDIG4_AFMT_GENERIC_7                                    =$4E2C;
 mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                      =$4E2D;
 mmDIG4_HDMI_ACR_32_0                                     =$4E2E;
 mmDIG4_HDMI_ACR_32_1                                     =$4E2F;
 mmDIG4_HDMI_ACR_44_0                                     =$4E30;
 mmDIG4_HDMI_ACR_44_1                                     =$4E31;
 mmDIG4_HDMI_ACR_48_0                                     =$4E32;
 mmDIG4_HDMI_ACR_48_1                                     =$4E33;
 mmDIG4_HDMI_ACR_STATUS_0                                 =$4E34;
 mmDIG4_HDMI_ACR_STATUS_1                                 =$4E35;
 mmDIG4_AFMT_AUDIO_INFO0                                  =$4E36;
 mmDIG4_AFMT_AUDIO_INFO1                                  =$4E37;
 mmDIG4_AFMT_60958_0                                      =$4E38;
 mmDIG4_AFMT_60958_1                                      =$4E39;
 mmDIG4_AFMT_AUDIO_CRC_CONTROL                            =$4E3A;
 mmDIG4_AFMT_RAMP_CONTROL0                                =$4E3B;
 mmDIG4_AFMT_RAMP_CONTROL1                                =$4E3C;
 mmDIG4_AFMT_RAMP_CONTROL2                                =$4E3D;
 mmDIG4_AFMT_RAMP_CONTROL3                                =$4E3E;
 mmDIG4_AFMT_60958_2                                      =$4E3F;
 mmDIG4_AFMT_AUDIO_CRC_RESULT                             =$4E40;
 mmDIG4_AFMT_STATUS                                       =$4E41;
 mmDIG4_AFMT_AUDIO_PACKET_CONTROL                         =$4E42;
 mmDIG4_AFMT_VBI_PACKET_CONTROL                           =$4E43;
 mmDIG4_AFMT_INFOFRAME_CONTROL0                           =$4E44;
 mmDIG4_AFMT_AUDIO_SRC_CONTROL                            =$4E45;
 mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL                           =$4E46;
 mmDIG4_DIG_BE_CNTL                                       =$4E47;
 mmDIG4_DIG_BE_EN_CNTL                                    =$4E48;
 mmDIG4_TMDS_CNTL                                         =$4E6B;
 mmDIG4_TMDS_CONTROL_CHAR                                 =$4E6C;
 mmDIG4_TMDS_CONTROL0_FEEDBACK                            =$4E6D;
 mmDIG4_TMDS_STEREOSYNC_CTL_SEL                           =$4E6E;
 mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                        =$4E6F;
 mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                        =$4E70;
 mmDIG4_TMDS_DEBUG                                        =$4E71;
 mmDIG4_TMDS_CTL_BITS                                     =$4E72;
 mmDIG4_TMDS_DCBALANCER_CONTROL                           =$4E73;
 mmDIG4_TMDS_CTL0_1_GEN_CNTL                              =$4E75;
 mmDIG4_TMDS_CTL2_3_GEN_CNTL                              =$4E76;
 mmDIG4_LVDS_DATA_CNTL                                    =$4E78;
 mmDIG4_DIG_LANE_ENABLE                                   =$4E79;
 mmDIG4_DIG_TEST_DEBUG_INDEX                              =$4E7A;
 mmDIG4_DIG_TEST_DEBUG_DATA                               =$4E7B;
 mmDIG4_DIG_FE_TEST_DEBUG_INDEX                           =$4E7C;
 mmDIG4_DIG_FE_TEST_DEBUG_DATA                            =$4E7D;
 mmDP4_DP_LINK_CNTL                                       =$4EA0;
 mmDP4_DP_PIXEL_FORMAT                                    =$4EA1;
 mmDP4_DP_MSA_COLORIMETRY                                 =$4EA2;
 mmDP4_DP_CONFIG                                          =$4EA3;
 mmDP4_DP_VID_STREAM_CNTL                                 =$4EA4;
 mmDP4_DP_STEER_FIFO                                      =$4EA5;
 mmDP4_DP_MSA_MISC                                        =$4EA6;
 mmDP4_DP_VID_TIMING                                      =$4EA8;
 mmDP4_DP_VID_N                                           =$4EA9;
 mmDP4_DP_VID_M                                           =$4EAA;
 mmDP4_DP_LINK_FRAMING_CNTL                               =$4EAB;
 mmDP4_DP_HBR2_EYE_PATTERN                                =$4EAC;
 mmDP4_DP_VID_MSA_VBID                                    =$4EAD;
 mmDP4_DP_VID_INTERRUPT_CNTL                              =$4EAE;
 mmDP4_DP_DPHY_CNTL                                       =$4EAF;
 mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                       =$4EB0;
 mmDP4_DP_DPHY_SYM0                                       =$4EB1;
 mmDP4_DP_DPHY_SYM1                                       =$4EB2;
 mmDP4_DP_DPHY_SYM2                                       =$4EB3;
 mmDP4_DP_DPHY_8B10B_CNTL                                 =$4EB4;
 mmDP4_DP_DPHY_PRBS_CNTL                                  =$4EB5;
 mmDP4_DP_DPHY_CRC_EN                                     =$4EB7;
 mmDP4_DP_DPHY_CRC_CNTL                                   =$4EB8;
 mmDP4_DP_DPHY_CRC_RESULT                                 =$4EB9;
 mmDP4_DP_DPHY_CRC_MST_CNTL                               =$4EBA;
 mmDP4_DP_DPHY_CRC_MST_STATUS                             =$4EBB;
 mmDP4_DP_DPHY_FAST_TRAINING                              =$4EBC;
 mmDP4_DP_DPHY_FAST_TRAINING_STATUS                       =$4EBD;
 mmDP4_DP_MSA_V_TIMING_OVERRIDE1                          =$4EBE;
 mmDP4_DP_MSA_V_TIMING_OVERRIDE2                          =$4EBF;
 mmDP4_DP_SEC_CNTL                                        =$4EC3;
 mmDP4_DP_SEC_CNTL1                                       =$4EC4;
 mmDP4_DP_SEC_FRAMING1                                    =$4EC5;
 mmDP4_DP_SEC_FRAMING2                                    =$4EC6;
 mmDP4_DP_SEC_FRAMING3                                    =$4EC7;
 mmDP4_DP_SEC_FRAMING4                                    =$4EC8;
 mmDP4_DP_SEC_AUD_N                                       =$4EC9;
 mmDP4_DP_SEC_AUD_N_READBACK                              =$4ECA;
 mmDP4_DP_SEC_AUD_M                                       =$4ECB;
 mmDP4_DP_SEC_AUD_M_READBACK                              =$4ECC;
 mmDP4_DP_SEC_TIMESTAMP                                   =$4ECD;
 mmDP4_DP_SEC_PACKET_CNTL                                 =$4ECE;
 mmDP4_DP_MSE_RATE_CNTL                                   =$4ECF;
 mmDP4_DP_MSE_RATE_UPDATE                                 =$4ED1;
 mmDP4_DP_MSE_SAT0                                        =$4ED2;
 mmDP4_DP_MSE_SAT1                                        =$4ED3;
 mmDP4_DP_MSE_SAT2                                        =$4ED4;
 mmDP4_DP_MSE_SAT_UPDATE                                  =$4ED5;
 mmDP4_DP_MSE_LINK_TIMING                                 =$4ED6;
 mmDP4_DP_MSE_MISC_CNTL                                   =$4ED7;
 mmDP4_DP_TEST_DEBUG_INDEX                                =$4ED8;
 mmDP4_DP_TEST_DEBUG_DATA                                 =$4ED9;
 mmDP4_DP_FE_TEST_DEBUG_INDEX                             =$4EDA;
 mmDP4_DP_FE_TEST_DEBUG_DATA                              =$4EDB;
 mmDIG5_DIG_FE_CNTL                                       =$4F00;
 mmDIG5_DIG_OUTPUT_CRC_CNTL                               =$4F01;
 mmDIG5_DIG_OUTPUT_CRC_RESULT                             =$4F02;
 mmDIG5_DIG_CLOCK_PATTERN                                 =$4F03;
 mmDIG5_DIG_TEST_PATTERN                                  =$4F04;
 mmDIG5_DIG_RANDOM_PATTERN_SEED                           =$4F05;
 mmDIG5_DIG_FIFO_STATUS                                   =$4F06;
 mmDIG5_DIG_DISPCLK_SWITCH_CNTL                           =$4F07;
 mmDIG5_DIG_DISPCLK_SWITCH_STATUS                         =$4F08;
 mmDIG5_HDMI_CONTROL                                      =$4F09;
 mmDIG5_HDMI_STATUS                                       =$4F0A;
 mmDIG5_HDMI_AUDIO_PACKET_CONTROL                         =$4F0B;
 mmDIG5_HDMI_ACR_PACKET_CONTROL                           =$4F0C;
 mmDIG5_HDMI_VBI_PACKET_CONTROL                           =$4F0D;
 mmDIG5_HDMI_INFOFRAME_CONTROL0                           =$4F0E;
 mmDIG5_HDMI_INFOFRAME_CONTROL1                           =$4F0F;
 mmDIG5_HDMI_GENERIC_PACKET_CONTROL0                      =$4F10;
 mmDIG5_HDMI_GC                                           =$4F13;
 mmDIG5_AFMT_AUDIO_PACKET_CONTROL2                        =$4F14;
 mmDIG5_AFMT_ISRC1_0                                      =$4F15;
 mmDIG5_AFMT_ISRC1_1                                      =$4F16;
 mmDIG5_AFMT_ISRC1_2                                      =$4F17;
 mmDIG5_AFMT_ISRC1_3                                      =$4F18;
 mmDIG5_AFMT_ISRC1_4                                      =$4F19;
 mmDIG5_AFMT_ISRC2_0                                      =$4F1A;
 mmDIG5_AFMT_ISRC2_1                                      =$4F1B;
 mmDIG5_AFMT_ISRC2_2                                      =$4F1C;
 mmDIG5_AFMT_ISRC2_3                                      =$4F1D;
 mmDIG5_AFMT_AVI_INFO0                                    =$4F1E;
 mmDIG5_AFMT_AVI_INFO1                                    =$4F1F;
 mmDIG5_AFMT_AVI_INFO2                                    =$4F20;
 mmDIG5_AFMT_AVI_INFO3                                    =$4F21;
 mmDIG5_AFMT_MPEG_INFO0                                   =$4F22;
 mmDIG5_AFMT_MPEG_INFO1                                   =$4F23;
 mmDIG5_AFMT_GENERIC_HDR                                  =$4F24;
 mmDIG5_AFMT_GENERIC_0                                    =$4F25;
 mmDIG5_AFMT_GENERIC_1                                    =$4F26;
 mmDIG5_AFMT_GENERIC_2                                    =$4F27;
 mmDIG5_AFMT_GENERIC_3                                    =$4F28;
 mmDIG5_AFMT_GENERIC_4                                    =$4F29;
 mmDIG5_AFMT_GENERIC_5                                    =$4F2A;
 mmDIG5_AFMT_GENERIC_6                                    =$4F2B;
 mmDIG5_AFMT_GENERIC_7                                    =$4F2C;
 mmDIG5_HDMI_GENERIC_PACKET_CONTROL1                      =$4F2D;
 mmDIG5_HDMI_ACR_32_0                                     =$4F2E;
 mmDIG5_HDMI_ACR_32_1                                     =$4F2F;
 mmDIG5_HDMI_ACR_44_0                                     =$4F30;
 mmDIG5_HDMI_ACR_44_1                                     =$4F31;
 mmDIG5_HDMI_ACR_48_0                                     =$4F32;
 mmDIG5_HDMI_ACR_48_1                                     =$4F33;
 mmDIG5_HDMI_ACR_STATUS_0                                 =$4F34;
 mmDIG5_HDMI_ACR_STATUS_1                                 =$4F35;
 mmDIG5_AFMT_AUDIO_INFO0                                  =$4F36;
 mmDIG5_AFMT_AUDIO_INFO1                                  =$4F37;
 mmDIG5_AFMT_60958_0                                      =$4F38;
 mmDIG5_AFMT_60958_1                                      =$4F39;
 mmDIG5_AFMT_AUDIO_CRC_CONTROL                            =$4F3A;
 mmDIG5_AFMT_RAMP_CONTROL0                                =$4F3B;
 mmDIG5_AFMT_RAMP_CONTROL1                                =$4F3C;
 mmDIG5_AFMT_RAMP_CONTROL2                                =$4F3D;
 mmDIG5_AFMT_RAMP_CONTROL3                                =$4F3E;
 mmDIG5_AFMT_60958_2                                      =$4F3F;
 mmDIG5_AFMT_AUDIO_CRC_RESULT                             =$4F40;
 mmDIG5_AFMT_STATUS                                       =$4F41;
 mmDIG5_AFMT_AUDIO_PACKET_CONTROL                         =$4F42;
 mmDIG5_AFMT_VBI_PACKET_CONTROL                           =$4F43;
 mmDIG5_AFMT_INFOFRAME_CONTROL0                           =$4F44;
 mmDIG5_AFMT_AUDIO_SRC_CONTROL                            =$4F45;
 mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL                           =$4F46;
 mmDIG5_DIG_BE_CNTL                                       =$4F47;
 mmDIG5_DIG_BE_EN_CNTL                                    =$4F48;
 mmDIG5_TMDS_CNTL                                         =$4F6B;
 mmDIG5_TMDS_CONTROL_CHAR                                 =$4F6C;
 mmDIG5_TMDS_CONTROL0_FEEDBACK                            =$4F6D;
 mmDIG5_TMDS_STEREOSYNC_CTL_SEL                           =$4F6E;
 mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1                        =$4F6F;
 mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3                        =$4F70;
 mmDIG5_TMDS_DEBUG                                        =$4F71;
 mmDIG5_TMDS_CTL_BITS                                     =$4F72;
 mmDIG5_TMDS_DCBALANCER_CONTROL                           =$4F73;
 mmDIG5_TMDS_CTL0_1_GEN_CNTL                              =$4F75;
 mmDIG5_TMDS_CTL2_3_GEN_CNTL                              =$4F76;
 mmDIG5_LVDS_DATA_CNTL                                    =$4F78;
 mmDIG5_DIG_LANE_ENABLE                                   =$4F79;
 mmDIG5_DIG_TEST_DEBUG_INDEX                              =$4F7A;
 mmDIG5_DIG_TEST_DEBUG_DATA                               =$4F7B;
 mmDIG5_DIG_FE_TEST_DEBUG_INDEX                           =$4F7C;
 mmDIG5_DIG_FE_TEST_DEBUG_DATA                            =$4F7D;
 mmDP5_DP_LINK_CNTL                                       =$4FA0;
 mmDP5_DP_PIXEL_FORMAT                                    =$4FA1;
 mmDP5_DP_MSA_COLORIMETRY                                 =$4FA2;
 mmDP5_DP_CONFIG                                          =$4FA3;
 mmDP5_DP_VID_STREAM_CNTL                                 =$4FA4;
 mmDP5_DP_STEER_FIFO                                      =$4FA5;
 mmDP5_DP_MSA_MISC                                        =$4FA6;
 mmDP5_DP_VID_TIMING                                      =$4FA8;
 mmDP5_DP_VID_N                                           =$4FA9;
 mmDP5_DP_VID_M                                           =$4FAA;
 mmDP5_DP_LINK_FRAMING_CNTL                               =$4FAB;
 mmDP5_DP_HBR2_EYE_PATTERN                                =$4FAC;
 mmDP5_DP_VID_MSA_VBID                                    =$4FAD;
 mmDP5_DP_VID_INTERRUPT_CNTL                              =$4FAE;
 mmDP5_DP_DPHY_CNTL                                       =$4FAF;
 mmDP5_DP_DPHY_TRAINING_PATTERN_SEL                       =$4FB0;
 mmDP5_DP_DPHY_SYM0                                       =$4FB1;
 mmDP5_DP_DPHY_SYM1                                       =$4FB2;
 mmDP5_DP_DPHY_SYM2                                       =$4FB3;
 mmDP5_DP_DPHY_8B10B_CNTL                                 =$4FB4;
 mmDP5_DP_DPHY_PRBS_CNTL                                  =$4FB5;
 mmDP5_DP_DPHY_CRC_EN                                     =$4FB7;
 mmDP5_DP_DPHY_CRC_CNTL                                   =$4FB8;
 mmDP5_DP_DPHY_CRC_RESULT                                 =$4FB9;
 mmDP5_DP_DPHY_CRC_MST_CNTL                               =$4FBA;
 mmDP5_DP_DPHY_CRC_MST_STATUS                             =$4FBB;
 mmDP5_DP_DPHY_FAST_TRAINING                              =$4FBC;
 mmDP5_DP_DPHY_FAST_TRAINING_STATUS                       =$4FBD;
 mmDP5_DP_MSA_V_TIMING_OVERRIDE1                          =$4FBE;
 mmDP5_DP_MSA_V_TIMING_OVERRIDE2                          =$4FBF;
 mmDP5_DP_SEC_CNTL                                        =$4FC3;
 mmDP5_DP_SEC_CNTL1                                       =$4FC4;
 mmDP5_DP_SEC_FRAMING1                                    =$4FC5;
 mmDP5_DP_SEC_FRAMING2                                    =$4FC6;
 mmDP5_DP_SEC_FRAMING3                                    =$4FC7;
 mmDP5_DP_SEC_FRAMING4                                    =$4FC8;
 mmDP5_DP_SEC_AUD_N                                       =$4FC9;
 mmDP5_DP_SEC_AUD_N_READBACK                              =$4FCA;
 mmDP5_DP_SEC_AUD_M                                       =$4FCB;
 mmDP5_DP_SEC_AUD_M_READBACK                              =$4FCC;
 mmDP5_DP_SEC_TIMESTAMP                                   =$4FCD;
 mmDP5_DP_SEC_PACKET_CNTL                                 =$4FCE;
 mmDP5_DP_MSE_RATE_CNTL                                   =$4FCF;
 mmDP5_DP_MSE_RATE_UPDATE                                 =$4FD1;
 mmDP5_DP_MSE_SAT0                                        =$4FD2;
 mmDP5_DP_MSE_SAT1                                        =$4FD3;
 mmDP5_DP_MSE_SAT2                                        =$4FD4;
 mmDP5_DP_MSE_SAT_UPDATE                                  =$4FD5;
 mmDP5_DP_MSE_LINK_TIMING                                 =$4FD6;
 mmDP5_DP_MSE_MISC_CNTL                                   =$4FD7;
 mmDP5_DP_TEST_DEBUG_INDEX                                =$4FD8;
 mmDP5_DP_TEST_DEBUG_DATA                                 =$4FD9;
 mmDP5_DP_FE_TEST_DEBUG_INDEX                             =$4FDA;
 mmDP5_DP_FE_TEST_DEBUG_DATA                              =$4FDB;
 mmDIG6_DIG_FE_CNTL                                       =$5400;
 mmDIG6_DIG_OUTPUT_CRC_CNTL                               =$5401;
 mmDIG6_DIG_OUTPUT_CRC_RESULT                             =$5402;
 mmDIG6_DIG_CLOCK_PATTERN                                 =$5403;
 mmDIG6_DIG_TEST_PATTERN                                  =$5404;
 mmDIG6_DIG_RANDOM_PATTERN_SEED                           =$5405;
 mmDIG6_DIG_FIFO_STATUS                                   =$5406;
 mmDIG6_DIG_DISPCLK_SWITCH_CNTL                           =$5407;
 mmDIG6_DIG_DISPCLK_SWITCH_STATUS                         =$5408;
 mmDIG6_HDMI_CONTROL                                      =$5409;
 mmDIG6_HDMI_STATUS                                       =$540A;
 mmDIG6_HDMI_AUDIO_PACKET_CONTROL                         =$540B;
 mmDIG6_HDMI_ACR_PACKET_CONTROL                           =$540C;
 mmDIG6_HDMI_VBI_PACKET_CONTROL                           =$540D;
 mmDIG6_HDMI_INFOFRAME_CONTROL0                           =$540E;
 mmDIG6_HDMI_INFOFRAME_CONTROL1                           =$540F;
 mmDIG6_HDMI_GENERIC_PACKET_CONTROL0                      =$5410;
 mmDIG6_HDMI_GC                                           =$5413;
 mmDIG6_AFMT_AUDIO_PACKET_CONTROL2                        =$5414;
 mmDIG6_AFMT_ISRC1_0                                      =$5415;
 mmDIG6_AFMT_ISRC1_1                                      =$5416;
 mmDIG6_AFMT_ISRC1_2                                      =$5417;
 mmDIG6_AFMT_ISRC1_3                                      =$5418;
 mmDIG6_AFMT_ISRC1_4                                      =$5419;
 mmDIG6_AFMT_ISRC2_0                                      =$541A;
 mmDIG6_AFMT_ISRC2_1                                      =$541B;
 mmDIG6_AFMT_ISRC2_2                                      =$541C;
 mmDIG6_AFMT_ISRC2_3                                      =$541D;
 mmDIG6_AFMT_AVI_INFO0                                    =$541E;
 mmDIG6_AFMT_AVI_INFO1                                    =$541F;
 mmDIG6_AFMT_AVI_INFO2                                    =$5420;
 mmDIG6_AFMT_AVI_INFO3                                    =$5421;
 mmDIG6_AFMT_MPEG_INFO0                                   =$5422;
 mmDIG6_AFMT_MPEG_INFO1                                   =$5423;
 mmDIG6_AFMT_GENERIC_HDR                                  =$5424;
 mmDIG6_AFMT_GENERIC_0                                    =$5425;
 mmDIG6_AFMT_GENERIC_1                                    =$5426;
 mmDIG6_AFMT_GENERIC_2                                    =$5427;
 mmDIG6_AFMT_GENERIC_3                                    =$5428;
 mmDIG6_AFMT_GENERIC_4                                    =$5429;
 mmDIG6_AFMT_GENERIC_5                                    =$542A;
 mmDIG6_AFMT_GENERIC_6                                    =$542B;
 mmDIG6_AFMT_GENERIC_7                                    =$542C;
 mmDIG6_HDMI_GENERIC_PACKET_CONTROL1                      =$542D;
 mmDIG6_HDMI_ACR_32_0                                     =$542E;
 mmDIG6_HDMI_ACR_32_1                                     =$542F;
 mmDIG6_HDMI_ACR_44_0                                     =$5430;
 mmDIG6_HDMI_ACR_44_1                                     =$5431;
 mmDIG6_HDMI_ACR_48_0                                     =$5432;
 mmDIG6_HDMI_ACR_48_1                                     =$5433;
 mmDIG6_HDMI_ACR_STATUS_0                                 =$5434;
 mmDIG6_HDMI_ACR_STATUS_1                                 =$5435;
 mmDIG6_AFMT_AUDIO_INFO0                                  =$5436;
 mmDIG6_AFMT_AUDIO_INFO1                                  =$5437;
 mmDIG6_AFMT_60958_0                                      =$5438;
 mmDIG6_AFMT_60958_1                                      =$5439;
 mmDIG6_AFMT_AUDIO_CRC_CONTROL                            =$543A;
 mmDIG6_AFMT_RAMP_CONTROL0                                =$543B;
 mmDIG6_AFMT_RAMP_CONTROL1                                =$543C;
 mmDIG6_AFMT_RAMP_CONTROL2                                =$543D;
 mmDIG6_AFMT_RAMP_CONTROL3                                =$543E;
 mmDIG6_AFMT_60958_2                                      =$543F;
 mmDIG6_AFMT_AUDIO_CRC_RESULT                             =$5440;
 mmDIG6_AFMT_STATUS                                       =$5441;
 mmDIG6_AFMT_AUDIO_PACKET_CONTROL                         =$5442;
 mmDIG6_AFMT_VBI_PACKET_CONTROL                           =$5443;
 mmDIG6_AFMT_INFOFRAME_CONTROL0                           =$5444;
 mmDIG6_AFMT_AUDIO_SRC_CONTROL                            =$5445;
 mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL                           =$5446;
 mmDIG6_DIG_BE_CNTL                                       =$5447;
 mmDIG6_DIG_BE_EN_CNTL                                    =$5448;
 mmDIG6_TMDS_CNTL                                         =$546B;
 mmDIG6_TMDS_CONTROL_CHAR                                 =$546C;
 mmDIG6_TMDS_CONTROL0_FEEDBACK                            =$546D;
 mmDIG6_TMDS_STEREOSYNC_CTL_SEL                           =$546E;
 mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1                        =$546F;
 mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3                        =$5470;
 mmDIG6_TMDS_DEBUG                                        =$5471;
 mmDIG6_TMDS_CTL_BITS                                     =$5472;
 mmDIG6_TMDS_DCBALANCER_CONTROL                           =$5473;
 mmDIG6_TMDS_CTL0_1_GEN_CNTL                              =$5475;
 mmDIG6_TMDS_CTL2_3_GEN_CNTL                              =$5476;
 mmDIG6_LVDS_DATA_CNTL                                    =$5478;
 mmDIG6_DIG_LANE_ENABLE                                   =$5479;
 mmDIG6_DIG_TEST_DEBUG_INDEX                              =$547A;
 mmDIG6_DIG_TEST_DEBUG_DATA                               =$547B;
 mmDIG6_DIG_FE_TEST_DEBUG_INDEX                           =$547C;
 mmDIG6_DIG_FE_TEST_DEBUG_DATA                            =$547D;
 mmDP6_DP_LINK_CNTL                                       =$54A0;
 mmDP6_DP_PIXEL_FORMAT                                    =$54A1;
 mmDP6_DP_MSA_COLORIMETRY                                 =$54A2;
 mmDP6_DP_CONFIG                                          =$54A3;
 mmDP6_DP_VID_STREAM_CNTL                                 =$54A4;
 mmDP6_DP_STEER_FIFO                                      =$54A5;
 mmDP6_DP_MSA_MISC                                        =$54A6;
 mmDP6_DP_VID_TIMING                                      =$54A8;
 mmDP6_DP_VID_N                                           =$54A9;
 mmDP6_DP_VID_M                                           =$54AA;
 mmDP6_DP_LINK_FRAMING_CNTL                               =$54AB;
 mmDP6_DP_HBR2_EYE_PATTERN                                =$54AC;
 mmDP6_DP_VID_MSA_VBID                                    =$54AD;
 mmDP6_DP_VID_INTERRUPT_CNTL                              =$54AE;
 mmDP6_DP_DPHY_CNTL                                       =$54AF;
 mmDP6_DP_DPHY_TRAINING_PATTERN_SEL                       =$54B0;
 mmDP6_DP_DPHY_SYM0                                       =$54B1;
 mmDP6_DP_DPHY_SYM1                                       =$54B2;
 mmDP6_DP_DPHY_SYM2                                       =$54B3;
 mmDP6_DP_DPHY_8B10B_CNTL                                 =$54B4;
 mmDP6_DP_DPHY_PRBS_CNTL                                  =$54B5;
 mmDP6_DP_DPHY_CRC_EN                                     =$54B7;
 mmDP6_DP_DPHY_CRC_CNTL                                   =$54B8;
 mmDP6_DP_DPHY_CRC_RESULT                                 =$54B9;
 mmDP6_DP_DPHY_CRC_MST_CNTL                               =$54BA;
 mmDP6_DP_DPHY_CRC_MST_STATUS                             =$54BB;
 mmDP6_DP_DPHY_FAST_TRAINING                              =$54BC;
 mmDP6_DP_DPHY_FAST_TRAINING_STATUS                       =$54BD;
 mmDP6_DP_MSA_V_TIMING_OVERRIDE1                          =$54BE;
 mmDP6_DP_MSA_V_TIMING_OVERRIDE2                          =$54BF;
 mmDP6_DP_SEC_CNTL                                        =$54C3;
 mmDP6_DP_SEC_CNTL1                                       =$54C4;
 mmDP6_DP_SEC_FRAMING1                                    =$54C5;
 mmDP6_DP_SEC_FRAMING2                                    =$54C6;
 mmDP6_DP_SEC_FRAMING3                                    =$54C7;
 mmDP6_DP_SEC_FRAMING4                                    =$54C8;
 mmDP6_DP_SEC_AUD_N                                       =$54C9;
 mmDP6_DP_SEC_AUD_N_READBACK                              =$54CA;
 mmDP6_DP_SEC_AUD_M                                       =$54CB;
 mmDP6_DP_SEC_AUD_M_READBACK                              =$54CC;
 mmDP6_DP_SEC_TIMESTAMP                                   =$54CD;
 mmDP6_DP_SEC_PACKET_CNTL                                 =$54CE;
 mmDP6_DP_MSE_RATE_CNTL                                   =$54CF;
 mmDP6_DP_MSE_RATE_UPDATE                                 =$54D1;
 mmDP6_DP_MSE_SAT0                                        =$54D2;
 mmDP6_DP_MSE_SAT1                                        =$54D3;
 mmDP6_DP_MSE_SAT2                                        =$54D4;
 mmDP6_DP_MSE_SAT_UPDATE                                  =$54D5;
 mmDP6_DP_MSE_LINK_TIMING                                 =$54D6;
 mmDP6_DP_MSE_MISC_CNTL                                   =$54D7;
 mmDP6_DP_TEST_DEBUG_INDEX                                =$54D8;
 mmDP6_DP_TEST_DEBUG_DATA                                 =$54D9;
 mmDP6_DP_FE_TEST_DEBUG_INDEX                             =$54DA;
 mmDP6_DP_FE_TEST_DEBUG_DATA                              =$54DB;
 mmDC_PERFMON10_PERFCOUNTER_CNTL                          =$59A0;
 mmDC_PERFMON10_PERFCOUNTER_STATE                         =$59A1;
 mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                   =$59A2;
 mmDC_PERFMON10_PERFMON_CNTL                              =$59A3;
 mmDC_PERFMON10_PERFMON_CVALUE_LOW                        =$59A4;
 mmDC_PERFMON10_PERFMON_HI                                =$59A5;
 mmDC_PERFMON10_PERFMON_LOW                               =$59A6;
 mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX                  =$59A7;
 mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA                   =$59A8;
 mmDC_PERFMON10_PERFMON_CNTL2                             =$59AA;
 mmAZF0STREAM8_AZALIA_STREAM_INDEX                        =$59C0;
 mmAZF0STREAM8_AZALIA_STREAM_DATA                         =$59C1;
 mmAZF0STREAM9_AZALIA_STREAM_INDEX                        =$59C2;
 mmAZF0STREAM9_AZALIA_STREAM_DATA                         =$59C3;
 mmAZF0STREAM10_AZALIA_STREAM_INDEX                       =$59C4;
 mmAZF0STREAM10_AZALIA_STREAM_DATA                        =$59C5;
 mmAZF0STREAM11_AZALIA_STREAM_INDEX                       =$59C6;
 mmAZF0STREAM11_AZALIA_STREAM_DATA                        =$59C7;
 mmAZF0STREAM12_AZALIA_STREAM_INDEX                       =$59C8;
 mmAZF0STREAM12_AZALIA_STREAM_DATA                        =$59C9;
 mmAZF0STREAM13_AZALIA_STREAM_INDEX                       =$59CA;
 mmAZF0STREAM13_AZALIA_STREAM_DATA                        =$59CB;
 mmAZF0STREAM14_AZALIA_STREAM_INDEX                       =$59CC;
 mmAZF0STREAM14_AZALIA_STREAM_DATA                        =$59CD;
 mmAZF0STREAM15_AZALIA_STREAM_INDEX                       =$59CE;
 mmAZF0STREAM15_AZALIA_STREAM_DATA                        =$59CF;
 mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                   =$59D4;
 mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                    =$59D5;
 mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59D8;
 mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59D9;
 mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59DC;
 mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59DD;
 mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59E0;
 mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59E1;
 mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59E4;
 mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59E5;
 mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59E8;
 mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59E9;
 mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59EC;
 mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59ED;
 mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59F0;
 mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59F1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED0                          =$5A84;
 mmDCRX_PHY_MACRO_CNTL_RESERVED1                          =$5A85;
 mmDCRX_PHY_MACRO_CNTL_RESERVED2                          =$5A86;
 mmDCRX_PHY_MACRO_CNTL_RESERVED3                          =$5A87;
 mmDCRX_PHY_MACRO_CNTL_RESERVED4                          =$5A88;
 mmDCRX_PHY_MACRO_CNTL_RESERVED5                          =$5A89;
 mmDCRX_PHY_MACRO_CNTL_RESERVED6                          =$5A8A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED7                          =$5A8B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED8                          =$5A8C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED9                          =$5A8D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED10                         =$5A8E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED11                         =$5A8F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED12                         =$5A90;
 mmDCRX_PHY_MACRO_CNTL_RESERVED13                         =$5A91;
 mmDCRX_PHY_MACRO_CNTL_RESERVED14                         =$5A92;
 mmDCRX_PHY_MACRO_CNTL_RESERVED15                         =$5A93;
 mmDCRX_PHY_MACRO_CNTL_RESERVED16                         =$5A94;
 mmDCRX_PHY_MACRO_CNTL_RESERVED17                         =$5A95;
 mmDCRX_PHY_MACRO_CNTL_RESERVED18                         =$5A96;
 mmDCRX_PHY_MACRO_CNTL_RESERVED19                         =$5A97;
 mmDCRX_PHY_MACRO_CNTL_RESERVED20                         =$5A98;
 mmDCRX_PHY_MACRO_CNTL_RESERVED21                         =$5A99;
 mmDCRX_PHY_MACRO_CNTL_RESERVED22                         =$5A9A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED23                         =$5A9B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED24                         =$5A9C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED25                         =$5A9D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED26                         =$5A9E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED27                         =$5A9F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED28                         =$5AA0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED29                         =$5AA1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED30                         =$5AA2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED31                         =$5AA3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED32                         =$5AA4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED33                         =$5AA5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED34                         =$5AA6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED35                         =$5AA7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED36                         =$5AA8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED37                         =$5AA9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED38                         =$5AAA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED39                         =$5AAB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED40                         =$5AAC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED41                         =$5AAD;
 mmDCRX_PHY_MACRO_CNTL_RESERVED42                         =$5AAE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED43                         =$5AAF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED44                         =$5AB0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED45                         =$5AB1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED46                         =$5AB2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED47                         =$5AB3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED48                         =$5AB4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED49                         =$5AB5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED50                         =$5AB6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED51                         =$5AB7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED52                         =$5AB8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED53                         =$5AB9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED54                         =$5ABA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED55                         =$5ABB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED56                         =$5ABC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED57                         =$5ABD;
 mmDCRX_PHY_MACRO_CNTL_RESERVED58                         =$5ABE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED59                         =$5ABF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED60                         =$5AC0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED61                         =$5AC1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED62                         =$5AC2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED63                         =$5AC3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED64                         =$5AC4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED65                         =$5AC5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED66                         =$5AC6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED67                         =$5AC7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED68                         =$5AC8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED69                         =$5AC9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED70                         =$5ACA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED71                         =$5ACB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED72                         =$5ACC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED73                         =$5ACD;
 mmDCRX_PHY_MACRO_CNTL_RESERVED74                         =$5ACE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED75                         =$5ACF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED76                         =$5AD0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED77                         =$5AD1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED78                         =$5AD2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED79                         =$5AD3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED80                         =$5AD4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED81                         =$5AD5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED82                         =$5AD6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED83                         =$5AD7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED84                         =$5AD8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED85                         =$5AD9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED86                         =$5ADA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED87                         =$5ADB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED88                         =$5ADC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED89                         =$5ADD;
 mmDCRX_PHY_MACRO_CNTL_RESERVED90                         =$5ADE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED91                         =$5ADF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED92                         =$5AE0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED93                         =$5AE1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED94                         =$5AE2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED95                         =$5AE3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED96                         =$5AE4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED97                         =$5AE5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED98                         =$5AE6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED99                         =$5AE7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED100                        =$5AE8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED101                        =$5AE9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED102                        =$5AEA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED103                        =$5AEB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED104                        =$5AEC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED105                        =$5AED;
 mmDCRX_PHY_MACRO_CNTL_RESERVED106                        =$5AEE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED107                        =$5AEF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED108                        =$5AF0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED109                        =$5AF1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED110                        =$5AF2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED111                        =$5AF3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED112                        =$5AF4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED113                        =$5AF5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED114                        =$5AF6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED115                        =$5AF7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED116                        =$5AF8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED117                        =$5AF9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED118                        =$5AFA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED119                        =$5AFB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED120                        =$5AFC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED121                        =$5AFD;
 mmDCRX_PHY_MACRO_CNTL_RESERVED122                        =$5AFE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED123                        =$5AFF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED124                        =$5B00;
 mmDCRX_PHY_MACRO_CNTL_RESERVED125                        =$5B01;
 mmDCRX_PHY_MACRO_CNTL_RESERVED126                        =$5B02;
 mmDCRX_PHY_MACRO_CNTL_RESERVED127                        =$5B03;
 mmDCRX_PHY_MACRO_CNTL_RESERVED128                        =$5B04;
 mmDCRX_PHY_MACRO_CNTL_RESERVED129                        =$5B05;
 mmDCRX_PHY_MACRO_CNTL_RESERVED130                        =$5B06;
 mmDCRX_PHY_MACRO_CNTL_RESERVED131                        =$5B07;
 mmDCRX_PHY_MACRO_CNTL_RESERVED132                        =$5B08;
 mmDCRX_PHY_MACRO_CNTL_RESERVED133                        =$5B09;
 mmDCRX_PHY_MACRO_CNTL_RESERVED134                        =$5B0A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED135                        =$5B0B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED136                        =$5B0C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED137                        =$5B0D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED138                        =$5B0E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED139                        =$5B0F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED140                        =$5B10;
 mmDCRX_PHY_MACRO_CNTL_RESERVED141                        =$5B11;
 mmDCRX_PHY_MACRO_CNTL_RESERVED142                        =$5B12;
 mmDCRX_PHY_MACRO_CNTL_RESERVED143                        =$5B13;
 mmDCRX_PHY_MACRO_CNTL_RESERVED144                        =$5B14;
 mmDCRX_PHY_MACRO_CNTL_RESERVED145                        =$5B15;
 mmDCRX_PHY_MACRO_CNTL_RESERVED146                        =$5B16;
 mmDCRX_PHY_MACRO_CNTL_RESERVED147                        =$5B17;
 mmDCRX_PHY_MACRO_CNTL_RESERVED148                        =$5B18;
 mmDCRX_PHY_MACRO_CNTL_RESERVED149                        =$5B19;
 mmDCRX_PHY_MACRO_CNTL_RESERVED150                        =$5B1A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED151                        =$5B1B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED152                        =$5B1C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED153                        =$5B1D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED154                        =$5B1E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED155                        =$5B1F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED156                        =$5B20;
 mmDCRX_PHY_MACRO_CNTL_RESERVED157                        =$5B21;
 mmDCRX_PHY_MACRO_CNTL_RESERVED158                        =$5B22;
 mmDCRX_PHY_MACRO_CNTL_RESERVED159                        =$5B23;
 mmDCRX_PHY_MACRO_CNTL_RESERVED160                        =$5B24;
 mmDCRX_PHY_MACRO_CNTL_RESERVED161                        =$5B25;
 mmDCRX_PHY_MACRO_CNTL_RESERVED162                        =$5B26;
 mmDCRX_PHY_MACRO_CNTL_RESERVED163                        =$5B27;
 mmDCRX_PHY_MACRO_CNTL_RESERVED164                        =$5B28;
 mmDCRX_PHY_MACRO_CNTL_RESERVED165                        =$5B29;
 mmDCRX_PHY_MACRO_CNTL_RESERVED166                        =$5B2A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED167                        =$5B2B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED168                        =$5B2C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED169                        =$5B2D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED170                        =$5B2E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED171                        =$5B2F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED172                        =$5B30;
 mmDCRX_PHY_MACRO_CNTL_RESERVED173                        =$5B31;
 mmDCRX_PHY_MACRO_CNTL_RESERVED174                        =$5B32;
 mmDCRX_PHY_MACRO_CNTL_RESERVED175                        =$5B33;
 mmDCRX_PHY_MACRO_CNTL_RESERVED176                        =$5B34;
 mmDCRX_PHY_MACRO_CNTL_RESERVED177                        =$5B35;
 mmDCRX_PHY_MACRO_CNTL_RESERVED178                        =$5B36;
 mmDCRX_PHY_MACRO_CNTL_RESERVED179                        =$5B37;
 mmDCRX_PHY_MACRO_CNTL_RESERVED180                        =$5B38;
 mmDCRX_PHY_MACRO_CNTL_RESERVED181                        =$5B39;
 mmDCRX_PHY_MACRO_CNTL_RESERVED182                        =$5B3A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED183                        =$5B3B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED184                        =$5B3C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED185                        =$5B3D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED186                        =$5B3E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED187                        =$5B3F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED188                        =$5B40;
 mmDCRX_PHY_MACRO_CNTL_RESERVED189                        =$5B41;
 mmDCRX_PHY_MACRO_CNTL_RESERVED190                        =$5B42;
 mmDCRX_PHY_MACRO_CNTL_RESERVED191                        =$5B43;
 mmDCRX_PHY_MACRO_CNTL_RESERVED192                        =$5B44;
 mmDCRX_PHY_MACRO_CNTL_RESERVED193                        =$5B45;
 mmDCRX_PHY_MACRO_CNTL_RESERVED194                        =$5B46;
 mmDCRX_PHY_MACRO_CNTL_RESERVED195                        =$5B47;
 mmDCRX_PHY_MACRO_CNTL_RESERVED196                        =$5B48;
 mmDCRX_PHY_MACRO_CNTL_RESERVED197                        =$5B49;
 mmDCRX_PHY_MACRO_CNTL_RESERVED198                        =$5B4A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED199                        =$5B4B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED200                        =$5B4C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED201                        =$5B4D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED202                        =$5B4E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED203                        =$5B4F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED204                        =$5B50;
 mmDCRX_PHY_MACRO_CNTL_RESERVED205                        =$5B51;
 mmDCRX_PHY_MACRO_CNTL_RESERVED206                        =$5B52;
 mmDCRX_PHY_MACRO_CNTL_RESERVED207                        =$5B53;
 mmDCRX_PHY_MACRO_CNTL_RESERVED208                        =$5B54;
 mmDCRX_PHY_MACRO_CNTL_RESERVED209                        =$5B55;
 mmDCRX_PHY_MACRO_CNTL_RESERVED210                        =$5B56;
 mmDCRX_PHY_MACRO_CNTL_RESERVED211                        =$5B57;
 mmDCRX_PHY_MACRO_CNTL_RESERVED212                        =$5B58;
 mmDCRX_PHY_MACRO_CNTL_RESERVED213                        =$5B59;
 mmDCRX_PHY_MACRO_CNTL_RESERVED214                        =$5B5A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED215                        =$5B5B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED216                        =$5B5C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED217                        =$5B5D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED218                        =$5B5E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED219                        =$5B5F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED220                        =$5B60;
 mmDCRX_PHY_MACRO_CNTL_RESERVED221                        =$5B61;
 mmDCRX_PHY_MACRO_CNTL_RESERVED222                        =$5B62;
 mmDCRX_PHY_MACRO_CNTL_RESERVED223                        =$5B63;
 mmDCRX_PHY_MACRO_CNTL_RESERVED224                        =$5B64;
 mmDCRX_PHY_MACRO_CNTL_RESERVED225                        =$5B65;
 mmDCRX_PHY_MACRO_CNTL_RESERVED226                        =$5B66;
 mmDCRX_PHY_MACRO_CNTL_RESERVED227                        =$5B67;
 mmDCRX_PHY_MACRO_CNTL_RESERVED228                        =$5B68;
 mmDCRX_PHY_MACRO_CNTL_RESERVED229                        =$5B69;
 mmDCRX_PHY_MACRO_CNTL_RESERVED230                        =$5B6A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED231                        =$5B6B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED232                        =$5B6C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED233                        =$5B6D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED234                        =$5B6E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED235                        =$5B6F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED236                        =$5B70;
 mmDCRX_PHY_MACRO_CNTL_RESERVED237                        =$5B71;
 mmDCRX_PHY_MACRO_CNTL_RESERVED238                        =$5B72;
 mmDCRX_PHY_MACRO_CNTL_RESERVED239                        =$5B73;
 mmDCRX_PHY_MACRO_CNTL_RESERVED240                        =$5B74;
 mmDCRX_PHY_MACRO_CNTL_RESERVED241                        =$5B75;
 mmDCRX_PHY_MACRO_CNTL_RESERVED242                        =$5B76;
 mmDCRX_PHY_MACRO_CNTL_RESERVED243                        =$5B77;
 mmDCRX_PHY_MACRO_CNTL_RESERVED244                        =$5B78;
 mmDCRX_PHY_MACRO_CNTL_RESERVED245                        =$5B79;
 mmDCRX_PHY_MACRO_CNTL_RESERVED246                        =$5B7A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED247                        =$5B7B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED248                        =$5B7C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED249                        =$5B7D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED250                        =$5B7E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED251                        =$5B7F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED252                        =$5B80;
 mmDCRX_PHY_MACRO_CNTL_RESERVED253                        =$5B81;
 mmDCRX_PHY_MACRO_CNTL_RESERVED254                        =$5B82;
 mmDCRX_PHY_MACRO_CNTL_RESERVED255                        =$5B83;
 mmDCRX_PHY_MACRO_CNTL_RESERVED256                        =$5B84;
 mmDCRX_PHY_MACRO_CNTL_RESERVED257                        =$5B85;
 mmDCRX_PHY_MACRO_CNTL_RESERVED258                        =$5B86;
 mmDCRX_PHY_MACRO_CNTL_RESERVED259                        =$5B87;
 mmDCRX_PHY_MACRO_CNTL_RESERVED260                        =$5B88;
 mmDCRX_PHY_MACRO_CNTL_RESERVED261                        =$5B89;
 mmDCRX_PHY_MACRO_CNTL_RESERVED262                        =$5B8A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED263                        =$5B8B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED264                        =$5B8C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED265                        =$5B8D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED266                        =$5B8E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED267                        =$5B8F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED268                        =$5B90;
 mmDCRX_PHY_MACRO_CNTL_RESERVED269                        =$5B91;
 mmDCRX_PHY_MACRO_CNTL_RESERVED270                        =$5B92;
 mmDCRX_PHY_MACRO_CNTL_RESERVED271                        =$5B93;
 mmDCRX_PHY_MACRO_CNTL_RESERVED272                        =$5B94;
 mmDCRX_PHY_MACRO_CNTL_RESERVED273                        =$5B95;
 mmDCRX_PHY_MACRO_CNTL_RESERVED274                        =$5B96;
 mmDCRX_PHY_MACRO_CNTL_RESERVED275                        =$5B97;
 mmDCRX_PHY_MACRO_CNTL_RESERVED276                        =$5B98;
 mmDCRX_PHY_MACRO_CNTL_RESERVED277                        =$5B99;
 mmDCRX_PHY_MACRO_CNTL_RESERVED278                        =$5B9A;
 mmDCRX_PHY_MACRO_CNTL_RESERVED279                        =$5B9B;
 mmDCRX_PHY_MACRO_CNTL_RESERVED280                        =$5B9C;
 mmDCRX_PHY_MACRO_CNTL_RESERVED281                        =$5B9D;
 mmDCRX_PHY_MACRO_CNTL_RESERVED282                        =$5B9E;
 mmDCRX_PHY_MACRO_CNTL_RESERVED283                        =$5B9F;
 mmDCRX_PHY_MACRO_CNTL_RESERVED284                        =$5BA0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED285                        =$5BA1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED286                        =$5BA2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED287                        =$5BA3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED288                        =$5BA4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED289                        =$5BA5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED290                        =$5BA6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED291                        =$5BA7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED292                        =$5BA8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED293                        =$5BA9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED294                        =$5BAA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED295                        =$5BAB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED296                        =$5BAC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED297                        =$5BAD;
 mmDCRX_PHY_MACRO_CNTL_RESERVED298                        =$5BAE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED299                        =$5BAF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED300                        =$5BB0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED301                        =$5BB1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED302                        =$5BB2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED303                        =$5BB3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED304                        =$5BB4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED305                        =$5BB5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED306                        =$5BB6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED307                        =$5BB7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED308                        =$5BB8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED309                        =$5BB9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED310                        =$5BBA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED311                        =$5BBB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED312                        =$5BBC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED313                        =$5BBD;
 mmDCRX_PHY_MACRO_CNTL_RESERVED314                        =$5BBE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED315                        =$5BBF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED316                        =$5BC0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED317                        =$5BC1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED318                        =$5BC2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED319                        =$5BC3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED320                        =$5BC4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED321                        =$5BC5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED322                        =$5BC6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED323                        =$5BC7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED324                        =$5BC8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED325                        =$5BC9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED326                        =$5BCA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED327                        =$5BCB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED328                        =$5BCC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED329                        =$5BCD;
 mmDCRX_PHY_MACRO_CNTL_RESERVED330                        =$5BCE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED331                        =$5BCF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED332                        =$5BD0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED333                        =$5BD1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED334                        =$5BD2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED335                        =$5BD3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED336                        =$5BD4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED337                        =$5BD5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED338                        =$5BD6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED339                        =$5BD7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED340                        =$5BD8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED341                        =$5BD9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED342                        =$5BDA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED343                        =$5BDB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED344                        =$5BDC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED345                        =$5BDD;
 mmDCRX_PHY_MACRO_CNTL_RESERVED346                        =$5BDE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED347                        =$5BDF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED348                        =$5BE0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED349                        =$5BE1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED350                        =$5BE2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED351                        =$5BE3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED352                        =$5BE4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED353                        =$5BE5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED354                        =$5BE6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED355                        =$5BE7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED356                        =$5BE8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED357                        =$5BE9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED358                        =$5BEA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED359                        =$5BEB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED360                        =$5BEC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED361                        =$5BED;
 mmDCRX_PHY_MACRO_CNTL_RESERVED362                        =$5BEE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED363                        =$5BEF;
 mmDCRX_PHY_MACRO_CNTL_RESERVED364                        =$5BF0;
 mmDCRX_PHY_MACRO_CNTL_RESERVED365                        =$5BF1;
 mmDCRX_PHY_MACRO_CNTL_RESERVED366                        =$5BF2;
 mmDCRX_PHY_MACRO_CNTL_RESERVED367                        =$5BF3;
 mmDCRX_PHY_MACRO_CNTL_RESERVED368                        =$5BF4;
 mmDCRX_PHY_MACRO_CNTL_RESERVED369                        =$5BF5;
 mmDCRX_PHY_MACRO_CNTL_RESERVED370                        =$5BF6;
 mmDCRX_PHY_MACRO_CNTL_RESERVED371                        =$5BF7;
 mmDCRX_PHY_MACRO_CNTL_RESERVED372                        =$5BF8;
 mmDCRX_PHY_MACRO_CNTL_RESERVED373                        =$5BF9;
 mmDCRX_PHY_MACRO_CNTL_RESERVED374                        =$5BFA;
 mmDCRX_PHY_MACRO_CNTL_RESERVED375                        =$5BFB;
 mmDCRX_PHY_MACRO_CNTL_RESERVED376                        =$5BFC;
 mmDCRX_PHY_MACRO_CNTL_RESERVED377                        =$5BFD;
 mmDCRX_PHY_MACRO_CNTL_RESERVED378                        =$5BFE;
 mmDCRX_PHY_MACRO_CNTL_RESERVED379                        =$5BFF;
 mmAUX_CONTROL                                            =$5C00;
 mmAUX_SW_CONTROL                                         =$5C01;
 mmAUX_ARB_CONTROL                                        =$5C02;
 mmAUX_INTERRUPT_CONTROL                                  =$5C03;
 mmAUX_SW_STATUS                                          =$5C04;
 mmAUX_LS_STATUS                                          =$5C05;
 mmAUX_SW_DATA                                            =$5C06;
 mmAUX_LS_DATA                                            =$5C07;
 mmAUX_DPHY_TX_REF_CONTROL                                =$5C08;
 mmAUX_DPHY_TX_CONTROL                                    =$5C09;
 mmAUX_DPHY_RX_CONTROL0                                   =$5C0A;
 mmAUX_DPHY_RX_CONTROL1                                   =$5C0B;
 mmAUX_DPHY_TX_STATUS                                     =$5C0C;
 mmAUX_DPHY_RX_STATUS                                     =$5C0D;
 mmAUX_GTC_SYNC_CONTROL                                   =$5C0E;
 mmAUX_GTC_SYNC_ERROR_CONTROL                             =$5C0F;
 mmAUX_GTC_SYNC_CONTROLLER_STATUS                         =$5C10;
 mmAUX_GTC_SYNC_STATUS                                    =$5C11;
 mmAUX_GTC_SYNC_DATA                                      =$5C12;
 mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                     =$5C13;
 mmAUX_TEST_DEBUG_INDEX                                   =$5C14;
 mmAUX_TEST_DEBUG_DATA                                    =$5C15;
 mmDP_AUX1_AUX_CONTROL                                    =$5C1C;
 mmDP_AUX1_AUX_SW_CONTROL                                 =$5C1D;
 mmDP_AUX1_AUX_ARB_CONTROL                                =$5C1E;
 mmDP_AUX1_AUX_INTERRUPT_CONTROL                          =$5C1F;
 mmDP_AUX1_AUX_SW_STATUS                                  =$5C20;
 mmDP_AUX1_AUX_LS_STATUS                                  =$5C21;
 mmDP_AUX1_AUX_SW_DATA                                    =$5C22;
 mmDP_AUX1_AUX_LS_DATA                                    =$5C23;
 mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                        =$5C24;
 mmDP_AUX1_AUX_DPHY_TX_CONTROL                            =$5C25;
 mmDP_AUX1_AUX_DPHY_RX_CONTROL0                           =$5C26;
 mmDP_AUX1_AUX_DPHY_RX_CONTROL1                           =$5C27;
 mmDP_AUX1_AUX_DPHY_TX_STATUS                             =$5C28;
 mmDP_AUX1_AUX_DPHY_RX_STATUS                             =$5C29;
 mmDP_AUX1_AUX_GTC_SYNC_CONTROL                           =$5C2A;
 mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                     =$5C2B;
 mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                 =$5C2C;
 mmDP_AUX1_AUX_GTC_SYNC_STATUS                            =$5C2D;
 mmDP_AUX1_AUX_GTC_SYNC_DATA                              =$5C2E;
 mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             =$5C2F;
 mmDP_AUX1_AUX_TEST_DEBUG_INDEX                           =$5C30;
 mmDP_AUX1_AUX_TEST_DEBUG_DATA                            =$5C31;
 mmDP_AUX2_AUX_CONTROL                                    =$5C38;
 mmDP_AUX2_AUX_SW_CONTROL                                 =$5C39;
 mmDP_AUX2_AUX_ARB_CONTROL                                =$5C3A;
 mmDP_AUX2_AUX_INTERRUPT_CONTROL                          =$5C3B;
 mmDP_AUX2_AUX_SW_STATUS                                  =$5C3C;
 mmDP_AUX2_AUX_LS_STATUS                                  =$5C3D;
 mmDP_AUX2_AUX_SW_DATA                                    =$5C3E;
 mmDP_AUX2_AUX_LS_DATA                                    =$5C3F;
 mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                        =$5C40;
 mmDP_AUX2_AUX_DPHY_TX_CONTROL                            =$5C41;
 mmDP_AUX2_AUX_DPHY_RX_CONTROL0                           =$5C42;
 mmDP_AUX2_AUX_DPHY_RX_CONTROL1                           =$5C43;
 mmDP_AUX2_AUX_DPHY_TX_STATUS                             =$5C44;
 mmDP_AUX2_AUX_DPHY_RX_STATUS                             =$5C45;
 mmDP_AUX2_AUX_GTC_SYNC_CONTROL                           =$5C46;
 mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                     =$5C47;
 mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                 =$5C48;
 mmDP_AUX2_AUX_GTC_SYNC_STATUS                            =$5C49;
 mmDP_AUX2_AUX_GTC_SYNC_DATA                              =$5C4A;
 mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             =$5C4B;
 mmDP_AUX2_AUX_TEST_DEBUG_INDEX                           =$5C4C;
 mmDP_AUX2_AUX_TEST_DEBUG_DATA                            =$5C4D;
 mmDP_AUX3_AUX_CONTROL                                    =$5C54;
 mmDP_AUX3_AUX_SW_CONTROL                                 =$5C55;
 mmDP_AUX3_AUX_ARB_CONTROL                                =$5C56;
 mmDP_AUX3_AUX_INTERRUPT_CONTROL                          =$5C57;
 mmDP_AUX3_AUX_SW_STATUS                                  =$5C58;
 mmDP_AUX3_AUX_LS_STATUS                                  =$5C59;
 mmDP_AUX3_AUX_SW_DATA                                    =$5C5A;
 mmDP_AUX3_AUX_LS_DATA                                    =$5C5B;
 mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                        =$5C5C;
 mmDP_AUX3_AUX_DPHY_TX_CONTROL                            =$5C5D;
 mmDP_AUX3_AUX_DPHY_RX_CONTROL0                           =$5C5E;
 mmDP_AUX3_AUX_DPHY_RX_CONTROL1                           =$5C5F;
 mmDP_AUX3_AUX_DPHY_TX_STATUS                             =$5C60;
 mmDP_AUX3_AUX_DPHY_RX_STATUS                             =$5C61;
 mmDP_AUX3_AUX_GTC_SYNC_CONTROL                           =$5C62;
 mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                     =$5C63;
 mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                 =$5C64;
 mmDP_AUX3_AUX_GTC_SYNC_STATUS                            =$5C65;
 mmDP_AUX3_AUX_GTC_SYNC_DATA                              =$5C66;
 mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             =$5C67;
 mmDP_AUX3_AUX_TEST_DEBUG_INDEX                           =$5C68;
 mmDP_AUX3_AUX_TEST_DEBUG_DATA                            =$5C69;
 mmDP_AUX4_AUX_CONTROL                                    =$5C70;
 mmDP_AUX4_AUX_SW_CONTROL                                 =$5C71;
 mmDP_AUX4_AUX_ARB_CONTROL                                =$5C72;
 mmDP_AUX4_AUX_INTERRUPT_CONTROL                          =$5C73;
 mmDP_AUX4_AUX_SW_STATUS                                  =$5C74;
 mmDP_AUX4_AUX_LS_STATUS                                  =$5C75;
 mmDP_AUX4_AUX_SW_DATA                                    =$5C76;
 mmDP_AUX4_AUX_LS_DATA                                    =$5C77;
 mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                        =$5C78;
 mmDP_AUX4_AUX_DPHY_TX_CONTROL                            =$5C79;
 mmDP_AUX4_AUX_DPHY_RX_CONTROL0                           =$5C7A;
 mmDP_AUX4_AUX_DPHY_RX_CONTROL1                           =$5C7B;
 mmDP_AUX4_AUX_DPHY_TX_STATUS                             =$5C7C;
 mmDP_AUX4_AUX_DPHY_RX_STATUS                             =$5C7D;
 mmDP_AUX4_AUX_GTC_SYNC_CONTROL                           =$5C7E;
 mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                     =$5C7F;
 mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                 =$5C80;
 mmDP_AUX4_AUX_GTC_SYNC_STATUS                            =$5C81;
 mmDP_AUX4_AUX_GTC_SYNC_DATA                              =$5C82;
 mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             =$5C83;
 mmDP_AUX4_AUX_TEST_DEBUG_INDEX                           =$5C84;
 mmDP_AUX4_AUX_TEST_DEBUG_DATA                            =$5C85;
 mmDP_AUX5_AUX_CONTROL                                    =$5C8C;
 mmDP_AUX5_AUX_SW_CONTROL                                 =$5C8D;
 mmDP_AUX5_AUX_ARB_CONTROL                                =$5C8E;
 mmDP_AUX5_AUX_INTERRUPT_CONTROL                          =$5C8F;
 mmDP_AUX5_AUX_SW_STATUS                                  =$5C90;
 mmDP_AUX5_AUX_LS_STATUS                                  =$5C91;
 mmDP_AUX5_AUX_SW_DATA                                    =$5C92;
 mmDP_AUX5_AUX_LS_DATA                                    =$5C93;
 mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL                        =$5C94;
 mmDP_AUX5_AUX_DPHY_TX_CONTROL                            =$5C95;
 mmDP_AUX5_AUX_DPHY_RX_CONTROL0                           =$5C96;
 mmDP_AUX5_AUX_DPHY_RX_CONTROL1                           =$5C97;
 mmDP_AUX5_AUX_DPHY_TX_STATUS                             =$5C98;
 mmDP_AUX5_AUX_DPHY_RX_STATUS                             =$5C99;
 mmDP_AUX5_AUX_GTC_SYNC_CONTROL                           =$5C9A;
 mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL                     =$5C9B;
 mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS                 =$5C9C;
 mmDP_AUX5_AUX_GTC_SYNC_STATUS                            =$5C9D;
 mmDP_AUX5_AUX_GTC_SYNC_DATA                              =$5C9E;
 mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             =$5C9F;
 mmDP_AUX5_AUX_TEST_DEBUG_INDEX                           =$5CA0;
 mmDP_AUX5_AUX_TEST_DEBUG_DATA                            =$5CA1;
 mmDPHY_MACRO_CNTL_RESERVED0                              =$5D98;
 mmDPHY_MACRO_CNTL_RESERVED1                              =$5D99;
 mmDPHY_MACRO_CNTL_RESERVED2                              =$5D9A;
 mmDPHY_MACRO_CNTL_RESERVED3                              =$5D9B;
 mmDPHY_MACRO_CNTL_RESERVED4                              =$5D9C;
 mmDPHY_MACRO_CNTL_RESERVED5                              =$5D9D;
 mmDPHY_MACRO_CNTL_RESERVED6                              =$5D9E;
 mmDPHY_MACRO_CNTL_RESERVED7                              =$5D9F;
 mmDPHY_MACRO_CNTL_RESERVED8                              =$5DA0;
 mmDPHY_MACRO_CNTL_RESERVED9                              =$5DA1;
 mmDPHY_MACRO_CNTL_RESERVED10                             =$5DA2;
 mmDPHY_MACRO_CNTL_RESERVED11                             =$5DA3;
 mmDPHY_MACRO_CNTL_RESERVED12                             =$5DA4;
 mmDPHY_MACRO_CNTL_RESERVED13                             =$5DA5;
 mmDPHY_MACRO_CNTL_RESERVED14                             =$5DA6;
 mmDPHY_MACRO_CNTL_RESERVED15                             =$5DA7;
 mmDPHY_MACRO_CNTL_RESERVED16                             =$5DA8;
 mmDPHY_MACRO_CNTL_RESERVED17                             =$5DA9;
 mmDPHY_MACRO_CNTL_RESERVED18                             =$5DAA;
 mmDPHY_MACRO_CNTL_RESERVED19                             =$5DAB;
 mmDPHY_MACRO_CNTL_RESERVED20                             =$5DAC;
 mmDPHY_MACRO_CNTL_RESERVED21                             =$5DAD;
 mmDPHY_MACRO_CNTL_RESERVED22                             =$5DAE;
 mmDPHY_MACRO_CNTL_RESERVED23                             =$5DAF;
 mmDPHY_MACRO_CNTL_RESERVED24                             =$5DB0;
 mmDPHY_MACRO_CNTL_RESERVED25                             =$5DB1;
 mmDPHY_MACRO_CNTL_RESERVED26                             =$5DB2;
 mmDPHY_MACRO_CNTL_RESERVED27                             =$5DB3;
 mmDPHY_MACRO_CNTL_RESERVED28                             =$5DB4;
 mmDPHY_MACRO_CNTL_RESERVED29                             =$5DB5;
 mmDPHY_MACRO_CNTL_RESERVED30                             =$5DB6;
 mmDPHY_MACRO_CNTL_RESERVED31                             =$5DB7;
 mmDPHY_MACRO_CNTL_RESERVED32                             =$5DB8;
 mmDPHY_MACRO_CNTL_RESERVED33                             =$5DB9;
 mmDPHY_MACRO_CNTL_RESERVED34                             =$5DBA;
 mmDPHY_MACRO_CNTL_RESERVED35                             =$5DBB;
 mmDPHY_MACRO_CNTL_RESERVED36                             =$5DBC;
 mmDPHY_MACRO_CNTL_RESERVED37                             =$5DBD;
 mmDPHY_MACRO_CNTL_RESERVED38                             =$5DBE;
 mmDPHY_MACRO_CNTL_RESERVED39                             =$5DBF;
 mmDPHY_MACRO_CNTL_RESERVED40                             =$5DC0;
 mmDPHY_MACRO_CNTL_RESERVED41                             =$5DC1;
 mmDPHY_MACRO_CNTL_RESERVED42                             =$5DC2;
 mmDPHY_MACRO_CNTL_RESERVED43                             =$5DC3;
 mmDPHY_MACRO_CNTL_RESERVED44                             =$5DC4;
 mmDPHY_MACRO_CNTL_RESERVED45                             =$5DC5;
 mmDPHY_MACRO_CNTL_RESERVED46                             =$5DC6;
 mmDPHY_MACRO_CNTL_RESERVED47                             =$5DC7;
 mmDPHY_MACRO_CNTL_RESERVED48                             =$5DC8;
 mmDPHY_MACRO_CNTL_RESERVED49                             =$5DC9;
 mmDPHY_MACRO_CNTL_RESERVED50                             =$5DCA;
 mmDPHY_MACRO_CNTL_RESERVED51                             =$5DCB;
 mmDPHY_MACRO_CNTL_RESERVED52                             =$5DCC;
 mmDPHY_MACRO_CNTL_RESERVED53                             =$5DCD;
 mmDPHY_MACRO_CNTL_RESERVED54                             =$5DCE;
 mmDPHY_MACRO_CNTL_RESERVED55                             =$5DCF;
 mmDPHY_MACRO_CNTL_RESERVED56                             =$5DD0;
 mmDPHY_MACRO_CNTL_RESERVED57                             =$5DD1;
 mmDPHY_MACRO_CNTL_RESERVED58                             =$5DD2;
 mmDPHY_MACRO_CNTL_RESERVED59                             =$5DD3;
 mmDPHY_MACRO_CNTL_RESERVED60                             =$5DD4;
 mmDPHY_MACRO_CNTL_RESERVED61                             =$5DD5;
 mmDPHY_MACRO_CNTL_RESERVED62                             =$5DD6;
 mmDPHY_MACRO_CNTL_RESERVED63                             =$5DD7;
 mmWB_ENABLE                                              =$5E18;
 mmWB_EC_CONFIG                                           =$5E19;
 mmCNV_MODE                                               =$5E1A;
 mmCNV_WINDOW_START                                       =$5E1B;
 mmCNV_WINDOW_SIZE                                        =$5E1C;
 mmCNV_UPDATE                                             =$5E1D;
 mmCNV_SOURCE_SIZE                                        =$5E1E;
 mmCNV_CSC_CONTROL                                        =$5E1F;
 mmCNV_CSC_C11_C12                                        =$5E20;
 mmCNV_CSC_C13_C14                                        =$5E21;
 mmCNV_CSC_C21_C22                                        =$5E22;
 mmCNV_CSC_C23_C24                                        =$5E23;
 mmCNV_CSC_C31_C32                                        =$5E24;
 mmCNV_CSC_C33_C34                                        =$5E25;
 mmCNV_CSC_ROUND_OFFSET_R                                 =$5E26;
 mmCNV_CSC_ROUND_OFFSET_G                                 =$5E27;
 mmCNV_CSC_ROUND_OFFSET_B                                 =$5E28;
 mmCNV_CSC_CLAMP_R                                        =$5E29;
 mmCNV_CSC_CLAMP_G                                        =$5E2A;
 mmCNV_CSC_CLAMP_B                                        =$5E2B;
 mmCNV_TEST_CNTL                                          =$5E2C;
 mmCNV_TEST_CRC_RED                                       =$5E2D;
 mmCNV_TEST_CRC_GREEN                                     =$5E2E;
 mmCNV_TEST_CRC_BLUE                                      =$5E2F;
 mmWB_DEBUG_CTRL                                          =$5E30;
 mmWB_DBG_MODE                                            =$5E31;
 mmWB_HW_DEBUG                                            =$5E32;
 mmCNV_INPUT_SELECT                                       =$5E33;
 mmCNV_TEST_DEBUG_INDEX                                   =$5E34;
 mmCNV_TEST_DEBUG_DATA                                    =$5E35;
 mmWB_SOFT_RESET                                          =$5E36;
 mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                     =$5E78;
 mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R                     =$5E79;
 mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS                         =$5E7A;
 mmMCIF_WB0_MCIF_WB_BUF_PITCH                             =$5E7B;
 mmMCIF_WB0_MCIF_WB_BUF_1_STATUS                          =$5E7C;
 mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2                         =$5E7D;
 mmMCIF_WB0_MCIF_WB_BUF_2_STATUS                          =$5E7E;
 mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2                         =$5E7F;
 mmMCIF_WB0_MCIF_WB_BUF_3_STATUS                          =$5E80;
 mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2                         =$5E81;
 mmMCIF_WB0_MCIF_WB_BUF_4_STATUS                          =$5E82;
 mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2                         =$5E83;
 mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL                   =$5E84;
 mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK                     =$5E85;
 mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX                      =$5E86;
 mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA                       =$5E87;
 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y                          =$5E88;
 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET                   =$5E89;
 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C                          =$5E8A;
 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET                   =$5E8B;
 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y                          =$5E8C;
 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET                   =$5E8D;
 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C                          =$5E8E;
 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET                   =$5E8F;
 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y                          =$5E90;
 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET                   =$5E91;
 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C                          =$5E92;
 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET                   =$5E93;
 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y                          =$5E94;
 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET                   =$5E95;
 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C                          =$5E96;
 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET                   =$5E97;
 mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL                    =$5E98;
 mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL                        =$5E99;
 mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                     =$5EB8;
 mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R                     =$5EB9;
 mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS                         =$5EBA;
 mmMCIF_WB1_MCIF_WB_BUF_PITCH                             =$5EBB;
 mmMCIF_WB1_MCIF_WB_BUF_1_STATUS                          =$5EBC;
 mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2                         =$5EBD;
 mmMCIF_WB1_MCIF_WB_BUF_2_STATUS                          =$5EBE;
 mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2                         =$5EBF;
 mmMCIF_WB1_MCIF_WB_BUF_3_STATUS                          =$5EC0;
 mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2                         =$5EC1;
 mmMCIF_WB1_MCIF_WB_BUF_4_STATUS                          =$5EC2;
 mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2                         =$5EC3;
 mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL                   =$5EC4;
 mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK                     =$5EC5;
 mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX                      =$5EC6;
 mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA                       =$5EC7;
 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y                          =$5EC8;
 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET                   =$5EC9;
 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C                          =$5ECA;
 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET                   =$5ECB;
 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y                          =$5ECC;
 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET                   =$5ECD;
 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C                          =$5ECE;
 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET                   =$5ECF;
 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y                          =$5ED0;
 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET                   =$5ED1;
 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C                          =$5ED2;
 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET                   =$5ED3;
 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y                          =$5ED4;
 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET                   =$5ED5;
 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C                          =$5ED6;
 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET                   =$5ED7;
 mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL                    =$5ED8;
 mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL                        =$5ED9;
 mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL                     =$5EF8;
 mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R                     =$5EF9;
 mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS                         =$5EFA;
 mmMCIF_WB2_MCIF_WB_BUF_PITCH                             =$5EFB;
 mmMCIF_WB2_MCIF_WB_BUF_1_STATUS                          =$5EFC;
 mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2                         =$5EFD;
 mmMCIF_WB2_MCIF_WB_BUF_2_STATUS                          =$5EFE;
 mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2                         =$5EFF;
 mmMCIF_WB2_MCIF_WB_BUF_3_STATUS                          =$5F00;
 mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2                         =$5F01;
 mmMCIF_WB2_MCIF_WB_BUF_4_STATUS                          =$5F02;
 mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2                         =$5F03;
 mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL                   =$5F04;
 mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK                     =$5F05;
 mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX                      =$5F06;
 mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA                       =$5F07;
 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y                          =$5F08;
 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET                   =$5F09;
 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C                          =$5F0A;
 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET                   =$5F0B;
 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y                          =$5F0C;
 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET                   =$5F0D;
 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C                          =$5F0E;
 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET                   =$5F0F;
 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y                          =$5F10;
 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET                   =$5F11;
 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C                          =$5F12;
 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET                   =$5F13;
 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y                          =$5F14;
 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET                   =$5F15;
 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C                          =$5F16;
 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET                   =$5F17;
 mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL                    =$5F18;
 mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL                        =$5F19;
 mmDC_PERFMON9_PERFCOUNTER_CNTL                           =$5F68;
 mmDC_PERFMON9_PERFCOUNTER_STATE                          =$5F69;
 mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                    =$5F6A;
 mmDC_PERFMON9_PERFMON_CNTL                               =$5F6B;
 mmDC_PERFMON9_PERFMON_CVALUE_LOW                         =$5F6C;
 mmDC_PERFMON9_PERFMON_HI                                 =$5F6D;
 mmDC_PERFMON9_PERFMON_LOW                                =$5F6E;
 mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX                   =$5F6F;
 mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA                    =$5F70;
 mmDC_PERFMON9_PERFMON_CNTL2                              =$5F72;
 mmCPLL_MACRO_CNTL_RESERVED0                              =$5FD0;
 mmCPLL_MACRO_CNTL_RESERVED1                              =$5FD1;
 mmCPLL_MACRO_CNTL_RESERVED2                              =$5FD2;
 mmCPLL_MACRO_CNTL_RESERVED3                              =$5FD3;
 mmCPLL_MACRO_CNTL_RESERVED4                              =$5FD4;
 mmCPLL_MACRO_CNTL_RESERVED5                              =$5FD5;
 mmCPLL_MACRO_CNTL_RESERVED6                              =$5FD6;
 mmCPLL_MACRO_CNTL_RESERVED7                              =$5FD7;
 mmCPLL_MACRO_CNTL_RESERVED8                              =$5FD8;
 mmCPLL_MACRO_CNTL_RESERVED9                              =$5FD9;
 mmCPLL_MACRO_CNTL_RESERVED10                             =$5FDA;
 mmCPLL_MACRO_CNTL_RESERVED11                             =$5FDB;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0                   =$5FDC;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1                   =$5FDD;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2                   =$5FDE;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3                   =$5FDF;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4                   =$5FE0;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5                   =$5FE1;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6                   =$5FE2;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7                   =$5FE3;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8                   =$5FE4;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9                   =$5FE5;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10                  =$5FE6;
 mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11                  =$5FE7;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0                   =$5FE8;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1                   =$5FE9;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2                   =$5FEA;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3                   =$5FEB;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4                   =$5FEC;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5                   =$5FED;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6                   =$5FEE;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7                   =$5FEF;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8                   =$5FF0;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9                   =$5FF1;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10                  =$5FF2;
 mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11                  =$5FF3;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0                   =$5FF4;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1                   =$5FF5;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2                   =$5FF6;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3                   =$5FF7;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4                   =$5FF8;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5                   =$5FF9;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6                   =$5FFA;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7                   =$5FFB;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8                   =$5FFC;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9                   =$5FFD;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10                  =$5FFE;
 mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11                  =$5FFF;
 mmSRBM_PERFMON_CNTL                                      =$7C00;
 mmSRBM_PERFCOUNTER0_SELECT                               =$7C01;
 mmSRBM_PERFCOUNTER1_SELECT                               =$7C02;
 mmSRBM_PERFCOUNTER0_LO                                   =$7C03;
 mmSRBM_PERFCOUNTER0_HI                                   =$7C04;
 mmSRBM_PERFCOUNTER1_LO                                   =$7C05;
 mmSRBM_PERFCOUNTER1_HI                                   =$7C06;
 mmVCE_STATUS                                             =$8001;
 mmVCE_VCPU_CNTL                                          =$8005;
 mmVCE_VCPU_CACHE_OFFSET0                                 =$8009;
 mmVCE_VCPU_CACHE_SIZE0                                   =$800A;
 mmVCE_VCPU_CACHE_OFFSET1                                 =$800B;
 mmVCE_VCPU_CACHE_SIZE1                                   =$800C;
 mmVCE_VCPU_CACHE_OFFSET2                                 =$800D;
 mmVCE_VCPU_CACHE_SIZE2                                   =$800E;
 mmVCE_SOFT_RESET                                         =$8048;
 mmVCE_RB_BASE_LO2                                        =$805B;
 mmVCE_RB_BASE_HI2                                        =$805C;
 mmVCE_RB_SIZE2                                           =$805D;
 mmVCE_RB_RPTR2                                           =$805E;
 mmVCE_RB_WPTR2                                           =$805F;
 mmVCE_RB_BASE_LO                                         =$8060;
 mmVCE_RB_BASE_HI                                         =$8061;
 mmVCE_RB_SIZE                                            =$8062;
 mmVCE_RB_RPTR                                            =$8063;
 mmVCE_RB_WPTR                                            =$8064;
 mmVCE_RB_ARB_CTRL                                        =$809F;
 mmVCE_RB_BASE_LO3                                        =$80D4;
 mmVCE_RB_BASE_HI3                                        =$80D5;
 mmVCE_RB_SIZE3                                           =$80D6;
 mmVCE_RB_RPTR3                                           =$80D7;
 mmVCE_RB_WPTR3                                           =$80D8;
 mmVCE_UENC_DMA_DCLK_CTRL                                 =$8390;
 mmVCE_SYS_INT_EN                                         =$8540;
 mmVCE_SYS_INT_ACK                                        =$8541;
 mmVCE_LMI_VCPU_CACHE_40BIT_BAR                           =$8597;
 mmVCE_LMI_CTRL2                                          =$859D;
 mmVCE_LMI_SWAP_CNTL3                                     =$859E;
 mmVCE_LMI_CTRL                                           =$85A6;
 mmVCE_LMI_SWAP_CNTL                                      =$85AD;
 mmVCE_LMI_SWAP_CNTL1                                     =$85AE;
 mmVCE_LMI_SWAP_CNTL2                                     =$85B3;
 mmVCE_LMI_CACHE_CTRL                                     =$85BD;
 mmSAM_IH_EXT_ERR_INTR                                    =$8810;
 mmSAM_IH_EXT_ERR_INTR_STATUS                             =$8812;
 mmSDMA0_PERFMON_CNTL                                     =$9000;
 mmSDMA0_PERFCOUNTER0_RESULT                              =$9001;
 mmSDMA0_PERFCOUNTER1_RESULT                              =$9002;
 mmSDMA1_PERFMON_CNTL                                     =$9010;
 mmSDMA1_PERFCOUNTER0_RESULT                              =$9011;
 mmSDMA1_PERFCOUNTER1_RESULT                              =$9012;
 mmDB_RENDER_CONTROL                                      =$A000;
 mmDB_COUNT_CONTROL                                       =$A001;
 mmDB_DEPTH_VIEW                                          =$A002;
 mmDB_RENDER_OVERRIDE                                     =$A003;
 mmDB_RENDER_OVERRIDE2                                    =$A004;
 mmDB_HTILE_DATA_BASE                                     =$A005;
 mmDB_DEPTH_BOUNDS_MIN                                    =$A008;
 mmDB_DEPTH_BOUNDS_MAX                                    =$A009;
 mmDB_STENCIL_CLEAR                                       =$A00A;
 mmDB_DEPTH_CLEAR                                         =$A00B;
 mmPA_SC_SCREEN_SCISSOR_TL                                =$A00C;
 mmPA_SC_SCREEN_SCISSOR_BR                                =$A00D;
 mmDB_DEPTH_INFO                                          =$A00F;
 mmDB_Z_INFO                                              =$A010;
 mmDB_STENCIL_INFO                                        =$A011;
 mmDB_Z_READ_BASE                                         =$A012;
 mmDB_STENCIL_READ_BASE                                   =$A013;
 mmDB_Z_WRITE_BASE                                        =$A014;
 mmDB_STENCIL_WRITE_BASE                                  =$A015;
 mmDB_DEPTH_SIZE                                          =$A016;
 mmDB_DEPTH_SLICE                                         =$A017;
 mmTA_BC_BASE_ADDR                                        =$A020;
 mmTA_BC_BASE_ADDR_HI                                     =$A021;
 mmCOHER_DEST_BASE_HI_0                                   =$A07A;
 mmCOHER_DEST_BASE_HI_1                                   =$A07B;
 mmCOHER_DEST_BASE_HI_2                                   =$A07C;
 mmCOHER_DEST_BASE_HI_3                                   =$A07D;
 mmCOHER_DEST_BASE_2                                      =$A07E;
 mmCOHER_DEST_BASE_3                                      =$A07F;
 mmPA_SC_WINDOW_OFFSET                                    =$A080;
 mmPA_SC_WINDOW_SCISSOR_TL                                =$A081;
 mmPA_SC_WINDOW_SCISSOR_BR                                =$A082;
 mmPA_SC_CLIPRECT_RULE                                    =$A083;
 mmPA_SC_CLIPRECT_0_TL                                    =$A084;
 mmPA_SC_CLIPRECT_0_BR                                    =$A085;
 mmPA_SC_CLIPRECT_1_TL                                    =$A086;
 mmPA_SC_CLIPRECT_1_BR                                    =$A087;
 mmPA_SC_CLIPRECT_2_TL                                    =$A088;
 mmPA_SC_CLIPRECT_2_BR                                    =$A089;
 mmPA_SC_CLIPRECT_3_TL                                    =$A08A;
 mmPA_SC_CLIPRECT_3_BR                                    =$A08B;
 mmPA_SC_EDGERULE                                         =$A08C;
 mmPA_SU_HARDWARE_SCREEN_OFFSET                           =$A08D;
 mmCB_TARGET_MASK                                         =$A08E;
 mmCB_SHADER_MASK                                         =$A08F;
 mmPA_SC_GENERIC_SCISSOR_TL                               =$A090;
 mmPA_SC_GENERIC_SCISSOR_BR                               =$A091;
 mmCOHER_DEST_BASE_0                                      =$A092;
 mmCOHER_DEST_BASE_1                                      =$A093;
 mmPA_SC_VPORT_SCISSOR_0_TL                               =$A094;
 mmPA_SC_VPORT_SCISSOR_0_BR                               =$A095;
 mmPA_SC_VPORT_SCISSOR_1_TL                               =$A096;
 mmPA_SC_VPORT_SCISSOR_1_BR                               =$A097;
 mmPA_SC_VPORT_SCISSOR_2_TL                               =$A098;
 mmPA_SC_VPORT_SCISSOR_2_BR                               =$A099;
 mmPA_SC_VPORT_SCISSOR_3_TL                               =$A09A;
 mmPA_SC_VPORT_SCISSOR_3_BR                               =$A09B;
 mmPA_SC_VPORT_SCISSOR_4_TL                               =$A09C;
 mmPA_SC_VPORT_SCISSOR_4_BR                               =$A09D;
 mmPA_SC_VPORT_SCISSOR_5_TL                               =$A09E;
 mmPA_SC_VPORT_SCISSOR_5_BR                               =$A09F;
 mmPA_SC_VPORT_SCISSOR_6_TL                               =$A0A0;
 mmPA_SC_VPORT_SCISSOR_6_BR                               =$A0A1;
 mmPA_SC_VPORT_SCISSOR_7_TL                               =$A0A2;
 mmPA_SC_VPORT_SCISSOR_7_BR                               =$A0A3;
 mmPA_SC_VPORT_SCISSOR_8_TL                               =$A0A4;
 mmPA_SC_VPORT_SCISSOR_8_BR                               =$A0A5;
 mmPA_SC_VPORT_SCISSOR_9_TL                               =$A0A6;
 mmPA_SC_VPORT_SCISSOR_9_BR                               =$A0A7;
 mmPA_SC_VPORT_SCISSOR_10_TL                              =$A0A8;
 mmPA_SC_VPORT_SCISSOR_10_BR                              =$A0A9;
 mmPA_SC_VPORT_SCISSOR_11_TL                              =$A0AA;
 mmPA_SC_VPORT_SCISSOR_11_BR                              =$A0AB;
 mmPA_SC_VPORT_SCISSOR_12_TL                              =$A0AC;
 mmPA_SC_VPORT_SCISSOR_12_BR                              =$A0AD;
 mmPA_SC_VPORT_SCISSOR_13_TL                              =$A0AE;
 mmPA_SC_VPORT_SCISSOR_13_BR                              =$A0AF;
 mmPA_SC_VPORT_SCISSOR_14_TL                              =$A0B0;
 mmPA_SC_VPORT_SCISSOR_14_BR                              =$A0B1;
 mmPA_SC_VPORT_SCISSOR_15_TL                              =$A0B2;
 mmPA_SC_VPORT_SCISSOR_15_BR                              =$A0B3;
 mmPA_SC_VPORT_ZMIN_0                                     =$A0B4;
 mmPA_SC_VPORT_ZMAX_0                                     =$A0B5;
 mmPA_SC_VPORT_ZMIN_1                                     =$A0B6;
 mmPA_SC_VPORT_ZMAX_1                                     =$A0B7;
 mmPA_SC_VPORT_ZMIN_2                                     =$A0B8;
 mmPA_SC_VPORT_ZMAX_2                                     =$A0B9;
 mmPA_SC_VPORT_ZMIN_3                                     =$A0BA;
 mmPA_SC_VPORT_ZMAX_3                                     =$A0BB;
 mmPA_SC_VPORT_ZMIN_4                                     =$A0BC;
 mmPA_SC_VPORT_ZMAX_4                                     =$A0BD;
 mmPA_SC_VPORT_ZMIN_5                                     =$A0BE;
 mmPA_SC_VPORT_ZMAX_5                                     =$A0BF;
 mmPA_SC_VPORT_ZMIN_6                                     =$A0C0;
 mmPA_SC_VPORT_ZMAX_6                                     =$A0C1;
 mmPA_SC_VPORT_ZMIN_7                                     =$A0C2;
 mmPA_SC_VPORT_ZMAX_7                                     =$A0C3;
 mmPA_SC_VPORT_ZMIN_8                                     =$A0C4;
 mmPA_SC_VPORT_ZMAX_8                                     =$A0C5;
 mmPA_SC_VPORT_ZMIN_9                                     =$A0C6;
 mmPA_SC_VPORT_ZMAX_9                                     =$A0C7;
 mmPA_SC_VPORT_ZMIN_10                                    =$A0C8;
 mmPA_SC_VPORT_ZMAX_10                                    =$A0C9;
 mmPA_SC_VPORT_ZMIN_11                                    =$A0CA;
 mmPA_SC_VPORT_ZMAX_11                                    =$A0CB;
 mmPA_SC_VPORT_ZMIN_12                                    =$A0CC;
 mmPA_SC_VPORT_ZMAX_12                                    =$A0CD;
 mmPA_SC_VPORT_ZMIN_13                                    =$A0CE;
 mmPA_SC_VPORT_ZMAX_13                                    =$A0CF;
 mmPA_SC_VPORT_ZMIN_14                                    =$A0D0;
 mmPA_SC_VPORT_ZMAX_14                                    =$A0D1;
 mmPA_SC_VPORT_ZMIN_15                                    =$A0D2;
 mmPA_SC_VPORT_ZMAX_15                                    =$A0D3;
 mmPA_SC_RASTER_CONFIG                                    =$A0D4;
 mmPA_SC_RASTER_CONFIG_1                                  =$A0D5;
 mmCP_PERFMON_CNTX_CNTL                                   =$A0D8;
 mmCP_PIPEID                                              =$A0D9;
 mmCP_VMID                                                =$A0DA;
 mmVGT_MAX_VTX_INDX                                       =$A100;
 mmVGT_MIN_VTX_INDX                                       =$A101;
 mmVGT_INDX_OFFSET                                        =$A102;
 mmVGT_MULTI_PRIM_IB_RESET_INDX                           =$A103;
 mmCB_BLEND_RED                                           =$A105;
 mmCB_BLEND_GREEN                                         =$A106;
 mmCB_BLEND_BLUE                                          =$A107;
 mmCB_BLEND_ALPHA                                         =$A108;
 mmCB_DCC_CONTROL                                         =$A109;
 mmDB_STENCIL_CONTROL                                     =$A10B;
 mmDB_STENCILREFMASK                                      =$A10C;
 mmDB_STENCILREFMASK_BF                                   =$A10D;
 mmPA_CL_VPORT_XSCALE                                     =$A10F;
 mmPA_CL_VPORT_XOFFSET                                    =$A110;
 mmPA_CL_VPORT_YSCALE                                     =$A111;
 mmPA_CL_VPORT_YOFFSET                                    =$A112;
 mmPA_CL_VPORT_ZSCALE                                     =$A113;
 mmPA_CL_VPORT_ZOFFSET                                    =$A114;
 mmPA_CL_VPORT_XSCALE_1                                   =$A115;
 mmPA_CL_VPORT_XOFFSET_1                                  =$A116;
 mmPA_CL_VPORT_YSCALE_1                                   =$A117;
 mmPA_CL_VPORT_YOFFSET_1                                  =$A118;
 mmPA_CL_VPORT_ZSCALE_1                                   =$A119;
 mmPA_CL_VPORT_ZOFFSET_1                                  =$A11A;
 mmPA_CL_VPORT_XSCALE_2                                   =$A11B;
 mmPA_CL_VPORT_XOFFSET_2                                  =$A11C;
 mmPA_CL_VPORT_YSCALE_2                                   =$A11D;
 mmPA_CL_VPORT_YOFFSET_2                                  =$A11E;
 mmPA_CL_VPORT_ZSCALE_2                                   =$A11F;
 mmPA_CL_VPORT_ZOFFSET_2                                  =$A120;
 mmPA_CL_VPORT_XSCALE_3                                   =$A121;
 mmPA_CL_VPORT_XOFFSET_3                                  =$A122;
 mmPA_CL_VPORT_YSCALE_3                                   =$A123;
 mmPA_CL_VPORT_YOFFSET_3                                  =$A124;
 mmPA_CL_VPORT_ZSCALE_3                                   =$A125;
 mmPA_CL_VPORT_ZOFFSET_3                                  =$A126;
 mmPA_CL_VPORT_XSCALE_4                                   =$A127;
 mmPA_CL_VPORT_XOFFSET_4                                  =$A128;
 mmPA_CL_VPORT_YSCALE_4                                   =$A129;
 mmPA_CL_VPORT_YOFFSET_4                                  =$A12A;
 mmPA_CL_VPORT_ZSCALE_4                                   =$A12B;
 mmPA_CL_VPORT_ZOFFSET_4                                  =$A12C;
 mmPA_CL_VPORT_XSCALE_5                                   =$A12D;
 mmPA_CL_VPORT_XOFFSET_5                                  =$A12E;
 mmPA_CL_VPORT_YSCALE_5                                   =$A12F;
 mmPA_CL_VPORT_YOFFSET_5                                  =$A130;
 mmPA_CL_VPORT_ZSCALE_5                                   =$A131;
 mmPA_CL_VPORT_ZOFFSET_5                                  =$A132;
 mmPA_CL_VPORT_XSCALE_6                                   =$A133;
 mmPA_CL_VPORT_XOFFSET_6                                  =$A134;
 mmPA_CL_VPORT_YSCALE_6                                   =$A135;
 mmPA_CL_VPORT_YOFFSET_6                                  =$A136;
 mmPA_CL_VPORT_ZSCALE_6                                   =$A137;
 mmPA_CL_VPORT_ZOFFSET_6                                  =$A138;
 mmPA_CL_VPORT_XSCALE_7                                   =$A139;
 mmPA_CL_VPORT_XOFFSET_7                                  =$A13A;
 mmPA_CL_VPORT_YSCALE_7                                   =$A13B;
 mmPA_CL_VPORT_YOFFSET_7                                  =$A13C;
 mmPA_CL_VPORT_ZSCALE_7                                   =$A13D;
 mmPA_CL_VPORT_ZOFFSET_7                                  =$A13E;
 mmPA_CL_VPORT_XSCALE_8                                   =$A13F;
 mmPA_CL_VPORT_XOFFSET_8                                  =$A140;
 mmPA_CL_VPORT_YSCALE_8                                   =$A141;
 mmPA_CL_VPORT_YOFFSET_8                                  =$A142;
 mmPA_CL_VPORT_ZSCALE_8                                   =$A143;
 mmPA_CL_VPORT_ZOFFSET_8                                  =$A144;
 mmPA_CL_VPORT_XSCALE_9                                   =$A145;
 mmPA_CL_VPORT_XOFFSET_9                                  =$A146;
 mmPA_CL_VPORT_YSCALE_9                                   =$A147;
 mmPA_CL_VPORT_YOFFSET_9                                  =$A148;
 mmPA_CL_VPORT_ZSCALE_9                                   =$A149;
 mmPA_CL_VPORT_ZOFFSET_9                                  =$A14A;
 mmPA_CL_VPORT_XSCALE_10                                  =$A14B;
 mmPA_CL_VPORT_XOFFSET_10                                 =$A14C;
 mmPA_CL_VPORT_YSCALE_10                                  =$A14D;
 mmPA_CL_VPORT_YOFFSET_10                                 =$A14E;
 mmPA_CL_VPORT_ZSCALE_10                                  =$A14F;
 mmPA_CL_VPORT_ZOFFSET_10                                 =$A150;
 mmPA_CL_VPORT_XSCALE_11                                  =$A151;
 mmPA_CL_VPORT_XOFFSET_11                                 =$A152;
 mmPA_CL_VPORT_YSCALE_11                                  =$A153;
 mmPA_CL_VPORT_YOFFSET_11                                 =$A154;
 mmPA_CL_VPORT_ZSCALE_11                                  =$A155;
 mmPA_CL_VPORT_ZOFFSET_11                                 =$A156;
 mmPA_CL_VPORT_XSCALE_12                                  =$A157;
 mmPA_CL_VPORT_XOFFSET_12                                 =$A158;
 mmPA_CL_VPORT_YSCALE_12                                  =$A159;
 mmPA_CL_VPORT_YOFFSET_12                                 =$A15A;
 mmPA_CL_VPORT_ZSCALE_12                                  =$A15B;
 mmPA_CL_VPORT_ZOFFSET_12                                 =$A15C;
 mmPA_CL_VPORT_XSCALE_13                                  =$A15D;
 mmPA_CL_VPORT_XOFFSET_13                                 =$A15E;
 mmPA_CL_VPORT_YSCALE_13                                  =$A15F;
 mmPA_CL_VPORT_YOFFSET_13                                 =$A160;
 mmPA_CL_VPORT_ZSCALE_13                                  =$A161;
 mmPA_CL_VPORT_ZOFFSET_13                                 =$A162;
 mmPA_CL_VPORT_XSCALE_14                                  =$A163;
 mmPA_CL_VPORT_XOFFSET_14                                 =$A164;
 mmPA_CL_VPORT_YSCALE_14                                  =$A165;
 mmPA_CL_VPORT_YOFFSET_14                                 =$A166;
 mmPA_CL_VPORT_ZSCALE_14                                  =$A167;
 mmPA_CL_VPORT_ZOFFSET_14                                 =$A168;
 mmPA_CL_VPORT_XSCALE_15                                  =$A169;
 mmPA_CL_VPORT_XOFFSET_15                                 =$A16A;
 mmPA_CL_VPORT_YSCALE_15                                  =$A16B;
 mmPA_CL_VPORT_YOFFSET_15                                 =$A16C;
 mmPA_CL_VPORT_ZSCALE_15                                  =$A16D;
 mmPA_CL_VPORT_ZOFFSET_15                                 =$A16E;
 mmPA_CL_UCP_0_X                                          =$A16F;
 mmPA_CL_UCP_0_Y                                          =$A170;
 mmPA_CL_UCP_0_Z                                          =$A171;
 mmPA_CL_UCP_0_W                                          =$A172;
 mmPA_CL_UCP_1_X                                          =$A173;
 mmPA_CL_UCP_1_Y                                          =$A174;
 mmPA_CL_UCP_1_Z                                          =$A175;
 mmPA_CL_UCP_1_W                                          =$A176;
 mmPA_CL_UCP_2_X                                          =$A177;
 mmPA_CL_UCP_2_Y                                          =$A178;
 mmPA_CL_UCP_2_Z                                          =$A179;
 mmPA_CL_UCP_2_W                                          =$A17A;
 mmPA_CL_UCP_3_X                                          =$A17B;
 mmPA_CL_UCP_3_Y                                          =$A17C;
 mmPA_CL_UCP_3_Z                                          =$A17D;
 mmPA_CL_UCP_3_W                                          =$A17E;
 mmPA_CL_UCP_4_X                                          =$A17F;
 mmPA_CL_UCP_4_Y                                          =$A180;
 mmPA_CL_UCP_4_Z                                          =$A181;
 mmPA_CL_UCP_4_W                                          =$A182;
 mmPA_CL_UCP_5_X                                          =$A183;
 mmPA_CL_UCP_5_Y                                          =$A184;
 mmPA_CL_UCP_5_Z                                          =$A185;
 mmPA_CL_UCP_5_W                                          =$A186;
 mmSPI_PS_INPUT_CNTL_0                                    =$A191;
 mmSPI_PS_INPUT_CNTL_1                                    =$A192;
 mmSPI_PS_INPUT_CNTL_2                                    =$A193;
 mmSPI_PS_INPUT_CNTL_3                                    =$A194;
 mmSPI_PS_INPUT_CNTL_4                                    =$A195;
 mmSPI_PS_INPUT_CNTL_5                                    =$A196;
 mmSPI_PS_INPUT_CNTL_6                                    =$A197;
 mmSPI_PS_INPUT_CNTL_7                                    =$A198;
 mmSPI_PS_INPUT_CNTL_8                                    =$A199;
 mmSPI_PS_INPUT_CNTL_9                                    =$A19A;
 mmSPI_PS_INPUT_CNTL_10                                   =$A19B;
 mmSPI_PS_INPUT_CNTL_11                                   =$A19C;
 mmSPI_PS_INPUT_CNTL_12                                   =$A19D;
 mmSPI_PS_INPUT_CNTL_13                                   =$A19E;
 mmSPI_PS_INPUT_CNTL_14                                   =$A19F;
 mmSPI_PS_INPUT_CNTL_15                                   =$A1A0;
 mmSPI_PS_INPUT_CNTL_16                                   =$A1A1;
 mmSPI_PS_INPUT_CNTL_17                                   =$A1A2;
 mmSPI_PS_INPUT_CNTL_18                                   =$A1A3;
 mmSPI_PS_INPUT_CNTL_19                                   =$A1A4;
 mmSPI_PS_INPUT_CNTL_20                                   =$A1A5;
 mmSPI_PS_INPUT_CNTL_21                                   =$A1A6;
 mmSPI_PS_INPUT_CNTL_22                                   =$A1A7;
 mmSPI_PS_INPUT_CNTL_23                                   =$A1A8;
 mmSPI_PS_INPUT_CNTL_24                                   =$A1A9;
 mmSPI_PS_INPUT_CNTL_25                                   =$A1AA;
 mmSPI_PS_INPUT_CNTL_26                                   =$A1AB;
 mmSPI_PS_INPUT_CNTL_27                                   =$A1AC;
 mmSPI_PS_INPUT_CNTL_28                                   =$A1AD;
 mmSPI_PS_INPUT_CNTL_29                                   =$A1AE;
 mmSPI_PS_INPUT_CNTL_30                                   =$A1AF;
 mmSPI_PS_INPUT_CNTL_31                                   =$A1B0;
 mmSPI_VS_OUT_CONFIG                                      =$A1B1;
 mmSPI_PS_INPUT_ENA                                       =$A1B3;
 mmSPI_PS_INPUT_ADDR                                      =$A1B4;
 mmSPI_INTERP_CONTROL_0                                   =$A1B5;
 mmSPI_PS_IN_CONTROL                                      =$A1B6;
 mmSPI_BARYC_CNTL                                         =$A1B8;
 mmSPI_TMPRING_SIZE                                       =$A1BA;
 mmSPI_SHADER_POS_FORMAT                                  =$A1C3;
 mmSPI_SHADER_Z_FORMAT                                    =$A1C4;
 mmSPI_SHADER_COL_FORMAT                                  =$A1C5;
 mmSX_PS_DOWNCONVERT                                      =$A1D5;
 mmSX_BLEND_OPT_EPSILON                                   =$A1D6;
 mmSX_BLEND_OPT_CONTROL                                   =$A1D7;
 mmSX_MRT0_BLEND_OPT                                      =$A1D8;
 mmSX_MRT1_BLEND_OPT                                      =$A1D9;
 mmSX_MRT2_BLEND_OPT                                      =$A1DA;
 mmSX_MRT3_BLEND_OPT                                      =$A1DB;
 mmSX_MRT4_BLEND_OPT                                      =$A1DC;
 mmSX_MRT5_BLEND_OPT                                      =$A1DD;
 mmSX_MRT6_BLEND_OPT                                      =$A1DE;
 mmSX_MRT7_BLEND_OPT                                      =$A1DF;
 mmCB_BLEND0_CONTROL                                      =$A1E0;
 mmCB_BLEND1_CONTROL                                      =$A1E1;
 mmCB_BLEND2_CONTROL                                      =$A1E2;
 mmCB_BLEND3_CONTROL                                      =$A1E3;
 mmCB_BLEND4_CONTROL                                      =$A1E4;
 mmCB_BLEND5_CONTROL                                      =$A1E5;
 mmCB_BLEND6_CONTROL                                      =$A1E6;
 mmCB_BLEND7_CONTROL                                      =$A1E7;
 mmCS_COPY_STATE                                          =$A1F3;
 mmGFX_COPY_STATE                                         =$A1F4;
 mmPA_CL_POINT_X_RAD                                      =$A1F5;
 mmPA_CL_POINT_Y_RAD                                      =$A1F6;
 mmPA_CL_POINT_SIZE                                       =$A1F7;
 mmPA_CL_POINT_CULL_RAD                                   =$A1F8;
 mmVGT_DMA_BASE_HI                                        =$A1F9;
 mmVGT_DMA_BASE                                           =$A1FA;
 mmVGT_DRAW_INITIATOR                                     =$A1FC;
 mmVGT_IMMED_DATA                                         =$A1FD;
 mmVGT_EVENT_ADDRESS_REG                                  =$A1FE;
 mmDB_DEPTH_CONTROL                                       =$A200;
 mmDB_EQAA                                                =$A201;
 mmCB_COLOR_CONTROL                                       =$A202;
 mmDB_SHADER_CONTROL                                      =$A203;
 mmPA_CL_CLIP_CNTL                                        =$A204;
 mmPA_SU_SC_MODE_CNTL                                     =$A205;
 mmPA_CL_VTE_CNTL                                         =$A206;
 mmPA_CL_VS_OUT_CNTL                                      =$A207;
 mmPA_CL_NANINF_CNTL                                      =$A208;
 mmPA_SU_LINE_STIPPLE_CNTL                                =$A209;
 mmPA_SU_LINE_STIPPLE_SCALE                               =$A20A;
 mmPA_SU_PRIM_FILTER_CNTL                                 =$A20B;
 mmPA_SU_POINT_SIZE                                       =$A280;
 mmPA_SU_POINT_MINMAX                                     =$A281;
 mmPA_SU_LINE_CNTL                                        =$A282;
 mmPA_SC_LINE_STIPPLE                                     =$A283;
 mmVGT_OUTPUT_PATH_CNTL                                   =$A284;
 mmVGT_HOS_CNTL                                           =$A285;
 mmVGT_HOS_MAX_TESS_LEVEL                                 =$A286;
 mmVGT_HOS_MIN_TESS_LEVEL                                 =$A287;
 mmVGT_HOS_REUSE_DEPTH                                    =$A288;
 mmVGT_GROUP_PRIM_TYPE                                    =$A289;
 mmVGT_GROUP_FIRST_DECR                                   =$A28A;
 mmVGT_GROUP_DECR                                         =$A28B;
 mmVGT_GROUP_VECT_0_CNTL                                  =$A28C;
 mmVGT_GROUP_VECT_1_CNTL                                  =$A28D;
 mmVGT_GROUP_VECT_0_FMT_CNTL                              =$A28E;
 mmVGT_GROUP_VECT_1_FMT_CNTL                              =$A28F;
 mmVGT_GS_MODE                                            =$A290;
 mmVGT_GS_ONCHIP_CNTL                                     =$A291;
 mmPA_SC_MODE_CNTL_0                                      =$A292;
 mmPA_SC_MODE_CNTL_1                                      =$A293;
 mmVGT_ENHANCE                                            =$A294;
 mmVGT_GS_PER_ES                                          =$A295;
 mmVGT_ES_PER_GS                                          =$A296;
 mmVGT_GS_PER_VS                                          =$A297;
 mmVGT_GSVS_RING_OFFSET_1                                 =$A298;
 mmVGT_GSVS_RING_OFFSET_2                                 =$A299;
 mmVGT_GSVS_RING_OFFSET_3                                 =$A29A;
 mmVGT_GS_OUT_PRIM_TYPE                                   =$A29B;
 mmIA_ENHANCE                                             =$A29C;
 mmVGT_DMA_SIZE                                           =$A29D;
 mmVGT_DMA_MAX_SIZE                                       =$A29E;
 mmVGT_DMA_INDEX_TYPE                                     =$A29F;
 mmWD_ENHANCE                                             =$A2A0;
 mmVGT_PRIMITIVEID_EN                                     =$A2A1;
 mmVGT_DMA_NUM_INSTANCES                                  =$A2A2;
 mmVGT_PRIMITIVEID_RESET                                  =$A2A3;
 mmVGT_EVENT_INITIATOR                                    =$A2A4;
 mmVGT_MULTI_PRIM_IB_RESET_EN                             =$A2A5;
 mmVGT_INSTANCE_STEP_RATE_0                               =$A2A8;
 mmVGT_INSTANCE_STEP_RATE_1                               =$A2A9;
 mmIA_MULTI_VGT_PARAM                                     =$A2AA;
 mmVGT_ESGS_RING_ITEMSIZE                                 =$A2AB;
 mmVGT_GSVS_RING_ITEMSIZE                                 =$A2AC;
 mmVGT_REUSE_OFF                                          =$A2AD;
 mmVGT_VTX_CNT_EN                                         =$A2AE;
 mmDB_HTILE_SURFACE                                       =$A2AF;
 mmDB_SRESULTS_COMPARE_STATE0                             =$A2B0;
 mmDB_SRESULTS_COMPARE_STATE1                             =$A2B1;
 mmDB_PRELOAD_CONTROL                                     =$A2B2;
 mmVGT_STRMOUT_BUFFER_SIZE_0                              =$A2B4;
 mmVGT_STRMOUT_VTX_STRIDE_0                               =$A2B5;
 mmVGT_STRMOUT_BUFFER_OFFSET_0                            =$A2B7;
 mmVGT_STRMOUT_BUFFER_SIZE_1                              =$A2B8;
 mmVGT_STRMOUT_VTX_STRIDE_1                               =$A2B9;
 mmVGT_STRMOUT_BUFFER_OFFSET_1                            =$A2BB;
 mmVGT_STRMOUT_BUFFER_SIZE_2                              =$A2BC;
 mmVGT_STRMOUT_VTX_STRIDE_2                               =$A2BD;
 mmVGT_STRMOUT_BUFFER_OFFSET_2                            =$A2BF;
 mmVGT_STRMOUT_BUFFER_SIZE_3                              =$A2C0;
 mmVGT_STRMOUT_VTX_STRIDE_3                               =$A2C1;
 mmVGT_STRMOUT_BUFFER_OFFSET_3                            =$A2C3;
 mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET                         =$A2CA;
 mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE             =$A2CB;
 mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE                  =$A2CC;
 mmVGT_GS_MAX_VERT_OUT                                    =$A2CE;
 mmVGT_TESS_DISTRIBUTION                                  =$A2D4;
 mmVGT_SHADER_STAGES_EN                                   =$A2D5;
 mmVGT_LS_HS_CONFIG                                       =$A2D6;
 mmVGT_GS_VERT_ITEMSIZE                                   =$A2D7;
 mmVGT_GS_VERT_ITEMSIZE_1                                 =$A2D8;
 mmVGT_GS_VERT_ITEMSIZE_2                                 =$A2D9;
 mmVGT_GS_VERT_ITEMSIZE_3                                 =$A2DA;
 mmVGT_TF_PARAM                                           =$A2DB;
 mmDB_ALPHA_TO_MASK                                       =$A2DC;
 mmVGT_DISPATCH_DRAW_INDEX                                =$A2DD;
 mmPA_SU_POLY_OFFSET_DB_FMT_CNTL                          =$A2DE;
 mmPA_SU_POLY_OFFSET_CLAMP                                =$A2DF;
 mmPA_SU_POLY_OFFSET_FRONT_SCALE                          =$A2E0;
 mmPA_SU_POLY_OFFSET_FRONT_OFFSET                         =$A2E1;
 mmPA_SU_POLY_OFFSET_BACK_SCALE                           =$A2E2;
 mmPA_SU_POLY_OFFSET_BACK_OFFSET                          =$A2E3;
 mmVGT_GS_INSTANCE_CNT                                    =$A2E4;
 mmVGT_STRMOUT_CONFIG                                     =$A2E5;
 mmVGT_STRMOUT_BUFFER_CONFIG                              =$A2E6;
 mmPA_SC_CENTROID_PRIORITY_0                              =$A2F5;
 mmPA_SC_CENTROID_PRIORITY_1                              =$A2F6;
 mmPA_SC_LINE_CNTL                                        =$A2F7;
 mmPA_SC_AA_CONFIG                                        =$A2F8;
 mmPA_SU_VTX_CNTL                                         =$A2F9;
 mmPA_CL_GB_VERT_CLIP_ADJ                                 =$A2FA;
 mmPA_CL_GB_VERT_DISC_ADJ                                 =$A2FB;
 mmPA_CL_GB_HORZ_CLIP_ADJ                                 =$A2FC;
 mmPA_CL_GB_HORZ_DISC_ADJ                                 =$A2FD;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0                      =$A2FE;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1                      =$A2FF;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2                      =$A300;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3                      =$A301;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0                      =$A302;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1                      =$A303;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2                      =$A304;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3                      =$A305;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0                      =$A306;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1                      =$A307;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2                      =$A308;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3                      =$A309;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0                      =$A30A;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1                      =$A30B;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2                      =$A30C;
 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3                      =$A30D;
 mmPA_SC_AA_MASK_X0Y0_X1Y0                                =$A30E;
 mmPA_SC_AA_MASK_X0Y1_X1Y1                                =$A30F;
 mmVGT_VERTEX_REUSE_BLOCK_CNTL                            =$A316;
 mmVGT_OUT_DEALLOC_CNTL                                   =$A317;
 mmCB_COLOR0_BASE                                         =$A318;
 mmCB_COLOR0_PITCH                                        =$A319;
 mmCB_COLOR0_SLICE                                        =$A31A;
 mmCB_COLOR0_VIEW                                         =$A31B;
 mmCB_COLOR0_INFO                                         =$A31C;
 mmCB_COLOR0_ATTRIB                                       =$A31D;
 mmCB_COLOR0_DCC_CONTROL                                  =$A31E;
 mmCB_COLOR0_CMASK                                        =$A31F;
 mmCB_COLOR0_CMASK_SLICE                                  =$A320;
 mmCB_COLOR0_FMASK                                        =$A321;
 mmCB_COLOR0_FMASK_SLICE                                  =$A322;
 mmCB_COLOR0_CLEAR_WORD0                                  =$A323;
 mmCB_COLOR0_CLEAR_WORD1                                  =$A324;
 mmCB_COLOR0_DCC_BASE                                     =$A325;
 mmCB_COLOR1_BASE                                         =$A327;
 mmCB_COLOR1_PITCH                                        =$A328;
 mmCB_COLOR1_SLICE                                        =$A329;
 mmCB_COLOR1_VIEW                                         =$A32A;
 mmCB_COLOR1_INFO                                         =$A32B;
 mmCB_COLOR1_ATTRIB                                       =$A32C;
 mmCB_COLOR1_DCC_CONTROL                                  =$A32D;
 mmCB_COLOR1_CMASK                                        =$A32E;
 mmCB_COLOR1_CMASK_SLICE                                  =$A32F;
 mmCB_COLOR1_FMASK                                        =$A330;
 mmCB_COLOR1_FMASK_SLICE                                  =$A331;
 mmCB_COLOR1_CLEAR_WORD0                                  =$A332;
 mmCB_COLOR1_CLEAR_WORD1                                  =$A333;
 mmCB_COLOR1_DCC_BASE                                     =$A334;
 mmCB_COLOR2_BASE                                         =$A336;
 mmCB_COLOR2_PITCH                                        =$A337;
 mmCB_COLOR2_SLICE                                        =$A338;
 mmCB_COLOR2_VIEW                                         =$A339;
 mmCB_COLOR2_INFO                                         =$A33A;
 mmCB_COLOR2_ATTRIB                                       =$A33B;
 mmCB_COLOR2_DCC_CONTROL                                  =$A33C;
 mmCB_COLOR2_CMASK                                        =$A33D;
 mmCB_COLOR2_CMASK_SLICE                                  =$A33E;
 mmCB_COLOR2_FMASK                                        =$A33F;
 mmCB_COLOR2_FMASK_SLICE                                  =$A340;
 mmCB_COLOR2_CLEAR_WORD0                                  =$A341;
 mmCB_COLOR2_CLEAR_WORD1                                  =$A342;
 mmCB_COLOR2_DCC_BASE                                     =$A343;
 mmCB_COLOR3_BASE                                         =$A345;
 mmCB_COLOR3_PITCH                                        =$A346;
 mmCB_COLOR3_SLICE                                        =$A347;
 mmCB_COLOR3_VIEW                                         =$A348;
 mmCB_COLOR3_INFO                                         =$A349;
 mmCB_COLOR3_ATTRIB                                       =$A34A;
 mmCB_COLOR3_DCC_CONTROL                                  =$A34B;
 mmCB_COLOR3_CMASK                                        =$A34C;
 mmCB_COLOR3_CMASK_SLICE                                  =$A34D;
 mmCB_COLOR3_FMASK                                        =$A34E;
 mmCB_COLOR3_FMASK_SLICE                                  =$A34F;
 mmCB_COLOR3_CLEAR_WORD0                                  =$A350;
 mmCB_COLOR3_CLEAR_WORD1                                  =$A351;
 mmCB_COLOR3_DCC_BASE                                     =$A352;
 mmCB_COLOR4_BASE                                         =$A354;
 mmCB_COLOR4_PITCH                                        =$A355;
 mmCB_COLOR4_SLICE                                        =$A356;
 mmCB_COLOR4_VIEW                                         =$A357;
 mmCB_COLOR4_INFO                                         =$A358;
 mmCB_COLOR4_ATTRIB                                       =$A359;
 mmCB_COLOR4_DCC_CONTROL                                  =$A35A;
 mmCB_COLOR4_CMASK                                        =$A35B;
 mmCB_COLOR4_CMASK_SLICE                                  =$A35C;
 mmCB_COLOR4_FMASK                                        =$A35D;
 mmCB_COLOR4_FMASK_SLICE                                  =$A35E;
 mmCB_COLOR4_CLEAR_WORD0                                  =$A35F;
 mmCB_COLOR4_CLEAR_WORD1                                  =$A360;
 mmCB_COLOR4_DCC_BASE                                     =$A361;
 mmCB_COLOR5_BASE                                         =$A363;
 mmCB_COLOR5_PITCH                                        =$A364;
 mmCB_COLOR5_SLICE                                        =$A365;
 mmCB_COLOR5_VIEW                                         =$A366;
 mmCB_COLOR5_INFO                                         =$A367;
 mmCB_COLOR5_ATTRIB                                       =$A368;
 mmCB_COLOR5_DCC_CONTROL                                  =$A369;
 mmCB_COLOR5_CMASK                                        =$A36A;
 mmCB_COLOR5_CMASK_SLICE                                  =$A36B;
 mmCB_COLOR5_FMASK                                        =$A36C;
 mmCB_COLOR5_FMASK_SLICE                                  =$A36D;
 mmCB_COLOR5_CLEAR_WORD0                                  =$A36E;
 mmCB_COLOR5_CLEAR_WORD1                                  =$A36F;
 mmCB_COLOR5_DCC_BASE                                     =$A370;
 mmCB_COLOR6_BASE                                         =$A372;
 mmCB_COLOR6_PITCH                                        =$A373;
 mmCB_COLOR6_SLICE                                        =$A374;
 mmCB_COLOR6_VIEW                                         =$A375;
 mmCB_COLOR6_INFO                                         =$A376;
 mmCB_COLOR6_ATTRIB                                       =$A377;
 mmCB_COLOR6_DCC_CONTROL                                  =$A378;
 mmCB_COLOR6_CMASK                                        =$A379;
 mmCB_COLOR6_CMASK_SLICE                                  =$A37A;
 mmCB_COLOR6_FMASK                                        =$A37B;
 mmCB_COLOR6_FMASK_SLICE                                  =$A37C;
 mmCB_COLOR6_CLEAR_WORD0                                  =$A37D;
 mmCB_COLOR6_CLEAR_WORD1                                  =$A37E;
 mmCB_COLOR6_DCC_BASE                                     =$A37F;
 mmCB_COLOR7_BASE                                         =$A381;
 mmCB_COLOR7_PITCH                                        =$A382;
 mmCB_COLOR7_SLICE                                        =$A383;
 mmCB_COLOR7_VIEW                                         =$A384;
 mmCB_COLOR7_INFO                                         =$A385;
 mmCB_COLOR7_ATTRIB                                       =$A386;
 mmCB_COLOR7_DCC_CONTROL                                  =$A387;
 mmCB_COLOR7_CMASK                                        =$A388;
 mmCB_COLOR7_CMASK_SLICE                                  =$A389;
 mmCB_COLOR7_FMASK                                        =$A38A;
 mmCB_COLOR7_FMASK_SLICE                                  =$A38B;
 mmCB_COLOR7_CLEAR_WORD0                                  =$A38C;
 mmCB_COLOR7_CLEAR_WORD1                                  =$A38D;
 mmCB_COLOR7_DCC_BASE                                     =$A38E;
 mmCP_EOP_DONE_ADDR_LO                                    =$C000;
 mmCP_EOP_DONE_ADDR_HI                                    =$C001;
 mmCP_EOP_DONE_DATA_LO                                    =$C002;
 mmCP_EOP_DONE_DATA_HI                                    =$C003;
 mmCP_EOP_LAST_FENCE_LO                                   =$C004;
 mmCP_EOP_LAST_FENCE_HI                                   =$C005;
 mmCP_STREAM_OUT_ADDR_LO                                  =$C006;
 mmCP_STREAM_OUT_ADDR_HI                                  =$C007;
 mmCP_NUM_PRIM_WRITTEN_COUNT0_LO                          =$C008;
 mmCP_NUM_PRIM_WRITTEN_COUNT0_HI                          =$C009;
 mmCP_NUM_PRIM_NEEDED_COUNT0_LO                           =$C00A;
 mmCP_NUM_PRIM_NEEDED_COUNT0_HI                           =$C00B;
 mmCP_NUM_PRIM_WRITTEN_COUNT1_LO                          =$C00C;
 mmCP_NUM_PRIM_WRITTEN_COUNT1_HI                          =$C00D;
 mmCP_NUM_PRIM_NEEDED_COUNT1_LO                           =$C00E;
 mmCP_NUM_PRIM_NEEDED_COUNT1_HI                           =$C00F;
 mmCP_NUM_PRIM_WRITTEN_COUNT2_LO                          =$C010;
 mmCP_NUM_PRIM_WRITTEN_COUNT2_HI                          =$C011;
 mmCP_NUM_PRIM_NEEDED_COUNT2_LO                           =$C012;
 mmCP_NUM_PRIM_NEEDED_COUNT2_HI                           =$C013;
 mmCP_NUM_PRIM_WRITTEN_COUNT3_LO                          =$C014;
 mmCP_NUM_PRIM_WRITTEN_COUNT3_HI                          =$C015;
 mmCP_NUM_PRIM_NEEDED_COUNT3_LO                           =$C016;
 mmCP_NUM_PRIM_NEEDED_COUNT3_HI                           =$C017;
 mmCP_PIPE_STATS_ADDR_LO                                  =$C018;
 mmCP_PIPE_STATS_ADDR_HI                                  =$C019;
 mmCP_VGT_IAVERT_COUNT_LO                                 =$C01A;
 mmCP_VGT_IAVERT_COUNT_HI                                 =$C01B;
 mmCP_VGT_IAPRIM_COUNT_LO                                 =$C01C;
 mmCP_VGT_IAPRIM_COUNT_HI                                 =$C01D;
 mmCP_VGT_GSPRIM_COUNT_LO                                 =$C01E;
 mmCP_VGT_GSPRIM_COUNT_HI                                 =$C01F;
 mmCP_VGT_VSINVOC_COUNT_LO                                =$C020;
 mmCP_VGT_VSINVOC_COUNT_HI                                =$C021;
 mmCP_VGT_GSINVOC_COUNT_LO                                =$C022;
 mmCP_VGT_GSINVOC_COUNT_HI                                =$C023;
 mmCP_VGT_HSINVOC_COUNT_LO                                =$C024;
 mmCP_VGT_HSINVOC_COUNT_HI                                =$C025;
 mmCP_VGT_DSINVOC_COUNT_LO                                =$C026;
 mmCP_VGT_DSINVOC_COUNT_HI                                =$C027;
 mmCP_PA_CINVOC_COUNT_LO                                  =$C028;
 mmCP_PA_CINVOC_COUNT_HI                                  =$C029;
 mmCP_PA_CPRIM_COUNT_LO                                   =$C02A;
 mmCP_PA_CPRIM_COUNT_HI                                   =$C02B;
 mmCP_SC_PSINVOC_COUNT0_LO                                =$C02C;
 mmCP_SC_PSINVOC_COUNT0_HI                                =$C02D;
 mmCP_SC_PSINVOC_COUNT1_LO                                =$C02E;
 mmCP_SC_PSINVOC_COUNT1_HI                                =$C02F;
 mmCP_VGT_CSINVOC_COUNT_LO                                =$C030;
 mmCP_VGT_CSINVOC_COUNT_HI                                =$C031;
 mmCP_PIPE_STATS_CONTROL                                  =$C03D;
 mmCP_STREAM_OUT_CONTROL                                  =$C03E;
 mmCP_STRMOUT_CNTL                                        =$C03F;
 mmSCRATCH_REG0                                           =$C040;
 mmSCRATCH_REG1                                           =$C041;
 mmSCRATCH_REG2                                           =$C042;
 mmSCRATCH_REG3                                           =$C043;
 mmSCRATCH_REG4                                           =$C044;
 mmSCRATCH_REG5                                           =$C045;
 mmSCRATCH_REG6                                           =$C046;
 mmSCRATCH_REG7                                           =$C047;
 mmSCRATCH_UMSK                                           =$C050;
 mmSCRATCH_ADDR                                           =$C051;
 mmCP_PFP_ATOMIC_PREOP_LO                                 =$C052;
 mmCP_PFP_ATOMIC_PREOP_HI                                 =$C053;
 mmCP_PFP_GDS_ATOMIC0_PREOP_LO                            =$C054;
 mmCP_PFP_GDS_ATOMIC0_PREOP_HI                            =$C055;
 mmCP_PFP_GDS_ATOMIC1_PREOP_LO                            =$C056;
 mmCP_PFP_GDS_ATOMIC1_PREOP_HI                            =$C057;
 mmCP_APPEND_ADDR_LO                                      =$C058;
 mmCP_APPEND_ADDR_HI                                      =$C059;
 mmCP_APPEND_DATA                                         =$C05A;
 mmCP_APPEND_LAST_CS_FENCE                                =$C05B;
 mmCP_APPEND_LAST_PS_FENCE                                =$C05C;
 mmCP_ATOMIC_PREOP_LO                                     =$C05D;
 mmCP_ATOMIC_PREOP_HI                                     =$C05E;
 mmCP_GDS_ATOMIC0_PREOP_LO                                =$C05F;
 mmCP_GDS_ATOMIC0_PREOP_HI                                =$C060;
 mmCP_GDS_ATOMIC1_PREOP_LO                                =$C061;
 mmCP_GDS_ATOMIC1_PREOP_HI                                =$C062;
 mmCP_ME_MC_WADDR_LO                                      =$C069;
 mmCP_ME_MC_WADDR_HI                                      =$C06A;
 mmCP_ME_MC_WDATA_LO                                      =$C06B;
 mmCP_ME_MC_WDATA_HI                                      =$C06C;
 mmCP_ME_MC_RADDR_LO                                      =$C06D;
 mmCP_ME_MC_RADDR_HI                                      =$C06E;
 mmCP_SEM_WAIT_TIMER                                      =$C06F;
 mmCP_SIG_SEM_ADDR_LO                                     =$C070;
 mmCP_SIG_SEM_ADDR_HI                                     =$C071;
 mmCP_WAIT_REG_MEM_TIMEOUT                                =$C074;
 mmCP_WAIT_SEM_ADDR_LO                                    =$C075;
 mmCP_WAIT_SEM_ADDR_HI                                    =$C076;
 mmCP_DMA_PFP_CONTROL                                     =$C077;
 mmCP_DMA_ME_CONTROL                                      =$C078;
 mmCP_COHER_BASE_HI                                       =$C079;
 mmCP_COHER_START_DELAY                                   =$C07B;
 mmCP_COHER_CNTL                                          =$C07C;
 mmCP_COHER_SIZE                                          =$C07D;
 mmCP_COHER_BASE                                          =$C07E;
 mmCP_COHER_STATUS                                        =$C07F;
 mmCP_DMA_ME_SRC_ADDR                                     =$C080;
 mmCP_DMA_ME_SRC_ADDR_HI                                  =$C081;
 mmCP_DMA_ME_DST_ADDR                                     =$C082;
 mmCP_DMA_ME_DST_ADDR_HI                                  =$C083;
 mmCP_DMA_ME_COMMAND                                      =$C084;
 mmCP_DMA_PFP_SRC_ADDR                                    =$C085;
 mmCP_DMA_PFP_SRC_ADDR_HI                                 =$C086;
 mmCP_DMA_PFP_DST_ADDR                                    =$C087;
 mmCP_DMA_PFP_DST_ADDR_HI                                 =$C088;
 mmCP_DMA_PFP_COMMAND                                     =$C089;
 mmCP_DMA_CNTL                                            =$C08A;
 mmCP_DMA_READ_TAGS                                       =$C08B;
 mmCP_COHER_SIZE_HI                                       =$C08C;
 mmCP_PFP_IB_CONTROL                                      =$C08D;
 mmCP_PFP_LOAD_CONTROL                                    =$C08E;
 mmCP_SCRATCH_INDEX                                       =$C08F;
 mmCP_SCRATCH_DATA                                        =$C090;
 mmCP_RB_OFFSET                                           =$C091;
 mmCP_IB1_OFFSET                                          =$C092;
 mmCP_IB2_OFFSET                                          =$C093;
 mmCP_IB1_PREAMBLE_BEGIN                                  =$C094;
 mmCP_IB1_PREAMBLE_END                                    =$C095;
 mmCP_IB2_PREAMBLE_BEGIN                                  =$C096;
 mmCP_IB2_PREAMBLE_END                                    =$C097;
 mmCP_CE_IB1_OFFSET                                       =$C098;
 mmCP_CE_IB2_OFFSET                                       =$C099;
 mmCP_CE_COUNTER                                          =$C09A;
 mmCP_CE_RB_OFFSET                                        =$C09B;
 mmCP_CE_INIT_BASE_LO                                     =$C0C3;
 mmCP_CE_INIT_BASE_HI                                     =$C0C4;
 mmCP_CE_INIT_BUFSZ                                       =$C0C5;
 mmCP_CE_IB1_BASE_LO                                      =$C0C6;
 mmCP_CE_IB1_BASE_HI                                      =$C0C7;
 mmCP_CE_IB1_BUFSZ                                        =$C0C8;
 mmCP_CE_IB2_BASE_LO                                      =$C0C9;
 mmCP_CE_IB2_BASE_HI                                      =$C0CA;
 mmCP_CE_IB2_BUFSZ                                        =$C0CB;
 mmCP_IB1_BASE_LO                                         =$C0CC;
 mmCP_IB1_BASE_HI                                         =$C0CD;
 mmCP_IB1_BUFSZ                                           =$C0CE;
 mmCP_IB2_BASE_LO                                         =$C0CF;
 mmCP_IB2_BASE_HI                                         =$C0D0;
 mmCP_IB2_BUFSZ                                           =$C0D1;
 mmCP_ST_BASE_LO                                          =$C0D2;
 mmCP_ST_BASE_HI                                          =$C0D3;
 mmCP_ST_BUFSZ                                            =$C0D4;
 mmCP_EOP_DONE_EVENT_CNTL                                 =$C0D5;
 mmCP_EOP_DONE_DATA_CNTL                                  =$C0D6;
 mmCP_EOP_DONE_CNTX_ID                                    =$C0D7;
 mmCP_PFP_COMPLETION_STATUS                               =$C0EC;
 mmCP_CE_COMPLETION_STATUS                                =$C0ED;
 mmCP_PRED_NOT_VISIBLE                                    =$C0EE;
 mmCP_PFP_METADATA_BASE_ADDR                              =$C0F0;
 mmCP_PFP_METADATA_BASE_ADDR_HI                           =$C0F1;
 mmCP_CE_METADATA_BASE_ADDR                               =$C0F2;
 mmCP_CE_METADATA_BASE_ADDR_HI                            =$C0F3;
 mmCP_DRAW_INDX_INDR_ADDR                                 =$C0F4;
 mmCP_DRAW_INDX_INDR_ADDR_HI                              =$C0F5;
 mmCP_DISPATCH_INDR_ADDR                                  =$C0F6;
 mmCP_DISPATCH_INDR_ADDR_HI                               =$C0F7;
 mmCP_INDEX_BASE_ADDR                                     =$C0F8;
 mmCP_INDEX_BASE_ADDR_HI                                  =$C0F9;
 mmCP_INDEX_TYPE                                          =$C0FA;
 mmCP_GDS_BKUP_ADDR                                       =$C0FB;
 mmCP_GDS_BKUP_ADDR_HI                                    =$C0FC;
 mmCP_SAMPLE_STATUS                                       =$C0FD;
 mmGRBM_GFX_INDEX                                         =$C200;
 mmVGT_ESGS_RING_SIZE                                     =$C240;
 mmVGT_GSVS_RING_SIZE                                     =$C241;
 mmVGT_PRIMITIVE_TYPE                                     =$C242;
 mmVGT_INDEX_TYPE                                         =$C243;
 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0                       =$C244;
 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1                       =$C245;
 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2                       =$C246;
 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3                       =$C247;
 mmVGT_NUM_INDICES                                        =$C24C;
 mmVGT_NUM_INSTANCES                                      =$C24D;
 mmVGT_TF_RING_SIZE                                       =$C24E;
 mmVGT_HS_OFFCHIP_PARAM                                   =$C24F;
 mmVGT_TF_MEMORY_BASE                                     =$C250;
 mmPA_SU_LINE_STIPPLE_VALUE                               =$C280;
 mmPA_SC_LINE_STIPPLE_STATE                               =$C281;
 mmPA_SC_P3D_TRAP_SCREEN_HV_EN                            =$C2A0;
 mmPA_SC_P3D_TRAP_SCREEN_H                                =$C2A1;
 mmPA_SC_P3D_TRAP_SCREEN_V                                =$C2A2;
 mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE                       =$C2A3;
 mmPA_SC_P3D_TRAP_SCREEN_COUNT                            =$C2A4;
 mmPA_SC_HP3D_TRAP_SCREEN_HV_EN                           =$C2A8;
 mmPA_SC_HP3D_TRAP_SCREEN_H                               =$C2A9;
 mmPA_SC_HP3D_TRAP_SCREEN_V                               =$C2AA;
 mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE                      =$C2AB;
 mmPA_SC_HP3D_TRAP_SCREEN_COUNT                           =$C2AC;
 mmPA_SC_TRAP_SCREEN_HV_EN                                =$C2B0;
 mmPA_SC_TRAP_SCREEN_H                                    =$C2B1;
 mmPA_SC_TRAP_SCREEN_V                                    =$C2B2;
 mmPA_SC_TRAP_SCREEN_OCCURRENCE                           =$C2B3;
 mmPA_SC_TRAP_SCREEN_COUNT                                =$C2B4;
 mmSQ_THREAD_TRACE_BASE                                   =$C330;
 mmSQ_THREAD_TRACE_SIZE                                   =$C331;
 mmSQ_THREAD_TRACE_MASK                                   =$C332;
 mmSQ_THREAD_TRACE_TOKEN_MASK                             =$C333;
 mmSQ_THREAD_TRACE_PERF_MASK                              =$C334;
 mmSQ_THREAD_TRACE_CTRL                                   =$C335;
 mmSQ_THREAD_TRACE_MODE                                   =$C336;
 mmSQ_THREAD_TRACE_BASE2                                  =$C337;
 mmSQ_THREAD_TRACE_TOKEN_MASK2                            =$C338;
 mmSQ_THREAD_TRACE_WPTR                                   =$C339;
 mmSQ_THREAD_TRACE_STATUS                                 =$C33A;
 mmSQ_THREAD_TRACE_HIWATER                                =$C33B;
 mmSQ_THREAD_TRACE_USERDATA_0                             =$C340;
 mmSQ_THREAD_TRACE_USERDATA_1                             =$C341;
 mmSQ_THREAD_TRACE_USERDATA_2                             =$C342;
 mmSQ_THREAD_TRACE_USERDATA_3                             =$C343;
 mmSQC_CACHES                                             =$C348;
 mmSQC_WRITEBACK                                          =$C349;
 mmTA_CS_BC_BASE_ADDR                                     =$C380;
 mmTA_CS_BC_BASE_ADDR_HI                                  =$C381;
 mmDB_OCCLUSION_COUNT0_LOW                                =$C3C0;
 mmDB_OCCLUSION_COUNT0_HI                                 =$C3C1;
 mmDB_OCCLUSION_COUNT1_LOW                                =$C3C2;
 mmDB_OCCLUSION_COUNT1_HI                                 =$C3C3;
 mmDB_OCCLUSION_COUNT2_LOW                                =$C3C4;
 mmDB_OCCLUSION_COUNT2_HI                                 =$C3C5;
 mmDB_OCCLUSION_COUNT3_LOW                                =$C3C6;
 mmDB_OCCLUSION_COUNT3_HI                                 =$C3C7;
 mmDB_ZPASS_COUNT_LOW                                     =$C3FE;
 mmDB_ZPASS_COUNT_HI                                      =$C3FF;
 mmGDS_RD_ADDR                                            =$C400;
 mmGDS_RD_DATA                                            =$C401;
 mmGDS_RD_BURST_ADDR                                      =$C402;
 mmGDS_RD_BURST_COUNT                                     =$C403;
 mmGDS_RD_BURST_DATA                                      =$C404;
 mmGDS_WR_ADDR                                            =$C405;
 mmGDS_WR_DATA                                            =$C406;
 mmGDS_WR_BURST_ADDR                                      =$C407;
 mmGDS_WR_BURST_DATA                                      =$C408;
 mmGDS_WRITE_COMPLETE                                     =$C409;
 mmGDS_ATOM_CNTL                                          =$C40A;
 mmGDS_ATOM_COMPLETE                                      =$C40B;
 mmGDS_ATOM_BASE                                          =$C40C;
 mmGDS_ATOM_SIZE                                          =$C40D;
 mmGDS_ATOM_OFFSET0                                       =$C40E;
 mmGDS_ATOM_OFFSET1                                       =$C40F;
 mmGDS_ATOM_DST                                           =$C410;
 mmGDS_ATOM_OP                                            =$C411;
 mmGDS_ATOM_SRC0                                          =$C412;
 mmGDS_ATOM_SRC0_U                                        =$C413;
 mmGDS_ATOM_SRC1                                          =$C414;
 mmGDS_ATOM_SRC1_U                                        =$C415;
 mmGDS_ATOM_READ0                                         =$C416;
 mmGDS_ATOM_READ0_U                                       =$C417;
 mmGDS_ATOM_READ1                                         =$C418;
 mmGDS_ATOM_READ1_U                                       =$C419;
 mmGDS_GWS_RESOURCE_CNTL                                  =$C41A;
 mmGDS_GWS_RESOURCE                                       =$C41B;
 mmGDS_GWS_RESOURCE_CNT                                   =$C41C;
 mmGDS_OA_CNTL                                            =$C41D;
 mmGDS_OA_COUNTER                                         =$C41E;
 mmGDS_OA_ADDRESS                                         =$C41F;
 mmGDS_OA_INCDEC                                          =$C420;
 mmGDS_OA_RING_SIZE                                       =$C421;
 mmCPG_PERFCOUNTER1_LO                                    =$D000;
 mmCPG_PERFCOUNTER1_HI                                    =$D001;
 mmCPG_PERFCOUNTER0_LO                                    =$D002;
 mmCPG_PERFCOUNTER0_HI                                    =$D003;
 mmCPC_PERFCOUNTER1_LO                                    =$D004;
 mmCPC_PERFCOUNTER1_HI                                    =$D005;
 mmCPC_PERFCOUNTER0_LO                                    =$D006;
 mmCPC_PERFCOUNTER0_HI                                    =$D007;
 mmCPF_PERFCOUNTER1_LO                                    =$D008;
 mmCPF_PERFCOUNTER1_HI                                    =$D009;
 mmCPF_PERFCOUNTER0_LO                                    =$D00A;
 mmCPF_PERFCOUNTER0_HI                                    =$D00B;
 mmGRBM_PERFCOUNTER0_LO                                   =$D040;
 mmGRBM_PERFCOUNTER0_HI                                   =$D041;
 mmGRBM_PERFCOUNTER1_LO                                   =$D043;
 mmGRBM_PERFCOUNTER1_HI                                   =$D044;
 mmGRBM_SE0_PERFCOUNTER_LO                                =$D045;
 mmGRBM_SE0_PERFCOUNTER_HI                                =$D046;
 mmGRBM_SE1_PERFCOUNTER_LO                                =$D047;
 mmGRBM_SE1_PERFCOUNTER_HI                                =$D048;
 mmGRBM_SE2_PERFCOUNTER_LO                                =$D049;
 mmGRBM_SE2_PERFCOUNTER_HI                                =$D04A;
 mmGRBM_SE3_PERFCOUNTER_LO                                =$D04B;
 mmGRBM_SE3_PERFCOUNTER_HI                                =$D04C;
 mmWD_PERFCOUNTER0_LO                                     =$D080;
 mmWD_PERFCOUNTER0_HI                                     =$D081;
 mmWD_PERFCOUNTER1_LO                                     =$D082;
 mmWD_PERFCOUNTER1_HI                                     =$D083;
 mmWD_PERFCOUNTER2_LO                                     =$D084;
 mmWD_PERFCOUNTER2_HI                                     =$D085;
 mmWD_PERFCOUNTER3_LO                                     =$D086;
 mmWD_PERFCOUNTER3_HI                                     =$D087;
 mmIA_PERFCOUNTER0_LO                                     =$D088;
 mmIA_PERFCOUNTER0_HI                                     =$D089;
 mmIA_PERFCOUNTER1_LO                                     =$D08A;
 mmIA_PERFCOUNTER1_HI                                     =$D08B;
 mmIA_PERFCOUNTER2_LO                                     =$D08C;
 mmIA_PERFCOUNTER2_HI                                     =$D08D;
 mmIA_PERFCOUNTER3_LO                                     =$D08E;
 mmIA_PERFCOUNTER3_HI                                     =$D08F;
 mmVGT_PERFCOUNTER0_LO                                    =$D090;
 mmVGT_PERFCOUNTER0_HI                                    =$D091;
 mmVGT_PERFCOUNTER1_LO                                    =$D092;
 mmVGT_PERFCOUNTER1_HI                                    =$D093;
 mmVGT_PERFCOUNTER2_LO                                    =$D094;
 mmVGT_PERFCOUNTER2_HI                                    =$D095;
 mmVGT_PERFCOUNTER3_LO                                    =$D096;
 mmVGT_PERFCOUNTER3_HI                                    =$D097;
 mmPA_SU_PERFCOUNTER0_LO                                  =$D100;
 mmPA_SU_PERFCOUNTER0_HI                                  =$D101;
 mmPA_SU_PERFCOUNTER1_LO                                  =$D102;
 mmPA_SU_PERFCOUNTER1_HI                                  =$D103;
 mmPA_SU_PERFCOUNTER2_LO                                  =$D104;
 mmPA_SU_PERFCOUNTER2_HI                                  =$D105;
 mmPA_SU_PERFCOUNTER3_LO                                  =$D106;
 mmPA_SU_PERFCOUNTER3_HI                                  =$D107;
 mmPA_SC_PERFCOUNTER0_LO                                  =$D140;
 mmPA_SC_PERFCOUNTER0_HI                                  =$D141;
 mmPA_SC_PERFCOUNTER1_LO                                  =$D142;
 mmPA_SC_PERFCOUNTER1_HI                                  =$D143;
 mmPA_SC_PERFCOUNTER2_LO                                  =$D144;
 mmPA_SC_PERFCOUNTER2_HI                                  =$D145;
 mmPA_SC_PERFCOUNTER3_LO                                  =$D146;
 mmPA_SC_PERFCOUNTER3_HI                                  =$D147;
 mmPA_SC_PERFCOUNTER4_LO                                  =$D148;
 mmPA_SC_PERFCOUNTER4_HI                                  =$D149;
 mmPA_SC_PERFCOUNTER5_LO                                  =$D14A;
 mmPA_SC_PERFCOUNTER5_HI                                  =$D14B;
 mmPA_SC_PERFCOUNTER6_LO                                  =$D14C;
 mmPA_SC_PERFCOUNTER6_HI                                  =$D14D;
 mmPA_SC_PERFCOUNTER7_LO                                  =$D14E;
 mmPA_SC_PERFCOUNTER7_HI                                  =$D14F;
 mmSPI_PERFCOUNTER0_HI                                    =$D180;
 mmSPI_PERFCOUNTER0_LO                                    =$D181;
 mmSPI_PERFCOUNTER1_HI                                    =$D182;
 mmSPI_PERFCOUNTER1_LO                                    =$D183;
 mmSPI_PERFCOUNTER2_HI                                    =$D184;
 mmSPI_PERFCOUNTER2_LO                                    =$D185;
 mmSPI_PERFCOUNTER3_HI                                    =$D186;
 mmSPI_PERFCOUNTER3_LO                                    =$D187;
 mmSPI_PERFCOUNTER4_HI                                    =$D188;
 mmSPI_PERFCOUNTER4_LO                                    =$D189;
 mmSPI_PERFCOUNTER5_HI                                    =$D18A;
 mmSPI_PERFCOUNTER5_LO                                    =$D18B;
 mmSQ_PERFCOUNTER0_LO                                     =$D1C0;
 mmSQ_PERFCOUNTER0_HI                                     =$D1C1;
 mmSQ_PERFCOUNTER1_LO                                     =$D1C2;
 mmSQ_PERFCOUNTER1_HI                                     =$D1C3;
 mmSQ_PERFCOUNTER2_LO                                     =$D1C4;
 mmSQ_PERFCOUNTER2_HI                                     =$D1C5;
 mmSQ_PERFCOUNTER3_LO                                     =$D1C6;
 mmSQ_PERFCOUNTER3_HI                                     =$D1C7;
 mmSQ_PERFCOUNTER4_LO                                     =$D1C8;
 mmSQ_PERFCOUNTER4_HI                                     =$D1C9;
 mmSQ_PERFCOUNTER5_LO                                     =$D1CA;
 mmSQ_PERFCOUNTER5_HI                                     =$D1CB;
 mmSQ_PERFCOUNTER6_LO                                     =$D1CC;
 mmSQ_PERFCOUNTER6_HI                                     =$D1CD;
 mmSQ_PERFCOUNTER7_LO                                     =$D1CE;
 mmSQ_PERFCOUNTER7_HI                                     =$D1CF;
 mmSQ_PERFCOUNTER8_LO                                     =$D1D0;
 mmSQ_PERFCOUNTER8_HI                                     =$D1D1;
 mmSQ_PERFCOUNTER9_LO                                     =$D1D2;
 mmSQ_PERFCOUNTER9_HI                                     =$D1D3;
 mmSQ_PERFCOUNTER10_LO                                    =$D1D4;
 mmSQ_PERFCOUNTER10_HI                                    =$D1D5;
 mmSQ_PERFCOUNTER11_LO                                    =$D1D6;
 mmSQ_PERFCOUNTER11_HI                                    =$D1D7;
 mmSQ_PERFCOUNTER12_LO                                    =$D1D8;
 mmSQ_PERFCOUNTER12_HI                                    =$D1D9;
 mmSQ_PERFCOUNTER13_LO                                    =$D1DA;
 mmSQ_PERFCOUNTER13_HI                                    =$D1DB;
 mmSQ_PERFCOUNTER14_LO                                    =$D1DC;
 mmSQ_PERFCOUNTER14_HI                                    =$D1DD;
 mmSQ_PERFCOUNTER15_LO                                    =$D1DE;
 mmSQ_PERFCOUNTER15_HI                                    =$D1DF;
 mmSX_PERFCOUNTER0_LO                                     =$D240;
 mmSX_PERFCOUNTER0_HI                                     =$D241;
 mmSX_PERFCOUNTER1_LO                                     =$D242;
 mmSX_PERFCOUNTER1_HI                                     =$D243;
 mmSX_PERFCOUNTER2_LO                                     =$D244;
 mmSX_PERFCOUNTER2_HI                                     =$D245;
 mmSX_PERFCOUNTER3_LO                                     =$D246;
 mmSX_PERFCOUNTER3_HI                                     =$D247;
 mmGDS_PERFCOUNTER0_LO                                    =$D280;
 mmGDS_PERFCOUNTER0_HI                                    =$D281;
 mmGDS_PERFCOUNTER1_LO                                    =$D282;
 mmGDS_PERFCOUNTER1_HI                                    =$D283;
 mmGDS_PERFCOUNTER2_LO                                    =$D284;
 mmGDS_PERFCOUNTER2_HI                                    =$D285;
 mmGDS_PERFCOUNTER3_LO                                    =$D286;
 mmGDS_PERFCOUNTER3_HI                                    =$D287;
 mmTA_PERFCOUNTER0_LO                                     =$D2C0;
 mmTA_PERFCOUNTER0_HI                                     =$D2C1;
 mmTA_PERFCOUNTER1_LO                                     =$D2C2;
 mmTA_PERFCOUNTER1_HI                                     =$D2C3;
 mmTD_PERFCOUNTER0_LO                                     =$D300;
 mmTD_PERFCOUNTER0_HI                                     =$D301;
 mmTD_PERFCOUNTER1_LO                                     =$D302;
 mmTD_PERFCOUNTER1_HI                                     =$D303;
 mmTCP_PERFCOUNTER0_LO                                    =$D340;
 mmTCP_PERFCOUNTER0_HI                                    =$D341;
 mmTCP_PERFCOUNTER1_LO                                    =$D342;
 mmTCP_PERFCOUNTER1_HI                                    =$D343;
 mmTCP_PERFCOUNTER2_LO                                    =$D344;
 mmTCP_PERFCOUNTER2_HI                                    =$D345;
 mmTCP_PERFCOUNTER3_LO                                    =$D346;
 mmTCP_PERFCOUNTER3_HI                                    =$D347;
 mmTCC_PERFCOUNTER0_LO                                    =$D380;
 mmTCC_PERFCOUNTER0_HI                                    =$D381;
 mmTCC_PERFCOUNTER1_LO                                    =$D382;
 mmTCC_PERFCOUNTER1_HI                                    =$D383;
 mmTCC_PERFCOUNTER2_LO                                    =$D384;
 mmTCC_PERFCOUNTER2_HI                                    =$D385;
 mmTCC_PERFCOUNTER3_LO                                    =$D386;
 mmTCC_PERFCOUNTER3_HI                                    =$D387;
 mmTCA_PERFCOUNTER0_LO                                    =$D390;
 mmTCA_PERFCOUNTER0_HI                                    =$D391;
 mmTCA_PERFCOUNTER1_LO                                    =$D392;
 mmTCA_PERFCOUNTER1_HI                                    =$D393;
 mmTCA_PERFCOUNTER2_LO                                    =$D394;
 mmTCA_PERFCOUNTER2_HI                                    =$D395;
 mmTCA_PERFCOUNTER3_LO                                    =$D396;
 mmTCA_PERFCOUNTER3_HI                                    =$D397;
 mmCB_PERFCOUNTER0_LO                                     =$D406;
 mmCB_PERFCOUNTER0_HI                                     =$D407;
 mmCB_PERFCOUNTER1_LO                                     =$D408;
 mmCB_PERFCOUNTER1_HI                                     =$D409;
 mmCB_PERFCOUNTER2_LO                                     =$D40A;
 mmCB_PERFCOUNTER2_HI                                     =$D40B;
 mmCB_PERFCOUNTER3_LO                                     =$D40C;
 mmCB_PERFCOUNTER3_HI                                     =$D40D;
 mmDB_PERFCOUNTER0_LO                                     =$D440;
 mmDB_PERFCOUNTER0_HI                                     =$D441;
 mmDB_PERFCOUNTER1_LO                                     =$D442;
 mmDB_PERFCOUNTER1_HI                                     =$D443;
 mmDB_PERFCOUNTER2_LO                                     =$D444;
 mmDB_PERFCOUNTER2_HI                                     =$D445;
 mmDB_PERFCOUNTER3_LO                                     =$D446;
 mmDB_PERFCOUNTER3_HI                                     =$D447;
 mmRLC_PERFCOUNTER0_LO                                    =$D480;
 mmRLC_PERFCOUNTER0_HI                                    =$D481;
 mmRLC_PERFCOUNTER1_LO                                    =$D482;
 mmRLC_PERFCOUNTER1_HI                                    =$D483;
 mmCPG_PERFCOUNTER1_SELECT                                =$D800;
 mmCPG_PERFCOUNTER0_SELECT1                               =$D801;
 mmCPG_PERFCOUNTER0_SELECT                                =$D802;
 mmCPC_PERFCOUNTER1_SELECT                                =$D803;
 mmCPC_PERFCOUNTER0_SELECT1                               =$D804;
 mmCPF_PERFCOUNTER1_SELECT                                =$D805;
 mmCPF_PERFCOUNTER0_SELECT1                               =$D806;
 mmCPF_PERFCOUNTER0_SELECT                                =$D807;
 mmCP_PERFMON_CNTL                                        =$D808;
 mmCPC_PERFCOUNTER0_SELECT                                =$D809;
 mmCP_DRAW_OBJECT                                         =$D810;
 mmCP_DRAW_OBJECT_COUNTER                                 =$D811;
 mmCP_DRAW_WINDOW_MASK_HI                                 =$D812;
 mmCP_DRAW_WINDOW_HI                                      =$D813;
 mmCP_DRAW_WINDOW_LO                                      =$D814;
 mmCP_DRAW_WINDOW_CNTL                                    =$D815;
 mmGRBM_PERFCOUNTER0_SELECT                               =$D840;
 mmGRBM_PERFCOUNTER1_SELECT                               =$D841;
 mmGRBM_SE0_PERFCOUNTER_SELECT                            =$D842;
 mmGRBM_SE1_PERFCOUNTER_SELECT                            =$D843;
 mmGRBM_SE2_PERFCOUNTER_SELECT                            =$D844;
 mmGRBM_SE3_PERFCOUNTER_SELECT                            =$D845;
 mmWD_PERFCOUNTER0_SELECT                                 =$D880;
 mmWD_PERFCOUNTER1_SELECT                                 =$D881;
 mmWD_PERFCOUNTER2_SELECT                                 =$D882;
 mmWD_PERFCOUNTER3_SELECT                                 =$D883;
 mmIA_PERFCOUNTER0_SELECT                                 =$D884;
 mmIA_PERFCOUNTER1_SELECT                                 =$D885;
 mmIA_PERFCOUNTER2_SELECT                                 =$D886;
 mmIA_PERFCOUNTER3_SELECT                                 =$D887;
 mmIA_PERFCOUNTER0_SELECT1                                =$D888;
 mmVGT_PERFCOUNTER0_SELECT                                =$D88C;
 mmVGT_PERFCOUNTER1_SELECT                                =$D88D;
 mmVGT_PERFCOUNTER2_SELECT                                =$D88E;
 mmVGT_PERFCOUNTER3_SELECT                                =$D88F;
 mmVGT_PERFCOUNTER0_SELECT1                               =$D890;
 mmVGT_PERFCOUNTER1_SELECT1                               =$D891;
 mmVGT_PERFCOUNTER_SEID_MASK                              =$D894;
 mmPA_SU_PERFCOUNTER0_SELECT                              =$D900;
 mmPA_SU_PERFCOUNTER0_SELECT1                             =$D901;
 mmPA_SU_PERFCOUNTER1_SELECT                              =$D902;
 mmPA_SU_PERFCOUNTER1_SELECT1                             =$D903;
 mmPA_SU_PERFCOUNTER2_SELECT                              =$D904;
 mmPA_SU_PERFCOUNTER3_SELECT                              =$D905;
 mmPA_SC_PERFCOUNTER0_SELECT                              =$D940;
 mmPA_SC_PERFCOUNTER0_SELECT1                             =$D941;
 mmPA_SC_PERFCOUNTER1_SELECT                              =$D942;
 mmPA_SC_PERFCOUNTER2_SELECT                              =$D943;
 mmPA_SC_PERFCOUNTER3_SELECT                              =$D944;
 mmPA_SC_PERFCOUNTER4_SELECT                              =$D945;
 mmPA_SC_PERFCOUNTER5_SELECT                              =$D946;
 mmPA_SC_PERFCOUNTER6_SELECT                              =$D947;
 mmPA_SC_PERFCOUNTER7_SELECT                              =$D948;
 mmSPI_PERFCOUNTER0_SELECT                                =$D980;
 mmSPI_PERFCOUNTER1_SELECT                                =$D981;
 mmSPI_PERFCOUNTER2_SELECT                                =$D982;
 mmSPI_PERFCOUNTER3_SELECT                                =$D983;
 mmSPI_PERFCOUNTER0_SELECT1                               =$D984;
 mmSPI_PERFCOUNTER1_SELECT1                               =$D985;
 mmSPI_PERFCOUNTER2_SELECT1                               =$D986;
 mmSPI_PERFCOUNTER3_SELECT1                               =$D987;
 mmSPI_PERFCOUNTER4_SELECT                                =$D988;
 mmSPI_PERFCOUNTER5_SELECT                                =$D989;
 mmSPI_PERFCOUNTER_BINS                                   =$D98A;
 mmSQ_PERFCOUNTER0_SELECT                                 =$D9C0;
 mmSQ_PERFCOUNTER1_SELECT                                 =$D9C1;
 mmSQ_PERFCOUNTER2_SELECT                                 =$D9C2;
 mmSQ_PERFCOUNTER3_SELECT                                 =$D9C3;
 mmSQ_PERFCOUNTER4_SELECT                                 =$D9C4;
 mmSQ_PERFCOUNTER5_SELECT                                 =$D9C5;
 mmSQ_PERFCOUNTER6_SELECT                                 =$D9C6;
 mmSQ_PERFCOUNTER7_SELECT                                 =$D9C7;
 mmSQ_PERFCOUNTER8_SELECT                                 =$D9C8;
 mmSQ_PERFCOUNTER9_SELECT                                 =$D9C9;
 mmSQ_PERFCOUNTER10_SELECT                                =$D9CA;
 mmSQ_PERFCOUNTER11_SELECT                                =$D9CB;
 mmSQ_PERFCOUNTER12_SELECT                                =$D9CC;
 mmSQ_PERFCOUNTER13_SELECT                                =$D9CD;
 mmSQ_PERFCOUNTER14_SELECT                                =$D9CE;
 mmSQ_PERFCOUNTER15_SELECT                                =$D9CF;
 mmSQ_PERFCOUNTER_CTRL                                    =$D9E0;
 mmSQ_PERFCOUNTER_MASK                                    =$D9E1;
 mmSQ_PERFCOUNTER_CTRL2                                   =$D9E2;
 mmSX_PERFCOUNTER0_SELECT                                 =$DA40;
 mmSX_PERFCOUNTER1_SELECT                                 =$DA41;
 mmSX_PERFCOUNTER2_SELECT                                 =$DA42;
 mmSX_PERFCOUNTER3_SELECT                                 =$DA43;
 mmSX_PERFCOUNTER0_SELECT1                                =$DA44;
 mmSX_PERFCOUNTER1_SELECT1                                =$DA45;
 mmGDS_PERFCOUNTER0_SELECT                                =$DA80;
 mmGDS_PERFCOUNTER1_SELECT                                =$DA81;
 mmGDS_PERFCOUNTER2_SELECT                                =$DA82;
 mmGDS_PERFCOUNTER3_SELECT                                =$DA83;
 mmGDS_PERFCOUNTER0_SELECT1                               =$DA84;
 mmTA_PERFCOUNTER0_SELECT                                 =$DAC0;
 mmTA_PERFCOUNTER0_SELECT1                                =$DAC1;
 mmTA_PERFCOUNTER1_SELECT                                 =$DAC2;
 mmTD_PERFCOUNTER0_SELECT                                 =$DB00;
 mmTD_PERFCOUNTER0_SELECT1                                =$DB01;
 mmTD_PERFCOUNTER1_SELECT                                 =$DB02;
 mmTCP_PERFCOUNTER0_SELECT                                =$DB40;
 mmTCP_PERFCOUNTER0_SELECT1                               =$DB41;
 mmTCP_PERFCOUNTER1_SELECT                                =$DB42;
 mmTCP_PERFCOUNTER1_SELECT1                               =$DB43;
 mmTCP_PERFCOUNTER2_SELECT                                =$DB44;
 mmTCP_PERFCOUNTER3_SELECT                                =$DB45;
 mmTCC_PERFCOUNTER0_SELECT                                =$DB80;
 mmTCC_PERFCOUNTER0_SELECT1                               =$DB81;
 mmTCC_PERFCOUNTER1_SELECT                                =$DB82;
 mmTCC_PERFCOUNTER1_SELECT1                               =$DB83;
 mmTCC_PERFCOUNTER2_SELECT                                =$DB84;
 mmTCC_PERFCOUNTER3_SELECT                                =$DB85;
 mmTCA_PERFCOUNTER0_SELECT                                =$DB90;
 mmTCA_PERFCOUNTER0_SELECT1                               =$DB91;
 mmTCA_PERFCOUNTER1_SELECT                                =$DB92;
 mmTCA_PERFCOUNTER1_SELECT1                               =$DB93;
 mmTCA_PERFCOUNTER2_SELECT                                =$DB94;
 mmTCA_PERFCOUNTER3_SELECT                                =$DB95;
 mmCB_PERFCOUNTER_FILTER                                  =$DC00;
 mmCB_PERFCOUNTER0_SELECT                                 =$DC01;
 mmCB_PERFCOUNTER0_SELECT1                                =$DC02;
 mmCB_PERFCOUNTER1_SELECT                                 =$DC03;
 mmCB_PERFCOUNTER2_SELECT                                 =$DC04;
 mmCB_PERFCOUNTER3_SELECT                                 =$DC05;
 mmDB_PERFCOUNTER0_SELECT                                 =$DC40;
 mmDB_PERFCOUNTER0_SELECT1                                =$DC41;
 mmDB_PERFCOUNTER1_SELECT                                 =$DC42;
 mmDB_PERFCOUNTER1_SELECT1                                =$DC43;
 mmDB_PERFCOUNTER2_SELECT                                 =$DC44;
 mmDB_PERFCOUNTER3_SELECT                                 =$DC46;

function getRegName(i:Word):RawByteString;

implementation

function getRegName(i:Word):RawByteString;
begin
 case i of
  mmGRBM_CNTL                                              :Result:='mmGRBM_CNTL';
  mmGRBM_SKEW_CNTL                                         :Result:='mmGRBM_SKEW_CNTL';
  mmGRBM_STATUS2                                           :Result:='mmGRBM_STATUS2';
  mmGRBM_PWR_CNTL                                          :Result:='mmGRBM_PWR_CNTL';
  mmGRBM_STATUS                                            :Result:='mmGRBM_STATUS';
  mmGRBM_STATUS_SE0                                        :Result:='mmGRBM_STATUS_SE0';
  mmGRBM_STATUS_SE1                                        :Result:='mmGRBM_STATUS_SE1';
  mmGRBM_SOFT_RESET                                        :Result:='mmGRBM_SOFT_RESET';
  mmGRBM_DEBUG_CNTL                                        :Result:='mmGRBM_DEBUG_CNTL';
  mmGRBM_DEBUG_DATA                                        :Result:='mmGRBM_DEBUG_DATA';
  mmGRBM_GFX_CLKEN_CNTL                                    :Result:='mmGRBM_GFX_CLKEN_CNTL';
  mmGRBM_WAIT_IDLE_CLOCKS                                  :Result:='mmGRBM_WAIT_IDLE_CLOCKS';
  mmGRBM_STATUS_SE2                                        :Result:='mmGRBM_STATUS_SE2';
  mmGRBM_STATUS_SE3                                        :Result:='mmGRBM_STATUS_SE3';
  mmGRBM_DEBUG                                             :Result:='mmGRBM_DEBUG';
  mmGRBM_DEBUG_SNAPSHOT                                    :Result:='mmGRBM_DEBUG_SNAPSHOT';
  mmGRBM_READ_ERROR                                        :Result:='mmGRBM_READ_ERROR';
  mmGRBM_READ_ERROR2                                       :Result:='mmGRBM_READ_ERROR2';
  mmGRBM_INT_CNTL                                          :Result:='mmGRBM_INT_CNTL';
  mmGRBM_TRAP_OP                                           :Result:='mmGRBM_TRAP_OP';
  mmGRBM_TRAP_ADDR                                         :Result:='mmGRBM_TRAP_ADDR';
  mmGRBM_TRAP_ADDR_MSK                                     :Result:='mmGRBM_TRAP_ADDR_MSK';
  mmGRBM_TRAP_WD                                           :Result:='mmGRBM_TRAP_WD';
  mmGRBM_TRAP_WD_MSK                                       :Result:='mmGRBM_TRAP_WD_MSK';
  mmGRBM_DSM_BYPASS                                        :Result:='mmGRBM_DSM_BYPASS';
  mmGRBM_WRITE_ERROR                                       :Result:='mmGRBM_WRITE_ERROR';
  mmDEBUG_INDEX                                            :Result:='mmDEBUG_INDEX';
  mmDEBUG_DATA                                             :Result:='mmDEBUG_DATA';
  mmGRBM_NOWHERE                                           :Result:='mmGRBM_NOWHERE';
  mmGRBM_SCRATCH_REG0                                      :Result:='mmGRBM_SCRATCH_REG0';
  mmGRBM_SCRATCH_REG1                                      :Result:='mmGRBM_SCRATCH_REG1';
  mmGRBM_SCRATCH_REG2                                      :Result:='mmGRBM_SCRATCH_REG2';
  mmGRBM_SCRATCH_REG3                                      :Result:='mmGRBM_SCRATCH_REG3';
  mmGRBM_SCRATCH_REG4                                      :Result:='mmGRBM_SCRATCH_REG4';
  mmGRBM_SCRATCH_REG5                                      :Result:='mmGRBM_SCRATCH_REG5';
  mmGRBM_SCRATCH_REG6                                      :Result:='mmGRBM_SCRATCH_REG6';
  mmGRBM_SCRATCH_REG7                                      :Result:='mmGRBM_SCRATCH_REG7';
  mmCP_CPC_STATUS                                          :Result:='mmCP_CPC_STATUS';
  mmCP_CPC_BUSY_STAT                                       :Result:='mmCP_CPC_BUSY_STAT';
  mmCP_CPC_STALLED_STAT1                                   :Result:='mmCP_CPC_STALLED_STAT1';
  mmCP_CPF_STATUS                                          :Result:='mmCP_CPF_STATUS';
  mmCP_CPF_BUSY_STAT                                       :Result:='mmCP_CPF_BUSY_STAT';
  mmCP_CPF_STALLED_STAT1                                   :Result:='mmCP_CPF_STALLED_STAT1';
  mmCP_CPC_GRBM_FREE_COUNT                                 :Result:='mmCP_CPC_GRBM_FREE_COUNT';
  mmCP_MEC_CNTL                                            :Result:='mmCP_MEC_CNTL';
  mmCP_MEC_ME1_HEADER_DUMP                                 :Result:='mmCP_MEC_ME1_HEADER_DUMP';
  mmCP_MEC_ME2_HEADER_DUMP                                 :Result:='mmCP_MEC_ME2_HEADER_DUMP';
  mmCP_CPC_SCRATCH_INDEX                                   :Result:='mmCP_CPC_SCRATCH_INDEX';
  mmCP_CPC_SCRATCH_DATA                                    :Result:='mmCP_CPC_SCRATCH_DATA';
  mmCP_CPC_HALT_HYST_COUNT                                 :Result:='mmCP_CPC_HALT_HYST_COUNT';
  mmCP_PRT_LOD_STATS_CNTL0                                 :Result:='mmCP_PRT_LOD_STATS_CNTL0';
  mmCP_PRT_LOD_STATS_CNTL1                                 :Result:='mmCP_PRT_LOD_STATS_CNTL1';
  mmCP_PRT_LOD_STATS_CNTL2                                 :Result:='mmCP_PRT_LOD_STATS_CNTL2';
  mmCP_CE_COMPARE_COUNT                                    :Result:='mmCP_CE_COMPARE_COUNT';
  mmCP_CE_DE_COUNT                                         :Result:='mmCP_CE_DE_COUNT';
  mmCP_DE_CE_COUNT                                         :Result:='mmCP_DE_CE_COUNT';
  mmCP_DE_LAST_INVAL_COUNT                                 :Result:='mmCP_DE_LAST_INVAL_COUNT';
  mmCP_DE_DE_COUNT                                         :Result:='mmCP_DE_DE_COUNT';
  mmCP_STALLED_STAT3                                       :Result:='mmCP_STALLED_STAT3';
  mmCP_STALLED_STAT1                                       :Result:='mmCP_STALLED_STAT1';
  mmCP_STALLED_STAT2                                       :Result:='mmCP_STALLED_STAT2';
  mmCP_BUSY_STAT                                           :Result:='mmCP_BUSY_STAT';
  mmCP_STAT                                                :Result:='mmCP_STAT';
  mmCP_ME_HEADER_DUMP                                      :Result:='mmCP_ME_HEADER_DUMP';
  mmCP_PFP_HEADER_DUMP                                     :Result:='mmCP_PFP_HEADER_DUMP';
  mmCP_GRBM_FREE_COUNT                                     :Result:='mmCP_GRBM_FREE_COUNT';
  mmCP_CE_HEADER_DUMP                                      :Result:='mmCP_CE_HEADER_DUMP';
  mmCP_CSF_STAT                                            :Result:='mmCP_CSF_STAT';
  mmCP_CSF_CNTL                                            :Result:='mmCP_CSF_CNTL';
  mmCP_ME_CNTL                                             :Result:='mmCP_ME_CNTL';
  mmCP_CNTX_STAT                                           :Result:='mmCP_CNTX_STAT';
  mmCP_ME_PREEMPTION                                       :Result:='mmCP_ME_PREEMPTION';
  mmCP_ROQ_THRESHOLDS                                      :Result:='mmCP_ROQ_THRESHOLDS';
  mmCP_MEQ_STQ_THRESHOLD                                   :Result:='mmCP_MEQ_STQ_THRESHOLD';
  mmCP_RB2_RPTR                                            :Result:='mmCP_RB2_RPTR';
  mmCP_RB1_RPTR                                            :Result:='mmCP_RB1_RPTR';
  mmCP_RB0_RPTR                                            :Result:='mmCP_RB0_RPTR';
  mmCP_RB_WPTR_DELAY                                       :Result:='mmCP_RB_WPTR_DELAY';
  mmCP_RB_WPTR_POLL_CNTL                                   :Result:='mmCP_RB_WPTR_POLL_CNTL';
  mmCP_ROQ1_THRESHOLDS                                     :Result:='mmCP_ROQ1_THRESHOLDS';
  mmCP_ROQ2_THRESHOLDS                                     :Result:='mmCP_ROQ2_THRESHOLDS';
  mmCP_STQ_THRESHOLDS                                      :Result:='mmCP_STQ_THRESHOLDS';
  mmCP_QUEUE_THRESHOLDS                                    :Result:='mmCP_QUEUE_THRESHOLDS';
  mmCP_MEQ_THRESHOLDS                                      :Result:='mmCP_MEQ_THRESHOLDS';
  mmCP_ROQ_AVAIL                                           :Result:='mmCP_ROQ_AVAIL';
  mmCP_STQ_AVAIL                                           :Result:='mmCP_STQ_AVAIL';
  mmCP_ROQ2_AVAIL                                          :Result:='mmCP_ROQ2_AVAIL';
  mmCP_MEQ_AVAIL                                           :Result:='mmCP_MEQ_AVAIL';
  mmCP_CMD_INDEX                                           :Result:='mmCP_CMD_INDEX';
  mmCP_CMD_DATA                                            :Result:='mmCP_CMD_DATA';
  mmCP_ROQ_RB_STAT                                         :Result:='mmCP_ROQ_RB_STAT';
  mmCP_ROQ_IB1_STAT                                        :Result:='mmCP_ROQ_IB1_STAT';
  mmCP_ROQ_IB2_STAT                                        :Result:='mmCP_ROQ_IB2_STAT';
  mmCP_STQ_STAT                                            :Result:='mmCP_STQ_STAT';
  mmCP_STQ_WR_STAT                                         :Result:='mmCP_STQ_WR_STAT';
  mmCP_MEQ_STAT                                            :Result:='mmCP_MEQ_STAT';
  mmCP_CEQ1_AVAIL                                          :Result:='mmCP_CEQ1_AVAIL';
  mmCP_CEQ2_AVAIL                                          :Result:='mmCP_CEQ2_AVAIL';
  mmCP_CE_ROQ_RB_STAT                                      :Result:='mmCP_CE_ROQ_RB_STAT';
  mmCP_CE_ROQ_IB1_STAT                                     :Result:='mmCP_CE_ROQ_IB1_STAT';
  mmCP_CE_ROQ_IB2_STAT                                     :Result:='mmCP_CE_ROQ_IB2_STAT';
  mmCP_INT_STAT_DEBUG                                      :Result:='mmCP_INT_STAT_DEBUG';
  mmCP_PERFCOUNTER_SELECT                                  :Result:='mmCP_PERFCOUNTER_SELECT';
  mmCP_PERFCOUNTER_LO                                      :Result:='mmCP_PERFCOUNTER_LO';
  mmCP_PERFCOUNTER_HI                                      :Result:='mmCP_PERFCOUNTER_HI';
  mmVGT_VTX_VECT_EJECT_REG                                 :Result:='mmVGT_VTX_VECT_EJECT_REG';
  mmVGT_DMA_DATA_FIFO_DEPTH                                :Result:='mmVGT_DMA_DATA_FIFO_DEPTH';
  mmVGT_DMA_REQ_FIFO_DEPTH                                 :Result:='mmVGT_DMA_REQ_FIFO_DEPTH';
  mmVGT_DRAW_INIT_FIFO_DEPTH                               :Result:='mmVGT_DRAW_INIT_FIFO_DEPTH';
  mmVGT_LAST_COPY_STATE                                    :Result:='mmVGT_LAST_COPY_STATE';
  mmVGT_CACHE_INVALIDATION                                 :Result:='mmVGT_CACHE_INVALIDATION';
  mmVGT_RESET_DEBUG                                        :Result:='mmVGT_RESET_DEBUG';
  mmVGT_STRMOUT_DELAY                                      :Result:='mmVGT_STRMOUT_DELAY';
  mmVGT_FIFO_DEPTHS                                        :Result:='mmVGT_FIFO_DEPTHS';
  mmVGT_GS_VERTEX_REUSE                                    :Result:='mmVGT_GS_VERTEX_REUSE';
  mmVGT_MC_LAT_CNTL                                        :Result:='mmVGT_MC_LAT_CNTL';
  mmIA_CNTL_STATUS                                         :Result:='mmIA_CNTL_STATUS';
  mmVGT_DEBUG_CNTL                                         :Result:='mmVGT_DEBUG_CNTL';
  mmVGT_DEBUG_DATA                                         :Result:='mmVGT_DEBUG_DATA';
  mmIA_DEBUG_CNTL                                          :Result:='mmIA_DEBUG_CNTL';
  mmIA_DEBUG_DATA                                          :Result:='mmIA_DEBUG_DATA';
  mmVGT_CNTL_STATUS                                        :Result:='mmVGT_CNTL_STATUS';
  mmWD_DEBUG_CNTL                                          :Result:='mmWD_DEBUG_CNTL';
  mmWD_DEBUG_DATA                                          :Result:='mmWD_DEBUG_DATA';
  mmWD_CNTL_STATUS                                         :Result:='mmWD_CNTL_STATUS';
  mmCC_GC_PRIM_CONFIG                                      :Result:='mmCC_GC_PRIM_CONFIG';
  mmGC_USER_PRIM_CONFIG                                    :Result:='mmGC_USER_PRIM_CONFIG';
  mmWD_QOS                                                 :Result:='mmWD_QOS';
  mmCGTT_VGT_CLK_CTRL                                      :Result:='mmCGTT_VGT_CLK_CTRL';
  mmCGTT_IA_CLK_CTRL                                       :Result:='mmCGTT_IA_CLK_CTRL';
  mmVGT_SYS_CONFIG                                         :Result:='mmVGT_SYS_CONFIG';
  mmVGT_VS_MAX_WAVE_ID                                     :Result:='mmVGT_VS_MAX_WAVE_ID';
  mmGFX_PIPE_CONTROL                                       :Result:='mmGFX_PIPE_CONTROL';
  mmCC_GC_SHADER_ARRAY_CONFIG                              :Result:='mmCC_GC_SHADER_ARRAY_CONFIG';
  mmGC_USER_SHADER_ARRAY_CONFIG                            :Result:='mmGC_USER_SHADER_ARRAY_CONFIG';
  mmVGT_DMA_PRIMITIVE_TYPE                                 :Result:='mmVGT_DMA_PRIMITIVE_TYPE';
  mmVGT_DMA_CONTROL                                        :Result:='mmVGT_DMA_CONTROL';
  mmVGT_DMA_LS_HS_CONFIG                                   :Result:='mmVGT_DMA_LS_HS_CONFIG';
  mmPA_SU_DEBUG_CNTL                                       :Result:='mmPA_SU_DEBUG_CNTL';
  mmPA_SU_DEBUG_DATA                                       :Result:='mmPA_SU_DEBUG_DATA';
  mmPA_CL_CNTL_STATUS                                      :Result:='mmPA_CL_CNTL_STATUS';
  mmPA_CL_ENHANCE                                          :Result:='mmPA_CL_ENHANCE';
  mmPA_CL_RESET_DEBUG                                      :Result:='mmPA_CL_RESET_DEBUG';
  mmPA_SU_CNTL_STATUS                                      :Result:='mmPA_SU_CNTL_STATUS';
  mmPA_SC_FIFO_DEPTH_CNTL                                  :Result:='mmPA_SC_FIFO_DEPTH_CNTL';
  mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK                          :Result:='mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK';
  mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK                         :Result:='mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK';
  mmPA_SC_TRAP_SCREEN_HV_LOCK                              :Result:='mmPA_SC_TRAP_SCREEN_HV_LOCK';
  mmPA_SC_FORCE_EOV_MAX_CNTS                               :Result:='mmPA_SC_FORCE_EOV_MAX_CNTS';
  mmCGTT_SC_CLK_CTRL                                       :Result:='mmCGTT_SC_CLK_CTRL';
  mmPA_SC_FIFO_SIZE                                        :Result:='mmPA_SC_FIFO_SIZE';
  mmPA_SC_IF_FIFO_SIZE                                     :Result:='mmPA_SC_IF_FIFO_SIZE';
  mmPA_SC_DEBUG_CNTL                                       :Result:='mmPA_SC_DEBUG_CNTL';
  mmPA_SC_DEBUG_DATA                                       :Result:='mmPA_SC_DEBUG_DATA';
  mmPA_SC_ENHANCE                                          :Result:='mmPA_SC_ENHANCE';
  mmSQ_CONFIG                                              :Result:='mmSQ_CONFIG';
  mmSQC_CONFIG                                             :Result:='mmSQC_CONFIG';
  mmSQ_RANDOM_WAVE_PRI                                     :Result:='mmSQ_RANDOM_WAVE_PRI';
  mmSQ_REG_CREDITS                                         :Result:='mmSQ_REG_CREDITS';
  mmSQ_FIFO_SIZES                                          :Result:='mmSQ_FIFO_SIZES';
  mmSQ_DSM_CNTL                                            :Result:='mmSQ_DSM_CNTL';
  mmCC_SQC_BANK_DISABLE                                    :Result:='mmCC_SQC_BANK_DISABLE';
  mmUSER_SQC_BANK_DISABLE                                  :Result:='mmUSER_SQC_BANK_DISABLE';
  mmSQ_DEBUG_STS_GLOBAL                                    :Result:='mmSQ_DEBUG_STS_GLOBAL';
  mmSH_MEM_BASES                                           :Result:='mmSH_MEM_BASES';
  mmSH_MEM_APE1_BASE                                       :Result:='mmSH_MEM_APE1_BASE';
  mmSH_MEM_APE1_LIMIT                                      :Result:='mmSH_MEM_APE1_LIMIT';
  mmSH_MEM_CONFIG                                          :Result:='mmSH_MEM_CONFIG';
  mmSQC_DSM_CNTL                                           :Result:='mmSQC_DSM_CNTL';
  mmSQ_DEBUG_STS_GLOBAL2                                   :Result:='mmSQ_DEBUG_STS_GLOBAL2';
  mmSQ_DEBUG_STS_GLOBAL3                                   :Result:='mmSQ_DEBUG_STS_GLOBAL3';
  mmCC_GC_SHADER_RATE_CONFIG                               :Result:='mmCC_GC_SHADER_RATE_CONFIG';
  mmGC_USER_SHADER_RATE_CONFIG                             :Result:='mmGC_USER_SHADER_RATE_CONFIG';
  mmSQ_INTERRUPT_AUTO_MASK                                 :Result:='mmSQ_INTERRUPT_AUTO_MASK';
  mmSQ_INTERRUPT_MSG_CTRL                                  :Result:='mmSQ_INTERRUPT_MSG_CTRL';
  mmSQ_ALU_CLK_CTRL                                        :Result:='mmSQ_ALU_CLK_CTRL';
  mmSQ_TEX_CLK_CTRL                                        :Result:='mmSQ_TEX_CLK_CTRL';
  mmCGTT_SQ_CLK_CTRL                                       :Result:='mmCGTT_SQ_CLK_CTRL';
  mmCGTT_SQG_CLK_CTRL                                      :Result:='mmCGTT_SQG_CLK_CTRL';
  mmSQ_REG_TIMESTAMP                                       :Result:='mmSQ_REG_TIMESTAMP';
  mmSQ_CMD_TIMESTAMP                                       :Result:='mmSQ_CMD_TIMESTAMP';
  mmSQ_IND_INDEX                                           :Result:='mmSQ_IND_INDEX';
  mmSQ_IND_DATA                                            :Result:='mmSQ_IND_DATA';
  mmSQ_CMD                                                 :Result:='mmSQ_CMD';
  mmSQ_TIME_HI                                             :Result:='mmSQ_TIME_HI';
  mmSQ_TIME_LO                                             :Result:='mmSQ_TIME_LO';
  mmSQ_DS_0                                                :Result:='mmSQ_DS_0';
  mmSQ_THREAD_TRACE_CNTR                                   :Result:='mmSQ_THREAD_TRACE_CNTR';
  mmSQ_POWER_THROTTLE                                      :Result:='mmSQ_POWER_THROTTLE';
  mmSQ_POWER_THROTTLE2                                     :Result:='mmSQ_POWER_THROTTLE2';
  mmSQ_LB_CTR_CTRL                                         :Result:='mmSQ_LB_CTR_CTRL';
  mmSQ_LB_DATA_ALU_CYCLES                                  :Result:='mmSQ_LB_DATA_ALU_CYCLES';
  mmSQ_LB_DATA_TEX_CYCLES                                  :Result:='mmSQ_LB_DATA_TEX_CYCLES';
  mmSQ_LB_DATA_ALU_STALLS                                  :Result:='mmSQ_LB_DATA_ALU_STALLS';
  mmSQ_LB_DATA_TEX_STALLS                                  :Result:='mmSQ_LB_DATA_TEX_STALLS';
  mmSQC_EDC_CNT                                            :Result:='mmSQC_EDC_CNT';
  mmSQ_EDC_SEC_CNT                                         :Result:='mmSQ_EDC_SEC_CNT';
  mmSQ_EDC_DED_CNT                                         :Result:='mmSQ_EDC_DED_CNT';
  mmSQ_EDC_INFO                                            :Result:='mmSQ_EDC_INFO';
  mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2                     :Result:='mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2';
  mmSQ_WREXEC_EXEC_HI                                      :Result:='mmSQ_WREXEC_EXEC_HI';
  mmSQC_GATCL1_CNTL                                        :Result:='mmSQC_GATCL1_CNTL';
  mmSQC_ATC_EDC_GATCL1_CNT                                 :Result:='mmSQC_ATC_EDC_GATCL1_CNT';
  mmSQ_BUF_RSRC_WORD0                                      :Result:='mmSQ_BUF_RSRC_WORD0';
  mmSQ_BUF_RSRC_WORD1                                      :Result:='mmSQ_BUF_RSRC_WORD1';
  mmSQ_BUF_RSRC_WORD2                                      :Result:='mmSQ_BUF_RSRC_WORD2';
  mmSQ_BUF_RSRC_WORD3                                      :Result:='mmSQ_BUF_RSRC_WORD3';
  mmSQ_IMG_RSRC_WORD0                                      :Result:='mmSQ_IMG_RSRC_WORD0';
  mmSQ_IMG_RSRC_WORD1                                      :Result:='mmSQ_IMG_RSRC_WORD1';
  mmSQ_IMG_RSRC_WORD2                                      :Result:='mmSQ_IMG_RSRC_WORD2';
  mmSQ_IMG_RSRC_WORD3                                      :Result:='mmSQ_IMG_RSRC_WORD3';
  mmSQ_IMG_RSRC_WORD4                                      :Result:='mmSQ_IMG_RSRC_WORD4';
  mmSQ_IMG_RSRC_WORD5                                      :Result:='mmSQ_IMG_RSRC_WORD5';
  mmSQ_IMG_RSRC_WORD6                                      :Result:='mmSQ_IMG_RSRC_WORD6';
  mmSQ_IMG_RSRC_WORD7                                      :Result:='mmSQ_IMG_RSRC_WORD7';
  mmSQ_IMG_SAMP_WORD0                                      :Result:='mmSQ_IMG_SAMP_WORD0';
  mmSQ_IMG_SAMP_WORD1                                      :Result:='mmSQ_IMG_SAMP_WORD1';
  mmSQ_IMG_SAMP_WORD2                                      :Result:='mmSQ_IMG_SAMP_WORD2';
  mmSQ_IMG_SAMP_WORD3                                      :Result:='mmSQ_IMG_SAMP_WORD3';
  mmSQ_FLAT_SCRATCH_WORD0                                  :Result:='mmSQ_FLAT_SCRATCH_WORD0';
  mmSQ_FLAT_SCRATCH_WORD1                                  :Result:='mmSQ_FLAT_SCRATCH_WORD1';
  mmSQ_M0_GPR_IDX_WORD                                     :Result:='mmSQ_M0_GPR_IDX_WORD';
  mmCGTT_SX_CLK_CTRL0                                      :Result:='mmCGTT_SX_CLK_CTRL0';
  mmCGTT_SX_CLK_CTRL1                                      :Result:='mmCGTT_SX_CLK_CTRL1';
  mmCGTT_SX_CLK_CTRL2                                      :Result:='mmCGTT_SX_CLK_CTRL2';
  mmCGTT_SX_CLK_CTRL3                                      :Result:='mmCGTT_SX_CLK_CTRL3';
  mmCGTT_SX_CLK_CTRL4                                      :Result:='mmCGTT_SX_CLK_CTRL4';
  mmSX_DEBUG_BUSY                                          :Result:='mmSX_DEBUG_BUSY';
  mmSX_DEBUG_BUSY_2                                        :Result:='mmSX_DEBUG_BUSY_2';
  mmSX_DEBUG_BUSY_3                                        :Result:='mmSX_DEBUG_BUSY_3';
  mmSX_DEBUG_BUSY_4                                        :Result:='mmSX_DEBUG_BUSY_4';
  mmSX_DEBUG_1                                             :Result:='mmSX_DEBUG_1';
  mmSPI_PS_MAX_WAVE_ID                                     :Result:='mmSPI_PS_MAX_WAVE_ID';
  mmSPI_START_PHASE                                        :Result:='mmSPI_START_PHASE';
  mmSPI_GFX_CNTL                                           :Result:='mmSPI_GFX_CNTL';
  mmSPI_CONFIG_CNTL                                        :Result:='mmSPI_CONFIG_CNTL';
  mmSPI_DEBUG_CNTL                                         :Result:='mmSPI_DEBUG_CNTL';
  mmSPI_DEBUG_READ                                         :Result:='mmSPI_DEBUG_READ';
  mmSPI_DSM_CNTL                                           :Result:='mmSPI_DSM_CNTL';
  mmSPI_EDC_CNT                                            :Result:='mmSPI_EDC_CNT';
  mmSPI_CONFIG_CNTL_1                                      :Result:='mmSPI_CONFIG_CNTL_1';
  mmSPI_DEBUG_BUSY                                         :Result:='mmSPI_DEBUG_BUSY';
  mmSPI_CONFIG_CNTL_2                                      :Result:='mmSPI_CONFIG_CNTL_2';
  mmCGTS_TCC_DISABLE                                       :Result:='mmCGTS_TCC_DISABLE';
  mmCGTS_USER_TCC_DISABLE                                  :Result:='mmCGTS_USER_TCC_DISABLE';
  mmCGTS_SM_CTRL_REG                                       :Result:='mmCGTS_SM_CTRL_REG';
  mmCGTS_RD_CTRL_REG                                       :Result:='mmCGTS_RD_CTRL_REG';
  mmCGTS_RD_REG                                            :Result:='mmCGTS_RD_REG';
  mmCGTT_PC_CLK_CTRL                                       :Result:='mmCGTT_PC_CLK_CTRL';
  mmCGTT_BCI_CLK_CTRL                                      :Result:='mmCGTT_BCI_CLK_CTRL';
  mmSPI_WF_LIFETIME_CNTL                                   :Result:='mmSPI_WF_LIFETIME_CNTL';
  mmSPI_WF_LIFETIME_LIMIT_0                                :Result:='mmSPI_WF_LIFETIME_LIMIT_0';
  mmSPI_WF_LIFETIME_LIMIT_1                                :Result:='mmSPI_WF_LIFETIME_LIMIT_1';
  mmSPI_WF_LIFETIME_LIMIT_2                                :Result:='mmSPI_WF_LIFETIME_LIMIT_2';
  mmSPI_WF_LIFETIME_LIMIT_3                                :Result:='mmSPI_WF_LIFETIME_LIMIT_3';
  mmSPI_WF_LIFETIME_LIMIT_4                                :Result:='mmSPI_WF_LIFETIME_LIMIT_4';
  mmSPI_WF_LIFETIME_LIMIT_5                                :Result:='mmSPI_WF_LIFETIME_LIMIT_5';
  mmSPI_WF_LIFETIME_LIMIT_6                                :Result:='mmSPI_WF_LIFETIME_LIMIT_6';
  mmSPI_WF_LIFETIME_LIMIT_7                                :Result:='mmSPI_WF_LIFETIME_LIMIT_7';
  mmSPI_WF_LIFETIME_LIMIT_8                                :Result:='mmSPI_WF_LIFETIME_LIMIT_8';
  mmSPI_WF_LIFETIME_LIMIT_9                                :Result:='mmSPI_WF_LIFETIME_LIMIT_9';
  mmSPI_WF_LIFETIME_STATUS_0                               :Result:='mmSPI_WF_LIFETIME_STATUS_0';
  mmSPI_WF_LIFETIME_STATUS_1                               :Result:='mmSPI_WF_LIFETIME_STATUS_1';
  mmSPI_WF_LIFETIME_STATUS_2                               :Result:='mmSPI_WF_LIFETIME_STATUS_2';
  mmSPI_WF_LIFETIME_STATUS_3                               :Result:='mmSPI_WF_LIFETIME_STATUS_3';
  mmSPI_WF_LIFETIME_STATUS_4                               :Result:='mmSPI_WF_LIFETIME_STATUS_4';
  mmSPI_WF_LIFETIME_STATUS_5                               :Result:='mmSPI_WF_LIFETIME_STATUS_5';
  mmSPI_WF_LIFETIME_STATUS_6                               :Result:='mmSPI_WF_LIFETIME_STATUS_6';
  mmSPI_WF_LIFETIME_STATUS_7                               :Result:='mmSPI_WF_LIFETIME_STATUS_7';
  mmSPI_WF_LIFETIME_STATUS_8                               :Result:='mmSPI_WF_LIFETIME_STATUS_8';
  mmSPI_WF_LIFETIME_STATUS_9                               :Result:='mmSPI_WF_LIFETIME_STATUS_9';
  mmSPI_WF_LIFETIME_STATUS_10                              :Result:='mmSPI_WF_LIFETIME_STATUS_10';
  mmSPI_WF_LIFETIME_STATUS_11                              :Result:='mmSPI_WF_LIFETIME_STATUS_11';
  mmSPI_WF_LIFETIME_STATUS_12                              :Result:='mmSPI_WF_LIFETIME_STATUS_12';
  mmSPI_WF_LIFETIME_STATUS_13                              :Result:='mmSPI_WF_LIFETIME_STATUS_13';
  mmSPI_WF_LIFETIME_STATUS_14                              :Result:='mmSPI_WF_LIFETIME_STATUS_14';
  mmSPI_WF_LIFETIME_STATUS_15                              :Result:='mmSPI_WF_LIFETIME_STATUS_15';
  mmSPI_WF_LIFETIME_STATUS_16                              :Result:='mmSPI_WF_LIFETIME_STATUS_16';
  mmSPI_WF_LIFETIME_STATUS_17                              :Result:='mmSPI_WF_LIFETIME_STATUS_17';
  mmSPI_WF_LIFETIME_STATUS_18                              :Result:='mmSPI_WF_LIFETIME_STATUS_18';
  mmSPI_WF_LIFETIME_STATUS_19                              :Result:='mmSPI_WF_LIFETIME_STATUS_19';
  mmSPI_WF_LIFETIME_STATUS_20                              :Result:='mmSPI_WF_LIFETIME_STATUS_20';
  mmSPI_WF_LIFETIME_DEBUG                                  :Result:='mmSPI_WF_LIFETIME_DEBUG';
  mmSPI_SLAVE_DEBUG_BUSY                                   :Result:='mmSPI_SLAVE_DEBUG_BUSY';
  mmSPI_LB_CTR_CTRL                                        :Result:='mmSPI_LB_CTR_CTRL';
  mmSPI_LB_CU_MASK                                         :Result:='mmSPI_LB_CU_MASK';
  mmSPI_LB_DATA_REG                                        :Result:='mmSPI_LB_DATA_REG';
  mmSPI_PG_ENABLE_STATIC_CU_MASK                           :Result:='mmSPI_PG_ENABLE_STATIC_CU_MASK';
  mmSPI_GDS_CREDITS                                        :Result:='mmSPI_GDS_CREDITS';
  mmSPI_SX_EXPORT_BUFFER_SIZES                             :Result:='mmSPI_SX_EXPORT_BUFFER_SIZES';
  mmSPI_SX_SCOREBOARD_BUFFER_SIZES                         :Result:='mmSPI_SX_SCOREBOARD_BUFFER_SIZES';
  mmSPI_CSQ_WF_ACTIVE_STATUS                               :Result:='mmSPI_CSQ_WF_ACTIVE_STATUS';
  mmSPI_CSQ_WF_ACTIVE_COUNT_0                              :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_0';
  mmSPI_CSQ_WF_ACTIVE_COUNT_1                              :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_1';
  mmSPI_CSQ_WF_ACTIVE_COUNT_2                              :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_2';
  mmSPI_CSQ_WF_ACTIVE_COUNT_3                              :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_3';
  mmSPI_CSQ_WF_ACTIVE_COUNT_4                              :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_4';
  mmSPI_CSQ_WF_ACTIVE_COUNT_5                              :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_5';
  mmSPI_CSQ_WF_ACTIVE_COUNT_6                              :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_6';
  mmSPI_CSQ_WF_ACTIVE_COUNT_7                              :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_7';
  mmBCI_DEBUG_READ                                         :Result:='mmBCI_DEBUG_READ';
  mmSPI_P0_TRAP_SCREEN_PSBA_LO                             :Result:='mmSPI_P0_TRAP_SCREEN_PSBA_LO';
  mmSPI_P0_TRAP_SCREEN_PSBA_HI                             :Result:='mmSPI_P0_TRAP_SCREEN_PSBA_HI';
  mmSPI_P0_TRAP_SCREEN_PSMA_LO                             :Result:='mmSPI_P0_TRAP_SCREEN_PSMA_LO';
  mmSPI_P0_TRAP_SCREEN_PSMA_HI                             :Result:='mmSPI_P0_TRAP_SCREEN_PSMA_HI';
  mmSPI_P0_TRAP_SCREEN_GPR_MIN                             :Result:='mmSPI_P0_TRAP_SCREEN_GPR_MIN';
  mmSPI_P1_TRAP_SCREEN_PSBA_LO                             :Result:='mmSPI_P1_TRAP_SCREEN_PSBA_LO';
  mmSPI_P1_TRAP_SCREEN_PSBA_HI                             :Result:='mmSPI_P1_TRAP_SCREEN_PSBA_HI';
  mmSPI_P1_TRAP_SCREEN_PSMA_LO                             :Result:='mmSPI_P1_TRAP_SCREEN_PSMA_LO';
  mmSPI_P1_TRAP_SCREEN_PSMA_HI                             :Result:='mmSPI_P1_TRAP_SCREEN_PSMA_HI';
  mmSPI_P1_TRAP_SCREEN_GPR_MIN                             :Result:='mmSPI_P1_TRAP_SCREEN_GPR_MIN';
  mmTD_CNTL                                                :Result:='mmTD_CNTL';
  mmTD_STATUS                                              :Result:='mmTD_STATUS';
  mmTD_CGTT_CTRL                                           :Result:='mmTD_CGTT_CTRL';
  mmTD_DEBUG_INDEX                                         :Result:='mmTD_DEBUG_INDEX';
  mmTD_DEBUG_DATA                                          :Result:='mmTD_DEBUG_DATA';
  mmTD_DSM_CNTL                                            :Result:='mmTD_DSM_CNTL';
  mmTD_SCRATCH                                             :Result:='mmTD_SCRATCH';
  mmTA_CNTL                                                :Result:='mmTA_CNTL';
  mmTA_CNTL_AUX                                            :Result:='mmTA_CNTL_AUX';
  mmTA_RESERVED_010C                                       :Result:='mmTA_RESERVED_010C';
  mmTA_CGTT_CTRL                                           :Result:='mmTA_CGTT_CTRL';
  mmTA_STATUS                                              :Result:='mmTA_STATUS';
  mmTA_DEBUG_INDEX                                         :Result:='mmTA_DEBUG_INDEX';
  mmTA_DEBUG_DATA                                          :Result:='mmTA_DEBUG_DATA';
  mmTA_SCRATCH                                             :Result:='mmTA_SCRATCH';
  mmSH_HIDDEN_PRIVATE_BASE_VMID                            :Result:='mmSH_HIDDEN_PRIVATE_BASE_VMID';
  mmSH_STATIC_MEM_CONFIG                                   :Result:='mmSH_STATIC_MEM_CONFIG';
  mmGDS_CONFIG                                             :Result:='mmGDS_CONFIG';
  mmGDS_CNTL_STATUS                                        :Result:='mmGDS_CNTL_STATUS';
  mmGDS_ENHANCE2                                           :Result:='mmGDS_ENHANCE2';
  mmGDS_PROTECTION_FAULT                                   :Result:='mmGDS_PROTECTION_FAULT';
  mmGDS_VM_PROTECTION_FAULT                                :Result:='mmGDS_VM_PROTECTION_FAULT';
  mmGDS_EDC_CNT                                            :Result:='mmGDS_EDC_CNT';
  mmGDS_EDC_GRBM_CNT                                       :Result:='mmGDS_EDC_GRBM_CNT';
  mmGDS_EDC_OA_DED                                         :Result:='mmGDS_EDC_OA_DED';
  mmGDS_DEBUG_CNTL                                         :Result:='mmGDS_DEBUG_CNTL';
  mmGDS_DEBUG_DATA                                         :Result:='mmGDS_DEBUG_DATA';
  mmGDS_DSM_CNTL                                           :Result:='mmGDS_DSM_CNTL';
  mmCGTT_GDS_CLK_CTRL                                      :Result:='mmCGTT_GDS_CLK_CTRL';
  mmGDS_SECDED_CNT                                         :Result:='mmGDS_SECDED_CNT';
  mmGDS_GRBM_SECDED_CNT                                    :Result:='mmGDS_GRBM_SECDED_CNT';
  mmGDS_OA_DED                                             :Result:='mmGDS_OA_DED';
  mmDB_DEBUG                                               :Result:='mmDB_DEBUG';
  mmDB_DEBUG2                                              :Result:='mmDB_DEBUG2';
  mmDB_DEBUG3                                              :Result:='mmDB_DEBUG3';
  mmDB_DEBUG4                                              :Result:='mmDB_DEBUG4';
  mmDB_CREDIT_LIMIT                                        :Result:='mmDB_CREDIT_LIMIT';
  mmDB_WATERMARKS                                          :Result:='mmDB_WATERMARKS';
  mmDB_SUBTILE_CONTROL                                     :Result:='mmDB_SUBTILE_CONTROL';
  mmDB_FREE_CACHELINES                                     :Result:='mmDB_FREE_CACHELINES';
  mmDB_FIFO_DEPTH1                                         :Result:='mmDB_FIFO_DEPTH1';
  mmDB_FIFO_DEPTH2                                         :Result:='mmDB_FIFO_DEPTH2';
  mmDB_CGTT_CLK_CTRL_0                                     :Result:='mmDB_CGTT_CLK_CTRL_0';
  mmDB_RING_CONTROL                                        :Result:='mmDB_RING_CONTROL';
  mmDB_READ_DEBUG_0                                        :Result:='mmDB_READ_DEBUG_0';
  mmDB_READ_DEBUG_1                                        :Result:='mmDB_READ_DEBUG_1';
  mmDB_READ_DEBUG_2                                        :Result:='mmDB_READ_DEBUG_2';
  mmDB_READ_DEBUG_3                                        :Result:='mmDB_READ_DEBUG_3';
  mmDB_READ_DEBUG_4                                        :Result:='mmDB_READ_DEBUG_4';
  mmDB_READ_DEBUG_5                                        :Result:='mmDB_READ_DEBUG_5';
  mmDB_READ_DEBUG_6                                        :Result:='mmDB_READ_DEBUG_6';
  mmDB_READ_DEBUG_7                                        :Result:='mmDB_READ_DEBUG_7';
  mmDB_READ_DEBUG_8                                        :Result:='mmDB_READ_DEBUG_8';
  mmDB_READ_DEBUG_9                                        :Result:='mmDB_READ_DEBUG_9';
  mmDB_READ_DEBUG_A                                        :Result:='mmDB_READ_DEBUG_A';
  mmDB_READ_DEBUG_B                                        :Result:='mmDB_READ_DEBUG_B';
  mmDB_READ_DEBUG_C                                        :Result:='mmDB_READ_DEBUG_C';
  mmDB_READ_DEBUG_D                                        :Result:='mmDB_READ_DEBUG_D';
  mmDB_READ_DEBUG_E                                        :Result:='mmDB_READ_DEBUG_E';
  mmDB_READ_DEBUG_F                                        :Result:='mmDB_READ_DEBUG_F';
  mmCC_RB_REDUNDANCY                                       :Result:='mmCC_RB_REDUNDANCY';
  mmCC_RB_BACKEND_DISABLE                                  :Result:='mmCC_RB_BACKEND_DISABLE';
  mmGB_ADDR_CONFIG                                         :Result:='mmGB_ADDR_CONFIG';
  mmGB_BACKEND_MAP                                         :Result:='mmGB_BACKEND_MAP';
  mmGB_GPU_ID                                              :Result:='mmGB_GPU_ID';
  mmCC_RB_DAISY_CHAIN                                      :Result:='mmCC_RB_DAISY_CHAIN';
  mmGB_TILE_MODE0                                          :Result:='mmGB_TILE_MODE0';
  mmGB_TILE_MODE1                                          :Result:='mmGB_TILE_MODE1';
  mmGB_TILE_MODE2                                          :Result:='mmGB_TILE_MODE2';
  mmGB_TILE_MODE3                                          :Result:='mmGB_TILE_MODE3';
  mmGB_TILE_MODE4                                          :Result:='mmGB_TILE_MODE4';
  mmGB_TILE_MODE5                                          :Result:='mmGB_TILE_MODE5';
  mmGB_TILE_MODE6                                          :Result:='mmGB_TILE_MODE6';
  mmGB_TILE_MODE7                                          :Result:='mmGB_TILE_MODE7';
  mmGB_TILE_MODE8                                          :Result:='mmGB_TILE_MODE8';
  mmGB_TILE_MODE9                                          :Result:='mmGB_TILE_MODE9';
  mmGB_TILE_MODE10                                         :Result:='mmGB_TILE_MODE10';
  mmGB_TILE_MODE11                                         :Result:='mmGB_TILE_MODE11';
  mmGB_TILE_MODE12                                         :Result:='mmGB_TILE_MODE12';
  mmGB_TILE_MODE13                                         :Result:='mmGB_TILE_MODE13';
  mmGB_TILE_MODE14                                         :Result:='mmGB_TILE_MODE14';
  mmGB_TILE_MODE15                                         :Result:='mmGB_TILE_MODE15';
  mmGB_TILE_MODE16                                         :Result:='mmGB_TILE_MODE16';
  mmGB_TILE_MODE17                                         :Result:='mmGB_TILE_MODE17';
  mmGB_TILE_MODE18                                         :Result:='mmGB_TILE_MODE18';
  mmGB_TILE_MODE19                                         :Result:='mmGB_TILE_MODE19';
  mmGB_TILE_MODE20                                         :Result:='mmGB_TILE_MODE20';
  mmGB_TILE_MODE21                                         :Result:='mmGB_TILE_MODE21';
  mmGB_TILE_MODE22                                         :Result:='mmGB_TILE_MODE22';
  mmGB_TILE_MODE23                                         :Result:='mmGB_TILE_MODE23';
  mmGB_TILE_MODE24                                         :Result:='mmGB_TILE_MODE24';
  mmGB_TILE_MODE25                                         :Result:='mmGB_TILE_MODE25';
  mmGB_TILE_MODE26                                         :Result:='mmGB_TILE_MODE26';
  mmGB_TILE_MODE27                                         :Result:='mmGB_TILE_MODE27';
  mmGB_TILE_MODE28                                         :Result:='mmGB_TILE_MODE28';
  mmGB_TILE_MODE29                                         :Result:='mmGB_TILE_MODE29';
  mmGB_TILE_MODE30                                         :Result:='mmGB_TILE_MODE30';
  mmGB_TILE_MODE31                                         :Result:='mmGB_TILE_MODE31';
  mmGB_MACROTILE_MODE0                                     :Result:='mmGB_MACROTILE_MODE0';
  mmGB_MACROTILE_MODE1                                     :Result:='mmGB_MACROTILE_MODE1';
  mmGB_MACROTILE_MODE2                                     :Result:='mmGB_MACROTILE_MODE2';
  mmGB_MACROTILE_MODE3                                     :Result:='mmGB_MACROTILE_MODE3';
  mmGB_MACROTILE_MODE4                                     :Result:='mmGB_MACROTILE_MODE4';
  mmGB_MACROTILE_MODE5                                     :Result:='mmGB_MACROTILE_MODE5';
  mmGB_MACROTILE_MODE6                                     :Result:='mmGB_MACROTILE_MODE6';
  mmGB_MACROTILE_MODE7                                     :Result:='mmGB_MACROTILE_MODE7';
  mmGB_MACROTILE_MODE8                                     :Result:='mmGB_MACROTILE_MODE8';
  mmGB_MACROTILE_MODE9                                     :Result:='mmGB_MACROTILE_MODE9';
  mmGB_MACROTILE_MODE10                                    :Result:='mmGB_MACROTILE_MODE10';
  mmGB_MACROTILE_MODE11                                    :Result:='mmGB_MACROTILE_MODE11';
  mmGB_MACROTILE_MODE12                                    :Result:='mmGB_MACROTILE_MODE12';
  mmGB_MACROTILE_MODE13                                    :Result:='mmGB_MACROTILE_MODE13';
  mmGB_MACROTILE_MODE14                                    :Result:='mmGB_MACROTILE_MODE14';
  mmGB_MACROTILE_MODE15                                    :Result:='mmGB_MACROTILE_MODE15';
  mmCB_HW_CONTROL_3                                        :Result:='mmCB_HW_CONTROL_3';
  mmCB_HW_CONTROL                                          :Result:='mmCB_HW_CONTROL';
  mmCB_HW_CONTROL_1                                        :Result:='mmCB_HW_CONTROL_1';
  mmCB_HW_CONTROL_2                                        :Result:='mmCB_HW_CONTROL_2';
  mmCB_DCC_CONFIG                                          :Result:='mmCB_DCC_CONFIG';
  mmCB_PERFCOUNTER0_SELECT0                                :Result:='mmCB_PERFCOUNTER0_SELECT0';
  mmCB_PERFCOUNTER1_SELECT0                                :Result:='mmCB_PERFCOUNTER1_SELECT0';
  mmCB_PERFCOUNTER1_SELECT1                                :Result:='mmCB_PERFCOUNTER1_SELECT1';
  mmCB_PERFCOUNTER2_SELECT0                                :Result:='mmCB_PERFCOUNTER2_SELECT0';
  mmCB_PERFCOUNTER2_SELECT1                                :Result:='mmCB_PERFCOUNTER2_SELECT1';
  mmCB_PERFCOUNTER3_SELECT0                                :Result:='mmCB_PERFCOUNTER3_SELECT0';
  mmCB_PERFCOUNTER3_SELECT1                                :Result:='mmCB_PERFCOUNTER3_SELECT1';
  mmCB_CGTT_SCLK_CTRL                                      :Result:='mmCB_CGTT_SCLK_CTRL';
  mmCB_DEBUG_BUS_1                                         :Result:='mmCB_DEBUG_BUS_1';
  mmCB_DEBUG_BUS_2                                         :Result:='mmCB_DEBUG_BUS_2';
  mmCB_DEBUG_BUS_13                                        :Result:='mmCB_DEBUG_BUS_13';
  mmCB_DEBUG_BUS_14                                        :Result:='mmCB_DEBUG_BUS_14';
  mmCB_DEBUG_BUS_15                                        :Result:='mmCB_DEBUG_BUS_15';
  mmCB_DEBUG_BUS_16                                        :Result:='mmCB_DEBUG_BUS_16';
  mmCB_DEBUG_BUS_17                                        :Result:='mmCB_DEBUG_BUS_17';
  mmCB_DEBUG_BUS_18                                        :Result:='mmCB_DEBUG_BUS_18';
  mmCB_DEBUG_BUS_19                                        :Result:='mmCB_DEBUG_BUS_19';
  mmCB_DEBUG_BUS_20                                        :Result:='mmCB_DEBUG_BUS_20';
  mmCB_DEBUG_BUS_21                                        :Result:='mmCB_DEBUG_BUS_21';
  mmCB_DEBUG_BUS_22                                        :Result:='mmCB_DEBUG_BUS_22';
  mmGC_USER_RB_REDUNDANCY                                  :Result:='mmGC_USER_RB_REDUNDANCY';
  mmGC_USER_RB_BACKEND_DISABLE                             :Result:='mmGC_USER_RB_BACKEND_DISABLE';
  mmTCP_INVALIDATE                                         :Result:='mmTCP_INVALIDATE';
  mmTCP_STATUS                                             :Result:='mmTCP_STATUS';
  mmTCP_CNTL                                               :Result:='mmTCP_CNTL';
  mmTCP_CHAN_STEER_LO                                      :Result:='mmTCP_CHAN_STEER_LO';
  mmTCP_CHAN_STEER_HI                                      :Result:='mmTCP_CHAN_STEER_HI';
  mmTCP_ADDR_CONFIG                                        :Result:='mmTCP_ADDR_CONFIG';
  mmTCP_CREDIT                                             :Result:='mmTCP_CREDIT';
  mmCGTT_TCP_CLK_CTRL                                      :Result:='mmCGTT_TCP_CLK_CTRL';
  mmTCP_BUFFER_ADDR_HASH_CNTL                              :Result:='mmTCP_BUFFER_ADDR_HASH_CNTL';
  mmTCP_EDC_CNT                                            :Result:='mmTCP_EDC_CNT';
  mmTC_CFG_L1_LOAD_POLICY0                                 :Result:='mmTC_CFG_L1_LOAD_POLICY0';
  mmTC_CFG_L1_LOAD_POLICY1                                 :Result:='mmTC_CFG_L1_LOAD_POLICY1';
  mmTC_CFG_L1_STORE_POLICY                                 :Result:='mmTC_CFG_L1_STORE_POLICY';
  mmTC_CFG_L2_LOAD_POLICY0                                 :Result:='mmTC_CFG_L2_LOAD_POLICY0';
  mmTC_CFG_L2_LOAD_POLICY1                                 :Result:='mmTC_CFG_L2_LOAD_POLICY1';
  mmTC_CFG_L2_STORE_POLICY0                                :Result:='mmTC_CFG_L2_STORE_POLICY0';
  mmTC_CFG_L2_STORE_POLICY1                                :Result:='mmTC_CFG_L2_STORE_POLICY1';
  mmTC_CFG_L2_ATOMIC_POLICY                                :Result:='mmTC_CFG_L2_ATOMIC_POLICY';
  mmTC_CFG_L1_VOLATILE                                     :Result:='mmTC_CFG_L1_VOLATILE';
  mmTC_CFG_L2_VOLATILE                                     :Result:='mmTC_CFG_L2_VOLATILE';
  mmCGTT_TCI_CLK_CTRL                                      :Result:='mmCGTT_TCI_CLK_CTRL';
  mmTCI_STATUS                                             :Result:='mmTCI_STATUS';
  mmTCI_CNTL_1                                             :Result:='mmTCI_CNTL_1';
  mmTCI_CNTL_2                                             :Result:='mmTCI_CNTL_2';
  mmTCC_CTRL                                               :Result:='mmTCC_CTRL';
  mmTCC_CGTT_SCLK_CTRL                                     :Result:='mmTCC_CGTT_SCLK_CTRL';
  mmTCC_EDC_CNT                                            :Result:='mmTCC_EDC_CNT';
  mmTCC_REDUNDANCY                                         :Result:='mmTCC_REDUNDANCY';
  mmTCC_EXE_DISABLE                                        :Result:='mmTCC_EXE_DISABLE';
  mmTCC_DSM_CNTL                                           :Result:='mmTCC_DSM_CNTL';
  mmTCA_CTRL                                               :Result:='mmTCA_CTRL';
  mmTCA_CGTT_SCLK_CTRL                                     :Result:='mmTCA_CGTT_SCLK_CTRL';
  mmSPI_SHADER_TBA_LO_PS                                   :Result:='mmSPI_SHADER_TBA_LO_PS';
  mmSPI_SHADER_TBA_HI_PS                                   :Result:='mmSPI_SHADER_TBA_HI_PS';
  mmSPI_SHADER_TMA_LO_PS                                   :Result:='mmSPI_SHADER_TMA_LO_PS';
  mmSPI_SHADER_TMA_HI_PS                                   :Result:='mmSPI_SHADER_TMA_HI_PS';
  mmSPI_SHADER_PGM_RSRC3_PS                                :Result:='mmSPI_SHADER_PGM_RSRC3_PS';
  mmSPI_SHADER_PGM_LO_PS                                   :Result:='mmSPI_SHADER_PGM_LO_PS';
  mmSPI_SHADER_PGM_HI_PS                                   :Result:='mmSPI_SHADER_PGM_HI_PS';
  mmSPI_SHADER_PGM_RSRC1_PS                                :Result:='mmSPI_SHADER_PGM_RSRC1_PS';
  mmSPI_SHADER_PGM_RSRC2_PS                                :Result:='mmSPI_SHADER_PGM_RSRC2_PS';
  mmSPI_SHADER_USER_DATA_PS_0                              :Result:='mmSPI_SHADER_USER_DATA_PS_0';
  mmSPI_SHADER_USER_DATA_PS_1                              :Result:='mmSPI_SHADER_USER_DATA_PS_1';
  mmSPI_SHADER_USER_DATA_PS_2                              :Result:='mmSPI_SHADER_USER_DATA_PS_2';
  mmSPI_SHADER_USER_DATA_PS_3                              :Result:='mmSPI_SHADER_USER_DATA_PS_3';
  mmSPI_SHADER_USER_DATA_PS_4                              :Result:='mmSPI_SHADER_USER_DATA_PS_4';
  mmSPI_SHADER_USER_DATA_PS_5                              :Result:='mmSPI_SHADER_USER_DATA_PS_5';
  mmSPI_SHADER_USER_DATA_PS_6                              :Result:='mmSPI_SHADER_USER_DATA_PS_6';
  mmSPI_SHADER_USER_DATA_PS_7                              :Result:='mmSPI_SHADER_USER_DATA_PS_7';
  mmSPI_SHADER_USER_DATA_PS_8                              :Result:='mmSPI_SHADER_USER_DATA_PS_8';
  mmSPI_SHADER_USER_DATA_PS_9                              :Result:='mmSPI_SHADER_USER_DATA_PS_9';
  mmSPI_SHADER_USER_DATA_PS_10                             :Result:='mmSPI_SHADER_USER_DATA_PS_10';
  mmSPI_SHADER_USER_DATA_PS_11                             :Result:='mmSPI_SHADER_USER_DATA_PS_11';
  mmSPI_SHADER_USER_DATA_PS_12                             :Result:='mmSPI_SHADER_USER_DATA_PS_12';
  mmSPI_SHADER_USER_DATA_PS_13                             :Result:='mmSPI_SHADER_USER_DATA_PS_13';
  mmSPI_SHADER_USER_DATA_PS_14                             :Result:='mmSPI_SHADER_USER_DATA_PS_14';
  mmSPI_SHADER_USER_DATA_PS_15                             :Result:='mmSPI_SHADER_USER_DATA_PS_15';
  mmSPI_SHADER_TBA_LO_VS                                   :Result:='mmSPI_SHADER_TBA_LO_VS';
  mmSPI_SHADER_TBA_HI_VS                                   :Result:='mmSPI_SHADER_TBA_HI_VS';
  mmSPI_SHADER_TMA_LO_VS                                   :Result:='mmSPI_SHADER_TMA_LO_VS';
  mmSPI_SHADER_TMA_HI_VS                                   :Result:='mmSPI_SHADER_TMA_HI_VS';
  mmSPI_SHADER_PGM_RSRC3_VS                                :Result:='mmSPI_SHADER_PGM_RSRC3_VS';
  mmSPI_SHADER_LATE_ALLOC_VS                               :Result:='mmSPI_SHADER_LATE_ALLOC_VS';
  mmSPI_SHADER_PGM_LO_VS                                   :Result:='mmSPI_SHADER_PGM_LO_VS';
  mmSPI_SHADER_PGM_HI_VS                                   :Result:='mmSPI_SHADER_PGM_HI_VS';
  mmSPI_SHADER_PGM_RSRC1_VS                                :Result:='mmSPI_SHADER_PGM_RSRC1_VS';
  mmSPI_SHADER_PGM_RSRC2_VS                                :Result:='mmSPI_SHADER_PGM_RSRC2_VS';
  mmSPI_SHADER_USER_DATA_VS_0                              :Result:='mmSPI_SHADER_USER_DATA_VS_0';
  mmSPI_SHADER_USER_DATA_VS_1                              :Result:='mmSPI_SHADER_USER_DATA_VS_1';
  mmSPI_SHADER_USER_DATA_VS_2                              :Result:='mmSPI_SHADER_USER_DATA_VS_2';
  mmSPI_SHADER_USER_DATA_VS_3                              :Result:='mmSPI_SHADER_USER_DATA_VS_3';
  mmSPI_SHADER_USER_DATA_VS_4                              :Result:='mmSPI_SHADER_USER_DATA_VS_4';
  mmSPI_SHADER_USER_DATA_VS_5                              :Result:='mmSPI_SHADER_USER_DATA_VS_5';
  mmSPI_SHADER_USER_DATA_VS_6                              :Result:='mmSPI_SHADER_USER_DATA_VS_6';
  mmSPI_SHADER_USER_DATA_VS_7                              :Result:='mmSPI_SHADER_USER_DATA_VS_7';
  mmSPI_SHADER_USER_DATA_VS_8                              :Result:='mmSPI_SHADER_USER_DATA_VS_8';
  mmSPI_SHADER_USER_DATA_VS_9                              :Result:='mmSPI_SHADER_USER_DATA_VS_9';
  mmSPI_SHADER_USER_DATA_VS_10                             :Result:='mmSPI_SHADER_USER_DATA_VS_10';
  mmSPI_SHADER_USER_DATA_VS_11                             :Result:='mmSPI_SHADER_USER_DATA_VS_11';
  mmSPI_SHADER_USER_DATA_VS_12                             :Result:='mmSPI_SHADER_USER_DATA_VS_12';
  mmSPI_SHADER_USER_DATA_VS_13                             :Result:='mmSPI_SHADER_USER_DATA_VS_13';
  mmSPI_SHADER_USER_DATA_VS_14                             :Result:='mmSPI_SHADER_USER_DATA_VS_14';
  mmSPI_SHADER_USER_DATA_VS_15                             :Result:='mmSPI_SHADER_USER_DATA_VS_15';
  mmSPI_SHADER_PGM_RSRC2_ES_VS                             :Result:='mmSPI_SHADER_PGM_RSRC2_ES_VS';
  mmSPI_SHADER_PGM_RSRC2_LS_VS                             :Result:='mmSPI_SHADER_PGM_RSRC2_LS_VS';
  mmSPI_SHADER_TBA_LO_GS                                   :Result:='mmSPI_SHADER_TBA_LO_GS';
  mmSPI_SHADER_TBA_HI_GS                                   :Result:='mmSPI_SHADER_TBA_HI_GS';
  mmSPI_SHADER_TMA_LO_GS                                   :Result:='mmSPI_SHADER_TMA_LO_GS';
  mmSPI_SHADER_TMA_HI_GS                                   :Result:='mmSPI_SHADER_TMA_HI_GS';
  mmSPI_SHADER_PGM_RSRC3_GS                                :Result:='mmSPI_SHADER_PGM_RSRC3_GS';
  mmSPI_SHADER_PGM_LO_GS                                   :Result:='mmSPI_SHADER_PGM_LO_GS';
  mmSPI_SHADER_PGM_HI_GS                                   :Result:='mmSPI_SHADER_PGM_HI_GS';
  mmSPI_SHADER_PGM_RSRC1_GS                                :Result:='mmSPI_SHADER_PGM_RSRC1_GS';
  mmSPI_SHADER_PGM_RSRC2_GS                                :Result:='mmSPI_SHADER_PGM_RSRC2_GS';
  mmSPI_SHADER_USER_DATA_GS_0                              :Result:='mmSPI_SHADER_USER_DATA_GS_0';
  mmSPI_SHADER_USER_DATA_GS_1                              :Result:='mmSPI_SHADER_USER_DATA_GS_1';
  mmSPI_SHADER_USER_DATA_GS_2                              :Result:='mmSPI_SHADER_USER_DATA_GS_2';
  mmSPI_SHADER_USER_DATA_GS_3                              :Result:='mmSPI_SHADER_USER_DATA_GS_3';
  mmSPI_SHADER_USER_DATA_GS_4                              :Result:='mmSPI_SHADER_USER_DATA_GS_4';
  mmSPI_SHADER_USER_DATA_GS_5                              :Result:='mmSPI_SHADER_USER_DATA_GS_5';
  mmSPI_SHADER_USER_DATA_GS_6                              :Result:='mmSPI_SHADER_USER_DATA_GS_6';
  mmSPI_SHADER_USER_DATA_GS_7                              :Result:='mmSPI_SHADER_USER_DATA_GS_7';
  mmSPI_SHADER_USER_DATA_GS_8                              :Result:='mmSPI_SHADER_USER_DATA_GS_8';
  mmSPI_SHADER_USER_DATA_GS_9                              :Result:='mmSPI_SHADER_USER_DATA_GS_9';
  mmSPI_SHADER_USER_DATA_GS_10                             :Result:='mmSPI_SHADER_USER_DATA_GS_10';
  mmSPI_SHADER_USER_DATA_GS_11                             :Result:='mmSPI_SHADER_USER_DATA_GS_11';
  mmSPI_SHADER_USER_DATA_GS_12                             :Result:='mmSPI_SHADER_USER_DATA_GS_12';
  mmSPI_SHADER_USER_DATA_GS_13                             :Result:='mmSPI_SHADER_USER_DATA_GS_13';
  mmSPI_SHADER_USER_DATA_GS_14                             :Result:='mmSPI_SHADER_USER_DATA_GS_14';
  mmSPI_SHADER_USER_DATA_GS_15                             :Result:='mmSPI_SHADER_USER_DATA_GS_15';
  mmSPI_SHADER_PGM_RSRC2_ES_GS                             :Result:='mmSPI_SHADER_PGM_RSRC2_ES_GS';
  mmSPI_SHADER_TBA_LO_ES                                   :Result:='mmSPI_SHADER_TBA_LO_ES';
  mmSPI_SHADER_TBA_HI_ES                                   :Result:='mmSPI_SHADER_TBA_HI_ES';
  mmSPI_SHADER_TMA_LO_ES                                   :Result:='mmSPI_SHADER_TMA_LO_ES';
  mmSPI_SHADER_TMA_HI_ES                                   :Result:='mmSPI_SHADER_TMA_HI_ES';
  mmSPI_SHADER_PGM_RSRC3_ES                                :Result:='mmSPI_SHADER_PGM_RSRC3_ES';
  mmSPI_SHADER_PGM_LO_ES                                   :Result:='mmSPI_SHADER_PGM_LO_ES';
  mmSPI_SHADER_PGM_HI_ES                                   :Result:='mmSPI_SHADER_PGM_HI_ES';
  mmSPI_SHADER_PGM_RSRC1_ES                                :Result:='mmSPI_SHADER_PGM_RSRC1_ES';
  mmSPI_SHADER_PGM_RSRC2_ES                                :Result:='mmSPI_SHADER_PGM_RSRC2_ES';
  mmSPI_SHADER_USER_DATA_ES_0                              :Result:='mmSPI_SHADER_USER_DATA_ES_0';
  mmSPI_SHADER_USER_DATA_ES_1                              :Result:='mmSPI_SHADER_USER_DATA_ES_1';
  mmSPI_SHADER_USER_DATA_ES_2                              :Result:='mmSPI_SHADER_USER_DATA_ES_2';
  mmSPI_SHADER_USER_DATA_ES_3                              :Result:='mmSPI_SHADER_USER_DATA_ES_3';
  mmSPI_SHADER_USER_DATA_ES_4                              :Result:='mmSPI_SHADER_USER_DATA_ES_4';
  mmSPI_SHADER_USER_DATA_ES_5                              :Result:='mmSPI_SHADER_USER_DATA_ES_5';
  mmSPI_SHADER_USER_DATA_ES_6                              :Result:='mmSPI_SHADER_USER_DATA_ES_6';
  mmSPI_SHADER_USER_DATA_ES_7                              :Result:='mmSPI_SHADER_USER_DATA_ES_7';
  mmSPI_SHADER_USER_DATA_ES_8                              :Result:='mmSPI_SHADER_USER_DATA_ES_8';
  mmSPI_SHADER_USER_DATA_ES_9                              :Result:='mmSPI_SHADER_USER_DATA_ES_9';
  mmSPI_SHADER_USER_DATA_ES_10                             :Result:='mmSPI_SHADER_USER_DATA_ES_10';
  mmSPI_SHADER_USER_DATA_ES_11                             :Result:='mmSPI_SHADER_USER_DATA_ES_11';
  mmSPI_SHADER_USER_DATA_ES_12                             :Result:='mmSPI_SHADER_USER_DATA_ES_12';
  mmSPI_SHADER_USER_DATA_ES_13                             :Result:='mmSPI_SHADER_USER_DATA_ES_13';
  mmSPI_SHADER_USER_DATA_ES_14                             :Result:='mmSPI_SHADER_USER_DATA_ES_14';
  mmSPI_SHADER_USER_DATA_ES_15                             :Result:='mmSPI_SHADER_USER_DATA_ES_15';
  mmSPI_SHADER_PGM_RSRC2_LS_ES                             :Result:='mmSPI_SHADER_PGM_RSRC2_LS_ES';
  mmSPI_SHADER_TBA_LO_HS                                   :Result:='mmSPI_SHADER_TBA_LO_HS';
  mmSPI_SHADER_TBA_HI_HS                                   :Result:='mmSPI_SHADER_TBA_HI_HS';
  mmSPI_SHADER_TMA_LO_HS                                   :Result:='mmSPI_SHADER_TMA_LO_HS';
  mmSPI_SHADER_TMA_HI_HS                                   :Result:='mmSPI_SHADER_TMA_HI_HS';
  mmSPI_SHADER_PGM_RSRC3_HS                                :Result:='mmSPI_SHADER_PGM_RSRC3_HS';
  mmSPI_SHADER_PGM_LO_HS                                   :Result:='mmSPI_SHADER_PGM_LO_HS';
  mmSPI_SHADER_PGM_HI_HS                                   :Result:='mmSPI_SHADER_PGM_HI_HS';
  mmSPI_SHADER_PGM_RSRC1_HS                                :Result:='mmSPI_SHADER_PGM_RSRC1_HS';
  mmSPI_SHADER_PGM_RSRC2_HS                                :Result:='mmSPI_SHADER_PGM_RSRC2_HS';
  mmSPI_SHADER_USER_DATA_HS_0                              :Result:='mmSPI_SHADER_USER_DATA_HS_0';
  mmSPI_SHADER_USER_DATA_HS_1                              :Result:='mmSPI_SHADER_USER_DATA_HS_1';
  mmSPI_SHADER_USER_DATA_HS_2                              :Result:='mmSPI_SHADER_USER_DATA_HS_2';
  mmSPI_SHADER_USER_DATA_HS_3                              :Result:='mmSPI_SHADER_USER_DATA_HS_3';
  mmSPI_SHADER_USER_DATA_HS_4                              :Result:='mmSPI_SHADER_USER_DATA_HS_4';
  mmSPI_SHADER_USER_DATA_HS_5                              :Result:='mmSPI_SHADER_USER_DATA_HS_5';
  mmSPI_SHADER_USER_DATA_HS_6                              :Result:='mmSPI_SHADER_USER_DATA_HS_6';
  mmSPI_SHADER_USER_DATA_HS_7                              :Result:='mmSPI_SHADER_USER_DATA_HS_7';
  mmSPI_SHADER_USER_DATA_HS_8                              :Result:='mmSPI_SHADER_USER_DATA_HS_8';
  mmSPI_SHADER_USER_DATA_HS_9                              :Result:='mmSPI_SHADER_USER_DATA_HS_9';
  mmSPI_SHADER_USER_DATA_HS_10                             :Result:='mmSPI_SHADER_USER_DATA_HS_10';
  mmSPI_SHADER_USER_DATA_HS_11                             :Result:='mmSPI_SHADER_USER_DATA_HS_11';
  mmSPI_SHADER_USER_DATA_HS_12                             :Result:='mmSPI_SHADER_USER_DATA_HS_12';
  mmSPI_SHADER_USER_DATA_HS_13                             :Result:='mmSPI_SHADER_USER_DATA_HS_13';
  mmSPI_SHADER_USER_DATA_HS_14                             :Result:='mmSPI_SHADER_USER_DATA_HS_14';
  mmSPI_SHADER_USER_DATA_HS_15                             :Result:='mmSPI_SHADER_USER_DATA_HS_15';
  mmSPI_SHADER_PGM_RSRC2_LS_HS                             :Result:='mmSPI_SHADER_PGM_RSRC2_LS_HS';
  mmSPI_SHADER_TBA_LO_LS                                   :Result:='mmSPI_SHADER_TBA_LO_LS';
  mmSPI_SHADER_TBA_HI_LS                                   :Result:='mmSPI_SHADER_TBA_HI_LS';
  mmSPI_SHADER_TMA_LO_LS                                   :Result:='mmSPI_SHADER_TMA_LO_LS';
  mmSPI_SHADER_TMA_HI_LS                                   :Result:='mmSPI_SHADER_TMA_HI_LS';
  mmSPI_SHADER_PGM_RSRC3_LS                                :Result:='mmSPI_SHADER_PGM_RSRC3_LS';
  mmSPI_SHADER_PGM_LO_LS                                   :Result:='mmSPI_SHADER_PGM_LO_LS';
  mmSPI_SHADER_PGM_HI_LS                                   :Result:='mmSPI_SHADER_PGM_HI_LS';
  mmSPI_SHADER_PGM_RSRC1_LS                                :Result:='mmSPI_SHADER_PGM_RSRC1_LS';
  mmSPI_SHADER_PGM_RSRC2_LS                                :Result:='mmSPI_SHADER_PGM_RSRC2_LS';
  mmSPI_SHADER_USER_DATA_LS_0                              :Result:='mmSPI_SHADER_USER_DATA_LS_0';
  mmSPI_SHADER_USER_DATA_LS_1                              :Result:='mmSPI_SHADER_USER_DATA_LS_1';
  mmSPI_SHADER_USER_DATA_LS_2                              :Result:='mmSPI_SHADER_USER_DATA_LS_2';
  mmSPI_SHADER_USER_DATA_LS_3                              :Result:='mmSPI_SHADER_USER_DATA_LS_3';
  mmSPI_SHADER_USER_DATA_LS_4                              :Result:='mmSPI_SHADER_USER_DATA_LS_4';
  mmSPI_SHADER_USER_DATA_LS_5                              :Result:='mmSPI_SHADER_USER_DATA_LS_5';
  mmSPI_SHADER_USER_DATA_LS_6                              :Result:='mmSPI_SHADER_USER_DATA_LS_6';
  mmSPI_SHADER_USER_DATA_LS_7                              :Result:='mmSPI_SHADER_USER_DATA_LS_7';
  mmSPI_SHADER_USER_DATA_LS_8                              :Result:='mmSPI_SHADER_USER_DATA_LS_8';
  mmSPI_SHADER_USER_DATA_LS_9                              :Result:='mmSPI_SHADER_USER_DATA_LS_9';
  mmSPI_SHADER_USER_DATA_LS_10                             :Result:='mmSPI_SHADER_USER_DATA_LS_10';
  mmSPI_SHADER_USER_DATA_LS_11                             :Result:='mmSPI_SHADER_USER_DATA_LS_11';
  mmSPI_SHADER_USER_DATA_LS_12                             :Result:='mmSPI_SHADER_USER_DATA_LS_12';
  mmSPI_SHADER_USER_DATA_LS_13                             :Result:='mmSPI_SHADER_USER_DATA_LS_13';
  mmSPI_SHADER_USER_DATA_LS_14                             :Result:='mmSPI_SHADER_USER_DATA_LS_14';
  mmSPI_SHADER_USER_DATA_LS_15                             :Result:='mmSPI_SHADER_USER_DATA_LS_15';
  mmCOMPUTE_DISPATCH_INITIATOR                             :Result:='mmCOMPUTE_DISPATCH_INITIATOR';
  mmCOMPUTE_DIM_X                                          :Result:='mmCOMPUTE_DIM_X';
  mmCOMPUTE_DIM_Y                                          :Result:='mmCOMPUTE_DIM_Y';
  mmCOMPUTE_DIM_Z                                          :Result:='mmCOMPUTE_DIM_Z';
  mmCOMPUTE_START_X                                        :Result:='mmCOMPUTE_START_X';
  mmCOMPUTE_START_Y                                        :Result:='mmCOMPUTE_START_Y';
  mmCOMPUTE_START_Z                                        :Result:='mmCOMPUTE_START_Z';
  mmCOMPUTE_NUM_THREAD_X                                   :Result:='mmCOMPUTE_NUM_THREAD_X';
  mmCOMPUTE_NUM_THREAD_Y                                   :Result:='mmCOMPUTE_NUM_THREAD_Y';
  mmCOMPUTE_NUM_THREAD_Z                                   :Result:='mmCOMPUTE_NUM_THREAD_Z';
  mmCOMPUTE_PIPELINESTAT_ENABLE                            :Result:='mmCOMPUTE_PIPELINESTAT_ENABLE';
  mmCOMPUTE_PERFCOUNT_ENABLE                               :Result:='mmCOMPUTE_PERFCOUNT_ENABLE';
  mmCOMPUTE_PGM_LO                                         :Result:='mmCOMPUTE_PGM_LO';
  mmCOMPUTE_PGM_HI                                         :Result:='mmCOMPUTE_PGM_HI';
  mmCOMPUTE_TBA_LO                                         :Result:='mmCOMPUTE_TBA_LO';
  mmCOMPUTE_TBA_HI                                         :Result:='mmCOMPUTE_TBA_HI';
  mmCOMPUTE_TMA_LO                                         :Result:='mmCOMPUTE_TMA_LO';
  mmCOMPUTE_TMA_HI                                         :Result:='mmCOMPUTE_TMA_HI';
  mmCOMPUTE_PGM_RSRC1                                      :Result:='mmCOMPUTE_PGM_RSRC1';
  mmCOMPUTE_PGM_RSRC2                                      :Result:='mmCOMPUTE_PGM_RSRC2';
  mmCOMPUTE_VMID                                           :Result:='mmCOMPUTE_VMID';
  mmCOMPUTE_RESOURCE_LIMITS                                :Result:='mmCOMPUTE_RESOURCE_LIMITS';
  mmCOMPUTE_STATIC_THREAD_MGMT_SE0                         :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE0';
  mmCOMPUTE_STATIC_THREAD_MGMT_SE1                         :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE1';
  mmCOMPUTE_TMPRING_SIZE                                   :Result:='mmCOMPUTE_TMPRING_SIZE';
  mmCOMPUTE_STATIC_THREAD_MGMT_SE2                         :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE2';
  mmCOMPUTE_STATIC_THREAD_MGMT_SE3                         :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE3';
  mmCOMPUTE_RESTART_X                                      :Result:='mmCOMPUTE_RESTART_X';
  mmCOMPUTE_RESTART_Y                                      :Result:='mmCOMPUTE_RESTART_Y';
  mmCOMPUTE_RESTART_Z                                      :Result:='mmCOMPUTE_RESTART_Z';
  mmCOMPUTE_THREAD_TRACE_ENABLE                            :Result:='mmCOMPUTE_THREAD_TRACE_ENABLE';
  mmCOMPUTE_MISC_RESERVED                                  :Result:='mmCOMPUTE_MISC_RESERVED';
  mmCOMPUTE_DISPATCH_ID                                    :Result:='mmCOMPUTE_DISPATCH_ID';
  mmCOMPUTE_THREADGROUP_ID                                 :Result:='mmCOMPUTE_THREADGROUP_ID';
  mmCOMPUTE_RELAUNCH                                       :Result:='mmCOMPUTE_RELAUNCH';
  mmCOMPUTE_WAVE_RESTORE_ADDR_LO                           :Result:='mmCOMPUTE_WAVE_RESTORE_ADDR_LO';
  mmCOMPUTE_WAVE_RESTORE_ADDR_HI                           :Result:='mmCOMPUTE_WAVE_RESTORE_ADDR_HI';
  mmCOMPUTE_WAVE_RESTORE_CONTROL                           :Result:='mmCOMPUTE_WAVE_RESTORE_CONTROL';
  mmCOMPUTE_USER_DATA_0                                    :Result:='mmCOMPUTE_USER_DATA_0';
  mmCOMPUTE_USER_DATA_1                                    :Result:='mmCOMPUTE_USER_DATA_1';
  mmCOMPUTE_USER_DATA_2                                    :Result:='mmCOMPUTE_USER_DATA_2';
  mmCOMPUTE_USER_DATA_3                                    :Result:='mmCOMPUTE_USER_DATA_3';
  mmCOMPUTE_USER_DATA_4                                    :Result:='mmCOMPUTE_USER_DATA_4';
  mmCOMPUTE_USER_DATA_5                                    :Result:='mmCOMPUTE_USER_DATA_5';
  mmCOMPUTE_USER_DATA_6                                    :Result:='mmCOMPUTE_USER_DATA_6';
  mmCOMPUTE_USER_DATA_7                                    :Result:='mmCOMPUTE_USER_DATA_7';
  mmCOMPUTE_USER_DATA_8                                    :Result:='mmCOMPUTE_USER_DATA_8';
  mmCOMPUTE_USER_DATA_9                                    :Result:='mmCOMPUTE_USER_DATA_9';
  mmCOMPUTE_USER_DATA_10                                   :Result:='mmCOMPUTE_USER_DATA_10';
  mmCOMPUTE_USER_DATA_11                                   :Result:='mmCOMPUTE_USER_DATA_11';
  mmCOMPUTE_USER_DATA_12                                   :Result:='mmCOMPUTE_USER_DATA_12';
  mmCOMPUTE_USER_DATA_13                                   :Result:='mmCOMPUTE_USER_DATA_13';
  mmCOMPUTE_USER_DATA_14                                   :Result:='mmCOMPUTE_USER_DATA_14';
  mmCOMPUTE_USER_DATA_15                                   :Result:='mmCOMPUTE_USER_DATA_15';
  mmCOMPUTE_NOWHERE                                        :Result:='mmCOMPUTE_NOWHERE';
  mmCP_DFY_CNTL                                            :Result:='mmCP_DFY_CNTL';
  mmCP_DFY_STAT                                            :Result:='mmCP_DFY_STAT';
  mmCP_DFY_ADDR_HI                                         :Result:='mmCP_DFY_ADDR_HI';
  mmCP_DFY_ADDR_LO                                         :Result:='mmCP_DFY_ADDR_LO';
  mmCP_DFY_DATA_0                                          :Result:='mmCP_DFY_DATA_0';
  mmCP_DFY_DATA_1                                          :Result:='mmCP_DFY_DATA_1';
  mmCP_DFY_DATA_2                                          :Result:='mmCP_DFY_DATA_2';
  mmCP_DFY_DATA_3                                          :Result:='mmCP_DFY_DATA_3';
  mmCP_DFY_DATA_4                                          :Result:='mmCP_DFY_DATA_4';
  mmCP_DFY_DATA_5                                          :Result:='mmCP_DFY_DATA_5';
  mmCP_DFY_DATA_6                                          :Result:='mmCP_DFY_DATA_6';
  mmCP_DFY_DATA_7                                          :Result:='mmCP_DFY_DATA_7';
  mmCP_DFY_DATA_8                                          :Result:='mmCP_DFY_DATA_8';
  mmCP_DFY_DATA_9                                          :Result:='mmCP_DFY_DATA_9';
  mmCP_DFY_DATA_10                                         :Result:='mmCP_DFY_DATA_10';
  mmCP_DFY_DATA_11                                         :Result:='mmCP_DFY_DATA_11';
  mmCP_DFY_DATA_12                                         :Result:='mmCP_DFY_DATA_12';
  mmCP_DFY_DATA_13                                         :Result:='mmCP_DFY_DATA_13';
  mmCP_DFY_DATA_14                                         :Result:='mmCP_DFY_DATA_14';
  mmCP_DFY_DATA_15                                         :Result:='mmCP_DFY_DATA_15';
  mmCP_DFY_CMD                                             :Result:='mmCP_DFY_CMD';
  mmCP_CPC_MGCG_SYNC_CNTL                                  :Result:='mmCP_CPC_MGCG_SYNC_CNTL';
  mmCP_VIRT_STATUS                                         :Result:='mmCP_VIRT_STATUS';
  mmCP_RB0_BASE                                            :Result:='mmCP_RB0_BASE';
  mmCP_RB0_CNTL                                            :Result:='mmCP_RB0_CNTL';
  mmCP_RB_RPTR_WR                                          :Result:='mmCP_RB_RPTR_WR';
  mmCP_RB0_RPTR_ADDR                                       :Result:='mmCP_RB0_RPTR_ADDR';
  mmCP_RB0_RPTR_ADDR_HI                                    :Result:='mmCP_RB0_RPTR_ADDR_HI';
  mmCP_RB0_WPTR                                            :Result:='mmCP_RB0_WPTR';
  mmCP_RB_WPTR_POLL_ADDR_LO                                :Result:='mmCP_RB_WPTR_POLL_ADDR_LO';
  mmCP_RB_WPTR_POLL_ADDR_HI                                :Result:='mmCP_RB_WPTR_POLL_ADDR_HI';
  mmCP_INT_CNTL                                            :Result:='mmCP_INT_CNTL';
  mmCP_INT_STATUS                                          :Result:='mmCP_INT_STATUS';
  mmCP_DEVICE_ID                                           :Result:='mmCP_DEVICE_ID';
  mmCP_ME0_PIPE_PRIORITY_CNTS                              :Result:='mmCP_ME0_PIPE_PRIORITY_CNTS';
  mmCP_ME0_PIPE0_PRIORITY                                  :Result:='mmCP_ME0_PIPE0_PRIORITY';
  mmCP_ME0_PIPE1_PRIORITY                                  :Result:='mmCP_ME0_PIPE1_PRIORITY';
  mmCP_ME0_PIPE2_PRIORITY                                  :Result:='mmCP_ME0_PIPE2_PRIORITY';
  mmCP_ENDIAN_SWAP                                         :Result:='mmCP_ENDIAN_SWAP';
  mmCP_RB_VMID                                             :Result:='mmCP_RB_VMID';
  mmCP_ME0_PIPE0_VMID                                      :Result:='mmCP_ME0_PIPE0_VMID';
  mmCP_ME0_PIPE1_VMID                                      :Result:='mmCP_ME0_PIPE1_VMID';
  mmCP_RB_DOORBELL_CONTROL                                 :Result:='mmCP_RB_DOORBELL_CONTROL';
  mmCP_RB_DOORBELL_RANGE_LOWER                             :Result:='mmCP_RB_DOORBELL_RANGE_LOWER';
  mmCP_RB_DOORBELL_RANGE_UPPER                             :Result:='mmCP_RB_DOORBELL_RANGE_UPPER';
  mmCP_MEC_DOORBELL_RANGE_LOWER                            :Result:='mmCP_MEC_DOORBELL_RANGE_LOWER';
  mmCP_MEC_DOORBELL_RANGE_UPPER                            :Result:='mmCP_MEC_DOORBELL_RANGE_UPPER';
  mmCP_RB1_BASE                                            :Result:='mmCP_RB1_BASE';
  mmCP_RB1_CNTL                                            :Result:='mmCP_RB1_CNTL';
  mmCP_RB1_RPTR_ADDR                                       :Result:='mmCP_RB1_RPTR_ADDR';
  mmCP_RB1_RPTR_ADDR_HI                                    :Result:='mmCP_RB1_RPTR_ADDR_HI';
  mmCP_RB1_WPTR                                            :Result:='mmCP_RB1_WPTR';
  mmCP_RB2_BASE                                            :Result:='mmCP_RB2_BASE';
  mmCP_RB2_CNTL                                            :Result:='mmCP_RB2_CNTL';
  mmCP_RB2_RPTR_ADDR                                       :Result:='mmCP_RB2_RPTR_ADDR';
  mmCP_RB2_RPTR_ADDR_HI                                    :Result:='mmCP_RB2_RPTR_ADDR_HI';
  mmCP_RB2_WPTR                                            :Result:='mmCP_RB2_WPTR';
  mmCP_INT_CNTL_RING0                                      :Result:='mmCP_INT_CNTL_RING0';
  mmCP_INT_CNTL_RING1                                      :Result:='mmCP_INT_CNTL_RING1';
  mmCP_INT_CNTL_RING2                                      :Result:='mmCP_INT_CNTL_RING2';
  mmCP_INT_STATUS_RING0                                    :Result:='mmCP_INT_STATUS_RING0';
  mmCP_INT_STATUS_RING1                                    :Result:='mmCP_INT_STATUS_RING1';
  mmCP_INT_STATUS_RING2                                    :Result:='mmCP_INT_STATUS_RING2';
  mmCP_PWR_CNTL                                            :Result:='mmCP_PWR_CNTL';
  mmCP_MEM_SLP_CNTL                                        :Result:='mmCP_MEM_SLP_CNTL';
  mmCP_ECC_FIRSTOCCURRENCE                                 :Result:='mmCP_ECC_FIRSTOCCURRENCE';
  mmCP_ECC_FIRSTOCCURRENCE_RING0                           :Result:='mmCP_ECC_FIRSTOCCURRENCE_RING0';
  mmCP_ECC_FIRSTOCCURRENCE_RING1                           :Result:='mmCP_ECC_FIRSTOCCURRENCE_RING1';
  mmCP_ECC_FIRSTOCCURRENCE_RING2                           :Result:='mmCP_ECC_FIRSTOCCURRENCE_RING2';
  mmGB_EDC_MODE                                            :Result:='mmGB_EDC_MODE';
  mmCP_DEBUG                                               :Result:='mmCP_DEBUG';
  mmCP_PQ_WPTR_POLL_CNTL                                   :Result:='mmCP_PQ_WPTR_POLL_CNTL';
  mmCP_PQ_WPTR_POLL_CNTL1                                  :Result:='mmCP_PQ_WPTR_POLL_CNTL1';
  mmCP_ME1_PIPE0_INT_CNTL                                  :Result:='mmCP_ME1_PIPE0_INT_CNTL';
  mmCP_ME1_PIPE1_INT_CNTL                                  :Result:='mmCP_ME1_PIPE1_INT_CNTL';
  mmCP_ME1_PIPE2_INT_CNTL                                  :Result:='mmCP_ME1_PIPE2_INT_CNTL';
  mmCP_ME1_PIPE3_INT_CNTL                                  :Result:='mmCP_ME1_PIPE3_INT_CNTL';
  mmCP_ME2_PIPE0_INT_CNTL                                  :Result:='mmCP_ME2_PIPE0_INT_CNTL';
  mmCP_ME2_PIPE1_INT_CNTL                                  :Result:='mmCP_ME2_PIPE1_INT_CNTL';
  mmCP_ME2_PIPE2_INT_CNTL                                  :Result:='mmCP_ME2_PIPE2_INT_CNTL';
  mmCP_ME2_PIPE3_INT_CNTL                                  :Result:='mmCP_ME2_PIPE3_INT_CNTL';
  mmCP_ME1_PIPE0_INT_STATUS                                :Result:='mmCP_ME1_PIPE0_INT_STATUS';
  mmCP_ME1_PIPE1_INT_STATUS                                :Result:='mmCP_ME1_PIPE1_INT_STATUS';
  mmCP_ME1_PIPE2_INT_STATUS                                :Result:='mmCP_ME1_PIPE2_INT_STATUS';
  mmCP_ME1_PIPE3_INT_STATUS                                :Result:='mmCP_ME1_PIPE3_INT_STATUS';
  mmCP_ME2_PIPE0_INT_STATUS                                :Result:='mmCP_ME2_PIPE0_INT_STATUS';
  mmCP_ME2_PIPE1_INT_STATUS                                :Result:='mmCP_ME2_PIPE1_INT_STATUS';
  mmCP_ME2_PIPE2_INT_STATUS                                :Result:='mmCP_ME2_PIPE2_INT_STATUS';
  mmCP_ME2_PIPE3_INT_STATUS                                :Result:='mmCP_ME2_PIPE3_INT_STATUS';
  mmCP_ME1_INT_STAT_DEBUG                                  :Result:='mmCP_ME1_INT_STAT_DEBUG';
  mmCP_ME2_INT_STAT_DEBUG                                  :Result:='mmCP_ME2_INT_STAT_DEBUG';
  mmCC_GC_EDC_CONFIG                                       :Result:='mmCC_GC_EDC_CONFIG';
  mmCP_ME1_PIPE_PRIORITY_CNTS                              :Result:='mmCP_ME1_PIPE_PRIORITY_CNTS';
  mmCP_ME1_PIPE0_PRIORITY                                  :Result:='mmCP_ME1_PIPE0_PRIORITY';
  mmCP_ME1_PIPE1_PRIORITY                                  :Result:='mmCP_ME1_PIPE1_PRIORITY';
  mmCP_ME1_PIPE2_PRIORITY                                  :Result:='mmCP_ME1_PIPE2_PRIORITY';
  mmCP_ME1_PIPE3_PRIORITY                                  :Result:='mmCP_ME1_PIPE3_PRIORITY';
  mmCP_ME2_PIPE_PRIORITY_CNTS                              :Result:='mmCP_ME2_PIPE_PRIORITY_CNTS';
  mmCP_ME2_PIPE0_PRIORITY                                  :Result:='mmCP_ME2_PIPE0_PRIORITY';
  mmCP_ME2_PIPE1_PRIORITY                                  :Result:='mmCP_ME2_PIPE1_PRIORITY';
  mmCP_ME2_PIPE2_PRIORITY                                  :Result:='mmCP_ME2_PIPE2_PRIORITY';
  mmCP_ME2_PIPE3_PRIORITY                                  :Result:='mmCP_ME2_PIPE3_PRIORITY';
  mmCP_CE_PRGRM_CNTR_START                                 :Result:='mmCP_CE_PRGRM_CNTR_START';
  mmCP_PFP_PRGRM_CNTR_START                                :Result:='mmCP_PFP_PRGRM_CNTR_START';
  mmCP_ME_PRGRM_CNTR_START                                 :Result:='mmCP_ME_PRGRM_CNTR_START';
  mmCP_MEC1_PRGRM_CNTR_START                               :Result:='mmCP_MEC1_PRGRM_CNTR_START';
  mmCP_MEC2_PRGRM_CNTR_START                               :Result:='mmCP_MEC2_PRGRM_CNTR_START';
  mmCP_CE_INTR_ROUTINE_START                               :Result:='mmCP_CE_INTR_ROUTINE_START';
  mmCP_PFP_INTR_ROUTINE_START                              :Result:='mmCP_PFP_INTR_ROUTINE_START';
  mmCP_ME_INTR_ROUTINE_START                               :Result:='mmCP_ME_INTR_ROUTINE_START';
  mmCP_MEC1_INTR_ROUTINE_START                             :Result:='mmCP_MEC1_INTR_ROUTINE_START';
  mmCP_MEC2_INTR_ROUTINE_START                             :Result:='mmCP_MEC2_INTR_ROUTINE_START';
  mmCP_CONTEXT_CNTL                                        :Result:='mmCP_CONTEXT_CNTL';
  mmCP_MAX_CONTEXT                                         :Result:='mmCP_MAX_CONTEXT';
  mmCP_IQ_WAIT_TIME1                                       :Result:='mmCP_IQ_WAIT_TIME1';
  mmCP_IQ_WAIT_TIME2                                       :Result:='mmCP_IQ_WAIT_TIME2';
  mmCP_RB0_BASE_HI                                         :Result:='mmCP_RB0_BASE_HI';
  mmCP_RB1_BASE_HI                                         :Result:='mmCP_RB1_BASE_HI';
  mmCP_VMID_RESET                                          :Result:='mmCP_VMID_RESET';
  mmCPC_INT_CNTL                                           :Result:='mmCPC_INT_CNTL';
  mmCPC_INT_STATUS                                         :Result:='mmCPC_INT_STATUS';
  mmCP_VMID_PREEMPT                                        :Result:='mmCP_VMID_PREEMPT';
  mmCPC_INT_CNTX_ID                                        :Result:='mmCPC_INT_CNTX_ID';
  mmCP_PQ_STATUS                                           :Result:='mmCP_PQ_STATUS';
  mmCP_CPC_IC_BASE_LO                                      :Result:='mmCP_CPC_IC_BASE_LO';
  mmCP_CPC_IC_BASE_HI                                      :Result:='mmCP_CPC_IC_BASE_HI';
  mmCP_CPC_IC_BASE_CNTL                                    :Result:='mmCP_CPC_IC_BASE_CNTL';
  mmCP_CPC_IC_OP_CNTL                                      :Result:='mmCP_CPC_IC_OP_CNTL';
  mmCP_MEC1_F32_INT_DIS                                    :Result:='mmCP_MEC1_F32_INT_DIS';
  mmCP_MEC2_F32_INT_DIS                                    :Result:='mmCP_MEC2_F32_INT_DIS';
  mmCP_VMID_STATUS                                         :Result:='mmCP_VMID_STATUS';
  mmRLC_LB_CNTL                                            :Result:='mmRLC_LB_CNTL';
  mmRLC_SAVE_AND_RESTORE_BASE                              :Result:='mmRLC_SAVE_AND_RESTORE_BASE';
  mmRLC_LB_CNTR_MAX                                        :Result:='mmRLC_LB_CNTR_MAX';
  mmRLC_LB_CNTR_INIT                                       :Result:='mmRLC_LB_CNTR_INIT';
  mmRLC_DRIVER_CPDMA_STATUS                                :Result:='mmRLC_DRIVER_CPDMA_STATUS';
  mmRLC_DEBUG_SELECT                                       :Result:='mmRLC_DEBUG_SELECT';
  mmRLC_DEBUG                                              :Result:='mmRLC_DEBUG';
  mmRLC_GPU_CLOCK_COUNT_LSB                                :Result:='mmRLC_GPU_CLOCK_COUNT_LSB';
  mmRLC_GPU_CLOCK_COUNT_MSB                                :Result:='mmRLC_GPU_CLOCK_COUNT_MSB';
  mmRLC_CAPTURE_GPU_CLOCK_COUNT                            :Result:='mmRLC_CAPTURE_GPU_CLOCK_COUNT';
  mmRLC_MC_CNTL                                            :Result:='mmRLC_MC_CNTL';
  mmRLC_UCODE_CNTL                                         :Result:='mmRLC_UCODE_CNTL';
  mmRLC_STAT                                               :Result:='mmRLC_STAT';
  mmRLC_GPU_CLOCK_32_RES_SEL                               :Result:='mmRLC_GPU_CLOCK_32_RES_SEL';
  mmRLC_GPU_CLOCK_32                                       :Result:='mmRLC_GPU_CLOCK_32';
  mmRLC_SOFT_RESET_GPU                                     :Result:='mmRLC_SOFT_RESET_GPU';
  mmRLC_PG_CNTL                                            :Result:='mmRLC_PG_CNTL';
  mmRLC_MEM_SLP_CNTL                                       :Result:='mmRLC_MEM_SLP_CNTL';
  mmRLC_PERFMON_CNTL                                       :Result:='mmRLC_PERFMON_CNTL';
  mmRLC_PERFCOUNTER0_SELECT                                :Result:='mmRLC_PERFCOUNTER0_SELECT';
  mmRLC_PERFCOUNTER1_SELECT                                :Result:='mmRLC_PERFCOUNTER1_SELECT';
  mmCGTT_RLC_CLK_CTRL                                      :Result:='mmCGTT_RLC_CLK_CTRL';
  mmRLC_LOAD_BALANCE_CNTR                                  :Result:='mmRLC_LOAD_BALANCE_CNTR';
  mmRLC_CGTT_MGCG_OVERRIDE                                 :Result:='mmRLC_CGTT_MGCG_OVERRIDE';
  mmRLC_CGCG_CGLS_CTRL                                     :Result:='mmRLC_CGCG_CGLS_CTRL';
  mmRLC_CGCG_RAMP_CTRL                                     :Result:='mmRLC_CGCG_RAMP_CTRL';
  mmRLC_DYN_PG_STATUS                                      :Result:='mmRLC_DYN_PG_STATUS';
  mmRLC_DYN_PG_REQUEST                                     :Result:='mmRLC_DYN_PG_REQUEST';
  mmRLC_CU_STATUS                                          :Result:='mmRLC_CU_STATUS';
  mmRLC_LB_INIT_CU_MASK                                    :Result:='mmRLC_LB_INIT_CU_MASK';
  mmRLC_LB_ALWAYS_ACTIVE_CU_MASK                           :Result:='mmRLC_LB_ALWAYS_ACTIVE_CU_MASK';
  mmRLC_LB_PARAMS                                          :Result:='mmRLC_LB_PARAMS';
  mmRLC_THREAD1_DELAY                                      :Result:='mmRLC_THREAD1_DELAY';
  mmRLC_PG_ALWAYS_ON_CU_MASK                               :Result:='mmRLC_PG_ALWAYS_ON_CU_MASK';
  mmRLC_MAX_PG_CU                                          :Result:='mmRLC_MAX_PG_CU';
  mmRLC_AUTO_PG_CTRL                                       :Result:='mmRLC_AUTO_PG_CTRL';
  mmRLC_SMU_GRBM_REG_SAVE_CTRL                             :Result:='mmRLC_SMU_GRBM_REG_SAVE_CTRL';
  mmRLC_SMU_PG_CTRL                                        :Result:='mmRLC_SMU_PG_CTRL';
  mmRLC_SMU_PG_WAKE_UP_CTRL                                :Result:='mmRLC_SMU_PG_WAKE_UP_CTRL';
  mmRLC_SERDES_RD_MASTER_INDEX                             :Result:='mmRLC_SERDES_RD_MASTER_INDEX';
  mmRLC_SERDES_RD_DATA_0                                   :Result:='mmRLC_SERDES_RD_DATA_0';
  mmRLC_SERDES_RD_DATA_1                                   :Result:='mmRLC_SERDES_RD_DATA_1';
  mmRLC_SERDES_RD_DATA_2                                   :Result:='mmRLC_SERDES_RD_DATA_2';
  mmRLC_SERDES_WR_CTRL                                     :Result:='mmRLC_SERDES_WR_CTRL';
  mmRLC_SERDES_WR_DATA                                     :Result:='mmRLC_SERDES_WR_DATA';
  mmSPI_ARB_PRIORITY                                       :Result:='mmSPI_ARB_PRIORITY';
  mmSPI_ARB_CYCLES_0                                       :Result:='mmSPI_ARB_CYCLES_0';
  mmSPI_ARB_CYCLES_1                                       :Result:='mmSPI_ARB_CYCLES_1';
  mmSPI_CDBG_SYS_GFX                                       :Result:='mmSPI_CDBG_SYS_GFX';
  mmSPI_CDBG_SYS_HP3D                                      :Result:='mmSPI_CDBG_SYS_HP3D';
  mmSPI_CDBG_SYS_CS0                                       :Result:='mmSPI_CDBG_SYS_CS0';
  mmSPI_CDBG_SYS_CS1                                       :Result:='mmSPI_CDBG_SYS_CS1';
  mmSPI_WCL_PIPE_PERCENT_GFX                               :Result:='mmSPI_WCL_PIPE_PERCENT_GFX';
  mmSPI_WCL_PIPE_PERCENT_HP3D                              :Result:='mmSPI_WCL_PIPE_PERCENT_HP3D';
  mmSPI_WCL_PIPE_PERCENT_CS0                               :Result:='mmSPI_WCL_PIPE_PERCENT_CS0';
  mmSPI_WCL_PIPE_PERCENT_CS1                               :Result:='mmSPI_WCL_PIPE_PERCENT_CS1';
  mmSPI_WCL_PIPE_PERCENT_CS2                               :Result:='mmSPI_WCL_PIPE_PERCENT_CS2';
  mmSPI_WCL_PIPE_PERCENT_CS3                               :Result:='mmSPI_WCL_PIPE_PERCENT_CS3';
  mmSPI_WCL_PIPE_PERCENT_CS4                               :Result:='mmSPI_WCL_PIPE_PERCENT_CS4';
  mmSPI_WCL_PIPE_PERCENT_CS5                               :Result:='mmSPI_WCL_PIPE_PERCENT_CS5';
  mmSPI_WCL_PIPE_PERCENT_CS6                               :Result:='mmSPI_WCL_PIPE_PERCENT_CS6';
  mmSPI_WCL_PIPE_PERCENT_CS7                               :Result:='mmSPI_WCL_PIPE_PERCENT_CS7';
  mmSPI_GDBG_WAVE_CNTL                                     :Result:='mmSPI_GDBG_WAVE_CNTL';
  mmSPI_GDBG_TRAP_CONFIG                                   :Result:='mmSPI_GDBG_TRAP_CONFIG';
  mmSPI_GDBG_TRAP_MASK                                     :Result:='mmSPI_GDBG_TRAP_MASK';
  mmSPI_GDBG_TBA_LO                                        :Result:='mmSPI_GDBG_TBA_LO';
  mmSPI_GDBG_TBA_HI                                        :Result:='mmSPI_GDBG_TBA_HI';
  mmSPI_GDBG_TMA_LO                                        :Result:='mmSPI_GDBG_TMA_LO';
  mmSPI_GDBG_TMA_HI                                        :Result:='mmSPI_GDBG_TMA_HI';
  mmSPI_GDBG_TRAP_DATA0                                    :Result:='mmSPI_GDBG_TRAP_DATA0';
  mmSPI_GDBG_TRAP_DATA1                                    :Result:='mmSPI_GDBG_TRAP_DATA1';
  mmSPI_RESET_DEBUG                                        :Result:='mmSPI_RESET_DEBUG';
  mmSPI_COMPUTE_QUEUE_RESET                                :Result:='mmSPI_COMPUTE_QUEUE_RESET';
  mmSPI_RESOURCE_RESERVE_CU_0                              :Result:='mmSPI_RESOURCE_RESERVE_CU_0';
  mmSPI_RESOURCE_RESERVE_CU_1                              :Result:='mmSPI_RESOURCE_RESERVE_CU_1';
  mmSPI_RESOURCE_RESERVE_CU_2                              :Result:='mmSPI_RESOURCE_RESERVE_CU_2';
  mmSPI_RESOURCE_RESERVE_CU_3                              :Result:='mmSPI_RESOURCE_RESERVE_CU_3';
  mmSPI_RESOURCE_RESERVE_CU_4                              :Result:='mmSPI_RESOURCE_RESERVE_CU_4';
  mmSPI_RESOURCE_RESERVE_CU_5                              :Result:='mmSPI_RESOURCE_RESERVE_CU_5';
  mmSPI_RESOURCE_RESERVE_CU_6                              :Result:='mmSPI_RESOURCE_RESERVE_CU_6';
  mmSPI_RESOURCE_RESERVE_CU_7                              :Result:='mmSPI_RESOURCE_RESERVE_CU_7';
  mmSPI_RESOURCE_RESERVE_CU_8                              :Result:='mmSPI_RESOURCE_RESERVE_CU_8';
  mmSPI_RESOURCE_RESERVE_CU_9                              :Result:='mmSPI_RESOURCE_RESERVE_CU_9';
  mmSPI_RESOURCE_RESERVE_EN_CU_0                           :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_0';
  mmSPI_RESOURCE_RESERVE_EN_CU_1                           :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_1';
  mmSPI_RESOURCE_RESERVE_EN_CU_2                           :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_2';
  mmSPI_RESOURCE_RESERVE_EN_CU_3                           :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_3';
  mmSPI_RESOURCE_RESERVE_EN_CU_4                           :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_4';
  mmSPI_RESOURCE_RESERVE_EN_CU_5                           :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_5';
  mmSPI_RESOURCE_RESERVE_EN_CU_6                           :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_6';
  mmSPI_RESOURCE_RESERVE_EN_CU_7                           :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_7';
  mmSPI_RESOURCE_RESERVE_EN_CU_8                           :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_8';
  mmSPI_RESOURCE_RESERVE_EN_CU_9                           :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_9';
  mmSPI_RESOURCE_RESERVE_CU_10                             :Result:='mmSPI_RESOURCE_RESERVE_CU_10';
  mmSPI_RESOURCE_RESERVE_CU_11                             :Result:='mmSPI_RESOURCE_RESERVE_CU_11';
  mmSPI_RESOURCE_RESERVE_EN_CU_10                          :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_10';
  mmSPI_RESOURCE_RESERVE_EN_CU_11                          :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_11';
  mmSPI_RESOURCE_RESERVE_CU_12                             :Result:='mmSPI_RESOURCE_RESERVE_CU_12';
  mmSPI_RESOURCE_RESERVE_CU_13                             :Result:='mmSPI_RESOURCE_RESERVE_CU_13';
  mmSPI_RESOURCE_RESERVE_CU_14                             :Result:='mmSPI_RESOURCE_RESERVE_CU_14';
  mmSPI_RESOURCE_RESERVE_CU_15                             :Result:='mmSPI_RESOURCE_RESERVE_CU_15';
  mmSPI_RESOURCE_RESERVE_EN_CU_12                          :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_12';
  mmSPI_RESOURCE_RESERVE_EN_CU_13                          :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_13';
  mmSPI_RESOURCE_RESERVE_EN_CU_14                          :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_14';
  mmSPI_RESOURCE_RESERVE_EN_CU_15                          :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_15';
  mmSPI_COMPUTE_WF_CTX_SAVE                                :Result:='mmSPI_COMPUTE_WF_CTX_SAVE';
  mmCP_HPD_ROQ_OFFSETS                                     :Result:='mmCP_HPD_ROQ_OFFSETS';
  mmCP_HPD_STATUS0                                         :Result:='mmCP_HPD_STATUS0';
  mmCP_MQD_BASE_ADDR                                       :Result:='mmCP_MQD_BASE_ADDR';
  mmCP_MQD_BASE_ADDR_HI                                    :Result:='mmCP_MQD_BASE_ADDR_HI';
  mmCP_HQD_ACTIVE                                          :Result:='mmCP_HQD_ACTIVE';
  mmCP_HQD_VMID                                            :Result:='mmCP_HQD_VMID';
  mmCP_HQD_PERSISTENT_STATE                                :Result:='mmCP_HQD_PERSISTENT_STATE';
  mmCP_HQD_PIPE_PRIORITY                                   :Result:='mmCP_HQD_PIPE_PRIORITY';
  mmCP_HQD_QUEUE_PRIORITY                                  :Result:='mmCP_HQD_QUEUE_PRIORITY';
  mmCP_HQD_QUANTUM                                         :Result:='mmCP_HQD_QUANTUM';
  mmCP_HQD_PQ_BASE                                         :Result:='mmCP_HQD_PQ_BASE';
  mmCP_HQD_PQ_BASE_HI                                      :Result:='mmCP_HQD_PQ_BASE_HI';
  mmCP_HQD_PQ_RPTR                                         :Result:='mmCP_HQD_PQ_RPTR';
  mmCP_HQD_PQ_RPTR_REPORT_ADDR                             :Result:='mmCP_HQD_PQ_RPTR_REPORT_ADDR';
  mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                          :Result:='mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI';
  mmCP_HQD_PQ_WPTR_POLL_ADDR                               :Result:='mmCP_HQD_PQ_WPTR_POLL_ADDR';
  mmCP_HQD_PQ_WPTR_POLL_ADDR_HI                            :Result:='mmCP_HQD_PQ_WPTR_POLL_ADDR_HI';
  mmCP_HQD_PQ_DOORBELL_CONTROL                             :Result:='mmCP_HQD_PQ_DOORBELL_CONTROL';
  mmCP_HQD_PQ_WPTR                                         :Result:='mmCP_HQD_PQ_WPTR';
  mmCP_HQD_PQ_CONTROL                                      :Result:='mmCP_HQD_PQ_CONTROL';
  mmCP_HQD_IB_BASE_ADDR                                    :Result:='mmCP_HQD_IB_BASE_ADDR';
  mmCP_HQD_IB_BASE_ADDR_HI                                 :Result:='mmCP_HQD_IB_BASE_ADDR_HI';
  mmCP_HQD_IB_RPTR                                         :Result:='mmCP_HQD_IB_RPTR';
  mmCP_HQD_IB_CONTROL                                      :Result:='mmCP_HQD_IB_CONTROL';
  mmCP_HQD_IQ_TIMER                                        :Result:='mmCP_HQD_IQ_TIMER';
  mmCP_HQD_IQ_RPTR                                         :Result:='mmCP_HQD_IQ_RPTR';
  mmCP_HQD_DEQUEUE_REQUEST                                 :Result:='mmCP_HQD_DEQUEUE_REQUEST';
  mmCP_HQD_DMA_OFFLOAD                                     :Result:='mmCP_HQD_DMA_OFFLOAD';
  mmCP_HQD_SEMA_CMD                                        :Result:='mmCP_HQD_SEMA_CMD';
  mmCP_HQD_MSG_TYPE                                        :Result:='mmCP_HQD_MSG_TYPE';
  mmCP_HQD_ATOMIC0_PREOP_LO                                :Result:='mmCP_HQD_ATOMIC0_PREOP_LO';
  mmCP_HQD_ATOMIC0_PREOP_HI                                :Result:='mmCP_HQD_ATOMIC0_PREOP_HI';
  mmCP_HQD_ATOMIC1_PREOP_LO                                :Result:='mmCP_HQD_ATOMIC1_PREOP_LO';
  mmCP_HQD_ATOMIC1_PREOP_HI                                :Result:='mmCP_HQD_ATOMIC1_PREOP_HI';
  mmCP_HQD_HQ_SCHEDULER0                                   :Result:='mmCP_HQD_HQ_SCHEDULER0';
  mmCP_HQD_HQ_SCHEDULER1                                   :Result:='mmCP_HQD_HQ_SCHEDULER1';
  mmCP_MQD_CONTROL                                         :Result:='mmCP_MQD_CONTROL';
  mmCP_HQD_HQ_STATUS1                                      :Result:='mmCP_HQD_HQ_STATUS1';
  mmCP_HQD_HQ_CONTROL1                                     :Result:='mmCP_HQD_HQ_CONTROL1';
  mmCP_HQD_EOP_BASE_ADDR                                   :Result:='mmCP_HQD_EOP_BASE_ADDR';
  mmCP_HQD_EOP_BASE_ADDR_HI                                :Result:='mmCP_HQD_EOP_BASE_ADDR_HI';
  mmCP_HQD_EOP_CONTROL                                     :Result:='mmCP_HQD_EOP_CONTROL';
  mmCP_HQD_EOP_RPTR                                        :Result:='mmCP_HQD_EOP_RPTR';
  mmCP_HQD_EOP_WPTR                                        :Result:='mmCP_HQD_EOP_WPTR';
  mmCP_HQD_EOP_EVENTS                                      :Result:='mmCP_HQD_EOP_EVENTS';
  mmCP_HQD_CTX_SAVE_BASE_ADDR_LO                           :Result:='mmCP_HQD_CTX_SAVE_BASE_ADDR_LO';
  mmCP_HQD_CTX_SAVE_BASE_ADDR_HI                           :Result:='mmCP_HQD_CTX_SAVE_BASE_ADDR_HI';
  mmCP_HQD_CTX_SAVE_CONTROL                                :Result:='mmCP_HQD_CTX_SAVE_CONTROL';
  mmCP_HQD_CNTL_STACK_OFFSET                               :Result:='mmCP_HQD_CNTL_STACK_OFFSET';
  mmCP_HQD_CNTL_STACK_SIZE                                 :Result:='mmCP_HQD_CNTL_STACK_SIZE';
  mmCP_HQD_WG_STATE_OFFSET                                 :Result:='mmCP_HQD_WG_STATE_OFFSET';
  mmCP_HQD_CTX_SAVE_SIZE                                   :Result:='mmCP_HQD_CTX_SAVE_SIZE';
  mmCP_HQD_GDS_RESOURCE_STATE                              :Result:='mmCP_HQD_GDS_RESOURCE_STATE';
  mmCP_HQD_ERROR                                           :Result:='mmCP_HQD_ERROR';
  mmCP_HQD_EOP_WPTR_MEM                                    :Result:='mmCP_HQD_EOP_WPTR_MEM';
  mmCP_HQD_EOP_DONES                                       :Result:='mmCP_HQD_EOP_DONES';
  mmDIDT_IND_INDEX                                         :Result:='mmDIDT_IND_INDEX';
  mmDIDT_IND_DATA                                          :Result:='mmDIDT_IND_DATA';
  mmGC_CAC_CGTT_CLK_CTRL                                   :Result:='mmGC_CAC_CGTT_CLK_CTRL';
  mmSE_CAC_CGTT_CLK_CTRL                                   :Result:='mmSE_CAC_CGTT_CLK_CTRL';
  mmGC_CAC_LKG_AGGR_LOWER                                  :Result:='mmGC_CAC_LKG_AGGR_LOWER';
  mmGC_CAC_LKG_AGGR_UPPER                                  :Result:='mmGC_CAC_LKG_AGGR_UPPER';
  mmTCP_WATCH0_ADDR_H                                      :Result:='mmTCP_WATCH0_ADDR_H';
  mmTCP_WATCH0_ADDR_L                                      :Result:='mmTCP_WATCH0_ADDR_L';
  mmTCP_WATCH0_CNTL                                        :Result:='mmTCP_WATCH0_CNTL';
  mmTCP_WATCH1_ADDR_H                                      :Result:='mmTCP_WATCH1_ADDR_H';
  mmTCP_WATCH1_ADDR_L                                      :Result:='mmTCP_WATCH1_ADDR_L';
  mmTCP_WATCH1_CNTL                                        :Result:='mmTCP_WATCH1_CNTL';
  mmTCP_WATCH2_ADDR_H                                      :Result:='mmTCP_WATCH2_ADDR_H';
  mmTCP_WATCH2_ADDR_L                                      :Result:='mmTCP_WATCH2_ADDR_L';
  mmTCP_WATCH2_CNTL                                        :Result:='mmTCP_WATCH2_CNTL';
  mmTCP_WATCH3_ADDR_H                                      :Result:='mmTCP_WATCH3_ADDR_H';
  mmTCP_WATCH3_ADDR_L                                      :Result:='mmTCP_WATCH3_ADDR_L';
  mmTCP_WATCH3_CNTL                                        :Result:='mmTCP_WATCH3_CNTL';
  mmTCP_GATCL1_CNTL                                        :Result:='mmTCP_GATCL1_CNTL';
  mmTCP_ATC_EDC_GATCL1_CNT                                 :Result:='mmTCP_ATC_EDC_GATCL1_CNT';
  mmTCP_GATCL1_DSM_CNTL                                    :Result:='mmTCP_GATCL1_DSM_CNTL';
  mmTCP_DSM_CNTL                                           :Result:='mmTCP_DSM_CNTL';
  mmTCP_CNTL2                                              :Result:='mmTCP_CNTL2';
  mmGDS_VMID0_BASE                                         :Result:='mmGDS_VMID0_BASE';
  mmGDS_VMID0_SIZE                                         :Result:='mmGDS_VMID0_SIZE';
  mmGDS_VMID1_BASE                                         :Result:='mmGDS_VMID1_BASE';
  mmGDS_VMID1_SIZE                                         :Result:='mmGDS_VMID1_SIZE';
  mmGDS_VMID2_BASE                                         :Result:='mmGDS_VMID2_BASE';
  mmGDS_VMID2_SIZE                                         :Result:='mmGDS_VMID2_SIZE';
  mmGDS_VMID3_BASE                                         :Result:='mmGDS_VMID3_BASE';
  mmGDS_VMID3_SIZE                                         :Result:='mmGDS_VMID3_SIZE';
  mmGDS_VMID4_BASE                                         :Result:='mmGDS_VMID4_BASE';
  mmGDS_VMID4_SIZE                                         :Result:='mmGDS_VMID4_SIZE';
  mmGDS_VMID5_BASE                                         :Result:='mmGDS_VMID5_BASE';
  mmGDS_VMID5_SIZE                                         :Result:='mmGDS_VMID5_SIZE';
  mmGDS_VMID6_BASE                                         :Result:='mmGDS_VMID6_BASE';
  mmGDS_VMID6_SIZE                                         :Result:='mmGDS_VMID6_SIZE';
  mmGDS_VMID7_BASE                                         :Result:='mmGDS_VMID7_BASE';
  mmGDS_VMID7_SIZE                                         :Result:='mmGDS_VMID7_SIZE';
  mmGDS_VMID8_BASE                                         :Result:='mmGDS_VMID8_BASE';
  mmGDS_VMID8_SIZE                                         :Result:='mmGDS_VMID8_SIZE';
  mmGDS_VMID9_BASE                                         :Result:='mmGDS_VMID9_BASE';
  mmGDS_VMID9_SIZE                                         :Result:='mmGDS_VMID9_SIZE';
  mmGDS_VMID10_BASE                                        :Result:='mmGDS_VMID10_BASE';
  mmGDS_VMID10_SIZE                                        :Result:='mmGDS_VMID10_SIZE';
  mmGDS_VMID11_BASE                                        :Result:='mmGDS_VMID11_BASE';
  mmGDS_VMID11_SIZE                                        :Result:='mmGDS_VMID11_SIZE';
  mmGDS_VMID12_BASE                                        :Result:='mmGDS_VMID12_BASE';
  mmGDS_VMID12_SIZE                                        :Result:='mmGDS_VMID12_SIZE';
  mmGDS_VMID13_BASE                                        :Result:='mmGDS_VMID13_BASE';
  mmGDS_VMID13_SIZE                                        :Result:='mmGDS_VMID13_SIZE';
  mmGDS_VMID14_BASE                                        :Result:='mmGDS_VMID14_BASE';
  mmGDS_VMID14_SIZE                                        :Result:='mmGDS_VMID14_SIZE';
  mmGDS_VMID15_BASE                                        :Result:='mmGDS_VMID15_BASE';
  mmGDS_VMID15_SIZE                                        :Result:='mmGDS_VMID15_SIZE';
  mmGDS_GWS_VMID0                                          :Result:='mmGDS_GWS_VMID0';
  mmGDS_GWS_VMID1                                          :Result:='mmGDS_GWS_VMID1';
  mmGDS_GWS_VMID2                                          :Result:='mmGDS_GWS_VMID2';
  mmGDS_GWS_VMID3                                          :Result:='mmGDS_GWS_VMID3';
  mmGDS_GWS_VMID4                                          :Result:='mmGDS_GWS_VMID4';
  mmGDS_GWS_VMID5                                          :Result:='mmGDS_GWS_VMID5';
  mmGDS_GWS_VMID6                                          :Result:='mmGDS_GWS_VMID6';
  mmGDS_GWS_VMID7                                          :Result:='mmGDS_GWS_VMID7';
  mmGDS_GWS_VMID8                                          :Result:='mmGDS_GWS_VMID8';
  mmGDS_GWS_VMID9                                          :Result:='mmGDS_GWS_VMID9';
  mmGDS_GWS_VMID10                                         :Result:='mmGDS_GWS_VMID10';
  mmGDS_GWS_VMID11                                         :Result:='mmGDS_GWS_VMID11';
  mmGDS_GWS_VMID12                                         :Result:='mmGDS_GWS_VMID12';
  mmGDS_GWS_VMID13                                         :Result:='mmGDS_GWS_VMID13';
  mmGDS_GWS_VMID14                                         :Result:='mmGDS_GWS_VMID14';
  mmGDS_GWS_VMID15                                         :Result:='mmGDS_GWS_VMID15';
  mmGDS_OA_VMID0                                           :Result:='mmGDS_OA_VMID0';
  mmGDS_OA_VMID1                                           :Result:='mmGDS_OA_VMID1';
  mmGDS_OA_VMID2                                           :Result:='mmGDS_OA_VMID2';
  mmGDS_OA_VMID3                                           :Result:='mmGDS_OA_VMID3';
  mmGDS_OA_VMID4                                           :Result:='mmGDS_OA_VMID4';
  mmGDS_OA_VMID5                                           :Result:='mmGDS_OA_VMID5';
  mmGDS_OA_VMID6                                           :Result:='mmGDS_OA_VMID6';
  mmGDS_OA_VMID7                                           :Result:='mmGDS_OA_VMID7';
  mmGDS_OA_VMID8                                           :Result:='mmGDS_OA_VMID8';
  mmGDS_OA_VMID9                                           :Result:='mmGDS_OA_VMID9';
  mmGDS_OA_VMID10                                          :Result:='mmGDS_OA_VMID10';
  mmGDS_OA_VMID11                                          :Result:='mmGDS_OA_VMID11';
  mmGDS_OA_VMID12                                          :Result:='mmGDS_OA_VMID12';
  mmGDS_OA_VMID13                                          :Result:='mmGDS_OA_VMID13';
  mmGDS_OA_VMID14                                          :Result:='mmGDS_OA_VMID14';
  mmGDS_OA_VMID15                                          :Result:='mmGDS_OA_VMID15';
  mmGDS_GWS_RESET0                                         :Result:='mmGDS_GWS_RESET0';
  mmGDS_GWS_RESET1                                         :Result:='mmGDS_GWS_RESET1';
  mmGDS_GWS_RESOURCE_RESET                                 :Result:='mmGDS_GWS_RESOURCE_RESET';
  mmGDS_COMPUTE_MAX_WAVE_ID                                :Result:='mmGDS_COMPUTE_MAX_WAVE_ID';
  mmGDS_OA_RESET_MASK                                      :Result:='mmGDS_OA_RESET_MASK';
  mmGDS_OA_RESET                                           :Result:='mmGDS_OA_RESET';
  mmGDS_ENHANCE                                            :Result:='mmGDS_ENHANCE';
  mmGDS_OA_CGPG_RESTORE                                    :Result:='mmGDS_OA_CGPG_RESTORE';
  mmGDS_CS_CTXSW_STATUS                                    :Result:='mmGDS_CS_CTXSW_STATUS';
  mmGDS_CS_CTXSW_CNT0                                      :Result:='mmGDS_CS_CTXSW_CNT0';
  mmGDS_CS_CTXSW_CNT1                                      :Result:='mmGDS_CS_CTXSW_CNT1';
  mmGDS_CS_CTXSW_CNT2                                      :Result:='mmGDS_CS_CTXSW_CNT2';
  mmGDS_CS_CTXSW_CNT3                                      :Result:='mmGDS_CS_CTXSW_CNT3';
  mmGDS_GFX_CTXSW_STATUS                                   :Result:='mmGDS_GFX_CTXSW_STATUS';
  mmGDS_VS_CTXSW_CNT0                                      :Result:='mmGDS_VS_CTXSW_CNT0';
  mmGDS_VS_CTXSW_CNT1                                      :Result:='mmGDS_VS_CTXSW_CNT1';
  mmGDS_VS_CTXSW_CNT2                                      :Result:='mmGDS_VS_CTXSW_CNT2';
  mmGDS_VS_CTXSW_CNT3                                      :Result:='mmGDS_VS_CTXSW_CNT3';
  mmGDS_PS0_CTXSW_CNT0                                     :Result:='mmGDS_PS0_CTXSW_CNT0';
  mmGDS_PS0_CTXSW_CNT1                                     :Result:='mmGDS_PS0_CTXSW_CNT1';
  mmGDS_PS0_CTXSW_CNT2                                     :Result:='mmGDS_PS0_CTXSW_CNT2';
  mmGDS_PS0_CTXSW_CNT3                                     :Result:='mmGDS_PS0_CTXSW_CNT3';
  mmGDS_PS1_CTXSW_CNT0                                     :Result:='mmGDS_PS1_CTXSW_CNT0';
  mmGDS_PS1_CTXSW_CNT1                                     :Result:='mmGDS_PS1_CTXSW_CNT1';
  mmGDS_PS1_CTXSW_CNT2                                     :Result:='mmGDS_PS1_CTXSW_CNT2';
  mmGDS_PS1_CTXSW_CNT3                                     :Result:='mmGDS_PS1_CTXSW_CNT3';
  mmGDS_PS2_CTXSW_CNT0                                     :Result:='mmGDS_PS2_CTXSW_CNT0';
  mmGDS_PS2_CTXSW_CNT1                                     :Result:='mmGDS_PS2_CTXSW_CNT1';
  mmGDS_PS2_CTXSW_CNT2                                     :Result:='mmGDS_PS2_CTXSW_CNT2';
  mmGDS_PS2_CTXSW_CNT3                                     :Result:='mmGDS_PS2_CTXSW_CNT3';
  mmGDS_PS3_CTXSW_CNT0                                     :Result:='mmGDS_PS3_CTXSW_CNT0';
  mmGDS_PS3_CTXSW_CNT1                                     :Result:='mmGDS_PS3_CTXSW_CNT1';
  mmGDS_PS3_CTXSW_CNT2                                     :Result:='mmGDS_PS3_CTXSW_CNT2';
  mmGDS_PS3_CTXSW_CNT3                                     :Result:='mmGDS_PS3_CTXSW_CNT3';
  mmGDS_PS4_CTXSW_CNT0                                     :Result:='mmGDS_PS4_CTXSW_CNT0';
  mmGDS_PS4_CTXSW_CNT1                                     :Result:='mmGDS_PS4_CTXSW_CNT1';
  mmGDS_PS4_CTXSW_CNT2                                     :Result:='mmGDS_PS4_CTXSW_CNT2';
  mmGDS_PS4_CTXSW_CNT3                                     :Result:='mmGDS_PS4_CTXSW_CNT3';
  mmGDS_PS5_CTXSW_CNT0                                     :Result:='mmGDS_PS5_CTXSW_CNT0';
  mmGDS_PS5_CTXSW_CNT1                                     :Result:='mmGDS_PS5_CTXSW_CNT1';
  mmGDS_PS5_CTXSW_CNT2                                     :Result:='mmGDS_PS5_CTXSW_CNT2';
  mmGDS_PS5_CTXSW_CNT3                                     :Result:='mmGDS_PS5_CTXSW_CNT3';
  mmGDS_PS6_CTXSW_CNT0                                     :Result:='mmGDS_PS6_CTXSW_CNT0';
  mmGDS_PS6_CTXSW_CNT1                                     :Result:='mmGDS_PS6_CTXSW_CNT1';
  mmGDS_PS6_CTXSW_CNT2                                     :Result:='mmGDS_PS6_CTXSW_CNT2';
  mmGDS_PS6_CTXSW_CNT3                                     :Result:='mmGDS_PS6_CTXSW_CNT3';
  mmGDS_PS7_CTXSW_CNT0                                     :Result:='mmGDS_PS7_CTXSW_CNT0';
  mmGDS_PS7_CTXSW_CNT1                                     :Result:='mmGDS_PS7_CTXSW_CNT1';
  mmGDS_PS7_CTXSW_CNT2                                     :Result:='mmGDS_PS7_CTXSW_CNT2';
  mmGDS_PS7_CTXSW_CNT3                                     :Result:='mmGDS_PS7_CTXSW_CNT3';
  mmRAS_SIGNATURE_CONTROL                                  :Result:='mmRAS_SIGNATURE_CONTROL';
  mmRAS_SIGNATURE_MASK                                     :Result:='mmRAS_SIGNATURE_MASK';
  mmRAS_SX_SIGNATURE0                                      :Result:='mmRAS_SX_SIGNATURE0';
  mmRAS_SX_SIGNATURE1                                      :Result:='mmRAS_SX_SIGNATURE1';
  mmRAS_SX_SIGNATURE2                                      :Result:='mmRAS_SX_SIGNATURE2';
  mmRAS_SX_SIGNATURE3                                      :Result:='mmRAS_SX_SIGNATURE3';
  mmRAS_DB_SIGNATURE0                                      :Result:='mmRAS_DB_SIGNATURE0';
  mmRAS_PA_SIGNATURE0                                      :Result:='mmRAS_PA_SIGNATURE0';
  mmRAS_VGT_SIGNATURE0                                     :Result:='mmRAS_VGT_SIGNATURE0';
  mmRAS_SQ_SIGNATURE0                                      :Result:='mmRAS_SQ_SIGNATURE0';
  mmRAS_SC_SIGNATURE0                                      :Result:='mmRAS_SC_SIGNATURE0';
  mmRAS_SC_SIGNATURE1                                      :Result:='mmRAS_SC_SIGNATURE1';
  mmRAS_SC_SIGNATURE2                                      :Result:='mmRAS_SC_SIGNATURE2';
  mmRAS_SC_SIGNATURE3                                      :Result:='mmRAS_SC_SIGNATURE3';
  mmRAS_SC_SIGNATURE4                                      :Result:='mmRAS_SC_SIGNATURE4';
  mmRAS_SC_SIGNATURE5                                      :Result:='mmRAS_SC_SIGNATURE5';
  mmRAS_SC_SIGNATURE6                                      :Result:='mmRAS_SC_SIGNATURE6';
  mmRAS_SC_SIGNATURE7                                      :Result:='mmRAS_SC_SIGNATURE7';
  mmRAS_IA_SIGNATURE0                                      :Result:='mmRAS_IA_SIGNATURE0';
  mmRAS_IA_SIGNATURE1                                      :Result:='mmRAS_IA_SIGNATURE1';
  mmRAS_SPI_SIGNATURE0                                     :Result:='mmRAS_SPI_SIGNATURE0';
  mmRAS_SPI_SIGNATURE1                                     :Result:='mmRAS_SPI_SIGNATURE1';
  mmRAS_TA_SIGNATURE0                                      :Result:='mmRAS_TA_SIGNATURE0';
  mmRAS_TD_SIGNATURE0                                      :Result:='mmRAS_TD_SIGNATURE0';
  mmRAS_CB_SIGNATURE0                                      :Result:='mmRAS_CB_SIGNATURE0';
  mmRAS_BCI_SIGNATURE0                                     :Result:='mmRAS_BCI_SIGNATURE0';
  mmRAS_BCI_SIGNATURE1                                     :Result:='mmRAS_BCI_SIGNATURE1';
  mmRAS_TA_SIGNATURE1                                      :Result:='mmRAS_TA_SIGNATURE1';
  mmSDMA0_UCODE_ADDR                                       :Result:='mmSDMA0_UCODE_ADDR';
  mmSDMA0_UCODE_DATA                                       :Result:='mmSDMA0_UCODE_DATA';
  mmSDMA0_POWER_CNTL                                       :Result:='mmSDMA0_POWER_CNTL';
  mmSDMA0_CLK_CTRL                                         :Result:='mmSDMA0_CLK_CTRL';
  mmSDMA0_CNTL                                             :Result:='mmSDMA0_CNTL';
  mmSDMA0_CHICKEN_BITS                                     :Result:='mmSDMA0_CHICKEN_BITS';
  mmSDMA0_TILING_CONFIG                                    :Result:='mmSDMA0_TILING_CONFIG';
  mmSDMA0_HASH                                             :Result:='mmSDMA0_HASH';
  mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL                         :Result:='mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL';
  mmSDMA0_RB_RPTR_FETCH                                    :Result:='mmSDMA0_RB_RPTR_FETCH';
  mmSDMA0_IB_OFFSET_FETCH                                  :Result:='mmSDMA0_IB_OFFSET_FETCH';
  mmSDMA0_PROGRAM                                          :Result:='mmSDMA0_PROGRAM';
  mmSDMA0_STATUS_REG                                       :Result:='mmSDMA0_STATUS_REG';
  mmSDMA0_STATUS1_REG                                      :Result:='mmSDMA0_STATUS1_REG';
  mmSDMA0_RD_BURST_CNTL                                    :Result:='mmSDMA0_RD_BURST_CNTL';
  mmSDMA0_F32_CNTL                                         :Result:='mmSDMA0_F32_CNTL';
  mmSDMA0_FREEZE                                           :Result:='mmSDMA0_FREEZE';
  mmSDMA0_PHASE0_QUANTUM                                   :Result:='mmSDMA0_PHASE0_QUANTUM';
  mmSDMA0_PHASE1_QUANTUM                                   :Result:='mmSDMA0_PHASE1_QUANTUM';
  mmSDMA_POWER_GATING                                      :Result:='mmSDMA_POWER_GATING';
  mmSDMA_PGFSM_CONFIG                                      :Result:='mmSDMA_PGFSM_CONFIG';
  mmSDMA_PGFSM_WRITE                                       :Result:='mmSDMA_PGFSM_WRITE';
  mmSDMA_PGFSM_READ                                        :Result:='mmSDMA_PGFSM_READ';
  mmSDMA0_EDC_CONFIG                                       :Result:='mmSDMA0_EDC_CONFIG';
  mmSDMA0_VM_CNTL                                          :Result:='mmSDMA0_VM_CNTL';
  mmSDMA0_VM_CTX_LO                                        :Result:='mmSDMA0_VM_CTX_LO';
  mmSDMA0_VM_CTX_HI                                        :Result:='mmSDMA0_VM_CTX_HI';
  mmSDMA0_STATUS2_REG                                      :Result:='mmSDMA0_STATUS2_REG';
  mmSDMA0_ACTIVE_FCN_ID                                    :Result:='mmSDMA0_ACTIVE_FCN_ID';
  mmSDMA0_VM_CTX_CNTL                                      :Result:='mmSDMA0_VM_CTX_CNTL';
  mmSDMA0_VIRT_RESET_REQ                                   :Result:='mmSDMA0_VIRT_RESET_REQ';
  mmSDMA0_VF_ENABLE                                        :Result:='mmSDMA0_VF_ENABLE';
  mmSDMA0_BA_THRESHOLD                                     :Result:='mmSDMA0_BA_THRESHOLD';
  mmSDMA0_ID                                               :Result:='mmSDMA0_ID';
  mmSDMA0_VERSION                                          :Result:='mmSDMA0_VERSION';
  mmSDMA0_ATOMIC_CNTL                                      :Result:='mmSDMA0_ATOMIC_CNTL';
  mmSDMA0_ATOMIC_PREOP_LO                                  :Result:='mmSDMA0_ATOMIC_PREOP_LO';
  mmSDMA0_ATOMIC_PREOP_HI                                  :Result:='mmSDMA0_ATOMIC_PREOP_HI';
  mmSDMA0_PERF_REG_TYPE0                                   :Result:='mmSDMA0_PERF_REG_TYPE0';
  mmSDMA0_CONTEXT_REG_TYPE0                                :Result:='mmSDMA0_CONTEXT_REG_TYPE0';
  mmSDMA0_CONTEXT_REG_TYPE1                                :Result:='mmSDMA0_CONTEXT_REG_TYPE1';
  mmSDMA0_CONTEXT_REG_TYPE2                                :Result:='mmSDMA0_CONTEXT_REG_TYPE2';
  mmSDMA0_PUB_REG_TYPE0                                    :Result:='mmSDMA0_PUB_REG_TYPE0';
  mmSDMA0_PUB_REG_TYPE1                                    :Result:='mmSDMA0_PUB_REG_TYPE1';
  mmSDMA0_GFX_RB_CNTL                                      :Result:='mmSDMA0_GFX_RB_CNTL';
  mmSDMA0_GFX_RB_BASE                                      :Result:='mmSDMA0_GFX_RB_BASE';
  mmSDMA0_GFX_RB_BASE_HI                                   :Result:='mmSDMA0_GFX_RB_BASE_HI';
  mmSDMA0_GFX_RB_RPTR                                      :Result:='mmSDMA0_GFX_RB_RPTR';
  mmSDMA0_GFX_RB_WPTR                                      :Result:='mmSDMA0_GFX_RB_WPTR';
  mmSDMA0_GFX_RB_WPTR_POLL_CNTL                            :Result:='mmSDMA0_GFX_RB_WPTR_POLL_CNTL';
  mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI                         :Result:='mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI';
  mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO                         :Result:='mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO';
  mmSDMA0_GFX_RB_RPTR_ADDR_HI                              :Result:='mmSDMA0_GFX_RB_RPTR_ADDR_HI';
  mmSDMA0_GFX_RB_RPTR_ADDR_LO                              :Result:='mmSDMA0_GFX_RB_RPTR_ADDR_LO';
  mmSDMA0_GFX_IB_CNTL                                      :Result:='mmSDMA0_GFX_IB_CNTL';
  mmSDMA0_GFX_IB_RPTR                                      :Result:='mmSDMA0_GFX_IB_RPTR';
  mmSDMA0_GFX_IB_OFFSET                                    :Result:='mmSDMA0_GFX_IB_OFFSET';
  mmSDMA0_GFX_IB_BASE_LO                                   :Result:='mmSDMA0_GFX_IB_BASE_LO';
  mmSDMA0_GFX_IB_BASE_HI                                   :Result:='mmSDMA0_GFX_IB_BASE_HI';
  mmSDMA0_GFX_IB_SIZE                                      :Result:='mmSDMA0_GFX_IB_SIZE';
  mmSDMA0_GFX_SKIP_CNTL                                    :Result:='mmSDMA0_GFX_SKIP_CNTL';
  mmSDMA0_GFX_CONTEXT_STATUS                               :Result:='mmSDMA0_GFX_CONTEXT_STATUS';
  mmSDMA0_GFX_DOORBELL                                     :Result:='mmSDMA0_GFX_DOORBELL';
  mmSDMA0_GFX_CONTEXT_CNTL                                 :Result:='mmSDMA0_GFX_CONTEXT_CNTL';
  mmSDMA0_GFX_VIRTUAL_ADDR                                 :Result:='mmSDMA0_GFX_VIRTUAL_ADDR';
  mmSDMA0_GFX_APE1_CNTL                                    :Result:='mmSDMA0_GFX_APE1_CNTL';
  mmSDMA0_GFX_DOORBELL_LOG                                 :Result:='mmSDMA0_GFX_DOORBELL_LOG';
  mmSDMA0_GFX_WATERMARK                                    :Result:='mmSDMA0_GFX_WATERMARK';
  mmSDMA0_GFX_CSA_ADDR_LO                                  :Result:='mmSDMA0_GFX_CSA_ADDR_LO';
  mmSDMA0_GFX_CSA_ADDR_HI                                  :Result:='mmSDMA0_GFX_CSA_ADDR_HI';
  mmSDMA0_GFX_IB_SUB_REMAIN                                :Result:='mmSDMA0_GFX_IB_SUB_REMAIN';
  mmSDMA0_GFX_PREEMPT                                      :Result:='mmSDMA0_GFX_PREEMPT';
  mmSDMA0_GFX_DUMMY_REG                                    :Result:='mmSDMA0_GFX_DUMMY_REG';
  mmSDMA0_GFX_MIDCMD_DATA0                                 :Result:='mmSDMA0_GFX_MIDCMD_DATA0';
  mmSDMA0_GFX_MIDCMD_DATA1                                 :Result:='mmSDMA0_GFX_MIDCMD_DATA1';
  mmSDMA0_GFX_MIDCMD_DATA2                                 :Result:='mmSDMA0_GFX_MIDCMD_DATA2';
  mmSDMA0_GFX_MIDCMD_DATA3                                 :Result:='mmSDMA0_GFX_MIDCMD_DATA3';
  mmSDMA0_GFX_MIDCMD_DATA4                                 :Result:='mmSDMA0_GFX_MIDCMD_DATA4';
  mmSDMA0_GFX_MIDCMD_DATA5                                 :Result:='mmSDMA0_GFX_MIDCMD_DATA5';
  mmSDMA0_GFX_MIDCMD_CNTL                                  :Result:='mmSDMA0_GFX_MIDCMD_CNTL';
  mmSDMA0_RLC0_RB_CNTL                                     :Result:='mmSDMA0_RLC0_RB_CNTL';
  mmSDMA0_RLC0_RB_BASE                                     :Result:='mmSDMA0_RLC0_RB_BASE';
  mmSDMA0_RLC0_RB_BASE_HI                                  :Result:='mmSDMA0_RLC0_RB_BASE_HI';
  mmSDMA0_RLC0_RB_RPTR                                     :Result:='mmSDMA0_RLC0_RB_RPTR';
  mmSDMA0_RLC0_RB_WPTR                                     :Result:='mmSDMA0_RLC0_RB_WPTR';
  mmSDMA0_RLC0_RB_WPTR_POLL_CNTL                           :Result:='mmSDMA0_RLC0_RB_WPTR_POLL_CNTL';
  mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI                        :Result:='mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI';
  mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO                        :Result:='mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO';
  mmSDMA0_RLC0_RB_RPTR_ADDR_HI                             :Result:='mmSDMA0_RLC0_RB_RPTR_ADDR_HI';
  mmSDMA0_RLC0_RB_RPTR_ADDR_LO                             :Result:='mmSDMA0_RLC0_RB_RPTR_ADDR_LO';
  mmSDMA0_RLC0_IB_CNTL                                     :Result:='mmSDMA0_RLC0_IB_CNTL';
  mmSDMA0_RLC0_IB_RPTR                                     :Result:='mmSDMA0_RLC0_IB_RPTR';
  mmSDMA0_RLC0_IB_OFFSET                                   :Result:='mmSDMA0_RLC0_IB_OFFSET';
  mmSDMA0_RLC0_IB_BASE_LO                                  :Result:='mmSDMA0_RLC0_IB_BASE_LO';
  mmSDMA0_RLC0_IB_BASE_HI                                  :Result:='mmSDMA0_RLC0_IB_BASE_HI';
  mmSDMA0_RLC0_IB_SIZE                                     :Result:='mmSDMA0_RLC0_IB_SIZE';
  mmSDMA0_RLC0_SKIP_CNTL                                   :Result:='mmSDMA0_RLC0_SKIP_CNTL';
  mmSDMA0_RLC0_CONTEXT_STATUS                              :Result:='mmSDMA0_RLC0_CONTEXT_STATUS';
  mmSDMA0_RLC0_DOORBELL                                    :Result:='mmSDMA0_RLC0_DOORBELL';
  mmSDMA0_RLC0_VIRTUAL_ADDR                                :Result:='mmSDMA0_RLC0_VIRTUAL_ADDR';
  mmSDMA0_RLC0_APE1_CNTL                                   :Result:='mmSDMA0_RLC0_APE1_CNTL';
  mmSDMA0_RLC0_DOORBELL_LOG                                :Result:='mmSDMA0_RLC0_DOORBELL_LOG';
  mmSDMA0_RLC0_WATERMARK                                   :Result:='mmSDMA0_RLC0_WATERMARK';
  mmSDMA0_RLC0_CSA_ADDR_LO                                 :Result:='mmSDMA0_RLC0_CSA_ADDR_LO';
  mmSDMA0_RLC0_CSA_ADDR_HI                                 :Result:='mmSDMA0_RLC0_CSA_ADDR_HI';
  mmSDMA0_RLC0_IB_SUB_REMAIN                               :Result:='mmSDMA0_RLC0_IB_SUB_REMAIN';
  mmSDMA0_RLC0_PREEMPT                                     :Result:='mmSDMA0_RLC0_PREEMPT';
  mmSDMA0_RLC0_DUMMY_REG                                   :Result:='mmSDMA0_RLC0_DUMMY_REG';
  mmSDMA0_RLC0_MIDCMD_DATA0                                :Result:='mmSDMA0_RLC0_MIDCMD_DATA0';
  mmSDMA0_RLC0_MIDCMD_DATA1                                :Result:='mmSDMA0_RLC0_MIDCMD_DATA1';
  mmSDMA0_RLC0_MIDCMD_DATA2                                :Result:='mmSDMA0_RLC0_MIDCMD_DATA2';
  mmSDMA0_RLC0_MIDCMD_DATA3                                :Result:='mmSDMA0_RLC0_MIDCMD_DATA3';
  mmSDMA0_RLC0_MIDCMD_DATA4                                :Result:='mmSDMA0_RLC0_MIDCMD_DATA4';
  mmSDMA0_RLC0_MIDCMD_DATA5                                :Result:='mmSDMA0_RLC0_MIDCMD_DATA5';
  mmSDMA0_RLC0_MIDCMD_CNTL                                 :Result:='mmSDMA0_RLC0_MIDCMD_CNTL';
  mmSDMA0_RLC1_RB_CNTL                                     :Result:='mmSDMA0_RLC1_RB_CNTL';
  mmSDMA0_RLC1_RB_BASE                                     :Result:='mmSDMA0_RLC1_RB_BASE';
  mmSDMA0_RLC1_RB_BASE_HI                                  :Result:='mmSDMA0_RLC1_RB_BASE_HI';
  mmSDMA0_RLC1_RB_RPTR                                     :Result:='mmSDMA0_RLC1_RB_RPTR';
  mmSDMA0_RLC1_RB_WPTR                                     :Result:='mmSDMA0_RLC1_RB_WPTR';
  mmSDMA0_RLC1_RB_WPTR_POLL_CNTL                           :Result:='mmSDMA0_RLC1_RB_WPTR_POLL_CNTL';
  mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI                        :Result:='mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI';
  mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO                        :Result:='mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO';
  mmSDMA0_RLC1_RB_RPTR_ADDR_HI                             :Result:='mmSDMA0_RLC1_RB_RPTR_ADDR_HI';
  mmSDMA0_RLC1_RB_RPTR_ADDR_LO                             :Result:='mmSDMA0_RLC1_RB_RPTR_ADDR_LO';
  mmSDMA0_RLC1_IB_CNTL                                     :Result:='mmSDMA0_RLC1_IB_CNTL';
  mmSDMA0_RLC1_IB_RPTR                                     :Result:='mmSDMA0_RLC1_IB_RPTR';
  mmSDMA0_RLC1_IB_OFFSET                                   :Result:='mmSDMA0_RLC1_IB_OFFSET';
  mmSDMA0_RLC1_IB_BASE_LO                                  :Result:='mmSDMA0_RLC1_IB_BASE_LO';
  mmSDMA0_RLC1_IB_BASE_HI                                  :Result:='mmSDMA0_RLC1_IB_BASE_HI';
  mmSDMA0_RLC1_IB_SIZE                                     :Result:='mmSDMA0_RLC1_IB_SIZE';
  mmSDMA0_RLC1_SKIP_CNTL                                   :Result:='mmSDMA0_RLC1_SKIP_CNTL';
  mmSDMA0_RLC1_CONTEXT_STATUS                              :Result:='mmSDMA0_RLC1_CONTEXT_STATUS';
  mmSDMA0_RLC1_DOORBELL                                    :Result:='mmSDMA0_RLC1_DOORBELL';
  mmSDMA0_RLC1_VIRTUAL_ADDR                                :Result:='mmSDMA0_RLC1_VIRTUAL_ADDR';
  mmSDMA0_RLC1_APE1_CNTL                                   :Result:='mmSDMA0_RLC1_APE1_CNTL';
  mmSDMA0_RLC1_DOORBELL_LOG                                :Result:='mmSDMA0_RLC1_DOORBELL_LOG';
  mmSDMA0_RLC1_WATERMARK                                   :Result:='mmSDMA0_RLC1_WATERMARK';
  mmSDMA0_RLC1_CSA_ADDR_LO                                 :Result:='mmSDMA0_RLC1_CSA_ADDR_LO';
  mmSDMA0_RLC1_CSA_ADDR_HI                                 :Result:='mmSDMA0_RLC1_CSA_ADDR_HI';
  mmSDMA0_RLC1_IB_SUB_REMAIN                               :Result:='mmSDMA0_RLC1_IB_SUB_REMAIN';
  mmSDMA0_RLC1_PREEMPT                                     :Result:='mmSDMA0_RLC1_PREEMPT';
  mmSDMA0_RLC1_DUMMY_REG                                   :Result:='mmSDMA0_RLC1_DUMMY_REG';
  mmSDMA0_RLC1_MIDCMD_DATA0                                :Result:='mmSDMA0_RLC1_MIDCMD_DATA0';
  mmSDMA0_RLC1_MIDCMD_DATA1                                :Result:='mmSDMA0_RLC1_MIDCMD_DATA1';
  mmSDMA0_RLC1_MIDCMD_DATA2                                :Result:='mmSDMA0_RLC1_MIDCMD_DATA2';
  mmSDMA0_RLC1_MIDCMD_DATA3                                :Result:='mmSDMA0_RLC1_MIDCMD_DATA3';
  mmSDMA0_RLC1_MIDCMD_DATA4                                :Result:='mmSDMA0_RLC1_MIDCMD_DATA4';
  mmSDMA0_RLC1_MIDCMD_DATA5                                :Result:='mmSDMA0_RLC1_MIDCMD_DATA5';
  mmSDMA0_RLC1_MIDCMD_CNTL                                 :Result:='mmSDMA0_RLC1_MIDCMD_CNTL';
  mmSDMA1_UCODE_ADDR                                       :Result:='mmSDMA1_UCODE_ADDR';
  mmSDMA1_UCODE_DATA                                       :Result:='mmSDMA1_UCODE_DATA';
  mmSDMA1_POWER_CNTL                                       :Result:='mmSDMA1_POWER_CNTL';
  mmSDMA1_CLK_CTRL                                         :Result:='mmSDMA1_CLK_CTRL';
  mmSDMA1_CNTL                                             :Result:='mmSDMA1_CNTL';
  mmSDMA1_CHICKEN_BITS                                     :Result:='mmSDMA1_CHICKEN_BITS';
  mmSDMA1_TILING_CONFIG                                    :Result:='mmSDMA1_TILING_CONFIG';
  mmSDMA1_HASH                                             :Result:='mmSDMA1_HASH';
  mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                         :Result:='mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL';
  mmSDMA1_RB_RPTR_FETCH                                    :Result:='mmSDMA1_RB_RPTR_FETCH';
  mmSDMA1_IB_OFFSET_FETCH                                  :Result:='mmSDMA1_IB_OFFSET_FETCH';
  mmSDMA1_PROGRAM                                          :Result:='mmSDMA1_PROGRAM';
  mmSDMA1_STATUS_REG                                       :Result:='mmSDMA1_STATUS_REG';
  mmSDMA1_STATUS1_REG                                      :Result:='mmSDMA1_STATUS1_REG';
  mmSDMA1_RD_BURST_CNTL                                    :Result:='mmSDMA1_RD_BURST_CNTL';
  mmSDMA1_F32_CNTL                                         :Result:='mmSDMA1_F32_CNTL';
  mmSDMA1_FREEZE                                           :Result:='mmSDMA1_FREEZE';
  mmSDMA1_PHASE0_QUANTUM                                   :Result:='mmSDMA1_PHASE0_QUANTUM';
  mmSDMA1_PHASE1_QUANTUM                                   :Result:='mmSDMA1_PHASE1_QUANTUM';
  mmSDMA1_EDC_CONFIG                                       :Result:='mmSDMA1_EDC_CONFIG';
  mmSDMA1_VM_CNTL                                          :Result:='mmSDMA1_VM_CNTL';
  mmSDMA1_VM_CTX_LO                                        :Result:='mmSDMA1_VM_CTX_LO';
  mmSDMA1_VM_CTX_HI                                        :Result:='mmSDMA1_VM_CTX_HI';
  mmSDMA1_STATUS2_REG                                      :Result:='mmSDMA1_STATUS2_REG';
  mmSDMA1_ACTIVE_FCN_ID                                    :Result:='mmSDMA1_ACTIVE_FCN_ID';
  mmSDMA1_VM_CTX_CNTL                                      :Result:='mmSDMA1_VM_CTX_CNTL';
  mmSDMA1_VIRT_RESET_REQ                                   :Result:='mmSDMA1_VIRT_RESET_REQ';
  mmSDMA1_VF_ENABLE                                        :Result:='mmSDMA1_VF_ENABLE';
  mmSDMA1_BA_THRESHOLD                                     :Result:='mmSDMA1_BA_THRESHOLD';
  mmSDMA1_ID                                               :Result:='mmSDMA1_ID';
  mmSDMA1_VERSION                                          :Result:='mmSDMA1_VERSION';
  mmSDMA1_ATOMIC_CNTL                                      :Result:='mmSDMA1_ATOMIC_CNTL';
  mmSDMA1_ATOMIC_PREOP_LO                                  :Result:='mmSDMA1_ATOMIC_PREOP_LO';
  mmSDMA1_ATOMIC_PREOP_HI                                  :Result:='mmSDMA1_ATOMIC_PREOP_HI';
  mmSDMA1_PERF_REG_TYPE0                                   :Result:='mmSDMA1_PERF_REG_TYPE0';
  mmSDMA1_CONTEXT_REG_TYPE0                                :Result:='mmSDMA1_CONTEXT_REG_TYPE0';
  mmSDMA1_CONTEXT_REG_TYPE1                                :Result:='mmSDMA1_CONTEXT_REG_TYPE1';
  mmSDMA1_CONTEXT_REG_TYPE2                                :Result:='mmSDMA1_CONTEXT_REG_TYPE2';
  mmSDMA1_PUB_REG_TYPE0                                    :Result:='mmSDMA1_PUB_REG_TYPE0';
  mmSDMA1_PUB_REG_TYPE1                                    :Result:='mmSDMA1_PUB_REG_TYPE1';
  mmSDMA1_GFX_RB_CNTL                                      :Result:='mmSDMA1_GFX_RB_CNTL';
  mmSDMA1_GFX_RB_BASE                                      :Result:='mmSDMA1_GFX_RB_BASE';
  mmSDMA1_GFX_RB_BASE_HI                                   :Result:='mmSDMA1_GFX_RB_BASE_HI';
  mmSDMA1_GFX_RB_RPTR                                      :Result:='mmSDMA1_GFX_RB_RPTR';
  mmSDMA1_GFX_RB_WPTR                                      :Result:='mmSDMA1_GFX_RB_WPTR';
  mmSDMA1_GFX_RB_WPTR_POLL_CNTL                            :Result:='mmSDMA1_GFX_RB_WPTR_POLL_CNTL';
  mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI                         :Result:='mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI';
  mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO                         :Result:='mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO';
  mmSDMA1_GFX_RB_RPTR_ADDR_HI                              :Result:='mmSDMA1_GFX_RB_RPTR_ADDR_HI';
  mmSDMA1_GFX_RB_RPTR_ADDR_LO                              :Result:='mmSDMA1_GFX_RB_RPTR_ADDR_LO';
  mmSDMA1_GFX_IB_CNTL                                      :Result:='mmSDMA1_GFX_IB_CNTL';
  mmSDMA1_GFX_IB_RPTR                                      :Result:='mmSDMA1_GFX_IB_RPTR';
  mmSDMA1_GFX_IB_OFFSET                                    :Result:='mmSDMA1_GFX_IB_OFFSET';
  mmSDMA1_GFX_IB_BASE_LO                                   :Result:='mmSDMA1_GFX_IB_BASE_LO';
  mmSDMA1_GFX_IB_BASE_HI                                   :Result:='mmSDMA1_GFX_IB_BASE_HI';
  mmSDMA1_GFX_IB_SIZE                                      :Result:='mmSDMA1_GFX_IB_SIZE';
  mmSDMA1_GFX_SKIP_CNTL                                    :Result:='mmSDMA1_GFX_SKIP_CNTL';
  mmSDMA1_GFX_CONTEXT_STATUS                               :Result:='mmSDMA1_GFX_CONTEXT_STATUS';
  mmSDMA1_GFX_DOORBELL                                     :Result:='mmSDMA1_GFX_DOORBELL';
  mmSDMA1_GFX_CONTEXT_CNTL                                 :Result:='mmSDMA1_GFX_CONTEXT_CNTL';
  mmSDMA1_GFX_VIRTUAL_ADDR                                 :Result:='mmSDMA1_GFX_VIRTUAL_ADDR';
  mmSDMA1_GFX_APE1_CNTL                                    :Result:='mmSDMA1_GFX_APE1_CNTL';
  mmSDMA1_GFX_DOORBELL_LOG                                 :Result:='mmSDMA1_GFX_DOORBELL_LOG';
  mmSDMA1_GFX_WATERMARK                                    :Result:='mmSDMA1_GFX_WATERMARK';
  mmSDMA1_GFX_CSA_ADDR_LO                                  :Result:='mmSDMA1_GFX_CSA_ADDR_LO';
  mmSDMA1_GFX_CSA_ADDR_HI                                  :Result:='mmSDMA1_GFX_CSA_ADDR_HI';
  mmSDMA1_GFX_IB_SUB_REMAIN                                :Result:='mmSDMA1_GFX_IB_SUB_REMAIN';
  mmSDMA1_GFX_PREEMPT                                      :Result:='mmSDMA1_GFX_PREEMPT';
  mmSDMA1_GFX_DUMMY_REG                                    :Result:='mmSDMA1_GFX_DUMMY_REG';
  mmSDMA1_GFX_MIDCMD_DATA0                                 :Result:='mmSDMA1_GFX_MIDCMD_DATA0';
  mmSDMA1_GFX_MIDCMD_DATA1                                 :Result:='mmSDMA1_GFX_MIDCMD_DATA1';
  mmSDMA1_GFX_MIDCMD_DATA2                                 :Result:='mmSDMA1_GFX_MIDCMD_DATA2';
  mmSDMA1_GFX_MIDCMD_DATA3                                 :Result:='mmSDMA1_GFX_MIDCMD_DATA3';
  mmSDMA1_GFX_MIDCMD_DATA4                                 :Result:='mmSDMA1_GFX_MIDCMD_DATA4';
  mmSDMA1_GFX_MIDCMD_DATA5                                 :Result:='mmSDMA1_GFX_MIDCMD_DATA5';
  mmSDMA1_GFX_MIDCMD_CNTL                                  :Result:='mmSDMA1_GFX_MIDCMD_CNTL';
  mmSDMA1_RLC0_RB_CNTL                                     :Result:='mmSDMA1_RLC0_RB_CNTL';
  mmSDMA1_RLC0_RB_BASE                                     :Result:='mmSDMA1_RLC0_RB_BASE';
  mmSDMA1_RLC0_RB_BASE_HI                                  :Result:='mmSDMA1_RLC0_RB_BASE_HI';
  mmSDMA1_RLC0_RB_RPTR                                     :Result:='mmSDMA1_RLC0_RB_RPTR';
  mmSDMA1_RLC0_RB_WPTR                                     :Result:='mmSDMA1_RLC0_RB_WPTR';
  mmSDMA1_RLC0_RB_WPTR_POLL_CNTL                           :Result:='mmSDMA1_RLC0_RB_WPTR_POLL_CNTL';
  mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                        :Result:='mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI';
  mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                        :Result:='mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO';
  mmSDMA1_RLC0_RB_RPTR_ADDR_HI                             :Result:='mmSDMA1_RLC0_RB_RPTR_ADDR_HI';
  mmSDMA1_RLC0_RB_RPTR_ADDR_LO                             :Result:='mmSDMA1_RLC0_RB_RPTR_ADDR_LO';
  mmSDMA1_RLC0_IB_CNTL                                     :Result:='mmSDMA1_RLC0_IB_CNTL';
  mmSDMA1_RLC0_IB_RPTR                                     :Result:='mmSDMA1_RLC0_IB_RPTR';
  mmSDMA1_RLC0_IB_OFFSET                                   :Result:='mmSDMA1_RLC0_IB_OFFSET';
  mmSDMA1_RLC0_IB_BASE_LO                                  :Result:='mmSDMA1_RLC0_IB_BASE_LO';
  mmSDMA1_RLC0_IB_BASE_HI                                  :Result:='mmSDMA1_RLC0_IB_BASE_HI';
  mmSDMA1_RLC0_IB_SIZE                                     :Result:='mmSDMA1_RLC0_IB_SIZE';
  mmSDMA1_RLC0_SKIP_CNTL                                   :Result:='mmSDMA1_RLC0_SKIP_CNTL';
  mmSDMA1_RLC0_CONTEXT_STATUS                              :Result:='mmSDMA1_RLC0_CONTEXT_STATUS';
  mmSDMA1_RLC0_DOORBELL                                    :Result:='mmSDMA1_RLC0_DOORBELL';
  mmSDMA1_RLC0_VIRTUAL_ADDR                                :Result:='mmSDMA1_RLC0_VIRTUAL_ADDR';
  mmSDMA1_RLC0_APE1_CNTL                                   :Result:='mmSDMA1_RLC0_APE1_CNTL';
  mmSDMA1_RLC0_DOORBELL_LOG                                :Result:='mmSDMA1_RLC0_DOORBELL_LOG';
  mmSDMA1_RLC0_WATERMARK                                   :Result:='mmSDMA1_RLC0_WATERMARK';
  mmSDMA1_RLC0_CSA_ADDR_LO                                 :Result:='mmSDMA1_RLC0_CSA_ADDR_LO';
  mmSDMA1_RLC0_CSA_ADDR_HI                                 :Result:='mmSDMA1_RLC0_CSA_ADDR_HI';
  mmSDMA1_RLC0_IB_SUB_REMAIN                               :Result:='mmSDMA1_RLC0_IB_SUB_REMAIN';
  mmSDMA1_RLC0_PREEMPT                                     :Result:='mmSDMA1_RLC0_PREEMPT';
  mmSDMA1_RLC0_DUMMY_REG                                   :Result:='mmSDMA1_RLC0_DUMMY_REG';
  mmSDMA1_RLC0_MIDCMD_DATA0                                :Result:='mmSDMA1_RLC0_MIDCMD_DATA0';
  mmSDMA1_RLC0_MIDCMD_DATA1                                :Result:='mmSDMA1_RLC0_MIDCMD_DATA1';
  mmSDMA1_RLC0_MIDCMD_DATA2                                :Result:='mmSDMA1_RLC0_MIDCMD_DATA2';
  mmSDMA1_RLC0_MIDCMD_DATA3                                :Result:='mmSDMA1_RLC0_MIDCMD_DATA3';
  mmSDMA1_RLC0_MIDCMD_DATA4                                :Result:='mmSDMA1_RLC0_MIDCMD_DATA4';
  mmSDMA1_RLC0_MIDCMD_DATA5                                :Result:='mmSDMA1_RLC0_MIDCMD_DATA5';
  mmSDMA1_RLC0_MIDCMD_CNTL                                 :Result:='mmSDMA1_RLC0_MIDCMD_CNTL';
  mmSDMA1_RLC1_RB_CNTL                                     :Result:='mmSDMA1_RLC1_RB_CNTL';
  mmSDMA1_RLC1_RB_BASE                                     :Result:='mmSDMA1_RLC1_RB_BASE';
  mmSDMA1_RLC1_RB_BASE_HI                                  :Result:='mmSDMA1_RLC1_RB_BASE_HI';
  mmSDMA1_RLC1_RB_RPTR                                     :Result:='mmSDMA1_RLC1_RB_RPTR';
  mmSDMA1_RLC1_RB_WPTR                                     :Result:='mmSDMA1_RLC1_RB_WPTR';
  mmSDMA1_RLC1_RB_WPTR_POLL_CNTL                           :Result:='mmSDMA1_RLC1_RB_WPTR_POLL_CNTL';
  mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                        :Result:='mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI';
  mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                        :Result:='mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO';
  mmSDMA1_RLC1_RB_RPTR_ADDR_HI                             :Result:='mmSDMA1_RLC1_RB_RPTR_ADDR_HI';
  mmSDMA1_RLC1_RB_RPTR_ADDR_LO                             :Result:='mmSDMA1_RLC1_RB_RPTR_ADDR_LO';
  mmSDMA1_RLC1_IB_CNTL                                     :Result:='mmSDMA1_RLC1_IB_CNTL';
  mmSDMA1_RLC1_IB_RPTR                                     :Result:='mmSDMA1_RLC1_IB_RPTR';
  mmSDMA1_RLC1_IB_OFFSET                                   :Result:='mmSDMA1_RLC1_IB_OFFSET';
  mmSDMA1_RLC1_IB_BASE_LO                                  :Result:='mmSDMA1_RLC1_IB_BASE_LO';
  mmSDMA1_RLC1_IB_BASE_HI                                  :Result:='mmSDMA1_RLC1_IB_BASE_HI';
  mmSDMA1_RLC1_IB_SIZE                                     :Result:='mmSDMA1_RLC1_IB_SIZE';
  mmSDMA1_RLC1_SKIP_CNTL                                   :Result:='mmSDMA1_RLC1_SKIP_CNTL';
  mmSDMA1_RLC1_CONTEXT_STATUS                              :Result:='mmSDMA1_RLC1_CONTEXT_STATUS';
  mmSDMA1_RLC1_DOORBELL                                    :Result:='mmSDMA1_RLC1_DOORBELL';
  mmSDMA1_RLC1_VIRTUAL_ADDR                                :Result:='mmSDMA1_RLC1_VIRTUAL_ADDR';
  mmSDMA1_RLC1_APE1_CNTL                                   :Result:='mmSDMA1_RLC1_APE1_CNTL';
  mmSDMA1_RLC1_DOORBELL_LOG                                :Result:='mmSDMA1_RLC1_DOORBELL_LOG';
  mmSDMA1_RLC1_WATERMARK                                   :Result:='mmSDMA1_RLC1_WATERMARK';
  mmSDMA1_RLC1_CSA_ADDR_LO                                 :Result:='mmSDMA1_RLC1_CSA_ADDR_LO';
  mmSDMA1_RLC1_CSA_ADDR_HI                                 :Result:='mmSDMA1_RLC1_CSA_ADDR_HI';
  mmSDMA1_RLC1_IB_SUB_REMAIN                               :Result:='mmSDMA1_RLC1_IB_SUB_REMAIN';
  mmSDMA1_RLC1_PREEMPT                                     :Result:='mmSDMA1_RLC1_PREEMPT';
  mmSDMA1_RLC1_DUMMY_REG                                   :Result:='mmSDMA1_RLC1_DUMMY_REG';
  mmSDMA1_RLC1_MIDCMD_DATA0                                :Result:='mmSDMA1_RLC1_MIDCMD_DATA0';
  mmSDMA1_RLC1_MIDCMD_DATA1                                :Result:='mmSDMA1_RLC1_MIDCMD_DATA1';
  mmSDMA1_RLC1_MIDCMD_DATA2                                :Result:='mmSDMA1_RLC1_MIDCMD_DATA2';
  mmSDMA1_RLC1_MIDCMD_DATA3                                :Result:='mmSDMA1_RLC1_MIDCMD_DATA3';
  mmSDMA1_RLC1_MIDCMD_DATA4                                :Result:='mmSDMA1_RLC1_MIDCMD_DATA4';
  mmSDMA1_RLC1_MIDCMD_DATA5                                :Result:='mmSDMA1_RLC1_MIDCMD_DATA5';
  mmSDMA1_RLC1_MIDCMD_CNTL                                 :Result:='mmSDMA1_RLC1_MIDCMD_CNTL';
  mmUVD_PGFSM_CONFIG                                       :Result:='mmUVD_PGFSM_CONFIG';
  mmUVD_PGFSM_READ_TILE1                                   :Result:='mmUVD_PGFSM_READ_TILE1';
  mmUVD_PGFSM_READ_TILE2                                   :Result:='mmUVD_PGFSM_READ_TILE2';
  mmUVD_POWER_STATUS                                       :Result:='mmUVD_POWER_STATUS';
  mmUVD_PGFSM_READ_TILE3                                   :Result:='mmUVD_PGFSM_READ_TILE3';
  mmUVD_PGFSM_READ_TILE4                                   :Result:='mmUVD_PGFSM_READ_TILE4';
  mmUVD_PGFSM_READ_TILE5                                   :Result:='mmUVD_PGFSM_READ_TILE5';
  mmUVD_PGFSM_READ_TILE6                                   :Result:='mmUVD_PGFSM_READ_TILE6';
  mmUVD_PGFSM_READ_TILE7                                   :Result:='mmUVD_PGFSM_READ_TILE7';
  mmUVD_MIF_CURR_ADDR_CONFIG                               :Result:='mmUVD_MIF_CURR_ADDR_CONFIG';
  mmUVD_MIF_REF_ADDR_CONFIG                                :Result:='mmUVD_MIF_REF_ADDR_CONFIG';
  mmUVD_MIF_RECON1_ADDR_CONFIG                             :Result:='mmUVD_MIF_RECON1_ADDR_CONFIG';
  mmUVD_JPEG_ADDR_CONFIG                                   :Result:='mmUVD_JPEG_ADDR_CONFIG';
  mmUVD_SEMA_ADDR_LOW                                      :Result:='mmUVD_SEMA_ADDR_LOW';
  mmUVD_SEMA_ADDR_HIGH                                     :Result:='mmUVD_SEMA_ADDR_HIGH';
  mmUVD_SEMA_CMD                                           :Result:='mmUVD_SEMA_CMD';
  mmUVD_GPCOM_VCPU_CMD                                     :Result:='mmUVD_GPCOM_VCPU_CMD';
  mmUVD_GPCOM_VCPU_DATA0                                   :Result:='mmUVD_GPCOM_VCPU_DATA0';
  mmUVD_GPCOM_VCPU_DATA1                                   :Result:='mmUVD_GPCOM_VCPU_DATA1';
  mmUVD_ENGINE_CNTL                                        :Result:='mmUVD_ENGINE_CNTL';
  mmUVD_UDEC_ADDR_CONFIG                                   :Result:='mmUVD_UDEC_ADDR_CONFIG';
  mmUVD_UDEC_DB_ADDR_CONFIG                                :Result:='mmUVD_UDEC_DB_ADDR_CONFIG';
  mmUVD_UDEC_DBW_ADDR_CONFIG                               :Result:='mmUVD_UDEC_DBW_ADDR_CONFIG';
  mmUVD_SUVD_CGC_GATE                                      :Result:='mmUVD_SUVD_CGC_GATE';
  mmUVD_SUVD_CGC_STATUS                                    :Result:='mmUVD_SUVD_CGC_STATUS';
  mmUVD_SUVD_CGC_CTRL                                      :Result:='mmUVD_SUVD_CGC_CTRL';
  mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                      :Result:='mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH';
  mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                       :Result:='mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW';
  mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH                          :Result:='mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH';
  mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                           :Result:='mmUVD_LMI_RBC_IB_64BIT_BAR_LOW';
  mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                          :Result:='mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH';
  mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                           :Result:='mmUVD_LMI_RBC_RB_64BIT_BAR_LOW';
  mmUVD_SEMA_CNTL                                          :Result:='mmUVD_SEMA_CNTL';
  mmUVD_LMI_EXT40_ADDR                                     :Result:='mmUVD_LMI_EXT40_ADDR';
  mmUVD_CTX_INDEX                                          :Result:='mmUVD_CTX_INDEX';
  mmUVD_CTX_DATA                                           :Result:='mmUVD_CTX_DATA';
  mmUVD_CGC_GATE                                           :Result:='mmUVD_CGC_GATE';
  mmUVD_CGC_STATUS                                         :Result:='mmUVD_CGC_STATUS';
  mmUVD_CGC_CTRL                                           :Result:='mmUVD_CGC_CTRL';
  mmUVD_CGC_UDEC_STATUS                                    :Result:='mmUVD_CGC_UDEC_STATUS';
  mmUVD_LMI_CTRL2                                          :Result:='mmUVD_LMI_CTRL2';
  mmUVD_MASTINT_EN                                         :Result:='mmUVD_MASTINT_EN';
  mmUVD_LMI_ADDR_EXT                                       :Result:='mmUVD_LMI_ADDR_EXT';
  mmUVD_LMI_CTRL                                           :Result:='mmUVD_LMI_CTRL';
  mmUVD_LMI_STATUS                                         :Result:='mmUVD_LMI_STATUS';
  mmUVD_LMI_SWAP_CNTL                                      :Result:='mmUVD_LMI_SWAP_CNTL';
  mmUVD_MP_SWAP_CNTL                                       :Result:='mmUVD_MP_SWAP_CNTL';
  mmUVD_MPC_CNTL                                           :Result:='mmUVD_MPC_CNTL';
  mmUVD_MPC_SET_MUXA0                                      :Result:='mmUVD_MPC_SET_MUXA0';
  mmUVD_MPC_SET_MUXA1                                      :Result:='mmUVD_MPC_SET_MUXA1';
  mmUVD_MPC_SET_MUXB0                                      :Result:='mmUVD_MPC_SET_MUXB0';
  mmUVD_MPC_SET_MUXB1                                      :Result:='mmUVD_MPC_SET_MUXB1';
  mmUVD_MPC_SET_MUX                                        :Result:='mmUVD_MPC_SET_MUX';
  mmUVD_MPC_SET_ALU                                        :Result:='mmUVD_MPC_SET_ALU';
  mmUVD_VCPU_CACHE_OFFSET0                                 :Result:='mmUVD_VCPU_CACHE_OFFSET0';
  mmUVD_VCPU_CACHE_SIZE0                                   :Result:='mmUVD_VCPU_CACHE_SIZE0';
  mmUVD_VCPU_CACHE_OFFSET1                                 :Result:='mmUVD_VCPU_CACHE_OFFSET1';
  mmUVD_VCPU_CACHE_SIZE1                                   :Result:='mmUVD_VCPU_CACHE_SIZE1';
  mmUVD_VCPU_CACHE_OFFSET2                                 :Result:='mmUVD_VCPU_CACHE_OFFSET2';
  mmUVD_VCPU_CACHE_SIZE2                                   :Result:='mmUVD_VCPU_CACHE_SIZE2';
  mmUVD_VCPU_CNTL                                          :Result:='mmUVD_VCPU_CNTL';
  mmUVD_SOFT_RESET                                         :Result:='mmUVD_SOFT_RESET';
  mmUVD_LMI_RBC_IB_VMID                                    :Result:='mmUVD_LMI_RBC_IB_VMID';
  mmUVD_RBC_IB_SIZE                                        :Result:='mmUVD_RBC_IB_SIZE';
  mmUVD_LMI_RBC_RB_VMID                                    :Result:='mmUVD_LMI_RBC_RB_VMID';
  mmUVD_RBC_RB_RPTR                                        :Result:='mmUVD_RBC_RB_RPTR';
  mmUVD_RBC_RB_WPTR                                        :Result:='mmUVD_RBC_RB_WPTR';
  mmUVD_RBC_RB_CNTL                                        :Result:='mmUVD_RBC_RB_CNTL';
  mmUVD_RBC_RB_RPTR_ADDR                                   :Result:='mmUVD_RBC_RB_RPTR_ADDR';
  mmUVD_STATUS                                             :Result:='mmUVD_STATUS';
  mmUVD_SEMA_TIMEOUT_STATUS                                :Result:='mmUVD_SEMA_TIMEOUT_STATUS';
  mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                  :Result:='mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL';
  mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                       :Result:='mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL';
  mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                :Result:='mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL';
  mmUVD_CONTEXT_ID                                         :Result:='mmUVD_CONTEXT_ID';
  mmDCP3_GRPH_ENABLE                                       :Result:='mmDCP3_GRPH_ENABLE';
  mmDCP3_GRPH_CONTROL                                      :Result:='mmDCP3_GRPH_CONTROL';
  mmDCP3_GRPH_LUT_10BIT_BYPASS                             :Result:='mmDCP3_GRPH_LUT_10BIT_BYPASS';
  mmDCP3_GRPH_SWAP_CNTL                                    :Result:='mmDCP3_GRPH_SWAP_CNTL';
  mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS                      :Result:='mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS';
  mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS                    :Result:='mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS';
  mmDCP3_GRPH_PITCH                                        :Result:='mmDCP3_GRPH_PITCH';
  mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                 :Result:='mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH';
  mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH               :Result:='mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH';
  mmDCP3_GRPH_SURFACE_OFFSET_X                             :Result:='mmDCP3_GRPH_SURFACE_OFFSET_X';
  mmDCP3_GRPH_SURFACE_OFFSET_Y                             :Result:='mmDCP3_GRPH_SURFACE_OFFSET_Y';
  mmDCP3_GRPH_X_START                                      :Result:='mmDCP3_GRPH_X_START';
  mmDCP3_GRPH_Y_START                                      :Result:='mmDCP3_GRPH_Y_START';
  mmDCP3_GRPH_X_END                                        :Result:='mmDCP3_GRPH_X_END';
  mmDCP3_GRPH_Y_END                                        :Result:='mmDCP3_GRPH_Y_END';
  mmDCP3_INPUT_GAMMA_CONTROL                               :Result:='mmDCP3_INPUT_GAMMA_CONTROL';
  mmDCP3_GRPH_UPDATE                                       :Result:='mmDCP3_GRPH_UPDATE';
  mmDCP3_GRPH_FLIP_CONTROL                                 :Result:='mmDCP3_GRPH_FLIP_CONTROL';
  mmDCP3_GRPH_SURFACE_ADDRESS_INUSE                        :Result:='mmDCP3_GRPH_SURFACE_ADDRESS_INUSE';
  mmDCP3_GRPH_DFQ_CONTROL                                  :Result:='mmDCP3_GRPH_DFQ_CONTROL';
  mmDCP3_GRPH_DFQ_STATUS                                   :Result:='mmDCP3_GRPH_DFQ_STATUS';
  mmDCP3_GRPH_INTERRUPT_STATUS                             :Result:='mmDCP3_GRPH_INTERRUPT_STATUS';
  mmDCP3_GRPH_INTERRUPT_CONTROL                            :Result:='mmDCP3_GRPH_INTERRUPT_CONTROL';
  mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE                   :Result:='mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE';
  mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS                     :Result:='mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS';
  mmDCP3_GRPH_COMPRESS_PITCH                               :Result:='mmDCP3_GRPH_COMPRESS_PITCH';
  mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                :Result:='mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH';
  mmDCP3_OVL_ENABLE                                        :Result:='mmDCP3_OVL_ENABLE';
  mmDCP3_OVL_CONTROL1                                      :Result:='mmDCP3_OVL_CONTROL1';
  mmDCP3_OVL_CONTROL2                                      :Result:='mmDCP3_OVL_CONTROL2';
  mmDCP3_OVL_SWAP_CNTL                                     :Result:='mmDCP3_OVL_SWAP_CNTL';
  mmDCP3_OVL_SURFACE_ADDRESS                               :Result:='mmDCP3_OVL_SURFACE_ADDRESS';
  mmDCP3_OVL_PITCH                                         :Result:='mmDCP3_OVL_PITCH';
  mmDCP3_OVL_SURFACE_ADDRESS_HIGH                          :Result:='mmDCP3_OVL_SURFACE_ADDRESS_HIGH';
  mmDCP3_OVL_SURFACE_OFFSET_X                              :Result:='mmDCP3_OVL_SURFACE_OFFSET_X';
  mmDCP3_OVL_SURFACE_OFFSET_Y                              :Result:='mmDCP3_OVL_SURFACE_OFFSET_Y';
  mmDCP3_OVL_START                                         :Result:='mmDCP3_OVL_START';
  mmDCP3_OVL_END                                           :Result:='mmDCP3_OVL_END';
  mmDCP3_OVL_UPDATE                                        :Result:='mmDCP3_OVL_UPDATE';
  mmDCP3_OVL_SURFACE_ADDRESS_INUSE                         :Result:='mmDCP3_OVL_SURFACE_ADDRESS_INUSE';
  mmDCP3_OVL_DFQ_CONTROL                                   :Result:='mmDCP3_OVL_DFQ_CONTROL';
  mmDCP3_OVL_DFQ_STATUS                                    :Result:='mmDCP3_OVL_DFQ_STATUS';
  mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE                    :Result:='mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE';
  mmDCP3_OVLSCL_EDGE_PIXEL_CNTL                            :Result:='mmDCP3_OVLSCL_EDGE_PIXEL_CNTL';
  mmDCP3_PRESCALE_GRPH_CONTROL                             :Result:='mmDCP3_PRESCALE_GRPH_CONTROL';
  mmDCP3_PRESCALE_VALUES_GRPH_R                            :Result:='mmDCP3_PRESCALE_VALUES_GRPH_R';
  mmDCP3_PRESCALE_VALUES_GRPH_G                            :Result:='mmDCP3_PRESCALE_VALUES_GRPH_G';
  mmDCP3_PRESCALE_VALUES_GRPH_B                            :Result:='mmDCP3_PRESCALE_VALUES_GRPH_B';
  mmDCP3_PRESCALE_OVL_CONTROL                              :Result:='mmDCP3_PRESCALE_OVL_CONTROL';
  mmDCP3_PRESCALE_VALUES_OVL_CB                            :Result:='mmDCP3_PRESCALE_VALUES_OVL_CB';
  mmDCP3_PRESCALE_VALUES_OVL_Y                             :Result:='mmDCP3_PRESCALE_VALUES_OVL_Y';
  mmDCP3_PRESCALE_VALUES_OVL_CR                            :Result:='mmDCP3_PRESCALE_VALUES_OVL_CR';
  mmDCP3_INPUT_CSC_CONTROL                                 :Result:='mmDCP3_INPUT_CSC_CONTROL';
  mmDCP3_INPUT_CSC_C11_C12                                 :Result:='mmDCP3_INPUT_CSC_C11_C12';
  mmDCP3_INPUT_CSC_C13_C14                                 :Result:='mmDCP3_INPUT_CSC_C13_C14';
  mmDCP3_INPUT_CSC_C21_C22                                 :Result:='mmDCP3_INPUT_CSC_C21_C22';
  mmDCP3_INPUT_CSC_C23_C24                                 :Result:='mmDCP3_INPUT_CSC_C23_C24';
  mmDCP3_INPUT_CSC_C31_C32                                 :Result:='mmDCP3_INPUT_CSC_C31_C32';
  mmDCP3_INPUT_CSC_C33_C34                                 :Result:='mmDCP3_INPUT_CSC_C33_C34';
  mmDCP3_OUTPUT_CSC_CONTROL                                :Result:='mmDCP3_OUTPUT_CSC_CONTROL';
  mmDCP3_OUTPUT_CSC_C11_C12                                :Result:='mmDCP3_OUTPUT_CSC_C11_C12';
  mmDCP3_OUTPUT_CSC_C13_C14                                :Result:='mmDCP3_OUTPUT_CSC_C13_C14';
  mmDCP3_OUTPUT_CSC_C21_C22                                :Result:='mmDCP3_OUTPUT_CSC_C21_C22';
  mmDCP3_OUTPUT_CSC_C23_C24                                :Result:='mmDCP3_OUTPUT_CSC_C23_C24';
  mmDCP3_OUTPUT_CSC_C31_C32                                :Result:='mmDCP3_OUTPUT_CSC_C31_C32';
  mmDCP3_OUTPUT_CSC_C33_C34                                :Result:='mmDCP3_OUTPUT_CSC_C33_C34';
  mmDCP3_COMM_MATRIXA_TRANS_C11_C12                        :Result:='mmDCP3_COMM_MATRIXA_TRANS_C11_C12';
  mmDCP3_COMM_MATRIXA_TRANS_C13_C14                        :Result:='mmDCP3_COMM_MATRIXA_TRANS_C13_C14';
  mmDCP3_COMM_MATRIXA_TRANS_C21_C22                        :Result:='mmDCP3_COMM_MATRIXA_TRANS_C21_C22';
  mmDCP3_COMM_MATRIXA_TRANS_C23_C24                        :Result:='mmDCP3_COMM_MATRIXA_TRANS_C23_C24';
  mmDCP3_COMM_MATRIXA_TRANS_C31_C32                        :Result:='mmDCP3_COMM_MATRIXA_TRANS_C31_C32';
  mmDCP3_COMM_MATRIXA_TRANS_C33_C34                        :Result:='mmDCP3_COMM_MATRIXA_TRANS_C33_C34';
  mmDCP3_COMM_MATRIXB_TRANS_C11_C12                        :Result:='mmDCP3_COMM_MATRIXB_TRANS_C11_C12';
  mmDCP3_COMM_MATRIXB_TRANS_C13_C14                        :Result:='mmDCP3_COMM_MATRIXB_TRANS_C13_C14';
  mmDCP3_COMM_MATRIXB_TRANS_C21_C22                        :Result:='mmDCP3_COMM_MATRIXB_TRANS_C21_C22';
  mmDCP3_COMM_MATRIXB_TRANS_C23_C24                        :Result:='mmDCP3_COMM_MATRIXB_TRANS_C23_C24';
  mmDCP3_COMM_MATRIXB_TRANS_C31_C32                        :Result:='mmDCP3_COMM_MATRIXB_TRANS_C31_C32';
  mmDCP3_COMM_MATRIXB_TRANS_C33_C34                        :Result:='mmDCP3_COMM_MATRIXB_TRANS_C33_C34';
  mmDCP3_DENORM_CONTROL                                    :Result:='mmDCP3_DENORM_CONTROL';
  mmDCP3_OUT_ROUND_CONTROL                                 :Result:='mmDCP3_OUT_ROUND_CONTROL';
  mmDCP3_OUT_CLAMP_CONTROL_R_CR                            :Result:='mmDCP3_OUT_CLAMP_CONTROL_R_CR';
  mmDCP3_KEY_CONTROL                                       :Result:='mmDCP3_KEY_CONTROL';
  mmDCP3_KEY_RANGE_ALPHA                                   :Result:='mmDCP3_KEY_RANGE_ALPHA';
  mmDCP3_KEY_RANGE_RED                                     :Result:='mmDCP3_KEY_RANGE_RED';
  mmDCP3_KEY_RANGE_GREEN                                   :Result:='mmDCP3_KEY_RANGE_GREEN';
  mmDCP3_KEY_RANGE_BLUE                                    :Result:='mmDCP3_KEY_RANGE_BLUE';
  mmDCP3_DEGAMMA_CONTROL                                   :Result:='mmDCP3_DEGAMMA_CONTROL';
  mmDCP3_GAMUT_REMAP_CONTROL                               :Result:='mmDCP3_GAMUT_REMAP_CONTROL';
  mmDCP3_GAMUT_REMAP_C11_C12                               :Result:='mmDCP3_GAMUT_REMAP_C11_C12';
  mmDCP3_GAMUT_REMAP_C13_C14                               :Result:='mmDCP3_GAMUT_REMAP_C13_C14';
  mmDCP3_GAMUT_REMAP_C21_C22                               :Result:='mmDCP3_GAMUT_REMAP_C21_C22';
  mmDCP3_GAMUT_REMAP_C23_C24                               :Result:='mmDCP3_GAMUT_REMAP_C23_C24';
  mmDCP3_GAMUT_REMAP_C31_C32                               :Result:='mmDCP3_GAMUT_REMAP_C31_C32';
  mmDCP3_GAMUT_REMAP_C33_C34                               :Result:='mmDCP3_GAMUT_REMAP_C33_C34';
  mmDCP3_DCP_SPATIAL_DITHER_CNTL                           :Result:='mmDCP3_DCP_SPATIAL_DITHER_CNTL';
  mmDCP3_DCP_RANDOM_SEEDS                                  :Result:='mmDCP3_DCP_RANDOM_SEEDS';
  mmDCP3_DCP_FP_CONVERTED_FIELD                            :Result:='mmDCP3_DCP_FP_CONVERTED_FIELD';
  mmDCP3_CUR_CONTROL                                       :Result:='mmDCP3_CUR_CONTROL';
  mmDCP3_CUR_SURFACE_ADDRESS                               :Result:='mmDCP3_CUR_SURFACE_ADDRESS';
  mmDCP3_CUR_SIZE                                          :Result:='mmDCP3_CUR_SIZE';
  mmDCP3_CUR_SURFACE_ADDRESS_HIGH                          :Result:='mmDCP3_CUR_SURFACE_ADDRESS_HIGH';
  mmDCP3_CUR_POSITION                                      :Result:='mmDCP3_CUR_POSITION';
  mmDCP3_CUR_HOT_SPOT                                      :Result:='mmDCP3_CUR_HOT_SPOT';
  mmDCP3_CUR_COLOR1                                        :Result:='mmDCP3_CUR_COLOR1';
  mmDCP3_CUR_COLOR2                                        :Result:='mmDCP3_CUR_COLOR2';
  mmDCP3_CUR_UPDATE                                        :Result:='mmDCP3_CUR_UPDATE';
  mmDCP3_CUR2_CONTROL                                      :Result:='mmDCP3_CUR2_CONTROL';
  mmDCP3_CUR2_SURFACE_ADDRESS                              :Result:='mmDCP3_CUR2_SURFACE_ADDRESS';
  mmDCP3_CUR2_SIZE                                         :Result:='mmDCP3_CUR2_SIZE';
  mmDCP3_CUR2_SURFACE_ADDRESS_HIGH                         :Result:='mmDCP3_CUR2_SURFACE_ADDRESS_HIGH';
  mmDCP3_CUR2_POSITION                                     :Result:='mmDCP3_CUR2_POSITION';
  mmDCP3_CUR2_HOT_SPOT                                     :Result:='mmDCP3_CUR2_HOT_SPOT';
  mmDCP3_CUR2_COLOR1                                       :Result:='mmDCP3_CUR2_COLOR1';
  mmDCP3_CUR2_COLOR2                                       :Result:='mmDCP3_CUR2_COLOR2';
  mmDCP3_CUR2_UPDATE                                       :Result:='mmDCP3_CUR2_UPDATE';
  mmDCP3_DC_LUT_RW_MODE                                    :Result:='mmDCP3_DC_LUT_RW_MODE';
  mmDCP3_DC_LUT_RW_INDEX                                   :Result:='mmDCP3_DC_LUT_RW_INDEX';
  mmDCP3_DC_LUT_SEQ_COLOR                                  :Result:='mmDCP3_DC_LUT_SEQ_COLOR';
  mmDCP3_DC_LUT_PWL_DATA                                   :Result:='mmDCP3_DC_LUT_PWL_DATA';
  mmDCP3_DC_LUT_30_COLOR                                   :Result:='mmDCP3_DC_LUT_30_COLOR';
  mmDCP3_DC_LUT_VGA_ACCESS_ENABLE                          :Result:='mmDCP3_DC_LUT_VGA_ACCESS_ENABLE';
  mmDCP3_DC_LUT_WRITE_EN_MASK                              :Result:='mmDCP3_DC_LUT_WRITE_EN_MASK';
  mmDCP3_DC_LUT_AUTOFILL                                   :Result:='mmDCP3_DC_LUT_AUTOFILL';
  mmDCP3_DC_LUT_CONTROL                                    :Result:='mmDCP3_DC_LUT_CONTROL';
  mmDCP3_DC_LUT_BLACK_OFFSET_BLUE                          :Result:='mmDCP3_DC_LUT_BLACK_OFFSET_BLUE';
  mmDCP3_DC_LUT_BLACK_OFFSET_GREEN                         :Result:='mmDCP3_DC_LUT_BLACK_OFFSET_GREEN';
  mmDCP3_DC_LUT_BLACK_OFFSET_RED                           :Result:='mmDCP3_DC_LUT_BLACK_OFFSET_RED';
  mmDCP3_DC_LUT_WHITE_OFFSET_BLUE                          :Result:='mmDCP3_DC_LUT_WHITE_OFFSET_BLUE';
  mmDCP3_DC_LUT_WHITE_OFFSET_GREEN                         :Result:='mmDCP3_DC_LUT_WHITE_OFFSET_GREEN';
  mmDCP3_DC_LUT_WHITE_OFFSET_RED                           :Result:='mmDCP3_DC_LUT_WHITE_OFFSET_RED';
  mmDCP3_DCP_CRC_CONTROL                                   :Result:='mmDCP3_DCP_CRC_CONTROL';
  mmDCP3_DCP_CRC_MASK                                      :Result:='mmDCP3_DCP_CRC_MASK';
  mmDCP3_DCP_CRC_CURRENT                                   :Result:='mmDCP3_DCP_CRC_CURRENT';
  mmDCP3_DCP_CRC_LAST                                      :Result:='mmDCP3_DCP_CRC_LAST';
  mmDCP3_DCP_DEBUG                                         :Result:='mmDCP3_DCP_DEBUG';
  mmDCP3_GRPH_FLIP_RATE_CNTL                               :Result:='mmDCP3_GRPH_FLIP_RATE_CNTL';
  mmDCP3_DCP_GSL_CONTROL                                   :Result:='mmDCP3_DCP_GSL_CONTROL';
  mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK                     :Result:='mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK';
  mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS                     :Result:='mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS';
  mmDCP3_OVL_STEREOSYNC_FLIP                               :Result:='mmDCP3_OVL_STEREOSYNC_FLIP';
  mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                :Result:='mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH';
  mmDCP3_DCP_TEST_DEBUG_INDEX                              :Result:='mmDCP3_DCP_TEST_DEBUG_INDEX';
  mmDCP3_DCP_TEST_DEBUG_DATA                               :Result:='mmDCP3_DCP_TEST_DEBUG_DATA';
  mmDCP3_GRPH_STEREOSYNC_FLIP                              :Result:='mmDCP3_GRPH_STEREOSYNC_FLIP';
  mmDCP3_DCP_DEBUG2                                        :Result:='mmDCP3_DCP_DEBUG2';
  mmDCP3_CUR_REQUEST_FILTER_CNTL                           :Result:='mmDCP3_CUR_REQUEST_FILTER_CNTL';
  mmDCP3_CUR_STEREO_CONTROL                                :Result:='mmDCP3_CUR_STEREO_CONTROL';
  mmDCP3_CUR2_STEREO_CONTROL                               :Result:='mmDCP3_CUR2_STEREO_CONTROL';
  mmDCP3_OUT_CLAMP_CONTROL_G_Y                             :Result:='mmDCP3_OUT_CLAMP_CONTROL_G_Y';
  mmDCP3_OUT_CLAMP_CONTROL_B_CB                            :Result:='mmDCP3_OUT_CLAMP_CONTROL_B_CB';
  mmDCP3_HW_ROTATION                                       :Result:='mmDCP3_HW_ROTATION';
  mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                :Result:='mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL';
  mmDCP3_REGAMMA_CONTROL                                   :Result:='mmDCP3_REGAMMA_CONTROL';
  mmDCP3_REGAMMA_LUT_INDEX                                 :Result:='mmDCP3_REGAMMA_LUT_INDEX';
  mmDCP3_REGAMMA_LUT_DATA                                  :Result:='mmDCP3_REGAMMA_LUT_DATA';
  mmDCP3_REGAMMA_LUT_WRITE_EN_MASK                         :Result:='mmDCP3_REGAMMA_LUT_WRITE_EN_MASK';
  mmDCP3_REGAMMA_CNTLA_START_CNTL                          :Result:='mmDCP3_REGAMMA_CNTLA_START_CNTL';
  mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL                          :Result:='mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL';
  mmDCP3_REGAMMA_CNTLA_END_CNTL1                           :Result:='mmDCP3_REGAMMA_CNTLA_END_CNTL1';
  mmDCP3_REGAMMA_CNTLA_END_CNTL2                           :Result:='mmDCP3_REGAMMA_CNTLA_END_CNTL2';
  mmDCP3_REGAMMA_CNTLA_REGION_0_1                          :Result:='mmDCP3_REGAMMA_CNTLA_REGION_0_1';
  mmDCP3_REGAMMA_CNTLA_REGION_2_3                          :Result:='mmDCP3_REGAMMA_CNTLA_REGION_2_3';
  mmDCP3_REGAMMA_CNTLA_REGION_4_5                          :Result:='mmDCP3_REGAMMA_CNTLA_REGION_4_5';
  mmDCP3_REGAMMA_CNTLA_REGION_6_7                          :Result:='mmDCP3_REGAMMA_CNTLA_REGION_6_7';
  mmDCP3_REGAMMA_CNTLA_REGION_8_9                          :Result:='mmDCP3_REGAMMA_CNTLA_REGION_8_9';
  mmDCP3_REGAMMA_CNTLA_REGION_10_11                        :Result:='mmDCP3_REGAMMA_CNTLA_REGION_10_11';
  mmDCP3_REGAMMA_CNTLA_REGION_12_13                        :Result:='mmDCP3_REGAMMA_CNTLA_REGION_12_13';
  mmDCP3_REGAMMA_CNTLA_REGION_14_15                        :Result:='mmDCP3_REGAMMA_CNTLA_REGION_14_15';
  mmDCP3_REGAMMA_CNTLB_START_CNTL                          :Result:='mmDCP3_REGAMMA_CNTLB_START_CNTL';
  mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL                          :Result:='mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL';
  mmDCP3_REGAMMA_CNTLB_END_CNTL1                           :Result:='mmDCP3_REGAMMA_CNTLB_END_CNTL1';
  mmDCP3_REGAMMA_CNTLB_END_CNTL2                           :Result:='mmDCP3_REGAMMA_CNTLB_END_CNTL2';
  mmDCP3_REGAMMA_CNTLB_REGION_0_1                          :Result:='mmDCP3_REGAMMA_CNTLB_REGION_0_1';
  mmDCP3_REGAMMA_CNTLB_REGION_2_3                          :Result:='mmDCP3_REGAMMA_CNTLB_REGION_2_3';
  mmDCP3_REGAMMA_CNTLB_REGION_4_5                          :Result:='mmDCP3_REGAMMA_CNTLB_REGION_4_5';
  mmDCP3_REGAMMA_CNTLB_REGION_6_7                          :Result:='mmDCP3_REGAMMA_CNTLB_REGION_6_7';
  mmDCP3_REGAMMA_CNTLB_REGION_8_9                          :Result:='mmDCP3_REGAMMA_CNTLB_REGION_8_9';
  mmDCP3_REGAMMA_CNTLB_REGION_10_11                        :Result:='mmDCP3_REGAMMA_CNTLB_REGION_10_11';
  mmDCP3_REGAMMA_CNTLB_REGION_12_13                        :Result:='mmDCP3_REGAMMA_CNTLB_REGION_12_13';
  mmDCP3_REGAMMA_CNTLB_REGION_14_15                        :Result:='mmDCP3_REGAMMA_CNTLB_REGION_14_15';
  mmDCP3_ALPHA_CONTROL                                     :Result:='mmDCP3_ALPHA_CONTROL';
  mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                :Result:='mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS';
  mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH           :Result:='mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH';
  mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS              :Result:='mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS';
  mmLB3_LB_DATA_FORMAT                                     :Result:='mmLB3_LB_DATA_FORMAT';
  mmLB3_LB_MEMORY_CTRL                                     :Result:='mmLB3_LB_MEMORY_CTRL';
  mmLB3_LB_MEMORY_SIZE_STATUS                              :Result:='mmLB3_LB_MEMORY_SIZE_STATUS';
  mmLB3_LB_DESKTOP_HEIGHT                                  :Result:='mmLB3_LB_DESKTOP_HEIGHT';
  mmLB3_LB_VLINE_START_END                                 :Result:='mmLB3_LB_VLINE_START_END';
  mmLB3_LB_VLINE2_START_END                                :Result:='mmLB3_LB_VLINE2_START_END';
  mmLB3_LB_V_COUNTER                                       :Result:='mmLB3_LB_V_COUNTER';
  mmLB3_LB_SNAPSHOT_V_COUNTER                              :Result:='mmLB3_LB_SNAPSHOT_V_COUNTER';
  mmLB3_LB_INTERRUPT_MASK                                  :Result:='mmLB3_LB_INTERRUPT_MASK';
  mmLB3_LB_VLINE_STATUS                                    :Result:='mmLB3_LB_VLINE_STATUS';
  mmLB3_LB_VLINE2_STATUS                                   :Result:='mmLB3_LB_VLINE2_STATUS';
  mmLB3_LB_VBLANK_STATUS                                   :Result:='mmLB3_LB_VBLANK_STATUS';
  mmLB3_LB_SYNC_RESET_SEL                                  :Result:='mmLB3_LB_SYNC_RESET_SEL';
  mmLB3_LB_BLACK_KEYER_R_CR                                :Result:='mmLB3_LB_BLACK_KEYER_R_CR';
  mmLB3_LB_BLACK_KEYER_G_Y                                 :Result:='mmLB3_LB_BLACK_KEYER_G_Y';
  mmLB3_LB_BLACK_KEYER_B_CB                                :Result:='mmLB3_LB_BLACK_KEYER_B_CB';
  mmLB3_LB_KEYER_COLOR_CTRL                                :Result:='mmLB3_LB_KEYER_COLOR_CTRL';
  mmLB3_LB_KEYER_COLOR_R_CR                                :Result:='mmLB3_LB_KEYER_COLOR_R_CR';
  mmLB3_LB_KEYER_COLOR_G_Y                                 :Result:='mmLB3_LB_KEYER_COLOR_G_Y';
  mmLB3_LB_KEYER_COLOR_B_CB                                :Result:='mmLB3_LB_KEYER_COLOR_B_CB';
  mmLB3_LB_KEYER_COLOR_REP_R_CR                            :Result:='mmLB3_LB_KEYER_COLOR_REP_R_CR';
  mmLB3_LB_KEYER_COLOR_REP_G_Y                             :Result:='mmLB3_LB_KEYER_COLOR_REP_G_Y';
  mmLB3_LB_KEYER_COLOR_REP_B_CB                            :Result:='mmLB3_LB_KEYER_COLOR_REP_B_CB';
  mmLB3_LB_BUFFER_LEVEL_STATUS                             :Result:='mmLB3_LB_BUFFER_LEVEL_STATUS';
  mmLB3_LB_BUFFER_URGENCY_CTRL                             :Result:='mmLB3_LB_BUFFER_URGENCY_CTRL';
  mmLB3_LB_BUFFER_URGENCY_STATUS                           :Result:='mmLB3_LB_BUFFER_URGENCY_STATUS';
  mmLB3_LB_BUFFER_STATUS                                   :Result:='mmLB3_LB_BUFFER_STATUS';
  mmLB2_DC_MVP_LB_CONTROL                                  :Result:='mmLB2_DC_MVP_LB_CONTROL';
  mmLB3_LB_NO_OUTSTANDING_REQ_STATUS                       :Result:='mmLB3_LB_NO_OUTSTANDING_REQ_STATUS';
  mmLB3_MVP_AFR_FLIP_MODE                                  :Result:='mmLB3_MVP_AFR_FLIP_MODE';
  mmLB3_MVP_AFR_FLIP_FIFO_CNTL                             :Result:='mmLB3_MVP_AFR_FLIP_FIFO_CNTL';
  mmLB3_MVP_FLIP_LINE_NUM_INSERT                           :Result:='mmLB3_MVP_FLIP_LINE_NUM_INSERT';
  mmLB3_DC_MVP_LB_CONTROL                                  :Result:='mmLB3_DC_MVP_LB_CONTROL';
  mmLB3_LB_DEBUG                                           :Result:='mmLB3_LB_DEBUG';
  mmLB3_LB_DEBUG2                                          :Result:='mmLB3_LB_DEBUG2';
  mmLB3_LB_DEBUG3                                          :Result:='mmLB3_LB_DEBUG3';
  mmLB2_LB_DEBUG                                           :Result:='mmLB2_LB_DEBUG';
  mmLB3_LB_TEST_DEBUG_INDEX                                :Result:='mmLB3_LB_TEST_DEBUG_INDEX';
  mmLB3_LB_TEST_DEBUG_DATA                                 :Result:='mmLB3_LB_TEST_DEBUG_DATA';
  mmDCFE3_DCFE_CLOCK_CONTROL                               :Result:='mmDCFE3_DCFE_CLOCK_CONTROL';
  mmDCFE3_DCFE_SOFT_RESET                                  :Result:='mmDCFE3_DCFE_SOFT_RESET';
  mmDCFE3_DCFE_DBG_CONFIG                                  :Result:='mmDCFE3_DCFE_DBG_CONFIG';
  mmDC_PERFMON6_PERFCOUNTER_CNTL                           :Result:='mmDC_PERFMON6_PERFCOUNTER_CNTL';
  mmDC_PERFMON6_PERFCOUNTER_STATE                          :Result:='mmDC_PERFMON6_PERFCOUNTER_STATE';
  mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                    :Result:='mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC';
  mmDC_PERFMON6_PERFMON_CNTL                               :Result:='mmDC_PERFMON6_PERFMON_CNTL';
  mmDC_PERFMON6_PERFMON_CVALUE_LOW                         :Result:='mmDC_PERFMON6_PERFMON_CVALUE_LOW';
  mmDC_PERFMON6_PERFMON_HI                                 :Result:='mmDC_PERFMON6_PERFMON_HI';
  mmDC_PERFMON6_PERFMON_LOW                                :Result:='mmDC_PERFMON6_PERFMON_LOW';
  mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX                   :Result:='mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX';
  mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA                    :Result:='mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA';
  mmDC_PERFMON6_PERFMON_CNTL2                              :Result:='mmDC_PERFMON6_PERFMON_CNTL2';
  mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1                 :Result:='mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1';
  mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2                 :Result:='mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2';
  mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL                    :Result:='mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL';
  mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL                      :Result:='mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL';
  mmDMIF_PG3_DPG_PIPE_DPM_CONTROL                          :Result:='mmDMIF_PG3_DPG_PIPE_DPM_CONTROL';
  mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL                      :Result:='mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL';
  mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             :Result:='mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL';
  mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             :Result:='mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH';
  mmDMIF_PG3_DPG_TEST_DEBUG_INDEX                          :Result:='mmDMIF_PG3_DPG_TEST_DEBUG_INDEX';
  mmDMIF_PG3_DPG_TEST_DEBUG_DATA                           :Result:='mmDMIF_PG3_DPG_TEST_DEBUG_DATA';
  mmDMIF_PG3_DPG_REPEATER_PROGRAM                          :Result:='mmDMIF_PG3_DPG_REPEATER_PROGRAM';
  mmDMIF_PG3_DPG_HW_DEBUG_A                                :Result:='mmDMIF_PG3_DPG_HW_DEBUG_A';
  mmDMIF_PG3_DPG_HW_DEBUG_B                                :Result:='mmDMIF_PG3_DPG_HW_DEBUG_B';
  mmDMIF_PG3_DPG_HW_DEBUG_11                               :Result:='mmDMIF_PG3_DPG_HW_DEBUG_11';
  mmSCL3_SCL_COEF_RAM_SELECT                               :Result:='mmSCL3_SCL_COEF_RAM_SELECT';
  mmSCL3_SCL_COEF_RAM_TAP_DATA                             :Result:='mmSCL3_SCL_COEF_RAM_TAP_DATA';
  mmSCL3_SCL_MODE                                          :Result:='mmSCL3_SCL_MODE';
  mmSCL3_SCL_TAP_CONTROL                                   :Result:='mmSCL3_SCL_TAP_CONTROL';
  mmSCL3_SCL_CONTROL                                       :Result:='mmSCL3_SCL_CONTROL';
  mmSCL3_SCL_BYPASS_CONTROL                                :Result:='mmSCL3_SCL_BYPASS_CONTROL';
  mmSCL3_SCL_MANUAL_REPLICATE_CONTROL                      :Result:='mmSCL3_SCL_MANUAL_REPLICATE_CONTROL';
  mmSCL3_SCL_AUTOMATIC_MODE_CONTROL                        :Result:='mmSCL3_SCL_AUTOMATIC_MODE_CONTROL';
  mmSCL3_SCL_HORZ_FILTER_CONTROL                           :Result:='mmSCL3_SCL_HORZ_FILTER_CONTROL';
  mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO                       :Result:='mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO';
  mmSCL3_SCL_HORZ_FILTER_INIT                              :Result:='mmSCL3_SCL_HORZ_FILTER_INIT';
  mmSCL3_SCL_VERT_FILTER_CONTROL                           :Result:='mmSCL3_SCL_VERT_FILTER_CONTROL';
  mmSCL3_SCL_VERT_FILTER_SCALE_RATIO                       :Result:='mmSCL3_SCL_VERT_FILTER_SCALE_RATIO';
  mmSCL3_SCL_VERT_FILTER_INIT                              :Result:='mmSCL3_SCL_VERT_FILTER_INIT';
  mmSCL3_SCL_VERT_FILTER_INIT_BOT                          :Result:='mmSCL3_SCL_VERT_FILTER_INIT_BOT';
  mmSCL3_SCL_ROUND_OFFSET                                  :Result:='mmSCL3_SCL_ROUND_OFFSET';
  mmSCL2_SCL_VERT_FILTER_INIT                              :Result:='mmSCL2_SCL_VERT_FILTER_INIT';
  mmSCL3_SCL_UPDATE                                        :Result:='mmSCL3_SCL_UPDATE';
  mmSCL3_SCL_F_SHARP_CONTROL                               :Result:='mmSCL3_SCL_F_SHARP_CONTROL';
  mmSCL3_SCL_ALU_CONTROL                                   :Result:='mmSCL3_SCL_ALU_CONTROL';
  mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS                      :Result:='mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS';
  mmSCL2_SCL_VERT_FILTER_INIT_BOT                          :Result:='mmSCL2_SCL_VERT_FILTER_INIT_BOT';
  mmSCL3_VIEWPORT_START_SECONDARY                          :Result:='mmSCL3_VIEWPORT_START_SECONDARY';
  mmSCL3_VIEWPORT_START                                    :Result:='mmSCL3_VIEWPORT_START';
  mmSCL3_VIEWPORT_SIZE                                     :Result:='mmSCL3_VIEWPORT_SIZE';
  mmSCL3_EXT_OVERSCAN_LEFT_RIGHT                           :Result:='mmSCL3_EXT_OVERSCAN_LEFT_RIGHT';
  mmSCL3_EXT_OVERSCAN_TOP_BOTTOM                           :Result:='mmSCL3_EXT_OVERSCAN_TOP_BOTTOM';
  mmSCL3_SCL_MODE_CHANGE_DET1                              :Result:='mmSCL3_SCL_MODE_CHANGE_DET1';
  mmSCL3_SCL_MODE_CHANGE_DET2                              :Result:='mmSCL3_SCL_MODE_CHANGE_DET2';
  mmSCL3_SCL_MODE_CHANGE_DET3                              :Result:='mmSCL3_SCL_MODE_CHANGE_DET3';
  mmSCL3_SCL_MODE_CHANGE_MASK                              :Result:='mmSCL3_SCL_MODE_CHANGE_MASK';
  mmSCL3_SCL_DEBUG2                                        :Result:='mmSCL3_SCL_DEBUG2';
  mmSCL3_SCL_DEBUG                                         :Result:='mmSCL3_SCL_DEBUG';
  mmSCL3_SCL_TEST_DEBUG_INDEX                              :Result:='mmSCL3_SCL_TEST_DEBUG_INDEX';
  mmSCL3_SCL_TEST_DEBUG_DATA                               :Result:='mmSCL3_SCL_TEST_DEBUG_DATA';
  mmBLND3_BLND_CONTROL                                     :Result:='mmBLND3_BLND_CONTROL';
  mmBLND3_SM_CONTROL2                                      :Result:='mmBLND3_SM_CONTROL2';
  mmBLND3_BLND_CONTROL2                                    :Result:='mmBLND3_BLND_CONTROL2';
  mmBLND3_BLND_UPDATE                                      :Result:='mmBLND3_BLND_UPDATE';
  mmBLND3_BLND_UNDERFLOW_INTERRUPT                         :Result:='mmBLND3_BLND_UNDERFLOW_INTERRUPT';
  mmBLND3_BLND_V_UPDATE_LOCK                               :Result:='mmBLND3_BLND_V_UPDATE_LOCK';
  mmBLND3_BLND_DEBUG                                       :Result:='mmBLND3_BLND_DEBUG';
  mmBLND3_BLND_TEST_DEBUG_INDEX                            :Result:='mmBLND3_BLND_TEST_DEBUG_INDEX';
  mmBLND3_BLND_TEST_DEBUG_DATA                             :Result:='mmBLND3_BLND_TEST_DEBUG_DATA';
  mmBLND3_BLND_REG_UPDATE_STATUS                           :Result:='mmBLND3_BLND_REG_UPDATE_STATUS';
  mmCRTC3_CRTC_3D_STRUCTURE_CONTROL                        :Result:='mmCRTC3_CRTC_3D_STRUCTURE_CONTROL';
  mmCRTC3_CRTC_GSL_VSYNC_GAP                               :Result:='mmCRTC3_CRTC_GSL_VSYNC_GAP';
  mmCRTC3_CRTC_GSL_WINDOW                                  :Result:='mmCRTC3_CRTC_GSL_WINDOW';
  mmCRTC3_CRTC_GSL_CONTROL                                 :Result:='mmCRTC3_CRTC_GSL_CONTROL';
  mmCRTC3_CRTC_DCFE_CLOCK_CONTROL                          :Result:='mmCRTC3_CRTC_DCFE_CLOCK_CONTROL';
  mmCRTC3_CRTC_H_BLANK_EARLY_NUM                           :Result:='mmCRTC3_CRTC_H_BLANK_EARLY_NUM';
  mmCRTC3_DCFE_DBG_SEL                                     :Result:='mmCRTC3_DCFE_DBG_SEL';
  mmCRTC3_DCFE_MEM_PWR_CTRL                                :Result:='mmCRTC3_DCFE_MEM_PWR_CTRL';
  mmCRTC3_CRTC_H_TOTAL                                     :Result:='mmCRTC3_CRTC_H_TOTAL';
  mmCRTC3_CRTC_H_BLANK_START_END                           :Result:='mmCRTC3_CRTC_H_BLANK_START_END';
  mmCRTC3_CRTC_H_SYNC_A                                    :Result:='mmCRTC3_CRTC_H_SYNC_A';
  mmCRTC3_CRTC_H_SYNC_A_CNTL                               :Result:='mmCRTC3_CRTC_H_SYNC_A_CNTL';
  mmCRTC3_CRTC_H_SYNC_B                                    :Result:='mmCRTC3_CRTC_H_SYNC_B';
  mmCRTC3_CRTC_H_SYNC_B_CNTL                               :Result:='mmCRTC3_CRTC_H_SYNC_B_CNTL';
  mmCRTC3_CRTC_VBI_END                                     :Result:='mmCRTC3_CRTC_VBI_END';
  mmCRTC3_CRTC_V_TOTAL                                     :Result:='mmCRTC3_CRTC_V_TOTAL';
  mmCRTC3_CRTC_V_TOTAL_MIN                                 :Result:='mmCRTC3_CRTC_V_TOTAL_MIN';
  mmCRTC3_CRTC_V_TOTAL_MAX                                 :Result:='mmCRTC3_CRTC_V_TOTAL_MAX';
  mmCRTC3_CRTC_V_TOTAL_CONTROL                             :Result:='mmCRTC3_CRTC_V_TOTAL_CONTROL';
  mmCRTC3_CRTC_V_TOTAL_INT_STATUS                          :Result:='mmCRTC3_CRTC_V_TOTAL_INT_STATUS';
  mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS                        :Result:='mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS';
  mmCRTC3_CRTC_V_BLANK_START_END                           :Result:='mmCRTC3_CRTC_V_BLANK_START_END';
  mmCRTC3_CRTC_V_SYNC_A                                    :Result:='mmCRTC3_CRTC_V_SYNC_A';
  mmCRTC3_CRTC_V_SYNC_A_CNTL                               :Result:='mmCRTC3_CRTC_V_SYNC_A_CNTL';
  mmCRTC3_CRTC_V_SYNC_B                                    :Result:='mmCRTC3_CRTC_V_SYNC_B';
  mmCRTC3_CRTC_V_SYNC_B_CNTL                               :Result:='mmCRTC3_CRTC_V_SYNC_B_CNTL';
  mmCRTC3_CRTC_DTMTEST_CNTL                                :Result:='mmCRTC3_CRTC_DTMTEST_CNTL';
  mmCRTC3_CRTC_DTMTEST_STATUS_POSITION                     :Result:='mmCRTC3_CRTC_DTMTEST_STATUS_POSITION';
  mmCRTC3_CRTC_TRIGA_CNTL                                  :Result:='mmCRTC3_CRTC_TRIGA_CNTL';
  mmCRTC3_CRTC_TRIGA_MANUAL_TRIG                           :Result:='mmCRTC3_CRTC_TRIGA_MANUAL_TRIG';
  mmCRTC3_CRTC_TRIGB_CNTL                                  :Result:='mmCRTC3_CRTC_TRIGB_CNTL';
  mmCRTC3_CRTC_TRIGB_MANUAL_TRIG                           :Result:='mmCRTC3_CRTC_TRIGB_MANUAL_TRIG';
  mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL                        :Result:='mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL';
  mmCRTC3_CRTC_FLOW_CONTROL                                :Result:='mmCRTC3_CRTC_FLOW_CONTROL';
  mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE                       :Result:='mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE';
  mmCRTC3_CRTC_AVSYNC_COUNTER                              :Result:='mmCRTC3_CRTC_AVSYNC_COUNTER';
  mmCRTC3_CRTC_CONTROL                                     :Result:='mmCRTC3_CRTC_CONTROL';
  mmCRTC3_CRTC_BLANK_CONTROL                               :Result:='mmCRTC3_CRTC_BLANK_CONTROL';
  mmCRTC3_CRTC_INTERLACE_CONTROL                           :Result:='mmCRTC3_CRTC_INTERLACE_CONTROL';
  mmCRTC3_CRTC_INTERLACE_STATUS                            :Result:='mmCRTC3_CRTC_INTERLACE_STATUS';
  mmCRTC3_CRTC_FIELD_INDICATION_CONTROL                    :Result:='mmCRTC3_CRTC_FIELD_INDICATION_CONTROL';
  mmCRTC3_CRTC_PIXEL_DATA_READBACK0                        :Result:='mmCRTC3_CRTC_PIXEL_DATA_READBACK0';
  mmCRTC3_CRTC_PIXEL_DATA_READBACK1                        :Result:='mmCRTC3_CRTC_PIXEL_DATA_READBACK1';
  mmCRTC3_CRTC_STATUS                                      :Result:='mmCRTC3_CRTC_STATUS';
  mmCRTC3_CRTC_STATUS_POSITION                             :Result:='mmCRTC3_CRTC_STATUS_POSITION';
  mmCRTC3_CRTC_NOM_VERT_POSITION                           :Result:='mmCRTC3_CRTC_NOM_VERT_POSITION';
  mmCRTC3_CRTC_STATUS_FRAME_COUNT                          :Result:='mmCRTC3_CRTC_STATUS_FRAME_COUNT';
  mmCRTC3_CRTC_STATUS_VF_COUNT                             :Result:='mmCRTC3_CRTC_STATUS_VF_COUNT';
  mmCRTC3_CRTC_STATUS_HV_COUNT                             :Result:='mmCRTC3_CRTC_STATUS_HV_COUNT';
  mmCRTC3_CRTC_COUNT_CONTROL                               :Result:='mmCRTC3_CRTC_COUNT_CONTROL';
  mmCRTC3_CRTC_COUNT_RESET                                 :Result:='mmCRTC3_CRTC_COUNT_RESET';
  mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                :Result:='mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE';
  mmCRTC3_CRTC_VERT_SYNC_CONTROL                           :Result:='mmCRTC3_CRTC_VERT_SYNC_CONTROL';
  mmCRTC3_CRTC_STEREO_STATUS                               :Result:='mmCRTC3_CRTC_STEREO_STATUS';
  mmCRTC3_CRTC_STEREO_CONTROL                              :Result:='mmCRTC3_CRTC_STEREO_CONTROL';
  mmCRTC3_CRTC_SNAPSHOT_STATUS                             :Result:='mmCRTC3_CRTC_SNAPSHOT_STATUS';
  mmCRTC3_CRTC_SNAPSHOT_CONTROL                            :Result:='mmCRTC3_CRTC_SNAPSHOT_CONTROL';
  mmCRTC3_CRTC_SNAPSHOT_POSITION                           :Result:='mmCRTC3_CRTC_SNAPSHOT_POSITION';
  mmCRTC3_CRTC_SNAPSHOT_FRAME                              :Result:='mmCRTC3_CRTC_SNAPSHOT_FRAME';
  mmCRTC3_CRTC_START_LINE_CONTROL                          :Result:='mmCRTC3_CRTC_START_LINE_CONTROL';
  mmCRTC3_CRTC_INTERRUPT_CONTROL                           :Result:='mmCRTC3_CRTC_INTERRUPT_CONTROL';
  mmCRTC3_CRTC_UPDATE_LOCK                                 :Result:='mmCRTC3_CRTC_UPDATE_LOCK';
  mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL                       :Result:='mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL';
  mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE                  :Result:='mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE';
  mmCRTC3_DCFE_MEM_PWR_CTRL2                               :Result:='mmCRTC3_DCFE_MEM_PWR_CTRL2';
  mmCRTC3_DCFE_MEM_PWR_STATUS                              :Result:='mmCRTC3_DCFE_MEM_PWR_STATUS';
  mmCRTC3_CRTC_TEST_PATTERN_CONTROL                        :Result:='mmCRTC3_CRTC_TEST_PATTERN_CONTROL';
  mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS                     :Result:='mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS';
  mmCRTC3_CRTC_TEST_PATTERN_COLOR                          :Result:='mmCRTC3_CRTC_TEST_PATTERN_COLOR';
  mmCRTC3_MASTER_UPDATE_LOCK                               :Result:='mmCRTC3_MASTER_UPDATE_LOCK';
  mmCRTC3_MASTER_UPDATE_MODE                               :Result:='mmCRTC3_MASTER_UPDATE_MODE';
  mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT                      :Result:='mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT';
  mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                :Result:='mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER';
  mmCRTC3_CRTC_MVP_STATUS                                  :Result:='mmCRTC3_CRTC_MVP_STATUS';
  mmCRTC3_CRTC_MASTER_EN                                   :Result:='mmCRTC3_CRTC_MASTER_EN';
  mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT                        :Result:='mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT';
  mmCRTC3_CRTC_V_UPDATE_INT_STATUS                         :Result:='mmCRTC3_CRTC_V_UPDATE_INT_STATUS';
  mmCRTC3_CRTC_TEST_DEBUG_INDEX                            :Result:='mmCRTC3_CRTC_TEST_DEBUG_INDEX';
  mmCRTC3_CRTC_TEST_DEBUG_DATA                             :Result:='mmCRTC3_CRTC_TEST_DEBUG_DATA';
  mmCRTC3_CRTC_OVERSCAN_COLOR                              :Result:='mmCRTC3_CRTC_OVERSCAN_COLOR';
  mmCRTC3_CRTC_OVERSCAN_COLOR_EXT                          :Result:='mmCRTC3_CRTC_OVERSCAN_COLOR_EXT';
  mmCRTC3_CRTC_BLANK_DATA_COLOR                            :Result:='mmCRTC3_CRTC_BLANK_DATA_COLOR';
  mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT                        :Result:='mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT';
  mmCRTC3_CRTC_BLACK_COLOR                                 :Result:='mmCRTC3_CRTC_BLACK_COLOR';
  mmCRTC3_CRTC_BLACK_COLOR_EXT                             :Result:='mmCRTC3_CRTC_BLACK_COLOR_EXT';
  mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION                :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION';
  mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL                 :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL';
  mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION                :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION';
  mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL                 :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL';
  mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION                :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION';
  mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL                 :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL';
  mmCRTC3_CRTC_CRC_CNTL                                    :Result:='mmCRTC3_CRTC_CRC_CNTL';
  mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL                      :Result:='mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL';
  mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL                      :Result:='mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL';
  mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL                      :Result:='mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL';
  mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL                      :Result:='mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL';
  mmCRTC3_CRTC_CRC0_DATA_RG                                :Result:='mmCRTC3_CRTC_CRC0_DATA_RG';
  mmCRTC3_CRTC_CRC0_DATA_B                                 :Result:='mmCRTC3_CRTC_CRC0_DATA_B';
  mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL                      :Result:='mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL';
  mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL                      :Result:='mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL';
  mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL                      :Result:='mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL';
  mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL                      :Result:='mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL';
  mmCRTC3_CRTC_CRC1_DATA_RG                                :Result:='mmCRTC3_CRTC_CRC1_DATA_RG';
  mmCRTC3_CRTC_CRC1_DATA_B                                 :Result:='mmCRTC3_CRTC_CRC1_DATA_B';
  mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL                     :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL';
  mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START                :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START';
  mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END                  :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END';
  mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL';
  mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL';
  mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL';
  mmCRTC3_CRTC_STATIC_SCREEN_CONTROL                       :Result:='mmCRTC3_CRTC_STATIC_SCREEN_CONTROL';
  mmFMT3_FMT_CLAMP_COMPONENT_R                             :Result:='mmFMT3_FMT_CLAMP_COMPONENT_R';
  mmFMT3_FMT_CLAMP_COMPONENT_G                             :Result:='mmFMT3_FMT_CLAMP_COMPONENT_G';
  mmFMT3_FMT_CLAMP_COMPONENT_B                             :Result:='mmFMT3_FMT_CLAMP_COMPONENT_B';
  mmFMT3_FMT_TEST_DEBUG_INDEX                              :Result:='mmFMT3_FMT_TEST_DEBUG_INDEX';
  mmFMT3_FMT_TEST_DEBUG_DATA                               :Result:='mmFMT3_FMT_TEST_DEBUG_DATA';
  mmFMT3_FMT_DYNAMIC_EXP_CNTL                              :Result:='mmFMT3_FMT_DYNAMIC_EXP_CNTL';
  mmFMT3_FMT_CONTROL                                       :Result:='mmFMT3_FMT_CONTROL';
  mmFMT3_FMT_FORCE_OUTPUT_CNTL                             :Result:='mmFMT3_FMT_FORCE_OUTPUT_CNTL';
  mmFMT3_FMT_FORCE_DATA_0_1                                :Result:='mmFMT3_FMT_FORCE_DATA_0_1';
  mmFMT3_FMT_FORCE_DATA_2_3                                :Result:='mmFMT3_FMT_FORCE_DATA_2_3';
  mmFMT3_FMT_BIT_DEPTH_CONTROL                             :Result:='mmFMT3_FMT_BIT_DEPTH_CONTROL';
  mmFMT3_FMT_DITHER_RAND_R_SEED                            :Result:='mmFMT3_FMT_DITHER_RAND_R_SEED';
  mmFMT3_FMT_DITHER_RAND_G_SEED                            :Result:='mmFMT3_FMT_DITHER_RAND_G_SEED';
  mmFMT3_FMT_DITHER_RAND_B_SEED                            :Result:='mmFMT3_FMT_DITHER_RAND_B_SEED';
  mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL               :Result:='mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL';
  mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :Result:='mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX';
  mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :Result:='mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX';
  mmFMT3_FMT_CLAMP_CNTL                                    :Result:='mmFMT3_FMT_CLAMP_CNTL';
  mmFMT3_FMT_CRC_CNTL                                      :Result:='mmFMT3_FMT_CRC_CNTL';
  mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK                        :Result:='mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK';
  mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK                     :Result:='mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK';
  mmFMT3_FMT_CRC_SIG_RED_GREEN                             :Result:='mmFMT3_FMT_CRC_SIG_RED_GREEN';
  mmFMT3_FMT_CRC_SIG_BLUE_CONTROL                          :Result:='mmFMT3_FMT_CRC_SIG_BLUE_CONTROL';
  mmFMT3_FMT_DEBUG_CNTL                                    :Result:='mmFMT3_FMT_DEBUG_CNTL';
  mmDCP4_GRPH_ENABLE                                       :Result:='mmDCP4_GRPH_ENABLE';
  mmDCP4_GRPH_CONTROL                                      :Result:='mmDCP4_GRPH_CONTROL';
  mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS                      :Result:='mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS';
  mmDCP4_GRPH_PITCH                                        :Result:='mmDCP4_GRPH_PITCH';
  mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                 :Result:='mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH';
  mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH               :Result:='mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH';
  mmDCP4_GRPH_SURFACE_OFFSET_X                             :Result:='mmDCP4_GRPH_SURFACE_OFFSET_X';
  mmDCP4_GRPH_SURFACE_OFFSET_Y                             :Result:='mmDCP4_GRPH_SURFACE_OFFSET_Y';
  mmDCP4_GRPH_X_START                                      :Result:='mmDCP4_GRPH_X_START';
  mmDCP4_INPUT_GAMMA_CONTROL                               :Result:='mmDCP4_INPUT_GAMMA_CONTROL';
  mmDCP4_GRPH_UPDATE                                       :Result:='mmDCP4_GRPH_UPDATE';
  mmDCP4_GRPH_FLIP_CONTROL                                 :Result:='mmDCP4_GRPH_FLIP_CONTROL';
  mmDCP4_GRPH_SURFACE_ADDRESS_INUSE                        :Result:='mmDCP4_GRPH_SURFACE_ADDRESS_INUSE';
  mmDCP4_GRPH_DFQ_CONTROL                                  :Result:='mmDCP4_GRPH_DFQ_CONTROL';
  mmDCP4_GRPH_DFQ_STATUS                                   :Result:='mmDCP4_GRPH_DFQ_STATUS';
  mmDCP4_OVL_SURFACE_ADDRESS                               :Result:='mmDCP4_OVL_SURFACE_ADDRESS';
  mmDCP4_OVL_UPDATE                                        :Result:='mmDCP4_OVL_UPDATE';
  mmDCP4_OVL_SURFACE_ADDRESS_INUSE                         :Result:='mmDCP4_OVL_SURFACE_ADDRESS_INUSE';
  mmDCP4_OVL_DFQ_CONTROL                                   :Result:='mmDCP4_OVL_DFQ_CONTROL';
  mmDCP4_OVL_DFQ_STATUS                                    :Result:='mmDCP4_OVL_DFQ_STATUS';
  mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE                    :Result:='mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE';
  mmDCP4_OVLSCL_EDGE_PIXEL_CNTL                            :Result:='mmDCP4_OVLSCL_EDGE_PIXEL_CNTL';
  mmDCP4_PRESCALE_GRPH_CONTROL                             :Result:='mmDCP4_PRESCALE_GRPH_CONTROL';
  mmDCP4_PRESCALE_VALUES_GRPH_R                            :Result:='mmDCP4_PRESCALE_VALUES_GRPH_R';
  mmDCP4_PRESCALE_VALUES_GRPH_G                            :Result:='mmDCP4_PRESCALE_VALUES_GRPH_G';
  mmDCP4_PRESCALE_VALUES_GRPH_B                            :Result:='mmDCP4_PRESCALE_VALUES_GRPH_B';
  mmDCP4_PRESCALE_OVL_CONTROL                              :Result:='mmDCP4_PRESCALE_OVL_CONTROL';
  mmDCP4_PRESCALE_VALUES_OVL_CB                            :Result:='mmDCP4_PRESCALE_VALUES_OVL_CB';
  mmDCP4_PRESCALE_VALUES_OVL_Y                             :Result:='mmDCP4_PRESCALE_VALUES_OVL_Y';
  mmDCP4_PRESCALE_VALUES_OVL_CR                            :Result:='mmDCP4_PRESCALE_VALUES_OVL_CR';
  mmDCP4_INPUT_CSC_CONTROL                                 :Result:='mmDCP4_INPUT_CSC_CONTROL';
  mmDCP4_INPUT_CSC_C11_C12                                 :Result:='mmDCP4_INPUT_CSC_C11_C12';
  mmDCP4_INPUT_CSC_C13_C14                                 :Result:='mmDCP4_INPUT_CSC_C13_C14';
  mmDCP4_INPUT_CSC_C21_C22                                 :Result:='mmDCP4_INPUT_CSC_C21_C22';
  mmDCP4_INPUT_CSC_C23_C24                                 :Result:='mmDCP4_INPUT_CSC_C23_C24';
  mmDCP4_INPUT_CSC_C31_C32                                 :Result:='mmDCP4_INPUT_CSC_C31_C32';
  mmDCP4_INPUT_CSC_C33_C34                                 :Result:='mmDCP4_INPUT_CSC_C33_C34';
  mmDCP4_OUTPUT_CSC_CONTROL                                :Result:='mmDCP4_OUTPUT_CSC_CONTROL';
  mmDCP4_OUTPUT_CSC_C11_C12                                :Result:='mmDCP4_OUTPUT_CSC_C11_C12';
  mmDCP4_OUTPUT_CSC_C13_C14                                :Result:='mmDCP4_OUTPUT_CSC_C13_C14';
  mmDCP4_OUTPUT_CSC_C21_C22                                :Result:='mmDCP4_OUTPUT_CSC_C21_C22';
  mmDCP4_OUTPUT_CSC_C23_C24                                :Result:='mmDCP4_OUTPUT_CSC_C23_C24';
  mmDCP4_OUTPUT_CSC_C31_C32                                :Result:='mmDCP4_OUTPUT_CSC_C31_C32';
  mmDCP4_OUTPUT_CSC_C33_C34                                :Result:='mmDCP4_OUTPUT_CSC_C33_C34';
  mmDCP4_COMM_MATRIXA_TRANS_C11_C12                        :Result:='mmDCP4_COMM_MATRIXA_TRANS_C11_C12';
  mmDCP4_COMM_MATRIXA_TRANS_C13_C14                        :Result:='mmDCP4_COMM_MATRIXA_TRANS_C13_C14';
  mmDCP4_COMM_MATRIXA_TRANS_C21_C22                        :Result:='mmDCP4_COMM_MATRIXA_TRANS_C21_C22';
  mmDCP4_COMM_MATRIXA_TRANS_C23_C24                        :Result:='mmDCP4_COMM_MATRIXA_TRANS_C23_C24';
  mmDCP4_COMM_MATRIXA_TRANS_C31_C32                        :Result:='mmDCP4_COMM_MATRIXA_TRANS_C31_C32';
  mmDCP4_COMM_MATRIXA_TRANS_C33_C34                        :Result:='mmDCP4_COMM_MATRIXA_TRANS_C33_C34';
  mmDCP4_COMM_MATRIXB_TRANS_C11_C12                        :Result:='mmDCP4_COMM_MATRIXB_TRANS_C11_C12';
  mmDCP4_COMM_MATRIXB_TRANS_C13_C14                        :Result:='mmDCP4_COMM_MATRIXB_TRANS_C13_C14';
  mmDCP4_COMM_MATRIXB_TRANS_C21_C22                        :Result:='mmDCP4_COMM_MATRIXB_TRANS_C21_C22';
  mmDCP4_COMM_MATRIXB_TRANS_C23_C24                        :Result:='mmDCP4_COMM_MATRIXB_TRANS_C23_C24';
  mmDCP4_COMM_MATRIXB_TRANS_C31_C32                        :Result:='mmDCP4_COMM_MATRIXB_TRANS_C31_C32';
  mmDCP4_COMM_MATRIXB_TRANS_C33_C34                        :Result:='mmDCP4_COMM_MATRIXB_TRANS_C33_C34';
  mmDCP4_DENORM_CONTROL                                    :Result:='mmDCP4_DENORM_CONTROL';
  mmDCP4_OUT_ROUND_CONTROL                                 :Result:='mmDCP4_OUT_ROUND_CONTROL';
  mmDCP4_OUT_CLAMP_CONTROL_R_CR                            :Result:='mmDCP4_OUT_CLAMP_CONTROL_R_CR';
  mmDCP4_KEY_CONTROL                                       :Result:='mmDCP4_KEY_CONTROL';
  mmDCP4_KEY_RANGE_ALPHA                                   :Result:='mmDCP4_KEY_RANGE_ALPHA';
  mmDCP4_KEY_RANGE_RED                                     :Result:='mmDCP4_KEY_RANGE_RED';
  mmDCP4_KEY_RANGE_GREEN                                   :Result:='mmDCP4_KEY_RANGE_GREEN';
  mmDCP4_KEY_RANGE_BLUE                                    :Result:='mmDCP4_KEY_RANGE_BLUE';
  mmDCP4_DEGAMMA_CONTROL                                   :Result:='mmDCP4_DEGAMMA_CONTROL';
  mmDCP4_GAMUT_REMAP_CONTROL                               :Result:='mmDCP4_GAMUT_REMAP_CONTROL';
  mmDCP4_GAMUT_REMAP_C11_C12                               :Result:='mmDCP4_GAMUT_REMAP_C11_C12';
  mmDCP4_GAMUT_REMAP_C13_C14                               :Result:='mmDCP4_GAMUT_REMAP_C13_C14';
  mmDCP4_GAMUT_REMAP_C21_C22                               :Result:='mmDCP4_GAMUT_REMAP_C21_C22';
  mmDCP4_GAMUT_REMAP_C23_C24                               :Result:='mmDCP4_GAMUT_REMAP_C23_C24';
  mmDCP4_GAMUT_REMAP_C31_C32                               :Result:='mmDCP4_GAMUT_REMAP_C31_C32';
  mmDCP4_GAMUT_REMAP_C33_C34                               :Result:='mmDCP4_GAMUT_REMAP_C33_C34';
  mmDCP4_DCP_SPATIAL_DITHER_CNTL                           :Result:='mmDCP4_DCP_SPATIAL_DITHER_CNTL';
  mmDCP4_DCP_RANDOM_SEEDS                                  :Result:='mmDCP4_DCP_RANDOM_SEEDS';
  mmDCP4_DCP_FP_CONVERTED_FIELD                            :Result:='mmDCP4_DCP_FP_CONVERTED_FIELD';
  mmDCP4_CUR_CONTROL                                       :Result:='mmDCP4_CUR_CONTROL';
  mmDCP4_CUR_SURFACE_ADDRESS                               :Result:='mmDCP4_CUR_SURFACE_ADDRESS';
  mmDCP4_CUR_SIZE                                          :Result:='mmDCP4_CUR_SIZE';
  mmDCP4_CUR_SURFACE_ADDRESS_HIGH                          :Result:='mmDCP4_CUR_SURFACE_ADDRESS_HIGH';
  mmDCP4_CUR_POSITION                                      :Result:='mmDCP4_CUR_POSITION';
  mmDCP4_CUR_HOT_SPOT                                      :Result:='mmDCP4_CUR_HOT_SPOT';
  mmDCP4_CUR_COLOR1                                        :Result:='mmDCP4_CUR_COLOR1';
  mmDCP4_CUR_COLOR2                                        :Result:='mmDCP4_CUR_COLOR2';
  mmDCP4_CUR_UPDATE                                        :Result:='mmDCP4_CUR_UPDATE';
  mmDCP4_CUR2_CONTROL                                      :Result:='mmDCP4_CUR2_CONTROL';
  mmDCP4_CUR2_SURFACE_ADDRESS                              :Result:='mmDCP4_CUR2_SURFACE_ADDRESS';
  mmDCP4_CUR2_SIZE                                         :Result:='mmDCP4_CUR2_SIZE';
  mmDCP4_CUR2_SURFACE_ADDRESS_HIGH                         :Result:='mmDCP4_CUR2_SURFACE_ADDRESS_HIGH';
  mmDCP4_CUR2_POSITION                                     :Result:='mmDCP4_CUR2_POSITION';
  mmDCP4_CUR2_HOT_SPOT                                     :Result:='mmDCP4_CUR2_HOT_SPOT';
  mmDCP4_CUR2_COLOR1                                       :Result:='mmDCP4_CUR2_COLOR1';
  mmDCP4_CUR2_COLOR2                                       :Result:='mmDCP4_CUR2_COLOR2';
  mmDCP4_CUR2_UPDATE                                       :Result:='mmDCP4_CUR2_UPDATE';
  mmDCP4_DC_LUT_RW_MODE                                    :Result:='mmDCP4_DC_LUT_RW_MODE';
  mmDCP4_DC_LUT_RW_INDEX                                   :Result:='mmDCP4_DC_LUT_RW_INDEX';
  mmDCP4_DC_LUT_SEQ_COLOR                                  :Result:='mmDCP4_DC_LUT_SEQ_COLOR';
  mmDCP4_DC_LUT_PWL_DATA                                   :Result:='mmDCP4_DC_LUT_PWL_DATA';
  mmDCP4_DC_LUT_VGA_ACCESS_ENABLE                          :Result:='mmDCP4_DC_LUT_VGA_ACCESS_ENABLE';
  mmDCP4_DC_LUT_WHITE_OFFSET_GREEN                         :Result:='mmDCP4_DC_LUT_WHITE_OFFSET_GREEN';
  mmDCP4_DCP_CRC_MASK                                      :Result:='mmDCP4_DCP_CRC_MASK';
  mmDCP4_DCP_CRC_CURRENT                                   :Result:='mmDCP4_DCP_CRC_CURRENT';
  mmDCP4_DCP_CRC_LAST                                      :Result:='mmDCP4_DCP_CRC_LAST';
  mmDCP4_DCP_DEBUG                                         :Result:='mmDCP4_DCP_DEBUG';
  mmDCP4_GRPH_FLIP_RATE_CNTL                               :Result:='mmDCP4_GRPH_FLIP_RATE_CNTL';
  mmDCP4_DCP_GSL_CONTROL                                   :Result:='mmDCP4_DCP_GSL_CONTROL';
  mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK                     :Result:='mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK';
  mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS                     :Result:='mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS';
  mmDCP4_OVL_STEREOSYNC_FLIP                               :Result:='mmDCP4_OVL_STEREOSYNC_FLIP';
  mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                :Result:='mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH';
  mmDCP4_DCP_TEST_DEBUG_INDEX                              :Result:='mmDCP4_DCP_TEST_DEBUG_INDEX';
  mmDCP4_DCP_TEST_DEBUG_DATA                               :Result:='mmDCP4_DCP_TEST_DEBUG_DATA';
  mmDCP4_GRPH_STEREOSYNC_FLIP                              :Result:='mmDCP4_GRPH_STEREOSYNC_FLIP';
  mmDCP4_DCP_DEBUG2                                        :Result:='mmDCP4_DCP_DEBUG2';
  mmDCP4_CUR_REQUEST_FILTER_CNTL                           :Result:='mmDCP4_CUR_REQUEST_FILTER_CNTL';
  mmDCP4_CUR_STEREO_CONTROL                                :Result:='mmDCP4_CUR_STEREO_CONTROL';
  mmDCP4_CUR2_STEREO_CONTROL                               :Result:='mmDCP4_CUR2_STEREO_CONTROL';
  mmDCP4_OUT_CLAMP_CONTROL_G_Y                             :Result:='mmDCP4_OUT_CLAMP_CONTROL_G_Y';
  mmDCP4_OUT_CLAMP_CONTROL_B_CB                            :Result:='mmDCP4_OUT_CLAMP_CONTROL_B_CB';
  mmDCP4_HW_ROTATION                                       :Result:='mmDCP4_HW_ROTATION';
  mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                :Result:='mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL';
  mmDCP4_REGAMMA_CONTROL                                   :Result:='mmDCP4_REGAMMA_CONTROL';
  mmDCP4_REGAMMA_LUT_INDEX                                 :Result:='mmDCP4_REGAMMA_LUT_INDEX';
  mmDCP4_REGAMMA_LUT_DATA                                  :Result:='mmDCP4_REGAMMA_LUT_DATA';
  mmDCP4_REGAMMA_LUT_WRITE_EN_MASK                         :Result:='mmDCP4_REGAMMA_LUT_WRITE_EN_MASK';
  mmDCP4_REGAMMA_CNTLA_START_CNTL                          :Result:='mmDCP4_REGAMMA_CNTLA_START_CNTL';
  mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL                          :Result:='mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL';
  mmDCP4_REGAMMA_CNTLA_END_CNTL1                           :Result:='mmDCP4_REGAMMA_CNTLA_END_CNTL1';
  mmDCP4_REGAMMA_CNTLA_END_CNTL2                           :Result:='mmDCP4_REGAMMA_CNTLA_END_CNTL2';
  mmDCP4_REGAMMA_CNTLA_REGION_0_1                          :Result:='mmDCP4_REGAMMA_CNTLA_REGION_0_1';
  mmDCP4_REGAMMA_CNTLA_REGION_2_3                          :Result:='mmDCP4_REGAMMA_CNTLA_REGION_2_3';
  mmDCP4_REGAMMA_CNTLA_REGION_4_5                          :Result:='mmDCP4_REGAMMA_CNTLA_REGION_4_5';
  mmDCP4_REGAMMA_CNTLA_REGION_6_7                          :Result:='mmDCP4_REGAMMA_CNTLA_REGION_6_7';
  mmDCP4_REGAMMA_CNTLA_REGION_8_9                          :Result:='mmDCP4_REGAMMA_CNTLA_REGION_8_9';
  mmDCP4_REGAMMA_CNTLA_REGION_10_11                        :Result:='mmDCP4_REGAMMA_CNTLA_REGION_10_11';
  mmDCP4_REGAMMA_CNTLA_REGION_12_13                        :Result:='mmDCP4_REGAMMA_CNTLA_REGION_12_13';
  mmDCP4_REGAMMA_CNTLA_REGION_14_15                        :Result:='mmDCP4_REGAMMA_CNTLA_REGION_14_15';
  mmDCP4_REGAMMA_CNTLB_START_CNTL                          :Result:='mmDCP4_REGAMMA_CNTLB_START_CNTL';
  mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL                          :Result:='mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL';
  mmDCP4_REGAMMA_CNTLB_END_CNTL1                           :Result:='mmDCP4_REGAMMA_CNTLB_END_CNTL1';
  mmDCP4_REGAMMA_CNTLB_END_CNTL2                           :Result:='mmDCP4_REGAMMA_CNTLB_END_CNTL2';
  mmDCP4_REGAMMA_CNTLB_REGION_0_1                          :Result:='mmDCP4_REGAMMA_CNTLB_REGION_0_1';
  mmDCP4_REGAMMA_CNTLB_REGION_2_3                          :Result:='mmDCP4_REGAMMA_CNTLB_REGION_2_3';
  mmDCP4_REGAMMA_CNTLB_REGION_4_5                          :Result:='mmDCP4_REGAMMA_CNTLB_REGION_4_5';
  mmDCP4_REGAMMA_CNTLB_REGION_6_7                          :Result:='mmDCP4_REGAMMA_CNTLB_REGION_6_7';
  mmDCP4_REGAMMA_CNTLB_REGION_8_9                          :Result:='mmDCP4_REGAMMA_CNTLB_REGION_8_9';
  mmDCP4_REGAMMA_CNTLB_REGION_10_11                        :Result:='mmDCP4_REGAMMA_CNTLB_REGION_10_11';
  mmDCP4_REGAMMA_CNTLB_REGION_12_13                        :Result:='mmDCP4_REGAMMA_CNTLB_REGION_12_13';
  mmDCP4_REGAMMA_CNTLB_REGION_14_15                        :Result:='mmDCP4_REGAMMA_CNTLB_REGION_14_15';
  mmDCP4_ALPHA_CONTROL                                     :Result:='mmDCP4_ALPHA_CONTROL';
  mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                :Result:='mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS';
  mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH           :Result:='mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH';
  mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS              :Result:='mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS';
  mmLB4_LB_DATA_FORMAT                                     :Result:='mmLB4_LB_DATA_FORMAT';
  mmLB4_LB_MEMORY_CTRL                                     :Result:='mmLB4_LB_MEMORY_CTRL';
  mmLB4_LB_MEMORY_SIZE_STATUS                              :Result:='mmLB4_LB_MEMORY_SIZE_STATUS';
  mmLB4_LB_DESKTOP_HEIGHT                                  :Result:='mmLB4_LB_DESKTOP_HEIGHT';
  mmLB4_LB_VLINE_START_END                                 :Result:='mmLB4_LB_VLINE_START_END';
  mmLB4_LB_VLINE2_START_END                                :Result:='mmLB4_LB_VLINE2_START_END';
  mmLB4_LB_V_COUNTER                                       :Result:='mmLB4_LB_V_COUNTER';
  mmLB4_LB_SNAPSHOT_V_COUNTER                              :Result:='mmLB4_LB_SNAPSHOT_V_COUNTER';
  mmLB4_LB_INTERRUPT_MASK                                  :Result:='mmLB4_LB_INTERRUPT_MASK';
  mmLB4_LB_VLINE_STATUS                                    :Result:='mmLB4_LB_VLINE_STATUS';
  mmLB4_LB_VLINE2_STATUS                                   :Result:='mmLB4_LB_VLINE2_STATUS';
  mmLB4_LB_VBLANK_STATUS                                   :Result:='mmLB4_LB_VBLANK_STATUS';
  mmLB4_LB_SYNC_RESET_SEL                                  :Result:='mmLB4_LB_SYNC_RESET_SEL';
  mmLB4_LB_BLACK_KEYER_R_CR                                :Result:='mmLB4_LB_BLACK_KEYER_R_CR';
  mmLB4_LB_BLACK_KEYER_G_Y                                 :Result:='mmLB4_LB_BLACK_KEYER_G_Y';
  mmLB4_LB_BLACK_KEYER_B_CB                                :Result:='mmLB4_LB_BLACK_KEYER_B_CB';
  mmLB4_LB_KEYER_COLOR_CTRL                                :Result:='mmLB4_LB_KEYER_COLOR_CTRL';
  mmLB4_LB_KEYER_COLOR_R_CR                                :Result:='mmLB4_LB_KEYER_COLOR_R_CR';
  mmLB4_LB_KEYER_COLOR_G_Y                                 :Result:='mmLB4_LB_KEYER_COLOR_G_Y';
  mmLB4_LB_KEYER_COLOR_B_CB                                :Result:='mmLB4_LB_KEYER_COLOR_B_CB';
  mmLB4_LB_KEYER_COLOR_REP_R_CR                            :Result:='mmLB4_LB_KEYER_COLOR_REP_R_CR';
  mmLB4_LB_KEYER_COLOR_REP_G_Y                             :Result:='mmLB4_LB_KEYER_COLOR_REP_G_Y';
  mmLB4_LB_KEYER_COLOR_REP_B_CB                            :Result:='mmLB4_LB_KEYER_COLOR_REP_B_CB';
  mmLB4_LB_BUFFER_LEVEL_STATUS                             :Result:='mmLB4_LB_BUFFER_LEVEL_STATUS';
  mmLB4_LB_BUFFER_URGENCY_CTRL                             :Result:='mmLB4_LB_BUFFER_URGENCY_CTRL';
  mmLB4_LB_BUFFER_URGENCY_STATUS                           :Result:='mmLB4_LB_BUFFER_URGENCY_STATUS';
  mmLB4_LB_BUFFER_STATUS                                   :Result:='mmLB4_LB_BUFFER_STATUS';
  mmLB4_LB_NO_OUTSTANDING_REQ_STATUS                       :Result:='mmLB4_LB_NO_OUTSTANDING_REQ_STATUS';
  mmLB4_MVP_AFR_FLIP_MODE                                  :Result:='mmLB4_MVP_AFR_FLIP_MODE';
  mmLB4_MVP_AFR_FLIP_FIFO_CNTL                             :Result:='mmLB4_MVP_AFR_FLIP_FIFO_CNTL';
  mmLB4_MVP_FLIP_LINE_NUM_INSERT                           :Result:='mmLB4_MVP_FLIP_LINE_NUM_INSERT';
  mmLB4_DC_MVP_LB_CONTROL                                  :Result:='mmLB4_DC_MVP_LB_CONTROL';
  mmLB4_LB_DEBUG                                           :Result:='mmLB4_LB_DEBUG';
  mmLB4_LB_DEBUG2                                          :Result:='mmLB4_LB_DEBUG2';
  mmLB4_LB_DEBUG3                                          :Result:='mmLB4_LB_DEBUG3';
  mmLB4_LB_TEST_DEBUG_INDEX                                :Result:='mmLB4_LB_TEST_DEBUG_INDEX';
  mmLB4_LB_TEST_DEBUG_DATA                                 :Result:='mmLB4_LB_TEST_DEBUG_DATA';
  mmDCFE4_DCFE_CLOCK_CONTROL                               :Result:='mmDCFE4_DCFE_CLOCK_CONTROL';
  mmDCFE4_DCFE_SOFT_RESET                                  :Result:='mmDCFE4_DCFE_SOFT_RESET';
  mmDCFE4_DCFE_DBG_CONFIG                                  :Result:='mmDCFE4_DCFE_DBG_CONFIG';
  mmDC_PERFMON7_PERFCOUNTER_CNTL                           :Result:='mmDC_PERFMON7_PERFCOUNTER_CNTL';
  mmDC_PERFMON7_PERFCOUNTER_STATE                          :Result:='mmDC_PERFMON7_PERFCOUNTER_STATE';
  mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                    :Result:='mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC';
  mmDC_PERFMON7_PERFMON_CNTL                               :Result:='mmDC_PERFMON7_PERFMON_CNTL';
  mmDC_PERFMON7_PERFMON_CVALUE_LOW                         :Result:='mmDC_PERFMON7_PERFMON_CVALUE_LOW';
  mmDC_PERFMON7_PERFMON_HI                                 :Result:='mmDC_PERFMON7_PERFMON_HI';
  mmDC_PERFMON7_PERFMON_LOW                                :Result:='mmDC_PERFMON7_PERFMON_LOW';
  mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX                   :Result:='mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX';
  mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA                    :Result:='mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA';
  mmDC_PERFMON7_PERFMON_CNTL2                              :Result:='mmDC_PERFMON7_PERFMON_CNTL2';
  mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1                 :Result:='mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1';
  mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2                 :Result:='mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2';
  mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL                    :Result:='mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL';
  mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL                      :Result:='mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL';
  mmDMIF_PG4_DPG_PIPE_DPM_CONTROL                          :Result:='mmDMIF_PG4_DPG_PIPE_DPM_CONTROL';
  mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL                      :Result:='mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL';
  mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             :Result:='mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL';
  mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             :Result:='mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH';
  mmDMIF_PG4_DPG_TEST_DEBUG_INDEX                          :Result:='mmDMIF_PG4_DPG_TEST_DEBUG_INDEX';
  mmDMIF_PG4_DPG_TEST_DEBUG_DATA                           :Result:='mmDMIF_PG4_DPG_TEST_DEBUG_DATA';
  mmDMIF_PG4_DPG_REPEATER_PROGRAM                          :Result:='mmDMIF_PG4_DPG_REPEATER_PROGRAM';
  mmDMIF_PG4_DPG_HW_DEBUG_A                                :Result:='mmDMIF_PG4_DPG_HW_DEBUG_A';
  mmDMIF_PG4_DPG_HW_DEBUG_B                                :Result:='mmDMIF_PG4_DPG_HW_DEBUG_B';
  mmDMIF_PG4_DPG_HW_DEBUG_11                               :Result:='mmDMIF_PG4_DPG_HW_DEBUG_11';
  mmSCL4_SCL_COEF_RAM_SELECT                               :Result:='mmSCL4_SCL_COEF_RAM_SELECT';
  mmSCL4_SCL_COEF_RAM_TAP_DATA                             :Result:='mmSCL4_SCL_COEF_RAM_TAP_DATA';
  mmSCL4_SCL_MODE                                          :Result:='mmSCL4_SCL_MODE';
  mmSCL4_SCL_TAP_CONTROL                                   :Result:='mmSCL4_SCL_TAP_CONTROL';
  mmSCL4_SCL_CONTROL                                       :Result:='mmSCL4_SCL_CONTROL';
  mmSCL4_SCL_BYPASS_CONTROL                                :Result:='mmSCL4_SCL_BYPASS_CONTROL';
  mmSCL4_SCL_MANUAL_REPLICATE_CONTROL                      :Result:='mmSCL4_SCL_MANUAL_REPLICATE_CONTROL';
  mmSCL4_SCL_AUTOMATIC_MODE_CONTROL                        :Result:='mmSCL4_SCL_AUTOMATIC_MODE_CONTROL';
  mmSCL4_SCL_HORZ_FILTER_CONTROL                           :Result:='mmSCL4_SCL_HORZ_FILTER_CONTROL';
  mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO                       :Result:='mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO';
  mmSCL4_SCL_HORZ_FILTER_INIT                              :Result:='mmSCL4_SCL_HORZ_FILTER_INIT';
  mmSCL4_SCL_VERT_FILTER_CONTROL                           :Result:='mmSCL4_SCL_VERT_FILTER_CONTROL';
  mmSCL4_SCL_VERT_FILTER_SCALE_RATIO                       :Result:='mmSCL4_SCL_VERT_FILTER_SCALE_RATIO';
  mmSCL4_SCL_VERT_FILTER_INIT                              :Result:='mmSCL4_SCL_VERT_FILTER_INIT';
  mmSCL4_SCL_VERT_FILTER_INIT_BOT                          :Result:='mmSCL4_SCL_VERT_FILTER_INIT_BOT';
  mmSCL4_SCL_ROUND_OFFSET                                  :Result:='mmSCL4_SCL_ROUND_OFFSET';
  mmSCL4_SCL_UPDATE                                        :Result:='mmSCL4_SCL_UPDATE';
  mmSCL4_SCL_F_SHARP_CONTROL                               :Result:='mmSCL4_SCL_F_SHARP_CONTROL';
  mmSCL4_SCL_ALU_CONTROL                                   :Result:='mmSCL4_SCL_ALU_CONTROL';
  mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS                      :Result:='mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS';
  mmSCL4_VIEWPORT_START_SECONDARY                          :Result:='mmSCL4_VIEWPORT_START_SECONDARY';
  mmSCL4_VIEWPORT_START                                    :Result:='mmSCL4_VIEWPORT_START';
  mmSCL4_VIEWPORT_SIZE                                     :Result:='mmSCL4_VIEWPORT_SIZE';
  mmSCL4_EXT_OVERSCAN_LEFT_RIGHT                           :Result:='mmSCL4_EXT_OVERSCAN_LEFT_RIGHT';
  mmSCL4_EXT_OVERSCAN_TOP_BOTTOM                           :Result:='mmSCL4_EXT_OVERSCAN_TOP_BOTTOM';
  mmSCL4_SCL_MODE_CHANGE_DET1                              :Result:='mmSCL4_SCL_MODE_CHANGE_DET1';
  mmSCL4_SCL_MODE_CHANGE_DET2                              :Result:='mmSCL4_SCL_MODE_CHANGE_DET2';
  mmSCL4_SCL_MODE_CHANGE_DET3                              :Result:='mmSCL4_SCL_MODE_CHANGE_DET3';
  mmSCL4_SCL_MODE_CHANGE_MASK                              :Result:='mmSCL4_SCL_MODE_CHANGE_MASK';
  mmSCL4_SCL_DEBUG2                                        :Result:='mmSCL4_SCL_DEBUG2';
  mmSCL4_SCL_DEBUG                                         :Result:='mmSCL4_SCL_DEBUG';
  mmSCL4_SCL_TEST_DEBUG_INDEX                              :Result:='mmSCL4_SCL_TEST_DEBUG_INDEX';
  mmSCL4_SCL_TEST_DEBUG_DATA                               :Result:='mmSCL4_SCL_TEST_DEBUG_DATA';
  mmBLND4_BLND_CONTROL                                     :Result:='mmBLND4_BLND_CONTROL';
  mmBLND4_SM_CONTROL2                                      :Result:='mmBLND4_SM_CONTROL2';
  mmBLND4_BLND_CONTROL2                                    :Result:='mmBLND4_BLND_CONTROL2';
  mmBLND4_BLND_UPDATE                                      :Result:='mmBLND4_BLND_UPDATE';
  mmBLND4_BLND_UNDERFLOW_INTERRUPT                         :Result:='mmBLND4_BLND_UNDERFLOW_INTERRUPT';
  mmBLND4_BLND_V_UPDATE_LOCK                               :Result:='mmBLND4_BLND_V_UPDATE_LOCK';
  mmBLND4_BLND_DEBUG                                       :Result:='mmBLND4_BLND_DEBUG';
  mmBLND4_BLND_TEST_DEBUG_INDEX                            :Result:='mmBLND4_BLND_TEST_DEBUG_INDEX';
  mmBLND4_BLND_TEST_DEBUG_DATA                             :Result:='mmBLND4_BLND_TEST_DEBUG_DATA';
  mmBLND4_BLND_REG_UPDATE_STATUS                           :Result:='mmBLND4_BLND_REG_UPDATE_STATUS';
  mmCRTC4_CRTC_3D_STRUCTURE_CONTROL                        :Result:='mmCRTC4_CRTC_3D_STRUCTURE_CONTROL';
  mmCRTC4_CRTC_GSL_VSYNC_GAP                               :Result:='mmCRTC4_CRTC_GSL_VSYNC_GAP';
  mmCRTC4_CRTC_GSL_WINDOW                                  :Result:='mmCRTC4_CRTC_GSL_WINDOW';
  mmCRTC4_CRTC_GSL_CONTROL                                 :Result:='mmCRTC4_CRTC_GSL_CONTROL';
  mmCRTC4_CRTC_DCFE_CLOCK_CONTROL                          :Result:='mmCRTC4_CRTC_DCFE_CLOCK_CONTROL';
  mmCRTC4_CRTC_H_BLANK_EARLY_NUM                           :Result:='mmCRTC4_CRTC_H_BLANK_EARLY_NUM';
  mmCRTC4_DCFE_DBG_SEL                                     :Result:='mmCRTC4_DCFE_DBG_SEL';
  mmCRTC4_DCFE_MEM_PWR_CTRL                                :Result:='mmCRTC4_DCFE_MEM_PWR_CTRL';
  mmCRTC4_CRTC_V_TOTAL_CONTROL                             :Result:='mmCRTC4_CRTC_V_TOTAL_CONTROL';
  mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS                        :Result:='mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS';
  mmCRTC4_CRTC_V_SYNC_A                                    :Result:='mmCRTC4_CRTC_V_SYNC_A';
  mmCRTC4_CRTC_V_SYNC_A_CNTL                               :Result:='mmCRTC4_CRTC_V_SYNC_A_CNTL';
  mmCRTC4_CRTC_V_SYNC_B                                    :Result:='mmCRTC4_CRTC_V_SYNC_B';
  mmCRTC4_CRTC_DTMTEST_CNTL                                :Result:='mmCRTC4_CRTC_DTMTEST_CNTL';
  mmCRTC4_CRTC_DTMTEST_STATUS_POSITION                     :Result:='mmCRTC4_CRTC_DTMTEST_STATUS_POSITION';
  mmCRTC4_CRTC_TRIGA_CNTL                                  :Result:='mmCRTC4_CRTC_TRIGA_CNTL';
  mmCRTC4_CRTC_TRIGB_MANUAL_TRIG                           :Result:='mmCRTC4_CRTC_TRIGB_MANUAL_TRIG';
  mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL                        :Result:='mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL';
  mmCRTC4_CRTC_FLOW_CONTROL                                :Result:='mmCRTC4_CRTC_FLOW_CONTROL';
  mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE                       :Result:='mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE';
  mmCRTC4_CRTC_AVSYNC_COUNTER                              :Result:='mmCRTC4_CRTC_AVSYNC_COUNTER';
  mmCRTC4_CRTC_CONTROL                                     :Result:='mmCRTC4_CRTC_CONTROL';
  mmCRTC4_CRTC_BLANK_CONTROL                               :Result:='mmCRTC4_CRTC_BLANK_CONTROL';
  mmCRTC4_CRTC_INTERLACE_CONTROL                           :Result:='mmCRTC4_CRTC_INTERLACE_CONTROL';
  mmCRTC4_CRTC_INTERLACE_STATUS                            :Result:='mmCRTC4_CRTC_INTERLACE_STATUS';
  mmCRTC4_CRTC_FIELD_INDICATION_CONTROL                    :Result:='mmCRTC4_CRTC_FIELD_INDICATION_CONTROL';
  mmCRTC4_CRTC_PIXEL_DATA_READBACK0                        :Result:='mmCRTC4_CRTC_PIXEL_DATA_READBACK0';
  mmCRTC4_CRTC_PIXEL_DATA_READBACK1                        :Result:='mmCRTC4_CRTC_PIXEL_DATA_READBACK1';
  mmCRTC4_CRTC_STATUS                                      :Result:='mmCRTC4_CRTC_STATUS';
  mmCRTC4_CRTC_STATUS_POSITION                             :Result:='mmCRTC4_CRTC_STATUS_POSITION';
  mmCRTC4_CRTC_NOM_VERT_POSITION                           :Result:='mmCRTC4_CRTC_NOM_VERT_POSITION';
  mmCRTC4_CRTC_STATUS_FRAME_COUNT                          :Result:='mmCRTC4_CRTC_STATUS_FRAME_COUNT';
  mmCRTC4_CRTC_STATUS_VF_COUNT                             :Result:='mmCRTC4_CRTC_STATUS_VF_COUNT';
  mmCRTC4_CRTC_STATUS_HV_COUNT                             :Result:='mmCRTC4_CRTC_STATUS_HV_COUNT';
  mmCRTC4_CRTC_COUNT_CONTROL                               :Result:='mmCRTC4_CRTC_COUNT_CONTROL';
  mmCRTC4_CRTC_COUNT_RESET                                 :Result:='mmCRTC4_CRTC_COUNT_RESET';
  mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                :Result:='mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE';
  mmCRTC4_CRTC_VERT_SYNC_CONTROL                           :Result:='mmCRTC4_CRTC_VERT_SYNC_CONTROL';
  mmCRTC4_CRTC_STEREO_STATUS                               :Result:='mmCRTC4_CRTC_STEREO_STATUS';
  mmCRTC4_CRTC_STEREO_CONTROL                              :Result:='mmCRTC4_CRTC_STEREO_CONTROL';
  mmCRTC4_CRTC_SNAPSHOT_STATUS                             :Result:='mmCRTC4_CRTC_SNAPSHOT_STATUS';
  mmCRTC4_CRTC_SNAPSHOT_CONTROL                            :Result:='mmCRTC4_CRTC_SNAPSHOT_CONTROL';
  mmCRTC4_CRTC_SNAPSHOT_POSITION                           :Result:='mmCRTC4_CRTC_SNAPSHOT_POSITION';
  mmCRTC4_CRTC_SNAPSHOT_FRAME                              :Result:='mmCRTC4_CRTC_SNAPSHOT_FRAME';
  mmCRTC4_CRTC_START_LINE_CONTROL                          :Result:='mmCRTC4_CRTC_START_LINE_CONTROL';
  mmCRTC4_CRTC_INTERRUPT_CONTROL                           :Result:='mmCRTC4_CRTC_INTERRUPT_CONTROL';
  mmCRTC4_CRTC_UPDATE_LOCK                                 :Result:='mmCRTC4_CRTC_UPDATE_LOCK';
  mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL                       :Result:='mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL';
  mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE                  :Result:='mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE';
  mmCRTC4_DCFE_MEM_PWR_CTRL2                               :Result:='mmCRTC4_DCFE_MEM_PWR_CTRL2';
  mmCRTC4_DCFE_MEM_PWR_STATUS                              :Result:='mmCRTC4_DCFE_MEM_PWR_STATUS';
  mmCRTC4_CRTC_TEST_PATTERN_CONTROL                        :Result:='mmCRTC4_CRTC_TEST_PATTERN_CONTROL';
  mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS                     :Result:='mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS';
  mmCRTC4_CRTC_TEST_PATTERN_COLOR                          :Result:='mmCRTC4_CRTC_TEST_PATTERN_COLOR';
  mmCRTC4_MASTER_UPDATE_LOCK                               :Result:='mmCRTC4_MASTER_UPDATE_LOCK';
  mmCRTC4_MASTER_UPDATE_MODE                               :Result:='mmCRTC4_MASTER_UPDATE_MODE';
  mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT                      :Result:='mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT';
  mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                :Result:='mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER';
  mmCRTC4_CRTC_MVP_STATUS                                  :Result:='mmCRTC4_CRTC_MVP_STATUS';
  mmCRTC4_CRTC_MASTER_EN                                   :Result:='mmCRTC4_CRTC_MASTER_EN';
  mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT                        :Result:='mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT';
  mmCRTC4_CRTC_V_UPDATE_INT_STATUS                         :Result:='mmCRTC4_CRTC_V_UPDATE_INT_STATUS';
  mmCRTC4_CRTC_TEST_DEBUG_INDEX                            :Result:='mmCRTC4_CRTC_TEST_DEBUG_INDEX';
  mmCRTC4_CRTC_TEST_DEBUG_DATA                             :Result:='mmCRTC4_CRTC_TEST_DEBUG_DATA';
  mmCRTC4_CRTC_OVERSCAN_COLOR                              :Result:='mmCRTC4_CRTC_OVERSCAN_COLOR';
  mmCRTC4_CRTC_OVERSCAN_COLOR_EXT                          :Result:='mmCRTC4_CRTC_OVERSCAN_COLOR_EXT';
  mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT                        :Result:='mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT';
  mmCRTC4_CRTC_BLACK_COLOR                                 :Result:='mmCRTC4_CRTC_BLACK_COLOR';
  mmCRTC4_CRTC_BLACK_COLOR_EXT                             :Result:='mmCRTC4_CRTC_BLACK_COLOR_EXT';
  mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION                :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION';
  mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL                 :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL';
  mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION                :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION';
  mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL                 :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL';
  mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION                :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION';
  mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL                 :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL';
  mmCRTC4_CRTC_CRC_CNTL                                    :Result:='mmCRTC4_CRTC_CRC_CNTL';
  mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL                      :Result:='mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL';
  mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL                      :Result:='mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL';
  mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL                      :Result:='mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL';
  mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL                      :Result:='mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL';
  mmCRTC4_CRTC_CRC0_DATA_RG                                :Result:='mmCRTC4_CRTC_CRC0_DATA_RG';
  mmCRTC4_CRTC_CRC0_DATA_B                                 :Result:='mmCRTC4_CRTC_CRC0_DATA_B';
  mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL                      :Result:='mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL';
  mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL                      :Result:='mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL';
  mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL                      :Result:='mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL';
  mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL                      :Result:='mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL';
  mmCRTC4_CRTC_CRC1_DATA_RG                                :Result:='mmCRTC4_CRTC_CRC1_DATA_RG';
  mmCRTC4_CRTC_CRC1_DATA_B                                 :Result:='mmCRTC4_CRTC_CRC1_DATA_B';
  mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL                     :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL';
  mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START                :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START';
  mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END                  :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END';
  mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL';
  mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL';
  mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL';
  mmCRTC4_CRTC_STATIC_SCREEN_CONTROL                       :Result:='mmCRTC4_CRTC_STATIC_SCREEN_CONTROL';
  mmFMT4_FMT_CLAMP_COMPONENT_R                             :Result:='mmFMT4_FMT_CLAMP_COMPONENT_R';
  mmFMT4_FMT_CLAMP_COMPONENT_G                             :Result:='mmFMT4_FMT_CLAMP_COMPONENT_G';
  mmFMT4_FMT_CLAMP_COMPONENT_B                             :Result:='mmFMT4_FMT_CLAMP_COMPONENT_B';
  mmFMT4_FMT_TEST_DEBUG_INDEX                              :Result:='mmFMT4_FMT_TEST_DEBUG_INDEX';
  mmFMT4_FMT_TEST_DEBUG_DATA                               :Result:='mmFMT4_FMT_TEST_DEBUG_DATA';
  mmFMT4_FMT_DYNAMIC_EXP_CNTL                              :Result:='mmFMT4_FMT_DYNAMIC_EXP_CNTL';
  mmFMT4_FMT_CONTROL                                       :Result:='mmFMT4_FMT_CONTROL';
  mmFMT4_FMT_FORCE_OUTPUT_CNTL                             :Result:='mmFMT4_FMT_FORCE_OUTPUT_CNTL';
  mmFMT4_FMT_FORCE_DATA_0_1                                :Result:='mmFMT4_FMT_FORCE_DATA_0_1';
  mmFMT4_FMT_FORCE_DATA_2_3                                :Result:='mmFMT4_FMT_FORCE_DATA_2_3';
  mmFMT4_FMT_BIT_DEPTH_CONTROL                             :Result:='mmFMT4_FMT_BIT_DEPTH_CONTROL';
  mmFMT4_FMT_DITHER_RAND_R_SEED                            :Result:='mmFMT4_FMT_DITHER_RAND_R_SEED';
  mmFMT4_FMT_DITHER_RAND_G_SEED                            :Result:='mmFMT4_FMT_DITHER_RAND_G_SEED';
  mmFMT4_FMT_DITHER_RAND_B_SEED                            :Result:='mmFMT4_FMT_DITHER_RAND_B_SEED';
  mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL               :Result:='mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL';
  mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :Result:='mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX';
  mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :Result:='mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX';
  mmFMT4_FMT_CLAMP_CNTL                                    :Result:='mmFMT4_FMT_CLAMP_CNTL';
  mmFMT4_FMT_CRC_CNTL                                      :Result:='mmFMT4_FMT_CRC_CNTL';
  mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK                        :Result:='mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK';
  mmFMT4_FMT_CRC_SIG_RED_GREEN                             :Result:='mmFMT4_FMT_CRC_SIG_RED_GREEN';
  mmDCP5_GRPH_ENABLE                                       :Result:='mmDCP5_GRPH_ENABLE';
  mmDCP5_GRPH_CONTROL                                      :Result:='mmDCP5_GRPH_CONTROL';
  mmDCP5_GRPH_LUT_10BIT_BYPASS                             :Result:='mmDCP5_GRPH_LUT_10BIT_BYPASS';
  mmDCP5_GRPH_SWAP_CNTL                                    :Result:='mmDCP5_GRPH_SWAP_CNTL';
  mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS                      :Result:='mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS';
  mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS                    :Result:='mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS';
  mmDCP5_GRPH_PITCH                                        :Result:='mmDCP5_GRPH_PITCH';
  mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                 :Result:='mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH';
  mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH               :Result:='mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH';
  mmDCP5_GRPH_SURFACE_OFFSET_X                             :Result:='mmDCP5_GRPH_SURFACE_OFFSET_X';
  mmDCP5_GRPH_SURFACE_OFFSET_Y                             :Result:='mmDCP5_GRPH_SURFACE_OFFSET_Y';
  mmDCP5_GRPH_X_START                                      :Result:='mmDCP5_GRPH_X_START';
  mmDCP5_GRPH_Y_START                                      :Result:='mmDCP5_GRPH_Y_START';
  mmDCP5_GRPH_X_END                                        :Result:='mmDCP5_GRPH_X_END';
  mmDCP5_GRPH_Y_END                                        :Result:='mmDCP5_GRPH_Y_END';
  mmDCP5_INPUT_GAMMA_CONTROL                               :Result:='mmDCP5_INPUT_GAMMA_CONTROL';
  mmDCP5_GRPH_UPDATE                                       :Result:='mmDCP5_GRPH_UPDATE';
  mmDCP5_GRPH_FLIP_CONTROL                                 :Result:='mmDCP5_GRPH_FLIP_CONTROL';
  mmDCP5_GRPH_SURFACE_ADDRESS_INUSE                        :Result:='mmDCP5_GRPH_SURFACE_ADDRESS_INUSE';
  mmDCP5_GRPH_DFQ_CONTROL                                  :Result:='mmDCP5_GRPH_DFQ_CONTROL';
  mmDCP5_GRPH_DFQ_STATUS                                   :Result:='mmDCP5_GRPH_DFQ_STATUS';
  mmDCP5_GRPH_INTERRUPT_STATUS                             :Result:='mmDCP5_GRPH_INTERRUPT_STATUS';
  mmDCP5_GRPH_INTERRUPT_CONTROL                            :Result:='mmDCP5_GRPH_INTERRUPT_CONTROL';
  mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE                   :Result:='mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE';
  mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS                     :Result:='mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS';
  mmDCP5_GRPH_COMPRESS_PITCH                               :Result:='mmDCP5_GRPH_COMPRESS_PITCH';
  mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                :Result:='mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH';
  mmDCP5_OVL_ENABLE                                        :Result:='mmDCP5_OVL_ENABLE';
  mmDCP5_OVL_CONTROL1                                      :Result:='mmDCP5_OVL_CONTROL1';
  mmDCP5_OVL_CONTROL2                                      :Result:='mmDCP5_OVL_CONTROL2';
  mmDCP5_OVL_SWAP_CNTL                                     :Result:='mmDCP5_OVL_SWAP_CNTL';
  mmDCP5_OVL_SURFACE_ADDRESS                               :Result:='mmDCP5_OVL_SURFACE_ADDRESS';
  mmDCP5_OVL_PITCH                                         :Result:='mmDCP5_OVL_PITCH';
  mmDCP5_OVL_SURFACE_ADDRESS_HIGH                          :Result:='mmDCP5_OVL_SURFACE_ADDRESS_HIGH';
  mmDCP5_OVL_SURFACE_OFFSET_X                              :Result:='mmDCP5_OVL_SURFACE_OFFSET_X';
  mmDCP5_OVL_SURFACE_OFFSET_Y                              :Result:='mmDCP5_OVL_SURFACE_OFFSET_Y';
  mmDCP5_OVL_START                                         :Result:='mmDCP5_OVL_START';
  mmDCP5_OVL_END                                           :Result:='mmDCP5_OVL_END';
  mmDCP5_OVL_UPDATE                                        :Result:='mmDCP5_OVL_UPDATE';
  mmDCP5_OVL_SURFACE_ADDRESS_INUSE                         :Result:='mmDCP5_OVL_SURFACE_ADDRESS_INUSE';
  mmDCP5_OVL_DFQ_CONTROL                                   :Result:='mmDCP5_OVL_DFQ_CONTROL';
  mmDCP5_OVL_DFQ_STATUS                                    :Result:='mmDCP5_OVL_DFQ_STATUS';
  mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE                    :Result:='mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE';
  mmDCP5_OVLSCL_EDGE_PIXEL_CNTL                            :Result:='mmDCP5_OVLSCL_EDGE_PIXEL_CNTL';
  mmDCP5_PRESCALE_GRPH_CONTROL                             :Result:='mmDCP5_PRESCALE_GRPH_CONTROL';
  mmDCP5_PRESCALE_VALUES_GRPH_R                            :Result:='mmDCP5_PRESCALE_VALUES_GRPH_R';
  mmDCP5_PRESCALE_VALUES_GRPH_G                            :Result:='mmDCP5_PRESCALE_VALUES_GRPH_G';
  mmDCP5_PRESCALE_VALUES_GRPH_B                            :Result:='mmDCP5_PRESCALE_VALUES_GRPH_B';
  mmDCP5_PRESCALE_OVL_CONTROL                              :Result:='mmDCP5_PRESCALE_OVL_CONTROL';
  mmDCP5_PRESCALE_VALUES_OVL_CB                            :Result:='mmDCP5_PRESCALE_VALUES_OVL_CB';
  mmDCP5_PRESCALE_VALUES_OVL_Y                             :Result:='mmDCP5_PRESCALE_VALUES_OVL_Y';
  mmDCP5_PRESCALE_VALUES_OVL_CR                            :Result:='mmDCP5_PRESCALE_VALUES_OVL_CR';
  mmDCP5_INPUT_CSC_CONTROL                                 :Result:='mmDCP5_INPUT_CSC_CONTROL';
  mmDCP5_INPUT_CSC_C11_C12                                 :Result:='mmDCP5_INPUT_CSC_C11_C12';
  mmDCP5_INPUT_CSC_C13_C14                                 :Result:='mmDCP5_INPUT_CSC_C13_C14';
  mmDCP5_INPUT_CSC_C21_C22                                 :Result:='mmDCP5_INPUT_CSC_C21_C22';
  mmDCP5_INPUT_CSC_C23_C24                                 :Result:='mmDCP5_INPUT_CSC_C23_C24';
  mmDCP5_INPUT_CSC_C31_C32                                 :Result:='mmDCP5_INPUT_CSC_C31_C32';
  mmDCP5_INPUT_CSC_C33_C34                                 :Result:='mmDCP5_INPUT_CSC_C33_C34';
  mmDCP5_OUTPUT_CSC_CONTROL                                :Result:='mmDCP5_OUTPUT_CSC_CONTROL';
  mmDCP5_OUTPUT_CSC_C11_C12                                :Result:='mmDCP5_OUTPUT_CSC_C11_C12';
  mmDCP5_OUTPUT_CSC_C13_C14                                :Result:='mmDCP5_OUTPUT_CSC_C13_C14';
  mmDCP5_OUTPUT_CSC_C21_C22                                :Result:='mmDCP5_OUTPUT_CSC_C21_C22';
  mmDCP5_OUTPUT_CSC_C23_C24                                :Result:='mmDCP5_OUTPUT_CSC_C23_C24';
  mmDCP5_OUTPUT_CSC_C31_C32                                :Result:='mmDCP5_OUTPUT_CSC_C31_C32';
  mmDCP5_OUTPUT_CSC_C33_C34                                :Result:='mmDCP5_OUTPUT_CSC_C33_C34';
  mmDCP5_COMM_MATRIXA_TRANS_C11_C12                        :Result:='mmDCP5_COMM_MATRIXA_TRANS_C11_C12';
  mmDCP5_COMM_MATRIXA_TRANS_C13_C14                        :Result:='mmDCP5_COMM_MATRIXA_TRANS_C13_C14';
  mmDCP5_COMM_MATRIXA_TRANS_C21_C22                        :Result:='mmDCP5_COMM_MATRIXA_TRANS_C21_C22';
  mmDCP5_COMM_MATRIXA_TRANS_C23_C24                        :Result:='mmDCP5_COMM_MATRIXA_TRANS_C23_C24';
  mmDCP5_COMM_MATRIXA_TRANS_C31_C32                        :Result:='mmDCP5_COMM_MATRIXA_TRANS_C31_C32';
  mmDCP5_COMM_MATRIXA_TRANS_C33_C34                        :Result:='mmDCP5_COMM_MATRIXA_TRANS_C33_C34';
  mmDCP5_COMM_MATRIXB_TRANS_C11_C12                        :Result:='mmDCP5_COMM_MATRIXB_TRANS_C11_C12';
  mmDCP5_COMM_MATRIXB_TRANS_C13_C14                        :Result:='mmDCP5_COMM_MATRIXB_TRANS_C13_C14';
  mmDCP5_COMM_MATRIXB_TRANS_C21_C22                        :Result:='mmDCP5_COMM_MATRIXB_TRANS_C21_C22';
  mmDCP5_COMM_MATRIXB_TRANS_C23_C24                        :Result:='mmDCP5_COMM_MATRIXB_TRANS_C23_C24';
  mmDCP5_COMM_MATRIXB_TRANS_C31_C32                        :Result:='mmDCP5_COMM_MATRIXB_TRANS_C31_C32';
  mmDCP5_COMM_MATRIXB_TRANS_C33_C34                        :Result:='mmDCP5_COMM_MATRIXB_TRANS_C33_C34';
  mmDCP5_DENORM_CONTROL                                    :Result:='mmDCP5_DENORM_CONTROL';
  mmDCP5_OUT_ROUND_CONTROL                                 :Result:='mmDCP5_OUT_ROUND_CONTROL';
  mmDCP5_OUT_CLAMP_CONTROL_R_CR                            :Result:='mmDCP5_OUT_CLAMP_CONTROL_R_CR';
  mmDCP5_KEY_CONTROL                                       :Result:='mmDCP5_KEY_CONTROL';
  mmDCP5_KEY_RANGE_ALPHA                                   :Result:='mmDCP5_KEY_RANGE_ALPHA';
  mmDCP5_KEY_RANGE_RED                                     :Result:='mmDCP5_KEY_RANGE_RED';
  mmDCP5_KEY_RANGE_GREEN                                   :Result:='mmDCP5_KEY_RANGE_GREEN';
  mmDCP5_KEY_RANGE_BLUE                                    :Result:='mmDCP5_KEY_RANGE_BLUE';
  mmDCP5_DEGAMMA_CONTROL                                   :Result:='mmDCP5_DEGAMMA_CONTROL';
  mmDCP5_GAMUT_REMAP_CONTROL                               :Result:='mmDCP5_GAMUT_REMAP_CONTROL';
  mmDCP5_GAMUT_REMAP_C11_C12                               :Result:='mmDCP5_GAMUT_REMAP_C11_C12';
  mmDCP5_GAMUT_REMAP_C13_C14                               :Result:='mmDCP5_GAMUT_REMAP_C13_C14';
  mmDCP5_GAMUT_REMAP_C21_C22                               :Result:='mmDCP5_GAMUT_REMAP_C21_C22';
  mmDCP5_GAMUT_REMAP_C23_C24                               :Result:='mmDCP5_GAMUT_REMAP_C23_C24';
  mmDCP5_GAMUT_REMAP_C31_C32                               :Result:='mmDCP5_GAMUT_REMAP_C31_C32';
  mmDCP5_GAMUT_REMAP_C33_C34                               :Result:='mmDCP5_GAMUT_REMAP_C33_C34';
  mmDCP5_DCP_SPATIAL_DITHER_CNTL                           :Result:='mmDCP5_DCP_SPATIAL_DITHER_CNTL';
  mmDCP5_DCP_RANDOM_SEEDS                                  :Result:='mmDCP5_DCP_RANDOM_SEEDS';
  mmDCP5_DCP_FP_CONVERTED_FIELD                            :Result:='mmDCP5_DCP_FP_CONVERTED_FIELD';
  mmDCP5_CUR_CONTROL                                       :Result:='mmDCP5_CUR_CONTROL';
  mmDCP5_CUR_SURFACE_ADDRESS                               :Result:='mmDCP5_CUR_SURFACE_ADDRESS';
  mmDCP5_CUR_SIZE                                          :Result:='mmDCP5_CUR_SIZE';
  mmDCP5_CUR_SURFACE_ADDRESS_HIGH                          :Result:='mmDCP5_CUR_SURFACE_ADDRESS_HIGH';
  mmDCP5_CUR_POSITION                                      :Result:='mmDCP5_CUR_POSITION';
  mmDCP5_CUR_HOT_SPOT                                      :Result:='mmDCP5_CUR_HOT_SPOT';
  mmDCP5_CUR_COLOR1                                        :Result:='mmDCP5_CUR_COLOR1';
  mmDCP5_CUR_COLOR2                                        :Result:='mmDCP5_CUR_COLOR2';
  mmDCP5_CUR_UPDATE                                        :Result:='mmDCP5_CUR_UPDATE';
  mmDCP5_CUR2_CONTROL                                      :Result:='mmDCP5_CUR2_CONTROL';
  mmDCP5_CUR2_SURFACE_ADDRESS                              :Result:='mmDCP5_CUR2_SURFACE_ADDRESS';
  mmDCP5_CUR2_SIZE                                         :Result:='mmDCP5_CUR2_SIZE';
  mmDCP5_CUR2_SURFACE_ADDRESS_HIGH                         :Result:='mmDCP5_CUR2_SURFACE_ADDRESS_HIGH';
  mmDCP5_CUR2_POSITION                                     :Result:='mmDCP5_CUR2_POSITION';
  mmDCP5_CUR2_HOT_SPOT                                     :Result:='mmDCP5_CUR2_HOT_SPOT';
  mmDCP5_CUR2_COLOR1                                       :Result:='mmDCP5_CUR2_COLOR1';
  mmDCP5_CUR2_COLOR2                                       :Result:='mmDCP5_CUR2_COLOR2';
  mmDCP5_CUR2_UPDATE                                       :Result:='mmDCP5_CUR2_UPDATE';
  mmDCP5_DC_LUT_RW_MODE                                    :Result:='mmDCP5_DC_LUT_RW_MODE';
  mmDCP5_DC_LUT_RW_INDEX                                   :Result:='mmDCP5_DC_LUT_RW_INDEX';
  mmDCP5_DC_LUT_SEQ_COLOR                                  :Result:='mmDCP5_DC_LUT_SEQ_COLOR';
  mmDCP5_DC_LUT_PWL_DATA                                   :Result:='mmDCP5_DC_LUT_PWL_DATA';
  mmDCP5_DC_LUT_30_COLOR                                   :Result:='mmDCP5_DC_LUT_30_COLOR';
  mmDCP5_DC_LUT_VGA_ACCESS_ENABLE                          :Result:='mmDCP5_DC_LUT_VGA_ACCESS_ENABLE';
  mmDCP5_DC_LUT_WRITE_EN_MASK                              :Result:='mmDCP5_DC_LUT_WRITE_EN_MASK';
  mmDCP5_DC_LUT_AUTOFILL                                   :Result:='mmDCP5_DC_LUT_AUTOFILL';
  mmDCP5_DC_LUT_CONTROL                                    :Result:='mmDCP5_DC_LUT_CONTROL';
  mmDCP5_DC_LUT_BLACK_OFFSET_BLUE                          :Result:='mmDCP5_DC_LUT_BLACK_OFFSET_BLUE';
  mmDCP5_DC_LUT_BLACK_OFFSET_GREEN                         :Result:='mmDCP5_DC_LUT_BLACK_OFFSET_GREEN';
  mmDCP5_DC_LUT_BLACK_OFFSET_RED                           :Result:='mmDCP5_DC_LUT_BLACK_OFFSET_RED';
  mmDCP5_DC_LUT_WHITE_OFFSET_BLUE                          :Result:='mmDCP5_DC_LUT_WHITE_OFFSET_BLUE';
  mmDCP5_DC_LUT_WHITE_OFFSET_GREEN                         :Result:='mmDCP5_DC_LUT_WHITE_OFFSET_GREEN';
  mmDCP5_DC_LUT_WHITE_OFFSET_RED                           :Result:='mmDCP5_DC_LUT_WHITE_OFFSET_RED';
  mmDCP5_DCP_CRC_CONTROL                                   :Result:='mmDCP5_DCP_CRC_CONTROL';
  mmDCP5_DCP_CRC_MASK                                      :Result:='mmDCP5_DCP_CRC_MASK';
  mmDCP5_DCP_CRC_CURRENT                                   :Result:='mmDCP5_DCP_CRC_CURRENT';
  mmDCP5_DCP_CRC_LAST                                      :Result:='mmDCP5_DCP_CRC_LAST';
  mmDCP5_DCP_DEBUG                                         :Result:='mmDCP5_DCP_DEBUG';
  mmDCP5_GRPH_FLIP_RATE_CNTL                               :Result:='mmDCP5_GRPH_FLIP_RATE_CNTL';
  mmDCP5_DCP_GSL_CONTROL                                   :Result:='mmDCP5_DCP_GSL_CONTROL';
  mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK                     :Result:='mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK';
  mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS                     :Result:='mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS';
  mmDCP5_OVL_STEREOSYNC_FLIP                               :Result:='mmDCP5_OVL_STEREOSYNC_FLIP';
  mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                :Result:='mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH';
  mmDCP5_DCP_TEST_DEBUG_INDEX                              :Result:='mmDCP5_DCP_TEST_DEBUG_INDEX';
  mmDCP5_DCP_TEST_DEBUG_DATA                               :Result:='mmDCP5_DCP_TEST_DEBUG_DATA';
  mmDCP5_GRPH_STEREOSYNC_FLIP                              :Result:='mmDCP5_GRPH_STEREOSYNC_FLIP';
  mmDCP5_DCP_DEBUG2                                        :Result:='mmDCP5_DCP_DEBUG2';
  mmDCP5_CUR_REQUEST_FILTER_CNTL                           :Result:='mmDCP5_CUR_REQUEST_FILTER_CNTL';
  mmDCP5_CUR_STEREO_CONTROL                                :Result:='mmDCP5_CUR_STEREO_CONTROL';
  mmDCP5_CUR2_STEREO_CONTROL                               :Result:='mmDCP5_CUR2_STEREO_CONTROL';
  mmDCP5_OUT_CLAMP_CONTROL_G_Y                             :Result:='mmDCP5_OUT_CLAMP_CONTROL_G_Y';
  mmDCP5_OUT_CLAMP_CONTROL_B_CB                            :Result:='mmDCP5_OUT_CLAMP_CONTROL_B_CB';
  mmDCP5_HW_ROTATION                                       :Result:='mmDCP5_HW_ROTATION';
  mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                :Result:='mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL';
  mmDCP5_REGAMMA_CONTROL                                   :Result:='mmDCP5_REGAMMA_CONTROL';
  mmDCP5_REGAMMA_LUT_INDEX                                 :Result:='mmDCP5_REGAMMA_LUT_INDEX';
  mmDCP5_REGAMMA_LUT_DATA                                  :Result:='mmDCP5_REGAMMA_LUT_DATA';
  mmDCP5_REGAMMA_LUT_WRITE_EN_MASK                         :Result:='mmDCP5_REGAMMA_LUT_WRITE_EN_MASK';
  mmDCP5_REGAMMA_CNTLA_START_CNTL                          :Result:='mmDCP5_REGAMMA_CNTLA_START_CNTL';
  mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL                          :Result:='mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL';
  mmDCP5_REGAMMA_CNTLA_END_CNTL1                           :Result:='mmDCP5_REGAMMA_CNTLA_END_CNTL1';
  mmDCP5_REGAMMA_CNTLA_END_CNTL2                           :Result:='mmDCP5_REGAMMA_CNTLA_END_CNTL2';
  mmDCP5_REGAMMA_CNTLA_REGION_0_1                          :Result:='mmDCP5_REGAMMA_CNTLA_REGION_0_1';
  mmDCP5_REGAMMA_CNTLA_REGION_2_3                          :Result:='mmDCP5_REGAMMA_CNTLA_REGION_2_3';
  mmDCP5_REGAMMA_CNTLA_REGION_4_5                          :Result:='mmDCP5_REGAMMA_CNTLA_REGION_4_5';
  mmDCP5_REGAMMA_CNTLA_REGION_6_7                          :Result:='mmDCP5_REGAMMA_CNTLA_REGION_6_7';
  mmDCP5_REGAMMA_CNTLA_REGION_8_9                          :Result:='mmDCP5_REGAMMA_CNTLA_REGION_8_9';
  mmDCP5_REGAMMA_CNTLA_REGION_10_11                        :Result:='mmDCP5_REGAMMA_CNTLA_REGION_10_11';
  mmDCP5_REGAMMA_CNTLA_REGION_12_13                        :Result:='mmDCP5_REGAMMA_CNTLA_REGION_12_13';
  mmDCP5_REGAMMA_CNTLA_REGION_14_15                        :Result:='mmDCP5_REGAMMA_CNTLA_REGION_14_15';
  mmDCP5_REGAMMA_CNTLB_START_CNTL                          :Result:='mmDCP5_REGAMMA_CNTLB_START_CNTL';
  mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL                          :Result:='mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL';
  mmDCP5_REGAMMA_CNTLB_END_CNTL1                           :Result:='mmDCP5_REGAMMA_CNTLB_END_CNTL1';
  mmDCP5_REGAMMA_CNTLB_END_CNTL2                           :Result:='mmDCP5_REGAMMA_CNTLB_END_CNTL2';
  mmDCP5_REGAMMA_CNTLB_REGION_0_1                          :Result:='mmDCP5_REGAMMA_CNTLB_REGION_0_1';
  mmDCP5_REGAMMA_CNTLB_REGION_2_3                          :Result:='mmDCP5_REGAMMA_CNTLB_REGION_2_3';
  mmDCP5_REGAMMA_CNTLB_REGION_4_5                          :Result:='mmDCP5_REGAMMA_CNTLB_REGION_4_5';
  mmDCP5_REGAMMA_CNTLB_REGION_6_7                          :Result:='mmDCP5_REGAMMA_CNTLB_REGION_6_7';
  mmDCP5_REGAMMA_CNTLB_REGION_8_9                          :Result:='mmDCP5_REGAMMA_CNTLB_REGION_8_9';
  mmDCP5_REGAMMA_CNTLB_REGION_10_11                        :Result:='mmDCP5_REGAMMA_CNTLB_REGION_10_11';
  mmDCP5_REGAMMA_CNTLB_REGION_12_13                        :Result:='mmDCP5_REGAMMA_CNTLB_REGION_12_13';
  mmDCP5_REGAMMA_CNTLB_REGION_14_15                        :Result:='mmDCP5_REGAMMA_CNTLB_REGION_14_15';
  mmDCP5_ALPHA_CONTROL                                     :Result:='mmDCP5_ALPHA_CONTROL';
  mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                :Result:='mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS';
  mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH           :Result:='mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH';
  mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS              :Result:='mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS';
  mmLB5_LB_DATA_FORMAT                                     :Result:='mmLB5_LB_DATA_FORMAT';
  mmLB5_LB_MEMORY_CTRL                                     :Result:='mmLB5_LB_MEMORY_CTRL';
  mmLB5_LB_MEMORY_SIZE_STATUS                              :Result:='mmLB5_LB_MEMORY_SIZE_STATUS';
  mmLB5_LB_DESKTOP_HEIGHT                                  :Result:='mmLB5_LB_DESKTOP_HEIGHT';
  mmLB5_LB_VLINE_START_END                                 :Result:='mmLB5_LB_VLINE_START_END';
  mmLB5_LB_VLINE2_START_END                                :Result:='mmLB5_LB_VLINE2_START_END';
  mmLB5_LB_V_COUNTER                                       :Result:='mmLB5_LB_V_COUNTER';
  mmLB5_LB_SNAPSHOT_V_COUNTER                              :Result:='mmLB5_LB_SNAPSHOT_V_COUNTER';
  mmLB5_LB_INTERRUPT_MASK                                  :Result:='mmLB5_LB_INTERRUPT_MASK';
  mmLB5_LB_VLINE_STATUS                                    :Result:='mmLB5_LB_VLINE_STATUS';
  mmLB5_LB_VLINE2_STATUS                                   :Result:='mmLB5_LB_VLINE2_STATUS';
  mmLB5_LB_VBLANK_STATUS                                   :Result:='mmLB5_LB_VBLANK_STATUS';
  mmLB5_LB_SYNC_RESET_SEL                                  :Result:='mmLB5_LB_SYNC_RESET_SEL';
  mmLB5_LB_BLACK_KEYER_R_CR                                :Result:='mmLB5_LB_BLACK_KEYER_R_CR';
  mmLB5_LB_BLACK_KEYER_G_Y                                 :Result:='mmLB5_LB_BLACK_KEYER_G_Y';
  mmLB5_LB_BLACK_KEYER_B_CB                                :Result:='mmLB5_LB_BLACK_KEYER_B_CB';
  mmLB5_LB_KEYER_COLOR_CTRL                                :Result:='mmLB5_LB_KEYER_COLOR_CTRL';
  mmLB5_LB_KEYER_COLOR_R_CR                                :Result:='mmLB5_LB_KEYER_COLOR_R_CR';
  mmLB5_LB_KEYER_COLOR_G_Y                                 :Result:='mmLB5_LB_KEYER_COLOR_G_Y';
  mmLB5_LB_KEYER_COLOR_B_CB                                :Result:='mmLB5_LB_KEYER_COLOR_B_CB';
  mmLB5_LB_KEYER_COLOR_REP_R_CR                            :Result:='mmLB5_LB_KEYER_COLOR_REP_R_CR';
  mmLB5_LB_KEYER_COLOR_REP_G_Y                             :Result:='mmLB5_LB_KEYER_COLOR_REP_G_Y';
  mmLB5_LB_KEYER_COLOR_REP_B_CB                            :Result:='mmLB5_LB_KEYER_COLOR_REP_B_CB';
  mmLB5_LB_BUFFER_LEVEL_STATUS                             :Result:='mmLB5_LB_BUFFER_LEVEL_STATUS';
  mmLB5_LB_BUFFER_URGENCY_CTRL                             :Result:='mmLB5_LB_BUFFER_URGENCY_CTRL';
  mmLB5_LB_BUFFER_URGENCY_STATUS                           :Result:='mmLB5_LB_BUFFER_URGENCY_STATUS';
  mmLB5_LB_BUFFER_STATUS                                   :Result:='mmLB5_LB_BUFFER_STATUS';
  mmLB5_LB_NO_OUTSTANDING_REQ_STATUS                       :Result:='mmLB5_LB_NO_OUTSTANDING_REQ_STATUS';
  mmLB5_MVP_AFR_FLIP_MODE                                  :Result:='mmLB5_MVP_AFR_FLIP_MODE';
  mmLB5_MVP_AFR_FLIP_FIFO_CNTL                             :Result:='mmLB5_MVP_AFR_FLIP_FIFO_CNTL';
  mmLB5_MVP_FLIP_LINE_NUM_INSERT                           :Result:='mmLB5_MVP_FLIP_LINE_NUM_INSERT';
  mmLB5_DC_MVP_LB_CONTROL                                  :Result:='mmLB5_DC_MVP_LB_CONTROL';
  mmLB5_LB_DEBUG                                           :Result:='mmLB5_LB_DEBUG';
  mmLB5_LB_DEBUG2                                          :Result:='mmLB5_LB_DEBUG2';
  mmLB5_LB_DEBUG3                                          :Result:='mmLB5_LB_DEBUG3';
  mmLB5_LB_TEST_DEBUG_INDEX                                :Result:='mmLB5_LB_TEST_DEBUG_INDEX';
  mmLB5_LB_TEST_DEBUG_DATA                                 :Result:='mmLB5_LB_TEST_DEBUG_DATA';
  mmDCFE5_DCFE_CLOCK_CONTROL                               :Result:='mmDCFE5_DCFE_CLOCK_CONTROL';
  mmDCFE5_DCFE_SOFT_RESET                                  :Result:='mmDCFE5_DCFE_SOFT_RESET';
  mmDCFE5_DCFE_DBG_CONFIG                                  :Result:='mmDCFE5_DCFE_DBG_CONFIG';
  mmDIG3_HDMI_GENERIC_PACKET_CONTROL                       :Result:='mmDIG3_HDMI_GENERIC_PACKET_CONTROL';
  mmDC_PERFMON8_PERFCOUNTER_CNTL                           :Result:='mmDC_PERFMON8_PERFCOUNTER_CNTL';
  mmDC_PERFMON8_PERFCOUNTER_STATE                          :Result:='mmDC_PERFMON8_PERFCOUNTER_STATE';
  mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                    :Result:='mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC';
  mmDC_PERFMON8_PERFMON_CNTL                               :Result:='mmDC_PERFMON8_PERFMON_CNTL';
  mmDC_PERFMON8_PERFMON_CVALUE_LOW                         :Result:='mmDC_PERFMON8_PERFMON_CVALUE_LOW';
  mmDC_PERFMON8_PERFMON_HI                                 :Result:='mmDC_PERFMON8_PERFMON_HI';
  mmDC_PERFMON8_PERFMON_LOW                                :Result:='mmDC_PERFMON8_PERFMON_LOW';
  mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX                   :Result:='mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX';
  mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA                    :Result:='mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA';
  mmDC_PERFMON8_PERFMON_CNTL2                              :Result:='mmDC_PERFMON8_PERFMON_CNTL2';
  mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1                 :Result:='mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1';
  mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2                 :Result:='mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2';
  mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL                    :Result:='mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL';
  mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL                      :Result:='mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL';
  mmDMIF_PG5_DPG_PIPE_DPM_CONTROL                          :Result:='mmDMIF_PG5_DPG_PIPE_DPM_CONTROL';
  mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL                      :Result:='mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL';
  mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             :Result:='mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL';
  mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             :Result:='mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH';
  mmDMIF_PG5_DPG_TEST_DEBUG_INDEX                          :Result:='mmDMIF_PG5_DPG_TEST_DEBUG_INDEX';
  mmDMIF_PG5_DPG_TEST_DEBUG_DATA                           :Result:='mmDMIF_PG5_DPG_TEST_DEBUG_DATA';
  mmDMIF_PG5_DPG_REPEATER_PROGRAM                          :Result:='mmDMIF_PG5_DPG_REPEATER_PROGRAM';
  mmDMIF_PG5_DPG_HW_DEBUG_A                                :Result:='mmDMIF_PG5_DPG_HW_DEBUG_A';
  mmDMIF_PG5_DPG_HW_DEBUG_B                                :Result:='mmDMIF_PG5_DPG_HW_DEBUG_B';
  mmDMIF_PG5_DPG_HW_DEBUG_11                               :Result:='mmDMIF_PG5_DPG_HW_DEBUG_11';
  mmSCL5_SCL_COEF_RAM_SELECT                               :Result:='mmSCL5_SCL_COEF_RAM_SELECT';
  mmSCL5_SCL_COEF_RAM_TAP_DATA                             :Result:='mmSCL5_SCL_COEF_RAM_TAP_DATA';
  mmSCL5_SCL_MODE                                          :Result:='mmSCL5_SCL_MODE';
  mmSCL5_SCL_TAP_CONTROL                                   :Result:='mmSCL5_SCL_TAP_CONTROL';
  mmSCL5_SCL_CONTROL                                       :Result:='mmSCL5_SCL_CONTROL';
  mmSCL5_SCL_BYPASS_CONTROL                                :Result:='mmSCL5_SCL_BYPASS_CONTROL';
  mmSCL5_SCL_MANUAL_REPLICATE_CONTROL                      :Result:='mmSCL5_SCL_MANUAL_REPLICATE_CONTROL';
  mmSCL5_SCL_AUTOMATIC_MODE_CONTROL                        :Result:='mmSCL5_SCL_AUTOMATIC_MODE_CONTROL';
  mmSCL5_SCL_HORZ_FILTER_CONTROL                           :Result:='mmSCL5_SCL_HORZ_FILTER_CONTROL';
  mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO                       :Result:='mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO';
  mmSCL5_SCL_HORZ_FILTER_INIT                              :Result:='mmSCL5_SCL_HORZ_FILTER_INIT';
  mmSCL5_SCL_VERT_FILTER_CONTROL                           :Result:='mmSCL5_SCL_VERT_FILTER_CONTROL';
  mmSCL5_SCL_VERT_FILTER_SCALE_RATIO                       :Result:='mmSCL5_SCL_VERT_FILTER_SCALE_RATIO';
  mmSCL5_SCL_VERT_FILTER_INIT                              :Result:='mmSCL5_SCL_VERT_FILTER_INIT';
  mmSCL5_SCL_VERT_FILTER_INIT_BOT                          :Result:='mmSCL5_SCL_VERT_FILTER_INIT_BOT';
  mmSCL5_SCL_ROUND_OFFSET                                  :Result:='mmSCL5_SCL_ROUND_OFFSET';
  mmSCL5_SCL_UPDATE                                        :Result:='mmSCL5_SCL_UPDATE';
  mmSCL5_SCL_F_SHARP_CONTROL                               :Result:='mmSCL5_SCL_F_SHARP_CONTROL';
  mmSCL5_SCL_ALU_CONTROL                                   :Result:='mmSCL5_SCL_ALU_CONTROL';
  mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS                      :Result:='mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS';
  mmSCL5_VIEWPORT_START_SECONDARY                          :Result:='mmSCL5_VIEWPORT_START_SECONDARY';
  mmSCL5_VIEWPORT_START                                    :Result:='mmSCL5_VIEWPORT_START';
  mmSCL5_VIEWPORT_SIZE                                     :Result:='mmSCL5_VIEWPORT_SIZE';
  mmSCL5_EXT_OVERSCAN_LEFT_RIGHT                           :Result:='mmSCL5_EXT_OVERSCAN_LEFT_RIGHT';
  mmSCL5_EXT_OVERSCAN_TOP_BOTTOM                           :Result:='mmSCL5_EXT_OVERSCAN_TOP_BOTTOM';
  mmSCL5_SCL_MODE_CHANGE_DET1                              :Result:='mmSCL5_SCL_MODE_CHANGE_DET1';
  mmSCL5_SCL_MODE_CHANGE_DET2                              :Result:='mmSCL5_SCL_MODE_CHANGE_DET2';
  mmSCL5_SCL_MODE_CHANGE_DET3                              :Result:='mmSCL5_SCL_MODE_CHANGE_DET3';
  mmSCL5_SCL_MODE_CHANGE_MASK                              :Result:='mmSCL5_SCL_MODE_CHANGE_MASK';
  mmSCL5_SCL_DEBUG2                                        :Result:='mmSCL5_SCL_DEBUG2';
  mmSCL5_SCL_DEBUG                                         :Result:='mmSCL5_SCL_DEBUG';
  mmSCL5_SCL_TEST_DEBUG_INDEX                              :Result:='mmSCL5_SCL_TEST_DEBUG_INDEX';
  mmSCL5_SCL_TEST_DEBUG_DATA                               :Result:='mmSCL5_SCL_TEST_DEBUG_DATA';
  mmBLND5_BLND_CONTROL                                     :Result:='mmBLND5_BLND_CONTROL';
  mmBLND5_SM_CONTROL2                                      :Result:='mmBLND5_SM_CONTROL2';
  mmBLND5_BLND_CONTROL2                                    :Result:='mmBLND5_BLND_CONTROL2';
  mmBLND5_BLND_UPDATE                                      :Result:='mmBLND5_BLND_UPDATE';
  mmBLND5_BLND_UNDERFLOW_INTERRUPT                         :Result:='mmBLND5_BLND_UNDERFLOW_INTERRUPT';
  mmBLND5_BLND_V_UPDATE_LOCK                               :Result:='mmBLND5_BLND_V_UPDATE_LOCK';
  mmBLND5_BLND_DEBUG                                       :Result:='mmBLND5_BLND_DEBUG';
  mmBLND5_BLND_TEST_DEBUG_INDEX                            :Result:='mmBLND5_BLND_TEST_DEBUG_INDEX';
  mmBLND5_BLND_TEST_DEBUG_DATA                             :Result:='mmBLND5_BLND_TEST_DEBUG_DATA';
  mmBLND5_BLND_REG_UPDATE_STATUS                           :Result:='mmBLND5_BLND_REG_UPDATE_STATUS';
  mmCRTC5_CRTC_3D_STRUCTURE_CONTROL                        :Result:='mmCRTC5_CRTC_3D_STRUCTURE_CONTROL';
  mmCRTC5_CRTC_GSL_VSYNC_GAP                               :Result:='mmCRTC5_CRTC_GSL_VSYNC_GAP';
  mmCRTC5_CRTC_GSL_WINDOW                                  :Result:='mmCRTC5_CRTC_GSL_WINDOW';
  mmCRTC5_CRTC_GSL_CONTROL                                 :Result:='mmCRTC5_CRTC_GSL_CONTROL';
  mmCRTC5_CRTC_DCFE_CLOCK_CONTROL                          :Result:='mmCRTC5_CRTC_DCFE_CLOCK_CONTROL';
  mmCRTC5_CRTC_H_BLANK_EARLY_NUM                           :Result:='mmCRTC5_CRTC_H_BLANK_EARLY_NUM';
  mmCRTC5_DCFE_DBG_SEL                                     :Result:='mmCRTC5_DCFE_DBG_SEL';
  mmCRTC5_DCFE_MEM_PWR_CTRL                                :Result:='mmCRTC5_DCFE_MEM_PWR_CTRL';
  mmCRTC5_CRTC_H_SYNC_B_CNTL                               :Result:='mmCRTC5_CRTC_H_SYNC_B_CNTL';
  mmCRTC5_CRTC_V_TOTAL_MIN                                 :Result:='mmCRTC5_CRTC_V_TOTAL_MIN';
  mmCRTC5_CRTC_V_TOTAL_MAX                                 :Result:='mmCRTC5_CRTC_V_TOTAL_MAX';
  mmCRTC5_CRTC_V_TOTAL_CONTROL                             :Result:='mmCRTC5_CRTC_V_TOTAL_CONTROL';
  mmCRTC5_CRTC_V_TOTAL_INT_STATUS                          :Result:='mmCRTC5_CRTC_V_TOTAL_INT_STATUS';
  mmCRTC5_CRTC_V_BLANK_START_END                           :Result:='mmCRTC5_CRTC_V_BLANK_START_END';
  mmCRTC5_CRTC_V_SYNC_A                                    :Result:='mmCRTC5_CRTC_V_SYNC_A';
  mmCRTC5_CRTC_V_SYNC_A_CNTL                               :Result:='mmCRTC5_CRTC_V_SYNC_A_CNTL';
  mmCRTC5_CRTC_V_SYNC_B                                    :Result:='mmCRTC5_CRTC_V_SYNC_B';
  mmCRTC5_CRTC_V_SYNC_B_CNTL                               :Result:='mmCRTC5_CRTC_V_SYNC_B_CNTL';
  mmCRTC5_CRTC_DTMTEST_CNTL                                :Result:='mmCRTC5_CRTC_DTMTEST_CNTL';
  mmCRTC5_CRTC_DTMTEST_STATUS_POSITION                     :Result:='mmCRTC5_CRTC_DTMTEST_STATUS_POSITION';
  mmCRTC5_CRTC_TRIGA_CNTL                                  :Result:='mmCRTC5_CRTC_TRIGA_CNTL';
  mmCRTC5_CRTC_TRIGA_MANUAL_TRIG                           :Result:='mmCRTC5_CRTC_TRIGA_MANUAL_TRIG';
  mmCRTC5_CRTC_TRIGB_CNTL                                  :Result:='mmCRTC5_CRTC_TRIGB_CNTL';
  mmCRTC5_CRTC_TRIGB_MANUAL_TRIG                           :Result:='mmCRTC5_CRTC_TRIGB_MANUAL_TRIG';
  mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL                        :Result:='mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL';
  mmCRTC5_CRTC_FLOW_CONTROL                                :Result:='mmCRTC5_CRTC_FLOW_CONTROL';
  mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE                       :Result:='mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE';
  mmCRTC5_CRTC_AVSYNC_COUNTER                              :Result:='mmCRTC5_CRTC_AVSYNC_COUNTER';
  mmCRTC5_CRTC_CONTROL                                     :Result:='mmCRTC5_CRTC_CONTROL';
  mmCRTC5_CRTC_BLANK_CONTROL                               :Result:='mmCRTC5_CRTC_BLANK_CONTROL';
  mmCRTC5_CRTC_INTERLACE_CONTROL                           :Result:='mmCRTC5_CRTC_INTERLACE_CONTROL';
  mmCRTC5_CRTC_INTERLACE_STATUS                            :Result:='mmCRTC5_CRTC_INTERLACE_STATUS';
  mmCRTC5_CRTC_FIELD_INDICATION_CONTROL                    :Result:='mmCRTC5_CRTC_FIELD_INDICATION_CONTROL';
  mmCRTC5_CRTC_PIXEL_DATA_READBACK0                        :Result:='mmCRTC5_CRTC_PIXEL_DATA_READBACK0';
  mmCRTC5_CRTC_PIXEL_DATA_READBACK1                        :Result:='mmCRTC5_CRTC_PIXEL_DATA_READBACK1';
  mmCRTC5_CRTC_STATUS                                      :Result:='mmCRTC5_CRTC_STATUS';
  mmCRTC5_CRTC_STATUS_POSITION                             :Result:='mmCRTC5_CRTC_STATUS_POSITION';
  mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                :Result:='mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE';
  mmCRTC5_CRTC_VERT_SYNC_CONTROL                           :Result:='mmCRTC5_CRTC_VERT_SYNC_CONTROL';
  mmCRTC5_CRTC_STEREO_STATUS                               :Result:='mmCRTC5_CRTC_STEREO_STATUS';
  mmCRTC5_CRTC_STEREO_CONTROL                              :Result:='mmCRTC5_CRTC_STEREO_CONTROL';
  mmCRTC5_CRTC_SNAPSHOT_STATUS                             :Result:='mmCRTC5_CRTC_SNAPSHOT_STATUS';
  mmCRTC5_CRTC_SNAPSHOT_CONTROL                            :Result:='mmCRTC5_CRTC_SNAPSHOT_CONTROL';
  mmCRTC5_CRTC_SNAPSHOT_POSITION                           :Result:='mmCRTC5_CRTC_SNAPSHOT_POSITION';
  mmCRTC5_CRTC_SNAPSHOT_FRAME                              :Result:='mmCRTC5_CRTC_SNAPSHOT_FRAME';
  mmCRTC5_CRTC_START_LINE_CONTROL                          :Result:='mmCRTC5_CRTC_START_LINE_CONTROL';
  mmCRTC5_CRTC_INTERRUPT_CONTROL                           :Result:='mmCRTC5_CRTC_INTERRUPT_CONTROL';
  mmCRTC5_CRTC_UPDATE_LOCK                                 :Result:='mmCRTC5_CRTC_UPDATE_LOCK';
  mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL                       :Result:='mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL';
  mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE                  :Result:='mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE';
  mmCRTC5_DCFE_MEM_PWR_CTRL2                               :Result:='mmCRTC5_DCFE_MEM_PWR_CTRL2';
  mmCRTC5_DCFE_MEM_PWR_STATUS                              :Result:='mmCRTC5_DCFE_MEM_PWR_STATUS';
  mmCRTC5_CRTC_TEST_PATTERN_CONTROL                        :Result:='mmCRTC5_CRTC_TEST_PATTERN_CONTROL';
  mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS                     :Result:='mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS';
  mmCRTC5_CRTC_TEST_PATTERN_COLOR                          :Result:='mmCRTC5_CRTC_TEST_PATTERN_COLOR';
  mmCRTC5_MASTER_UPDATE_LOCK                               :Result:='mmCRTC5_MASTER_UPDATE_LOCK';
  mmCRTC5_MASTER_UPDATE_MODE                               :Result:='mmCRTC5_MASTER_UPDATE_MODE';
  mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT                      :Result:='mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT';
  mmCRTC5_CRTC_TEST_DEBUG_INDEX                            :Result:='mmCRTC5_CRTC_TEST_DEBUG_INDEX';
  mmCRTC5_CRTC_TEST_DEBUG_DATA                             :Result:='mmCRTC5_CRTC_TEST_DEBUG_DATA';
  mmCRTC5_CRTC_OVERSCAN_COLOR                              :Result:='mmCRTC5_CRTC_OVERSCAN_COLOR';
  mmCRTC5_CRTC_OVERSCAN_COLOR_EXT                          :Result:='mmCRTC5_CRTC_OVERSCAN_COLOR_EXT';
  mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT                        :Result:='mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT';
  mmCRTC5_CRTC_BLACK_COLOR                                 :Result:='mmCRTC5_CRTC_BLACK_COLOR';
  mmCRTC5_CRTC_BLACK_COLOR_EXT                             :Result:='mmCRTC5_CRTC_BLACK_COLOR_EXT';
  mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION                :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION';
  mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL                 :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL';
  mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION                :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION';
  mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL                 :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL';
  mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION                :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION';
  mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL                 :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL';
  mmCRTC5_CRTC_CRC_CNTL                                    :Result:='mmCRTC5_CRTC_CRC_CNTL';
  mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL                      :Result:='mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL';
  mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL                      :Result:='mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL';
  mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL                      :Result:='mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL';
  mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL                      :Result:='mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL';
  mmCRTC5_CRTC_CRC0_DATA_RG                                :Result:='mmCRTC5_CRTC_CRC0_DATA_RG';
  mmCRTC5_CRTC_CRC0_DATA_B                                 :Result:='mmCRTC5_CRTC_CRC0_DATA_B';
  mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL                      :Result:='mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL';
  mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL                      :Result:='mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL';
  mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL                      :Result:='mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL';
  mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL                      :Result:='mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL';
  mmCRTC5_CRTC_CRC1_DATA_RG                                :Result:='mmCRTC5_CRTC_CRC1_DATA_RG';
  mmCRTC5_CRTC_CRC1_DATA_B                                 :Result:='mmCRTC5_CRTC_CRC1_DATA_B';
  mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL                     :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL';
  mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START                :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START';
  mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END                  :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END';
  mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL';
  mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL';
  mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL';
  mmCRTC5_CRTC_STATIC_SCREEN_CONTROL                       :Result:='mmCRTC5_CRTC_STATIC_SCREEN_CONTROL';
  mmFMT5_FMT_CLAMP_COMPONENT_R                             :Result:='mmFMT5_FMT_CLAMP_COMPONENT_R';
  mmFMT5_FMT_CLAMP_COMPONENT_G                             :Result:='mmFMT5_FMT_CLAMP_COMPONENT_G';
  mmFMT5_FMT_CLAMP_COMPONENT_B                             :Result:='mmFMT5_FMT_CLAMP_COMPONENT_B';
  mmFMT5_FMT_TEST_DEBUG_INDEX                              :Result:='mmFMT5_FMT_TEST_DEBUG_INDEX';
  mmFMT5_FMT_TEST_DEBUG_DATA                               :Result:='mmFMT5_FMT_TEST_DEBUG_DATA';
  mmFMT5_FMT_DYNAMIC_EXP_CNTL                              :Result:='mmFMT5_FMT_DYNAMIC_EXP_CNTL';
  mmFMT5_FMT_CONTROL                                       :Result:='mmFMT5_FMT_CONTROL';
  mmFMT5_FMT_FORCE_OUTPUT_CNTL                             :Result:='mmFMT5_FMT_FORCE_OUTPUT_CNTL';
  mmFMT5_FMT_FORCE_DATA_0_1                                :Result:='mmFMT5_FMT_FORCE_DATA_0_1';
  mmFMT5_FMT_FORCE_DATA_2_3                                :Result:='mmFMT5_FMT_FORCE_DATA_2_3';
  mmFMT5_FMT_BIT_DEPTH_CONTROL                             :Result:='mmFMT5_FMT_BIT_DEPTH_CONTROL';
  mmFMT5_FMT_DITHER_RAND_R_SEED                            :Result:='mmFMT5_FMT_DITHER_RAND_R_SEED';
  mmFMT5_FMT_DITHER_RAND_G_SEED                            :Result:='mmFMT5_FMT_DITHER_RAND_G_SEED';
  mmFMT5_FMT_DITHER_RAND_B_SEED                            :Result:='mmFMT5_FMT_DITHER_RAND_B_SEED';
  mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL               :Result:='mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL';
  mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :Result:='mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX';
  mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :Result:='mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX';
  mmFMT5_FMT_CLAMP_CNTL                                    :Result:='mmFMT5_FMT_CLAMP_CNTL';
  mmFMT5_FMT_CRC_CNTL                                      :Result:='mmFMT5_FMT_CRC_CNTL';
  mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK                        :Result:='mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK';
  mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK                     :Result:='mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK';
  mmFMT5_FMT_CRC_SIG_RED_GREEN                             :Result:='mmFMT5_FMT_CRC_SIG_RED_GREEN';
  mmFMT5_FMT_CRC_SIG_BLUE_CONTROL                          :Result:='mmFMT5_FMT_CRC_SIG_BLUE_CONTROL';
  mmFMT5_FMT_DEBUG_CNTL                                    :Result:='mmFMT5_FMT_DEBUG_CNTL';
  mmUNP_GRPH_ENABLE                                        :Result:='mmUNP_GRPH_ENABLE';
  mmUNP_GRPH_CONTROL                                       :Result:='mmUNP_GRPH_CONTROL';
  mmUNP_GRPH_CONTROL_EXP                                   :Result:='mmUNP_GRPH_CONTROL_EXP';
  mmUNP_GRPH_SWAP_CNTL                                     :Result:='mmUNP_GRPH_SWAP_CNTL';
  mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                     :Result:='mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L';
  mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                     :Result:='mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C';
  mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                :Result:='mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L';
  mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                :Result:='mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C';
  mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L              :Result:='mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L';
  mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C              :Result:='mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C';
  mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L         :Result:='mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L';
  mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C         :Result:='mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C';
  mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                   :Result:='mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L';
  mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                   :Result:='mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C';
  mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L              :Result:='mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L';
  mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C              :Result:='mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C';
  mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L            :Result:='mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L';
  mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C            :Result:='mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C';
  mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L       :Result:='mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L';
  mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C       :Result:='mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C';
  mmUNP_GRPH_PITCH_L                                       :Result:='mmUNP_GRPH_PITCH_L';
  mmUNP_GRPH_PITCH_C                                       :Result:='mmUNP_GRPH_PITCH_C';
  mmUNP_GRPH_SURFACE_OFFSET_X_L                            :Result:='mmUNP_GRPH_SURFACE_OFFSET_X_L';
  mmUNP_GRPH_SURFACE_OFFSET_X_C                            :Result:='mmUNP_GRPH_SURFACE_OFFSET_X_C';
  mmUNP_GRPH_SURFACE_OFFSET_Y_L                            :Result:='mmUNP_GRPH_SURFACE_OFFSET_Y_L';
  mmUNP_GRPH_SURFACE_OFFSET_Y_C                            :Result:='mmUNP_GRPH_SURFACE_OFFSET_Y_C';
  mmUNP_GRPH_X_START_L                                     :Result:='mmUNP_GRPH_X_START_L';
  mmUNP_GRPH_X_START_C                                     :Result:='mmUNP_GRPH_X_START_C';
  mmUNP_GRPH_Y_START_L                                     :Result:='mmUNP_GRPH_Y_START_L';
  mmUNP_GRPH_Y_START_C                                     :Result:='mmUNP_GRPH_Y_START_C';
  mmUNP_GRPH_X_END_L                                       :Result:='mmUNP_GRPH_X_END_L';
  mmUNP_GRPH_X_END_C                                       :Result:='mmUNP_GRPH_X_END_C';
  mmUNP_GRPH_Y_END_L                                       :Result:='mmUNP_GRPH_Y_END_L';
  mmUNP_GRPH_Y_END_C                                       :Result:='mmUNP_GRPH_Y_END_C';
  mmUNP_GRPH_UPDATE                                        :Result:='mmUNP_GRPH_UPDATE';
  mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L                       :Result:='mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L';
  mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C                       :Result:='mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C';
  mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                  :Result:='mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L';
  mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                  :Result:='mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C';
  mmUNP_GRPH_DFQ_CONTROL                                   :Result:='mmUNP_GRPH_DFQ_CONTROL';
  mmUNP_GRPH_DFQ_STATUS                                    :Result:='mmUNP_GRPH_DFQ_STATUS';
  mmUNP_GRPH_INTERRUPT_STATUS                              :Result:='mmUNP_GRPH_INTERRUPT_STATUS';
  mmUNP_GRPH_INTERRUPT_CONTROL                             :Result:='mmUNP_GRPH_INTERRUPT_CONTROL';
  mmUNP_GRPH_STEREOSYNC_FLIP                               :Result:='mmUNP_GRPH_STEREOSYNC_FLIP';
  mmUNP_GRPH_FLIP_RATE_CNTL                                :Result:='mmUNP_GRPH_FLIP_RATE_CNTL';
  mmUNP_CRC_CONTROL                                        :Result:='mmUNP_CRC_CONTROL';
  mmUNP_CRC_MASK                                           :Result:='mmUNP_CRC_MASK';
  mmUNP_CRC_CURRENT                                        :Result:='mmUNP_CRC_CURRENT';
  mmUNP_CRC_LAST                                           :Result:='mmUNP_CRC_LAST';
  mmUNP_LB_DATA_GAP_BETWEEN_CHUNK                          :Result:='mmUNP_LB_DATA_GAP_BETWEEN_CHUNK';
  mmUNP_HW_ROTATION                                        :Result:='mmUNP_HW_ROTATION';
  mmUNP_DEBUG                                              :Result:='mmUNP_DEBUG';
  mmUNP_DEBUG2                                             :Result:='mmUNP_DEBUG2';
  mmUNP_TEST_DEBUG_INDEX                                   :Result:='mmUNP_TEST_DEBUG_INDEX';
  mmUNP_TEST_DEBUG_DATA                                    :Result:='mmUNP_TEST_DEBUG_DATA';
  mmLBV_DATA_FORMAT                                        :Result:='mmLBV_DATA_FORMAT';
  mmLBV_MEMORY_CTRL                                        :Result:='mmLBV_MEMORY_CTRL';
  mmLBV_MEMORY_SIZE_STATUS                                 :Result:='mmLBV_MEMORY_SIZE_STATUS';
  mmLBV_DESKTOP_HEIGHT                                     :Result:='mmLBV_DESKTOP_HEIGHT';
  mmLBV_VLINE_START_END                                    :Result:='mmLBV_VLINE_START_END';
  mmLBV_VLINE2_START_END                                   :Result:='mmLBV_VLINE2_START_END';
  mmLBV_V_COUNTER                                          :Result:='mmLBV_V_COUNTER';
  mmLBV_SNAPSHOT_V_COUNTER                                 :Result:='mmLBV_SNAPSHOT_V_COUNTER';
  mmLBV_V_COUNTER_CHROMA                                   :Result:='mmLBV_V_COUNTER_CHROMA';
  mmLBV_SNAPSHOT_V_COUNTER_CHROMA                          :Result:='mmLBV_SNAPSHOT_V_COUNTER_CHROMA';
  mmLBV_INTERRUPT_MASK                                     :Result:='mmLBV_INTERRUPT_MASK';
  mmLBV_VLINE_STATUS                                       :Result:='mmLBV_VLINE_STATUS';
  mmLBV_VLINE2_STATUS                                      :Result:='mmLBV_VLINE2_STATUS';
  mmLBV_VBLANK_STATUS                                      :Result:='mmLBV_VBLANK_STATUS';
  mmLBV_SYNC_RESET_SEL                                     :Result:='mmLBV_SYNC_RESET_SEL';
  mmLBV_BLACK_KEYER_R_CR                                   :Result:='mmLBV_BLACK_KEYER_R_CR';
  mmLBV_BLACK_KEYER_G_Y                                    :Result:='mmLBV_BLACK_KEYER_G_Y';
  mmLBV_BLACK_KEYER_B_CB                                   :Result:='mmLBV_BLACK_KEYER_B_CB';
  mmLBV_KEYER_COLOR_CTRL                                   :Result:='mmLBV_KEYER_COLOR_CTRL';
  mmLBV_KEYER_COLOR_R_CR                                   :Result:='mmLBV_KEYER_COLOR_R_CR';
  mmLBV_KEYER_COLOR_G_Y                                    :Result:='mmLBV_KEYER_COLOR_G_Y';
  mmLBV_KEYER_COLOR_B_CB                                   :Result:='mmLBV_KEYER_COLOR_B_CB';
  mmLBV_KEYER_COLOR_REP_R_CR                               :Result:='mmLBV_KEYER_COLOR_REP_R_CR';
  mmLBV_KEYER_COLOR_REP_G_Y                                :Result:='mmLBV_KEYER_COLOR_REP_G_Y';
  mmLBV_KEYER_COLOR_REP_B_CB                               :Result:='mmLBV_KEYER_COLOR_REP_B_CB';
  mmLBV_BUFFER_LEVEL_STATUS                                :Result:='mmLBV_BUFFER_LEVEL_STATUS';
  mmLBV_BUFFER_URGENCY_CTRL                                :Result:='mmLBV_BUFFER_URGENCY_CTRL';
  mmLBV_BUFFER_URGENCY_STATUS                              :Result:='mmLBV_BUFFER_URGENCY_STATUS';
  mmLBV_BUFFER_STATUS                                      :Result:='mmLBV_BUFFER_STATUS';
  mmLBV_NO_OUTSTANDING_REQ_STATUS                          :Result:='mmLBV_NO_OUTSTANDING_REQ_STATUS';
  mmLBV_DEBUG                                              :Result:='mmLBV_DEBUG';
  mmLBV_DEBUG2                                             :Result:='mmLBV_DEBUG2';
  mmLBV_DEBUG3                                             :Result:='mmLBV_DEBUG3';
  mmLBV_TEST_DEBUG_INDEX                                   :Result:='mmLBV_TEST_DEBUG_INDEX';
  mmLBV_TEST_DEBUG_DATA                                    :Result:='mmLBV_TEST_DEBUG_DATA';
  mmSCLV_COEF_RAM_SELECT                                   :Result:='mmSCLV_COEF_RAM_SELECT';
  mmSCLV_COEF_RAM_TAP_DATA                                 :Result:='mmSCLV_COEF_RAM_TAP_DATA';
  mmSCLV_MODE                                              :Result:='mmSCLV_MODE';
  mmSCLV_TAP_CONTROL                                       :Result:='mmSCLV_TAP_CONTROL';
  mmSCLV_CONTROL                                           :Result:='mmSCLV_CONTROL';
  mmSCLV_MANUAL_REPLICATE_CONTROL                          :Result:='mmSCLV_MANUAL_REPLICATE_CONTROL';
  mmSCLV_AUTOMATIC_MODE_CONTROL                            :Result:='mmSCLV_AUTOMATIC_MODE_CONTROL';
  mmSCLV_HORZ_FILTER_CONTROL                               :Result:='mmSCLV_HORZ_FILTER_CONTROL';
  mmSCLV_HORZ_FILTER_SCALE_RATIO                           :Result:='mmSCLV_HORZ_FILTER_SCALE_RATIO';
  mmSCLV_HORZ_FILTER_INIT                                  :Result:='mmSCLV_HORZ_FILTER_INIT';
  mmSCLV_HORZ_FILTER_SCALE_RATIO_C                         :Result:='mmSCLV_HORZ_FILTER_SCALE_RATIO_C';
  mmSCLV_HORZ_FILTER_INIT_C                                :Result:='mmSCLV_HORZ_FILTER_INIT_C';
  mmSCLV_VERT_FILTER_CONTROL                               :Result:='mmSCLV_VERT_FILTER_CONTROL';
  mmSCLV_VERT_FILTER_SCALE_RATIO                           :Result:='mmSCLV_VERT_FILTER_SCALE_RATIO';
  mmSCLV_VERT_FILTER_INIT                                  :Result:='mmSCLV_VERT_FILTER_INIT';
  mmSCLV_VERT_FILTER_INIT_BOT                              :Result:='mmSCLV_VERT_FILTER_INIT_BOT';
  mmSCLV_VERT_FILTER_SCALE_RATIO_C                         :Result:='mmSCLV_VERT_FILTER_SCALE_RATIO_C';
  mmSCLV_VERT_FILTER_INIT_C                                :Result:='mmSCLV_VERT_FILTER_INIT_C';
  mmSCLV_VERT_FILTER_INIT_BOT_C                            :Result:='mmSCLV_VERT_FILTER_INIT_BOT_C';
  mmSCLV_ROUND_OFFSET                                      :Result:='mmSCLV_ROUND_OFFSET';
  mmSCLV_UPDATE                                            :Result:='mmSCLV_UPDATE';
  mmSCLV_ALU_CONTROL                                       :Result:='mmSCLV_ALU_CONTROL';
  mmSCLV_VIEWPORT_START                                    :Result:='mmSCLV_VIEWPORT_START';
  mmSCLV_VIEWPORT_START_SECONDARY                          :Result:='mmSCLV_VIEWPORT_START_SECONDARY';
  mmSCLV_VIEWPORT_SIZE                                     :Result:='mmSCLV_VIEWPORT_SIZE';
  mmSCLV_VIEWPORT_START_C                                  :Result:='mmSCLV_VIEWPORT_START_C';
  mmSCLV_VIEWPORT_START_SECONDARY_C                        :Result:='mmSCLV_VIEWPORT_START_SECONDARY_C';
  mmSCLV_VIEWPORT_SIZE_C                                   :Result:='mmSCLV_VIEWPORT_SIZE_C';
  mmSCLV_EXT_OVERSCAN_LEFT_RIGHT                           :Result:='mmSCLV_EXT_OVERSCAN_LEFT_RIGHT';
  mmSCLV_EXT_OVERSCAN_TOP_BOTTOM                           :Result:='mmSCLV_EXT_OVERSCAN_TOP_BOTTOM';
  mmSCLV_MODE_CHANGE_DET1                                  :Result:='mmSCLV_MODE_CHANGE_DET1';
  mmSCLV_MODE_CHANGE_DET2                                  :Result:='mmSCLV_MODE_CHANGE_DET2';
  mmSCLV_MODE_CHANGE_DET3                                  :Result:='mmSCLV_MODE_CHANGE_DET3';
  mmSCLV_MODE_CHANGE_MASK                                  :Result:='mmSCLV_MODE_CHANGE_MASK';
  mmSCLV_DEBUG2                                            :Result:='mmSCLV_DEBUG2';
  mmSCLV_DEBUG                                             :Result:='mmSCLV_DEBUG';
  mmSCLV_TEST_DEBUG_INDEX                                  :Result:='mmSCLV_TEST_DEBUG_INDEX';
  mmSCLV_TEST_DEBUG_DATA                                   :Result:='mmSCLV_TEST_DEBUG_DATA';
  mmCOL_MAN_UPDATE                                         :Result:='mmCOL_MAN_UPDATE';
  mmCOL_MAN_INPUT_CSC_CONTROL                              :Result:='mmCOL_MAN_INPUT_CSC_CONTROL';
  mmINPUT_CSC_C11_C12_A                                    :Result:='mmINPUT_CSC_C11_C12_A';
  mmINPUT_CSC_C13_C14_A                                    :Result:='mmINPUT_CSC_C13_C14_A';
  mmINPUT_CSC_C21_C22_A                                    :Result:='mmINPUT_CSC_C21_C22_A';
  mmINPUT_CSC_C23_C24_A                                    :Result:='mmINPUT_CSC_C23_C24_A';
  mmINPUT_CSC_C31_C32_A                                    :Result:='mmINPUT_CSC_C31_C32_A';
  mmINPUT_CSC_C33_C34_A                                    :Result:='mmINPUT_CSC_C33_C34_A';
  mmINPUT_CSC_C11_C12_B                                    :Result:='mmINPUT_CSC_C11_C12_B';
  mmINPUT_CSC_C13_C14_B                                    :Result:='mmINPUT_CSC_C13_C14_B';
  mmINPUT_CSC_C21_C22_B                                    :Result:='mmINPUT_CSC_C21_C22_B';
  mmINPUT_CSC_C23_C24_B                                    :Result:='mmINPUT_CSC_C23_C24_B';
  mmINPUT_CSC_C31_C32_B                                    :Result:='mmINPUT_CSC_C31_C32_B';
  mmINPUT_CSC_C33_C34_B                                    :Result:='mmINPUT_CSC_C33_C34_B';
  mmPRESCALE_CONTROL                                       :Result:='mmPRESCALE_CONTROL';
  mmPRESCALE_VALUES_R                                      :Result:='mmPRESCALE_VALUES_R';
  mmPRESCALE_VALUES_G                                      :Result:='mmPRESCALE_VALUES_G';
  mmPRESCALE_VALUES_B                                      :Result:='mmPRESCALE_VALUES_B';
  mmCOL_MAN_OUTPUT_CSC_CONTROL                             :Result:='mmCOL_MAN_OUTPUT_CSC_CONTROL';
  mmOUTPUT_CSC_C11_C12_A                                   :Result:='mmOUTPUT_CSC_C11_C12_A';
  mmOUTPUT_CSC_C13_C14_A                                   :Result:='mmOUTPUT_CSC_C13_C14_A';
  mmOUTPUT_CSC_C21_C22_A                                   :Result:='mmOUTPUT_CSC_C21_C22_A';
  mmOUTPUT_CSC_C23_C24_A                                   :Result:='mmOUTPUT_CSC_C23_C24_A';
  mmOUTPUT_CSC_C31_C32_A                                   :Result:='mmOUTPUT_CSC_C31_C32_A';
  mmOUTPUT_CSC_C33_C34_A                                   :Result:='mmOUTPUT_CSC_C33_C34_A';
  mmOUTPUT_CSC_C11_C12_B                                   :Result:='mmOUTPUT_CSC_C11_C12_B';
  mmOUTPUT_CSC_C13_C14_B                                   :Result:='mmOUTPUT_CSC_C13_C14_B';
  mmOUTPUT_CSC_C21_C22_B                                   :Result:='mmOUTPUT_CSC_C21_C22_B';
  mmOUTPUT_CSC_C23_C24_B                                   :Result:='mmOUTPUT_CSC_C23_C24_B';
  mmOUTPUT_CSC_C31_C32_B                                   :Result:='mmOUTPUT_CSC_C31_C32_B';
  mmOUTPUT_CSC_C33_C34_B                                   :Result:='mmOUTPUT_CSC_C33_C34_B';
  mmDENORM_CLAMP_CONTROL                                   :Result:='mmDENORM_CLAMP_CONTROL';
  mmDENORM_CLAMP_RANGE_R_CR                                :Result:='mmDENORM_CLAMP_RANGE_R_CR';
  mmDENORM_CLAMP_RANGE_G_Y                                 :Result:='mmDENORM_CLAMP_RANGE_G_Y';
  mmDENORM_CLAMP_RANGE_B_CB                                :Result:='mmDENORM_CLAMP_RANGE_B_CB';
  mmCOL_MAN_FP_CONVERTED_FIELD                             :Result:='mmCOL_MAN_FP_CONVERTED_FIELD';
  mmGAMMA_CORR_CONTROL                                     :Result:='mmGAMMA_CORR_CONTROL';
  mmGAMMA_CORR_LUT_INDEX                                   :Result:='mmGAMMA_CORR_LUT_INDEX';
  mmGAMMA_CORR_LUT_DATA                                    :Result:='mmGAMMA_CORR_LUT_DATA';
  mmGAMMA_CORR_LUT_WRITE_EN_MASK                           :Result:='mmGAMMA_CORR_LUT_WRITE_EN_MASK';
  mmGAMMA_CORR_CNTLA_START_CNTL                            :Result:='mmGAMMA_CORR_CNTLA_START_CNTL';
  mmGAMMA_CORR_CNTLA_SLOPE_CNTL                            :Result:='mmGAMMA_CORR_CNTLA_SLOPE_CNTL';
  mmGAMMA_CORR_CNTLA_END_CNTL1                             :Result:='mmGAMMA_CORR_CNTLA_END_CNTL1';
  mmGAMMA_CORR_CNTLA_END_CNTL2                             :Result:='mmGAMMA_CORR_CNTLA_END_CNTL2';
  mmGAMMA_CORR_CNTLA_REGION_0_1                            :Result:='mmGAMMA_CORR_CNTLA_REGION_0_1';
  mmGAMMA_CORR_CNTLA_REGION_2_3                            :Result:='mmGAMMA_CORR_CNTLA_REGION_2_3';
  mmGAMMA_CORR_CNTLA_REGION_4_5                            :Result:='mmGAMMA_CORR_CNTLA_REGION_4_5';
  mmGAMMA_CORR_CNTLA_REGION_6_7                            :Result:='mmGAMMA_CORR_CNTLA_REGION_6_7';
  mmGAMMA_CORR_CNTLA_REGION_8_9                            :Result:='mmGAMMA_CORR_CNTLA_REGION_8_9';
  mmGAMMA_CORR_CNTLA_REGION_10_11                          :Result:='mmGAMMA_CORR_CNTLA_REGION_10_11';
  mmGAMMA_CORR_CNTLA_REGION_12_13                          :Result:='mmGAMMA_CORR_CNTLA_REGION_12_13';
  mmGAMMA_CORR_CNTLA_REGION_14_15                          :Result:='mmGAMMA_CORR_CNTLA_REGION_14_15';
  mmGAMMA_CORR_CNTLB_START_CNTL                            :Result:='mmGAMMA_CORR_CNTLB_START_CNTL';
  mmGAMMA_CORR_CNTLB_SLOPE_CNTL                            :Result:='mmGAMMA_CORR_CNTLB_SLOPE_CNTL';
  mmGAMMA_CORR_CNTLB_END_CNTL1                             :Result:='mmGAMMA_CORR_CNTLB_END_CNTL1';
  mmGAMMA_CORR_CNTLB_END_CNTL2                             :Result:='mmGAMMA_CORR_CNTLB_END_CNTL2';
  mmGAMMA_CORR_CNTLB_REGION_0_1                            :Result:='mmGAMMA_CORR_CNTLB_REGION_0_1';
  mmGAMMA_CORR_CNTLB_REGION_2_3                            :Result:='mmGAMMA_CORR_CNTLB_REGION_2_3';
  mmGAMMA_CORR_CNTLB_REGION_4_5                            :Result:='mmGAMMA_CORR_CNTLB_REGION_4_5';
  mmGAMMA_CORR_CNTLB_REGION_6_7                            :Result:='mmGAMMA_CORR_CNTLB_REGION_6_7';
  mmGAMMA_CORR_CNTLB_REGION_8_9                            :Result:='mmGAMMA_CORR_CNTLB_REGION_8_9';
  mmGAMMA_CORR_CNTLB_REGION_10_11                          :Result:='mmGAMMA_CORR_CNTLB_REGION_10_11';
  mmGAMMA_CORR_CNTLB_REGION_12_13                          :Result:='mmGAMMA_CORR_CNTLB_REGION_12_13';
  mmGAMMA_CORR_CNTLB_REGION_14_15                          :Result:='mmGAMMA_CORR_CNTLB_REGION_14_15';
  mmCOL_MAN_TEST_DEBUG_INDEX                               :Result:='mmCOL_MAN_TEST_DEBUG_INDEX';
  mmCOL_MAN_TEST_DEBUG_DATA                                :Result:='mmCOL_MAN_TEST_DEBUG_DATA';
  mmCOL_MAN_DEBUG_CONTROL                                  :Result:='mmCOL_MAN_DEBUG_CONTROL';
  mmDCFEV_CLOCK_CONTROL                                    :Result:='mmDCFEV_CLOCK_CONTROL';
  mmDCFEV_SOFT_RESET                                       :Result:='mmDCFEV_SOFT_RESET';
  mmDCFEV_DMIFV_CLOCK_CONTROL                              :Result:='mmDCFEV_DMIFV_CLOCK_CONTROL';
  mmDCFEV_DBG_CONFIG                                       :Result:='mmDCFEV_DBG_CONFIG';
  mmDCFEV_DMIFV_MEM_PWR_CTRL                               :Result:='mmDCFEV_DMIFV_MEM_PWR_CTRL';
  mmDCFEV_DMIFV_MEM_PWR_STATUS                             :Result:='mmDCFEV_DMIFV_MEM_PWR_STATUS';
  mmDC_PERFMON11_PERFCOUNTER_CNTL                          :Result:='mmDC_PERFMON11_PERFCOUNTER_CNTL';
  mmDC_PERFMON11_PERFCOUNTER_STATE                         :Result:='mmDC_PERFMON11_PERFCOUNTER_STATE';
  mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                   :Result:='mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC';
  mmDC_PERFMON11_PERFMON_CNTL                              :Result:='mmDC_PERFMON11_PERFMON_CNTL';
  mmDC_PERFMON11_PERFMON_CVALUE_LOW                        :Result:='mmDC_PERFMON11_PERFMON_CVALUE_LOW';
  mmDC_PERFMON11_PERFMON_HI                                :Result:='mmDC_PERFMON11_PERFMON_HI';
  mmDC_PERFMON11_PERFMON_LOW                               :Result:='mmDC_PERFMON11_PERFMON_LOW';
  mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX                  :Result:='mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX';
  mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA                   :Result:='mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA';
  mmDC_PERFMON11_PERFMON_CNTL2                             :Result:='mmDC_PERFMON11_PERFMON_CNTL2';
  mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1                 :Result:='mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1';
  mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2                 :Result:='mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2';
  mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL                    :Result:='mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL';
  mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL                      :Result:='mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL';
  mmDMIF_PG6_DPG_PIPE_DPM_CONTROL                          :Result:='mmDMIF_PG6_DPG_PIPE_DPM_CONTROL';
  mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL                      :Result:='mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL';
  mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             :Result:='mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL';
  mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             :Result:='mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH';
  mmDMIF_PG6_DPG_TEST_DEBUG_INDEX                          :Result:='mmDMIF_PG6_DPG_TEST_DEBUG_INDEX';
  mmDMIF_PG6_DPG_TEST_DEBUG_DATA                           :Result:='mmDMIF_PG6_DPG_TEST_DEBUG_DATA';
  mmDMIF_PG6_DPG_REPEATER_PROGRAM                          :Result:='mmDMIF_PG6_DPG_REPEATER_PROGRAM';
  mmDMIF_PG6_DPG_HW_DEBUG_A                                :Result:='mmDMIF_PG6_DPG_HW_DEBUG_A';
  mmDMIF_PG6_DPG_HW_DEBUG_B                                :Result:='mmDMIF_PG6_DPG_HW_DEBUG_B';
  mmDMIF_PG6_DPG_HW_DEBUG_11                               :Result:='mmDMIF_PG6_DPG_HW_DEBUG_11';
  mmBLND6_BLND_CONTROL                                     :Result:='mmBLND6_BLND_CONTROL';
  mmBLND6_SM_CONTROL2                                      :Result:='mmBLND6_SM_CONTROL2';
  mmBLND6_BLND_CONTROL2                                    :Result:='mmBLND6_BLND_CONTROL2';
  mmBLND6_BLND_UPDATE                                      :Result:='mmBLND6_BLND_UPDATE';
  mmBLND6_BLND_UNDERFLOW_INTERRUPT                         :Result:='mmBLND6_BLND_UNDERFLOW_INTERRUPT';
  mmBLND6_BLND_V_UPDATE_LOCK                               :Result:='mmBLND6_BLND_V_UPDATE_LOCK';
  mmBLND6_BLND_DEBUG                                       :Result:='mmBLND6_BLND_DEBUG';
  mmBLND6_BLND_TEST_DEBUG_INDEX                            :Result:='mmBLND6_BLND_TEST_DEBUG_INDEX';
  mmBLND6_BLND_TEST_DEBUG_DATA                             :Result:='mmBLND6_BLND_TEST_DEBUG_DATA';
  mmBLND6_BLND_REG_UPDATE_STATUS                           :Result:='mmBLND6_BLND_REG_UPDATE_STATUS';
  mmCRTC6_CRTC_3D_STRUCTURE_CONTROL                        :Result:='mmCRTC6_CRTC_3D_STRUCTURE_CONTROL';
  mmCRTC6_CRTC_GSL_VSYNC_GAP                               :Result:='mmCRTC6_CRTC_GSL_VSYNC_GAP';
  mmCRTC6_CRTC_GSL_WINDOW                                  :Result:='mmCRTC6_CRTC_GSL_WINDOW';
  mmCRTC6_CRTC_GSL_CONTROL                                 :Result:='mmCRTC6_CRTC_GSL_CONTROL';
  mmCRTC6_CRTC_DCFE_CLOCK_CONTROL                          :Result:='mmCRTC6_CRTC_DCFE_CLOCK_CONTROL';
  mmCRTC6_CRTC_H_BLANK_EARLY_NUM                           :Result:='mmCRTC6_CRTC_H_BLANK_EARLY_NUM';
  mmCRTC6_DCFE_DBG_SEL                                     :Result:='mmCRTC6_DCFE_DBG_SEL';
  mmCRTC6_DCFE_MEM_PWR_CTRL                                :Result:='mmCRTC6_DCFE_MEM_PWR_CTRL';
  mmCRTC6_CRTC_H_TOTAL                                     :Result:='mmCRTC6_CRTC_H_TOTAL';
  mmCRTC6_CRTC_H_BLANK_START_END                           :Result:='mmCRTC6_CRTC_H_BLANK_START_END';
  mmCRTC6_CRTC_H_SYNC_A                                    :Result:='mmCRTC6_CRTC_H_SYNC_A';
  mmCRTC6_CRTC_H_SYNC_A_CNTL                               :Result:='mmCRTC6_CRTC_H_SYNC_A_CNTL';
  mmCRTC6_CRTC_H_SYNC_B                                    :Result:='mmCRTC6_CRTC_H_SYNC_B';
  mmCRTC6_CRTC_H_SYNC_B_CNTL                               :Result:='mmCRTC6_CRTC_H_SYNC_B_CNTL';
  mmCRTC6_CRTC_VBI_END                                     :Result:='mmCRTC6_CRTC_VBI_END';
  mmCRTC6_CRTC_V_TOTAL                                     :Result:='mmCRTC6_CRTC_V_TOTAL';
  mmCRTC6_CRTC_V_TOTAL_MIN                                 :Result:='mmCRTC6_CRTC_V_TOTAL_MIN';
  mmCRTC6_CRTC_V_TOTAL_MAX                                 :Result:='mmCRTC6_CRTC_V_TOTAL_MAX';
  mmCRTC6_CRTC_V_TOTAL_CONTROL                             :Result:='mmCRTC6_CRTC_V_TOTAL_CONTROL';
  mmCRTC6_CRTC_V_TOTAL_INT_STATUS                          :Result:='mmCRTC6_CRTC_V_TOTAL_INT_STATUS';
  mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS                        :Result:='mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS';
  mmCRTC6_CRTC_V_BLANK_START_END                           :Result:='mmCRTC6_CRTC_V_BLANK_START_END';
  mmCRTC6_CRTC_V_SYNC_A                                    :Result:='mmCRTC6_CRTC_V_SYNC_A';
  mmCRTC6_CRTC_V_SYNC_A_CNTL                               :Result:='mmCRTC6_CRTC_V_SYNC_A_CNTL';
  mmCRTC6_CRTC_V_SYNC_B                                    :Result:='mmCRTC6_CRTC_V_SYNC_B';
  mmCRTC6_CRTC_V_SYNC_B_CNTL                               :Result:='mmCRTC6_CRTC_V_SYNC_B_CNTL';
  mmCRTC6_CRTC_DTMTEST_CNTL                                :Result:='mmCRTC6_CRTC_DTMTEST_CNTL';
  mmCRTC6_CRTC_DTMTEST_STATUS_POSITION                     :Result:='mmCRTC6_CRTC_DTMTEST_STATUS_POSITION';
  mmCRTC6_CRTC_TRIGA_CNTL                                  :Result:='mmCRTC6_CRTC_TRIGA_CNTL';
  mmCRTC6_CRTC_TRIGA_MANUAL_TRIG                           :Result:='mmCRTC6_CRTC_TRIGA_MANUAL_TRIG';
  mmCRTC6_CRTC_TRIGB_CNTL                                  :Result:='mmCRTC6_CRTC_TRIGB_CNTL';
  mmCRTC6_CRTC_TRIGB_MANUAL_TRIG                           :Result:='mmCRTC6_CRTC_TRIGB_MANUAL_TRIG';
  mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL                        :Result:='mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL';
  mmCRTC6_CRTC_FLOW_CONTROL                                :Result:='mmCRTC6_CRTC_FLOW_CONTROL';
  mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE                       :Result:='mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE';
  mmCRTC6_CRTC_AVSYNC_COUNTER                              :Result:='mmCRTC6_CRTC_AVSYNC_COUNTER';
  mmCRTC6_CRTC_CONTROL                                     :Result:='mmCRTC6_CRTC_CONTROL';
  mmCRTC6_CRTC_BLANK_CONTROL                               :Result:='mmCRTC6_CRTC_BLANK_CONTROL';
  mmCRTC6_CRTC_INTERLACE_CONTROL                           :Result:='mmCRTC6_CRTC_INTERLACE_CONTROL';
  mmCRTC6_CRTC_INTERLACE_STATUS                            :Result:='mmCRTC6_CRTC_INTERLACE_STATUS';
  mmCRTC6_CRTC_FIELD_INDICATION_CONTROL                    :Result:='mmCRTC6_CRTC_FIELD_INDICATION_CONTROL';
  mmCRTC6_CRTC_PIXEL_DATA_READBACK0                        :Result:='mmCRTC6_CRTC_PIXEL_DATA_READBACK0';
  mmCRTC6_CRTC_PIXEL_DATA_READBACK1                        :Result:='mmCRTC6_CRTC_PIXEL_DATA_READBACK1';
  mmCRTC6_CRTC_STATUS                                      :Result:='mmCRTC6_CRTC_STATUS';
  mmCRTC6_CRTC_STATUS_POSITION                             :Result:='mmCRTC6_CRTC_STATUS_POSITION';
  mmCRTC6_CRTC_NOM_VERT_POSITION                           :Result:='mmCRTC6_CRTC_NOM_VERT_POSITION';
  mmCRTC6_CRTC_STATUS_FRAME_COUNT                          :Result:='mmCRTC6_CRTC_STATUS_FRAME_COUNT';
  mmCRTC6_CRTC_STATUS_VF_COUNT                             :Result:='mmCRTC6_CRTC_STATUS_VF_COUNT';
  mmCRTC6_CRTC_STATUS_HV_COUNT                             :Result:='mmCRTC6_CRTC_STATUS_HV_COUNT';
  mmCRTC6_CRTC_COUNT_CONTROL                               :Result:='mmCRTC6_CRTC_COUNT_CONTROL';
  mmCRTC6_CRTC_COUNT_RESET                                 :Result:='mmCRTC6_CRTC_COUNT_RESET';
  mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                :Result:='mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE';
  mmCRTC6_CRTC_VERT_SYNC_CONTROL                           :Result:='mmCRTC6_CRTC_VERT_SYNC_CONTROL';
  mmCRTC6_CRTC_STEREO_STATUS                               :Result:='mmCRTC6_CRTC_STEREO_STATUS';
  mmCRTC6_CRTC_STEREO_CONTROL                              :Result:='mmCRTC6_CRTC_STEREO_CONTROL';
  mmCRTC6_CRTC_SNAPSHOT_STATUS                             :Result:='mmCRTC6_CRTC_SNAPSHOT_STATUS';
  mmCRTC6_CRTC_SNAPSHOT_CONTROL                            :Result:='mmCRTC6_CRTC_SNAPSHOT_CONTROL';
  mmCRTC6_CRTC_SNAPSHOT_POSITION                           :Result:='mmCRTC6_CRTC_SNAPSHOT_POSITION';
  mmCRTC6_CRTC_SNAPSHOT_FRAME                              :Result:='mmCRTC6_CRTC_SNAPSHOT_FRAME';
  mmCRTC6_CRTC_START_LINE_CONTROL                          :Result:='mmCRTC6_CRTC_START_LINE_CONTROL';
  mmCRTC6_CRTC_INTERRUPT_CONTROL                           :Result:='mmCRTC6_CRTC_INTERRUPT_CONTROL';
  mmCRTC6_CRTC_UPDATE_LOCK                                 :Result:='mmCRTC6_CRTC_UPDATE_LOCK';
  mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL                       :Result:='mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL';
  mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE                  :Result:='mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE';
  mmCRTC6_DCFE_MEM_PWR_CTRL2                               :Result:='mmCRTC6_DCFE_MEM_PWR_CTRL2';
  mmCRTC6_DCFE_MEM_PWR_STATUS                              :Result:='mmCRTC6_DCFE_MEM_PWR_STATUS';
  mmCRTC6_CRTC_TEST_PATTERN_CONTROL                        :Result:='mmCRTC6_CRTC_TEST_PATTERN_CONTROL';
  mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS                     :Result:='mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS';
  mmCRTC6_CRTC_TEST_PATTERN_COLOR                          :Result:='mmCRTC6_CRTC_TEST_PATTERN_COLOR';
  mmCRTC6_MASTER_UPDATE_LOCK                               :Result:='mmCRTC6_MASTER_UPDATE_LOCK';
  mmCRTC6_MASTER_UPDATE_MODE                               :Result:='mmCRTC6_MASTER_UPDATE_MODE';
  mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT                      :Result:='mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT';
  mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                :Result:='mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER';
  mmCRTC6_CRTC_MVP_STATUS                                  :Result:='mmCRTC6_CRTC_MVP_STATUS';
  mmCRTC6_CRTC_MASTER_EN                                   :Result:='mmCRTC6_CRTC_MASTER_EN';
  mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT                        :Result:='mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT';
  mmCRTC6_CRTC_V_UPDATE_INT_STATUS                         :Result:='mmCRTC6_CRTC_V_UPDATE_INT_STATUS';
  mmCRTC6_CRTC_TEST_DEBUG_INDEX                            :Result:='mmCRTC6_CRTC_TEST_DEBUG_INDEX';
  mmCRTC6_CRTC_TEST_DEBUG_DATA                             :Result:='mmCRTC6_CRTC_TEST_DEBUG_DATA';
  mmCRTC6_CRTC_OVERSCAN_COLOR                              :Result:='mmCRTC6_CRTC_OVERSCAN_COLOR';
  mmCRTC6_CRTC_OVERSCAN_COLOR_EXT                          :Result:='mmCRTC6_CRTC_OVERSCAN_COLOR_EXT';
  mmCRTC6_CRTC_BLANK_DATA_COLOR                            :Result:='mmCRTC6_CRTC_BLANK_DATA_COLOR';
  mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT                        :Result:='mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT';
  mmCRTC6_CRTC_BLACK_COLOR                                 :Result:='mmCRTC6_CRTC_BLACK_COLOR';
  mmCRTC6_CRTC_BLACK_COLOR_EXT                             :Result:='mmCRTC6_CRTC_BLACK_COLOR_EXT';
  mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION                :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION';
  mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL                 :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL';
  mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION                :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION';
  mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL                 :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL';
  mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION                :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION';
  mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL                 :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL';
  mmCRTC6_CRTC_CRC_CNTL                                    :Result:='mmCRTC6_CRTC_CRC_CNTL';
  mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL                      :Result:='mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL';
  mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL                      :Result:='mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL';
  mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL                      :Result:='mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL';
  mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL                      :Result:='mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL';
  mmCRTC6_CRTC_CRC0_DATA_RG                                :Result:='mmCRTC6_CRTC_CRC0_DATA_RG';
  mmCRTC6_CRTC_CRC0_DATA_B                                 :Result:='mmCRTC6_CRTC_CRC0_DATA_B';
  mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL                      :Result:='mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL';
  mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL                      :Result:='mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL';
  mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL                      :Result:='mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL';
  mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL                      :Result:='mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL';
  mmCRTC6_CRTC_CRC1_DATA_RG                                :Result:='mmCRTC6_CRTC_CRC1_DATA_RG';
  mmCRTC6_CRTC_CRC1_DATA_B                                 :Result:='mmCRTC6_CRTC_CRC1_DATA_B';
  mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL                     :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL';
  mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START                :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START';
  mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END                  :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END';
  mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL';
  mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL';
  mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL';
  mmCRTC6_CRTC_STATIC_SCREEN_CONTROL                       :Result:='mmCRTC6_CRTC_STATIC_SCREEN_CONTROL';
  mmDC_GENERICA                                            :Result:='mmDC_GENERICA';
  mmDC_GENERICB                                            :Result:='mmDC_GENERICB';
  mmDC_PAD_EXTERN_SIG                                      :Result:='mmDC_PAD_EXTERN_SIG';
  mmDC_REF_CLK_CNTL                                        :Result:='mmDC_REF_CLK_CNTL';
  mmDC_GPIO_DEBUG                                          :Result:='mmDC_GPIO_DEBUG';
  mmUNIPHYA_LINK_CNTL                                      :Result:='mmUNIPHYA_LINK_CNTL';
  mmUNIPHYA_CHANNEL_XBAR_CNTL                              :Result:='mmUNIPHYA_CHANNEL_XBAR_CNTL';
  mmUNIPHYB_LINK_CNTL                                      :Result:='mmUNIPHYB_LINK_CNTL';
  mmUNIPHYB_CHANNEL_XBAR_CNTL                              :Result:='mmUNIPHYB_CHANNEL_XBAR_CNTL';
  mmUNIPHYC_LINK_CNTL                                      :Result:='mmUNIPHYC_LINK_CNTL';
  mmUNIPHYC_CHANNEL_XBAR_CNTL                              :Result:='mmUNIPHYC_CHANNEL_XBAR_CNTL';
  mmUNIPHYD_LINK_CNTL                                      :Result:='mmUNIPHYD_LINK_CNTL';
  mmUNIPHYD_CHANNEL_XBAR_CNTL                              :Result:='mmUNIPHYD_CHANNEL_XBAR_CNTL';
  mmUNIPHYE_LINK_CNTL                                      :Result:='mmUNIPHYE_LINK_CNTL';
  mmUNIPHYE_CHANNEL_XBAR_CNTL                              :Result:='mmUNIPHYE_CHANNEL_XBAR_CNTL';
  mmUNIPHYF_LINK_CNTL                                      :Result:='mmUNIPHYF_LINK_CNTL';
  mmUNIPHYF_CHANNEL_XBAR_CNTL                              :Result:='mmUNIPHYF_CHANNEL_XBAR_CNTL';
  mmUNIPHYG_LINK_CNTL                                      :Result:='mmUNIPHYG_LINK_CNTL';
  mmUNIPHYG_CHANNEL_XBAR_CNTL                              :Result:='mmUNIPHYG_CHANNEL_XBAR_CNTL';
  mmDIG4_HDMI_GENERIC_PACKET_CONTROL                       :Result:='mmDIG4_HDMI_GENERIC_PACKET_CONTROL';
  mmDCIO_WRCMD_DELAY                                       :Result:='mmDCIO_WRCMD_DELAY';
  mmDC_PINSTRAPS                                           :Result:='mmDC_PINSTRAPS';
  mmDC_DVODATA_CONFIG                                      :Result:='mmDC_DVODATA_CONFIG';
  mmLVTMA_PWRSEQ_CNTL                                      :Result:='mmLVTMA_PWRSEQ_CNTL';
  mmLVTMA_PWRSEQ_STATE                                     :Result:='mmLVTMA_PWRSEQ_STATE';
  mmLVTMA_PWRSEQ_REF_DIV                                   :Result:='mmLVTMA_PWRSEQ_REF_DIV';
  mmLVTMA_PWRSEQ_DELAY1                                    :Result:='mmLVTMA_PWRSEQ_DELAY1';
  mmLVTMA_PWRSEQ_DELAY2                                    :Result:='mmLVTMA_PWRSEQ_DELAY2';
  mmBL_PWM_CNTL                                            :Result:='mmBL_PWM_CNTL';
  mmBL_PWM_CNTL2                                           :Result:='mmBL_PWM_CNTL2';
  mmBL_PWM_PERIOD_CNTL                                     :Result:='mmBL_PWM_PERIOD_CNTL';
  mmBL_PWM_GRP1_REG_LOCK                                   :Result:='mmBL_PWM_GRP1_REG_LOCK';
  mmDCIO_GSL_GENLK_PAD_CNTL                                :Result:='mmDCIO_GSL_GENLK_PAD_CNTL';
  mmDCIO_GSL_SWAPLOCK_PAD_CNTL                             :Result:='mmDCIO_GSL_SWAPLOCK_PAD_CNTL';
  mmDCIO_GSL0_CNTL                                         :Result:='mmDCIO_GSL0_CNTL';
  mmDCIO_GSL1_CNTL                                         :Result:='mmDCIO_GSL1_CNTL';
  mmDCIO_GSL2_CNTL                                         :Result:='mmDCIO_GSL2_CNTL';
  mmDC_GPU_TIMER_START_POSITION_V_UPDATE                   :Result:='mmDC_GPU_TIMER_START_POSITION_V_UPDATE';
  mmDC_GPU_TIMER_START_POSITION_P_FLIP                     :Result:='mmDC_GPU_TIMER_START_POSITION_P_FLIP';
  mmDC_GPU_TIMER_READ                                      :Result:='mmDC_GPU_TIMER_READ';
  mmDC_GPU_TIMER_READ_CNTL                                 :Result:='mmDC_GPU_TIMER_READ_CNTL';
  mmDCIO_CLOCK_CNTL                                        :Result:='mmDCIO_CLOCK_CNTL';
  mmDCIO_DEBUG                                             :Result:='mmDCIO_DEBUG';
  mmDCO_DCFE_EXT_VSYNC_CNTL                                :Result:='mmDCO_DCFE_EXT_VSYNC_CNTL';
  mmDCIO_TEST_DEBUG_INDEX                                  :Result:='mmDCIO_TEST_DEBUG_INDEX';
  mmDCIO_TEST_DEBUG_DATA                                   :Result:='mmDCIO_TEST_DEBUG_DATA';
  mmDBG_OUT_CNTL                                           :Result:='mmDBG_OUT_CNTL';
  mmDCIO_DEBUG_CONFIG                                      :Result:='mmDCIO_DEBUG_CONFIG';
  mmDCIO_SOFT_RESET                                        :Result:='mmDCIO_SOFT_RESET';
  mmDCIO_DPHY_SEL                                          :Result:='mmDCIO_DPHY_SEL';
  mmUNIPHY_IMPCAL_LINKA                                    :Result:='mmUNIPHY_IMPCAL_LINKA';
  mmUNIPHY_IMPCAL_LINKB                                    :Result:='mmUNIPHY_IMPCAL_LINKB';
  mmUNIPHY_IMPCAL_PERIOD                                   :Result:='mmUNIPHY_IMPCAL_PERIOD';
  mmAUXP_IMPCAL                                            :Result:='mmAUXP_IMPCAL';
  mmAUXN_IMPCAL                                            :Result:='mmAUXN_IMPCAL';
  mmDCIO_IMPCAL_CNTL                                       :Result:='mmDCIO_IMPCAL_CNTL';
  mmUNIPHY_IMPCAL_PSW_AB                                   :Result:='mmUNIPHY_IMPCAL_PSW_AB';
  mmUNIPHY_IMPCAL_LINKC                                    :Result:='mmUNIPHY_IMPCAL_LINKC';
  mmUNIPHY_IMPCAL_LINKD                                    :Result:='mmUNIPHY_IMPCAL_LINKD';
  mmDCIO_IMPCAL_CNTL_CD                                    :Result:='mmDCIO_IMPCAL_CNTL_CD';
  mmUNIPHY_IMPCAL_PSW_CD                                   :Result:='mmUNIPHY_IMPCAL_PSW_CD';
  mmUNIPHY_IMPCAL_LINKE                                    :Result:='mmUNIPHY_IMPCAL_LINKE';
  mmUNIPHY_IMPCAL_LINKF                                    :Result:='mmUNIPHY_IMPCAL_LINKF';
  mmDCIO_IMPCAL_CNTL_EF                                    :Result:='mmDCIO_IMPCAL_CNTL_EF';
  mmUNIPHY_IMPCAL_PSW_EF                                   :Result:='mmUNIPHY_IMPCAL_PSW_EF';
  mmDC_GPIO_GENERIC_MASK                                   :Result:='mmDC_GPIO_GENERIC_MASK';
  mmDC_GPIO_GENERIC_A                                      :Result:='mmDC_GPIO_GENERIC_A';
  mmDC_GPIO_GENERIC_EN                                     :Result:='mmDC_GPIO_GENERIC_EN';
  mmDC_GPIO_GENERIC_Y                                      :Result:='mmDC_GPIO_GENERIC_Y';
  mmDC_GPIO_DVODATA_MASK                                   :Result:='mmDC_GPIO_DVODATA_MASK';
  mmDC_GPIO_DVODATA_A                                      :Result:='mmDC_GPIO_DVODATA_A';
  mmDC_GPIO_DVODATA_EN                                     :Result:='mmDC_GPIO_DVODATA_EN';
  mmDC_GPIO_DVODATA_Y                                      :Result:='mmDC_GPIO_DVODATA_Y';
  mmDC_GPIO_DDC1_MASK                                      :Result:='mmDC_GPIO_DDC1_MASK';
  mmDC_GPIO_DDC1_A                                         :Result:='mmDC_GPIO_DDC1_A';
  mmDC_GPIO_DDC1_EN                                        :Result:='mmDC_GPIO_DDC1_EN';
  mmDC_GPIO_DDC1_Y                                         :Result:='mmDC_GPIO_DDC1_Y';
  mmDC_GPIO_DDC2_MASK                                      :Result:='mmDC_GPIO_DDC2_MASK';
  mmDC_GPIO_DDC2_A                                         :Result:='mmDC_GPIO_DDC2_A';
  mmDC_GPIO_DDC2_EN                                        :Result:='mmDC_GPIO_DDC2_EN';
  mmDC_GPIO_DDC2_Y                                         :Result:='mmDC_GPIO_DDC2_Y';
  mmDC_GPIO_DDC3_MASK                                      :Result:='mmDC_GPIO_DDC3_MASK';
  mmDC_GPIO_DDC3_A                                         :Result:='mmDC_GPIO_DDC3_A';
  mmDC_GPIO_DDC3_EN                                        :Result:='mmDC_GPIO_DDC3_EN';
  mmDC_GPIO_DDC3_Y                                         :Result:='mmDC_GPIO_DDC3_Y';
  mmDC_GPIO_DDC4_MASK                                      :Result:='mmDC_GPIO_DDC4_MASK';
  mmDC_GPIO_DDC4_A                                         :Result:='mmDC_GPIO_DDC4_A';
  mmDC_GPIO_DDC4_EN                                        :Result:='mmDC_GPIO_DDC4_EN';
  mmDC_GPIO_DDC4_Y                                         :Result:='mmDC_GPIO_DDC4_Y';
  mmDC_GPIO_DDC5_MASK                                      :Result:='mmDC_GPIO_DDC5_MASK';
  mmDC_GPIO_DDC5_A                                         :Result:='mmDC_GPIO_DDC5_A';
  mmDC_GPIO_DDC5_EN                                        :Result:='mmDC_GPIO_DDC5_EN';
  mmDC_GPIO_DDC5_Y                                         :Result:='mmDC_GPIO_DDC5_Y';
  mmDC_GPIO_DDC6_MASK                                      :Result:='mmDC_GPIO_DDC6_MASK';
  mmDC_GPIO_DDC6_A                                         :Result:='mmDC_GPIO_DDC6_A';
  mmDC_GPIO_DDC6_EN                                        :Result:='mmDC_GPIO_DDC6_EN';
  mmDC_GPIO_DDC6_Y                                         :Result:='mmDC_GPIO_DDC6_Y';
  mmDC_GPIO_DDCVGA_MASK                                    :Result:='mmDC_GPIO_DDCVGA_MASK';
  mmDC_GPIO_DDCVGA_A                                       :Result:='mmDC_GPIO_DDCVGA_A';
  mmDC_GPIO_DDCVGA_EN                                      :Result:='mmDC_GPIO_DDCVGA_EN';
  mmDC_GPIO_DDCVGA_Y                                       :Result:='mmDC_GPIO_DDCVGA_Y';
  mmDC_GPIO_SYNCA_MASK                                     :Result:='mmDC_GPIO_SYNCA_MASK';
  mmDC_GPIO_SYNCA_A                                        :Result:='mmDC_GPIO_SYNCA_A';
  mmDC_GPIO_SYNCA_EN                                       :Result:='mmDC_GPIO_SYNCA_EN';
  mmDC_GPIO_SYNCA_Y                                        :Result:='mmDC_GPIO_SYNCA_Y';
  mmDC_GPIO_GENLK_MASK                                     :Result:='mmDC_GPIO_GENLK_MASK';
  mmDC_GPIO_GENLK_A                                        :Result:='mmDC_GPIO_GENLK_A';
  mmDC_GPIO_GENLK_EN                                       :Result:='mmDC_GPIO_GENLK_EN';
  mmDC_GPIO_GENLK_Y                                        :Result:='mmDC_GPIO_GENLK_Y';
  mmDC_GPIO_HPD_MASK                                       :Result:='mmDC_GPIO_HPD_MASK';
  mmDC_GPIO_HPD_A                                          :Result:='mmDC_GPIO_HPD_A';
  mmDC_GPIO_HPD_EN                                         :Result:='mmDC_GPIO_HPD_EN';
  mmDC_GPIO_HPD_Y                                          :Result:='mmDC_GPIO_HPD_Y';
  mmDC_GPIO_PWRSEQ_MASK                                    :Result:='mmDC_GPIO_PWRSEQ_MASK';
  mmDC_GPIO_PWRSEQ_A                                       :Result:='mmDC_GPIO_PWRSEQ_A';
  mmDC_GPIO_PWRSEQ_EN                                      :Result:='mmDC_GPIO_PWRSEQ_EN';
  mmDC_GPIO_PWRSEQ_Y                                       :Result:='mmDC_GPIO_PWRSEQ_Y';
  mmDC_GPIO_PAD_STRENGTH_1                                 :Result:='mmDC_GPIO_PAD_STRENGTH_1';
  mmDC_GPIO_PAD_STRENGTH_2                                 :Result:='mmDC_GPIO_PAD_STRENGTH_2';
  mmPHY_AUX_CNTL                                           :Result:='mmPHY_AUX_CNTL';
  mmDC_GPIO_I2CPAD_MASK                                    :Result:='mmDC_GPIO_I2CPAD_MASK';
  mmDC_GPIO_I2CPAD_A                                       :Result:='mmDC_GPIO_I2CPAD_A';
  mmDC_GPIO_I2CPAD_EN                                      :Result:='mmDC_GPIO_I2CPAD_EN';
  mmDC_GPIO_I2CPAD_Y                                       :Result:='mmDC_GPIO_I2CPAD_Y';
  mmDC_GPIO_I2CPAD_STRENGTH                                :Result:='mmDC_GPIO_I2CPAD_STRENGTH';
  mmDVO_STRENGTH_CONTROL                                   :Result:='mmDVO_STRENGTH_CONTROL';
  mmDVO_VREF_CONTROL                                       :Result:='mmDVO_VREF_CONTROL';
  mmDVO_SKEW_ADJUST                                        :Result:='mmDVO_SKEW_ADJUST';
  mmDAC_MACRO_CNTL_RESERVED0                               :Result:='mmDAC_MACRO_CNTL_RESERVED0';
  mmBPHYC_DAC_MACRO_CNTL                                   :Result:='mmBPHYC_DAC_MACRO_CNTL';
  mmBPHYC_DAC_AUTO_CALIB_CONTROL                           :Result:='mmBPHYC_DAC_AUTO_CALIB_CONTROL';
  mmDAC_MACRO_CNTL_RESERVED3                               :Result:='mmDAC_MACRO_CNTL_RESERVED3';
  mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1                       :Result:='mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1';
  mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2                       :Result:='mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2';
  mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3                       :Result:='mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3';
  mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4                       :Result:='mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4';
  mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL                     :Result:='mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL';
  mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV                         :Result:='mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV';
  mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1                      :Result:='mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1';
  mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2                      :Result:='mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2';
  mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE                  :Result:='mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE';
  mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL                       :Result:='mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL';
  mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION              :Result:='mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION';
  mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT                   :Result:='mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT';
  mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL                     :Result:='mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL';
  mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2                  :Result:='mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19';
  mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL                       :Result:='mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL';
  mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED                          :Result:='mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED';
  mmBPHYC_UNIPHY0_UNIPHY_DEBUG                             :Result:='mmBPHYC_UNIPHY0_UNIPHY_DEBUG';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30';
  mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31              :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31';
  mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1                       :Result:='mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1';
  mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2                       :Result:='mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2';
  mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3                       :Result:='mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3';
  mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4                       :Result:='mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4';
  mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL                     :Result:='mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL';
  mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV                         :Result:='mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV';
  mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1                      :Result:='mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1';
  mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2                      :Result:='mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2';
  mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE                  :Result:='mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE';
  mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL                       :Result:='mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL';
  mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION              :Result:='mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION';
  mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT                   :Result:='mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT';
  mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL                     :Result:='mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL';
  mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2                  :Result:='mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19';
  mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL                       :Result:='mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL';
  mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED                          :Result:='mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED';
  mmBPHYC_UNIPHY1_UNIPHY_DEBUG                             :Result:='mmBPHYC_UNIPHY1_UNIPHY_DEBUG';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30';
  mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31              :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31';
  mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1                       :Result:='mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1';
  mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2                       :Result:='mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2';
  mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3                       :Result:='mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3';
  mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4                       :Result:='mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4';
  mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL                     :Result:='mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL';
  mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV                         :Result:='mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV';
  mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1                      :Result:='mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1';
  mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2                      :Result:='mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2';
  mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE                  :Result:='mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE';
  mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL                       :Result:='mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL';
  mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION              :Result:='mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION';
  mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT                   :Result:='mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT';
  mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL                     :Result:='mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL';
  mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2                  :Result:='mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19';
  mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL                       :Result:='mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL';
  mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED                          :Result:='mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED';
  mmBPHYC_UNIPHY2_UNIPHY_DEBUG                             :Result:='mmBPHYC_UNIPHY2_UNIPHY_DEBUG';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30';
  mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31              :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31';
  mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1                       :Result:='mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1';
  mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2                       :Result:='mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2';
  mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3                       :Result:='mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3';
  mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4                       :Result:='mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4';
  mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL                     :Result:='mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL';
  mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV                         :Result:='mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV';
  mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1                      :Result:='mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1';
  mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2                      :Result:='mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2';
  mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE                  :Result:='mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE';
  mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL                       :Result:='mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL';
  mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION              :Result:='mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION';
  mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT                   :Result:='mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT';
  mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL                     :Result:='mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL';
  mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2                  :Result:='mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19';
  mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL                       :Result:='mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL';
  mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED                          :Result:='mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED';
  mmBPHYC_UNIPHY3_UNIPHY_DEBUG                             :Result:='mmBPHYC_UNIPHY3_UNIPHY_DEBUG';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30';
  mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31              :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31';
  mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1                       :Result:='mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1';
  mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2                       :Result:='mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2';
  mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3                       :Result:='mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3';
  mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4                       :Result:='mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4';
  mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL                     :Result:='mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL';
  mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV                         :Result:='mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV';
  mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1                      :Result:='mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1';
  mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2                      :Result:='mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2';
  mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE                  :Result:='mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE';
  mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL                       :Result:='mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL';
  mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION              :Result:='mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION';
  mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT                   :Result:='mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT';
  mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL                     :Result:='mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL';
  mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2                  :Result:='mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19';
  mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL                       :Result:='mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL';
  mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED                          :Result:='mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED';
  mmBPHYC_UNIPHY4_UNIPHY_DEBUG                             :Result:='mmBPHYC_UNIPHY4_UNIPHY_DEBUG';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30';
  mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31              :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31';
  mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1                       :Result:='mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1';
  mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2                       :Result:='mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2';
  mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3                       :Result:='mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3';
  mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4                       :Result:='mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4';
  mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL                     :Result:='mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL';
  mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV                         :Result:='mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV';
  mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1                      :Result:='mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1';
  mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2                      :Result:='mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2';
  mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE                  :Result:='mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE';
  mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL                       :Result:='mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL';
  mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION              :Result:='mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION';
  mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT                   :Result:='mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT';
  mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL                     :Result:='mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL';
  mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2                  :Result:='mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19';
  mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL                       :Result:='mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL';
  mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED                          :Result:='mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED';
  mmBPHYC_UNIPHY5_UNIPHY_DEBUG                             :Result:='mmBPHYC_UNIPHY5_UNIPHY_DEBUG';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30';
  mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31              :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31';
  mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1                       :Result:='mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1';
  mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2                       :Result:='mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2';
  mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3                       :Result:='mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3';
  mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4                       :Result:='mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4';
  mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL                     :Result:='mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL';
  mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV                         :Result:='mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV';
  mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1                      :Result:='mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1';
  mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2                      :Result:='mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2';
  mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE                  :Result:='mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE';
  mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL                       :Result:='mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL';
  mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION              :Result:='mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION';
  mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT                   :Result:='mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT';
  mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL                     :Result:='mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL';
  mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2                  :Result:='mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19';
  mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL                       :Result:='mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL';
  mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED                          :Result:='mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED';
  mmBPHYC_UNIPHY6_UNIPHY_DEBUG                             :Result:='mmBPHYC_UNIPHY6_UNIPHY_DEBUG';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30';
  mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31              :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31';
  mmDIG0_DIG_FE_CNTL                                       :Result:='mmDIG0_DIG_FE_CNTL';
  mmDIG0_DIG_OUTPUT_CRC_CNTL                               :Result:='mmDIG0_DIG_OUTPUT_CRC_CNTL';
  mmDIG0_DIG_OUTPUT_CRC_RESULT                             :Result:='mmDIG0_DIG_OUTPUT_CRC_RESULT';
  mmDIG0_DIG_CLOCK_PATTERN                                 :Result:='mmDIG0_DIG_CLOCK_PATTERN';
  mmDIG0_DIG_TEST_PATTERN                                  :Result:='mmDIG0_DIG_TEST_PATTERN';
  mmDIG0_DIG_RANDOM_PATTERN_SEED                           :Result:='mmDIG0_DIG_RANDOM_PATTERN_SEED';
  mmDIG0_DIG_FIFO_STATUS                                   :Result:='mmDIG0_DIG_FIFO_STATUS';
  mmDIG0_DIG_DISPCLK_SWITCH_CNTL                           :Result:='mmDIG0_DIG_DISPCLK_SWITCH_CNTL';
  mmDIG0_DIG_DISPCLK_SWITCH_STATUS                         :Result:='mmDIG0_DIG_DISPCLK_SWITCH_STATUS';
  mmDIG0_HDMI_CONTROL                                      :Result:='mmDIG0_HDMI_CONTROL';
  mmDIG0_HDMI_STATUS                                       :Result:='mmDIG0_HDMI_STATUS';
  mmDIG0_HDMI_AUDIO_PACKET_CONTROL                         :Result:='mmDIG0_HDMI_AUDIO_PACKET_CONTROL';
  mmDIG0_HDMI_ACR_PACKET_CONTROL                           :Result:='mmDIG0_HDMI_ACR_PACKET_CONTROL';
  mmDIG0_HDMI_VBI_PACKET_CONTROL                           :Result:='mmDIG0_HDMI_VBI_PACKET_CONTROL';
  mmDIG0_HDMI_INFOFRAME_CONTROL0                           :Result:='mmDIG0_HDMI_INFOFRAME_CONTROL0';
  mmDIG0_HDMI_INFOFRAME_CONTROL1                           :Result:='mmDIG0_HDMI_INFOFRAME_CONTROL1';
  mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                      :Result:='mmDIG0_HDMI_GENERIC_PACKET_CONTROL0';
  mmDIG0_HDMI_GC                                           :Result:='mmDIG0_HDMI_GC';
  mmAFMT_AUDIO_PACKET_CONTROL2                             :Result:='mmAFMT_AUDIO_PACKET_CONTROL2';
  mmAFMT_ISRC1_0                                           :Result:='mmAFMT_ISRC1_0';
  mmAFMT_ISRC1_1                                           :Result:='mmAFMT_ISRC1_1';
  mmAFMT_ISRC1_2                                           :Result:='mmAFMT_ISRC1_2';
  mmAFMT_ISRC1_3                                           :Result:='mmAFMT_ISRC1_3';
  mmAFMT_ISRC1_4                                           :Result:='mmAFMT_ISRC1_4';
  mmAFMT_ISRC2_0                                           :Result:='mmAFMT_ISRC2_0';
  mmAFMT_ISRC2_1                                           :Result:='mmAFMT_ISRC2_1';
  mmAFMT_ISRC2_2                                           :Result:='mmAFMT_ISRC2_2';
  mmAFMT_ISRC2_3                                           :Result:='mmAFMT_ISRC2_3';
  mmAFMT_AVI_INFO0                                         :Result:='mmAFMT_AVI_INFO0';
  mmAFMT_AVI_INFO1                                         :Result:='mmAFMT_AVI_INFO1';
  mmAFMT_AVI_INFO2                                         :Result:='mmAFMT_AVI_INFO2';
  mmAFMT_AVI_INFO3                                         :Result:='mmAFMT_AVI_INFO3';
  mmAFMT_MPEG_INFO0                                        :Result:='mmAFMT_MPEG_INFO0';
  mmAFMT_MPEG_INFO1                                        :Result:='mmAFMT_MPEG_INFO1';
  mmAFMT_GENERIC_HDR                                       :Result:='mmAFMT_GENERIC_HDR';
  mmAFMT_GENERIC_0                                         :Result:='mmAFMT_GENERIC_0';
  mmAFMT_GENERIC_1                                         :Result:='mmAFMT_GENERIC_1';
  mmAFMT_GENERIC_2                                         :Result:='mmAFMT_GENERIC_2';
  mmAFMT_GENERIC_3                                         :Result:='mmAFMT_GENERIC_3';
  mmAFMT_GENERIC_4                                         :Result:='mmAFMT_GENERIC_4';
  mmAFMT_GENERIC_5                                         :Result:='mmAFMT_GENERIC_5';
  mmAFMT_GENERIC_6                                         :Result:='mmAFMT_GENERIC_6';
  mmAFMT_GENERIC_7                                         :Result:='mmAFMT_GENERIC_7';
  mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                      :Result:='mmDIG0_HDMI_GENERIC_PACKET_CONTROL1';
  mmDIG0_HDMI_ACR_32_0                                     :Result:='mmDIG0_HDMI_ACR_32_0';
  mmDIG0_HDMI_ACR_32_1                                     :Result:='mmDIG0_HDMI_ACR_32_1';
  mmDIG0_HDMI_ACR_44_0                                     :Result:='mmDIG0_HDMI_ACR_44_0';
  mmDIG0_HDMI_ACR_44_1                                     :Result:='mmDIG0_HDMI_ACR_44_1';
  mmDIG0_HDMI_ACR_48_0                                     :Result:='mmDIG0_HDMI_ACR_48_0';
  mmDIG0_HDMI_ACR_48_1                                     :Result:='mmDIG0_HDMI_ACR_48_1';
  mmDIG0_HDMI_ACR_STATUS_0                                 :Result:='mmDIG0_HDMI_ACR_STATUS_0';
  mmDIG0_HDMI_ACR_STATUS_1                                 :Result:='mmDIG0_HDMI_ACR_STATUS_1';
  mmAFMT_AUDIO_INFO0                                       :Result:='mmAFMT_AUDIO_INFO0';
  mmAFMT_AUDIO_INFO1                                       :Result:='mmAFMT_AUDIO_INFO1';
  mmAFMT_60958_0                                           :Result:='mmAFMT_60958_0';
  mmAFMT_60958_1                                           :Result:='mmAFMT_60958_1';
  mmAFMT_AUDIO_CRC_CONTROL                                 :Result:='mmAFMT_AUDIO_CRC_CONTROL';
  mmAFMT_RAMP_CONTROL0                                     :Result:='mmAFMT_RAMP_CONTROL0';
  mmAFMT_RAMP_CONTROL1                                     :Result:='mmAFMT_RAMP_CONTROL1';
  mmAFMT_RAMP_CONTROL2                                     :Result:='mmAFMT_RAMP_CONTROL2';
  mmAFMT_RAMP_CONTROL3                                     :Result:='mmAFMT_RAMP_CONTROL3';
  mmAFMT_60958_2                                           :Result:='mmAFMT_60958_2';
  mmAFMT_AUDIO_CRC_RESULT                                  :Result:='mmAFMT_AUDIO_CRC_RESULT';
  mmAFMT_STATUS                                            :Result:='mmAFMT_STATUS';
  mmAFMT_AUDIO_PACKET_CONTROL                              :Result:='mmAFMT_AUDIO_PACKET_CONTROL';
  mmAFMT_VBI_PACKET_CONTROL                                :Result:='mmAFMT_VBI_PACKET_CONTROL';
  mmAFMT_INFOFRAME_CONTROL0                                :Result:='mmAFMT_INFOFRAME_CONTROL0';
  mmAFMT_AUDIO_SRC_CONTROL                                 :Result:='mmAFMT_AUDIO_SRC_CONTROL';
  mmAFMT_AUDIO_DBG_DTO_CNTL                                :Result:='mmAFMT_AUDIO_DBG_DTO_CNTL';
  mmDIG0_DIG_BE_CNTL                                       :Result:='mmDIG0_DIG_BE_CNTL';
  mmDIG0_DIG_BE_EN_CNTL                                    :Result:='mmDIG0_DIG_BE_EN_CNTL';
  mmDIG0_TMDS_CNTL                                         :Result:='mmDIG0_TMDS_CNTL';
  mmDIG0_TMDS_CONTROL_CHAR                                 :Result:='mmDIG0_TMDS_CONTROL_CHAR';
  mmDIG0_TMDS_CONTROL0_FEEDBACK                            :Result:='mmDIG0_TMDS_CONTROL0_FEEDBACK';
  mmDIG0_TMDS_STEREOSYNC_CTL_SEL                           :Result:='mmDIG0_TMDS_STEREOSYNC_CTL_SEL';
  mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                        :Result:='mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1';
  mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                        :Result:='mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3';
  mmDIG0_TMDS_DEBUG                                        :Result:='mmDIG0_TMDS_DEBUG';
  mmDIG0_TMDS_CTL_BITS                                     :Result:='mmDIG0_TMDS_CTL_BITS';
  mmDIG0_TMDS_DCBALANCER_CONTROL                           :Result:='mmDIG0_TMDS_DCBALANCER_CONTROL';
  mmDIG0_TMDS_CTL0_1_GEN_CNTL                              :Result:='mmDIG0_TMDS_CTL0_1_GEN_CNTL';
  mmDIG0_TMDS_CTL2_3_GEN_CNTL                              :Result:='mmDIG0_TMDS_CTL2_3_GEN_CNTL';
  mmDIG0_LVDS_DATA_CNTL                                    :Result:='mmDIG0_LVDS_DATA_CNTL';
  mmDIG0_DIG_LANE_ENABLE                                   :Result:='mmDIG0_DIG_LANE_ENABLE';
  mmDIG0_DIG_TEST_DEBUG_INDEX                              :Result:='mmDIG0_DIG_TEST_DEBUG_INDEX';
  mmDIG0_DIG_TEST_DEBUG_DATA                               :Result:='mmDIG0_DIG_TEST_DEBUG_DATA';
  mmDIG0_DIG_FE_TEST_DEBUG_INDEX                           :Result:='mmDIG0_DIG_FE_TEST_DEBUG_INDEX';
  mmDIG0_DIG_FE_TEST_DEBUG_DATA                            :Result:='mmDIG0_DIG_FE_TEST_DEBUG_DATA';
  mmCRTC5_CRTC_PIXEL_DATA_READBACK                         :Result:='mmCRTC5_CRTC_PIXEL_DATA_READBACK';
  mmDP0_DP_LINK_CNTL                                       :Result:='mmDP0_DP_LINK_CNTL';
  mmDP0_DP_PIXEL_FORMAT                                    :Result:='mmDP0_DP_PIXEL_FORMAT';
  mmDP0_DP_MSA_COLORIMETRY                                 :Result:='mmDP0_DP_MSA_COLORIMETRY';
  mmDP0_DP_CONFIG                                          :Result:='mmDP0_DP_CONFIG';
  mmDP0_DP_VID_STREAM_CNTL                                 :Result:='mmDP0_DP_VID_STREAM_CNTL';
  mmDP0_DP_STEER_FIFO                                      :Result:='mmDP0_DP_STEER_FIFO';
  mmDP0_DP_MSA_MISC                                        :Result:='mmDP0_DP_MSA_MISC';
  mmDP0_DP_VID_TIMING                                      :Result:='mmDP0_DP_VID_TIMING';
  mmDP0_DP_VID_N                                           :Result:='mmDP0_DP_VID_N';
  mmDP0_DP_VID_M                                           :Result:='mmDP0_DP_VID_M';
  mmDP0_DP_LINK_FRAMING_CNTL                               :Result:='mmDP0_DP_LINK_FRAMING_CNTL';
  mmDP0_DP_HBR2_EYE_PATTERN                                :Result:='mmDP0_DP_HBR2_EYE_PATTERN';
  mmDP0_DP_VID_MSA_VBID                                    :Result:='mmDP0_DP_VID_MSA_VBID';
  mmDP0_DP_VID_INTERRUPT_CNTL                              :Result:='mmDP0_DP_VID_INTERRUPT_CNTL';
  mmDP0_DP_DPHY_CNTL                                       :Result:='mmDP0_DP_DPHY_CNTL';
  mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                       :Result:='mmDP0_DP_DPHY_TRAINING_PATTERN_SEL';
  mmDP0_DP_DPHY_SYM0                                       :Result:='mmDP0_DP_DPHY_SYM0';
  mmDP0_DP_DPHY_SYM1                                       :Result:='mmDP0_DP_DPHY_SYM1';
  mmDP0_DP_DPHY_SYM2                                       :Result:='mmDP0_DP_DPHY_SYM2';
  mmDP0_DP_DPHY_8B10B_CNTL                                 :Result:='mmDP0_DP_DPHY_8B10B_CNTL';
  mmDP0_DP_DPHY_PRBS_CNTL                                  :Result:='mmDP0_DP_DPHY_PRBS_CNTL';
  mmDP0_DP_DPHY_CRC_EN                                     :Result:='mmDP0_DP_DPHY_CRC_EN';
  mmDP0_DP_DPHY_CRC_CNTL                                   :Result:='mmDP0_DP_DPHY_CRC_CNTL';
  mmDP0_DP_DPHY_CRC_RESULT                                 :Result:='mmDP0_DP_DPHY_CRC_RESULT';
  mmDP0_DP_DPHY_CRC_MST_CNTL                               :Result:='mmDP0_DP_DPHY_CRC_MST_CNTL';
  mmDP0_DP_DPHY_CRC_MST_STATUS                             :Result:='mmDP0_DP_DPHY_CRC_MST_STATUS';
  mmDP0_DP_DPHY_FAST_TRAINING                              :Result:='mmDP0_DP_DPHY_FAST_TRAINING';
  mmDP0_DP_DPHY_FAST_TRAINING_STATUS                       :Result:='mmDP0_DP_DPHY_FAST_TRAINING_STATUS';
  mmDP0_DP_MSA_V_TIMING_OVERRIDE1                          :Result:='mmDP0_DP_MSA_V_TIMING_OVERRIDE1';
  mmDP0_DP_MSA_V_TIMING_OVERRIDE2                          :Result:='mmDP0_DP_MSA_V_TIMING_OVERRIDE2';
  mmDP0_DP_SEC_CNTL                                        :Result:='mmDP0_DP_SEC_CNTL';
  mmDP0_DP_SEC_CNTL1                                       :Result:='mmDP0_DP_SEC_CNTL1';
  mmDP0_DP_SEC_FRAMING1                                    :Result:='mmDP0_DP_SEC_FRAMING1';
  mmDP0_DP_SEC_FRAMING2                                    :Result:='mmDP0_DP_SEC_FRAMING2';
  mmDP0_DP_SEC_FRAMING3                                    :Result:='mmDP0_DP_SEC_FRAMING3';
  mmDP0_DP_SEC_FRAMING4                                    :Result:='mmDP0_DP_SEC_FRAMING4';
  mmDP0_DP_SEC_AUD_N                                       :Result:='mmDP0_DP_SEC_AUD_N';
  mmDP0_DP_SEC_AUD_N_READBACK                              :Result:='mmDP0_DP_SEC_AUD_N_READBACK';
  mmDP0_DP_SEC_AUD_M                                       :Result:='mmDP0_DP_SEC_AUD_M';
  mmDP0_DP_SEC_AUD_M_READBACK                              :Result:='mmDP0_DP_SEC_AUD_M_READBACK';
  mmDP0_DP_SEC_TIMESTAMP                                   :Result:='mmDP0_DP_SEC_TIMESTAMP';
  mmDP0_DP_SEC_PACKET_CNTL                                 :Result:='mmDP0_DP_SEC_PACKET_CNTL';
  mmDP0_DP_MSE_RATE_CNTL                                   :Result:='mmDP0_DP_MSE_RATE_CNTL';
  mmDP0_DP_MSE_RATE_UPDATE                                 :Result:='mmDP0_DP_MSE_RATE_UPDATE';
  mmDP0_DP_MSE_SAT0                                        :Result:='mmDP0_DP_MSE_SAT0';
  mmDP0_DP_MSE_SAT1                                        :Result:='mmDP0_DP_MSE_SAT1';
  mmDP0_DP_MSE_SAT2                                        :Result:='mmDP0_DP_MSE_SAT2';
  mmDP0_DP_MSE_SAT_UPDATE                                  :Result:='mmDP0_DP_MSE_SAT_UPDATE';
  mmDP0_DP_MSE_LINK_TIMING                                 :Result:='mmDP0_DP_MSE_LINK_TIMING';
  mmDP0_DP_MSE_MISC_CNTL                                   :Result:='mmDP0_DP_MSE_MISC_CNTL';
  mmDP0_DP_TEST_DEBUG_INDEX                                :Result:='mmDP0_DP_TEST_DEBUG_INDEX';
  mmDP0_DP_TEST_DEBUG_DATA                                 :Result:='mmDP0_DP_TEST_DEBUG_DATA';
  mmDP0_DP_FE_TEST_DEBUG_INDEX                             :Result:='mmDP0_DP_FE_TEST_DEBUG_INDEX';
  mmDP0_DP_FE_TEST_DEBUG_DATA                              :Result:='mmDP0_DP_FE_TEST_DEBUG_DATA';
  mmDIG1_DIG_FE_CNTL                                       :Result:='mmDIG1_DIG_FE_CNTL';
  mmDIG1_DIG_OUTPUT_CRC_CNTL                               :Result:='mmDIG1_DIG_OUTPUT_CRC_CNTL';
  mmDIG1_DIG_OUTPUT_CRC_RESULT                             :Result:='mmDIG1_DIG_OUTPUT_CRC_RESULT';
  mmDIG1_DIG_CLOCK_PATTERN                                 :Result:='mmDIG1_DIG_CLOCK_PATTERN';
  mmDIG1_DIG_TEST_PATTERN                                  :Result:='mmDIG1_DIG_TEST_PATTERN';
  mmDIG1_DIG_RANDOM_PATTERN_SEED                           :Result:='mmDIG1_DIG_RANDOM_PATTERN_SEED';
  mmDIG1_DIG_FIFO_STATUS                                   :Result:='mmDIG1_DIG_FIFO_STATUS';
  mmDIG1_DIG_DISPCLK_SWITCH_CNTL                           :Result:='mmDIG1_DIG_DISPCLK_SWITCH_CNTL';
  mmDIG1_DIG_DISPCLK_SWITCH_STATUS                         :Result:='mmDIG1_DIG_DISPCLK_SWITCH_STATUS';
  mmDIG1_HDMI_CONTROL                                      :Result:='mmDIG1_HDMI_CONTROL';
  mmDIG1_HDMI_STATUS                                       :Result:='mmDIG1_HDMI_STATUS';
  mmDIG1_HDMI_AUDIO_PACKET_CONTROL                         :Result:='mmDIG1_HDMI_AUDIO_PACKET_CONTROL';
  mmDIG1_HDMI_ACR_PACKET_CONTROL                           :Result:='mmDIG1_HDMI_ACR_PACKET_CONTROL';
  mmDIG1_HDMI_VBI_PACKET_CONTROL                           :Result:='mmDIG1_HDMI_VBI_PACKET_CONTROL';
  mmDIG1_HDMI_INFOFRAME_CONTROL0                           :Result:='mmDIG1_HDMI_INFOFRAME_CONTROL0';
  mmDIG1_HDMI_INFOFRAME_CONTROL1                           :Result:='mmDIG1_HDMI_INFOFRAME_CONTROL1';
  mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                      :Result:='mmDIG1_HDMI_GENERIC_PACKET_CONTROL0';
  mmDIG1_HDMI_GC                                           :Result:='mmDIG1_HDMI_GC';
  mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                        :Result:='mmDIG1_AFMT_AUDIO_PACKET_CONTROL2';
  mmDIG1_AFMT_ISRC1_0                                      :Result:='mmDIG1_AFMT_ISRC1_0';
  mmDIG1_AFMT_ISRC1_1                                      :Result:='mmDIG1_AFMT_ISRC1_1';
  mmDIG1_AFMT_ISRC1_2                                      :Result:='mmDIG1_AFMT_ISRC1_2';
  mmDIG1_AFMT_ISRC1_3                                      :Result:='mmDIG1_AFMT_ISRC1_3';
  mmDIG1_AFMT_ISRC1_4                                      :Result:='mmDIG1_AFMT_ISRC1_4';
  mmDIG1_AFMT_ISRC2_0                                      :Result:='mmDIG1_AFMT_ISRC2_0';
  mmDIG1_AFMT_ISRC2_1                                      :Result:='mmDIG1_AFMT_ISRC2_1';
  mmDIG1_AFMT_ISRC2_2                                      :Result:='mmDIG1_AFMT_ISRC2_2';
  mmDIG1_AFMT_ISRC2_3                                      :Result:='mmDIG1_AFMT_ISRC2_3';
  mmDIG1_AFMT_AVI_INFO0                                    :Result:='mmDIG1_AFMT_AVI_INFO0';
  mmDIG1_AFMT_AVI_INFO1                                    :Result:='mmDIG1_AFMT_AVI_INFO1';
  mmDIG1_AFMT_AVI_INFO2                                    :Result:='mmDIG1_AFMT_AVI_INFO2';
  mmDIG1_AFMT_AVI_INFO3                                    :Result:='mmDIG1_AFMT_AVI_INFO3';
  mmDIG1_AFMT_MPEG_INFO0                                   :Result:='mmDIG1_AFMT_MPEG_INFO0';
  mmDIG1_AFMT_MPEG_INFO1                                   :Result:='mmDIG1_AFMT_MPEG_INFO1';
  mmDIG1_AFMT_GENERIC_HDR                                  :Result:='mmDIG1_AFMT_GENERIC_HDR';
  mmDIG1_AFMT_GENERIC_0                                    :Result:='mmDIG1_AFMT_GENERIC_0';
  mmDIG1_AFMT_GENERIC_1                                    :Result:='mmDIG1_AFMT_GENERIC_1';
  mmDIG1_AFMT_GENERIC_2                                    :Result:='mmDIG1_AFMT_GENERIC_2';
  mmDIG1_AFMT_GENERIC_3                                    :Result:='mmDIG1_AFMT_GENERIC_3';
  mmDIG1_AFMT_GENERIC_4                                    :Result:='mmDIG1_AFMT_GENERIC_4';
  mmDIG1_AFMT_GENERIC_5                                    :Result:='mmDIG1_AFMT_GENERIC_5';
  mmDIG1_AFMT_GENERIC_6                                    :Result:='mmDIG1_AFMT_GENERIC_6';
  mmDIG1_AFMT_GENERIC_7                                    :Result:='mmDIG1_AFMT_GENERIC_7';
  mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                      :Result:='mmDIG1_HDMI_GENERIC_PACKET_CONTROL1';
  mmDIG1_HDMI_ACR_32_0                                     :Result:='mmDIG1_HDMI_ACR_32_0';
  mmDIG1_HDMI_ACR_32_1                                     :Result:='mmDIG1_HDMI_ACR_32_1';
  mmDIG1_HDMI_ACR_44_0                                     :Result:='mmDIG1_HDMI_ACR_44_0';
  mmDIG1_HDMI_ACR_44_1                                     :Result:='mmDIG1_HDMI_ACR_44_1';
  mmDIG1_HDMI_ACR_48_0                                     :Result:='mmDIG1_HDMI_ACR_48_0';
  mmDIG1_HDMI_ACR_48_1                                     :Result:='mmDIG1_HDMI_ACR_48_1';
  mmDIG1_HDMI_ACR_STATUS_0                                 :Result:='mmDIG1_HDMI_ACR_STATUS_0';
  mmDIG1_HDMI_ACR_STATUS_1                                 :Result:='mmDIG1_HDMI_ACR_STATUS_1';
  mmDIG1_AFMT_AUDIO_INFO0                                  :Result:='mmDIG1_AFMT_AUDIO_INFO0';
  mmDIG1_AFMT_AUDIO_INFO1                                  :Result:='mmDIG1_AFMT_AUDIO_INFO1';
  mmDIG1_AFMT_60958_0                                      :Result:='mmDIG1_AFMT_60958_0';
  mmDIG1_AFMT_60958_1                                      :Result:='mmDIG1_AFMT_60958_1';
  mmDIG1_AFMT_AUDIO_CRC_CONTROL                            :Result:='mmDIG1_AFMT_AUDIO_CRC_CONTROL';
  mmDIG1_AFMT_RAMP_CONTROL0                                :Result:='mmDIG1_AFMT_RAMP_CONTROL0';
  mmDIG1_AFMT_RAMP_CONTROL1                                :Result:='mmDIG1_AFMT_RAMP_CONTROL1';
  mmDIG1_AFMT_RAMP_CONTROL2                                :Result:='mmDIG1_AFMT_RAMP_CONTROL2';
  mmDIG1_AFMT_RAMP_CONTROL3                                :Result:='mmDIG1_AFMT_RAMP_CONTROL3';
  mmDIG1_AFMT_60958_2                                      :Result:='mmDIG1_AFMT_60958_2';
  mmDIG1_AFMT_AUDIO_CRC_RESULT                             :Result:='mmDIG1_AFMT_AUDIO_CRC_RESULT';
  mmDIG1_AFMT_STATUS                                       :Result:='mmDIG1_AFMT_STATUS';
  mmDIG1_AFMT_AUDIO_PACKET_CONTROL                         :Result:='mmDIG1_AFMT_AUDIO_PACKET_CONTROL';
  mmDIG1_AFMT_VBI_PACKET_CONTROL                           :Result:='mmDIG1_AFMT_VBI_PACKET_CONTROL';
  mmDIG1_AFMT_INFOFRAME_CONTROL0                           :Result:='mmDIG1_AFMT_INFOFRAME_CONTROL0';
  mmDIG1_AFMT_AUDIO_SRC_CONTROL                            :Result:='mmDIG1_AFMT_AUDIO_SRC_CONTROL';
  mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL                           :Result:='mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL';
  mmDIG1_DIG_BE_CNTL                                       :Result:='mmDIG1_DIG_BE_CNTL';
  mmDIG1_DIG_BE_EN_CNTL                                    :Result:='mmDIG1_DIG_BE_EN_CNTL';
  mmDIG1_TMDS_CNTL                                         :Result:='mmDIG1_TMDS_CNTL';
  mmDIG1_TMDS_CONTROL_CHAR                                 :Result:='mmDIG1_TMDS_CONTROL_CHAR';
  mmDIG1_TMDS_CONTROL0_FEEDBACK                            :Result:='mmDIG1_TMDS_CONTROL0_FEEDBACK';
  mmDIG1_TMDS_STEREOSYNC_CTL_SEL                           :Result:='mmDIG1_TMDS_STEREOSYNC_CTL_SEL';
  mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                        :Result:='mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1';
  mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                        :Result:='mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3';
  mmDIG1_TMDS_DEBUG                                        :Result:='mmDIG1_TMDS_DEBUG';
  mmDIG1_TMDS_CTL_BITS                                     :Result:='mmDIG1_TMDS_CTL_BITS';
  mmDIG1_TMDS_DCBALANCER_CONTROL                           :Result:='mmDIG1_TMDS_DCBALANCER_CONTROL';
  mmDIG1_TMDS_CTL0_1_GEN_CNTL                              :Result:='mmDIG1_TMDS_CTL0_1_GEN_CNTL';
  mmDIG1_TMDS_CTL2_3_GEN_CNTL                              :Result:='mmDIG1_TMDS_CTL2_3_GEN_CNTL';
  mmDIG1_LVDS_DATA_CNTL                                    :Result:='mmDIG1_LVDS_DATA_CNTL';
  mmDIG1_DIG_LANE_ENABLE                                   :Result:='mmDIG1_DIG_LANE_ENABLE';
  mmDIG1_DIG_TEST_DEBUG_INDEX                              :Result:='mmDIG1_DIG_TEST_DEBUG_INDEX';
  mmDIG1_DIG_TEST_DEBUG_DATA                               :Result:='mmDIG1_DIG_TEST_DEBUG_DATA';
  mmDIG1_DIG_FE_TEST_DEBUG_INDEX                           :Result:='mmDIG1_DIG_FE_TEST_DEBUG_INDEX';
  mmDIG1_DIG_FE_TEST_DEBUG_DATA                            :Result:='mmDIG1_DIG_FE_TEST_DEBUG_DATA';
  mmDP1_DP_LINK_CNTL                                       :Result:='mmDP1_DP_LINK_CNTL';
  mmDP1_DP_PIXEL_FORMAT                                    :Result:='mmDP1_DP_PIXEL_FORMAT';
  mmDP1_DP_MSA_COLORIMETRY                                 :Result:='mmDP1_DP_MSA_COLORIMETRY';
  mmDP1_DP_CONFIG                                          :Result:='mmDP1_DP_CONFIG';
  mmDP1_DP_VID_STREAM_CNTL                                 :Result:='mmDP1_DP_VID_STREAM_CNTL';
  mmDP1_DP_STEER_FIFO                                      :Result:='mmDP1_DP_STEER_FIFO';
  mmDP1_DP_MSA_MISC                                        :Result:='mmDP1_DP_MSA_MISC';
  mmDP1_DP_VID_TIMING                                      :Result:='mmDP1_DP_VID_TIMING';
  mmDP1_DP_VID_N                                           :Result:='mmDP1_DP_VID_N';
  mmDP1_DP_VID_M                                           :Result:='mmDP1_DP_VID_M';
  mmDP1_DP_LINK_FRAMING_CNTL                               :Result:='mmDP1_DP_LINK_FRAMING_CNTL';
  mmDP1_DP_HBR2_EYE_PATTERN                                :Result:='mmDP1_DP_HBR2_EYE_PATTERN';
  mmDP1_DP_VID_MSA_VBID                                    :Result:='mmDP1_DP_VID_MSA_VBID';
  mmDP1_DP_VID_INTERRUPT_CNTL                              :Result:='mmDP1_DP_VID_INTERRUPT_CNTL';
  mmDP1_DP_DPHY_CNTL                                       :Result:='mmDP1_DP_DPHY_CNTL';
  mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                       :Result:='mmDP1_DP_DPHY_TRAINING_PATTERN_SEL';
  mmDP1_DP_DPHY_SYM0                                       :Result:='mmDP1_DP_DPHY_SYM0';
  mmDP1_DP_DPHY_SYM1                                       :Result:='mmDP1_DP_DPHY_SYM1';
  mmDP1_DP_DPHY_SYM2                                       :Result:='mmDP1_DP_DPHY_SYM2';
  mmDP1_DP_DPHY_8B10B_CNTL                                 :Result:='mmDP1_DP_DPHY_8B10B_CNTL';
  mmDP1_DP_DPHY_PRBS_CNTL                                  :Result:='mmDP1_DP_DPHY_PRBS_CNTL';
  mmDP1_DP_DPHY_CRC_EN                                     :Result:='mmDP1_DP_DPHY_CRC_EN';
  mmDP1_DP_DPHY_CRC_CNTL                                   :Result:='mmDP1_DP_DPHY_CRC_CNTL';
  mmDP1_DP_DPHY_CRC_RESULT                                 :Result:='mmDP1_DP_DPHY_CRC_RESULT';
  mmDP1_DP_DPHY_CRC_MST_CNTL                               :Result:='mmDP1_DP_DPHY_CRC_MST_CNTL';
  mmDP1_DP_DPHY_CRC_MST_STATUS                             :Result:='mmDP1_DP_DPHY_CRC_MST_STATUS';
  mmDP1_DP_DPHY_FAST_TRAINING                              :Result:='mmDP1_DP_DPHY_FAST_TRAINING';
  mmDP1_DP_DPHY_FAST_TRAINING_STATUS                       :Result:='mmDP1_DP_DPHY_FAST_TRAINING_STATUS';
  mmDP1_DP_MSA_V_TIMING_OVERRIDE1                          :Result:='mmDP1_DP_MSA_V_TIMING_OVERRIDE1';
  mmDP1_DP_MSA_V_TIMING_OVERRIDE2                          :Result:='mmDP1_DP_MSA_V_TIMING_OVERRIDE2';
  mmDP1_DP_SEC_CNTL                                        :Result:='mmDP1_DP_SEC_CNTL';
  mmDP1_DP_SEC_CNTL1                                       :Result:='mmDP1_DP_SEC_CNTL1';
  mmDP1_DP_SEC_FRAMING1                                    :Result:='mmDP1_DP_SEC_FRAMING1';
  mmDP1_DP_SEC_FRAMING2                                    :Result:='mmDP1_DP_SEC_FRAMING2';
  mmDP1_DP_SEC_FRAMING3                                    :Result:='mmDP1_DP_SEC_FRAMING3';
  mmDP1_DP_SEC_FRAMING4                                    :Result:='mmDP1_DP_SEC_FRAMING4';
  mmDP1_DP_SEC_AUD_N                                       :Result:='mmDP1_DP_SEC_AUD_N';
  mmDP1_DP_SEC_AUD_N_READBACK                              :Result:='mmDP1_DP_SEC_AUD_N_READBACK';
  mmDP1_DP_SEC_AUD_M                                       :Result:='mmDP1_DP_SEC_AUD_M';
  mmDP1_DP_SEC_AUD_M_READBACK                              :Result:='mmDP1_DP_SEC_AUD_M_READBACK';
  mmDP1_DP_SEC_TIMESTAMP                                   :Result:='mmDP1_DP_SEC_TIMESTAMP';
  mmDP1_DP_SEC_PACKET_CNTL                                 :Result:='mmDP1_DP_SEC_PACKET_CNTL';
  mmDP1_DP_MSE_RATE_CNTL                                   :Result:='mmDP1_DP_MSE_RATE_CNTL';
  mmDP1_DP_MSE_RATE_UPDATE                                 :Result:='mmDP1_DP_MSE_RATE_UPDATE';
  mmDP1_DP_MSE_SAT0                                        :Result:='mmDP1_DP_MSE_SAT0';
  mmDP1_DP_MSE_SAT1                                        :Result:='mmDP1_DP_MSE_SAT1';
  mmDP1_DP_MSE_SAT2                                        :Result:='mmDP1_DP_MSE_SAT2';
  mmDP1_DP_MSE_SAT_UPDATE                                  :Result:='mmDP1_DP_MSE_SAT_UPDATE';
  mmDP1_DP_MSE_LINK_TIMING                                 :Result:='mmDP1_DP_MSE_LINK_TIMING';
  mmDP1_DP_MSE_MISC_CNTL                                   :Result:='mmDP1_DP_MSE_MISC_CNTL';
  mmDP1_DP_TEST_DEBUG_INDEX                                :Result:='mmDP1_DP_TEST_DEBUG_INDEX';
  mmDP1_DP_TEST_DEBUG_DATA                                 :Result:='mmDP1_DP_TEST_DEBUG_DATA';
  mmDP1_DP_FE_TEST_DEBUG_INDEX                             :Result:='mmDP1_DP_FE_TEST_DEBUG_INDEX';
  mmDP1_DP_FE_TEST_DEBUG_DATA                              :Result:='mmDP1_DP_FE_TEST_DEBUG_DATA';
  mmDIG2_DIG_FE_CNTL                                       :Result:='mmDIG2_DIG_FE_CNTL';
  mmDIG2_DIG_OUTPUT_CRC_CNTL                               :Result:='mmDIG2_DIG_OUTPUT_CRC_CNTL';
  mmDIG2_DIG_OUTPUT_CRC_RESULT                             :Result:='mmDIG2_DIG_OUTPUT_CRC_RESULT';
  mmDIG2_DIG_CLOCK_PATTERN                                 :Result:='mmDIG2_DIG_CLOCK_PATTERN';
  mmDIG2_DIG_TEST_PATTERN                                  :Result:='mmDIG2_DIG_TEST_PATTERN';
  mmDIG2_DIG_RANDOM_PATTERN_SEED                           :Result:='mmDIG2_DIG_RANDOM_PATTERN_SEED';
  mmDIG2_DIG_FIFO_STATUS                                   :Result:='mmDIG2_DIG_FIFO_STATUS';
  mmDIG2_DIG_DISPCLK_SWITCH_CNTL                           :Result:='mmDIG2_DIG_DISPCLK_SWITCH_CNTL';
  mmDIG2_DIG_DISPCLK_SWITCH_STATUS                         :Result:='mmDIG2_DIG_DISPCLK_SWITCH_STATUS';
  mmDIG2_HDMI_CONTROL                                      :Result:='mmDIG2_HDMI_CONTROL';
  mmDIG2_HDMI_STATUS                                       :Result:='mmDIG2_HDMI_STATUS';
  mmDIG2_HDMI_AUDIO_PACKET_CONTROL                         :Result:='mmDIG2_HDMI_AUDIO_PACKET_CONTROL';
  mmDIG2_HDMI_ACR_PACKET_CONTROL                           :Result:='mmDIG2_HDMI_ACR_PACKET_CONTROL';
  mmDIG2_HDMI_VBI_PACKET_CONTROL                           :Result:='mmDIG2_HDMI_VBI_PACKET_CONTROL';
  mmDIG2_HDMI_INFOFRAME_CONTROL0                           :Result:='mmDIG2_HDMI_INFOFRAME_CONTROL0';
  mmDIG2_HDMI_INFOFRAME_CONTROL1                           :Result:='mmDIG2_HDMI_INFOFRAME_CONTROL1';
  mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                      :Result:='mmDIG2_HDMI_GENERIC_PACKET_CONTROL0';
  mmDIG2_HDMI_GC                                           :Result:='mmDIG2_HDMI_GC';
  mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                        :Result:='mmDIG2_AFMT_AUDIO_PACKET_CONTROL2';
  mmDIG2_AFMT_ISRC1_0                                      :Result:='mmDIG2_AFMT_ISRC1_0';
  mmDIG2_AFMT_ISRC1_1                                      :Result:='mmDIG2_AFMT_ISRC1_1';
  mmDIG2_AFMT_ISRC1_2                                      :Result:='mmDIG2_AFMT_ISRC1_2';
  mmDIG2_AFMT_ISRC1_3                                      :Result:='mmDIG2_AFMT_ISRC1_3';
  mmDIG2_AFMT_ISRC1_4                                      :Result:='mmDIG2_AFMT_ISRC1_4';
  mmDIG2_AFMT_ISRC2_0                                      :Result:='mmDIG2_AFMT_ISRC2_0';
  mmDIG2_AFMT_ISRC2_1                                      :Result:='mmDIG2_AFMT_ISRC2_1';
  mmDIG2_AFMT_ISRC2_2                                      :Result:='mmDIG2_AFMT_ISRC2_2';
  mmDIG2_AFMT_ISRC2_3                                      :Result:='mmDIG2_AFMT_ISRC2_3';
  mmDIG2_AFMT_AVI_INFO0                                    :Result:='mmDIG2_AFMT_AVI_INFO0';
  mmDIG2_AFMT_AVI_INFO1                                    :Result:='mmDIG2_AFMT_AVI_INFO1';
  mmDIG2_AFMT_AVI_INFO2                                    :Result:='mmDIG2_AFMT_AVI_INFO2';
  mmDIG2_AFMT_AVI_INFO3                                    :Result:='mmDIG2_AFMT_AVI_INFO3';
  mmDIG2_AFMT_MPEG_INFO0                                   :Result:='mmDIG2_AFMT_MPEG_INFO0';
  mmDIG2_AFMT_MPEG_INFO1                                   :Result:='mmDIG2_AFMT_MPEG_INFO1';
  mmDIG2_AFMT_GENERIC_HDR                                  :Result:='mmDIG2_AFMT_GENERIC_HDR';
  mmDIG2_AFMT_GENERIC_0                                    :Result:='mmDIG2_AFMT_GENERIC_0';
  mmDIG2_AFMT_GENERIC_1                                    :Result:='mmDIG2_AFMT_GENERIC_1';
  mmDIG2_AFMT_GENERIC_2                                    :Result:='mmDIG2_AFMT_GENERIC_2';
  mmDIG2_AFMT_GENERIC_3                                    :Result:='mmDIG2_AFMT_GENERIC_3';
  mmDIG2_AFMT_GENERIC_4                                    :Result:='mmDIG2_AFMT_GENERIC_4';
  mmDIG2_AFMT_GENERIC_5                                    :Result:='mmDIG2_AFMT_GENERIC_5';
  mmDIG2_AFMT_GENERIC_6                                    :Result:='mmDIG2_AFMT_GENERIC_6';
  mmDIG2_AFMT_GENERIC_7                                    :Result:='mmDIG2_AFMT_GENERIC_7';
  mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                      :Result:='mmDIG2_HDMI_GENERIC_PACKET_CONTROL1';
  mmDIG2_HDMI_ACR_32_0                                     :Result:='mmDIG2_HDMI_ACR_32_0';
  mmDIG2_HDMI_ACR_32_1                                     :Result:='mmDIG2_HDMI_ACR_32_1';
  mmDIG2_HDMI_ACR_44_0                                     :Result:='mmDIG2_HDMI_ACR_44_0';
  mmDIG2_HDMI_ACR_44_1                                     :Result:='mmDIG2_HDMI_ACR_44_1';
  mmDIG2_HDMI_ACR_48_0                                     :Result:='mmDIG2_HDMI_ACR_48_0';
  mmDIG2_HDMI_ACR_48_1                                     :Result:='mmDIG2_HDMI_ACR_48_1';
  mmDIG2_HDMI_ACR_STATUS_0                                 :Result:='mmDIG2_HDMI_ACR_STATUS_0';
  mmDIG2_HDMI_ACR_STATUS_1                                 :Result:='mmDIG2_HDMI_ACR_STATUS_1';
  mmDIG2_AFMT_AUDIO_INFO0                                  :Result:='mmDIG2_AFMT_AUDIO_INFO0';
  mmDIG2_AFMT_AUDIO_INFO1                                  :Result:='mmDIG2_AFMT_AUDIO_INFO1';
  mmDIG2_AFMT_60958_0                                      :Result:='mmDIG2_AFMT_60958_0';
  mmDIG2_AFMT_60958_1                                      :Result:='mmDIG2_AFMT_60958_1';
  mmDIG2_AFMT_AUDIO_CRC_CONTROL                            :Result:='mmDIG2_AFMT_AUDIO_CRC_CONTROL';
  mmDIG2_AFMT_RAMP_CONTROL0                                :Result:='mmDIG2_AFMT_RAMP_CONTROL0';
  mmDIG2_AFMT_RAMP_CONTROL1                                :Result:='mmDIG2_AFMT_RAMP_CONTROL1';
  mmDIG2_AFMT_RAMP_CONTROL2                                :Result:='mmDIG2_AFMT_RAMP_CONTROL2';
  mmDIG2_AFMT_RAMP_CONTROL3                                :Result:='mmDIG2_AFMT_RAMP_CONTROL3';
  mmDIG2_AFMT_60958_2                                      :Result:='mmDIG2_AFMT_60958_2';
  mmDIG2_AFMT_AUDIO_CRC_RESULT                             :Result:='mmDIG2_AFMT_AUDIO_CRC_RESULT';
  mmDIG2_AFMT_STATUS                                       :Result:='mmDIG2_AFMT_STATUS';
  mmDIG2_AFMT_AUDIO_PACKET_CONTROL                         :Result:='mmDIG2_AFMT_AUDIO_PACKET_CONTROL';
  mmDIG2_AFMT_VBI_PACKET_CONTROL                           :Result:='mmDIG2_AFMT_VBI_PACKET_CONTROL';
  mmDIG2_AFMT_INFOFRAME_CONTROL0                           :Result:='mmDIG2_AFMT_INFOFRAME_CONTROL0';
  mmDIG2_AFMT_AUDIO_SRC_CONTROL                            :Result:='mmDIG2_AFMT_AUDIO_SRC_CONTROL';
  mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL                           :Result:='mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL';
  mmDIG2_DIG_BE_CNTL                                       :Result:='mmDIG2_DIG_BE_CNTL';
  mmDIG2_DIG_BE_EN_CNTL                                    :Result:='mmDIG2_DIG_BE_EN_CNTL';
  mmDIG2_TMDS_CNTL                                         :Result:='mmDIG2_TMDS_CNTL';
  mmDIG2_TMDS_CONTROL_CHAR                                 :Result:='mmDIG2_TMDS_CONTROL_CHAR';
  mmDIG2_TMDS_CONTROL0_FEEDBACK                            :Result:='mmDIG2_TMDS_CONTROL0_FEEDBACK';
  mmDIG2_TMDS_STEREOSYNC_CTL_SEL                           :Result:='mmDIG2_TMDS_STEREOSYNC_CTL_SEL';
  mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                        :Result:='mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1';
  mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                        :Result:='mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3';
  mmDIG2_TMDS_DEBUG                                        :Result:='mmDIG2_TMDS_DEBUG';
  mmDIG2_TMDS_CTL_BITS                                     :Result:='mmDIG2_TMDS_CTL_BITS';
  mmDIG2_TMDS_DCBALANCER_CONTROL                           :Result:='mmDIG2_TMDS_DCBALANCER_CONTROL';
  mmDIG2_TMDS_CTL0_1_GEN_CNTL                              :Result:='mmDIG2_TMDS_CTL0_1_GEN_CNTL';
  mmDIG2_TMDS_CTL2_3_GEN_CNTL                              :Result:='mmDIG2_TMDS_CTL2_3_GEN_CNTL';
  mmDIG2_LVDS_DATA_CNTL                                    :Result:='mmDIG2_LVDS_DATA_CNTL';
  mmDIG2_DIG_LANE_ENABLE                                   :Result:='mmDIG2_DIG_LANE_ENABLE';
  mmDIG2_DIG_TEST_DEBUG_INDEX                              :Result:='mmDIG2_DIG_TEST_DEBUG_INDEX';
  mmDIG2_DIG_TEST_DEBUG_DATA                               :Result:='mmDIG2_DIG_TEST_DEBUG_DATA';
  mmDIG2_DIG_FE_TEST_DEBUG_INDEX                           :Result:='mmDIG2_DIG_FE_TEST_DEBUG_INDEX';
  mmDIG2_DIG_FE_TEST_DEBUG_DATA                            :Result:='mmDIG2_DIG_FE_TEST_DEBUG_DATA';
  mmDP2_DP_LINK_CNTL                                       :Result:='mmDP2_DP_LINK_CNTL';
  mmDP2_DP_PIXEL_FORMAT                                    :Result:='mmDP2_DP_PIXEL_FORMAT';
  mmDP2_DP_MSA_COLORIMETRY                                 :Result:='mmDP2_DP_MSA_COLORIMETRY';
  mmDP2_DP_CONFIG                                          :Result:='mmDP2_DP_CONFIG';
  mmDP2_DP_VID_STREAM_CNTL                                 :Result:='mmDP2_DP_VID_STREAM_CNTL';
  mmDP2_DP_STEER_FIFO                                      :Result:='mmDP2_DP_STEER_FIFO';
  mmDP2_DP_MSA_MISC                                        :Result:='mmDP2_DP_MSA_MISC';
  mmDP2_DP_VID_TIMING                                      :Result:='mmDP2_DP_VID_TIMING';
  mmDP2_DP_VID_N                                           :Result:='mmDP2_DP_VID_N';
  mmDP2_DP_VID_M                                           :Result:='mmDP2_DP_VID_M';
  mmDP2_DP_LINK_FRAMING_CNTL                               :Result:='mmDP2_DP_LINK_FRAMING_CNTL';
  mmDP2_DP_HBR2_EYE_PATTERN                                :Result:='mmDP2_DP_HBR2_EYE_PATTERN';
  mmDP2_DP_VID_MSA_VBID                                    :Result:='mmDP2_DP_VID_MSA_VBID';
  mmDP2_DP_VID_INTERRUPT_CNTL                              :Result:='mmDP2_DP_VID_INTERRUPT_CNTL';
  mmDP2_DP_DPHY_CNTL                                       :Result:='mmDP2_DP_DPHY_CNTL';
  mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                       :Result:='mmDP2_DP_DPHY_TRAINING_PATTERN_SEL';
  mmDP2_DP_DPHY_SYM0                                       :Result:='mmDP2_DP_DPHY_SYM0';
  mmDP2_DP_DPHY_SYM1                                       :Result:='mmDP2_DP_DPHY_SYM1';
  mmDP2_DP_DPHY_SYM2                                       :Result:='mmDP2_DP_DPHY_SYM2';
  mmDP2_DP_DPHY_8B10B_CNTL                                 :Result:='mmDP2_DP_DPHY_8B10B_CNTL';
  mmDP2_DP_DPHY_PRBS_CNTL                                  :Result:='mmDP2_DP_DPHY_PRBS_CNTL';
  mmDP2_DP_DPHY_CRC_EN                                     :Result:='mmDP2_DP_DPHY_CRC_EN';
  mmDP2_DP_DPHY_CRC_CNTL                                   :Result:='mmDP2_DP_DPHY_CRC_CNTL';
  mmDP2_DP_DPHY_CRC_RESULT                                 :Result:='mmDP2_DP_DPHY_CRC_RESULT';
  mmDP2_DP_DPHY_CRC_MST_CNTL                               :Result:='mmDP2_DP_DPHY_CRC_MST_CNTL';
  mmDP2_DP_DPHY_CRC_MST_STATUS                             :Result:='mmDP2_DP_DPHY_CRC_MST_STATUS';
  mmDP2_DP_DPHY_FAST_TRAINING                              :Result:='mmDP2_DP_DPHY_FAST_TRAINING';
  mmDP2_DP_DPHY_FAST_TRAINING_STATUS                       :Result:='mmDP2_DP_DPHY_FAST_TRAINING_STATUS';
  mmDP2_DP_MSA_V_TIMING_OVERRIDE1                          :Result:='mmDP2_DP_MSA_V_TIMING_OVERRIDE1';
  mmDP2_DP_MSA_V_TIMING_OVERRIDE2                          :Result:='mmDP2_DP_MSA_V_TIMING_OVERRIDE2';
  mmDP2_DP_SEC_CNTL                                        :Result:='mmDP2_DP_SEC_CNTL';
  mmDP2_DP_SEC_CNTL1                                       :Result:='mmDP2_DP_SEC_CNTL1';
  mmDP2_DP_SEC_FRAMING1                                    :Result:='mmDP2_DP_SEC_FRAMING1';
  mmDP2_DP_SEC_FRAMING2                                    :Result:='mmDP2_DP_SEC_FRAMING2';
  mmDP2_DP_SEC_FRAMING3                                    :Result:='mmDP2_DP_SEC_FRAMING3';
  mmDP2_DP_SEC_FRAMING4                                    :Result:='mmDP2_DP_SEC_FRAMING4';
  mmDP2_DP_SEC_AUD_N                                       :Result:='mmDP2_DP_SEC_AUD_N';
  mmDP2_DP_SEC_AUD_N_READBACK                              :Result:='mmDP2_DP_SEC_AUD_N_READBACK';
  mmDP2_DP_SEC_AUD_M                                       :Result:='mmDP2_DP_SEC_AUD_M';
  mmDP2_DP_SEC_AUD_M_READBACK                              :Result:='mmDP2_DP_SEC_AUD_M_READBACK';
  mmDP2_DP_SEC_TIMESTAMP                                   :Result:='mmDP2_DP_SEC_TIMESTAMP';
  mmDP2_DP_SEC_PACKET_CNTL                                 :Result:='mmDP2_DP_SEC_PACKET_CNTL';
  mmDP2_DP_MSE_RATE_CNTL                                   :Result:='mmDP2_DP_MSE_RATE_CNTL';
  mmDP2_DP_MSE_RATE_UPDATE                                 :Result:='mmDP2_DP_MSE_RATE_UPDATE';
  mmDP2_DP_MSE_SAT0                                        :Result:='mmDP2_DP_MSE_SAT0';
  mmDP2_DP_MSE_SAT1                                        :Result:='mmDP2_DP_MSE_SAT1';
  mmDP2_DP_MSE_SAT2                                        :Result:='mmDP2_DP_MSE_SAT2';
  mmDP2_DP_MSE_SAT_UPDATE                                  :Result:='mmDP2_DP_MSE_SAT_UPDATE';
  mmDP2_DP_MSE_LINK_TIMING                                 :Result:='mmDP2_DP_MSE_LINK_TIMING';
  mmDP2_DP_MSE_MISC_CNTL                                   :Result:='mmDP2_DP_MSE_MISC_CNTL';
  mmDP2_DP_TEST_DEBUG_INDEX                                :Result:='mmDP2_DP_TEST_DEBUG_INDEX';
  mmDP2_DP_TEST_DEBUG_DATA                                 :Result:='mmDP2_DP_TEST_DEBUG_DATA';
  mmDP2_DP_FE_TEST_DEBUG_INDEX                             :Result:='mmDP2_DP_FE_TEST_DEBUG_INDEX';
  mmDP2_DP_FE_TEST_DEBUG_DATA                              :Result:='mmDP2_DP_FE_TEST_DEBUG_DATA';
  mmDIG3_DIG_FE_CNTL                                       :Result:='mmDIG3_DIG_FE_CNTL';
  mmDIG3_DIG_OUTPUT_CRC_CNTL                               :Result:='mmDIG3_DIG_OUTPUT_CRC_CNTL';
  mmDIG3_DIG_OUTPUT_CRC_RESULT                             :Result:='mmDIG3_DIG_OUTPUT_CRC_RESULT';
  mmDIG3_DIG_CLOCK_PATTERN                                 :Result:='mmDIG3_DIG_CLOCK_PATTERN';
  mmDIG3_DIG_TEST_PATTERN                                  :Result:='mmDIG3_DIG_TEST_PATTERN';
  mmDIG3_DIG_RANDOM_PATTERN_SEED                           :Result:='mmDIG3_DIG_RANDOM_PATTERN_SEED';
  mmDIG3_DIG_FIFO_STATUS                                   :Result:='mmDIG3_DIG_FIFO_STATUS';
  mmDIG3_DIG_DISPCLK_SWITCH_CNTL                           :Result:='mmDIG3_DIG_DISPCLK_SWITCH_CNTL';
  mmDIG3_DIG_DISPCLK_SWITCH_STATUS                         :Result:='mmDIG3_DIG_DISPCLK_SWITCH_STATUS';
  mmDIG3_HDMI_CONTROL                                      :Result:='mmDIG3_HDMI_CONTROL';
  mmDIG3_HDMI_STATUS                                       :Result:='mmDIG3_HDMI_STATUS';
  mmDIG3_HDMI_AUDIO_PACKET_CONTROL                         :Result:='mmDIG3_HDMI_AUDIO_PACKET_CONTROL';
  mmDIG3_HDMI_ACR_PACKET_CONTROL                           :Result:='mmDIG3_HDMI_ACR_PACKET_CONTROL';
  mmDIG3_HDMI_VBI_PACKET_CONTROL                           :Result:='mmDIG3_HDMI_VBI_PACKET_CONTROL';
  mmDIG3_HDMI_INFOFRAME_CONTROL0                           :Result:='mmDIG3_HDMI_INFOFRAME_CONTROL0';
  mmDIG3_HDMI_INFOFRAME_CONTROL1                           :Result:='mmDIG3_HDMI_INFOFRAME_CONTROL1';
  mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                      :Result:='mmDIG3_HDMI_GENERIC_PACKET_CONTROL0';
  mmDIG3_HDMI_GC                                           :Result:='mmDIG3_HDMI_GC';
  mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                        :Result:='mmDIG3_AFMT_AUDIO_PACKET_CONTROL2';
  mmDIG3_AFMT_ISRC1_0                                      :Result:='mmDIG3_AFMT_ISRC1_0';
  mmDIG3_AFMT_ISRC1_1                                      :Result:='mmDIG3_AFMT_ISRC1_1';
  mmDIG3_AFMT_ISRC1_2                                      :Result:='mmDIG3_AFMT_ISRC1_2';
  mmDIG3_AFMT_ISRC1_3                                      :Result:='mmDIG3_AFMT_ISRC1_3';
  mmDIG3_AFMT_ISRC1_4                                      :Result:='mmDIG3_AFMT_ISRC1_4';
  mmDIG3_AFMT_ISRC2_0                                      :Result:='mmDIG3_AFMT_ISRC2_0';
  mmDIG3_AFMT_ISRC2_1                                      :Result:='mmDIG3_AFMT_ISRC2_1';
  mmDIG3_AFMT_ISRC2_2                                      :Result:='mmDIG3_AFMT_ISRC2_2';
  mmDIG3_AFMT_ISRC2_3                                      :Result:='mmDIG3_AFMT_ISRC2_3';
  mmDIG3_AFMT_AVI_INFO0                                    :Result:='mmDIG3_AFMT_AVI_INFO0';
  mmDIG3_AFMT_AVI_INFO1                                    :Result:='mmDIG3_AFMT_AVI_INFO1';
  mmDIG3_AFMT_AVI_INFO2                                    :Result:='mmDIG3_AFMT_AVI_INFO2';
  mmDIG3_AFMT_AVI_INFO3                                    :Result:='mmDIG3_AFMT_AVI_INFO3';
  mmDIG3_AFMT_MPEG_INFO0                                   :Result:='mmDIG3_AFMT_MPEG_INFO0';
  mmDIG3_AFMT_MPEG_INFO1                                   :Result:='mmDIG3_AFMT_MPEG_INFO1';
  mmDIG3_AFMT_GENERIC_HDR                                  :Result:='mmDIG3_AFMT_GENERIC_HDR';
  mmDIG3_AFMT_GENERIC_0                                    :Result:='mmDIG3_AFMT_GENERIC_0';
  mmDIG3_AFMT_GENERIC_1                                    :Result:='mmDIG3_AFMT_GENERIC_1';
  mmDIG3_AFMT_GENERIC_2                                    :Result:='mmDIG3_AFMT_GENERIC_2';
  mmDIG3_AFMT_GENERIC_3                                    :Result:='mmDIG3_AFMT_GENERIC_3';
  mmDIG3_AFMT_GENERIC_4                                    :Result:='mmDIG3_AFMT_GENERIC_4';
  mmDIG3_AFMT_GENERIC_5                                    :Result:='mmDIG3_AFMT_GENERIC_5';
  mmDIG3_AFMT_GENERIC_6                                    :Result:='mmDIG3_AFMT_GENERIC_6';
  mmDIG3_AFMT_GENERIC_7                                    :Result:='mmDIG3_AFMT_GENERIC_7';
  mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                      :Result:='mmDIG3_HDMI_GENERIC_PACKET_CONTROL1';
  mmDIG3_HDMI_ACR_32_0                                     :Result:='mmDIG3_HDMI_ACR_32_0';
  mmDIG3_HDMI_ACR_32_1                                     :Result:='mmDIG3_HDMI_ACR_32_1';
  mmDIG3_HDMI_ACR_44_0                                     :Result:='mmDIG3_HDMI_ACR_44_0';
  mmDIG3_HDMI_ACR_44_1                                     :Result:='mmDIG3_HDMI_ACR_44_1';
  mmDIG3_HDMI_ACR_48_0                                     :Result:='mmDIG3_HDMI_ACR_48_0';
  mmDIG3_HDMI_ACR_48_1                                     :Result:='mmDIG3_HDMI_ACR_48_1';
  mmDIG3_HDMI_ACR_STATUS_0                                 :Result:='mmDIG3_HDMI_ACR_STATUS_0';
  mmDIG3_HDMI_ACR_STATUS_1                                 :Result:='mmDIG3_HDMI_ACR_STATUS_1';
  mmDIG3_AFMT_AUDIO_INFO0                                  :Result:='mmDIG3_AFMT_AUDIO_INFO0';
  mmDIG3_AFMT_AUDIO_INFO1                                  :Result:='mmDIG3_AFMT_AUDIO_INFO1';
  mmDIG3_AFMT_60958_0                                      :Result:='mmDIG3_AFMT_60958_0';
  mmDIG3_AFMT_60958_1                                      :Result:='mmDIG3_AFMT_60958_1';
  mmDIG3_AFMT_AUDIO_CRC_CONTROL                            :Result:='mmDIG3_AFMT_AUDIO_CRC_CONTROL';
  mmDIG3_AFMT_RAMP_CONTROL0                                :Result:='mmDIG3_AFMT_RAMP_CONTROL0';
  mmDIG3_AFMT_RAMP_CONTROL1                                :Result:='mmDIG3_AFMT_RAMP_CONTROL1';
  mmDIG3_AFMT_RAMP_CONTROL2                                :Result:='mmDIG3_AFMT_RAMP_CONTROL2';
  mmDIG3_AFMT_RAMP_CONTROL3                                :Result:='mmDIG3_AFMT_RAMP_CONTROL3';
  mmDIG3_AFMT_60958_2                                      :Result:='mmDIG3_AFMT_60958_2';
  mmDIG3_AFMT_AUDIO_CRC_RESULT                             :Result:='mmDIG3_AFMT_AUDIO_CRC_RESULT';
  mmDIG3_AFMT_STATUS                                       :Result:='mmDIG3_AFMT_STATUS';
  mmDIG3_AFMT_AUDIO_PACKET_CONTROL                         :Result:='mmDIG3_AFMT_AUDIO_PACKET_CONTROL';
  mmDIG3_AFMT_VBI_PACKET_CONTROL                           :Result:='mmDIG3_AFMT_VBI_PACKET_CONTROL';
  mmDIG3_AFMT_INFOFRAME_CONTROL0                           :Result:='mmDIG3_AFMT_INFOFRAME_CONTROL0';
  mmDIG3_AFMT_AUDIO_SRC_CONTROL                            :Result:='mmDIG3_AFMT_AUDIO_SRC_CONTROL';
  mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL                           :Result:='mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL';
  mmDIG3_DIG_BE_CNTL                                       :Result:='mmDIG3_DIG_BE_CNTL';
  mmDIG3_DIG_BE_EN_CNTL                                    :Result:='mmDIG3_DIG_BE_EN_CNTL';
  mmDIG3_TMDS_CNTL                                         :Result:='mmDIG3_TMDS_CNTL';
  mmDIG3_TMDS_CONTROL_CHAR                                 :Result:='mmDIG3_TMDS_CONTROL_CHAR';
  mmDIG3_TMDS_CONTROL0_FEEDBACK                            :Result:='mmDIG3_TMDS_CONTROL0_FEEDBACK';
  mmDIG3_TMDS_STEREOSYNC_CTL_SEL                           :Result:='mmDIG3_TMDS_STEREOSYNC_CTL_SEL';
  mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                        :Result:='mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1';
  mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                        :Result:='mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3';
  mmDIG3_TMDS_DEBUG                                        :Result:='mmDIG3_TMDS_DEBUG';
  mmDIG3_TMDS_CTL_BITS                                     :Result:='mmDIG3_TMDS_CTL_BITS';
  mmDIG3_TMDS_DCBALANCER_CONTROL                           :Result:='mmDIG3_TMDS_DCBALANCER_CONTROL';
  mmDIG3_TMDS_CTL0_1_GEN_CNTL                              :Result:='mmDIG3_TMDS_CTL0_1_GEN_CNTL';
  mmDIG3_TMDS_CTL2_3_GEN_CNTL                              :Result:='mmDIG3_TMDS_CTL2_3_GEN_CNTL';
  mmDIG3_LVDS_DATA_CNTL                                    :Result:='mmDIG3_LVDS_DATA_CNTL';
  mmDIG3_DIG_LANE_ENABLE                                   :Result:='mmDIG3_DIG_LANE_ENABLE';
  mmDIG3_DIG_TEST_DEBUG_INDEX                              :Result:='mmDIG3_DIG_TEST_DEBUG_INDEX';
  mmDIG3_DIG_TEST_DEBUG_DATA                               :Result:='mmDIG3_DIG_TEST_DEBUG_DATA';
  mmDIG3_DIG_FE_TEST_DEBUG_INDEX                           :Result:='mmDIG3_DIG_FE_TEST_DEBUG_INDEX';
  mmDIG3_DIG_FE_TEST_DEBUG_DATA                            :Result:='mmDIG3_DIG_FE_TEST_DEBUG_DATA';
  mmDP3_DP_LINK_CNTL                                       :Result:='mmDP3_DP_LINK_CNTL';
  mmDP3_DP_PIXEL_FORMAT                                    :Result:='mmDP3_DP_PIXEL_FORMAT';
  mmDP3_DP_MSA_COLORIMETRY                                 :Result:='mmDP3_DP_MSA_COLORIMETRY';
  mmDP3_DP_CONFIG                                          :Result:='mmDP3_DP_CONFIG';
  mmDP3_DP_VID_STREAM_CNTL                                 :Result:='mmDP3_DP_VID_STREAM_CNTL';
  mmDP3_DP_STEER_FIFO                                      :Result:='mmDP3_DP_STEER_FIFO';
  mmDP3_DP_MSA_MISC                                        :Result:='mmDP3_DP_MSA_MISC';
  mmDP3_DP_VID_TIMING                                      :Result:='mmDP3_DP_VID_TIMING';
  mmDP3_DP_VID_N                                           :Result:='mmDP3_DP_VID_N';
  mmDP3_DP_VID_M                                           :Result:='mmDP3_DP_VID_M';
  mmDP3_DP_LINK_FRAMING_CNTL                               :Result:='mmDP3_DP_LINK_FRAMING_CNTL';
  mmDP3_DP_HBR2_EYE_PATTERN                                :Result:='mmDP3_DP_HBR2_EYE_PATTERN';
  mmDP3_DP_VID_MSA_VBID                                    :Result:='mmDP3_DP_VID_MSA_VBID';
  mmDP3_DP_VID_INTERRUPT_CNTL                              :Result:='mmDP3_DP_VID_INTERRUPT_CNTL';
  mmDP3_DP_DPHY_CNTL                                       :Result:='mmDP3_DP_DPHY_CNTL';
  mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                       :Result:='mmDP3_DP_DPHY_TRAINING_PATTERN_SEL';
  mmDP3_DP_DPHY_SYM0                                       :Result:='mmDP3_DP_DPHY_SYM0';
  mmDP3_DP_DPHY_SYM1                                       :Result:='mmDP3_DP_DPHY_SYM1';
  mmDP3_DP_DPHY_SYM2                                       :Result:='mmDP3_DP_DPHY_SYM2';
  mmDP3_DP_DPHY_8B10B_CNTL                                 :Result:='mmDP3_DP_DPHY_8B10B_CNTL';
  mmDP3_DP_DPHY_PRBS_CNTL                                  :Result:='mmDP3_DP_DPHY_PRBS_CNTL';
  mmDP3_DP_DPHY_CRC_EN                                     :Result:='mmDP3_DP_DPHY_CRC_EN';
  mmDP3_DP_DPHY_CRC_CNTL                                   :Result:='mmDP3_DP_DPHY_CRC_CNTL';
  mmDP3_DP_DPHY_CRC_RESULT                                 :Result:='mmDP3_DP_DPHY_CRC_RESULT';
  mmDP3_DP_DPHY_CRC_MST_CNTL                               :Result:='mmDP3_DP_DPHY_CRC_MST_CNTL';
  mmDP3_DP_DPHY_CRC_MST_STATUS                             :Result:='mmDP3_DP_DPHY_CRC_MST_STATUS';
  mmDP3_DP_DPHY_FAST_TRAINING                              :Result:='mmDP3_DP_DPHY_FAST_TRAINING';
  mmDP3_DP_DPHY_FAST_TRAINING_STATUS                       :Result:='mmDP3_DP_DPHY_FAST_TRAINING_STATUS';
  mmDP3_DP_MSA_V_TIMING_OVERRIDE1                          :Result:='mmDP3_DP_MSA_V_TIMING_OVERRIDE1';
  mmDP3_DP_MSA_V_TIMING_OVERRIDE2                          :Result:='mmDP3_DP_MSA_V_TIMING_OVERRIDE2';
  mmDP3_DP_SEC_CNTL                                        :Result:='mmDP3_DP_SEC_CNTL';
  mmDP3_DP_SEC_CNTL1                                       :Result:='mmDP3_DP_SEC_CNTL1';
  mmDP3_DP_SEC_FRAMING1                                    :Result:='mmDP3_DP_SEC_FRAMING1';
  mmDP3_DP_SEC_FRAMING2                                    :Result:='mmDP3_DP_SEC_FRAMING2';
  mmDP3_DP_SEC_FRAMING3                                    :Result:='mmDP3_DP_SEC_FRAMING3';
  mmDP3_DP_SEC_FRAMING4                                    :Result:='mmDP3_DP_SEC_FRAMING4';
  mmDP3_DP_SEC_AUD_N                                       :Result:='mmDP3_DP_SEC_AUD_N';
  mmDP3_DP_SEC_AUD_N_READBACK                              :Result:='mmDP3_DP_SEC_AUD_N_READBACK';
  mmDP3_DP_SEC_AUD_M                                       :Result:='mmDP3_DP_SEC_AUD_M';
  mmDP3_DP_SEC_AUD_M_READBACK                              :Result:='mmDP3_DP_SEC_AUD_M_READBACK';
  mmDP3_DP_SEC_TIMESTAMP                                   :Result:='mmDP3_DP_SEC_TIMESTAMP';
  mmDP3_DP_SEC_PACKET_CNTL                                 :Result:='mmDP3_DP_SEC_PACKET_CNTL';
  mmDP3_DP_MSE_RATE_CNTL                                   :Result:='mmDP3_DP_MSE_RATE_CNTL';
  mmDP3_DP_MSE_RATE_UPDATE                                 :Result:='mmDP3_DP_MSE_RATE_UPDATE';
  mmDP3_DP_MSE_SAT0                                        :Result:='mmDP3_DP_MSE_SAT0';
  mmDP3_DP_MSE_SAT1                                        :Result:='mmDP3_DP_MSE_SAT1';
  mmDP3_DP_MSE_SAT2                                        :Result:='mmDP3_DP_MSE_SAT2';
  mmDP3_DP_MSE_SAT_UPDATE                                  :Result:='mmDP3_DP_MSE_SAT_UPDATE';
  mmDP3_DP_MSE_LINK_TIMING                                 :Result:='mmDP3_DP_MSE_LINK_TIMING';
  mmDP3_DP_MSE_MISC_CNTL                                   :Result:='mmDP3_DP_MSE_MISC_CNTL';
  mmDP3_DP_TEST_DEBUG_INDEX                                :Result:='mmDP3_DP_TEST_DEBUG_INDEX';
  mmDP3_DP_TEST_DEBUG_DATA                                 :Result:='mmDP3_DP_TEST_DEBUG_DATA';
  mmDP3_DP_FE_TEST_DEBUG_INDEX                             :Result:='mmDP3_DP_FE_TEST_DEBUG_INDEX';
  mmDP3_DP_FE_TEST_DEBUG_DATA                              :Result:='mmDP3_DP_FE_TEST_DEBUG_DATA';
  mmDIG4_DIG_FE_CNTL                                       :Result:='mmDIG4_DIG_FE_CNTL';
  mmDIG4_DIG_OUTPUT_CRC_CNTL                               :Result:='mmDIG4_DIG_OUTPUT_CRC_CNTL';
  mmDIG4_DIG_OUTPUT_CRC_RESULT                             :Result:='mmDIG4_DIG_OUTPUT_CRC_RESULT';
  mmDIG4_DIG_CLOCK_PATTERN                                 :Result:='mmDIG4_DIG_CLOCK_PATTERN';
  mmDIG4_DIG_TEST_PATTERN                                  :Result:='mmDIG4_DIG_TEST_PATTERN';
  mmDIG4_DIG_RANDOM_PATTERN_SEED                           :Result:='mmDIG4_DIG_RANDOM_PATTERN_SEED';
  mmDIG4_DIG_FIFO_STATUS                                   :Result:='mmDIG4_DIG_FIFO_STATUS';
  mmDIG4_DIG_DISPCLK_SWITCH_CNTL                           :Result:='mmDIG4_DIG_DISPCLK_SWITCH_CNTL';
  mmDIG4_DIG_DISPCLK_SWITCH_STATUS                         :Result:='mmDIG4_DIG_DISPCLK_SWITCH_STATUS';
  mmDIG4_HDMI_CONTROL                                      :Result:='mmDIG4_HDMI_CONTROL';
  mmDIG4_HDMI_STATUS                                       :Result:='mmDIG4_HDMI_STATUS';
  mmDIG4_HDMI_AUDIO_PACKET_CONTROL                         :Result:='mmDIG4_HDMI_AUDIO_PACKET_CONTROL';
  mmDIG4_HDMI_ACR_PACKET_CONTROL                           :Result:='mmDIG4_HDMI_ACR_PACKET_CONTROL';
  mmDIG4_HDMI_VBI_PACKET_CONTROL                           :Result:='mmDIG4_HDMI_VBI_PACKET_CONTROL';
  mmDIG4_HDMI_INFOFRAME_CONTROL0                           :Result:='mmDIG4_HDMI_INFOFRAME_CONTROL0';
  mmDIG4_HDMI_INFOFRAME_CONTROL1                           :Result:='mmDIG4_HDMI_INFOFRAME_CONTROL1';
  mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                      :Result:='mmDIG4_HDMI_GENERIC_PACKET_CONTROL0';
  mmDIG4_HDMI_GC                                           :Result:='mmDIG4_HDMI_GC';
  mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                        :Result:='mmDIG4_AFMT_AUDIO_PACKET_CONTROL2';
  mmDIG4_AFMT_ISRC1_0                                      :Result:='mmDIG4_AFMT_ISRC1_0';
  mmDIG4_AFMT_ISRC1_1                                      :Result:='mmDIG4_AFMT_ISRC1_1';
  mmDIG4_AFMT_ISRC1_2                                      :Result:='mmDIG4_AFMT_ISRC1_2';
  mmDIG4_AFMT_ISRC1_3                                      :Result:='mmDIG4_AFMT_ISRC1_3';
  mmDIG4_AFMT_ISRC1_4                                      :Result:='mmDIG4_AFMT_ISRC1_4';
  mmDIG4_AFMT_ISRC2_0                                      :Result:='mmDIG4_AFMT_ISRC2_0';
  mmDIG4_AFMT_ISRC2_1                                      :Result:='mmDIG4_AFMT_ISRC2_1';
  mmDIG4_AFMT_ISRC2_2                                      :Result:='mmDIG4_AFMT_ISRC2_2';
  mmDIG4_AFMT_ISRC2_3                                      :Result:='mmDIG4_AFMT_ISRC2_3';
  mmDIG4_AFMT_AVI_INFO0                                    :Result:='mmDIG4_AFMT_AVI_INFO0';
  mmDIG4_AFMT_AVI_INFO1                                    :Result:='mmDIG4_AFMT_AVI_INFO1';
  mmDIG4_AFMT_AVI_INFO2                                    :Result:='mmDIG4_AFMT_AVI_INFO2';
  mmDIG4_AFMT_AVI_INFO3                                    :Result:='mmDIG4_AFMT_AVI_INFO3';
  mmDIG4_AFMT_MPEG_INFO0                                   :Result:='mmDIG4_AFMT_MPEG_INFO0';
  mmDIG4_AFMT_MPEG_INFO1                                   :Result:='mmDIG4_AFMT_MPEG_INFO1';
  mmDIG4_AFMT_GENERIC_HDR                                  :Result:='mmDIG4_AFMT_GENERIC_HDR';
  mmDIG4_AFMT_GENERIC_0                                    :Result:='mmDIG4_AFMT_GENERIC_0';
  mmDIG4_AFMT_GENERIC_1                                    :Result:='mmDIG4_AFMT_GENERIC_1';
  mmDIG4_AFMT_GENERIC_2                                    :Result:='mmDIG4_AFMT_GENERIC_2';
  mmDIG4_AFMT_GENERIC_3                                    :Result:='mmDIG4_AFMT_GENERIC_3';
  mmDIG4_AFMT_GENERIC_4                                    :Result:='mmDIG4_AFMT_GENERIC_4';
  mmDIG4_AFMT_GENERIC_5                                    :Result:='mmDIG4_AFMT_GENERIC_5';
  mmDIG4_AFMT_GENERIC_6                                    :Result:='mmDIG4_AFMT_GENERIC_6';
  mmDIG4_AFMT_GENERIC_7                                    :Result:='mmDIG4_AFMT_GENERIC_7';
  mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                      :Result:='mmDIG4_HDMI_GENERIC_PACKET_CONTROL1';
  mmDIG4_HDMI_ACR_32_0                                     :Result:='mmDIG4_HDMI_ACR_32_0';
  mmDIG4_HDMI_ACR_32_1                                     :Result:='mmDIG4_HDMI_ACR_32_1';
  mmDIG4_HDMI_ACR_44_0                                     :Result:='mmDIG4_HDMI_ACR_44_0';
  mmDIG4_HDMI_ACR_44_1                                     :Result:='mmDIG4_HDMI_ACR_44_1';
  mmDIG4_HDMI_ACR_48_0                                     :Result:='mmDIG4_HDMI_ACR_48_0';
  mmDIG4_HDMI_ACR_48_1                                     :Result:='mmDIG4_HDMI_ACR_48_1';
  mmDIG4_HDMI_ACR_STATUS_0                                 :Result:='mmDIG4_HDMI_ACR_STATUS_0';
  mmDIG4_HDMI_ACR_STATUS_1                                 :Result:='mmDIG4_HDMI_ACR_STATUS_1';
  mmDIG4_AFMT_AUDIO_INFO0                                  :Result:='mmDIG4_AFMT_AUDIO_INFO0';
  mmDIG4_AFMT_AUDIO_INFO1                                  :Result:='mmDIG4_AFMT_AUDIO_INFO1';
  mmDIG4_AFMT_60958_0                                      :Result:='mmDIG4_AFMT_60958_0';
  mmDIG4_AFMT_60958_1                                      :Result:='mmDIG4_AFMT_60958_1';
  mmDIG4_AFMT_AUDIO_CRC_CONTROL                            :Result:='mmDIG4_AFMT_AUDIO_CRC_CONTROL';
  mmDIG4_AFMT_RAMP_CONTROL0                                :Result:='mmDIG4_AFMT_RAMP_CONTROL0';
  mmDIG4_AFMT_RAMP_CONTROL1                                :Result:='mmDIG4_AFMT_RAMP_CONTROL1';
  mmDIG4_AFMT_RAMP_CONTROL2                                :Result:='mmDIG4_AFMT_RAMP_CONTROL2';
  mmDIG4_AFMT_RAMP_CONTROL3                                :Result:='mmDIG4_AFMT_RAMP_CONTROL3';
  mmDIG4_AFMT_60958_2                                      :Result:='mmDIG4_AFMT_60958_2';
  mmDIG4_AFMT_AUDIO_CRC_RESULT                             :Result:='mmDIG4_AFMT_AUDIO_CRC_RESULT';
  mmDIG4_AFMT_STATUS                                       :Result:='mmDIG4_AFMT_STATUS';
  mmDIG4_AFMT_AUDIO_PACKET_CONTROL                         :Result:='mmDIG4_AFMT_AUDIO_PACKET_CONTROL';
  mmDIG4_AFMT_VBI_PACKET_CONTROL                           :Result:='mmDIG4_AFMT_VBI_PACKET_CONTROL';
  mmDIG4_AFMT_INFOFRAME_CONTROL0                           :Result:='mmDIG4_AFMT_INFOFRAME_CONTROL0';
  mmDIG4_AFMT_AUDIO_SRC_CONTROL                            :Result:='mmDIG4_AFMT_AUDIO_SRC_CONTROL';
  mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL                           :Result:='mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL';
  mmDIG4_DIG_BE_CNTL                                       :Result:='mmDIG4_DIG_BE_CNTL';
  mmDIG4_DIG_BE_EN_CNTL                                    :Result:='mmDIG4_DIG_BE_EN_CNTL';
  mmDIG4_TMDS_CNTL                                         :Result:='mmDIG4_TMDS_CNTL';
  mmDIG4_TMDS_CONTROL_CHAR                                 :Result:='mmDIG4_TMDS_CONTROL_CHAR';
  mmDIG4_TMDS_CONTROL0_FEEDBACK                            :Result:='mmDIG4_TMDS_CONTROL0_FEEDBACK';
  mmDIG4_TMDS_STEREOSYNC_CTL_SEL                           :Result:='mmDIG4_TMDS_STEREOSYNC_CTL_SEL';
  mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                        :Result:='mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1';
  mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                        :Result:='mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3';
  mmDIG4_TMDS_DEBUG                                        :Result:='mmDIG4_TMDS_DEBUG';
  mmDIG4_TMDS_CTL_BITS                                     :Result:='mmDIG4_TMDS_CTL_BITS';
  mmDIG4_TMDS_DCBALANCER_CONTROL                           :Result:='mmDIG4_TMDS_DCBALANCER_CONTROL';
  mmDIG4_TMDS_CTL0_1_GEN_CNTL                              :Result:='mmDIG4_TMDS_CTL0_1_GEN_CNTL';
  mmDIG4_TMDS_CTL2_3_GEN_CNTL                              :Result:='mmDIG4_TMDS_CTL2_3_GEN_CNTL';
  mmDIG4_LVDS_DATA_CNTL                                    :Result:='mmDIG4_LVDS_DATA_CNTL';
  mmDIG4_DIG_LANE_ENABLE                                   :Result:='mmDIG4_DIG_LANE_ENABLE';
  mmDIG4_DIG_TEST_DEBUG_INDEX                              :Result:='mmDIG4_DIG_TEST_DEBUG_INDEX';
  mmDIG4_DIG_TEST_DEBUG_DATA                               :Result:='mmDIG4_DIG_TEST_DEBUG_DATA';
  mmDIG4_DIG_FE_TEST_DEBUG_INDEX                           :Result:='mmDIG4_DIG_FE_TEST_DEBUG_INDEX';
  mmDIG4_DIG_FE_TEST_DEBUG_DATA                            :Result:='mmDIG4_DIG_FE_TEST_DEBUG_DATA';
  mmDP4_DP_LINK_CNTL                                       :Result:='mmDP4_DP_LINK_CNTL';
  mmDP4_DP_PIXEL_FORMAT                                    :Result:='mmDP4_DP_PIXEL_FORMAT';
  mmDP4_DP_MSA_COLORIMETRY                                 :Result:='mmDP4_DP_MSA_COLORIMETRY';
  mmDP4_DP_CONFIG                                          :Result:='mmDP4_DP_CONFIG';
  mmDP4_DP_VID_STREAM_CNTL                                 :Result:='mmDP4_DP_VID_STREAM_CNTL';
  mmDP4_DP_STEER_FIFO                                      :Result:='mmDP4_DP_STEER_FIFO';
  mmDP4_DP_MSA_MISC                                        :Result:='mmDP4_DP_MSA_MISC';
  mmDP4_DP_VID_TIMING                                      :Result:='mmDP4_DP_VID_TIMING';
  mmDP4_DP_VID_N                                           :Result:='mmDP4_DP_VID_N';
  mmDP4_DP_VID_M                                           :Result:='mmDP4_DP_VID_M';
  mmDP4_DP_LINK_FRAMING_CNTL                               :Result:='mmDP4_DP_LINK_FRAMING_CNTL';
  mmDP4_DP_HBR2_EYE_PATTERN                                :Result:='mmDP4_DP_HBR2_EYE_PATTERN';
  mmDP4_DP_VID_MSA_VBID                                    :Result:='mmDP4_DP_VID_MSA_VBID';
  mmDP4_DP_VID_INTERRUPT_CNTL                              :Result:='mmDP4_DP_VID_INTERRUPT_CNTL';
  mmDP4_DP_DPHY_CNTL                                       :Result:='mmDP4_DP_DPHY_CNTL';
  mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                       :Result:='mmDP4_DP_DPHY_TRAINING_PATTERN_SEL';
  mmDP4_DP_DPHY_SYM0                                       :Result:='mmDP4_DP_DPHY_SYM0';
  mmDP4_DP_DPHY_SYM1                                       :Result:='mmDP4_DP_DPHY_SYM1';
  mmDP4_DP_DPHY_SYM2                                       :Result:='mmDP4_DP_DPHY_SYM2';
  mmDP4_DP_DPHY_8B10B_CNTL                                 :Result:='mmDP4_DP_DPHY_8B10B_CNTL';
  mmDP4_DP_DPHY_PRBS_CNTL                                  :Result:='mmDP4_DP_DPHY_PRBS_CNTL';
  mmDP4_DP_DPHY_CRC_EN                                     :Result:='mmDP4_DP_DPHY_CRC_EN';
  mmDP4_DP_DPHY_CRC_CNTL                                   :Result:='mmDP4_DP_DPHY_CRC_CNTL';
  mmDP4_DP_DPHY_CRC_RESULT                                 :Result:='mmDP4_DP_DPHY_CRC_RESULT';
  mmDP4_DP_DPHY_CRC_MST_CNTL                               :Result:='mmDP4_DP_DPHY_CRC_MST_CNTL';
  mmDP4_DP_DPHY_CRC_MST_STATUS                             :Result:='mmDP4_DP_DPHY_CRC_MST_STATUS';
  mmDP4_DP_DPHY_FAST_TRAINING                              :Result:='mmDP4_DP_DPHY_FAST_TRAINING';
  mmDP4_DP_DPHY_FAST_TRAINING_STATUS                       :Result:='mmDP4_DP_DPHY_FAST_TRAINING_STATUS';
  mmDP4_DP_MSA_V_TIMING_OVERRIDE1                          :Result:='mmDP4_DP_MSA_V_TIMING_OVERRIDE1';
  mmDP4_DP_MSA_V_TIMING_OVERRIDE2                          :Result:='mmDP4_DP_MSA_V_TIMING_OVERRIDE2';
  mmDP4_DP_SEC_CNTL                                        :Result:='mmDP4_DP_SEC_CNTL';
  mmDP4_DP_SEC_CNTL1                                       :Result:='mmDP4_DP_SEC_CNTL1';
  mmDP4_DP_SEC_FRAMING1                                    :Result:='mmDP4_DP_SEC_FRAMING1';
  mmDP4_DP_SEC_FRAMING2                                    :Result:='mmDP4_DP_SEC_FRAMING2';
  mmDP4_DP_SEC_FRAMING3                                    :Result:='mmDP4_DP_SEC_FRAMING3';
  mmDP4_DP_SEC_FRAMING4                                    :Result:='mmDP4_DP_SEC_FRAMING4';
  mmDP4_DP_SEC_AUD_N                                       :Result:='mmDP4_DP_SEC_AUD_N';
  mmDP4_DP_SEC_AUD_N_READBACK                              :Result:='mmDP4_DP_SEC_AUD_N_READBACK';
  mmDP4_DP_SEC_AUD_M                                       :Result:='mmDP4_DP_SEC_AUD_M';
  mmDP4_DP_SEC_AUD_M_READBACK                              :Result:='mmDP4_DP_SEC_AUD_M_READBACK';
  mmDP4_DP_SEC_TIMESTAMP                                   :Result:='mmDP4_DP_SEC_TIMESTAMP';
  mmDP4_DP_SEC_PACKET_CNTL                                 :Result:='mmDP4_DP_SEC_PACKET_CNTL';
  mmDP4_DP_MSE_RATE_CNTL                                   :Result:='mmDP4_DP_MSE_RATE_CNTL';
  mmDP4_DP_MSE_RATE_UPDATE                                 :Result:='mmDP4_DP_MSE_RATE_UPDATE';
  mmDP4_DP_MSE_SAT0                                        :Result:='mmDP4_DP_MSE_SAT0';
  mmDP4_DP_MSE_SAT1                                        :Result:='mmDP4_DP_MSE_SAT1';
  mmDP4_DP_MSE_SAT2                                        :Result:='mmDP4_DP_MSE_SAT2';
  mmDP4_DP_MSE_SAT_UPDATE                                  :Result:='mmDP4_DP_MSE_SAT_UPDATE';
  mmDP4_DP_MSE_LINK_TIMING                                 :Result:='mmDP4_DP_MSE_LINK_TIMING';
  mmDP4_DP_MSE_MISC_CNTL                                   :Result:='mmDP4_DP_MSE_MISC_CNTL';
  mmDP4_DP_TEST_DEBUG_INDEX                                :Result:='mmDP4_DP_TEST_DEBUG_INDEX';
  mmDP4_DP_TEST_DEBUG_DATA                                 :Result:='mmDP4_DP_TEST_DEBUG_DATA';
  mmDP4_DP_FE_TEST_DEBUG_INDEX                             :Result:='mmDP4_DP_FE_TEST_DEBUG_INDEX';
  mmDP4_DP_FE_TEST_DEBUG_DATA                              :Result:='mmDP4_DP_FE_TEST_DEBUG_DATA';
  mmDIG5_DIG_FE_CNTL                                       :Result:='mmDIG5_DIG_FE_CNTL';
  mmDIG5_DIG_OUTPUT_CRC_CNTL                               :Result:='mmDIG5_DIG_OUTPUT_CRC_CNTL';
  mmDIG5_DIG_OUTPUT_CRC_RESULT                             :Result:='mmDIG5_DIG_OUTPUT_CRC_RESULT';
  mmDIG5_DIG_CLOCK_PATTERN                                 :Result:='mmDIG5_DIG_CLOCK_PATTERN';
  mmDIG5_DIG_TEST_PATTERN                                  :Result:='mmDIG5_DIG_TEST_PATTERN';
  mmDIG5_DIG_RANDOM_PATTERN_SEED                           :Result:='mmDIG5_DIG_RANDOM_PATTERN_SEED';
  mmDIG5_DIG_FIFO_STATUS                                   :Result:='mmDIG5_DIG_FIFO_STATUS';
  mmDIG5_DIG_DISPCLK_SWITCH_CNTL                           :Result:='mmDIG5_DIG_DISPCLK_SWITCH_CNTL';
  mmDIG5_DIG_DISPCLK_SWITCH_STATUS                         :Result:='mmDIG5_DIG_DISPCLK_SWITCH_STATUS';
  mmDIG5_HDMI_CONTROL                                      :Result:='mmDIG5_HDMI_CONTROL';
  mmDIG5_HDMI_STATUS                                       :Result:='mmDIG5_HDMI_STATUS';
  mmDIG5_HDMI_AUDIO_PACKET_CONTROL                         :Result:='mmDIG5_HDMI_AUDIO_PACKET_CONTROL';
  mmDIG5_HDMI_ACR_PACKET_CONTROL                           :Result:='mmDIG5_HDMI_ACR_PACKET_CONTROL';
  mmDIG5_HDMI_VBI_PACKET_CONTROL                           :Result:='mmDIG5_HDMI_VBI_PACKET_CONTROL';
  mmDIG5_HDMI_INFOFRAME_CONTROL0                           :Result:='mmDIG5_HDMI_INFOFRAME_CONTROL0';
  mmDIG5_HDMI_INFOFRAME_CONTROL1                           :Result:='mmDIG5_HDMI_INFOFRAME_CONTROL1';
  mmDIG5_HDMI_GENERIC_PACKET_CONTROL0                      :Result:='mmDIG5_HDMI_GENERIC_PACKET_CONTROL0';
  mmDIG5_HDMI_GC                                           :Result:='mmDIG5_HDMI_GC';
  mmDIG5_AFMT_AUDIO_PACKET_CONTROL2                        :Result:='mmDIG5_AFMT_AUDIO_PACKET_CONTROL2';
  mmDIG5_AFMT_ISRC1_0                                      :Result:='mmDIG5_AFMT_ISRC1_0';
  mmDIG5_AFMT_ISRC1_1                                      :Result:='mmDIG5_AFMT_ISRC1_1';
  mmDIG5_AFMT_ISRC1_2                                      :Result:='mmDIG5_AFMT_ISRC1_2';
  mmDIG5_AFMT_ISRC1_3                                      :Result:='mmDIG5_AFMT_ISRC1_3';
  mmDIG5_AFMT_ISRC1_4                                      :Result:='mmDIG5_AFMT_ISRC1_4';
  mmDIG5_AFMT_ISRC2_0                                      :Result:='mmDIG5_AFMT_ISRC2_0';
  mmDIG5_AFMT_ISRC2_1                                      :Result:='mmDIG5_AFMT_ISRC2_1';
  mmDIG5_AFMT_ISRC2_2                                      :Result:='mmDIG5_AFMT_ISRC2_2';
  mmDIG5_AFMT_ISRC2_3                                      :Result:='mmDIG5_AFMT_ISRC2_3';
  mmDIG5_AFMT_AVI_INFO0                                    :Result:='mmDIG5_AFMT_AVI_INFO0';
  mmDIG5_AFMT_AVI_INFO1                                    :Result:='mmDIG5_AFMT_AVI_INFO1';
  mmDIG5_AFMT_AVI_INFO2                                    :Result:='mmDIG5_AFMT_AVI_INFO2';
  mmDIG5_AFMT_AVI_INFO3                                    :Result:='mmDIG5_AFMT_AVI_INFO3';
  mmDIG5_AFMT_MPEG_INFO0                                   :Result:='mmDIG5_AFMT_MPEG_INFO0';
  mmDIG5_AFMT_MPEG_INFO1                                   :Result:='mmDIG5_AFMT_MPEG_INFO1';
  mmDIG5_AFMT_GENERIC_HDR                                  :Result:='mmDIG5_AFMT_GENERIC_HDR';
  mmDIG5_AFMT_GENERIC_0                                    :Result:='mmDIG5_AFMT_GENERIC_0';
  mmDIG5_AFMT_GENERIC_1                                    :Result:='mmDIG5_AFMT_GENERIC_1';
  mmDIG5_AFMT_GENERIC_2                                    :Result:='mmDIG5_AFMT_GENERIC_2';
  mmDIG5_AFMT_GENERIC_3                                    :Result:='mmDIG5_AFMT_GENERIC_3';
  mmDIG5_AFMT_GENERIC_4                                    :Result:='mmDIG5_AFMT_GENERIC_4';
  mmDIG5_AFMT_GENERIC_5                                    :Result:='mmDIG5_AFMT_GENERIC_5';
  mmDIG5_AFMT_GENERIC_6                                    :Result:='mmDIG5_AFMT_GENERIC_6';
  mmDIG5_AFMT_GENERIC_7                                    :Result:='mmDIG5_AFMT_GENERIC_7';
  mmDIG5_HDMI_GENERIC_PACKET_CONTROL1                      :Result:='mmDIG5_HDMI_GENERIC_PACKET_CONTROL1';
  mmDIG5_HDMI_ACR_32_0                                     :Result:='mmDIG5_HDMI_ACR_32_0';
  mmDIG5_HDMI_ACR_32_1                                     :Result:='mmDIG5_HDMI_ACR_32_1';
  mmDIG5_HDMI_ACR_44_0                                     :Result:='mmDIG5_HDMI_ACR_44_0';
  mmDIG5_HDMI_ACR_44_1                                     :Result:='mmDIG5_HDMI_ACR_44_1';
  mmDIG5_HDMI_ACR_48_0                                     :Result:='mmDIG5_HDMI_ACR_48_0';
  mmDIG5_HDMI_ACR_48_1                                     :Result:='mmDIG5_HDMI_ACR_48_1';
  mmDIG5_HDMI_ACR_STATUS_0                                 :Result:='mmDIG5_HDMI_ACR_STATUS_0';
  mmDIG5_HDMI_ACR_STATUS_1                                 :Result:='mmDIG5_HDMI_ACR_STATUS_1';
  mmDIG5_AFMT_AUDIO_INFO0                                  :Result:='mmDIG5_AFMT_AUDIO_INFO0';
  mmDIG5_AFMT_AUDIO_INFO1                                  :Result:='mmDIG5_AFMT_AUDIO_INFO1';
  mmDIG5_AFMT_60958_0                                      :Result:='mmDIG5_AFMT_60958_0';
  mmDIG5_AFMT_60958_1                                      :Result:='mmDIG5_AFMT_60958_1';
  mmDIG5_AFMT_AUDIO_CRC_CONTROL                            :Result:='mmDIG5_AFMT_AUDIO_CRC_CONTROL';
  mmDIG5_AFMT_RAMP_CONTROL0                                :Result:='mmDIG5_AFMT_RAMP_CONTROL0';
  mmDIG5_AFMT_RAMP_CONTROL1                                :Result:='mmDIG5_AFMT_RAMP_CONTROL1';
  mmDIG5_AFMT_RAMP_CONTROL2                                :Result:='mmDIG5_AFMT_RAMP_CONTROL2';
  mmDIG5_AFMT_RAMP_CONTROL3                                :Result:='mmDIG5_AFMT_RAMP_CONTROL3';
  mmDIG5_AFMT_60958_2                                      :Result:='mmDIG5_AFMT_60958_2';
  mmDIG5_AFMT_AUDIO_CRC_RESULT                             :Result:='mmDIG5_AFMT_AUDIO_CRC_RESULT';
  mmDIG5_AFMT_STATUS                                       :Result:='mmDIG5_AFMT_STATUS';
  mmDIG5_AFMT_AUDIO_PACKET_CONTROL                         :Result:='mmDIG5_AFMT_AUDIO_PACKET_CONTROL';
  mmDIG5_AFMT_VBI_PACKET_CONTROL                           :Result:='mmDIG5_AFMT_VBI_PACKET_CONTROL';
  mmDIG5_AFMT_INFOFRAME_CONTROL0                           :Result:='mmDIG5_AFMT_INFOFRAME_CONTROL0';
  mmDIG5_AFMT_AUDIO_SRC_CONTROL                            :Result:='mmDIG5_AFMT_AUDIO_SRC_CONTROL';
  mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL                           :Result:='mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL';
  mmDIG5_DIG_BE_CNTL                                       :Result:='mmDIG5_DIG_BE_CNTL';
  mmDIG5_DIG_BE_EN_CNTL                                    :Result:='mmDIG5_DIG_BE_EN_CNTL';
  mmDIG5_TMDS_CNTL                                         :Result:='mmDIG5_TMDS_CNTL';
  mmDIG5_TMDS_CONTROL_CHAR                                 :Result:='mmDIG5_TMDS_CONTROL_CHAR';
  mmDIG5_TMDS_CONTROL0_FEEDBACK                            :Result:='mmDIG5_TMDS_CONTROL0_FEEDBACK';
  mmDIG5_TMDS_STEREOSYNC_CTL_SEL                           :Result:='mmDIG5_TMDS_STEREOSYNC_CTL_SEL';
  mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1                        :Result:='mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1';
  mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3                        :Result:='mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3';
  mmDIG5_TMDS_DEBUG                                        :Result:='mmDIG5_TMDS_DEBUG';
  mmDIG5_TMDS_CTL_BITS                                     :Result:='mmDIG5_TMDS_CTL_BITS';
  mmDIG5_TMDS_DCBALANCER_CONTROL                           :Result:='mmDIG5_TMDS_DCBALANCER_CONTROL';
  mmDIG5_TMDS_CTL0_1_GEN_CNTL                              :Result:='mmDIG5_TMDS_CTL0_1_GEN_CNTL';
  mmDIG5_TMDS_CTL2_3_GEN_CNTL                              :Result:='mmDIG5_TMDS_CTL2_3_GEN_CNTL';
  mmDIG5_LVDS_DATA_CNTL                                    :Result:='mmDIG5_LVDS_DATA_CNTL';
  mmDIG5_DIG_LANE_ENABLE                                   :Result:='mmDIG5_DIG_LANE_ENABLE';
  mmDIG5_DIG_TEST_DEBUG_INDEX                              :Result:='mmDIG5_DIG_TEST_DEBUG_INDEX';
  mmDIG5_DIG_TEST_DEBUG_DATA                               :Result:='mmDIG5_DIG_TEST_DEBUG_DATA';
  mmDIG5_DIG_FE_TEST_DEBUG_INDEX                           :Result:='mmDIG5_DIG_FE_TEST_DEBUG_INDEX';
  mmDIG5_DIG_FE_TEST_DEBUG_DATA                            :Result:='mmDIG5_DIG_FE_TEST_DEBUG_DATA';
  mmDP5_DP_LINK_CNTL                                       :Result:='mmDP5_DP_LINK_CNTL';
  mmDP5_DP_PIXEL_FORMAT                                    :Result:='mmDP5_DP_PIXEL_FORMAT';
  mmDP5_DP_MSA_COLORIMETRY                                 :Result:='mmDP5_DP_MSA_COLORIMETRY';
  mmDP5_DP_CONFIG                                          :Result:='mmDP5_DP_CONFIG';
  mmDP5_DP_VID_STREAM_CNTL                                 :Result:='mmDP5_DP_VID_STREAM_CNTL';
  mmDP5_DP_STEER_FIFO                                      :Result:='mmDP5_DP_STEER_FIFO';
  mmDP5_DP_MSA_MISC                                        :Result:='mmDP5_DP_MSA_MISC';
  mmDP5_DP_VID_TIMING                                      :Result:='mmDP5_DP_VID_TIMING';
  mmDP5_DP_VID_N                                           :Result:='mmDP5_DP_VID_N';
  mmDP5_DP_VID_M                                           :Result:='mmDP5_DP_VID_M';
  mmDP5_DP_LINK_FRAMING_CNTL                               :Result:='mmDP5_DP_LINK_FRAMING_CNTL';
  mmDP5_DP_HBR2_EYE_PATTERN                                :Result:='mmDP5_DP_HBR2_EYE_PATTERN';
  mmDP5_DP_VID_MSA_VBID                                    :Result:='mmDP5_DP_VID_MSA_VBID';
  mmDP5_DP_VID_INTERRUPT_CNTL                              :Result:='mmDP5_DP_VID_INTERRUPT_CNTL';
  mmDP5_DP_DPHY_CNTL                                       :Result:='mmDP5_DP_DPHY_CNTL';
  mmDP5_DP_DPHY_TRAINING_PATTERN_SEL                       :Result:='mmDP5_DP_DPHY_TRAINING_PATTERN_SEL';
  mmDP5_DP_DPHY_SYM0                                       :Result:='mmDP5_DP_DPHY_SYM0';
  mmDP5_DP_DPHY_SYM1                                       :Result:='mmDP5_DP_DPHY_SYM1';
  mmDP5_DP_DPHY_SYM2                                       :Result:='mmDP5_DP_DPHY_SYM2';
  mmDP5_DP_DPHY_8B10B_CNTL                                 :Result:='mmDP5_DP_DPHY_8B10B_CNTL';
  mmDP5_DP_DPHY_PRBS_CNTL                                  :Result:='mmDP5_DP_DPHY_PRBS_CNTL';
  mmDP5_DP_DPHY_CRC_EN                                     :Result:='mmDP5_DP_DPHY_CRC_EN';
  mmDP5_DP_DPHY_CRC_CNTL                                   :Result:='mmDP5_DP_DPHY_CRC_CNTL';
  mmDP5_DP_DPHY_CRC_RESULT                                 :Result:='mmDP5_DP_DPHY_CRC_RESULT';
  mmDP5_DP_DPHY_CRC_MST_CNTL                               :Result:='mmDP5_DP_DPHY_CRC_MST_CNTL';
  mmDP5_DP_DPHY_CRC_MST_STATUS                             :Result:='mmDP5_DP_DPHY_CRC_MST_STATUS';
  mmDP5_DP_DPHY_FAST_TRAINING                              :Result:='mmDP5_DP_DPHY_FAST_TRAINING';
  mmDP5_DP_DPHY_FAST_TRAINING_STATUS                       :Result:='mmDP5_DP_DPHY_FAST_TRAINING_STATUS';
  mmDP5_DP_MSA_V_TIMING_OVERRIDE1                          :Result:='mmDP5_DP_MSA_V_TIMING_OVERRIDE1';
  mmDP5_DP_MSA_V_TIMING_OVERRIDE2                          :Result:='mmDP5_DP_MSA_V_TIMING_OVERRIDE2';
  mmDP5_DP_SEC_CNTL                                        :Result:='mmDP5_DP_SEC_CNTL';
  mmDP5_DP_SEC_CNTL1                                       :Result:='mmDP5_DP_SEC_CNTL1';
  mmDP5_DP_SEC_FRAMING1                                    :Result:='mmDP5_DP_SEC_FRAMING1';
  mmDP5_DP_SEC_FRAMING2                                    :Result:='mmDP5_DP_SEC_FRAMING2';
  mmDP5_DP_SEC_FRAMING3                                    :Result:='mmDP5_DP_SEC_FRAMING3';
  mmDP5_DP_SEC_FRAMING4                                    :Result:='mmDP5_DP_SEC_FRAMING4';
  mmDP5_DP_SEC_AUD_N                                       :Result:='mmDP5_DP_SEC_AUD_N';
  mmDP5_DP_SEC_AUD_N_READBACK                              :Result:='mmDP5_DP_SEC_AUD_N_READBACK';
  mmDP5_DP_SEC_AUD_M                                       :Result:='mmDP5_DP_SEC_AUD_M';
  mmDP5_DP_SEC_AUD_M_READBACK                              :Result:='mmDP5_DP_SEC_AUD_M_READBACK';
  mmDP5_DP_SEC_TIMESTAMP                                   :Result:='mmDP5_DP_SEC_TIMESTAMP';
  mmDP5_DP_SEC_PACKET_CNTL                                 :Result:='mmDP5_DP_SEC_PACKET_CNTL';
  mmDP5_DP_MSE_RATE_CNTL                                   :Result:='mmDP5_DP_MSE_RATE_CNTL';
  mmDP5_DP_MSE_RATE_UPDATE                                 :Result:='mmDP5_DP_MSE_RATE_UPDATE';
  mmDP5_DP_MSE_SAT0                                        :Result:='mmDP5_DP_MSE_SAT0';
  mmDP5_DP_MSE_SAT1                                        :Result:='mmDP5_DP_MSE_SAT1';
  mmDP5_DP_MSE_SAT2                                        :Result:='mmDP5_DP_MSE_SAT2';
  mmDP5_DP_MSE_SAT_UPDATE                                  :Result:='mmDP5_DP_MSE_SAT_UPDATE';
  mmDP5_DP_MSE_LINK_TIMING                                 :Result:='mmDP5_DP_MSE_LINK_TIMING';
  mmDP5_DP_MSE_MISC_CNTL                                   :Result:='mmDP5_DP_MSE_MISC_CNTL';
  mmDP5_DP_TEST_DEBUG_INDEX                                :Result:='mmDP5_DP_TEST_DEBUG_INDEX';
  mmDP5_DP_TEST_DEBUG_DATA                                 :Result:='mmDP5_DP_TEST_DEBUG_DATA';
  mmDP5_DP_FE_TEST_DEBUG_INDEX                             :Result:='mmDP5_DP_FE_TEST_DEBUG_INDEX';
  mmDP5_DP_FE_TEST_DEBUG_DATA                              :Result:='mmDP5_DP_FE_TEST_DEBUG_DATA';
  mmDIG6_DIG_FE_CNTL                                       :Result:='mmDIG6_DIG_FE_CNTL';
  mmDIG6_DIG_OUTPUT_CRC_CNTL                               :Result:='mmDIG6_DIG_OUTPUT_CRC_CNTL';
  mmDIG6_DIG_OUTPUT_CRC_RESULT                             :Result:='mmDIG6_DIG_OUTPUT_CRC_RESULT';
  mmDIG6_DIG_CLOCK_PATTERN                                 :Result:='mmDIG6_DIG_CLOCK_PATTERN';
  mmDIG6_DIG_TEST_PATTERN                                  :Result:='mmDIG6_DIG_TEST_PATTERN';
  mmDIG6_DIG_RANDOM_PATTERN_SEED                           :Result:='mmDIG6_DIG_RANDOM_PATTERN_SEED';
  mmDIG6_DIG_FIFO_STATUS                                   :Result:='mmDIG6_DIG_FIFO_STATUS';
  mmDIG6_DIG_DISPCLK_SWITCH_CNTL                           :Result:='mmDIG6_DIG_DISPCLK_SWITCH_CNTL';
  mmDIG6_DIG_DISPCLK_SWITCH_STATUS                         :Result:='mmDIG6_DIG_DISPCLK_SWITCH_STATUS';
  mmDIG6_HDMI_CONTROL                                      :Result:='mmDIG6_HDMI_CONTROL';
  mmDIG6_HDMI_STATUS                                       :Result:='mmDIG6_HDMI_STATUS';
  mmDIG6_HDMI_AUDIO_PACKET_CONTROL                         :Result:='mmDIG6_HDMI_AUDIO_PACKET_CONTROL';
  mmDIG6_HDMI_ACR_PACKET_CONTROL                           :Result:='mmDIG6_HDMI_ACR_PACKET_CONTROL';
  mmDIG6_HDMI_VBI_PACKET_CONTROL                           :Result:='mmDIG6_HDMI_VBI_PACKET_CONTROL';
  mmDIG6_HDMI_INFOFRAME_CONTROL0                           :Result:='mmDIG6_HDMI_INFOFRAME_CONTROL0';
  mmDIG6_HDMI_INFOFRAME_CONTROL1                           :Result:='mmDIG6_HDMI_INFOFRAME_CONTROL1';
  mmDIG6_HDMI_GENERIC_PACKET_CONTROL0                      :Result:='mmDIG6_HDMI_GENERIC_PACKET_CONTROL0';
  mmDIG6_HDMI_GC                                           :Result:='mmDIG6_HDMI_GC';
  mmDIG6_AFMT_AUDIO_PACKET_CONTROL2                        :Result:='mmDIG6_AFMT_AUDIO_PACKET_CONTROL2';
  mmDIG6_AFMT_ISRC1_0                                      :Result:='mmDIG6_AFMT_ISRC1_0';
  mmDIG6_AFMT_ISRC1_1                                      :Result:='mmDIG6_AFMT_ISRC1_1';
  mmDIG6_AFMT_ISRC1_2                                      :Result:='mmDIG6_AFMT_ISRC1_2';
  mmDIG6_AFMT_ISRC1_3                                      :Result:='mmDIG6_AFMT_ISRC1_3';
  mmDIG6_AFMT_ISRC1_4                                      :Result:='mmDIG6_AFMT_ISRC1_4';
  mmDIG6_AFMT_ISRC2_0                                      :Result:='mmDIG6_AFMT_ISRC2_0';
  mmDIG6_AFMT_ISRC2_1                                      :Result:='mmDIG6_AFMT_ISRC2_1';
  mmDIG6_AFMT_ISRC2_2                                      :Result:='mmDIG6_AFMT_ISRC2_2';
  mmDIG6_AFMT_ISRC2_3                                      :Result:='mmDIG6_AFMT_ISRC2_3';
  mmDIG6_AFMT_AVI_INFO0                                    :Result:='mmDIG6_AFMT_AVI_INFO0';
  mmDIG6_AFMT_AVI_INFO1                                    :Result:='mmDIG6_AFMT_AVI_INFO1';
  mmDIG6_AFMT_AVI_INFO2                                    :Result:='mmDIG6_AFMT_AVI_INFO2';
  mmDIG6_AFMT_AVI_INFO3                                    :Result:='mmDIG6_AFMT_AVI_INFO3';
  mmDIG6_AFMT_MPEG_INFO0                                   :Result:='mmDIG6_AFMT_MPEG_INFO0';
  mmDIG6_AFMT_MPEG_INFO1                                   :Result:='mmDIG6_AFMT_MPEG_INFO1';
  mmDIG6_AFMT_GENERIC_HDR                                  :Result:='mmDIG6_AFMT_GENERIC_HDR';
  mmDIG6_AFMT_GENERIC_0                                    :Result:='mmDIG6_AFMT_GENERIC_0';
  mmDIG6_AFMT_GENERIC_1                                    :Result:='mmDIG6_AFMT_GENERIC_1';
  mmDIG6_AFMT_GENERIC_2                                    :Result:='mmDIG6_AFMT_GENERIC_2';
  mmDIG6_AFMT_GENERIC_3                                    :Result:='mmDIG6_AFMT_GENERIC_3';
  mmDIG6_AFMT_GENERIC_4                                    :Result:='mmDIG6_AFMT_GENERIC_4';
  mmDIG6_AFMT_GENERIC_5                                    :Result:='mmDIG6_AFMT_GENERIC_5';
  mmDIG6_AFMT_GENERIC_6                                    :Result:='mmDIG6_AFMT_GENERIC_6';
  mmDIG6_AFMT_GENERIC_7                                    :Result:='mmDIG6_AFMT_GENERIC_7';
  mmDIG6_HDMI_GENERIC_PACKET_CONTROL1                      :Result:='mmDIG6_HDMI_GENERIC_PACKET_CONTROL1';
  mmDIG6_HDMI_ACR_32_0                                     :Result:='mmDIG6_HDMI_ACR_32_0';
  mmDIG6_HDMI_ACR_32_1                                     :Result:='mmDIG6_HDMI_ACR_32_1';
  mmDIG6_HDMI_ACR_44_0                                     :Result:='mmDIG6_HDMI_ACR_44_0';
  mmDIG6_HDMI_ACR_44_1                                     :Result:='mmDIG6_HDMI_ACR_44_1';
  mmDIG6_HDMI_ACR_48_0                                     :Result:='mmDIG6_HDMI_ACR_48_0';
  mmDIG6_HDMI_ACR_48_1                                     :Result:='mmDIG6_HDMI_ACR_48_1';
  mmDIG6_HDMI_ACR_STATUS_0                                 :Result:='mmDIG6_HDMI_ACR_STATUS_0';
  mmDIG6_HDMI_ACR_STATUS_1                                 :Result:='mmDIG6_HDMI_ACR_STATUS_1';
  mmDIG6_AFMT_AUDIO_INFO0                                  :Result:='mmDIG6_AFMT_AUDIO_INFO0';
  mmDIG6_AFMT_AUDIO_INFO1                                  :Result:='mmDIG6_AFMT_AUDIO_INFO1';
  mmDIG6_AFMT_60958_0                                      :Result:='mmDIG6_AFMT_60958_0';
  mmDIG6_AFMT_60958_1                                      :Result:='mmDIG6_AFMT_60958_1';
  mmDIG6_AFMT_AUDIO_CRC_CONTROL                            :Result:='mmDIG6_AFMT_AUDIO_CRC_CONTROL';
  mmDIG6_AFMT_RAMP_CONTROL0                                :Result:='mmDIG6_AFMT_RAMP_CONTROL0';
  mmDIG6_AFMT_RAMP_CONTROL1                                :Result:='mmDIG6_AFMT_RAMP_CONTROL1';
  mmDIG6_AFMT_RAMP_CONTROL2                                :Result:='mmDIG6_AFMT_RAMP_CONTROL2';
  mmDIG6_AFMT_RAMP_CONTROL3                                :Result:='mmDIG6_AFMT_RAMP_CONTROL3';
  mmDIG6_AFMT_60958_2                                      :Result:='mmDIG6_AFMT_60958_2';
  mmDIG6_AFMT_AUDIO_CRC_RESULT                             :Result:='mmDIG6_AFMT_AUDIO_CRC_RESULT';
  mmDIG6_AFMT_STATUS                                       :Result:='mmDIG6_AFMT_STATUS';
  mmDIG6_AFMT_AUDIO_PACKET_CONTROL                         :Result:='mmDIG6_AFMT_AUDIO_PACKET_CONTROL';
  mmDIG6_AFMT_VBI_PACKET_CONTROL                           :Result:='mmDIG6_AFMT_VBI_PACKET_CONTROL';
  mmDIG6_AFMT_INFOFRAME_CONTROL0                           :Result:='mmDIG6_AFMT_INFOFRAME_CONTROL0';
  mmDIG6_AFMT_AUDIO_SRC_CONTROL                            :Result:='mmDIG6_AFMT_AUDIO_SRC_CONTROL';
  mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL                           :Result:='mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL';
  mmDIG6_DIG_BE_CNTL                                       :Result:='mmDIG6_DIG_BE_CNTL';
  mmDIG6_DIG_BE_EN_CNTL                                    :Result:='mmDIG6_DIG_BE_EN_CNTL';
  mmDIG6_TMDS_CNTL                                         :Result:='mmDIG6_TMDS_CNTL';
  mmDIG6_TMDS_CONTROL_CHAR                                 :Result:='mmDIG6_TMDS_CONTROL_CHAR';
  mmDIG6_TMDS_CONTROL0_FEEDBACK                            :Result:='mmDIG6_TMDS_CONTROL0_FEEDBACK';
  mmDIG6_TMDS_STEREOSYNC_CTL_SEL                           :Result:='mmDIG6_TMDS_STEREOSYNC_CTL_SEL';
  mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1                        :Result:='mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1';
  mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3                        :Result:='mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3';
  mmDIG6_TMDS_DEBUG                                        :Result:='mmDIG6_TMDS_DEBUG';
  mmDIG6_TMDS_CTL_BITS                                     :Result:='mmDIG6_TMDS_CTL_BITS';
  mmDIG6_TMDS_DCBALANCER_CONTROL                           :Result:='mmDIG6_TMDS_DCBALANCER_CONTROL';
  mmDIG6_TMDS_CTL0_1_GEN_CNTL                              :Result:='mmDIG6_TMDS_CTL0_1_GEN_CNTL';
  mmDIG6_TMDS_CTL2_3_GEN_CNTL                              :Result:='mmDIG6_TMDS_CTL2_3_GEN_CNTL';
  mmDIG6_LVDS_DATA_CNTL                                    :Result:='mmDIG6_LVDS_DATA_CNTL';
  mmDIG6_DIG_LANE_ENABLE                                   :Result:='mmDIG6_DIG_LANE_ENABLE';
  mmDIG6_DIG_TEST_DEBUG_INDEX                              :Result:='mmDIG6_DIG_TEST_DEBUG_INDEX';
  mmDIG6_DIG_TEST_DEBUG_DATA                               :Result:='mmDIG6_DIG_TEST_DEBUG_DATA';
  mmDIG6_DIG_FE_TEST_DEBUG_INDEX                           :Result:='mmDIG6_DIG_FE_TEST_DEBUG_INDEX';
  mmDIG6_DIG_FE_TEST_DEBUG_DATA                            :Result:='mmDIG6_DIG_FE_TEST_DEBUG_DATA';
  mmDP6_DP_LINK_CNTL                                       :Result:='mmDP6_DP_LINK_CNTL';
  mmDP6_DP_PIXEL_FORMAT                                    :Result:='mmDP6_DP_PIXEL_FORMAT';
  mmDP6_DP_MSA_COLORIMETRY                                 :Result:='mmDP6_DP_MSA_COLORIMETRY';
  mmDP6_DP_CONFIG                                          :Result:='mmDP6_DP_CONFIG';
  mmDP6_DP_VID_STREAM_CNTL                                 :Result:='mmDP6_DP_VID_STREAM_CNTL';
  mmDP6_DP_STEER_FIFO                                      :Result:='mmDP6_DP_STEER_FIFO';
  mmDP6_DP_MSA_MISC                                        :Result:='mmDP6_DP_MSA_MISC';
  mmDP6_DP_VID_TIMING                                      :Result:='mmDP6_DP_VID_TIMING';
  mmDP6_DP_VID_N                                           :Result:='mmDP6_DP_VID_N';
  mmDP6_DP_VID_M                                           :Result:='mmDP6_DP_VID_M';
  mmDP6_DP_LINK_FRAMING_CNTL                               :Result:='mmDP6_DP_LINK_FRAMING_CNTL';
  mmDP6_DP_HBR2_EYE_PATTERN                                :Result:='mmDP6_DP_HBR2_EYE_PATTERN';
  mmDP6_DP_VID_MSA_VBID                                    :Result:='mmDP6_DP_VID_MSA_VBID';
  mmDP6_DP_VID_INTERRUPT_CNTL                              :Result:='mmDP6_DP_VID_INTERRUPT_CNTL';
  mmDP6_DP_DPHY_CNTL                                       :Result:='mmDP6_DP_DPHY_CNTL';
  mmDP6_DP_DPHY_TRAINING_PATTERN_SEL                       :Result:='mmDP6_DP_DPHY_TRAINING_PATTERN_SEL';
  mmDP6_DP_DPHY_SYM0                                       :Result:='mmDP6_DP_DPHY_SYM0';
  mmDP6_DP_DPHY_SYM1                                       :Result:='mmDP6_DP_DPHY_SYM1';
  mmDP6_DP_DPHY_SYM2                                       :Result:='mmDP6_DP_DPHY_SYM2';
  mmDP6_DP_DPHY_8B10B_CNTL                                 :Result:='mmDP6_DP_DPHY_8B10B_CNTL';
  mmDP6_DP_DPHY_PRBS_CNTL                                  :Result:='mmDP6_DP_DPHY_PRBS_CNTL';
  mmDP6_DP_DPHY_CRC_EN                                     :Result:='mmDP6_DP_DPHY_CRC_EN';
  mmDP6_DP_DPHY_CRC_CNTL                                   :Result:='mmDP6_DP_DPHY_CRC_CNTL';
  mmDP6_DP_DPHY_CRC_RESULT                                 :Result:='mmDP6_DP_DPHY_CRC_RESULT';
  mmDP6_DP_DPHY_CRC_MST_CNTL                               :Result:='mmDP6_DP_DPHY_CRC_MST_CNTL';
  mmDP6_DP_DPHY_CRC_MST_STATUS                             :Result:='mmDP6_DP_DPHY_CRC_MST_STATUS';
  mmDP6_DP_DPHY_FAST_TRAINING                              :Result:='mmDP6_DP_DPHY_FAST_TRAINING';
  mmDP6_DP_DPHY_FAST_TRAINING_STATUS                       :Result:='mmDP6_DP_DPHY_FAST_TRAINING_STATUS';
  mmDP6_DP_MSA_V_TIMING_OVERRIDE1                          :Result:='mmDP6_DP_MSA_V_TIMING_OVERRIDE1';
  mmDP6_DP_MSA_V_TIMING_OVERRIDE2                          :Result:='mmDP6_DP_MSA_V_TIMING_OVERRIDE2';
  mmDP6_DP_SEC_CNTL                                        :Result:='mmDP6_DP_SEC_CNTL';
  mmDP6_DP_SEC_CNTL1                                       :Result:='mmDP6_DP_SEC_CNTL1';
  mmDP6_DP_SEC_FRAMING1                                    :Result:='mmDP6_DP_SEC_FRAMING1';
  mmDP6_DP_SEC_FRAMING2                                    :Result:='mmDP6_DP_SEC_FRAMING2';
  mmDP6_DP_SEC_FRAMING3                                    :Result:='mmDP6_DP_SEC_FRAMING3';
  mmDP6_DP_SEC_FRAMING4                                    :Result:='mmDP6_DP_SEC_FRAMING4';
  mmDP6_DP_SEC_AUD_N                                       :Result:='mmDP6_DP_SEC_AUD_N';
  mmDP6_DP_SEC_AUD_N_READBACK                              :Result:='mmDP6_DP_SEC_AUD_N_READBACK';
  mmDP6_DP_SEC_AUD_M                                       :Result:='mmDP6_DP_SEC_AUD_M';
  mmDP6_DP_SEC_AUD_M_READBACK                              :Result:='mmDP6_DP_SEC_AUD_M_READBACK';
  mmDP6_DP_SEC_TIMESTAMP                                   :Result:='mmDP6_DP_SEC_TIMESTAMP';
  mmDP6_DP_SEC_PACKET_CNTL                                 :Result:='mmDP6_DP_SEC_PACKET_CNTL';
  mmDP6_DP_MSE_RATE_CNTL                                   :Result:='mmDP6_DP_MSE_RATE_CNTL';
  mmDP6_DP_MSE_RATE_UPDATE                                 :Result:='mmDP6_DP_MSE_RATE_UPDATE';
  mmDP6_DP_MSE_SAT0                                        :Result:='mmDP6_DP_MSE_SAT0';
  mmDP6_DP_MSE_SAT1                                        :Result:='mmDP6_DP_MSE_SAT1';
  mmDP6_DP_MSE_SAT2                                        :Result:='mmDP6_DP_MSE_SAT2';
  mmDP6_DP_MSE_SAT_UPDATE                                  :Result:='mmDP6_DP_MSE_SAT_UPDATE';
  mmDP6_DP_MSE_LINK_TIMING                                 :Result:='mmDP6_DP_MSE_LINK_TIMING';
  mmDP6_DP_MSE_MISC_CNTL                                   :Result:='mmDP6_DP_MSE_MISC_CNTL';
  mmDP6_DP_TEST_DEBUG_INDEX                                :Result:='mmDP6_DP_TEST_DEBUG_INDEX';
  mmDP6_DP_TEST_DEBUG_DATA                                 :Result:='mmDP6_DP_TEST_DEBUG_DATA';
  mmDP6_DP_FE_TEST_DEBUG_INDEX                             :Result:='mmDP6_DP_FE_TEST_DEBUG_INDEX';
  mmDP6_DP_FE_TEST_DEBUG_DATA                              :Result:='mmDP6_DP_FE_TEST_DEBUG_DATA';
  mmDC_PERFMON10_PERFCOUNTER_CNTL                          :Result:='mmDC_PERFMON10_PERFCOUNTER_CNTL';
  mmDC_PERFMON10_PERFCOUNTER_STATE                         :Result:='mmDC_PERFMON10_PERFCOUNTER_STATE';
  mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                   :Result:='mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC';
  mmDC_PERFMON10_PERFMON_CNTL                              :Result:='mmDC_PERFMON10_PERFMON_CNTL';
  mmDC_PERFMON10_PERFMON_CVALUE_LOW                        :Result:='mmDC_PERFMON10_PERFMON_CVALUE_LOW';
  mmDC_PERFMON10_PERFMON_HI                                :Result:='mmDC_PERFMON10_PERFMON_HI';
  mmDC_PERFMON10_PERFMON_LOW                               :Result:='mmDC_PERFMON10_PERFMON_LOW';
  mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX                  :Result:='mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX';
  mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA                   :Result:='mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA';
  mmDC_PERFMON10_PERFMON_CNTL2                             :Result:='mmDC_PERFMON10_PERFMON_CNTL2';
  mmAZF0STREAM8_AZALIA_STREAM_INDEX                        :Result:='mmAZF0STREAM8_AZALIA_STREAM_INDEX';
  mmAZF0STREAM8_AZALIA_STREAM_DATA                         :Result:='mmAZF0STREAM8_AZALIA_STREAM_DATA';
  mmAZF0STREAM9_AZALIA_STREAM_INDEX                        :Result:='mmAZF0STREAM9_AZALIA_STREAM_INDEX';
  mmAZF0STREAM9_AZALIA_STREAM_DATA                         :Result:='mmAZF0STREAM9_AZALIA_STREAM_DATA';
  mmAZF0STREAM10_AZALIA_STREAM_INDEX                       :Result:='mmAZF0STREAM10_AZALIA_STREAM_INDEX';
  mmAZF0STREAM10_AZALIA_STREAM_DATA                        :Result:='mmAZF0STREAM10_AZALIA_STREAM_DATA';
  mmAZF0STREAM11_AZALIA_STREAM_INDEX                       :Result:='mmAZF0STREAM11_AZALIA_STREAM_INDEX';
  mmAZF0STREAM11_AZALIA_STREAM_DATA                        :Result:='mmAZF0STREAM11_AZALIA_STREAM_DATA';
  mmAZF0STREAM12_AZALIA_STREAM_INDEX                       :Result:='mmAZF0STREAM12_AZALIA_STREAM_INDEX';
  mmAZF0STREAM12_AZALIA_STREAM_DATA                        :Result:='mmAZF0STREAM12_AZALIA_STREAM_DATA';
  mmAZF0STREAM13_AZALIA_STREAM_INDEX                       :Result:='mmAZF0STREAM13_AZALIA_STREAM_INDEX';
  mmAZF0STREAM13_AZALIA_STREAM_DATA                        :Result:='mmAZF0STREAM13_AZALIA_STREAM_DATA';
  mmAZF0STREAM14_AZALIA_STREAM_INDEX                       :Result:='mmAZF0STREAM14_AZALIA_STREAM_INDEX';
  mmAZF0STREAM14_AZALIA_STREAM_DATA                        :Result:='mmAZF0STREAM14_AZALIA_STREAM_DATA';
  mmAZF0STREAM15_AZALIA_STREAM_INDEX                       :Result:='mmAZF0STREAM15_AZALIA_STREAM_INDEX';
  mmAZF0STREAM15_AZALIA_STREAM_DATA                        :Result:='mmAZF0STREAM15_AZALIA_STREAM_DATA';
  mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                   :Result:='mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX';
  mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                    :Result:='mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA';
  mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX';
  mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA';
  mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX';
  mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA';
  mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX';
  mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA';
  mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX';
  mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA';
  mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX';
  mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA';
  mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX';
  mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA';
  mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX';
  mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA';
  mmDCRX_PHY_MACRO_CNTL_RESERVED0                          :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED0';
  mmDCRX_PHY_MACRO_CNTL_RESERVED1                          :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED1';
  mmDCRX_PHY_MACRO_CNTL_RESERVED2                          :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED2';
  mmDCRX_PHY_MACRO_CNTL_RESERVED3                          :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED3';
  mmDCRX_PHY_MACRO_CNTL_RESERVED4                          :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED4';
  mmDCRX_PHY_MACRO_CNTL_RESERVED5                          :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED5';
  mmDCRX_PHY_MACRO_CNTL_RESERVED6                          :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED6';
  mmDCRX_PHY_MACRO_CNTL_RESERVED7                          :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED7';
  mmDCRX_PHY_MACRO_CNTL_RESERVED8                          :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED8';
  mmDCRX_PHY_MACRO_CNTL_RESERVED9                          :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED9';
  mmDCRX_PHY_MACRO_CNTL_RESERVED10                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED10';
  mmDCRX_PHY_MACRO_CNTL_RESERVED11                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED11';
  mmDCRX_PHY_MACRO_CNTL_RESERVED12                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED12';
  mmDCRX_PHY_MACRO_CNTL_RESERVED13                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED13';
  mmDCRX_PHY_MACRO_CNTL_RESERVED14                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED14';
  mmDCRX_PHY_MACRO_CNTL_RESERVED15                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED15';
  mmDCRX_PHY_MACRO_CNTL_RESERVED16                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED16';
  mmDCRX_PHY_MACRO_CNTL_RESERVED17                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED17';
  mmDCRX_PHY_MACRO_CNTL_RESERVED18                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED18';
  mmDCRX_PHY_MACRO_CNTL_RESERVED19                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED19';
  mmDCRX_PHY_MACRO_CNTL_RESERVED20                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED20';
  mmDCRX_PHY_MACRO_CNTL_RESERVED21                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED21';
  mmDCRX_PHY_MACRO_CNTL_RESERVED22                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED22';
  mmDCRX_PHY_MACRO_CNTL_RESERVED23                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED23';
  mmDCRX_PHY_MACRO_CNTL_RESERVED24                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED24';
  mmDCRX_PHY_MACRO_CNTL_RESERVED25                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED25';
  mmDCRX_PHY_MACRO_CNTL_RESERVED26                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED26';
  mmDCRX_PHY_MACRO_CNTL_RESERVED27                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED27';
  mmDCRX_PHY_MACRO_CNTL_RESERVED28                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED28';
  mmDCRX_PHY_MACRO_CNTL_RESERVED29                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED29';
  mmDCRX_PHY_MACRO_CNTL_RESERVED30                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED30';
  mmDCRX_PHY_MACRO_CNTL_RESERVED31                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED31';
  mmDCRX_PHY_MACRO_CNTL_RESERVED32                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED32';
  mmDCRX_PHY_MACRO_CNTL_RESERVED33                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED33';
  mmDCRX_PHY_MACRO_CNTL_RESERVED34                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED34';
  mmDCRX_PHY_MACRO_CNTL_RESERVED35                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED35';
  mmDCRX_PHY_MACRO_CNTL_RESERVED36                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED36';
  mmDCRX_PHY_MACRO_CNTL_RESERVED37                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED37';
  mmDCRX_PHY_MACRO_CNTL_RESERVED38                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED38';
  mmDCRX_PHY_MACRO_CNTL_RESERVED39                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED39';
  mmDCRX_PHY_MACRO_CNTL_RESERVED40                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED40';
  mmDCRX_PHY_MACRO_CNTL_RESERVED41                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED41';
  mmDCRX_PHY_MACRO_CNTL_RESERVED42                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED42';
  mmDCRX_PHY_MACRO_CNTL_RESERVED43                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED43';
  mmDCRX_PHY_MACRO_CNTL_RESERVED44                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED44';
  mmDCRX_PHY_MACRO_CNTL_RESERVED45                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED45';
  mmDCRX_PHY_MACRO_CNTL_RESERVED46                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED46';
  mmDCRX_PHY_MACRO_CNTL_RESERVED47                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED47';
  mmDCRX_PHY_MACRO_CNTL_RESERVED48                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED48';
  mmDCRX_PHY_MACRO_CNTL_RESERVED49                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED49';
  mmDCRX_PHY_MACRO_CNTL_RESERVED50                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED50';
  mmDCRX_PHY_MACRO_CNTL_RESERVED51                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED51';
  mmDCRX_PHY_MACRO_CNTL_RESERVED52                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED52';
  mmDCRX_PHY_MACRO_CNTL_RESERVED53                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED53';
  mmDCRX_PHY_MACRO_CNTL_RESERVED54                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED54';
  mmDCRX_PHY_MACRO_CNTL_RESERVED55                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED55';
  mmDCRX_PHY_MACRO_CNTL_RESERVED56                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED56';
  mmDCRX_PHY_MACRO_CNTL_RESERVED57                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED57';
  mmDCRX_PHY_MACRO_CNTL_RESERVED58                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED58';
  mmDCRX_PHY_MACRO_CNTL_RESERVED59                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED59';
  mmDCRX_PHY_MACRO_CNTL_RESERVED60                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED60';
  mmDCRX_PHY_MACRO_CNTL_RESERVED61                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED61';
  mmDCRX_PHY_MACRO_CNTL_RESERVED62                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED62';
  mmDCRX_PHY_MACRO_CNTL_RESERVED63                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED63';
  mmDCRX_PHY_MACRO_CNTL_RESERVED64                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED64';
  mmDCRX_PHY_MACRO_CNTL_RESERVED65                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED65';
  mmDCRX_PHY_MACRO_CNTL_RESERVED66                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED66';
  mmDCRX_PHY_MACRO_CNTL_RESERVED67                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED67';
  mmDCRX_PHY_MACRO_CNTL_RESERVED68                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED68';
  mmDCRX_PHY_MACRO_CNTL_RESERVED69                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED69';
  mmDCRX_PHY_MACRO_CNTL_RESERVED70                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED70';
  mmDCRX_PHY_MACRO_CNTL_RESERVED71                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED71';
  mmDCRX_PHY_MACRO_CNTL_RESERVED72                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED72';
  mmDCRX_PHY_MACRO_CNTL_RESERVED73                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED73';
  mmDCRX_PHY_MACRO_CNTL_RESERVED74                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED74';
  mmDCRX_PHY_MACRO_CNTL_RESERVED75                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED75';
  mmDCRX_PHY_MACRO_CNTL_RESERVED76                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED76';
  mmDCRX_PHY_MACRO_CNTL_RESERVED77                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED77';
  mmDCRX_PHY_MACRO_CNTL_RESERVED78                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED78';
  mmDCRX_PHY_MACRO_CNTL_RESERVED79                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED79';
  mmDCRX_PHY_MACRO_CNTL_RESERVED80                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED80';
  mmDCRX_PHY_MACRO_CNTL_RESERVED81                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED81';
  mmDCRX_PHY_MACRO_CNTL_RESERVED82                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED82';
  mmDCRX_PHY_MACRO_CNTL_RESERVED83                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED83';
  mmDCRX_PHY_MACRO_CNTL_RESERVED84                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED84';
  mmDCRX_PHY_MACRO_CNTL_RESERVED85                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED85';
  mmDCRX_PHY_MACRO_CNTL_RESERVED86                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED86';
  mmDCRX_PHY_MACRO_CNTL_RESERVED87                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED87';
  mmDCRX_PHY_MACRO_CNTL_RESERVED88                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED88';
  mmDCRX_PHY_MACRO_CNTL_RESERVED89                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED89';
  mmDCRX_PHY_MACRO_CNTL_RESERVED90                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED90';
  mmDCRX_PHY_MACRO_CNTL_RESERVED91                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED91';
  mmDCRX_PHY_MACRO_CNTL_RESERVED92                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED92';
  mmDCRX_PHY_MACRO_CNTL_RESERVED93                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED93';
  mmDCRX_PHY_MACRO_CNTL_RESERVED94                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED94';
  mmDCRX_PHY_MACRO_CNTL_RESERVED95                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED95';
  mmDCRX_PHY_MACRO_CNTL_RESERVED96                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED96';
  mmDCRX_PHY_MACRO_CNTL_RESERVED97                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED97';
  mmDCRX_PHY_MACRO_CNTL_RESERVED98                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED98';
  mmDCRX_PHY_MACRO_CNTL_RESERVED99                         :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED99';
  mmDCRX_PHY_MACRO_CNTL_RESERVED100                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED100';
  mmDCRX_PHY_MACRO_CNTL_RESERVED101                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED101';
  mmDCRX_PHY_MACRO_CNTL_RESERVED102                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED102';
  mmDCRX_PHY_MACRO_CNTL_RESERVED103                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED103';
  mmDCRX_PHY_MACRO_CNTL_RESERVED104                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED104';
  mmDCRX_PHY_MACRO_CNTL_RESERVED105                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED105';
  mmDCRX_PHY_MACRO_CNTL_RESERVED106                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED106';
  mmDCRX_PHY_MACRO_CNTL_RESERVED107                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED107';
  mmDCRX_PHY_MACRO_CNTL_RESERVED108                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED108';
  mmDCRX_PHY_MACRO_CNTL_RESERVED109                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED109';
  mmDCRX_PHY_MACRO_CNTL_RESERVED110                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED110';
  mmDCRX_PHY_MACRO_CNTL_RESERVED111                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED111';
  mmDCRX_PHY_MACRO_CNTL_RESERVED112                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED112';
  mmDCRX_PHY_MACRO_CNTL_RESERVED113                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED113';
  mmDCRX_PHY_MACRO_CNTL_RESERVED114                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED114';
  mmDCRX_PHY_MACRO_CNTL_RESERVED115                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED115';
  mmDCRX_PHY_MACRO_CNTL_RESERVED116                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED116';
  mmDCRX_PHY_MACRO_CNTL_RESERVED117                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED117';
  mmDCRX_PHY_MACRO_CNTL_RESERVED118                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED118';
  mmDCRX_PHY_MACRO_CNTL_RESERVED119                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED119';
  mmDCRX_PHY_MACRO_CNTL_RESERVED120                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED120';
  mmDCRX_PHY_MACRO_CNTL_RESERVED121                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED121';
  mmDCRX_PHY_MACRO_CNTL_RESERVED122                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED122';
  mmDCRX_PHY_MACRO_CNTL_RESERVED123                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED123';
  mmDCRX_PHY_MACRO_CNTL_RESERVED124                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED124';
  mmDCRX_PHY_MACRO_CNTL_RESERVED125                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED125';
  mmDCRX_PHY_MACRO_CNTL_RESERVED126                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED126';
  mmDCRX_PHY_MACRO_CNTL_RESERVED127                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED127';
  mmDCRX_PHY_MACRO_CNTL_RESERVED128                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED128';
  mmDCRX_PHY_MACRO_CNTL_RESERVED129                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED129';
  mmDCRX_PHY_MACRO_CNTL_RESERVED130                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED130';
  mmDCRX_PHY_MACRO_CNTL_RESERVED131                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED131';
  mmDCRX_PHY_MACRO_CNTL_RESERVED132                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED132';
  mmDCRX_PHY_MACRO_CNTL_RESERVED133                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED133';
  mmDCRX_PHY_MACRO_CNTL_RESERVED134                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED134';
  mmDCRX_PHY_MACRO_CNTL_RESERVED135                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED135';
  mmDCRX_PHY_MACRO_CNTL_RESERVED136                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED136';
  mmDCRX_PHY_MACRO_CNTL_RESERVED137                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED137';
  mmDCRX_PHY_MACRO_CNTL_RESERVED138                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED138';
  mmDCRX_PHY_MACRO_CNTL_RESERVED139                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED139';
  mmDCRX_PHY_MACRO_CNTL_RESERVED140                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED140';
  mmDCRX_PHY_MACRO_CNTL_RESERVED141                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED141';
  mmDCRX_PHY_MACRO_CNTL_RESERVED142                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED142';
  mmDCRX_PHY_MACRO_CNTL_RESERVED143                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED143';
  mmDCRX_PHY_MACRO_CNTL_RESERVED144                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED144';
  mmDCRX_PHY_MACRO_CNTL_RESERVED145                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED145';
  mmDCRX_PHY_MACRO_CNTL_RESERVED146                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED146';
  mmDCRX_PHY_MACRO_CNTL_RESERVED147                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED147';
  mmDCRX_PHY_MACRO_CNTL_RESERVED148                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED148';
  mmDCRX_PHY_MACRO_CNTL_RESERVED149                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED149';
  mmDCRX_PHY_MACRO_CNTL_RESERVED150                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED150';
  mmDCRX_PHY_MACRO_CNTL_RESERVED151                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED151';
  mmDCRX_PHY_MACRO_CNTL_RESERVED152                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED152';
  mmDCRX_PHY_MACRO_CNTL_RESERVED153                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED153';
  mmDCRX_PHY_MACRO_CNTL_RESERVED154                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED154';
  mmDCRX_PHY_MACRO_CNTL_RESERVED155                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED155';
  mmDCRX_PHY_MACRO_CNTL_RESERVED156                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED156';
  mmDCRX_PHY_MACRO_CNTL_RESERVED157                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED157';
  mmDCRX_PHY_MACRO_CNTL_RESERVED158                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED158';
  mmDCRX_PHY_MACRO_CNTL_RESERVED159                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED159';
  mmDCRX_PHY_MACRO_CNTL_RESERVED160                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED160';
  mmDCRX_PHY_MACRO_CNTL_RESERVED161                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED161';
  mmDCRX_PHY_MACRO_CNTL_RESERVED162                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED162';
  mmDCRX_PHY_MACRO_CNTL_RESERVED163                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED163';
  mmDCRX_PHY_MACRO_CNTL_RESERVED164                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED164';
  mmDCRX_PHY_MACRO_CNTL_RESERVED165                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED165';
  mmDCRX_PHY_MACRO_CNTL_RESERVED166                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED166';
  mmDCRX_PHY_MACRO_CNTL_RESERVED167                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED167';
  mmDCRX_PHY_MACRO_CNTL_RESERVED168                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED168';
  mmDCRX_PHY_MACRO_CNTL_RESERVED169                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED169';
  mmDCRX_PHY_MACRO_CNTL_RESERVED170                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED170';
  mmDCRX_PHY_MACRO_CNTL_RESERVED171                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED171';
  mmDCRX_PHY_MACRO_CNTL_RESERVED172                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED172';
  mmDCRX_PHY_MACRO_CNTL_RESERVED173                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED173';
  mmDCRX_PHY_MACRO_CNTL_RESERVED174                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED174';
  mmDCRX_PHY_MACRO_CNTL_RESERVED175                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED175';
  mmDCRX_PHY_MACRO_CNTL_RESERVED176                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED176';
  mmDCRX_PHY_MACRO_CNTL_RESERVED177                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED177';
  mmDCRX_PHY_MACRO_CNTL_RESERVED178                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED178';
  mmDCRX_PHY_MACRO_CNTL_RESERVED179                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED179';
  mmDCRX_PHY_MACRO_CNTL_RESERVED180                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED180';
  mmDCRX_PHY_MACRO_CNTL_RESERVED181                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED181';
  mmDCRX_PHY_MACRO_CNTL_RESERVED182                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED182';
  mmDCRX_PHY_MACRO_CNTL_RESERVED183                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED183';
  mmDCRX_PHY_MACRO_CNTL_RESERVED184                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED184';
  mmDCRX_PHY_MACRO_CNTL_RESERVED185                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED185';
  mmDCRX_PHY_MACRO_CNTL_RESERVED186                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED186';
  mmDCRX_PHY_MACRO_CNTL_RESERVED187                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED187';
  mmDCRX_PHY_MACRO_CNTL_RESERVED188                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED188';
  mmDCRX_PHY_MACRO_CNTL_RESERVED189                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED189';
  mmDCRX_PHY_MACRO_CNTL_RESERVED190                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED190';
  mmDCRX_PHY_MACRO_CNTL_RESERVED191                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED191';
  mmDCRX_PHY_MACRO_CNTL_RESERVED192                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED192';
  mmDCRX_PHY_MACRO_CNTL_RESERVED193                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED193';
  mmDCRX_PHY_MACRO_CNTL_RESERVED194                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED194';
  mmDCRX_PHY_MACRO_CNTL_RESERVED195                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED195';
  mmDCRX_PHY_MACRO_CNTL_RESERVED196                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED196';
  mmDCRX_PHY_MACRO_CNTL_RESERVED197                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED197';
  mmDCRX_PHY_MACRO_CNTL_RESERVED198                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED198';
  mmDCRX_PHY_MACRO_CNTL_RESERVED199                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED199';
  mmDCRX_PHY_MACRO_CNTL_RESERVED200                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED200';
  mmDCRX_PHY_MACRO_CNTL_RESERVED201                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED201';
  mmDCRX_PHY_MACRO_CNTL_RESERVED202                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED202';
  mmDCRX_PHY_MACRO_CNTL_RESERVED203                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED203';
  mmDCRX_PHY_MACRO_CNTL_RESERVED204                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED204';
  mmDCRX_PHY_MACRO_CNTL_RESERVED205                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED205';
  mmDCRX_PHY_MACRO_CNTL_RESERVED206                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED206';
  mmDCRX_PHY_MACRO_CNTL_RESERVED207                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED207';
  mmDCRX_PHY_MACRO_CNTL_RESERVED208                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED208';
  mmDCRX_PHY_MACRO_CNTL_RESERVED209                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED209';
  mmDCRX_PHY_MACRO_CNTL_RESERVED210                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED210';
  mmDCRX_PHY_MACRO_CNTL_RESERVED211                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED211';
  mmDCRX_PHY_MACRO_CNTL_RESERVED212                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED212';
  mmDCRX_PHY_MACRO_CNTL_RESERVED213                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED213';
  mmDCRX_PHY_MACRO_CNTL_RESERVED214                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED214';
  mmDCRX_PHY_MACRO_CNTL_RESERVED215                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED215';
  mmDCRX_PHY_MACRO_CNTL_RESERVED216                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED216';
  mmDCRX_PHY_MACRO_CNTL_RESERVED217                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED217';
  mmDCRX_PHY_MACRO_CNTL_RESERVED218                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED218';
  mmDCRX_PHY_MACRO_CNTL_RESERVED219                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED219';
  mmDCRX_PHY_MACRO_CNTL_RESERVED220                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED220';
  mmDCRX_PHY_MACRO_CNTL_RESERVED221                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED221';
  mmDCRX_PHY_MACRO_CNTL_RESERVED222                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED222';
  mmDCRX_PHY_MACRO_CNTL_RESERVED223                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED223';
  mmDCRX_PHY_MACRO_CNTL_RESERVED224                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED224';
  mmDCRX_PHY_MACRO_CNTL_RESERVED225                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED225';
  mmDCRX_PHY_MACRO_CNTL_RESERVED226                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED226';
  mmDCRX_PHY_MACRO_CNTL_RESERVED227                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED227';
  mmDCRX_PHY_MACRO_CNTL_RESERVED228                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED228';
  mmDCRX_PHY_MACRO_CNTL_RESERVED229                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED229';
  mmDCRX_PHY_MACRO_CNTL_RESERVED230                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED230';
  mmDCRX_PHY_MACRO_CNTL_RESERVED231                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED231';
  mmDCRX_PHY_MACRO_CNTL_RESERVED232                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED232';
  mmDCRX_PHY_MACRO_CNTL_RESERVED233                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED233';
  mmDCRX_PHY_MACRO_CNTL_RESERVED234                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED234';
  mmDCRX_PHY_MACRO_CNTL_RESERVED235                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED235';
  mmDCRX_PHY_MACRO_CNTL_RESERVED236                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED236';
  mmDCRX_PHY_MACRO_CNTL_RESERVED237                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED237';
  mmDCRX_PHY_MACRO_CNTL_RESERVED238                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED238';
  mmDCRX_PHY_MACRO_CNTL_RESERVED239                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED239';
  mmDCRX_PHY_MACRO_CNTL_RESERVED240                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED240';
  mmDCRX_PHY_MACRO_CNTL_RESERVED241                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED241';
  mmDCRX_PHY_MACRO_CNTL_RESERVED242                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED242';
  mmDCRX_PHY_MACRO_CNTL_RESERVED243                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED243';
  mmDCRX_PHY_MACRO_CNTL_RESERVED244                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED244';
  mmDCRX_PHY_MACRO_CNTL_RESERVED245                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED245';
  mmDCRX_PHY_MACRO_CNTL_RESERVED246                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED246';
  mmDCRX_PHY_MACRO_CNTL_RESERVED247                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED247';
  mmDCRX_PHY_MACRO_CNTL_RESERVED248                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED248';
  mmDCRX_PHY_MACRO_CNTL_RESERVED249                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED249';
  mmDCRX_PHY_MACRO_CNTL_RESERVED250                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED250';
  mmDCRX_PHY_MACRO_CNTL_RESERVED251                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED251';
  mmDCRX_PHY_MACRO_CNTL_RESERVED252                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED252';
  mmDCRX_PHY_MACRO_CNTL_RESERVED253                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED253';
  mmDCRX_PHY_MACRO_CNTL_RESERVED254                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED254';
  mmDCRX_PHY_MACRO_CNTL_RESERVED255                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED255';
  mmDCRX_PHY_MACRO_CNTL_RESERVED256                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED256';
  mmDCRX_PHY_MACRO_CNTL_RESERVED257                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED257';
  mmDCRX_PHY_MACRO_CNTL_RESERVED258                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED258';
  mmDCRX_PHY_MACRO_CNTL_RESERVED259                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED259';
  mmDCRX_PHY_MACRO_CNTL_RESERVED260                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED260';
  mmDCRX_PHY_MACRO_CNTL_RESERVED261                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED261';
  mmDCRX_PHY_MACRO_CNTL_RESERVED262                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED262';
  mmDCRX_PHY_MACRO_CNTL_RESERVED263                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED263';
  mmDCRX_PHY_MACRO_CNTL_RESERVED264                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED264';
  mmDCRX_PHY_MACRO_CNTL_RESERVED265                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED265';
  mmDCRX_PHY_MACRO_CNTL_RESERVED266                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED266';
  mmDCRX_PHY_MACRO_CNTL_RESERVED267                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED267';
  mmDCRX_PHY_MACRO_CNTL_RESERVED268                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED268';
  mmDCRX_PHY_MACRO_CNTL_RESERVED269                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED269';
  mmDCRX_PHY_MACRO_CNTL_RESERVED270                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED270';
  mmDCRX_PHY_MACRO_CNTL_RESERVED271                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED271';
  mmDCRX_PHY_MACRO_CNTL_RESERVED272                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED272';
  mmDCRX_PHY_MACRO_CNTL_RESERVED273                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED273';
  mmDCRX_PHY_MACRO_CNTL_RESERVED274                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED274';
  mmDCRX_PHY_MACRO_CNTL_RESERVED275                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED275';
  mmDCRX_PHY_MACRO_CNTL_RESERVED276                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED276';
  mmDCRX_PHY_MACRO_CNTL_RESERVED277                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED277';
  mmDCRX_PHY_MACRO_CNTL_RESERVED278                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED278';
  mmDCRX_PHY_MACRO_CNTL_RESERVED279                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED279';
  mmDCRX_PHY_MACRO_CNTL_RESERVED280                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED280';
  mmDCRX_PHY_MACRO_CNTL_RESERVED281                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED281';
  mmDCRX_PHY_MACRO_CNTL_RESERVED282                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED282';
  mmDCRX_PHY_MACRO_CNTL_RESERVED283                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED283';
  mmDCRX_PHY_MACRO_CNTL_RESERVED284                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED284';
  mmDCRX_PHY_MACRO_CNTL_RESERVED285                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED285';
  mmDCRX_PHY_MACRO_CNTL_RESERVED286                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED286';
  mmDCRX_PHY_MACRO_CNTL_RESERVED287                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED287';
  mmDCRX_PHY_MACRO_CNTL_RESERVED288                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED288';
  mmDCRX_PHY_MACRO_CNTL_RESERVED289                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED289';
  mmDCRX_PHY_MACRO_CNTL_RESERVED290                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED290';
  mmDCRX_PHY_MACRO_CNTL_RESERVED291                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED291';
  mmDCRX_PHY_MACRO_CNTL_RESERVED292                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED292';
  mmDCRX_PHY_MACRO_CNTL_RESERVED293                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED293';
  mmDCRX_PHY_MACRO_CNTL_RESERVED294                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED294';
  mmDCRX_PHY_MACRO_CNTL_RESERVED295                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED295';
  mmDCRX_PHY_MACRO_CNTL_RESERVED296                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED296';
  mmDCRX_PHY_MACRO_CNTL_RESERVED297                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED297';
  mmDCRX_PHY_MACRO_CNTL_RESERVED298                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED298';
  mmDCRX_PHY_MACRO_CNTL_RESERVED299                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED299';
  mmDCRX_PHY_MACRO_CNTL_RESERVED300                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED300';
  mmDCRX_PHY_MACRO_CNTL_RESERVED301                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED301';
  mmDCRX_PHY_MACRO_CNTL_RESERVED302                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED302';
  mmDCRX_PHY_MACRO_CNTL_RESERVED303                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED303';
  mmDCRX_PHY_MACRO_CNTL_RESERVED304                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED304';
  mmDCRX_PHY_MACRO_CNTL_RESERVED305                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED305';
  mmDCRX_PHY_MACRO_CNTL_RESERVED306                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED306';
  mmDCRX_PHY_MACRO_CNTL_RESERVED307                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED307';
  mmDCRX_PHY_MACRO_CNTL_RESERVED308                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED308';
  mmDCRX_PHY_MACRO_CNTL_RESERVED309                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED309';
  mmDCRX_PHY_MACRO_CNTL_RESERVED310                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED310';
  mmDCRX_PHY_MACRO_CNTL_RESERVED311                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED311';
  mmDCRX_PHY_MACRO_CNTL_RESERVED312                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED312';
  mmDCRX_PHY_MACRO_CNTL_RESERVED313                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED313';
  mmDCRX_PHY_MACRO_CNTL_RESERVED314                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED314';
  mmDCRX_PHY_MACRO_CNTL_RESERVED315                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED315';
  mmDCRX_PHY_MACRO_CNTL_RESERVED316                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED316';
  mmDCRX_PHY_MACRO_CNTL_RESERVED317                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED317';
  mmDCRX_PHY_MACRO_CNTL_RESERVED318                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED318';
  mmDCRX_PHY_MACRO_CNTL_RESERVED319                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED319';
  mmDCRX_PHY_MACRO_CNTL_RESERVED320                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED320';
  mmDCRX_PHY_MACRO_CNTL_RESERVED321                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED321';
  mmDCRX_PHY_MACRO_CNTL_RESERVED322                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED322';
  mmDCRX_PHY_MACRO_CNTL_RESERVED323                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED323';
  mmDCRX_PHY_MACRO_CNTL_RESERVED324                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED324';
  mmDCRX_PHY_MACRO_CNTL_RESERVED325                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED325';
  mmDCRX_PHY_MACRO_CNTL_RESERVED326                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED326';
  mmDCRX_PHY_MACRO_CNTL_RESERVED327                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED327';
  mmDCRX_PHY_MACRO_CNTL_RESERVED328                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED328';
  mmDCRX_PHY_MACRO_CNTL_RESERVED329                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED329';
  mmDCRX_PHY_MACRO_CNTL_RESERVED330                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED330';
  mmDCRX_PHY_MACRO_CNTL_RESERVED331                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED331';
  mmDCRX_PHY_MACRO_CNTL_RESERVED332                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED332';
  mmDCRX_PHY_MACRO_CNTL_RESERVED333                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED333';
  mmDCRX_PHY_MACRO_CNTL_RESERVED334                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED334';
  mmDCRX_PHY_MACRO_CNTL_RESERVED335                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED335';
  mmDCRX_PHY_MACRO_CNTL_RESERVED336                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED336';
  mmDCRX_PHY_MACRO_CNTL_RESERVED337                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED337';
  mmDCRX_PHY_MACRO_CNTL_RESERVED338                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED338';
  mmDCRX_PHY_MACRO_CNTL_RESERVED339                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED339';
  mmDCRX_PHY_MACRO_CNTL_RESERVED340                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED340';
  mmDCRX_PHY_MACRO_CNTL_RESERVED341                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED341';
  mmDCRX_PHY_MACRO_CNTL_RESERVED342                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED342';
  mmDCRX_PHY_MACRO_CNTL_RESERVED343                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED343';
  mmDCRX_PHY_MACRO_CNTL_RESERVED344                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED344';
  mmDCRX_PHY_MACRO_CNTL_RESERVED345                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED345';
  mmDCRX_PHY_MACRO_CNTL_RESERVED346                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED346';
  mmDCRX_PHY_MACRO_CNTL_RESERVED347                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED347';
  mmDCRX_PHY_MACRO_CNTL_RESERVED348                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED348';
  mmDCRX_PHY_MACRO_CNTL_RESERVED349                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED349';
  mmDCRX_PHY_MACRO_CNTL_RESERVED350                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED350';
  mmDCRX_PHY_MACRO_CNTL_RESERVED351                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED351';
  mmDCRX_PHY_MACRO_CNTL_RESERVED352                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED352';
  mmDCRX_PHY_MACRO_CNTL_RESERVED353                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED353';
  mmDCRX_PHY_MACRO_CNTL_RESERVED354                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED354';
  mmDCRX_PHY_MACRO_CNTL_RESERVED355                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED355';
  mmDCRX_PHY_MACRO_CNTL_RESERVED356                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED356';
  mmDCRX_PHY_MACRO_CNTL_RESERVED357                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED357';
  mmDCRX_PHY_MACRO_CNTL_RESERVED358                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED358';
  mmDCRX_PHY_MACRO_CNTL_RESERVED359                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED359';
  mmDCRX_PHY_MACRO_CNTL_RESERVED360                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED360';
  mmDCRX_PHY_MACRO_CNTL_RESERVED361                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED361';
  mmDCRX_PHY_MACRO_CNTL_RESERVED362                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED362';
  mmDCRX_PHY_MACRO_CNTL_RESERVED363                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED363';
  mmDCRX_PHY_MACRO_CNTL_RESERVED364                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED364';
  mmDCRX_PHY_MACRO_CNTL_RESERVED365                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED365';
  mmDCRX_PHY_MACRO_CNTL_RESERVED366                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED366';
  mmDCRX_PHY_MACRO_CNTL_RESERVED367                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED367';
  mmDCRX_PHY_MACRO_CNTL_RESERVED368                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED368';
  mmDCRX_PHY_MACRO_CNTL_RESERVED369                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED369';
  mmDCRX_PHY_MACRO_CNTL_RESERVED370                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED370';
  mmDCRX_PHY_MACRO_CNTL_RESERVED371                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED371';
  mmDCRX_PHY_MACRO_CNTL_RESERVED372                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED372';
  mmDCRX_PHY_MACRO_CNTL_RESERVED373                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED373';
  mmDCRX_PHY_MACRO_CNTL_RESERVED374                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED374';
  mmDCRX_PHY_MACRO_CNTL_RESERVED375                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED375';
  mmDCRX_PHY_MACRO_CNTL_RESERVED376                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED376';
  mmDCRX_PHY_MACRO_CNTL_RESERVED377                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED377';
  mmDCRX_PHY_MACRO_CNTL_RESERVED378                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED378';
  mmDCRX_PHY_MACRO_CNTL_RESERVED379                        :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED379';
  mmAUX_CONTROL                                            :Result:='mmAUX_CONTROL';
  mmAUX_SW_CONTROL                                         :Result:='mmAUX_SW_CONTROL';
  mmAUX_ARB_CONTROL                                        :Result:='mmAUX_ARB_CONTROL';
  mmAUX_INTERRUPT_CONTROL                                  :Result:='mmAUX_INTERRUPT_CONTROL';
  mmAUX_SW_STATUS                                          :Result:='mmAUX_SW_STATUS';
  mmAUX_LS_STATUS                                          :Result:='mmAUX_LS_STATUS';
  mmAUX_SW_DATA                                            :Result:='mmAUX_SW_DATA';
  mmAUX_LS_DATA                                            :Result:='mmAUX_LS_DATA';
  mmAUX_DPHY_TX_REF_CONTROL                                :Result:='mmAUX_DPHY_TX_REF_CONTROL';
  mmAUX_DPHY_TX_CONTROL                                    :Result:='mmAUX_DPHY_TX_CONTROL';
  mmAUX_DPHY_RX_CONTROL0                                   :Result:='mmAUX_DPHY_RX_CONTROL0';
  mmAUX_DPHY_RX_CONTROL1                                   :Result:='mmAUX_DPHY_RX_CONTROL1';
  mmAUX_DPHY_TX_STATUS                                     :Result:='mmAUX_DPHY_TX_STATUS';
  mmAUX_DPHY_RX_STATUS                                     :Result:='mmAUX_DPHY_RX_STATUS';
  mmAUX_GTC_SYNC_CONTROL                                   :Result:='mmAUX_GTC_SYNC_CONTROL';
  mmAUX_GTC_SYNC_ERROR_CONTROL                             :Result:='mmAUX_GTC_SYNC_ERROR_CONTROL';
  mmAUX_GTC_SYNC_CONTROLLER_STATUS                         :Result:='mmAUX_GTC_SYNC_CONTROLLER_STATUS';
  mmAUX_GTC_SYNC_STATUS                                    :Result:='mmAUX_GTC_SYNC_STATUS';
  mmAUX_GTC_SYNC_DATA                                      :Result:='mmAUX_GTC_SYNC_DATA';
  mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                     :Result:='mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE';
  mmAUX_TEST_DEBUG_INDEX                                   :Result:='mmAUX_TEST_DEBUG_INDEX';
  mmAUX_TEST_DEBUG_DATA                                    :Result:='mmAUX_TEST_DEBUG_DATA';
  mmDP_AUX1_AUX_CONTROL                                    :Result:='mmDP_AUX1_AUX_CONTROL';
  mmDP_AUX1_AUX_SW_CONTROL                                 :Result:='mmDP_AUX1_AUX_SW_CONTROL';
  mmDP_AUX1_AUX_ARB_CONTROL                                :Result:='mmDP_AUX1_AUX_ARB_CONTROL';
  mmDP_AUX1_AUX_INTERRUPT_CONTROL                          :Result:='mmDP_AUX1_AUX_INTERRUPT_CONTROL';
  mmDP_AUX1_AUX_SW_STATUS                                  :Result:='mmDP_AUX1_AUX_SW_STATUS';
  mmDP_AUX1_AUX_LS_STATUS                                  :Result:='mmDP_AUX1_AUX_LS_STATUS';
  mmDP_AUX1_AUX_SW_DATA                                    :Result:='mmDP_AUX1_AUX_SW_DATA';
  mmDP_AUX1_AUX_LS_DATA                                    :Result:='mmDP_AUX1_AUX_LS_DATA';
  mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                        :Result:='mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL';
  mmDP_AUX1_AUX_DPHY_TX_CONTROL                            :Result:='mmDP_AUX1_AUX_DPHY_TX_CONTROL';
  mmDP_AUX1_AUX_DPHY_RX_CONTROL0                           :Result:='mmDP_AUX1_AUX_DPHY_RX_CONTROL0';
  mmDP_AUX1_AUX_DPHY_RX_CONTROL1                           :Result:='mmDP_AUX1_AUX_DPHY_RX_CONTROL1';
  mmDP_AUX1_AUX_DPHY_TX_STATUS                             :Result:='mmDP_AUX1_AUX_DPHY_TX_STATUS';
  mmDP_AUX1_AUX_DPHY_RX_STATUS                             :Result:='mmDP_AUX1_AUX_DPHY_RX_STATUS';
  mmDP_AUX1_AUX_GTC_SYNC_CONTROL                           :Result:='mmDP_AUX1_AUX_GTC_SYNC_CONTROL';
  mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                     :Result:='mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL';
  mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                 :Result:='mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS';
  mmDP_AUX1_AUX_GTC_SYNC_STATUS                            :Result:='mmDP_AUX1_AUX_GTC_SYNC_STATUS';
  mmDP_AUX1_AUX_GTC_SYNC_DATA                              :Result:='mmDP_AUX1_AUX_GTC_SYNC_DATA';
  mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             :Result:='mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE';
  mmDP_AUX1_AUX_TEST_DEBUG_INDEX                           :Result:='mmDP_AUX1_AUX_TEST_DEBUG_INDEX';
  mmDP_AUX1_AUX_TEST_DEBUG_DATA                            :Result:='mmDP_AUX1_AUX_TEST_DEBUG_DATA';
  mmDP_AUX2_AUX_CONTROL                                    :Result:='mmDP_AUX2_AUX_CONTROL';
  mmDP_AUX2_AUX_SW_CONTROL                                 :Result:='mmDP_AUX2_AUX_SW_CONTROL';
  mmDP_AUX2_AUX_ARB_CONTROL                                :Result:='mmDP_AUX2_AUX_ARB_CONTROL';
  mmDP_AUX2_AUX_INTERRUPT_CONTROL                          :Result:='mmDP_AUX2_AUX_INTERRUPT_CONTROL';
  mmDP_AUX2_AUX_SW_STATUS                                  :Result:='mmDP_AUX2_AUX_SW_STATUS';
  mmDP_AUX2_AUX_LS_STATUS                                  :Result:='mmDP_AUX2_AUX_LS_STATUS';
  mmDP_AUX2_AUX_SW_DATA                                    :Result:='mmDP_AUX2_AUX_SW_DATA';
  mmDP_AUX2_AUX_LS_DATA                                    :Result:='mmDP_AUX2_AUX_LS_DATA';
  mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                        :Result:='mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL';
  mmDP_AUX2_AUX_DPHY_TX_CONTROL                            :Result:='mmDP_AUX2_AUX_DPHY_TX_CONTROL';
  mmDP_AUX2_AUX_DPHY_RX_CONTROL0                           :Result:='mmDP_AUX2_AUX_DPHY_RX_CONTROL0';
  mmDP_AUX2_AUX_DPHY_RX_CONTROL1                           :Result:='mmDP_AUX2_AUX_DPHY_RX_CONTROL1';
  mmDP_AUX2_AUX_DPHY_TX_STATUS                             :Result:='mmDP_AUX2_AUX_DPHY_TX_STATUS';
  mmDP_AUX2_AUX_DPHY_RX_STATUS                             :Result:='mmDP_AUX2_AUX_DPHY_RX_STATUS';
  mmDP_AUX2_AUX_GTC_SYNC_CONTROL                           :Result:='mmDP_AUX2_AUX_GTC_SYNC_CONTROL';
  mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                     :Result:='mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL';
  mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                 :Result:='mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS';
  mmDP_AUX2_AUX_GTC_SYNC_STATUS                            :Result:='mmDP_AUX2_AUX_GTC_SYNC_STATUS';
  mmDP_AUX2_AUX_GTC_SYNC_DATA                              :Result:='mmDP_AUX2_AUX_GTC_SYNC_DATA';
  mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             :Result:='mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE';
  mmDP_AUX2_AUX_TEST_DEBUG_INDEX                           :Result:='mmDP_AUX2_AUX_TEST_DEBUG_INDEX';
  mmDP_AUX2_AUX_TEST_DEBUG_DATA                            :Result:='mmDP_AUX2_AUX_TEST_DEBUG_DATA';
  mmDP_AUX3_AUX_CONTROL                                    :Result:='mmDP_AUX3_AUX_CONTROL';
  mmDP_AUX3_AUX_SW_CONTROL                                 :Result:='mmDP_AUX3_AUX_SW_CONTROL';
  mmDP_AUX3_AUX_ARB_CONTROL                                :Result:='mmDP_AUX3_AUX_ARB_CONTROL';
  mmDP_AUX3_AUX_INTERRUPT_CONTROL                          :Result:='mmDP_AUX3_AUX_INTERRUPT_CONTROL';
  mmDP_AUX3_AUX_SW_STATUS                                  :Result:='mmDP_AUX3_AUX_SW_STATUS';
  mmDP_AUX3_AUX_LS_STATUS                                  :Result:='mmDP_AUX3_AUX_LS_STATUS';
  mmDP_AUX3_AUX_SW_DATA                                    :Result:='mmDP_AUX3_AUX_SW_DATA';
  mmDP_AUX3_AUX_LS_DATA                                    :Result:='mmDP_AUX3_AUX_LS_DATA';
  mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                        :Result:='mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL';
  mmDP_AUX3_AUX_DPHY_TX_CONTROL                            :Result:='mmDP_AUX3_AUX_DPHY_TX_CONTROL';
  mmDP_AUX3_AUX_DPHY_RX_CONTROL0                           :Result:='mmDP_AUX3_AUX_DPHY_RX_CONTROL0';
  mmDP_AUX3_AUX_DPHY_RX_CONTROL1                           :Result:='mmDP_AUX3_AUX_DPHY_RX_CONTROL1';
  mmDP_AUX3_AUX_DPHY_TX_STATUS                             :Result:='mmDP_AUX3_AUX_DPHY_TX_STATUS';
  mmDP_AUX3_AUX_DPHY_RX_STATUS                             :Result:='mmDP_AUX3_AUX_DPHY_RX_STATUS';
  mmDP_AUX3_AUX_GTC_SYNC_CONTROL                           :Result:='mmDP_AUX3_AUX_GTC_SYNC_CONTROL';
  mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                     :Result:='mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL';
  mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                 :Result:='mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS';
  mmDP_AUX3_AUX_GTC_SYNC_STATUS                            :Result:='mmDP_AUX3_AUX_GTC_SYNC_STATUS';
  mmDP_AUX3_AUX_GTC_SYNC_DATA                              :Result:='mmDP_AUX3_AUX_GTC_SYNC_DATA';
  mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             :Result:='mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE';
  mmDP_AUX3_AUX_TEST_DEBUG_INDEX                           :Result:='mmDP_AUX3_AUX_TEST_DEBUG_INDEX';
  mmDP_AUX3_AUX_TEST_DEBUG_DATA                            :Result:='mmDP_AUX3_AUX_TEST_DEBUG_DATA';
  mmDP_AUX4_AUX_CONTROL                                    :Result:='mmDP_AUX4_AUX_CONTROL';
  mmDP_AUX4_AUX_SW_CONTROL                                 :Result:='mmDP_AUX4_AUX_SW_CONTROL';
  mmDP_AUX4_AUX_ARB_CONTROL                                :Result:='mmDP_AUX4_AUX_ARB_CONTROL';
  mmDP_AUX4_AUX_INTERRUPT_CONTROL                          :Result:='mmDP_AUX4_AUX_INTERRUPT_CONTROL';
  mmDP_AUX4_AUX_SW_STATUS                                  :Result:='mmDP_AUX4_AUX_SW_STATUS';
  mmDP_AUX4_AUX_LS_STATUS                                  :Result:='mmDP_AUX4_AUX_LS_STATUS';
  mmDP_AUX4_AUX_SW_DATA                                    :Result:='mmDP_AUX4_AUX_SW_DATA';
  mmDP_AUX4_AUX_LS_DATA                                    :Result:='mmDP_AUX4_AUX_LS_DATA';
  mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                        :Result:='mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL';
  mmDP_AUX4_AUX_DPHY_TX_CONTROL                            :Result:='mmDP_AUX4_AUX_DPHY_TX_CONTROL';
  mmDP_AUX4_AUX_DPHY_RX_CONTROL0                           :Result:='mmDP_AUX4_AUX_DPHY_RX_CONTROL0';
  mmDP_AUX4_AUX_DPHY_RX_CONTROL1                           :Result:='mmDP_AUX4_AUX_DPHY_RX_CONTROL1';
  mmDP_AUX4_AUX_DPHY_TX_STATUS                             :Result:='mmDP_AUX4_AUX_DPHY_TX_STATUS';
  mmDP_AUX4_AUX_DPHY_RX_STATUS                             :Result:='mmDP_AUX4_AUX_DPHY_RX_STATUS';
  mmDP_AUX4_AUX_GTC_SYNC_CONTROL                           :Result:='mmDP_AUX4_AUX_GTC_SYNC_CONTROL';
  mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                     :Result:='mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL';
  mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                 :Result:='mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS';
  mmDP_AUX4_AUX_GTC_SYNC_STATUS                            :Result:='mmDP_AUX4_AUX_GTC_SYNC_STATUS';
  mmDP_AUX4_AUX_GTC_SYNC_DATA                              :Result:='mmDP_AUX4_AUX_GTC_SYNC_DATA';
  mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             :Result:='mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE';
  mmDP_AUX4_AUX_TEST_DEBUG_INDEX                           :Result:='mmDP_AUX4_AUX_TEST_DEBUG_INDEX';
  mmDP_AUX4_AUX_TEST_DEBUG_DATA                            :Result:='mmDP_AUX4_AUX_TEST_DEBUG_DATA';
  mmDP_AUX5_AUX_CONTROL                                    :Result:='mmDP_AUX5_AUX_CONTROL';
  mmDP_AUX5_AUX_SW_CONTROL                                 :Result:='mmDP_AUX5_AUX_SW_CONTROL';
  mmDP_AUX5_AUX_ARB_CONTROL                                :Result:='mmDP_AUX5_AUX_ARB_CONTROL';
  mmDP_AUX5_AUX_INTERRUPT_CONTROL                          :Result:='mmDP_AUX5_AUX_INTERRUPT_CONTROL';
  mmDP_AUX5_AUX_SW_STATUS                                  :Result:='mmDP_AUX5_AUX_SW_STATUS';
  mmDP_AUX5_AUX_LS_STATUS                                  :Result:='mmDP_AUX5_AUX_LS_STATUS';
  mmDP_AUX5_AUX_SW_DATA                                    :Result:='mmDP_AUX5_AUX_SW_DATA';
  mmDP_AUX5_AUX_LS_DATA                                    :Result:='mmDP_AUX5_AUX_LS_DATA';
  mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL                        :Result:='mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL';
  mmDP_AUX5_AUX_DPHY_TX_CONTROL                            :Result:='mmDP_AUX5_AUX_DPHY_TX_CONTROL';
  mmDP_AUX5_AUX_DPHY_RX_CONTROL0                           :Result:='mmDP_AUX5_AUX_DPHY_RX_CONTROL0';
  mmDP_AUX5_AUX_DPHY_RX_CONTROL1                           :Result:='mmDP_AUX5_AUX_DPHY_RX_CONTROL1';
  mmDP_AUX5_AUX_DPHY_TX_STATUS                             :Result:='mmDP_AUX5_AUX_DPHY_TX_STATUS';
  mmDP_AUX5_AUX_DPHY_RX_STATUS                             :Result:='mmDP_AUX5_AUX_DPHY_RX_STATUS';
  mmDP_AUX5_AUX_GTC_SYNC_CONTROL                           :Result:='mmDP_AUX5_AUX_GTC_SYNC_CONTROL';
  mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL                     :Result:='mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL';
  mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS                 :Result:='mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS';
  mmDP_AUX5_AUX_GTC_SYNC_STATUS                            :Result:='mmDP_AUX5_AUX_GTC_SYNC_STATUS';
  mmDP_AUX5_AUX_GTC_SYNC_DATA                              :Result:='mmDP_AUX5_AUX_GTC_SYNC_DATA';
  mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             :Result:='mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE';
  mmDP_AUX5_AUX_TEST_DEBUG_INDEX                           :Result:='mmDP_AUX5_AUX_TEST_DEBUG_INDEX';
  mmDP_AUX5_AUX_TEST_DEBUG_DATA                            :Result:='mmDP_AUX5_AUX_TEST_DEBUG_DATA';
  mmDPHY_MACRO_CNTL_RESERVED0                              :Result:='mmDPHY_MACRO_CNTL_RESERVED0';
  mmDPHY_MACRO_CNTL_RESERVED1                              :Result:='mmDPHY_MACRO_CNTL_RESERVED1';
  mmDPHY_MACRO_CNTL_RESERVED2                              :Result:='mmDPHY_MACRO_CNTL_RESERVED2';
  mmDPHY_MACRO_CNTL_RESERVED3                              :Result:='mmDPHY_MACRO_CNTL_RESERVED3';
  mmDPHY_MACRO_CNTL_RESERVED4                              :Result:='mmDPHY_MACRO_CNTL_RESERVED4';
  mmDPHY_MACRO_CNTL_RESERVED5                              :Result:='mmDPHY_MACRO_CNTL_RESERVED5';
  mmDPHY_MACRO_CNTL_RESERVED6                              :Result:='mmDPHY_MACRO_CNTL_RESERVED6';
  mmDPHY_MACRO_CNTL_RESERVED7                              :Result:='mmDPHY_MACRO_CNTL_RESERVED7';
  mmDPHY_MACRO_CNTL_RESERVED8                              :Result:='mmDPHY_MACRO_CNTL_RESERVED8';
  mmDPHY_MACRO_CNTL_RESERVED9                              :Result:='mmDPHY_MACRO_CNTL_RESERVED9';
  mmDPHY_MACRO_CNTL_RESERVED10                             :Result:='mmDPHY_MACRO_CNTL_RESERVED10';
  mmDPHY_MACRO_CNTL_RESERVED11                             :Result:='mmDPHY_MACRO_CNTL_RESERVED11';
  mmDPHY_MACRO_CNTL_RESERVED12                             :Result:='mmDPHY_MACRO_CNTL_RESERVED12';
  mmDPHY_MACRO_CNTL_RESERVED13                             :Result:='mmDPHY_MACRO_CNTL_RESERVED13';
  mmDPHY_MACRO_CNTL_RESERVED14                             :Result:='mmDPHY_MACRO_CNTL_RESERVED14';
  mmDPHY_MACRO_CNTL_RESERVED15                             :Result:='mmDPHY_MACRO_CNTL_RESERVED15';
  mmDPHY_MACRO_CNTL_RESERVED16                             :Result:='mmDPHY_MACRO_CNTL_RESERVED16';
  mmDPHY_MACRO_CNTL_RESERVED17                             :Result:='mmDPHY_MACRO_CNTL_RESERVED17';
  mmDPHY_MACRO_CNTL_RESERVED18                             :Result:='mmDPHY_MACRO_CNTL_RESERVED18';
  mmDPHY_MACRO_CNTL_RESERVED19                             :Result:='mmDPHY_MACRO_CNTL_RESERVED19';
  mmDPHY_MACRO_CNTL_RESERVED20                             :Result:='mmDPHY_MACRO_CNTL_RESERVED20';
  mmDPHY_MACRO_CNTL_RESERVED21                             :Result:='mmDPHY_MACRO_CNTL_RESERVED21';
  mmDPHY_MACRO_CNTL_RESERVED22                             :Result:='mmDPHY_MACRO_CNTL_RESERVED22';
  mmDPHY_MACRO_CNTL_RESERVED23                             :Result:='mmDPHY_MACRO_CNTL_RESERVED23';
  mmDPHY_MACRO_CNTL_RESERVED24                             :Result:='mmDPHY_MACRO_CNTL_RESERVED24';
  mmDPHY_MACRO_CNTL_RESERVED25                             :Result:='mmDPHY_MACRO_CNTL_RESERVED25';
  mmDPHY_MACRO_CNTL_RESERVED26                             :Result:='mmDPHY_MACRO_CNTL_RESERVED26';
  mmDPHY_MACRO_CNTL_RESERVED27                             :Result:='mmDPHY_MACRO_CNTL_RESERVED27';
  mmDPHY_MACRO_CNTL_RESERVED28                             :Result:='mmDPHY_MACRO_CNTL_RESERVED28';
  mmDPHY_MACRO_CNTL_RESERVED29                             :Result:='mmDPHY_MACRO_CNTL_RESERVED29';
  mmDPHY_MACRO_CNTL_RESERVED30                             :Result:='mmDPHY_MACRO_CNTL_RESERVED30';
  mmDPHY_MACRO_CNTL_RESERVED31                             :Result:='mmDPHY_MACRO_CNTL_RESERVED31';
  mmDPHY_MACRO_CNTL_RESERVED32                             :Result:='mmDPHY_MACRO_CNTL_RESERVED32';
  mmDPHY_MACRO_CNTL_RESERVED33                             :Result:='mmDPHY_MACRO_CNTL_RESERVED33';
  mmDPHY_MACRO_CNTL_RESERVED34                             :Result:='mmDPHY_MACRO_CNTL_RESERVED34';
  mmDPHY_MACRO_CNTL_RESERVED35                             :Result:='mmDPHY_MACRO_CNTL_RESERVED35';
  mmDPHY_MACRO_CNTL_RESERVED36                             :Result:='mmDPHY_MACRO_CNTL_RESERVED36';
  mmDPHY_MACRO_CNTL_RESERVED37                             :Result:='mmDPHY_MACRO_CNTL_RESERVED37';
  mmDPHY_MACRO_CNTL_RESERVED38                             :Result:='mmDPHY_MACRO_CNTL_RESERVED38';
  mmDPHY_MACRO_CNTL_RESERVED39                             :Result:='mmDPHY_MACRO_CNTL_RESERVED39';
  mmDPHY_MACRO_CNTL_RESERVED40                             :Result:='mmDPHY_MACRO_CNTL_RESERVED40';
  mmDPHY_MACRO_CNTL_RESERVED41                             :Result:='mmDPHY_MACRO_CNTL_RESERVED41';
  mmDPHY_MACRO_CNTL_RESERVED42                             :Result:='mmDPHY_MACRO_CNTL_RESERVED42';
  mmDPHY_MACRO_CNTL_RESERVED43                             :Result:='mmDPHY_MACRO_CNTL_RESERVED43';
  mmDPHY_MACRO_CNTL_RESERVED44                             :Result:='mmDPHY_MACRO_CNTL_RESERVED44';
  mmDPHY_MACRO_CNTL_RESERVED45                             :Result:='mmDPHY_MACRO_CNTL_RESERVED45';
  mmDPHY_MACRO_CNTL_RESERVED46                             :Result:='mmDPHY_MACRO_CNTL_RESERVED46';
  mmDPHY_MACRO_CNTL_RESERVED47                             :Result:='mmDPHY_MACRO_CNTL_RESERVED47';
  mmDPHY_MACRO_CNTL_RESERVED48                             :Result:='mmDPHY_MACRO_CNTL_RESERVED48';
  mmDPHY_MACRO_CNTL_RESERVED49                             :Result:='mmDPHY_MACRO_CNTL_RESERVED49';
  mmDPHY_MACRO_CNTL_RESERVED50                             :Result:='mmDPHY_MACRO_CNTL_RESERVED50';
  mmDPHY_MACRO_CNTL_RESERVED51                             :Result:='mmDPHY_MACRO_CNTL_RESERVED51';
  mmDPHY_MACRO_CNTL_RESERVED52                             :Result:='mmDPHY_MACRO_CNTL_RESERVED52';
  mmDPHY_MACRO_CNTL_RESERVED53                             :Result:='mmDPHY_MACRO_CNTL_RESERVED53';
  mmDPHY_MACRO_CNTL_RESERVED54                             :Result:='mmDPHY_MACRO_CNTL_RESERVED54';
  mmDPHY_MACRO_CNTL_RESERVED55                             :Result:='mmDPHY_MACRO_CNTL_RESERVED55';
  mmDPHY_MACRO_CNTL_RESERVED56                             :Result:='mmDPHY_MACRO_CNTL_RESERVED56';
  mmDPHY_MACRO_CNTL_RESERVED57                             :Result:='mmDPHY_MACRO_CNTL_RESERVED57';
  mmDPHY_MACRO_CNTL_RESERVED58                             :Result:='mmDPHY_MACRO_CNTL_RESERVED58';
  mmDPHY_MACRO_CNTL_RESERVED59                             :Result:='mmDPHY_MACRO_CNTL_RESERVED59';
  mmDPHY_MACRO_CNTL_RESERVED60                             :Result:='mmDPHY_MACRO_CNTL_RESERVED60';
  mmDPHY_MACRO_CNTL_RESERVED61                             :Result:='mmDPHY_MACRO_CNTL_RESERVED61';
  mmDPHY_MACRO_CNTL_RESERVED62                             :Result:='mmDPHY_MACRO_CNTL_RESERVED62';
  mmDPHY_MACRO_CNTL_RESERVED63                             :Result:='mmDPHY_MACRO_CNTL_RESERVED63';
  mmWB_ENABLE                                              :Result:='mmWB_ENABLE';
  mmWB_EC_CONFIG                                           :Result:='mmWB_EC_CONFIG';
  mmCNV_MODE                                               :Result:='mmCNV_MODE';
  mmCNV_WINDOW_START                                       :Result:='mmCNV_WINDOW_START';
  mmCNV_WINDOW_SIZE                                        :Result:='mmCNV_WINDOW_SIZE';
  mmCNV_UPDATE                                             :Result:='mmCNV_UPDATE';
  mmCNV_SOURCE_SIZE                                        :Result:='mmCNV_SOURCE_SIZE';
  mmCNV_CSC_CONTROL                                        :Result:='mmCNV_CSC_CONTROL';
  mmCNV_CSC_C11_C12                                        :Result:='mmCNV_CSC_C11_C12';
  mmCNV_CSC_C13_C14                                        :Result:='mmCNV_CSC_C13_C14';
  mmCNV_CSC_C21_C22                                        :Result:='mmCNV_CSC_C21_C22';
  mmCNV_CSC_C23_C24                                        :Result:='mmCNV_CSC_C23_C24';
  mmCNV_CSC_C31_C32                                        :Result:='mmCNV_CSC_C31_C32';
  mmCNV_CSC_C33_C34                                        :Result:='mmCNV_CSC_C33_C34';
  mmCNV_CSC_ROUND_OFFSET_R                                 :Result:='mmCNV_CSC_ROUND_OFFSET_R';
  mmCNV_CSC_ROUND_OFFSET_G                                 :Result:='mmCNV_CSC_ROUND_OFFSET_G';
  mmCNV_CSC_ROUND_OFFSET_B                                 :Result:='mmCNV_CSC_ROUND_OFFSET_B';
  mmCNV_CSC_CLAMP_R                                        :Result:='mmCNV_CSC_CLAMP_R';
  mmCNV_CSC_CLAMP_G                                        :Result:='mmCNV_CSC_CLAMP_G';
  mmCNV_CSC_CLAMP_B                                        :Result:='mmCNV_CSC_CLAMP_B';
  mmCNV_TEST_CNTL                                          :Result:='mmCNV_TEST_CNTL';
  mmCNV_TEST_CRC_RED                                       :Result:='mmCNV_TEST_CRC_RED';
  mmCNV_TEST_CRC_GREEN                                     :Result:='mmCNV_TEST_CRC_GREEN';
  mmCNV_TEST_CRC_BLUE                                      :Result:='mmCNV_TEST_CRC_BLUE';
  mmWB_DEBUG_CTRL                                          :Result:='mmWB_DEBUG_CTRL';
  mmWB_DBG_MODE                                            :Result:='mmWB_DBG_MODE';
  mmWB_HW_DEBUG                                            :Result:='mmWB_HW_DEBUG';
  mmCNV_INPUT_SELECT                                       :Result:='mmCNV_INPUT_SELECT';
  mmCNV_TEST_DEBUG_INDEX                                   :Result:='mmCNV_TEST_DEBUG_INDEX';
  mmCNV_TEST_DEBUG_DATA                                    :Result:='mmCNV_TEST_DEBUG_DATA';
  mmWB_SOFT_RESET                                          :Result:='mmWB_SOFT_RESET';
  mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                     :Result:='mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL';
  mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R                     :Result:='mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R';
  mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS                         :Result:='mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS';
  mmMCIF_WB0_MCIF_WB_BUF_PITCH                             :Result:='mmMCIF_WB0_MCIF_WB_BUF_PITCH';
  mmMCIF_WB0_MCIF_WB_BUF_1_STATUS                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_STATUS';
  mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2                         :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2';
  mmMCIF_WB0_MCIF_WB_BUF_2_STATUS                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_STATUS';
  mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2                         :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2';
  mmMCIF_WB0_MCIF_WB_BUF_3_STATUS                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_STATUS';
  mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2                         :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2';
  mmMCIF_WB0_MCIF_WB_BUF_4_STATUS                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_STATUS';
  mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2                         :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2';
  mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL                   :Result:='mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL';
  mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK                     :Result:='mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK';
  mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX                      :Result:='mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX';
  mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA                       :Result:='mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA';
  mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y';
  mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET';
  mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C';
  mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET                   :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET';
  mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y';
  mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET';
  mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C';
  mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET                   :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET';
  mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y';
  mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET';
  mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C';
  mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET                   :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET';
  mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y';
  mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET';
  mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C                          :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C';
  mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET                   :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET';
  mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL                    :Result:='mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL';
  mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL                        :Result:='mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL';
  mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                     :Result:='mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL';
  mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R                     :Result:='mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R';
  mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS                         :Result:='mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS';
  mmMCIF_WB1_MCIF_WB_BUF_PITCH                             :Result:='mmMCIF_WB1_MCIF_WB_BUF_PITCH';
  mmMCIF_WB1_MCIF_WB_BUF_1_STATUS                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_STATUS';
  mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2                         :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2';
  mmMCIF_WB1_MCIF_WB_BUF_2_STATUS                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_STATUS';
  mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2                         :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2';
  mmMCIF_WB1_MCIF_WB_BUF_3_STATUS                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_STATUS';
  mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2                         :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2';
  mmMCIF_WB1_MCIF_WB_BUF_4_STATUS                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_STATUS';
  mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2                         :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2';
  mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL                   :Result:='mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL';
  mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK                     :Result:='mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK';
  mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX                      :Result:='mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX';
  mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA                       :Result:='mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA';
  mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y';
  mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET';
  mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C';
  mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET                   :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET';
  mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y';
  mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET';
  mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C';
  mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET                   :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET';
  mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y';
  mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET';
  mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C';
  mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET                   :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET';
  mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y';
  mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET';
  mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C                          :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C';
  mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET                   :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET';
  mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL                    :Result:='mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL';
  mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL                        :Result:='mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL';
  mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL                     :Result:='mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL';
  mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R                     :Result:='mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R';
  mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS                         :Result:='mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS';
  mmMCIF_WB2_MCIF_WB_BUF_PITCH                             :Result:='mmMCIF_WB2_MCIF_WB_BUF_PITCH';
  mmMCIF_WB2_MCIF_WB_BUF_1_STATUS                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_STATUS';
  mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2                         :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2';
  mmMCIF_WB2_MCIF_WB_BUF_2_STATUS                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_STATUS';
  mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2                         :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2';
  mmMCIF_WB2_MCIF_WB_BUF_3_STATUS                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_STATUS';
  mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2                         :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2';
  mmMCIF_WB2_MCIF_WB_BUF_4_STATUS                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_STATUS';
  mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2                         :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2';
  mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL                   :Result:='mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL';
  mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK                     :Result:='mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK';
  mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX                      :Result:='mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX';
  mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA                       :Result:='mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA';
  mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y';
  mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET';
  mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C';
  mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET                   :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET';
  mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y';
  mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET';
  mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C';
  mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET                   :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET';
  mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y';
  mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET';
  mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C';
  mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET                   :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET';
  mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y';
  mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET                   :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET';
  mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C                          :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C';
  mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET                   :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET';
  mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL                    :Result:='mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL';
  mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL                        :Result:='mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL';
  mmDC_PERFMON9_PERFCOUNTER_CNTL                           :Result:='mmDC_PERFMON9_PERFCOUNTER_CNTL';
  mmDC_PERFMON9_PERFCOUNTER_STATE                          :Result:='mmDC_PERFMON9_PERFCOUNTER_STATE';
  mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                    :Result:='mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC';
  mmDC_PERFMON9_PERFMON_CNTL                               :Result:='mmDC_PERFMON9_PERFMON_CNTL';
  mmDC_PERFMON9_PERFMON_CVALUE_LOW                         :Result:='mmDC_PERFMON9_PERFMON_CVALUE_LOW';
  mmDC_PERFMON9_PERFMON_HI                                 :Result:='mmDC_PERFMON9_PERFMON_HI';
  mmDC_PERFMON9_PERFMON_LOW                                :Result:='mmDC_PERFMON9_PERFMON_LOW';
  mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX                   :Result:='mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX';
  mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA                    :Result:='mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA';
  mmDC_PERFMON9_PERFMON_CNTL2                              :Result:='mmDC_PERFMON9_PERFMON_CNTL2';
  mmCPLL_MACRO_CNTL_RESERVED0                              :Result:='mmCPLL_MACRO_CNTL_RESERVED0';
  mmCPLL_MACRO_CNTL_RESERVED1                              :Result:='mmCPLL_MACRO_CNTL_RESERVED1';
  mmCPLL_MACRO_CNTL_RESERVED2                              :Result:='mmCPLL_MACRO_CNTL_RESERVED2';
  mmCPLL_MACRO_CNTL_RESERVED3                              :Result:='mmCPLL_MACRO_CNTL_RESERVED3';
  mmCPLL_MACRO_CNTL_RESERVED4                              :Result:='mmCPLL_MACRO_CNTL_RESERVED4';
  mmCPLL_MACRO_CNTL_RESERVED5                              :Result:='mmCPLL_MACRO_CNTL_RESERVED5';
  mmCPLL_MACRO_CNTL_RESERVED6                              :Result:='mmCPLL_MACRO_CNTL_RESERVED6';
  mmCPLL_MACRO_CNTL_RESERVED7                              :Result:='mmCPLL_MACRO_CNTL_RESERVED7';
  mmCPLL_MACRO_CNTL_RESERVED8                              :Result:='mmCPLL_MACRO_CNTL_RESERVED8';
  mmCPLL_MACRO_CNTL_RESERVED9                              :Result:='mmCPLL_MACRO_CNTL_RESERVED9';
  mmCPLL_MACRO_CNTL_RESERVED10                             :Result:='mmCPLL_MACRO_CNTL_RESERVED10';
  mmCPLL_MACRO_CNTL_RESERVED11                             :Result:='mmCPLL_MACRO_CNTL_RESERVED11';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0                   :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1                   :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2                   :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3                   :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4                   :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5                   :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6                   :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7                   :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8                   :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9                   :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10                  :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10';
  mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11                  :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0                   :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1                   :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2                   :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3                   :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4                   :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5                   :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6                   :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7                   :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8                   :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9                   :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10                  :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10';
  mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11                  :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0                   :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1                   :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2                   :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3                   :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4                   :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5                   :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6                   :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7                   :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8                   :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9                   :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10                  :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10';
  mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11                  :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11';
  mmSRBM_PERFMON_CNTL                                      :Result:='mmSRBM_PERFMON_CNTL';
  mmSRBM_PERFCOUNTER0_SELECT                               :Result:='mmSRBM_PERFCOUNTER0_SELECT';
  mmSRBM_PERFCOUNTER1_SELECT                               :Result:='mmSRBM_PERFCOUNTER1_SELECT';
  mmSRBM_PERFCOUNTER0_LO                                   :Result:='mmSRBM_PERFCOUNTER0_LO';
  mmSRBM_PERFCOUNTER0_HI                                   :Result:='mmSRBM_PERFCOUNTER0_HI';
  mmSRBM_PERFCOUNTER1_LO                                   :Result:='mmSRBM_PERFCOUNTER1_LO';
  mmSRBM_PERFCOUNTER1_HI                                   :Result:='mmSRBM_PERFCOUNTER1_HI';
  mmVCE_STATUS                                             :Result:='mmVCE_STATUS';
  mmVCE_VCPU_CNTL                                          :Result:='mmVCE_VCPU_CNTL';
  mmVCE_VCPU_CACHE_OFFSET0                                 :Result:='mmVCE_VCPU_CACHE_OFFSET0';
  mmVCE_VCPU_CACHE_SIZE0                                   :Result:='mmVCE_VCPU_CACHE_SIZE0';
  mmVCE_VCPU_CACHE_OFFSET1                                 :Result:='mmVCE_VCPU_CACHE_OFFSET1';
  mmVCE_VCPU_CACHE_SIZE1                                   :Result:='mmVCE_VCPU_CACHE_SIZE1';
  mmVCE_VCPU_CACHE_OFFSET2                                 :Result:='mmVCE_VCPU_CACHE_OFFSET2';
  mmVCE_VCPU_CACHE_SIZE2                                   :Result:='mmVCE_VCPU_CACHE_SIZE2';
  mmVCE_SOFT_RESET                                         :Result:='mmVCE_SOFT_RESET';
  mmVCE_RB_BASE_LO2                                        :Result:='mmVCE_RB_BASE_LO2';
  mmVCE_RB_BASE_HI2                                        :Result:='mmVCE_RB_BASE_HI2';
  mmVCE_RB_SIZE2                                           :Result:='mmVCE_RB_SIZE2';
  mmVCE_RB_RPTR2                                           :Result:='mmVCE_RB_RPTR2';
  mmVCE_RB_WPTR2                                           :Result:='mmVCE_RB_WPTR2';
  mmVCE_RB_BASE_LO                                         :Result:='mmVCE_RB_BASE_LO';
  mmVCE_RB_BASE_HI                                         :Result:='mmVCE_RB_BASE_HI';
  mmVCE_RB_SIZE                                            :Result:='mmVCE_RB_SIZE';
  mmVCE_RB_RPTR                                            :Result:='mmVCE_RB_RPTR';
  mmVCE_RB_WPTR                                            :Result:='mmVCE_RB_WPTR';
  mmVCE_RB_ARB_CTRL                                        :Result:='mmVCE_RB_ARB_CTRL';
  mmVCE_RB_BASE_LO3                                        :Result:='mmVCE_RB_BASE_LO3';
  mmVCE_RB_BASE_HI3                                        :Result:='mmVCE_RB_BASE_HI3';
  mmVCE_RB_SIZE3                                           :Result:='mmVCE_RB_SIZE3';
  mmVCE_RB_RPTR3                                           :Result:='mmVCE_RB_RPTR3';
  mmVCE_RB_WPTR3                                           :Result:='mmVCE_RB_WPTR3';
  mmVCE_UENC_DMA_DCLK_CTRL                                 :Result:='mmVCE_UENC_DMA_DCLK_CTRL';
  mmVCE_SYS_INT_EN                                         :Result:='mmVCE_SYS_INT_EN';
  mmVCE_SYS_INT_ACK                                        :Result:='mmVCE_SYS_INT_ACK';
  mmVCE_LMI_VCPU_CACHE_40BIT_BAR                           :Result:='mmVCE_LMI_VCPU_CACHE_40BIT_BAR';
  mmVCE_LMI_CTRL2                                          :Result:='mmVCE_LMI_CTRL2';
  mmVCE_LMI_SWAP_CNTL3                                     :Result:='mmVCE_LMI_SWAP_CNTL3';
  mmVCE_LMI_CTRL                                           :Result:='mmVCE_LMI_CTRL';
  mmVCE_LMI_SWAP_CNTL                                      :Result:='mmVCE_LMI_SWAP_CNTL';
  mmVCE_LMI_SWAP_CNTL1                                     :Result:='mmVCE_LMI_SWAP_CNTL1';
  mmVCE_LMI_SWAP_CNTL2                                     :Result:='mmVCE_LMI_SWAP_CNTL2';
  mmVCE_LMI_CACHE_CTRL                                     :Result:='mmVCE_LMI_CACHE_CTRL';
  mmSAM_IH_EXT_ERR_INTR                                    :Result:='mmSAM_IH_EXT_ERR_INTR';
  mmSAM_IH_EXT_ERR_INTR_STATUS                             :Result:='mmSAM_IH_EXT_ERR_INTR_STATUS';
  mmSDMA0_PERFMON_CNTL                                     :Result:='mmSDMA0_PERFMON_CNTL';
  mmSDMA0_PERFCOUNTER0_RESULT                              :Result:='mmSDMA0_PERFCOUNTER0_RESULT';
  mmSDMA0_PERFCOUNTER1_RESULT                              :Result:='mmSDMA0_PERFCOUNTER1_RESULT';
  mmSDMA1_PERFMON_CNTL                                     :Result:='mmSDMA1_PERFMON_CNTL';
  mmSDMA1_PERFCOUNTER0_RESULT                              :Result:='mmSDMA1_PERFCOUNTER0_RESULT';
  mmSDMA1_PERFCOUNTER1_RESULT                              :Result:='mmSDMA1_PERFCOUNTER1_RESULT';
  mmDB_RENDER_CONTROL                                      :Result:='mmDB_RENDER_CONTROL';
  mmDB_COUNT_CONTROL                                       :Result:='mmDB_COUNT_CONTROL';
  mmDB_DEPTH_VIEW                                          :Result:='mmDB_DEPTH_VIEW';
  mmDB_RENDER_OVERRIDE                                     :Result:='mmDB_RENDER_OVERRIDE';
  mmDB_RENDER_OVERRIDE2                                    :Result:='mmDB_RENDER_OVERRIDE2';
  mmDB_HTILE_DATA_BASE                                     :Result:='mmDB_HTILE_DATA_BASE';
  mmDB_DEPTH_BOUNDS_MIN                                    :Result:='mmDB_DEPTH_BOUNDS_MIN';
  mmDB_DEPTH_BOUNDS_MAX                                    :Result:='mmDB_DEPTH_BOUNDS_MAX';
  mmDB_STENCIL_CLEAR                                       :Result:='mmDB_STENCIL_CLEAR';
  mmDB_DEPTH_CLEAR                                         :Result:='mmDB_DEPTH_CLEAR';
  mmPA_SC_SCREEN_SCISSOR_TL                                :Result:='mmPA_SC_SCREEN_SCISSOR_TL';
  mmPA_SC_SCREEN_SCISSOR_BR                                :Result:='mmPA_SC_SCREEN_SCISSOR_BR';
  mmDB_DEPTH_INFO                                          :Result:='mmDB_DEPTH_INFO';
  mmDB_Z_INFO                                              :Result:='mmDB_Z_INFO';
  mmDB_STENCIL_INFO                                        :Result:='mmDB_STENCIL_INFO';
  mmDB_Z_READ_BASE                                         :Result:='mmDB_Z_READ_BASE';
  mmDB_STENCIL_READ_BASE                                   :Result:='mmDB_STENCIL_READ_BASE';
  mmDB_Z_WRITE_BASE                                        :Result:='mmDB_Z_WRITE_BASE';
  mmDB_STENCIL_WRITE_BASE                                  :Result:='mmDB_STENCIL_WRITE_BASE';
  mmDB_DEPTH_SIZE                                          :Result:='mmDB_DEPTH_SIZE';
  mmDB_DEPTH_SLICE                                         :Result:='mmDB_DEPTH_SLICE';
  mmTA_BC_BASE_ADDR                                        :Result:='mmTA_BC_BASE_ADDR';
  mmTA_BC_BASE_ADDR_HI                                     :Result:='mmTA_BC_BASE_ADDR_HI';
  mmCOHER_DEST_BASE_HI_0                                   :Result:='mmCOHER_DEST_BASE_HI_0';
  mmCOHER_DEST_BASE_HI_1                                   :Result:='mmCOHER_DEST_BASE_HI_1';
  mmCOHER_DEST_BASE_HI_2                                   :Result:='mmCOHER_DEST_BASE_HI_2';
  mmCOHER_DEST_BASE_HI_3                                   :Result:='mmCOHER_DEST_BASE_HI_3';
  mmCOHER_DEST_BASE_2                                      :Result:='mmCOHER_DEST_BASE_2';
  mmCOHER_DEST_BASE_3                                      :Result:='mmCOHER_DEST_BASE_3';
  mmPA_SC_WINDOW_OFFSET                                    :Result:='mmPA_SC_WINDOW_OFFSET';
  mmPA_SC_WINDOW_SCISSOR_TL                                :Result:='mmPA_SC_WINDOW_SCISSOR_TL';
  mmPA_SC_WINDOW_SCISSOR_BR                                :Result:='mmPA_SC_WINDOW_SCISSOR_BR';
  mmPA_SC_CLIPRECT_RULE                                    :Result:='mmPA_SC_CLIPRECT_RULE';
  mmPA_SC_CLIPRECT_0_TL                                    :Result:='mmPA_SC_CLIPRECT_0_TL';
  mmPA_SC_CLIPRECT_0_BR                                    :Result:='mmPA_SC_CLIPRECT_0_BR';
  mmPA_SC_CLIPRECT_1_TL                                    :Result:='mmPA_SC_CLIPRECT_1_TL';
  mmPA_SC_CLIPRECT_1_BR                                    :Result:='mmPA_SC_CLIPRECT_1_BR';
  mmPA_SC_CLIPRECT_2_TL                                    :Result:='mmPA_SC_CLIPRECT_2_TL';
  mmPA_SC_CLIPRECT_2_BR                                    :Result:='mmPA_SC_CLIPRECT_2_BR';
  mmPA_SC_CLIPRECT_3_TL                                    :Result:='mmPA_SC_CLIPRECT_3_TL';
  mmPA_SC_CLIPRECT_3_BR                                    :Result:='mmPA_SC_CLIPRECT_3_BR';
  mmPA_SC_EDGERULE                                         :Result:='mmPA_SC_EDGERULE';
  mmPA_SU_HARDWARE_SCREEN_OFFSET                           :Result:='mmPA_SU_HARDWARE_SCREEN_OFFSET';
  mmCB_TARGET_MASK                                         :Result:='mmCB_TARGET_MASK';
  mmCB_SHADER_MASK                                         :Result:='mmCB_SHADER_MASK';
  mmPA_SC_GENERIC_SCISSOR_TL                               :Result:='mmPA_SC_GENERIC_SCISSOR_TL';
  mmPA_SC_GENERIC_SCISSOR_BR                               :Result:='mmPA_SC_GENERIC_SCISSOR_BR';
  mmCOHER_DEST_BASE_0                                      :Result:='mmCOHER_DEST_BASE_0';
  mmCOHER_DEST_BASE_1                                      :Result:='mmCOHER_DEST_BASE_1';
  mmPA_SC_VPORT_SCISSOR_0_TL                               :Result:='mmPA_SC_VPORT_SCISSOR_0_TL';
  mmPA_SC_VPORT_SCISSOR_0_BR                               :Result:='mmPA_SC_VPORT_SCISSOR_0_BR';
  mmPA_SC_VPORT_SCISSOR_1_TL                               :Result:='mmPA_SC_VPORT_SCISSOR_1_TL';
  mmPA_SC_VPORT_SCISSOR_1_BR                               :Result:='mmPA_SC_VPORT_SCISSOR_1_BR';
  mmPA_SC_VPORT_SCISSOR_2_TL                               :Result:='mmPA_SC_VPORT_SCISSOR_2_TL';
  mmPA_SC_VPORT_SCISSOR_2_BR                               :Result:='mmPA_SC_VPORT_SCISSOR_2_BR';
  mmPA_SC_VPORT_SCISSOR_3_TL                               :Result:='mmPA_SC_VPORT_SCISSOR_3_TL';
  mmPA_SC_VPORT_SCISSOR_3_BR                               :Result:='mmPA_SC_VPORT_SCISSOR_3_BR';
  mmPA_SC_VPORT_SCISSOR_4_TL                               :Result:='mmPA_SC_VPORT_SCISSOR_4_TL';
  mmPA_SC_VPORT_SCISSOR_4_BR                               :Result:='mmPA_SC_VPORT_SCISSOR_4_BR';
  mmPA_SC_VPORT_SCISSOR_5_TL                               :Result:='mmPA_SC_VPORT_SCISSOR_5_TL';
  mmPA_SC_VPORT_SCISSOR_5_BR                               :Result:='mmPA_SC_VPORT_SCISSOR_5_BR';
  mmPA_SC_VPORT_SCISSOR_6_TL                               :Result:='mmPA_SC_VPORT_SCISSOR_6_TL';
  mmPA_SC_VPORT_SCISSOR_6_BR                               :Result:='mmPA_SC_VPORT_SCISSOR_6_BR';
  mmPA_SC_VPORT_SCISSOR_7_TL                               :Result:='mmPA_SC_VPORT_SCISSOR_7_TL';
  mmPA_SC_VPORT_SCISSOR_7_BR                               :Result:='mmPA_SC_VPORT_SCISSOR_7_BR';
  mmPA_SC_VPORT_SCISSOR_8_TL                               :Result:='mmPA_SC_VPORT_SCISSOR_8_TL';
  mmPA_SC_VPORT_SCISSOR_8_BR                               :Result:='mmPA_SC_VPORT_SCISSOR_8_BR';
  mmPA_SC_VPORT_SCISSOR_9_TL                               :Result:='mmPA_SC_VPORT_SCISSOR_9_TL';
  mmPA_SC_VPORT_SCISSOR_9_BR                               :Result:='mmPA_SC_VPORT_SCISSOR_9_BR';
  mmPA_SC_VPORT_SCISSOR_10_TL                              :Result:='mmPA_SC_VPORT_SCISSOR_10_TL';
  mmPA_SC_VPORT_SCISSOR_10_BR                              :Result:='mmPA_SC_VPORT_SCISSOR_10_BR';
  mmPA_SC_VPORT_SCISSOR_11_TL                              :Result:='mmPA_SC_VPORT_SCISSOR_11_TL';
  mmPA_SC_VPORT_SCISSOR_11_BR                              :Result:='mmPA_SC_VPORT_SCISSOR_11_BR';
  mmPA_SC_VPORT_SCISSOR_12_TL                              :Result:='mmPA_SC_VPORT_SCISSOR_12_TL';
  mmPA_SC_VPORT_SCISSOR_12_BR                              :Result:='mmPA_SC_VPORT_SCISSOR_12_BR';
  mmPA_SC_VPORT_SCISSOR_13_TL                              :Result:='mmPA_SC_VPORT_SCISSOR_13_TL';
  mmPA_SC_VPORT_SCISSOR_13_BR                              :Result:='mmPA_SC_VPORT_SCISSOR_13_BR';
  mmPA_SC_VPORT_SCISSOR_14_TL                              :Result:='mmPA_SC_VPORT_SCISSOR_14_TL';
  mmPA_SC_VPORT_SCISSOR_14_BR                              :Result:='mmPA_SC_VPORT_SCISSOR_14_BR';
  mmPA_SC_VPORT_SCISSOR_15_TL                              :Result:='mmPA_SC_VPORT_SCISSOR_15_TL';
  mmPA_SC_VPORT_SCISSOR_15_BR                              :Result:='mmPA_SC_VPORT_SCISSOR_15_BR';
  mmPA_SC_VPORT_ZMIN_0                                     :Result:='mmPA_SC_VPORT_ZMIN_0';
  mmPA_SC_VPORT_ZMAX_0                                     :Result:='mmPA_SC_VPORT_ZMAX_0';
  mmPA_SC_VPORT_ZMIN_1                                     :Result:='mmPA_SC_VPORT_ZMIN_1';
  mmPA_SC_VPORT_ZMAX_1                                     :Result:='mmPA_SC_VPORT_ZMAX_1';
  mmPA_SC_VPORT_ZMIN_2                                     :Result:='mmPA_SC_VPORT_ZMIN_2';
  mmPA_SC_VPORT_ZMAX_2                                     :Result:='mmPA_SC_VPORT_ZMAX_2';
  mmPA_SC_VPORT_ZMIN_3                                     :Result:='mmPA_SC_VPORT_ZMIN_3';
  mmPA_SC_VPORT_ZMAX_3                                     :Result:='mmPA_SC_VPORT_ZMAX_3';
  mmPA_SC_VPORT_ZMIN_4                                     :Result:='mmPA_SC_VPORT_ZMIN_4';
  mmPA_SC_VPORT_ZMAX_4                                     :Result:='mmPA_SC_VPORT_ZMAX_4';
  mmPA_SC_VPORT_ZMIN_5                                     :Result:='mmPA_SC_VPORT_ZMIN_5';
  mmPA_SC_VPORT_ZMAX_5                                     :Result:='mmPA_SC_VPORT_ZMAX_5';
  mmPA_SC_VPORT_ZMIN_6                                     :Result:='mmPA_SC_VPORT_ZMIN_6';
  mmPA_SC_VPORT_ZMAX_6                                     :Result:='mmPA_SC_VPORT_ZMAX_6';
  mmPA_SC_VPORT_ZMIN_7                                     :Result:='mmPA_SC_VPORT_ZMIN_7';
  mmPA_SC_VPORT_ZMAX_7                                     :Result:='mmPA_SC_VPORT_ZMAX_7';
  mmPA_SC_VPORT_ZMIN_8                                     :Result:='mmPA_SC_VPORT_ZMIN_8';
  mmPA_SC_VPORT_ZMAX_8                                     :Result:='mmPA_SC_VPORT_ZMAX_8';
  mmPA_SC_VPORT_ZMIN_9                                     :Result:='mmPA_SC_VPORT_ZMIN_9';
  mmPA_SC_VPORT_ZMAX_9                                     :Result:='mmPA_SC_VPORT_ZMAX_9';
  mmPA_SC_VPORT_ZMIN_10                                    :Result:='mmPA_SC_VPORT_ZMIN_10';
  mmPA_SC_VPORT_ZMAX_10                                    :Result:='mmPA_SC_VPORT_ZMAX_10';
  mmPA_SC_VPORT_ZMIN_11                                    :Result:='mmPA_SC_VPORT_ZMIN_11';
  mmPA_SC_VPORT_ZMAX_11                                    :Result:='mmPA_SC_VPORT_ZMAX_11';
  mmPA_SC_VPORT_ZMIN_12                                    :Result:='mmPA_SC_VPORT_ZMIN_12';
  mmPA_SC_VPORT_ZMAX_12                                    :Result:='mmPA_SC_VPORT_ZMAX_12';
  mmPA_SC_VPORT_ZMIN_13                                    :Result:='mmPA_SC_VPORT_ZMIN_13';
  mmPA_SC_VPORT_ZMAX_13                                    :Result:='mmPA_SC_VPORT_ZMAX_13';
  mmPA_SC_VPORT_ZMIN_14                                    :Result:='mmPA_SC_VPORT_ZMIN_14';
  mmPA_SC_VPORT_ZMAX_14                                    :Result:='mmPA_SC_VPORT_ZMAX_14';
  mmPA_SC_VPORT_ZMIN_15                                    :Result:='mmPA_SC_VPORT_ZMIN_15';
  mmPA_SC_VPORT_ZMAX_15                                    :Result:='mmPA_SC_VPORT_ZMAX_15';
  mmPA_SC_RASTER_CONFIG                                    :Result:='mmPA_SC_RASTER_CONFIG';
  mmPA_SC_RASTER_CONFIG_1                                  :Result:='mmPA_SC_RASTER_CONFIG_1';
  mmCP_PERFMON_CNTX_CNTL                                   :Result:='mmCP_PERFMON_CNTX_CNTL';
  mmCP_PIPEID                                              :Result:='mmCP_PIPEID';
  mmCP_VMID                                                :Result:='mmCP_VMID';
  mmVGT_MAX_VTX_INDX                                       :Result:='mmVGT_MAX_VTX_INDX';
  mmVGT_MIN_VTX_INDX                                       :Result:='mmVGT_MIN_VTX_INDX';
  mmVGT_INDX_OFFSET                                        :Result:='mmVGT_INDX_OFFSET';
  mmVGT_MULTI_PRIM_IB_RESET_INDX                           :Result:='mmVGT_MULTI_PRIM_IB_RESET_INDX';
  mmCB_BLEND_RED                                           :Result:='mmCB_BLEND_RED';
  mmCB_BLEND_GREEN                                         :Result:='mmCB_BLEND_GREEN';
  mmCB_BLEND_BLUE                                          :Result:='mmCB_BLEND_BLUE';
  mmCB_BLEND_ALPHA                                         :Result:='mmCB_BLEND_ALPHA';
  mmCB_DCC_CONTROL                                         :Result:='mmCB_DCC_CONTROL';
  mmDB_STENCIL_CONTROL                                     :Result:='mmDB_STENCIL_CONTROL';
  mmDB_STENCILREFMASK                                      :Result:='mmDB_STENCILREFMASK';
  mmDB_STENCILREFMASK_BF                                   :Result:='mmDB_STENCILREFMASK_BF';
  mmPA_CL_VPORT_XSCALE                                     :Result:='mmPA_CL_VPORT_XSCALE';
  mmPA_CL_VPORT_XOFFSET                                    :Result:='mmPA_CL_VPORT_XOFFSET';
  mmPA_CL_VPORT_YSCALE                                     :Result:='mmPA_CL_VPORT_YSCALE';
  mmPA_CL_VPORT_YOFFSET                                    :Result:='mmPA_CL_VPORT_YOFFSET';
  mmPA_CL_VPORT_ZSCALE                                     :Result:='mmPA_CL_VPORT_ZSCALE';
  mmPA_CL_VPORT_ZOFFSET                                    :Result:='mmPA_CL_VPORT_ZOFFSET';
  mmPA_CL_VPORT_XSCALE_1                                   :Result:='mmPA_CL_VPORT_XSCALE_1';
  mmPA_CL_VPORT_XOFFSET_1                                  :Result:='mmPA_CL_VPORT_XOFFSET_1';
  mmPA_CL_VPORT_YSCALE_1                                   :Result:='mmPA_CL_VPORT_YSCALE_1';
  mmPA_CL_VPORT_YOFFSET_1                                  :Result:='mmPA_CL_VPORT_YOFFSET_1';
  mmPA_CL_VPORT_ZSCALE_1                                   :Result:='mmPA_CL_VPORT_ZSCALE_1';
  mmPA_CL_VPORT_ZOFFSET_1                                  :Result:='mmPA_CL_VPORT_ZOFFSET_1';
  mmPA_CL_VPORT_XSCALE_2                                   :Result:='mmPA_CL_VPORT_XSCALE_2';
  mmPA_CL_VPORT_XOFFSET_2                                  :Result:='mmPA_CL_VPORT_XOFFSET_2';
  mmPA_CL_VPORT_YSCALE_2                                   :Result:='mmPA_CL_VPORT_YSCALE_2';
  mmPA_CL_VPORT_YOFFSET_2                                  :Result:='mmPA_CL_VPORT_YOFFSET_2';
  mmPA_CL_VPORT_ZSCALE_2                                   :Result:='mmPA_CL_VPORT_ZSCALE_2';
  mmPA_CL_VPORT_ZOFFSET_2                                  :Result:='mmPA_CL_VPORT_ZOFFSET_2';
  mmPA_CL_VPORT_XSCALE_3                                   :Result:='mmPA_CL_VPORT_XSCALE_3';
  mmPA_CL_VPORT_XOFFSET_3                                  :Result:='mmPA_CL_VPORT_XOFFSET_3';
  mmPA_CL_VPORT_YSCALE_3                                   :Result:='mmPA_CL_VPORT_YSCALE_3';
  mmPA_CL_VPORT_YOFFSET_3                                  :Result:='mmPA_CL_VPORT_YOFFSET_3';
  mmPA_CL_VPORT_ZSCALE_3                                   :Result:='mmPA_CL_VPORT_ZSCALE_3';
  mmPA_CL_VPORT_ZOFFSET_3                                  :Result:='mmPA_CL_VPORT_ZOFFSET_3';
  mmPA_CL_VPORT_XSCALE_4                                   :Result:='mmPA_CL_VPORT_XSCALE_4';
  mmPA_CL_VPORT_XOFFSET_4                                  :Result:='mmPA_CL_VPORT_XOFFSET_4';
  mmPA_CL_VPORT_YSCALE_4                                   :Result:='mmPA_CL_VPORT_YSCALE_4';
  mmPA_CL_VPORT_YOFFSET_4                                  :Result:='mmPA_CL_VPORT_YOFFSET_4';
  mmPA_CL_VPORT_ZSCALE_4                                   :Result:='mmPA_CL_VPORT_ZSCALE_4';
  mmPA_CL_VPORT_ZOFFSET_4                                  :Result:='mmPA_CL_VPORT_ZOFFSET_4';
  mmPA_CL_VPORT_XSCALE_5                                   :Result:='mmPA_CL_VPORT_XSCALE_5';
  mmPA_CL_VPORT_XOFFSET_5                                  :Result:='mmPA_CL_VPORT_XOFFSET_5';
  mmPA_CL_VPORT_YSCALE_5                                   :Result:='mmPA_CL_VPORT_YSCALE_5';
  mmPA_CL_VPORT_YOFFSET_5                                  :Result:='mmPA_CL_VPORT_YOFFSET_5';
  mmPA_CL_VPORT_ZSCALE_5                                   :Result:='mmPA_CL_VPORT_ZSCALE_5';
  mmPA_CL_VPORT_ZOFFSET_5                                  :Result:='mmPA_CL_VPORT_ZOFFSET_5';
  mmPA_CL_VPORT_XSCALE_6                                   :Result:='mmPA_CL_VPORT_XSCALE_6';
  mmPA_CL_VPORT_XOFFSET_6                                  :Result:='mmPA_CL_VPORT_XOFFSET_6';
  mmPA_CL_VPORT_YSCALE_6                                   :Result:='mmPA_CL_VPORT_YSCALE_6';
  mmPA_CL_VPORT_YOFFSET_6                                  :Result:='mmPA_CL_VPORT_YOFFSET_6';
  mmPA_CL_VPORT_ZSCALE_6                                   :Result:='mmPA_CL_VPORT_ZSCALE_6';
  mmPA_CL_VPORT_ZOFFSET_6                                  :Result:='mmPA_CL_VPORT_ZOFFSET_6';
  mmPA_CL_VPORT_XSCALE_7                                   :Result:='mmPA_CL_VPORT_XSCALE_7';
  mmPA_CL_VPORT_XOFFSET_7                                  :Result:='mmPA_CL_VPORT_XOFFSET_7';
  mmPA_CL_VPORT_YSCALE_7                                   :Result:='mmPA_CL_VPORT_YSCALE_7';
  mmPA_CL_VPORT_YOFFSET_7                                  :Result:='mmPA_CL_VPORT_YOFFSET_7';
  mmPA_CL_VPORT_ZSCALE_7                                   :Result:='mmPA_CL_VPORT_ZSCALE_7';
  mmPA_CL_VPORT_ZOFFSET_7                                  :Result:='mmPA_CL_VPORT_ZOFFSET_7';
  mmPA_CL_VPORT_XSCALE_8                                   :Result:='mmPA_CL_VPORT_XSCALE_8';
  mmPA_CL_VPORT_XOFFSET_8                                  :Result:='mmPA_CL_VPORT_XOFFSET_8';
  mmPA_CL_VPORT_YSCALE_8                                   :Result:='mmPA_CL_VPORT_YSCALE_8';
  mmPA_CL_VPORT_YOFFSET_8                                  :Result:='mmPA_CL_VPORT_YOFFSET_8';
  mmPA_CL_VPORT_ZSCALE_8                                   :Result:='mmPA_CL_VPORT_ZSCALE_8';
  mmPA_CL_VPORT_ZOFFSET_8                                  :Result:='mmPA_CL_VPORT_ZOFFSET_8';
  mmPA_CL_VPORT_XSCALE_9                                   :Result:='mmPA_CL_VPORT_XSCALE_9';
  mmPA_CL_VPORT_XOFFSET_9                                  :Result:='mmPA_CL_VPORT_XOFFSET_9';
  mmPA_CL_VPORT_YSCALE_9                                   :Result:='mmPA_CL_VPORT_YSCALE_9';
  mmPA_CL_VPORT_YOFFSET_9                                  :Result:='mmPA_CL_VPORT_YOFFSET_9';
  mmPA_CL_VPORT_ZSCALE_9                                   :Result:='mmPA_CL_VPORT_ZSCALE_9';
  mmPA_CL_VPORT_ZOFFSET_9                                  :Result:='mmPA_CL_VPORT_ZOFFSET_9';
  mmPA_CL_VPORT_XSCALE_10                                  :Result:='mmPA_CL_VPORT_XSCALE_10';
  mmPA_CL_VPORT_XOFFSET_10                                 :Result:='mmPA_CL_VPORT_XOFFSET_10';
  mmPA_CL_VPORT_YSCALE_10                                  :Result:='mmPA_CL_VPORT_YSCALE_10';
  mmPA_CL_VPORT_YOFFSET_10                                 :Result:='mmPA_CL_VPORT_YOFFSET_10';
  mmPA_CL_VPORT_ZSCALE_10                                  :Result:='mmPA_CL_VPORT_ZSCALE_10';
  mmPA_CL_VPORT_ZOFFSET_10                                 :Result:='mmPA_CL_VPORT_ZOFFSET_10';
  mmPA_CL_VPORT_XSCALE_11                                  :Result:='mmPA_CL_VPORT_XSCALE_11';
  mmPA_CL_VPORT_XOFFSET_11                                 :Result:='mmPA_CL_VPORT_XOFFSET_11';
  mmPA_CL_VPORT_YSCALE_11                                  :Result:='mmPA_CL_VPORT_YSCALE_11';
  mmPA_CL_VPORT_YOFFSET_11                                 :Result:='mmPA_CL_VPORT_YOFFSET_11';
  mmPA_CL_VPORT_ZSCALE_11                                  :Result:='mmPA_CL_VPORT_ZSCALE_11';
  mmPA_CL_VPORT_ZOFFSET_11                                 :Result:='mmPA_CL_VPORT_ZOFFSET_11';
  mmPA_CL_VPORT_XSCALE_12                                  :Result:='mmPA_CL_VPORT_XSCALE_12';
  mmPA_CL_VPORT_XOFFSET_12                                 :Result:='mmPA_CL_VPORT_XOFFSET_12';
  mmPA_CL_VPORT_YSCALE_12                                  :Result:='mmPA_CL_VPORT_YSCALE_12';
  mmPA_CL_VPORT_YOFFSET_12                                 :Result:='mmPA_CL_VPORT_YOFFSET_12';
  mmPA_CL_VPORT_ZSCALE_12                                  :Result:='mmPA_CL_VPORT_ZSCALE_12';
  mmPA_CL_VPORT_ZOFFSET_12                                 :Result:='mmPA_CL_VPORT_ZOFFSET_12';
  mmPA_CL_VPORT_XSCALE_13                                  :Result:='mmPA_CL_VPORT_XSCALE_13';
  mmPA_CL_VPORT_XOFFSET_13                                 :Result:='mmPA_CL_VPORT_XOFFSET_13';
  mmPA_CL_VPORT_YSCALE_13                                  :Result:='mmPA_CL_VPORT_YSCALE_13';
  mmPA_CL_VPORT_YOFFSET_13                                 :Result:='mmPA_CL_VPORT_YOFFSET_13';
  mmPA_CL_VPORT_ZSCALE_13                                  :Result:='mmPA_CL_VPORT_ZSCALE_13';
  mmPA_CL_VPORT_ZOFFSET_13                                 :Result:='mmPA_CL_VPORT_ZOFFSET_13';
  mmPA_CL_VPORT_XSCALE_14                                  :Result:='mmPA_CL_VPORT_XSCALE_14';
  mmPA_CL_VPORT_XOFFSET_14                                 :Result:='mmPA_CL_VPORT_XOFFSET_14';
  mmPA_CL_VPORT_YSCALE_14                                  :Result:='mmPA_CL_VPORT_YSCALE_14';
  mmPA_CL_VPORT_YOFFSET_14                                 :Result:='mmPA_CL_VPORT_YOFFSET_14';
  mmPA_CL_VPORT_ZSCALE_14                                  :Result:='mmPA_CL_VPORT_ZSCALE_14';
  mmPA_CL_VPORT_ZOFFSET_14                                 :Result:='mmPA_CL_VPORT_ZOFFSET_14';
  mmPA_CL_VPORT_XSCALE_15                                  :Result:='mmPA_CL_VPORT_XSCALE_15';
  mmPA_CL_VPORT_XOFFSET_15                                 :Result:='mmPA_CL_VPORT_XOFFSET_15';
  mmPA_CL_VPORT_YSCALE_15                                  :Result:='mmPA_CL_VPORT_YSCALE_15';
  mmPA_CL_VPORT_YOFFSET_15                                 :Result:='mmPA_CL_VPORT_YOFFSET_15';
  mmPA_CL_VPORT_ZSCALE_15                                  :Result:='mmPA_CL_VPORT_ZSCALE_15';
  mmPA_CL_VPORT_ZOFFSET_15                                 :Result:='mmPA_CL_VPORT_ZOFFSET_15';
  mmPA_CL_UCP_0_X                                          :Result:='mmPA_CL_UCP_0_X';
  mmPA_CL_UCP_0_Y                                          :Result:='mmPA_CL_UCP_0_Y';
  mmPA_CL_UCP_0_Z                                          :Result:='mmPA_CL_UCP_0_Z';
  mmPA_CL_UCP_0_W                                          :Result:='mmPA_CL_UCP_0_W';
  mmPA_CL_UCP_1_X                                          :Result:='mmPA_CL_UCP_1_X';
  mmPA_CL_UCP_1_Y                                          :Result:='mmPA_CL_UCP_1_Y';
  mmPA_CL_UCP_1_Z                                          :Result:='mmPA_CL_UCP_1_Z';
  mmPA_CL_UCP_1_W                                          :Result:='mmPA_CL_UCP_1_W';
  mmPA_CL_UCP_2_X                                          :Result:='mmPA_CL_UCP_2_X';
  mmPA_CL_UCP_2_Y                                          :Result:='mmPA_CL_UCP_2_Y';
  mmPA_CL_UCP_2_Z                                          :Result:='mmPA_CL_UCP_2_Z';
  mmPA_CL_UCP_2_W                                          :Result:='mmPA_CL_UCP_2_W';
  mmPA_CL_UCP_3_X                                          :Result:='mmPA_CL_UCP_3_X';
  mmPA_CL_UCP_3_Y                                          :Result:='mmPA_CL_UCP_3_Y';
  mmPA_CL_UCP_3_Z                                          :Result:='mmPA_CL_UCP_3_Z';
  mmPA_CL_UCP_3_W                                          :Result:='mmPA_CL_UCP_3_W';
  mmPA_CL_UCP_4_X                                          :Result:='mmPA_CL_UCP_4_X';
  mmPA_CL_UCP_4_Y                                          :Result:='mmPA_CL_UCP_4_Y';
  mmPA_CL_UCP_4_Z                                          :Result:='mmPA_CL_UCP_4_Z';
  mmPA_CL_UCP_4_W                                          :Result:='mmPA_CL_UCP_4_W';
  mmPA_CL_UCP_5_X                                          :Result:='mmPA_CL_UCP_5_X';
  mmPA_CL_UCP_5_Y                                          :Result:='mmPA_CL_UCP_5_Y';
  mmPA_CL_UCP_5_Z                                          :Result:='mmPA_CL_UCP_5_Z';
  mmPA_CL_UCP_5_W                                          :Result:='mmPA_CL_UCP_5_W';
  mmSPI_PS_INPUT_CNTL_0                                    :Result:='mmSPI_PS_INPUT_CNTL_0';
  mmSPI_PS_INPUT_CNTL_1                                    :Result:='mmSPI_PS_INPUT_CNTL_1';
  mmSPI_PS_INPUT_CNTL_2                                    :Result:='mmSPI_PS_INPUT_CNTL_2';
  mmSPI_PS_INPUT_CNTL_3                                    :Result:='mmSPI_PS_INPUT_CNTL_3';
  mmSPI_PS_INPUT_CNTL_4                                    :Result:='mmSPI_PS_INPUT_CNTL_4';
  mmSPI_PS_INPUT_CNTL_5                                    :Result:='mmSPI_PS_INPUT_CNTL_5';
  mmSPI_PS_INPUT_CNTL_6                                    :Result:='mmSPI_PS_INPUT_CNTL_6';
  mmSPI_PS_INPUT_CNTL_7                                    :Result:='mmSPI_PS_INPUT_CNTL_7';
  mmSPI_PS_INPUT_CNTL_8                                    :Result:='mmSPI_PS_INPUT_CNTL_8';
  mmSPI_PS_INPUT_CNTL_9                                    :Result:='mmSPI_PS_INPUT_CNTL_9';
  mmSPI_PS_INPUT_CNTL_10                                   :Result:='mmSPI_PS_INPUT_CNTL_10';
  mmSPI_PS_INPUT_CNTL_11                                   :Result:='mmSPI_PS_INPUT_CNTL_11';
  mmSPI_PS_INPUT_CNTL_12                                   :Result:='mmSPI_PS_INPUT_CNTL_12';
  mmSPI_PS_INPUT_CNTL_13                                   :Result:='mmSPI_PS_INPUT_CNTL_13';
  mmSPI_PS_INPUT_CNTL_14                                   :Result:='mmSPI_PS_INPUT_CNTL_14';
  mmSPI_PS_INPUT_CNTL_15                                   :Result:='mmSPI_PS_INPUT_CNTL_15';
  mmSPI_PS_INPUT_CNTL_16                                   :Result:='mmSPI_PS_INPUT_CNTL_16';
  mmSPI_PS_INPUT_CNTL_17                                   :Result:='mmSPI_PS_INPUT_CNTL_17';
  mmSPI_PS_INPUT_CNTL_18                                   :Result:='mmSPI_PS_INPUT_CNTL_18';
  mmSPI_PS_INPUT_CNTL_19                                   :Result:='mmSPI_PS_INPUT_CNTL_19';
  mmSPI_PS_INPUT_CNTL_20                                   :Result:='mmSPI_PS_INPUT_CNTL_20';
  mmSPI_PS_INPUT_CNTL_21                                   :Result:='mmSPI_PS_INPUT_CNTL_21';
  mmSPI_PS_INPUT_CNTL_22                                   :Result:='mmSPI_PS_INPUT_CNTL_22';
  mmSPI_PS_INPUT_CNTL_23                                   :Result:='mmSPI_PS_INPUT_CNTL_23';
  mmSPI_PS_INPUT_CNTL_24                                   :Result:='mmSPI_PS_INPUT_CNTL_24';
  mmSPI_PS_INPUT_CNTL_25                                   :Result:='mmSPI_PS_INPUT_CNTL_25';
  mmSPI_PS_INPUT_CNTL_26                                   :Result:='mmSPI_PS_INPUT_CNTL_26';
  mmSPI_PS_INPUT_CNTL_27                                   :Result:='mmSPI_PS_INPUT_CNTL_27';
  mmSPI_PS_INPUT_CNTL_28                                   :Result:='mmSPI_PS_INPUT_CNTL_28';
  mmSPI_PS_INPUT_CNTL_29                                   :Result:='mmSPI_PS_INPUT_CNTL_29';
  mmSPI_PS_INPUT_CNTL_30                                   :Result:='mmSPI_PS_INPUT_CNTL_30';
  mmSPI_PS_INPUT_CNTL_31                                   :Result:='mmSPI_PS_INPUT_CNTL_31';
  mmSPI_VS_OUT_CONFIG                                      :Result:='mmSPI_VS_OUT_CONFIG';
  mmSPI_PS_INPUT_ENA                                       :Result:='mmSPI_PS_INPUT_ENA';
  mmSPI_PS_INPUT_ADDR                                      :Result:='mmSPI_PS_INPUT_ADDR';
  mmSPI_INTERP_CONTROL_0                                   :Result:='mmSPI_INTERP_CONTROL_0';
  mmSPI_PS_IN_CONTROL                                      :Result:='mmSPI_PS_IN_CONTROL';
  mmSPI_BARYC_CNTL                                         :Result:='mmSPI_BARYC_CNTL';
  mmSPI_TMPRING_SIZE                                       :Result:='mmSPI_TMPRING_SIZE';
  mmSPI_SHADER_POS_FORMAT                                  :Result:='mmSPI_SHADER_POS_FORMAT';
  mmSPI_SHADER_Z_FORMAT                                    :Result:='mmSPI_SHADER_Z_FORMAT';
  mmSPI_SHADER_COL_FORMAT                                  :Result:='mmSPI_SHADER_COL_FORMAT';
  mmSX_PS_DOWNCONVERT                                      :Result:='mmSX_PS_DOWNCONVERT';
  mmSX_BLEND_OPT_EPSILON                                   :Result:='mmSX_BLEND_OPT_EPSILON';
  mmSX_BLEND_OPT_CONTROL                                   :Result:='mmSX_BLEND_OPT_CONTROL';
  mmSX_MRT0_BLEND_OPT                                      :Result:='mmSX_MRT0_BLEND_OPT';
  mmSX_MRT1_BLEND_OPT                                      :Result:='mmSX_MRT1_BLEND_OPT';
  mmSX_MRT2_BLEND_OPT                                      :Result:='mmSX_MRT2_BLEND_OPT';
  mmSX_MRT3_BLEND_OPT                                      :Result:='mmSX_MRT3_BLEND_OPT';
  mmSX_MRT4_BLEND_OPT                                      :Result:='mmSX_MRT4_BLEND_OPT';
  mmSX_MRT5_BLEND_OPT                                      :Result:='mmSX_MRT5_BLEND_OPT';
  mmSX_MRT6_BLEND_OPT                                      :Result:='mmSX_MRT6_BLEND_OPT';
  mmSX_MRT7_BLEND_OPT                                      :Result:='mmSX_MRT7_BLEND_OPT';
  mmCB_BLEND0_CONTROL                                      :Result:='mmCB_BLEND0_CONTROL';
  mmCB_BLEND1_CONTROL                                      :Result:='mmCB_BLEND1_CONTROL';
  mmCB_BLEND2_CONTROL                                      :Result:='mmCB_BLEND2_CONTROL';
  mmCB_BLEND3_CONTROL                                      :Result:='mmCB_BLEND3_CONTROL';
  mmCB_BLEND4_CONTROL                                      :Result:='mmCB_BLEND4_CONTROL';
  mmCB_BLEND5_CONTROL                                      :Result:='mmCB_BLEND5_CONTROL';
  mmCB_BLEND6_CONTROL                                      :Result:='mmCB_BLEND6_CONTROL';
  mmCB_BLEND7_CONTROL                                      :Result:='mmCB_BLEND7_CONTROL';
  mmCS_COPY_STATE                                          :Result:='mmCS_COPY_STATE';
  mmGFX_COPY_STATE                                         :Result:='mmGFX_COPY_STATE';
  mmPA_CL_POINT_X_RAD                                      :Result:='mmPA_CL_POINT_X_RAD';
  mmPA_CL_POINT_Y_RAD                                      :Result:='mmPA_CL_POINT_Y_RAD';
  mmPA_CL_POINT_SIZE                                       :Result:='mmPA_CL_POINT_SIZE';
  mmPA_CL_POINT_CULL_RAD                                   :Result:='mmPA_CL_POINT_CULL_RAD';
  mmVGT_DMA_BASE_HI                                        :Result:='mmVGT_DMA_BASE_HI';
  mmVGT_DMA_BASE                                           :Result:='mmVGT_DMA_BASE';
  mmVGT_DRAW_INITIATOR                                     :Result:='mmVGT_DRAW_INITIATOR';
  mmVGT_IMMED_DATA                                         :Result:='mmVGT_IMMED_DATA';
  mmVGT_EVENT_ADDRESS_REG                                  :Result:='mmVGT_EVENT_ADDRESS_REG';
  mmDB_DEPTH_CONTROL                                       :Result:='mmDB_DEPTH_CONTROL';
  mmDB_EQAA                                                :Result:='mmDB_EQAA';
  mmCB_COLOR_CONTROL                                       :Result:='mmCB_COLOR_CONTROL';
  mmDB_SHADER_CONTROL                                      :Result:='mmDB_SHADER_CONTROL';
  mmPA_CL_CLIP_CNTL                                        :Result:='mmPA_CL_CLIP_CNTL';
  mmPA_SU_SC_MODE_CNTL                                     :Result:='mmPA_SU_SC_MODE_CNTL';
  mmPA_CL_VTE_CNTL                                         :Result:='mmPA_CL_VTE_CNTL';
  mmPA_CL_VS_OUT_CNTL                                      :Result:='mmPA_CL_VS_OUT_CNTL';
  mmPA_CL_NANINF_CNTL                                      :Result:='mmPA_CL_NANINF_CNTL';
  mmPA_SU_LINE_STIPPLE_CNTL                                :Result:='mmPA_SU_LINE_STIPPLE_CNTL';
  mmPA_SU_LINE_STIPPLE_SCALE                               :Result:='mmPA_SU_LINE_STIPPLE_SCALE';
  mmPA_SU_PRIM_FILTER_CNTL                                 :Result:='mmPA_SU_PRIM_FILTER_CNTL';
  mmPA_SU_POINT_SIZE                                       :Result:='mmPA_SU_POINT_SIZE';
  mmPA_SU_POINT_MINMAX                                     :Result:='mmPA_SU_POINT_MINMAX';
  mmPA_SU_LINE_CNTL                                        :Result:='mmPA_SU_LINE_CNTL';
  mmPA_SC_LINE_STIPPLE                                     :Result:='mmPA_SC_LINE_STIPPLE';
  mmVGT_OUTPUT_PATH_CNTL                                   :Result:='mmVGT_OUTPUT_PATH_CNTL';
  mmVGT_HOS_CNTL                                           :Result:='mmVGT_HOS_CNTL';
  mmVGT_HOS_MAX_TESS_LEVEL                                 :Result:='mmVGT_HOS_MAX_TESS_LEVEL';
  mmVGT_HOS_MIN_TESS_LEVEL                                 :Result:='mmVGT_HOS_MIN_TESS_LEVEL';
  mmVGT_HOS_REUSE_DEPTH                                    :Result:='mmVGT_HOS_REUSE_DEPTH';
  mmVGT_GROUP_PRIM_TYPE                                    :Result:='mmVGT_GROUP_PRIM_TYPE';
  mmVGT_GROUP_FIRST_DECR                                   :Result:='mmVGT_GROUP_FIRST_DECR';
  mmVGT_GROUP_DECR                                         :Result:='mmVGT_GROUP_DECR';
  mmVGT_GROUP_VECT_0_CNTL                                  :Result:='mmVGT_GROUP_VECT_0_CNTL';
  mmVGT_GROUP_VECT_1_CNTL                                  :Result:='mmVGT_GROUP_VECT_1_CNTL';
  mmVGT_GROUP_VECT_0_FMT_CNTL                              :Result:='mmVGT_GROUP_VECT_0_FMT_CNTL';
  mmVGT_GROUP_VECT_1_FMT_CNTL                              :Result:='mmVGT_GROUP_VECT_1_FMT_CNTL';
  mmVGT_GS_MODE                                            :Result:='mmVGT_GS_MODE';
  mmVGT_GS_ONCHIP_CNTL                                     :Result:='mmVGT_GS_ONCHIP_CNTL';
  mmPA_SC_MODE_CNTL_0                                      :Result:='mmPA_SC_MODE_CNTL_0';
  mmPA_SC_MODE_CNTL_1                                      :Result:='mmPA_SC_MODE_CNTL_1';
  mmVGT_ENHANCE                                            :Result:='mmVGT_ENHANCE';
  mmVGT_GS_PER_ES                                          :Result:='mmVGT_GS_PER_ES';
  mmVGT_ES_PER_GS                                          :Result:='mmVGT_ES_PER_GS';
  mmVGT_GS_PER_VS                                          :Result:='mmVGT_GS_PER_VS';
  mmVGT_GSVS_RING_OFFSET_1                                 :Result:='mmVGT_GSVS_RING_OFFSET_1';
  mmVGT_GSVS_RING_OFFSET_2                                 :Result:='mmVGT_GSVS_RING_OFFSET_2';
  mmVGT_GSVS_RING_OFFSET_3                                 :Result:='mmVGT_GSVS_RING_OFFSET_3';
  mmVGT_GS_OUT_PRIM_TYPE                                   :Result:='mmVGT_GS_OUT_PRIM_TYPE';
  mmIA_ENHANCE                                             :Result:='mmIA_ENHANCE';
  mmVGT_DMA_SIZE                                           :Result:='mmVGT_DMA_SIZE';
  mmVGT_DMA_MAX_SIZE                                       :Result:='mmVGT_DMA_MAX_SIZE';
  mmVGT_DMA_INDEX_TYPE                                     :Result:='mmVGT_DMA_INDEX_TYPE';
  mmWD_ENHANCE                                             :Result:='mmWD_ENHANCE';
  mmVGT_PRIMITIVEID_EN                                     :Result:='mmVGT_PRIMITIVEID_EN';
  mmVGT_DMA_NUM_INSTANCES                                  :Result:='mmVGT_DMA_NUM_INSTANCES';
  mmVGT_PRIMITIVEID_RESET                                  :Result:='mmVGT_PRIMITIVEID_RESET';
  mmVGT_EVENT_INITIATOR                                    :Result:='mmVGT_EVENT_INITIATOR';
  mmVGT_MULTI_PRIM_IB_RESET_EN                             :Result:='mmVGT_MULTI_PRIM_IB_RESET_EN';
  mmVGT_INSTANCE_STEP_RATE_0                               :Result:='mmVGT_INSTANCE_STEP_RATE_0';
  mmVGT_INSTANCE_STEP_RATE_1                               :Result:='mmVGT_INSTANCE_STEP_RATE_1';
  mmIA_MULTI_VGT_PARAM                                     :Result:='mmIA_MULTI_VGT_PARAM';
  mmVGT_ESGS_RING_ITEMSIZE                                 :Result:='mmVGT_ESGS_RING_ITEMSIZE';
  mmVGT_GSVS_RING_ITEMSIZE                                 :Result:='mmVGT_GSVS_RING_ITEMSIZE';
  mmVGT_REUSE_OFF                                          :Result:='mmVGT_REUSE_OFF';
  mmVGT_VTX_CNT_EN                                         :Result:='mmVGT_VTX_CNT_EN';
  mmDB_HTILE_SURFACE                                       :Result:='mmDB_HTILE_SURFACE';
  mmDB_SRESULTS_COMPARE_STATE0                             :Result:='mmDB_SRESULTS_COMPARE_STATE0';
  mmDB_SRESULTS_COMPARE_STATE1                             :Result:='mmDB_SRESULTS_COMPARE_STATE1';
  mmDB_PRELOAD_CONTROL                                     :Result:='mmDB_PRELOAD_CONTROL';
  mmVGT_STRMOUT_BUFFER_SIZE_0                              :Result:='mmVGT_STRMOUT_BUFFER_SIZE_0';
  mmVGT_STRMOUT_VTX_STRIDE_0                               :Result:='mmVGT_STRMOUT_VTX_STRIDE_0';
  mmVGT_STRMOUT_BUFFER_OFFSET_0                            :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_0';
  mmVGT_STRMOUT_BUFFER_SIZE_1                              :Result:='mmVGT_STRMOUT_BUFFER_SIZE_1';
  mmVGT_STRMOUT_VTX_STRIDE_1                               :Result:='mmVGT_STRMOUT_VTX_STRIDE_1';
  mmVGT_STRMOUT_BUFFER_OFFSET_1                            :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_1';
  mmVGT_STRMOUT_BUFFER_SIZE_2                              :Result:='mmVGT_STRMOUT_BUFFER_SIZE_2';
  mmVGT_STRMOUT_VTX_STRIDE_2                               :Result:='mmVGT_STRMOUT_VTX_STRIDE_2';
  mmVGT_STRMOUT_BUFFER_OFFSET_2                            :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_2';
  mmVGT_STRMOUT_BUFFER_SIZE_3                              :Result:='mmVGT_STRMOUT_BUFFER_SIZE_3';
  mmVGT_STRMOUT_VTX_STRIDE_3                               :Result:='mmVGT_STRMOUT_VTX_STRIDE_3';
  mmVGT_STRMOUT_BUFFER_OFFSET_3                            :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_3';
  mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET                         :Result:='mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET';
  mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE             :Result:='mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE';
  mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE                  :Result:='mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE';
  mmVGT_GS_MAX_VERT_OUT                                    :Result:='mmVGT_GS_MAX_VERT_OUT';
  mmVGT_TESS_DISTRIBUTION                                  :Result:='mmVGT_TESS_DISTRIBUTION';
  mmVGT_SHADER_STAGES_EN                                   :Result:='mmVGT_SHADER_STAGES_EN';
  mmVGT_LS_HS_CONFIG                                       :Result:='mmVGT_LS_HS_CONFIG';
  mmVGT_GS_VERT_ITEMSIZE                                   :Result:='mmVGT_GS_VERT_ITEMSIZE';
  mmVGT_GS_VERT_ITEMSIZE_1                                 :Result:='mmVGT_GS_VERT_ITEMSIZE_1';
  mmVGT_GS_VERT_ITEMSIZE_2                                 :Result:='mmVGT_GS_VERT_ITEMSIZE_2';
  mmVGT_GS_VERT_ITEMSIZE_3                                 :Result:='mmVGT_GS_VERT_ITEMSIZE_3';
  mmVGT_TF_PARAM                                           :Result:='mmVGT_TF_PARAM';
  mmDB_ALPHA_TO_MASK                                       :Result:='mmDB_ALPHA_TO_MASK';
  mmVGT_DISPATCH_DRAW_INDEX                                :Result:='mmVGT_DISPATCH_DRAW_INDEX';
  mmPA_SU_POLY_OFFSET_DB_FMT_CNTL                          :Result:='mmPA_SU_POLY_OFFSET_DB_FMT_CNTL';
  mmPA_SU_POLY_OFFSET_CLAMP                                :Result:='mmPA_SU_POLY_OFFSET_CLAMP';
  mmPA_SU_POLY_OFFSET_FRONT_SCALE                          :Result:='mmPA_SU_POLY_OFFSET_FRONT_SCALE';
  mmPA_SU_POLY_OFFSET_FRONT_OFFSET                         :Result:='mmPA_SU_POLY_OFFSET_FRONT_OFFSET';
  mmPA_SU_POLY_OFFSET_BACK_SCALE                           :Result:='mmPA_SU_POLY_OFFSET_BACK_SCALE';
  mmPA_SU_POLY_OFFSET_BACK_OFFSET                          :Result:='mmPA_SU_POLY_OFFSET_BACK_OFFSET';
  mmVGT_GS_INSTANCE_CNT                                    :Result:='mmVGT_GS_INSTANCE_CNT';
  mmVGT_STRMOUT_CONFIG                                     :Result:='mmVGT_STRMOUT_CONFIG';
  mmVGT_STRMOUT_BUFFER_CONFIG                              :Result:='mmVGT_STRMOUT_BUFFER_CONFIG';
  mmPA_SC_CENTROID_PRIORITY_0                              :Result:='mmPA_SC_CENTROID_PRIORITY_0';
  mmPA_SC_CENTROID_PRIORITY_1                              :Result:='mmPA_SC_CENTROID_PRIORITY_1';
  mmPA_SC_LINE_CNTL                                        :Result:='mmPA_SC_LINE_CNTL';
  mmPA_SC_AA_CONFIG                                        :Result:='mmPA_SC_AA_CONFIG';
  mmPA_SU_VTX_CNTL                                         :Result:='mmPA_SU_VTX_CNTL';
  mmPA_CL_GB_VERT_CLIP_ADJ                                 :Result:='mmPA_CL_GB_VERT_CLIP_ADJ';
  mmPA_CL_GB_VERT_DISC_ADJ                                 :Result:='mmPA_CL_GB_VERT_DISC_ADJ';
  mmPA_CL_GB_HORZ_CLIP_ADJ                                 :Result:='mmPA_CL_GB_HORZ_CLIP_ADJ';
  mmPA_CL_GB_HORZ_DISC_ADJ                                 :Result:='mmPA_CL_GB_HORZ_DISC_ADJ';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2';
  mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3                      :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3';
  mmPA_SC_AA_MASK_X0Y0_X1Y0                                :Result:='mmPA_SC_AA_MASK_X0Y0_X1Y0';
  mmPA_SC_AA_MASK_X0Y1_X1Y1                                :Result:='mmPA_SC_AA_MASK_X0Y1_X1Y1';
  mmVGT_VERTEX_REUSE_BLOCK_CNTL                            :Result:='mmVGT_VERTEX_REUSE_BLOCK_CNTL';
  mmVGT_OUT_DEALLOC_CNTL                                   :Result:='mmVGT_OUT_DEALLOC_CNTL';
  mmCB_COLOR0_BASE                                         :Result:='mmCB_COLOR0_BASE';
  mmCB_COLOR0_PITCH                                        :Result:='mmCB_COLOR0_PITCH';
  mmCB_COLOR0_SLICE                                        :Result:='mmCB_COLOR0_SLICE';
  mmCB_COLOR0_VIEW                                         :Result:='mmCB_COLOR0_VIEW';
  mmCB_COLOR0_INFO                                         :Result:='mmCB_COLOR0_INFO';
  mmCB_COLOR0_ATTRIB                                       :Result:='mmCB_COLOR0_ATTRIB';
  mmCB_COLOR0_DCC_CONTROL                                  :Result:='mmCB_COLOR0_DCC_CONTROL';
  mmCB_COLOR0_CMASK                                        :Result:='mmCB_COLOR0_CMASK';
  mmCB_COLOR0_CMASK_SLICE                                  :Result:='mmCB_COLOR0_CMASK_SLICE';
  mmCB_COLOR0_FMASK                                        :Result:='mmCB_COLOR0_FMASK';
  mmCB_COLOR0_FMASK_SLICE                                  :Result:='mmCB_COLOR0_FMASK_SLICE';
  mmCB_COLOR0_CLEAR_WORD0                                  :Result:='mmCB_COLOR0_CLEAR_WORD0';
  mmCB_COLOR0_CLEAR_WORD1                                  :Result:='mmCB_COLOR0_CLEAR_WORD1';
  mmCB_COLOR0_DCC_BASE                                     :Result:='mmCB_COLOR0_DCC_BASE';
  mmCB_COLOR1_BASE                                         :Result:='mmCB_COLOR1_BASE';
  mmCB_COLOR1_PITCH                                        :Result:='mmCB_COLOR1_PITCH';
  mmCB_COLOR1_SLICE                                        :Result:='mmCB_COLOR1_SLICE';
  mmCB_COLOR1_VIEW                                         :Result:='mmCB_COLOR1_VIEW';
  mmCB_COLOR1_INFO                                         :Result:='mmCB_COLOR1_INFO';
  mmCB_COLOR1_ATTRIB                                       :Result:='mmCB_COLOR1_ATTRIB';
  mmCB_COLOR1_DCC_CONTROL                                  :Result:='mmCB_COLOR1_DCC_CONTROL';
  mmCB_COLOR1_CMASK                                        :Result:='mmCB_COLOR1_CMASK';
  mmCB_COLOR1_CMASK_SLICE                                  :Result:='mmCB_COLOR1_CMASK_SLICE';
  mmCB_COLOR1_FMASK                                        :Result:='mmCB_COLOR1_FMASK';
  mmCB_COLOR1_FMASK_SLICE                                  :Result:='mmCB_COLOR1_FMASK_SLICE';
  mmCB_COLOR1_CLEAR_WORD0                                  :Result:='mmCB_COLOR1_CLEAR_WORD0';
  mmCB_COLOR1_CLEAR_WORD1                                  :Result:='mmCB_COLOR1_CLEAR_WORD1';
  mmCB_COLOR1_DCC_BASE                                     :Result:='mmCB_COLOR1_DCC_BASE';
  mmCB_COLOR2_BASE                                         :Result:='mmCB_COLOR2_BASE';
  mmCB_COLOR2_PITCH                                        :Result:='mmCB_COLOR2_PITCH';
  mmCB_COLOR2_SLICE                                        :Result:='mmCB_COLOR2_SLICE';
  mmCB_COLOR2_VIEW                                         :Result:='mmCB_COLOR2_VIEW';
  mmCB_COLOR2_INFO                                         :Result:='mmCB_COLOR2_INFO';
  mmCB_COLOR2_ATTRIB                                       :Result:='mmCB_COLOR2_ATTRIB';
  mmCB_COLOR2_DCC_CONTROL                                  :Result:='mmCB_COLOR2_DCC_CONTROL';
  mmCB_COLOR2_CMASK                                        :Result:='mmCB_COLOR2_CMASK';
  mmCB_COLOR2_CMASK_SLICE                                  :Result:='mmCB_COLOR2_CMASK_SLICE';
  mmCB_COLOR2_FMASK                                        :Result:='mmCB_COLOR2_FMASK';
  mmCB_COLOR2_FMASK_SLICE                                  :Result:='mmCB_COLOR2_FMASK_SLICE';
  mmCB_COLOR2_CLEAR_WORD0                                  :Result:='mmCB_COLOR2_CLEAR_WORD0';
  mmCB_COLOR2_CLEAR_WORD1                                  :Result:='mmCB_COLOR2_CLEAR_WORD1';
  mmCB_COLOR2_DCC_BASE                                     :Result:='mmCB_COLOR2_DCC_BASE';
  mmCB_COLOR3_BASE                                         :Result:='mmCB_COLOR3_BASE';
  mmCB_COLOR3_PITCH                                        :Result:='mmCB_COLOR3_PITCH';
  mmCB_COLOR3_SLICE                                        :Result:='mmCB_COLOR3_SLICE';
  mmCB_COLOR3_VIEW                                         :Result:='mmCB_COLOR3_VIEW';
  mmCB_COLOR3_INFO                                         :Result:='mmCB_COLOR3_INFO';
  mmCB_COLOR3_ATTRIB                                       :Result:='mmCB_COLOR3_ATTRIB';
  mmCB_COLOR3_DCC_CONTROL                                  :Result:='mmCB_COLOR3_DCC_CONTROL';
  mmCB_COLOR3_CMASK                                        :Result:='mmCB_COLOR3_CMASK';
  mmCB_COLOR3_CMASK_SLICE                                  :Result:='mmCB_COLOR3_CMASK_SLICE';
  mmCB_COLOR3_FMASK                                        :Result:='mmCB_COLOR3_FMASK';
  mmCB_COLOR3_FMASK_SLICE                                  :Result:='mmCB_COLOR3_FMASK_SLICE';
  mmCB_COLOR3_CLEAR_WORD0                                  :Result:='mmCB_COLOR3_CLEAR_WORD0';
  mmCB_COLOR3_CLEAR_WORD1                                  :Result:='mmCB_COLOR3_CLEAR_WORD1';
  mmCB_COLOR3_DCC_BASE                                     :Result:='mmCB_COLOR3_DCC_BASE';
  mmCB_COLOR4_BASE                                         :Result:='mmCB_COLOR4_BASE';
  mmCB_COLOR4_PITCH                                        :Result:='mmCB_COLOR4_PITCH';
  mmCB_COLOR4_SLICE                                        :Result:='mmCB_COLOR4_SLICE';
  mmCB_COLOR4_VIEW                                         :Result:='mmCB_COLOR4_VIEW';
  mmCB_COLOR4_INFO                                         :Result:='mmCB_COLOR4_INFO';
  mmCB_COLOR4_ATTRIB                                       :Result:='mmCB_COLOR4_ATTRIB';
  mmCB_COLOR4_DCC_CONTROL                                  :Result:='mmCB_COLOR4_DCC_CONTROL';
  mmCB_COLOR4_CMASK                                        :Result:='mmCB_COLOR4_CMASK';
  mmCB_COLOR4_CMASK_SLICE                                  :Result:='mmCB_COLOR4_CMASK_SLICE';
  mmCB_COLOR4_FMASK                                        :Result:='mmCB_COLOR4_FMASK';
  mmCB_COLOR4_FMASK_SLICE                                  :Result:='mmCB_COLOR4_FMASK_SLICE';
  mmCB_COLOR4_CLEAR_WORD0                                  :Result:='mmCB_COLOR4_CLEAR_WORD0';
  mmCB_COLOR4_CLEAR_WORD1                                  :Result:='mmCB_COLOR4_CLEAR_WORD1';
  mmCB_COLOR4_DCC_BASE                                     :Result:='mmCB_COLOR4_DCC_BASE';
  mmCB_COLOR5_BASE                                         :Result:='mmCB_COLOR5_BASE';
  mmCB_COLOR5_PITCH                                        :Result:='mmCB_COLOR5_PITCH';
  mmCB_COLOR5_SLICE                                        :Result:='mmCB_COLOR5_SLICE';
  mmCB_COLOR5_VIEW                                         :Result:='mmCB_COLOR5_VIEW';
  mmCB_COLOR5_INFO                                         :Result:='mmCB_COLOR5_INFO';
  mmCB_COLOR5_ATTRIB                                       :Result:='mmCB_COLOR5_ATTRIB';
  mmCB_COLOR5_DCC_CONTROL                                  :Result:='mmCB_COLOR5_DCC_CONTROL';
  mmCB_COLOR5_CMASK                                        :Result:='mmCB_COLOR5_CMASK';
  mmCB_COLOR5_CMASK_SLICE                                  :Result:='mmCB_COLOR5_CMASK_SLICE';
  mmCB_COLOR5_FMASK                                        :Result:='mmCB_COLOR5_FMASK';
  mmCB_COLOR5_FMASK_SLICE                                  :Result:='mmCB_COLOR5_FMASK_SLICE';
  mmCB_COLOR5_CLEAR_WORD0                                  :Result:='mmCB_COLOR5_CLEAR_WORD0';
  mmCB_COLOR5_CLEAR_WORD1                                  :Result:='mmCB_COLOR5_CLEAR_WORD1';
  mmCB_COLOR5_DCC_BASE                                     :Result:='mmCB_COLOR5_DCC_BASE';
  mmCB_COLOR6_BASE                                         :Result:='mmCB_COLOR6_BASE';
  mmCB_COLOR6_PITCH                                        :Result:='mmCB_COLOR6_PITCH';
  mmCB_COLOR6_SLICE                                        :Result:='mmCB_COLOR6_SLICE';
  mmCB_COLOR6_VIEW                                         :Result:='mmCB_COLOR6_VIEW';
  mmCB_COLOR6_INFO                                         :Result:='mmCB_COLOR6_INFO';
  mmCB_COLOR6_ATTRIB                                       :Result:='mmCB_COLOR6_ATTRIB';
  mmCB_COLOR6_DCC_CONTROL                                  :Result:='mmCB_COLOR6_DCC_CONTROL';
  mmCB_COLOR6_CMASK                                        :Result:='mmCB_COLOR6_CMASK';
  mmCB_COLOR6_CMASK_SLICE                                  :Result:='mmCB_COLOR6_CMASK_SLICE';
  mmCB_COLOR6_FMASK                                        :Result:='mmCB_COLOR6_FMASK';
  mmCB_COLOR6_FMASK_SLICE                                  :Result:='mmCB_COLOR6_FMASK_SLICE';
  mmCB_COLOR6_CLEAR_WORD0                                  :Result:='mmCB_COLOR6_CLEAR_WORD0';
  mmCB_COLOR6_CLEAR_WORD1                                  :Result:='mmCB_COLOR6_CLEAR_WORD1';
  mmCB_COLOR6_DCC_BASE                                     :Result:='mmCB_COLOR6_DCC_BASE';
  mmCB_COLOR7_BASE                                         :Result:='mmCB_COLOR7_BASE';
  mmCB_COLOR7_PITCH                                        :Result:='mmCB_COLOR7_PITCH';
  mmCB_COLOR7_SLICE                                        :Result:='mmCB_COLOR7_SLICE';
  mmCB_COLOR7_VIEW                                         :Result:='mmCB_COLOR7_VIEW';
  mmCB_COLOR7_INFO                                         :Result:='mmCB_COLOR7_INFO';
  mmCB_COLOR7_ATTRIB                                       :Result:='mmCB_COLOR7_ATTRIB';
  mmCB_COLOR7_DCC_CONTROL                                  :Result:='mmCB_COLOR7_DCC_CONTROL';
  mmCB_COLOR7_CMASK                                        :Result:='mmCB_COLOR7_CMASK';
  mmCB_COLOR7_CMASK_SLICE                                  :Result:='mmCB_COLOR7_CMASK_SLICE';
  mmCB_COLOR7_FMASK                                        :Result:='mmCB_COLOR7_FMASK';
  mmCB_COLOR7_FMASK_SLICE                                  :Result:='mmCB_COLOR7_FMASK_SLICE';
  mmCB_COLOR7_CLEAR_WORD0                                  :Result:='mmCB_COLOR7_CLEAR_WORD0';
  mmCB_COLOR7_CLEAR_WORD1                                  :Result:='mmCB_COLOR7_CLEAR_WORD1';
  mmCB_COLOR7_DCC_BASE                                     :Result:='mmCB_COLOR7_DCC_BASE';
  mmCP_EOP_DONE_ADDR_LO                                    :Result:='mmCP_EOP_DONE_ADDR_LO';
  mmCP_EOP_DONE_ADDR_HI                                    :Result:='mmCP_EOP_DONE_ADDR_HI';
  mmCP_EOP_DONE_DATA_LO                                    :Result:='mmCP_EOP_DONE_DATA_LO';
  mmCP_EOP_DONE_DATA_HI                                    :Result:='mmCP_EOP_DONE_DATA_HI';
  mmCP_EOP_LAST_FENCE_LO                                   :Result:='mmCP_EOP_LAST_FENCE_LO';
  mmCP_EOP_LAST_FENCE_HI                                   :Result:='mmCP_EOP_LAST_FENCE_HI';
  mmCP_STREAM_OUT_ADDR_LO                                  :Result:='mmCP_STREAM_OUT_ADDR_LO';
  mmCP_STREAM_OUT_ADDR_HI                                  :Result:='mmCP_STREAM_OUT_ADDR_HI';
  mmCP_NUM_PRIM_WRITTEN_COUNT0_LO                          :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT0_LO';
  mmCP_NUM_PRIM_WRITTEN_COUNT0_HI                          :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT0_HI';
  mmCP_NUM_PRIM_NEEDED_COUNT0_LO                           :Result:='mmCP_NUM_PRIM_NEEDED_COUNT0_LO';
  mmCP_NUM_PRIM_NEEDED_COUNT0_HI                           :Result:='mmCP_NUM_PRIM_NEEDED_COUNT0_HI';
  mmCP_NUM_PRIM_WRITTEN_COUNT1_LO                          :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT1_LO';
  mmCP_NUM_PRIM_WRITTEN_COUNT1_HI                          :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT1_HI';
  mmCP_NUM_PRIM_NEEDED_COUNT1_LO                           :Result:='mmCP_NUM_PRIM_NEEDED_COUNT1_LO';
  mmCP_NUM_PRIM_NEEDED_COUNT1_HI                           :Result:='mmCP_NUM_PRIM_NEEDED_COUNT1_HI';
  mmCP_NUM_PRIM_WRITTEN_COUNT2_LO                          :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT2_LO';
  mmCP_NUM_PRIM_WRITTEN_COUNT2_HI                          :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT2_HI';
  mmCP_NUM_PRIM_NEEDED_COUNT2_LO                           :Result:='mmCP_NUM_PRIM_NEEDED_COUNT2_LO';
  mmCP_NUM_PRIM_NEEDED_COUNT2_HI                           :Result:='mmCP_NUM_PRIM_NEEDED_COUNT2_HI';
  mmCP_NUM_PRIM_WRITTEN_COUNT3_LO                          :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT3_LO';
  mmCP_NUM_PRIM_WRITTEN_COUNT3_HI                          :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT3_HI';
  mmCP_NUM_PRIM_NEEDED_COUNT3_LO                           :Result:='mmCP_NUM_PRIM_NEEDED_COUNT3_LO';
  mmCP_NUM_PRIM_NEEDED_COUNT3_HI                           :Result:='mmCP_NUM_PRIM_NEEDED_COUNT3_HI';
  mmCP_PIPE_STATS_ADDR_LO                                  :Result:='mmCP_PIPE_STATS_ADDR_LO';
  mmCP_PIPE_STATS_ADDR_HI                                  :Result:='mmCP_PIPE_STATS_ADDR_HI';
  mmCP_VGT_IAVERT_COUNT_LO                                 :Result:='mmCP_VGT_IAVERT_COUNT_LO';
  mmCP_VGT_IAVERT_COUNT_HI                                 :Result:='mmCP_VGT_IAVERT_COUNT_HI';
  mmCP_VGT_IAPRIM_COUNT_LO                                 :Result:='mmCP_VGT_IAPRIM_COUNT_LO';
  mmCP_VGT_IAPRIM_COUNT_HI                                 :Result:='mmCP_VGT_IAPRIM_COUNT_HI';
  mmCP_VGT_GSPRIM_COUNT_LO                                 :Result:='mmCP_VGT_GSPRIM_COUNT_LO';
  mmCP_VGT_GSPRIM_COUNT_HI                                 :Result:='mmCP_VGT_GSPRIM_COUNT_HI';
  mmCP_VGT_VSINVOC_COUNT_LO                                :Result:='mmCP_VGT_VSINVOC_COUNT_LO';
  mmCP_VGT_VSINVOC_COUNT_HI                                :Result:='mmCP_VGT_VSINVOC_COUNT_HI';
  mmCP_VGT_GSINVOC_COUNT_LO                                :Result:='mmCP_VGT_GSINVOC_COUNT_LO';
  mmCP_VGT_GSINVOC_COUNT_HI                                :Result:='mmCP_VGT_GSINVOC_COUNT_HI';
  mmCP_VGT_HSINVOC_COUNT_LO                                :Result:='mmCP_VGT_HSINVOC_COUNT_LO';
  mmCP_VGT_HSINVOC_COUNT_HI                                :Result:='mmCP_VGT_HSINVOC_COUNT_HI';
  mmCP_VGT_DSINVOC_COUNT_LO                                :Result:='mmCP_VGT_DSINVOC_COUNT_LO';
  mmCP_VGT_DSINVOC_COUNT_HI                                :Result:='mmCP_VGT_DSINVOC_COUNT_HI';
  mmCP_PA_CINVOC_COUNT_LO                                  :Result:='mmCP_PA_CINVOC_COUNT_LO';
  mmCP_PA_CINVOC_COUNT_HI                                  :Result:='mmCP_PA_CINVOC_COUNT_HI';
  mmCP_PA_CPRIM_COUNT_LO                                   :Result:='mmCP_PA_CPRIM_COUNT_LO';
  mmCP_PA_CPRIM_COUNT_HI                                   :Result:='mmCP_PA_CPRIM_COUNT_HI';
  mmCP_SC_PSINVOC_COUNT0_LO                                :Result:='mmCP_SC_PSINVOC_COUNT0_LO';
  mmCP_SC_PSINVOC_COUNT0_HI                                :Result:='mmCP_SC_PSINVOC_COUNT0_HI';
  mmCP_SC_PSINVOC_COUNT1_LO                                :Result:='mmCP_SC_PSINVOC_COUNT1_LO';
  mmCP_SC_PSINVOC_COUNT1_HI                                :Result:='mmCP_SC_PSINVOC_COUNT1_HI';
  mmCP_VGT_CSINVOC_COUNT_LO                                :Result:='mmCP_VGT_CSINVOC_COUNT_LO';
  mmCP_VGT_CSINVOC_COUNT_HI                                :Result:='mmCP_VGT_CSINVOC_COUNT_HI';
  mmCP_PIPE_STATS_CONTROL                                  :Result:='mmCP_PIPE_STATS_CONTROL';
  mmCP_STREAM_OUT_CONTROL                                  :Result:='mmCP_STREAM_OUT_CONTROL';
  mmCP_STRMOUT_CNTL                                        :Result:='mmCP_STRMOUT_CNTL';
  mmSCRATCH_REG0                                           :Result:='mmSCRATCH_REG0';
  mmSCRATCH_REG1                                           :Result:='mmSCRATCH_REG1';
  mmSCRATCH_REG2                                           :Result:='mmSCRATCH_REG2';
  mmSCRATCH_REG3                                           :Result:='mmSCRATCH_REG3';
  mmSCRATCH_REG4                                           :Result:='mmSCRATCH_REG4';
  mmSCRATCH_REG5                                           :Result:='mmSCRATCH_REG5';
  mmSCRATCH_REG6                                           :Result:='mmSCRATCH_REG6';
  mmSCRATCH_REG7                                           :Result:='mmSCRATCH_REG7';
  mmSCRATCH_UMSK                                           :Result:='mmSCRATCH_UMSK';
  mmSCRATCH_ADDR                                           :Result:='mmSCRATCH_ADDR';
  mmCP_PFP_ATOMIC_PREOP_LO                                 :Result:='mmCP_PFP_ATOMIC_PREOP_LO';
  mmCP_PFP_ATOMIC_PREOP_HI                                 :Result:='mmCP_PFP_ATOMIC_PREOP_HI';
  mmCP_PFP_GDS_ATOMIC0_PREOP_LO                            :Result:='mmCP_PFP_GDS_ATOMIC0_PREOP_LO';
  mmCP_PFP_GDS_ATOMIC0_PREOP_HI                            :Result:='mmCP_PFP_GDS_ATOMIC0_PREOP_HI';
  mmCP_PFP_GDS_ATOMIC1_PREOP_LO                            :Result:='mmCP_PFP_GDS_ATOMIC1_PREOP_LO';
  mmCP_PFP_GDS_ATOMIC1_PREOP_HI                            :Result:='mmCP_PFP_GDS_ATOMIC1_PREOP_HI';
  mmCP_APPEND_ADDR_LO                                      :Result:='mmCP_APPEND_ADDR_LO';
  mmCP_APPEND_ADDR_HI                                      :Result:='mmCP_APPEND_ADDR_HI';
  mmCP_APPEND_DATA                                         :Result:='mmCP_APPEND_DATA';
  mmCP_APPEND_LAST_CS_FENCE                                :Result:='mmCP_APPEND_LAST_CS_FENCE';
  mmCP_APPEND_LAST_PS_FENCE                                :Result:='mmCP_APPEND_LAST_PS_FENCE';
  mmCP_ATOMIC_PREOP_LO                                     :Result:='mmCP_ATOMIC_PREOP_LO';
  mmCP_ATOMIC_PREOP_HI                                     :Result:='mmCP_ATOMIC_PREOP_HI';
  mmCP_GDS_ATOMIC0_PREOP_LO                                :Result:='mmCP_GDS_ATOMIC0_PREOP_LO';
  mmCP_GDS_ATOMIC0_PREOP_HI                                :Result:='mmCP_GDS_ATOMIC0_PREOP_HI';
  mmCP_GDS_ATOMIC1_PREOP_LO                                :Result:='mmCP_GDS_ATOMIC1_PREOP_LO';
  mmCP_GDS_ATOMIC1_PREOP_HI                                :Result:='mmCP_GDS_ATOMIC1_PREOP_HI';
  mmCP_ME_MC_WADDR_LO                                      :Result:='mmCP_ME_MC_WADDR_LO';
  mmCP_ME_MC_WADDR_HI                                      :Result:='mmCP_ME_MC_WADDR_HI';
  mmCP_ME_MC_WDATA_LO                                      :Result:='mmCP_ME_MC_WDATA_LO';
  mmCP_ME_MC_WDATA_HI                                      :Result:='mmCP_ME_MC_WDATA_HI';
  mmCP_ME_MC_RADDR_LO                                      :Result:='mmCP_ME_MC_RADDR_LO';
  mmCP_ME_MC_RADDR_HI                                      :Result:='mmCP_ME_MC_RADDR_HI';
  mmCP_SEM_WAIT_TIMER                                      :Result:='mmCP_SEM_WAIT_TIMER';
  mmCP_SIG_SEM_ADDR_LO                                     :Result:='mmCP_SIG_SEM_ADDR_LO';
  mmCP_SIG_SEM_ADDR_HI                                     :Result:='mmCP_SIG_SEM_ADDR_HI';
  mmCP_WAIT_REG_MEM_TIMEOUT                                :Result:='mmCP_WAIT_REG_MEM_TIMEOUT';
  mmCP_WAIT_SEM_ADDR_LO                                    :Result:='mmCP_WAIT_SEM_ADDR_LO';
  mmCP_WAIT_SEM_ADDR_HI                                    :Result:='mmCP_WAIT_SEM_ADDR_HI';
  mmCP_DMA_PFP_CONTROL                                     :Result:='mmCP_DMA_PFP_CONTROL';
  mmCP_DMA_ME_CONTROL                                      :Result:='mmCP_DMA_ME_CONTROL';
  mmCP_COHER_BASE_HI                                       :Result:='mmCP_COHER_BASE_HI';
  mmCP_COHER_START_DELAY                                   :Result:='mmCP_COHER_START_DELAY';
  mmCP_COHER_CNTL                                          :Result:='mmCP_COHER_CNTL';
  mmCP_COHER_SIZE                                          :Result:='mmCP_COHER_SIZE';
  mmCP_COHER_BASE                                          :Result:='mmCP_COHER_BASE';
  mmCP_COHER_STATUS                                        :Result:='mmCP_COHER_STATUS';
  mmCP_DMA_ME_SRC_ADDR                                     :Result:='mmCP_DMA_ME_SRC_ADDR';
  mmCP_DMA_ME_SRC_ADDR_HI                                  :Result:='mmCP_DMA_ME_SRC_ADDR_HI';
  mmCP_DMA_ME_DST_ADDR                                     :Result:='mmCP_DMA_ME_DST_ADDR';
  mmCP_DMA_ME_DST_ADDR_HI                                  :Result:='mmCP_DMA_ME_DST_ADDR_HI';
  mmCP_DMA_ME_COMMAND                                      :Result:='mmCP_DMA_ME_COMMAND';
  mmCP_DMA_PFP_SRC_ADDR                                    :Result:='mmCP_DMA_PFP_SRC_ADDR';
  mmCP_DMA_PFP_SRC_ADDR_HI                                 :Result:='mmCP_DMA_PFP_SRC_ADDR_HI';
  mmCP_DMA_PFP_DST_ADDR                                    :Result:='mmCP_DMA_PFP_DST_ADDR';
  mmCP_DMA_PFP_DST_ADDR_HI                                 :Result:='mmCP_DMA_PFP_DST_ADDR_HI';
  mmCP_DMA_PFP_COMMAND                                     :Result:='mmCP_DMA_PFP_COMMAND';
  mmCP_DMA_CNTL                                            :Result:='mmCP_DMA_CNTL';
  mmCP_DMA_READ_TAGS                                       :Result:='mmCP_DMA_READ_TAGS';
  mmCP_COHER_SIZE_HI                                       :Result:='mmCP_COHER_SIZE_HI';
  mmCP_PFP_IB_CONTROL                                      :Result:='mmCP_PFP_IB_CONTROL';
  mmCP_PFP_LOAD_CONTROL                                    :Result:='mmCP_PFP_LOAD_CONTROL';
  mmCP_SCRATCH_INDEX                                       :Result:='mmCP_SCRATCH_INDEX';
  mmCP_SCRATCH_DATA                                        :Result:='mmCP_SCRATCH_DATA';
  mmCP_RB_OFFSET                                           :Result:='mmCP_RB_OFFSET';
  mmCP_IB1_OFFSET                                          :Result:='mmCP_IB1_OFFSET';
  mmCP_IB2_OFFSET                                          :Result:='mmCP_IB2_OFFSET';
  mmCP_IB1_PREAMBLE_BEGIN                                  :Result:='mmCP_IB1_PREAMBLE_BEGIN';
  mmCP_IB1_PREAMBLE_END                                    :Result:='mmCP_IB1_PREAMBLE_END';
  mmCP_IB2_PREAMBLE_BEGIN                                  :Result:='mmCP_IB2_PREAMBLE_BEGIN';
  mmCP_IB2_PREAMBLE_END                                    :Result:='mmCP_IB2_PREAMBLE_END';
  mmCP_CE_IB1_OFFSET                                       :Result:='mmCP_CE_IB1_OFFSET';
  mmCP_CE_IB2_OFFSET                                       :Result:='mmCP_CE_IB2_OFFSET';
  mmCP_CE_COUNTER                                          :Result:='mmCP_CE_COUNTER';
  mmCP_CE_RB_OFFSET                                        :Result:='mmCP_CE_RB_OFFSET';
  mmCP_CE_INIT_BASE_LO                                     :Result:='mmCP_CE_INIT_BASE_LO';
  mmCP_CE_INIT_BASE_HI                                     :Result:='mmCP_CE_INIT_BASE_HI';
  mmCP_CE_INIT_BUFSZ                                       :Result:='mmCP_CE_INIT_BUFSZ';
  mmCP_CE_IB1_BASE_LO                                      :Result:='mmCP_CE_IB1_BASE_LO';
  mmCP_CE_IB1_BASE_HI                                      :Result:='mmCP_CE_IB1_BASE_HI';
  mmCP_CE_IB1_BUFSZ                                        :Result:='mmCP_CE_IB1_BUFSZ';
  mmCP_CE_IB2_BASE_LO                                      :Result:='mmCP_CE_IB2_BASE_LO';
  mmCP_CE_IB2_BASE_HI                                      :Result:='mmCP_CE_IB2_BASE_HI';
  mmCP_CE_IB2_BUFSZ                                        :Result:='mmCP_CE_IB2_BUFSZ';
  mmCP_IB1_BASE_LO                                         :Result:='mmCP_IB1_BASE_LO';
  mmCP_IB1_BASE_HI                                         :Result:='mmCP_IB1_BASE_HI';
  mmCP_IB1_BUFSZ                                           :Result:='mmCP_IB1_BUFSZ';
  mmCP_IB2_BASE_LO                                         :Result:='mmCP_IB2_BASE_LO';
  mmCP_IB2_BASE_HI                                         :Result:='mmCP_IB2_BASE_HI';
  mmCP_IB2_BUFSZ                                           :Result:='mmCP_IB2_BUFSZ';
  mmCP_ST_BASE_LO                                          :Result:='mmCP_ST_BASE_LO';
  mmCP_ST_BASE_HI                                          :Result:='mmCP_ST_BASE_HI';
  mmCP_ST_BUFSZ                                            :Result:='mmCP_ST_BUFSZ';
  mmCP_EOP_DONE_EVENT_CNTL                                 :Result:='mmCP_EOP_DONE_EVENT_CNTL';
  mmCP_EOP_DONE_DATA_CNTL                                  :Result:='mmCP_EOP_DONE_DATA_CNTL';
  mmCP_EOP_DONE_CNTX_ID                                    :Result:='mmCP_EOP_DONE_CNTX_ID';
  mmCP_PFP_COMPLETION_STATUS                               :Result:='mmCP_PFP_COMPLETION_STATUS';
  mmCP_CE_COMPLETION_STATUS                                :Result:='mmCP_CE_COMPLETION_STATUS';
  mmCP_PRED_NOT_VISIBLE                                    :Result:='mmCP_PRED_NOT_VISIBLE';
  mmCP_PFP_METADATA_BASE_ADDR                              :Result:='mmCP_PFP_METADATA_BASE_ADDR';
  mmCP_PFP_METADATA_BASE_ADDR_HI                           :Result:='mmCP_PFP_METADATA_BASE_ADDR_HI';
  mmCP_CE_METADATA_BASE_ADDR                               :Result:='mmCP_CE_METADATA_BASE_ADDR';
  mmCP_CE_METADATA_BASE_ADDR_HI                            :Result:='mmCP_CE_METADATA_BASE_ADDR_HI';
  mmCP_DRAW_INDX_INDR_ADDR                                 :Result:='mmCP_DRAW_INDX_INDR_ADDR';
  mmCP_DRAW_INDX_INDR_ADDR_HI                              :Result:='mmCP_DRAW_INDX_INDR_ADDR_HI';
  mmCP_DISPATCH_INDR_ADDR                                  :Result:='mmCP_DISPATCH_INDR_ADDR';
  mmCP_DISPATCH_INDR_ADDR_HI                               :Result:='mmCP_DISPATCH_INDR_ADDR_HI';
  mmCP_INDEX_BASE_ADDR                                     :Result:='mmCP_INDEX_BASE_ADDR';
  mmCP_INDEX_BASE_ADDR_HI                                  :Result:='mmCP_INDEX_BASE_ADDR_HI';
  mmCP_INDEX_TYPE                                          :Result:='mmCP_INDEX_TYPE';
  mmCP_GDS_BKUP_ADDR                                       :Result:='mmCP_GDS_BKUP_ADDR';
  mmCP_GDS_BKUP_ADDR_HI                                    :Result:='mmCP_GDS_BKUP_ADDR_HI';
  mmCP_SAMPLE_STATUS                                       :Result:='mmCP_SAMPLE_STATUS';
  mmGRBM_GFX_INDEX                                         :Result:='mmGRBM_GFX_INDEX';
  mmVGT_ESGS_RING_SIZE                                     :Result:='mmVGT_ESGS_RING_SIZE';
  mmVGT_GSVS_RING_SIZE                                     :Result:='mmVGT_GSVS_RING_SIZE';
  mmVGT_PRIMITIVE_TYPE                                     :Result:='mmVGT_PRIMITIVE_TYPE';
  mmVGT_INDEX_TYPE                                         :Result:='mmVGT_INDEX_TYPE';
  mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0                       :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0';
  mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1                       :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1';
  mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2                       :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2';
  mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3                       :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3';
  mmVGT_NUM_INDICES                                        :Result:='mmVGT_NUM_INDICES';
  mmVGT_NUM_INSTANCES                                      :Result:='mmVGT_NUM_INSTANCES';
  mmVGT_TF_RING_SIZE                                       :Result:='mmVGT_TF_RING_SIZE';
  mmVGT_HS_OFFCHIP_PARAM                                   :Result:='mmVGT_HS_OFFCHIP_PARAM';
  mmVGT_TF_MEMORY_BASE                                     :Result:='mmVGT_TF_MEMORY_BASE';
  mmPA_SU_LINE_STIPPLE_VALUE                               :Result:='mmPA_SU_LINE_STIPPLE_VALUE';
  mmPA_SC_LINE_STIPPLE_STATE                               :Result:='mmPA_SC_LINE_STIPPLE_STATE';
  mmPA_SC_P3D_TRAP_SCREEN_HV_EN                            :Result:='mmPA_SC_P3D_TRAP_SCREEN_HV_EN';
  mmPA_SC_P3D_TRAP_SCREEN_H                                :Result:='mmPA_SC_P3D_TRAP_SCREEN_H';
  mmPA_SC_P3D_TRAP_SCREEN_V                                :Result:='mmPA_SC_P3D_TRAP_SCREEN_V';
  mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE                       :Result:='mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE';
  mmPA_SC_P3D_TRAP_SCREEN_COUNT                            :Result:='mmPA_SC_P3D_TRAP_SCREEN_COUNT';
  mmPA_SC_HP3D_TRAP_SCREEN_HV_EN                           :Result:='mmPA_SC_HP3D_TRAP_SCREEN_HV_EN';
  mmPA_SC_HP3D_TRAP_SCREEN_H                               :Result:='mmPA_SC_HP3D_TRAP_SCREEN_H';
  mmPA_SC_HP3D_TRAP_SCREEN_V                               :Result:='mmPA_SC_HP3D_TRAP_SCREEN_V';
  mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE                      :Result:='mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE';
  mmPA_SC_HP3D_TRAP_SCREEN_COUNT                           :Result:='mmPA_SC_HP3D_TRAP_SCREEN_COUNT';
  mmPA_SC_TRAP_SCREEN_HV_EN                                :Result:='mmPA_SC_TRAP_SCREEN_HV_EN';
  mmPA_SC_TRAP_SCREEN_H                                    :Result:='mmPA_SC_TRAP_SCREEN_H';
  mmPA_SC_TRAP_SCREEN_V                                    :Result:='mmPA_SC_TRAP_SCREEN_V';
  mmPA_SC_TRAP_SCREEN_OCCURRENCE                           :Result:='mmPA_SC_TRAP_SCREEN_OCCURRENCE';
  mmPA_SC_TRAP_SCREEN_COUNT                                :Result:='mmPA_SC_TRAP_SCREEN_COUNT';
  mmSQ_THREAD_TRACE_BASE                                   :Result:='mmSQ_THREAD_TRACE_BASE';
  mmSQ_THREAD_TRACE_SIZE                                   :Result:='mmSQ_THREAD_TRACE_SIZE';
  mmSQ_THREAD_TRACE_MASK                                   :Result:='mmSQ_THREAD_TRACE_MASK';
  mmSQ_THREAD_TRACE_TOKEN_MASK                             :Result:='mmSQ_THREAD_TRACE_TOKEN_MASK';
  mmSQ_THREAD_TRACE_PERF_MASK                              :Result:='mmSQ_THREAD_TRACE_PERF_MASK';
  mmSQ_THREAD_TRACE_CTRL                                   :Result:='mmSQ_THREAD_TRACE_CTRL';
  mmSQ_THREAD_TRACE_MODE                                   :Result:='mmSQ_THREAD_TRACE_MODE';
  mmSQ_THREAD_TRACE_BASE2                                  :Result:='mmSQ_THREAD_TRACE_BASE2';
  mmSQ_THREAD_TRACE_TOKEN_MASK2                            :Result:='mmSQ_THREAD_TRACE_TOKEN_MASK2';
  mmSQ_THREAD_TRACE_WPTR                                   :Result:='mmSQ_THREAD_TRACE_WPTR';
  mmSQ_THREAD_TRACE_STATUS                                 :Result:='mmSQ_THREAD_TRACE_STATUS';
  mmSQ_THREAD_TRACE_HIWATER                                :Result:='mmSQ_THREAD_TRACE_HIWATER';
  mmSQ_THREAD_TRACE_USERDATA_0                             :Result:='mmSQ_THREAD_TRACE_USERDATA_0';
  mmSQ_THREAD_TRACE_USERDATA_1                             :Result:='mmSQ_THREAD_TRACE_USERDATA_1';
  mmSQ_THREAD_TRACE_USERDATA_2                             :Result:='mmSQ_THREAD_TRACE_USERDATA_2';
  mmSQ_THREAD_TRACE_USERDATA_3                             :Result:='mmSQ_THREAD_TRACE_USERDATA_3';
  mmSQC_CACHES                                             :Result:='mmSQC_CACHES';
  mmSQC_WRITEBACK                                          :Result:='mmSQC_WRITEBACK';
  mmTA_CS_BC_BASE_ADDR                                     :Result:='mmTA_CS_BC_BASE_ADDR';
  mmTA_CS_BC_BASE_ADDR_HI                                  :Result:='mmTA_CS_BC_BASE_ADDR_HI';
  mmDB_OCCLUSION_COUNT0_LOW                                :Result:='mmDB_OCCLUSION_COUNT0_LOW';
  mmDB_OCCLUSION_COUNT0_HI                                 :Result:='mmDB_OCCLUSION_COUNT0_HI';
  mmDB_OCCLUSION_COUNT1_LOW                                :Result:='mmDB_OCCLUSION_COUNT1_LOW';
  mmDB_OCCLUSION_COUNT1_HI                                 :Result:='mmDB_OCCLUSION_COUNT1_HI';
  mmDB_OCCLUSION_COUNT2_LOW                                :Result:='mmDB_OCCLUSION_COUNT2_LOW';
  mmDB_OCCLUSION_COUNT2_HI                                 :Result:='mmDB_OCCLUSION_COUNT2_HI';
  mmDB_OCCLUSION_COUNT3_LOW                                :Result:='mmDB_OCCLUSION_COUNT3_LOW';
  mmDB_OCCLUSION_COUNT3_HI                                 :Result:='mmDB_OCCLUSION_COUNT3_HI';
  mmDB_ZPASS_COUNT_LOW                                     :Result:='mmDB_ZPASS_COUNT_LOW';
  mmDB_ZPASS_COUNT_HI                                      :Result:='mmDB_ZPASS_COUNT_HI';
  mmGDS_RD_ADDR                                            :Result:='mmGDS_RD_ADDR';
  mmGDS_RD_DATA                                            :Result:='mmGDS_RD_DATA';
  mmGDS_RD_BURST_ADDR                                      :Result:='mmGDS_RD_BURST_ADDR';
  mmGDS_RD_BURST_COUNT                                     :Result:='mmGDS_RD_BURST_COUNT';
  mmGDS_RD_BURST_DATA                                      :Result:='mmGDS_RD_BURST_DATA';
  mmGDS_WR_ADDR                                            :Result:='mmGDS_WR_ADDR';
  mmGDS_WR_DATA                                            :Result:='mmGDS_WR_DATA';
  mmGDS_WR_BURST_ADDR                                      :Result:='mmGDS_WR_BURST_ADDR';
  mmGDS_WR_BURST_DATA                                      :Result:='mmGDS_WR_BURST_DATA';
  mmGDS_WRITE_COMPLETE                                     :Result:='mmGDS_WRITE_COMPLETE';
  mmGDS_ATOM_CNTL                                          :Result:='mmGDS_ATOM_CNTL';
  mmGDS_ATOM_COMPLETE                                      :Result:='mmGDS_ATOM_COMPLETE';
  mmGDS_ATOM_BASE                                          :Result:='mmGDS_ATOM_BASE';
  mmGDS_ATOM_SIZE                                          :Result:='mmGDS_ATOM_SIZE';
  mmGDS_ATOM_OFFSET0                                       :Result:='mmGDS_ATOM_OFFSET0';
  mmGDS_ATOM_OFFSET1                                       :Result:='mmGDS_ATOM_OFFSET1';
  mmGDS_ATOM_DST                                           :Result:='mmGDS_ATOM_DST';
  mmGDS_ATOM_OP                                            :Result:='mmGDS_ATOM_OP';
  mmGDS_ATOM_SRC0                                          :Result:='mmGDS_ATOM_SRC0';
  mmGDS_ATOM_SRC0_U                                        :Result:='mmGDS_ATOM_SRC0_U';
  mmGDS_ATOM_SRC1                                          :Result:='mmGDS_ATOM_SRC1';
  mmGDS_ATOM_SRC1_U                                        :Result:='mmGDS_ATOM_SRC1_U';
  mmGDS_ATOM_READ0                                         :Result:='mmGDS_ATOM_READ0';
  mmGDS_ATOM_READ0_U                                       :Result:='mmGDS_ATOM_READ0_U';
  mmGDS_ATOM_READ1                                         :Result:='mmGDS_ATOM_READ1';
  mmGDS_ATOM_READ1_U                                       :Result:='mmGDS_ATOM_READ1_U';
  mmGDS_GWS_RESOURCE_CNTL                                  :Result:='mmGDS_GWS_RESOURCE_CNTL';
  mmGDS_GWS_RESOURCE                                       :Result:='mmGDS_GWS_RESOURCE';
  mmGDS_GWS_RESOURCE_CNT                                   :Result:='mmGDS_GWS_RESOURCE_CNT';
  mmGDS_OA_CNTL                                            :Result:='mmGDS_OA_CNTL';
  mmGDS_OA_COUNTER                                         :Result:='mmGDS_OA_COUNTER';
  mmGDS_OA_ADDRESS                                         :Result:='mmGDS_OA_ADDRESS';
  mmGDS_OA_INCDEC                                          :Result:='mmGDS_OA_INCDEC';
  mmGDS_OA_RING_SIZE                                       :Result:='mmGDS_OA_RING_SIZE';
  mmCPG_PERFCOUNTER1_LO                                    :Result:='mmCPG_PERFCOUNTER1_LO';
  mmCPG_PERFCOUNTER1_HI                                    :Result:='mmCPG_PERFCOUNTER1_HI';
  mmCPG_PERFCOUNTER0_LO                                    :Result:='mmCPG_PERFCOUNTER0_LO';
  mmCPG_PERFCOUNTER0_HI                                    :Result:='mmCPG_PERFCOUNTER0_HI';
  mmCPC_PERFCOUNTER1_LO                                    :Result:='mmCPC_PERFCOUNTER1_LO';
  mmCPC_PERFCOUNTER1_HI                                    :Result:='mmCPC_PERFCOUNTER1_HI';
  mmCPC_PERFCOUNTER0_LO                                    :Result:='mmCPC_PERFCOUNTER0_LO';
  mmCPC_PERFCOUNTER0_HI                                    :Result:='mmCPC_PERFCOUNTER0_HI';
  mmCPF_PERFCOUNTER1_LO                                    :Result:='mmCPF_PERFCOUNTER1_LO';
  mmCPF_PERFCOUNTER1_HI                                    :Result:='mmCPF_PERFCOUNTER1_HI';
  mmCPF_PERFCOUNTER0_LO                                    :Result:='mmCPF_PERFCOUNTER0_LO';
  mmCPF_PERFCOUNTER0_HI                                    :Result:='mmCPF_PERFCOUNTER0_HI';
  mmGRBM_PERFCOUNTER0_LO                                   :Result:='mmGRBM_PERFCOUNTER0_LO';
  mmGRBM_PERFCOUNTER0_HI                                   :Result:='mmGRBM_PERFCOUNTER0_HI';
  mmGRBM_PERFCOUNTER1_LO                                   :Result:='mmGRBM_PERFCOUNTER1_LO';
  mmGRBM_PERFCOUNTER1_HI                                   :Result:='mmGRBM_PERFCOUNTER1_HI';
  mmGRBM_SE0_PERFCOUNTER_LO                                :Result:='mmGRBM_SE0_PERFCOUNTER_LO';
  mmGRBM_SE0_PERFCOUNTER_HI                                :Result:='mmGRBM_SE0_PERFCOUNTER_HI';
  mmGRBM_SE1_PERFCOUNTER_LO                                :Result:='mmGRBM_SE1_PERFCOUNTER_LO';
  mmGRBM_SE1_PERFCOUNTER_HI                                :Result:='mmGRBM_SE1_PERFCOUNTER_HI';
  mmGRBM_SE2_PERFCOUNTER_LO                                :Result:='mmGRBM_SE2_PERFCOUNTER_LO';
  mmGRBM_SE2_PERFCOUNTER_HI                                :Result:='mmGRBM_SE2_PERFCOUNTER_HI';
  mmGRBM_SE3_PERFCOUNTER_LO                                :Result:='mmGRBM_SE3_PERFCOUNTER_LO';
  mmGRBM_SE3_PERFCOUNTER_HI                                :Result:='mmGRBM_SE3_PERFCOUNTER_HI';
  mmWD_PERFCOUNTER0_LO                                     :Result:='mmWD_PERFCOUNTER0_LO';
  mmWD_PERFCOUNTER0_HI                                     :Result:='mmWD_PERFCOUNTER0_HI';
  mmWD_PERFCOUNTER1_LO                                     :Result:='mmWD_PERFCOUNTER1_LO';
  mmWD_PERFCOUNTER1_HI                                     :Result:='mmWD_PERFCOUNTER1_HI';
  mmWD_PERFCOUNTER2_LO                                     :Result:='mmWD_PERFCOUNTER2_LO';
  mmWD_PERFCOUNTER2_HI                                     :Result:='mmWD_PERFCOUNTER2_HI';
  mmWD_PERFCOUNTER3_LO                                     :Result:='mmWD_PERFCOUNTER3_LO';
  mmWD_PERFCOUNTER3_HI                                     :Result:='mmWD_PERFCOUNTER3_HI';
  mmIA_PERFCOUNTER0_LO                                     :Result:='mmIA_PERFCOUNTER0_LO';
  mmIA_PERFCOUNTER0_HI                                     :Result:='mmIA_PERFCOUNTER0_HI';
  mmIA_PERFCOUNTER1_LO                                     :Result:='mmIA_PERFCOUNTER1_LO';
  mmIA_PERFCOUNTER1_HI                                     :Result:='mmIA_PERFCOUNTER1_HI';
  mmIA_PERFCOUNTER2_LO                                     :Result:='mmIA_PERFCOUNTER2_LO';
  mmIA_PERFCOUNTER2_HI                                     :Result:='mmIA_PERFCOUNTER2_HI';
  mmIA_PERFCOUNTER3_LO                                     :Result:='mmIA_PERFCOUNTER3_LO';
  mmIA_PERFCOUNTER3_HI                                     :Result:='mmIA_PERFCOUNTER3_HI';
  mmVGT_PERFCOUNTER0_LO                                    :Result:='mmVGT_PERFCOUNTER0_LO';
  mmVGT_PERFCOUNTER0_HI                                    :Result:='mmVGT_PERFCOUNTER0_HI';
  mmVGT_PERFCOUNTER1_LO                                    :Result:='mmVGT_PERFCOUNTER1_LO';
  mmVGT_PERFCOUNTER1_HI                                    :Result:='mmVGT_PERFCOUNTER1_HI';
  mmVGT_PERFCOUNTER2_LO                                    :Result:='mmVGT_PERFCOUNTER2_LO';
  mmVGT_PERFCOUNTER2_HI                                    :Result:='mmVGT_PERFCOUNTER2_HI';
  mmVGT_PERFCOUNTER3_LO                                    :Result:='mmVGT_PERFCOUNTER3_LO';
  mmVGT_PERFCOUNTER3_HI                                    :Result:='mmVGT_PERFCOUNTER3_HI';
  mmPA_SU_PERFCOUNTER0_LO                                  :Result:='mmPA_SU_PERFCOUNTER0_LO';
  mmPA_SU_PERFCOUNTER0_HI                                  :Result:='mmPA_SU_PERFCOUNTER0_HI';
  mmPA_SU_PERFCOUNTER1_LO                                  :Result:='mmPA_SU_PERFCOUNTER1_LO';
  mmPA_SU_PERFCOUNTER1_HI                                  :Result:='mmPA_SU_PERFCOUNTER1_HI';
  mmPA_SU_PERFCOUNTER2_LO                                  :Result:='mmPA_SU_PERFCOUNTER2_LO';
  mmPA_SU_PERFCOUNTER2_HI                                  :Result:='mmPA_SU_PERFCOUNTER2_HI';
  mmPA_SU_PERFCOUNTER3_LO                                  :Result:='mmPA_SU_PERFCOUNTER3_LO';
  mmPA_SU_PERFCOUNTER3_HI                                  :Result:='mmPA_SU_PERFCOUNTER3_HI';
  mmPA_SC_PERFCOUNTER0_LO                                  :Result:='mmPA_SC_PERFCOUNTER0_LO';
  mmPA_SC_PERFCOUNTER0_HI                                  :Result:='mmPA_SC_PERFCOUNTER0_HI';
  mmPA_SC_PERFCOUNTER1_LO                                  :Result:='mmPA_SC_PERFCOUNTER1_LO';
  mmPA_SC_PERFCOUNTER1_HI                                  :Result:='mmPA_SC_PERFCOUNTER1_HI';
  mmPA_SC_PERFCOUNTER2_LO                                  :Result:='mmPA_SC_PERFCOUNTER2_LO';
  mmPA_SC_PERFCOUNTER2_HI                                  :Result:='mmPA_SC_PERFCOUNTER2_HI';
  mmPA_SC_PERFCOUNTER3_LO                                  :Result:='mmPA_SC_PERFCOUNTER3_LO';
  mmPA_SC_PERFCOUNTER3_HI                                  :Result:='mmPA_SC_PERFCOUNTER3_HI';
  mmPA_SC_PERFCOUNTER4_LO                                  :Result:='mmPA_SC_PERFCOUNTER4_LO';
  mmPA_SC_PERFCOUNTER4_HI                                  :Result:='mmPA_SC_PERFCOUNTER4_HI';
  mmPA_SC_PERFCOUNTER5_LO                                  :Result:='mmPA_SC_PERFCOUNTER5_LO';
  mmPA_SC_PERFCOUNTER5_HI                                  :Result:='mmPA_SC_PERFCOUNTER5_HI';
  mmPA_SC_PERFCOUNTER6_LO                                  :Result:='mmPA_SC_PERFCOUNTER6_LO';
  mmPA_SC_PERFCOUNTER6_HI                                  :Result:='mmPA_SC_PERFCOUNTER6_HI';
  mmPA_SC_PERFCOUNTER7_LO                                  :Result:='mmPA_SC_PERFCOUNTER7_LO';
  mmPA_SC_PERFCOUNTER7_HI                                  :Result:='mmPA_SC_PERFCOUNTER7_HI';
  mmSPI_PERFCOUNTER0_HI                                    :Result:='mmSPI_PERFCOUNTER0_HI';
  mmSPI_PERFCOUNTER0_LO                                    :Result:='mmSPI_PERFCOUNTER0_LO';
  mmSPI_PERFCOUNTER1_HI                                    :Result:='mmSPI_PERFCOUNTER1_HI';
  mmSPI_PERFCOUNTER1_LO                                    :Result:='mmSPI_PERFCOUNTER1_LO';
  mmSPI_PERFCOUNTER2_HI                                    :Result:='mmSPI_PERFCOUNTER2_HI';
  mmSPI_PERFCOUNTER2_LO                                    :Result:='mmSPI_PERFCOUNTER2_LO';
  mmSPI_PERFCOUNTER3_HI                                    :Result:='mmSPI_PERFCOUNTER3_HI';
  mmSPI_PERFCOUNTER3_LO                                    :Result:='mmSPI_PERFCOUNTER3_LO';
  mmSPI_PERFCOUNTER4_HI                                    :Result:='mmSPI_PERFCOUNTER4_HI';
  mmSPI_PERFCOUNTER4_LO                                    :Result:='mmSPI_PERFCOUNTER4_LO';
  mmSPI_PERFCOUNTER5_HI                                    :Result:='mmSPI_PERFCOUNTER5_HI';
  mmSPI_PERFCOUNTER5_LO                                    :Result:='mmSPI_PERFCOUNTER5_LO';
  mmSQ_PERFCOUNTER0_LO                                     :Result:='mmSQ_PERFCOUNTER0_LO';
  mmSQ_PERFCOUNTER0_HI                                     :Result:='mmSQ_PERFCOUNTER0_HI';
  mmSQ_PERFCOUNTER1_LO                                     :Result:='mmSQ_PERFCOUNTER1_LO';
  mmSQ_PERFCOUNTER1_HI                                     :Result:='mmSQ_PERFCOUNTER1_HI';
  mmSQ_PERFCOUNTER2_LO                                     :Result:='mmSQ_PERFCOUNTER2_LO';
  mmSQ_PERFCOUNTER2_HI                                     :Result:='mmSQ_PERFCOUNTER2_HI';
  mmSQ_PERFCOUNTER3_LO                                     :Result:='mmSQ_PERFCOUNTER3_LO';
  mmSQ_PERFCOUNTER3_HI                                     :Result:='mmSQ_PERFCOUNTER3_HI';
  mmSQ_PERFCOUNTER4_LO                                     :Result:='mmSQ_PERFCOUNTER4_LO';
  mmSQ_PERFCOUNTER4_HI                                     :Result:='mmSQ_PERFCOUNTER4_HI';
  mmSQ_PERFCOUNTER5_LO                                     :Result:='mmSQ_PERFCOUNTER5_LO';
  mmSQ_PERFCOUNTER5_HI                                     :Result:='mmSQ_PERFCOUNTER5_HI';
  mmSQ_PERFCOUNTER6_LO                                     :Result:='mmSQ_PERFCOUNTER6_LO';
  mmSQ_PERFCOUNTER6_HI                                     :Result:='mmSQ_PERFCOUNTER6_HI';
  mmSQ_PERFCOUNTER7_LO                                     :Result:='mmSQ_PERFCOUNTER7_LO';
  mmSQ_PERFCOUNTER7_HI                                     :Result:='mmSQ_PERFCOUNTER7_HI';
  mmSQ_PERFCOUNTER8_LO                                     :Result:='mmSQ_PERFCOUNTER8_LO';
  mmSQ_PERFCOUNTER8_HI                                     :Result:='mmSQ_PERFCOUNTER8_HI';
  mmSQ_PERFCOUNTER9_LO                                     :Result:='mmSQ_PERFCOUNTER9_LO';
  mmSQ_PERFCOUNTER9_HI                                     :Result:='mmSQ_PERFCOUNTER9_HI';
  mmSQ_PERFCOUNTER10_LO                                    :Result:='mmSQ_PERFCOUNTER10_LO';
  mmSQ_PERFCOUNTER10_HI                                    :Result:='mmSQ_PERFCOUNTER10_HI';
  mmSQ_PERFCOUNTER11_LO                                    :Result:='mmSQ_PERFCOUNTER11_LO';
  mmSQ_PERFCOUNTER11_HI                                    :Result:='mmSQ_PERFCOUNTER11_HI';
  mmSQ_PERFCOUNTER12_LO                                    :Result:='mmSQ_PERFCOUNTER12_LO';
  mmSQ_PERFCOUNTER12_HI                                    :Result:='mmSQ_PERFCOUNTER12_HI';
  mmSQ_PERFCOUNTER13_LO                                    :Result:='mmSQ_PERFCOUNTER13_LO';
  mmSQ_PERFCOUNTER13_HI                                    :Result:='mmSQ_PERFCOUNTER13_HI';
  mmSQ_PERFCOUNTER14_LO                                    :Result:='mmSQ_PERFCOUNTER14_LO';
  mmSQ_PERFCOUNTER14_HI                                    :Result:='mmSQ_PERFCOUNTER14_HI';
  mmSQ_PERFCOUNTER15_LO                                    :Result:='mmSQ_PERFCOUNTER15_LO';
  mmSQ_PERFCOUNTER15_HI                                    :Result:='mmSQ_PERFCOUNTER15_HI';
  mmSX_PERFCOUNTER0_LO                                     :Result:='mmSX_PERFCOUNTER0_LO';
  mmSX_PERFCOUNTER0_HI                                     :Result:='mmSX_PERFCOUNTER0_HI';
  mmSX_PERFCOUNTER1_LO                                     :Result:='mmSX_PERFCOUNTER1_LO';
  mmSX_PERFCOUNTER1_HI                                     :Result:='mmSX_PERFCOUNTER1_HI';
  mmSX_PERFCOUNTER2_LO                                     :Result:='mmSX_PERFCOUNTER2_LO';
  mmSX_PERFCOUNTER2_HI                                     :Result:='mmSX_PERFCOUNTER2_HI';
  mmSX_PERFCOUNTER3_LO                                     :Result:='mmSX_PERFCOUNTER3_LO';
  mmSX_PERFCOUNTER3_HI                                     :Result:='mmSX_PERFCOUNTER3_HI';
  mmGDS_PERFCOUNTER0_LO                                    :Result:='mmGDS_PERFCOUNTER0_LO';
  mmGDS_PERFCOUNTER0_HI                                    :Result:='mmGDS_PERFCOUNTER0_HI';
  mmGDS_PERFCOUNTER1_LO                                    :Result:='mmGDS_PERFCOUNTER1_LO';
  mmGDS_PERFCOUNTER1_HI                                    :Result:='mmGDS_PERFCOUNTER1_HI';
  mmGDS_PERFCOUNTER2_LO                                    :Result:='mmGDS_PERFCOUNTER2_LO';
  mmGDS_PERFCOUNTER2_HI                                    :Result:='mmGDS_PERFCOUNTER2_HI';
  mmGDS_PERFCOUNTER3_LO                                    :Result:='mmGDS_PERFCOUNTER3_LO';
  mmGDS_PERFCOUNTER3_HI                                    :Result:='mmGDS_PERFCOUNTER3_HI';
  mmTA_PERFCOUNTER0_LO                                     :Result:='mmTA_PERFCOUNTER0_LO';
  mmTA_PERFCOUNTER0_HI                                     :Result:='mmTA_PERFCOUNTER0_HI';
  mmTA_PERFCOUNTER1_LO                                     :Result:='mmTA_PERFCOUNTER1_LO';
  mmTA_PERFCOUNTER1_HI                                     :Result:='mmTA_PERFCOUNTER1_HI';
  mmTD_PERFCOUNTER0_LO                                     :Result:='mmTD_PERFCOUNTER0_LO';
  mmTD_PERFCOUNTER0_HI                                     :Result:='mmTD_PERFCOUNTER0_HI';
  mmTD_PERFCOUNTER1_LO                                     :Result:='mmTD_PERFCOUNTER1_LO';
  mmTD_PERFCOUNTER1_HI                                     :Result:='mmTD_PERFCOUNTER1_HI';
  mmTCP_PERFCOUNTER0_LO                                    :Result:='mmTCP_PERFCOUNTER0_LO';
  mmTCP_PERFCOUNTER0_HI                                    :Result:='mmTCP_PERFCOUNTER0_HI';
  mmTCP_PERFCOUNTER1_LO                                    :Result:='mmTCP_PERFCOUNTER1_LO';
  mmTCP_PERFCOUNTER1_HI                                    :Result:='mmTCP_PERFCOUNTER1_HI';
  mmTCP_PERFCOUNTER2_LO                                    :Result:='mmTCP_PERFCOUNTER2_LO';
  mmTCP_PERFCOUNTER2_HI                                    :Result:='mmTCP_PERFCOUNTER2_HI';
  mmTCP_PERFCOUNTER3_LO                                    :Result:='mmTCP_PERFCOUNTER3_LO';
  mmTCP_PERFCOUNTER3_HI                                    :Result:='mmTCP_PERFCOUNTER3_HI';
  mmTCC_PERFCOUNTER0_LO                                    :Result:='mmTCC_PERFCOUNTER0_LO';
  mmTCC_PERFCOUNTER0_HI                                    :Result:='mmTCC_PERFCOUNTER0_HI';
  mmTCC_PERFCOUNTER1_LO                                    :Result:='mmTCC_PERFCOUNTER1_LO';
  mmTCC_PERFCOUNTER1_HI                                    :Result:='mmTCC_PERFCOUNTER1_HI';
  mmTCC_PERFCOUNTER2_LO                                    :Result:='mmTCC_PERFCOUNTER2_LO';
  mmTCC_PERFCOUNTER2_HI                                    :Result:='mmTCC_PERFCOUNTER2_HI';
  mmTCC_PERFCOUNTER3_LO                                    :Result:='mmTCC_PERFCOUNTER3_LO';
  mmTCC_PERFCOUNTER3_HI                                    :Result:='mmTCC_PERFCOUNTER3_HI';
  mmTCA_PERFCOUNTER0_LO                                    :Result:='mmTCA_PERFCOUNTER0_LO';
  mmTCA_PERFCOUNTER0_HI                                    :Result:='mmTCA_PERFCOUNTER0_HI';
  mmTCA_PERFCOUNTER1_LO                                    :Result:='mmTCA_PERFCOUNTER1_LO';
  mmTCA_PERFCOUNTER1_HI                                    :Result:='mmTCA_PERFCOUNTER1_HI';
  mmTCA_PERFCOUNTER2_LO                                    :Result:='mmTCA_PERFCOUNTER2_LO';
  mmTCA_PERFCOUNTER2_HI                                    :Result:='mmTCA_PERFCOUNTER2_HI';
  mmTCA_PERFCOUNTER3_LO                                    :Result:='mmTCA_PERFCOUNTER3_LO';
  mmTCA_PERFCOUNTER3_HI                                    :Result:='mmTCA_PERFCOUNTER3_HI';
  mmCB_PERFCOUNTER0_LO                                     :Result:='mmCB_PERFCOUNTER0_LO';
  mmCB_PERFCOUNTER0_HI                                     :Result:='mmCB_PERFCOUNTER0_HI';
  mmCB_PERFCOUNTER1_LO                                     :Result:='mmCB_PERFCOUNTER1_LO';
  mmCB_PERFCOUNTER1_HI                                     :Result:='mmCB_PERFCOUNTER1_HI';
  mmCB_PERFCOUNTER2_LO                                     :Result:='mmCB_PERFCOUNTER2_LO';
  mmCB_PERFCOUNTER2_HI                                     :Result:='mmCB_PERFCOUNTER2_HI';
  mmCB_PERFCOUNTER3_LO                                     :Result:='mmCB_PERFCOUNTER3_LO';
  mmCB_PERFCOUNTER3_HI                                     :Result:='mmCB_PERFCOUNTER3_HI';
  mmDB_PERFCOUNTER0_LO                                     :Result:='mmDB_PERFCOUNTER0_LO';
  mmDB_PERFCOUNTER0_HI                                     :Result:='mmDB_PERFCOUNTER0_HI';
  mmDB_PERFCOUNTER1_LO                                     :Result:='mmDB_PERFCOUNTER1_LO';
  mmDB_PERFCOUNTER1_HI                                     :Result:='mmDB_PERFCOUNTER1_HI';
  mmDB_PERFCOUNTER2_LO                                     :Result:='mmDB_PERFCOUNTER2_LO';
  mmDB_PERFCOUNTER2_HI                                     :Result:='mmDB_PERFCOUNTER2_HI';
  mmDB_PERFCOUNTER3_LO                                     :Result:='mmDB_PERFCOUNTER3_LO';
  mmDB_PERFCOUNTER3_HI                                     :Result:='mmDB_PERFCOUNTER3_HI';
  mmRLC_PERFCOUNTER0_LO                                    :Result:='mmRLC_PERFCOUNTER0_LO';
  mmRLC_PERFCOUNTER0_HI                                    :Result:='mmRLC_PERFCOUNTER0_HI';
  mmRLC_PERFCOUNTER1_LO                                    :Result:='mmRLC_PERFCOUNTER1_LO';
  mmRLC_PERFCOUNTER1_HI                                    :Result:='mmRLC_PERFCOUNTER1_HI';
  mmCPG_PERFCOUNTER1_SELECT                                :Result:='mmCPG_PERFCOUNTER1_SELECT';
  mmCPG_PERFCOUNTER0_SELECT1                               :Result:='mmCPG_PERFCOUNTER0_SELECT1';
  mmCPG_PERFCOUNTER0_SELECT                                :Result:='mmCPG_PERFCOUNTER0_SELECT';
  mmCPC_PERFCOUNTER1_SELECT                                :Result:='mmCPC_PERFCOUNTER1_SELECT';
  mmCPC_PERFCOUNTER0_SELECT1                               :Result:='mmCPC_PERFCOUNTER0_SELECT1';
  mmCPF_PERFCOUNTER1_SELECT                                :Result:='mmCPF_PERFCOUNTER1_SELECT';
  mmCPF_PERFCOUNTER0_SELECT1                               :Result:='mmCPF_PERFCOUNTER0_SELECT1';
  mmCPF_PERFCOUNTER0_SELECT                                :Result:='mmCPF_PERFCOUNTER0_SELECT';
  mmCP_PERFMON_CNTL                                        :Result:='mmCP_PERFMON_CNTL';
  mmCPC_PERFCOUNTER0_SELECT                                :Result:='mmCPC_PERFCOUNTER0_SELECT';
  mmCP_DRAW_OBJECT                                         :Result:='mmCP_DRAW_OBJECT';
  mmCP_DRAW_OBJECT_COUNTER                                 :Result:='mmCP_DRAW_OBJECT_COUNTER';
  mmCP_DRAW_WINDOW_MASK_HI                                 :Result:='mmCP_DRAW_WINDOW_MASK_HI';
  mmCP_DRAW_WINDOW_HI                                      :Result:='mmCP_DRAW_WINDOW_HI';
  mmCP_DRAW_WINDOW_LO                                      :Result:='mmCP_DRAW_WINDOW_LO';
  mmCP_DRAW_WINDOW_CNTL                                    :Result:='mmCP_DRAW_WINDOW_CNTL';
  mmGRBM_PERFCOUNTER0_SELECT                               :Result:='mmGRBM_PERFCOUNTER0_SELECT';
  mmGRBM_PERFCOUNTER1_SELECT                               :Result:='mmGRBM_PERFCOUNTER1_SELECT';
  mmGRBM_SE0_PERFCOUNTER_SELECT                            :Result:='mmGRBM_SE0_PERFCOUNTER_SELECT';
  mmGRBM_SE1_PERFCOUNTER_SELECT                            :Result:='mmGRBM_SE1_PERFCOUNTER_SELECT';
  mmGRBM_SE2_PERFCOUNTER_SELECT                            :Result:='mmGRBM_SE2_PERFCOUNTER_SELECT';
  mmGRBM_SE3_PERFCOUNTER_SELECT                            :Result:='mmGRBM_SE3_PERFCOUNTER_SELECT';
  mmWD_PERFCOUNTER0_SELECT                                 :Result:='mmWD_PERFCOUNTER0_SELECT';
  mmWD_PERFCOUNTER1_SELECT                                 :Result:='mmWD_PERFCOUNTER1_SELECT';
  mmWD_PERFCOUNTER2_SELECT                                 :Result:='mmWD_PERFCOUNTER2_SELECT';
  mmWD_PERFCOUNTER3_SELECT                                 :Result:='mmWD_PERFCOUNTER3_SELECT';
  mmIA_PERFCOUNTER0_SELECT                                 :Result:='mmIA_PERFCOUNTER0_SELECT';
  mmIA_PERFCOUNTER1_SELECT                                 :Result:='mmIA_PERFCOUNTER1_SELECT';
  mmIA_PERFCOUNTER2_SELECT                                 :Result:='mmIA_PERFCOUNTER2_SELECT';
  mmIA_PERFCOUNTER3_SELECT                                 :Result:='mmIA_PERFCOUNTER3_SELECT';
  mmIA_PERFCOUNTER0_SELECT1                                :Result:='mmIA_PERFCOUNTER0_SELECT1';
  mmVGT_PERFCOUNTER0_SELECT                                :Result:='mmVGT_PERFCOUNTER0_SELECT';
  mmVGT_PERFCOUNTER1_SELECT                                :Result:='mmVGT_PERFCOUNTER1_SELECT';
  mmVGT_PERFCOUNTER2_SELECT                                :Result:='mmVGT_PERFCOUNTER2_SELECT';
  mmVGT_PERFCOUNTER3_SELECT                                :Result:='mmVGT_PERFCOUNTER3_SELECT';
  mmVGT_PERFCOUNTER0_SELECT1                               :Result:='mmVGT_PERFCOUNTER0_SELECT1';
  mmVGT_PERFCOUNTER1_SELECT1                               :Result:='mmVGT_PERFCOUNTER1_SELECT1';
  mmVGT_PERFCOUNTER_SEID_MASK                              :Result:='mmVGT_PERFCOUNTER_SEID_MASK';
  mmPA_SU_PERFCOUNTER0_SELECT                              :Result:='mmPA_SU_PERFCOUNTER0_SELECT';
  mmPA_SU_PERFCOUNTER0_SELECT1                             :Result:='mmPA_SU_PERFCOUNTER0_SELECT1';
  mmPA_SU_PERFCOUNTER1_SELECT                              :Result:='mmPA_SU_PERFCOUNTER1_SELECT';
  mmPA_SU_PERFCOUNTER1_SELECT1                             :Result:='mmPA_SU_PERFCOUNTER1_SELECT1';
  mmPA_SU_PERFCOUNTER2_SELECT                              :Result:='mmPA_SU_PERFCOUNTER2_SELECT';
  mmPA_SU_PERFCOUNTER3_SELECT                              :Result:='mmPA_SU_PERFCOUNTER3_SELECT';
  mmPA_SC_PERFCOUNTER0_SELECT                              :Result:='mmPA_SC_PERFCOUNTER0_SELECT';
  mmPA_SC_PERFCOUNTER0_SELECT1                             :Result:='mmPA_SC_PERFCOUNTER0_SELECT1';
  mmPA_SC_PERFCOUNTER1_SELECT                              :Result:='mmPA_SC_PERFCOUNTER1_SELECT';
  mmPA_SC_PERFCOUNTER2_SELECT                              :Result:='mmPA_SC_PERFCOUNTER2_SELECT';
  mmPA_SC_PERFCOUNTER3_SELECT                              :Result:='mmPA_SC_PERFCOUNTER3_SELECT';
  mmPA_SC_PERFCOUNTER4_SELECT                              :Result:='mmPA_SC_PERFCOUNTER4_SELECT';
  mmPA_SC_PERFCOUNTER5_SELECT                              :Result:='mmPA_SC_PERFCOUNTER5_SELECT';
  mmPA_SC_PERFCOUNTER6_SELECT                              :Result:='mmPA_SC_PERFCOUNTER6_SELECT';
  mmPA_SC_PERFCOUNTER7_SELECT                              :Result:='mmPA_SC_PERFCOUNTER7_SELECT';
  mmSPI_PERFCOUNTER0_SELECT                                :Result:='mmSPI_PERFCOUNTER0_SELECT';
  mmSPI_PERFCOUNTER1_SELECT                                :Result:='mmSPI_PERFCOUNTER1_SELECT';
  mmSPI_PERFCOUNTER2_SELECT                                :Result:='mmSPI_PERFCOUNTER2_SELECT';
  mmSPI_PERFCOUNTER3_SELECT                                :Result:='mmSPI_PERFCOUNTER3_SELECT';
  mmSPI_PERFCOUNTER0_SELECT1                               :Result:='mmSPI_PERFCOUNTER0_SELECT1';
  mmSPI_PERFCOUNTER1_SELECT1                               :Result:='mmSPI_PERFCOUNTER1_SELECT1';
  mmSPI_PERFCOUNTER2_SELECT1                               :Result:='mmSPI_PERFCOUNTER2_SELECT1';
  mmSPI_PERFCOUNTER3_SELECT1                               :Result:='mmSPI_PERFCOUNTER3_SELECT1';
  mmSPI_PERFCOUNTER4_SELECT                                :Result:='mmSPI_PERFCOUNTER4_SELECT';
  mmSPI_PERFCOUNTER5_SELECT                                :Result:='mmSPI_PERFCOUNTER5_SELECT';
  mmSPI_PERFCOUNTER_BINS                                   :Result:='mmSPI_PERFCOUNTER_BINS';
  mmSQ_PERFCOUNTER0_SELECT                                 :Result:='mmSQ_PERFCOUNTER0_SELECT';
  mmSQ_PERFCOUNTER1_SELECT                                 :Result:='mmSQ_PERFCOUNTER1_SELECT';
  mmSQ_PERFCOUNTER2_SELECT                                 :Result:='mmSQ_PERFCOUNTER2_SELECT';
  mmSQ_PERFCOUNTER3_SELECT                                 :Result:='mmSQ_PERFCOUNTER3_SELECT';
  mmSQ_PERFCOUNTER4_SELECT                                 :Result:='mmSQ_PERFCOUNTER4_SELECT';
  mmSQ_PERFCOUNTER5_SELECT                                 :Result:='mmSQ_PERFCOUNTER5_SELECT';
  mmSQ_PERFCOUNTER6_SELECT                                 :Result:='mmSQ_PERFCOUNTER6_SELECT';
  mmSQ_PERFCOUNTER7_SELECT                                 :Result:='mmSQ_PERFCOUNTER7_SELECT';
  mmSQ_PERFCOUNTER8_SELECT                                 :Result:='mmSQ_PERFCOUNTER8_SELECT';
  mmSQ_PERFCOUNTER9_SELECT                                 :Result:='mmSQ_PERFCOUNTER9_SELECT';
  mmSQ_PERFCOUNTER10_SELECT                                :Result:='mmSQ_PERFCOUNTER10_SELECT';
  mmSQ_PERFCOUNTER11_SELECT                                :Result:='mmSQ_PERFCOUNTER11_SELECT';
  mmSQ_PERFCOUNTER12_SELECT                                :Result:='mmSQ_PERFCOUNTER12_SELECT';
  mmSQ_PERFCOUNTER13_SELECT                                :Result:='mmSQ_PERFCOUNTER13_SELECT';
  mmSQ_PERFCOUNTER14_SELECT                                :Result:='mmSQ_PERFCOUNTER14_SELECT';
  mmSQ_PERFCOUNTER15_SELECT                                :Result:='mmSQ_PERFCOUNTER15_SELECT';
  mmSQ_PERFCOUNTER_CTRL                                    :Result:='mmSQ_PERFCOUNTER_CTRL';
  mmSQ_PERFCOUNTER_MASK                                    :Result:='mmSQ_PERFCOUNTER_MASK';
  mmSQ_PERFCOUNTER_CTRL2                                   :Result:='mmSQ_PERFCOUNTER_CTRL2';
  mmSX_PERFCOUNTER0_SELECT                                 :Result:='mmSX_PERFCOUNTER0_SELECT';
  mmSX_PERFCOUNTER1_SELECT                                 :Result:='mmSX_PERFCOUNTER1_SELECT';
  mmSX_PERFCOUNTER2_SELECT                                 :Result:='mmSX_PERFCOUNTER2_SELECT';
  mmSX_PERFCOUNTER3_SELECT                                 :Result:='mmSX_PERFCOUNTER3_SELECT';
  mmSX_PERFCOUNTER0_SELECT1                                :Result:='mmSX_PERFCOUNTER0_SELECT1';
  mmSX_PERFCOUNTER1_SELECT1                                :Result:='mmSX_PERFCOUNTER1_SELECT1';
  mmGDS_PERFCOUNTER0_SELECT                                :Result:='mmGDS_PERFCOUNTER0_SELECT';
  mmGDS_PERFCOUNTER1_SELECT                                :Result:='mmGDS_PERFCOUNTER1_SELECT';
  mmGDS_PERFCOUNTER2_SELECT                                :Result:='mmGDS_PERFCOUNTER2_SELECT';
  mmGDS_PERFCOUNTER3_SELECT                                :Result:='mmGDS_PERFCOUNTER3_SELECT';
  mmGDS_PERFCOUNTER0_SELECT1                               :Result:='mmGDS_PERFCOUNTER0_SELECT1';
  mmTA_PERFCOUNTER0_SELECT                                 :Result:='mmTA_PERFCOUNTER0_SELECT';
  mmTA_PERFCOUNTER0_SELECT1                                :Result:='mmTA_PERFCOUNTER0_SELECT1';
  mmTA_PERFCOUNTER1_SELECT                                 :Result:='mmTA_PERFCOUNTER1_SELECT';
  mmTD_PERFCOUNTER0_SELECT                                 :Result:='mmTD_PERFCOUNTER0_SELECT';
  mmTD_PERFCOUNTER0_SELECT1                                :Result:='mmTD_PERFCOUNTER0_SELECT1';
  mmTD_PERFCOUNTER1_SELECT                                 :Result:='mmTD_PERFCOUNTER1_SELECT';
  mmTCP_PERFCOUNTER0_SELECT                                :Result:='mmTCP_PERFCOUNTER0_SELECT';
  mmTCP_PERFCOUNTER0_SELECT1                               :Result:='mmTCP_PERFCOUNTER0_SELECT1';
  mmTCP_PERFCOUNTER1_SELECT                                :Result:='mmTCP_PERFCOUNTER1_SELECT';
  mmTCP_PERFCOUNTER1_SELECT1                               :Result:='mmTCP_PERFCOUNTER1_SELECT1';
  mmTCP_PERFCOUNTER2_SELECT                                :Result:='mmTCP_PERFCOUNTER2_SELECT';
  mmTCP_PERFCOUNTER3_SELECT                                :Result:='mmTCP_PERFCOUNTER3_SELECT';
  mmTCC_PERFCOUNTER0_SELECT                                :Result:='mmTCC_PERFCOUNTER0_SELECT';
  mmTCC_PERFCOUNTER0_SELECT1                               :Result:='mmTCC_PERFCOUNTER0_SELECT1';
  mmTCC_PERFCOUNTER1_SELECT                                :Result:='mmTCC_PERFCOUNTER1_SELECT';
  mmTCC_PERFCOUNTER1_SELECT1                               :Result:='mmTCC_PERFCOUNTER1_SELECT1';
  mmTCC_PERFCOUNTER2_SELECT                                :Result:='mmTCC_PERFCOUNTER2_SELECT';
  mmTCC_PERFCOUNTER3_SELECT                                :Result:='mmTCC_PERFCOUNTER3_SELECT';
  mmTCA_PERFCOUNTER0_SELECT                                :Result:='mmTCA_PERFCOUNTER0_SELECT';
  mmTCA_PERFCOUNTER0_SELECT1                               :Result:='mmTCA_PERFCOUNTER0_SELECT1';
  mmTCA_PERFCOUNTER1_SELECT                                :Result:='mmTCA_PERFCOUNTER1_SELECT';
  mmTCA_PERFCOUNTER1_SELECT1                               :Result:='mmTCA_PERFCOUNTER1_SELECT1';
  mmTCA_PERFCOUNTER2_SELECT                                :Result:='mmTCA_PERFCOUNTER2_SELECT';
  mmTCA_PERFCOUNTER3_SELECT                                :Result:='mmTCA_PERFCOUNTER3_SELECT';
  mmCB_PERFCOUNTER_FILTER                                  :Result:='mmCB_PERFCOUNTER_FILTER';
  mmCB_PERFCOUNTER0_SELECT                                 :Result:='mmCB_PERFCOUNTER0_SELECT';
  mmCB_PERFCOUNTER0_SELECT1                                :Result:='mmCB_PERFCOUNTER0_SELECT1';
  mmCB_PERFCOUNTER1_SELECT                                 :Result:='mmCB_PERFCOUNTER1_SELECT';
  mmCB_PERFCOUNTER2_SELECT                                 :Result:='mmCB_PERFCOUNTER2_SELECT';
  mmCB_PERFCOUNTER3_SELECT                                 :Result:='mmCB_PERFCOUNTER3_SELECT';
  mmDB_PERFCOUNTER0_SELECT                                 :Result:='mmDB_PERFCOUNTER0_SELECT';
  mmDB_PERFCOUNTER0_SELECT1                                :Result:='mmDB_PERFCOUNTER0_SELECT1';
  mmDB_PERFCOUNTER1_SELECT                                 :Result:='mmDB_PERFCOUNTER1_SELECT';
  mmDB_PERFCOUNTER1_SELECT1                                :Result:='mmDB_PERFCOUNTER1_SELECT1';
  mmDB_PERFCOUNTER2_SELECT                                 :Result:='mmDB_PERFCOUNTER2_SELECT';
  mmDB_PERFCOUNTER3_SELECT                                 :Result:='mmDB_PERFCOUNTER3_SELECT';
 else
  Result:=HexStr(i,4);
 end;
end;

end.

