unit si_ci_vi_merged_groups;

{$mode objfpc}{$H+}

interface

uses
 si_ci_vi_merged_registers;

type
 TRENDER_TARGET=packed record
  BASE       :TCB_COLOR0_BASE       ; //mmCB_COLOR0_BASE_DEFAULT
  PITCH      :TCB_COLOR0_PITCH      ; //mmCB_COLOR0_PITCH_DEFAULT
  SLICE      :TCB_COLOR0_SLICE      ; //mmCB_COLOR0_SLICE_DEFAULT
  VIEW       :TCB_COLOR0_VIEW       ; //mmCB_COLOR0_VIEW_DEFAULT
  INFO       :TCB_COLOR0_INFO       ; //mmCB_COLOR0_INFO_DEFAULT
  ATTRIB     :TCB_COLOR0_ATTRIB     ; //mmCB_COLOR0_ATTRIB_DEFAULT
  DCC_CONTROL:TCB_COLOR0_DCC_CONTROL; //mmCB_COLOR0_DCC_CONTROL_DEFAULT
  CMASK      :TCB_COLOR0_CMASK      ; //mmCB_COLOR0_CMASK_DEFAULT
  CMASK_SLICE:TCB_COLOR0_CMASK_SLICE; //mmCB_COLOR0_CMASK_SLICE_DEFAULT
  FMASK      :TCB_COLOR0_FMASK      ; //mmCB_COLOR0_FMASK_DEFAULT
  FMASK_SLICE:TCB_COLOR0_FMASK_SLICE; //mmCB_COLOR0_FMASK_SLICE_DEFAULT
  CLEAR_WORD :QWORD;                  //mmCB_COLOR0_CLEAR_WORD0_DEFAULT
                                      //mmCB_COLOR0_CLEAR_WORD1_DEFAULT
  DCC_BASE   :TCB_COLOR0_DCC_BASE   ; //mmCB_COLOR0_DCC_BASE_DEFAULT
  ALIGN      :DWORD;
 end;

 TGB_CLIP=packed record
  VERT_CLIP_ADJ:Single;
  VERT_DISC_ADJ:Single;
  HORZ_CLIP_ADJ:Single;
  HORZ_DISC_ADJ:Single;
 end; 

 TVPORT_SCISSOR=packed record
  TL:TPA_SC_VPORT_SCISSOR_0_TL;
  BR:TPA_SC_VPORT_SCISSOR_0_BR;
 end;

 TVPORT_ZMIN_MAX=packed record
  ZMIN:Single;
  ZMAX:Single;
 end;

 TVPORT_SCALE_OFFSET=packed record
  XSCALE :Single;
  XOFFSET:Single;
  YSCALE :Single;
  YOFFSET:Single;
  ZSCALE :Single;
  ZOFFSET:Single;
 end;

 TSPI_USER_DATA=array[0..15] of DWORD;

 TSH_REG_GFX_GROUP=bitpacked record
  SPI_SHADER_TBA_LO_PS      :TSPI_SHADER_TBA_LO_PS;       // 0x2C00
  SPI_SHADER_TBA_HI_PS      :TSPI_SHADER_TBA_HI_PS;       // 0x2C01
  SPI_SHADER_TMA_LO_PS      :TSPI_SHADER_TMA_LO_PS;       // 0x2C02
  SPI_SHADER_TMA_HI_PS      :TSPI_SHADER_TMA_HI_PS;       // 0x2C03
  REG_2C04_2C06             :array[0..2] of DWORD;        // 0x2C04
  SPI_SHADER_PGM_RSRC3_PS   :TSPI_SHADER_PGM_RSRC3_PS;    // 0x2C07
  SPI_SHADER_PGM_LO_PS      :TSPI_SHADER_PGM_LO_PS;       // 0x2C08
  SPI_SHADER_PGM_HI_PS      :TSPI_SHADER_PGM_HI_PS;       // 0x2C09
  SPI_SHADER_PGM_RSRC1_PS   :TSPI_SHADER_PGM_RSRC1_PS;    // 0x2C0A
  SPI_SHADER_PGM_RSRC2_PS   :TSPI_SHADER_PGM_RSRC2_PS;    // 0x2C0B
  SPI_SHADER_USER_DATA_PS   :TSPI_USER_DATA;              // 0x2C0C
  REG_2C1C_2C3F             :array[0..35] of DWORD;       // 0x2C1C
  SPI_SHADER_TBA_LO_VS      :TSPI_SHADER_TBA_LO_VS;       // 0x2C40
  SPI_SHADER_TBA_HI_VS      :TSPI_SHADER_TBA_HI_VS;       // 0x2C41
  SPI_SHADER_TMA_LO_VS      :TSPI_SHADER_TMA_LO_VS;       // 0x2C42
  SPI_SHADER_TMA_HI_VS      :TSPI_SHADER_TMA_HI_VS;       // 0x2C43
  REG_2C44_2C45             :array[0..1] of DWORD;        // 0x2C44
  SPI_SHADER_PGM_RSRC3_VS   :TSPI_SHADER_PGM_RSRC3_VS;    // 0x2C46
  SPI_SHADER_LATE_ALLOC_VS  :TSPI_SHADER_LATE_ALLOC_VS;   // 0x2C47
  SPI_SHADER_PGM_LO_VS      :TSPI_SHADER_PGM_LO_VS;       // 0x2C48
  SPI_SHADER_PGM_HI_VS      :TSPI_SHADER_PGM_HI_VS;       // 0x2C49
  SPI_SHADER_PGM_RSRC1_VS   :TSPI_SHADER_PGM_RSRC1_VS;    // 0x2C4A
  SPI_SHADER_PGM_RSRC2_VS   :TSPI_SHADER_PGM_RSRC2_VS;    // 0x2C4B
  SPI_SHADER_USER_DATA_VS   :TSPI_USER_DATA;              // 0x2C4C
  REG_2C5C_2C7B             :array[0..31] of DWORD;       // 0x2C5C
  SPI_SHADER_PGM_RSRC2_ES_VS:TSPI_SHADER_PGM_RSRC2_ES_VS; // 0x2C7C
  SPI_SHADER_PGM_RSRC2_LS_VS:TSPI_SHADER_PGM_RSRC2_LS_VS; // 0x2C7D
  REG_2C7E_2C7F             :array[0..1] of DWORD;        // 0x2C7E
  SPI_SHADER_TBA_LO_GS      :TSPI_SHADER_TBA_LO_GS;       // 0x2C80
  SPI_SHADER_TBA_HI_GS      :TSPI_SHADER_TBA_HI_GS;       // 0x2C81
  SPI_SHADER_TMA_LO_GS      :TSPI_SHADER_TMA_LO_GS;       // 0x2C82
  SPI_SHADER_TMA_HI_GS      :TSPI_SHADER_TMA_HI_GS;       // 0x2C83
  REG_2C84_2C86             :array[0..2] of DWORD;        // 0x2C84
  SPI_SHADER_PGM_RSRC3_GS   :TSPI_SHADER_PGM_RSRC3_GS;    // 0x2C87
  SPI_SHADER_PGM_LO_GS      :TSPI_SHADER_PGM_LO_GS;       // 0x2C88
  SPI_SHADER_PGM_HI_GS      :TSPI_SHADER_PGM_HI_GS;       // 0x2C89
  SPI_SHADER_PGM_RSRC1_GS   :TSPI_SHADER_PGM_RSRC1_GS;    // 0x2C8A
  SPI_SHADER_PGM_RSRC2_GS   :TSPI_SHADER_PGM_RSRC2_GS;    // 0x2C8B
  SPI_SHADER_USER_DATA_GS   :TSPI_USER_DATA;              // 0x2C8C
  REG_2C9C_2CBB             :array[0..31] of DWORD;       // 0x2C9C
  SPI_SHADER_PGM_RSRC2_ES_GS:TSPI_SHADER_PGM_RSRC2_ES_GS; // 0x2CBC
  REG_2CBD_2CBF             :array[0..2] of DWORD;        // 0x2CBD
  SPI_SHADER_TBA_LO_ES      :TSPI_SHADER_TBA_LO_ES;       // 0x2CC0
  SPI_SHADER_TBA_HI_ES      :TSPI_SHADER_TBA_HI_ES;       // 0x2CC1
  SPI_SHADER_TMA_LO_ES      :TSPI_SHADER_TMA_LO_ES;       // 0x2CC2
  SPI_SHADER_TMA_HI_ES      :TSPI_SHADER_TMA_HI_ES;       // 0x2CC3
  REG_2CC4_2CC6             :array[0..2] of DWORD;        // 0x2CC4
  SPI_SHADER_PGM_RSRC3_ES   :TSPI_SHADER_PGM_RSRC3_ES;    // 0x2CC7
  SPI_SHADER_PGM_LO_ES      :TSPI_SHADER_PGM_LO_ES;       // 0x2CC8
  SPI_SHADER_PGM_HI_ES      :TSPI_SHADER_PGM_HI_ES;       // 0x2CC9
  SPI_SHADER_PGM_RSRC1_ES   :TSPI_SHADER_PGM_RSRC1_ES;    // 0x2CCA
  SPI_SHADER_PGM_RSRC2_ES   :TSPI_SHADER_PGM_RSRC2_ES;    // 0x2CCB
  SPI_SHADER_USER_DATA_ES   :TSPI_USER_DATA;              // 0x2CCC
  REG_2CDC_2CFC             :array[0..32] of DWORD;       // 0x2CDC
  SPI_SHADER_PGM_RSRC2_LS_ES:TSPI_SHADER_PGM_RSRC2_LS_ES; // 0x2CFD
  REG_2CFE_2CFF             :array[0..1] of DWORD;        // 0x2CFE
  SPI_SHADER_TBA_LO_HS      :TSPI_SHADER_TBA_LO_HS;       // 0x2D00
  SPI_SHADER_TBA_HI_HS      :TSPI_SHADER_TBA_HI_HS;       // 0x2D01
  SPI_SHADER_TMA_LO_HS      :TSPI_SHADER_TMA_LO_HS;       // 0x2D02
  SPI_SHADER_TMA_HI_HS      :TSPI_SHADER_TMA_HI_HS;       // 0x2D03
  REG_2D04_2D06             :array[0..2] of DWORD;        // 0x2D04
  SPI_SHADER_PGM_RSRC3_HS   :TSPI_SHADER_PGM_RSRC3_HS;    // 0x2D07
  SPI_SHADER_PGM_LO_HS      :TSPI_SHADER_PGM_LO_HS;       // 0x2D08
  SPI_SHADER_PGM_HI_HS      :TSPI_SHADER_PGM_HI_HS;       // 0x2D09
  SPI_SHADER_PGM_RSRC1_HS   :TSPI_SHADER_PGM_RSRC1_HS;    // 0x2D0A
  SPI_SHADER_PGM_RSRC2_HS   :TSPI_SHADER_PGM_RSRC2_HS;    // 0x2D0B
  SPI_SHADER_USER_DATA_HS   :TSPI_USER_DATA;              // 0x2D0C
  REG_2D1C_2D3C             :array[0..32] of DWORD;       // 0x2D1C
  SPI_SHADER_PGM_RSRC2_LS_HS:TSPI_SHADER_PGM_RSRC2_LS_HS; // 0x2D3D
  REG_2D3E_2D3F             :array[0..1] of DWORD;        // 0x2D3E
  SPI_SHADER_TBA_LO_LS      :TSPI_SHADER_TBA_LO_LS;       // 0x2D40
  SPI_SHADER_TBA_HI_LS      :TSPI_SHADER_TBA_HI_LS;       // 0x2D41
  SPI_SHADER_TMA_LO_LS      :TSPI_SHADER_TMA_LO_LS;       // 0x2D42
  SPI_SHADER_TMA_HI_LS      :TSPI_SHADER_TMA_HI_LS;       // 0x2D43
  REG_2D44_2D46             :array[0..2] of DWORD;        // 0x2D44
  SPI_SHADER_PGM_RSRC3_LS   :TSPI_SHADER_PGM_RSRC3_LS;    // 0x2D47
  SPI_SHADER_PGM_LO_LS      :TSPI_SHADER_PGM_LO_LS;       // 0x2D48
  SPI_SHADER_PGM_HI_LS      :TSPI_SHADER_PGM_HI_LS;       // 0x2D49
  SPI_SHADER_PGM_RSRC1_LS   :TSPI_SHADER_PGM_RSRC1_LS;    // 0x2D4A
  SPI_SHADER_PGM_RSRC2_LS   :TSPI_SHADER_PGM_RSRC2_LS;    // 0x2D4B
  SPI_SHADER_USER_DATA_LS   :TSPI_USER_DATA;              // 0x2D4C
 end;

 TSH_REG_COMPUTE_GROUP=bitpacked record
  COMPUTE_DISPATCH_INITIATOR    :TCOMPUTE_DISPATCH_INITIATOR;     // 0x2E00
  COMPUTE_DIM_X                 :TCOMPUTE_DIM_X;                  // 0x2E01
  COMPUTE_DIM_Y                 :TCOMPUTE_DIM_Y;                  // 0x2E02
  COMPUTE_DIM_Z                 :TCOMPUTE_DIM_Z;                  // 0x2E03
  COMPUTE_START_X               :TCOMPUTE_START_X;                // 0x2E04
  COMPUTE_START_Y               :TCOMPUTE_START_Y;                // 0x2E05
  COMPUTE_START_Z               :TCOMPUTE_START_Z;                // 0x2E06
  COMPUTE_NUM_THREAD_X          :TCOMPUTE_NUM_THREAD_X;           // 0x2E07
  COMPUTE_NUM_THREAD_Y          :TCOMPUTE_NUM_THREAD_Y;           // 0x2E08
  COMPUTE_NUM_THREAD_Z          :TCOMPUTE_NUM_THREAD_Z;           // 0x2E09
  COMPUTE_PIPELINESTAT_ENABLE   :TCOMPUTE_PIPELINESTAT_ENABLE;    // 0x2E0A
  COMPUTE_PERFCOUNT_ENABLE      :TCOMPUTE_PERFCOUNT_ENABLE;       // 0x2E0B
  COMPUTE_PGM_LO                :TCOMPUTE_PGM_LO;                 // 0x2E0C
  COMPUTE_PGM_HI                :TCOMPUTE_PGM_HI;                 // 0x2E0D
  COMPUTE_TBA_LO                :TCOMPUTE_TBA_LO;                 // 0x2E0E
  COMPUTE_TBA_HI                :TCOMPUTE_TBA_HI;                 // 0x2E0F
  COMPUTE_TMA_LO                :TCOMPUTE_TMA_LO;                 // 0x2E10
  COMPUTE_TMA_HI                :TCOMPUTE_TMA_HI;                 // 0x2E11
  COMPUTE_PGM_RSRC1             :TCOMPUTE_PGM_RSRC1;              // 0x2E12
  COMPUTE_PGM_RSRC2             :TCOMPUTE_PGM_RSRC2;              // 0x2E13
  COMPUTE_VMID                  :TCOMPUTE_VMID;                   // 0x2E14
  COMPUTE_RESOURCE_LIMITS       :TCOMPUTE_RESOURCE_LIMITS;        // 0x2E15
  COMPUTE_STATIC_THREAD_MGMT_SE0:TCOMPUTE_STATIC_THREAD_MGMT_SE0; // 0x2E16
  COMPUTE_STATIC_THREAD_MGMT_SE1:TCOMPUTE_STATIC_THREAD_MGMT_SE1; // 0x2E17
  COMPUTE_TMPRING_SIZE          :TCOMPUTE_TMPRING_SIZE;           // 0x2E18
  COMPUTE_STATIC_THREAD_MGMT_SE2:TCOMPUTE_STATIC_THREAD_MGMT_SE2; // 0x2E19
  COMPUTE_STATIC_THREAD_MGMT_SE3:TCOMPUTE_STATIC_THREAD_MGMT_SE3; // 0x2E1A
  COMPUTE_RESTART_X             :TCOMPUTE_RESTART_X;              // 0x2E1B
  COMPUTE_RESTART_Y             :TCOMPUTE_RESTART_Y;              // 0x2E1C
  COMPUTE_RESTART_Z             :TCOMPUTE_RESTART_Z;              // 0x2E1D
  COMPUTE_THREAD_TRACE_ENABLE   :TCOMPUTE_THREAD_TRACE_ENABLE;    // 0x2E1E
  COMPUTE_MISC_RESERVED         :TCOMPUTE_MISC_RESERVED;          // 0x2E1F
  COMPUTE_DISPATCH_ID           :TCOMPUTE_DISPATCH_ID;            // 0x2E20
  COMPUTE_THREADGROUP_ID        :TCOMPUTE_THREADGROUP_ID;         // 0x2E21
  COMPUTE_RELAUNCH              :TCOMPUTE_RELAUNCH;               // 0x2E22
  COMPUTE_WAVE_RESTORE_ADDR_LO  :TCOMPUTE_WAVE_RESTORE_ADDR_LO;   // 0x2E23
  COMPUTE_WAVE_RESTORE_ADDR_HI  :TCOMPUTE_WAVE_RESTORE_ADDR_HI;   // 0x2E24
  COMPUTE_WAVE_RESTORE_CONTROL  :TCOMPUTE_WAVE_RESTORE_CONTROL;   // 0x2E25
  REG_2E26_2E3F                 :array[0..25] of DWORD;           // 0x2E26
  COMPUTE_USER_DATA             :TSPI_USER_DATA;                  // 0x2E40
  REG_2E50_2E7E                 :array[0..46] of DWORD;           // 0x2E50
  COMPUTE_NOWHERE               :TCOMPUTE_NOWHERE;                // 0x2E7F
 end;

 TCONTEXT_REG_GROUP=bitpacked record
  DB_RENDER_CONTROL                         :TDB_RENDER_CONTROL;                          // 0xA000
  DB_COUNT_CONTROL                          :TDB_COUNT_CONTROL;                           // 0xA001
  DB_DEPTH_VIEW                             :TDB_DEPTH_VIEW;                              // 0xA002
  DB_RENDER_OVERRIDE                        :TDB_RENDER_OVERRIDE;                         // 0xA003
  DB_RENDER_OVERRIDE2                       :TDB_RENDER_OVERRIDE2;                        // 0xA004
  DB_HTILE_DATA_BASE                        :TDB_HTILE_DATA_BASE;                         // 0xA005
  REG_A006_A007                             :array[0..1] of DWORD;                        // 0xA006
  DB_DEPTH_BOUNDS_MIN                       :TDB_DEPTH_BOUNDS_MIN;                        // 0xA008
  DB_DEPTH_BOUNDS_MAX                       :TDB_DEPTH_BOUNDS_MAX;                        // 0xA009
  DB_STENCIL_CLEAR                          :TDB_STENCIL_CLEAR;                           // 0xA00A
  DB_DEPTH_CLEAR                            :TDB_DEPTH_CLEAR;                             // 0xA00B
  PA_SC_SCREEN_SCISSOR_TL                   :TPA_SC_SCREEN_SCISSOR_TL;                    // 0xA00C
  PA_SC_SCREEN_SCISSOR_BR                   :TPA_SC_SCREEN_SCISSOR_BR;                    // 0xA00D
  REG_A00E                                  :DWORD;                                       // 0xA00E
  DB_DEPTH_INFO                             :TDB_DEPTH_INFO;                              // 0xA00F
  DB_Z_INFO                                 :TDB_Z_INFO;                                  // 0xA010
  DB_STENCIL_INFO                           :TDB_STENCIL_INFO;                            // 0xA011
  DB_Z_READ_BASE                            :TDB_Z_READ_BASE;                             // 0xA012
  DB_STENCIL_READ_BASE                      :TDB_STENCIL_READ_BASE;                       // 0xA013
  DB_Z_WRITE_BASE                           :TDB_Z_WRITE_BASE;                            // 0xA014
  DB_STENCIL_WRITE_BASE                     :TDB_STENCIL_WRITE_BASE;                      // 0xA015
  DB_DEPTH_SIZE                             :TDB_DEPTH_SIZE;                              // 0xA016
  DB_DEPTH_SLICE                            :TDB_DEPTH_SLICE;                             // 0xA017
  REG_A018_A01F                             :array[0..7] of DWORD;                        // 0xA018
  TA_BC_BASE_ADDR                           :TTA_BC_BASE_ADDR;                            // 0xA020
  TA_BC_BASE_ADDR_HI                        :TTA_BC_BASE_ADDR_HI;                         // 0xA021
  REG_A022_A079                             :array[0..87] of DWORD;                       // 0xA022
  COHER_DEST_BASE_HI_0                      :TCOHER_DEST_BASE_HI_0;                       // 0xA07A
  COHER_DEST_BASE_HI_1                      :TCOHER_DEST_BASE_HI_1;                       // 0xA07B
  COHER_DEST_BASE_HI_2                      :TCOHER_DEST_BASE_HI_2;                       // 0xA07C
  COHER_DEST_BASE_HI_3                      :TCOHER_DEST_BASE_HI_3;                       // 0xA07D
  COHER_DEST_BASE_2                         :TCOHER_DEST_BASE_2;                          // 0xA07E
  COHER_DEST_BASE_3                         :TCOHER_DEST_BASE_3;                          // 0xA07F
  PA_SC_WINDOW_OFFSET                       :TPA_SC_WINDOW_OFFSET;                        // 0xA080
  PA_SC_WINDOW_SCISSOR_TL                   :TPA_SC_WINDOW_SCISSOR_TL;                    // 0xA081
  PA_SC_WINDOW_SCISSOR_BR                   :TPA_SC_WINDOW_SCISSOR_BR;                    // 0xA082
  PA_SC_CLIPRECT_RULE                       :TPA_SC_CLIPRECT_RULE;                        // 0xA083
  PA_SC_CLIPRECT_0_TL                       :TPA_SC_CLIPRECT_0_TL;                        // 0xA084
  PA_SC_CLIPRECT_0_BR                       :TPA_SC_CLIPRECT_0_BR;                        // 0xA085
  PA_SC_CLIPRECT_1_TL                       :TPA_SC_CLIPRECT_1_TL;                        // 0xA086
  PA_SC_CLIPRECT_1_BR                       :TPA_SC_CLIPRECT_1_BR;                        // 0xA087
  PA_SC_CLIPRECT_2_TL                       :TPA_SC_CLIPRECT_2_TL;                        // 0xA088
  PA_SC_CLIPRECT_2_BR                       :TPA_SC_CLIPRECT_2_BR;                        // 0xA089
  PA_SC_CLIPRECT_3_TL                       :TPA_SC_CLIPRECT_3_TL;                        // 0xA08A
  PA_SC_CLIPRECT_3_BR                       :TPA_SC_CLIPRECT_3_BR;                        // 0xA08B
  PA_SC_EDGERULE                            :TPA_SC_EDGERULE;                             // 0xA08C
  PA_SU_HARDWARE_SCREEN_OFFSET              :TPA_SU_HARDWARE_SCREEN_OFFSET;               // 0xA08D
  CB_TARGET_MASK                            :TCB_TARGET_MASK;                             // 0xA08E
  CB_SHADER_MASK                            :TCB_SHADER_MASK;                             // 0xA08F
  PA_SC_GENERIC_SCISSOR                     :TVPORT_SCISSOR;                              // 0xA090
  COHER_DEST_BASE_0                         :TCOHER_DEST_BASE_0;                          // 0xA092
  COHER_DEST_BASE_1                         :TCOHER_DEST_BASE_1;                          // 0xA093
  PA_SC_VPORT_SCISSOR                       :array[0..15] of TVPORT_SCISSOR;              // 0xA094
  PA_SC_VPORT_ZMIN_MAX                      :array[0..15] of TVPORT_ZMIN_MAX;             // 0xA0B4
  PA_SC_RASTER_CONFIG                       :TPA_SC_RASTER_CONFIG;                        // 0xA0D4
  PA_SC_RASTER_CONFIG_1                     :TPA_SC_RASTER_CONFIG_1;                      // 0xA0D5
  REG_A0D6_A0D7                             :array[0..1] of DWORD;                        // 0xA0D6
  CP_PERFMON_CNTX_CNTL                      :TCP_PERFMON_CNTX_CNTL;                       // 0xA0D8
  CP_PIPEID                                 :TCP_PIPEID;                                  // 0xA0D9
  CP_VMID                                   :TCP_VMID;                                    // 0xA0DA
  REG_A0DB_A0FF                             :array[0..36] of DWORD;                       // 0xA0DB
  VGT_MAX_VTX_INDX                          :TVGT_MAX_VTX_INDX;                           // 0xA100
  VGT_MIN_VTX_INDX                          :TVGT_MIN_VTX_INDX;                           // 0xA101
  VGT_INDX_OFFSET                           :TVGT_INDX_OFFSET;                            // 0xA102
  VGT_MULTI_PRIM_IB_RESET_INDX              :TVGT_MULTI_PRIM_IB_RESET_INDX;               // 0xA103
  REG_A104                                  :DWORD;                                       // 0xA104
  CB_BLEND_RGBA                             :array[0..3] of Single;                       // 0xA105
  CB_DCC_CONTROL                            :TCB_DCC_CONTROL;                             // 0xA109
  REG_A10A                                  :DWORD;                                       // 0xA10A
  DB_STENCIL_CONTROL                        :TDB_STENCIL_CONTROL;                         // 0xA10B
  DB_STENCILREFMASK                         :TDB_STENCILREFMASK;                          // 0xA10C
  DB_STENCILREFMASK_BF                      :TDB_STENCILREFMASK_BF;                       // 0xA10D
  REG_A10E                                  :DWORD;                                       // 0xA10E
  PA_CL_VPORT_SCALE_OFFSET                  :array[0..15] of TVPORT_SCALE_OFFSET;         // 0xA10F
  PA_CL_UCP_0_X                             :TPA_CL_UCP_0_X;                              // 0xA16F
  PA_CL_UCP_0_Y                             :TPA_CL_UCP_0_Y;                              // 0xA170
  PA_CL_UCP_0_Z                             :TPA_CL_UCP_0_Z;                              // 0xA171
  PA_CL_UCP_0_W                             :TPA_CL_UCP_0_W;                              // 0xA172
  PA_CL_UCP_1_X                             :TPA_CL_UCP_1_X;                              // 0xA173
  PA_CL_UCP_1_Y                             :TPA_CL_UCP_1_Y;                              // 0xA174
  PA_CL_UCP_1_Z                             :TPA_CL_UCP_1_Z;                              // 0xA175
  PA_CL_UCP_1_W                             :TPA_CL_UCP_1_W;                              // 0xA176
  PA_CL_UCP_2_X                             :TPA_CL_UCP_2_X;                              // 0xA177
  PA_CL_UCP_2_Y                             :TPA_CL_UCP_2_Y;                              // 0xA178
  PA_CL_UCP_2_Z                             :TPA_CL_UCP_2_Z;                              // 0xA179
  PA_CL_UCP_2_W                             :TPA_CL_UCP_2_W;                              // 0xA17A
  PA_CL_UCP_3_X                             :TPA_CL_UCP_3_X;                              // 0xA17B
  PA_CL_UCP_3_Y                             :TPA_CL_UCP_3_Y;                              // 0xA17C
  PA_CL_UCP_3_Z                             :TPA_CL_UCP_3_Z;                              // 0xA17D
  PA_CL_UCP_3_W                             :TPA_CL_UCP_3_W;                              // 0xA17E
  PA_CL_UCP_4_X                             :TPA_CL_UCP_4_X;                              // 0xA17F
  PA_CL_UCP_4_Y                             :TPA_CL_UCP_4_Y;                              // 0xA180
  PA_CL_UCP_4_Z                             :TPA_CL_UCP_4_Z;                              // 0xA181
  PA_CL_UCP_4_W                             :TPA_CL_UCP_4_W;                              // 0xA182
  PA_CL_UCP_5_X                             :TPA_CL_UCP_5_X;                              // 0xA183
  PA_CL_UCP_5_Y                             :TPA_CL_UCP_5_Y;                              // 0xA184
  PA_CL_UCP_5_Z                             :TPA_CL_UCP_5_Z;                              // 0xA185
  PA_CL_UCP_5_W                             :TPA_CL_UCP_5_W;                              // 0xA186
  REG_A187_A190                             :array[0..9] of DWORD;                        // 0xA187
  SPI_PS_INPUT_CNTL                         :array[0..31] of TSPI_PS_INPUT_CNTL_0;        // 0xA191
  SPI_VS_OUT_CONFIG                         :TSPI_VS_OUT_CONFIG;                          // 0xA1B1
  REG_A1B2                                  :DWORD;                                       // 0xA1B2
  SPI_PS_INPUT_ENA                          :TSPI_PS_INPUT_ENA;                           // 0xA1B3
  SPI_PS_INPUT_ADDR                         :TSPI_PS_INPUT_ADDR;                          // 0xA1B4
  SPI_INTERP_CONTROL_0                      :TSPI_INTERP_CONTROL_0;                       // 0xA1B5
  SPI_PS_IN_CONTROL                         :TSPI_PS_IN_CONTROL;                          // 0xA1B6
  REG_A1B7                                  :DWORD;                                       // 0xA1B7
  SPI_BARYC_CNTL                            :TSPI_BARYC_CNTL;                             // 0xA1B8
  REG_A1B9                                  :DWORD;                                       // 0xA1B9
  SPI_TMPRING_SIZE                          :TSPI_TMPRING_SIZE;                           // 0xA1BA
  REG_A1BB_A1C2                             :array[0..7] of DWORD;                        // 0xA1BB
  SPI_SHADER_POS_FORMAT                     :TSPI_SHADER_POS_FORMAT;                      // 0xA1C3
  SPI_SHADER_Z_FORMAT                       :TSPI_SHADER_Z_FORMAT;                        // 0xA1C4
  SPI_SHADER_COL_FORMAT                     :TSPI_SHADER_COL_FORMAT;                      // 0xA1C5
  REG_A1C6_A1D4                             :array[0..14] of DWORD;                       // 0xA1C6
  SX_PS_DOWNCONVERT                         :TSX_PS_DOWNCONVERT;                          // 0xA1D5
  SX_BLEND_OPT_EPSILON                      :TSX_BLEND_OPT_EPSILON;                       // 0xA1D6
  SX_BLEND_OPT_CONTROL                      :TSX_BLEND_OPT_CONTROL;                       // 0xA1D7
  SX_MRT0_BLEND_OPT                         :TSX_MRT0_BLEND_OPT;                          // 0xA1D8
  SX_MRT1_BLEND_OPT                         :TSX_MRT1_BLEND_OPT;                          // 0xA1D9
  SX_MRT2_BLEND_OPT                         :TSX_MRT2_BLEND_OPT;                          // 0xA1DA
  SX_MRT3_BLEND_OPT                         :TSX_MRT3_BLEND_OPT;                          // 0xA1DB
  SX_MRT4_BLEND_OPT                         :TSX_MRT4_BLEND_OPT;                          // 0xA1DC
  SX_MRT5_BLEND_OPT                         :TSX_MRT5_BLEND_OPT;                          // 0xA1DD
  SX_MRT6_BLEND_OPT                         :TSX_MRT6_BLEND_OPT;                          // 0xA1DE
  SX_MRT7_BLEND_OPT                         :TSX_MRT7_BLEND_OPT;                          // 0xA1DF
  CB_BLEND_CONTROL                          :array[0..7] of TCB_BLEND0_CONTROL;           // 0xA1E0
  REG_A1E8_A1F2                             :array[0..10] of DWORD;                       // 0xA1E8
  CS_COPY_STATE                             :TCS_COPY_STATE;                              // 0xA1F3
  GFX_COPY_STATE                            :TGFX_COPY_STATE;                             // 0xA1F4
  PA_CL_POINT_X_RAD                         :TPA_CL_POINT_X_RAD;                          // 0xA1F5
  PA_CL_POINT_Y_RAD                         :TPA_CL_POINT_Y_RAD;                          // 0xA1F6
  PA_CL_POINT_SIZE                          :TPA_CL_POINT_SIZE;                           // 0xA1F7
  PA_CL_POINT_CULL_RAD                      :TPA_CL_POINT_CULL_RAD;                       // 0xA1F8
  VGT_DMA_BASE_HI                           :TVGT_DMA_BASE_HI;                            // 0xA1F9
  VGT_DMA_BASE                              :TVGT_DMA_BASE;                               // 0xA1FA
  REG_A1FB                                  :DWORD;                                       // 0xA1FB
  VGT_DRAW_INITIATOR                        :TVGT_DRAW_INITIATOR;                         // 0xA1FC
  VGT_IMMED_DATA                            :TVGT_IMMED_DATA;                             // 0xA1FD
  VGT_EVENT_ADDRESS_REG                     :TVGT_EVENT_ADDRESS_REG;                      // 0xA1FE
  REG_A1FF                                  :DWORD;                                       // 0xA1FF
  DB_DEPTH_CONTROL                          :TDB_DEPTH_CONTROL;                           // 0xA200
  DB_EQAA                                   :TDB_EQAA;                                    // 0xA201
  CB_COLOR_CONTROL                          :TCB_COLOR_CONTROL;                           // 0xA202
  DB_SHADER_CONTROL                         :TDB_SHADER_CONTROL;                          // 0xA203
  PA_CL_CLIP_CNTL                           :TPA_CL_CLIP_CNTL;                            // 0xA204
  PA_SU_SC_MODE_CNTL                        :TPA_SU_SC_MODE_CNTL;                         // 0xA205
  PA_CL_VTE_CNTL                            :TPA_CL_VTE_CNTL;                             // 0xA206
  PA_CL_VS_OUT_CNTL                         :TPA_CL_VS_OUT_CNTL;                          // 0xA207
  PA_CL_NANINF_CNTL                         :TPA_CL_NANINF_CNTL;                          // 0xA208
  PA_SU_LINE_STIPPLE_CNTL                   :TPA_SU_LINE_STIPPLE_CNTL;                    // 0xA209
  PA_SU_LINE_STIPPLE_SCALE                  :TPA_SU_LINE_STIPPLE_SCALE;                   // 0xA20A
  PA_SU_PRIM_FILTER_CNTL                    :TPA_SU_PRIM_FILTER_CNTL;                     // 0xA20B
  REG_A20C_A27F                             :array[0..115] of DWORD;                      // 0xA20C
  PA_SU_POINT_SIZE                          :TPA_SU_POINT_SIZE;                           // 0xA280
  PA_SU_POINT_MINMAX                        :TPA_SU_POINT_MINMAX;                         // 0xA281
  PA_SU_LINE_CNTL                           :TPA_SU_LINE_CNTL;                            // 0xA282
  PA_SC_LINE_STIPPLE                        :TPA_SC_LINE_STIPPLE;                         // 0xA283
  VGT_OUTPUT_PATH_CNTL                      :TVGT_OUTPUT_PATH_CNTL;                       // 0xA284
  VGT_HOS_CNTL                              :TVGT_HOS_CNTL;                               // 0xA285
  VGT_HOS_MAX_TESS_LEVEL                    :TVGT_HOS_MAX_TESS_LEVEL;                     // 0xA286
  VGT_HOS_MIN_TESS_LEVEL                    :TVGT_HOS_MIN_TESS_LEVEL;                     // 0xA287
  VGT_HOS_REUSE_DEPTH                       :TVGT_HOS_REUSE_DEPTH;                        // 0xA288
  VGT_GROUP_PRIM_TYPE                       :TVGT_GROUP_PRIM_TYPE;                        // 0xA289
  VGT_GROUP_FIRST_DECR                      :TVGT_GROUP_FIRST_DECR;                       // 0xA28A
  VGT_GROUP_DECR                            :TVGT_GROUP_DECR;                             // 0xA28B
  VGT_GROUP_VECT_0_CNTL                     :TVGT_GROUP_VECT_0_CNTL;                      // 0xA28C
  VGT_GROUP_VECT_1_CNTL                     :TVGT_GROUP_VECT_1_CNTL;                      // 0xA28D
  VGT_GROUP_VECT_0_FMT_CNTL                 :TVGT_GROUP_VECT_0_FMT_CNTL;                  // 0xA28E
  VGT_GROUP_VECT_1_FMT_CNTL                 :TVGT_GROUP_VECT_1_FMT_CNTL;                  // 0xA28F
  VGT_GS_MODE                               :TVGT_GS_MODE;                                // 0xA290
  VGT_GS_ONCHIP_CNTL                        :TVGT_GS_ONCHIP_CNTL;                         // 0xA291
  PA_SC_MODE_CNTL_0                         :TPA_SC_MODE_CNTL_0;                          // 0xA292
  PA_SC_MODE_CNTL_1                         :TPA_SC_MODE_CNTL_1;                          // 0xA293
  VGT_ENHANCE                               :TVGT_ENHANCE;                                // 0xA294
  VGT_GS_PER_ES                             :TVGT_GS_PER_ES;                              // 0xA295
  VGT_ES_PER_GS                             :TVGT_ES_PER_GS;                              // 0xA296
  VGT_GS_PER_VS                             :TVGT_GS_PER_VS;                              // 0xA297
  VGT_GSVS_RING_OFFSET_1                    :TVGT_GSVS_RING_OFFSET_1;                     // 0xA298
  VGT_GSVS_RING_OFFSET_2                    :TVGT_GSVS_RING_OFFSET_2;                     // 0xA299
  VGT_GSVS_RING_OFFSET_3                    :TVGT_GSVS_RING_OFFSET_3;                     // 0xA29A
  VGT_GS_OUT_PRIM_TYPE                      :TVGT_GS_OUT_PRIM_TYPE;                       // 0xA29B
  IA_ENHANCE                                :TIA_ENHANCE;                                 // 0xA29C
  VGT_DMA_SIZE                              :TVGT_DMA_SIZE;                               // 0xA29D
  VGT_DMA_MAX_SIZE                          :TVGT_DMA_MAX_SIZE;                           // 0xA29E
  VGT_DMA_INDEX_TYPE                        :TVGT_DMA_INDEX_TYPE;                         // 0xA29F
  WD_ENHANCE                                :TWD_ENHANCE;                                 // 0xA2A0
  VGT_PRIMITIVEID_EN                        :TVGT_PRIMITIVEID_EN;                         // 0xA2A1
  VGT_DMA_NUM_INSTANCES                     :TVGT_DMA_NUM_INSTANCES;                      // 0xA2A2
  VGT_PRIMITIVEID_RESET                     :TVGT_PRIMITIVEID_RESET;                      // 0xA2A3
  VGT_EVENT_INITIATOR                       :TVGT_EVENT_INITIATOR;                        // 0xA2A4
  VGT_MULTI_PRIM_IB_RESET_EN                :TVGT_MULTI_PRIM_IB_RESET_EN;                 // 0xA2A5
  REG_A2A6_A2A7                             :array[0..1] of DWORD;                        // 0xA2A6
  VGT_INSTANCE_STEP_RATE_0                  :TVGT_INSTANCE_STEP_RATE_0;                   // 0xA2A8
  VGT_INSTANCE_STEP_RATE_1                  :TVGT_INSTANCE_STEP_RATE_1;                   // 0xA2A9
  IA_MULTI_VGT_PARAM                        :TIA_MULTI_VGT_PARAM;                         // 0xA2AA
  VGT_ESGS_RING_ITEMSIZE                    :TVGT_ESGS_RING_ITEMSIZE;                     // 0xA2AB
  VGT_GSVS_RING_ITEMSIZE                    :TVGT_GSVS_RING_ITEMSIZE;                     // 0xA2AC
  VGT_REUSE_OFF                             :TVGT_REUSE_OFF;                              // 0xA2AD
  VGT_VTX_CNT_EN                            :TVGT_VTX_CNT_EN;                             // 0xA2AE
  DB_HTILE_SURFACE                          :TDB_HTILE_SURFACE;                           // 0xA2AF
  DB_SRESULTS_COMPARE_STATE0                :TDB_SRESULTS_COMPARE_STATE0;                 // 0xA2B0
  DB_SRESULTS_COMPARE_STATE1                :TDB_SRESULTS_COMPARE_STATE1;                 // 0xA2B1
  DB_PRELOAD_CONTROL                        :TDB_PRELOAD_CONTROL;                         // 0xA2B2
  REG_A2B3                                  :DWORD;                                       // 0xA2B3
  VGT_STRMOUT_BUFFER_SIZE_0                 :TVGT_STRMOUT_BUFFER_SIZE_0;                  // 0xA2B4
  VGT_STRMOUT_VTX_STRIDE_0                  :TVGT_STRMOUT_VTX_STRIDE_0;                   // 0xA2B5
  REG_A2B6                                  :DWORD;                                       // 0xA2B6
  VGT_STRMOUT_BUFFER_OFFSET_0               :TVGT_STRMOUT_BUFFER_OFFSET_0;                // 0xA2B7
  VGT_STRMOUT_BUFFER_SIZE_1                 :TVGT_STRMOUT_BUFFER_SIZE_1;                  // 0xA2B8
  VGT_STRMOUT_VTX_STRIDE_1                  :TVGT_STRMOUT_VTX_STRIDE_1;                   // 0xA2B9
  REG_A2BA                                  :DWORD;                                       // 0xA2BA
  VGT_STRMOUT_BUFFER_OFFSET_1               :TVGT_STRMOUT_BUFFER_OFFSET_1;                // 0xA2BB
  VGT_STRMOUT_BUFFER_SIZE_2                 :TVGT_STRMOUT_BUFFER_SIZE_2;                  // 0xA2BC
  VGT_STRMOUT_VTX_STRIDE_2                  :TVGT_STRMOUT_VTX_STRIDE_2;                   // 0xA2BD
  REG_A2BE                                  :DWORD;                                       // 0xA2BE
  VGT_STRMOUT_BUFFER_OFFSET_2               :TVGT_STRMOUT_BUFFER_OFFSET_2;                // 0xA2BF
  VGT_STRMOUT_BUFFER_SIZE_3                 :TVGT_STRMOUT_BUFFER_SIZE_3;                  // 0xA2C0
  VGT_STRMOUT_VTX_STRIDE_3                  :TVGT_STRMOUT_VTX_STRIDE_3;                   // 0xA2C1
  REG_A2C2                                  :DWORD;                                       // 0xA2C2
  VGT_STRMOUT_BUFFER_OFFSET_3               :TVGT_STRMOUT_BUFFER_OFFSET_3;                // 0xA2C3
  REG_A2C4_A2C9                             :array[0..5] of DWORD;                        // 0xA2C4
  VGT_STRMOUT_DRAW_OPAQUE_OFFSET            :TVGT_STRMOUT_DRAW_OPAQUE_OFFSET;             // 0xA2CA
  VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE:TVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE; // 0xA2CB
  VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE     :TVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE;      // 0xA2CC
  REG_A2CD                                  :DWORD;                                       // 0xA2CD
  VGT_GS_MAX_VERT_OUT                       :TVGT_GS_MAX_VERT_OUT;                        // 0xA2CE
  REG_A2CF_A2D3                             :array[0..4] of DWORD;                        // 0xA2CF
  VGT_TESS_DISTRIBUTION                     :TVGT_TESS_DISTRIBUTION;                      // 0xA2D4
  VGT_SHADER_STAGES_EN                      :TVGT_SHADER_STAGES_EN;                       // 0xA2D5
  VGT_LS_HS_CONFIG                          :TVGT_LS_HS_CONFIG;                           // 0xA2D6
  VGT_GS_VERT_ITEMSIZE                      :TVGT_GS_VERT_ITEMSIZE;                       // 0xA2D7
  VGT_GS_VERT_ITEMSIZE_1                    :TVGT_GS_VERT_ITEMSIZE_1;                     // 0xA2D8
  VGT_GS_VERT_ITEMSIZE_2                    :TVGT_GS_VERT_ITEMSIZE_2;                     // 0xA2D9
  VGT_GS_VERT_ITEMSIZE_3                    :TVGT_GS_VERT_ITEMSIZE_3;                     // 0xA2DA
  VGT_TF_PARAM                              :TVGT_TF_PARAM;                               // 0xA2DB
  DB_ALPHA_TO_MASK                          :TDB_ALPHA_TO_MASK;                           // 0xA2DC
  VGT_DISPATCH_DRAW_INDEX                   :TVGT_DISPATCH_DRAW_INDEX;                    // 0xA2DD
  PA_SU_POLY_OFFSET_DB_FMT_CNTL             :TPA_SU_POLY_OFFSET_DB_FMT_CNTL;              // 0xA2DE
  PA_SU_POLY_OFFSET_CLAMP                   :TPA_SU_POLY_OFFSET_CLAMP;                    // 0xA2DF
  PA_SU_POLY_OFFSET_FRONT_SCALE             :TPA_SU_POLY_OFFSET_FRONT_SCALE;              // 0xA2E0
  PA_SU_POLY_OFFSET_FRONT_OFFSET            :TPA_SU_POLY_OFFSET_FRONT_OFFSET;             // 0xA2E1
  PA_SU_POLY_OFFSET_BACK_SCALE              :TPA_SU_POLY_OFFSET_BACK_SCALE;               // 0xA2E2
  PA_SU_POLY_OFFSET_BACK_OFFSET             :TPA_SU_POLY_OFFSET_BACK_OFFSET;              // 0xA2E3
  VGT_GS_INSTANCE_CNT                       :TVGT_GS_INSTANCE_CNT;                        // 0xA2E4
  VGT_STRMOUT_CONFIG                        :TVGT_STRMOUT_CONFIG;                         // 0xA2E5
  VGT_STRMOUT_BUFFER_CONFIG                 :TVGT_STRMOUT_BUFFER_CONFIG;                  // 0xA2E6
  REG_A2E7_A2F4                             :array[0..13] of DWORD;                       // 0xA2E7
  PA_SC_CENTROID_PRIORITY_0                 :TPA_SC_CENTROID_PRIORITY_0;                  // 0xA2F5
  PA_SC_CENTROID_PRIORITY_1                 :TPA_SC_CENTROID_PRIORITY_1;                  // 0xA2F6
  PA_SC_LINE_CNTL                           :TPA_SC_LINE_CNTL;                            // 0xA2F7
  PA_SC_AA_CONFIG                           :TPA_SC_AA_CONFIG;                            // 0xA2F8
  PA_SU_VTX_CNTL                            :TPA_SU_VTX_CNTL;                             // 0xA2F9
  GB_CLIP                                   :TGB_CLIP;                                    // 0xA2FA
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0;          // 0xA2FE
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1;          // 0xA2FF
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2;          // 0xA300
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3;          // 0xA301
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0;          // 0xA302
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1;          // 0xA303
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2;          // 0xA304
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3;          // 0xA305
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0;          // 0xA306
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1;          // 0xA307
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2;          // 0xA308
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3;          // 0xA309
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0;          // 0xA30A
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1;          // 0xA30B
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2;          // 0xA30C
  PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3         :TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3;          // 0xA30D
  PA_SC_AA_MASK_X0Y0_X1Y0                   :TPA_SC_AA_MASK_X0Y0_X1Y0;                    // 0xA30E
  PA_SC_AA_MASK_X0Y1_X1Y1                   :TPA_SC_AA_MASK_X0Y1_X1Y1;                    // 0xA30F
  REG_A310_A315                             :array[0..5] of DWORD;                        // 0xA310
  VGT_VERTEX_REUSE_BLOCK_CNTL               :TVGT_VERTEX_REUSE_BLOCK_CNTL;                // 0xA316
  VGT_OUT_DEALLOC_CNTL                      :TVGT_OUT_DEALLOC_CNTL;                       // 0xA317
  RENDER_TARGET                             :array[0..7] of TRENDER_TARGET;               // 0xA318
 end;

 TCONFIG_SPACE_GROUP=bitpacked record
  GRBM_CNTL                                              :TGRBM_CNTL;                                        // 0x2000
  GRBM_SKEW_CNTL                                         :TGRBM_SKEW_CNTL;                                   // 0x2001
  GRBM_STATUS2                                           :TGRBM_STATUS2;                                     // 0x2002
  GRBM_PWR_CNTL                                          :TGRBM_PWR_CNTL;                                    // 0x2003
  GRBM_STATUS                                            :TGRBM_STATUS;                                      // 0x2004
  GRBM_STATUS_SE0                                        :TGRBM_STATUS_SE0;                                  // 0x2005
  GRBM_STATUS_SE1                                        :TGRBM_STATUS_SE1;                                  // 0x2006
  REG_2007                                               :DWORD;                                             // 0x2007
  GRBM_SOFT_RESET                                        :TGRBM_SOFT_RESET;                                  // 0x2008
  GRBM_DEBUG_CNTL                                        :TGRBM_DEBUG_CNTL;                                  // 0x2009
  GRBM_DEBUG_DATA                                        :TGRBM_DEBUG_DATA;                                  // 0x200A
  REG_200B                                               :DWORD;                                             // 0x200B
  GRBM_GFX_CLKEN_CNTL                                    :TGRBM_GFX_CLKEN_CNTL;                              // 0x200C
  GRBM_WAIT_IDLE_CLOCKS                                  :TGRBM_WAIT_IDLE_CLOCKS;                            // 0x200D
  GRBM_STATUS_SE2                                        :TGRBM_STATUS_SE2;                                  // 0x200E
  GRBM_STATUS_SE3                                        :TGRBM_STATUS_SE3;                                  // 0x200F
  REG_2010_2013                                          :array[0..3] of DWORD;                              // 0x2010
  GRBM_DEBUG                                             :TGRBM_DEBUG;                                       // 0x2014
  GRBM_DEBUG_SNAPSHOT                                    :TGRBM_DEBUG_SNAPSHOT;                              // 0x2015
  GRBM_READ_ERROR                                        :TGRBM_READ_ERROR;                                  // 0x2016
  GRBM_READ_ERROR2                                       :TGRBM_READ_ERROR2;                                 // 0x2017
  GRBM_INT_CNTL                                          :TGRBM_INT_CNTL;                                    // 0x2018
  GRBM_TRAP_OP                                           :TGRBM_TRAP_OP;                                     // 0x2019
  GRBM_TRAP_ADDR                                         :TGRBM_TRAP_ADDR;                                   // 0x201A
  GRBM_TRAP_ADDR_MSK                                     :TGRBM_TRAP_ADDR_MSK;                               // 0x201B
  GRBM_TRAP_WD                                           :TGRBM_TRAP_WD;                                     // 0x201C
  GRBM_TRAP_WD_MSK                                       :TGRBM_TRAP_WD_MSK;                                 // 0x201D
  GRBM_DSM_BYPASS                                        :TGRBM_DSM_BYPASS;                                  // 0x201E
  GRBM_WRITE_ERROR                                       :TGRBM_WRITE_ERROR;                                 // 0x201F
  REG_2020_203B                                          :array[0..27] of DWORD;                             // 0x2020
  DEBUG_INDEX                                            :TDEBUG_INDEX;                                      // 0x203C
  DEBUG_DATA                                             :TDEBUG_DATA;                                       // 0x203D
  REG_203E                                               :DWORD;                                             // 0x203E
  GRBM_NOWHERE                                           :TGRBM_NOWHERE;                                     // 0x203F
  GRBM_SCRATCH_REG0                                      :TGRBM_SCRATCH_REG0;                                // 0x2040
  GRBM_SCRATCH_REG1                                      :TGRBM_SCRATCH_REG1;                                // 0x2041
  GRBM_SCRATCH_REG2                                      :TGRBM_SCRATCH_REG2;                                // 0x2042
  GRBM_SCRATCH_REG3                                      :TGRBM_SCRATCH_REG3;                                // 0x2043
  GRBM_SCRATCH_REG4                                      :TGRBM_SCRATCH_REG4;                                // 0x2044
  GRBM_SCRATCH_REG5                                      :TGRBM_SCRATCH_REG5;                                // 0x2045
  GRBM_SCRATCH_REG6                                      :TGRBM_SCRATCH_REG6;                                // 0x2046
  GRBM_SCRATCH_REG7                                      :TGRBM_SCRATCH_REG7;                                // 0x2047
  REG_2048_2083                                          :array[0..59] of DWORD;                             // 0x2048
  CP_CPC_STATUS                                          :TCP_CPC_STATUS;                                    // 0x2084
  CP_CPC_BUSY_STAT                                       :TCP_CPC_BUSY_STAT;                                 // 0x2085
  CP_CPC_STALLED_STAT1                                   :TCP_CPC_STALLED_STAT1;                             // 0x2086
  CP_CPF_STATUS                                          :TCP_CPF_STATUS;                                    // 0x2087
  CP_CPF_BUSY_STAT                                       :TCP_CPF_BUSY_STAT;                                 // 0x2088
  CP_CPF_STALLED_STAT1                                   :TCP_CPF_STALLED_STAT1;                             // 0x2089
  REG_208A                                               :DWORD;                                             // 0x208A
  CP_CPC_GRBM_FREE_COUNT                                 :TCP_CPC_GRBM_FREE_COUNT;                           // 0x208B
  REG_208C                                               :DWORD;                                             // 0x208C
  CP_MEC_CNTL                                            :TCP_MEC_CNTL;                                      // 0x208D
  CP_MEC_ME1_HEADER_DUMP                                 :TCP_MEC_ME1_HEADER_DUMP;                           // 0x208E
  CP_MEC_ME2_HEADER_DUMP                                 :TCP_MEC_ME2_HEADER_DUMP;                           // 0x208F
  CP_CPC_SCRATCH_INDEX                                   :TCP_CPC_SCRATCH_INDEX;                             // 0x2090
  CP_CPC_SCRATCH_DATA                                    :TCP_CPC_SCRATCH_DATA;                              // 0x2091
  REG_2092_20A6                                          :array[0..20] of DWORD;                             // 0x2092
  CP_CPC_HALT_HYST_COUNT                                 :TCP_CPC_HALT_HYST_COUNT;                           // 0x20A7
  REG_20A8_20AC                                          :array[0..4] of DWORD;                              // 0x20A8
  CP_PRT_LOD_STATS_CNTL0                                 :TCP_PRT_LOD_STATS_CNTL0;                           // 0x20AD
  CP_PRT_LOD_STATS_CNTL1                                 :TCP_PRT_LOD_STATS_CNTL1;                           // 0x20AE
  CP_PRT_LOD_STATS_CNTL2                                 :TCP_PRT_LOD_STATS_CNTL2;                           // 0x20AF
  REG_20B0_20BF                                          :array[0..15] of DWORD;                             // 0x20B0
  CP_CE_COMPARE_COUNT                                    :TCP_CE_COMPARE_COUNT;                              // 0x20C0
  CP_CE_DE_COUNT                                         :TCP_CE_DE_COUNT;                                   // 0x20C1
  CP_DE_CE_COUNT                                         :TCP_DE_CE_COUNT;                                   // 0x20C2
  CP_DE_LAST_INVAL_COUNT                                 :TCP_DE_LAST_INVAL_COUNT;                           // 0x20C3
  CP_DE_DE_COUNT                                         :TCP_DE_DE_COUNT;                                   // 0x20C4
  REG_20C5_219B                                          :array[0..214] of DWORD;                            // 0x20C5
  CP_STALLED_STAT3                                       :TCP_STALLED_STAT3;                                 // 0x219C
  CP_STALLED_STAT1                                       :TCP_STALLED_STAT1;                                 // 0x219D
  CP_STALLED_STAT2                                       :TCP_STALLED_STAT2;                                 // 0x219E
  CP_BUSY_STAT                                           :TCP_BUSY_STAT;                                     // 0x219F
  CP_STAT                                                :TCP_STAT;                                          // 0x21A0
  CP_ME_HEADER_DUMP                                      :TCP_ME_HEADER_DUMP;                                // 0x21A1
  CP_PFP_HEADER_DUMP                                     :TCP_PFP_HEADER_DUMP;                               // 0x21A2
  CP_GRBM_FREE_COUNT                                     :TCP_GRBM_FREE_COUNT;                               // 0x21A3
  CP_CE_HEADER_DUMP                                      :TCP_CE_HEADER_DUMP;                                // 0x21A4
  REG_21A5_21B3                                          :array[0..14] of DWORD;                             // 0x21A5
  CP_CSF_STAT                                            :TCP_CSF_STAT;                                      // 0x21B4
  CP_CSF_CNTL                                            :TCP_CSF_CNTL;                                      // 0x21B5
  CP_ME_CNTL                                             :TCP_ME_CNTL;                                       // 0x21B6
  REG_21B7                                               :DWORD;                                             // 0x21B7
  CP_CNTX_STAT                                           :TCP_CNTX_STAT;                                     // 0x21B8
  CP_ME_PREEMPTION                                       :TCP_ME_PREEMPTION;                                 // 0x21B9
  REG_21BA_21BB                                          :array[0..1] of DWORD;                              // 0x21BA
  CP_ROQ_THRESHOLDS                                      :TCP_ROQ_THRESHOLDS;                                // 0x21BC
  CP_MEQ_STQ_THRESHOLD                                   :TCP_MEQ_STQ_THRESHOLD;                             // 0x21BD
  CP_RB2_RPTR                                            :TCP_RB2_RPTR;                                      // 0x21BE
  CP_RB1_RPTR                                            :TCP_RB1_RPTR;                                      // 0x21BF
  CP_RB0_RPTR                                            :TCP_RB0_RPTR;                                      // 0x21C0
  CP_RB_WPTR_DELAY                                       :TCP_RB_WPTR_DELAY;                                 // 0x21C1
  CP_RB_WPTR_POLL_CNTL                                   :TCP_RB_WPTR_POLL_CNTL;                             // 0x21C2
  REG_21C3_21D4                                          :array[0..17] of DWORD;                             // 0x21C3
  CP_ROQ1_THRESHOLDS                                     :TCP_ROQ1_THRESHOLDS;                               // 0x21D5
  CP_ROQ2_THRESHOLDS                                     :TCP_ROQ2_THRESHOLDS;                               // 0x21D6
  CP_STQ_THRESHOLDS                                      :TCP_STQ_THRESHOLDS;                                // 0x21D7
  CP_QUEUE_THRESHOLDS                                    :TCP_QUEUE_THRESHOLDS;                              // 0x21D8
  CP_MEQ_THRESHOLDS                                      :TCP_MEQ_THRESHOLDS;                                // 0x21D9
  CP_ROQ_AVAIL                                           :TCP_ROQ_AVAIL;                                     // 0x21DA
  CP_STQ_AVAIL                                           :TCP_STQ_AVAIL;                                     // 0x21DB
  CP_ROQ2_AVAIL                                          :TCP_ROQ2_AVAIL;                                    // 0x21DC
  CP_MEQ_AVAIL                                           :TCP_MEQ_AVAIL;                                     // 0x21DD
  CP_CMD_INDEX                                           :TCP_CMD_INDEX;                                     // 0x21DE
  CP_CMD_DATA                                            :TCP_CMD_DATA;                                      // 0x21DF
  CP_ROQ_RB_STAT                                         :TCP_ROQ_RB_STAT;                                   // 0x21E0
  CP_ROQ_IB1_STAT                                        :TCP_ROQ_IB1_STAT;                                  // 0x21E1
  CP_ROQ_IB2_STAT                                        :TCP_ROQ_IB2_STAT;                                  // 0x21E2
  CP_STQ_STAT                                            :TCP_STQ_STAT;                                      // 0x21E3
  CP_STQ_WR_STAT                                         :TCP_STQ_WR_STAT;                                   // 0x21E4
  CP_MEQ_STAT                                            :TCP_MEQ_STAT;                                      // 0x21E5
  CP_CEQ1_AVAIL                                          :TCP_CEQ1_AVAIL;                                    // 0x21E6
  CP_CEQ2_AVAIL                                          :TCP_CEQ2_AVAIL;                                    // 0x21E7
  CP_CE_ROQ_RB_STAT                                      :TCP_CE_ROQ_RB_STAT;                                // 0x21E8
  CP_CE_ROQ_IB1_STAT                                     :TCP_CE_ROQ_IB1_STAT;                               // 0x21E9
  CP_CE_ROQ_IB2_STAT                                     :TCP_CE_ROQ_IB2_STAT;                               // 0x21EA
  REG_21EB_21F6                                          :array[0..11] of DWORD;                             // 0x21EB
  CP_INT_STAT_DEBUG                                      :TCP_INT_STAT_DEBUG;                                // 0x21F7
  REG_21F8_21FB                                          :array[0..3] of DWORD;                              // 0x21F8
  CP_PERFCOUNTER_SELECT                                  :TCP_PERFCOUNTER_SELECT;                            // 0x21FC
  CP_PERFCOUNTER_LO                                      :TCP_PERFCOUNTER_LO;                                // 0x21FD
  CP_PERFCOUNTER_HI                                      :TCP_PERFCOUNTER_HI;                                // 0x21FE
  REG_21FF_222B                                          :array[0..44] of DWORD;                             // 0x21FF
  VGT_VTX_VECT_EJECT_REG                                 :TVGT_VTX_VECT_EJECT_REG;                           // 0x222C
  VGT_DMA_DATA_FIFO_DEPTH                                :TVGT_DMA_DATA_FIFO_DEPTH;                          // 0x222D
  VGT_DMA_REQ_FIFO_DEPTH                                 :TVGT_DMA_REQ_FIFO_DEPTH;                           // 0x222E
  VGT_DRAW_INIT_FIFO_DEPTH                               :TVGT_DRAW_INIT_FIFO_DEPTH;                         // 0x222F
  VGT_LAST_COPY_STATE                                    :TVGT_LAST_COPY_STATE;                              // 0x2230
  VGT_CACHE_INVALIDATION                                 :TVGT_CACHE_INVALIDATION;                           // 0x2231
  VGT_RESET_DEBUG                                        :TVGT_RESET_DEBUG;                                  // 0x2232
  VGT_STRMOUT_DELAY                                      :TVGT_STRMOUT_DELAY;                                // 0x2233
  VGT_FIFO_DEPTHS                                        :TVGT_FIFO_DEPTHS;                                  // 0x2234
  VGT_GS_VERTEX_REUSE                                    :TVGT_GS_VERTEX_REUSE;                              // 0x2235
  VGT_MC_LAT_CNTL                                        :TVGT_MC_LAT_CNTL;                                  // 0x2236
  IA_CNTL_STATUS                                         :TIA_CNTL_STATUS;                                   // 0x2237
  VGT_DEBUG_CNTL                                         :TVGT_DEBUG_CNTL;                                   // 0x2238
  VGT_DEBUG_DATA                                         :TVGT_DEBUG_DATA;                                   // 0x2239
  IA_DEBUG_CNTL                                          :TIA_DEBUG_CNTL;                                    // 0x223A
  IA_DEBUG_DATA                                          :TIA_DEBUG_DATA;                                    // 0x223B
  VGT_CNTL_STATUS                                        :TVGT_CNTL_STATUS;                                  // 0x223C
  WD_DEBUG_CNTL                                          :TWD_DEBUG_CNTL;                                    // 0x223D
  WD_DEBUG_DATA                                          :TWD_DEBUG_DATA;                                    // 0x223E
  WD_CNTL_STATUS                                         :TWD_CNTL_STATUS;                                   // 0x223F
  CC_GC_PRIM_CONFIG                                      :TCC_GC_PRIM_CONFIG;                                // 0x2240
  GC_USER_PRIM_CONFIG                                    :TGC_USER_PRIM_CONFIG;                              // 0x2241
  WD_QOS                                                 :TWD_QOS;                                           // 0x2242
  REG_2243_225E                                          :array[0..27] of DWORD;                             // 0x2243
  CGTT_VGT_CLK_CTRL                                      :TCGTT_VGT_CLK_CTRL;                                // 0x225F
  REG_2260                                               :DWORD;                                             // 0x2260
  CGTT_IA_CLK_CTRL                                       :TCGTT_IA_CLK_CTRL;                                 // 0x2261
  REG_2262                                               :DWORD;                                             // 0x2262
  VGT_SYS_CONFIG                                         :TVGT_SYS_CONFIG;                                   // 0x2263
  REG_2264_2267                                          :array[0..3] of DWORD;                              // 0x2264
  VGT_VS_MAX_WAVE_ID                                     :TVGT_VS_MAX_WAVE_ID;                               // 0x2268
  REG_2269_226C                                          :array[0..3] of DWORD;                              // 0x2269
  GFX_PIPE_CONTROL                                       :TGFX_PIPE_CONTROL;                                 // 0x226D
  REG_226E                                               :DWORD;                                             // 0x226E
  CC_GC_SHADER_ARRAY_CONFIG                              :TCC_GC_SHADER_ARRAY_CONFIG;                        // 0x226F
  GC_USER_SHADER_ARRAY_CONFIG                            :TGC_USER_SHADER_ARRAY_CONFIG;                      // 0x2270
  VGT_DMA_PRIMITIVE_TYPE                                 :TVGT_DMA_PRIMITIVE_TYPE;                           // 0x2271
  VGT_DMA_CONTROL                                        :TVGT_DMA_CONTROL;                                  // 0x2272
  VGT_DMA_LS_HS_CONFIG                                   :TVGT_DMA_LS_HS_CONFIG;                             // 0x2273
  REG_2274_227F                                          :array[0..11] of DWORD;                             // 0x2274
  PA_SU_DEBUG_CNTL                                       :TPA_SU_DEBUG_CNTL;                                 // 0x2280
  PA_SU_DEBUG_DATA                                       :TPA_SU_DEBUG_DATA;                                 // 0x2281
  REG_2282_2283                                          :array[0..1] of DWORD;                              // 0x2282
  PA_CL_CNTL_STATUS                                      :TPA_CL_CNTL_STATUS;                                // 0x2284
  PA_CL_ENHANCE                                          :TPA_CL_ENHANCE;                                    // 0x2285
  PA_CL_RESET_DEBUG                                      :TPA_CL_RESET_DEBUG;                                // 0x2286
  REG_2287_2293                                          :array[0..12] of DWORD;                             // 0x2287
  PA_SU_CNTL_STATUS                                      :TPA_SU_CNTL_STATUS;                                // 0x2294
  PA_SC_FIFO_DEPTH_CNTL                                  :TPA_SC_FIFO_DEPTH_CNTL;                            // 0x2295
  REG_2296_22BF                                          :array[0..41] of DWORD;                             // 0x2296
  PA_SC_P3D_TRAP_SCREEN_HV_LOCK                          :TPA_SC_P3D_TRAP_SCREEN_HV_LOCK;                    // 0x22C0
  PA_SC_HP3D_TRAP_SCREEN_HV_LOCK                         :TPA_SC_HP3D_TRAP_SCREEN_HV_LOCK;                   // 0x22C1
  PA_SC_TRAP_SCREEN_HV_LOCK                              :TPA_SC_TRAP_SCREEN_HV_LOCK;                        // 0x22C2
  REG_22C3_22C8                                          :array[0..5] of DWORD;                              // 0x22C3
  PA_SC_FORCE_EOV_MAX_CNTS                               :TPA_SC_FORCE_EOV_MAX_CNTS;                         // 0x22C9
  CGTT_SC_CLK_CTRL                                       :TCGTT_SC_CLK_CTRL;                                 // 0x22CA
  REG_22CB_22F2                                          :array[0..39] of DWORD;                             // 0x22CB
  PA_SC_FIFO_SIZE                                        :TPA_SC_FIFO_SIZE;                                  // 0x22F3
  REG_22F4                                               :DWORD;                                             // 0x22F4
  PA_SC_IF_FIFO_SIZE                                     :TPA_SC_IF_FIFO_SIZE;                               // 0x22F5
  PA_SC_DEBUG_CNTL                                       :TPA_SC_DEBUG_CNTL;                                 // 0x22F6
  PA_SC_DEBUG_DATA                                       :TPA_SC_DEBUG_DATA;                                 // 0x22F7
  REG_22F8_22FB                                          :array[0..3] of DWORD;                              // 0x22F8
  PA_SC_ENHANCE                                          :TPA_SC_ENHANCE;                                    // 0x22FC
  REG_22FD_22FF                                          :array[0..2] of DWORD;                              // 0x22FD
  SQ_CONFIG                                              :TSQ_CONFIG;                                        // 0x2300
  SQC_CONFIG                                             :TSQC_CONFIG;                                       // 0x2301
  REG_2302                                               :DWORD;                                             // 0x2302
  SQ_RANDOM_WAVE_PRI                                     :TSQ_RANDOM_WAVE_PRI;                               // 0x2303
  SQ_REG_CREDITS                                         :TSQ_REG_CREDITS;                                   // 0x2304
  SQ_FIFO_SIZES                                          :TSQ_FIFO_SIZES;                                    // 0x2305
  SQ_DSM_CNTL                                            :TSQ_DSM_CNTL;                                      // 0x2306
  CC_SQC_BANK_DISABLE                                    :TCC_SQC_BANK_DISABLE;                              // 0x2307
  USER_SQC_BANK_DISABLE                                  :TUSER_SQC_BANK_DISABLE;                            // 0x2308
  SQ_DEBUG_STS_GLOBAL                                    :TSQ_DEBUG_STS_GLOBAL;                              // 0x2309
  SH_MEM_BASES                                           :TSH_MEM_BASES;                                     // 0x230A
  SH_MEM_APE1_BASE                                       :TSH_MEM_APE1_BASE;                                 // 0x230B
  SH_MEM_APE1_LIMIT                                      :TSH_MEM_APE1_LIMIT;                                // 0x230C
  SH_MEM_CONFIG                                          :TSH_MEM_CONFIG;                                    // 0x230D
  REG_230E                                               :DWORD;                                             // 0x230E
  SQC_DSM_CNTL                                           :TSQC_DSM_CNTL;                                     // 0x230F
  SQ_DEBUG_STS_GLOBAL2                                   :TSQ_DEBUG_STS_GLOBAL2;                             // 0x2310
  SQ_DEBUG_STS_GLOBAL3                                   :TSQ_DEBUG_STS_GLOBAL3;                             // 0x2311
  CC_GC_SHADER_RATE_CONFIG                               :TCC_GC_SHADER_RATE_CONFIG;                         // 0x2312
  GC_USER_SHADER_RATE_CONFIG                             :TGC_USER_SHADER_RATE_CONFIG;                       // 0x2313
  SQ_INTERRUPT_AUTO_MASK                                 :TSQ_INTERRUPT_AUTO_MASK;                           // 0x2314
  SQ_INTERRUPT_MSG_CTRL                                  :TSQ_INTERRUPT_MSG_CTRL;                            // 0x2315
  REG_2316_235F                                          :array[0..73] of DWORD;                             // 0x2316
  SQ_ALU_CLK_CTRL                                        :TSQ_ALU_CLK_CTRL;                                  // 0x2360
  SQ_TEX_CLK_CTRL                                        :TSQ_TEX_CLK_CTRL;                                  // 0x2361
  CGTT_SQ_CLK_CTRL                                       :TCGTT_SQ_CLK_CTRL;                                 // 0x2362
  CGTT_SQG_CLK_CTRL                                      :TCGTT_SQG_CLK_CTRL;                                // 0x2363
  REG_2364_2373                                          :array[0..15] of DWORD;                             // 0x2364
  SQ_REG_TIMESTAMP                                       :TSQ_REG_TIMESTAMP;                                 // 0x2374
  SQ_CMD_TIMESTAMP                                       :TSQ_CMD_TIMESTAMP;                                 // 0x2375
  REG_2376_2377                                          :array[0..1] of DWORD;                              // 0x2376
  SQ_IND_INDEX                                           :TSQ_IND_INDEX;                                     // 0x2378
  SQ_IND_DATA                                            :TSQ_IND_DATA;                                      // 0x2379
  REG_237A                                               :DWORD;                                             // 0x237A
  SQ_CMD                                                 :TSQ_CMD;                                           // 0x237B
  SQ_TIME_HI                                             :TSQ_TIME_HI;                                       // 0x237C
  SQ_TIME_LO                                             :TSQ_TIME_LO;                                       // 0x237D
  REG_237E                                               :DWORD;                                             // 0x237E
  SQ_DS_0                                                :TSQ_DS_0;                                          // 0x237F
  REG_2380_238F                                          :array[0..15] of DWORD;                             // 0x2380
  SQ_THREAD_TRACE_CNTR                                   :TSQ_THREAD_TRACE_CNTR;                             // 0x2390
  REG_2391_2395                                          :array[0..4] of DWORD;                              // 0x2391
  SQ_POWER_THROTTLE                                      :TSQ_POWER_THROTTLE;                                // 0x2396
  SQ_POWER_THROTTLE2                                     :TSQ_POWER_THROTTLE2;                               // 0x2397
  SQ_LB_CTR_CTRL                                         :TSQ_LB_CTR_CTRL;                                   // 0x2398
  SQ_LB_DATA_ALU_CYCLES                                  :TSQ_LB_DATA_ALU_CYCLES;                            // 0x2399
  SQ_LB_DATA_TEX_CYCLES                                  :TSQ_LB_DATA_TEX_CYCLES;                            // 0x239A
  SQ_LB_DATA_ALU_STALLS                                  :TSQ_LB_DATA_ALU_STALLS;                            // 0x239B
  SQ_LB_DATA_TEX_STALLS                                  :TSQ_LB_DATA_TEX_STALLS;                            // 0x239C
  REG_239D_239F                                          :array[0..2] of DWORD;                              // 0x239D
  SQC_EDC_CNT                                            :TSQC_EDC_CNT;                                      // 0x23A0
  SQ_EDC_SEC_CNT                                         :TSQ_EDC_SEC_CNT;                                   // 0x23A1
  SQ_EDC_DED_CNT                                         :TSQ_EDC_DED_CNT;                                   // 0x23A2
  SQ_EDC_INFO                                            :TSQ_EDC_INFO;                                      // 0x23A3
  REG_23A4_23AF                                          :array[0..11] of DWORD;                             // 0x23A4
  SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2                     :TSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2;               // 0x23B0
  SQ_WREXEC_EXEC_HI                                      :TSQ_WREXEC_EXEC_HI;                                // 0x23B1
  SQC_GATCL1_CNTL                                        :TSQC_GATCL1_CNTL;                                  // 0x23B2
  SQC_ATC_EDC_GATCL1_CNT                                 :TSQC_ATC_EDC_GATCL1_CNT;                           // 0x23B3
  REG_23B4_23BF                                          :array[0..11] of DWORD;                             // 0x23B4
  SQ_BUF_RSRC_WORD0                                      :TSQ_BUF_RSRC_WORD0;                                // 0x23C0
  SQ_BUF_RSRC_WORD1                                      :TSQ_BUF_RSRC_WORD1;                                // 0x23C1
  SQ_BUF_RSRC_WORD2                                      :TSQ_BUF_RSRC_WORD2;                                // 0x23C2
  SQ_BUF_RSRC_WORD3                                      :TSQ_BUF_RSRC_WORD3;                                // 0x23C3
  SQ_IMG_RSRC_WORD0                                      :TSQ_IMG_RSRC_WORD0;                                // 0x23C4
  SQ_IMG_RSRC_WORD1                                      :TSQ_IMG_RSRC_WORD1;                                // 0x23C5
  SQ_IMG_RSRC_WORD2                                      :TSQ_IMG_RSRC_WORD2;                                // 0x23C6
  SQ_IMG_RSRC_WORD3                                      :TSQ_IMG_RSRC_WORD3;                                // 0x23C7
  SQ_IMG_RSRC_WORD4                                      :TSQ_IMG_RSRC_WORD4;                                // 0x23C8
  SQ_IMG_RSRC_WORD5                                      :TSQ_IMG_RSRC_WORD5;                                // 0x23C9
  SQ_IMG_RSRC_WORD6                                      :TSQ_IMG_RSRC_WORD6;                                // 0x23CA
  SQ_IMG_RSRC_WORD7                                      :TSQ_IMG_RSRC_WORD7;                                // 0x23CB
  SQ_IMG_SAMP_WORD0                                      :TSQ_IMG_SAMP_WORD0;                                // 0x23CC
  SQ_IMG_SAMP_WORD1                                      :TSQ_IMG_SAMP_WORD1;                                // 0x23CD
  SQ_IMG_SAMP_WORD2                                      :TSQ_IMG_SAMP_WORD2;                                // 0x23CE
  SQ_IMG_SAMP_WORD3                                      :TSQ_IMG_SAMP_WORD3;                                // 0x23CF
  SQ_FLAT_SCRATCH_WORD0                                  :TSQ_FLAT_SCRATCH_WORD0;                            // 0x23D0
  SQ_FLAT_SCRATCH_WORD1                                  :TSQ_FLAT_SCRATCH_WORD1;                            // 0x23D1
  SQ_M0_GPR_IDX_WORD                                     :TSQ_M0_GPR_IDX_WORD;                               // 0x23D2
  REG_23D3_240B                                          :array[0..56] of DWORD;                             // 0x23D3
  CGTT_SX_CLK_CTRL0                                      :TCGTT_SX_CLK_CTRL0;                                // 0x240C
  CGTT_SX_CLK_CTRL1                                      :TCGTT_SX_CLK_CTRL1;                                // 0x240D
  CGTT_SX_CLK_CTRL2                                      :TCGTT_SX_CLK_CTRL2;                                // 0x240E
  CGTT_SX_CLK_CTRL3                                      :TCGTT_SX_CLK_CTRL3;                                // 0x240F
  CGTT_SX_CLK_CTRL4                                      :TCGTT_SX_CLK_CTRL4;                                // 0x2410
  REG_2411_2413                                          :array[0..2] of DWORD;                              // 0x2411
  SX_DEBUG_BUSY                                          :TSX_DEBUG_BUSY;                                    // 0x2414
  SX_DEBUG_BUSY_2                                        :TSX_DEBUG_BUSY_2;                                  // 0x2415
  SX_DEBUG_BUSY_3                                        :TSX_DEBUG_BUSY_3;                                  // 0x2416
  SX_DEBUG_BUSY_4                                        :TSX_DEBUG_BUSY_4;                                  // 0x2417
  SX_DEBUG_1                                             :TSX_DEBUG_1;                                       // 0x2418
  REG_2419_2439                                          :array[0..32] of DWORD;                             // 0x2419
  SPI_PS_MAX_WAVE_ID                                     :TSPI_PS_MAX_WAVE_ID;                               // 0x243A
  SPI_START_PHASE                                        :TSPI_START_PHASE;                                  // 0x243B
  SPI_GFX_CNTL                                           :TSPI_GFX_CNTL;                                     // 0x243C
  REG_243D_243F                                          :array[0..2] of DWORD;                              // 0x243D
  SPI_CONFIG_CNTL                                        :TSPI_CONFIG_CNTL;                                  // 0x2440
  SPI_DEBUG_CNTL                                         :TSPI_DEBUG_CNTL;                                   // 0x2441
  SPI_DEBUG_READ                                         :TSPI_DEBUG_READ;                                   // 0x2442
  SPI_DSM_CNTL                                           :TSPI_DSM_CNTL;                                     // 0x2443
  SPI_EDC_CNT                                            :TSPI_EDC_CNT;                                      // 0x2444
  REG_2445_244E                                          :array[0..9] of DWORD;                              // 0x2445
  SPI_CONFIG_CNTL_1                                      :TSPI_CONFIG_CNTL_1;                                // 0x244F
  SPI_DEBUG_BUSY                                         :TSPI_DEBUG_BUSY;                                   // 0x2450
  SPI_CONFIG_CNTL_2                                      :TSPI_CONFIG_CNTL_2;                                // 0x2451
  CGTS_TCC_DISABLE                                       :TCGTS_TCC_DISABLE;                                 // 0x2452
  CGTS_USER_TCC_DISABLE                                  :TCGTS_USER_TCC_DISABLE;                            // 0x2453
  CGTS_SM_CTRL_REG                                       :TCGTS_SM_CTRL_REG;                                 // 0x2454
  CGTS_RD_CTRL_REG                                       :TCGTS_RD_CTRL_REG;                                 // 0x2455
  CGTS_RD_REG                                            :TCGTS_RD_REG;                                      // 0x2456
  REG_2457_24A7                                          :array[0..80] of DWORD;                             // 0x2457
  CGTT_PC_CLK_CTRL                                       :TCGTT_PC_CLK_CTRL;                                 // 0x24A8
  CGTT_BCI_CLK_CTRL                                      :TCGTT_BCI_CLK_CTRL;                                // 0x24A9
  SPI_WF_LIFETIME_CNTL                                   :TSPI_WF_LIFETIME_CNTL;                             // 0x24AA
  SPI_WF_LIFETIME_LIMIT_0                                :TSPI_WF_LIFETIME_LIMIT_0;                          // 0x24AB
  SPI_WF_LIFETIME_LIMIT_1                                :TSPI_WF_LIFETIME_LIMIT_1;                          // 0x24AC
  SPI_WF_LIFETIME_LIMIT_2                                :TSPI_WF_LIFETIME_LIMIT_2;                          // 0x24AD
  SPI_WF_LIFETIME_LIMIT_3                                :TSPI_WF_LIFETIME_LIMIT_3;                          // 0x24AE
  SPI_WF_LIFETIME_LIMIT_4                                :TSPI_WF_LIFETIME_LIMIT_4;                          // 0x24AF
  SPI_WF_LIFETIME_LIMIT_5                                :TSPI_WF_LIFETIME_LIMIT_5;                          // 0x24B0
  SPI_WF_LIFETIME_LIMIT_6                                :TSPI_WF_LIFETIME_LIMIT_6;                          // 0x24B1
  SPI_WF_LIFETIME_LIMIT_7                                :TSPI_WF_LIFETIME_LIMIT_7;                          // 0x24B2
  SPI_WF_LIFETIME_LIMIT_8                                :TSPI_WF_LIFETIME_LIMIT_8;                          // 0x24B3
  SPI_WF_LIFETIME_LIMIT_9                                :TSPI_WF_LIFETIME_LIMIT_9;                          // 0x24B4
  SPI_WF_LIFETIME_STATUS_0                               :TSPI_WF_LIFETIME_STATUS_0;                         // 0x24B5
  SPI_WF_LIFETIME_STATUS_1                               :TSPI_WF_LIFETIME_STATUS_1;                         // 0x24B6
  SPI_WF_LIFETIME_STATUS_2                               :TSPI_WF_LIFETIME_STATUS_2;                         // 0x24B7
  SPI_WF_LIFETIME_STATUS_3                               :TSPI_WF_LIFETIME_STATUS_3;                         // 0x24B8
  SPI_WF_LIFETIME_STATUS_4                               :TSPI_WF_LIFETIME_STATUS_4;                         // 0x24B9
  SPI_WF_LIFETIME_STATUS_5                               :TSPI_WF_LIFETIME_STATUS_5;                         // 0x24BA
  SPI_WF_LIFETIME_STATUS_6                               :TSPI_WF_LIFETIME_STATUS_6;                         // 0x24BB
  SPI_WF_LIFETIME_STATUS_7                               :TSPI_WF_LIFETIME_STATUS_7;                         // 0x24BC
  SPI_WF_LIFETIME_STATUS_8                               :TSPI_WF_LIFETIME_STATUS_8;                         // 0x24BD
  SPI_WF_LIFETIME_STATUS_9                               :TSPI_WF_LIFETIME_STATUS_9;                         // 0x24BE
  SPI_WF_LIFETIME_STATUS_10                              :TSPI_WF_LIFETIME_STATUS_10;                        // 0x24BF
  SPI_WF_LIFETIME_STATUS_11                              :TSPI_WF_LIFETIME_STATUS_11;                        // 0x24C0
  SPI_WF_LIFETIME_STATUS_12                              :TSPI_WF_LIFETIME_STATUS_12;                        // 0x24C1
  SPI_WF_LIFETIME_STATUS_13                              :TSPI_WF_LIFETIME_STATUS_13;                        // 0x24C2
  SPI_WF_LIFETIME_STATUS_14                              :TSPI_WF_LIFETIME_STATUS_14;                        // 0x24C3
  SPI_WF_LIFETIME_STATUS_15                              :TSPI_WF_LIFETIME_STATUS_15;                        // 0x24C4
  SPI_WF_LIFETIME_STATUS_16                              :TSPI_WF_LIFETIME_STATUS_16;                        // 0x24C5
  SPI_WF_LIFETIME_STATUS_17                              :TSPI_WF_LIFETIME_STATUS_17;                        // 0x24C6
  SPI_WF_LIFETIME_STATUS_18                              :TSPI_WF_LIFETIME_STATUS_18;                        // 0x24C7
  SPI_WF_LIFETIME_STATUS_19                              :TSPI_WF_LIFETIME_STATUS_19;                        // 0x24C8
  SPI_WF_LIFETIME_STATUS_20                              :TSPI_WF_LIFETIME_STATUS_20;                        // 0x24C9
  SPI_WF_LIFETIME_DEBUG                                  :TSPI_WF_LIFETIME_DEBUG;                            // 0x24CA
  REG_24CB_24D2                                          :array[0..7] of DWORD;                              // 0x24CB
  SPI_SLAVE_DEBUG_BUSY                                   :TSPI_SLAVE_DEBUG_BUSY;                             // 0x24D3
  SPI_LB_CTR_CTRL                                        :TSPI_LB_CTR_CTRL;                                  // 0x24D4
  SPI_LB_CU_MASK                                         :TSPI_LB_CU_MASK;                                   // 0x24D5
  SPI_LB_DATA_REG                                        :TSPI_LB_DATA_REG;                                  // 0x24D6
  SPI_PG_ENABLE_STATIC_CU_MASK                           :TSPI_PG_ENABLE_STATIC_CU_MASK;                     // 0x24D7
  SPI_GDS_CREDITS                                        :TSPI_GDS_CREDITS;                                  // 0x24D8
  SPI_SX_EXPORT_BUFFER_SIZES                             :TSPI_SX_EXPORT_BUFFER_SIZES;                       // 0x24D9
  SPI_SX_SCOREBOARD_BUFFER_SIZES                         :TSPI_SX_SCOREBOARD_BUFFER_SIZES;                   // 0x24DA
  SPI_CSQ_WF_ACTIVE_STATUS                               :TSPI_CSQ_WF_ACTIVE_STATUS;                         // 0x24DB
  SPI_CSQ_WF_ACTIVE_COUNT_0                              :TSPI_CSQ_WF_ACTIVE_COUNT_0;                        // 0x24DC
  SPI_CSQ_WF_ACTIVE_COUNT_1                              :TSPI_CSQ_WF_ACTIVE_COUNT_1;                        // 0x24DD
  SPI_CSQ_WF_ACTIVE_COUNT_2                              :TSPI_CSQ_WF_ACTIVE_COUNT_2;                        // 0x24DE
  SPI_CSQ_WF_ACTIVE_COUNT_3                              :TSPI_CSQ_WF_ACTIVE_COUNT_3;                        // 0x24DF
  SPI_CSQ_WF_ACTIVE_COUNT_4                              :TSPI_CSQ_WF_ACTIVE_COUNT_4;                        // 0x24E0
  SPI_CSQ_WF_ACTIVE_COUNT_5                              :TSPI_CSQ_WF_ACTIVE_COUNT_5;                        // 0x24E1
  SPI_CSQ_WF_ACTIVE_COUNT_6                              :TSPI_CSQ_WF_ACTIVE_COUNT_6;                        // 0x24E2
  SPI_CSQ_WF_ACTIVE_COUNT_7                              :TSPI_CSQ_WF_ACTIVE_COUNT_7;                        // 0x24E3
  REG_24E4_24EA                                          :array[0..6] of DWORD;                              // 0x24E4
  BCI_DEBUG_READ                                         :TBCI_DEBUG_READ;                                   // 0x24EB
  SPI_P0_TRAP_SCREEN_PSBA_LO                             :TSPI_P0_TRAP_SCREEN_PSBA_LO;                       // 0x24EC
  SPI_P0_TRAP_SCREEN_PSBA_HI                             :TSPI_P0_TRAP_SCREEN_PSBA_HI;                       // 0x24ED
  SPI_P0_TRAP_SCREEN_PSMA_LO                             :TSPI_P0_TRAP_SCREEN_PSMA_LO;                       // 0x24EE
  SPI_P0_TRAP_SCREEN_PSMA_HI                             :TSPI_P0_TRAP_SCREEN_PSMA_HI;                       // 0x24EF
  SPI_P0_TRAP_SCREEN_GPR_MIN                             :TSPI_P0_TRAP_SCREEN_GPR_MIN;                       // 0x24F0
  SPI_P1_TRAP_SCREEN_PSBA_LO                             :TSPI_P1_TRAP_SCREEN_PSBA_LO;                       // 0x24F1
  SPI_P1_TRAP_SCREEN_PSBA_HI                             :TSPI_P1_TRAP_SCREEN_PSBA_HI;                       // 0x24F2
  SPI_P1_TRAP_SCREEN_PSMA_LO                             :TSPI_P1_TRAP_SCREEN_PSMA_LO;                       // 0x24F3
  SPI_P1_TRAP_SCREEN_PSMA_HI                             :TSPI_P1_TRAP_SCREEN_PSMA_HI;                       // 0x24F4
  SPI_P1_TRAP_SCREEN_GPR_MIN                             :TSPI_P1_TRAP_SCREEN_GPR_MIN;                       // 0x24F5
  REG_24F6_2524                                          :array[0..46] of DWORD;                             // 0x24F6
  TD_CNTL                                                :TTD_CNTL;                                          // 0x2525
  TD_STATUS                                              :TTD_STATUS;                                        // 0x2526
  TD_CGTT_CTRL                                           :TTD_CGTT_CTRL;                                     // 0x2527
  TD_DEBUG_INDEX                                         :TTD_DEBUG_INDEX;                                   // 0x2528
  TD_DEBUG_DATA                                          :TTD_DEBUG_DATA;                                    // 0x2529
  REG_252A_252E                                          :array[0..4] of DWORD;                              // 0x252A
  TD_DSM_CNTL                                            :TTD_DSM_CNTL;                                      // 0x252F
  REG_2530_2532                                          :array[0..2] of DWORD;                              // 0x2530
  TD_SCRATCH                                             :TTD_SCRATCH;                                       // 0x2533
  REG_2534_2540                                          :array[0..12] of DWORD;                             // 0x2534
  TA_CNTL                                                :TTA_CNTL;                                          // 0x2541
  TA_CNTL_AUX                                            :TTA_CNTL_AUX;                                      // 0x2542
  TA_RESERVED_010C                                       :TTA_RESERVED_010C;                                 // 0x2543
  TA_CGTT_CTRL                                           :TTA_CGTT_CTRL;                                     // 0x2544
  REG_2545_2547                                          :array[0..2] of DWORD;                              // 0x2545
  TA_STATUS                                              :TTA_STATUS;                                        // 0x2548
  REG_2549_254B                                          :array[0..2] of DWORD;                              // 0x2549
  TA_DEBUG_INDEX                                         :TTA_DEBUG_INDEX;                                   // 0x254C
  TA_DEBUG_DATA                                          :TTA_DEBUG_DATA;                                    // 0x254D
  REG_254E_2563                                          :array[0..21] of DWORD;                             // 0x254E
  TA_SCRATCH                                             :TTA_SCRATCH;                                       // 0x2564
  REG_2565_257F                                          :array[0..26] of DWORD;                             // 0x2565
  SH_HIDDEN_PRIVATE_BASE_VMID                            :TSH_HIDDEN_PRIVATE_BASE_VMID;                      // 0x2580
  SH_STATIC_MEM_CONFIG                                   :TSH_STATIC_MEM_CONFIG;                             // 0x2581
  REG_2582_25BF                                          :array[0..61] of DWORD;                             // 0x2582
  GDS_CONFIG                                             :TGDS_CONFIG;                                       // 0x25C0
  GDS_CNTL_STATUS                                        :TGDS_CNTL_STATUS;                                  // 0x25C1
  GDS_ENHANCE2                                           :TGDS_ENHANCE2;                                     // 0x25C2
  GDS_PROTECTION_FAULT                                   :TGDS_PROTECTION_FAULT;                             // 0x25C3
  GDS_VM_PROTECTION_FAULT                                :TGDS_VM_PROTECTION_FAULT;                          // 0x25C4
  GDS_EDC_CNT                                            :TGDS_EDC_CNT;                                      // 0x25C5
  GDS_EDC_GRBM_CNT                                       :TGDS_EDC_GRBM_CNT;                                 // 0x25C6
  GDS_EDC_OA_DED                                         :TGDS_EDC_OA_DED;                                   // 0x25C7
  GDS_DEBUG_CNTL                                         :TGDS_DEBUG_CNTL;                                   // 0x25C8
  GDS_DEBUG_DATA                                         :TGDS_DEBUG_DATA;                                   // 0x25C9
  GDS_DSM_CNTL                                           :TGDS_DSM_CNTL;                                     // 0x25CA
  REG_25CB_25DC                                          :array[0..17] of DWORD;                             // 0x25CB
  CGTT_GDS_CLK_CTRL                                      :TCGTT_GDS_CLK_CTRL;                                // 0x25DD
  REG_25DE_25E1                                          :array[0..3] of DWORD;                              // 0x25DE
  GDS_SECDED_CNT                                         :TGDS_SECDED_CNT;                                   // 0x25E2
  GDS_GRBM_SECDED_CNT                                    :TGDS_GRBM_SECDED_CNT;                              // 0x25E3
  GDS_OA_DED                                             :TGDS_OA_DED;                                       // 0x25E4
  REG_25E5_260B                                          :array[0..38] of DWORD;                             // 0x25E5
  DB_DEBUG                                               :TDB_DEBUG;                                         // 0x260C
  DB_DEBUG2                                              :TDB_DEBUG2;                                        // 0x260D
  DB_DEBUG3                                              :TDB_DEBUG3;                                        // 0x260E
  DB_DEBUG4                                              :TDB_DEBUG4;                                        // 0x260F
  REG_2610_2613                                          :array[0..3] of DWORD;                              // 0x2610
  DB_CREDIT_LIMIT                                        :TDB_CREDIT_LIMIT;                                  // 0x2614
  DB_WATERMARKS                                          :TDB_WATERMARKS;                                    // 0x2615
  DB_SUBTILE_CONTROL                                     :TDB_SUBTILE_CONTROL;                               // 0x2616
  DB_FREE_CACHELINES                                     :TDB_FREE_CACHELINES;                               // 0x2617
  DB_FIFO_DEPTH1                                         :TDB_FIFO_DEPTH1;                                   // 0x2618
  DB_FIFO_DEPTH2                                         :TDB_FIFO_DEPTH2;                                   // 0x2619
  DB_CGTT_CLK_CTRL_0                                     :TDB_CGTT_CLK_CTRL_0;                               // 0x261A
  DB_RING_CONTROL                                        :TDB_RING_CONTROL;                                  // 0x261B
  REG_261C_261F                                          :array[0..3] of DWORD;                              // 0x261C
  DB_READ_DEBUG_0                                        :TDB_READ_DEBUG_0;                                  // 0x2620
  DB_READ_DEBUG_1                                        :TDB_READ_DEBUG_1;                                  // 0x2621
  DB_READ_DEBUG_2                                        :TDB_READ_DEBUG_2;                                  // 0x2622
  DB_READ_DEBUG_3                                        :TDB_READ_DEBUG_3;                                  // 0x2623
  DB_READ_DEBUG_4                                        :TDB_READ_DEBUG_4;                                  // 0x2624
  DB_READ_DEBUG_5                                        :TDB_READ_DEBUG_5;                                  // 0x2625
  DB_READ_DEBUG_6                                        :TDB_READ_DEBUG_6;                                  // 0x2626
  DB_READ_DEBUG_7                                        :TDB_READ_DEBUG_7;                                  // 0x2627
  DB_READ_DEBUG_8                                        :TDB_READ_DEBUG_8;                                  // 0x2628
  DB_READ_DEBUG_9                                        :TDB_READ_DEBUG_9;                                  // 0x2629
  DB_READ_DEBUG_A                                        :TDB_READ_DEBUG_A;                                  // 0x262A
  DB_READ_DEBUG_B                                        :TDB_READ_DEBUG_B;                                  // 0x262B
  DB_READ_DEBUG_C                                        :TDB_READ_DEBUG_C;                                  // 0x262C
  DB_READ_DEBUG_D                                        :TDB_READ_DEBUG_D;                                  // 0x262D
  DB_READ_DEBUG_E                                        :TDB_READ_DEBUG_E;                                  // 0x262E
  DB_READ_DEBUG_F                                        :TDB_READ_DEBUG_F;                                  // 0x262F
  REG_2630_263B                                          :array[0..11] of DWORD;                             // 0x2630
  CC_RB_REDUNDANCY                                       :TCC_RB_REDUNDANCY;                                 // 0x263C
  CC_RB_BACKEND_DISABLE                                  :TCC_RB_BACKEND_DISABLE;                            // 0x263D
  GB_ADDR_CONFIG                                         :TGB_ADDR_CONFIG;                                   // 0x263E
  GB_BACKEND_MAP                                         :TGB_BACKEND_MAP;                                   // 0x263F
  GB_GPU_ID                                              :TGB_GPU_ID;                                        // 0x2640
  CC_RB_DAISY_CHAIN                                      :TCC_RB_DAISY_CHAIN;                                // 0x2641
  REG_2642_2643                                          :array[0..1] of DWORD;                              // 0x2642
  GB_TILE_MODE0                                          :TGB_TILE_MODE0;                                    // 0x2644
  GB_TILE_MODE1                                          :TGB_TILE_MODE1;                                    // 0x2645
  GB_TILE_MODE2                                          :TGB_TILE_MODE2;                                    // 0x2646
  GB_TILE_MODE3                                          :TGB_TILE_MODE3;                                    // 0x2647
  GB_TILE_MODE4                                          :TGB_TILE_MODE4;                                    // 0x2648
  GB_TILE_MODE5                                          :TGB_TILE_MODE5;                                    // 0x2649
  GB_TILE_MODE6                                          :TGB_TILE_MODE6;                                    // 0x264A
  GB_TILE_MODE7                                          :TGB_TILE_MODE7;                                    // 0x264B
  GB_TILE_MODE8                                          :TGB_TILE_MODE8;                                    // 0x264C
  GB_TILE_MODE9                                          :TGB_TILE_MODE9;                                    // 0x264D
  GB_TILE_MODE10                                         :TGB_TILE_MODE10;                                   // 0x264E
  GB_TILE_MODE11                                         :TGB_TILE_MODE11;                                   // 0x264F
  GB_TILE_MODE12                                         :TGB_TILE_MODE12;                                   // 0x2650
  GB_TILE_MODE13                                         :TGB_TILE_MODE13;                                   // 0x2651
  GB_TILE_MODE14                                         :TGB_TILE_MODE14;                                   // 0x2652
  GB_TILE_MODE15                                         :TGB_TILE_MODE15;                                   // 0x2653
  GB_TILE_MODE16                                         :TGB_TILE_MODE16;                                   // 0x2654
  GB_TILE_MODE17                                         :TGB_TILE_MODE17;                                   // 0x2655
  GB_TILE_MODE18                                         :TGB_TILE_MODE18;                                   // 0x2656
  GB_TILE_MODE19                                         :TGB_TILE_MODE19;                                   // 0x2657
  GB_TILE_MODE20                                         :TGB_TILE_MODE20;                                   // 0x2658
  GB_TILE_MODE21                                         :TGB_TILE_MODE21;                                   // 0x2659
  GB_TILE_MODE22                                         :TGB_TILE_MODE22;                                   // 0x265A
  GB_TILE_MODE23                                         :TGB_TILE_MODE23;                                   // 0x265B
  GB_TILE_MODE24                                         :TGB_TILE_MODE24;                                   // 0x265C
  GB_TILE_MODE25                                         :TGB_TILE_MODE25;                                   // 0x265D
  GB_TILE_MODE26                                         :TGB_TILE_MODE26;                                   // 0x265E
  GB_TILE_MODE27                                         :TGB_TILE_MODE27;                                   // 0x265F
  GB_TILE_MODE28                                         :TGB_TILE_MODE28;                                   // 0x2660
  GB_TILE_MODE29                                         :TGB_TILE_MODE29;                                   // 0x2661
  GB_TILE_MODE30                                         :TGB_TILE_MODE30;                                   // 0x2662
  GB_TILE_MODE31                                         :TGB_TILE_MODE31;                                   // 0x2663
  GB_MACROTILE_MODE0                                     :TGB_MACROTILE_MODE0;                               // 0x2664
  GB_MACROTILE_MODE1                                     :TGB_MACROTILE_MODE1;                               // 0x2665
  GB_MACROTILE_MODE2                                     :TGB_MACROTILE_MODE2;                               // 0x2666
  GB_MACROTILE_MODE3                                     :TGB_MACROTILE_MODE3;                               // 0x2667
  GB_MACROTILE_MODE4                                     :TGB_MACROTILE_MODE4;                               // 0x2668
  GB_MACROTILE_MODE5                                     :TGB_MACROTILE_MODE5;                               // 0x2669
  GB_MACROTILE_MODE6                                     :TGB_MACROTILE_MODE6;                               // 0x266A
  GB_MACROTILE_MODE7                                     :TGB_MACROTILE_MODE7;                               // 0x266B
  GB_MACROTILE_MODE8                                     :TGB_MACROTILE_MODE8;                               // 0x266C
  GB_MACROTILE_MODE9                                     :TGB_MACROTILE_MODE9;                               // 0x266D
  GB_MACROTILE_MODE10                                    :TGB_MACROTILE_MODE10;                              // 0x266E
  GB_MACROTILE_MODE11                                    :TGB_MACROTILE_MODE11;                              // 0x266F
  GB_MACROTILE_MODE12                                    :TGB_MACROTILE_MODE12;                              // 0x2670
  GB_MACROTILE_MODE13                                    :TGB_MACROTILE_MODE13;                              // 0x2671
  GB_MACROTILE_MODE14                                    :TGB_MACROTILE_MODE14;                              // 0x2672
  GB_MACROTILE_MODE15                                    :TGB_MACROTILE_MODE15;                              // 0x2673
  REG_2674_2682                                          :array[0..14] of DWORD;                             // 0x2674
  CB_HW_CONTROL_3                                        :TCB_HW_CONTROL_3;                                  // 0x2683
  CB_HW_CONTROL                                          :TCB_HW_CONTROL;                                    // 0x2684
  CB_HW_CONTROL_1                                        :TCB_HW_CONTROL_1;                                  // 0x2685
  CB_HW_CONTROL_2                                        :TCB_HW_CONTROL_2;                                  // 0x2686
  CB_DCC_CONFIG                                          :TCB_DCC_CONFIG;                                    // 0x2687
  CB_PERFCOUNTER0_SELECT0                                :TCB_PERFCOUNTER0_SELECT0;                          // 0x2688
  REG_2689                                               :DWORD;                                             // 0x2689
  CB_PERFCOUNTER1_SELECT0                                :TCB_PERFCOUNTER1_SELECT0;                          // 0x268A
  CB_PERFCOUNTER1_SELECT1                                :TCB_PERFCOUNTER1_SELECT1;                          // 0x268B
  CB_PERFCOUNTER2_SELECT0                                :TCB_PERFCOUNTER2_SELECT0;                          // 0x268C
  CB_PERFCOUNTER2_SELECT1                                :TCB_PERFCOUNTER2_SELECT1;                          // 0x268D
  CB_PERFCOUNTER3_SELECT0                                :TCB_PERFCOUNTER3_SELECT0;                          // 0x268E
  CB_PERFCOUNTER3_SELECT1                                :TCB_PERFCOUNTER3_SELECT1;                          // 0x268F
  REG_2690_2697                                          :array[0..7] of DWORD;                              // 0x2690
  CB_CGTT_SCLK_CTRL                                      :TCB_CGTT_SCLK_CTRL;                                // 0x2698
  CB_DEBUG_BUS_1                                         :TCB_DEBUG_BUS_1;                                   // 0x2699
  CB_DEBUG_BUS_2                                         :TCB_DEBUG_BUS_2;                                   // 0x269A
  REG_269B_26A4                                          :array[0..9] of DWORD;                              // 0x269B
  CB_DEBUG_BUS_13                                        :TCB_DEBUG_BUS_13;                                  // 0x26A5
  CB_DEBUG_BUS_14                                        :TCB_DEBUG_BUS_14;                                  // 0x26A6
  CB_DEBUG_BUS_15                                        :TCB_DEBUG_BUS_15;                                  // 0x26A7
  CB_DEBUG_BUS_16                                        :TCB_DEBUG_BUS_16;                                  // 0x26A8
  CB_DEBUG_BUS_17                                        :TCB_DEBUG_BUS_17;                                  // 0x26A9
  CB_DEBUG_BUS_18                                        :TCB_DEBUG_BUS_18;                                  // 0x26AA
  CB_DEBUG_BUS_19                                        :TCB_DEBUG_BUS_19;                                  // 0x26AB
  CB_DEBUG_BUS_20                                        :TCB_DEBUG_BUS_20;                                  // 0x26AC
  CB_DEBUG_BUS_21                                        :TCB_DEBUG_BUS_21;                                  // 0x26AD
  CB_DEBUG_BUS_22                                        :TCB_DEBUG_BUS_22;                                  // 0x26AE
  REG_26AF_26DD                                          :array[0..46] of DWORD;                             // 0x26AF
  GC_USER_RB_REDUNDANCY                                  :TGC_USER_RB_REDUNDANCY;                            // 0x26DE
  GC_USER_RB_BACKEND_DISABLE                             :TGC_USER_RB_BACKEND_DISABLE;                       // 0x26DF
  REG_26E0_2AFF                                          :array[0..1055] of DWORD;                           // 0x26E0
  TCP_INVALIDATE                                         :TTCP_INVALIDATE;                                   // 0x2B00
  TCP_STATUS                                             :TTCP_STATUS;                                       // 0x2B01
  TCP_CNTL                                               :TTCP_CNTL;                                         // 0x2B02
  TCP_CHAN_STEER_LO                                      :TTCP_CHAN_STEER_LO;                                // 0x2B03
  TCP_CHAN_STEER_HI                                      :TTCP_CHAN_STEER_HI;                                // 0x2B04
  TCP_ADDR_CONFIG                                        :TTCP_ADDR_CONFIG;                                  // 0x2B05
  TCP_CREDIT                                             :TTCP_CREDIT;                                       // 0x2B06
  REG_2B07_2B14                                          :array[0..13] of DWORD;                             // 0x2B07
  CGTT_TCP_CLK_CTRL                                      :TCGTT_TCP_CLK_CTRL;                                // 0x2B15
  TCP_BUFFER_ADDR_HASH_CNTL                              :TTCP_BUFFER_ADDR_HASH_CNTL;                        // 0x2B16
  TCP_EDC_CNT                                            :TTCP_EDC_CNT;                                      // 0x2B17
  REG_2B18_2B19                                          :array[0..1] of DWORD;                              // 0x2B18
  TC_CFG_L1_LOAD_POLICY0                                 :TTC_CFG_L1_LOAD_POLICY0;                           // 0x2B1A
  TC_CFG_L1_LOAD_POLICY1                                 :TTC_CFG_L1_LOAD_POLICY1;                           // 0x2B1B
  TC_CFG_L1_STORE_POLICY                                 :TTC_CFG_L1_STORE_POLICY;                           // 0x2B1C
  TC_CFG_L2_LOAD_POLICY0                                 :TTC_CFG_L2_LOAD_POLICY0;                           // 0x2B1D
  TC_CFG_L2_LOAD_POLICY1                                 :TTC_CFG_L2_LOAD_POLICY1;                           // 0x2B1E
  TC_CFG_L2_STORE_POLICY0                                :TTC_CFG_L2_STORE_POLICY0;                          // 0x2B1F
  TC_CFG_L2_STORE_POLICY1                                :TTC_CFG_L2_STORE_POLICY1;                          // 0x2B20
  TC_CFG_L2_ATOMIC_POLICY                                :TTC_CFG_L2_ATOMIC_POLICY;                          // 0x2B21
  TC_CFG_L1_VOLATILE                                     :TTC_CFG_L1_VOLATILE;                               // 0x2B22
  TC_CFG_L2_VOLATILE                                     :TTC_CFG_L2_VOLATILE;                               // 0x2B23
  REG_2B24_2B5F                                          :array[0..59] of DWORD;                             // 0x2B24
  CGTT_TCI_CLK_CTRL                                      :TCGTT_TCI_CLK_CTRL;                                // 0x2B60
  TCI_STATUS                                             :TTCI_STATUS;                                       // 0x2B61
  TCI_CNTL_1                                             :TTCI_CNTL_1;                                       // 0x2B62
  TCI_CNTL_2                                             :TTCI_CNTL_2;                                       // 0x2B63
  REG_2B64_2B7F                                          :array[0..27] of DWORD;                             // 0x2B64
  TCC_CTRL                                               :TTCC_CTRL;                                         // 0x2B80
  TCC_CGTT_SCLK_CTRL                                     :TTCC_CGTT_SCLK_CTRL;                               // 0x2B81
  TCC_EDC_CNT                                            :TTCC_EDC_CNT;                                      // 0x2B82
  TCC_REDUNDANCY                                         :TTCC_REDUNDANCY;                                   // 0x2B83
  TCC_EXE_DISABLE                                        :TTCC_EXE_DISABLE;                                  // 0x2B84
  TCC_DSM_CNTL                                           :TTCC_DSM_CNTL;                                     // 0x2B85
  REG_2B86_2BBF                                          :array[0..57] of DWORD;                             // 0x2B86
  TCA_CTRL                                               :TTCA_CTRL;                                         // 0x2BC0
  TCA_CGTT_SCLK_CTRL                                     :TTCA_CGTT_SCLK_CTRL;                               // 0x2BC1
  REG_2BC2_301F                                          :array[0..1117] of DWORD;                           // 0x2BC2
  CP_DFY_CNTL                                            :TCP_DFY_CNTL;                                      // 0x3020
  CP_DFY_STAT                                            :TCP_DFY_STAT;                                      // 0x3021
  CP_DFY_ADDR_HI                                         :TCP_DFY_ADDR_HI;                                   // 0x3022
  CP_DFY_ADDR_LO                                         :TCP_DFY_ADDR_LO;                                   // 0x3023
  CP_DFY_DATA_0                                          :TCP_DFY_DATA_0;                                    // 0x3024
  CP_DFY_DATA_1                                          :TCP_DFY_DATA_1;                                    // 0x3025
  CP_DFY_DATA_2                                          :TCP_DFY_DATA_2;                                    // 0x3026
  CP_DFY_DATA_3                                          :TCP_DFY_DATA_3;                                    // 0x3027
  CP_DFY_DATA_4                                          :TCP_DFY_DATA_4;                                    // 0x3028
  CP_DFY_DATA_5                                          :TCP_DFY_DATA_5;                                    // 0x3029
  CP_DFY_DATA_6                                          :TCP_DFY_DATA_6;                                    // 0x302A
  CP_DFY_DATA_7                                          :TCP_DFY_DATA_7;                                    // 0x302B
  CP_DFY_DATA_8                                          :TCP_DFY_DATA_8;                                    // 0x302C
  CP_DFY_DATA_9                                          :TCP_DFY_DATA_9;                                    // 0x302D
  CP_DFY_DATA_10                                         :TCP_DFY_DATA_10;                                   // 0x302E
  CP_DFY_DATA_11                                         :TCP_DFY_DATA_11;                                   // 0x302F
  CP_DFY_DATA_12                                         :TCP_DFY_DATA_12;                                   // 0x3030
  CP_DFY_DATA_13                                         :TCP_DFY_DATA_13;                                   // 0x3031
  CP_DFY_DATA_14                                         :TCP_DFY_DATA_14;                                   // 0x3032
  CP_DFY_DATA_15                                         :TCP_DFY_DATA_15;                                   // 0x3033
  CP_DFY_CMD                                             :TCP_DFY_CMD;                                       // 0x3034
  REG_3035                                               :DWORD;                                             // 0x3035
  CP_CPC_MGCG_SYNC_CNTL                                  :TCP_CPC_MGCG_SYNC_CNTL;                            // 0x3036
  REG_3037                                               :DWORD;                                             // 0x3037
  CP_VIRT_STATUS                                         :TCP_VIRT_STATUS;                                   // 0x3038
  REG_3039_303F                                          :array[0..6] of DWORD;                              // 0x3039
  CP_RB0_BASE                                            :TCP_RB0_BASE;                                      // 0x3040
  CP_RB0_CNTL                                            :TCP_RB0_CNTL;                                      // 0x3041
  CP_RB_RPTR_WR                                          :TCP_RB_RPTR_WR;                                    // 0x3042
  CP_RB0_RPTR_ADDR                                       :TCP_RB0_RPTR_ADDR;                                 // 0x3043
  CP_RB0_RPTR_ADDR_HI                                    :TCP_RB0_RPTR_ADDR_HI;                              // 0x3044
  CP_RB0_WPTR                                            :TCP_RB0_WPTR;                                      // 0x3045
  CP_RB_WPTR_POLL_ADDR_LO                                :TCP_RB_WPTR_POLL_ADDR_LO;                          // 0x3046
  CP_RB_WPTR_POLL_ADDR_HI                                :TCP_RB_WPTR_POLL_ADDR_HI;                          // 0x3047
  REG_3048                                               :DWORD;                                             // 0x3048
  CP_INT_CNTL                                            :TCP_INT_CNTL;                                      // 0x3049
  CP_INT_STATUS                                          :TCP_INT_STATUS;                                    // 0x304A
  CP_DEVICE_ID                                           :TCP_DEVICE_ID;                                     // 0x304B
  CP_ME0_PIPE_PRIORITY_CNTS                              :TCP_ME0_PIPE_PRIORITY_CNTS;                        // 0x304C
  CP_ME0_PIPE0_PRIORITY                                  :TCP_ME0_PIPE0_PRIORITY;                            // 0x304D
  CP_ME0_PIPE1_PRIORITY                                  :TCP_ME0_PIPE1_PRIORITY;                            // 0x304E
  CP_ME0_PIPE2_PRIORITY                                  :TCP_ME0_PIPE2_PRIORITY;                            // 0x304F
  CP_ENDIAN_SWAP                                         :TCP_ENDIAN_SWAP;                                   // 0x3050
  CP_RB_VMID                                             :TCP_RB_VMID;                                       // 0x3051
  CP_ME0_PIPE0_VMID                                      :TCP_ME0_PIPE0_VMID;                                // 0x3052
  CP_ME0_PIPE1_VMID                                      :TCP_ME0_PIPE1_VMID;                                // 0x3053
  REG_3054_3058                                          :array[0..4] of DWORD;                              // 0x3054
  CP_RB_DOORBELL_CONTROL                                 :TCP_RB_DOORBELL_CONTROL;                           // 0x3059
  CP_RB_DOORBELL_RANGE_LOWER                             :TCP_RB_DOORBELL_RANGE_LOWER;                       // 0x305A
  CP_RB_DOORBELL_RANGE_UPPER                             :TCP_RB_DOORBELL_RANGE_UPPER;                       // 0x305B
  CP_MEC_DOORBELL_RANGE_LOWER                            :TCP_MEC_DOORBELL_RANGE_LOWER;                      // 0x305C
  CP_MEC_DOORBELL_RANGE_UPPER                            :TCP_MEC_DOORBELL_RANGE_UPPER;                      // 0x305D
  REG_305E_305F                                          :array[0..1] of DWORD;                              // 0x305E
  CP_RB1_BASE                                            :TCP_RB1_BASE;                                      // 0x3060
  CP_RB1_CNTL                                            :TCP_RB1_CNTL;                                      // 0x3061
  CP_RB1_RPTR_ADDR                                       :TCP_RB1_RPTR_ADDR;                                 // 0x3062
  CP_RB1_RPTR_ADDR_HI                                    :TCP_RB1_RPTR_ADDR_HI;                              // 0x3063
  CP_RB1_WPTR                                            :TCP_RB1_WPTR;                                      // 0x3064
  CP_RB2_BASE                                            :TCP_RB2_BASE;                                      // 0x3065
  CP_RB2_CNTL                                            :TCP_RB2_CNTL;                                      // 0x3066
  CP_RB2_RPTR_ADDR                                       :TCP_RB2_RPTR_ADDR;                                 // 0x3067
  CP_RB2_RPTR_ADDR_HI                                    :TCP_RB2_RPTR_ADDR_HI;                              // 0x3068
  CP_RB2_WPTR                                            :TCP_RB2_WPTR;                                      // 0x3069
  CP_INT_CNTL_RING0                                      :TCP_INT_CNTL_RING0;                                // 0x306A
  CP_INT_CNTL_RING1                                      :TCP_INT_CNTL_RING1;                                // 0x306B
  CP_INT_CNTL_RING2                                      :TCP_INT_CNTL_RING2;                                // 0x306C
  CP_INT_STATUS_RING0                                    :TCP_INT_STATUS_RING0;                              // 0x306D
  CP_INT_STATUS_RING1                                    :TCP_INT_STATUS_RING1;                              // 0x306E
  CP_INT_STATUS_RING2                                    :TCP_INT_STATUS_RING2;                              // 0x306F
  REG_3070_3077                                          :array[0..7] of DWORD;                              // 0x3070
  CP_PWR_CNTL                                            :TCP_PWR_CNTL;                                      // 0x3078
  CP_MEM_SLP_CNTL                                        :TCP_MEM_SLP_CNTL;                                  // 0x3079
  CP_ECC_FIRSTOCCURRENCE                                 :TCP_ECC_FIRSTOCCURRENCE;                           // 0x307A
  CP_ECC_FIRSTOCCURRENCE_RING0                           :TCP_ECC_FIRSTOCCURRENCE_RING0;                     // 0x307B
  CP_ECC_FIRSTOCCURRENCE_RING1                           :TCP_ECC_FIRSTOCCURRENCE_RING1;                     // 0x307C
  CP_ECC_FIRSTOCCURRENCE_RING2                           :TCP_ECC_FIRSTOCCURRENCE_RING2;                     // 0x307D
  GB_EDC_MODE                                            :TGB_EDC_MODE;                                      // 0x307E
  CP_DEBUG                                               :TCP_DEBUG;                                         // 0x307F
  REG_3080_3082                                          :array[0..2] of DWORD;                              // 0x3080
  CP_PQ_WPTR_POLL_CNTL                                   :TCP_PQ_WPTR_POLL_CNTL;                             // 0x3083
  CP_PQ_WPTR_POLL_CNTL1                                  :TCP_PQ_WPTR_POLL_CNTL1;                            // 0x3084
  CP_ME1_PIPE0_INT_CNTL                                  :TCP_ME1_PIPE0_INT_CNTL;                            // 0x3085
  CP_ME1_PIPE1_INT_CNTL                                  :TCP_ME1_PIPE1_INT_CNTL;                            // 0x3086
  CP_ME1_PIPE2_INT_CNTL                                  :TCP_ME1_PIPE2_INT_CNTL;                            // 0x3087
  CP_ME1_PIPE3_INT_CNTL                                  :TCP_ME1_PIPE3_INT_CNTL;                            // 0x3088
  CP_ME2_PIPE0_INT_CNTL                                  :TCP_ME2_PIPE0_INT_CNTL;                            // 0x3089
  CP_ME2_PIPE1_INT_CNTL                                  :TCP_ME2_PIPE1_INT_CNTL;                            // 0x308A
  CP_ME2_PIPE2_INT_CNTL                                  :TCP_ME2_PIPE2_INT_CNTL;                            // 0x308B
  CP_ME2_PIPE3_INT_CNTL                                  :TCP_ME2_PIPE3_INT_CNTL;                            // 0x308C
  CP_ME1_PIPE0_INT_STATUS                                :TCP_ME1_PIPE0_INT_STATUS;                          // 0x308D
  CP_ME1_PIPE1_INT_STATUS                                :TCP_ME1_PIPE1_INT_STATUS;                          // 0x308E
  CP_ME1_PIPE2_INT_STATUS                                :TCP_ME1_PIPE2_INT_STATUS;                          // 0x308F
  CP_ME1_PIPE3_INT_STATUS                                :TCP_ME1_PIPE3_INT_STATUS;                          // 0x3090
  CP_ME2_PIPE0_INT_STATUS                                :TCP_ME2_PIPE0_INT_STATUS;                          // 0x3091
  CP_ME2_PIPE1_INT_STATUS                                :TCP_ME2_PIPE1_INT_STATUS;                          // 0x3092
  CP_ME2_PIPE2_INT_STATUS                                :TCP_ME2_PIPE2_INT_STATUS;                          // 0x3093
  CP_ME2_PIPE3_INT_STATUS                                :TCP_ME2_PIPE3_INT_STATUS;                          // 0x3094
  CP_ME1_INT_STAT_DEBUG                                  :TCP_ME1_INT_STAT_DEBUG;                            // 0x3095
  CP_ME2_INT_STAT_DEBUG                                  :TCP_ME2_INT_STAT_DEBUG;                            // 0x3096
  REG_3097                                               :DWORD;                                             // 0x3097
  CC_GC_EDC_CONFIG                                       :TCC_GC_EDC_CONFIG;                                 // 0x3098
  CP_ME1_PIPE_PRIORITY_CNTS                              :TCP_ME1_PIPE_PRIORITY_CNTS;                        // 0x3099
  CP_ME1_PIPE0_PRIORITY                                  :TCP_ME1_PIPE0_PRIORITY;                            // 0x309A
  CP_ME1_PIPE1_PRIORITY                                  :TCP_ME1_PIPE1_PRIORITY;                            // 0x309B
  CP_ME1_PIPE2_PRIORITY                                  :TCP_ME1_PIPE2_PRIORITY;                            // 0x309C
  CP_ME1_PIPE3_PRIORITY                                  :TCP_ME1_PIPE3_PRIORITY;                            // 0x309D
  CP_ME2_PIPE_PRIORITY_CNTS                              :TCP_ME2_PIPE_PRIORITY_CNTS;                        // 0x309E
  CP_ME2_PIPE0_PRIORITY                                  :TCP_ME2_PIPE0_PRIORITY;                            // 0x309F
  CP_ME2_PIPE1_PRIORITY                                  :TCP_ME2_PIPE1_PRIORITY;                            // 0x30A0
  CP_ME2_PIPE2_PRIORITY                                  :TCP_ME2_PIPE2_PRIORITY;                            // 0x30A1
  CP_ME2_PIPE3_PRIORITY                                  :TCP_ME2_PIPE3_PRIORITY;                            // 0x30A2
  CP_CE_PRGRM_CNTR_START                                 :TCP_CE_PRGRM_CNTR_START;                           // 0x30A3
  CP_PFP_PRGRM_CNTR_START                                :TCP_PFP_PRGRM_CNTR_START;                          // 0x30A4
  CP_ME_PRGRM_CNTR_START                                 :TCP_ME_PRGRM_CNTR_START;                           // 0x30A5
  CP_MEC1_PRGRM_CNTR_START                               :TCP_MEC1_PRGRM_CNTR_START;                         // 0x30A6
  CP_MEC2_PRGRM_CNTR_START                               :TCP_MEC2_PRGRM_CNTR_START;                         // 0x30A7
  CP_CE_INTR_ROUTINE_START                               :TCP_CE_INTR_ROUTINE_START;                         // 0x30A8
  CP_PFP_INTR_ROUTINE_START                              :TCP_PFP_INTR_ROUTINE_START;                        // 0x30A9
  CP_ME_INTR_ROUTINE_START                               :TCP_ME_INTR_ROUTINE_START;                         // 0x30AA
  CP_MEC1_INTR_ROUTINE_START                             :TCP_MEC1_INTR_ROUTINE_START;                       // 0x30AB
  CP_MEC2_INTR_ROUTINE_START                             :TCP_MEC2_INTR_ROUTINE_START;                       // 0x30AC
  CP_CONTEXT_CNTL                                        :TCP_CONTEXT_CNTL;                                  // 0x30AD
  CP_MAX_CONTEXT                                         :TCP_MAX_CONTEXT;                                   // 0x30AE
  CP_IQ_WAIT_TIME1                                       :TCP_IQ_WAIT_TIME1;                                 // 0x30AF
  CP_IQ_WAIT_TIME2                                       :TCP_IQ_WAIT_TIME2;                                 // 0x30B0
  CP_RB0_BASE_HI                                         :TCP_RB0_BASE_HI;                                   // 0x30B1
  CP_RB1_BASE_HI                                         :TCP_RB1_BASE_HI;                                   // 0x30B2
  CP_VMID_RESET                                          :TCP_VMID_RESET;                                    // 0x30B3
  CPC_INT_CNTL                                           :TCPC_INT_CNTL;                                     // 0x30B4
  CPC_INT_STATUS                                         :TCPC_INT_STATUS;                                   // 0x30B5
  CP_VMID_PREEMPT                                        :TCP_VMID_PREEMPT;                                  // 0x30B6
  CPC_INT_CNTX_ID                                        :TCPC_INT_CNTX_ID;                                  // 0x30B7
  CP_PQ_STATUS                                           :TCP_PQ_STATUS;                                     // 0x30B8
  CP_CPC_IC_BASE_LO                                      :TCP_CPC_IC_BASE_LO;                                // 0x30B9
  CP_CPC_IC_BASE_HI                                      :TCP_CPC_IC_BASE_HI;                                // 0x30BA
  CP_CPC_IC_BASE_CNTL                                    :TCP_CPC_IC_BASE_CNTL;                              // 0x30BB
  CP_CPC_IC_OP_CNTL                                      :TCP_CPC_IC_OP_CNTL;                                // 0x30BC
  CP_MEC1_F32_INT_DIS                                    :TCP_MEC1_F32_INT_DIS;                              // 0x30BD
  CP_MEC2_F32_INT_DIS                                    :TCP_MEC2_F32_INT_DIS;                              // 0x30BE
  CP_VMID_STATUS                                         :TCP_VMID_STATUS;                                   // 0x30BF
  REG_30C0_30C2                                          :array[0..2] of DWORD;                              // 0x30C0
  RLC_LB_CNTL                                            :TRLC_LB_CNTL;                                      // 0x30C3
  RLC_SAVE_AND_RESTORE_BASE                              :TRLC_SAVE_AND_RESTORE_BASE;                        // 0x30C4
  RLC_LB_CNTR_MAX                                        :TRLC_LB_CNTR_MAX;                                  // 0x30C5
  RLC_LB_CNTR_INIT                                       :TRLC_LB_CNTR_INIT;                                 // 0x30C6
  RLC_DRIVER_CPDMA_STATUS                                :TRLC_DRIVER_CPDMA_STATUS;                          // 0x30C7
  REG_30C8                                               :DWORD;                                             // 0x30C8
  RLC_DEBUG_SELECT                                       :TRLC_DEBUG_SELECT;                                 // 0x30C9
  RLC_DEBUG                                              :TRLC_DEBUG;                                        // 0x30CA
  REG_30CB_30CD                                          :array[0..2] of DWORD;                              // 0x30CB
  RLC_GPU_CLOCK_COUNT_LSB                                :TRLC_GPU_CLOCK_COUNT_LSB;                          // 0x30CE
  RLC_GPU_CLOCK_COUNT_MSB                                :TRLC_GPU_CLOCK_COUNT_MSB;                          // 0x30CF
  RLC_CAPTURE_GPU_CLOCK_COUNT                            :TRLC_CAPTURE_GPU_CLOCK_COUNT;                      // 0x30D0
  RLC_MC_CNTL                                            :TRLC_MC_CNTL;                                      // 0x30D1
  RLC_UCODE_CNTL                                         :TRLC_UCODE_CNTL;                                   // 0x30D2
  RLC_STAT                                               :TRLC_STAT;                                         // 0x30D3
  RLC_GPU_CLOCK_32_RES_SEL                               :TRLC_GPU_CLOCK_32_RES_SEL;                         // 0x30D4
  RLC_GPU_CLOCK_32                                       :TRLC_GPU_CLOCK_32;                                 // 0x30D5
  RLC_SOFT_RESET_GPU                                     :TRLC_SOFT_RESET_GPU;                               // 0x30D6
  RLC_PG_CNTL                                            :TRLC_PG_CNTL;                                      // 0x30D7
  RLC_MEM_SLP_CNTL                                       :TRLC_MEM_SLP_CNTL;                                 // 0x30D8
  RLC_PERFMON_CNTL                                       :TRLC_PERFMON_CNTL;                                 // 0x30D9
  RLC_PERFCOUNTER0_SELECT                                :TRLC_PERFCOUNTER0_SELECT;                          // 0x30DA
  REG_30DB_30DC                                          :array[0..1] of DWORD;                              // 0x30DB
  RLC_PERFCOUNTER1_SELECT                                :TRLC_PERFCOUNTER1_SELECT;                          // 0x30DD
  REG_30DE_30DF                                          :array[0..1] of DWORD;                              // 0x30DE
  CGTT_RLC_CLK_CTRL                                      :TCGTT_RLC_CLK_CTRL;                                // 0x30E0
  REG_30E1_30F5                                          :array[0..20] of DWORD;                             // 0x30E1
  RLC_LOAD_BALANCE_CNTR                                  :TRLC_LOAD_BALANCE_CNTR;                            // 0x30F6
  REG_30F7_30FF                                          :array[0..8] of DWORD;                              // 0x30F7
  RLC_CGTT_MGCG_OVERRIDE                                 :TRLC_CGTT_MGCG_OVERRIDE;                           // 0x3100
  RLC_CGCG_CGLS_CTRL                                     :TRLC_CGCG_CGLS_CTRL;                               // 0x3101
  RLC_CGCG_RAMP_CTRL                                     :TRLC_CGCG_RAMP_CTRL;                               // 0x3102
  RLC_DYN_PG_STATUS                                      :TRLC_DYN_PG_STATUS;                                // 0x3103
  RLC_DYN_PG_REQUEST                                     :TRLC_DYN_PG_REQUEST;                               // 0x3104
  REG_3105                                               :DWORD;                                             // 0x3105
  RLC_CU_STATUS                                          :TRLC_CU_STATUS;                                    // 0x3106
  RLC_LB_INIT_CU_MASK                                    :TRLC_LB_INIT_CU_MASK;                              // 0x3107
  RLC_LB_ALWAYS_ACTIVE_CU_MASK                           :TRLC_LB_ALWAYS_ACTIVE_CU_MASK;                     // 0x3108
  RLC_LB_PARAMS                                          :TRLC_LB_PARAMS;                                    // 0x3109
  RLC_THREAD1_DELAY                                      :TRLC_THREAD1_DELAY;                                // 0x310A
  RLC_PG_ALWAYS_ON_CU_MASK                               :TRLC_PG_ALWAYS_ON_CU_MASK;                         // 0x310B
  RLC_MAX_PG_CU                                          :TRLC_MAX_PG_CU;                                    // 0x310C
  RLC_AUTO_PG_CTRL                                       :TRLC_AUTO_PG_CTRL;                                 // 0x310D
  RLC_SMU_GRBM_REG_SAVE_CTRL                             :TRLC_SMU_GRBM_REG_SAVE_CTRL;                       // 0x310E
  RLC_SMU_PG_CTRL                                        :TRLC_SMU_PG_CTRL;                                  // 0x310F
  RLC_SMU_PG_WAKE_UP_CTRL                                :TRLC_SMU_PG_WAKE_UP_CTRL;                          // 0x3110
  RLC_SERDES_RD_MASTER_INDEX                             :TRLC_SERDES_RD_MASTER_INDEX;                       // 0x3111
  RLC_SERDES_RD_DATA_0                                   :TRLC_SERDES_RD_DATA_0;                             // 0x3112
  RLC_SERDES_RD_DATA_1                                   :TRLC_SERDES_RD_DATA_1;                             // 0x3113
  RLC_SERDES_RD_DATA_2                                   :TRLC_SERDES_RD_DATA_2;                             // 0x3114
  REG_3115_3116                                          :array[0..1] of DWORD;                              // 0x3115
  RLC_SERDES_WR_CTRL                                     :TRLC_SERDES_WR_CTRL;                               // 0x3117
  RLC_SERDES_WR_DATA                                     :TRLC_SERDES_WR_DATA;                               // 0x3118
  REG_3119_31BF                                          :array[0..166] of DWORD;                            // 0x3119
  SPI_ARB_PRIORITY                                       :TSPI_ARB_PRIORITY;                                 // 0x31C0
  SPI_ARB_CYCLES_0                                       :TSPI_ARB_CYCLES_0;                                 // 0x31C1
  SPI_ARB_CYCLES_1                                       :TSPI_ARB_CYCLES_1;                                 // 0x31C2
  SPI_CDBG_SYS_GFX                                       :TSPI_CDBG_SYS_GFX;                                 // 0x31C3
  SPI_CDBG_SYS_HP3D                                      :TSPI_CDBG_SYS_HP3D;                                // 0x31C4
  SPI_CDBG_SYS_CS0                                       :TSPI_CDBG_SYS_CS0;                                 // 0x31C5
  SPI_CDBG_SYS_CS1                                       :TSPI_CDBG_SYS_CS1;                                 // 0x31C6
  SPI_WCL_PIPE_PERCENT_GFX                               :TSPI_WCL_PIPE_PERCENT_GFX;                         // 0x31C7
  SPI_WCL_PIPE_PERCENT_HP3D                              :TSPI_WCL_PIPE_PERCENT_HP3D;                        // 0x31C8
  SPI_WCL_PIPE_PERCENT_CS0                               :TSPI_WCL_PIPE_PERCENT_CS0;                         // 0x31C9
  SPI_WCL_PIPE_PERCENT_CS1                               :TSPI_WCL_PIPE_PERCENT_CS1;                         // 0x31CA
  SPI_WCL_PIPE_PERCENT_CS2                               :TSPI_WCL_PIPE_PERCENT_CS2;                         // 0x31CB
  SPI_WCL_PIPE_PERCENT_CS3                               :TSPI_WCL_PIPE_PERCENT_CS3;                         // 0x31CC
  SPI_WCL_PIPE_PERCENT_CS4                               :TSPI_WCL_PIPE_PERCENT_CS4;                         // 0x31CD
  SPI_WCL_PIPE_PERCENT_CS5                               :TSPI_WCL_PIPE_PERCENT_CS5;                         // 0x31CE
  SPI_WCL_PIPE_PERCENT_CS6                               :TSPI_WCL_PIPE_PERCENT_CS6;                         // 0x31CF
  SPI_WCL_PIPE_PERCENT_CS7                               :TSPI_WCL_PIPE_PERCENT_CS7;                         // 0x31D0
  SPI_GDBG_WAVE_CNTL                                     :TSPI_GDBG_WAVE_CNTL;                               // 0x31D1
  SPI_GDBG_TRAP_CONFIG                                   :TSPI_GDBG_TRAP_CONFIG;                             // 0x31D2
  SPI_GDBG_TRAP_MASK                                     :TSPI_GDBG_TRAP_MASK;                               // 0x31D3
  SPI_GDBG_TBA_LO                                        :TSPI_GDBG_TBA_LO;                                  // 0x31D4
  SPI_GDBG_TBA_HI                                        :TSPI_GDBG_TBA_HI;                                  // 0x31D5
  SPI_GDBG_TMA_LO                                        :TSPI_GDBG_TMA_LO;                                  // 0x31D6
  SPI_GDBG_TMA_HI                                        :TSPI_GDBG_TMA_HI;                                  // 0x31D7
  SPI_GDBG_TRAP_DATA0                                    :TSPI_GDBG_TRAP_DATA0;                              // 0x31D8
  SPI_GDBG_TRAP_DATA1                                    :TSPI_GDBG_TRAP_DATA1;                              // 0x31D9
  SPI_RESET_DEBUG                                        :TSPI_RESET_DEBUG;                                  // 0x31DA
  SPI_COMPUTE_QUEUE_RESET                                :TSPI_COMPUTE_QUEUE_RESET;                          // 0x31DB
  SPI_RESOURCE_RESERVE_CU_0                              :TSPI_RESOURCE_RESERVE_CU_0;                        // 0x31DC
  SPI_RESOURCE_RESERVE_CU_1                              :TSPI_RESOURCE_RESERVE_CU_1;                        // 0x31DD
  SPI_RESOURCE_RESERVE_CU_2                              :TSPI_RESOURCE_RESERVE_CU_2;                        // 0x31DE
  SPI_RESOURCE_RESERVE_CU_3                              :TSPI_RESOURCE_RESERVE_CU_3;                        // 0x31DF
  SPI_RESOURCE_RESERVE_CU_4                              :TSPI_RESOURCE_RESERVE_CU_4;                        // 0x31E0
  SPI_RESOURCE_RESERVE_CU_5                              :TSPI_RESOURCE_RESERVE_CU_5;                        // 0x31E1
  SPI_RESOURCE_RESERVE_CU_6                              :TSPI_RESOURCE_RESERVE_CU_6;                        // 0x31E2
  SPI_RESOURCE_RESERVE_CU_7                              :TSPI_RESOURCE_RESERVE_CU_7;                        // 0x31E3
  SPI_RESOURCE_RESERVE_CU_8                              :TSPI_RESOURCE_RESERVE_CU_8;                        // 0x31E4
  SPI_RESOURCE_RESERVE_CU_9                              :TSPI_RESOURCE_RESERVE_CU_9;                        // 0x31E5
  SPI_RESOURCE_RESERVE_EN_CU_0                           :TSPI_RESOURCE_RESERVE_EN_CU_0;                     // 0x31E6
  SPI_RESOURCE_RESERVE_EN_CU_1                           :TSPI_RESOURCE_RESERVE_EN_CU_1;                     // 0x31E7
  SPI_RESOURCE_RESERVE_EN_CU_2                           :TSPI_RESOURCE_RESERVE_EN_CU_2;                     // 0x31E8
  SPI_RESOURCE_RESERVE_EN_CU_3                           :TSPI_RESOURCE_RESERVE_EN_CU_3;                     // 0x31E9
  SPI_RESOURCE_RESERVE_EN_CU_4                           :TSPI_RESOURCE_RESERVE_EN_CU_4;                     // 0x31EA
  SPI_RESOURCE_RESERVE_EN_CU_5                           :TSPI_RESOURCE_RESERVE_EN_CU_5;                     // 0x31EB
  SPI_RESOURCE_RESERVE_EN_CU_6                           :TSPI_RESOURCE_RESERVE_EN_CU_6;                     // 0x31EC
  SPI_RESOURCE_RESERVE_EN_CU_7                           :TSPI_RESOURCE_RESERVE_EN_CU_7;                     // 0x31ED
  SPI_RESOURCE_RESERVE_EN_CU_8                           :TSPI_RESOURCE_RESERVE_EN_CU_8;                     // 0x31EE
  SPI_RESOURCE_RESERVE_EN_CU_9                           :TSPI_RESOURCE_RESERVE_EN_CU_9;                     // 0x31EF
  SPI_RESOURCE_RESERVE_CU_10                             :TSPI_RESOURCE_RESERVE_CU_10;                       // 0x31F0
  SPI_RESOURCE_RESERVE_CU_11                             :TSPI_RESOURCE_RESERVE_CU_11;                       // 0x31F1
  SPI_RESOURCE_RESERVE_EN_CU_10                          :TSPI_RESOURCE_RESERVE_EN_CU_10;                    // 0x31F2
  SPI_RESOURCE_RESERVE_EN_CU_11                          :TSPI_RESOURCE_RESERVE_EN_CU_11;                    // 0x31F3
  SPI_RESOURCE_RESERVE_CU_12                             :TSPI_RESOURCE_RESERVE_CU_12;                       // 0x31F4
  SPI_RESOURCE_RESERVE_CU_13                             :TSPI_RESOURCE_RESERVE_CU_13;                       // 0x31F5
  SPI_RESOURCE_RESERVE_CU_14                             :TSPI_RESOURCE_RESERVE_CU_14;                       // 0x31F6
  SPI_RESOURCE_RESERVE_CU_15                             :TSPI_RESOURCE_RESERVE_CU_15;                       // 0x31F7
  SPI_RESOURCE_RESERVE_EN_CU_12                          :TSPI_RESOURCE_RESERVE_EN_CU_12;                    // 0x31F8
  SPI_RESOURCE_RESERVE_EN_CU_13                          :TSPI_RESOURCE_RESERVE_EN_CU_13;                    // 0x31F9
  SPI_RESOURCE_RESERVE_EN_CU_14                          :TSPI_RESOURCE_RESERVE_EN_CU_14;                    // 0x31FA
  SPI_RESOURCE_RESERVE_EN_CU_15                          :TSPI_RESOURCE_RESERVE_EN_CU_15;                    // 0x31FB
  SPI_COMPUTE_WF_CTX_SAVE                                :TSPI_COMPUTE_WF_CTX_SAVE;                          // 0x31FC
  REG_31FD_323F                                          :array[0..66] of DWORD;                             // 0x31FD
  CP_HPD_ROQ_OFFSETS                                     :TCP_HPD_ROQ_OFFSETS;                               // 0x3240
  CP_HPD_STATUS0                                         :TCP_HPD_STATUS0;                                   // 0x3241
  REG_3242_3244                                          :array[0..2] of DWORD;                              // 0x3242
  CP_MQD_BASE_ADDR                                       :TCP_MQD_BASE_ADDR;                                 // 0x3245
  CP_MQD_BASE_ADDR_HI                                    :TCP_MQD_BASE_ADDR_HI;                              // 0x3246
  CP_HQD_ACTIVE                                          :TCP_HQD_ACTIVE;                                    // 0x3247
  CP_HQD_VMID                                            :TCP_HQD_VMID;                                      // 0x3248
  CP_HQD_PERSISTENT_STATE                                :TCP_HQD_PERSISTENT_STATE;                          // 0x3249
  CP_HQD_PIPE_PRIORITY                                   :TCP_HQD_PIPE_PRIORITY;                             // 0x324A
  CP_HQD_QUEUE_PRIORITY                                  :TCP_HQD_QUEUE_PRIORITY;                            // 0x324B
  CP_HQD_QUANTUM                                         :TCP_HQD_QUANTUM;                                   // 0x324C
  CP_HQD_PQ_BASE                                         :TCP_HQD_PQ_BASE;                                   // 0x324D
  CP_HQD_PQ_BASE_HI                                      :TCP_HQD_PQ_BASE_HI;                                // 0x324E
  CP_HQD_PQ_RPTR                                         :TCP_HQD_PQ_RPTR;                                   // 0x324F
  CP_HQD_PQ_RPTR_REPORT_ADDR                             :TCP_HQD_PQ_RPTR_REPORT_ADDR;                       // 0x3250
  CP_HQD_PQ_RPTR_REPORT_ADDR_HI                          :TCP_HQD_PQ_RPTR_REPORT_ADDR_HI;                    // 0x3251
  CP_HQD_PQ_WPTR_POLL_ADDR                               :TCP_HQD_PQ_WPTR_POLL_ADDR;                         // 0x3252
  CP_HQD_PQ_WPTR_POLL_ADDR_HI                            :TCP_HQD_PQ_WPTR_POLL_ADDR_HI;                      // 0x3253
  CP_HQD_PQ_DOORBELL_CONTROL                             :TCP_HQD_PQ_DOORBELL_CONTROL;                       // 0x3254
  CP_HQD_PQ_WPTR                                         :TCP_HQD_PQ_WPTR;                                   // 0x3255
  CP_HQD_PQ_CONTROL                                      :TCP_HQD_PQ_CONTROL;                                // 0x3256
  CP_HQD_IB_BASE_ADDR                                    :TCP_HQD_IB_BASE_ADDR;                              // 0x3257
  CP_HQD_IB_BASE_ADDR_HI                                 :TCP_HQD_IB_BASE_ADDR_HI;                           // 0x3258
  CP_HQD_IB_RPTR                                         :TCP_HQD_IB_RPTR;                                   // 0x3259
  CP_HQD_IB_CONTROL                                      :TCP_HQD_IB_CONTROL;                                // 0x325A
  CP_HQD_IQ_TIMER                                        :TCP_HQD_IQ_TIMER;                                  // 0x325B
  CP_HQD_IQ_RPTR                                         :TCP_HQD_IQ_RPTR;                                   // 0x325C
  CP_HQD_DEQUEUE_REQUEST                                 :TCP_HQD_DEQUEUE_REQUEST;                           // 0x325D
  CP_HQD_DMA_OFFLOAD                                     :TCP_HQD_DMA_OFFLOAD;                               // 0x325E
  CP_HQD_SEMA_CMD                                        :TCP_HQD_SEMA_CMD;                                  // 0x325F
  CP_HQD_MSG_TYPE                                        :TCP_HQD_MSG_TYPE;                                  // 0x3260
  CP_HQD_ATOMIC0_PREOP_LO                                :TCP_HQD_ATOMIC0_PREOP_LO;                          // 0x3261
  CP_HQD_ATOMIC0_PREOP_HI                                :TCP_HQD_ATOMIC0_PREOP_HI;                          // 0x3262
  CP_HQD_ATOMIC1_PREOP_LO                                :TCP_HQD_ATOMIC1_PREOP_LO;                          // 0x3263
  CP_HQD_ATOMIC1_PREOP_HI                                :TCP_HQD_ATOMIC1_PREOP_HI;                          // 0x3264
  CP_HQD_HQ_SCHEDULER0                                   :TCP_HQD_HQ_SCHEDULER0;                             // 0x3265
  CP_HQD_HQ_SCHEDULER1                                   :TCP_HQD_HQ_SCHEDULER1;                             // 0x3266
  CP_MQD_CONTROL                                         :TCP_MQD_CONTROL;                                   // 0x3267
  CP_HQD_HQ_STATUS1                                      :TCP_HQD_HQ_STATUS1;                                // 0x3268
  CP_HQD_HQ_CONTROL1                                     :TCP_HQD_HQ_CONTROL1;                               // 0x3269
  CP_HQD_EOP_BASE_ADDR                                   :TCP_HQD_EOP_BASE_ADDR;                             // 0x326A
  CP_HQD_EOP_BASE_ADDR_HI                                :TCP_HQD_EOP_BASE_ADDR_HI;                          // 0x326B
  CP_HQD_EOP_CONTROL                                     :TCP_HQD_EOP_CONTROL;                               // 0x326C
  CP_HQD_EOP_RPTR                                        :TCP_HQD_EOP_RPTR;                                  // 0x326D
  CP_HQD_EOP_WPTR                                        :TCP_HQD_EOP_WPTR;                                  // 0x326E
  CP_HQD_EOP_EVENTS                                      :TCP_HQD_EOP_EVENTS;                                // 0x326F
  CP_HQD_CTX_SAVE_BASE_ADDR_LO                           :TCP_HQD_CTX_SAVE_BASE_ADDR_LO;                     // 0x3270
  CP_HQD_CTX_SAVE_BASE_ADDR_HI                           :TCP_HQD_CTX_SAVE_BASE_ADDR_HI;                     // 0x3271
  CP_HQD_CTX_SAVE_CONTROL                                :TCP_HQD_CTX_SAVE_CONTROL;                          // 0x3272
  CP_HQD_CNTL_STACK_OFFSET                               :TCP_HQD_CNTL_STACK_OFFSET;                         // 0x3273
  CP_HQD_CNTL_STACK_SIZE                                 :TCP_HQD_CNTL_STACK_SIZE;                           // 0x3274
  CP_HQD_WG_STATE_OFFSET                                 :TCP_HQD_WG_STATE_OFFSET;                           // 0x3275
  CP_HQD_CTX_SAVE_SIZE                                   :TCP_HQD_CTX_SAVE_SIZE;                             // 0x3276
  CP_HQD_GDS_RESOURCE_STATE                              :TCP_HQD_GDS_RESOURCE_STATE;                        // 0x3277
  CP_HQD_ERROR                                           :TCP_HQD_ERROR;                                     // 0x3278
  CP_HQD_EOP_WPTR_MEM                                    :TCP_HQD_EOP_WPTR_MEM;                              // 0x3279
  CP_HQD_EOP_DONES                                       :TCP_HQD_EOP_DONES;                                 // 0x327A
  REG_327B_327F                                          :array[0..4] of DWORD;                              // 0x327B
  DIDT_IND_INDEX                                         :TDIDT_IND_INDEX;                                   // 0x3280
  DIDT_IND_DATA                                          :TDIDT_IND_DATA;                                    // 0x3281
  REG_3282_3291                                          :array[0..15] of DWORD;                             // 0x3282
  GC_CAC_CGTT_CLK_CTRL                                   :TGC_CAC_CGTT_CLK_CTRL;                             // 0x3292
  SE_CAC_CGTT_CLK_CTRL                                   :TSE_CAC_CGTT_CLK_CTRL;                             // 0x3293
  REG_3294_3295                                          :array[0..1] of DWORD;                              // 0x3294
  GC_CAC_LKG_AGGR_LOWER                                  :TGC_CAC_LKG_AGGR_LOWER;                            // 0x3296
  GC_CAC_LKG_AGGR_UPPER                                  :TGC_CAC_LKG_AGGR_UPPER;                            // 0x3297
  REG_3298_329F                                          :array[0..7] of DWORD;                              // 0x3298
  TCP_WATCH0_ADDR_H                                      :TTCP_WATCH0_ADDR_H;                                // 0x32A0
  TCP_WATCH0_ADDR_L                                      :TTCP_WATCH0_ADDR_L;                                // 0x32A1
  TCP_WATCH0_CNTL                                        :TTCP_WATCH0_CNTL;                                  // 0x32A2
  TCP_WATCH1_ADDR_H                                      :TTCP_WATCH1_ADDR_H;                                // 0x32A3
  TCP_WATCH1_ADDR_L                                      :TTCP_WATCH1_ADDR_L;                                // 0x32A4
  TCP_WATCH1_CNTL                                        :TTCP_WATCH1_CNTL;                                  // 0x32A5
  TCP_WATCH2_ADDR_H                                      :TTCP_WATCH2_ADDR_H;                                // 0x32A6
  TCP_WATCH2_ADDR_L                                      :TTCP_WATCH2_ADDR_L;                                // 0x32A7
  TCP_WATCH2_CNTL                                        :TTCP_WATCH2_CNTL;                                  // 0x32A8
  TCP_WATCH3_ADDR_H                                      :TTCP_WATCH3_ADDR_H;                                // 0x32A9
  TCP_WATCH3_ADDR_L                                      :TTCP_WATCH3_ADDR_L;                                // 0x32AA
  TCP_WATCH3_CNTL                                        :TTCP_WATCH3_CNTL;                                  // 0x32AB
  REG_32AC_32AF                                          :array[0..3] of DWORD;                              // 0x32AC
  TCP_GATCL1_CNTL                                        :TTCP_GATCL1_CNTL;                                  // 0x32B0
  TCP_ATC_EDC_GATCL1_CNT                                 :TTCP_ATC_EDC_GATCL1_CNT;                           // 0x32B1
  TCP_GATCL1_DSM_CNTL                                    :TTCP_GATCL1_DSM_CNTL;                              // 0x32B2
  TCP_DSM_CNTL                                           :TTCP_DSM_CNTL;                                     // 0x32B3
  TCP_CNTL2                                              :TTCP_CNTL2;                                        // 0x32B4
  REG_32B5_32FF                                          :array[0..74] of DWORD;                             // 0x32B5
  GDS_VMID0_BASE                                         :TGDS_VMID0_BASE;                                   // 0x3300
  GDS_VMID0_SIZE                                         :TGDS_VMID0_SIZE;                                   // 0x3301
  GDS_VMID1_BASE                                         :TGDS_VMID1_BASE;                                   // 0x3302
  GDS_VMID1_SIZE                                         :TGDS_VMID1_SIZE;                                   // 0x3303
  GDS_VMID2_BASE                                         :TGDS_VMID2_BASE;                                   // 0x3304
  GDS_VMID2_SIZE                                         :TGDS_VMID2_SIZE;                                   // 0x3305
  GDS_VMID3_BASE                                         :TGDS_VMID3_BASE;                                   // 0x3306
  GDS_VMID3_SIZE                                         :TGDS_VMID3_SIZE;                                   // 0x3307
  GDS_VMID4_BASE                                         :TGDS_VMID4_BASE;                                   // 0x3308
  GDS_VMID4_SIZE                                         :TGDS_VMID4_SIZE;                                   // 0x3309
  GDS_VMID5_BASE                                         :TGDS_VMID5_BASE;                                   // 0x330A
  GDS_VMID5_SIZE                                         :TGDS_VMID5_SIZE;                                   // 0x330B
  GDS_VMID6_BASE                                         :TGDS_VMID6_BASE;                                   // 0x330C
  GDS_VMID6_SIZE                                         :TGDS_VMID6_SIZE;                                   // 0x330D
  GDS_VMID7_BASE                                         :TGDS_VMID7_BASE;                                   // 0x330E
  GDS_VMID7_SIZE                                         :TGDS_VMID7_SIZE;                                   // 0x330F
  GDS_VMID8_BASE                                         :TGDS_VMID8_BASE;                                   // 0x3310
  GDS_VMID8_SIZE                                         :TGDS_VMID8_SIZE;                                   // 0x3311
  GDS_VMID9_BASE                                         :TGDS_VMID9_BASE;                                   // 0x3312
  GDS_VMID9_SIZE                                         :TGDS_VMID9_SIZE;                                   // 0x3313
  GDS_VMID10_BASE                                        :TGDS_VMID10_BASE;                                  // 0x3314
  GDS_VMID10_SIZE                                        :TGDS_VMID10_SIZE;                                  // 0x3315
  GDS_VMID11_BASE                                        :TGDS_VMID11_BASE;                                  // 0x3316
  GDS_VMID11_SIZE                                        :TGDS_VMID11_SIZE;                                  // 0x3317
  GDS_VMID12_BASE                                        :TGDS_VMID12_BASE;                                  // 0x3318
  GDS_VMID12_SIZE                                        :TGDS_VMID12_SIZE;                                  // 0x3319
  GDS_VMID13_BASE                                        :TGDS_VMID13_BASE;                                  // 0x331A
  GDS_VMID13_SIZE                                        :TGDS_VMID13_SIZE;                                  // 0x331B
  GDS_VMID14_BASE                                        :TGDS_VMID14_BASE;                                  // 0x331C
  GDS_VMID14_SIZE                                        :TGDS_VMID14_SIZE;                                  // 0x331D
  GDS_VMID15_BASE                                        :TGDS_VMID15_BASE;                                  // 0x331E
  GDS_VMID15_SIZE                                        :TGDS_VMID15_SIZE;                                  // 0x331F
  GDS_GWS_VMID0                                          :TGDS_GWS_VMID0;                                    // 0x3320
  GDS_GWS_VMID1                                          :TGDS_GWS_VMID1;                                    // 0x3321
  GDS_GWS_VMID2                                          :TGDS_GWS_VMID2;                                    // 0x3322
  GDS_GWS_VMID3                                          :TGDS_GWS_VMID3;                                    // 0x3323
  GDS_GWS_VMID4                                          :TGDS_GWS_VMID4;                                    // 0x3324
  GDS_GWS_VMID5                                          :TGDS_GWS_VMID5;                                    // 0x3325
  GDS_GWS_VMID6                                          :TGDS_GWS_VMID6;                                    // 0x3326
  GDS_GWS_VMID7                                          :TGDS_GWS_VMID7;                                    // 0x3327
  GDS_GWS_VMID8                                          :TGDS_GWS_VMID8;                                    // 0x3328
  GDS_GWS_VMID9                                          :TGDS_GWS_VMID9;                                    // 0x3329
  GDS_GWS_VMID10                                         :TGDS_GWS_VMID10;                                   // 0x332A
  GDS_GWS_VMID11                                         :TGDS_GWS_VMID11;                                   // 0x332B
  GDS_GWS_VMID12                                         :TGDS_GWS_VMID12;                                   // 0x332C
  GDS_GWS_VMID13                                         :TGDS_GWS_VMID13;                                   // 0x332D
  GDS_GWS_VMID14                                         :TGDS_GWS_VMID14;                                   // 0x332E
  GDS_GWS_VMID15                                         :TGDS_GWS_VMID15;                                   // 0x332F
  GDS_OA_VMID0                                           :TGDS_OA_VMID0;                                     // 0x3330
  GDS_OA_VMID1                                           :TGDS_OA_VMID1;                                     // 0x3331
  GDS_OA_VMID2                                           :TGDS_OA_VMID2;                                     // 0x3332
  GDS_OA_VMID3                                           :TGDS_OA_VMID3;                                     // 0x3333
  GDS_OA_VMID4                                           :TGDS_OA_VMID4;                                     // 0x3334
  GDS_OA_VMID5                                           :TGDS_OA_VMID5;                                     // 0x3335
  GDS_OA_VMID6                                           :TGDS_OA_VMID6;                                     // 0x3336
  GDS_OA_VMID7                                           :TGDS_OA_VMID7;                                     // 0x3337
  GDS_OA_VMID8                                           :TGDS_OA_VMID8;                                     // 0x3338
  GDS_OA_VMID9                                           :TGDS_OA_VMID9;                                     // 0x3339
  GDS_OA_VMID10                                          :TGDS_OA_VMID10;                                    // 0x333A
  GDS_OA_VMID11                                          :TGDS_OA_VMID11;                                    // 0x333B
  GDS_OA_VMID12                                          :TGDS_OA_VMID12;                                    // 0x333C
  GDS_OA_VMID13                                          :TGDS_OA_VMID13;                                    // 0x333D
  GDS_OA_VMID14                                          :TGDS_OA_VMID14;                                    // 0x333E
  GDS_OA_VMID15                                          :TGDS_OA_VMID15;                                    // 0x333F
  REG_3340_3343                                          :array[0..3] of DWORD;                              // 0x3340
  GDS_GWS_RESET0                                         :TGDS_GWS_RESET0;                                   // 0x3344
  GDS_GWS_RESET1                                         :TGDS_GWS_RESET1;                                   // 0x3345
  GDS_GWS_RESOURCE_RESET                                 :TGDS_GWS_RESOURCE_RESET;                           // 0x3346
  REG_3347                                               :DWORD;                                             // 0x3347
  GDS_COMPUTE_MAX_WAVE_ID                                :TGDS_COMPUTE_MAX_WAVE_ID;                          // 0x3348
  GDS_OA_RESET_MASK                                      :TGDS_OA_RESET_MASK;                                // 0x3349
  GDS_OA_RESET                                           :TGDS_OA_RESET;                                     // 0x334A
  GDS_ENHANCE                                            :TGDS_ENHANCE;                                      // 0x334B
  GDS_OA_CGPG_RESTORE                                    :TGDS_OA_CGPG_RESTORE;                              // 0x334C
  GDS_CS_CTXSW_STATUS                                    :TGDS_CS_CTXSW_STATUS;                              // 0x334D
  GDS_CS_CTXSW_CNT0                                      :TGDS_CS_CTXSW_CNT0;                                // 0x334E
  GDS_CS_CTXSW_CNT1                                      :TGDS_CS_CTXSW_CNT1;                                // 0x334F
  GDS_CS_CTXSW_CNT2                                      :TGDS_CS_CTXSW_CNT2;                                // 0x3350
  GDS_CS_CTXSW_CNT3                                      :TGDS_CS_CTXSW_CNT3;                                // 0x3351
  GDS_GFX_CTXSW_STATUS                                   :TGDS_GFX_CTXSW_STATUS;                             // 0x3352
  GDS_VS_CTXSW_CNT0                                      :TGDS_VS_CTXSW_CNT0;                                // 0x3353
  GDS_VS_CTXSW_CNT1                                      :TGDS_VS_CTXSW_CNT1;                                // 0x3354
  GDS_VS_CTXSW_CNT2                                      :TGDS_VS_CTXSW_CNT2;                                // 0x3355
  GDS_VS_CTXSW_CNT3                                      :TGDS_VS_CTXSW_CNT3;                                // 0x3356
  GDS_PS0_CTXSW_CNT0                                     :TGDS_PS0_CTXSW_CNT0;                               // 0x3357
  GDS_PS0_CTXSW_CNT1                                     :TGDS_PS0_CTXSW_CNT1;                               // 0x3358
  GDS_PS0_CTXSW_CNT2                                     :TGDS_PS0_CTXSW_CNT2;                               // 0x3359
  GDS_PS0_CTXSW_CNT3                                     :TGDS_PS0_CTXSW_CNT3;                               // 0x335A
  GDS_PS1_CTXSW_CNT0                                     :TGDS_PS1_CTXSW_CNT0;                               // 0x335B
  GDS_PS1_CTXSW_CNT1                                     :TGDS_PS1_CTXSW_CNT1;                               // 0x335C
  GDS_PS1_CTXSW_CNT2                                     :TGDS_PS1_CTXSW_CNT2;                               // 0x335D
  GDS_PS1_CTXSW_CNT3                                     :TGDS_PS1_CTXSW_CNT3;                               // 0x335E
  GDS_PS2_CTXSW_CNT0                                     :TGDS_PS2_CTXSW_CNT0;                               // 0x335F
  GDS_PS2_CTXSW_CNT1                                     :TGDS_PS2_CTXSW_CNT1;                               // 0x3360
  GDS_PS2_CTXSW_CNT2                                     :TGDS_PS2_CTXSW_CNT2;                               // 0x3361
  GDS_PS2_CTXSW_CNT3                                     :TGDS_PS2_CTXSW_CNT3;                               // 0x3362
  GDS_PS3_CTXSW_CNT0                                     :TGDS_PS3_CTXSW_CNT0;                               // 0x3363
  GDS_PS3_CTXSW_CNT1                                     :TGDS_PS3_CTXSW_CNT1;                               // 0x3364
  GDS_PS3_CTXSW_CNT2                                     :TGDS_PS3_CTXSW_CNT2;                               // 0x3365
  GDS_PS3_CTXSW_CNT3                                     :TGDS_PS3_CTXSW_CNT3;                               // 0x3366
  GDS_PS4_CTXSW_CNT0                                     :TGDS_PS4_CTXSW_CNT0;                               // 0x3367
  GDS_PS4_CTXSW_CNT1                                     :TGDS_PS4_CTXSW_CNT1;                               // 0x3368
  GDS_PS4_CTXSW_CNT2                                     :TGDS_PS4_CTXSW_CNT2;                               // 0x3369
  GDS_PS4_CTXSW_CNT3                                     :TGDS_PS4_CTXSW_CNT3;                               // 0x336A
  GDS_PS5_CTXSW_CNT0                                     :TGDS_PS5_CTXSW_CNT0;                               // 0x336B
  GDS_PS5_CTXSW_CNT1                                     :TGDS_PS5_CTXSW_CNT1;                               // 0x336C
  GDS_PS5_CTXSW_CNT2                                     :TGDS_PS5_CTXSW_CNT2;                               // 0x336D
  GDS_PS5_CTXSW_CNT3                                     :TGDS_PS5_CTXSW_CNT3;                               // 0x336E
  GDS_PS6_CTXSW_CNT0                                     :TGDS_PS6_CTXSW_CNT0;                               // 0x336F
  GDS_PS6_CTXSW_CNT1                                     :TGDS_PS6_CTXSW_CNT1;                               // 0x3370
  GDS_PS6_CTXSW_CNT2                                     :TGDS_PS6_CTXSW_CNT2;                               // 0x3371
  GDS_PS6_CTXSW_CNT3                                     :TGDS_PS6_CTXSW_CNT3;                               // 0x3372
  GDS_PS7_CTXSW_CNT0                                     :TGDS_PS7_CTXSW_CNT0;                               // 0x3373
  GDS_PS7_CTXSW_CNT1                                     :TGDS_PS7_CTXSW_CNT1;                               // 0x3374
  GDS_PS7_CTXSW_CNT2                                     :TGDS_PS7_CTXSW_CNT2;                               // 0x3375
  GDS_PS7_CTXSW_CNT3                                     :TGDS_PS7_CTXSW_CNT3;                               // 0x3376
  REG_3377_337F                                          :array[0..8] of DWORD;                              // 0x3377
  RAS_SIGNATURE_CONTROL                                  :TRAS_SIGNATURE_CONTROL;                            // 0x3380
  RAS_SIGNATURE_MASK                                     :TRAS_SIGNATURE_MASK;                               // 0x3381
  RAS_SX_SIGNATURE0                                      :TRAS_SX_SIGNATURE0;                                // 0x3382
  RAS_SX_SIGNATURE1                                      :TRAS_SX_SIGNATURE1;                                // 0x3383
  RAS_SX_SIGNATURE2                                      :TRAS_SX_SIGNATURE2;                                // 0x3384
  RAS_SX_SIGNATURE3                                      :TRAS_SX_SIGNATURE3;                                // 0x3385
  REG_3386_338A                                          :array[0..4] of DWORD;                              // 0x3386
  RAS_DB_SIGNATURE0                                      :TRAS_DB_SIGNATURE0;                                // 0x338B
  RAS_PA_SIGNATURE0                                      :TRAS_PA_SIGNATURE0;                                // 0x338C
  RAS_VGT_SIGNATURE0                                     :TRAS_VGT_SIGNATURE0;                               // 0x338D
  RAS_SQ_SIGNATURE0                                      :TRAS_SQ_SIGNATURE0;                                // 0x338E
  RAS_SC_SIGNATURE0                                      :TRAS_SC_SIGNATURE0;                                // 0x338F
  RAS_SC_SIGNATURE1                                      :TRAS_SC_SIGNATURE1;                                // 0x3390
  RAS_SC_SIGNATURE2                                      :TRAS_SC_SIGNATURE2;                                // 0x3391
  RAS_SC_SIGNATURE3                                      :TRAS_SC_SIGNATURE3;                                // 0x3392
  RAS_SC_SIGNATURE4                                      :TRAS_SC_SIGNATURE4;                                // 0x3393
  RAS_SC_SIGNATURE5                                      :TRAS_SC_SIGNATURE5;                                // 0x3394
  RAS_SC_SIGNATURE6                                      :TRAS_SC_SIGNATURE6;                                // 0x3395
  RAS_SC_SIGNATURE7                                      :TRAS_SC_SIGNATURE7;                                // 0x3396
  RAS_IA_SIGNATURE0                                      :TRAS_IA_SIGNATURE0;                                // 0x3397
  RAS_IA_SIGNATURE1                                      :TRAS_IA_SIGNATURE1;                                // 0x3398
  RAS_SPI_SIGNATURE0                                     :TRAS_SPI_SIGNATURE0;                               // 0x3399
  RAS_SPI_SIGNATURE1                                     :TRAS_SPI_SIGNATURE1;                               // 0x339A
  RAS_TA_SIGNATURE0                                      :TRAS_TA_SIGNATURE0;                                // 0x339B
  RAS_TD_SIGNATURE0                                      :TRAS_TD_SIGNATURE0;                                // 0x339C
  RAS_CB_SIGNATURE0                                      :TRAS_CB_SIGNATURE0;                                // 0x339D
  RAS_BCI_SIGNATURE0                                     :TRAS_BCI_SIGNATURE0;                               // 0x339E
  RAS_BCI_SIGNATURE1                                     :TRAS_BCI_SIGNATURE1;                               // 0x339F
  RAS_TA_SIGNATURE1                                      :TRAS_TA_SIGNATURE1;                                // 0x33A0
  REG_33A1_33FF                                          :array[0..94] of DWORD;                             // 0x33A1
  SDMA0_UCODE_ADDR                                       :TSDMA0_UCODE_ADDR;                                 // 0x3400
  SDMA0_UCODE_DATA                                       :TSDMA0_UCODE_DATA;                                 // 0x3401
  SDMA0_POWER_CNTL                                       :TSDMA0_POWER_CNTL;                                 // 0x3402
  SDMA0_CLK_CTRL                                         :TSDMA0_CLK_CTRL;                                   // 0x3403
  SDMA0_CNTL                                             :TSDMA0_CNTL;                                       // 0x3404
  SDMA0_CHICKEN_BITS                                     :TSDMA0_CHICKEN_BITS;                               // 0x3405
  SDMA0_TILING_CONFIG                                    :TSDMA0_TILING_CONFIG;                              // 0x3406
  SDMA0_HASH                                             :TSDMA0_HASH;                                       // 0x3407
  REG_3408                                               :DWORD;                                             // 0x3408
  SDMA0_SEM_WAIT_FAIL_TIMER_CNTL                         :TSDMA0_SEM_WAIT_FAIL_TIMER_CNTL;                   // 0x3409
  SDMA0_RB_RPTR_FETCH                                    :TSDMA0_RB_RPTR_FETCH;                              // 0x340A
  SDMA0_IB_OFFSET_FETCH                                  :TSDMA0_IB_OFFSET_FETCH;                            // 0x340B
  SDMA0_PROGRAM                                          :TSDMA0_PROGRAM;                                    // 0x340C
  SDMA0_STATUS_REG                                       :TSDMA0_STATUS_REG;                                 // 0x340D
  SDMA0_STATUS1_REG                                      :TSDMA0_STATUS1_REG;                                // 0x340E
  SDMA0_RD_BURST_CNTL                                    :TSDMA0_RD_BURST_CNTL;                              // 0x340F
  REG_3410_3411                                          :array[0..1] of DWORD;                              // 0x3410
  SDMA0_F32_CNTL                                         :TSDMA0_F32_CNTL;                                   // 0x3412
  SDMA0_FREEZE                                           :TSDMA0_FREEZE;                                     // 0x3413
  SDMA0_PHASE0_QUANTUM                                   :TSDMA0_PHASE0_QUANTUM;                             // 0x3414
  SDMA0_PHASE1_QUANTUM                                   :TSDMA0_PHASE1_QUANTUM;                             // 0x3415
  SDMA_POWER_GATING                                      :TSDMA_POWER_GATING;                                // 0x3416
  SDMA_PGFSM_CONFIG                                      :TSDMA_PGFSM_CONFIG;                                // 0x3417
  SDMA_PGFSM_WRITE                                       :TSDMA_PGFSM_WRITE;                                 // 0x3418
  SDMA_PGFSM_READ                                        :TSDMA_PGFSM_READ;                                  // 0x3419
  SDMA0_EDC_CONFIG                                       :TSDMA0_EDC_CONFIG;                                 // 0x341A
  SDMA0_VM_CNTL                                          :TSDMA0_VM_CNTL;                                    // 0x341B
  SDMA0_VM_CTX_LO                                        :TSDMA0_VM_CTX_LO;                                  // 0x341C
  SDMA0_VM_CTX_HI                                        :TSDMA0_VM_CTX_HI;                                  // 0x341D
  SDMA0_STATUS2_REG                                      :TSDMA0_STATUS2_REG;                                // 0x341E
  SDMA0_ACTIVE_FCN_ID                                    :TSDMA0_ACTIVE_FCN_ID;                              // 0x341F
  SDMA0_VM_CTX_CNTL                                      :TSDMA0_VM_CTX_CNTL;                                // 0x3420
  SDMA0_VIRT_RESET_REQ                                   :TSDMA0_VIRT_RESET_REQ;                             // 0x3421
  REG_3422_3429                                          :array[0..7] of DWORD;                              // 0x3422
  SDMA0_VF_ENABLE                                        :TSDMA0_VF_ENABLE;                                  // 0x342A
  SDMA0_BA_THRESHOLD                                     :TSDMA0_BA_THRESHOLD;                               // 0x342B
  SDMA0_ID                                               :TSDMA0_ID;                                         // 0x342C
  SDMA0_VERSION                                          :TSDMA0_VERSION;                                    // 0x342D
  SDMA0_ATOMIC_CNTL                                      :TSDMA0_ATOMIC_CNTL;                                // 0x342E
  SDMA0_ATOMIC_PREOP_LO                                  :TSDMA0_ATOMIC_PREOP_LO;                            // 0x342F
  SDMA0_ATOMIC_PREOP_HI                                  :TSDMA0_ATOMIC_PREOP_HI;                            // 0x3430
  REG_3431_3476                                          :array[0..69] of DWORD;                             // 0x3431
  SDMA0_PERF_REG_TYPE0                                   :TSDMA0_PERF_REG_TYPE0;                             // 0x3477
  SDMA0_CONTEXT_REG_TYPE0                                :TSDMA0_CONTEXT_REG_TYPE0;                          // 0x3478
  SDMA0_CONTEXT_REG_TYPE1                                :TSDMA0_CONTEXT_REG_TYPE1;                          // 0x3479
  SDMA0_CONTEXT_REG_TYPE2                                :TSDMA0_CONTEXT_REG_TYPE2;                          // 0x347A
  REG_347B                                               :DWORD;                                             // 0x347B
  SDMA0_PUB_REG_TYPE0                                    :TSDMA0_PUB_REG_TYPE0;                              // 0x347C
  SDMA0_PUB_REG_TYPE1                                    :TSDMA0_PUB_REG_TYPE1;                              // 0x347D
  REG_347E_347F                                          :array[0..1] of DWORD;                              // 0x347E
  SDMA0_GFX_RB_CNTL                                      :TSDMA0_GFX_RB_CNTL;                                // 0x3480
  SDMA0_GFX_RB_BASE                                      :TSDMA0_GFX_RB_BASE;                                // 0x3481
  SDMA0_GFX_RB_BASE_HI                                   :TSDMA0_GFX_RB_BASE_HI;                             // 0x3482
  SDMA0_GFX_RB_RPTR                                      :TSDMA0_GFX_RB_RPTR;                                // 0x3483
  SDMA0_GFX_RB_WPTR                                      :TSDMA0_GFX_RB_WPTR;                                // 0x3484
  SDMA0_GFX_RB_WPTR_POLL_CNTL                            :TSDMA0_GFX_RB_WPTR_POLL_CNTL;                      // 0x3485
  SDMA0_GFX_RB_WPTR_POLL_ADDR_HI                         :TSDMA0_GFX_RB_WPTR_POLL_ADDR_HI;                   // 0x3486
  SDMA0_GFX_RB_WPTR_POLL_ADDR_LO                         :TSDMA0_GFX_RB_WPTR_POLL_ADDR_LO;                   // 0x3487
  SDMA0_GFX_RB_RPTR_ADDR_HI                              :TSDMA0_GFX_RB_RPTR_ADDR_HI;                        // 0x3488
  SDMA0_GFX_RB_RPTR_ADDR_LO                              :TSDMA0_GFX_RB_RPTR_ADDR_LO;                        // 0x3489
  SDMA0_GFX_IB_CNTL                                      :TSDMA0_GFX_IB_CNTL;                                // 0x348A
  SDMA0_GFX_IB_RPTR                                      :TSDMA0_GFX_IB_RPTR;                                // 0x348B
  SDMA0_GFX_IB_OFFSET                                    :TSDMA0_GFX_IB_OFFSET;                              // 0x348C
  SDMA0_GFX_IB_BASE_LO                                   :TSDMA0_GFX_IB_BASE_LO;                             // 0x348D
  SDMA0_GFX_IB_BASE_HI                                   :TSDMA0_GFX_IB_BASE_HI;                             // 0x348E
  SDMA0_GFX_IB_SIZE                                      :TSDMA0_GFX_IB_SIZE;                                // 0x348F
  SDMA0_GFX_SKIP_CNTL                                    :TSDMA0_GFX_SKIP_CNTL;                              // 0x3490
  SDMA0_GFX_CONTEXT_STATUS                               :TSDMA0_GFX_CONTEXT_STATUS;                         // 0x3491
  SDMA0_GFX_DOORBELL                                     :TSDMA0_GFX_DOORBELL;                               // 0x3492
  SDMA0_GFX_CONTEXT_CNTL                                 :TSDMA0_GFX_CONTEXT_CNTL;                           // 0x3493
  REG_3494_34A6                                          :array[0..18] of DWORD;                             // 0x3494
  SDMA0_GFX_VIRTUAL_ADDR                                 :TSDMA0_GFX_VIRTUAL_ADDR;                           // 0x34A7
  SDMA0_GFX_APE1_CNTL                                    :TSDMA0_GFX_APE1_CNTL;                              // 0x34A8
  SDMA0_GFX_DOORBELL_LOG                                 :TSDMA0_GFX_DOORBELL_LOG;                           // 0x34A9
  SDMA0_GFX_WATERMARK                                    :TSDMA0_GFX_WATERMARK;                              // 0x34AA
  REG_34AB                                               :DWORD;                                             // 0x34AB
  SDMA0_GFX_CSA_ADDR_LO                                  :TSDMA0_GFX_CSA_ADDR_LO;                            // 0x34AC
  SDMA0_GFX_CSA_ADDR_HI                                  :TSDMA0_GFX_CSA_ADDR_HI;                            // 0x34AD
  REG_34AE                                               :DWORD;                                             // 0x34AE
  SDMA0_GFX_IB_SUB_REMAIN                                :TSDMA0_GFX_IB_SUB_REMAIN;                          // 0x34AF
  SDMA0_GFX_PREEMPT                                      :TSDMA0_GFX_PREEMPT;                                // 0x34B0
  SDMA0_GFX_DUMMY_REG                                    :TSDMA0_GFX_DUMMY_REG;                              // 0x34B1
  REG_34B2_34C0                                          :array[0..14] of DWORD;                             // 0x34B2
  SDMA0_GFX_MIDCMD_DATA0                                 :TSDMA0_GFX_MIDCMD_DATA0;                           // 0x34C1
  SDMA0_GFX_MIDCMD_DATA1                                 :TSDMA0_GFX_MIDCMD_DATA1;                           // 0x34C2
  SDMA0_GFX_MIDCMD_DATA2                                 :TSDMA0_GFX_MIDCMD_DATA2;                           // 0x34C3
  SDMA0_GFX_MIDCMD_DATA3                                 :TSDMA0_GFX_MIDCMD_DATA3;                           // 0x34C4
  SDMA0_GFX_MIDCMD_DATA4                                 :TSDMA0_GFX_MIDCMD_DATA4;                           // 0x34C5
  SDMA0_GFX_MIDCMD_DATA5                                 :TSDMA0_GFX_MIDCMD_DATA5;                           // 0x34C6
  SDMA0_GFX_MIDCMD_CNTL                                  :TSDMA0_GFX_MIDCMD_CNTL;                            // 0x34C7
  REG_34C8_34FF                                          :array[0..55] of DWORD;                             // 0x34C8
  SDMA0_RLC0_RB_CNTL                                     :TSDMA0_RLC0_RB_CNTL;                               // 0x3500
  SDMA0_RLC0_RB_BASE                                     :TSDMA0_RLC0_RB_BASE;                               // 0x3501
  SDMA0_RLC0_RB_BASE_HI                                  :TSDMA0_RLC0_RB_BASE_HI;                            // 0x3502
  SDMA0_RLC0_RB_RPTR                                     :TSDMA0_RLC0_RB_RPTR;                               // 0x3503
  SDMA0_RLC0_RB_WPTR                                     :TSDMA0_RLC0_RB_WPTR;                               // 0x3504
  SDMA0_RLC0_RB_WPTR_POLL_CNTL                           :TSDMA0_RLC0_RB_WPTR_POLL_CNTL;                     // 0x3505
  SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI                        :TSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI;                  // 0x3506
  SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO                        :TSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO;                  // 0x3507
  SDMA0_RLC0_RB_RPTR_ADDR_HI                             :TSDMA0_RLC0_RB_RPTR_ADDR_HI;                       // 0x3508
  SDMA0_RLC0_RB_RPTR_ADDR_LO                             :TSDMA0_RLC0_RB_RPTR_ADDR_LO;                       // 0x3509
  SDMA0_RLC0_IB_CNTL                                     :TSDMA0_RLC0_IB_CNTL;                               // 0x350A
  SDMA0_RLC0_IB_RPTR                                     :TSDMA0_RLC0_IB_RPTR;                               // 0x350B
  SDMA0_RLC0_IB_OFFSET                                   :TSDMA0_RLC0_IB_OFFSET;                             // 0x350C
  SDMA0_RLC0_IB_BASE_LO                                  :TSDMA0_RLC0_IB_BASE_LO;                            // 0x350D
  SDMA0_RLC0_IB_BASE_HI                                  :TSDMA0_RLC0_IB_BASE_HI;                            // 0x350E
  SDMA0_RLC0_IB_SIZE                                     :TSDMA0_RLC0_IB_SIZE;                               // 0x350F
  SDMA0_RLC0_SKIP_CNTL                                   :TSDMA0_RLC0_SKIP_CNTL;                             // 0x3510
  SDMA0_RLC0_CONTEXT_STATUS                              :TSDMA0_RLC0_CONTEXT_STATUS;                        // 0x3511
  SDMA0_RLC0_DOORBELL                                    :TSDMA0_RLC0_DOORBELL;                              // 0x3512
  REG_3513_3526                                          :array[0..19] of DWORD;                             // 0x3513
  SDMA0_RLC0_VIRTUAL_ADDR                                :TSDMA0_RLC0_VIRTUAL_ADDR;                          // 0x3527
  SDMA0_RLC0_APE1_CNTL                                   :TSDMA0_RLC0_APE1_CNTL;                             // 0x3528
  SDMA0_RLC0_DOORBELL_LOG                                :TSDMA0_RLC0_DOORBELL_LOG;                          // 0x3529
  SDMA0_RLC0_WATERMARK                                   :TSDMA0_RLC0_WATERMARK;                             // 0x352A
  REG_352B                                               :DWORD;                                             // 0x352B
  SDMA0_RLC0_CSA_ADDR_LO                                 :TSDMA0_RLC0_CSA_ADDR_LO;                           // 0x352C
  SDMA0_RLC0_CSA_ADDR_HI                                 :TSDMA0_RLC0_CSA_ADDR_HI;                           // 0x352D
  REG_352E                                               :DWORD;                                             // 0x352E
  SDMA0_RLC0_IB_SUB_REMAIN                               :TSDMA0_RLC0_IB_SUB_REMAIN;                         // 0x352F
  SDMA0_RLC0_PREEMPT                                     :TSDMA0_RLC0_PREEMPT;                               // 0x3530
  SDMA0_RLC0_DUMMY_REG                                   :TSDMA0_RLC0_DUMMY_REG;                             // 0x3531
  REG_3532_3540                                          :array[0..14] of DWORD;                             // 0x3532
  SDMA0_RLC0_MIDCMD_DATA0                                :TSDMA0_RLC0_MIDCMD_DATA0;                          // 0x3541
  SDMA0_RLC0_MIDCMD_DATA1                                :TSDMA0_RLC0_MIDCMD_DATA1;                          // 0x3542
  SDMA0_RLC0_MIDCMD_DATA2                                :TSDMA0_RLC0_MIDCMD_DATA2;                          // 0x3543
  SDMA0_RLC0_MIDCMD_DATA3                                :TSDMA0_RLC0_MIDCMD_DATA3;                          // 0x3544
  SDMA0_RLC0_MIDCMD_DATA4                                :TSDMA0_RLC0_MIDCMD_DATA4;                          // 0x3545
  SDMA0_RLC0_MIDCMD_DATA5                                :TSDMA0_RLC0_MIDCMD_DATA5;                          // 0x3546
  SDMA0_RLC0_MIDCMD_CNTL                                 :TSDMA0_RLC0_MIDCMD_CNTL;                           // 0x3547
  REG_3548_357F                                          :array[0..55] of DWORD;                             // 0x3548
  SDMA0_RLC1_RB_CNTL                                     :TSDMA0_RLC1_RB_CNTL;                               // 0x3580
  SDMA0_RLC1_RB_BASE                                     :TSDMA0_RLC1_RB_BASE;                               // 0x3581
  SDMA0_RLC1_RB_BASE_HI                                  :TSDMA0_RLC1_RB_BASE_HI;                            // 0x3582
  SDMA0_RLC1_RB_RPTR                                     :TSDMA0_RLC1_RB_RPTR;                               // 0x3583
  SDMA0_RLC1_RB_WPTR                                     :TSDMA0_RLC1_RB_WPTR;                               // 0x3584
  SDMA0_RLC1_RB_WPTR_POLL_CNTL                           :TSDMA0_RLC1_RB_WPTR_POLL_CNTL;                     // 0x3585
  SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI                        :TSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI;                  // 0x3586
  SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO                        :TSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO;                  // 0x3587
  SDMA0_RLC1_RB_RPTR_ADDR_HI                             :TSDMA0_RLC1_RB_RPTR_ADDR_HI;                       // 0x3588
  SDMA0_RLC1_RB_RPTR_ADDR_LO                             :TSDMA0_RLC1_RB_RPTR_ADDR_LO;                       // 0x3589
  SDMA0_RLC1_IB_CNTL                                     :TSDMA0_RLC1_IB_CNTL;                               // 0x358A
  SDMA0_RLC1_IB_RPTR                                     :TSDMA0_RLC1_IB_RPTR;                               // 0x358B
  SDMA0_RLC1_IB_OFFSET                                   :TSDMA0_RLC1_IB_OFFSET;                             // 0x358C
  SDMA0_RLC1_IB_BASE_LO                                  :TSDMA0_RLC1_IB_BASE_LO;                            // 0x358D
  SDMA0_RLC1_IB_BASE_HI                                  :TSDMA0_RLC1_IB_BASE_HI;                            // 0x358E
  SDMA0_RLC1_IB_SIZE                                     :TSDMA0_RLC1_IB_SIZE;                               // 0x358F
  SDMA0_RLC1_SKIP_CNTL                                   :TSDMA0_RLC1_SKIP_CNTL;                             // 0x3590
  SDMA0_RLC1_CONTEXT_STATUS                              :TSDMA0_RLC1_CONTEXT_STATUS;                        // 0x3591
  SDMA0_RLC1_DOORBELL                                    :TSDMA0_RLC1_DOORBELL;                              // 0x3592
  REG_3593_35A6                                          :array[0..19] of DWORD;                             // 0x3593
  SDMA0_RLC1_VIRTUAL_ADDR                                :TSDMA0_RLC1_VIRTUAL_ADDR;                          // 0x35A7
  SDMA0_RLC1_APE1_CNTL                                   :TSDMA0_RLC1_APE1_CNTL;                             // 0x35A8
  SDMA0_RLC1_DOORBELL_LOG                                :TSDMA0_RLC1_DOORBELL_LOG;                          // 0x35A9
  SDMA0_RLC1_WATERMARK                                   :TSDMA0_RLC1_WATERMARK;                             // 0x35AA
  REG_35AB                                               :DWORD;                                             // 0x35AB
  SDMA0_RLC1_CSA_ADDR_LO                                 :TSDMA0_RLC1_CSA_ADDR_LO;                           // 0x35AC
  SDMA0_RLC1_CSA_ADDR_HI                                 :TSDMA0_RLC1_CSA_ADDR_HI;                           // 0x35AD
  REG_35AE                                               :DWORD;                                             // 0x35AE
  SDMA0_RLC1_IB_SUB_REMAIN                               :TSDMA0_RLC1_IB_SUB_REMAIN;                         // 0x35AF
  SDMA0_RLC1_PREEMPT                                     :TSDMA0_RLC1_PREEMPT;                               // 0x35B0
  SDMA0_RLC1_DUMMY_REG                                   :TSDMA0_RLC1_DUMMY_REG;                             // 0x35B1
  REG_35B2_35C0                                          :array[0..14] of DWORD;                             // 0x35B2
  SDMA0_RLC1_MIDCMD_DATA0                                :TSDMA0_RLC1_MIDCMD_DATA0;                          // 0x35C1
  SDMA0_RLC1_MIDCMD_DATA1                                :TSDMA0_RLC1_MIDCMD_DATA1;                          // 0x35C2
  SDMA0_RLC1_MIDCMD_DATA2                                :TSDMA0_RLC1_MIDCMD_DATA2;                          // 0x35C3
  SDMA0_RLC1_MIDCMD_DATA3                                :TSDMA0_RLC1_MIDCMD_DATA3;                          // 0x35C4
  SDMA0_RLC1_MIDCMD_DATA4                                :TSDMA0_RLC1_MIDCMD_DATA4;                          // 0x35C5
  SDMA0_RLC1_MIDCMD_DATA5                                :TSDMA0_RLC1_MIDCMD_DATA5;                          // 0x35C6
  SDMA0_RLC1_MIDCMD_CNTL                                 :TSDMA0_RLC1_MIDCMD_CNTL;                           // 0x35C7
  REG_35C8_35FF                                          :array[0..55] of DWORD;                             // 0x35C8
  SDMA1_UCODE_ADDR                                       :TSDMA1_UCODE_ADDR;                                 // 0x3600
  SDMA1_UCODE_DATA                                       :TSDMA1_UCODE_DATA;                                 // 0x3601
  SDMA1_POWER_CNTL                                       :TSDMA1_POWER_CNTL;                                 // 0x3602
  SDMA1_CLK_CTRL                                         :TSDMA1_CLK_CTRL;                                   // 0x3603
  SDMA1_CNTL                                             :TSDMA1_CNTL;                                       // 0x3604
  SDMA1_CHICKEN_BITS                                     :TSDMA1_CHICKEN_BITS;                               // 0x3605
  SDMA1_TILING_CONFIG                                    :TSDMA1_TILING_CONFIG;                              // 0x3606
  SDMA1_HASH                                             :TSDMA1_HASH;                                       // 0x3607
  REG_3608                                               :DWORD;                                             // 0x3608
  SDMA1_SEM_WAIT_FAIL_TIMER_CNTL                         :TSDMA1_SEM_WAIT_FAIL_TIMER_CNTL;                   // 0x3609
  SDMA1_RB_RPTR_FETCH                                    :TSDMA1_RB_RPTR_FETCH;                              // 0x360A
  SDMA1_IB_OFFSET_FETCH                                  :TSDMA1_IB_OFFSET_FETCH;                            // 0x360B
  SDMA1_PROGRAM                                          :TSDMA1_PROGRAM;                                    // 0x360C
  SDMA1_STATUS_REG                                       :TSDMA1_STATUS_REG;                                 // 0x360D
  SDMA1_STATUS1_REG                                      :TSDMA1_STATUS1_REG;                                // 0x360E
  SDMA1_RD_BURST_CNTL                                    :TSDMA1_RD_BURST_CNTL;                              // 0x360F
  REG_3610_3611                                          :array[0..1] of DWORD;                              // 0x3610
  SDMA1_F32_CNTL                                         :TSDMA1_F32_CNTL;                                   // 0x3612
  SDMA1_FREEZE                                           :TSDMA1_FREEZE;                                     // 0x3613
  SDMA1_PHASE0_QUANTUM                                   :TSDMA1_PHASE0_QUANTUM;                             // 0x3614
  SDMA1_PHASE1_QUANTUM                                   :TSDMA1_PHASE1_QUANTUM;                             // 0x3615
  REG_3616_3619                                          :array[0..3] of DWORD;                              // 0x3616
  SDMA1_EDC_CONFIG                                       :TSDMA1_EDC_CONFIG;                                 // 0x361A
  SDMA1_VM_CNTL                                          :TSDMA1_VM_CNTL;                                    // 0x361B
  SDMA1_VM_CTX_LO                                        :TSDMA1_VM_CTX_LO;                                  // 0x361C
  SDMA1_VM_CTX_HI                                        :TSDMA1_VM_CTX_HI;                                  // 0x361D
  SDMA1_STATUS2_REG                                      :TSDMA1_STATUS2_REG;                                // 0x361E
  SDMA1_ACTIVE_FCN_ID                                    :TSDMA1_ACTIVE_FCN_ID;                              // 0x361F
  SDMA1_VM_CTX_CNTL                                      :TSDMA1_VM_CTX_CNTL;                                // 0x3620
  SDMA1_VIRT_RESET_REQ                                   :TSDMA1_VIRT_RESET_REQ;                             // 0x3621
  REG_3622_3629                                          :array[0..7] of DWORD;                              // 0x3622
  SDMA1_VF_ENABLE                                        :TSDMA1_VF_ENABLE;                                  // 0x362A
  SDMA1_BA_THRESHOLD                                     :TSDMA1_BA_THRESHOLD;                               // 0x362B
  SDMA1_ID                                               :TSDMA1_ID;                                         // 0x362C
  SDMA1_VERSION                                          :TSDMA1_VERSION;                                    // 0x362D
  SDMA1_ATOMIC_CNTL                                      :TSDMA1_ATOMIC_CNTL;                                // 0x362E
  SDMA1_ATOMIC_PREOP_LO                                  :TSDMA1_ATOMIC_PREOP_LO;                            // 0x362F
  SDMA1_ATOMIC_PREOP_HI                                  :TSDMA1_ATOMIC_PREOP_HI;                            // 0x3630
  REG_3631_3676                                          :array[0..69] of DWORD;                             // 0x3631
  SDMA1_PERF_REG_TYPE0                                   :TSDMA1_PERF_REG_TYPE0;                             // 0x3677
  SDMA1_CONTEXT_REG_TYPE0                                :TSDMA1_CONTEXT_REG_TYPE0;                          // 0x3678
  SDMA1_CONTEXT_REG_TYPE1                                :TSDMA1_CONTEXT_REG_TYPE1;                          // 0x3679
  SDMA1_CONTEXT_REG_TYPE2                                :TSDMA1_CONTEXT_REG_TYPE2;                          // 0x367A
  REG_367B                                               :DWORD;                                             // 0x367B
  SDMA1_PUB_REG_TYPE0                                    :TSDMA1_PUB_REG_TYPE0;                              // 0x367C
  SDMA1_PUB_REG_TYPE1                                    :TSDMA1_PUB_REG_TYPE1;                              // 0x367D
  REG_367E_367F                                          :array[0..1] of DWORD;                              // 0x367E
  SDMA1_GFX_RB_CNTL                                      :TSDMA1_GFX_RB_CNTL;                                // 0x3680
  SDMA1_GFX_RB_BASE                                      :TSDMA1_GFX_RB_BASE;                                // 0x3681
  SDMA1_GFX_RB_BASE_HI                                   :TSDMA1_GFX_RB_BASE_HI;                             // 0x3682
  SDMA1_GFX_RB_RPTR                                      :TSDMA1_GFX_RB_RPTR;                                // 0x3683
  SDMA1_GFX_RB_WPTR                                      :TSDMA1_GFX_RB_WPTR;                                // 0x3684
  SDMA1_GFX_RB_WPTR_POLL_CNTL                            :TSDMA1_GFX_RB_WPTR_POLL_CNTL;                      // 0x3685
  SDMA1_GFX_RB_WPTR_POLL_ADDR_HI                         :TSDMA1_GFX_RB_WPTR_POLL_ADDR_HI;                   // 0x3686
  SDMA1_GFX_RB_WPTR_POLL_ADDR_LO                         :TSDMA1_GFX_RB_WPTR_POLL_ADDR_LO;                   // 0x3687
  SDMA1_GFX_RB_RPTR_ADDR_HI                              :TSDMA1_GFX_RB_RPTR_ADDR_HI;                        // 0x3688
  SDMA1_GFX_RB_RPTR_ADDR_LO                              :TSDMA1_GFX_RB_RPTR_ADDR_LO;                        // 0x3689
  SDMA1_GFX_IB_CNTL                                      :TSDMA1_GFX_IB_CNTL;                                // 0x368A
  SDMA1_GFX_IB_RPTR                                      :TSDMA1_GFX_IB_RPTR;                                // 0x368B
  SDMA1_GFX_IB_OFFSET                                    :TSDMA1_GFX_IB_OFFSET;                              // 0x368C
  SDMA1_GFX_IB_BASE_LO                                   :TSDMA1_GFX_IB_BASE_LO;                             // 0x368D
  SDMA1_GFX_IB_BASE_HI                                   :TSDMA1_GFX_IB_BASE_HI;                             // 0x368E
  SDMA1_GFX_IB_SIZE                                      :TSDMA1_GFX_IB_SIZE;                                // 0x368F
  SDMA1_GFX_SKIP_CNTL                                    :TSDMA1_GFX_SKIP_CNTL;                              // 0x3690
  SDMA1_GFX_CONTEXT_STATUS                               :TSDMA1_GFX_CONTEXT_STATUS;                         // 0x3691
  SDMA1_GFX_DOORBELL                                     :TSDMA1_GFX_DOORBELL;                               // 0x3692
  SDMA1_GFX_CONTEXT_CNTL                                 :TSDMA1_GFX_CONTEXT_CNTL;                           // 0x3693
  REG_3694_36A6                                          :array[0..18] of DWORD;                             // 0x3694
  SDMA1_GFX_VIRTUAL_ADDR                                 :TSDMA1_GFX_VIRTUAL_ADDR;                           // 0x36A7
  SDMA1_GFX_APE1_CNTL                                    :TSDMA1_GFX_APE1_CNTL;                              // 0x36A8
  SDMA1_GFX_DOORBELL_LOG                                 :TSDMA1_GFX_DOORBELL_LOG;                           // 0x36A9
  SDMA1_GFX_WATERMARK                                    :TSDMA1_GFX_WATERMARK;                              // 0x36AA
  REG_36AB                                               :DWORD;                                             // 0x36AB
  SDMA1_GFX_CSA_ADDR_LO                                  :TSDMA1_GFX_CSA_ADDR_LO;                            // 0x36AC
  SDMA1_GFX_CSA_ADDR_HI                                  :TSDMA1_GFX_CSA_ADDR_HI;                            // 0x36AD
  REG_36AE                                               :DWORD;                                             // 0x36AE
  SDMA1_GFX_IB_SUB_REMAIN                                :TSDMA1_GFX_IB_SUB_REMAIN;                          // 0x36AF
  SDMA1_GFX_PREEMPT                                      :TSDMA1_GFX_PREEMPT;                                // 0x36B0
  SDMA1_GFX_DUMMY_REG                                    :TSDMA1_GFX_DUMMY_REG;                              // 0x36B1
  REG_36B2_36C0                                          :array[0..14] of DWORD;                             // 0x36B2
  SDMA1_GFX_MIDCMD_DATA0                                 :TSDMA1_GFX_MIDCMD_DATA0;                           // 0x36C1
  SDMA1_GFX_MIDCMD_DATA1                                 :TSDMA1_GFX_MIDCMD_DATA1;                           // 0x36C2
  SDMA1_GFX_MIDCMD_DATA2                                 :TSDMA1_GFX_MIDCMD_DATA2;                           // 0x36C3
  SDMA1_GFX_MIDCMD_DATA3                                 :TSDMA1_GFX_MIDCMD_DATA3;                           // 0x36C4
  SDMA1_GFX_MIDCMD_DATA4                                 :TSDMA1_GFX_MIDCMD_DATA4;                           // 0x36C5
  SDMA1_GFX_MIDCMD_DATA5                                 :TSDMA1_GFX_MIDCMD_DATA5;                           // 0x36C6
  SDMA1_GFX_MIDCMD_CNTL                                  :TSDMA1_GFX_MIDCMD_CNTL;                            // 0x36C7
  REG_36C8_36FF                                          :array[0..55] of DWORD;                             // 0x36C8
  SDMA1_RLC0_RB_CNTL                                     :TSDMA1_RLC0_RB_CNTL;                               // 0x3700
  SDMA1_RLC0_RB_BASE                                     :TSDMA1_RLC0_RB_BASE;                               // 0x3701
  SDMA1_RLC0_RB_BASE_HI                                  :TSDMA1_RLC0_RB_BASE_HI;                            // 0x3702
  SDMA1_RLC0_RB_RPTR                                     :TSDMA1_RLC0_RB_RPTR;                               // 0x3703
  SDMA1_RLC0_RB_WPTR                                     :TSDMA1_RLC0_RB_WPTR;                               // 0x3704
  SDMA1_RLC0_RB_WPTR_POLL_CNTL                           :TSDMA1_RLC0_RB_WPTR_POLL_CNTL;                     // 0x3705
  SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                        :TSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI;                  // 0x3706
  SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                        :TSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO;                  // 0x3707
  SDMA1_RLC0_RB_RPTR_ADDR_HI                             :TSDMA1_RLC0_RB_RPTR_ADDR_HI;                       // 0x3708
  SDMA1_RLC0_RB_RPTR_ADDR_LO                             :TSDMA1_RLC0_RB_RPTR_ADDR_LO;                       // 0x3709
  SDMA1_RLC0_IB_CNTL                                     :TSDMA1_RLC0_IB_CNTL;                               // 0x370A
  SDMA1_RLC0_IB_RPTR                                     :TSDMA1_RLC0_IB_RPTR;                               // 0x370B
  SDMA1_RLC0_IB_OFFSET                                   :TSDMA1_RLC0_IB_OFFSET;                             // 0x370C
  SDMA1_RLC0_IB_BASE_LO                                  :TSDMA1_RLC0_IB_BASE_LO;                            // 0x370D
  SDMA1_RLC0_IB_BASE_HI                                  :TSDMA1_RLC0_IB_BASE_HI;                            // 0x370E
  SDMA1_RLC0_IB_SIZE                                     :TSDMA1_RLC0_IB_SIZE;                               // 0x370F
  SDMA1_RLC0_SKIP_CNTL                                   :TSDMA1_RLC0_SKIP_CNTL;                             // 0x3710
  SDMA1_RLC0_CONTEXT_STATUS                              :TSDMA1_RLC0_CONTEXT_STATUS;                        // 0x3711
  SDMA1_RLC0_DOORBELL                                    :TSDMA1_RLC0_DOORBELL;                              // 0x3712
  REG_3713_3726                                          :array[0..19] of DWORD;                             // 0x3713
  SDMA1_RLC0_VIRTUAL_ADDR                                :TSDMA1_RLC0_VIRTUAL_ADDR;                          // 0x3727
  SDMA1_RLC0_APE1_CNTL                                   :TSDMA1_RLC0_APE1_CNTL;                             // 0x3728
  SDMA1_RLC0_DOORBELL_LOG                                :TSDMA1_RLC0_DOORBELL_LOG;                          // 0x3729
  SDMA1_RLC0_WATERMARK                                   :TSDMA1_RLC0_WATERMARK;                             // 0x372A
  REG_372B                                               :DWORD;                                             // 0x372B
  SDMA1_RLC0_CSA_ADDR_LO                                 :TSDMA1_RLC0_CSA_ADDR_LO;                           // 0x372C
  SDMA1_RLC0_CSA_ADDR_HI                                 :TSDMA1_RLC0_CSA_ADDR_HI;                           // 0x372D
  REG_372E                                               :DWORD;                                             // 0x372E
  SDMA1_RLC0_IB_SUB_REMAIN                               :TSDMA1_RLC0_IB_SUB_REMAIN;                         // 0x372F
  SDMA1_RLC0_PREEMPT                                     :TSDMA1_RLC0_PREEMPT;                               // 0x3730
  SDMA1_RLC0_DUMMY_REG                                   :TSDMA1_RLC0_DUMMY_REG;                             // 0x3731
  REG_3732_3740                                          :array[0..14] of DWORD;                             // 0x3732
  SDMA1_RLC0_MIDCMD_DATA0                                :TSDMA1_RLC0_MIDCMD_DATA0;                          // 0x3741
  SDMA1_RLC0_MIDCMD_DATA1                                :TSDMA1_RLC0_MIDCMD_DATA1;                          // 0x3742
  SDMA1_RLC0_MIDCMD_DATA2                                :TSDMA1_RLC0_MIDCMD_DATA2;                          // 0x3743
  SDMA1_RLC0_MIDCMD_DATA3                                :TSDMA1_RLC0_MIDCMD_DATA3;                          // 0x3744
  SDMA1_RLC0_MIDCMD_DATA4                                :TSDMA1_RLC0_MIDCMD_DATA4;                          // 0x3745
  SDMA1_RLC0_MIDCMD_DATA5                                :TSDMA1_RLC0_MIDCMD_DATA5;                          // 0x3746
  SDMA1_RLC0_MIDCMD_CNTL                                 :TSDMA1_RLC0_MIDCMD_CNTL;                           // 0x3747
  REG_3748_377F                                          :array[0..55] of DWORD;                             // 0x3748
  SDMA1_RLC1_RB_CNTL                                     :TSDMA1_RLC1_RB_CNTL;                               // 0x3780
  SDMA1_RLC1_RB_BASE                                     :TSDMA1_RLC1_RB_BASE;                               // 0x3781
  SDMA1_RLC1_RB_BASE_HI                                  :TSDMA1_RLC1_RB_BASE_HI;                            // 0x3782
  SDMA1_RLC1_RB_RPTR                                     :TSDMA1_RLC1_RB_RPTR;                               // 0x3783
  SDMA1_RLC1_RB_WPTR                                     :TSDMA1_RLC1_RB_WPTR;                               // 0x3784
  SDMA1_RLC1_RB_WPTR_POLL_CNTL                           :TSDMA1_RLC1_RB_WPTR_POLL_CNTL;                     // 0x3785
  SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                        :TSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI;                  // 0x3786
  SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                        :TSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO;                  // 0x3787
  SDMA1_RLC1_RB_RPTR_ADDR_HI                             :TSDMA1_RLC1_RB_RPTR_ADDR_HI;                       // 0x3788
  SDMA1_RLC1_RB_RPTR_ADDR_LO                             :TSDMA1_RLC1_RB_RPTR_ADDR_LO;                       // 0x3789
  SDMA1_RLC1_IB_CNTL                                     :TSDMA1_RLC1_IB_CNTL;                               // 0x378A
  SDMA1_RLC1_IB_RPTR                                     :TSDMA1_RLC1_IB_RPTR;                               // 0x378B
  SDMA1_RLC1_IB_OFFSET                                   :TSDMA1_RLC1_IB_OFFSET;                             // 0x378C
  SDMA1_RLC1_IB_BASE_LO                                  :TSDMA1_RLC1_IB_BASE_LO;                            // 0x378D
  SDMA1_RLC1_IB_BASE_HI                                  :TSDMA1_RLC1_IB_BASE_HI;                            // 0x378E
  SDMA1_RLC1_IB_SIZE                                     :TSDMA1_RLC1_IB_SIZE;                               // 0x378F
  SDMA1_RLC1_SKIP_CNTL                                   :TSDMA1_RLC1_SKIP_CNTL;                             // 0x3790
  SDMA1_RLC1_CONTEXT_STATUS                              :TSDMA1_RLC1_CONTEXT_STATUS;                        // 0x3791
  SDMA1_RLC1_DOORBELL                                    :TSDMA1_RLC1_DOORBELL;                              // 0x3792
  REG_3793_37A6                                          :array[0..19] of DWORD;                             // 0x3793
  SDMA1_RLC1_VIRTUAL_ADDR                                :TSDMA1_RLC1_VIRTUAL_ADDR;                          // 0x37A7
  SDMA1_RLC1_APE1_CNTL                                   :TSDMA1_RLC1_APE1_CNTL;                             // 0x37A8
  SDMA1_RLC1_DOORBELL_LOG                                :TSDMA1_RLC1_DOORBELL_LOG;                          // 0x37A9
  SDMA1_RLC1_WATERMARK                                   :TSDMA1_RLC1_WATERMARK;                             // 0x37AA
  REG_37AB                                               :DWORD;                                             // 0x37AB
  SDMA1_RLC1_CSA_ADDR_LO                                 :TSDMA1_RLC1_CSA_ADDR_LO;                           // 0x37AC
  SDMA1_RLC1_CSA_ADDR_HI                                 :TSDMA1_RLC1_CSA_ADDR_HI;                           // 0x37AD
  REG_37AE                                               :DWORD;                                             // 0x37AE
  SDMA1_RLC1_IB_SUB_REMAIN                               :TSDMA1_RLC1_IB_SUB_REMAIN;                         // 0x37AF
  SDMA1_RLC1_PREEMPT                                     :TSDMA1_RLC1_PREEMPT;                               // 0x37B0
  SDMA1_RLC1_DUMMY_REG                                   :TSDMA1_RLC1_DUMMY_REG;                             // 0x37B1
  REG_37B2_37C0                                          :array[0..14] of DWORD;                             // 0x37B2
  SDMA1_RLC1_MIDCMD_DATA0                                :TSDMA1_RLC1_MIDCMD_DATA0;                          // 0x37C1
  SDMA1_RLC1_MIDCMD_DATA1                                :TSDMA1_RLC1_MIDCMD_DATA1;                          // 0x37C2
  SDMA1_RLC1_MIDCMD_DATA2                                :TSDMA1_RLC1_MIDCMD_DATA2;                          // 0x37C3
  SDMA1_RLC1_MIDCMD_DATA3                                :TSDMA1_RLC1_MIDCMD_DATA3;                          // 0x37C4
  SDMA1_RLC1_MIDCMD_DATA4                                :TSDMA1_RLC1_MIDCMD_DATA4;                          // 0x37C5
  SDMA1_RLC1_MIDCMD_DATA5                                :TSDMA1_RLC1_MIDCMD_DATA5;                          // 0x37C6
  SDMA1_RLC1_MIDCMD_CNTL                                 :TSDMA1_RLC1_MIDCMD_CNTL;                           // 0x37C7
  REG_37C8_38BF                                          :array[0..247] of DWORD;                            // 0x37C8
  UVD_PGFSM_CONFIG                                       :TUVD_PGFSM_CONFIG;                                 // 0x38C0
  REG_38C1                                               :DWORD;                                             // 0x38C1
  UVD_PGFSM_READ_TILE1                                   :TUVD_PGFSM_READ_TILE1;                             // 0x38C2
  UVD_PGFSM_READ_TILE2                                   :TUVD_PGFSM_READ_TILE2;                             // 0x38C3
  UVD_POWER_STATUS                                       :TUVD_POWER_STATUS;                                 // 0x38C4
  UVD_PGFSM_READ_TILE3                                   :TUVD_PGFSM_READ_TILE3;                             // 0x38C5
  UVD_PGFSM_READ_TILE4                                   :TUVD_PGFSM_READ_TILE4;                             // 0x38C6
  REG_38C7                                               :DWORD;                                             // 0x38C7
  UVD_PGFSM_READ_TILE5                                   :TUVD_PGFSM_READ_TILE5;                             // 0x38C8
  REG_38C9_38ED                                          :array[0..36] of DWORD;                             // 0x38C9
  UVD_PGFSM_READ_TILE6                                   :TUVD_PGFSM_READ_TILE6;                             // 0x38EE
  UVD_PGFSM_READ_TILE7                                   :TUVD_PGFSM_READ_TILE7;                             // 0x38EF
  REG_38F0_3991                                          :array[0..161] of DWORD;                            // 0x38F0
  UVD_MIF_CURR_ADDR_CONFIG                               :TUVD_MIF_CURR_ADDR_CONFIG;                         // 0x3992
  UVD_MIF_REF_ADDR_CONFIG                                :TUVD_MIF_REF_ADDR_CONFIG;                          // 0x3993
  REG_3994_39C4                                          :array[0..48] of DWORD;                             // 0x3994
  UVD_MIF_RECON1_ADDR_CONFIG                             :TUVD_MIF_RECON1_ADDR_CONFIG;                       // 0x39C5
  REG_39C6_3A1E                                          :array[0..88] of DWORD;                             // 0x39C6
  UVD_JPEG_ADDR_CONFIG                                   :TUVD_JPEG_ADDR_CONFIG;                             // 0x3A1F
  REG_3A20_3BBF                                          :array[0..415] of DWORD;                            // 0x3A20
  UVD_SEMA_ADDR_LOW                                      :TUVD_SEMA_ADDR_LOW;                                // 0x3BC0
  UVD_SEMA_ADDR_HIGH                                     :TUVD_SEMA_ADDR_HIGH;                               // 0x3BC1
  UVD_SEMA_CMD                                           :TUVD_SEMA_CMD;                                     // 0x3BC2
  UVD_GPCOM_VCPU_CMD                                     :TUVD_GPCOM_VCPU_CMD;                               // 0x3BC3
  UVD_GPCOM_VCPU_DATA0                                   :TUVD_GPCOM_VCPU_DATA0;                             // 0x3BC4
  UVD_GPCOM_VCPU_DATA1                                   :TUVD_GPCOM_VCPU_DATA1;                             // 0x3BC5
  UVD_ENGINE_CNTL                                        :TUVD_ENGINE_CNTL;                                  // 0x3BC6
  REG_3BC7_3BD2                                          :array[0..11] of DWORD;                             // 0x3BC7
  UVD_UDEC_ADDR_CONFIG                                   :TUVD_UDEC_ADDR_CONFIG;                             // 0x3BD3
  UVD_UDEC_DB_ADDR_CONFIG                                :TUVD_UDEC_DB_ADDR_CONFIG;                          // 0x3BD4
  UVD_UDEC_DBW_ADDR_CONFIG                               :TUVD_UDEC_DBW_ADDR_CONFIG;                         // 0x3BD5
  REG_3BD6_3BE3                                          :array[0..13] of DWORD;                             // 0x3BD6
  UVD_SUVD_CGC_GATE                                      :TUVD_SUVD_CGC_GATE;                                // 0x3BE4
  UVD_SUVD_CGC_STATUS                                    :TUVD_SUVD_CGC_STATUS;                              // 0x3BE5
  UVD_SUVD_CGC_CTRL                                      :TUVD_SUVD_CGC_CTRL;                                // 0x3BE6
  REG_3BE7_3C5D                                          :array[0..118] of DWORD;                            // 0x3BE7
  UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                      :TUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH;                // 0x3C5E
  UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                       :TUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW;                 // 0x3C5F
  REG_3C60_3C65                                          :array[0..5] of DWORD;                              // 0x3C60
  UVD_LMI_RBC_IB_64BIT_BAR_HIGH                          :TUVD_LMI_RBC_IB_64BIT_BAR_HIGH;                    // 0x3C66
  UVD_LMI_RBC_IB_64BIT_BAR_LOW                           :TUVD_LMI_RBC_IB_64BIT_BAR_LOW;                     // 0x3C67
  UVD_LMI_RBC_RB_64BIT_BAR_HIGH                          :TUVD_LMI_RBC_RB_64BIT_BAR_HIGH;                    // 0x3C68
  UVD_LMI_RBC_RB_64BIT_BAR_LOW                           :TUVD_LMI_RBC_RB_64BIT_BAR_LOW;                     // 0x3C69
  REG_3C6A_3CFF                                          :array[0..149] of DWORD;                            // 0x3C6A
  UVD_SEMA_CNTL                                          :TUVD_SEMA_CNTL;                                    // 0x3D00
  REG_3D01_3D25                                          :array[0..36] of DWORD;                             // 0x3D01
  UVD_LMI_EXT40_ADDR                                     :TUVD_LMI_EXT40_ADDR;                               // 0x3D26
  REG_3D27                                               :DWORD;                                             // 0x3D27
  UVD_CTX_INDEX                                          :TUVD_CTX_INDEX;                                    // 0x3D28
  UVD_CTX_DATA                                           :TUVD_CTX_DATA;                                     // 0x3D29
  UVD_CGC_GATE                                           :TUVD_CGC_GATE;                                     // 0x3D2A
  UVD_CGC_STATUS                                         :TUVD_CGC_STATUS;                                   // 0x3D2B
  UVD_CGC_CTRL                                           :TUVD_CGC_CTRL;                                     // 0x3D2C
  UVD_CGC_UDEC_STATUS                                    :TUVD_CGC_UDEC_STATUS;                              // 0x3D2D
  REG_3D2E_3D3C                                          :array[0..14] of DWORD;                             // 0x3D2E
  UVD_LMI_CTRL2                                          :TUVD_LMI_CTRL2;                                    // 0x3D3D
  REG_3D3E_3D3F                                          :array[0..1] of DWORD;                              // 0x3D3E
  UVD_MASTINT_EN                                         :TUVD_MASTINT_EN;                                   // 0x3D40
  REG_3D41_3D64                                          :array[0..35] of DWORD;                             // 0x3D41
  UVD_LMI_ADDR_EXT                                       :TUVD_LMI_ADDR_EXT;                                 // 0x3D65
  UVD_LMI_CTRL                                           :TUVD_LMI_CTRL;                                     // 0x3D66
  UVD_LMI_STATUS                                         :TUVD_LMI_STATUS;                                   // 0x3D67
  REG_3D68_3D6C                                          :array[0..4] of DWORD;                              // 0x3D68
  UVD_LMI_SWAP_CNTL                                      :TUVD_LMI_SWAP_CNTL;                                // 0x3D6D
  REG_3D6E                                               :DWORD;                                             // 0x3D6E
  UVD_MP_SWAP_CNTL                                       :TUVD_MP_SWAP_CNTL;                                 // 0x3D6F
  REG_3D70_3D76                                          :array[0..6] of DWORD;                              // 0x3D70
  UVD_MPC_CNTL                                           :TUVD_MPC_CNTL;                                     // 0x3D77
  REG_3D78                                               :DWORD;                                             // 0x3D78
  UVD_MPC_SET_MUXA0                                      :TUVD_MPC_SET_MUXA0;                                // 0x3D79
  UVD_MPC_SET_MUXA1                                      :TUVD_MPC_SET_MUXA1;                                // 0x3D7A
  UVD_MPC_SET_MUXB0                                      :TUVD_MPC_SET_MUXB0;                                // 0x3D7B
  UVD_MPC_SET_MUXB1                                      :TUVD_MPC_SET_MUXB1;                                // 0x3D7C
  UVD_MPC_SET_MUX                                        :TUVD_MPC_SET_MUX;                                  // 0x3D7D
  UVD_MPC_SET_ALU                                        :TUVD_MPC_SET_ALU;                                  // 0x3D7E
  REG_3D7F_3D81                                          :array[0..2] of DWORD;                              // 0x3D7F
  UVD_VCPU_CACHE_OFFSET0                                 :TUVD_VCPU_CACHE_OFFSET0;                           // 0x3D82
  UVD_VCPU_CACHE_SIZE0                                   :TUVD_VCPU_CACHE_SIZE0;                             // 0x3D83
  UVD_VCPU_CACHE_OFFSET1                                 :TUVD_VCPU_CACHE_OFFSET1;                           // 0x3D84
  UVD_VCPU_CACHE_SIZE1                                   :TUVD_VCPU_CACHE_SIZE1;                             // 0x3D85
  UVD_VCPU_CACHE_OFFSET2                                 :TUVD_VCPU_CACHE_OFFSET2;                           // 0x3D86
  UVD_VCPU_CACHE_SIZE2                                   :TUVD_VCPU_CACHE_SIZE2;                             // 0x3D87
  REG_3D88_3D97                                          :array[0..15] of DWORD;                             // 0x3D88
  UVD_VCPU_CNTL                                          :TUVD_VCPU_CNTL;                                    // 0x3D98
  REG_3D99_3D9F                                          :array[0..6] of DWORD;                              // 0x3D99
  UVD_SOFT_RESET                                         :TUVD_SOFT_RESET;                                   // 0x3DA0
  UVD_LMI_RBC_IB_VMID                                    :TUVD_LMI_RBC_IB_VMID;                              // 0x3DA1
  UVD_RBC_IB_SIZE                                        :TUVD_RBC_IB_SIZE;                                  // 0x3DA2
  UVD_LMI_RBC_RB_VMID                                    :TUVD_LMI_RBC_RB_VMID;                              // 0x3DA3
  UVD_RBC_RB_RPTR                                        :TUVD_RBC_RB_RPTR;                                  // 0x3DA4
  UVD_RBC_RB_WPTR                                        :TUVD_RBC_RB_WPTR;                                  // 0x3DA5
  REG_3DA6_3DA8                                          :array[0..2] of DWORD;                              // 0x3DA6
  UVD_RBC_RB_CNTL                                        :TUVD_RBC_RB_CNTL;                                  // 0x3DA9
  UVD_RBC_RB_RPTR_ADDR                                   :TUVD_RBC_RB_RPTR_ADDR;                             // 0x3DAA
  REG_3DAB_3DAE                                          :array[0..3] of DWORD;                              // 0x3DAB
  UVD_STATUS                                             :TUVD_STATUS;                                       // 0x3DAF
  UVD_SEMA_TIMEOUT_STATUS                                :TUVD_SEMA_TIMEOUT_STATUS;                          // 0x3DB0
  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                  :TUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL;            // 0x3DB1
  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                       :TUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL;                 // 0x3DB2
  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                :TUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL;          // 0x3DB3
  REG_3DB4_3DBC                                          :array[0..8] of DWORD;                              // 0x3DB4
  UVD_CONTEXT_ID                                         :TUVD_CONTEXT_ID;                                   // 0x3DBD
  REG_3DBE_3FFF                                          :array[0..577] of DWORD;                            // 0x3DBE
  DCP3_GRPH_ENABLE                                       :DWORD;                                             // 0x4000
  DCP3_GRPH_CONTROL                                      :DWORD;                                             // 0x4001
  DCP3_GRPH_LUT_10BIT_BYPASS                             :DWORD;                                             // 0x4002
  DCP3_GRPH_SWAP_CNTL                                    :DWORD;                                             // 0x4003
  DCP3_GRPH_PRIMARY_SURFACE_ADDRESS                      :DWORD;                                             // 0x4004
  DCP3_GRPH_SECONDARY_SURFACE_ADDRESS                    :DWORD;                                             // 0x4005
  DCP3_GRPH_PITCH                                        :DWORD;                                             // 0x4006
  DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                 :DWORD;                                             // 0x4007
  DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH               :DWORD;                                             // 0x4008
  DCP3_GRPH_SURFACE_OFFSET_X                             :DWORD;                                             // 0x4009
  DCP3_GRPH_SURFACE_OFFSET_Y                             :DWORD;                                             // 0x400A
  DCP3_GRPH_X_START                                      :DWORD;                                             // 0x400B
  DCP3_GRPH_Y_START                                      :DWORD;                                             // 0x400C
  DCP3_GRPH_X_END                                        :DWORD;                                             // 0x400D
  DCP3_GRPH_Y_END                                        :DWORD;                                             // 0x400E
  REG_400F                                               :DWORD;                                             // 0x400F
  DCP3_INPUT_GAMMA_CONTROL                               :DWORD;                                             // 0x4010
  DCP3_GRPH_UPDATE                                       :DWORD;                                             // 0x4011
  DCP3_GRPH_FLIP_CONTROL                                 :DWORD;                                             // 0x4012
  DCP3_GRPH_SURFACE_ADDRESS_INUSE                        :DWORD;                                             // 0x4013
  DCP3_GRPH_DFQ_CONTROL                                  :DWORD;                                             // 0x4014
  DCP3_GRPH_DFQ_STATUS                                   :DWORD;                                             // 0x4015
  DCP3_GRPH_INTERRUPT_STATUS                             :DWORD;                                             // 0x4016
  DCP3_GRPH_INTERRUPT_CONTROL                            :DWORD;                                             // 0x4017
  DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE                   :DWORD;                                             // 0x4018
  DCP3_GRPH_COMPRESS_SURFACE_ADDRESS                     :DWORD;                                             // 0x4019
  DCP3_GRPH_COMPRESS_PITCH                               :DWORD;                                             // 0x401A
  DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                :DWORD;                                             // 0x401B
  DCP3_OVL_ENABLE                                        :DWORD;                                             // 0x401C
  DCP3_OVL_CONTROL1                                      :DWORD;                                             // 0x401D
  DCP3_OVL_CONTROL2                                      :DWORD;                                             // 0x401E
  DCP3_OVL_SWAP_CNTL                                     :DWORD;                                             // 0x401F
  DCP3_OVL_SURFACE_ADDRESS                               :DWORD;                                             // 0x4020
  DCP3_OVL_PITCH                                         :DWORD;                                             // 0x4021
  DCP3_OVL_SURFACE_ADDRESS_HIGH                          :DWORD;                                             // 0x4022
  DCP3_OVL_SURFACE_OFFSET_X                              :DWORD;                                             // 0x4023
  DCP3_OVL_SURFACE_OFFSET_Y                              :DWORD;                                             // 0x4024
  DCP3_OVL_START                                         :DWORD;                                             // 0x4025
  DCP3_OVL_END                                           :DWORD;                                             // 0x4026
  DCP3_OVL_UPDATE                                        :DWORD;                                             // 0x4027
  DCP3_OVL_SURFACE_ADDRESS_INUSE                         :DWORD;                                             // 0x4028
  DCP3_OVL_DFQ_CONTROL                                   :DWORD;                                             // 0x4029
  DCP3_OVL_DFQ_STATUS                                    :DWORD;                                             // 0x402A
  DCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE                    :DWORD;                                             // 0x402B
  DCP3_OVLSCL_EDGE_PIXEL_CNTL                            :DWORD;                                             // 0x402C
  DCP3_PRESCALE_GRPH_CONTROL                             :DWORD;                                             // 0x402D
  DCP3_PRESCALE_VALUES_GRPH_R                            :DWORD;                                             // 0x402E
  DCP3_PRESCALE_VALUES_GRPH_G                            :DWORD;                                             // 0x402F
  DCP3_PRESCALE_VALUES_GRPH_B                            :DWORD;                                             // 0x4030
  DCP3_PRESCALE_OVL_CONTROL                              :DWORD;                                             // 0x4031
  DCP3_PRESCALE_VALUES_OVL_CB                            :DWORD;                                             // 0x4032
  DCP3_PRESCALE_VALUES_OVL_Y                             :DWORD;                                             // 0x4033
  DCP3_PRESCALE_VALUES_OVL_CR                            :DWORD;                                             // 0x4034
  DCP3_INPUT_CSC_CONTROL                                 :DWORD;                                             // 0x4035
  DCP3_INPUT_CSC_C11_C12                                 :DWORD;                                             // 0x4036
  DCP3_INPUT_CSC_C13_C14                                 :DWORD;                                             // 0x4037
  DCP3_INPUT_CSC_C21_C22                                 :DWORD;                                             // 0x4038
  DCP3_INPUT_CSC_C23_C24                                 :DWORD;                                             // 0x4039
  DCP3_INPUT_CSC_C31_C32                                 :DWORD;                                             // 0x403A
  DCP3_INPUT_CSC_C33_C34                                 :DWORD;                                             // 0x403B
  DCP3_OUTPUT_CSC_CONTROL                                :DWORD;                                             // 0x403C
  DCP3_OUTPUT_CSC_C11_C12                                :DWORD;                                             // 0x403D
  DCP3_OUTPUT_CSC_C13_C14                                :DWORD;                                             // 0x403E
  DCP3_OUTPUT_CSC_C21_C22                                :DWORD;                                             // 0x403F
  DCP3_OUTPUT_CSC_C23_C24                                :DWORD;                                             // 0x4040
  DCP3_OUTPUT_CSC_C31_C32                                :DWORD;                                             // 0x4041
  DCP3_OUTPUT_CSC_C33_C34                                :DWORD;                                             // 0x4042
  DCP3_COMM_MATRIXA_TRANS_C11_C12                        :DWORD;                                             // 0x4043
  DCP3_COMM_MATRIXA_TRANS_C13_C14                        :DWORD;                                             // 0x4044
  DCP3_COMM_MATRIXA_TRANS_C21_C22                        :DWORD;                                             // 0x4045
  DCP3_COMM_MATRIXA_TRANS_C23_C24                        :DWORD;                                             // 0x4046
  DCP3_COMM_MATRIXA_TRANS_C31_C32                        :DWORD;                                             // 0x4047
  DCP3_COMM_MATRIXA_TRANS_C33_C34                        :DWORD;                                             // 0x4048
  DCP3_COMM_MATRIXB_TRANS_C11_C12                        :DWORD;                                             // 0x4049
  DCP3_COMM_MATRIXB_TRANS_C13_C14                        :DWORD;                                             // 0x404A
  DCP3_COMM_MATRIXB_TRANS_C21_C22                        :DWORD;                                             // 0x404B
  DCP3_COMM_MATRIXB_TRANS_C23_C24                        :DWORD;                                             // 0x404C
  DCP3_COMM_MATRIXB_TRANS_C31_C32                        :DWORD;                                             // 0x404D
  DCP3_COMM_MATRIXB_TRANS_C33_C34                        :DWORD;                                             // 0x404E
  REG_404F                                               :DWORD;                                             // 0x404F
  DCP3_DENORM_CONTROL                                    :DWORD;                                             // 0x4050
  DCP3_OUT_ROUND_CONTROL                                 :DWORD;                                             // 0x4051
  DCP3_OUT_CLAMP_CONTROL_R_CR                            :DWORD;                                             // 0x4052
  DCP3_KEY_CONTROL                                       :DWORD;                                             // 0x4053
  DCP3_KEY_RANGE_ALPHA                                   :DWORD;                                             // 0x4054
  DCP3_KEY_RANGE_RED                                     :DWORD;                                             // 0x4055
  DCP3_KEY_RANGE_GREEN                                   :DWORD;                                             // 0x4056
  DCP3_KEY_RANGE_BLUE                                    :DWORD;                                             // 0x4057
  DCP3_DEGAMMA_CONTROL                                   :DWORD;                                             // 0x4058
  DCP3_GAMUT_REMAP_CONTROL                               :DWORD;                                             // 0x4059
  DCP3_GAMUT_REMAP_C11_C12                               :DWORD;                                             // 0x405A
  DCP3_GAMUT_REMAP_C13_C14                               :DWORD;                                             // 0x405B
  DCP3_GAMUT_REMAP_C21_C22                               :DWORD;                                             // 0x405C
  DCP3_GAMUT_REMAP_C23_C24                               :DWORD;                                             // 0x405D
  DCP3_GAMUT_REMAP_C31_C32                               :DWORD;                                             // 0x405E
  DCP3_GAMUT_REMAP_C33_C34                               :DWORD;                                             // 0x405F
  DCP3_DCP_SPATIAL_DITHER_CNTL                           :DWORD;                                             // 0x4060
  DCP3_DCP_RANDOM_SEEDS                                  :DWORD;                                             // 0x4061
  REG_4062_4064                                          :array[0..2] of DWORD;                              // 0x4062
  DCP3_DCP_FP_CONVERTED_FIELD                            :DWORD;                                             // 0x4065
  DCP3_CUR_CONTROL                                       :DWORD;                                             // 0x4066
  DCP3_CUR_SURFACE_ADDRESS                               :DWORD;                                             // 0x4067
  DCP3_CUR_SIZE                                          :DWORD;                                             // 0x4068
  DCP3_CUR_SURFACE_ADDRESS_HIGH                          :DWORD;                                             // 0x4069
  DCP3_CUR_POSITION                                      :DWORD;                                             // 0x406A
  DCP3_CUR_HOT_SPOT                                      :DWORD;                                             // 0x406B
  DCP3_CUR_COLOR1                                        :DWORD;                                             // 0x406C
  DCP3_CUR_COLOR2                                        :DWORD;                                             // 0x406D
  DCP3_CUR_UPDATE                                        :DWORD;                                             // 0x406E
  DCP3_CUR2_CONTROL                                      :DWORD;                                             // 0x406F
  DCP3_CUR2_SURFACE_ADDRESS                              :DWORD;                                             // 0x4070
  DCP3_CUR2_SIZE                                         :DWORD;                                             // 0x4071
  DCP3_CUR2_SURFACE_ADDRESS_HIGH                         :DWORD;                                             // 0x4072
  DCP3_CUR2_POSITION                                     :DWORD;                                             // 0x4073
  DCP3_CUR2_HOT_SPOT                                     :DWORD;                                             // 0x4074
  DCP3_CUR2_COLOR1                                       :DWORD;                                             // 0x4075
  DCP3_CUR2_COLOR2                                       :DWORD;                                             // 0x4076
  DCP3_CUR2_UPDATE                                       :DWORD;                                             // 0x4077
  DCP3_DC_LUT_RW_MODE                                    :DWORD;                                             // 0x4078
  DCP3_DC_LUT_RW_INDEX                                   :DWORD;                                             // 0x4079
  DCP3_DC_LUT_SEQ_COLOR                                  :DWORD;                                             // 0x407A
  DCP3_DC_LUT_PWL_DATA                                   :DWORD;                                             // 0x407B
  DCP3_DC_LUT_30_COLOR                                   :DWORD;                                             // 0x407C
  DCP3_DC_LUT_VGA_ACCESS_ENABLE                          :DWORD;                                             // 0x407D
  DCP3_DC_LUT_WRITE_EN_MASK                              :DWORD;                                             // 0x407E
  DCP3_DC_LUT_AUTOFILL                                   :DWORD;                                             // 0x407F
  DCP3_DC_LUT_CONTROL                                    :DWORD;                                             // 0x4080
  DCP3_DC_LUT_BLACK_OFFSET_BLUE                          :DWORD;                                             // 0x4081
  DCP3_DC_LUT_BLACK_OFFSET_GREEN                         :DWORD;                                             // 0x4082
  DCP3_DC_LUT_BLACK_OFFSET_RED                           :DWORD;                                             // 0x4083
  DCP3_DC_LUT_WHITE_OFFSET_BLUE                          :DWORD;                                             // 0x4084
  DCP3_DC_LUT_WHITE_OFFSET_GREEN                         :DWORD;                                             // 0x4085
  DCP3_DC_LUT_WHITE_OFFSET_RED                           :DWORD;                                             // 0x4086
  DCP3_DCP_CRC_CONTROL                                   :DWORD;                                             // 0x4087
  DCP3_DCP_CRC_MASK                                      :DWORD;                                             // 0x4088
  DCP3_DCP_CRC_CURRENT                                   :DWORD;                                             // 0x4089
  REG_408A                                               :DWORD;                                             // 0x408A
  DCP3_DCP_CRC_LAST                                      :DWORD;                                             // 0x408B
  REG_408C                                               :DWORD;                                             // 0x408C
  DCP3_DCP_DEBUG                                         :DWORD;                                             // 0x408D
  DCP3_GRPH_FLIP_RATE_CNTL                               :DWORD;                                             // 0x408E
  REG_408F                                               :DWORD;                                             // 0x408F
  DCP3_DCP_GSL_CONTROL                                   :DWORD;                                             // 0x4090
  DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK                     :DWORD;                                             // 0x4091
  DCP3_OVL_SECONDARY_SURFACE_ADDRESS                     :DWORD;                                             // 0x4092
  DCP3_OVL_STEREOSYNC_FLIP                               :DWORD;                                             // 0x4093
  DCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                :DWORD;                                             // 0x4094
  DCP3_DCP_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x4095
  DCP3_DCP_TEST_DEBUG_DATA                               :DWORD;                                             // 0x4096
  DCP3_GRPH_STEREOSYNC_FLIP                              :DWORD;                                             // 0x4097
  DCP3_DCP_DEBUG2                                        :DWORD;                                             // 0x4098
  DCP3_CUR_REQUEST_FILTER_CNTL                           :DWORD;                                             // 0x4099
  DCP3_CUR_STEREO_CONTROL                                :DWORD;                                             // 0x409A
  DCP3_CUR2_STEREO_CONTROL                               :DWORD;                                             // 0x409B
  DCP3_OUT_CLAMP_CONTROL_G_Y                             :DWORD;                                             // 0x409C
  DCP3_OUT_CLAMP_CONTROL_B_CB                            :DWORD;                                             // 0x409D
  DCP3_HW_ROTATION                                       :DWORD;                                             // 0x409E
  DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                :DWORD;                                             // 0x409F
  DCP3_REGAMMA_CONTROL                                   :DWORD;                                             // 0x40A0
  DCP3_REGAMMA_LUT_INDEX                                 :DWORD;                                             // 0x40A1
  DCP3_REGAMMA_LUT_DATA                                  :DWORD;                                             // 0x40A2
  DCP3_REGAMMA_LUT_WRITE_EN_MASK                         :DWORD;                                             // 0x40A3
  DCP3_REGAMMA_CNTLA_START_CNTL                          :DWORD;                                             // 0x40A4
  DCP3_REGAMMA_CNTLA_SLOPE_CNTL                          :DWORD;                                             // 0x40A5
  DCP3_REGAMMA_CNTLA_END_CNTL1                           :DWORD;                                             // 0x40A6
  DCP3_REGAMMA_CNTLA_END_CNTL2                           :DWORD;                                             // 0x40A7
  DCP3_REGAMMA_CNTLA_REGION_0_1                          :DWORD;                                             // 0x40A8
  DCP3_REGAMMA_CNTLA_REGION_2_3                          :DWORD;                                             // 0x40A9
  DCP3_REGAMMA_CNTLA_REGION_4_5                          :DWORD;                                             // 0x40AA
  DCP3_REGAMMA_CNTLA_REGION_6_7                          :DWORD;                                             // 0x40AB
  DCP3_REGAMMA_CNTLA_REGION_8_9                          :DWORD;                                             // 0x40AC
  DCP3_REGAMMA_CNTLA_REGION_10_11                        :DWORD;                                             // 0x40AD
  DCP3_REGAMMA_CNTLA_REGION_12_13                        :DWORD;                                             // 0x40AE
  DCP3_REGAMMA_CNTLA_REGION_14_15                        :DWORD;                                             // 0x40AF
  DCP3_REGAMMA_CNTLB_START_CNTL                          :DWORD;                                             // 0x40B0
  DCP3_REGAMMA_CNTLB_SLOPE_CNTL                          :DWORD;                                             // 0x40B1
  DCP3_REGAMMA_CNTLB_END_CNTL1                           :DWORD;                                             // 0x40B2
  DCP3_REGAMMA_CNTLB_END_CNTL2                           :DWORD;                                             // 0x40B3
  DCP3_REGAMMA_CNTLB_REGION_0_1                          :DWORD;                                             // 0x40B4
  DCP3_REGAMMA_CNTLB_REGION_2_3                          :DWORD;                                             // 0x40B5
  DCP3_REGAMMA_CNTLB_REGION_4_5                          :DWORD;                                             // 0x40B6
  DCP3_REGAMMA_CNTLB_REGION_6_7                          :DWORD;                                             // 0x40B7
  DCP3_REGAMMA_CNTLB_REGION_8_9                          :DWORD;                                             // 0x40B8
  DCP3_REGAMMA_CNTLB_REGION_10_11                        :DWORD;                                             // 0x40B9
  DCP3_REGAMMA_CNTLB_REGION_12_13                        :DWORD;                                             // 0x40BA
  DCP3_REGAMMA_CNTLB_REGION_14_15                        :DWORD;                                             // 0x40BB
  DCP3_ALPHA_CONTROL                                     :DWORD;                                             // 0x40BC
  DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                :DWORD;                                             // 0x40BD
  DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH           :DWORD;                                             // 0x40BE
  DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS              :DWORD;                                             // 0x40BF
  LB3_LB_DATA_FORMAT                                     :DWORD;                                             // 0x40C0
  LB3_LB_MEMORY_CTRL                                     :DWORD;                                             // 0x40C1
  LB3_LB_MEMORY_SIZE_STATUS                              :DWORD;                                             // 0x40C2
  LB3_LB_DESKTOP_HEIGHT                                  :DWORD;                                             // 0x40C3
  LB3_LB_VLINE_START_END                                 :DWORD;                                             // 0x40C4
  LB3_LB_VLINE2_START_END                                :DWORD;                                             // 0x40C5
  LB3_LB_V_COUNTER                                       :DWORD;                                             // 0x40C6
  LB3_LB_SNAPSHOT_V_COUNTER                              :DWORD;                                             // 0x40C7
  LB3_LB_INTERRUPT_MASK                                  :DWORD;                                             // 0x40C8
  LB3_LB_VLINE_STATUS                                    :DWORD;                                             // 0x40C9
  LB3_LB_VLINE2_STATUS                                   :DWORD;                                             // 0x40CA
  LB3_LB_VBLANK_STATUS                                   :DWORD;                                             // 0x40CB
  LB3_LB_SYNC_RESET_SEL                                  :DWORD;                                             // 0x40CC
  LB3_LB_BLACK_KEYER_R_CR                                :DWORD;                                             // 0x40CD
  LB3_LB_BLACK_KEYER_G_Y                                 :DWORD;                                             // 0x40CE
  LB3_LB_BLACK_KEYER_B_CB                                :DWORD;                                             // 0x40CF
  LB3_LB_KEYER_COLOR_CTRL                                :DWORD;                                             // 0x40D0
  LB3_LB_KEYER_COLOR_R_CR                                :DWORD;                                             // 0x40D1
  LB3_LB_KEYER_COLOR_G_Y                                 :DWORD;                                             // 0x40D2
  LB3_LB_KEYER_COLOR_B_CB                                :DWORD;                                             // 0x40D3
  LB3_LB_KEYER_COLOR_REP_R_CR                            :DWORD;                                             // 0x40D4
  LB3_LB_KEYER_COLOR_REP_G_Y                             :DWORD;                                             // 0x40D5
  LB3_LB_KEYER_COLOR_REP_B_CB                            :DWORD;                                             // 0x40D6
  LB3_LB_BUFFER_LEVEL_STATUS                             :DWORD;                                             // 0x40D7
  LB3_LB_BUFFER_URGENCY_CTRL                             :DWORD;                                             // 0x40D8
  LB3_LB_BUFFER_URGENCY_STATUS                           :DWORD;                                             // 0x40D9
  LB3_LB_BUFFER_STATUS                                   :DWORD;                                             // 0x40DA
  LB2_DC_MVP_LB_CONTROL                                  :DWORD;                                             // 0x40DB
  LB3_LB_NO_OUTSTANDING_REQ_STATUS                       :DWORD;                                             // 0x40DC
  REG_40DD_40DF                                          :array[0..2] of DWORD;                              // 0x40DD
  LB3_MVP_AFR_FLIP_MODE                                  :DWORD;                                             // 0x40E0
  LB3_MVP_AFR_FLIP_FIFO_CNTL                             :DWORD;                                             // 0x40E1
  LB3_MVP_FLIP_LINE_NUM_INSERT                           :DWORD;                                             // 0x40E2
  LB3_DC_MVP_LB_CONTROL                                  :DWORD;                                             // 0x40E3
  LB3_LB_DEBUG                                           :DWORD;                                             // 0x40E4
  LB3_LB_DEBUG2                                          :DWORD;                                             // 0x40E5
  LB3_LB_DEBUG3                                          :DWORD;                                             // 0x40E6
  REG_40E7_40FB                                          :array[0..20] of DWORD;                             // 0x40E7
  LB2_LB_DEBUG                                           :DWORD;                                             // 0x40FC
  REG_40FD                                               :DWORD;                                             // 0x40FD
  LB3_LB_TEST_DEBUG_INDEX                                :DWORD;                                             // 0x40FE
  LB3_LB_TEST_DEBUG_DATA                                 :DWORD;                                             // 0x40FF
  DCFE3_DCFE_CLOCK_CONTROL                               :DWORD;                                             // 0x4100
  DCFE3_DCFE_SOFT_RESET                                  :DWORD;                                             // 0x4101
  DCFE3_DCFE_DBG_CONFIG                                  :DWORD;                                             // 0x4102
  REG_4103_4123                                          :array[0..32] of DWORD;                             // 0x4103
  DC_PERFMON6_PERFCOUNTER_CNTL                           :DWORD;                                             // 0x4124
  DC_PERFMON6_PERFCOUNTER_STATE                          :DWORD;                                             // 0x4125
  DC_PERFMON6_PERFMON_CVALUE_INT_MISC                    :DWORD;                                             // 0x4126
  DC_PERFMON6_PERFMON_CNTL                               :DWORD;                                             // 0x4127
  DC_PERFMON6_PERFMON_CVALUE_LOW                         :DWORD;                                             // 0x4128
  DC_PERFMON6_PERFMON_HI                                 :DWORD;                                             // 0x4129
  DC_PERFMON6_PERFMON_LOW                                :DWORD;                                             // 0x412A
  DC_PERFMON6_PERFMON_TEST_DEBUG_INDEX                   :DWORD;                                             // 0x412B
  DC_PERFMON6_PERFMON_TEST_DEBUG_DATA                    :DWORD;                                             // 0x412C
  REG_412D                                               :DWORD;                                             // 0x412D
  DC_PERFMON6_PERFMON_CNTL2                              :DWORD;                                             // 0x412E
  REG_412F                                               :DWORD;                                             // 0x412F
  DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1                 :DWORD;                                             // 0x4130
  DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2                 :DWORD;                                             // 0x4131
  DMIF_PG3_DPG_WATERMARK_MASK_CONTROL                    :DWORD;                                             // 0x4132
  DMIF_PG3_DPG_PIPE_URGENCY_CONTROL                      :DWORD;                                             // 0x4133
  DMIF_PG3_DPG_PIPE_DPM_CONTROL                          :DWORD;                                             // 0x4134
  DMIF_PG3_DPG_PIPE_STUTTER_CONTROL                      :DWORD;                                             // 0x4135
  DMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             :DWORD;                                             // 0x4136
  DMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             :DWORD;                                             // 0x4137
  DMIF_PG3_DPG_TEST_DEBUG_INDEX                          :DWORD;                                             // 0x4138
  DMIF_PG3_DPG_TEST_DEBUG_DATA                           :DWORD;                                             // 0x4139
  DMIF_PG3_DPG_REPEATER_PROGRAM                          :DWORD;                                             // 0x413A
  DMIF_PG3_DPG_HW_DEBUG_A                                :DWORD;                                             // 0x413B
  DMIF_PG3_DPG_HW_DEBUG_B                                :DWORD;                                             // 0x413C
  DMIF_PG3_DPG_HW_DEBUG_11                               :DWORD;                                             // 0x413D
  REG_413E_413F                                          :array[0..1] of DWORD;                              // 0x413E
  SCL3_SCL_COEF_RAM_SELECT                               :DWORD;                                             // 0x4140
  SCL3_SCL_COEF_RAM_TAP_DATA                             :DWORD;                                             // 0x4141
  SCL3_SCL_MODE                                          :DWORD;                                             // 0x4142
  SCL3_SCL_TAP_CONTROL                                   :DWORD;                                             // 0x4143
  SCL3_SCL_CONTROL                                       :DWORD;                                             // 0x4144
  SCL3_SCL_BYPASS_CONTROL                                :DWORD;                                             // 0x4145
  SCL3_SCL_MANUAL_REPLICATE_CONTROL                      :DWORD;                                             // 0x4146
  SCL3_SCL_AUTOMATIC_MODE_CONTROL                        :DWORD;                                             // 0x4147
  SCL3_SCL_HORZ_FILTER_CONTROL                           :DWORD;                                             // 0x4148
  SCL3_SCL_HORZ_FILTER_SCALE_RATIO                       :DWORD;                                             // 0x4149
  SCL3_SCL_HORZ_FILTER_INIT                              :DWORD;                                             // 0x414A
  SCL3_SCL_VERT_FILTER_CONTROL                           :DWORD;                                             // 0x414B
  SCL3_SCL_VERT_FILTER_SCALE_RATIO                       :DWORD;                                             // 0x414C
  SCL3_SCL_VERT_FILTER_INIT                              :DWORD;                                             // 0x414D
  SCL3_SCL_VERT_FILTER_INIT_BOT                          :DWORD;                                             // 0x414E
  SCL3_SCL_ROUND_OFFSET                                  :DWORD;                                             // 0x414F
  SCL2_SCL_VERT_FILTER_INIT                              :DWORD;                                             // 0x4150
  SCL3_SCL_UPDATE                                        :DWORD;                                             // 0x4151
  REG_4152                                               :DWORD;                                             // 0x4152
  SCL3_SCL_F_SHARP_CONTROL                               :DWORD;                                             // 0x4153
  SCL3_SCL_ALU_CONTROL                                   :DWORD;                                             // 0x4154
  SCL3_SCL_COEF_RAM_CONFLICT_STATUS                      :DWORD;                                             // 0x4155
  REG_4156                                               :DWORD;                                             // 0x4156
  SCL2_SCL_VERT_FILTER_INIT_BOT                          :DWORD;                                             // 0x4157
  REG_4158_415A                                          :array[0..2] of DWORD;                              // 0x4158
  SCL3_VIEWPORT_START_SECONDARY                          :DWORD;                                             // 0x415B
  SCL3_VIEWPORT_START                                    :DWORD;                                             // 0x415C
  SCL3_VIEWPORT_SIZE                                     :DWORD;                                             // 0x415D
  SCL3_EXT_OVERSCAN_LEFT_RIGHT                           :DWORD;                                             // 0x415E
  SCL3_EXT_OVERSCAN_TOP_BOTTOM                           :DWORD;                                             // 0x415F
  SCL3_SCL_MODE_CHANGE_DET1                              :DWORD;                                             // 0x4160
  SCL3_SCL_MODE_CHANGE_DET2                              :DWORD;                                             // 0x4161
  SCL3_SCL_MODE_CHANGE_DET3                              :DWORD;                                             // 0x4162
  SCL3_SCL_MODE_CHANGE_MASK                              :DWORD;                                             // 0x4163
  REG_4164_4168                                          :array[0..4] of DWORD;                              // 0x4164
  SCL3_SCL_DEBUG2                                        :DWORD;                                             // 0x4169
  SCL3_SCL_DEBUG                                         :DWORD;                                             // 0x416A
  SCL3_SCL_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x416B
  SCL3_SCL_TEST_DEBUG_DATA                               :DWORD;                                             // 0x416C
  BLND3_BLND_CONTROL                                     :DWORD;                                             // 0x416D
  BLND3_SM_CONTROL2                                      :DWORD;                                             // 0x416E
  BLND3_BLND_CONTROL2                                    :DWORD;                                             // 0x416F
  BLND3_BLND_UPDATE                                      :DWORD;                                             // 0x4170
  BLND3_BLND_UNDERFLOW_INTERRUPT                         :DWORD;                                             // 0x4171
  REG_4172                                               :DWORD;                                             // 0x4172
  BLND3_BLND_V_UPDATE_LOCK                               :DWORD;                                             // 0x4173
  BLND3_BLND_DEBUG                                       :DWORD;                                             // 0x4174
  BLND3_BLND_TEST_DEBUG_INDEX                            :DWORD;                                             // 0x4175
  BLND3_BLND_TEST_DEBUG_DATA                             :DWORD;                                             // 0x4176
  BLND3_BLND_REG_UPDATE_STATUS                           :DWORD;                                             // 0x4177
  CRTC3_CRTC_3D_STRUCTURE_CONTROL                        :DWORD;                                             // 0x4178
  CRTC3_CRTC_GSL_VSYNC_GAP                               :DWORD;                                             // 0x4179
  CRTC3_CRTC_GSL_WINDOW                                  :DWORD;                                             // 0x417A
  CRTC3_CRTC_GSL_CONTROL                                 :DWORD;                                             // 0x417B
  CRTC3_CRTC_DCFE_CLOCK_CONTROL                          :DWORD;                                             // 0x417C
  CRTC3_CRTC_H_BLANK_EARLY_NUM                           :DWORD;                                             // 0x417D
  CRTC3_DCFE_DBG_SEL                                     :DWORD;                                             // 0x417E
  CRTC3_DCFE_MEM_PWR_CTRL                                :DWORD;                                             // 0x417F
  CRTC3_CRTC_H_TOTAL                                     :DWORD;                                             // 0x4180
  CRTC3_CRTC_H_BLANK_START_END                           :DWORD;                                             // 0x4181
  CRTC3_CRTC_H_SYNC_A                                    :DWORD;                                             // 0x4182
  CRTC3_CRTC_H_SYNC_A_CNTL                               :DWORD;                                             // 0x4183
  CRTC3_CRTC_H_SYNC_B                                    :DWORD;                                             // 0x4184
  CRTC3_CRTC_H_SYNC_B_CNTL                               :DWORD;                                             // 0x4185
  CRTC3_CRTC_VBI_END                                     :DWORD;                                             // 0x4186
  CRTC3_CRTC_V_TOTAL                                     :DWORD;                                             // 0x4187
  CRTC3_CRTC_V_TOTAL_MIN                                 :DWORD;                                             // 0x4188
  CRTC3_CRTC_V_TOTAL_MAX                                 :DWORD;                                             // 0x4189
  CRTC3_CRTC_V_TOTAL_CONTROL                             :DWORD;                                             // 0x418A
  CRTC3_CRTC_V_TOTAL_INT_STATUS                          :DWORD;                                             // 0x418B
  CRTC3_CRTC_VSYNC_NOM_INT_STATUS                        :DWORD;                                             // 0x418C
  CRTC3_CRTC_V_BLANK_START_END                           :DWORD;                                             // 0x418D
  CRTC3_CRTC_V_SYNC_A                                    :DWORD;                                             // 0x418E
  CRTC3_CRTC_V_SYNC_A_CNTL                               :DWORD;                                             // 0x418F
  CRTC3_CRTC_V_SYNC_B                                    :DWORD;                                             // 0x4190
  CRTC3_CRTC_V_SYNC_B_CNTL                               :DWORD;                                             // 0x4191
  CRTC3_CRTC_DTMTEST_CNTL                                :DWORD;                                             // 0x4192
  CRTC3_CRTC_DTMTEST_STATUS_POSITION                     :DWORD;                                             // 0x4193
  CRTC3_CRTC_TRIGA_CNTL                                  :DWORD;                                             // 0x4194
  CRTC3_CRTC_TRIGA_MANUAL_TRIG                           :DWORD;                                             // 0x4195
  CRTC3_CRTC_TRIGB_CNTL                                  :DWORD;                                             // 0x4196
  CRTC3_CRTC_TRIGB_MANUAL_TRIG                           :DWORD;                                             // 0x4197
  CRTC3_CRTC_FORCE_COUNT_NOW_CNTL                        :DWORD;                                             // 0x4198
  CRTC3_CRTC_FLOW_CONTROL                                :DWORD;                                             // 0x4199
  CRTC3_CRTC_STEREO_FORCE_NEXT_EYE                       :DWORD;                                             // 0x419A
  CRTC3_CRTC_AVSYNC_COUNTER                              :DWORD;                                             // 0x419B
  CRTC3_CRTC_CONTROL                                     :DWORD;                                             // 0x419C
  CRTC3_CRTC_BLANK_CONTROL                               :DWORD;                                             // 0x419D
  CRTC3_CRTC_INTERLACE_CONTROL                           :DWORD;                                             // 0x419E
  CRTC3_CRTC_INTERLACE_STATUS                            :DWORD;                                             // 0x419F
  CRTC3_CRTC_FIELD_INDICATION_CONTROL                    :DWORD;                                             // 0x41A0
  CRTC3_CRTC_PIXEL_DATA_READBACK0                        :DWORD;                                             // 0x41A1
  CRTC3_CRTC_PIXEL_DATA_READBACK1                        :DWORD;                                             // 0x41A2
  CRTC3_CRTC_STATUS                                      :DWORD;                                             // 0x41A3
  CRTC3_CRTC_STATUS_POSITION                             :DWORD;                                             // 0x41A4
  CRTC3_CRTC_NOM_VERT_POSITION                           :DWORD;                                             // 0x41A5
  CRTC3_CRTC_STATUS_FRAME_COUNT                          :DWORD;                                             // 0x41A6
  CRTC3_CRTC_STATUS_VF_COUNT                             :DWORD;                                             // 0x41A7
  CRTC3_CRTC_STATUS_HV_COUNT                             :DWORD;                                             // 0x41A8
  CRTC3_CRTC_COUNT_CONTROL                               :DWORD;                                             // 0x41A9
  CRTC3_CRTC_COUNT_RESET                                 :DWORD;                                             // 0x41AA
  CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                :DWORD;                                             // 0x41AB
  CRTC3_CRTC_VERT_SYNC_CONTROL                           :DWORD;                                             // 0x41AC
  CRTC3_CRTC_STEREO_STATUS                               :DWORD;                                             // 0x41AD
  CRTC3_CRTC_STEREO_CONTROL                              :DWORD;                                             // 0x41AE
  CRTC3_CRTC_SNAPSHOT_STATUS                             :DWORD;                                             // 0x41AF
  CRTC3_CRTC_SNAPSHOT_CONTROL                            :DWORD;                                             // 0x41B0
  CRTC3_CRTC_SNAPSHOT_POSITION                           :DWORD;                                             // 0x41B1
  CRTC3_CRTC_SNAPSHOT_FRAME                              :DWORD;                                             // 0x41B2
  CRTC3_CRTC_START_LINE_CONTROL                          :DWORD;                                             // 0x41B3
  CRTC3_CRTC_INTERRUPT_CONTROL                           :DWORD;                                             // 0x41B4
  CRTC3_CRTC_UPDATE_LOCK                                 :DWORD;                                             // 0x41B5
  CRTC3_CRTC_DOUBLE_BUFFER_CONTROL                       :DWORD;                                             // 0x41B6
  CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE                  :DWORD;                                             // 0x41B7
  CRTC3_DCFE_MEM_PWR_CTRL2                               :DWORD;                                             // 0x41B8
  CRTC3_DCFE_MEM_PWR_STATUS                              :DWORD;                                             // 0x41B9
  CRTC3_CRTC_TEST_PATTERN_CONTROL                        :DWORD;                                             // 0x41BA
  CRTC3_CRTC_TEST_PATTERN_PARAMETERS                     :DWORD;                                             // 0x41BB
  CRTC3_CRTC_TEST_PATTERN_COLOR                          :DWORD;                                             // 0x41BC
  CRTC3_MASTER_UPDATE_LOCK                               :DWORD;                                             // 0x41BD
  CRTC3_MASTER_UPDATE_MODE                               :DWORD;                                             // 0x41BE
  CRTC3_CRTC_MVP_INBAND_CNTL_INSERT                      :DWORD;                                             // 0x41BF
  CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                :DWORD;                                             // 0x41C0
  CRTC3_CRTC_MVP_STATUS                                  :DWORD;                                             // 0x41C1
  CRTC3_CRTC_MASTER_EN                                   :DWORD;                                             // 0x41C2
  CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT                        :DWORD;                                             // 0x41C3
  CRTC3_CRTC_V_UPDATE_INT_STATUS                         :DWORD;                                             // 0x41C4
  REG_41C5                                               :DWORD;                                             // 0x41C5
  CRTC3_CRTC_TEST_DEBUG_INDEX                            :DWORD;                                             // 0x41C6
  CRTC3_CRTC_TEST_DEBUG_DATA                             :DWORD;                                             // 0x41C7
  CRTC3_CRTC_OVERSCAN_COLOR                              :DWORD;                                             // 0x41C8
  CRTC3_CRTC_OVERSCAN_COLOR_EXT                          :DWORD;                                             // 0x41C9
  CRTC3_CRTC_BLANK_DATA_COLOR                            :DWORD;                                             // 0x41CA
  CRTC3_CRTC_BLANK_DATA_COLOR_EXT                        :DWORD;                                             // 0x41CB
  CRTC3_CRTC_BLACK_COLOR                                 :DWORD;                                             // 0x41CC
  CRTC3_CRTC_BLACK_COLOR_EXT                             :DWORD;                                             // 0x41CD
  CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION                :DWORD;                                             // 0x41CE
  CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL                 :DWORD;                                             // 0x41CF
  CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION                :DWORD;                                             // 0x41D0
  CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL                 :DWORD;                                             // 0x41D1
  CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION                :DWORD;                                             // 0x41D2
  CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL                 :DWORD;                                             // 0x41D3
  CRTC3_CRTC_CRC_CNTL                                    :DWORD;                                             // 0x41D4
  CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL                      :DWORD;                                             // 0x41D5
  CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL                      :DWORD;                                             // 0x41D6
  CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL                      :DWORD;                                             // 0x41D7
  CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL                      :DWORD;                                             // 0x41D8
  CRTC3_CRTC_CRC0_DATA_RG                                :DWORD;                                             // 0x41D9
  CRTC3_CRTC_CRC0_DATA_B                                 :DWORD;                                             // 0x41DA
  CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL                      :DWORD;                                             // 0x41DB
  CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL                      :DWORD;                                             // 0x41DC
  CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL                      :DWORD;                                             // 0x41DD
  CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL                      :DWORD;                                             // 0x41DE
  CRTC3_CRTC_CRC1_DATA_RG                                :DWORD;                                             // 0x41DF
  CRTC3_CRTC_CRC1_DATA_B                                 :DWORD;                                             // 0x41E0
  CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL                     :DWORD;                                             // 0x41E1
  CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START                :DWORD;                                             // 0x41E2
  CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END                  :DWORD;                                             // 0x41E3
  CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      :DWORD;                                             // 0x41E4
  CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           :DWORD;                                             // 0x41E5
  CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    :DWORD;                                             // 0x41E6
  CRTC3_CRTC_STATIC_SCREEN_CONTROL                       :DWORD;                                             // 0x41E7
  FMT3_FMT_CLAMP_COMPONENT_R                             :DWORD;                                             // 0x41E8
  FMT3_FMT_CLAMP_COMPONENT_G                             :DWORD;                                             // 0x41E9
  FMT3_FMT_CLAMP_COMPONENT_B                             :DWORD;                                             // 0x41EA
  FMT3_FMT_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x41EB
  FMT3_FMT_TEST_DEBUG_DATA                               :DWORD;                                             // 0x41EC
  FMT3_FMT_DYNAMIC_EXP_CNTL                              :DWORD;                                             // 0x41ED
  FMT3_FMT_CONTROL                                       :DWORD;                                             // 0x41EE
  FMT3_FMT_FORCE_OUTPUT_CNTL                             :DWORD;                                             // 0x41EF
  FMT3_FMT_FORCE_DATA_0_1                                :DWORD;                                             // 0x41F0
  FMT3_FMT_FORCE_DATA_2_3                                :DWORD;                                             // 0x41F1
  FMT3_FMT_BIT_DEPTH_CONTROL                             :DWORD;                                             // 0x41F2
  FMT3_FMT_DITHER_RAND_R_SEED                            :DWORD;                                             // 0x41F3
  FMT3_FMT_DITHER_RAND_G_SEED                            :DWORD;                                             // 0x41F4
  FMT3_FMT_DITHER_RAND_B_SEED                            :DWORD;                                             // 0x41F5
  FMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL               :DWORD;                                             // 0x41F6
  FMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :DWORD;                                             // 0x41F7
  FMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :DWORD;                                             // 0x41F8
  FMT3_FMT_CLAMP_CNTL                                    :DWORD;                                             // 0x41F9
  FMT3_FMT_CRC_CNTL                                      :DWORD;                                             // 0x41FA
  FMT3_FMT_CRC_SIG_RED_GREEN_MASK                        :DWORD;                                             // 0x41FB
  FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK                     :DWORD;                                             // 0x41FC
  FMT3_FMT_CRC_SIG_RED_GREEN                             :DWORD;                                             // 0x41FD
  FMT3_FMT_CRC_SIG_BLUE_CONTROL                          :DWORD;                                             // 0x41FE
  FMT3_FMT_DEBUG_CNTL                                    :DWORD;                                             // 0x41FF
  DCP4_GRPH_ENABLE                                       :DWORD;                                             // 0x4200
  DCP4_GRPH_CONTROL                                      :DWORD;                                             // 0x4201
  REG_4202_4203                                          :array[0..1] of DWORD;                              // 0x4202
  DCP4_GRPH_PRIMARY_SURFACE_ADDRESS                      :DWORD;                                             // 0x4204
  REG_4205                                               :DWORD;                                             // 0x4205
  DCP4_GRPH_PITCH                                        :DWORD;                                             // 0x4206
  DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                 :DWORD;                                             // 0x4207
  DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH               :DWORD;                                             // 0x4208
  DCP4_GRPH_SURFACE_OFFSET_X                             :DWORD;                                             // 0x4209
  DCP4_GRPH_SURFACE_OFFSET_Y                             :DWORD;                                             // 0x420A
  DCP4_GRPH_X_START                                      :DWORD;                                             // 0x420B
  REG_420C_420F                                          :array[0..3] of DWORD;                              // 0x420C
  DCP4_INPUT_GAMMA_CONTROL                               :DWORD;                                             // 0x4210
  DCP4_GRPH_UPDATE                                       :DWORD;                                             // 0x4211
  DCP4_GRPH_FLIP_CONTROL                                 :DWORD;                                             // 0x4212
  DCP4_GRPH_SURFACE_ADDRESS_INUSE                        :DWORD;                                             // 0x4213
  DCP4_GRPH_DFQ_CONTROL                                  :DWORD;                                             // 0x4214
  DCP4_GRPH_DFQ_STATUS                                   :DWORD;                                             // 0x4215
  REG_4216_421F                                          :array[0..9] of DWORD;                              // 0x4216
  DCP4_OVL_SURFACE_ADDRESS                               :DWORD;                                             // 0x4220
  REG_4221_4226                                          :array[0..5] of DWORD;                              // 0x4221
  DCP4_OVL_UPDATE                                        :DWORD;                                             // 0x4227
  DCP4_OVL_SURFACE_ADDRESS_INUSE                         :DWORD;                                             // 0x4228
  DCP4_OVL_DFQ_CONTROL                                   :DWORD;                                             // 0x4229
  DCP4_OVL_DFQ_STATUS                                    :DWORD;                                             // 0x422A
  DCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE                    :DWORD;                                             // 0x422B
  DCP4_OVLSCL_EDGE_PIXEL_CNTL                            :DWORD;                                             // 0x422C
  DCP4_PRESCALE_GRPH_CONTROL                             :DWORD;                                             // 0x422D
  DCP4_PRESCALE_VALUES_GRPH_R                            :DWORD;                                             // 0x422E
  DCP4_PRESCALE_VALUES_GRPH_G                            :DWORD;                                             // 0x422F
  DCP4_PRESCALE_VALUES_GRPH_B                            :DWORD;                                             // 0x4230
  DCP4_PRESCALE_OVL_CONTROL                              :DWORD;                                             // 0x4231
  DCP4_PRESCALE_VALUES_OVL_CB                            :DWORD;                                             // 0x4232
  DCP4_PRESCALE_VALUES_OVL_Y                             :DWORD;                                             // 0x4233
  DCP4_PRESCALE_VALUES_OVL_CR                            :DWORD;                                             // 0x4234
  DCP4_INPUT_CSC_CONTROL                                 :DWORD;                                             // 0x4235
  DCP4_INPUT_CSC_C11_C12                                 :DWORD;                                             // 0x4236
  DCP4_INPUT_CSC_C13_C14                                 :DWORD;                                             // 0x4237
  DCP4_INPUT_CSC_C21_C22                                 :DWORD;                                             // 0x4238
  DCP4_INPUT_CSC_C23_C24                                 :DWORD;                                             // 0x4239
  DCP4_INPUT_CSC_C31_C32                                 :DWORD;                                             // 0x423A
  DCP4_INPUT_CSC_C33_C34                                 :DWORD;                                             // 0x423B
  DCP4_OUTPUT_CSC_CONTROL                                :DWORD;                                             // 0x423C
  DCP4_OUTPUT_CSC_C11_C12                                :DWORD;                                             // 0x423D
  DCP4_OUTPUT_CSC_C13_C14                                :DWORD;                                             // 0x423E
  DCP4_OUTPUT_CSC_C21_C22                                :DWORD;                                             // 0x423F
  DCP4_OUTPUT_CSC_C23_C24                                :DWORD;                                             // 0x4240
  DCP4_OUTPUT_CSC_C31_C32                                :DWORD;                                             // 0x4241
  DCP4_OUTPUT_CSC_C33_C34                                :DWORD;                                             // 0x4242
  DCP4_COMM_MATRIXA_TRANS_C11_C12                        :DWORD;                                             // 0x4243
  DCP4_COMM_MATRIXA_TRANS_C13_C14                        :DWORD;                                             // 0x4244
  DCP4_COMM_MATRIXA_TRANS_C21_C22                        :DWORD;                                             // 0x4245
  DCP4_COMM_MATRIXA_TRANS_C23_C24                        :DWORD;                                             // 0x4246
  DCP4_COMM_MATRIXA_TRANS_C31_C32                        :DWORD;                                             // 0x4247
  DCP4_COMM_MATRIXA_TRANS_C33_C34                        :DWORD;                                             // 0x4248
  DCP4_COMM_MATRIXB_TRANS_C11_C12                        :DWORD;                                             // 0x4249
  DCP4_COMM_MATRIXB_TRANS_C13_C14                        :DWORD;                                             // 0x424A
  DCP4_COMM_MATRIXB_TRANS_C21_C22                        :DWORD;                                             // 0x424B
  DCP4_COMM_MATRIXB_TRANS_C23_C24                        :DWORD;                                             // 0x424C
  DCP4_COMM_MATRIXB_TRANS_C31_C32                        :DWORD;                                             // 0x424D
  DCP4_COMM_MATRIXB_TRANS_C33_C34                        :DWORD;                                             // 0x424E
  REG_424F                                               :DWORD;                                             // 0x424F
  DCP4_DENORM_CONTROL                                    :DWORD;                                             // 0x4250
  DCP4_OUT_ROUND_CONTROL                                 :DWORD;                                             // 0x4251
  DCP4_OUT_CLAMP_CONTROL_R_CR                            :DWORD;                                             // 0x4252
  DCP4_KEY_CONTROL                                       :DWORD;                                             // 0x4253
  DCP4_KEY_RANGE_ALPHA                                   :DWORD;                                             // 0x4254
  DCP4_KEY_RANGE_RED                                     :DWORD;                                             // 0x4255
  DCP4_KEY_RANGE_GREEN                                   :DWORD;                                             // 0x4256
  DCP4_KEY_RANGE_BLUE                                    :DWORD;                                             // 0x4257
  DCP4_DEGAMMA_CONTROL                                   :DWORD;                                             // 0x4258
  DCP4_GAMUT_REMAP_CONTROL                               :DWORD;                                             // 0x4259
  DCP4_GAMUT_REMAP_C11_C12                               :DWORD;                                             // 0x425A
  DCP4_GAMUT_REMAP_C13_C14                               :DWORD;                                             // 0x425B
  DCP4_GAMUT_REMAP_C21_C22                               :DWORD;                                             // 0x425C
  DCP4_GAMUT_REMAP_C23_C24                               :DWORD;                                             // 0x425D
  DCP4_GAMUT_REMAP_C31_C32                               :DWORD;                                             // 0x425E
  DCP4_GAMUT_REMAP_C33_C34                               :DWORD;                                             // 0x425F
  DCP4_DCP_SPATIAL_DITHER_CNTL                           :DWORD;                                             // 0x4260
  DCP4_DCP_RANDOM_SEEDS                                  :DWORD;                                             // 0x4261
  REG_4262_4264                                          :array[0..2] of DWORD;                              // 0x4262
  DCP4_DCP_FP_CONVERTED_FIELD                            :DWORD;                                             // 0x4265
  DCP4_CUR_CONTROL                                       :DWORD;                                             // 0x4266
  DCP4_CUR_SURFACE_ADDRESS                               :DWORD;                                             // 0x4267
  DCP4_CUR_SIZE                                          :DWORD;                                             // 0x4268
  DCP4_CUR_SURFACE_ADDRESS_HIGH                          :DWORD;                                             // 0x4269
  DCP4_CUR_POSITION                                      :DWORD;                                             // 0x426A
  DCP4_CUR_HOT_SPOT                                      :DWORD;                                             // 0x426B
  DCP4_CUR_COLOR1                                        :DWORD;                                             // 0x426C
  DCP4_CUR_COLOR2                                        :DWORD;                                             // 0x426D
  DCP4_CUR_UPDATE                                        :DWORD;                                             // 0x426E
  DCP4_CUR2_CONTROL                                      :DWORD;                                             // 0x426F
  DCP4_CUR2_SURFACE_ADDRESS                              :DWORD;                                             // 0x4270
  DCP4_CUR2_SIZE                                         :DWORD;                                             // 0x4271
  DCP4_CUR2_SURFACE_ADDRESS_HIGH                         :DWORD;                                             // 0x4272
  DCP4_CUR2_POSITION                                     :DWORD;                                             // 0x4273
  DCP4_CUR2_HOT_SPOT                                     :DWORD;                                             // 0x4274
  DCP4_CUR2_COLOR1                                       :DWORD;                                             // 0x4275
  DCP4_CUR2_COLOR2                                       :DWORD;                                             // 0x4276
  DCP4_CUR2_UPDATE                                       :DWORD;                                             // 0x4277
  DCP4_DC_LUT_RW_MODE                                    :DWORD;                                             // 0x4278
  DCP4_DC_LUT_RW_INDEX                                   :DWORD;                                             // 0x4279
  DCP4_DC_LUT_SEQ_COLOR                                  :DWORD;                                             // 0x427A
  DCP4_DC_LUT_PWL_DATA                                   :DWORD;                                             // 0x427B
  REG_427C                                               :DWORD;                                             // 0x427C
  DCP4_DC_LUT_VGA_ACCESS_ENABLE                          :DWORD;                                             // 0x427D
  REG_427E_4284                                          :array[0..6] of DWORD;                              // 0x427E
  DCP4_DC_LUT_WHITE_OFFSET_GREEN                         :DWORD;                                             // 0x4285
  REG_4286_4287                                          :array[0..1] of DWORD;                              // 0x4286
  DCP4_DCP_CRC_MASK                                      :DWORD;                                             // 0x4288
  DCP4_DCP_CRC_CURRENT                                   :DWORD;                                             // 0x4289
  REG_428A                                               :DWORD;                                             // 0x428A
  DCP4_DCP_CRC_LAST                                      :DWORD;                                             // 0x428B
  REG_428C                                               :DWORD;                                             // 0x428C
  DCP4_DCP_DEBUG                                         :DWORD;                                             // 0x428D
  DCP4_GRPH_FLIP_RATE_CNTL                               :DWORD;                                             // 0x428E
  REG_428F                                               :DWORD;                                             // 0x428F
  DCP4_DCP_GSL_CONTROL                                   :DWORD;                                             // 0x4290
  DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK                     :DWORD;                                             // 0x4291
  DCP4_OVL_SECONDARY_SURFACE_ADDRESS                     :DWORD;                                             // 0x4292
  DCP4_OVL_STEREOSYNC_FLIP                               :DWORD;                                             // 0x4293
  DCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                :DWORD;                                             // 0x4294
  DCP4_DCP_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x4295
  DCP4_DCP_TEST_DEBUG_DATA                               :DWORD;                                             // 0x4296
  DCP4_GRPH_STEREOSYNC_FLIP                              :DWORD;                                             // 0x4297
  DCP4_DCP_DEBUG2                                        :DWORD;                                             // 0x4298
  DCP4_CUR_REQUEST_FILTER_CNTL                           :DWORD;                                             // 0x4299
  DCP4_CUR_STEREO_CONTROL                                :DWORD;                                             // 0x429A
  DCP4_CUR2_STEREO_CONTROL                               :DWORD;                                             // 0x429B
  DCP4_OUT_CLAMP_CONTROL_G_Y                             :DWORD;                                             // 0x429C
  DCP4_OUT_CLAMP_CONTROL_B_CB                            :DWORD;                                             // 0x429D
  DCP4_HW_ROTATION                                       :DWORD;                                             // 0x429E
  DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                :DWORD;                                             // 0x429F
  DCP4_REGAMMA_CONTROL                                   :DWORD;                                             // 0x42A0
  DCP4_REGAMMA_LUT_INDEX                                 :DWORD;                                             // 0x42A1
  DCP4_REGAMMA_LUT_DATA                                  :DWORD;                                             // 0x42A2
  DCP4_REGAMMA_LUT_WRITE_EN_MASK                         :DWORD;                                             // 0x42A3
  DCP4_REGAMMA_CNTLA_START_CNTL                          :DWORD;                                             // 0x42A4
  DCP4_REGAMMA_CNTLA_SLOPE_CNTL                          :DWORD;                                             // 0x42A5
  DCP4_REGAMMA_CNTLA_END_CNTL1                           :DWORD;                                             // 0x42A6
  DCP4_REGAMMA_CNTLA_END_CNTL2                           :DWORD;                                             // 0x42A7
  DCP4_REGAMMA_CNTLA_REGION_0_1                          :DWORD;                                             // 0x42A8
  DCP4_REGAMMA_CNTLA_REGION_2_3                          :DWORD;                                             // 0x42A9
  DCP4_REGAMMA_CNTLA_REGION_4_5                          :DWORD;                                             // 0x42AA
  DCP4_REGAMMA_CNTLA_REGION_6_7                          :DWORD;                                             // 0x42AB
  DCP4_REGAMMA_CNTLA_REGION_8_9                          :DWORD;                                             // 0x42AC
  DCP4_REGAMMA_CNTLA_REGION_10_11                        :DWORD;                                             // 0x42AD
  DCP4_REGAMMA_CNTLA_REGION_12_13                        :DWORD;                                             // 0x42AE
  DCP4_REGAMMA_CNTLA_REGION_14_15                        :DWORD;                                             // 0x42AF
  DCP4_REGAMMA_CNTLB_START_CNTL                          :DWORD;                                             // 0x42B0
  DCP4_REGAMMA_CNTLB_SLOPE_CNTL                          :DWORD;                                             // 0x42B1
  DCP4_REGAMMA_CNTLB_END_CNTL1                           :DWORD;                                             // 0x42B2
  DCP4_REGAMMA_CNTLB_END_CNTL2                           :DWORD;                                             // 0x42B3
  DCP4_REGAMMA_CNTLB_REGION_0_1                          :DWORD;                                             // 0x42B4
  DCP4_REGAMMA_CNTLB_REGION_2_3                          :DWORD;                                             // 0x42B5
  DCP4_REGAMMA_CNTLB_REGION_4_5                          :DWORD;                                             // 0x42B6
  DCP4_REGAMMA_CNTLB_REGION_6_7                          :DWORD;                                             // 0x42B7
  DCP4_REGAMMA_CNTLB_REGION_8_9                          :DWORD;                                             // 0x42B8
  DCP4_REGAMMA_CNTLB_REGION_10_11                        :DWORD;                                             // 0x42B9
  DCP4_REGAMMA_CNTLB_REGION_12_13                        :DWORD;                                             // 0x42BA
  DCP4_REGAMMA_CNTLB_REGION_14_15                        :DWORD;                                             // 0x42BB
  DCP4_ALPHA_CONTROL                                     :DWORD;                                             // 0x42BC
  DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                :DWORD;                                             // 0x42BD
  DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH           :DWORD;                                             // 0x42BE
  DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS              :DWORD;                                             // 0x42BF
  LB4_LB_DATA_FORMAT                                     :DWORD;                                             // 0x42C0
  LB4_LB_MEMORY_CTRL                                     :DWORD;                                             // 0x42C1
  LB4_LB_MEMORY_SIZE_STATUS                              :DWORD;                                             // 0x42C2
  LB4_LB_DESKTOP_HEIGHT                                  :DWORD;                                             // 0x42C3
  LB4_LB_VLINE_START_END                                 :DWORD;                                             // 0x42C4
  LB4_LB_VLINE2_START_END                                :DWORD;                                             // 0x42C5
  LB4_LB_V_COUNTER                                       :DWORD;                                             // 0x42C6
  LB4_LB_SNAPSHOT_V_COUNTER                              :DWORD;                                             // 0x42C7
  LB4_LB_INTERRUPT_MASK                                  :DWORD;                                             // 0x42C8
  LB4_LB_VLINE_STATUS                                    :DWORD;                                             // 0x42C9
  LB4_LB_VLINE2_STATUS                                   :DWORD;                                             // 0x42CA
  LB4_LB_VBLANK_STATUS                                   :DWORD;                                             // 0x42CB
  LB4_LB_SYNC_RESET_SEL                                  :DWORD;                                             // 0x42CC
  LB4_LB_BLACK_KEYER_R_CR                                :DWORD;                                             // 0x42CD
  LB4_LB_BLACK_KEYER_G_Y                                 :DWORD;                                             // 0x42CE
  LB4_LB_BLACK_KEYER_B_CB                                :DWORD;                                             // 0x42CF
  LB4_LB_KEYER_COLOR_CTRL                                :DWORD;                                             // 0x42D0
  LB4_LB_KEYER_COLOR_R_CR                                :DWORD;                                             // 0x42D1
  LB4_LB_KEYER_COLOR_G_Y                                 :DWORD;                                             // 0x42D2
  LB4_LB_KEYER_COLOR_B_CB                                :DWORD;                                             // 0x42D3
  LB4_LB_KEYER_COLOR_REP_R_CR                            :DWORD;                                             // 0x42D4
  LB4_LB_KEYER_COLOR_REP_G_Y                             :DWORD;                                             // 0x42D5
  LB4_LB_KEYER_COLOR_REP_B_CB                            :DWORD;                                             // 0x42D6
  LB4_LB_BUFFER_LEVEL_STATUS                             :DWORD;                                             // 0x42D7
  LB4_LB_BUFFER_URGENCY_CTRL                             :DWORD;                                             // 0x42D8
  LB4_LB_BUFFER_URGENCY_STATUS                           :DWORD;                                             // 0x42D9
  LB4_LB_BUFFER_STATUS                                   :DWORD;                                             // 0x42DA
  REG_42DB                                               :DWORD;                                             // 0x42DB
  LB4_LB_NO_OUTSTANDING_REQ_STATUS                       :DWORD;                                             // 0x42DC
  REG_42DD_42DF                                          :array[0..2] of DWORD;                              // 0x42DD
  LB4_MVP_AFR_FLIP_MODE                                  :DWORD;                                             // 0x42E0
  LB4_MVP_AFR_FLIP_FIFO_CNTL                             :DWORD;                                             // 0x42E1
  LB4_MVP_FLIP_LINE_NUM_INSERT                           :DWORD;                                             // 0x42E2
  LB4_DC_MVP_LB_CONTROL                                  :DWORD;                                             // 0x42E3
  LB4_LB_DEBUG                                           :DWORD;                                             // 0x42E4
  LB4_LB_DEBUG2                                          :DWORD;                                             // 0x42E5
  LB4_LB_DEBUG3                                          :DWORD;                                             // 0x42E6
  REG_42E7_42FD                                          :array[0..22] of DWORD;                             // 0x42E7
  LB4_LB_TEST_DEBUG_INDEX                                :DWORD;                                             // 0x42FE
  LB4_LB_TEST_DEBUG_DATA                                 :DWORD;                                             // 0x42FF
  DCFE4_DCFE_CLOCK_CONTROL                               :DWORD;                                             // 0x4300
  DCFE4_DCFE_SOFT_RESET                                  :DWORD;                                             // 0x4301
  DCFE4_DCFE_DBG_CONFIG                                  :DWORD;                                             // 0x4302
  REG_4303_4323                                          :array[0..32] of DWORD;                             // 0x4303
  DC_PERFMON7_PERFCOUNTER_CNTL                           :DWORD;                                             // 0x4324
  DC_PERFMON7_PERFCOUNTER_STATE                          :DWORD;                                             // 0x4325
  DC_PERFMON7_PERFMON_CVALUE_INT_MISC                    :DWORD;                                             // 0x4326
  DC_PERFMON7_PERFMON_CNTL                               :DWORD;                                             // 0x4327
  DC_PERFMON7_PERFMON_CVALUE_LOW                         :DWORD;                                             // 0x4328
  DC_PERFMON7_PERFMON_HI                                 :DWORD;                                             // 0x4329
  DC_PERFMON7_PERFMON_LOW                                :DWORD;                                             // 0x432A
  DC_PERFMON7_PERFMON_TEST_DEBUG_INDEX                   :DWORD;                                             // 0x432B
  DC_PERFMON7_PERFMON_TEST_DEBUG_DATA                    :DWORD;                                             // 0x432C
  REG_432D                                               :DWORD;                                             // 0x432D
  DC_PERFMON7_PERFMON_CNTL2                              :DWORD;                                             // 0x432E
  REG_432F                                               :DWORD;                                             // 0x432F
  DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1                 :DWORD;                                             // 0x4330
  DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2                 :DWORD;                                             // 0x4331
  DMIF_PG4_DPG_WATERMARK_MASK_CONTROL                    :DWORD;                                             // 0x4332
  DMIF_PG4_DPG_PIPE_URGENCY_CONTROL                      :DWORD;                                             // 0x4333
  DMIF_PG4_DPG_PIPE_DPM_CONTROL                          :DWORD;                                             // 0x4334
  DMIF_PG4_DPG_PIPE_STUTTER_CONTROL                      :DWORD;                                             // 0x4335
  DMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             :DWORD;                                             // 0x4336
  DMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             :DWORD;                                             // 0x4337
  DMIF_PG4_DPG_TEST_DEBUG_INDEX                          :DWORD;                                             // 0x4338
  DMIF_PG4_DPG_TEST_DEBUG_DATA                           :DWORD;                                             // 0x4339
  DMIF_PG4_DPG_REPEATER_PROGRAM                          :DWORD;                                             // 0x433A
  DMIF_PG4_DPG_HW_DEBUG_A                                :DWORD;                                             // 0x433B
  DMIF_PG4_DPG_HW_DEBUG_B                                :DWORD;                                             // 0x433C
  DMIF_PG4_DPG_HW_DEBUG_11                               :DWORD;                                             // 0x433D
  REG_433E_433F                                          :array[0..1] of DWORD;                              // 0x433E
  SCL4_SCL_COEF_RAM_SELECT                               :DWORD;                                             // 0x4340
  SCL4_SCL_COEF_RAM_TAP_DATA                             :DWORD;                                             // 0x4341
  SCL4_SCL_MODE                                          :DWORD;                                             // 0x4342
  SCL4_SCL_TAP_CONTROL                                   :DWORD;                                             // 0x4343
  SCL4_SCL_CONTROL                                       :DWORD;                                             // 0x4344
  SCL4_SCL_BYPASS_CONTROL                                :DWORD;                                             // 0x4345
  SCL4_SCL_MANUAL_REPLICATE_CONTROL                      :DWORD;                                             // 0x4346
  SCL4_SCL_AUTOMATIC_MODE_CONTROL                        :DWORD;                                             // 0x4347
  SCL4_SCL_HORZ_FILTER_CONTROL                           :DWORD;                                             // 0x4348
  SCL4_SCL_HORZ_FILTER_SCALE_RATIO                       :DWORD;                                             // 0x4349
  SCL4_SCL_HORZ_FILTER_INIT                              :DWORD;                                             // 0x434A
  SCL4_SCL_VERT_FILTER_CONTROL                           :DWORD;                                             // 0x434B
  SCL4_SCL_VERT_FILTER_SCALE_RATIO                       :DWORD;                                             // 0x434C
  SCL4_SCL_VERT_FILTER_INIT                              :DWORD;                                             // 0x434D
  SCL4_SCL_VERT_FILTER_INIT_BOT                          :DWORD;                                             // 0x434E
  SCL4_SCL_ROUND_OFFSET                                  :DWORD;                                             // 0x434F
  REG_4350                                               :DWORD;                                             // 0x4350
  SCL4_SCL_UPDATE                                        :DWORD;                                             // 0x4351
  REG_4352                                               :DWORD;                                             // 0x4352
  SCL4_SCL_F_SHARP_CONTROL                               :DWORD;                                             // 0x4353
  SCL4_SCL_ALU_CONTROL                                   :DWORD;                                             // 0x4354
  SCL4_SCL_COEF_RAM_CONFLICT_STATUS                      :DWORD;                                             // 0x4355
  REG_4356_435A                                          :array[0..4] of DWORD;                              // 0x4356
  SCL4_VIEWPORT_START_SECONDARY                          :DWORD;                                             // 0x435B
  SCL4_VIEWPORT_START                                    :DWORD;                                             // 0x435C
  SCL4_VIEWPORT_SIZE                                     :DWORD;                                             // 0x435D
  SCL4_EXT_OVERSCAN_LEFT_RIGHT                           :DWORD;                                             // 0x435E
  SCL4_EXT_OVERSCAN_TOP_BOTTOM                           :DWORD;                                             // 0x435F
  SCL4_SCL_MODE_CHANGE_DET1                              :DWORD;                                             // 0x4360
  SCL4_SCL_MODE_CHANGE_DET2                              :DWORD;                                             // 0x4361
  SCL4_SCL_MODE_CHANGE_DET3                              :DWORD;                                             // 0x4362
  SCL4_SCL_MODE_CHANGE_MASK                              :DWORD;                                             // 0x4363
  REG_4364_4368                                          :array[0..4] of DWORD;                              // 0x4364
  SCL4_SCL_DEBUG2                                        :DWORD;                                             // 0x4369
  SCL4_SCL_DEBUG                                         :DWORD;                                             // 0x436A
  SCL4_SCL_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x436B
  SCL4_SCL_TEST_DEBUG_DATA                               :DWORD;                                             // 0x436C
  BLND4_BLND_CONTROL                                     :DWORD;                                             // 0x436D
  BLND4_SM_CONTROL2                                      :DWORD;                                             // 0x436E
  BLND4_BLND_CONTROL2                                    :DWORD;                                             // 0x436F
  BLND4_BLND_UPDATE                                      :DWORD;                                             // 0x4370
  BLND4_BLND_UNDERFLOW_INTERRUPT                         :DWORD;                                             // 0x4371
  REG_4372                                               :DWORD;                                             // 0x4372
  BLND4_BLND_V_UPDATE_LOCK                               :DWORD;                                             // 0x4373
  BLND4_BLND_DEBUG                                       :DWORD;                                             // 0x4374
  BLND4_BLND_TEST_DEBUG_INDEX                            :DWORD;                                             // 0x4375
  BLND4_BLND_TEST_DEBUG_DATA                             :DWORD;                                             // 0x4376
  BLND4_BLND_REG_UPDATE_STATUS                           :DWORD;                                             // 0x4377
  CRTC4_CRTC_3D_STRUCTURE_CONTROL                        :DWORD;                                             // 0x4378
  CRTC4_CRTC_GSL_VSYNC_GAP                               :DWORD;                                             // 0x4379
  CRTC4_CRTC_GSL_WINDOW                                  :DWORD;                                             // 0x437A
  CRTC4_CRTC_GSL_CONTROL                                 :DWORD;                                             // 0x437B
  CRTC4_CRTC_DCFE_CLOCK_CONTROL                          :DWORD;                                             // 0x437C
  CRTC4_CRTC_H_BLANK_EARLY_NUM                           :DWORD;                                             // 0x437D
  CRTC4_DCFE_DBG_SEL                                     :DWORD;                                             // 0x437E
  CRTC4_DCFE_MEM_PWR_CTRL                                :DWORD;                                             // 0x437F
  REG_4380_4389                                          :array[0..9] of DWORD;                              // 0x4380
  CRTC4_CRTC_V_TOTAL_CONTROL                             :DWORD;                                             // 0x438A
  REG_438B                                               :DWORD;                                             // 0x438B
  CRTC4_CRTC_VSYNC_NOM_INT_STATUS                        :DWORD;                                             // 0x438C
  REG_438D                                               :DWORD;                                             // 0x438D
  CRTC4_CRTC_V_SYNC_A                                    :DWORD;                                             // 0x438E
  CRTC4_CRTC_V_SYNC_A_CNTL                               :DWORD;                                             // 0x438F
  CRTC4_CRTC_V_SYNC_B                                    :DWORD;                                             // 0x4390
  REG_4391                                               :DWORD;                                             // 0x4391
  CRTC4_CRTC_DTMTEST_CNTL                                :DWORD;                                             // 0x4392
  CRTC4_CRTC_DTMTEST_STATUS_POSITION                     :DWORD;                                             // 0x4393
  CRTC4_CRTC_TRIGA_CNTL                                  :DWORD;                                             // 0x4394
  REG_4395_4396                                          :array[0..1] of DWORD;                              // 0x4395
  CRTC4_CRTC_TRIGB_MANUAL_TRIG                           :DWORD;                                             // 0x4397
  CRTC4_CRTC_FORCE_COUNT_NOW_CNTL                        :DWORD;                                             // 0x4398
  CRTC4_CRTC_FLOW_CONTROL                                :DWORD;                                             // 0x4399
  CRTC4_CRTC_STEREO_FORCE_NEXT_EYE                       :DWORD;                                             // 0x439A
  CRTC4_CRTC_AVSYNC_COUNTER                              :DWORD;                                             // 0x439B
  CRTC4_CRTC_CONTROL                                     :DWORD;                                             // 0x439C
  CRTC4_CRTC_BLANK_CONTROL                               :DWORD;                                             // 0x439D
  CRTC4_CRTC_INTERLACE_CONTROL                           :DWORD;                                             // 0x439E
  CRTC4_CRTC_INTERLACE_STATUS                            :DWORD;                                             // 0x439F
  CRTC4_CRTC_FIELD_INDICATION_CONTROL                    :DWORD;                                             // 0x43A0
  CRTC4_CRTC_PIXEL_DATA_READBACK0                        :DWORD;                                             // 0x43A1
  CRTC4_CRTC_PIXEL_DATA_READBACK1                        :DWORD;                                             // 0x43A2
  CRTC4_CRTC_STATUS                                      :DWORD;                                             // 0x43A3
  CRTC4_CRTC_STATUS_POSITION                             :DWORD;                                             // 0x43A4
  CRTC4_CRTC_NOM_VERT_POSITION                           :DWORD;                                             // 0x43A5
  CRTC4_CRTC_STATUS_FRAME_COUNT                          :DWORD;                                             // 0x43A6
  CRTC4_CRTC_STATUS_VF_COUNT                             :DWORD;                                             // 0x43A7
  CRTC4_CRTC_STATUS_HV_COUNT                             :DWORD;                                             // 0x43A8
  CRTC4_CRTC_COUNT_CONTROL                               :DWORD;                                             // 0x43A9
  CRTC4_CRTC_COUNT_RESET                                 :DWORD;                                             // 0x43AA
  CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                :DWORD;                                             // 0x43AB
  CRTC4_CRTC_VERT_SYNC_CONTROL                           :DWORD;                                             // 0x43AC
  CRTC4_CRTC_STEREO_STATUS                               :DWORD;                                             // 0x43AD
  CRTC4_CRTC_STEREO_CONTROL                              :DWORD;                                             // 0x43AE
  CRTC4_CRTC_SNAPSHOT_STATUS                             :DWORD;                                             // 0x43AF
  CRTC4_CRTC_SNAPSHOT_CONTROL                            :DWORD;                                             // 0x43B0
  CRTC4_CRTC_SNAPSHOT_POSITION                           :DWORD;                                             // 0x43B1
  CRTC4_CRTC_SNAPSHOT_FRAME                              :DWORD;                                             // 0x43B2
  CRTC4_CRTC_START_LINE_CONTROL                          :DWORD;                                             // 0x43B3
  CRTC4_CRTC_INTERRUPT_CONTROL                           :DWORD;                                             // 0x43B4
  CRTC4_CRTC_UPDATE_LOCK                                 :DWORD;                                             // 0x43B5
  CRTC4_CRTC_DOUBLE_BUFFER_CONTROL                       :DWORD;                                             // 0x43B6
  CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE                  :DWORD;                                             // 0x43B7
  CRTC4_DCFE_MEM_PWR_CTRL2                               :DWORD;                                             // 0x43B8
  CRTC4_DCFE_MEM_PWR_STATUS                              :DWORD;                                             // 0x43B9
  CRTC4_CRTC_TEST_PATTERN_CONTROL                        :DWORD;                                             // 0x43BA
  CRTC4_CRTC_TEST_PATTERN_PARAMETERS                     :DWORD;                                             // 0x43BB
  CRTC4_CRTC_TEST_PATTERN_COLOR                          :DWORD;                                             // 0x43BC
  CRTC4_MASTER_UPDATE_LOCK                               :DWORD;                                             // 0x43BD
  CRTC4_MASTER_UPDATE_MODE                               :DWORD;                                             // 0x43BE
  CRTC4_CRTC_MVP_INBAND_CNTL_INSERT                      :DWORD;                                             // 0x43BF
  CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                :DWORD;                                             // 0x43C0
  CRTC4_CRTC_MVP_STATUS                                  :DWORD;                                             // 0x43C1
  CRTC4_CRTC_MASTER_EN                                   :DWORD;                                             // 0x43C2
  CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT                        :DWORD;                                             // 0x43C3
  CRTC4_CRTC_V_UPDATE_INT_STATUS                         :DWORD;                                             // 0x43C4
  REG_43C5                                               :DWORD;                                             // 0x43C5
  CRTC4_CRTC_TEST_DEBUG_INDEX                            :DWORD;                                             // 0x43C6
  CRTC4_CRTC_TEST_DEBUG_DATA                             :DWORD;                                             // 0x43C7
  CRTC4_CRTC_OVERSCAN_COLOR                              :DWORD;                                             // 0x43C8
  CRTC4_CRTC_OVERSCAN_COLOR_EXT                          :DWORD;                                             // 0x43C9
  REG_43CA                                               :DWORD;                                             // 0x43CA
  CRTC4_CRTC_BLANK_DATA_COLOR_EXT                        :DWORD;                                             // 0x43CB
  CRTC4_CRTC_BLACK_COLOR                                 :DWORD;                                             // 0x43CC
  CRTC4_CRTC_BLACK_COLOR_EXT                             :DWORD;                                             // 0x43CD
  CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION                :DWORD;                                             // 0x43CE
  CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL                 :DWORD;                                             // 0x43CF
  CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION                :DWORD;                                             // 0x43D0
  CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL                 :DWORD;                                             // 0x43D1
  CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION                :DWORD;                                             // 0x43D2
  CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL                 :DWORD;                                             // 0x43D3
  CRTC4_CRTC_CRC_CNTL                                    :DWORD;                                             // 0x43D4
  CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL                      :DWORD;                                             // 0x43D5
  CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL                      :DWORD;                                             // 0x43D6
  CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL                      :DWORD;                                             // 0x43D7
  CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL                      :DWORD;                                             // 0x43D8
  CRTC4_CRTC_CRC0_DATA_RG                                :DWORD;                                             // 0x43D9
  CRTC4_CRTC_CRC0_DATA_B                                 :DWORD;                                             // 0x43DA
  CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL                      :DWORD;                                             // 0x43DB
  CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL                      :DWORD;                                             // 0x43DC
  CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL                      :DWORD;                                             // 0x43DD
  CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL                      :DWORD;                                             // 0x43DE
  CRTC4_CRTC_CRC1_DATA_RG                                :DWORD;                                             // 0x43DF
  CRTC4_CRTC_CRC1_DATA_B                                 :DWORD;                                             // 0x43E0
  CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL                     :DWORD;                                             // 0x43E1
  CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START                :DWORD;                                             // 0x43E2
  CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END                  :DWORD;                                             // 0x43E3
  CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      :DWORD;                                             // 0x43E4
  CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           :DWORD;                                             // 0x43E5
  CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    :DWORD;                                             // 0x43E6
  CRTC4_CRTC_STATIC_SCREEN_CONTROL                       :DWORD;                                             // 0x43E7
  FMT4_FMT_CLAMP_COMPONENT_R                             :DWORD;                                             // 0x43E8
  FMT4_FMT_CLAMP_COMPONENT_G                             :DWORD;                                             // 0x43E9
  FMT4_FMT_CLAMP_COMPONENT_B                             :DWORD;                                             // 0x43EA
  FMT4_FMT_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x43EB
  FMT4_FMT_TEST_DEBUG_DATA                               :DWORD;                                             // 0x43EC
  FMT4_FMT_DYNAMIC_EXP_CNTL                              :DWORD;                                             // 0x43ED
  FMT4_FMT_CONTROL                                       :DWORD;                                             // 0x43EE
  FMT4_FMT_FORCE_OUTPUT_CNTL                             :DWORD;                                             // 0x43EF
  FMT4_FMT_FORCE_DATA_0_1                                :DWORD;                                             // 0x43F0
  FMT4_FMT_FORCE_DATA_2_3                                :DWORD;                                             // 0x43F1
  FMT4_FMT_BIT_DEPTH_CONTROL                             :DWORD;                                             // 0x43F2
  FMT4_FMT_DITHER_RAND_R_SEED                            :DWORD;                                             // 0x43F3
  FMT4_FMT_DITHER_RAND_G_SEED                            :DWORD;                                             // 0x43F4
  FMT4_FMT_DITHER_RAND_B_SEED                            :DWORD;                                             // 0x43F5
  FMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL               :DWORD;                                             // 0x43F6
  FMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :DWORD;                                             // 0x43F7
  FMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :DWORD;                                             // 0x43F8
  FMT4_FMT_CLAMP_CNTL                                    :DWORD;                                             // 0x43F9
  FMT4_FMT_CRC_CNTL                                      :DWORD;                                             // 0x43FA
  FMT4_FMT_CRC_SIG_RED_GREEN_MASK                        :DWORD;                                             // 0x43FB
  REG_43FC                                               :DWORD;                                             // 0x43FC
  FMT4_FMT_CRC_SIG_RED_GREEN                             :DWORD;                                             // 0x43FD
  REG_43FE_43FF                                          :array[0..1] of DWORD;                              // 0x43FE
  DCP5_GRPH_ENABLE                                       :DWORD;                                             // 0x4400
  DCP5_GRPH_CONTROL                                      :DWORD;                                             // 0x4401
  DCP5_GRPH_LUT_10BIT_BYPASS                             :DWORD;                                             // 0x4402
  DCP5_GRPH_SWAP_CNTL                                    :DWORD;                                             // 0x4403
  DCP5_GRPH_PRIMARY_SURFACE_ADDRESS                      :DWORD;                                             // 0x4404
  DCP5_GRPH_SECONDARY_SURFACE_ADDRESS                    :DWORD;                                             // 0x4405
  DCP5_GRPH_PITCH                                        :DWORD;                                             // 0x4406
  DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                 :DWORD;                                             // 0x4407
  DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH               :DWORD;                                             // 0x4408
  DCP5_GRPH_SURFACE_OFFSET_X                             :DWORD;                                             // 0x4409
  DCP5_GRPH_SURFACE_OFFSET_Y                             :DWORD;                                             // 0x440A
  DCP5_GRPH_X_START                                      :DWORD;                                             // 0x440B
  DCP5_GRPH_Y_START                                      :DWORD;                                             // 0x440C
  DCP5_GRPH_X_END                                        :DWORD;                                             // 0x440D
  DCP5_GRPH_Y_END                                        :DWORD;                                             // 0x440E
  REG_440F                                               :DWORD;                                             // 0x440F
  DCP5_INPUT_GAMMA_CONTROL                               :DWORD;                                             // 0x4410
  DCP5_GRPH_UPDATE                                       :DWORD;                                             // 0x4411
  DCP5_GRPH_FLIP_CONTROL                                 :DWORD;                                             // 0x4412
  DCP5_GRPH_SURFACE_ADDRESS_INUSE                        :DWORD;                                             // 0x4413
  DCP5_GRPH_DFQ_CONTROL                                  :DWORD;                                             // 0x4414
  DCP5_GRPH_DFQ_STATUS                                   :DWORD;                                             // 0x4415
  DCP5_GRPH_INTERRUPT_STATUS                             :DWORD;                                             // 0x4416
  DCP5_GRPH_INTERRUPT_CONTROL                            :DWORD;                                             // 0x4417
  DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE                   :DWORD;                                             // 0x4418
  DCP5_GRPH_COMPRESS_SURFACE_ADDRESS                     :DWORD;                                             // 0x4419
  DCP5_GRPH_COMPRESS_PITCH                               :DWORD;                                             // 0x441A
  DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                :DWORD;                                             // 0x441B
  DCP5_OVL_ENABLE                                        :DWORD;                                             // 0x441C
  DCP5_OVL_CONTROL1                                      :DWORD;                                             // 0x441D
  DCP5_OVL_CONTROL2                                      :DWORD;                                             // 0x441E
  DCP5_OVL_SWAP_CNTL                                     :DWORD;                                             // 0x441F
  DCP5_OVL_SURFACE_ADDRESS                               :DWORD;                                             // 0x4420
  DCP5_OVL_PITCH                                         :DWORD;                                             // 0x4421
  DCP5_OVL_SURFACE_ADDRESS_HIGH                          :DWORD;                                             // 0x4422
  DCP5_OVL_SURFACE_OFFSET_X                              :DWORD;                                             // 0x4423
  DCP5_OVL_SURFACE_OFFSET_Y                              :DWORD;                                             // 0x4424
  DCP5_OVL_START                                         :DWORD;                                             // 0x4425
  DCP5_OVL_END                                           :DWORD;                                             // 0x4426
  DCP5_OVL_UPDATE                                        :DWORD;                                             // 0x4427
  DCP5_OVL_SURFACE_ADDRESS_INUSE                         :DWORD;                                             // 0x4428
  DCP5_OVL_DFQ_CONTROL                                   :DWORD;                                             // 0x4429
  DCP5_OVL_DFQ_STATUS                                    :DWORD;                                             // 0x442A
  DCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE                    :DWORD;                                             // 0x442B
  DCP5_OVLSCL_EDGE_PIXEL_CNTL                            :DWORD;                                             // 0x442C
  DCP5_PRESCALE_GRPH_CONTROL                             :DWORD;                                             // 0x442D
  DCP5_PRESCALE_VALUES_GRPH_R                            :DWORD;                                             // 0x442E
  DCP5_PRESCALE_VALUES_GRPH_G                            :DWORD;                                             // 0x442F
  DCP5_PRESCALE_VALUES_GRPH_B                            :DWORD;                                             // 0x4430
  DCP5_PRESCALE_OVL_CONTROL                              :DWORD;                                             // 0x4431
  DCP5_PRESCALE_VALUES_OVL_CB                            :DWORD;                                             // 0x4432
  DCP5_PRESCALE_VALUES_OVL_Y                             :DWORD;                                             // 0x4433
  DCP5_PRESCALE_VALUES_OVL_CR                            :DWORD;                                             // 0x4434
  DCP5_INPUT_CSC_CONTROL                                 :DWORD;                                             // 0x4435
  DCP5_INPUT_CSC_C11_C12                                 :DWORD;                                             // 0x4436
  DCP5_INPUT_CSC_C13_C14                                 :DWORD;                                             // 0x4437
  DCP5_INPUT_CSC_C21_C22                                 :DWORD;                                             // 0x4438
  DCP5_INPUT_CSC_C23_C24                                 :DWORD;                                             // 0x4439
  DCP5_INPUT_CSC_C31_C32                                 :DWORD;                                             // 0x443A
  DCP5_INPUT_CSC_C33_C34                                 :DWORD;                                             // 0x443B
  DCP5_OUTPUT_CSC_CONTROL                                :DWORD;                                             // 0x443C
  DCP5_OUTPUT_CSC_C11_C12                                :DWORD;                                             // 0x443D
  DCP5_OUTPUT_CSC_C13_C14                                :DWORD;                                             // 0x443E
  DCP5_OUTPUT_CSC_C21_C22                                :DWORD;                                             // 0x443F
  DCP5_OUTPUT_CSC_C23_C24                                :DWORD;                                             // 0x4440
  DCP5_OUTPUT_CSC_C31_C32                                :DWORD;                                             // 0x4441
  DCP5_OUTPUT_CSC_C33_C34                                :DWORD;                                             // 0x4442
  DCP5_COMM_MATRIXA_TRANS_C11_C12                        :DWORD;                                             // 0x4443
  DCP5_COMM_MATRIXA_TRANS_C13_C14                        :DWORD;                                             // 0x4444
  DCP5_COMM_MATRIXA_TRANS_C21_C22                        :DWORD;                                             // 0x4445
  DCP5_COMM_MATRIXA_TRANS_C23_C24                        :DWORD;                                             // 0x4446
  DCP5_COMM_MATRIXA_TRANS_C31_C32                        :DWORD;                                             // 0x4447
  DCP5_COMM_MATRIXA_TRANS_C33_C34                        :DWORD;                                             // 0x4448
  DCP5_COMM_MATRIXB_TRANS_C11_C12                        :DWORD;                                             // 0x4449
  DCP5_COMM_MATRIXB_TRANS_C13_C14                        :DWORD;                                             // 0x444A
  DCP5_COMM_MATRIXB_TRANS_C21_C22                        :DWORD;                                             // 0x444B
  DCP5_COMM_MATRIXB_TRANS_C23_C24                        :DWORD;                                             // 0x444C
  DCP5_COMM_MATRIXB_TRANS_C31_C32                        :DWORD;                                             // 0x444D
  DCP5_COMM_MATRIXB_TRANS_C33_C34                        :DWORD;                                             // 0x444E
  REG_444F                                               :DWORD;                                             // 0x444F
  DCP5_DENORM_CONTROL                                    :DWORD;                                             // 0x4450
  DCP5_OUT_ROUND_CONTROL                                 :DWORD;                                             // 0x4451
  DCP5_OUT_CLAMP_CONTROL_R_CR                            :DWORD;                                             // 0x4452
  DCP5_KEY_CONTROL                                       :DWORD;                                             // 0x4453
  DCP5_KEY_RANGE_ALPHA                                   :DWORD;                                             // 0x4454
  DCP5_KEY_RANGE_RED                                     :DWORD;                                             // 0x4455
  DCP5_KEY_RANGE_GREEN                                   :DWORD;                                             // 0x4456
  DCP5_KEY_RANGE_BLUE                                    :DWORD;                                             // 0x4457
  DCP5_DEGAMMA_CONTROL                                   :DWORD;                                             // 0x4458
  DCP5_GAMUT_REMAP_CONTROL                               :DWORD;                                             // 0x4459
  DCP5_GAMUT_REMAP_C11_C12                               :DWORD;                                             // 0x445A
  DCP5_GAMUT_REMAP_C13_C14                               :DWORD;                                             // 0x445B
  DCP5_GAMUT_REMAP_C21_C22                               :DWORD;                                             // 0x445C
  DCP5_GAMUT_REMAP_C23_C24                               :DWORD;                                             // 0x445D
  DCP5_GAMUT_REMAP_C31_C32                               :DWORD;                                             // 0x445E
  DCP5_GAMUT_REMAP_C33_C34                               :DWORD;                                             // 0x445F
  DCP5_DCP_SPATIAL_DITHER_CNTL                           :DWORD;                                             // 0x4460
  DCP5_DCP_RANDOM_SEEDS                                  :DWORD;                                             // 0x4461
  REG_4462_4464                                          :array[0..2] of DWORD;                              // 0x4462
  DCP5_DCP_FP_CONVERTED_FIELD                            :DWORD;                                             // 0x4465
  DCP5_CUR_CONTROL                                       :DWORD;                                             // 0x4466
  DCP5_CUR_SURFACE_ADDRESS                               :DWORD;                                             // 0x4467
  DCP5_CUR_SIZE                                          :DWORD;                                             // 0x4468
  DCP5_CUR_SURFACE_ADDRESS_HIGH                          :DWORD;                                             // 0x4469
  DCP5_CUR_POSITION                                      :DWORD;                                             // 0x446A
  DCP5_CUR_HOT_SPOT                                      :DWORD;                                             // 0x446B
  DCP5_CUR_COLOR1                                        :DWORD;                                             // 0x446C
  DCP5_CUR_COLOR2                                        :DWORD;                                             // 0x446D
  DCP5_CUR_UPDATE                                        :DWORD;                                             // 0x446E
  DCP5_CUR2_CONTROL                                      :DWORD;                                             // 0x446F
  DCP5_CUR2_SURFACE_ADDRESS                              :DWORD;                                             // 0x4470
  DCP5_CUR2_SIZE                                         :DWORD;                                             // 0x4471
  DCP5_CUR2_SURFACE_ADDRESS_HIGH                         :DWORD;                                             // 0x4472
  DCP5_CUR2_POSITION                                     :DWORD;                                             // 0x4473
  DCP5_CUR2_HOT_SPOT                                     :DWORD;                                             // 0x4474
  DCP5_CUR2_COLOR1                                       :DWORD;                                             // 0x4475
  DCP5_CUR2_COLOR2                                       :DWORD;                                             // 0x4476
  DCP5_CUR2_UPDATE                                       :DWORD;                                             // 0x4477
  DCP5_DC_LUT_RW_MODE                                    :DWORD;                                             // 0x4478
  DCP5_DC_LUT_RW_INDEX                                   :DWORD;                                             // 0x4479
  DCP5_DC_LUT_SEQ_COLOR                                  :DWORD;                                             // 0x447A
  DCP5_DC_LUT_PWL_DATA                                   :DWORD;                                             // 0x447B
  DCP5_DC_LUT_30_COLOR                                   :DWORD;                                             // 0x447C
  DCP5_DC_LUT_VGA_ACCESS_ENABLE                          :DWORD;                                             // 0x447D
  DCP5_DC_LUT_WRITE_EN_MASK                              :DWORD;                                             // 0x447E
  DCP5_DC_LUT_AUTOFILL                                   :DWORD;                                             // 0x447F
  DCP5_DC_LUT_CONTROL                                    :DWORD;                                             // 0x4480
  DCP5_DC_LUT_BLACK_OFFSET_BLUE                          :DWORD;                                             // 0x4481
  DCP5_DC_LUT_BLACK_OFFSET_GREEN                         :DWORD;                                             // 0x4482
  DCP5_DC_LUT_BLACK_OFFSET_RED                           :DWORD;                                             // 0x4483
  DCP5_DC_LUT_WHITE_OFFSET_BLUE                          :DWORD;                                             // 0x4484
  DCP5_DC_LUT_WHITE_OFFSET_GREEN                         :DWORD;                                             // 0x4485
  DCP5_DC_LUT_WHITE_OFFSET_RED                           :DWORD;                                             // 0x4486
  DCP5_DCP_CRC_CONTROL                                   :DWORD;                                             // 0x4487
  DCP5_DCP_CRC_MASK                                      :DWORD;                                             // 0x4488
  DCP5_DCP_CRC_CURRENT                                   :DWORD;                                             // 0x4489
  REG_448A                                               :DWORD;                                             // 0x448A
  DCP5_DCP_CRC_LAST                                      :DWORD;                                             // 0x448B
  REG_448C                                               :DWORD;                                             // 0x448C
  DCP5_DCP_DEBUG                                         :DWORD;                                             // 0x448D
  DCP5_GRPH_FLIP_RATE_CNTL                               :DWORD;                                             // 0x448E
  REG_448F                                               :DWORD;                                             // 0x448F
  DCP5_DCP_GSL_CONTROL                                   :DWORD;                                             // 0x4490
  DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK                     :DWORD;                                             // 0x4491
  DCP5_OVL_SECONDARY_SURFACE_ADDRESS                     :DWORD;                                             // 0x4492
  DCP5_OVL_STEREOSYNC_FLIP                               :DWORD;                                             // 0x4493
  DCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                :DWORD;                                             // 0x4494
  DCP5_DCP_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x4495
  DCP5_DCP_TEST_DEBUG_DATA                               :DWORD;                                             // 0x4496
  DCP5_GRPH_STEREOSYNC_FLIP                              :DWORD;                                             // 0x4497
  DCP5_DCP_DEBUG2                                        :DWORD;                                             // 0x4498
  DCP5_CUR_REQUEST_FILTER_CNTL                           :DWORD;                                             // 0x4499
  DCP5_CUR_STEREO_CONTROL                                :DWORD;                                             // 0x449A
  DCP5_CUR2_STEREO_CONTROL                               :DWORD;                                             // 0x449B
  DCP5_OUT_CLAMP_CONTROL_G_Y                             :DWORD;                                             // 0x449C
  DCP5_OUT_CLAMP_CONTROL_B_CB                            :DWORD;                                             // 0x449D
  DCP5_HW_ROTATION                                       :DWORD;                                             // 0x449E
  DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                :DWORD;                                             // 0x449F
  DCP5_REGAMMA_CONTROL                                   :DWORD;                                             // 0x44A0
  DCP5_REGAMMA_LUT_INDEX                                 :DWORD;                                             // 0x44A1
  DCP5_REGAMMA_LUT_DATA                                  :DWORD;                                             // 0x44A2
  DCP5_REGAMMA_LUT_WRITE_EN_MASK                         :DWORD;                                             // 0x44A3
  DCP5_REGAMMA_CNTLA_START_CNTL                          :DWORD;                                             // 0x44A4
  DCP5_REGAMMA_CNTLA_SLOPE_CNTL                          :DWORD;                                             // 0x44A5
  DCP5_REGAMMA_CNTLA_END_CNTL1                           :DWORD;                                             // 0x44A6
  DCP5_REGAMMA_CNTLA_END_CNTL2                           :DWORD;                                             // 0x44A7
  DCP5_REGAMMA_CNTLA_REGION_0_1                          :DWORD;                                             // 0x44A8
  DCP5_REGAMMA_CNTLA_REGION_2_3                          :DWORD;                                             // 0x44A9
  DCP5_REGAMMA_CNTLA_REGION_4_5                          :DWORD;                                             // 0x44AA
  DCP5_REGAMMA_CNTLA_REGION_6_7                          :DWORD;                                             // 0x44AB
  DCP5_REGAMMA_CNTLA_REGION_8_9                          :DWORD;                                             // 0x44AC
  DCP5_REGAMMA_CNTLA_REGION_10_11                        :DWORD;                                             // 0x44AD
  DCP5_REGAMMA_CNTLA_REGION_12_13                        :DWORD;                                             // 0x44AE
  DCP5_REGAMMA_CNTLA_REGION_14_15                        :DWORD;                                             // 0x44AF
  DCP5_REGAMMA_CNTLB_START_CNTL                          :DWORD;                                             // 0x44B0
  DCP5_REGAMMA_CNTLB_SLOPE_CNTL                          :DWORD;                                             // 0x44B1
  DCP5_REGAMMA_CNTLB_END_CNTL1                           :DWORD;                                             // 0x44B2
  DCP5_REGAMMA_CNTLB_END_CNTL2                           :DWORD;                                             // 0x44B3
  DCP5_REGAMMA_CNTLB_REGION_0_1                          :DWORD;                                             // 0x44B4
  DCP5_REGAMMA_CNTLB_REGION_2_3                          :DWORD;                                             // 0x44B5
  DCP5_REGAMMA_CNTLB_REGION_4_5                          :DWORD;                                             // 0x44B6
  DCP5_REGAMMA_CNTLB_REGION_6_7                          :DWORD;                                             // 0x44B7
  DCP5_REGAMMA_CNTLB_REGION_8_9                          :DWORD;                                             // 0x44B8
  DCP5_REGAMMA_CNTLB_REGION_10_11                        :DWORD;                                             // 0x44B9
  DCP5_REGAMMA_CNTLB_REGION_12_13                        :DWORD;                                             // 0x44BA
  DCP5_REGAMMA_CNTLB_REGION_14_15                        :DWORD;                                             // 0x44BB
  DCP5_ALPHA_CONTROL                                     :DWORD;                                             // 0x44BC
  DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                :DWORD;                                             // 0x44BD
  DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH           :DWORD;                                             // 0x44BE
  DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS              :DWORD;                                             // 0x44BF
  LB5_LB_DATA_FORMAT                                     :DWORD;                                             // 0x44C0
  LB5_LB_MEMORY_CTRL                                     :DWORD;                                             // 0x44C1
  LB5_LB_MEMORY_SIZE_STATUS                              :DWORD;                                             // 0x44C2
  LB5_LB_DESKTOP_HEIGHT                                  :DWORD;                                             // 0x44C3
  LB5_LB_VLINE_START_END                                 :DWORD;                                             // 0x44C4
  LB5_LB_VLINE2_START_END                                :DWORD;                                             // 0x44C5
  LB5_LB_V_COUNTER                                       :DWORD;                                             // 0x44C6
  LB5_LB_SNAPSHOT_V_COUNTER                              :DWORD;                                             // 0x44C7
  LB5_LB_INTERRUPT_MASK                                  :DWORD;                                             // 0x44C8
  LB5_LB_VLINE_STATUS                                    :DWORD;                                             // 0x44C9
  LB5_LB_VLINE2_STATUS                                   :DWORD;                                             // 0x44CA
  LB5_LB_VBLANK_STATUS                                   :DWORD;                                             // 0x44CB
  LB5_LB_SYNC_RESET_SEL                                  :DWORD;                                             // 0x44CC
  LB5_LB_BLACK_KEYER_R_CR                                :DWORD;                                             // 0x44CD
  LB5_LB_BLACK_KEYER_G_Y                                 :DWORD;                                             // 0x44CE
  LB5_LB_BLACK_KEYER_B_CB                                :DWORD;                                             // 0x44CF
  LB5_LB_KEYER_COLOR_CTRL                                :DWORD;                                             // 0x44D0
  LB5_LB_KEYER_COLOR_R_CR                                :DWORD;                                             // 0x44D1
  LB5_LB_KEYER_COLOR_G_Y                                 :DWORD;                                             // 0x44D2
  LB5_LB_KEYER_COLOR_B_CB                                :DWORD;                                             // 0x44D3
  LB5_LB_KEYER_COLOR_REP_R_CR                            :DWORD;                                             // 0x44D4
  LB5_LB_KEYER_COLOR_REP_G_Y                             :DWORD;                                             // 0x44D5
  LB5_LB_KEYER_COLOR_REP_B_CB                            :DWORD;                                             // 0x44D6
  LB5_LB_BUFFER_LEVEL_STATUS                             :DWORD;                                             // 0x44D7
  LB5_LB_BUFFER_URGENCY_CTRL                             :DWORD;                                             // 0x44D8
  LB5_LB_BUFFER_URGENCY_STATUS                           :DWORD;                                             // 0x44D9
  LB5_LB_BUFFER_STATUS                                   :DWORD;                                             // 0x44DA
  REG_44DB                                               :DWORD;                                             // 0x44DB
  LB5_LB_NO_OUTSTANDING_REQ_STATUS                       :DWORD;                                             // 0x44DC
  REG_44DD_44DF                                          :array[0..2] of DWORD;                              // 0x44DD
  LB5_MVP_AFR_FLIP_MODE                                  :DWORD;                                             // 0x44E0
  LB5_MVP_AFR_FLIP_FIFO_CNTL                             :DWORD;                                             // 0x44E1
  LB5_MVP_FLIP_LINE_NUM_INSERT                           :DWORD;                                             // 0x44E2
  LB5_DC_MVP_LB_CONTROL                                  :DWORD;                                             // 0x44E3
  LB5_LB_DEBUG                                           :DWORD;                                             // 0x44E4
  LB5_LB_DEBUG2                                          :DWORD;                                             // 0x44E5
  LB5_LB_DEBUG3                                          :DWORD;                                             // 0x44E6
  REG_44E7_44FD                                          :array[0..22] of DWORD;                             // 0x44E7
  LB5_LB_TEST_DEBUG_INDEX                                :DWORD;                                             // 0x44FE
  LB5_LB_TEST_DEBUG_DATA                                 :DWORD;                                             // 0x44FF
  DCFE5_DCFE_CLOCK_CONTROL                               :DWORD;                                             // 0x4500
  DCFE5_DCFE_SOFT_RESET                                  :DWORD;                                             // 0x4501
  DCFE5_DCFE_DBG_CONFIG                                  :DWORD;                                             // 0x4502
  REG_4503_4512                                          :array[0..15] of DWORD;                             // 0x4503
  DIG3_HDMI_GENERIC_PACKET_CONTROL                       :DWORD;                                             // 0x4513
  REG_4514_4523                                          :array[0..15] of DWORD;                             // 0x4514
  DC_PERFMON8_PERFCOUNTER_CNTL                           :DWORD;                                             // 0x4524
  DC_PERFMON8_PERFCOUNTER_STATE                          :DWORD;                                             // 0x4525
  DC_PERFMON8_PERFMON_CVALUE_INT_MISC                    :DWORD;                                             // 0x4526
  DC_PERFMON8_PERFMON_CNTL                               :DWORD;                                             // 0x4527
  DC_PERFMON8_PERFMON_CVALUE_LOW                         :DWORD;                                             // 0x4528
  DC_PERFMON8_PERFMON_HI                                 :DWORD;                                             // 0x4529
  DC_PERFMON8_PERFMON_LOW                                :DWORD;                                             // 0x452A
  DC_PERFMON8_PERFMON_TEST_DEBUG_INDEX                   :DWORD;                                             // 0x452B
  DC_PERFMON8_PERFMON_TEST_DEBUG_DATA                    :DWORD;                                             // 0x452C
  REG_452D                                               :DWORD;                                             // 0x452D
  DC_PERFMON8_PERFMON_CNTL2                              :DWORD;                                             // 0x452E
  REG_452F                                               :DWORD;                                             // 0x452F
  DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1                 :DWORD;                                             // 0x4530
  DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2                 :DWORD;                                             // 0x4531
  DMIF_PG5_DPG_WATERMARK_MASK_CONTROL                    :DWORD;                                             // 0x4532
  DMIF_PG5_DPG_PIPE_URGENCY_CONTROL                      :DWORD;                                             // 0x4533
  DMIF_PG5_DPG_PIPE_DPM_CONTROL                          :DWORD;                                             // 0x4534
  DMIF_PG5_DPG_PIPE_STUTTER_CONTROL                      :DWORD;                                             // 0x4535
  DMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             :DWORD;                                             // 0x4536
  DMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             :DWORD;                                             // 0x4537
  DMIF_PG5_DPG_TEST_DEBUG_INDEX                          :DWORD;                                             // 0x4538
  DMIF_PG5_DPG_TEST_DEBUG_DATA                           :DWORD;                                             // 0x4539
  DMIF_PG5_DPG_REPEATER_PROGRAM                          :DWORD;                                             // 0x453A
  DMIF_PG5_DPG_HW_DEBUG_A                                :DWORD;                                             // 0x453B
  DMIF_PG5_DPG_HW_DEBUG_B                                :DWORD;                                             // 0x453C
  DMIF_PG5_DPG_HW_DEBUG_11                               :DWORD;                                             // 0x453D
  REG_453E_453F                                          :array[0..1] of DWORD;                              // 0x453E
  SCL5_SCL_COEF_RAM_SELECT                               :DWORD;                                             // 0x4540
  SCL5_SCL_COEF_RAM_TAP_DATA                             :DWORD;                                             // 0x4541
  SCL5_SCL_MODE                                          :DWORD;                                             // 0x4542
  SCL5_SCL_TAP_CONTROL                                   :DWORD;                                             // 0x4543
  SCL5_SCL_CONTROL                                       :DWORD;                                             // 0x4544
  SCL5_SCL_BYPASS_CONTROL                                :DWORD;                                             // 0x4545
  SCL5_SCL_MANUAL_REPLICATE_CONTROL                      :DWORD;                                             // 0x4546
  SCL5_SCL_AUTOMATIC_MODE_CONTROL                        :DWORD;                                             // 0x4547
  SCL5_SCL_HORZ_FILTER_CONTROL                           :DWORD;                                             // 0x4548
  SCL5_SCL_HORZ_FILTER_SCALE_RATIO                       :DWORD;                                             // 0x4549
  SCL5_SCL_HORZ_FILTER_INIT                              :DWORD;                                             // 0x454A
  SCL5_SCL_VERT_FILTER_CONTROL                           :DWORD;                                             // 0x454B
  SCL5_SCL_VERT_FILTER_SCALE_RATIO                       :DWORD;                                             // 0x454C
  SCL5_SCL_VERT_FILTER_INIT                              :DWORD;                                             // 0x454D
  SCL5_SCL_VERT_FILTER_INIT_BOT                          :DWORD;                                             // 0x454E
  SCL5_SCL_ROUND_OFFSET                                  :DWORD;                                             // 0x454F
  REG_4550                                               :DWORD;                                             // 0x4550
  SCL5_SCL_UPDATE                                        :DWORD;                                             // 0x4551
  REG_4552                                               :DWORD;                                             // 0x4552
  SCL5_SCL_F_SHARP_CONTROL                               :DWORD;                                             // 0x4553
  SCL5_SCL_ALU_CONTROL                                   :DWORD;                                             // 0x4554
  SCL5_SCL_COEF_RAM_CONFLICT_STATUS                      :DWORD;                                             // 0x4555
  REG_4556_455A                                          :array[0..4] of DWORD;                              // 0x4556
  SCL5_VIEWPORT_START_SECONDARY                          :DWORD;                                             // 0x455B
  SCL5_VIEWPORT_START                                    :DWORD;                                             // 0x455C
  SCL5_VIEWPORT_SIZE                                     :DWORD;                                             // 0x455D
  SCL5_EXT_OVERSCAN_LEFT_RIGHT                           :DWORD;                                             // 0x455E
  SCL5_EXT_OVERSCAN_TOP_BOTTOM                           :DWORD;                                             // 0x455F
  SCL5_SCL_MODE_CHANGE_DET1                              :DWORD;                                             // 0x4560
  SCL5_SCL_MODE_CHANGE_DET2                              :DWORD;                                             // 0x4561
  SCL5_SCL_MODE_CHANGE_DET3                              :DWORD;                                             // 0x4562
  SCL5_SCL_MODE_CHANGE_MASK                              :DWORD;                                             // 0x4563
  REG_4564_4568                                          :array[0..4] of DWORD;                              // 0x4564
  SCL5_SCL_DEBUG2                                        :DWORD;                                             // 0x4569
  SCL5_SCL_DEBUG                                         :DWORD;                                             // 0x456A
  SCL5_SCL_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x456B
  SCL5_SCL_TEST_DEBUG_DATA                               :DWORD;                                             // 0x456C
  BLND5_BLND_CONTROL                                     :DWORD;                                             // 0x456D
  BLND5_SM_CONTROL2                                      :DWORD;                                             // 0x456E
  BLND5_BLND_CONTROL2                                    :DWORD;                                             // 0x456F
  BLND5_BLND_UPDATE                                      :DWORD;                                             // 0x4570
  BLND5_BLND_UNDERFLOW_INTERRUPT                         :DWORD;                                             // 0x4571
  REG_4572                                               :DWORD;                                             // 0x4572
  BLND5_BLND_V_UPDATE_LOCK                               :DWORD;                                             // 0x4573
  BLND5_BLND_DEBUG                                       :DWORD;                                             // 0x4574
  BLND5_BLND_TEST_DEBUG_INDEX                            :DWORD;                                             // 0x4575
  BLND5_BLND_TEST_DEBUG_DATA                             :DWORD;                                             // 0x4576
  BLND5_BLND_REG_UPDATE_STATUS                           :DWORD;                                             // 0x4577
  CRTC5_CRTC_3D_STRUCTURE_CONTROL                        :DWORD;                                             // 0x4578
  CRTC5_CRTC_GSL_VSYNC_GAP                               :DWORD;                                             // 0x4579
  CRTC5_CRTC_GSL_WINDOW                                  :DWORD;                                             // 0x457A
  CRTC5_CRTC_GSL_CONTROL                                 :DWORD;                                             // 0x457B
  CRTC5_CRTC_DCFE_CLOCK_CONTROL                          :DWORD;                                             // 0x457C
  CRTC5_CRTC_H_BLANK_EARLY_NUM                           :DWORD;                                             // 0x457D
  CRTC5_DCFE_DBG_SEL                                     :DWORD;                                             // 0x457E
  CRTC5_DCFE_MEM_PWR_CTRL                                :DWORD;                                             // 0x457F
  REG_4580_4584                                          :array[0..4] of DWORD;                              // 0x4580
  CRTC5_CRTC_H_SYNC_B_CNTL                               :DWORD;                                             // 0x4585
  REG_4586_4587                                          :array[0..1] of DWORD;                              // 0x4586
  CRTC5_CRTC_V_TOTAL_MIN                                 :DWORD;                                             // 0x4588
  CRTC5_CRTC_V_TOTAL_MAX                                 :DWORD;                                             // 0x4589
  CRTC5_CRTC_V_TOTAL_CONTROL                             :DWORD;                                             // 0x458A
  CRTC5_CRTC_V_TOTAL_INT_STATUS                          :DWORD;                                             // 0x458B
  REG_458C                                               :DWORD;                                             // 0x458C
  CRTC5_CRTC_V_BLANK_START_END                           :DWORD;                                             // 0x458D
  CRTC5_CRTC_V_SYNC_A                                    :DWORD;                                             // 0x458E
  CRTC5_CRTC_V_SYNC_A_CNTL                               :DWORD;                                             // 0x458F
  CRTC5_CRTC_V_SYNC_B                                    :DWORD;                                             // 0x4590
  CRTC5_CRTC_V_SYNC_B_CNTL                               :DWORD;                                             // 0x4591
  CRTC5_CRTC_DTMTEST_CNTL                                :DWORD;                                             // 0x4592
  CRTC5_CRTC_DTMTEST_STATUS_POSITION                     :DWORD;                                             // 0x4593
  CRTC5_CRTC_TRIGA_CNTL                                  :DWORD;                                             // 0x4594
  CRTC5_CRTC_TRIGA_MANUAL_TRIG                           :DWORD;                                             // 0x4595
  CRTC5_CRTC_TRIGB_CNTL                                  :DWORD;                                             // 0x4596
  CRTC5_CRTC_TRIGB_MANUAL_TRIG                           :DWORD;                                             // 0x4597
  CRTC5_CRTC_FORCE_COUNT_NOW_CNTL                        :DWORD;                                             // 0x4598
  CRTC5_CRTC_FLOW_CONTROL                                :DWORD;                                             // 0x4599
  CRTC5_CRTC_STEREO_FORCE_NEXT_EYE                       :DWORD;                                             // 0x459A
  CRTC5_CRTC_AVSYNC_COUNTER                              :DWORD;                                             // 0x459B
  CRTC5_CRTC_CONTROL                                     :DWORD;                                             // 0x459C
  CRTC5_CRTC_BLANK_CONTROL                               :DWORD;                                             // 0x459D
  CRTC5_CRTC_INTERLACE_CONTROL                           :DWORD;                                             // 0x459E
  CRTC5_CRTC_INTERLACE_STATUS                            :DWORD;                                             // 0x459F
  CRTC5_CRTC_FIELD_INDICATION_CONTROL                    :DWORD;                                             // 0x45A0
  CRTC5_CRTC_PIXEL_DATA_READBACK0                        :DWORD;                                             // 0x45A1
  CRTC5_CRTC_PIXEL_DATA_READBACK1                        :DWORD;                                             // 0x45A2
  CRTC5_CRTC_STATUS                                      :DWORD;                                             // 0x45A3
  CRTC5_CRTC_STATUS_POSITION                             :DWORD;                                             // 0x45A4
  REG_45A5_45AA                                          :array[0..5] of DWORD;                              // 0x45A5
  CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                :DWORD;                                             // 0x45AB
  CRTC5_CRTC_VERT_SYNC_CONTROL                           :DWORD;                                             // 0x45AC
  CRTC5_CRTC_STEREO_STATUS                               :DWORD;                                             // 0x45AD
  CRTC5_CRTC_STEREO_CONTROL                              :DWORD;                                             // 0x45AE
  CRTC5_CRTC_SNAPSHOT_STATUS                             :DWORD;                                             // 0x45AF
  CRTC5_CRTC_SNAPSHOT_CONTROL                            :DWORD;                                             // 0x45B0
  CRTC5_CRTC_SNAPSHOT_POSITION                           :DWORD;                                             // 0x45B1
  CRTC5_CRTC_SNAPSHOT_FRAME                              :DWORD;                                             // 0x45B2
  CRTC5_CRTC_START_LINE_CONTROL                          :DWORD;                                             // 0x45B3
  CRTC5_CRTC_INTERRUPT_CONTROL                           :DWORD;                                             // 0x45B4
  CRTC5_CRTC_UPDATE_LOCK                                 :DWORD;                                             // 0x45B5
  CRTC5_CRTC_DOUBLE_BUFFER_CONTROL                       :DWORD;                                             // 0x45B6
  CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE                  :DWORD;                                             // 0x45B7
  CRTC5_DCFE_MEM_PWR_CTRL2                               :DWORD;                                             // 0x45B8
  CRTC5_DCFE_MEM_PWR_STATUS                              :DWORD;                                             // 0x45B9
  CRTC5_CRTC_TEST_PATTERN_CONTROL                        :DWORD;                                             // 0x45BA
  CRTC5_CRTC_TEST_PATTERN_PARAMETERS                     :DWORD;                                             // 0x45BB
  CRTC5_CRTC_TEST_PATTERN_COLOR                          :DWORD;                                             // 0x45BC
  CRTC5_MASTER_UPDATE_LOCK                               :DWORD;                                             // 0x45BD
  CRTC5_MASTER_UPDATE_MODE                               :DWORD;                                             // 0x45BE
  CRTC5_CRTC_MVP_INBAND_CNTL_INSERT                      :DWORD;                                             // 0x45BF
  REG_45C0_45C5                                          :array[0..5] of DWORD;                              // 0x45C0
  CRTC5_CRTC_TEST_DEBUG_INDEX                            :DWORD;                                             // 0x45C6
  CRTC5_CRTC_TEST_DEBUG_DATA                             :DWORD;                                             // 0x45C7
  CRTC5_CRTC_OVERSCAN_COLOR                              :DWORD;                                             // 0x45C8
  CRTC5_CRTC_OVERSCAN_COLOR_EXT                          :DWORD;                                             // 0x45C9
  REG_45CA                                               :DWORD;                                             // 0x45CA
  CRTC5_CRTC_BLANK_DATA_COLOR_EXT                        :DWORD;                                             // 0x45CB
  CRTC5_CRTC_BLACK_COLOR                                 :DWORD;                                             // 0x45CC
  CRTC5_CRTC_BLACK_COLOR_EXT                             :DWORD;                                             // 0x45CD
  CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION                :DWORD;                                             // 0x45CE
  CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL                 :DWORD;                                             // 0x45CF
  CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION                :DWORD;                                             // 0x45D0
  CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL                 :DWORD;                                             // 0x45D1
  CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION                :DWORD;                                             // 0x45D2
  CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL                 :DWORD;                                             // 0x45D3
  CRTC5_CRTC_CRC_CNTL                                    :DWORD;                                             // 0x45D4
  CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL                      :DWORD;                                             // 0x45D5
  CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL                      :DWORD;                                             // 0x45D6
  CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL                      :DWORD;                                             // 0x45D7
  CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL                      :DWORD;                                             // 0x45D8
  CRTC5_CRTC_CRC0_DATA_RG                                :DWORD;                                             // 0x45D9
  CRTC5_CRTC_CRC0_DATA_B                                 :DWORD;                                             // 0x45DA
  CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL                      :DWORD;                                             // 0x45DB
  CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL                      :DWORD;                                             // 0x45DC
  CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL                      :DWORD;                                             // 0x45DD
  CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL                      :DWORD;                                             // 0x45DE
  CRTC5_CRTC_CRC1_DATA_RG                                :DWORD;                                             // 0x45DF
  CRTC5_CRTC_CRC1_DATA_B                                 :DWORD;                                             // 0x45E0
  CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL                     :DWORD;                                             // 0x45E1
  CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START                :DWORD;                                             // 0x45E2
  CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END                  :DWORD;                                             // 0x45E3
  CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      :DWORD;                                             // 0x45E4
  CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           :DWORD;                                             // 0x45E5
  CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    :DWORD;                                             // 0x45E6
  CRTC5_CRTC_STATIC_SCREEN_CONTROL                       :DWORD;                                             // 0x45E7
  FMT5_FMT_CLAMP_COMPONENT_R                             :DWORD;                                             // 0x45E8
  FMT5_FMT_CLAMP_COMPONENT_G                             :DWORD;                                             // 0x45E9
  FMT5_FMT_CLAMP_COMPONENT_B                             :DWORD;                                             // 0x45EA
  FMT5_FMT_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x45EB
  FMT5_FMT_TEST_DEBUG_DATA                               :DWORD;                                             // 0x45EC
  FMT5_FMT_DYNAMIC_EXP_CNTL                              :DWORD;                                             // 0x45ED
  FMT5_FMT_CONTROL                                       :DWORD;                                             // 0x45EE
  FMT5_FMT_FORCE_OUTPUT_CNTL                             :DWORD;                                             // 0x45EF
  FMT5_FMT_FORCE_DATA_0_1                                :DWORD;                                             // 0x45F0
  FMT5_FMT_FORCE_DATA_2_3                                :DWORD;                                             // 0x45F1
  FMT5_FMT_BIT_DEPTH_CONTROL                             :DWORD;                                             // 0x45F2
  FMT5_FMT_DITHER_RAND_R_SEED                            :DWORD;                                             // 0x45F3
  FMT5_FMT_DITHER_RAND_G_SEED                            :DWORD;                                             // 0x45F4
  FMT5_FMT_DITHER_RAND_B_SEED                            :DWORD;                                             // 0x45F5
  FMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL               :DWORD;                                             // 0x45F6
  FMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :DWORD;                                             // 0x45F7
  FMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :DWORD;                                             // 0x45F8
  FMT5_FMT_CLAMP_CNTL                                    :DWORD;                                             // 0x45F9
  FMT5_FMT_CRC_CNTL                                      :DWORD;                                             // 0x45FA
  FMT5_FMT_CRC_SIG_RED_GREEN_MASK                        :DWORD;                                             // 0x45FB
  FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK                     :DWORD;                                             // 0x45FC
  FMT5_FMT_CRC_SIG_RED_GREEN                             :DWORD;                                             // 0x45FD
  FMT5_FMT_CRC_SIG_BLUE_CONTROL                          :DWORD;                                             // 0x45FE
  FMT5_FMT_DEBUG_CNTL                                    :DWORD;                                             // 0x45FF
  UNP_GRPH_ENABLE                                        :TUNP_GRPH_ENABLE;                                  // 0x4600
  UNP_GRPH_CONTROL                                       :TUNP_GRPH_CONTROL;                                 // 0x4601
  REG_4602                                               :DWORD;                                             // 0x4602
  UNP_GRPH_CONTROL_EXP                                   :TUNP_GRPH_CONTROL_EXP;                             // 0x4603
  REG_4604                                               :DWORD;                                             // 0x4604
  UNP_GRPH_SWAP_CNTL                                     :TUNP_GRPH_SWAP_CNTL;                               // 0x4605
  UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                     :TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L;               // 0x4606
  UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                     :TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C;               // 0x4607
  UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                :TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L;          // 0x4608
  UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                :TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C;          // 0x4609
  UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L              :TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L;        // 0x460A
  UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C              :TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C;        // 0x460B
  UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L         :TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L;   // 0x460C
  UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C         :TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C;   // 0x460D
  UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                   :TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L;             // 0x460E
  UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                   :TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C;             // 0x460F
  UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L              :TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L;        // 0x4610
  UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C              :TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C;        // 0x4611
  UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L            :TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L;      // 0x4612
  UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C            :TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C;      // 0x4613
  UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L       :TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L; // 0x4614
  UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C       :TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C; // 0x4615
  UNP_GRPH_PITCH_L                                       :TUNP_GRPH_PITCH_L;                                 // 0x4616
  UNP_GRPH_PITCH_C                                       :TUNP_GRPH_PITCH_C;                                 // 0x4617
  UNP_GRPH_SURFACE_OFFSET_X_L                            :TUNP_GRPH_SURFACE_OFFSET_X_L;                      // 0x4618
  UNP_GRPH_SURFACE_OFFSET_X_C                            :TUNP_GRPH_SURFACE_OFFSET_X_C;                      // 0x4619
  UNP_GRPH_SURFACE_OFFSET_Y_L                            :TUNP_GRPH_SURFACE_OFFSET_Y_L;                      // 0x461A
  UNP_GRPH_SURFACE_OFFSET_Y_C                            :TUNP_GRPH_SURFACE_OFFSET_Y_C;                      // 0x461B
  UNP_GRPH_X_START_L                                     :TUNP_GRPH_X_START_L;                               // 0x461C
  UNP_GRPH_X_START_C                                     :TUNP_GRPH_X_START_C;                               // 0x461D
  UNP_GRPH_Y_START_L                                     :TUNP_GRPH_Y_START_L;                               // 0x461E
  UNP_GRPH_Y_START_C                                     :TUNP_GRPH_Y_START_C;                               // 0x461F
  UNP_GRPH_X_END_L                                       :TUNP_GRPH_X_END_L;                                 // 0x4620
  UNP_GRPH_X_END_C                                       :TUNP_GRPH_X_END_C;                                 // 0x4621
  UNP_GRPH_Y_END_L                                       :TUNP_GRPH_Y_END_L;                                 // 0x4622
  UNP_GRPH_Y_END_C                                       :TUNP_GRPH_Y_END_C;                                 // 0x4623
  UNP_GRPH_UPDATE                                        :TUNP_GRPH_UPDATE;                                  // 0x4624
  UNP_GRPH_SURFACE_ADDRESS_INUSE_L                       :TUNP_GRPH_SURFACE_ADDRESS_INUSE_L;                 // 0x4625
  UNP_GRPH_SURFACE_ADDRESS_INUSE_C                       :TUNP_GRPH_SURFACE_ADDRESS_INUSE_C;                 // 0x4626
  UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                  :TUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L;            // 0x4627
  UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                  :TUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C;            // 0x4628
  UNP_GRPH_DFQ_CONTROL                                   :TUNP_GRPH_DFQ_CONTROL;                             // 0x4629
  UNP_GRPH_DFQ_STATUS                                    :TUNP_GRPH_DFQ_STATUS;                              // 0x462A
  UNP_GRPH_INTERRUPT_STATUS                              :TUNP_GRPH_INTERRUPT_STATUS;                        // 0x462B
  UNP_GRPH_INTERRUPT_CONTROL                             :TUNP_GRPH_INTERRUPT_CONTROL;                       // 0x462C
  REG_462D                                               :DWORD;                                             // 0x462D
  UNP_GRPH_STEREOSYNC_FLIP                               :TUNP_GRPH_STEREOSYNC_FLIP;                         // 0x462E
  UNP_GRPH_FLIP_RATE_CNTL                                :TUNP_GRPH_FLIP_RATE_CNTL;                          // 0x462F
  UNP_CRC_CONTROL                                        :TUNP_CRC_CONTROL;                                  // 0x4630
  UNP_CRC_MASK                                           :TUNP_CRC_MASK;                                     // 0x4631
  UNP_CRC_CURRENT                                        :TUNP_CRC_CURRENT;                                  // 0x4632
  UNP_CRC_LAST                                           :TUNP_CRC_LAST;                                     // 0x4633
  UNP_LB_DATA_GAP_BETWEEN_CHUNK                          :TUNP_LB_DATA_GAP_BETWEEN_CHUNK;                    // 0x4634
  UNP_HW_ROTATION                                        :TUNP_HW_ROTATION;                                  // 0x4635
  UNP_DEBUG                                              :TUNP_DEBUG;                                        // 0x4636
  UNP_DEBUG2                                             :TUNP_DEBUG2;                                       // 0x4637
  UNP_TEST_DEBUG_INDEX                                   :TUNP_TEST_DEBUG_INDEX;                             // 0x4638
  UNP_TEST_DEBUG_DATA                                    :TUNP_TEST_DEBUG_DATA;                              // 0x4639
  REG_463A_463B                                          :array[0..1] of DWORD;                              // 0x463A
  LBV_DATA_FORMAT                                        :TLBV_DATA_FORMAT;                                  // 0x463C
  LBV_MEMORY_CTRL                                        :TLBV_MEMORY_CTRL;                                  // 0x463D
  LBV_MEMORY_SIZE_STATUS                                 :TLBV_MEMORY_SIZE_STATUS;                           // 0x463E
  LBV_DESKTOP_HEIGHT                                     :TLBV_DESKTOP_HEIGHT;                               // 0x463F
  LBV_VLINE_START_END                                    :TLBV_VLINE_START_END;                              // 0x4640
  LBV_VLINE2_START_END                                   :TLBV_VLINE2_START_END;                             // 0x4641
  LBV_V_COUNTER                                          :TLBV_V_COUNTER;                                    // 0x4642
  LBV_SNAPSHOT_V_COUNTER                                 :TLBV_SNAPSHOT_V_COUNTER;                           // 0x4643
  LBV_V_COUNTER_CHROMA                                   :TLBV_V_COUNTER_CHROMA;                             // 0x4644
  LBV_SNAPSHOT_V_COUNTER_CHROMA                          :TLBV_SNAPSHOT_V_COUNTER_CHROMA;                    // 0x4645
  LBV_INTERRUPT_MASK                                     :TLBV_INTERRUPT_MASK;                               // 0x4646
  LBV_VLINE_STATUS                                       :TLBV_VLINE_STATUS;                                 // 0x4647
  LBV_VLINE2_STATUS                                      :TLBV_VLINE2_STATUS;                                // 0x4648
  LBV_VBLANK_STATUS                                      :TLBV_VBLANK_STATUS;                                // 0x4649
  LBV_SYNC_RESET_SEL                                     :TLBV_SYNC_RESET_SEL;                               // 0x464A
  LBV_BLACK_KEYER_R_CR                                   :TLBV_BLACK_KEYER_R_CR;                             // 0x464B
  LBV_BLACK_KEYER_G_Y                                    :TLBV_BLACK_KEYER_G_Y;                              // 0x464C
  LBV_BLACK_KEYER_B_CB                                   :TLBV_BLACK_KEYER_B_CB;                             // 0x464D
  LBV_KEYER_COLOR_CTRL                                   :TLBV_KEYER_COLOR_CTRL;                             // 0x464E
  LBV_KEYER_COLOR_R_CR                                   :TLBV_KEYER_COLOR_R_CR;                             // 0x464F
  LBV_KEYER_COLOR_G_Y                                    :TLBV_KEYER_COLOR_G_Y;                              // 0x4650
  LBV_KEYER_COLOR_B_CB                                   :TLBV_KEYER_COLOR_B_CB;                             // 0x4651
  LBV_KEYER_COLOR_REP_R_CR                               :TLBV_KEYER_COLOR_REP_R_CR;                         // 0x4652
  LBV_KEYER_COLOR_REP_G_Y                                :TLBV_KEYER_COLOR_REP_G_Y;                          // 0x4653
  LBV_KEYER_COLOR_REP_B_CB                               :TLBV_KEYER_COLOR_REP_B_CB;                         // 0x4654
  LBV_BUFFER_LEVEL_STATUS                                :TLBV_BUFFER_LEVEL_STATUS;                          // 0x4655
  LBV_BUFFER_URGENCY_CTRL                                :TLBV_BUFFER_URGENCY_CTRL;                          // 0x4656
  LBV_BUFFER_URGENCY_STATUS                              :TLBV_BUFFER_URGENCY_STATUS;                        // 0x4657
  LBV_BUFFER_STATUS                                      :TLBV_BUFFER_STATUS;                                // 0x4658
  LBV_NO_OUTSTANDING_REQ_STATUS                          :TLBV_NO_OUTSTANDING_REQ_STATUS;                    // 0x4659
  LBV_DEBUG                                              :TLBV_DEBUG;                                        // 0x465A
  LBV_DEBUG2                                             :TLBV_DEBUG2;                                       // 0x465B
  LBV_DEBUG3                                             :TLBV_DEBUG3;                                       // 0x465C
  REG_465D_4665                                          :array[0..8] of DWORD;                              // 0x465D
  LBV_TEST_DEBUG_INDEX                                   :TLBV_TEST_DEBUG_INDEX;                             // 0x4666
  LBV_TEST_DEBUG_DATA                                    :TLBV_TEST_DEBUG_DATA;                              // 0x4667
  REG_4668_466F                                          :array[0..7] of DWORD;                              // 0x4668
  SCLV_COEF_RAM_SELECT                                   :TSCLV_COEF_RAM_SELECT;                             // 0x4670
  SCLV_COEF_RAM_TAP_DATA                                 :TSCLV_COEF_RAM_TAP_DATA;                           // 0x4671
  SCLV_MODE                                              :TSCLV_MODE;                                        // 0x4672
  SCLV_TAP_CONTROL                                       :TSCLV_TAP_CONTROL;                                 // 0x4673
  SCLV_CONTROL                                           :TSCLV_CONTROL;                                     // 0x4674
  SCLV_MANUAL_REPLICATE_CONTROL                          :TSCLV_MANUAL_REPLICATE_CONTROL;                    // 0x4675
  SCLV_AUTOMATIC_MODE_CONTROL                            :TSCLV_AUTOMATIC_MODE_CONTROL;                      // 0x4676
  SCLV_HORZ_FILTER_CONTROL                               :TSCLV_HORZ_FILTER_CONTROL;                         // 0x4677
  SCLV_HORZ_FILTER_SCALE_RATIO                           :TSCLV_HORZ_FILTER_SCALE_RATIO;                     // 0x4678
  SCLV_HORZ_FILTER_INIT                                  :TSCLV_HORZ_FILTER_INIT;                            // 0x4679
  SCLV_HORZ_FILTER_SCALE_RATIO_C                         :TSCLV_HORZ_FILTER_SCALE_RATIO_C;                   // 0x467A
  SCLV_HORZ_FILTER_INIT_C                                :TSCLV_HORZ_FILTER_INIT_C;                          // 0x467B
  SCLV_VERT_FILTER_CONTROL                               :TSCLV_VERT_FILTER_CONTROL;                         // 0x467C
  SCLV_VERT_FILTER_SCALE_RATIO                           :TSCLV_VERT_FILTER_SCALE_RATIO;                     // 0x467D
  SCLV_VERT_FILTER_INIT                                  :TSCLV_VERT_FILTER_INIT;                            // 0x467E
  SCLV_VERT_FILTER_INIT_BOT                              :TSCLV_VERT_FILTER_INIT_BOT;                        // 0x467F
  SCLV_VERT_FILTER_SCALE_RATIO_C                         :TSCLV_VERT_FILTER_SCALE_RATIO_C;                   // 0x4680
  SCLV_VERT_FILTER_INIT_C                                :TSCLV_VERT_FILTER_INIT_C;                          // 0x4681
  SCLV_VERT_FILTER_INIT_BOT_C                            :TSCLV_VERT_FILTER_INIT_BOT_C;                      // 0x4682
  SCLV_ROUND_OFFSET                                      :TSCLV_ROUND_OFFSET;                                // 0x4683
  SCLV_UPDATE                                            :TSCLV_UPDATE;                                      // 0x4684
  SCLV_ALU_CONTROL                                       :TSCLV_ALU_CONTROL;                                 // 0x4685
  SCLV_VIEWPORT_START                                    :TSCLV_VIEWPORT_START;                              // 0x4686
  SCLV_VIEWPORT_START_SECONDARY                          :TSCLV_VIEWPORT_START_SECONDARY;                    // 0x4687
  SCLV_VIEWPORT_SIZE                                     :TSCLV_VIEWPORT_SIZE;                               // 0x4688
  SCLV_VIEWPORT_START_C                                  :TSCLV_VIEWPORT_START_C;                            // 0x4689
  SCLV_VIEWPORT_START_SECONDARY_C                        :TSCLV_VIEWPORT_START_SECONDARY_C;                  // 0x468A
  SCLV_VIEWPORT_SIZE_C                                   :TSCLV_VIEWPORT_SIZE_C;                             // 0x468B
  SCLV_EXT_OVERSCAN_LEFT_RIGHT                           :TSCLV_EXT_OVERSCAN_LEFT_RIGHT;                     // 0x468C
  SCLV_EXT_OVERSCAN_TOP_BOTTOM                           :TSCLV_EXT_OVERSCAN_TOP_BOTTOM;                     // 0x468D
  SCLV_MODE_CHANGE_DET1                                  :TSCLV_MODE_CHANGE_DET1;                            // 0x468E
  SCLV_MODE_CHANGE_DET2                                  :TSCLV_MODE_CHANGE_DET2;                            // 0x468F
  SCLV_MODE_CHANGE_DET3                                  :TSCLV_MODE_CHANGE_DET3;                            // 0x4690
  SCLV_MODE_CHANGE_MASK                                  :TSCLV_MODE_CHANGE_MASK;                            // 0x4691
  SCLV_DEBUG2                                            :TSCLV_DEBUG2;                                      // 0x4692
  SCLV_DEBUG                                             :TSCLV_DEBUG;                                       // 0x4693
  SCLV_TEST_DEBUG_INDEX                                  :TSCLV_TEST_DEBUG_INDEX;                            // 0x4694
  SCLV_TEST_DEBUG_DATA                                   :TSCLV_TEST_DEBUG_DATA;                             // 0x4695
  REG_4696_46A3                                          :array[0..13] of DWORD;                             // 0x4696
  COL_MAN_UPDATE                                         :TCOL_MAN_UPDATE;                                   // 0x46A4
  COL_MAN_INPUT_CSC_CONTROL                              :TCOL_MAN_INPUT_CSC_CONTROL;                        // 0x46A5
  INPUT_CSC_C11_C12_A                                    :TINPUT_CSC_C11_C12_A;                              // 0x46A6
  INPUT_CSC_C13_C14_A                                    :TINPUT_CSC_C13_C14_A;                              // 0x46A7
  INPUT_CSC_C21_C22_A                                    :TINPUT_CSC_C21_C22_A;                              // 0x46A8
  INPUT_CSC_C23_C24_A                                    :TINPUT_CSC_C23_C24_A;                              // 0x46A9
  INPUT_CSC_C31_C32_A                                    :TINPUT_CSC_C31_C32_A;                              // 0x46AA
  INPUT_CSC_C33_C34_A                                    :TINPUT_CSC_C33_C34_A;                              // 0x46AB
  INPUT_CSC_C11_C12_B                                    :TINPUT_CSC_C11_C12_B;                              // 0x46AC
  INPUT_CSC_C13_C14_B                                    :TINPUT_CSC_C13_C14_B;                              // 0x46AD
  INPUT_CSC_C21_C22_B                                    :TINPUT_CSC_C21_C22_B;                              // 0x46AE
  INPUT_CSC_C23_C24_B                                    :TINPUT_CSC_C23_C24_B;                              // 0x46AF
  INPUT_CSC_C31_C32_B                                    :TINPUT_CSC_C31_C32_B;                              // 0x46B0
  INPUT_CSC_C33_C34_B                                    :TINPUT_CSC_C33_C34_B;                              // 0x46B1
  PRESCALE_CONTROL                                       :TPRESCALE_CONTROL;                                 // 0x46B2
  PRESCALE_VALUES_R                                      :TPRESCALE_VALUES_R;                                // 0x46B3
  PRESCALE_VALUES_G                                      :TPRESCALE_VALUES_G;                                // 0x46B4
  PRESCALE_VALUES_B                                      :TPRESCALE_VALUES_B;                                // 0x46B5
  COL_MAN_OUTPUT_CSC_CONTROL                             :TCOL_MAN_OUTPUT_CSC_CONTROL;                       // 0x46B6
  OUTPUT_CSC_C11_C12_A                                   :TOUTPUT_CSC_C11_C12_A;                             // 0x46B7
  OUTPUT_CSC_C13_C14_A                                   :TOUTPUT_CSC_C13_C14_A;                             // 0x46B8
  OUTPUT_CSC_C21_C22_A                                   :TOUTPUT_CSC_C21_C22_A;                             // 0x46B9
  OUTPUT_CSC_C23_C24_A                                   :TOUTPUT_CSC_C23_C24_A;                             // 0x46BA
  OUTPUT_CSC_C31_C32_A                                   :TOUTPUT_CSC_C31_C32_A;                             // 0x46BB
  OUTPUT_CSC_C33_C34_A                                   :TOUTPUT_CSC_C33_C34_A;                             // 0x46BC
  OUTPUT_CSC_C11_C12_B                                   :TOUTPUT_CSC_C11_C12_B;                             // 0x46BD
  OUTPUT_CSC_C13_C14_B                                   :TOUTPUT_CSC_C13_C14_B;                             // 0x46BE
  OUTPUT_CSC_C21_C22_B                                   :TOUTPUT_CSC_C21_C22_B;                             // 0x46BF
  OUTPUT_CSC_C23_C24_B                                   :TOUTPUT_CSC_C23_C24_B;                             // 0x46C0
  OUTPUT_CSC_C31_C32_B                                   :TOUTPUT_CSC_C31_C32_B;                             // 0x46C1
  OUTPUT_CSC_C33_C34_B                                   :TOUTPUT_CSC_C33_C34_B;                             // 0x46C2
  DENORM_CLAMP_CONTROL                                   :TDENORM_CLAMP_CONTROL;                             // 0x46C3
  DENORM_CLAMP_RANGE_R_CR                                :TDENORM_CLAMP_RANGE_R_CR;                          // 0x46C4
  DENORM_CLAMP_RANGE_G_Y                                 :TDENORM_CLAMP_RANGE_G_Y;                           // 0x46C5
  DENORM_CLAMP_RANGE_B_CB                                :TDENORM_CLAMP_RANGE_B_CB;                          // 0x46C6
  COL_MAN_FP_CONVERTED_FIELD                             :TCOL_MAN_FP_CONVERTED_FIELD;                       // 0x46C7
  GAMMA_CORR_CONTROL                                     :TGAMMA_CORR_CONTROL;                               // 0x46C8
  GAMMA_CORR_LUT_INDEX                                   :TGAMMA_CORR_LUT_INDEX;                             // 0x46C9
  GAMMA_CORR_LUT_DATA                                    :TGAMMA_CORR_LUT_DATA;                              // 0x46CA
  GAMMA_CORR_LUT_WRITE_EN_MASK                           :TGAMMA_CORR_LUT_WRITE_EN_MASK;                     // 0x46CB
  GAMMA_CORR_CNTLA_START_CNTL                            :TGAMMA_CORR_CNTLA_START_CNTL;                      // 0x46CC
  GAMMA_CORR_CNTLA_SLOPE_CNTL                            :TGAMMA_CORR_CNTLA_SLOPE_CNTL;                      // 0x46CD
  GAMMA_CORR_CNTLA_END_CNTL1                             :TGAMMA_CORR_CNTLA_END_CNTL1;                       // 0x46CE
  GAMMA_CORR_CNTLA_END_CNTL2                             :TGAMMA_CORR_CNTLA_END_CNTL2;                       // 0x46CF
  GAMMA_CORR_CNTLA_REGION_0_1                            :TGAMMA_CORR_CNTLA_REGION_0_1;                      // 0x46D0
  GAMMA_CORR_CNTLA_REGION_2_3                            :TGAMMA_CORR_CNTLA_REGION_2_3;                      // 0x46D1
  GAMMA_CORR_CNTLA_REGION_4_5                            :TGAMMA_CORR_CNTLA_REGION_4_5;                      // 0x46D2
  GAMMA_CORR_CNTLA_REGION_6_7                            :TGAMMA_CORR_CNTLA_REGION_6_7;                      // 0x46D3
  GAMMA_CORR_CNTLA_REGION_8_9                            :TGAMMA_CORR_CNTLA_REGION_8_9;                      // 0x46D4
  GAMMA_CORR_CNTLA_REGION_10_11                          :TGAMMA_CORR_CNTLA_REGION_10_11;                    // 0x46D5
  GAMMA_CORR_CNTLA_REGION_12_13                          :TGAMMA_CORR_CNTLA_REGION_12_13;                    // 0x46D6
  GAMMA_CORR_CNTLA_REGION_14_15                          :TGAMMA_CORR_CNTLA_REGION_14_15;                    // 0x46D7
  GAMMA_CORR_CNTLB_START_CNTL                            :TGAMMA_CORR_CNTLB_START_CNTL;                      // 0x46D8
  GAMMA_CORR_CNTLB_SLOPE_CNTL                            :TGAMMA_CORR_CNTLB_SLOPE_CNTL;                      // 0x46D9
  GAMMA_CORR_CNTLB_END_CNTL1                             :TGAMMA_CORR_CNTLB_END_CNTL1;                       // 0x46DA
  GAMMA_CORR_CNTLB_END_CNTL2                             :TGAMMA_CORR_CNTLB_END_CNTL2;                       // 0x46DB
  GAMMA_CORR_CNTLB_REGION_0_1                            :TGAMMA_CORR_CNTLB_REGION_0_1;                      // 0x46DC
  GAMMA_CORR_CNTLB_REGION_2_3                            :TGAMMA_CORR_CNTLB_REGION_2_3;                      // 0x46DD
  GAMMA_CORR_CNTLB_REGION_4_5                            :TGAMMA_CORR_CNTLB_REGION_4_5;                      // 0x46DE
  GAMMA_CORR_CNTLB_REGION_6_7                            :TGAMMA_CORR_CNTLB_REGION_6_7;                      // 0x46DF
  GAMMA_CORR_CNTLB_REGION_8_9                            :TGAMMA_CORR_CNTLB_REGION_8_9;                      // 0x46E0
  GAMMA_CORR_CNTLB_REGION_10_11                          :TGAMMA_CORR_CNTLB_REGION_10_11;                    // 0x46E1
  GAMMA_CORR_CNTLB_REGION_12_13                          :TGAMMA_CORR_CNTLB_REGION_12_13;                    // 0x46E2
  GAMMA_CORR_CNTLB_REGION_14_15                          :TGAMMA_CORR_CNTLB_REGION_14_15;                    // 0x46E3
  COL_MAN_TEST_DEBUG_INDEX                               :TCOL_MAN_TEST_DEBUG_INDEX;                         // 0x46E4
  COL_MAN_TEST_DEBUG_DATA                                :TCOL_MAN_TEST_DEBUG_DATA;                          // 0x46E5
  COL_MAN_DEBUG_CONTROL                                  :TCOL_MAN_DEBUG_CONTROL;                            // 0x46E6
  REG_46E7_46F3                                          :array[0..12] of DWORD;                             // 0x46E7
  DCFEV_CLOCK_CONTROL                                    :TDCFEV_CLOCK_CONTROL;                              // 0x46F4
  DCFEV_SOFT_RESET                                       :TDCFEV_SOFT_RESET;                                 // 0x46F5
  DCFEV_DMIFV_CLOCK_CONTROL                              :TDCFEV_DMIFV_CLOCK_CONTROL;                        // 0x46F6
  DCFEV_DBG_CONFIG                                       :TDCFEV_DBG_CONFIG;                                 // 0x46F7
  DCFEV_DMIFV_MEM_PWR_CTRL                               :TDCFEV_DMIFV_MEM_PWR_CTRL;                         // 0x46F8
  DCFEV_DMIFV_MEM_PWR_STATUS                             :TDCFEV_DMIFV_MEM_PWR_STATUS;                       // 0x46F9
  REG_46FA_4723                                          :array[0..41] of DWORD;                             // 0x46FA
  DC_PERFMON11_PERFCOUNTER_CNTL                          :DWORD;                                             // 0x4724
  DC_PERFMON11_PERFCOUNTER_STATE                         :DWORD;                                             // 0x4725
  DC_PERFMON11_PERFMON_CVALUE_INT_MISC                   :DWORD;                                             // 0x4726
  DC_PERFMON11_PERFMON_CNTL                              :DWORD;                                             // 0x4727
  DC_PERFMON11_PERFMON_CVALUE_LOW                        :DWORD;                                             // 0x4728
  DC_PERFMON11_PERFMON_HI                                :DWORD;                                             // 0x4729
  DC_PERFMON11_PERFMON_LOW                               :DWORD;                                             // 0x472A
  DC_PERFMON11_PERFMON_TEST_DEBUG_INDEX                  :DWORD;                                             // 0x472B
  DC_PERFMON11_PERFMON_TEST_DEBUG_DATA                   :DWORD;                                             // 0x472C
  REG_472D                                               :DWORD;                                             // 0x472D
  DC_PERFMON11_PERFMON_CNTL2                             :DWORD;                                             // 0x472E
  REG_472F                                               :DWORD;                                             // 0x472F
  DMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1                 :DWORD;                                             // 0x4730
  DMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2                 :DWORD;                                             // 0x4731
  DMIF_PG6_DPG_WATERMARK_MASK_CONTROL                    :DWORD;                                             // 0x4732
  DMIF_PG6_DPG_PIPE_URGENCY_CONTROL                      :DWORD;                                             // 0x4733
  DMIF_PG6_DPG_PIPE_DPM_CONTROL                          :DWORD;                                             // 0x4734
  DMIF_PG6_DPG_PIPE_STUTTER_CONTROL                      :DWORD;                                             // 0x4735
  DMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL             :DWORD;                                             // 0x4736
  DMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH             :DWORD;                                             // 0x4737
  DMIF_PG6_DPG_TEST_DEBUG_INDEX                          :DWORD;                                             // 0x4738
  DMIF_PG6_DPG_TEST_DEBUG_DATA                           :DWORD;                                             // 0x4739
  DMIF_PG6_DPG_REPEATER_PROGRAM                          :DWORD;                                             // 0x473A
  DMIF_PG6_DPG_HW_DEBUG_A                                :DWORD;                                             // 0x473B
  DMIF_PG6_DPG_HW_DEBUG_B                                :DWORD;                                             // 0x473C
  DMIF_PG6_DPG_HW_DEBUG_11                               :DWORD;                                             // 0x473D
  REG_473E_476C                                          :array[0..46] of DWORD;                             // 0x473E
  BLND6_BLND_CONTROL                                     :DWORD;                                             // 0x476D
  BLND6_SM_CONTROL2                                      :DWORD;                                             // 0x476E
  BLND6_BLND_CONTROL2                                    :DWORD;                                             // 0x476F
  BLND6_BLND_UPDATE                                      :DWORD;                                             // 0x4770
  BLND6_BLND_UNDERFLOW_INTERRUPT                         :DWORD;                                             // 0x4771
  REG_4772                                               :DWORD;                                             // 0x4772
  BLND6_BLND_V_UPDATE_LOCK                               :DWORD;                                             // 0x4773
  BLND6_BLND_DEBUG                                       :DWORD;                                             // 0x4774
  BLND6_BLND_TEST_DEBUG_INDEX                            :DWORD;                                             // 0x4775
  BLND6_BLND_TEST_DEBUG_DATA                             :DWORD;                                             // 0x4776
  BLND6_BLND_REG_UPDATE_STATUS                           :DWORD;                                             // 0x4777
  CRTC6_CRTC_3D_STRUCTURE_CONTROL                        :DWORD;                                             // 0x4778
  CRTC6_CRTC_GSL_VSYNC_GAP                               :DWORD;                                             // 0x4779
  CRTC6_CRTC_GSL_WINDOW                                  :DWORD;                                             // 0x477A
  CRTC6_CRTC_GSL_CONTROL                                 :DWORD;                                             // 0x477B
  CRTC6_CRTC_DCFE_CLOCK_CONTROL                          :DWORD;                                             // 0x477C
  CRTC6_CRTC_H_BLANK_EARLY_NUM                           :DWORD;                                             // 0x477D
  CRTC6_DCFE_DBG_SEL                                     :DWORD;                                             // 0x477E
  CRTC6_DCFE_MEM_PWR_CTRL                                :DWORD;                                             // 0x477F
  CRTC6_CRTC_H_TOTAL                                     :DWORD;                                             // 0x4780
  CRTC6_CRTC_H_BLANK_START_END                           :DWORD;                                             // 0x4781
  CRTC6_CRTC_H_SYNC_A                                    :DWORD;                                             // 0x4782
  CRTC6_CRTC_H_SYNC_A_CNTL                               :DWORD;                                             // 0x4783
  CRTC6_CRTC_H_SYNC_B                                    :DWORD;                                             // 0x4784
  CRTC6_CRTC_H_SYNC_B_CNTL                               :DWORD;                                             // 0x4785
  CRTC6_CRTC_VBI_END                                     :DWORD;                                             // 0x4786
  CRTC6_CRTC_V_TOTAL                                     :DWORD;                                             // 0x4787
  CRTC6_CRTC_V_TOTAL_MIN                                 :DWORD;                                             // 0x4788
  CRTC6_CRTC_V_TOTAL_MAX                                 :DWORD;                                             // 0x4789
  CRTC6_CRTC_V_TOTAL_CONTROL                             :DWORD;                                             // 0x478A
  CRTC6_CRTC_V_TOTAL_INT_STATUS                          :DWORD;                                             // 0x478B
  CRTC6_CRTC_VSYNC_NOM_INT_STATUS                        :DWORD;                                             // 0x478C
  CRTC6_CRTC_V_BLANK_START_END                           :DWORD;                                             // 0x478D
  CRTC6_CRTC_V_SYNC_A                                    :DWORD;                                             // 0x478E
  CRTC6_CRTC_V_SYNC_A_CNTL                               :DWORD;                                             // 0x478F
  CRTC6_CRTC_V_SYNC_B                                    :DWORD;                                             // 0x4790
  CRTC6_CRTC_V_SYNC_B_CNTL                               :DWORD;                                             // 0x4791
  CRTC6_CRTC_DTMTEST_CNTL                                :DWORD;                                             // 0x4792
  CRTC6_CRTC_DTMTEST_STATUS_POSITION                     :DWORD;                                             // 0x4793
  CRTC6_CRTC_TRIGA_CNTL                                  :DWORD;                                             // 0x4794
  CRTC6_CRTC_TRIGA_MANUAL_TRIG                           :DWORD;                                             // 0x4795
  CRTC6_CRTC_TRIGB_CNTL                                  :DWORD;                                             // 0x4796
  CRTC6_CRTC_TRIGB_MANUAL_TRIG                           :DWORD;                                             // 0x4797
  CRTC6_CRTC_FORCE_COUNT_NOW_CNTL                        :DWORD;                                             // 0x4798
  CRTC6_CRTC_FLOW_CONTROL                                :DWORD;                                             // 0x4799
  CRTC6_CRTC_STEREO_FORCE_NEXT_EYE                       :DWORD;                                             // 0x479A
  CRTC6_CRTC_AVSYNC_COUNTER                              :DWORD;                                             // 0x479B
  CRTC6_CRTC_CONTROL                                     :DWORD;                                             // 0x479C
  CRTC6_CRTC_BLANK_CONTROL                               :DWORD;                                             // 0x479D
  CRTC6_CRTC_INTERLACE_CONTROL                           :DWORD;                                             // 0x479E
  CRTC6_CRTC_INTERLACE_STATUS                            :DWORD;                                             // 0x479F
  CRTC6_CRTC_FIELD_INDICATION_CONTROL                    :DWORD;                                             // 0x47A0
  CRTC6_CRTC_PIXEL_DATA_READBACK0                        :DWORD;                                             // 0x47A1
  CRTC6_CRTC_PIXEL_DATA_READBACK1                        :DWORD;                                             // 0x47A2
  CRTC6_CRTC_STATUS                                      :DWORD;                                             // 0x47A3
  CRTC6_CRTC_STATUS_POSITION                             :DWORD;                                             // 0x47A4
  CRTC6_CRTC_NOM_VERT_POSITION                           :DWORD;                                             // 0x47A5
  CRTC6_CRTC_STATUS_FRAME_COUNT                          :DWORD;                                             // 0x47A6
  CRTC6_CRTC_STATUS_VF_COUNT                             :DWORD;                                             // 0x47A7
  CRTC6_CRTC_STATUS_HV_COUNT                             :DWORD;                                             // 0x47A8
  CRTC6_CRTC_COUNT_CONTROL                               :DWORD;                                             // 0x47A9
  CRTC6_CRTC_COUNT_RESET                                 :DWORD;                                             // 0x47AA
  CRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                :DWORD;                                             // 0x47AB
  CRTC6_CRTC_VERT_SYNC_CONTROL                           :DWORD;                                             // 0x47AC
  CRTC6_CRTC_STEREO_STATUS                               :DWORD;                                             // 0x47AD
  CRTC6_CRTC_STEREO_CONTROL                              :DWORD;                                             // 0x47AE
  CRTC6_CRTC_SNAPSHOT_STATUS                             :DWORD;                                             // 0x47AF
  CRTC6_CRTC_SNAPSHOT_CONTROL                            :DWORD;                                             // 0x47B0
  CRTC6_CRTC_SNAPSHOT_POSITION                           :DWORD;                                             // 0x47B1
  CRTC6_CRTC_SNAPSHOT_FRAME                              :DWORD;                                             // 0x47B2
  CRTC6_CRTC_START_LINE_CONTROL                          :DWORD;                                             // 0x47B3
  CRTC6_CRTC_INTERRUPT_CONTROL                           :DWORD;                                             // 0x47B4
  CRTC6_CRTC_UPDATE_LOCK                                 :DWORD;                                             // 0x47B5
  CRTC6_CRTC_DOUBLE_BUFFER_CONTROL                       :DWORD;                                             // 0x47B6
  CRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE                  :DWORD;                                             // 0x47B7
  CRTC6_DCFE_MEM_PWR_CTRL2                               :DWORD;                                             // 0x47B8
  CRTC6_DCFE_MEM_PWR_STATUS                              :DWORD;                                             // 0x47B9
  CRTC6_CRTC_TEST_PATTERN_CONTROL                        :DWORD;                                             // 0x47BA
  CRTC6_CRTC_TEST_PATTERN_PARAMETERS                     :DWORD;                                             // 0x47BB
  CRTC6_CRTC_TEST_PATTERN_COLOR                          :DWORD;                                             // 0x47BC
  CRTC6_MASTER_UPDATE_LOCK                               :DWORD;                                             // 0x47BD
  CRTC6_MASTER_UPDATE_MODE                               :DWORD;                                             // 0x47BE
  CRTC6_CRTC_MVP_INBAND_CNTL_INSERT                      :DWORD;                                             // 0x47BF
  CRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                :DWORD;                                             // 0x47C0
  CRTC6_CRTC_MVP_STATUS                                  :DWORD;                                             // 0x47C1
  CRTC6_CRTC_MASTER_EN                                   :DWORD;                                             // 0x47C2
  CRTC6_CRTC_ALLOW_STOP_OFF_V_CNT                        :DWORD;                                             // 0x47C3
  CRTC6_CRTC_V_UPDATE_INT_STATUS                         :DWORD;                                             // 0x47C4
  REG_47C5                                               :DWORD;                                             // 0x47C5
  CRTC6_CRTC_TEST_DEBUG_INDEX                            :DWORD;                                             // 0x47C6
  CRTC6_CRTC_TEST_DEBUG_DATA                             :DWORD;                                             // 0x47C7
  CRTC6_CRTC_OVERSCAN_COLOR                              :DWORD;                                             // 0x47C8
  CRTC6_CRTC_OVERSCAN_COLOR_EXT                          :DWORD;                                             // 0x47C9
  CRTC6_CRTC_BLANK_DATA_COLOR                            :DWORD;                                             // 0x47CA
  CRTC6_CRTC_BLANK_DATA_COLOR_EXT                        :DWORD;                                             // 0x47CB
  CRTC6_CRTC_BLACK_COLOR                                 :DWORD;                                             // 0x47CC
  CRTC6_CRTC_BLACK_COLOR_EXT                             :DWORD;                                             // 0x47CD
  CRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION                :DWORD;                                             // 0x47CE
  CRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL                 :DWORD;                                             // 0x47CF
  CRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION                :DWORD;                                             // 0x47D0
  CRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL                 :DWORD;                                             // 0x47D1
  CRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION                :DWORD;                                             // 0x47D2
  CRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL                 :DWORD;                                             // 0x47D3
  CRTC6_CRTC_CRC_CNTL                                    :DWORD;                                             // 0x47D4
  CRTC6_CRTC_CRC0_WINDOWA_X_CONTROL                      :DWORD;                                             // 0x47D5
  CRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL                      :DWORD;                                             // 0x47D6
  CRTC6_CRTC_CRC0_WINDOWB_X_CONTROL                      :DWORD;                                             // 0x47D7
  CRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL                      :DWORD;                                             // 0x47D8
  CRTC6_CRTC_CRC0_DATA_RG                                :DWORD;                                             // 0x47D9
  CRTC6_CRTC_CRC0_DATA_B                                 :DWORD;                                             // 0x47DA
  CRTC6_CRTC_CRC1_WINDOWA_X_CONTROL                      :DWORD;                                             // 0x47DB
  CRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL                      :DWORD;                                             // 0x47DC
  CRTC6_CRTC_CRC1_WINDOWB_X_CONTROL                      :DWORD;                                             // 0x47DD
  CRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL                      :DWORD;                                             // 0x47DE
  CRTC6_CRTC_CRC1_DATA_RG                                :DWORD;                                             // 0x47DF
  CRTC6_CRTC_CRC1_DATA_B                                 :DWORD;                                             // 0x47E0
  CRTC6_CRTC_EXT_TIMING_SYNC_CONTROL                     :DWORD;                                             // 0x47E1
  CRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START                :DWORD;                                             // 0x47E2
  CRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END                  :DWORD;                                             // 0x47E3
  CRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL      :DWORD;                                             // 0x47E4
  CRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL           :DWORD;                                             // 0x47E5
  CRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL    :DWORD;                                             // 0x47E6
  CRTC6_CRTC_STATIC_SCREEN_CONTROL                       :DWORD;                                             // 0x47E7
  REG_47E8_47FF                                          :array[0..23] of DWORD;                             // 0x47E8
  DC_GENERICA                                            :TDC_GENERICA;                                      // 0x4800
  DC_GENERICB                                            :TDC_GENERICB;                                      // 0x4801
  DC_PAD_EXTERN_SIG                                      :TDC_PAD_EXTERN_SIG;                                // 0x4802
  DC_REF_CLK_CNTL                                        :TDC_REF_CLK_CNTL;                                  // 0x4803
  DC_GPIO_DEBUG                                          :TDC_GPIO_DEBUG;                                    // 0x4804
  UNIPHYA_LINK_CNTL                                      :TUNIPHYA_LINK_CNTL;                                // 0x4805
  UNIPHYA_CHANNEL_XBAR_CNTL                              :TUNIPHYA_CHANNEL_XBAR_CNTL;                        // 0x4806
  UNIPHYB_LINK_CNTL                                      :TUNIPHYB_LINK_CNTL;                                // 0x4807
  UNIPHYB_CHANNEL_XBAR_CNTL                              :TUNIPHYB_CHANNEL_XBAR_CNTL;                        // 0x4808
  UNIPHYC_LINK_CNTL                                      :TUNIPHYC_LINK_CNTL;                                // 0x4809
  UNIPHYC_CHANNEL_XBAR_CNTL                              :TUNIPHYC_CHANNEL_XBAR_CNTL;                        // 0x480A
  UNIPHYD_LINK_CNTL                                      :TUNIPHYD_LINK_CNTL;                                // 0x480B
  UNIPHYD_CHANNEL_XBAR_CNTL                              :TUNIPHYD_CHANNEL_XBAR_CNTL;                        // 0x480C
  UNIPHYE_LINK_CNTL                                      :TUNIPHYE_LINK_CNTL;                                // 0x480D
  UNIPHYE_CHANNEL_XBAR_CNTL                              :TUNIPHYE_CHANNEL_XBAR_CNTL;                        // 0x480E
  UNIPHYF_LINK_CNTL                                      :TUNIPHYF_LINK_CNTL;                                // 0x480F
  UNIPHYF_CHANNEL_XBAR_CNTL                              :TUNIPHYF_CHANNEL_XBAR_CNTL;                        // 0x4810
  UNIPHYG_LINK_CNTL                                      :TUNIPHYG_LINK_CNTL;                                // 0x4811
  UNIPHYG_CHANNEL_XBAR_CNTL                              :TUNIPHYG_CHANNEL_XBAR_CNTL;                        // 0x4812
  DIG4_HDMI_GENERIC_PACKET_CONTROL                       :DWORD;                                             // 0x4813
  REG_4814_4815                                          :array[0..1] of DWORD;                              // 0x4814
  DCIO_WRCMD_DELAY                                       :TDCIO_WRCMD_DELAY;                                 // 0x4816
  REG_4817                                               :DWORD;                                             // 0x4817
  DC_PINSTRAPS                                           :TDC_PINSTRAPS;                                     // 0x4818
  REG_4819                                               :DWORD;                                             // 0x4819
  DC_DVODATA_CONFIG                                      :TDC_DVODATA_CONFIG;                                // 0x481A
  LVTMA_PWRSEQ_CNTL                                      :TLVTMA_PWRSEQ_CNTL;                                // 0x481B
  LVTMA_PWRSEQ_STATE                                     :TLVTMA_PWRSEQ_STATE;                               // 0x481C
  LVTMA_PWRSEQ_REF_DIV                                   :TLVTMA_PWRSEQ_REF_DIV;                             // 0x481D
  LVTMA_PWRSEQ_DELAY1                                    :TLVTMA_PWRSEQ_DELAY1;                              // 0x481E
  LVTMA_PWRSEQ_DELAY2                                    :TLVTMA_PWRSEQ_DELAY2;                              // 0x481F
  BL_PWM_CNTL                                            :TBL_PWM_CNTL;                                      // 0x4820
  BL_PWM_CNTL2                                           :TBL_PWM_CNTL2;                                     // 0x4821
  BL_PWM_PERIOD_CNTL                                     :TBL_PWM_PERIOD_CNTL;                               // 0x4822
  BL_PWM_GRP1_REG_LOCK                                   :TBL_PWM_GRP1_REG_LOCK;                             // 0x4823
  DCIO_GSL_GENLK_PAD_CNTL                                :TDCIO_GSL_GENLK_PAD_CNTL;                          // 0x4824
  DCIO_GSL_SWAPLOCK_PAD_CNTL                             :TDCIO_GSL_SWAPLOCK_PAD_CNTL;                       // 0x4825
  DCIO_GSL0_CNTL                                         :TDCIO_GSL0_CNTL;                                   // 0x4826
  DCIO_GSL1_CNTL                                         :TDCIO_GSL1_CNTL;                                   // 0x4827
  DCIO_GSL2_CNTL                                         :TDCIO_GSL2_CNTL;                                   // 0x4828
  DC_GPU_TIMER_START_POSITION_V_UPDATE                   :TDC_GPU_TIMER_START_POSITION_V_UPDATE;             // 0x4829
  DC_GPU_TIMER_START_POSITION_P_FLIP                     :TDC_GPU_TIMER_START_POSITION_P_FLIP;               // 0x482A
  DC_GPU_TIMER_READ                                      :TDC_GPU_TIMER_READ;                                // 0x482B
  DC_GPU_TIMER_READ_CNTL                                 :TDC_GPU_TIMER_READ_CNTL;                           // 0x482C
  DCIO_CLOCK_CNTL                                        :TDCIO_CLOCK_CNTL;                                  // 0x482D
  REG_482E                                               :DWORD;                                             // 0x482E
  DCIO_DEBUG                                             :TDCIO_DEBUG;                                       // 0x482F
  DCO_DCFE_EXT_VSYNC_CNTL                                :TDCO_DCFE_EXT_VSYNC_CNTL;                          // 0x4830
  DCIO_TEST_DEBUG_INDEX                                  :TDCIO_TEST_DEBUG_INDEX;                            // 0x4831
  DCIO_TEST_DEBUG_DATA                                   :TDCIO_TEST_DEBUG_DATA;                             // 0x4832
  REG_4833                                               :DWORD;                                             // 0x4833
  DBG_OUT_CNTL                                           :TDBG_OUT_CNTL;                                     // 0x4834
  DCIO_DEBUG_CONFIG                                      :TDCIO_DEBUG_CONFIG;                                // 0x4835
  DCIO_SOFT_RESET                                        :TDCIO_SOFT_RESET;                                  // 0x4836
  DCIO_DPHY_SEL                                          :TDCIO_DPHY_SEL;                                    // 0x4837
  UNIPHY_IMPCAL_LINKA                                    :TUNIPHY_IMPCAL_LINKA;                              // 0x4838
  UNIPHY_IMPCAL_LINKB                                    :TUNIPHY_IMPCAL_LINKB;                              // 0x4839
  UNIPHY_IMPCAL_PERIOD                                   :TUNIPHY_IMPCAL_PERIOD;                             // 0x483A
  AUXP_IMPCAL                                            :TAUXP_IMPCAL;                                      // 0x483B
  AUXN_IMPCAL                                            :TAUXN_IMPCAL;                                      // 0x483C
  DCIO_IMPCAL_CNTL                                       :TDCIO_IMPCAL_CNTL;                                 // 0x483D
  UNIPHY_IMPCAL_PSW_AB                                   :TUNIPHY_IMPCAL_PSW_AB;                             // 0x483E
  UNIPHY_IMPCAL_LINKC                                    :TUNIPHY_IMPCAL_LINKC;                              // 0x483F
  UNIPHY_IMPCAL_LINKD                                    :TUNIPHY_IMPCAL_LINKD;                              // 0x4840
  DCIO_IMPCAL_CNTL_CD                                    :TDCIO_IMPCAL_CNTL_CD;                              // 0x4841
  UNIPHY_IMPCAL_PSW_CD                                   :TUNIPHY_IMPCAL_PSW_CD;                             // 0x4842
  UNIPHY_IMPCAL_LINKE                                    :TUNIPHY_IMPCAL_LINKE;                              // 0x4843
  UNIPHY_IMPCAL_LINKF                                    :TUNIPHY_IMPCAL_LINKF;                              // 0x4844
  DCIO_IMPCAL_CNTL_EF                                    :TDCIO_IMPCAL_CNTL_EF;                              // 0x4845
  UNIPHY_IMPCAL_PSW_EF                                   :TUNIPHY_IMPCAL_PSW_EF;                             // 0x4846
  REG_4847_485F                                          :array[0..24] of DWORD;                             // 0x4847
  DC_GPIO_GENERIC_MASK                                   :TDC_GPIO_GENERIC_MASK;                             // 0x4860
  DC_GPIO_GENERIC_A                                      :TDC_GPIO_GENERIC_A;                                // 0x4861
  DC_GPIO_GENERIC_EN                                     :TDC_GPIO_GENERIC_EN;                               // 0x4862
  DC_GPIO_GENERIC_Y                                      :TDC_GPIO_GENERIC_Y;                                // 0x4863
  DC_GPIO_DVODATA_MASK                                   :TDC_GPIO_DVODATA_MASK;                             // 0x4864
  DC_GPIO_DVODATA_A                                      :TDC_GPIO_DVODATA_A;                                // 0x4865
  DC_GPIO_DVODATA_EN                                     :TDC_GPIO_DVODATA_EN;                               // 0x4866
  DC_GPIO_DVODATA_Y                                      :TDC_GPIO_DVODATA_Y;                                // 0x4867
  DC_GPIO_DDC1_MASK                                      :TDC_GPIO_DDC1_MASK;                                // 0x4868
  DC_GPIO_DDC1_A                                         :TDC_GPIO_DDC1_A;                                   // 0x4869
  DC_GPIO_DDC1_EN                                        :TDC_GPIO_DDC1_EN;                                  // 0x486A
  DC_GPIO_DDC1_Y                                         :TDC_GPIO_DDC1_Y;                                   // 0x486B
  DC_GPIO_DDC2_MASK                                      :TDC_GPIO_DDC2_MASK;                                // 0x486C
  DC_GPIO_DDC2_A                                         :TDC_GPIO_DDC2_A;                                   // 0x486D
  DC_GPIO_DDC2_EN                                        :TDC_GPIO_DDC2_EN;                                  // 0x486E
  DC_GPIO_DDC2_Y                                         :TDC_GPIO_DDC2_Y;                                   // 0x486F
  DC_GPIO_DDC3_MASK                                      :TDC_GPIO_DDC3_MASK;                                // 0x4870
  DC_GPIO_DDC3_A                                         :TDC_GPIO_DDC3_A;                                   // 0x4871
  DC_GPIO_DDC3_EN                                        :TDC_GPIO_DDC3_EN;                                  // 0x4872
  DC_GPIO_DDC3_Y                                         :TDC_GPIO_DDC3_Y;                                   // 0x4873
  DC_GPIO_DDC4_MASK                                      :TDC_GPIO_DDC4_MASK;                                // 0x4874
  DC_GPIO_DDC4_A                                         :TDC_GPIO_DDC4_A;                                   // 0x4875
  DC_GPIO_DDC4_EN                                        :TDC_GPIO_DDC4_EN;                                  // 0x4876
  DC_GPIO_DDC4_Y                                         :TDC_GPIO_DDC4_Y;                                   // 0x4877
  DC_GPIO_DDC5_MASK                                      :TDC_GPIO_DDC5_MASK;                                // 0x4878
  DC_GPIO_DDC5_A                                         :TDC_GPIO_DDC5_A;                                   // 0x4879
  DC_GPIO_DDC5_EN                                        :TDC_GPIO_DDC5_EN;                                  // 0x487A
  DC_GPIO_DDC5_Y                                         :TDC_GPIO_DDC5_Y;                                   // 0x487B
  DC_GPIO_DDC6_MASK                                      :TDC_GPIO_DDC6_MASK;                                // 0x487C
  DC_GPIO_DDC6_A                                         :TDC_GPIO_DDC6_A;                                   // 0x487D
  DC_GPIO_DDC6_EN                                        :TDC_GPIO_DDC6_EN;                                  // 0x487E
  DC_GPIO_DDC6_Y                                         :TDC_GPIO_DDC6_Y;                                   // 0x487F
  DC_GPIO_DDCVGA_MASK                                    :TDC_GPIO_DDCVGA_MASK;                              // 0x4880
  DC_GPIO_DDCVGA_A                                       :TDC_GPIO_DDCVGA_A;                                 // 0x4881
  DC_GPIO_DDCVGA_EN                                      :TDC_GPIO_DDCVGA_EN;                                // 0x4882
  DC_GPIO_DDCVGA_Y                                       :TDC_GPIO_DDCVGA_Y;                                 // 0x4883
  DC_GPIO_SYNCA_MASK                                     :TDC_GPIO_SYNCA_MASK;                               // 0x4884
  DC_GPIO_SYNCA_A                                        :TDC_GPIO_SYNCA_A;                                  // 0x4885
  DC_GPIO_SYNCA_EN                                       :TDC_GPIO_SYNCA_EN;                                 // 0x4886
  DC_GPIO_SYNCA_Y                                        :TDC_GPIO_SYNCA_Y;                                  // 0x4887
  DC_GPIO_GENLK_MASK                                     :TDC_GPIO_GENLK_MASK;                               // 0x4888
  DC_GPIO_GENLK_A                                        :TDC_GPIO_GENLK_A;                                  // 0x4889
  DC_GPIO_GENLK_EN                                       :TDC_GPIO_GENLK_EN;                                 // 0x488A
  DC_GPIO_GENLK_Y                                        :TDC_GPIO_GENLK_Y;                                  // 0x488B
  DC_GPIO_HPD_MASK                                       :TDC_GPIO_HPD_MASK;                                 // 0x488C
  DC_GPIO_HPD_A                                          :TDC_GPIO_HPD_A;                                    // 0x488D
  DC_GPIO_HPD_EN                                         :TDC_GPIO_HPD_EN;                                   // 0x488E
  DC_GPIO_HPD_Y                                          :TDC_GPIO_HPD_Y;                                    // 0x488F
  DC_GPIO_PWRSEQ_MASK                                    :TDC_GPIO_PWRSEQ_MASK;                              // 0x4890
  DC_GPIO_PWRSEQ_A                                       :TDC_GPIO_PWRSEQ_A;                                 // 0x4891
  DC_GPIO_PWRSEQ_EN                                      :TDC_GPIO_PWRSEQ_EN;                                // 0x4892
  DC_GPIO_PWRSEQ_Y                                       :TDC_GPIO_PWRSEQ_Y;                                 // 0x4893
  DC_GPIO_PAD_STRENGTH_1                                 :TDC_GPIO_PAD_STRENGTH_1;                           // 0x4894
  DC_GPIO_PAD_STRENGTH_2                                 :TDC_GPIO_PAD_STRENGTH_2;                           // 0x4895
  REG_4896                                               :DWORD;                                             // 0x4896
  PHY_AUX_CNTL                                           :TPHY_AUX_CNTL;                                     // 0x4897
  DC_GPIO_I2CPAD_MASK                                    :TDC_GPIO_I2CPAD_MASK;                              // 0x4898
  DC_GPIO_I2CPAD_A                                       :TDC_GPIO_I2CPAD_A;                                 // 0x4899
  DC_GPIO_I2CPAD_EN                                      :TDC_GPIO_I2CPAD_EN;                                // 0x489A
  DC_GPIO_I2CPAD_Y                                       :TDC_GPIO_I2CPAD_Y;                                 // 0x489B
  DC_GPIO_I2CPAD_STRENGTH                                :TDC_GPIO_I2CPAD_STRENGTH;                          // 0x489C
  DVO_STRENGTH_CONTROL                                   :TDVO_STRENGTH_CONTROL;                             // 0x489D
  DVO_VREF_CONTROL                                       :TDVO_VREF_CONTROL;                                 // 0x489E
  DVO_SKEW_ADJUST                                        :TDVO_SKEW_ADJUST;                                  // 0x489F
  REG_48A0_48B7                                          :array[0..23] of DWORD;                             // 0x48A0
  DAC_MACRO_CNTL_RESERVED0                               :TDAC_MACRO_CNTL_RESERVED0;                         // 0x48B8
  BPHYC_DAC_MACRO_CNTL                                   :TBPHYC_DAC_MACRO_CNTL;                             // 0x48B9
  BPHYC_DAC_AUTO_CALIB_CONTROL                           :TBPHYC_DAC_AUTO_CALIB_CONTROL;                     // 0x48BA
  DAC_MACRO_CNTL_RESERVED3                               :TDAC_MACRO_CNTL_RESERVED3;                         // 0x48BB
  REG_48BC_48BF                                          :array[0..3] of DWORD;                              // 0x48BC
  BPHYC_UNIPHY0_UNIPHY_TX_CONTROL1                       :DWORD;                                             // 0x48C0
  BPHYC_UNIPHY0_UNIPHY_TX_CONTROL2                       :DWORD;                                             // 0x48C1
  BPHYC_UNIPHY0_UNIPHY_TX_CONTROL3                       :DWORD;                                             // 0x48C2
  BPHYC_UNIPHY0_UNIPHY_TX_CONTROL4                       :DWORD;                                             // 0x48C3
  BPHYC_UNIPHY0_UNIPHY_POWER_CONTROL                     :DWORD;                                             // 0x48C4
  BPHYC_UNIPHY0_UNIPHY_PLL_FBDIV                         :DWORD;                                             // 0x48C5
  BPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1                      :DWORD;                                             // 0x48C6
  BPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2                      :DWORD;                                             // 0x48C7
  BPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE                  :DWORD;                                             // 0x48C8
  BPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL                       :DWORD;                                             // 0x48C9
  BPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION              :DWORD;                                             // 0x48CA
  BPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT                   :DWORD;                                             // 0x48CB
  BPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL                     :DWORD;                                             // 0x48CC
  BPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2                  :DWORD;                                             // 0x48CD
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14              :DWORD;                                             // 0x48CE
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15              :DWORD;                                             // 0x48CF
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16              :DWORD;                                             // 0x48D0
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17              :DWORD;                                             // 0x48D1
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18              :DWORD;                                             // 0x48D2
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19              :DWORD;                                             // 0x48D3
  BPHYC_UNIPHY0_UNIPHY_TPG_CONTROL                       :DWORD;                                             // 0x48D4
  BPHYC_UNIPHY0_UNIPHY_TPG_SEED                          :DWORD;                                             // 0x48D5
  BPHYC_UNIPHY0_UNIPHY_DEBUG                             :DWORD;                                             // 0x48D6
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23              :DWORD;                                             // 0x48D7
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24              :DWORD;                                             // 0x48D8
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25              :DWORD;                                             // 0x48D9
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26              :DWORD;                                             // 0x48DA
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27              :DWORD;                                             // 0x48DB
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28              :DWORD;                                             // 0x48DC
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29              :DWORD;                                             // 0x48DD
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30              :DWORD;                                             // 0x48DE
  DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31              :DWORD;                                             // 0x48DF
  BPHYC_UNIPHY1_UNIPHY_TX_CONTROL1                       :DWORD;                                             // 0x48E0
  BPHYC_UNIPHY1_UNIPHY_TX_CONTROL2                       :DWORD;                                             // 0x48E1
  BPHYC_UNIPHY1_UNIPHY_TX_CONTROL3                       :DWORD;                                             // 0x48E2
  BPHYC_UNIPHY1_UNIPHY_TX_CONTROL4                       :DWORD;                                             // 0x48E3
  BPHYC_UNIPHY1_UNIPHY_POWER_CONTROL                     :DWORD;                                             // 0x48E4
  BPHYC_UNIPHY1_UNIPHY_PLL_FBDIV                         :DWORD;                                             // 0x48E5
  BPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1                      :DWORD;                                             // 0x48E6
  BPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2                      :DWORD;                                             // 0x48E7
  BPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE                  :DWORD;                                             // 0x48E8
  BPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL                       :DWORD;                                             // 0x48E9
  BPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION              :DWORD;                                             // 0x48EA
  BPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT                   :DWORD;                                             // 0x48EB
  BPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL                     :DWORD;                                             // 0x48EC
  BPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2                  :DWORD;                                             // 0x48ED
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14              :DWORD;                                             // 0x48EE
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15              :DWORD;                                             // 0x48EF
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16              :DWORD;                                             // 0x48F0
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17              :DWORD;                                             // 0x48F1
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18              :DWORD;                                             // 0x48F2
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19              :DWORD;                                             // 0x48F3
  BPHYC_UNIPHY1_UNIPHY_TPG_CONTROL                       :DWORD;                                             // 0x48F4
  BPHYC_UNIPHY1_UNIPHY_TPG_SEED                          :DWORD;                                             // 0x48F5
  BPHYC_UNIPHY1_UNIPHY_DEBUG                             :DWORD;                                             // 0x48F6
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23              :DWORD;                                             // 0x48F7
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24              :DWORD;                                             // 0x48F8
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25              :DWORD;                                             // 0x48F9
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26              :DWORD;                                             // 0x48FA
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27              :DWORD;                                             // 0x48FB
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28              :DWORD;                                             // 0x48FC
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29              :DWORD;                                             // 0x48FD
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30              :DWORD;                                             // 0x48FE
  DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31              :DWORD;                                             // 0x48FF
  BPHYC_UNIPHY2_UNIPHY_TX_CONTROL1                       :DWORD;                                             // 0x4900
  BPHYC_UNIPHY2_UNIPHY_TX_CONTROL2                       :DWORD;                                             // 0x4901
  BPHYC_UNIPHY2_UNIPHY_TX_CONTROL3                       :DWORD;                                             // 0x4902
  BPHYC_UNIPHY2_UNIPHY_TX_CONTROL4                       :DWORD;                                             // 0x4903
  BPHYC_UNIPHY2_UNIPHY_POWER_CONTROL                     :DWORD;                                             // 0x4904
  BPHYC_UNIPHY2_UNIPHY_PLL_FBDIV                         :DWORD;                                             // 0x4905
  BPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1                      :DWORD;                                             // 0x4906
  BPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2                      :DWORD;                                             // 0x4907
  BPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE                  :DWORD;                                             // 0x4908
  BPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL                       :DWORD;                                             // 0x4909
  BPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION              :DWORD;                                             // 0x490A
  BPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT                   :DWORD;                                             // 0x490B
  BPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL                     :DWORD;                                             // 0x490C
  BPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2                  :DWORD;                                             // 0x490D
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14              :DWORD;                                             // 0x490E
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15              :DWORD;                                             // 0x490F
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16              :DWORD;                                             // 0x4910
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17              :DWORD;                                             // 0x4911
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18              :DWORD;                                             // 0x4912
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19              :DWORD;                                             // 0x4913
  BPHYC_UNIPHY2_UNIPHY_TPG_CONTROL                       :DWORD;                                             // 0x4914
  BPHYC_UNIPHY2_UNIPHY_TPG_SEED                          :DWORD;                                             // 0x4915
  BPHYC_UNIPHY2_UNIPHY_DEBUG                             :DWORD;                                             // 0x4916
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23              :DWORD;                                             // 0x4917
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24              :DWORD;                                             // 0x4918
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25              :DWORD;                                             // 0x4919
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26              :DWORD;                                             // 0x491A
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27              :DWORD;                                             // 0x491B
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28              :DWORD;                                             // 0x491C
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29              :DWORD;                                             // 0x491D
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30              :DWORD;                                             // 0x491E
  DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31              :DWORD;                                             // 0x491F
  BPHYC_UNIPHY3_UNIPHY_TX_CONTROL1                       :DWORD;                                             // 0x4920
  BPHYC_UNIPHY3_UNIPHY_TX_CONTROL2                       :DWORD;                                             // 0x4921
  BPHYC_UNIPHY3_UNIPHY_TX_CONTROL3                       :DWORD;                                             // 0x4922
  BPHYC_UNIPHY3_UNIPHY_TX_CONTROL4                       :DWORD;                                             // 0x4923
  BPHYC_UNIPHY3_UNIPHY_POWER_CONTROL                     :DWORD;                                             // 0x4924
  BPHYC_UNIPHY3_UNIPHY_PLL_FBDIV                         :DWORD;                                             // 0x4925
  BPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1                      :DWORD;                                             // 0x4926
  BPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2                      :DWORD;                                             // 0x4927
  BPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE                  :DWORD;                                             // 0x4928
  BPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL                       :DWORD;                                             // 0x4929
  BPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION              :DWORD;                                             // 0x492A
  BPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT                   :DWORD;                                             // 0x492B
  BPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL                     :DWORD;                                             // 0x492C
  BPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2                  :DWORD;                                             // 0x492D
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14              :DWORD;                                             // 0x492E
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15              :DWORD;                                             // 0x492F
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16              :DWORD;                                             // 0x4930
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17              :DWORD;                                             // 0x4931
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18              :DWORD;                                             // 0x4932
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19              :DWORD;                                             // 0x4933
  BPHYC_UNIPHY3_UNIPHY_TPG_CONTROL                       :DWORD;                                             // 0x4934
  BPHYC_UNIPHY3_UNIPHY_TPG_SEED                          :DWORD;                                             // 0x4935
  BPHYC_UNIPHY3_UNIPHY_DEBUG                             :DWORD;                                             // 0x4936
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23              :DWORD;                                             // 0x4937
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24              :DWORD;                                             // 0x4938
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25              :DWORD;                                             // 0x4939
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26              :DWORD;                                             // 0x493A
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27              :DWORD;                                             // 0x493B
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28              :DWORD;                                             // 0x493C
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29              :DWORD;                                             // 0x493D
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30              :DWORD;                                             // 0x493E
  DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31              :DWORD;                                             // 0x493F
  BPHYC_UNIPHY4_UNIPHY_TX_CONTROL1                       :DWORD;                                             // 0x4940
  BPHYC_UNIPHY4_UNIPHY_TX_CONTROL2                       :DWORD;                                             // 0x4941
  BPHYC_UNIPHY4_UNIPHY_TX_CONTROL3                       :DWORD;                                             // 0x4942
  BPHYC_UNIPHY4_UNIPHY_TX_CONTROL4                       :DWORD;                                             // 0x4943
  BPHYC_UNIPHY4_UNIPHY_POWER_CONTROL                     :DWORD;                                             // 0x4944
  BPHYC_UNIPHY4_UNIPHY_PLL_FBDIV                         :DWORD;                                             // 0x4945
  BPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1                      :DWORD;                                             // 0x4946
  BPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2                      :DWORD;                                             // 0x4947
  BPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE                  :DWORD;                                             // 0x4948
  BPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL                       :DWORD;                                             // 0x4949
  BPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION              :DWORD;                                             // 0x494A
  BPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT                   :DWORD;                                             // 0x494B
  BPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL                     :DWORD;                                             // 0x494C
  BPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2                  :DWORD;                                             // 0x494D
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14              :DWORD;                                             // 0x494E
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15              :DWORD;                                             // 0x494F
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16              :DWORD;                                             // 0x4950
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17              :DWORD;                                             // 0x4951
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18              :DWORD;                                             // 0x4952
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19              :DWORD;                                             // 0x4953
  BPHYC_UNIPHY4_UNIPHY_TPG_CONTROL                       :DWORD;                                             // 0x4954
  BPHYC_UNIPHY4_UNIPHY_TPG_SEED                          :DWORD;                                             // 0x4955
  BPHYC_UNIPHY4_UNIPHY_DEBUG                             :DWORD;                                             // 0x4956
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23              :DWORD;                                             // 0x4957
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24              :DWORD;                                             // 0x4958
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25              :DWORD;                                             // 0x4959
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26              :DWORD;                                             // 0x495A
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27              :DWORD;                                             // 0x495B
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28              :DWORD;                                             // 0x495C
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29              :DWORD;                                             // 0x495D
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30              :DWORD;                                             // 0x495E
  DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31              :DWORD;                                             // 0x495F
  BPHYC_UNIPHY5_UNIPHY_TX_CONTROL1                       :DWORD;                                             // 0x4960
  BPHYC_UNIPHY5_UNIPHY_TX_CONTROL2                       :DWORD;                                             // 0x4961
  BPHYC_UNIPHY5_UNIPHY_TX_CONTROL3                       :DWORD;                                             // 0x4962
  BPHYC_UNIPHY5_UNIPHY_TX_CONTROL4                       :DWORD;                                             // 0x4963
  BPHYC_UNIPHY5_UNIPHY_POWER_CONTROL                     :DWORD;                                             // 0x4964
  BPHYC_UNIPHY5_UNIPHY_PLL_FBDIV                         :DWORD;                                             // 0x4965
  BPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1                      :DWORD;                                             // 0x4966
  BPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2                      :DWORD;                                             // 0x4967
  BPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE                  :DWORD;                                             // 0x4968
  BPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL                       :DWORD;                                             // 0x4969
  BPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION              :DWORD;                                             // 0x496A
  BPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT                   :DWORD;                                             // 0x496B
  BPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL                     :DWORD;                                             // 0x496C
  BPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2                  :DWORD;                                             // 0x496D
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14              :DWORD;                                             // 0x496E
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15              :DWORD;                                             // 0x496F
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16              :DWORD;                                             // 0x4970
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17              :DWORD;                                             // 0x4971
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18              :DWORD;                                             // 0x4972
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19              :DWORD;                                             // 0x4973
  BPHYC_UNIPHY5_UNIPHY_TPG_CONTROL                       :DWORD;                                             // 0x4974
  BPHYC_UNIPHY5_UNIPHY_TPG_SEED                          :DWORD;                                             // 0x4975
  BPHYC_UNIPHY5_UNIPHY_DEBUG                             :DWORD;                                             // 0x4976
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23              :DWORD;                                             // 0x4977
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24              :DWORD;                                             // 0x4978
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25              :DWORD;                                             // 0x4979
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26              :DWORD;                                             // 0x497A
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27              :DWORD;                                             // 0x497B
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28              :DWORD;                                             // 0x497C
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29              :DWORD;                                             // 0x497D
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30              :DWORD;                                             // 0x497E
  DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31              :DWORD;                                             // 0x497F
  BPHYC_UNIPHY6_UNIPHY_TX_CONTROL1                       :DWORD;                                             // 0x4980
  BPHYC_UNIPHY6_UNIPHY_TX_CONTROL2                       :DWORD;                                             // 0x4981
  BPHYC_UNIPHY6_UNIPHY_TX_CONTROL3                       :DWORD;                                             // 0x4982
  BPHYC_UNIPHY6_UNIPHY_TX_CONTROL4                       :DWORD;                                             // 0x4983
  BPHYC_UNIPHY6_UNIPHY_POWER_CONTROL                     :DWORD;                                             // 0x4984
  BPHYC_UNIPHY6_UNIPHY_PLL_FBDIV                         :DWORD;                                             // 0x4985
  BPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1                      :DWORD;                                             // 0x4986
  BPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2                      :DWORD;                                             // 0x4987
  BPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE                  :DWORD;                                             // 0x4988
  BPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL                       :DWORD;                                             // 0x4989
  BPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION              :DWORD;                                             // 0x498A
  BPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT                   :DWORD;                                             // 0x498B
  BPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL                     :DWORD;                                             // 0x498C
  BPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2                  :DWORD;                                             // 0x498D
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14              :DWORD;                                             // 0x498E
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15              :DWORD;                                             // 0x498F
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16              :DWORD;                                             // 0x4990
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17              :DWORD;                                             // 0x4991
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18              :DWORD;                                             // 0x4992
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19              :DWORD;                                             // 0x4993
  BPHYC_UNIPHY6_UNIPHY_TPG_CONTROL                       :DWORD;                                             // 0x4994
  BPHYC_UNIPHY6_UNIPHY_TPG_SEED                          :DWORD;                                             // 0x4995
  BPHYC_UNIPHY6_UNIPHY_DEBUG                             :DWORD;                                             // 0x4996
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23              :DWORD;                                             // 0x4997
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24              :DWORD;                                             // 0x4998
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25              :DWORD;                                             // 0x4999
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26              :DWORD;                                             // 0x499A
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27              :DWORD;                                             // 0x499B
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28              :DWORD;                                             // 0x499C
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29              :DWORD;                                             // 0x499D
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30              :DWORD;                                             // 0x499E
  DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31              :DWORD;                                             // 0x499F
  REG_49A0_49FF                                          :array[0..95] of DWORD;                             // 0x49A0
  DIG0_DIG_FE_CNTL                                       :DWORD;                                             // 0x4A00
  DIG0_DIG_OUTPUT_CRC_CNTL                               :DWORD;                                             // 0x4A01
  DIG0_DIG_OUTPUT_CRC_RESULT                             :DWORD;                                             // 0x4A02
  DIG0_DIG_CLOCK_PATTERN                                 :DWORD;                                             // 0x4A03
  DIG0_DIG_TEST_PATTERN                                  :DWORD;                                             // 0x4A04
  DIG0_DIG_RANDOM_PATTERN_SEED                           :DWORD;                                             // 0x4A05
  DIG0_DIG_FIFO_STATUS                                   :DWORD;                                             // 0x4A06
  DIG0_DIG_DISPCLK_SWITCH_CNTL                           :DWORD;                                             // 0x4A07
  DIG0_DIG_DISPCLK_SWITCH_STATUS                         :DWORD;                                             // 0x4A08
  DIG0_HDMI_CONTROL                                      :DWORD;                                             // 0x4A09
  DIG0_HDMI_STATUS                                       :DWORD;                                             // 0x4A0A
  DIG0_HDMI_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4A0B
  DIG0_HDMI_ACR_PACKET_CONTROL                           :DWORD;                                             // 0x4A0C
  DIG0_HDMI_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4A0D
  DIG0_HDMI_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4A0E
  DIG0_HDMI_INFOFRAME_CONTROL1                           :DWORD;                                             // 0x4A0F
  DIG0_HDMI_GENERIC_PACKET_CONTROL0                      :DWORD;                                             // 0x4A10
  REG_4A11_4A12                                          :array[0..1] of DWORD;                              // 0x4A11
  DIG0_HDMI_GC                                           :DWORD;                                             // 0x4A13
  AFMT_AUDIO_PACKET_CONTROL2                             :TAFMT_AUDIO_PACKET_CONTROL2;                       // 0x4A14
  AFMT_ISRC1_0                                           :TAFMT_ISRC1_0;                                     // 0x4A15
  AFMT_ISRC1_1                                           :TAFMT_ISRC1_1;                                     // 0x4A16
  AFMT_ISRC1_2                                           :TAFMT_ISRC1_2;                                     // 0x4A17
  AFMT_ISRC1_3                                           :TAFMT_ISRC1_3;                                     // 0x4A18
  AFMT_ISRC1_4                                           :TAFMT_ISRC1_4;                                     // 0x4A19
  AFMT_ISRC2_0                                           :TAFMT_ISRC2_0;                                     // 0x4A1A
  AFMT_ISRC2_1                                           :TAFMT_ISRC2_1;                                     // 0x4A1B
  AFMT_ISRC2_2                                           :TAFMT_ISRC2_2;                                     // 0x4A1C
  AFMT_ISRC2_3                                           :TAFMT_ISRC2_3;                                     // 0x4A1D
  AFMT_AVI_INFO0                                         :TAFMT_AVI_INFO0;                                   // 0x4A1E
  AFMT_AVI_INFO1                                         :TAFMT_AVI_INFO1;                                   // 0x4A1F
  AFMT_AVI_INFO2                                         :TAFMT_AVI_INFO2;                                   // 0x4A20
  AFMT_AVI_INFO3                                         :TAFMT_AVI_INFO3;                                   // 0x4A21
  AFMT_MPEG_INFO0                                        :TAFMT_MPEG_INFO0;                                  // 0x4A22
  AFMT_MPEG_INFO1                                        :TAFMT_MPEG_INFO1;                                  // 0x4A23
  AFMT_GENERIC_HDR                                       :TAFMT_GENERIC_HDR;                                 // 0x4A24
  AFMT_GENERIC_0                                         :TAFMT_GENERIC_0;                                   // 0x4A25
  AFMT_GENERIC_1                                         :TAFMT_GENERIC_1;                                   // 0x4A26
  AFMT_GENERIC_2                                         :TAFMT_GENERIC_2;                                   // 0x4A27
  AFMT_GENERIC_3                                         :TAFMT_GENERIC_3;                                   // 0x4A28
  AFMT_GENERIC_4                                         :TAFMT_GENERIC_4;                                   // 0x4A29
  AFMT_GENERIC_5                                         :TAFMT_GENERIC_5;                                   // 0x4A2A
  AFMT_GENERIC_6                                         :TAFMT_GENERIC_6;                                   // 0x4A2B
  AFMT_GENERIC_7                                         :TAFMT_GENERIC_7;                                   // 0x4A2C
  DIG0_HDMI_GENERIC_PACKET_CONTROL1                      :DWORD;                                             // 0x4A2D
  DIG0_HDMI_ACR_32_0                                     :DWORD;                                             // 0x4A2E
  DIG0_HDMI_ACR_32_1                                     :DWORD;                                             // 0x4A2F
  DIG0_HDMI_ACR_44_0                                     :DWORD;                                             // 0x4A30
  DIG0_HDMI_ACR_44_1                                     :DWORD;                                             // 0x4A31
  DIG0_HDMI_ACR_48_0                                     :DWORD;                                             // 0x4A32
  DIG0_HDMI_ACR_48_1                                     :DWORD;                                             // 0x4A33
  DIG0_HDMI_ACR_STATUS_0                                 :DWORD;                                             // 0x4A34
  DIG0_HDMI_ACR_STATUS_1                                 :DWORD;                                             // 0x4A35
  AFMT_AUDIO_INFO0                                       :TAFMT_AUDIO_INFO0;                                 // 0x4A36
  AFMT_AUDIO_INFO1                                       :TAFMT_AUDIO_INFO1;                                 // 0x4A37
  AFMT_60958_0                                           :TAFMT_60958_0;                                     // 0x4A38
  AFMT_60958_1                                           :TAFMT_60958_1;                                     // 0x4A39
  AFMT_AUDIO_CRC_CONTROL                                 :TAFMT_AUDIO_CRC_CONTROL;                           // 0x4A3A
  AFMT_RAMP_CONTROL0                                     :TAFMT_RAMP_CONTROL0;                               // 0x4A3B
  AFMT_RAMP_CONTROL1                                     :TAFMT_RAMP_CONTROL1;                               // 0x4A3C
  AFMT_RAMP_CONTROL2                                     :TAFMT_RAMP_CONTROL2;                               // 0x4A3D
  AFMT_RAMP_CONTROL3                                     :TAFMT_RAMP_CONTROL3;                               // 0x4A3E
  AFMT_60958_2                                           :TAFMT_60958_2;                                     // 0x4A3F
  AFMT_AUDIO_CRC_RESULT                                  :TAFMT_AUDIO_CRC_RESULT;                            // 0x4A40
  AFMT_STATUS                                            :TAFMT_STATUS;                                      // 0x4A41
  AFMT_AUDIO_PACKET_CONTROL                              :TAFMT_AUDIO_PACKET_CONTROL;                        // 0x4A42
  AFMT_VBI_PACKET_CONTROL                                :TAFMT_VBI_PACKET_CONTROL;                          // 0x4A43
  AFMT_INFOFRAME_CONTROL0                                :TAFMT_INFOFRAME_CONTROL0;                          // 0x4A44
  AFMT_AUDIO_SRC_CONTROL                                 :TAFMT_AUDIO_SRC_CONTROL;                           // 0x4A45
  AFMT_AUDIO_DBG_DTO_CNTL                                :TAFMT_AUDIO_DBG_DTO_CNTL;                          // 0x4A46
  DIG0_DIG_BE_CNTL                                       :DWORD;                                             // 0x4A47
  DIG0_DIG_BE_EN_CNTL                                    :DWORD;                                             // 0x4A48
  REG_4A49_4A6A                                          :array[0..33] of DWORD;                             // 0x4A49
  DIG0_TMDS_CNTL                                         :DWORD;                                             // 0x4A6B
  DIG0_TMDS_CONTROL_CHAR                                 :DWORD;                                             // 0x4A6C
  DIG0_TMDS_CONTROL0_FEEDBACK                            :DWORD;                                             // 0x4A6D
  DIG0_TMDS_STEREOSYNC_CTL_SEL                           :DWORD;                                             // 0x4A6E
  DIG0_TMDS_SYNC_CHAR_PATTERN_0_1                        :DWORD;                                             // 0x4A6F
  DIG0_TMDS_SYNC_CHAR_PATTERN_2_3                        :DWORD;                                             // 0x4A70
  DIG0_TMDS_DEBUG                                        :DWORD;                                             // 0x4A71
  DIG0_TMDS_CTL_BITS                                     :DWORD;                                             // 0x4A72
  DIG0_TMDS_DCBALANCER_CONTROL                           :DWORD;                                             // 0x4A73
  REG_4A74                                               :DWORD;                                             // 0x4A74
  DIG0_TMDS_CTL0_1_GEN_CNTL                              :DWORD;                                             // 0x4A75
  DIG0_TMDS_CTL2_3_GEN_CNTL                              :DWORD;                                             // 0x4A76
  REG_4A77                                               :DWORD;                                             // 0x4A77
  DIG0_LVDS_DATA_CNTL                                    :DWORD;                                             // 0x4A78
  DIG0_DIG_LANE_ENABLE                                   :DWORD;                                             // 0x4A79
  DIG0_DIG_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x4A7A
  DIG0_DIG_TEST_DEBUG_DATA                               :DWORD;                                             // 0x4A7B
  DIG0_DIG_FE_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x4A7C
  DIG0_DIG_FE_TEST_DEBUG_DATA                            :DWORD;                                             // 0x4A7D
  REG_4A7E_4A99                                          :array[0..27] of DWORD;                             // 0x4A7E
  CRTC5_CRTC_PIXEL_DATA_READBACK                         :DWORD;                                             // 0x4A9A
  REG_4A9B_4A9F                                          :array[0..4] of DWORD;                              // 0x4A9B
  DP0_DP_LINK_CNTL                                       :DWORD;                                             // 0x4AA0
  DP0_DP_PIXEL_FORMAT                                    :DWORD;                                             // 0x4AA1
  DP0_DP_MSA_COLORIMETRY                                 :DWORD;                                             // 0x4AA2
  DP0_DP_CONFIG                                          :DWORD;                                             // 0x4AA3
  DP0_DP_VID_STREAM_CNTL                                 :DWORD;                                             // 0x4AA4
  DP0_DP_STEER_FIFO                                      :DWORD;                                             // 0x4AA5
  DP0_DP_MSA_MISC                                        :DWORD;                                             // 0x4AA6
  REG_4AA7                                               :DWORD;                                             // 0x4AA7
  DP0_DP_VID_TIMING                                      :DWORD;                                             // 0x4AA8
  DP0_DP_VID_N                                           :DWORD;                                             // 0x4AA9
  DP0_DP_VID_M                                           :DWORD;                                             // 0x4AAA
  DP0_DP_LINK_FRAMING_CNTL                               :DWORD;                                             // 0x4AAB
  DP0_DP_HBR2_EYE_PATTERN                                :DWORD;                                             // 0x4AAC
  DP0_DP_VID_MSA_VBID                                    :DWORD;                                             // 0x4AAD
  DP0_DP_VID_INTERRUPT_CNTL                              :DWORD;                                             // 0x4AAE
  DP0_DP_DPHY_CNTL                                       :DWORD;                                             // 0x4AAF
  DP0_DP_DPHY_TRAINING_PATTERN_SEL                       :DWORD;                                             // 0x4AB0
  DP0_DP_DPHY_SYM0                                       :DWORD;                                             // 0x4AB1
  DP0_DP_DPHY_SYM1                                       :DWORD;                                             // 0x4AB2
  DP0_DP_DPHY_SYM2                                       :DWORD;                                             // 0x4AB3
  DP0_DP_DPHY_8B10B_CNTL                                 :DWORD;                                             // 0x4AB4
  DP0_DP_DPHY_PRBS_CNTL                                  :DWORD;                                             // 0x4AB5
  REG_4AB6                                               :DWORD;                                             // 0x4AB6
  DP0_DP_DPHY_CRC_EN                                     :DWORD;                                             // 0x4AB7
  DP0_DP_DPHY_CRC_CNTL                                   :DWORD;                                             // 0x4AB8
  DP0_DP_DPHY_CRC_RESULT                                 :DWORD;                                             // 0x4AB9
  DP0_DP_DPHY_CRC_MST_CNTL                               :DWORD;                                             // 0x4ABA
  DP0_DP_DPHY_CRC_MST_STATUS                             :DWORD;                                             // 0x4ABB
  DP0_DP_DPHY_FAST_TRAINING                              :DWORD;                                             // 0x4ABC
  DP0_DP_DPHY_FAST_TRAINING_STATUS                       :DWORD;                                             // 0x4ABD
  DP0_DP_MSA_V_TIMING_OVERRIDE1                          :DWORD;                                             // 0x4ABE
  DP0_DP_MSA_V_TIMING_OVERRIDE2                          :DWORD;                                             // 0x4ABF
  REG_4AC0_4AC2                                          :array[0..2] of DWORD;                              // 0x4AC0
  DP0_DP_SEC_CNTL                                        :DWORD;                                             // 0x4AC3
  DP0_DP_SEC_CNTL1                                       :DWORD;                                             // 0x4AC4
  DP0_DP_SEC_FRAMING1                                    :DWORD;                                             // 0x4AC5
  DP0_DP_SEC_FRAMING2                                    :DWORD;                                             // 0x4AC6
  DP0_DP_SEC_FRAMING3                                    :DWORD;                                             // 0x4AC7
  DP0_DP_SEC_FRAMING4                                    :DWORD;                                             // 0x4AC8
  DP0_DP_SEC_AUD_N                                       :DWORD;                                             // 0x4AC9
  DP0_DP_SEC_AUD_N_READBACK                              :DWORD;                                             // 0x4ACA
  DP0_DP_SEC_AUD_M                                       :DWORD;                                             // 0x4ACB
  DP0_DP_SEC_AUD_M_READBACK                              :DWORD;                                             // 0x4ACC
  DP0_DP_SEC_TIMESTAMP                                   :DWORD;                                             // 0x4ACD
  DP0_DP_SEC_PACKET_CNTL                                 :DWORD;                                             // 0x4ACE
  DP0_DP_MSE_RATE_CNTL                                   :DWORD;                                             // 0x4ACF
  REG_4AD0                                               :DWORD;                                             // 0x4AD0
  DP0_DP_MSE_RATE_UPDATE                                 :DWORD;                                             // 0x4AD1
  DP0_DP_MSE_SAT0                                        :DWORD;                                             // 0x4AD2
  DP0_DP_MSE_SAT1                                        :DWORD;                                             // 0x4AD3
  DP0_DP_MSE_SAT2                                        :DWORD;                                             // 0x4AD4
  DP0_DP_MSE_SAT_UPDATE                                  :DWORD;                                             // 0x4AD5
  DP0_DP_MSE_LINK_TIMING                                 :DWORD;                                             // 0x4AD6
  DP0_DP_MSE_MISC_CNTL                                   :DWORD;                                             // 0x4AD7
  DP0_DP_TEST_DEBUG_INDEX                                :DWORD;                                             // 0x4AD8
  DP0_DP_TEST_DEBUG_DATA                                 :DWORD;                                             // 0x4AD9
  DP0_DP_FE_TEST_DEBUG_INDEX                             :DWORD;                                             // 0x4ADA
  DP0_DP_FE_TEST_DEBUG_DATA                              :DWORD;                                             // 0x4ADB
  REG_4ADC_4AFF                                          :array[0..35] of DWORD;                             // 0x4ADC
  DIG1_DIG_FE_CNTL                                       :DWORD;                                             // 0x4B00
  DIG1_DIG_OUTPUT_CRC_CNTL                               :DWORD;                                             // 0x4B01
  DIG1_DIG_OUTPUT_CRC_RESULT                             :DWORD;                                             // 0x4B02
  DIG1_DIG_CLOCK_PATTERN                                 :DWORD;                                             // 0x4B03
  DIG1_DIG_TEST_PATTERN                                  :DWORD;                                             // 0x4B04
  DIG1_DIG_RANDOM_PATTERN_SEED                           :DWORD;                                             // 0x4B05
  DIG1_DIG_FIFO_STATUS                                   :DWORD;                                             // 0x4B06
  DIG1_DIG_DISPCLK_SWITCH_CNTL                           :DWORD;                                             // 0x4B07
  DIG1_DIG_DISPCLK_SWITCH_STATUS                         :DWORD;                                             // 0x4B08
  DIG1_HDMI_CONTROL                                      :DWORD;                                             // 0x4B09
  DIG1_HDMI_STATUS                                       :DWORD;                                             // 0x4B0A
  DIG1_HDMI_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4B0B
  DIG1_HDMI_ACR_PACKET_CONTROL                           :DWORD;                                             // 0x4B0C
  DIG1_HDMI_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4B0D
  DIG1_HDMI_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4B0E
  DIG1_HDMI_INFOFRAME_CONTROL1                           :DWORD;                                             // 0x4B0F
  DIG1_HDMI_GENERIC_PACKET_CONTROL0                      :DWORD;                                             // 0x4B10
  REG_4B11_4B12                                          :array[0..1] of DWORD;                              // 0x4B11
  DIG1_HDMI_GC                                           :DWORD;                                             // 0x4B13
  DIG1_AFMT_AUDIO_PACKET_CONTROL2                        :DWORD;                                             // 0x4B14
  DIG1_AFMT_ISRC1_0                                      :DWORD;                                             // 0x4B15
  DIG1_AFMT_ISRC1_1                                      :DWORD;                                             // 0x4B16
  DIG1_AFMT_ISRC1_2                                      :DWORD;                                             // 0x4B17
  DIG1_AFMT_ISRC1_3                                      :DWORD;                                             // 0x4B18
  DIG1_AFMT_ISRC1_4                                      :DWORD;                                             // 0x4B19
  DIG1_AFMT_ISRC2_0                                      :DWORD;                                             // 0x4B1A
  DIG1_AFMT_ISRC2_1                                      :DWORD;                                             // 0x4B1B
  DIG1_AFMT_ISRC2_2                                      :DWORD;                                             // 0x4B1C
  DIG1_AFMT_ISRC2_3                                      :DWORD;                                             // 0x4B1D
  DIG1_AFMT_AVI_INFO0                                    :DWORD;                                             // 0x4B1E
  DIG1_AFMT_AVI_INFO1                                    :DWORD;                                             // 0x4B1F
  DIG1_AFMT_AVI_INFO2                                    :DWORD;                                             // 0x4B20
  DIG1_AFMT_AVI_INFO3                                    :DWORD;                                             // 0x4B21
  DIG1_AFMT_MPEG_INFO0                                   :DWORD;                                             // 0x4B22
  DIG1_AFMT_MPEG_INFO1                                   :DWORD;                                             // 0x4B23
  DIG1_AFMT_GENERIC_HDR                                  :DWORD;                                             // 0x4B24
  DIG1_AFMT_GENERIC_0                                    :DWORD;                                             // 0x4B25
  DIG1_AFMT_GENERIC_1                                    :DWORD;                                             // 0x4B26
  DIG1_AFMT_GENERIC_2                                    :DWORD;                                             // 0x4B27
  DIG1_AFMT_GENERIC_3                                    :DWORD;                                             // 0x4B28
  DIG1_AFMT_GENERIC_4                                    :DWORD;                                             // 0x4B29
  DIG1_AFMT_GENERIC_5                                    :DWORD;                                             // 0x4B2A
  DIG1_AFMT_GENERIC_6                                    :DWORD;                                             // 0x4B2B
  DIG1_AFMT_GENERIC_7                                    :DWORD;                                             // 0x4B2C
  DIG1_HDMI_GENERIC_PACKET_CONTROL1                      :DWORD;                                             // 0x4B2D
  DIG1_HDMI_ACR_32_0                                     :DWORD;                                             // 0x4B2E
  DIG1_HDMI_ACR_32_1                                     :DWORD;                                             // 0x4B2F
  DIG1_HDMI_ACR_44_0                                     :DWORD;                                             // 0x4B30
  DIG1_HDMI_ACR_44_1                                     :DWORD;                                             // 0x4B31
  DIG1_HDMI_ACR_48_0                                     :DWORD;                                             // 0x4B32
  DIG1_HDMI_ACR_48_1                                     :DWORD;                                             // 0x4B33
  DIG1_HDMI_ACR_STATUS_0                                 :DWORD;                                             // 0x4B34
  DIG1_HDMI_ACR_STATUS_1                                 :DWORD;                                             // 0x4B35
  DIG1_AFMT_AUDIO_INFO0                                  :DWORD;                                             // 0x4B36
  DIG1_AFMT_AUDIO_INFO1                                  :DWORD;                                             // 0x4B37
  DIG1_AFMT_60958_0                                      :DWORD;                                             // 0x4B38
  DIG1_AFMT_60958_1                                      :DWORD;                                             // 0x4B39
  DIG1_AFMT_AUDIO_CRC_CONTROL                            :DWORD;                                             // 0x4B3A
  DIG1_AFMT_RAMP_CONTROL0                                :DWORD;                                             // 0x4B3B
  DIG1_AFMT_RAMP_CONTROL1                                :DWORD;                                             // 0x4B3C
  DIG1_AFMT_RAMP_CONTROL2                                :DWORD;                                             // 0x4B3D
  DIG1_AFMT_RAMP_CONTROL3                                :DWORD;                                             // 0x4B3E
  DIG1_AFMT_60958_2                                      :DWORD;                                             // 0x4B3F
  DIG1_AFMT_AUDIO_CRC_RESULT                             :DWORD;                                             // 0x4B40
  DIG1_AFMT_STATUS                                       :DWORD;                                             // 0x4B41
  DIG1_AFMT_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4B42
  DIG1_AFMT_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4B43
  DIG1_AFMT_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4B44
  DIG1_AFMT_AUDIO_SRC_CONTROL                            :DWORD;                                             // 0x4B45
  DIG1_AFMT_AUDIO_DBG_DTO_CNTL                           :DWORD;                                             // 0x4B46
  DIG1_DIG_BE_CNTL                                       :DWORD;                                             // 0x4B47
  DIG1_DIG_BE_EN_CNTL                                    :DWORD;                                             // 0x4B48
  REG_4B49_4B6A                                          :array[0..33] of DWORD;                             // 0x4B49
  DIG1_TMDS_CNTL                                         :DWORD;                                             // 0x4B6B
  DIG1_TMDS_CONTROL_CHAR                                 :DWORD;                                             // 0x4B6C
  DIG1_TMDS_CONTROL0_FEEDBACK                            :DWORD;                                             // 0x4B6D
  DIG1_TMDS_STEREOSYNC_CTL_SEL                           :DWORD;                                             // 0x4B6E
  DIG1_TMDS_SYNC_CHAR_PATTERN_0_1                        :DWORD;                                             // 0x4B6F
  DIG1_TMDS_SYNC_CHAR_PATTERN_2_3                        :DWORD;                                             // 0x4B70
  DIG1_TMDS_DEBUG                                        :DWORD;                                             // 0x4B71
  DIG1_TMDS_CTL_BITS                                     :DWORD;                                             // 0x4B72
  DIG1_TMDS_DCBALANCER_CONTROL                           :DWORD;                                             // 0x4B73
  REG_4B74                                               :DWORD;                                             // 0x4B74
  DIG1_TMDS_CTL0_1_GEN_CNTL                              :DWORD;                                             // 0x4B75
  DIG1_TMDS_CTL2_3_GEN_CNTL                              :DWORD;                                             // 0x4B76
  REG_4B77                                               :DWORD;                                             // 0x4B77
  DIG1_LVDS_DATA_CNTL                                    :DWORD;                                             // 0x4B78
  DIG1_DIG_LANE_ENABLE                                   :DWORD;                                             // 0x4B79
  DIG1_DIG_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x4B7A
  DIG1_DIG_TEST_DEBUG_DATA                               :DWORD;                                             // 0x4B7B
  DIG1_DIG_FE_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x4B7C
  DIG1_DIG_FE_TEST_DEBUG_DATA                            :DWORD;                                             // 0x4B7D
  REG_4B7E_4B9F                                          :array[0..33] of DWORD;                             // 0x4B7E
  DP1_DP_LINK_CNTL                                       :DWORD;                                             // 0x4BA0
  DP1_DP_PIXEL_FORMAT                                    :DWORD;                                             // 0x4BA1
  DP1_DP_MSA_COLORIMETRY                                 :DWORD;                                             // 0x4BA2
  DP1_DP_CONFIG                                          :DWORD;                                             // 0x4BA3
  DP1_DP_VID_STREAM_CNTL                                 :DWORD;                                             // 0x4BA4
  DP1_DP_STEER_FIFO                                      :DWORD;                                             // 0x4BA5
  DP1_DP_MSA_MISC                                        :DWORD;                                             // 0x4BA6
  REG_4BA7                                               :DWORD;                                             // 0x4BA7
  DP1_DP_VID_TIMING                                      :DWORD;                                             // 0x4BA8
  DP1_DP_VID_N                                           :DWORD;                                             // 0x4BA9
  DP1_DP_VID_M                                           :DWORD;                                             // 0x4BAA
  DP1_DP_LINK_FRAMING_CNTL                               :DWORD;                                             // 0x4BAB
  DP1_DP_HBR2_EYE_PATTERN                                :DWORD;                                             // 0x4BAC
  DP1_DP_VID_MSA_VBID                                    :DWORD;                                             // 0x4BAD
  DP1_DP_VID_INTERRUPT_CNTL                              :DWORD;                                             // 0x4BAE
  DP1_DP_DPHY_CNTL                                       :DWORD;                                             // 0x4BAF
  DP1_DP_DPHY_TRAINING_PATTERN_SEL                       :DWORD;                                             // 0x4BB0
  DP1_DP_DPHY_SYM0                                       :DWORD;                                             // 0x4BB1
  DP1_DP_DPHY_SYM1                                       :DWORD;                                             // 0x4BB2
  DP1_DP_DPHY_SYM2                                       :DWORD;                                             // 0x4BB3
  DP1_DP_DPHY_8B10B_CNTL                                 :DWORD;                                             // 0x4BB4
  DP1_DP_DPHY_PRBS_CNTL                                  :DWORD;                                             // 0x4BB5
  REG_4BB6                                               :DWORD;                                             // 0x4BB6
  DP1_DP_DPHY_CRC_EN                                     :DWORD;                                             // 0x4BB7
  DP1_DP_DPHY_CRC_CNTL                                   :DWORD;                                             // 0x4BB8
  DP1_DP_DPHY_CRC_RESULT                                 :DWORD;                                             // 0x4BB9
  DP1_DP_DPHY_CRC_MST_CNTL                               :DWORD;                                             // 0x4BBA
  DP1_DP_DPHY_CRC_MST_STATUS                             :DWORD;                                             // 0x4BBB
  DP1_DP_DPHY_FAST_TRAINING                              :DWORD;                                             // 0x4BBC
  DP1_DP_DPHY_FAST_TRAINING_STATUS                       :DWORD;                                             // 0x4BBD
  DP1_DP_MSA_V_TIMING_OVERRIDE1                          :DWORD;                                             // 0x4BBE
  DP1_DP_MSA_V_TIMING_OVERRIDE2                          :DWORD;                                             // 0x4BBF
  REG_4BC0_4BC2                                          :array[0..2] of DWORD;                              // 0x4BC0
  DP1_DP_SEC_CNTL                                        :DWORD;                                             // 0x4BC3
  DP1_DP_SEC_CNTL1                                       :DWORD;                                             // 0x4BC4
  DP1_DP_SEC_FRAMING1                                    :DWORD;                                             // 0x4BC5
  DP1_DP_SEC_FRAMING2                                    :DWORD;                                             // 0x4BC6
  DP1_DP_SEC_FRAMING3                                    :DWORD;                                             // 0x4BC7
  DP1_DP_SEC_FRAMING4                                    :DWORD;                                             // 0x4BC8
  DP1_DP_SEC_AUD_N                                       :DWORD;                                             // 0x4BC9
  DP1_DP_SEC_AUD_N_READBACK                              :DWORD;                                             // 0x4BCA
  DP1_DP_SEC_AUD_M                                       :DWORD;                                             // 0x4BCB
  DP1_DP_SEC_AUD_M_READBACK                              :DWORD;                                             // 0x4BCC
  DP1_DP_SEC_TIMESTAMP                                   :DWORD;                                             // 0x4BCD
  DP1_DP_SEC_PACKET_CNTL                                 :DWORD;                                             // 0x4BCE
  DP1_DP_MSE_RATE_CNTL                                   :DWORD;                                             // 0x4BCF
  REG_4BD0                                               :DWORD;                                             // 0x4BD0
  DP1_DP_MSE_RATE_UPDATE                                 :DWORD;                                             // 0x4BD1
  DP1_DP_MSE_SAT0                                        :DWORD;                                             // 0x4BD2
  DP1_DP_MSE_SAT1                                        :DWORD;                                             // 0x4BD3
  DP1_DP_MSE_SAT2                                        :DWORD;                                             // 0x4BD4
  DP1_DP_MSE_SAT_UPDATE                                  :DWORD;                                             // 0x4BD5
  DP1_DP_MSE_LINK_TIMING                                 :DWORD;                                             // 0x4BD6
  DP1_DP_MSE_MISC_CNTL                                   :DWORD;                                             // 0x4BD7
  DP1_DP_TEST_DEBUG_INDEX                                :DWORD;                                             // 0x4BD8
  DP1_DP_TEST_DEBUG_DATA                                 :DWORD;                                             // 0x4BD9
  DP1_DP_FE_TEST_DEBUG_INDEX                             :DWORD;                                             // 0x4BDA
  DP1_DP_FE_TEST_DEBUG_DATA                              :DWORD;                                             // 0x4BDB
  REG_4BDC_4BFF                                          :array[0..35] of DWORD;                             // 0x4BDC
  DIG2_DIG_FE_CNTL                                       :DWORD;                                             // 0x4C00
  DIG2_DIG_OUTPUT_CRC_CNTL                               :DWORD;                                             // 0x4C01
  DIG2_DIG_OUTPUT_CRC_RESULT                             :DWORD;                                             // 0x4C02
  DIG2_DIG_CLOCK_PATTERN                                 :DWORD;                                             // 0x4C03
  DIG2_DIG_TEST_PATTERN                                  :DWORD;                                             // 0x4C04
  DIG2_DIG_RANDOM_PATTERN_SEED                           :DWORD;                                             // 0x4C05
  DIG2_DIG_FIFO_STATUS                                   :DWORD;                                             // 0x4C06
  DIG2_DIG_DISPCLK_SWITCH_CNTL                           :DWORD;                                             // 0x4C07
  DIG2_DIG_DISPCLK_SWITCH_STATUS                         :DWORD;                                             // 0x4C08
  DIG2_HDMI_CONTROL                                      :DWORD;                                             // 0x4C09
  DIG2_HDMI_STATUS                                       :DWORD;                                             // 0x4C0A
  DIG2_HDMI_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4C0B
  DIG2_HDMI_ACR_PACKET_CONTROL                           :DWORD;                                             // 0x4C0C
  DIG2_HDMI_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4C0D
  DIG2_HDMI_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4C0E
  DIG2_HDMI_INFOFRAME_CONTROL1                           :DWORD;                                             // 0x4C0F
  DIG2_HDMI_GENERIC_PACKET_CONTROL0                      :DWORD;                                             // 0x4C10
  REG_4C11_4C12                                          :array[0..1] of DWORD;                              // 0x4C11
  DIG2_HDMI_GC                                           :DWORD;                                             // 0x4C13
  DIG2_AFMT_AUDIO_PACKET_CONTROL2                        :DWORD;                                             // 0x4C14
  DIG2_AFMT_ISRC1_0                                      :DWORD;                                             // 0x4C15
  DIG2_AFMT_ISRC1_1                                      :DWORD;                                             // 0x4C16
  DIG2_AFMT_ISRC1_2                                      :DWORD;                                             // 0x4C17
  DIG2_AFMT_ISRC1_3                                      :DWORD;                                             // 0x4C18
  DIG2_AFMT_ISRC1_4                                      :DWORD;                                             // 0x4C19
  DIG2_AFMT_ISRC2_0                                      :DWORD;                                             // 0x4C1A
  DIG2_AFMT_ISRC2_1                                      :DWORD;                                             // 0x4C1B
  DIG2_AFMT_ISRC2_2                                      :DWORD;                                             // 0x4C1C
  DIG2_AFMT_ISRC2_3                                      :DWORD;                                             // 0x4C1D
  DIG2_AFMT_AVI_INFO0                                    :DWORD;                                             // 0x4C1E
  DIG2_AFMT_AVI_INFO1                                    :DWORD;                                             // 0x4C1F
  DIG2_AFMT_AVI_INFO2                                    :DWORD;                                             // 0x4C20
  DIG2_AFMT_AVI_INFO3                                    :DWORD;                                             // 0x4C21
  DIG2_AFMT_MPEG_INFO0                                   :DWORD;                                             // 0x4C22
  DIG2_AFMT_MPEG_INFO1                                   :DWORD;                                             // 0x4C23
  DIG2_AFMT_GENERIC_HDR                                  :DWORD;                                             // 0x4C24
  DIG2_AFMT_GENERIC_0                                    :DWORD;                                             // 0x4C25
  DIG2_AFMT_GENERIC_1                                    :DWORD;                                             // 0x4C26
  DIG2_AFMT_GENERIC_2                                    :DWORD;                                             // 0x4C27
  DIG2_AFMT_GENERIC_3                                    :DWORD;                                             // 0x4C28
  DIG2_AFMT_GENERIC_4                                    :DWORD;                                             // 0x4C29
  DIG2_AFMT_GENERIC_5                                    :DWORD;                                             // 0x4C2A
  DIG2_AFMT_GENERIC_6                                    :DWORD;                                             // 0x4C2B
  DIG2_AFMT_GENERIC_7                                    :DWORD;                                             // 0x4C2C
  DIG2_HDMI_GENERIC_PACKET_CONTROL1                      :DWORD;                                             // 0x4C2D
  DIG2_HDMI_ACR_32_0                                     :DWORD;                                             // 0x4C2E
  DIG2_HDMI_ACR_32_1                                     :DWORD;                                             // 0x4C2F
  DIG2_HDMI_ACR_44_0                                     :DWORD;                                             // 0x4C30
  DIG2_HDMI_ACR_44_1                                     :DWORD;                                             // 0x4C31
  DIG2_HDMI_ACR_48_0                                     :DWORD;                                             // 0x4C32
  DIG2_HDMI_ACR_48_1                                     :DWORD;                                             // 0x4C33
  DIG2_HDMI_ACR_STATUS_0                                 :DWORD;                                             // 0x4C34
  DIG2_HDMI_ACR_STATUS_1                                 :DWORD;                                             // 0x4C35
  DIG2_AFMT_AUDIO_INFO0                                  :DWORD;                                             // 0x4C36
  DIG2_AFMT_AUDIO_INFO1                                  :DWORD;                                             // 0x4C37
  DIG2_AFMT_60958_0                                      :DWORD;                                             // 0x4C38
  DIG2_AFMT_60958_1                                      :DWORD;                                             // 0x4C39
  DIG2_AFMT_AUDIO_CRC_CONTROL                            :DWORD;                                             // 0x4C3A
  DIG2_AFMT_RAMP_CONTROL0                                :DWORD;                                             // 0x4C3B
  DIG2_AFMT_RAMP_CONTROL1                                :DWORD;                                             // 0x4C3C
  DIG2_AFMT_RAMP_CONTROL2                                :DWORD;                                             // 0x4C3D
  DIG2_AFMT_RAMP_CONTROL3                                :DWORD;                                             // 0x4C3E
  DIG2_AFMT_60958_2                                      :DWORD;                                             // 0x4C3F
  DIG2_AFMT_AUDIO_CRC_RESULT                             :DWORD;                                             // 0x4C40
  DIG2_AFMT_STATUS                                       :DWORD;                                             // 0x4C41
  DIG2_AFMT_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4C42
  DIG2_AFMT_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4C43
  DIG2_AFMT_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4C44
  DIG2_AFMT_AUDIO_SRC_CONTROL                            :DWORD;                                             // 0x4C45
  DIG2_AFMT_AUDIO_DBG_DTO_CNTL                           :DWORD;                                             // 0x4C46
  DIG2_DIG_BE_CNTL                                       :DWORD;                                             // 0x4C47
  DIG2_DIG_BE_EN_CNTL                                    :DWORD;                                             // 0x4C48
  REG_4C49_4C6A                                          :array[0..33] of DWORD;                             // 0x4C49
  DIG2_TMDS_CNTL                                         :DWORD;                                             // 0x4C6B
  DIG2_TMDS_CONTROL_CHAR                                 :DWORD;                                             // 0x4C6C
  DIG2_TMDS_CONTROL0_FEEDBACK                            :DWORD;                                             // 0x4C6D
  DIG2_TMDS_STEREOSYNC_CTL_SEL                           :DWORD;                                             // 0x4C6E
  DIG2_TMDS_SYNC_CHAR_PATTERN_0_1                        :DWORD;                                             // 0x4C6F
  DIG2_TMDS_SYNC_CHAR_PATTERN_2_3                        :DWORD;                                             // 0x4C70
  DIG2_TMDS_DEBUG                                        :DWORD;                                             // 0x4C71
  DIG2_TMDS_CTL_BITS                                     :DWORD;                                             // 0x4C72
  DIG2_TMDS_DCBALANCER_CONTROL                           :DWORD;                                             // 0x4C73
  REG_4C74                                               :DWORD;                                             // 0x4C74
  DIG2_TMDS_CTL0_1_GEN_CNTL                              :DWORD;                                             // 0x4C75
  DIG2_TMDS_CTL2_3_GEN_CNTL                              :DWORD;                                             // 0x4C76
  REG_4C77                                               :DWORD;                                             // 0x4C77
  DIG2_LVDS_DATA_CNTL                                    :DWORD;                                             // 0x4C78
  DIG2_DIG_LANE_ENABLE                                   :DWORD;                                             // 0x4C79
  DIG2_DIG_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x4C7A
  DIG2_DIG_TEST_DEBUG_DATA                               :DWORD;                                             // 0x4C7B
  DIG2_DIG_FE_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x4C7C
  DIG2_DIG_FE_TEST_DEBUG_DATA                            :DWORD;                                             // 0x4C7D
  REG_4C7E_4C9F                                          :array[0..33] of DWORD;                             // 0x4C7E
  DP2_DP_LINK_CNTL                                       :DWORD;                                             // 0x4CA0
  DP2_DP_PIXEL_FORMAT                                    :DWORD;                                             // 0x4CA1
  DP2_DP_MSA_COLORIMETRY                                 :DWORD;                                             // 0x4CA2
  DP2_DP_CONFIG                                          :DWORD;                                             // 0x4CA3
  DP2_DP_VID_STREAM_CNTL                                 :DWORD;                                             // 0x4CA4
  DP2_DP_STEER_FIFO                                      :DWORD;                                             // 0x4CA5
  DP2_DP_MSA_MISC                                        :DWORD;                                             // 0x4CA6
  REG_4CA7                                               :DWORD;                                             // 0x4CA7
  DP2_DP_VID_TIMING                                      :DWORD;                                             // 0x4CA8
  DP2_DP_VID_N                                           :DWORD;                                             // 0x4CA9
  DP2_DP_VID_M                                           :DWORD;                                             // 0x4CAA
  DP2_DP_LINK_FRAMING_CNTL                               :DWORD;                                             // 0x4CAB
  DP2_DP_HBR2_EYE_PATTERN                                :DWORD;                                             // 0x4CAC
  DP2_DP_VID_MSA_VBID                                    :DWORD;                                             // 0x4CAD
  DP2_DP_VID_INTERRUPT_CNTL                              :DWORD;                                             // 0x4CAE
  DP2_DP_DPHY_CNTL                                       :DWORD;                                             // 0x4CAF
  DP2_DP_DPHY_TRAINING_PATTERN_SEL                       :DWORD;                                             // 0x4CB0
  DP2_DP_DPHY_SYM0                                       :DWORD;                                             // 0x4CB1
  DP2_DP_DPHY_SYM1                                       :DWORD;                                             // 0x4CB2
  DP2_DP_DPHY_SYM2                                       :DWORD;                                             // 0x4CB3
  DP2_DP_DPHY_8B10B_CNTL                                 :DWORD;                                             // 0x4CB4
  DP2_DP_DPHY_PRBS_CNTL                                  :DWORD;                                             // 0x4CB5
  REG_4CB6                                               :DWORD;                                             // 0x4CB6
  DP2_DP_DPHY_CRC_EN                                     :DWORD;                                             // 0x4CB7
  DP2_DP_DPHY_CRC_CNTL                                   :DWORD;                                             // 0x4CB8
  DP2_DP_DPHY_CRC_RESULT                                 :DWORD;                                             // 0x4CB9
  DP2_DP_DPHY_CRC_MST_CNTL                               :DWORD;                                             // 0x4CBA
  DP2_DP_DPHY_CRC_MST_STATUS                             :DWORD;                                             // 0x4CBB
  DP2_DP_DPHY_FAST_TRAINING                              :DWORD;                                             // 0x4CBC
  DP2_DP_DPHY_FAST_TRAINING_STATUS                       :DWORD;                                             // 0x4CBD
  DP2_DP_MSA_V_TIMING_OVERRIDE1                          :DWORD;                                             // 0x4CBE
  DP2_DP_MSA_V_TIMING_OVERRIDE2                          :DWORD;                                             // 0x4CBF
  REG_4CC0_4CC2                                          :array[0..2] of DWORD;                              // 0x4CC0
  DP2_DP_SEC_CNTL                                        :DWORD;                                             // 0x4CC3
  DP2_DP_SEC_CNTL1                                       :DWORD;                                             // 0x4CC4
  DP2_DP_SEC_FRAMING1                                    :DWORD;                                             // 0x4CC5
  DP2_DP_SEC_FRAMING2                                    :DWORD;                                             // 0x4CC6
  DP2_DP_SEC_FRAMING3                                    :DWORD;                                             // 0x4CC7
  DP2_DP_SEC_FRAMING4                                    :DWORD;                                             // 0x4CC8
  DP2_DP_SEC_AUD_N                                       :DWORD;                                             // 0x4CC9
  DP2_DP_SEC_AUD_N_READBACK                              :DWORD;                                             // 0x4CCA
  DP2_DP_SEC_AUD_M                                       :DWORD;                                             // 0x4CCB
  DP2_DP_SEC_AUD_M_READBACK                              :DWORD;                                             // 0x4CCC
  DP2_DP_SEC_TIMESTAMP                                   :DWORD;                                             // 0x4CCD
  DP2_DP_SEC_PACKET_CNTL                                 :DWORD;                                             // 0x4CCE
  DP2_DP_MSE_RATE_CNTL                                   :DWORD;                                             // 0x4CCF
  REG_4CD0                                               :DWORD;                                             // 0x4CD0
  DP2_DP_MSE_RATE_UPDATE                                 :DWORD;                                             // 0x4CD1
  DP2_DP_MSE_SAT0                                        :DWORD;                                             // 0x4CD2
  DP2_DP_MSE_SAT1                                        :DWORD;                                             // 0x4CD3
  DP2_DP_MSE_SAT2                                        :DWORD;                                             // 0x4CD4
  DP2_DP_MSE_SAT_UPDATE                                  :DWORD;                                             // 0x4CD5
  DP2_DP_MSE_LINK_TIMING                                 :DWORD;                                             // 0x4CD6
  DP2_DP_MSE_MISC_CNTL                                   :DWORD;                                             // 0x4CD7
  DP2_DP_TEST_DEBUG_INDEX                                :DWORD;                                             // 0x4CD8
  DP2_DP_TEST_DEBUG_DATA                                 :DWORD;                                             // 0x4CD9
  DP2_DP_FE_TEST_DEBUG_INDEX                             :DWORD;                                             // 0x4CDA
  DP2_DP_FE_TEST_DEBUG_DATA                              :DWORD;                                             // 0x4CDB
  REG_4CDC_4CFF                                          :array[0..35] of DWORD;                             // 0x4CDC
  DIG3_DIG_FE_CNTL                                       :DWORD;                                             // 0x4D00
  DIG3_DIG_OUTPUT_CRC_CNTL                               :DWORD;                                             // 0x4D01
  DIG3_DIG_OUTPUT_CRC_RESULT                             :DWORD;                                             // 0x4D02
  DIG3_DIG_CLOCK_PATTERN                                 :DWORD;                                             // 0x4D03
  DIG3_DIG_TEST_PATTERN                                  :DWORD;                                             // 0x4D04
  DIG3_DIG_RANDOM_PATTERN_SEED                           :DWORD;                                             // 0x4D05
  DIG3_DIG_FIFO_STATUS                                   :DWORD;                                             // 0x4D06
  DIG3_DIG_DISPCLK_SWITCH_CNTL                           :DWORD;                                             // 0x4D07
  DIG3_DIG_DISPCLK_SWITCH_STATUS                         :DWORD;                                             // 0x4D08
  DIG3_HDMI_CONTROL                                      :DWORD;                                             // 0x4D09
  DIG3_HDMI_STATUS                                       :DWORD;                                             // 0x4D0A
  DIG3_HDMI_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4D0B
  DIG3_HDMI_ACR_PACKET_CONTROL                           :DWORD;                                             // 0x4D0C
  DIG3_HDMI_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4D0D
  DIG3_HDMI_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4D0E
  DIG3_HDMI_INFOFRAME_CONTROL1                           :DWORD;                                             // 0x4D0F
  DIG3_HDMI_GENERIC_PACKET_CONTROL0                      :DWORD;                                             // 0x4D10
  REG_4D11_4D12                                          :array[0..1] of DWORD;                              // 0x4D11
  DIG3_HDMI_GC                                           :DWORD;                                             // 0x4D13
  DIG3_AFMT_AUDIO_PACKET_CONTROL2                        :DWORD;                                             // 0x4D14
  DIG3_AFMT_ISRC1_0                                      :DWORD;                                             // 0x4D15
  DIG3_AFMT_ISRC1_1                                      :DWORD;                                             // 0x4D16
  DIG3_AFMT_ISRC1_2                                      :DWORD;                                             // 0x4D17
  DIG3_AFMT_ISRC1_3                                      :DWORD;                                             // 0x4D18
  DIG3_AFMT_ISRC1_4                                      :DWORD;                                             // 0x4D19
  DIG3_AFMT_ISRC2_0                                      :DWORD;                                             // 0x4D1A
  DIG3_AFMT_ISRC2_1                                      :DWORD;                                             // 0x4D1B
  DIG3_AFMT_ISRC2_2                                      :DWORD;                                             // 0x4D1C
  DIG3_AFMT_ISRC2_3                                      :DWORD;                                             // 0x4D1D
  DIG3_AFMT_AVI_INFO0                                    :DWORD;                                             // 0x4D1E
  DIG3_AFMT_AVI_INFO1                                    :DWORD;                                             // 0x4D1F
  DIG3_AFMT_AVI_INFO2                                    :DWORD;                                             // 0x4D20
  DIG3_AFMT_AVI_INFO3                                    :DWORD;                                             // 0x4D21
  DIG3_AFMT_MPEG_INFO0                                   :DWORD;                                             // 0x4D22
  DIG3_AFMT_MPEG_INFO1                                   :DWORD;                                             // 0x4D23
  DIG3_AFMT_GENERIC_HDR                                  :DWORD;                                             // 0x4D24
  DIG3_AFMT_GENERIC_0                                    :DWORD;                                             // 0x4D25
  DIG3_AFMT_GENERIC_1                                    :DWORD;                                             // 0x4D26
  DIG3_AFMT_GENERIC_2                                    :DWORD;                                             // 0x4D27
  DIG3_AFMT_GENERIC_3                                    :DWORD;                                             // 0x4D28
  DIG3_AFMT_GENERIC_4                                    :DWORD;                                             // 0x4D29
  DIG3_AFMT_GENERIC_5                                    :DWORD;                                             // 0x4D2A
  DIG3_AFMT_GENERIC_6                                    :DWORD;                                             // 0x4D2B
  DIG3_AFMT_GENERIC_7                                    :DWORD;                                             // 0x4D2C
  DIG3_HDMI_GENERIC_PACKET_CONTROL1                      :DWORD;                                             // 0x4D2D
  DIG3_HDMI_ACR_32_0                                     :DWORD;                                             // 0x4D2E
  DIG3_HDMI_ACR_32_1                                     :DWORD;                                             // 0x4D2F
  DIG3_HDMI_ACR_44_0                                     :DWORD;                                             // 0x4D30
  DIG3_HDMI_ACR_44_1                                     :DWORD;                                             // 0x4D31
  DIG3_HDMI_ACR_48_0                                     :DWORD;                                             // 0x4D32
  DIG3_HDMI_ACR_48_1                                     :DWORD;                                             // 0x4D33
  DIG3_HDMI_ACR_STATUS_0                                 :DWORD;                                             // 0x4D34
  DIG3_HDMI_ACR_STATUS_1                                 :DWORD;                                             // 0x4D35
  DIG3_AFMT_AUDIO_INFO0                                  :DWORD;                                             // 0x4D36
  DIG3_AFMT_AUDIO_INFO1                                  :DWORD;                                             // 0x4D37
  DIG3_AFMT_60958_0                                      :DWORD;                                             // 0x4D38
  DIG3_AFMT_60958_1                                      :DWORD;                                             // 0x4D39
  DIG3_AFMT_AUDIO_CRC_CONTROL                            :DWORD;                                             // 0x4D3A
  DIG3_AFMT_RAMP_CONTROL0                                :DWORD;                                             // 0x4D3B
  DIG3_AFMT_RAMP_CONTROL1                                :DWORD;                                             // 0x4D3C
  DIG3_AFMT_RAMP_CONTROL2                                :DWORD;                                             // 0x4D3D
  DIG3_AFMT_RAMP_CONTROL3                                :DWORD;                                             // 0x4D3E
  DIG3_AFMT_60958_2                                      :DWORD;                                             // 0x4D3F
  DIG3_AFMT_AUDIO_CRC_RESULT                             :DWORD;                                             // 0x4D40
  DIG3_AFMT_STATUS                                       :DWORD;                                             // 0x4D41
  DIG3_AFMT_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4D42
  DIG3_AFMT_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4D43
  DIG3_AFMT_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4D44
  DIG3_AFMT_AUDIO_SRC_CONTROL                            :DWORD;                                             // 0x4D45
  DIG3_AFMT_AUDIO_DBG_DTO_CNTL                           :DWORD;                                             // 0x4D46
  DIG3_DIG_BE_CNTL                                       :DWORD;                                             // 0x4D47
  DIG3_DIG_BE_EN_CNTL                                    :DWORD;                                             // 0x4D48
  REG_4D49_4D6A                                          :array[0..33] of DWORD;                             // 0x4D49
  DIG3_TMDS_CNTL                                         :DWORD;                                             // 0x4D6B
  DIG3_TMDS_CONTROL_CHAR                                 :DWORD;                                             // 0x4D6C
  DIG3_TMDS_CONTROL0_FEEDBACK                            :DWORD;                                             // 0x4D6D
  DIG3_TMDS_STEREOSYNC_CTL_SEL                           :DWORD;                                             // 0x4D6E
  DIG3_TMDS_SYNC_CHAR_PATTERN_0_1                        :DWORD;                                             // 0x4D6F
  DIG3_TMDS_SYNC_CHAR_PATTERN_2_3                        :DWORD;                                             // 0x4D70
  DIG3_TMDS_DEBUG                                        :DWORD;                                             // 0x4D71
  DIG3_TMDS_CTL_BITS                                     :DWORD;                                             // 0x4D72
  DIG3_TMDS_DCBALANCER_CONTROL                           :DWORD;                                             // 0x4D73
  REG_4D74                                               :DWORD;                                             // 0x4D74
  DIG3_TMDS_CTL0_1_GEN_CNTL                              :DWORD;                                             // 0x4D75
  DIG3_TMDS_CTL2_3_GEN_CNTL                              :DWORD;                                             // 0x4D76
  REG_4D77                                               :DWORD;                                             // 0x4D77
  DIG3_LVDS_DATA_CNTL                                    :DWORD;                                             // 0x4D78
  DIG3_DIG_LANE_ENABLE                                   :DWORD;                                             // 0x4D79
  DIG3_DIG_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x4D7A
  DIG3_DIG_TEST_DEBUG_DATA                               :DWORD;                                             // 0x4D7B
  DIG3_DIG_FE_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x4D7C
  DIG3_DIG_FE_TEST_DEBUG_DATA                            :DWORD;                                             // 0x4D7D
  REG_4D7E_4D9F                                          :array[0..33] of DWORD;                             // 0x4D7E
  DP3_DP_LINK_CNTL                                       :DWORD;                                             // 0x4DA0
  DP3_DP_PIXEL_FORMAT                                    :DWORD;                                             // 0x4DA1
  DP3_DP_MSA_COLORIMETRY                                 :DWORD;                                             // 0x4DA2
  DP3_DP_CONFIG                                          :DWORD;                                             // 0x4DA3
  DP3_DP_VID_STREAM_CNTL                                 :DWORD;                                             // 0x4DA4
  DP3_DP_STEER_FIFO                                      :DWORD;                                             // 0x4DA5
  DP3_DP_MSA_MISC                                        :DWORD;                                             // 0x4DA6
  REG_4DA7                                               :DWORD;                                             // 0x4DA7
  DP3_DP_VID_TIMING                                      :DWORD;                                             // 0x4DA8
  DP3_DP_VID_N                                           :DWORD;                                             // 0x4DA9
  DP3_DP_VID_M                                           :DWORD;                                             // 0x4DAA
  DP3_DP_LINK_FRAMING_CNTL                               :DWORD;                                             // 0x4DAB
  DP3_DP_HBR2_EYE_PATTERN                                :DWORD;                                             // 0x4DAC
  DP3_DP_VID_MSA_VBID                                    :DWORD;                                             // 0x4DAD
  DP3_DP_VID_INTERRUPT_CNTL                              :DWORD;                                             // 0x4DAE
  DP3_DP_DPHY_CNTL                                       :DWORD;                                             // 0x4DAF
  DP3_DP_DPHY_TRAINING_PATTERN_SEL                       :DWORD;                                             // 0x4DB0
  DP3_DP_DPHY_SYM0                                       :DWORD;                                             // 0x4DB1
  DP3_DP_DPHY_SYM1                                       :DWORD;                                             // 0x4DB2
  DP3_DP_DPHY_SYM2                                       :DWORD;                                             // 0x4DB3
  DP3_DP_DPHY_8B10B_CNTL                                 :DWORD;                                             // 0x4DB4
  DP3_DP_DPHY_PRBS_CNTL                                  :DWORD;                                             // 0x4DB5
  REG_4DB6                                               :DWORD;                                             // 0x4DB6
  DP3_DP_DPHY_CRC_EN                                     :DWORD;                                             // 0x4DB7
  DP3_DP_DPHY_CRC_CNTL                                   :DWORD;                                             // 0x4DB8
  DP3_DP_DPHY_CRC_RESULT                                 :DWORD;                                             // 0x4DB9
  DP3_DP_DPHY_CRC_MST_CNTL                               :DWORD;                                             // 0x4DBA
  DP3_DP_DPHY_CRC_MST_STATUS                             :DWORD;                                             // 0x4DBB
  DP3_DP_DPHY_FAST_TRAINING                              :DWORD;                                             // 0x4DBC
  DP3_DP_DPHY_FAST_TRAINING_STATUS                       :DWORD;                                             // 0x4DBD
  DP3_DP_MSA_V_TIMING_OVERRIDE1                          :DWORD;                                             // 0x4DBE
  DP3_DP_MSA_V_TIMING_OVERRIDE2                          :DWORD;                                             // 0x4DBF
  REG_4DC0_4DC2                                          :array[0..2] of DWORD;                              // 0x4DC0
  DP3_DP_SEC_CNTL                                        :DWORD;                                             // 0x4DC3
  DP3_DP_SEC_CNTL1                                       :DWORD;                                             // 0x4DC4
  DP3_DP_SEC_FRAMING1                                    :DWORD;                                             // 0x4DC5
  DP3_DP_SEC_FRAMING2                                    :DWORD;                                             // 0x4DC6
  DP3_DP_SEC_FRAMING3                                    :DWORD;                                             // 0x4DC7
  DP3_DP_SEC_FRAMING4                                    :DWORD;                                             // 0x4DC8
  DP3_DP_SEC_AUD_N                                       :DWORD;                                             // 0x4DC9
  DP3_DP_SEC_AUD_N_READBACK                              :DWORD;                                             // 0x4DCA
  DP3_DP_SEC_AUD_M                                       :DWORD;                                             // 0x4DCB
  DP3_DP_SEC_AUD_M_READBACK                              :DWORD;                                             // 0x4DCC
  DP3_DP_SEC_TIMESTAMP                                   :DWORD;                                             // 0x4DCD
  DP3_DP_SEC_PACKET_CNTL                                 :DWORD;                                             // 0x4DCE
  DP3_DP_MSE_RATE_CNTL                                   :DWORD;                                             // 0x4DCF
  REG_4DD0                                               :DWORD;                                             // 0x4DD0
  DP3_DP_MSE_RATE_UPDATE                                 :DWORD;                                             // 0x4DD1
  DP3_DP_MSE_SAT0                                        :DWORD;                                             // 0x4DD2
  DP3_DP_MSE_SAT1                                        :DWORD;                                             // 0x4DD3
  DP3_DP_MSE_SAT2                                        :DWORD;                                             // 0x4DD4
  DP3_DP_MSE_SAT_UPDATE                                  :DWORD;                                             // 0x4DD5
  DP3_DP_MSE_LINK_TIMING                                 :DWORD;                                             // 0x4DD6
  DP3_DP_MSE_MISC_CNTL                                   :DWORD;                                             // 0x4DD7
  DP3_DP_TEST_DEBUG_INDEX                                :DWORD;                                             // 0x4DD8
  DP3_DP_TEST_DEBUG_DATA                                 :DWORD;                                             // 0x4DD9
  DP3_DP_FE_TEST_DEBUG_INDEX                             :DWORD;                                             // 0x4DDA
  DP3_DP_FE_TEST_DEBUG_DATA                              :DWORD;                                             // 0x4DDB
  REG_4DDC_4DFF                                          :array[0..35] of DWORD;                             // 0x4DDC
  DIG4_DIG_FE_CNTL                                       :DWORD;                                             // 0x4E00
  DIG4_DIG_OUTPUT_CRC_CNTL                               :DWORD;                                             // 0x4E01
  DIG4_DIG_OUTPUT_CRC_RESULT                             :DWORD;                                             // 0x4E02
  DIG4_DIG_CLOCK_PATTERN                                 :DWORD;                                             // 0x4E03
  DIG4_DIG_TEST_PATTERN                                  :DWORD;                                             // 0x4E04
  DIG4_DIG_RANDOM_PATTERN_SEED                           :DWORD;                                             // 0x4E05
  DIG4_DIG_FIFO_STATUS                                   :DWORD;                                             // 0x4E06
  DIG4_DIG_DISPCLK_SWITCH_CNTL                           :DWORD;                                             // 0x4E07
  DIG4_DIG_DISPCLK_SWITCH_STATUS                         :DWORD;                                             // 0x4E08
  DIG4_HDMI_CONTROL                                      :DWORD;                                             // 0x4E09
  DIG4_HDMI_STATUS                                       :DWORD;                                             // 0x4E0A
  DIG4_HDMI_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4E0B
  DIG4_HDMI_ACR_PACKET_CONTROL                           :DWORD;                                             // 0x4E0C
  DIG4_HDMI_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4E0D
  DIG4_HDMI_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4E0E
  DIG4_HDMI_INFOFRAME_CONTROL1                           :DWORD;                                             // 0x4E0F
  DIG4_HDMI_GENERIC_PACKET_CONTROL0                      :DWORD;                                             // 0x4E10
  REG_4E11_4E12                                          :array[0..1] of DWORD;                              // 0x4E11
  DIG4_HDMI_GC                                           :DWORD;                                             // 0x4E13
  DIG4_AFMT_AUDIO_PACKET_CONTROL2                        :DWORD;                                             // 0x4E14
  DIG4_AFMT_ISRC1_0                                      :DWORD;                                             // 0x4E15
  DIG4_AFMT_ISRC1_1                                      :DWORD;                                             // 0x4E16
  DIG4_AFMT_ISRC1_2                                      :DWORD;                                             // 0x4E17
  DIG4_AFMT_ISRC1_3                                      :DWORD;                                             // 0x4E18
  DIG4_AFMT_ISRC1_4                                      :DWORD;                                             // 0x4E19
  DIG4_AFMT_ISRC2_0                                      :DWORD;                                             // 0x4E1A
  DIG4_AFMT_ISRC2_1                                      :DWORD;                                             // 0x4E1B
  DIG4_AFMT_ISRC2_2                                      :DWORD;                                             // 0x4E1C
  DIG4_AFMT_ISRC2_3                                      :DWORD;                                             // 0x4E1D
  DIG4_AFMT_AVI_INFO0                                    :DWORD;                                             // 0x4E1E
  DIG4_AFMT_AVI_INFO1                                    :DWORD;                                             // 0x4E1F
  DIG4_AFMT_AVI_INFO2                                    :DWORD;                                             // 0x4E20
  DIG4_AFMT_AVI_INFO3                                    :DWORD;                                             // 0x4E21
  DIG4_AFMT_MPEG_INFO0                                   :DWORD;                                             // 0x4E22
  DIG4_AFMT_MPEG_INFO1                                   :DWORD;                                             // 0x4E23
  DIG4_AFMT_GENERIC_HDR                                  :DWORD;                                             // 0x4E24
  DIG4_AFMT_GENERIC_0                                    :DWORD;                                             // 0x4E25
  DIG4_AFMT_GENERIC_1                                    :DWORD;                                             // 0x4E26
  DIG4_AFMT_GENERIC_2                                    :DWORD;                                             // 0x4E27
  DIG4_AFMT_GENERIC_3                                    :DWORD;                                             // 0x4E28
  DIG4_AFMT_GENERIC_4                                    :DWORD;                                             // 0x4E29
  DIG4_AFMT_GENERIC_5                                    :DWORD;                                             // 0x4E2A
  DIG4_AFMT_GENERIC_6                                    :DWORD;                                             // 0x4E2B
  DIG4_AFMT_GENERIC_7                                    :DWORD;                                             // 0x4E2C
  DIG4_HDMI_GENERIC_PACKET_CONTROL1                      :DWORD;                                             // 0x4E2D
  DIG4_HDMI_ACR_32_0                                     :DWORD;                                             // 0x4E2E
  DIG4_HDMI_ACR_32_1                                     :DWORD;                                             // 0x4E2F
  DIG4_HDMI_ACR_44_0                                     :DWORD;                                             // 0x4E30
  DIG4_HDMI_ACR_44_1                                     :DWORD;                                             // 0x4E31
  DIG4_HDMI_ACR_48_0                                     :DWORD;                                             // 0x4E32
  DIG4_HDMI_ACR_48_1                                     :DWORD;                                             // 0x4E33
  DIG4_HDMI_ACR_STATUS_0                                 :DWORD;                                             // 0x4E34
  DIG4_HDMI_ACR_STATUS_1                                 :DWORD;                                             // 0x4E35
  DIG4_AFMT_AUDIO_INFO0                                  :DWORD;                                             // 0x4E36
  DIG4_AFMT_AUDIO_INFO1                                  :DWORD;                                             // 0x4E37
  DIG4_AFMT_60958_0                                      :DWORD;                                             // 0x4E38
  DIG4_AFMT_60958_1                                      :DWORD;                                             // 0x4E39
  DIG4_AFMT_AUDIO_CRC_CONTROL                            :DWORD;                                             // 0x4E3A
  DIG4_AFMT_RAMP_CONTROL0                                :DWORD;                                             // 0x4E3B
  DIG4_AFMT_RAMP_CONTROL1                                :DWORD;                                             // 0x4E3C
  DIG4_AFMT_RAMP_CONTROL2                                :DWORD;                                             // 0x4E3D
  DIG4_AFMT_RAMP_CONTROL3                                :DWORD;                                             // 0x4E3E
  DIG4_AFMT_60958_2                                      :DWORD;                                             // 0x4E3F
  DIG4_AFMT_AUDIO_CRC_RESULT                             :DWORD;                                             // 0x4E40
  DIG4_AFMT_STATUS                                       :DWORD;                                             // 0x4E41
  DIG4_AFMT_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4E42
  DIG4_AFMT_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4E43
  DIG4_AFMT_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4E44
  DIG4_AFMT_AUDIO_SRC_CONTROL                            :DWORD;                                             // 0x4E45
  DIG4_AFMT_AUDIO_DBG_DTO_CNTL                           :DWORD;                                             // 0x4E46
  DIG4_DIG_BE_CNTL                                       :DWORD;                                             // 0x4E47
  DIG4_DIG_BE_EN_CNTL                                    :DWORD;                                             // 0x4E48
  REG_4E49_4E6A                                          :array[0..33] of DWORD;                             // 0x4E49
  DIG4_TMDS_CNTL                                         :DWORD;                                             // 0x4E6B
  DIG4_TMDS_CONTROL_CHAR                                 :DWORD;                                             // 0x4E6C
  DIG4_TMDS_CONTROL0_FEEDBACK                            :DWORD;                                             // 0x4E6D
  DIG4_TMDS_STEREOSYNC_CTL_SEL                           :DWORD;                                             // 0x4E6E
  DIG4_TMDS_SYNC_CHAR_PATTERN_0_1                        :DWORD;                                             // 0x4E6F
  DIG4_TMDS_SYNC_CHAR_PATTERN_2_3                        :DWORD;                                             // 0x4E70
  DIG4_TMDS_DEBUG                                        :DWORD;                                             // 0x4E71
  DIG4_TMDS_CTL_BITS                                     :DWORD;                                             // 0x4E72
  DIG4_TMDS_DCBALANCER_CONTROL                           :DWORD;                                             // 0x4E73
  REG_4E74                                               :DWORD;                                             // 0x4E74
  DIG4_TMDS_CTL0_1_GEN_CNTL                              :DWORD;                                             // 0x4E75
  DIG4_TMDS_CTL2_3_GEN_CNTL                              :DWORD;                                             // 0x4E76
  REG_4E77                                               :DWORD;                                             // 0x4E77
  DIG4_LVDS_DATA_CNTL                                    :DWORD;                                             // 0x4E78
  DIG4_DIG_LANE_ENABLE                                   :DWORD;                                             // 0x4E79
  DIG4_DIG_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x4E7A
  DIG4_DIG_TEST_DEBUG_DATA                               :DWORD;                                             // 0x4E7B
  DIG4_DIG_FE_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x4E7C
  DIG4_DIG_FE_TEST_DEBUG_DATA                            :DWORD;                                             // 0x4E7D
  REG_4E7E_4E9F                                          :array[0..33] of DWORD;                             // 0x4E7E
  DP4_DP_LINK_CNTL                                       :DWORD;                                             // 0x4EA0
  DP4_DP_PIXEL_FORMAT                                    :DWORD;                                             // 0x4EA1
  DP4_DP_MSA_COLORIMETRY                                 :DWORD;                                             // 0x4EA2
  DP4_DP_CONFIG                                          :DWORD;                                             // 0x4EA3
  DP4_DP_VID_STREAM_CNTL                                 :DWORD;                                             // 0x4EA4
  DP4_DP_STEER_FIFO                                      :DWORD;                                             // 0x4EA5
  DP4_DP_MSA_MISC                                        :DWORD;                                             // 0x4EA6
  REG_4EA7                                               :DWORD;                                             // 0x4EA7
  DP4_DP_VID_TIMING                                      :DWORD;                                             // 0x4EA8
  DP4_DP_VID_N                                           :DWORD;                                             // 0x4EA9
  DP4_DP_VID_M                                           :DWORD;                                             // 0x4EAA
  DP4_DP_LINK_FRAMING_CNTL                               :DWORD;                                             // 0x4EAB
  DP4_DP_HBR2_EYE_PATTERN                                :DWORD;                                             // 0x4EAC
  DP4_DP_VID_MSA_VBID                                    :DWORD;                                             // 0x4EAD
  DP4_DP_VID_INTERRUPT_CNTL                              :DWORD;                                             // 0x4EAE
  DP4_DP_DPHY_CNTL                                       :DWORD;                                             // 0x4EAF
  DP4_DP_DPHY_TRAINING_PATTERN_SEL                       :DWORD;                                             // 0x4EB0
  DP4_DP_DPHY_SYM0                                       :DWORD;                                             // 0x4EB1
  DP4_DP_DPHY_SYM1                                       :DWORD;                                             // 0x4EB2
  DP4_DP_DPHY_SYM2                                       :DWORD;                                             // 0x4EB3
  DP4_DP_DPHY_8B10B_CNTL                                 :DWORD;                                             // 0x4EB4
  DP4_DP_DPHY_PRBS_CNTL                                  :DWORD;                                             // 0x4EB5
  REG_4EB6                                               :DWORD;                                             // 0x4EB6
  DP4_DP_DPHY_CRC_EN                                     :DWORD;                                             // 0x4EB7
  DP4_DP_DPHY_CRC_CNTL                                   :DWORD;                                             // 0x4EB8
  DP4_DP_DPHY_CRC_RESULT                                 :DWORD;                                             // 0x4EB9
  DP4_DP_DPHY_CRC_MST_CNTL                               :DWORD;                                             // 0x4EBA
  DP4_DP_DPHY_CRC_MST_STATUS                             :DWORD;                                             // 0x4EBB
  DP4_DP_DPHY_FAST_TRAINING                              :DWORD;                                             // 0x4EBC
  DP4_DP_DPHY_FAST_TRAINING_STATUS                       :DWORD;                                             // 0x4EBD
  DP4_DP_MSA_V_TIMING_OVERRIDE1                          :DWORD;                                             // 0x4EBE
  DP4_DP_MSA_V_TIMING_OVERRIDE2                          :DWORD;                                             // 0x4EBF
  REG_4EC0_4EC2                                          :array[0..2] of DWORD;                              // 0x4EC0
  DP4_DP_SEC_CNTL                                        :DWORD;                                             // 0x4EC3
  DP4_DP_SEC_CNTL1                                       :DWORD;                                             // 0x4EC4
  DP4_DP_SEC_FRAMING1                                    :DWORD;                                             // 0x4EC5
  DP4_DP_SEC_FRAMING2                                    :DWORD;                                             // 0x4EC6
  DP4_DP_SEC_FRAMING3                                    :DWORD;                                             // 0x4EC7
  DP4_DP_SEC_FRAMING4                                    :DWORD;                                             // 0x4EC8
  DP4_DP_SEC_AUD_N                                       :DWORD;                                             // 0x4EC9
  DP4_DP_SEC_AUD_N_READBACK                              :DWORD;                                             // 0x4ECA
  DP4_DP_SEC_AUD_M                                       :DWORD;                                             // 0x4ECB
  DP4_DP_SEC_AUD_M_READBACK                              :DWORD;                                             // 0x4ECC
  DP4_DP_SEC_TIMESTAMP                                   :DWORD;                                             // 0x4ECD
  DP4_DP_SEC_PACKET_CNTL                                 :DWORD;                                             // 0x4ECE
  DP4_DP_MSE_RATE_CNTL                                   :DWORD;                                             // 0x4ECF
  REG_4ED0                                               :DWORD;                                             // 0x4ED0
  DP4_DP_MSE_RATE_UPDATE                                 :DWORD;                                             // 0x4ED1
  DP4_DP_MSE_SAT0                                        :DWORD;                                             // 0x4ED2
  DP4_DP_MSE_SAT1                                        :DWORD;                                             // 0x4ED3
  DP4_DP_MSE_SAT2                                        :DWORD;                                             // 0x4ED4
  DP4_DP_MSE_SAT_UPDATE                                  :DWORD;                                             // 0x4ED5
  DP4_DP_MSE_LINK_TIMING                                 :DWORD;                                             // 0x4ED6
  DP4_DP_MSE_MISC_CNTL                                   :DWORD;                                             // 0x4ED7
  DP4_DP_TEST_DEBUG_INDEX                                :DWORD;                                             // 0x4ED8
  DP4_DP_TEST_DEBUG_DATA                                 :DWORD;                                             // 0x4ED9
  DP4_DP_FE_TEST_DEBUG_INDEX                             :DWORD;                                             // 0x4EDA
  DP4_DP_FE_TEST_DEBUG_DATA                              :DWORD;                                             // 0x4EDB
  REG_4EDC_4EFF                                          :array[0..35] of DWORD;                             // 0x4EDC
  DIG5_DIG_FE_CNTL                                       :DWORD;                                             // 0x4F00
  DIG5_DIG_OUTPUT_CRC_CNTL                               :DWORD;                                             // 0x4F01
  DIG5_DIG_OUTPUT_CRC_RESULT                             :DWORD;                                             // 0x4F02
  DIG5_DIG_CLOCK_PATTERN                                 :DWORD;                                             // 0x4F03
  DIG5_DIG_TEST_PATTERN                                  :DWORD;                                             // 0x4F04
  DIG5_DIG_RANDOM_PATTERN_SEED                           :DWORD;                                             // 0x4F05
  DIG5_DIG_FIFO_STATUS                                   :DWORD;                                             // 0x4F06
  DIG5_DIG_DISPCLK_SWITCH_CNTL                           :DWORD;                                             // 0x4F07
  DIG5_DIG_DISPCLK_SWITCH_STATUS                         :DWORD;                                             // 0x4F08
  DIG5_HDMI_CONTROL                                      :DWORD;                                             // 0x4F09
  DIG5_HDMI_STATUS                                       :DWORD;                                             // 0x4F0A
  DIG5_HDMI_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4F0B
  DIG5_HDMI_ACR_PACKET_CONTROL                           :DWORD;                                             // 0x4F0C
  DIG5_HDMI_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4F0D
  DIG5_HDMI_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4F0E
  DIG5_HDMI_INFOFRAME_CONTROL1                           :DWORD;                                             // 0x4F0F
  DIG5_HDMI_GENERIC_PACKET_CONTROL0                      :DWORD;                                             // 0x4F10
  REG_4F11_4F12                                          :array[0..1] of DWORD;                              // 0x4F11
  DIG5_HDMI_GC                                           :DWORD;                                             // 0x4F13
  DIG5_AFMT_AUDIO_PACKET_CONTROL2                        :DWORD;                                             // 0x4F14
  DIG5_AFMT_ISRC1_0                                      :DWORD;                                             // 0x4F15
  DIG5_AFMT_ISRC1_1                                      :DWORD;                                             // 0x4F16
  DIG5_AFMT_ISRC1_2                                      :DWORD;                                             // 0x4F17
  DIG5_AFMT_ISRC1_3                                      :DWORD;                                             // 0x4F18
  DIG5_AFMT_ISRC1_4                                      :DWORD;                                             // 0x4F19
  DIG5_AFMT_ISRC2_0                                      :DWORD;                                             // 0x4F1A
  DIG5_AFMT_ISRC2_1                                      :DWORD;                                             // 0x4F1B
  DIG5_AFMT_ISRC2_2                                      :DWORD;                                             // 0x4F1C
  DIG5_AFMT_ISRC2_3                                      :DWORD;                                             // 0x4F1D
  DIG5_AFMT_AVI_INFO0                                    :DWORD;                                             // 0x4F1E
  DIG5_AFMT_AVI_INFO1                                    :DWORD;                                             // 0x4F1F
  DIG5_AFMT_AVI_INFO2                                    :DWORD;                                             // 0x4F20
  DIG5_AFMT_AVI_INFO3                                    :DWORD;                                             // 0x4F21
  DIG5_AFMT_MPEG_INFO0                                   :DWORD;                                             // 0x4F22
  DIG5_AFMT_MPEG_INFO1                                   :DWORD;                                             // 0x4F23
  DIG5_AFMT_GENERIC_HDR                                  :DWORD;                                             // 0x4F24
  DIG5_AFMT_GENERIC_0                                    :DWORD;                                             // 0x4F25
  DIG5_AFMT_GENERIC_1                                    :DWORD;                                             // 0x4F26
  DIG5_AFMT_GENERIC_2                                    :DWORD;                                             // 0x4F27
  DIG5_AFMT_GENERIC_3                                    :DWORD;                                             // 0x4F28
  DIG5_AFMT_GENERIC_4                                    :DWORD;                                             // 0x4F29
  DIG5_AFMT_GENERIC_5                                    :DWORD;                                             // 0x4F2A
  DIG5_AFMT_GENERIC_6                                    :DWORD;                                             // 0x4F2B
  DIG5_AFMT_GENERIC_7                                    :DWORD;                                             // 0x4F2C
  DIG5_HDMI_GENERIC_PACKET_CONTROL1                      :DWORD;                                             // 0x4F2D
  DIG5_HDMI_ACR_32_0                                     :DWORD;                                             // 0x4F2E
  DIG5_HDMI_ACR_32_1                                     :DWORD;                                             // 0x4F2F
  DIG5_HDMI_ACR_44_0                                     :DWORD;                                             // 0x4F30
  DIG5_HDMI_ACR_44_1                                     :DWORD;                                             // 0x4F31
  DIG5_HDMI_ACR_48_0                                     :DWORD;                                             // 0x4F32
  DIG5_HDMI_ACR_48_1                                     :DWORD;                                             // 0x4F33
  DIG5_HDMI_ACR_STATUS_0                                 :DWORD;                                             // 0x4F34
  DIG5_HDMI_ACR_STATUS_1                                 :DWORD;                                             // 0x4F35
  DIG5_AFMT_AUDIO_INFO0                                  :DWORD;                                             // 0x4F36
  DIG5_AFMT_AUDIO_INFO1                                  :DWORD;                                             // 0x4F37
  DIG5_AFMT_60958_0                                      :DWORD;                                             // 0x4F38
  DIG5_AFMT_60958_1                                      :DWORD;                                             // 0x4F39
  DIG5_AFMT_AUDIO_CRC_CONTROL                            :DWORD;                                             // 0x4F3A
  DIG5_AFMT_RAMP_CONTROL0                                :DWORD;                                             // 0x4F3B
  DIG5_AFMT_RAMP_CONTROL1                                :DWORD;                                             // 0x4F3C
  DIG5_AFMT_RAMP_CONTROL2                                :DWORD;                                             // 0x4F3D
  DIG5_AFMT_RAMP_CONTROL3                                :DWORD;                                             // 0x4F3E
  DIG5_AFMT_60958_2                                      :DWORD;                                             // 0x4F3F
  DIG5_AFMT_AUDIO_CRC_RESULT                             :DWORD;                                             // 0x4F40
  DIG5_AFMT_STATUS                                       :DWORD;                                             // 0x4F41
  DIG5_AFMT_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x4F42
  DIG5_AFMT_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x4F43
  DIG5_AFMT_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x4F44
  DIG5_AFMT_AUDIO_SRC_CONTROL                            :DWORD;                                             // 0x4F45
  DIG5_AFMT_AUDIO_DBG_DTO_CNTL                           :DWORD;                                             // 0x4F46
  DIG5_DIG_BE_CNTL                                       :DWORD;                                             // 0x4F47
  DIG5_DIG_BE_EN_CNTL                                    :DWORD;                                             // 0x4F48
  REG_4F49_4F6A                                          :array[0..33] of DWORD;                             // 0x4F49
  DIG5_TMDS_CNTL                                         :DWORD;                                             // 0x4F6B
  DIG5_TMDS_CONTROL_CHAR                                 :DWORD;                                             // 0x4F6C
  DIG5_TMDS_CONTROL0_FEEDBACK                            :DWORD;                                             // 0x4F6D
  DIG5_TMDS_STEREOSYNC_CTL_SEL                           :DWORD;                                             // 0x4F6E
  DIG5_TMDS_SYNC_CHAR_PATTERN_0_1                        :DWORD;                                             // 0x4F6F
  DIG5_TMDS_SYNC_CHAR_PATTERN_2_3                        :DWORD;                                             // 0x4F70
  DIG5_TMDS_DEBUG                                        :DWORD;                                             // 0x4F71
  DIG5_TMDS_CTL_BITS                                     :DWORD;                                             // 0x4F72
  DIG5_TMDS_DCBALANCER_CONTROL                           :DWORD;                                             // 0x4F73
  REG_4F74                                               :DWORD;                                             // 0x4F74
  DIG5_TMDS_CTL0_1_GEN_CNTL                              :DWORD;                                             // 0x4F75
  DIG5_TMDS_CTL2_3_GEN_CNTL                              :DWORD;                                             // 0x4F76
  REG_4F77                                               :DWORD;                                             // 0x4F77
  DIG5_LVDS_DATA_CNTL                                    :DWORD;                                             // 0x4F78
  DIG5_DIG_LANE_ENABLE                                   :DWORD;                                             // 0x4F79
  DIG5_DIG_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x4F7A
  DIG5_DIG_TEST_DEBUG_DATA                               :DWORD;                                             // 0x4F7B
  DIG5_DIG_FE_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x4F7C
  DIG5_DIG_FE_TEST_DEBUG_DATA                            :DWORD;                                             // 0x4F7D
  REG_4F7E_4F9F                                          :array[0..33] of DWORD;                             // 0x4F7E
  DP5_DP_LINK_CNTL                                       :DWORD;                                             // 0x4FA0
  DP5_DP_PIXEL_FORMAT                                    :DWORD;                                             // 0x4FA1
  DP5_DP_MSA_COLORIMETRY                                 :DWORD;                                             // 0x4FA2
  DP5_DP_CONFIG                                          :DWORD;                                             // 0x4FA3
  DP5_DP_VID_STREAM_CNTL                                 :DWORD;                                             // 0x4FA4
  DP5_DP_STEER_FIFO                                      :DWORD;                                             // 0x4FA5
  DP5_DP_MSA_MISC                                        :DWORD;                                             // 0x4FA6
  REG_4FA7                                               :DWORD;                                             // 0x4FA7
  DP5_DP_VID_TIMING                                      :DWORD;                                             // 0x4FA8
  DP5_DP_VID_N                                           :DWORD;                                             // 0x4FA9
  DP5_DP_VID_M                                           :DWORD;                                             // 0x4FAA
  DP5_DP_LINK_FRAMING_CNTL                               :DWORD;                                             // 0x4FAB
  DP5_DP_HBR2_EYE_PATTERN                                :DWORD;                                             // 0x4FAC
  DP5_DP_VID_MSA_VBID                                    :DWORD;                                             // 0x4FAD
  DP5_DP_VID_INTERRUPT_CNTL                              :DWORD;                                             // 0x4FAE
  DP5_DP_DPHY_CNTL                                       :DWORD;                                             // 0x4FAF
  DP5_DP_DPHY_TRAINING_PATTERN_SEL                       :DWORD;                                             // 0x4FB0
  DP5_DP_DPHY_SYM0                                       :DWORD;                                             // 0x4FB1
  DP5_DP_DPHY_SYM1                                       :DWORD;                                             // 0x4FB2
  DP5_DP_DPHY_SYM2                                       :DWORD;                                             // 0x4FB3
  DP5_DP_DPHY_8B10B_CNTL                                 :DWORD;                                             // 0x4FB4
  DP5_DP_DPHY_PRBS_CNTL                                  :DWORD;                                             // 0x4FB5
  REG_4FB6                                               :DWORD;                                             // 0x4FB6
  DP5_DP_DPHY_CRC_EN                                     :DWORD;                                             // 0x4FB7
  DP5_DP_DPHY_CRC_CNTL                                   :DWORD;                                             // 0x4FB8
  DP5_DP_DPHY_CRC_RESULT                                 :DWORD;                                             // 0x4FB9
  DP5_DP_DPHY_CRC_MST_CNTL                               :DWORD;                                             // 0x4FBA
  DP5_DP_DPHY_CRC_MST_STATUS                             :DWORD;                                             // 0x4FBB
  DP5_DP_DPHY_FAST_TRAINING                              :DWORD;                                             // 0x4FBC
  DP5_DP_DPHY_FAST_TRAINING_STATUS                       :DWORD;                                             // 0x4FBD
  DP5_DP_MSA_V_TIMING_OVERRIDE1                          :DWORD;                                             // 0x4FBE
  DP5_DP_MSA_V_TIMING_OVERRIDE2                          :DWORD;                                             // 0x4FBF
  REG_4FC0_4FC2                                          :array[0..2] of DWORD;                              // 0x4FC0
  DP5_DP_SEC_CNTL                                        :DWORD;                                             // 0x4FC3
  DP5_DP_SEC_CNTL1                                       :DWORD;                                             // 0x4FC4
  DP5_DP_SEC_FRAMING1                                    :DWORD;                                             // 0x4FC5
  DP5_DP_SEC_FRAMING2                                    :DWORD;                                             // 0x4FC6
  DP5_DP_SEC_FRAMING3                                    :DWORD;                                             // 0x4FC7
  DP5_DP_SEC_FRAMING4                                    :DWORD;                                             // 0x4FC8
  DP5_DP_SEC_AUD_N                                       :DWORD;                                             // 0x4FC9
  DP5_DP_SEC_AUD_N_READBACK                              :DWORD;                                             // 0x4FCA
  DP5_DP_SEC_AUD_M                                       :DWORD;                                             // 0x4FCB
  DP5_DP_SEC_AUD_M_READBACK                              :DWORD;                                             // 0x4FCC
  DP5_DP_SEC_TIMESTAMP                                   :DWORD;                                             // 0x4FCD
  DP5_DP_SEC_PACKET_CNTL                                 :DWORD;                                             // 0x4FCE
  DP5_DP_MSE_RATE_CNTL                                   :DWORD;                                             // 0x4FCF
  REG_4FD0                                               :DWORD;                                             // 0x4FD0
  DP5_DP_MSE_RATE_UPDATE                                 :DWORD;                                             // 0x4FD1
  DP5_DP_MSE_SAT0                                        :DWORD;                                             // 0x4FD2
  DP5_DP_MSE_SAT1                                        :DWORD;                                             // 0x4FD3
  DP5_DP_MSE_SAT2                                        :DWORD;                                             // 0x4FD4
  DP5_DP_MSE_SAT_UPDATE                                  :DWORD;                                             // 0x4FD5
  DP5_DP_MSE_LINK_TIMING                                 :DWORD;                                             // 0x4FD6
  DP5_DP_MSE_MISC_CNTL                                   :DWORD;                                             // 0x4FD7
  DP5_DP_TEST_DEBUG_INDEX                                :DWORD;                                             // 0x4FD8
  DP5_DP_TEST_DEBUG_DATA                                 :DWORD;                                             // 0x4FD9
  DP5_DP_FE_TEST_DEBUG_INDEX                             :DWORD;                                             // 0x4FDA
  DP5_DP_FE_TEST_DEBUG_DATA                              :DWORD;                                             // 0x4FDB
  REG_4FDC_53FF                                          :array[0..1059] of DWORD;                           // 0x4FDC
  DIG6_DIG_FE_CNTL                                       :DWORD;                                             // 0x5400
  DIG6_DIG_OUTPUT_CRC_CNTL                               :DWORD;                                             // 0x5401
  DIG6_DIG_OUTPUT_CRC_RESULT                             :DWORD;                                             // 0x5402
  DIG6_DIG_CLOCK_PATTERN                                 :DWORD;                                             // 0x5403
  DIG6_DIG_TEST_PATTERN                                  :DWORD;                                             // 0x5404
  DIG6_DIG_RANDOM_PATTERN_SEED                           :DWORD;                                             // 0x5405
  DIG6_DIG_FIFO_STATUS                                   :DWORD;                                             // 0x5406
  DIG6_DIG_DISPCLK_SWITCH_CNTL                           :DWORD;                                             // 0x5407
  DIG6_DIG_DISPCLK_SWITCH_STATUS                         :DWORD;                                             // 0x5408
  DIG6_HDMI_CONTROL                                      :DWORD;                                             // 0x5409
  DIG6_HDMI_STATUS                                       :DWORD;                                             // 0x540A
  DIG6_HDMI_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x540B
  DIG6_HDMI_ACR_PACKET_CONTROL                           :DWORD;                                             // 0x540C
  DIG6_HDMI_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x540D
  DIG6_HDMI_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x540E
  DIG6_HDMI_INFOFRAME_CONTROL1                           :DWORD;                                             // 0x540F
  DIG6_HDMI_GENERIC_PACKET_CONTROL0                      :DWORD;                                             // 0x5410
  REG_5411_5412                                          :array[0..1] of DWORD;                              // 0x5411
  DIG6_HDMI_GC                                           :DWORD;                                             // 0x5413
  DIG6_AFMT_AUDIO_PACKET_CONTROL2                        :DWORD;                                             // 0x5414
  DIG6_AFMT_ISRC1_0                                      :DWORD;                                             // 0x5415
  DIG6_AFMT_ISRC1_1                                      :DWORD;                                             // 0x5416
  DIG6_AFMT_ISRC1_2                                      :DWORD;                                             // 0x5417
  DIG6_AFMT_ISRC1_3                                      :DWORD;                                             // 0x5418
  DIG6_AFMT_ISRC1_4                                      :DWORD;                                             // 0x5419
  DIG6_AFMT_ISRC2_0                                      :DWORD;                                             // 0x541A
  DIG6_AFMT_ISRC2_1                                      :DWORD;                                             // 0x541B
  DIG6_AFMT_ISRC2_2                                      :DWORD;                                             // 0x541C
  DIG6_AFMT_ISRC2_3                                      :DWORD;                                             // 0x541D
  DIG6_AFMT_AVI_INFO0                                    :DWORD;                                             // 0x541E
  DIG6_AFMT_AVI_INFO1                                    :DWORD;                                             // 0x541F
  DIG6_AFMT_AVI_INFO2                                    :DWORD;                                             // 0x5420
  DIG6_AFMT_AVI_INFO3                                    :DWORD;                                             // 0x5421
  DIG6_AFMT_MPEG_INFO0                                   :DWORD;                                             // 0x5422
  DIG6_AFMT_MPEG_INFO1                                   :DWORD;                                             // 0x5423
  DIG6_AFMT_GENERIC_HDR                                  :DWORD;                                             // 0x5424
  DIG6_AFMT_GENERIC_0                                    :DWORD;                                             // 0x5425
  DIG6_AFMT_GENERIC_1                                    :DWORD;                                             // 0x5426
  DIG6_AFMT_GENERIC_2                                    :DWORD;                                             // 0x5427
  DIG6_AFMT_GENERIC_3                                    :DWORD;                                             // 0x5428
  DIG6_AFMT_GENERIC_4                                    :DWORD;                                             // 0x5429
  DIG6_AFMT_GENERIC_5                                    :DWORD;                                             // 0x542A
  DIG6_AFMT_GENERIC_6                                    :DWORD;                                             // 0x542B
  DIG6_AFMT_GENERIC_7                                    :DWORD;                                             // 0x542C
  DIG6_HDMI_GENERIC_PACKET_CONTROL1                      :DWORD;                                             // 0x542D
  DIG6_HDMI_ACR_32_0                                     :DWORD;                                             // 0x542E
  DIG6_HDMI_ACR_32_1                                     :DWORD;                                             // 0x542F
  DIG6_HDMI_ACR_44_0                                     :DWORD;                                             // 0x5430
  DIG6_HDMI_ACR_44_1                                     :DWORD;                                             // 0x5431
  DIG6_HDMI_ACR_48_0                                     :DWORD;                                             // 0x5432
  DIG6_HDMI_ACR_48_1                                     :DWORD;                                             // 0x5433
  DIG6_HDMI_ACR_STATUS_0                                 :DWORD;                                             // 0x5434
  DIG6_HDMI_ACR_STATUS_1                                 :DWORD;                                             // 0x5435
  DIG6_AFMT_AUDIO_INFO0                                  :DWORD;                                             // 0x5436
  DIG6_AFMT_AUDIO_INFO1                                  :DWORD;                                             // 0x5437
  DIG6_AFMT_60958_0                                      :DWORD;                                             // 0x5438
  DIG6_AFMT_60958_1                                      :DWORD;                                             // 0x5439
  DIG6_AFMT_AUDIO_CRC_CONTROL                            :DWORD;                                             // 0x543A
  DIG6_AFMT_RAMP_CONTROL0                                :DWORD;                                             // 0x543B
  DIG6_AFMT_RAMP_CONTROL1                                :DWORD;                                             // 0x543C
  DIG6_AFMT_RAMP_CONTROL2                                :DWORD;                                             // 0x543D
  DIG6_AFMT_RAMP_CONTROL3                                :DWORD;                                             // 0x543E
  DIG6_AFMT_60958_2                                      :DWORD;                                             // 0x543F
  DIG6_AFMT_AUDIO_CRC_RESULT                             :DWORD;                                             // 0x5440
  DIG6_AFMT_STATUS                                       :DWORD;                                             // 0x5441
  DIG6_AFMT_AUDIO_PACKET_CONTROL                         :DWORD;                                             // 0x5442
  DIG6_AFMT_VBI_PACKET_CONTROL                           :DWORD;                                             // 0x5443
  DIG6_AFMT_INFOFRAME_CONTROL0                           :DWORD;                                             // 0x5444
  DIG6_AFMT_AUDIO_SRC_CONTROL                            :DWORD;                                             // 0x5445
  DIG6_AFMT_AUDIO_DBG_DTO_CNTL                           :DWORD;                                             // 0x5446
  DIG6_DIG_BE_CNTL                                       :DWORD;                                             // 0x5447
  DIG6_DIG_BE_EN_CNTL                                    :DWORD;                                             // 0x5448
  REG_5449_546A                                          :array[0..33] of DWORD;                             // 0x5449
  DIG6_TMDS_CNTL                                         :DWORD;                                             // 0x546B
  DIG6_TMDS_CONTROL_CHAR                                 :DWORD;                                             // 0x546C
  DIG6_TMDS_CONTROL0_FEEDBACK                            :DWORD;                                             // 0x546D
  DIG6_TMDS_STEREOSYNC_CTL_SEL                           :DWORD;                                             // 0x546E
  DIG6_TMDS_SYNC_CHAR_PATTERN_0_1                        :DWORD;                                             // 0x546F
  DIG6_TMDS_SYNC_CHAR_PATTERN_2_3                        :DWORD;                                             // 0x5470
  DIG6_TMDS_DEBUG                                        :DWORD;                                             // 0x5471
  DIG6_TMDS_CTL_BITS                                     :DWORD;                                             // 0x5472
  DIG6_TMDS_DCBALANCER_CONTROL                           :DWORD;                                             // 0x5473
  REG_5474                                               :DWORD;                                             // 0x5474
  DIG6_TMDS_CTL0_1_GEN_CNTL                              :DWORD;                                             // 0x5475
  DIG6_TMDS_CTL2_3_GEN_CNTL                              :DWORD;                                             // 0x5476
  REG_5477                                               :DWORD;                                             // 0x5477
  DIG6_LVDS_DATA_CNTL                                    :DWORD;                                             // 0x5478
  DIG6_DIG_LANE_ENABLE                                   :DWORD;                                             // 0x5479
  DIG6_DIG_TEST_DEBUG_INDEX                              :DWORD;                                             // 0x547A
  DIG6_DIG_TEST_DEBUG_DATA                               :DWORD;                                             // 0x547B
  DIG6_DIG_FE_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x547C
  DIG6_DIG_FE_TEST_DEBUG_DATA                            :DWORD;                                             // 0x547D
  REG_547E_549F                                          :array[0..33] of DWORD;                             // 0x547E
  DP6_DP_LINK_CNTL                                       :DWORD;                                             // 0x54A0
  DP6_DP_PIXEL_FORMAT                                    :DWORD;                                             // 0x54A1
  DP6_DP_MSA_COLORIMETRY                                 :DWORD;                                             // 0x54A2
  DP6_DP_CONFIG                                          :DWORD;                                             // 0x54A3
  DP6_DP_VID_STREAM_CNTL                                 :DWORD;                                             // 0x54A4
  DP6_DP_STEER_FIFO                                      :DWORD;                                             // 0x54A5
  DP6_DP_MSA_MISC                                        :DWORD;                                             // 0x54A6
  REG_54A7                                               :DWORD;                                             // 0x54A7
  DP6_DP_VID_TIMING                                      :DWORD;                                             // 0x54A8
  DP6_DP_VID_N                                           :DWORD;                                             // 0x54A9
  DP6_DP_VID_M                                           :DWORD;                                             // 0x54AA
  DP6_DP_LINK_FRAMING_CNTL                               :DWORD;                                             // 0x54AB
  DP6_DP_HBR2_EYE_PATTERN                                :DWORD;                                             // 0x54AC
  DP6_DP_VID_MSA_VBID                                    :DWORD;                                             // 0x54AD
  DP6_DP_VID_INTERRUPT_CNTL                              :DWORD;                                             // 0x54AE
  DP6_DP_DPHY_CNTL                                       :DWORD;                                             // 0x54AF
  DP6_DP_DPHY_TRAINING_PATTERN_SEL                       :DWORD;                                             // 0x54B0
  DP6_DP_DPHY_SYM0                                       :DWORD;                                             // 0x54B1
  DP6_DP_DPHY_SYM1                                       :DWORD;                                             // 0x54B2
  DP6_DP_DPHY_SYM2                                       :DWORD;                                             // 0x54B3
  DP6_DP_DPHY_8B10B_CNTL                                 :DWORD;                                             // 0x54B4
  DP6_DP_DPHY_PRBS_CNTL                                  :DWORD;                                             // 0x54B5
  REG_54B6                                               :DWORD;                                             // 0x54B6
  DP6_DP_DPHY_CRC_EN                                     :DWORD;                                             // 0x54B7
  DP6_DP_DPHY_CRC_CNTL                                   :DWORD;                                             // 0x54B8
  DP6_DP_DPHY_CRC_RESULT                                 :DWORD;                                             // 0x54B9
  DP6_DP_DPHY_CRC_MST_CNTL                               :DWORD;                                             // 0x54BA
  DP6_DP_DPHY_CRC_MST_STATUS                             :DWORD;                                             // 0x54BB
  DP6_DP_DPHY_FAST_TRAINING                              :DWORD;                                             // 0x54BC
  DP6_DP_DPHY_FAST_TRAINING_STATUS                       :DWORD;                                             // 0x54BD
  DP6_DP_MSA_V_TIMING_OVERRIDE1                          :DWORD;                                             // 0x54BE
  DP6_DP_MSA_V_TIMING_OVERRIDE2                          :DWORD;                                             // 0x54BF
  REG_54C0_54C2                                          :array[0..2] of DWORD;                              // 0x54C0
  DP6_DP_SEC_CNTL                                        :DWORD;                                             // 0x54C3
  DP6_DP_SEC_CNTL1                                       :DWORD;                                             // 0x54C4
  DP6_DP_SEC_FRAMING1                                    :DWORD;                                             // 0x54C5
  DP6_DP_SEC_FRAMING2                                    :DWORD;                                             // 0x54C6
  DP6_DP_SEC_FRAMING3                                    :DWORD;                                             // 0x54C7
  DP6_DP_SEC_FRAMING4                                    :DWORD;                                             // 0x54C8
  DP6_DP_SEC_AUD_N                                       :DWORD;                                             // 0x54C9
  DP6_DP_SEC_AUD_N_READBACK                              :DWORD;                                             // 0x54CA
  DP6_DP_SEC_AUD_M                                       :DWORD;                                             // 0x54CB
  DP6_DP_SEC_AUD_M_READBACK                              :DWORD;                                             // 0x54CC
  DP6_DP_SEC_TIMESTAMP                                   :DWORD;                                             // 0x54CD
  DP6_DP_SEC_PACKET_CNTL                                 :DWORD;                                             // 0x54CE
  DP6_DP_MSE_RATE_CNTL                                   :DWORD;                                             // 0x54CF
  REG_54D0                                               :DWORD;                                             // 0x54D0
  DP6_DP_MSE_RATE_UPDATE                                 :DWORD;                                             // 0x54D1
  DP6_DP_MSE_SAT0                                        :DWORD;                                             // 0x54D2
  DP6_DP_MSE_SAT1                                        :DWORD;                                             // 0x54D3
  DP6_DP_MSE_SAT2                                        :DWORD;                                             // 0x54D4
  DP6_DP_MSE_SAT_UPDATE                                  :DWORD;                                             // 0x54D5
  DP6_DP_MSE_LINK_TIMING                                 :DWORD;                                             // 0x54D6
  DP6_DP_MSE_MISC_CNTL                                   :DWORD;                                             // 0x54D7
  DP6_DP_TEST_DEBUG_INDEX                                :DWORD;                                             // 0x54D8
  DP6_DP_TEST_DEBUG_DATA                                 :DWORD;                                             // 0x54D9
  DP6_DP_FE_TEST_DEBUG_INDEX                             :DWORD;                                             // 0x54DA
  DP6_DP_FE_TEST_DEBUG_DATA                              :DWORD;                                             // 0x54DB
  REG_54DC_599F                                          :array[0..1219] of DWORD;                           // 0x54DC
  DC_PERFMON10_PERFCOUNTER_CNTL                          :DWORD;                                             // 0x59A0
  DC_PERFMON10_PERFCOUNTER_STATE                         :DWORD;                                             // 0x59A1
  DC_PERFMON10_PERFMON_CVALUE_INT_MISC                   :DWORD;                                             // 0x59A2
  DC_PERFMON10_PERFMON_CNTL                              :DWORD;                                             // 0x59A3
  DC_PERFMON10_PERFMON_CVALUE_LOW                        :DWORD;                                             // 0x59A4
  DC_PERFMON10_PERFMON_HI                                :DWORD;                                             // 0x59A5
  DC_PERFMON10_PERFMON_LOW                               :DWORD;                                             // 0x59A6
  DC_PERFMON10_PERFMON_TEST_DEBUG_INDEX                  :DWORD;                                             // 0x59A7
  DC_PERFMON10_PERFMON_TEST_DEBUG_DATA                   :DWORD;                                             // 0x59A8
  REG_59A9                                               :DWORD;                                             // 0x59A9
  DC_PERFMON10_PERFMON_CNTL2                             :DWORD;                                             // 0x59AA
  REG_59AB_59BF                                          :array[0..20] of DWORD;                             // 0x59AB
  AZF0STREAM8_AZALIA_STREAM_INDEX                        :DWORD;                                             // 0x59C0
  AZF0STREAM8_AZALIA_STREAM_DATA                         :DWORD;                                             // 0x59C1
  AZF0STREAM9_AZALIA_STREAM_INDEX                        :DWORD;                                             // 0x59C2
  AZF0STREAM9_AZALIA_STREAM_DATA                         :DWORD;                                             // 0x59C3
  AZF0STREAM10_AZALIA_STREAM_INDEX                       :DWORD;                                             // 0x59C4
  AZF0STREAM10_AZALIA_STREAM_DATA                        :DWORD;                                             // 0x59C5
  AZF0STREAM11_AZALIA_STREAM_INDEX                       :DWORD;                                             // 0x59C6
  AZF0STREAM11_AZALIA_STREAM_DATA                        :DWORD;                                             // 0x59C7
  AZF0STREAM12_AZALIA_STREAM_INDEX                       :DWORD;                                             // 0x59C8
  AZF0STREAM12_AZALIA_STREAM_DATA                        :DWORD;                                             // 0x59C9
  AZF0STREAM13_AZALIA_STREAM_INDEX                       :DWORD;                                             // 0x59CA
  AZF0STREAM13_AZALIA_STREAM_DATA                        :DWORD;                                             // 0x59CB
  AZF0STREAM14_AZALIA_STREAM_INDEX                       :DWORD;                                             // 0x59CC
  AZF0STREAM14_AZALIA_STREAM_DATA                        :DWORD;                                             // 0x59CD
  AZF0STREAM15_AZALIA_STREAM_INDEX                       :DWORD;                                             // 0x59CE
  AZF0STREAM15_AZALIA_STREAM_DATA                        :DWORD;                                             // 0x59CF
  REG_59D0_59D3                                          :array[0..3] of DWORD;                              // 0x59D0
  AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                   :TAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX;             // 0x59D4
  AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                    :TAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA;              // 0x59D5
  REG_59D6_59D7                                          :array[0..1] of DWORD;                              // 0x59D6
  AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD;                                             // 0x59D8
  AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD;                                             // 0x59D9
  REG_59DA_59DB                                          :array[0..1] of DWORD;                              // 0x59DA
  AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD;                                             // 0x59DC
  AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD;                                             // 0x59DD
  REG_59DE_59DF                                          :array[0..1] of DWORD;                              // 0x59DE
  AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD;                                             // 0x59E0
  AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD;                                             // 0x59E1
  REG_59E2_59E3                                          :array[0..1] of DWORD;                              // 0x59E2
  AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD;                                             // 0x59E4
  AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD;                                             // 0x59E5
  REG_59E6_59E7                                          :array[0..1] of DWORD;                              // 0x59E6
  AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD;                                             // 0x59E8
  AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD;                                             // 0x59E9
  REG_59EA_59EB                                          :array[0..1] of DWORD;                              // 0x59EA
  AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD;                                             // 0x59EC
  AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD;                                             // 0x59ED
  REG_59EE_59EF                                          :array[0..1] of DWORD;                              // 0x59EE
  AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD;                                             // 0x59F0
  AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD;                                             // 0x59F1
  REG_59F2_5A83                                          :array[0..145] of DWORD;                            // 0x59F2
  DCRX_PHY_MACRO_CNTL_RESERVED0                          :TDCRX_PHY_MACRO_CNTL_RESERVED0;                    // 0x5A84
  DCRX_PHY_MACRO_CNTL_RESERVED1                          :TDCRX_PHY_MACRO_CNTL_RESERVED1;                    // 0x5A85
  DCRX_PHY_MACRO_CNTL_RESERVED2                          :TDCRX_PHY_MACRO_CNTL_RESERVED2;                    // 0x5A86
  DCRX_PHY_MACRO_CNTL_RESERVED3                          :TDCRX_PHY_MACRO_CNTL_RESERVED3;                    // 0x5A87
  DCRX_PHY_MACRO_CNTL_RESERVED4                          :TDCRX_PHY_MACRO_CNTL_RESERVED4;                    // 0x5A88
  DCRX_PHY_MACRO_CNTL_RESERVED5                          :TDCRX_PHY_MACRO_CNTL_RESERVED5;                    // 0x5A89
  DCRX_PHY_MACRO_CNTL_RESERVED6                          :TDCRX_PHY_MACRO_CNTL_RESERVED6;                    // 0x5A8A
  DCRX_PHY_MACRO_CNTL_RESERVED7                          :TDCRX_PHY_MACRO_CNTL_RESERVED7;                    // 0x5A8B
  DCRX_PHY_MACRO_CNTL_RESERVED8                          :TDCRX_PHY_MACRO_CNTL_RESERVED8;                    // 0x5A8C
  DCRX_PHY_MACRO_CNTL_RESERVED9                          :TDCRX_PHY_MACRO_CNTL_RESERVED9;                    // 0x5A8D
  DCRX_PHY_MACRO_CNTL_RESERVED10                         :TDCRX_PHY_MACRO_CNTL_RESERVED10;                   // 0x5A8E
  DCRX_PHY_MACRO_CNTL_RESERVED11                         :TDCRX_PHY_MACRO_CNTL_RESERVED11;                   // 0x5A8F
  DCRX_PHY_MACRO_CNTL_RESERVED12                         :TDCRX_PHY_MACRO_CNTL_RESERVED12;                   // 0x5A90
  DCRX_PHY_MACRO_CNTL_RESERVED13                         :TDCRX_PHY_MACRO_CNTL_RESERVED13;                   // 0x5A91
  DCRX_PHY_MACRO_CNTL_RESERVED14                         :TDCRX_PHY_MACRO_CNTL_RESERVED14;                   // 0x5A92
  DCRX_PHY_MACRO_CNTL_RESERVED15                         :TDCRX_PHY_MACRO_CNTL_RESERVED15;                   // 0x5A93
  DCRX_PHY_MACRO_CNTL_RESERVED16                         :TDCRX_PHY_MACRO_CNTL_RESERVED16;                   // 0x5A94
  DCRX_PHY_MACRO_CNTL_RESERVED17                         :TDCRX_PHY_MACRO_CNTL_RESERVED17;                   // 0x5A95
  DCRX_PHY_MACRO_CNTL_RESERVED18                         :TDCRX_PHY_MACRO_CNTL_RESERVED18;                   // 0x5A96
  DCRX_PHY_MACRO_CNTL_RESERVED19                         :TDCRX_PHY_MACRO_CNTL_RESERVED19;                   // 0x5A97
  DCRX_PHY_MACRO_CNTL_RESERVED20                         :TDCRX_PHY_MACRO_CNTL_RESERVED20;                   // 0x5A98
  DCRX_PHY_MACRO_CNTL_RESERVED21                         :TDCRX_PHY_MACRO_CNTL_RESERVED21;                   // 0x5A99
  DCRX_PHY_MACRO_CNTL_RESERVED22                         :TDCRX_PHY_MACRO_CNTL_RESERVED22;                   // 0x5A9A
  DCRX_PHY_MACRO_CNTL_RESERVED23                         :TDCRX_PHY_MACRO_CNTL_RESERVED23;                   // 0x5A9B
  DCRX_PHY_MACRO_CNTL_RESERVED24                         :TDCRX_PHY_MACRO_CNTL_RESERVED24;                   // 0x5A9C
  DCRX_PHY_MACRO_CNTL_RESERVED25                         :TDCRX_PHY_MACRO_CNTL_RESERVED25;                   // 0x5A9D
  DCRX_PHY_MACRO_CNTL_RESERVED26                         :TDCRX_PHY_MACRO_CNTL_RESERVED26;                   // 0x5A9E
  DCRX_PHY_MACRO_CNTL_RESERVED27                         :TDCRX_PHY_MACRO_CNTL_RESERVED27;                   // 0x5A9F
  DCRX_PHY_MACRO_CNTL_RESERVED28                         :TDCRX_PHY_MACRO_CNTL_RESERVED28;                   // 0x5AA0
  DCRX_PHY_MACRO_CNTL_RESERVED29                         :TDCRX_PHY_MACRO_CNTL_RESERVED29;                   // 0x5AA1
  DCRX_PHY_MACRO_CNTL_RESERVED30                         :TDCRX_PHY_MACRO_CNTL_RESERVED30;                   // 0x5AA2
  DCRX_PHY_MACRO_CNTL_RESERVED31                         :TDCRX_PHY_MACRO_CNTL_RESERVED31;                   // 0x5AA3
  DCRX_PHY_MACRO_CNTL_RESERVED32                         :TDCRX_PHY_MACRO_CNTL_RESERVED32;                   // 0x5AA4
  DCRX_PHY_MACRO_CNTL_RESERVED33                         :TDCRX_PHY_MACRO_CNTL_RESERVED33;                   // 0x5AA5
  DCRX_PHY_MACRO_CNTL_RESERVED34                         :TDCRX_PHY_MACRO_CNTL_RESERVED34;                   // 0x5AA6
  DCRX_PHY_MACRO_CNTL_RESERVED35                         :TDCRX_PHY_MACRO_CNTL_RESERVED35;                   // 0x5AA7
  DCRX_PHY_MACRO_CNTL_RESERVED36                         :TDCRX_PHY_MACRO_CNTL_RESERVED36;                   // 0x5AA8
  DCRX_PHY_MACRO_CNTL_RESERVED37                         :TDCRX_PHY_MACRO_CNTL_RESERVED37;                   // 0x5AA9
  DCRX_PHY_MACRO_CNTL_RESERVED38                         :TDCRX_PHY_MACRO_CNTL_RESERVED38;                   // 0x5AAA
  DCRX_PHY_MACRO_CNTL_RESERVED39                         :TDCRX_PHY_MACRO_CNTL_RESERVED39;                   // 0x5AAB
  DCRX_PHY_MACRO_CNTL_RESERVED40                         :TDCRX_PHY_MACRO_CNTL_RESERVED40;                   // 0x5AAC
  DCRX_PHY_MACRO_CNTL_RESERVED41                         :TDCRX_PHY_MACRO_CNTL_RESERVED41;                   // 0x5AAD
  DCRX_PHY_MACRO_CNTL_RESERVED42                         :TDCRX_PHY_MACRO_CNTL_RESERVED42;                   // 0x5AAE
  DCRX_PHY_MACRO_CNTL_RESERVED43                         :TDCRX_PHY_MACRO_CNTL_RESERVED43;                   // 0x5AAF
  DCRX_PHY_MACRO_CNTL_RESERVED44                         :TDCRX_PHY_MACRO_CNTL_RESERVED44;                   // 0x5AB0
  DCRX_PHY_MACRO_CNTL_RESERVED45                         :TDCRX_PHY_MACRO_CNTL_RESERVED45;                   // 0x5AB1
  DCRX_PHY_MACRO_CNTL_RESERVED46                         :TDCRX_PHY_MACRO_CNTL_RESERVED46;                   // 0x5AB2
  DCRX_PHY_MACRO_CNTL_RESERVED47                         :TDCRX_PHY_MACRO_CNTL_RESERVED47;                   // 0x5AB3
  DCRX_PHY_MACRO_CNTL_RESERVED48                         :TDCRX_PHY_MACRO_CNTL_RESERVED48;                   // 0x5AB4
  DCRX_PHY_MACRO_CNTL_RESERVED49                         :TDCRX_PHY_MACRO_CNTL_RESERVED49;                   // 0x5AB5
  DCRX_PHY_MACRO_CNTL_RESERVED50                         :TDCRX_PHY_MACRO_CNTL_RESERVED50;                   // 0x5AB6
  DCRX_PHY_MACRO_CNTL_RESERVED51                         :TDCRX_PHY_MACRO_CNTL_RESERVED51;                   // 0x5AB7
  DCRX_PHY_MACRO_CNTL_RESERVED52                         :TDCRX_PHY_MACRO_CNTL_RESERVED52;                   // 0x5AB8
  DCRX_PHY_MACRO_CNTL_RESERVED53                         :TDCRX_PHY_MACRO_CNTL_RESERVED53;                   // 0x5AB9
  DCRX_PHY_MACRO_CNTL_RESERVED54                         :TDCRX_PHY_MACRO_CNTL_RESERVED54;                   // 0x5ABA
  DCRX_PHY_MACRO_CNTL_RESERVED55                         :TDCRX_PHY_MACRO_CNTL_RESERVED55;                   // 0x5ABB
  DCRX_PHY_MACRO_CNTL_RESERVED56                         :TDCRX_PHY_MACRO_CNTL_RESERVED56;                   // 0x5ABC
  DCRX_PHY_MACRO_CNTL_RESERVED57                         :TDCRX_PHY_MACRO_CNTL_RESERVED57;                   // 0x5ABD
  DCRX_PHY_MACRO_CNTL_RESERVED58                         :TDCRX_PHY_MACRO_CNTL_RESERVED58;                   // 0x5ABE
  DCRX_PHY_MACRO_CNTL_RESERVED59                         :TDCRX_PHY_MACRO_CNTL_RESERVED59;                   // 0x5ABF
  DCRX_PHY_MACRO_CNTL_RESERVED60                         :TDCRX_PHY_MACRO_CNTL_RESERVED60;                   // 0x5AC0
  DCRX_PHY_MACRO_CNTL_RESERVED61                         :TDCRX_PHY_MACRO_CNTL_RESERVED61;                   // 0x5AC1
  DCRX_PHY_MACRO_CNTL_RESERVED62                         :TDCRX_PHY_MACRO_CNTL_RESERVED62;                   // 0x5AC2
  DCRX_PHY_MACRO_CNTL_RESERVED63                         :TDCRX_PHY_MACRO_CNTL_RESERVED63;                   // 0x5AC3
  DCRX_PHY_MACRO_CNTL_RESERVED64                         :TDCRX_PHY_MACRO_CNTL_RESERVED64;                   // 0x5AC4
  DCRX_PHY_MACRO_CNTL_RESERVED65                         :TDCRX_PHY_MACRO_CNTL_RESERVED65;                   // 0x5AC5
  DCRX_PHY_MACRO_CNTL_RESERVED66                         :TDCRX_PHY_MACRO_CNTL_RESERVED66;                   // 0x5AC6
  DCRX_PHY_MACRO_CNTL_RESERVED67                         :TDCRX_PHY_MACRO_CNTL_RESERVED67;                   // 0x5AC7
  DCRX_PHY_MACRO_CNTL_RESERVED68                         :TDCRX_PHY_MACRO_CNTL_RESERVED68;                   // 0x5AC8
  DCRX_PHY_MACRO_CNTL_RESERVED69                         :TDCRX_PHY_MACRO_CNTL_RESERVED69;                   // 0x5AC9
  DCRX_PHY_MACRO_CNTL_RESERVED70                         :TDCRX_PHY_MACRO_CNTL_RESERVED70;                   // 0x5ACA
  DCRX_PHY_MACRO_CNTL_RESERVED71                         :TDCRX_PHY_MACRO_CNTL_RESERVED71;                   // 0x5ACB
  DCRX_PHY_MACRO_CNTL_RESERVED72                         :TDCRX_PHY_MACRO_CNTL_RESERVED72;                   // 0x5ACC
  DCRX_PHY_MACRO_CNTL_RESERVED73                         :TDCRX_PHY_MACRO_CNTL_RESERVED73;                   // 0x5ACD
  DCRX_PHY_MACRO_CNTL_RESERVED74                         :TDCRX_PHY_MACRO_CNTL_RESERVED74;                   // 0x5ACE
  DCRX_PHY_MACRO_CNTL_RESERVED75                         :TDCRX_PHY_MACRO_CNTL_RESERVED75;                   // 0x5ACF
  DCRX_PHY_MACRO_CNTL_RESERVED76                         :TDCRX_PHY_MACRO_CNTL_RESERVED76;                   // 0x5AD0
  DCRX_PHY_MACRO_CNTL_RESERVED77                         :TDCRX_PHY_MACRO_CNTL_RESERVED77;                   // 0x5AD1
  DCRX_PHY_MACRO_CNTL_RESERVED78                         :TDCRX_PHY_MACRO_CNTL_RESERVED78;                   // 0x5AD2
  DCRX_PHY_MACRO_CNTL_RESERVED79                         :TDCRX_PHY_MACRO_CNTL_RESERVED79;                   // 0x5AD3
  DCRX_PHY_MACRO_CNTL_RESERVED80                         :TDCRX_PHY_MACRO_CNTL_RESERVED80;                   // 0x5AD4
  DCRX_PHY_MACRO_CNTL_RESERVED81                         :TDCRX_PHY_MACRO_CNTL_RESERVED81;                   // 0x5AD5
  DCRX_PHY_MACRO_CNTL_RESERVED82                         :TDCRX_PHY_MACRO_CNTL_RESERVED82;                   // 0x5AD6
  DCRX_PHY_MACRO_CNTL_RESERVED83                         :TDCRX_PHY_MACRO_CNTL_RESERVED83;                   // 0x5AD7
  DCRX_PHY_MACRO_CNTL_RESERVED84                         :TDCRX_PHY_MACRO_CNTL_RESERVED84;                   // 0x5AD8
  DCRX_PHY_MACRO_CNTL_RESERVED85                         :TDCRX_PHY_MACRO_CNTL_RESERVED85;                   // 0x5AD9
  DCRX_PHY_MACRO_CNTL_RESERVED86                         :TDCRX_PHY_MACRO_CNTL_RESERVED86;                   // 0x5ADA
  DCRX_PHY_MACRO_CNTL_RESERVED87                         :TDCRX_PHY_MACRO_CNTL_RESERVED87;                   // 0x5ADB
  DCRX_PHY_MACRO_CNTL_RESERVED88                         :TDCRX_PHY_MACRO_CNTL_RESERVED88;                   // 0x5ADC
  DCRX_PHY_MACRO_CNTL_RESERVED89                         :TDCRX_PHY_MACRO_CNTL_RESERVED89;                   // 0x5ADD
  DCRX_PHY_MACRO_CNTL_RESERVED90                         :TDCRX_PHY_MACRO_CNTL_RESERVED90;                   // 0x5ADE
  DCRX_PHY_MACRO_CNTL_RESERVED91                         :TDCRX_PHY_MACRO_CNTL_RESERVED91;                   // 0x5ADF
  DCRX_PHY_MACRO_CNTL_RESERVED92                         :TDCRX_PHY_MACRO_CNTL_RESERVED92;                   // 0x5AE0
  DCRX_PHY_MACRO_CNTL_RESERVED93                         :TDCRX_PHY_MACRO_CNTL_RESERVED93;                   // 0x5AE1
  DCRX_PHY_MACRO_CNTL_RESERVED94                         :TDCRX_PHY_MACRO_CNTL_RESERVED94;                   // 0x5AE2
  DCRX_PHY_MACRO_CNTL_RESERVED95                         :TDCRX_PHY_MACRO_CNTL_RESERVED95;                   // 0x5AE3
  DCRX_PHY_MACRO_CNTL_RESERVED96                         :TDCRX_PHY_MACRO_CNTL_RESERVED96;                   // 0x5AE4
  DCRX_PHY_MACRO_CNTL_RESERVED97                         :TDCRX_PHY_MACRO_CNTL_RESERVED97;                   // 0x5AE5
  DCRX_PHY_MACRO_CNTL_RESERVED98                         :TDCRX_PHY_MACRO_CNTL_RESERVED98;                   // 0x5AE6
  DCRX_PHY_MACRO_CNTL_RESERVED99                         :TDCRX_PHY_MACRO_CNTL_RESERVED99;                   // 0x5AE7
  DCRX_PHY_MACRO_CNTL_RESERVED100                        :TDCRX_PHY_MACRO_CNTL_RESERVED100;                  // 0x5AE8
  DCRX_PHY_MACRO_CNTL_RESERVED101                        :TDCRX_PHY_MACRO_CNTL_RESERVED101;                  // 0x5AE9
  DCRX_PHY_MACRO_CNTL_RESERVED102                        :TDCRX_PHY_MACRO_CNTL_RESERVED102;                  // 0x5AEA
  DCRX_PHY_MACRO_CNTL_RESERVED103                        :TDCRX_PHY_MACRO_CNTL_RESERVED103;                  // 0x5AEB
  DCRX_PHY_MACRO_CNTL_RESERVED104                        :TDCRX_PHY_MACRO_CNTL_RESERVED104;                  // 0x5AEC
  DCRX_PHY_MACRO_CNTL_RESERVED105                        :TDCRX_PHY_MACRO_CNTL_RESERVED105;                  // 0x5AED
  DCRX_PHY_MACRO_CNTL_RESERVED106                        :TDCRX_PHY_MACRO_CNTL_RESERVED106;                  // 0x5AEE
  DCRX_PHY_MACRO_CNTL_RESERVED107                        :TDCRX_PHY_MACRO_CNTL_RESERVED107;                  // 0x5AEF
  DCRX_PHY_MACRO_CNTL_RESERVED108                        :TDCRX_PHY_MACRO_CNTL_RESERVED108;                  // 0x5AF0
  DCRX_PHY_MACRO_CNTL_RESERVED109                        :TDCRX_PHY_MACRO_CNTL_RESERVED109;                  // 0x5AF1
  DCRX_PHY_MACRO_CNTL_RESERVED110                        :TDCRX_PHY_MACRO_CNTL_RESERVED110;                  // 0x5AF2
  DCRX_PHY_MACRO_CNTL_RESERVED111                        :TDCRX_PHY_MACRO_CNTL_RESERVED111;                  // 0x5AF3
  DCRX_PHY_MACRO_CNTL_RESERVED112                        :TDCRX_PHY_MACRO_CNTL_RESERVED112;                  // 0x5AF4
  DCRX_PHY_MACRO_CNTL_RESERVED113                        :TDCRX_PHY_MACRO_CNTL_RESERVED113;                  // 0x5AF5
  DCRX_PHY_MACRO_CNTL_RESERVED114                        :TDCRX_PHY_MACRO_CNTL_RESERVED114;                  // 0x5AF6
  DCRX_PHY_MACRO_CNTL_RESERVED115                        :TDCRX_PHY_MACRO_CNTL_RESERVED115;                  // 0x5AF7
  DCRX_PHY_MACRO_CNTL_RESERVED116                        :TDCRX_PHY_MACRO_CNTL_RESERVED116;                  // 0x5AF8
  DCRX_PHY_MACRO_CNTL_RESERVED117                        :TDCRX_PHY_MACRO_CNTL_RESERVED117;                  // 0x5AF9
  DCRX_PHY_MACRO_CNTL_RESERVED118                        :TDCRX_PHY_MACRO_CNTL_RESERVED118;                  // 0x5AFA
  DCRX_PHY_MACRO_CNTL_RESERVED119                        :TDCRX_PHY_MACRO_CNTL_RESERVED119;                  // 0x5AFB
  DCRX_PHY_MACRO_CNTL_RESERVED120                        :TDCRX_PHY_MACRO_CNTL_RESERVED120;                  // 0x5AFC
  DCRX_PHY_MACRO_CNTL_RESERVED121                        :TDCRX_PHY_MACRO_CNTL_RESERVED121;                  // 0x5AFD
  DCRX_PHY_MACRO_CNTL_RESERVED122                        :TDCRX_PHY_MACRO_CNTL_RESERVED122;                  // 0x5AFE
  DCRX_PHY_MACRO_CNTL_RESERVED123                        :TDCRX_PHY_MACRO_CNTL_RESERVED123;                  // 0x5AFF
  DCRX_PHY_MACRO_CNTL_RESERVED124                        :TDCRX_PHY_MACRO_CNTL_RESERVED124;                  // 0x5B00
  DCRX_PHY_MACRO_CNTL_RESERVED125                        :TDCRX_PHY_MACRO_CNTL_RESERVED125;                  // 0x5B01
  DCRX_PHY_MACRO_CNTL_RESERVED126                        :TDCRX_PHY_MACRO_CNTL_RESERVED126;                  // 0x5B02
  DCRX_PHY_MACRO_CNTL_RESERVED127                        :TDCRX_PHY_MACRO_CNTL_RESERVED127;                  // 0x5B03
  DCRX_PHY_MACRO_CNTL_RESERVED128                        :TDCRX_PHY_MACRO_CNTL_RESERVED128;                  // 0x5B04
  DCRX_PHY_MACRO_CNTL_RESERVED129                        :TDCRX_PHY_MACRO_CNTL_RESERVED129;                  // 0x5B05
  DCRX_PHY_MACRO_CNTL_RESERVED130                        :TDCRX_PHY_MACRO_CNTL_RESERVED130;                  // 0x5B06
  DCRX_PHY_MACRO_CNTL_RESERVED131                        :TDCRX_PHY_MACRO_CNTL_RESERVED131;                  // 0x5B07
  DCRX_PHY_MACRO_CNTL_RESERVED132                        :TDCRX_PHY_MACRO_CNTL_RESERVED132;                  // 0x5B08
  DCRX_PHY_MACRO_CNTL_RESERVED133                        :TDCRX_PHY_MACRO_CNTL_RESERVED133;                  // 0x5B09
  DCRX_PHY_MACRO_CNTL_RESERVED134                        :TDCRX_PHY_MACRO_CNTL_RESERVED134;                  // 0x5B0A
  DCRX_PHY_MACRO_CNTL_RESERVED135                        :TDCRX_PHY_MACRO_CNTL_RESERVED135;                  // 0x5B0B
  DCRX_PHY_MACRO_CNTL_RESERVED136                        :TDCRX_PHY_MACRO_CNTL_RESERVED136;                  // 0x5B0C
  DCRX_PHY_MACRO_CNTL_RESERVED137                        :TDCRX_PHY_MACRO_CNTL_RESERVED137;                  // 0x5B0D
  DCRX_PHY_MACRO_CNTL_RESERVED138                        :TDCRX_PHY_MACRO_CNTL_RESERVED138;                  // 0x5B0E
  DCRX_PHY_MACRO_CNTL_RESERVED139                        :TDCRX_PHY_MACRO_CNTL_RESERVED139;                  // 0x5B0F
  DCRX_PHY_MACRO_CNTL_RESERVED140                        :TDCRX_PHY_MACRO_CNTL_RESERVED140;                  // 0x5B10
  DCRX_PHY_MACRO_CNTL_RESERVED141                        :TDCRX_PHY_MACRO_CNTL_RESERVED141;                  // 0x5B11
  DCRX_PHY_MACRO_CNTL_RESERVED142                        :TDCRX_PHY_MACRO_CNTL_RESERVED142;                  // 0x5B12
  DCRX_PHY_MACRO_CNTL_RESERVED143                        :TDCRX_PHY_MACRO_CNTL_RESERVED143;                  // 0x5B13
  DCRX_PHY_MACRO_CNTL_RESERVED144                        :TDCRX_PHY_MACRO_CNTL_RESERVED144;                  // 0x5B14
  DCRX_PHY_MACRO_CNTL_RESERVED145                        :TDCRX_PHY_MACRO_CNTL_RESERVED145;                  // 0x5B15
  DCRX_PHY_MACRO_CNTL_RESERVED146                        :TDCRX_PHY_MACRO_CNTL_RESERVED146;                  // 0x5B16
  DCRX_PHY_MACRO_CNTL_RESERVED147                        :TDCRX_PHY_MACRO_CNTL_RESERVED147;                  // 0x5B17
  DCRX_PHY_MACRO_CNTL_RESERVED148                        :TDCRX_PHY_MACRO_CNTL_RESERVED148;                  // 0x5B18
  DCRX_PHY_MACRO_CNTL_RESERVED149                        :TDCRX_PHY_MACRO_CNTL_RESERVED149;                  // 0x5B19
  DCRX_PHY_MACRO_CNTL_RESERVED150                        :TDCRX_PHY_MACRO_CNTL_RESERVED150;                  // 0x5B1A
  DCRX_PHY_MACRO_CNTL_RESERVED151                        :TDCRX_PHY_MACRO_CNTL_RESERVED151;                  // 0x5B1B
  DCRX_PHY_MACRO_CNTL_RESERVED152                        :TDCRX_PHY_MACRO_CNTL_RESERVED152;                  // 0x5B1C
  DCRX_PHY_MACRO_CNTL_RESERVED153                        :TDCRX_PHY_MACRO_CNTL_RESERVED153;                  // 0x5B1D
  DCRX_PHY_MACRO_CNTL_RESERVED154                        :TDCRX_PHY_MACRO_CNTL_RESERVED154;                  // 0x5B1E
  DCRX_PHY_MACRO_CNTL_RESERVED155                        :TDCRX_PHY_MACRO_CNTL_RESERVED155;                  // 0x5B1F
  DCRX_PHY_MACRO_CNTL_RESERVED156                        :TDCRX_PHY_MACRO_CNTL_RESERVED156;                  // 0x5B20
  DCRX_PHY_MACRO_CNTL_RESERVED157                        :TDCRX_PHY_MACRO_CNTL_RESERVED157;                  // 0x5B21
  DCRX_PHY_MACRO_CNTL_RESERVED158                        :TDCRX_PHY_MACRO_CNTL_RESERVED158;                  // 0x5B22
  DCRX_PHY_MACRO_CNTL_RESERVED159                        :TDCRX_PHY_MACRO_CNTL_RESERVED159;                  // 0x5B23
  DCRX_PHY_MACRO_CNTL_RESERVED160                        :TDCRX_PHY_MACRO_CNTL_RESERVED160;                  // 0x5B24
  DCRX_PHY_MACRO_CNTL_RESERVED161                        :TDCRX_PHY_MACRO_CNTL_RESERVED161;                  // 0x5B25
  DCRX_PHY_MACRO_CNTL_RESERVED162                        :TDCRX_PHY_MACRO_CNTL_RESERVED162;                  // 0x5B26
  DCRX_PHY_MACRO_CNTL_RESERVED163                        :TDCRX_PHY_MACRO_CNTL_RESERVED163;                  // 0x5B27
  DCRX_PHY_MACRO_CNTL_RESERVED164                        :TDCRX_PHY_MACRO_CNTL_RESERVED164;                  // 0x5B28
  DCRX_PHY_MACRO_CNTL_RESERVED165                        :TDCRX_PHY_MACRO_CNTL_RESERVED165;                  // 0x5B29
  DCRX_PHY_MACRO_CNTL_RESERVED166                        :TDCRX_PHY_MACRO_CNTL_RESERVED166;                  // 0x5B2A
  DCRX_PHY_MACRO_CNTL_RESERVED167                        :TDCRX_PHY_MACRO_CNTL_RESERVED167;                  // 0x5B2B
  DCRX_PHY_MACRO_CNTL_RESERVED168                        :TDCRX_PHY_MACRO_CNTL_RESERVED168;                  // 0x5B2C
  DCRX_PHY_MACRO_CNTL_RESERVED169                        :TDCRX_PHY_MACRO_CNTL_RESERVED169;                  // 0x5B2D
  DCRX_PHY_MACRO_CNTL_RESERVED170                        :TDCRX_PHY_MACRO_CNTL_RESERVED170;                  // 0x5B2E
  DCRX_PHY_MACRO_CNTL_RESERVED171                        :TDCRX_PHY_MACRO_CNTL_RESERVED171;                  // 0x5B2F
  DCRX_PHY_MACRO_CNTL_RESERVED172                        :TDCRX_PHY_MACRO_CNTL_RESERVED172;                  // 0x5B30
  DCRX_PHY_MACRO_CNTL_RESERVED173                        :TDCRX_PHY_MACRO_CNTL_RESERVED173;                  // 0x5B31
  DCRX_PHY_MACRO_CNTL_RESERVED174                        :TDCRX_PHY_MACRO_CNTL_RESERVED174;                  // 0x5B32
  DCRX_PHY_MACRO_CNTL_RESERVED175                        :TDCRX_PHY_MACRO_CNTL_RESERVED175;                  // 0x5B33
  DCRX_PHY_MACRO_CNTL_RESERVED176                        :TDCRX_PHY_MACRO_CNTL_RESERVED176;                  // 0x5B34
  DCRX_PHY_MACRO_CNTL_RESERVED177                        :TDCRX_PHY_MACRO_CNTL_RESERVED177;                  // 0x5B35
  DCRX_PHY_MACRO_CNTL_RESERVED178                        :TDCRX_PHY_MACRO_CNTL_RESERVED178;                  // 0x5B36
  DCRX_PHY_MACRO_CNTL_RESERVED179                        :TDCRX_PHY_MACRO_CNTL_RESERVED179;                  // 0x5B37
  DCRX_PHY_MACRO_CNTL_RESERVED180                        :TDCRX_PHY_MACRO_CNTL_RESERVED180;                  // 0x5B38
  DCRX_PHY_MACRO_CNTL_RESERVED181                        :TDCRX_PHY_MACRO_CNTL_RESERVED181;                  // 0x5B39
  DCRX_PHY_MACRO_CNTL_RESERVED182                        :TDCRX_PHY_MACRO_CNTL_RESERVED182;                  // 0x5B3A
  DCRX_PHY_MACRO_CNTL_RESERVED183                        :TDCRX_PHY_MACRO_CNTL_RESERVED183;                  // 0x5B3B
  DCRX_PHY_MACRO_CNTL_RESERVED184                        :TDCRX_PHY_MACRO_CNTL_RESERVED184;                  // 0x5B3C
  DCRX_PHY_MACRO_CNTL_RESERVED185                        :TDCRX_PHY_MACRO_CNTL_RESERVED185;                  // 0x5B3D
  DCRX_PHY_MACRO_CNTL_RESERVED186                        :TDCRX_PHY_MACRO_CNTL_RESERVED186;                  // 0x5B3E
  DCRX_PHY_MACRO_CNTL_RESERVED187                        :TDCRX_PHY_MACRO_CNTL_RESERVED187;                  // 0x5B3F
  DCRX_PHY_MACRO_CNTL_RESERVED188                        :TDCRX_PHY_MACRO_CNTL_RESERVED188;                  // 0x5B40
  DCRX_PHY_MACRO_CNTL_RESERVED189                        :TDCRX_PHY_MACRO_CNTL_RESERVED189;                  // 0x5B41
  DCRX_PHY_MACRO_CNTL_RESERVED190                        :TDCRX_PHY_MACRO_CNTL_RESERVED190;                  // 0x5B42
  DCRX_PHY_MACRO_CNTL_RESERVED191                        :TDCRX_PHY_MACRO_CNTL_RESERVED191;                  // 0x5B43
  DCRX_PHY_MACRO_CNTL_RESERVED192                        :TDCRX_PHY_MACRO_CNTL_RESERVED192;                  // 0x5B44
  DCRX_PHY_MACRO_CNTL_RESERVED193                        :TDCRX_PHY_MACRO_CNTL_RESERVED193;                  // 0x5B45
  DCRX_PHY_MACRO_CNTL_RESERVED194                        :TDCRX_PHY_MACRO_CNTL_RESERVED194;                  // 0x5B46
  DCRX_PHY_MACRO_CNTL_RESERVED195                        :TDCRX_PHY_MACRO_CNTL_RESERVED195;                  // 0x5B47
  DCRX_PHY_MACRO_CNTL_RESERVED196                        :TDCRX_PHY_MACRO_CNTL_RESERVED196;                  // 0x5B48
  DCRX_PHY_MACRO_CNTL_RESERVED197                        :TDCRX_PHY_MACRO_CNTL_RESERVED197;                  // 0x5B49
  DCRX_PHY_MACRO_CNTL_RESERVED198                        :TDCRX_PHY_MACRO_CNTL_RESERVED198;                  // 0x5B4A
  DCRX_PHY_MACRO_CNTL_RESERVED199                        :TDCRX_PHY_MACRO_CNTL_RESERVED199;                  // 0x5B4B
  DCRX_PHY_MACRO_CNTL_RESERVED200                        :TDCRX_PHY_MACRO_CNTL_RESERVED200;                  // 0x5B4C
  DCRX_PHY_MACRO_CNTL_RESERVED201                        :TDCRX_PHY_MACRO_CNTL_RESERVED201;                  // 0x5B4D
  DCRX_PHY_MACRO_CNTL_RESERVED202                        :TDCRX_PHY_MACRO_CNTL_RESERVED202;                  // 0x5B4E
  DCRX_PHY_MACRO_CNTL_RESERVED203                        :TDCRX_PHY_MACRO_CNTL_RESERVED203;                  // 0x5B4F
  DCRX_PHY_MACRO_CNTL_RESERVED204                        :TDCRX_PHY_MACRO_CNTL_RESERVED204;                  // 0x5B50
  DCRX_PHY_MACRO_CNTL_RESERVED205                        :TDCRX_PHY_MACRO_CNTL_RESERVED205;                  // 0x5B51
  DCRX_PHY_MACRO_CNTL_RESERVED206                        :TDCRX_PHY_MACRO_CNTL_RESERVED206;                  // 0x5B52
  DCRX_PHY_MACRO_CNTL_RESERVED207                        :TDCRX_PHY_MACRO_CNTL_RESERVED207;                  // 0x5B53
  DCRX_PHY_MACRO_CNTL_RESERVED208                        :TDCRX_PHY_MACRO_CNTL_RESERVED208;                  // 0x5B54
  DCRX_PHY_MACRO_CNTL_RESERVED209                        :TDCRX_PHY_MACRO_CNTL_RESERVED209;                  // 0x5B55
  DCRX_PHY_MACRO_CNTL_RESERVED210                        :TDCRX_PHY_MACRO_CNTL_RESERVED210;                  // 0x5B56
  DCRX_PHY_MACRO_CNTL_RESERVED211                        :TDCRX_PHY_MACRO_CNTL_RESERVED211;                  // 0x5B57
  DCRX_PHY_MACRO_CNTL_RESERVED212                        :TDCRX_PHY_MACRO_CNTL_RESERVED212;                  // 0x5B58
  DCRX_PHY_MACRO_CNTL_RESERVED213                        :TDCRX_PHY_MACRO_CNTL_RESERVED213;                  // 0x5B59
  DCRX_PHY_MACRO_CNTL_RESERVED214                        :TDCRX_PHY_MACRO_CNTL_RESERVED214;                  // 0x5B5A
  DCRX_PHY_MACRO_CNTL_RESERVED215                        :TDCRX_PHY_MACRO_CNTL_RESERVED215;                  // 0x5B5B
  DCRX_PHY_MACRO_CNTL_RESERVED216                        :TDCRX_PHY_MACRO_CNTL_RESERVED216;                  // 0x5B5C
  DCRX_PHY_MACRO_CNTL_RESERVED217                        :TDCRX_PHY_MACRO_CNTL_RESERVED217;                  // 0x5B5D
  DCRX_PHY_MACRO_CNTL_RESERVED218                        :TDCRX_PHY_MACRO_CNTL_RESERVED218;                  // 0x5B5E
  DCRX_PHY_MACRO_CNTL_RESERVED219                        :TDCRX_PHY_MACRO_CNTL_RESERVED219;                  // 0x5B5F
  DCRX_PHY_MACRO_CNTL_RESERVED220                        :TDCRX_PHY_MACRO_CNTL_RESERVED220;                  // 0x5B60
  DCRX_PHY_MACRO_CNTL_RESERVED221                        :TDCRX_PHY_MACRO_CNTL_RESERVED221;                  // 0x5B61
  DCRX_PHY_MACRO_CNTL_RESERVED222                        :TDCRX_PHY_MACRO_CNTL_RESERVED222;                  // 0x5B62
  DCRX_PHY_MACRO_CNTL_RESERVED223                        :TDCRX_PHY_MACRO_CNTL_RESERVED223;                  // 0x5B63
  DCRX_PHY_MACRO_CNTL_RESERVED224                        :TDCRX_PHY_MACRO_CNTL_RESERVED224;                  // 0x5B64
  DCRX_PHY_MACRO_CNTL_RESERVED225                        :TDCRX_PHY_MACRO_CNTL_RESERVED225;                  // 0x5B65
  DCRX_PHY_MACRO_CNTL_RESERVED226                        :TDCRX_PHY_MACRO_CNTL_RESERVED226;                  // 0x5B66
  DCRX_PHY_MACRO_CNTL_RESERVED227                        :TDCRX_PHY_MACRO_CNTL_RESERVED227;                  // 0x5B67
  DCRX_PHY_MACRO_CNTL_RESERVED228                        :TDCRX_PHY_MACRO_CNTL_RESERVED228;                  // 0x5B68
  DCRX_PHY_MACRO_CNTL_RESERVED229                        :TDCRX_PHY_MACRO_CNTL_RESERVED229;                  // 0x5B69
  DCRX_PHY_MACRO_CNTL_RESERVED230                        :TDCRX_PHY_MACRO_CNTL_RESERVED230;                  // 0x5B6A
  DCRX_PHY_MACRO_CNTL_RESERVED231                        :TDCRX_PHY_MACRO_CNTL_RESERVED231;                  // 0x5B6B
  DCRX_PHY_MACRO_CNTL_RESERVED232                        :TDCRX_PHY_MACRO_CNTL_RESERVED232;                  // 0x5B6C
  DCRX_PHY_MACRO_CNTL_RESERVED233                        :TDCRX_PHY_MACRO_CNTL_RESERVED233;                  // 0x5B6D
  DCRX_PHY_MACRO_CNTL_RESERVED234                        :TDCRX_PHY_MACRO_CNTL_RESERVED234;                  // 0x5B6E
  DCRX_PHY_MACRO_CNTL_RESERVED235                        :TDCRX_PHY_MACRO_CNTL_RESERVED235;                  // 0x5B6F
  DCRX_PHY_MACRO_CNTL_RESERVED236                        :TDCRX_PHY_MACRO_CNTL_RESERVED236;                  // 0x5B70
  DCRX_PHY_MACRO_CNTL_RESERVED237                        :TDCRX_PHY_MACRO_CNTL_RESERVED237;                  // 0x5B71
  DCRX_PHY_MACRO_CNTL_RESERVED238                        :TDCRX_PHY_MACRO_CNTL_RESERVED238;                  // 0x5B72
  DCRX_PHY_MACRO_CNTL_RESERVED239                        :TDCRX_PHY_MACRO_CNTL_RESERVED239;                  // 0x5B73
  DCRX_PHY_MACRO_CNTL_RESERVED240                        :TDCRX_PHY_MACRO_CNTL_RESERVED240;                  // 0x5B74
  DCRX_PHY_MACRO_CNTL_RESERVED241                        :TDCRX_PHY_MACRO_CNTL_RESERVED241;                  // 0x5B75
  DCRX_PHY_MACRO_CNTL_RESERVED242                        :TDCRX_PHY_MACRO_CNTL_RESERVED242;                  // 0x5B76
  DCRX_PHY_MACRO_CNTL_RESERVED243                        :TDCRX_PHY_MACRO_CNTL_RESERVED243;                  // 0x5B77
  DCRX_PHY_MACRO_CNTL_RESERVED244                        :TDCRX_PHY_MACRO_CNTL_RESERVED244;                  // 0x5B78
  DCRX_PHY_MACRO_CNTL_RESERVED245                        :TDCRX_PHY_MACRO_CNTL_RESERVED245;                  // 0x5B79
  DCRX_PHY_MACRO_CNTL_RESERVED246                        :TDCRX_PHY_MACRO_CNTL_RESERVED246;                  // 0x5B7A
  DCRX_PHY_MACRO_CNTL_RESERVED247                        :TDCRX_PHY_MACRO_CNTL_RESERVED247;                  // 0x5B7B
  DCRX_PHY_MACRO_CNTL_RESERVED248                        :TDCRX_PHY_MACRO_CNTL_RESERVED248;                  // 0x5B7C
  DCRX_PHY_MACRO_CNTL_RESERVED249                        :TDCRX_PHY_MACRO_CNTL_RESERVED249;                  // 0x5B7D
  DCRX_PHY_MACRO_CNTL_RESERVED250                        :TDCRX_PHY_MACRO_CNTL_RESERVED250;                  // 0x5B7E
  DCRX_PHY_MACRO_CNTL_RESERVED251                        :TDCRX_PHY_MACRO_CNTL_RESERVED251;                  // 0x5B7F
  DCRX_PHY_MACRO_CNTL_RESERVED252                        :TDCRX_PHY_MACRO_CNTL_RESERVED252;                  // 0x5B80
  DCRX_PHY_MACRO_CNTL_RESERVED253                        :TDCRX_PHY_MACRO_CNTL_RESERVED253;                  // 0x5B81
  DCRX_PHY_MACRO_CNTL_RESERVED254                        :TDCRX_PHY_MACRO_CNTL_RESERVED254;                  // 0x5B82
  DCRX_PHY_MACRO_CNTL_RESERVED255                        :TDCRX_PHY_MACRO_CNTL_RESERVED255;                  // 0x5B83
  DCRX_PHY_MACRO_CNTL_RESERVED256                        :TDCRX_PHY_MACRO_CNTL_RESERVED256;                  // 0x5B84
  DCRX_PHY_MACRO_CNTL_RESERVED257                        :TDCRX_PHY_MACRO_CNTL_RESERVED257;                  // 0x5B85
  DCRX_PHY_MACRO_CNTL_RESERVED258                        :TDCRX_PHY_MACRO_CNTL_RESERVED258;                  // 0x5B86
  DCRX_PHY_MACRO_CNTL_RESERVED259                        :TDCRX_PHY_MACRO_CNTL_RESERVED259;                  // 0x5B87
  DCRX_PHY_MACRO_CNTL_RESERVED260                        :TDCRX_PHY_MACRO_CNTL_RESERVED260;                  // 0x5B88
  DCRX_PHY_MACRO_CNTL_RESERVED261                        :TDCRX_PHY_MACRO_CNTL_RESERVED261;                  // 0x5B89
  DCRX_PHY_MACRO_CNTL_RESERVED262                        :TDCRX_PHY_MACRO_CNTL_RESERVED262;                  // 0x5B8A
  DCRX_PHY_MACRO_CNTL_RESERVED263                        :TDCRX_PHY_MACRO_CNTL_RESERVED263;                  // 0x5B8B
  DCRX_PHY_MACRO_CNTL_RESERVED264                        :TDCRX_PHY_MACRO_CNTL_RESERVED264;                  // 0x5B8C
  DCRX_PHY_MACRO_CNTL_RESERVED265                        :TDCRX_PHY_MACRO_CNTL_RESERVED265;                  // 0x5B8D
  DCRX_PHY_MACRO_CNTL_RESERVED266                        :TDCRX_PHY_MACRO_CNTL_RESERVED266;                  // 0x5B8E
  DCRX_PHY_MACRO_CNTL_RESERVED267                        :TDCRX_PHY_MACRO_CNTL_RESERVED267;                  // 0x5B8F
  DCRX_PHY_MACRO_CNTL_RESERVED268                        :TDCRX_PHY_MACRO_CNTL_RESERVED268;                  // 0x5B90
  DCRX_PHY_MACRO_CNTL_RESERVED269                        :TDCRX_PHY_MACRO_CNTL_RESERVED269;                  // 0x5B91
  DCRX_PHY_MACRO_CNTL_RESERVED270                        :TDCRX_PHY_MACRO_CNTL_RESERVED270;                  // 0x5B92
  DCRX_PHY_MACRO_CNTL_RESERVED271                        :TDCRX_PHY_MACRO_CNTL_RESERVED271;                  // 0x5B93
  DCRX_PHY_MACRO_CNTL_RESERVED272                        :TDCRX_PHY_MACRO_CNTL_RESERVED272;                  // 0x5B94
  DCRX_PHY_MACRO_CNTL_RESERVED273                        :TDCRX_PHY_MACRO_CNTL_RESERVED273;                  // 0x5B95
  DCRX_PHY_MACRO_CNTL_RESERVED274                        :TDCRX_PHY_MACRO_CNTL_RESERVED274;                  // 0x5B96
  DCRX_PHY_MACRO_CNTL_RESERVED275                        :TDCRX_PHY_MACRO_CNTL_RESERVED275;                  // 0x5B97
  DCRX_PHY_MACRO_CNTL_RESERVED276                        :TDCRX_PHY_MACRO_CNTL_RESERVED276;                  // 0x5B98
  DCRX_PHY_MACRO_CNTL_RESERVED277                        :TDCRX_PHY_MACRO_CNTL_RESERVED277;                  // 0x5B99
  DCRX_PHY_MACRO_CNTL_RESERVED278                        :TDCRX_PHY_MACRO_CNTL_RESERVED278;                  // 0x5B9A
  DCRX_PHY_MACRO_CNTL_RESERVED279                        :TDCRX_PHY_MACRO_CNTL_RESERVED279;                  // 0x5B9B
  DCRX_PHY_MACRO_CNTL_RESERVED280                        :TDCRX_PHY_MACRO_CNTL_RESERVED280;                  // 0x5B9C
  DCRX_PHY_MACRO_CNTL_RESERVED281                        :TDCRX_PHY_MACRO_CNTL_RESERVED281;                  // 0x5B9D
  DCRX_PHY_MACRO_CNTL_RESERVED282                        :TDCRX_PHY_MACRO_CNTL_RESERVED282;                  // 0x5B9E
  DCRX_PHY_MACRO_CNTL_RESERVED283                        :TDCRX_PHY_MACRO_CNTL_RESERVED283;                  // 0x5B9F
  DCRX_PHY_MACRO_CNTL_RESERVED284                        :TDCRX_PHY_MACRO_CNTL_RESERVED284;                  // 0x5BA0
  DCRX_PHY_MACRO_CNTL_RESERVED285                        :TDCRX_PHY_MACRO_CNTL_RESERVED285;                  // 0x5BA1
  DCRX_PHY_MACRO_CNTL_RESERVED286                        :TDCRX_PHY_MACRO_CNTL_RESERVED286;                  // 0x5BA2
  DCRX_PHY_MACRO_CNTL_RESERVED287                        :TDCRX_PHY_MACRO_CNTL_RESERVED287;                  // 0x5BA3
  DCRX_PHY_MACRO_CNTL_RESERVED288                        :TDCRX_PHY_MACRO_CNTL_RESERVED288;                  // 0x5BA4
  DCRX_PHY_MACRO_CNTL_RESERVED289                        :TDCRX_PHY_MACRO_CNTL_RESERVED289;                  // 0x5BA5
  DCRX_PHY_MACRO_CNTL_RESERVED290                        :TDCRX_PHY_MACRO_CNTL_RESERVED290;                  // 0x5BA6
  DCRX_PHY_MACRO_CNTL_RESERVED291                        :TDCRX_PHY_MACRO_CNTL_RESERVED291;                  // 0x5BA7
  DCRX_PHY_MACRO_CNTL_RESERVED292                        :TDCRX_PHY_MACRO_CNTL_RESERVED292;                  // 0x5BA8
  DCRX_PHY_MACRO_CNTL_RESERVED293                        :TDCRX_PHY_MACRO_CNTL_RESERVED293;                  // 0x5BA9
  DCRX_PHY_MACRO_CNTL_RESERVED294                        :TDCRX_PHY_MACRO_CNTL_RESERVED294;                  // 0x5BAA
  DCRX_PHY_MACRO_CNTL_RESERVED295                        :TDCRX_PHY_MACRO_CNTL_RESERVED295;                  // 0x5BAB
  DCRX_PHY_MACRO_CNTL_RESERVED296                        :TDCRX_PHY_MACRO_CNTL_RESERVED296;                  // 0x5BAC
  DCRX_PHY_MACRO_CNTL_RESERVED297                        :TDCRX_PHY_MACRO_CNTL_RESERVED297;                  // 0x5BAD
  DCRX_PHY_MACRO_CNTL_RESERVED298                        :TDCRX_PHY_MACRO_CNTL_RESERVED298;                  // 0x5BAE
  DCRX_PHY_MACRO_CNTL_RESERVED299                        :TDCRX_PHY_MACRO_CNTL_RESERVED299;                  // 0x5BAF
  DCRX_PHY_MACRO_CNTL_RESERVED300                        :TDCRX_PHY_MACRO_CNTL_RESERVED300;                  // 0x5BB0
  DCRX_PHY_MACRO_CNTL_RESERVED301                        :TDCRX_PHY_MACRO_CNTL_RESERVED301;                  // 0x5BB1
  DCRX_PHY_MACRO_CNTL_RESERVED302                        :TDCRX_PHY_MACRO_CNTL_RESERVED302;                  // 0x5BB2
  DCRX_PHY_MACRO_CNTL_RESERVED303                        :TDCRX_PHY_MACRO_CNTL_RESERVED303;                  // 0x5BB3
  DCRX_PHY_MACRO_CNTL_RESERVED304                        :TDCRX_PHY_MACRO_CNTL_RESERVED304;                  // 0x5BB4
  DCRX_PHY_MACRO_CNTL_RESERVED305                        :TDCRX_PHY_MACRO_CNTL_RESERVED305;                  // 0x5BB5
  DCRX_PHY_MACRO_CNTL_RESERVED306                        :TDCRX_PHY_MACRO_CNTL_RESERVED306;                  // 0x5BB6
  DCRX_PHY_MACRO_CNTL_RESERVED307                        :TDCRX_PHY_MACRO_CNTL_RESERVED307;                  // 0x5BB7
  DCRX_PHY_MACRO_CNTL_RESERVED308                        :TDCRX_PHY_MACRO_CNTL_RESERVED308;                  // 0x5BB8
  DCRX_PHY_MACRO_CNTL_RESERVED309                        :TDCRX_PHY_MACRO_CNTL_RESERVED309;                  // 0x5BB9
  DCRX_PHY_MACRO_CNTL_RESERVED310                        :TDCRX_PHY_MACRO_CNTL_RESERVED310;                  // 0x5BBA
  DCRX_PHY_MACRO_CNTL_RESERVED311                        :TDCRX_PHY_MACRO_CNTL_RESERVED311;                  // 0x5BBB
  DCRX_PHY_MACRO_CNTL_RESERVED312                        :TDCRX_PHY_MACRO_CNTL_RESERVED312;                  // 0x5BBC
  DCRX_PHY_MACRO_CNTL_RESERVED313                        :TDCRX_PHY_MACRO_CNTL_RESERVED313;                  // 0x5BBD
  DCRX_PHY_MACRO_CNTL_RESERVED314                        :TDCRX_PHY_MACRO_CNTL_RESERVED314;                  // 0x5BBE
  DCRX_PHY_MACRO_CNTL_RESERVED315                        :TDCRX_PHY_MACRO_CNTL_RESERVED315;                  // 0x5BBF
  DCRX_PHY_MACRO_CNTL_RESERVED316                        :TDCRX_PHY_MACRO_CNTL_RESERVED316;                  // 0x5BC0
  DCRX_PHY_MACRO_CNTL_RESERVED317                        :TDCRX_PHY_MACRO_CNTL_RESERVED317;                  // 0x5BC1
  DCRX_PHY_MACRO_CNTL_RESERVED318                        :TDCRX_PHY_MACRO_CNTL_RESERVED318;                  // 0x5BC2
  DCRX_PHY_MACRO_CNTL_RESERVED319                        :TDCRX_PHY_MACRO_CNTL_RESERVED319;                  // 0x5BC3
  DCRX_PHY_MACRO_CNTL_RESERVED320                        :TDCRX_PHY_MACRO_CNTL_RESERVED320;                  // 0x5BC4
  DCRX_PHY_MACRO_CNTL_RESERVED321                        :TDCRX_PHY_MACRO_CNTL_RESERVED321;                  // 0x5BC5
  DCRX_PHY_MACRO_CNTL_RESERVED322                        :TDCRX_PHY_MACRO_CNTL_RESERVED322;                  // 0x5BC6
  DCRX_PHY_MACRO_CNTL_RESERVED323                        :TDCRX_PHY_MACRO_CNTL_RESERVED323;                  // 0x5BC7
  DCRX_PHY_MACRO_CNTL_RESERVED324                        :TDCRX_PHY_MACRO_CNTL_RESERVED324;                  // 0x5BC8
  DCRX_PHY_MACRO_CNTL_RESERVED325                        :TDCRX_PHY_MACRO_CNTL_RESERVED325;                  // 0x5BC9
  DCRX_PHY_MACRO_CNTL_RESERVED326                        :TDCRX_PHY_MACRO_CNTL_RESERVED326;                  // 0x5BCA
  DCRX_PHY_MACRO_CNTL_RESERVED327                        :TDCRX_PHY_MACRO_CNTL_RESERVED327;                  // 0x5BCB
  DCRX_PHY_MACRO_CNTL_RESERVED328                        :TDCRX_PHY_MACRO_CNTL_RESERVED328;                  // 0x5BCC
  DCRX_PHY_MACRO_CNTL_RESERVED329                        :TDCRX_PHY_MACRO_CNTL_RESERVED329;                  // 0x5BCD
  DCRX_PHY_MACRO_CNTL_RESERVED330                        :TDCRX_PHY_MACRO_CNTL_RESERVED330;                  // 0x5BCE
  DCRX_PHY_MACRO_CNTL_RESERVED331                        :TDCRX_PHY_MACRO_CNTL_RESERVED331;                  // 0x5BCF
  DCRX_PHY_MACRO_CNTL_RESERVED332                        :TDCRX_PHY_MACRO_CNTL_RESERVED332;                  // 0x5BD0
  DCRX_PHY_MACRO_CNTL_RESERVED333                        :TDCRX_PHY_MACRO_CNTL_RESERVED333;                  // 0x5BD1
  DCRX_PHY_MACRO_CNTL_RESERVED334                        :TDCRX_PHY_MACRO_CNTL_RESERVED334;                  // 0x5BD2
  DCRX_PHY_MACRO_CNTL_RESERVED335                        :TDCRX_PHY_MACRO_CNTL_RESERVED335;                  // 0x5BD3
  DCRX_PHY_MACRO_CNTL_RESERVED336                        :TDCRX_PHY_MACRO_CNTL_RESERVED336;                  // 0x5BD4
  DCRX_PHY_MACRO_CNTL_RESERVED337                        :TDCRX_PHY_MACRO_CNTL_RESERVED337;                  // 0x5BD5
  DCRX_PHY_MACRO_CNTL_RESERVED338                        :TDCRX_PHY_MACRO_CNTL_RESERVED338;                  // 0x5BD6
  DCRX_PHY_MACRO_CNTL_RESERVED339                        :TDCRX_PHY_MACRO_CNTL_RESERVED339;                  // 0x5BD7
  DCRX_PHY_MACRO_CNTL_RESERVED340                        :TDCRX_PHY_MACRO_CNTL_RESERVED340;                  // 0x5BD8
  DCRX_PHY_MACRO_CNTL_RESERVED341                        :TDCRX_PHY_MACRO_CNTL_RESERVED341;                  // 0x5BD9
  DCRX_PHY_MACRO_CNTL_RESERVED342                        :TDCRX_PHY_MACRO_CNTL_RESERVED342;                  // 0x5BDA
  DCRX_PHY_MACRO_CNTL_RESERVED343                        :TDCRX_PHY_MACRO_CNTL_RESERVED343;                  // 0x5BDB
  DCRX_PHY_MACRO_CNTL_RESERVED344                        :TDCRX_PHY_MACRO_CNTL_RESERVED344;                  // 0x5BDC
  DCRX_PHY_MACRO_CNTL_RESERVED345                        :TDCRX_PHY_MACRO_CNTL_RESERVED345;                  // 0x5BDD
  DCRX_PHY_MACRO_CNTL_RESERVED346                        :TDCRX_PHY_MACRO_CNTL_RESERVED346;                  // 0x5BDE
  DCRX_PHY_MACRO_CNTL_RESERVED347                        :TDCRX_PHY_MACRO_CNTL_RESERVED347;                  // 0x5BDF
  DCRX_PHY_MACRO_CNTL_RESERVED348                        :TDCRX_PHY_MACRO_CNTL_RESERVED348;                  // 0x5BE0
  DCRX_PHY_MACRO_CNTL_RESERVED349                        :TDCRX_PHY_MACRO_CNTL_RESERVED349;                  // 0x5BE1
  DCRX_PHY_MACRO_CNTL_RESERVED350                        :TDCRX_PHY_MACRO_CNTL_RESERVED350;                  // 0x5BE2
  DCRX_PHY_MACRO_CNTL_RESERVED351                        :TDCRX_PHY_MACRO_CNTL_RESERVED351;                  // 0x5BE3
  DCRX_PHY_MACRO_CNTL_RESERVED352                        :TDCRX_PHY_MACRO_CNTL_RESERVED352;                  // 0x5BE4
  DCRX_PHY_MACRO_CNTL_RESERVED353                        :TDCRX_PHY_MACRO_CNTL_RESERVED353;                  // 0x5BE5
  DCRX_PHY_MACRO_CNTL_RESERVED354                        :TDCRX_PHY_MACRO_CNTL_RESERVED354;                  // 0x5BE6
  DCRX_PHY_MACRO_CNTL_RESERVED355                        :TDCRX_PHY_MACRO_CNTL_RESERVED355;                  // 0x5BE7
  DCRX_PHY_MACRO_CNTL_RESERVED356                        :TDCRX_PHY_MACRO_CNTL_RESERVED356;                  // 0x5BE8
  DCRX_PHY_MACRO_CNTL_RESERVED357                        :TDCRX_PHY_MACRO_CNTL_RESERVED357;                  // 0x5BE9
  DCRX_PHY_MACRO_CNTL_RESERVED358                        :TDCRX_PHY_MACRO_CNTL_RESERVED358;                  // 0x5BEA
  DCRX_PHY_MACRO_CNTL_RESERVED359                        :TDCRX_PHY_MACRO_CNTL_RESERVED359;                  // 0x5BEB
  DCRX_PHY_MACRO_CNTL_RESERVED360                        :TDCRX_PHY_MACRO_CNTL_RESERVED360;                  // 0x5BEC
  DCRX_PHY_MACRO_CNTL_RESERVED361                        :TDCRX_PHY_MACRO_CNTL_RESERVED361;                  // 0x5BED
  DCRX_PHY_MACRO_CNTL_RESERVED362                        :TDCRX_PHY_MACRO_CNTL_RESERVED362;                  // 0x5BEE
  DCRX_PHY_MACRO_CNTL_RESERVED363                        :TDCRX_PHY_MACRO_CNTL_RESERVED363;                  // 0x5BEF
  DCRX_PHY_MACRO_CNTL_RESERVED364                        :TDCRX_PHY_MACRO_CNTL_RESERVED364;                  // 0x5BF0
  DCRX_PHY_MACRO_CNTL_RESERVED365                        :TDCRX_PHY_MACRO_CNTL_RESERVED365;                  // 0x5BF1
  DCRX_PHY_MACRO_CNTL_RESERVED366                        :TDCRX_PHY_MACRO_CNTL_RESERVED366;                  // 0x5BF2
  DCRX_PHY_MACRO_CNTL_RESERVED367                        :TDCRX_PHY_MACRO_CNTL_RESERVED367;                  // 0x5BF3
  DCRX_PHY_MACRO_CNTL_RESERVED368                        :TDCRX_PHY_MACRO_CNTL_RESERVED368;                  // 0x5BF4
  DCRX_PHY_MACRO_CNTL_RESERVED369                        :TDCRX_PHY_MACRO_CNTL_RESERVED369;                  // 0x5BF5
  DCRX_PHY_MACRO_CNTL_RESERVED370                        :TDCRX_PHY_MACRO_CNTL_RESERVED370;                  // 0x5BF6
  DCRX_PHY_MACRO_CNTL_RESERVED371                        :TDCRX_PHY_MACRO_CNTL_RESERVED371;                  // 0x5BF7
  DCRX_PHY_MACRO_CNTL_RESERVED372                        :TDCRX_PHY_MACRO_CNTL_RESERVED372;                  // 0x5BF8
  DCRX_PHY_MACRO_CNTL_RESERVED373                        :TDCRX_PHY_MACRO_CNTL_RESERVED373;                  // 0x5BF9
  DCRX_PHY_MACRO_CNTL_RESERVED374                        :TDCRX_PHY_MACRO_CNTL_RESERVED374;                  // 0x5BFA
  DCRX_PHY_MACRO_CNTL_RESERVED375                        :TDCRX_PHY_MACRO_CNTL_RESERVED375;                  // 0x5BFB
  DCRX_PHY_MACRO_CNTL_RESERVED376                        :TDCRX_PHY_MACRO_CNTL_RESERVED376;                  // 0x5BFC
  DCRX_PHY_MACRO_CNTL_RESERVED377                        :TDCRX_PHY_MACRO_CNTL_RESERVED377;                  // 0x5BFD
  DCRX_PHY_MACRO_CNTL_RESERVED378                        :TDCRX_PHY_MACRO_CNTL_RESERVED378;                  // 0x5BFE
  DCRX_PHY_MACRO_CNTL_RESERVED379                        :TDCRX_PHY_MACRO_CNTL_RESERVED379;                  // 0x5BFF
  AUX_CONTROL                                            :TAUX_CONTROL;                                      // 0x5C00
  AUX_SW_CONTROL                                         :TAUX_SW_CONTROL;                                   // 0x5C01
  AUX_ARB_CONTROL                                        :TAUX_ARB_CONTROL;                                  // 0x5C02
  AUX_INTERRUPT_CONTROL                                  :TAUX_INTERRUPT_CONTROL;                            // 0x5C03
  AUX_SW_STATUS                                          :TAUX_SW_STATUS;                                    // 0x5C04
  AUX_LS_STATUS                                          :TAUX_LS_STATUS;                                    // 0x5C05
  AUX_SW_DATA                                            :TAUX_SW_DATA;                                      // 0x5C06
  AUX_LS_DATA                                            :TAUX_LS_DATA;                                      // 0x5C07
  AUX_DPHY_TX_REF_CONTROL                                :TAUX_DPHY_TX_REF_CONTROL;                          // 0x5C08
  AUX_DPHY_TX_CONTROL                                    :TAUX_DPHY_TX_CONTROL;                              // 0x5C09
  AUX_DPHY_RX_CONTROL0                                   :TAUX_DPHY_RX_CONTROL0;                             // 0x5C0A
  AUX_DPHY_RX_CONTROL1                                   :TAUX_DPHY_RX_CONTROL1;                             // 0x5C0B
  AUX_DPHY_TX_STATUS                                     :TAUX_DPHY_TX_STATUS;                               // 0x5C0C
  AUX_DPHY_RX_STATUS                                     :TAUX_DPHY_RX_STATUS;                               // 0x5C0D
  AUX_GTC_SYNC_CONTROL                                   :TAUX_GTC_SYNC_CONTROL;                             // 0x5C0E
  AUX_GTC_SYNC_ERROR_CONTROL                             :TAUX_GTC_SYNC_ERROR_CONTROL;                       // 0x5C0F
  AUX_GTC_SYNC_CONTROLLER_STATUS                         :TAUX_GTC_SYNC_CONTROLLER_STATUS;                   // 0x5C10
  AUX_GTC_SYNC_STATUS                                    :TAUX_GTC_SYNC_STATUS;                              // 0x5C11
  AUX_GTC_SYNC_DATA                                      :TAUX_GTC_SYNC_DATA;                                // 0x5C12
  AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                     :TAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE;               // 0x5C13
  AUX_TEST_DEBUG_INDEX                                   :TAUX_TEST_DEBUG_INDEX;                             // 0x5C14
  AUX_TEST_DEBUG_DATA                                    :TAUX_TEST_DEBUG_DATA;                              // 0x5C15
  REG_5C16_5C1B                                          :array[0..5] of DWORD;                              // 0x5C16
  DP_AUX1_AUX_CONTROL                                    :DWORD;                                             // 0x5C1C
  DP_AUX1_AUX_SW_CONTROL                                 :DWORD;                                             // 0x5C1D
  DP_AUX1_AUX_ARB_CONTROL                                :DWORD;                                             // 0x5C1E
  DP_AUX1_AUX_INTERRUPT_CONTROL                          :DWORD;                                             // 0x5C1F
  DP_AUX1_AUX_SW_STATUS                                  :DWORD;                                             // 0x5C20
  DP_AUX1_AUX_LS_STATUS                                  :DWORD;                                             // 0x5C21
  DP_AUX1_AUX_SW_DATA                                    :DWORD;                                             // 0x5C22
  DP_AUX1_AUX_LS_DATA                                    :DWORD;                                             // 0x5C23
  DP_AUX1_AUX_DPHY_TX_REF_CONTROL                        :DWORD;                                             // 0x5C24
  DP_AUX1_AUX_DPHY_TX_CONTROL                            :DWORD;                                             // 0x5C25
  DP_AUX1_AUX_DPHY_RX_CONTROL0                           :DWORD;                                             // 0x5C26
  DP_AUX1_AUX_DPHY_RX_CONTROL1                           :DWORD;                                             // 0x5C27
  DP_AUX1_AUX_DPHY_TX_STATUS                             :DWORD;                                             // 0x5C28
  DP_AUX1_AUX_DPHY_RX_STATUS                             :DWORD;                                             // 0x5C29
  DP_AUX1_AUX_GTC_SYNC_CONTROL                           :DWORD;                                             // 0x5C2A
  DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                     :DWORD;                                             // 0x5C2B
  DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                 :DWORD;                                             // 0x5C2C
  DP_AUX1_AUX_GTC_SYNC_STATUS                            :DWORD;                                             // 0x5C2D
  DP_AUX1_AUX_GTC_SYNC_DATA                              :DWORD;                                             // 0x5C2E
  DP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             :DWORD;                                             // 0x5C2F
  DP_AUX1_AUX_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x5C30
  DP_AUX1_AUX_TEST_DEBUG_DATA                            :DWORD;                                             // 0x5C31
  REG_5C32_5C37                                          :array[0..5] of DWORD;                              // 0x5C32
  DP_AUX2_AUX_CONTROL                                    :DWORD;                                             // 0x5C38
  DP_AUX2_AUX_SW_CONTROL                                 :DWORD;                                             // 0x5C39
  DP_AUX2_AUX_ARB_CONTROL                                :DWORD;                                             // 0x5C3A
  DP_AUX2_AUX_INTERRUPT_CONTROL                          :DWORD;                                             // 0x5C3B
  DP_AUX2_AUX_SW_STATUS                                  :DWORD;                                             // 0x5C3C
  DP_AUX2_AUX_LS_STATUS                                  :DWORD;                                             // 0x5C3D
  DP_AUX2_AUX_SW_DATA                                    :DWORD;                                             // 0x5C3E
  DP_AUX2_AUX_LS_DATA                                    :DWORD;                                             // 0x5C3F
  DP_AUX2_AUX_DPHY_TX_REF_CONTROL                        :DWORD;                                             // 0x5C40
  DP_AUX2_AUX_DPHY_TX_CONTROL                            :DWORD;                                             // 0x5C41
  DP_AUX2_AUX_DPHY_RX_CONTROL0                           :DWORD;                                             // 0x5C42
  DP_AUX2_AUX_DPHY_RX_CONTROL1                           :DWORD;                                             // 0x5C43
  DP_AUX2_AUX_DPHY_TX_STATUS                             :DWORD;                                             // 0x5C44
  DP_AUX2_AUX_DPHY_RX_STATUS                             :DWORD;                                             // 0x5C45
  DP_AUX2_AUX_GTC_SYNC_CONTROL                           :DWORD;                                             // 0x5C46
  DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                     :DWORD;                                             // 0x5C47
  DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                 :DWORD;                                             // 0x5C48
  DP_AUX2_AUX_GTC_SYNC_STATUS                            :DWORD;                                             // 0x5C49
  DP_AUX2_AUX_GTC_SYNC_DATA                              :DWORD;                                             // 0x5C4A
  DP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             :DWORD;                                             // 0x5C4B
  DP_AUX2_AUX_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x5C4C
  DP_AUX2_AUX_TEST_DEBUG_DATA                            :DWORD;                                             // 0x5C4D
  REG_5C4E_5C53                                          :array[0..5] of DWORD;                              // 0x5C4E
  DP_AUX3_AUX_CONTROL                                    :DWORD;                                             // 0x5C54
  DP_AUX3_AUX_SW_CONTROL                                 :DWORD;                                             // 0x5C55
  DP_AUX3_AUX_ARB_CONTROL                                :DWORD;                                             // 0x5C56
  DP_AUX3_AUX_INTERRUPT_CONTROL                          :DWORD;                                             // 0x5C57
  DP_AUX3_AUX_SW_STATUS                                  :DWORD;                                             // 0x5C58
  DP_AUX3_AUX_LS_STATUS                                  :DWORD;                                             // 0x5C59
  DP_AUX3_AUX_SW_DATA                                    :DWORD;                                             // 0x5C5A
  DP_AUX3_AUX_LS_DATA                                    :DWORD;                                             // 0x5C5B
  DP_AUX3_AUX_DPHY_TX_REF_CONTROL                        :DWORD;                                             // 0x5C5C
  DP_AUX3_AUX_DPHY_TX_CONTROL                            :DWORD;                                             // 0x5C5D
  DP_AUX3_AUX_DPHY_RX_CONTROL0                           :DWORD;                                             // 0x5C5E
  DP_AUX3_AUX_DPHY_RX_CONTROL1                           :DWORD;                                             // 0x5C5F
  DP_AUX3_AUX_DPHY_TX_STATUS                             :DWORD;                                             // 0x5C60
  DP_AUX3_AUX_DPHY_RX_STATUS                             :DWORD;                                             // 0x5C61
  DP_AUX3_AUX_GTC_SYNC_CONTROL                           :DWORD;                                             // 0x5C62
  DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                     :DWORD;                                             // 0x5C63
  DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                 :DWORD;                                             // 0x5C64
  DP_AUX3_AUX_GTC_SYNC_STATUS                            :DWORD;                                             // 0x5C65
  DP_AUX3_AUX_GTC_SYNC_DATA                              :DWORD;                                             // 0x5C66
  DP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             :DWORD;                                             // 0x5C67
  DP_AUX3_AUX_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x5C68
  DP_AUX3_AUX_TEST_DEBUG_DATA                            :DWORD;                                             // 0x5C69
  REG_5C6A_5C6F                                          :array[0..5] of DWORD;                              // 0x5C6A
  DP_AUX4_AUX_CONTROL                                    :DWORD;                                             // 0x5C70
  DP_AUX4_AUX_SW_CONTROL                                 :DWORD;                                             // 0x5C71
  DP_AUX4_AUX_ARB_CONTROL                                :DWORD;                                             // 0x5C72
  DP_AUX4_AUX_INTERRUPT_CONTROL                          :DWORD;                                             // 0x5C73
  DP_AUX4_AUX_SW_STATUS                                  :DWORD;                                             // 0x5C74
  DP_AUX4_AUX_LS_STATUS                                  :DWORD;                                             // 0x5C75
  DP_AUX4_AUX_SW_DATA                                    :DWORD;                                             // 0x5C76
  DP_AUX4_AUX_LS_DATA                                    :DWORD;                                             // 0x5C77
  DP_AUX4_AUX_DPHY_TX_REF_CONTROL                        :DWORD;                                             // 0x5C78
  DP_AUX4_AUX_DPHY_TX_CONTROL                            :DWORD;                                             // 0x5C79
  DP_AUX4_AUX_DPHY_RX_CONTROL0                           :DWORD;                                             // 0x5C7A
  DP_AUX4_AUX_DPHY_RX_CONTROL1                           :DWORD;                                             // 0x5C7B
  DP_AUX4_AUX_DPHY_TX_STATUS                             :DWORD;                                             // 0x5C7C
  DP_AUX4_AUX_DPHY_RX_STATUS                             :DWORD;                                             // 0x5C7D
  DP_AUX4_AUX_GTC_SYNC_CONTROL                           :DWORD;                                             // 0x5C7E
  DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                     :DWORD;                                             // 0x5C7F
  DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                 :DWORD;                                             // 0x5C80
  DP_AUX4_AUX_GTC_SYNC_STATUS                            :DWORD;                                             // 0x5C81
  DP_AUX4_AUX_GTC_SYNC_DATA                              :DWORD;                                             // 0x5C82
  DP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             :DWORD;                                             // 0x5C83
  DP_AUX4_AUX_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x5C84
  DP_AUX4_AUX_TEST_DEBUG_DATA                            :DWORD;                                             // 0x5C85
  REG_5C86_5C8B                                          :array[0..5] of DWORD;                              // 0x5C86
  DP_AUX5_AUX_CONTROL                                    :DWORD;                                             // 0x5C8C
  DP_AUX5_AUX_SW_CONTROL                                 :DWORD;                                             // 0x5C8D
  DP_AUX5_AUX_ARB_CONTROL                                :DWORD;                                             // 0x5C8E
  DP_AUX5_AUX_INTERRUPT_CONTROL                          :DWORD;                                             // 0x5C8F
  DP_AUX5_AUX_SW_STATUS                                  :DWORD;                                             // 0x5C90
  DP_AUX5_AUX_LS_STATUS                                  :DWORD;                                             // 0x5C91
  DP_AUX5_AUX_SW_DATA                                    :DWORD;                                             // 0x5C92
  DP_AUX5_AUX_LS_DATA                                    :DWORD;                                             // 0x5C93
  DP_AUX5_AUX_DPHY_TX_REF_CONTROL                        :DWORD;                                             // 0x5C94
  DP_AUX5_AUX_DPHY_TX_CONTROL                            :DWORD;                                             // 0x5C95
  DP_AUX5_AUX_DPHY_RX_CONTROL0                           :DWORD;                                             // 0x5C96
  DP_AUX5_AUX_DPHY_RX_CONTROL1                           :DWORD;                                             // 0x5C97
  DP_AUX5_AUX_DPHY_TX_STATUS                             :DWORD;                                             // 0x5C98
  DP_AUX5_AUX_DPHY_RX_STATUS                             :DWORD;                                             // 0x5C99
  DP_AUX5_AUX_GTC_SYNC_CONTROL                           :DWORD;                                             // 0x5C9A
  DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL                     :DWORD;                                             // 0x5C9B
  DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS                 :DWORD;                                             // 0x5C9C
  DP_AUX5_AUX_GTC_SYNC_STATUS                            :DWORD;                                             // 0x5C9D
  DP_AUX5_AUX_GTC_SYNC_DATA                              :DWORD;                                             // 0x5C9E
  DP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE             :DWORD;                                             // 0x5C9F
  DP_AUX5_AUX_TEST_DEBUG_INDEX                           :DWORD;                                             // 0x5CA0
  DP_AUX5_AUX_TEST_DEBUG_DATA                            :DWORD;                                             // 0x5CA1
  REG_5CA2_5D97                                          :array[0..245] of DWORD;                            // 0x5CA2
  DPHY_MACRO_CNTL_RESERVED0                              :TDPHY_MACRO_CNTL_RESERVED0;                        // 0x5D98
  DPHY_MACRO_CNTL_RESERVED1                              :TDPHY_MACRO_CNTL_RESERVED1;                        // 0x5D99
  DPHY_MACRO_CNTL_RESERVED2                              :TDPHY_MACRO_CNTL_RESERVED2;                        // 0x5D9A
  DPHY_MACRO_CNTL_RESERVED3                              :TDPHY_MACRO_CNTL_RESERVED3;                        // 0x5D9B
  DPHY_MACRO_CNTL_RESERVED4                              :TDPHY_MACRO_CNTL_RESERVED4;                        // 0x5D9C
  DPHY_MACRO_CNTL_RESERVED5                              :TDPHY_MACRO_CNTL_RESERVED5;                        // 0x5D9D
  DPHY_MACRO_CNTL_RESERVED6                              :TDPHY_MACRO_CNTL_RESERVED6;                        // 0x5D9E
  DPHY_MACRO_CNTL_RESERVED7                              :TDPHY_MACRO_CNTL_RESERVED7;                        // 0x5D9F
  DPHY_MACRO_CNTL_RESERVED8                              :TDPHY_MACRO_CNTL_RESERVED8;                        // 0x5DA0
  DPHY_MACRO_CNTL_RESERVED9                              :TDPHY_MACRO_CNTL_RESERVED9;                        // 0x5DA1
  DPHY_MACRO_CNTL_RESERVED10                             :TDPHY_MACRO_CNTL_RESERVED10;                       // 0x5DA2
  DPHY_MACRO_CNTL_RESERVED11                             :TDPHY_MACRO_CNTL_RESERVED11;                       // 0x5DA3
  DPHY_MACRO_CNTL_RESERVED12                             :TDPHY_MACRO_CNTL_RESERVED12;                       // 0x5DA4
  DPHY_MACRO_CNTL_RESERVED13                             :TDPHY_MACRO_CNTL_RESERVED13;                       // 0x5DA5
  DPHY_MACRO_CNTL_RESERVED14                             :TDPHY_MACRO_CNTL_RESERVED14;                       // 0x5DA6
  DPHY_MACRO_CNTL_RESERVED15                             :TDPHY_MACRO_CNTL_RESERVED15;                       // 0x5DA7
  DPHY_MACRO_CNTL_RESERVED16                             :TDPHY_MACRO_CNTL_RESERVED16;                       // 0x5DA8
  DPHY_MACRO_CNTL_RESERVED17                             :TDPHY_MACRO_CNTL_RESERVED17;                       // 0x5DA9
  DPHY_MACRO_CNTL_RESERVED18                             :TDPHY_MACRO_CNTL_RESERVED18;                       // 0x5DAA
  DPHY_MACRO_CNTL_RESERVED19                             :TDPHY_MACRO_CNTL_RESERVED19;                       // 0x5DAB
  DPHY_MACRO_CNTL_RESERVED20                             :TDPHY_MACRO_CNTL_RESERVED20;                       // 0x5DAC
  DPHY_MACRO_CNTL_RESERVED21                             :TDPHY_MACRO_CNTL_RESERVED21;                       // 0x5DAD
  DPHY_MACRO_CNTL_RESERVED22                             :TDPHY_MACRO_CNTL_RESERVED22;                       // 0x5DAE
  DPHY_MACRO_CNTL_RESERVED23                             :TDPHY_MACRO_CNTL_RESERVED23;                       // 0x5DAF
  DPHY_MACRO_CNTL_RESERVED24                             :TDPHY_MACRO_CNTL_RESERVED24;                       // 0x5DB0
  DPHY_MACRO_CNTL_RESERVED25                             :TDPHY_MACRO_CNTL_RESERVED25;                       // 0x5DB1
  DPHY_MACRO_CNTL_RESERVED26                             :TDPHY_MACRO_CNTL_RESERVED26;                       // 0x5DB2
  DPHY_MACRO_CNTL_RESERVED27                             :TDPHY_MACRO_CNTL_RESERVED27;                       // 0x5DB3
  DPHY_MACRO_CNTL_RESERVED28                             :TDPHY_MACRO_CNTL_RESERVED28;                       // 0x5DB4
  DPHY_MACRO_CNTL_RESERVED29                             :TDPHY_MACRO_CNTL_RESERVED29;                       // 0x5DB5
  DPHY_MACRO_CNTL_RESERVED30                             :TDPHY_MACRO_CNTL_RESERVED30;                       // 0x5DB6
  DPHY_MACRO_CNTL_RESERVED31                             :TDPHY_MACRO_CNTL_RESERVED31;                       // 0x5DB7
  DPHY_MACRO_CNTL_RESERVED32                             :TDPHY_MACRO_CNTL_RESERVED32;                       // 0x5DB8
  DPHY_MACRO_CNTL_RESERVED33                             :TDPHY_MACRO_CNTL_RESERVED33;                       // 0x5DB9
  DPHY_MACRO_CNTL_RESERVED34                             :TDPHY_MACRO_CNTL_RESERVED34;                       // 0x5DBA
  DPHY_MACRO_CNTL_RESERVED35                             :TDPHY_MACRO_CNTL_RESERVED35;                       // 0x5DBB
  DPHY_MACRO_CNTL_RESERVED36                             :TDPHY_MACRO_CNTL_RESERVED36;                       // 0x5DBC
  DPHY_MACRO_CNTL_RESERVED37                             :TDPHY_MACRO_CNTL_RESERVED37;                       // 0x5DBD
  DPHY_MACRO_CNTL_RESERVED38                             :TDPHY_MACRO_CNTL_RESERVED38;                       // 0x5DBE
  DPHY_MACRO_CNTL_RESERVED39                             :TDPHY_MACRO_CNTL_RESERVED39;                       // 0x5DBF
  DPHY_MACRO_CNTL_RESERVED40                             :TDPHY_MACRO_CNTL_RESERVED40;                       // 0x5DC0
  DPHY_MACRO_CNTL_RESERVED41                             :TDPHY_MACRO_CNTL_RESERVED41;                       // 0x5DC1
  DPHY_MACRO_CNTL_RESERVED42                             :TDPHY_MACRO_CNTL_RESERVED42;                       // 0x5DC2
  DPHY_MACRO_CNTL_RESERVED43                             :TDPHY_MACRO_CNTL_RESERVED43;                       // 0x5DC3
  DPHY_MACRO_CNTL_RESERVED44                             :TDPHY_MACRO_CNTL_RESERVED44;                       // 0x5DC4
  DPHY_MACRO_CNTL_RESERVED45                             :TDPHY_MACRO_CNTL_RESERVED45;                       // 0x5DC5
  DPHY_MACRO_CNTL_RESERVED46                             :TDPHY_MACRO_CNTL_RESERVED46;                       // 0x5DC6
  DPHY_MACRO_CNTL_RESERVED47                             :TDPHY_MACRO_CNTL_RESERVED47;                       // 0x5DC7
  DPHY_MACRO_CNTL_RESERVED48                             :TDPHY_MACRO_CNTL_RESERVED48;                       // 0x5DC8
  DPHY_MACRO_CNTL_RESERVED49                             :TDPHY_MACRO_CNTL_RESERVED49;                       // 0x5DC9
  DPHY_MACRO_CNTL_RESERVED50                             :TDPHY_MACRO_CNTL_RESERVED50;                       // 0x5DCA
  DPHY_MACRO_CNTL_RESERVED51                             :TDPHY_MACRO_CNTL_RESERVED51;                       // 0x5DCB
  DPHY_MACRO_CNTL_RESERVED52                             :TDPHY_MACRO_CNTL_RESERVED52;                       // 0x5DCC
  DPHY_MACRO_CNTL_RESERVED53                             :TDPHY_MACRO_CNTL_RESERVED53;                       // 0x5DCD
  DPHY_MACRO_CNTL_RESERVED54                             :TDPHY_MACRO_CNTL_RESERVED54;                       // 0x5DCE
  DPHY_MACRO_CNTL_RESERVED55                             :TDPHY_MACRO_CNTL_RESERVED55;                       // 0x5DCF
  DPHY_MACRO_CNTL_RESERVED56                             :TDPHY_MACRO_CNTL_RESERVED56;                       // 0x5DD0
  DPHY_MACRO_CNTL_RESERVED57                             :TDPHY_MACRO_CNTL_RESERVED57;                       // 0x5DD1
  DPHY_MACRO_CNTL_RESERVED58                             :TDPHY_MACRO_CNTL_RESERVED58;                       // 0x5DD2
  DPHY_MACRO_CNTL_RESERVED59                             :TDPHY_MACRO_CNTL_RESERVED59;                       // 0x5DD3
  DPHY_MACRO_CNTL_RESERVED60                             :TDPHY_MACRO_CNTL_RESERVED60;                       // 0x5DD4
  DPHY_MACRO_CNTL_RESERVED61                             :TDPHY_MACRO_CNTL_RESERVED61;                       // 0x5DD5
  DPHY_MACRO_CNTL_RESERVED62                             :TDPHY_MACRO_CNTL_RESERVED62;                       // 0x5DD6
  DPHY_MACRO_CNTL_RESERVED63                             :TDPHY_MACRO_CNTL_RESERVED63;                       // 0x5DD7
  REG_5DD8_5E17                                          :array[0..63] of DWORD;                             // 0x5DD8
  WB_ENABLE                                              :TWB_ENABLE;                                        // 0x5E18
  WB_EC_CONFIG                                           :TWB_EC_CONFIG;                                     // 0x5E19
  CNV_MODE                                               :TCNV_MODE;                                         // 0x5E1A
  CNV_WINDOW_START                                       :TCNV_WINDOW_START;                                 // 0x5E1B
  CNV_WINDOW_SIZE                                        :TCNV_WINDOW_SIZE;                                  // 0x5E1C
  CNV_UPDATE                                             :TCNV_UPDATE;                                       // 0x5E1D
  CNV_SOURCE_SIZE                                        :TCNV_SOURCE_SIZE;                                  // 0x5E1E
  CNV_CSC_CONTROL                                        :TCNV_CSC_CONTROL;                                  // 0x5E1F
  CNV_CSC_C11_C12                                        :TCNV_CSC_C11_C12;                                  // 0x5E20
  CNV_CSC_C13_C14                                        :TCNV_CSC_C13_C14;                                  // 0x5E21
  CNV_CSC_C21_C22                                        :TCNV_CSC_C21_C22;                                  // 0x5E22
  CNV_CSC_C23_C24                                        :TCNV_CSC_C23_C24;                                  // 0x5E23
  CNV_CSC_C31_C32                                        :TCNV_CSC_C31_C32;                                  // 0x5E24
  CNV_CSC_C33_C34                                        :TCNV_CSC_C33_C34;                                  // 0x5E25
  CNV_CSC_ROUND_OFFSET_R                                 :TCNV_CSC_ROUND_OFFSET_R;                           // 0x5E26
  CNV_CSC_ROUND_OFFSET_G                                 :TCNV_CSC_ROUND_OFFSET_G;                           // 0x5E27
  CNV_CSC_ROUND_OFFSET_B                                 :TCNV_CSC_ROUND_OFFSET_B;                           // 0x5E28
  CNV_CSC_CLAMP_R                                        :TCNV_CSC_CLAMP_R;                                  // 0x5E29
  CNV_CSC_CLAMP_G                                        :TCNV_CSC_CLAMP_G;                                  // 0x5E2A
  CNV_CSC_CLAMP_B                                        :TCNV_CSC_CLAMP_B;                                  // 0x5E2B
  CNV_TEST_CNTL                                          :TCNV_TEST_CNTL;                                    // 0x5E2C
  CNV_TEST_CRC_RED                                       :TCNV_TEST_CRC_RED;                                 // 0x5E2D
  CNV_TEST_CRC_GREEN                                     :TCNV_TEST_CRC_GREEN;                               // 0x5E2E
  CNV_TEST_CRC_BLUE                                      :TCNV_TEST_CRC_BLUE;                                // 0x5E2F
  WB_DEBUG_CTRL                                          :TWB_DEBUG_CTRL;                                    // 0x5E30
  WB_DBG_MODE                                            :TWB_DBG_MODE;                                      // 0x5E31
  WB_HW_DEBUG                                            :TWB_HW_DEBUG;                                      // 0x5E32
  CNV_INPUT_SELECT                                       :TCNV_INPUT_SELECT;                                 // 0x5E33
  CNV_TEST_DEBUG_INDEX                                   :TCNV_TEST_DEBUG_INDEX;                             // 0x5E34
  CNV_TEST_DEBUG_DATA                                    :TCNV_TEST_DEBUG_DATA;                              // 0x5E35
  WB_SOFT_RESET                                          :TWB_SOFT_RESET;                                    // 0x5E36
  REG_5E37_5E77                                          :array[0..64] of DWORD;                             // 0x5E37
  MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                     :DWORD;                                             // 0x5E78
  MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R                     :DWORD;                                             // 0x5E79
  MCIF_WB0_MCIF_WB_BUFMGR_STATUS                         :DWORD;                                             // 0x5E7A
  MCIF_WB0_MCIF_WB_BUF_PITCH                             :DWORD;                                             // 0x5E7B
  MCIF_WB0_MCIF_WB_BUF_1_STATUS                          :DWORD;                                             // 0x5E7C
  MCIF_WB0_MCIF_WB_BUF_1_STATUS2                         :DWORD;                                             // 0x5E7D
  MCIF_WB0_MCIF_WB_BUF_2_STATUS                          :DWORD;                                             // 0x5E7E
  MCIF_WB0_MCIF_WB_BUF_2_STATUS2                         :DWORD;                                             // 0x5E7F
  MCIF_WB0_MCIF_WB_BUF_3_STATUS                          :DWORD;                                             // 0x5E80
  MCIF_WB0_MCIF_WB_BUF_3_STATUS2                         :DWORD;                                             // 0x5E81
  MCIF_WB0_MCIF_WB_BUF_4_STATUS                          :DWORD;                                             // 0x5E82
  MCIF_WB0_MCIF_WB_BUF_4_STATUS2                         :DWORD;                                             // 0x5E83
  MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL                   :DWORD;                                             // 0x5E84
  MCIF_WB0_MCIF_WB_URGENCY_WATERMARK                     :DWORD;                                             // 0x5E85
  MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX                      :DWORD;                                             // 0x5E86
  MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA                       :DWORD;                                             // 0x5E87
  MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y                          :DWORD;                                             // 0x5E88
  MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5E89
  MCIF_WB0_MCIF_WB_BUF_1_ADDR_C                          :DWORD;                                             // 0x5E8A
  MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET                   :DWORD;                                             // 0x5E8B
  MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y                          :DWORD;                                             // 0x5E8C
  MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5E8D
  MCIF_WB0_MCIF_WB_BUF_2_ADDR_C                          :DWORD;                                             // 0x5E8E
  MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET                   :DWORD;                                             // 0x5E8F
  MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y                          :DWORD;                                             // 0x5E90
  MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5E91
  MCIF_WB0_MCIF_WB_BUF_3_ADDR_C                          :DWORD;                                             // 0x5E92
  MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET                   :DWORD;                                             // 0x5E93
  MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y                          :DWORD;                                             // 0x5E94
  MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5E95
  MCIF_WB0_MCIF_WB_BUF_4_ADDR_C                          :DWORD;                                             // 0x5E96
  MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET                   :DWORD;                                             // 0x5E97
  MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL                    :DWORD;                                             // 0x5E98
  MCIF_WB0_MCIF_WB_HVVMID_CONTROL                        :DWORD;                                             // 0x5E99
  REG_5E9A_5EB7                                          :array[0..29] of DWORD;                             // 0x5E9A
  MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                     :DWORD;                                             // 0x5EB8
  MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R                     :DWORD;                                             // 0x5EB9
  MCIF_WB1_MCIF_WB_BUFMGR_STATUS                         :DWORD;                                             // 0x5EBA
  MCIF_WB1_MCIF_WB_BUF_PITCH                             :DWORD;                                             // 0x5EBB
  MCIF_WB1_MCIF_WB_BUF_1_STATUS                          :DWORD;                                             // 0x5EBC
  MCIF_WB1_MCIF_WB_BUF_1_STATUS2                         :DWORD;                                             // 0x5EBD
  MCIF_WB1_MCIF_WB_BUF_2_STATUS                          :DWORD;                                             // 0x5EBE
  MCIF_WB1_MCIF_WB_BUF_2_STATUS2                         :DWORD;                                             // 0x5EBF
  MCIF_WB1_MCIF_WB_BUF_3_STATUS                          :DWORD;                                             // 0x5EC0
  MCIF_WB1_MCIF_WB_BUF_3_STATUS2                         :DWORD;                                             // 0x5EC1
  MCIF_WB1_MCIF_WB_BUF_4_STATUS                          :DWORD;                                             // 0x5EC2
  MCIF_WB1_MCIF_WB_BUF_4_STATUS2                         :DWORD;                                             // 0x5EC3
  MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL                   :DWORD;                                             // 0x5EC4
  MCIF_WB1_MCIF_WB_URGENCY_WATERMARK                     :DWORD;                                             // 0x5EC5
  MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX                      :DWORD;                                             // 0x5EC6
  MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA                       :DWORD;                                             // 0x5EC7
  MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y                          :DWORD;                                             // 0x5EC8
  MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5EC9
  MCIF_WB1_MCIF_WB_BUF_1_ADDR_C                          :DWORD;                                             // 0x5ECA
  MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET                   :DWORD;                                             // 0x5ECB
  MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y                          :DWORD;                                             // 0x5ECC
  MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5ECD
  MCIF_WB1_MCIF_WB_BUF_2_ADDR_C                          :DWORD;                                             // 0x5ECE
  MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET                   :DWORD;                                             // 0x5ECF
  MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y                          :DWORD;                                             // 0x5ED0
  MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5ED1
  MCIF_WB1_MCIF_WB_BUF_3_ADDR_C                          :DWORD;                                             // 0x5ED2
  MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET                   :DWORD;                                             // 0x5ED3
  MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y                          :DWORD;                                             // 0x5ED4
  MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5ED5
  MCIF_WB1_MCIF_WB_BUF_4_ADDR_C                          :DWORD;                                             // 0x5ED6
  MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET                   :DWORD;                                             // 0x5ED7
  MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL                    :DWORD;                                             // 0x5ED8
  MCIF_WB1_MCIF_WB_HVVMID_CONTROL                        :DWORD;                                             // 0x5ED9
  REG_5EDA_5EF7                                          :array[0..29] of DWORD;                             // 0x5EDA
  MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL                     :DWORD;                                             // 0x5EF8
  MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R                     :DWORD;                                             // 0x5EF9
  MCIF_WB2_MCIF_WB_BUFMGR_STATUS                         :DWORD;                                             // 0x5EFA
  MCIF_WB2_MCIF_WB_BUF_PITCH                             :DWORD;                                             // 0x5EFB
  MCIF_WB2_MCIF_WB_BUF_1_STATUS                          :DWORD;                                             // 0x5EFC
  MCIF_WB2_MCIF_WB_BUF_1_STATUS2                         :DWORD;                                             // 0x5EFD
  MCIF_WB2_MCIF_WB_BUF_2_STATUS                          :DWORD;                                             // 0x5EFE
  MCIF_WB2_MCIF_WB_BUF_2_STATUS2                         :DWORD;                                             // 0x5EFF
  MCIF_WB2_MCIF_WB_BUF_3_STATUS                          :DWORD;                                             // 0x5F00
  MCIF_WB2_MCIF_WB_BUF_3_STATUS2                         :DWORD;                                             // 0x5F01
  MCIF_WB2_MCIF_WB_BUF_4_STATUS                          :DWORD;                                             // 0x5F02
  MCIF_WB2_MCIF_WB_BUF_4_STATUS2                         :DWORD;                                             // 0x5F03
  MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL                   :DWORD;                                             // 0x5F04
  MCIF_WB2_MCIF_WB_URGENCY_WATERMARK                     :DWORD;                                             // 0x5F05
  MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX                      :DWORD;                                             // 0x5F06
  MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA                       :DWORD;                                             // 0x5F07
  MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y                          :DWORD;                                             // 0x5F08
  MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5F09
  MCIF_WB2_MCIF_WB_BUF_1_ADDR_C                          :DWORD;                                             // 0x5F0A
  MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET                   :DWORD;                                             // 0x5F0B
  MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y                          :DWORD;                                             // 0x5F0C
  MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5F0D
  MCIF_WB2_MCIF_WB_BUF_2_ADDR_C                          :DWORD;                                             // 0x5F0E
  MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET                   :DWORD;                                             // 0x5F0F
  MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y                          :DWORD;                                             // 0x5F10
  MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5F11
  MCIF_WB2_MCIF_WB_BUF_3_ADDR_C                          :DWORD;                                             // 0x5F12
  MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET                   :DWORD;                                             // 0x5F13
  MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y                          :DWORD;                                             // 0x5F14
  MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET                   :DWORD;                                             // 0x5F15
  MCIF_WB2_MCIF_WB_BUF_4_ADDR_C                          :DWORD;                                             // 0x5F16
  MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET                   :DWORD;                                             // 0x5F17
  MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL                    :DWORD;                                             // 0x5F18
  MCIF_WB2_MCIF_WB_HVVMID_CONTROL                        :DWORD;                                             // 0x5F19
  REG_5F1A_5F67                                          :array[0..77] of DWORD;                             // 0x5F1A
  DC_PERFMON9_PERFCOUNTER_CNTL                           :DWORD;                                             // 0x5F68
  DC_PERFMON9_PERFCOUNTER_STATE                          :DWORD;                                             // 0x5F69
  DC_PERFMON9_PERFMON_CVALUE_INT_MISC                    :DWORD;                                             // 0x5F6A
  DC_PERFMON9_PERFMON_CNTL                               :DWORD;                                             // 0x5F6B
  DC_PERFMON9_PERFMON_CVALUE_LOW                         :DWORD;                                             // 0x5F6C
  DC_PERFMON9_PERFMON_HI                                 :DWORD;                                             // 0x5F6D
  DC_PERFMON9_PERFMON_LOW                                :DWORD;                                             // 0x5F6E
  DC_PERFMON9_PERFMON_TEST_DEBUG_INDEX                   :DWORD;                                             // 0x5F6F
  DC_PERFMON9_PERFMON_TEST_DEBUG_DATA                    :DWORD;                                             // 0x5F70
  REG_5F71                                               :DWORD;                                             // 0x5F71
  DC_PERFMON9_PERFMON_CNTL2                              :DWORD;                                             // 0x5F72
  REG_5F73_5FCF                                          :array[0..92] of DWORD;                             // 0x5F73
  CPLL_MACRO_CNTL_RESERVED0                              :TCPLL_MACRO_CNTL_RESERVED0;                        // 0x5FD0
  CPLL_MACRO_CNTL_RESERVED1                              :TCPLL_MACRO_CNTL_RESERVED1;                        // 0x5FD1
  CPLL_MACRO_CNTL_RESERVED2                              :TCPLL_MACRO_CNTL_RESERVED2;                        // 0x5FD2
  CPLL_MACRO_CNTL_RESERVED3                              :TCPLL_MACRO_CNTL_RESERVED3;                        // 0x5FD3
  CPLL_MACRO_CNTL_RESERVED4                              :TCPLL_MACRO_CNTL_RESERVED4;                        // 0x5FD4
  CPLL_MACRO_CNTL_RESERVED5                              :TCPLL_MACRO_CNTL_RESERVED5;                        // 0x5FD5
  CPLL_MACRO_CNTL_RESERVED6                              :TCPLL_MACRO_CNTL_RESERVED6;                        // 0x5FD6
  CPLL_MACRO_CNTL_RESERVED7                              :TCPLL_MACRO_CNTL_RESERVED7;                        // 0x5FD7
  CPLL_MACRO_CNTL_RESERVED8                              :TCPLL_MACRO_CNTL_RESERVED8;                        // 0x5FD8
  CPLL_MACRO_CNTL_RESERVED9                              :TCPLL_MACRO_CNTL_RESERVED9;                        // 0x5FD9
  CPLL_MACRO_CNTL_RESERVED10                             :TCPLL_MACRO_CNTL_RESERVED10;                       // 0x5FDA
  CPLL_MACRO_CNTL_RESERVED11                             :TCPLL_MACRO_CNTL_RESERVED11;                       // 0x5FDB
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0                   :DWORD;                                             // 0x5FDC
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1                   :DWORD;                                             // 0x5FDD
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2                   :DWORD;                                             // 0x5FDE
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3                   :DWORD;                                             // 0x5FDF
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4                   :DWORD;                                             // 0x5FE0
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5                   :DWORD;                                             // 0x5FE1
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6                   :DWORD;                                             // 0x5FE2
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7                   :DWORD;                                             // 0x5FE3
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8                   :DWORD;                                             // 0x5FE4
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9                   :DWORD;                                             // 0x5FE5
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10                  :DWORD;                                             // 0x5FE6
  DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11                  :DWORD;                                             // 0x5FE7
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0                   :DWORD;                                             // 0x5FE8
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1                   :DWORD;                                             // 0x5FE9
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2                   :DWORD;                                             // 0x5FEA
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3                   :DWORD;                                             // 0x5FEB
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4                   :DWORD;                                             // 0x5FEC
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5                   :DWORD;                                             // 0x5FED
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6                   :DWORD;                                             // 0x5FEE
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7                   :DWORD;                                             // 0x5FEF
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8                   :DWORD;                                             // 0x5FF0
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9                   :DWORD;                                             // 0x5FF1
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10                  :DWORD;                                             // 0x5FF2
  DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11                  :DWORD;                                             // 0x5FF3
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0                   :DWORD;                                             // 0x5FF4
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1                   :DWORD;                                             // 0x5FF5
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2                   :DWORD;                                             // 0x5FF6
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3                   :DWORD;                                             // 0x5FF7
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4                   :DWORD;                                             // 0x5FF8
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5                   :DWORD;                                             // 0x5FF9
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6                   :DWORD;                                             // 0x5FFA
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7                   :DWORD;                                             // 0x5FFB
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8                   :DWORD;                                             // 0x5FFC
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9                   :DWORD;                                             // 0x5FFD
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10                  :DWORD;                                             // 0x5FFE
  DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11                  :DWORD;                                             // 0x5FFF
  REG_6000_7BFF                                          :array[0..7167] of DWORD;                           // 0x6000
  SRBM_PERFMON_CNTL                                      :TSRBM_PERFMON_CNTL;                                // 0x7C00
  SRBM_PERFCOUNTER0_SELECT                               :TSRBM_PERFCOUNTER0_SELECT;                         // 0x7C01
  SRBM_PERFCOUNTER1_SELECT                               :TSRBM_PERFCOUNTER1_SELECT;                         // 0x7C02
  SRBM_PERFCOUNTER0_LO                                   :TSRBM_PERFCOUNTER0_LO;                             // 0x7C03
  SRBM_PERFCOUNTER0_HI                                   :TSRBM_PERFCOUNTER0_HI;                             // 0x7C04
  SRBM_PERFCOUNTER1_LO                                   :TSRBM_PERFCOUNTER1_LO;                             // 0x7C05
  SRBM_PERFCOUNTER1_HI                                   :TSRBM_PERFCOUNTER1_HI;                             // 0x7C06
  REG_7C07_8000                                          :array[0..1017] of DWORD;                           // 0x7C07
  VCE_STATUS                                             :TVCE_STATUS;                                       // 0x8001
  REG_8002_8004                                          :array[0..2] of DWORD;                              // 0x8002
  VCE_VCPU_CNTL                                          :TVCE_VCPU_CNTL;                                    // 0x8005
  REG_8006_8008                                          :array[0..2] of DWORD;                              // 0x8006
  VCE_VCPU_CACHE_OFFSET0                                 :TVCE_VCPU_CACHE_OFFSET0;                           // 0x8009
  VCE_VCPU_CACHE_SIZE0                                   :TVCE_VCPU_CACHE_SIZE0;                             // 0x800A
  VCE_VCPU_CACHE_OFFSET1                                 :TVCE_VCPU_CACHE_OFFSET1;                           // 0x800B
  VCE_VCPU_CACHE_SIZE1                                   :TVCE_VCPU_CACHE_SIZE1;                             // 0x800C
  VCE_VCPU_CACHE_OFFSET2                                 :TVCE_VCPU_CACHE_OFFSET2;                           // 0x800D
  VCE_VCPU_CACHE_SIZE2                                   :TVCE_VCPU_CACHE_SIZE2;                             // 0x800E
  REG_800F_8047                                          :array[0..56] of DWORD;                             // 0x800F
  VCE_SOFT_RESET                                         :TVCE_SOFT_RESET;                                   // 0x8048
  REG_8049_805A                                          :array[0..17] of DWORD;                             // 0x8049
  VCE_RB_BASE_LO2                                        :TVCE_RB_BASE_LO2;                                  // 0x805B
  VCE_RB_BASE_HI2                                        :TVCE_RB_BASE_HI2;                                  // 0x805C
  VCE_RB_SIZE2                                           :TVCE_RB_SIZE2;                                     // 0x805D
  VCE_RB_RPTR2                                           :TVCE_RB_RPTR2;                                     // 0x805E
  VCE_RB_WPTR2                                           :TVCE_RB_WPTR2;                                     // 0x805F
  VCE_RB_BASE_LO                                         :TVCE_RB_BASE_LO;                                   // 0x8060
  VCE_RB_BASE_HI                                         :TVCE_RB_BASE_HI;                                   // 0x8061
  VCE_RB_SIZE                                            :TVCE_RB_SIZE;                                      // 0x8062
  VCE_RB_RPTR                                            :TVCE_RB_RPTR;                                      // 0x8063
  VCE_RB_WPTR                                            :TVCE_RB_WPTR;                                      // 0x8064
  REG_8065_809E                                          :array[0..57] of DWORD;                             // 0x8065
  VCE_RB_ARB_CTRL                                        :TVCE_RB_ARB_CTRL;                                  // 0x809F
  REG_80A0_80D3                                          :array[0..51] of DWORD;                             // 0x80A0
  VCE_RB_BASE_LO3                                        :TVCE_RB_BASE_LO3;                                  // 0x80D4
  VCE_RB_BASE_HI3                                        :TVCE_RB_BASE_HI3;                                  // 0x80D5
  VCE_RB_SIZE3                                           :TVCE_RB_SIZE3;                                     // 0x80D6
  VCE_RB_RPTR3                                           :TVCE_RB_RPTR3;                                     // 0x80D7
  VCE_RB_WPTR3                                           :TVCE_RB_WPTR3;                                     // 0x80D8
  REG_80D9_838F                                          :array[0..694] of DWORD;                            // 0x80D9
  VCE_UENC_DMA_DCLK_CTRL                                 :TVCE_UENC_DMA_DCLK_CTRL;                           // 0x8390
  REG_8391_853F                                          :array[0..430] of DWORD;                            // 0x8391
  VCE_SYS_INT_EN                                         :TVCE_SYS_INT_EN;                                   // 0x8540
  VCE_SYS_INT_ACK                                        :TVCE_SYS_INT_ACK;                                  // 0x8541
  REG_8542_8596                                          :array[0..84] of DWORD;                             // 0x8542
  VCE_LMI_VCPU_CACHE_40BIT_BAR                           :TVCE_LMI_VCPU_CACHE_40BIT_BAR;                     // 0x8597
  REG_8598_859C                                          :array[0..4] of DWORD;                              // 0x8598
  VCE_LMI_CTRL2                                          :TVCE_LMI_CTRL2;                                    // 0x859D
  VCE_LMI_SWAP_CNTL3                                     :TVCE_LMI_SWAP_CNTL3;                               // 0x859E
  REG_859F_85A5                                          :array[0..6] of DWORD;                              // 0x859F
  VCE_LMI_CTRL                                           :TVCE_LMI_CTRL;                                     // 0x85A6
  REG_85A7_85AC                                          :array[0..5] of DWORD;                              // 0x85A7
  VCE_LMI_SWAP_CNTL                                      :TVCE_LMI_SWAP_CNTL;                                // 0x85AD
  VCE_LMI_SWAP_CNTL1                                     :TVCE_LMI_SWAP_CNTL1;                               // 0x85AE
  REG_85AF_85B2                                          :array[0..3] of DWORD;                              // 0x85AF
  VCE_LMI_SWAP_CNTL2                                     :TVCE_LMI_SWAP_CNTL2;                               // 0x85B3
  REG_85B4_85BC                                          :array[0..8] of DWORD;                              // 0x85B4
  VCE_LMI_CACHE_CTRL                                     :TVCE_LMI_CACHE_CTRL;                               // 0x85BD
  REG_85BE_880F                                          :array[0..593] of DWORD;                            // 0x85BE
  SAM_IH_EXT_ERR_INTR                                    :TSAM_IH_EXT_ERR_INTR;                              // 0x8810
  REG_8811                                               :DWORD;                                             // 0x8811
  SAM_IH_EXT_ERR_INTR_STATUS                             :TSAM_IH_EXT_ERR_INTR_STATUS;                       // 0x8812
  REG_8813_8FFF                                          :array[0..2028] of DWORD;                           // 0x8813
  SDMA0_PERFMON_CNTL                                     :TSDMA0_PERFMON_CNTL;                               // 0x9000
  SDMA0_PERFCOUNTER0_RESULT                              :TSDMA0_PERFCOUNTER0_RESULT;                        // 0x9001
  SDMA0_PERFCOUNTER1_RESULT                              :TSDMA0_PERFCOUNTER1_RESULT;                        // 0x9002
  REG_9003_900F                                          :array[0..12] of DWORD;                             // 0x9003
  SDMA1_PERFMON_CNTL                                     :TSDMA1_PERFMON_CNTL;                               // 0x9010
  SDMA1_PERFCOUNTER0_RESULT                              :TSDMA1_PERFCOUNTER0_RESULT;                        // 0x9011
  SDMA1_PERFCOUNTER1_RESULT                              :TSDMA1_PERFCOUNTER1_RESULT;                        // 0x9012
 end;

 TUSERCONFIG_REG_GROUP=bitpacked record
  CP_EOP_DONE_ADDR_LO              :TCP_EOP_DONE_ADDR_LO;               // 0xC000
  CP_EOP_DONE_ADDR_HI              :TCP_EOP_DONE_ADDR_HI;               // 0xC001
  CP_EOP_DONE_DATA_LO              :TCP_EOP_DONE_DATA_LO;               // 0xC002
  CP_EOP_DONE_DATA_HI              :TCP_EOP_DONE_DATA_HI;               // 0xC003
  CP_EOP_LAST_FENCE_LO             :TCP_EOP_LAST_FENCE_LO;              // 0xC004
  CP_EOP_LAST_FENCE_HI             :TCP_EOP_LAST_FENCE_HI;              // 0xC005
  CP_STREAM_OUT_ADDR_LO            :TCP_STREAM_OUT_ADDR_LO;             // 0xC006
  CP_STREAM_OUT_ADDR_HI            :TCP_STREAM_OUT_ADDR_HI;             // 0xC007
  CP_NUM_PRIM_WRITTEN_COUNT0_LO    :TCP_NUM_PRIM_WRITTEN_COUNT0_LO;     // 0xC008
  CP_NUM_PRIM_WRITTEN_COUNT0_HI    :TCP_NUM_PRIM_WRITTEN_COUNT0_HI;     // 0xC009
  CP_NUM_PRIM_NEEDED_COUNT0_LO     :TCP_NUM_PRIM_NEEDED_COUNT0_LO;      // 0xC00A
  CP_NUM_PRIM_NEEDED_COUNT0_HI     :TCP_NUM_PRIM_NEEDED_COUNT0_HI;      // 0xC00B
  CP_NUM_PRIM_WRITTEN_COUNT1_LO    :TCP_NUM_PRIM_WRITTEN_COUNT1_LO;     // 0xC00C
  CP_NUM_PRIM_WRITTEN_COUNT1_HI    :TCP_NUM_PRIM_WRITTEN_COUNT1_HI;     // 0xC00D
  CP_NUM_PRIM_NEEDED_COUNT1_LO     :TCP_NUM_PRIM_NEEDED_COUNT1_LO;      // 0xC00E
  CP_NUM_PRIM_NEEDED_COUNT1_HI     :TCP_NUM_PRIM_NEEDED_COUNT1_HI;      // 0xC00F
  CP_NUM_PRIM_WRITTEN_COUNT2_LO    :TCP_NUM_PRIM_WRITTEN_COUNT2_LO;     // 0xC010
  CP_NUM_PRIM_WRITTEN_COUNT2_HI    :TCP_NUM_PRIM_WRITTEN_COUNT2_HI;     // 0xC011
  CP_NUM_PRIM_NEEDED_COUNT2_LO     :TCP_NUM_PRIM_NEEDED_COUNT2_LO;      // 0xC012
  CP_NUM_PRIM_NEEDED_COUNT2_HI     :TCP_NUM_PRIM_NEEDED_COUNT2_HI;      // 0xC013
  CP_NUM_PRIM_WRITTEN_COUNT3_LO    :TCP_NUM_PRIM_WRITTEN_COUNT3_LO;     // 0xC014
  CP_NUM_PRIM_WRITTEN_COUNT3_HI    :TCP_NUM_PRIM_WRITTEN_COUNT3_HI;     // 0xC015
  CP_NUM_PRIM_NEEDED_COUNT3_LO     :TCP_NUM_PRIM_NEEDED_COUNT3_LO;      // 0xC016
  CP_NUM_PRIM_NEEDED_COUNT3_HI     :TCP_NUM_PRIM_NEEDED_COUNT3_HI;      // 0xC017
  CP_PIPE_STATS_ADDR_LO            :TCP_PIPE_STATS_ADDR_LO;             // 0xC018
  CP_PIPE_STATS_ADDR_HI            :TCP_PIPE_STATS_ADDR_HI;             // 0xC019
  CP_VGT_IAVERT_COUNT_LO           :TCP_VGT_IAVERT_COUNT_LO;            // 0xC01A
  CP_VGT_IAVERT_COUNT_HI           :TCP_VGT_IAVERT_COUNT_HI;            // 0xC01B
  CP_VGT_IAPRIM_COUNT_LO           :TCP_VGT_IAPRIM_COUNT_LO;            // 0xC01C
  CP_VGT_IAPRIM_COUNT_HI           :TCP_VGT_IAPRIM_COUNT_HI;            // 0xC01D
  CP_VGT_GSPRIM_COUNT_LO           :TCP_VGT_GSPRIM_COUNT_LO;            // 0xC01E
  CP_VGT_GSPRIM_COUNT_HI           :TCP_VGT_GSPRIM_COUNT_HI;            // 0xC01F
  CP_VGT_VSINVOC_COUNT_LO          :TCP_VGT_VSINVOC_COUNT_LO;           // 0xC020
  CP_VGT_VSINVOC_COUNT_HI          :TCP_VGT_VSINVOC_COUNT_HI;           // 0xC021
  CP_VGT_GSINVOC_COUNT_LO          :TCP_VGT_GSINVOC_COUNT_LO;           // 0xC022
  CP_VGT_GSINVOC_COUNT_HI          :TCP_VGT_GSINVOC_COUNT_HI;           // 0xC023
  CP_VGT_HSINVOC_COUNT_LO          :TCP_VGT_HSINVOC_COUNT_LO;           // 0xC024
  CP_VGT_HSINVOC_COUNT_HI          :TCP_VGT_HSINVOC_COUNT_HI;           // 0xC025
  CP_VGT_DSINVOC_COUNT_LO          :TCP_VGT_DSINVOC_COUNT_LO;           // 0xC026
  CP_VGT_DSINVOC_COUNT_HI          :TCP_VGT_DSINVOC_COUNT_HI;           // 0xC027
  CP_PA_CINVOC_COUNT_LO            :TCP_PA_CINVOC_COUNT_LO;             // 0xC028
  CP_PA_CINVOC_COUNT_HI            :TCP_PA_CINVOC_COUNT_HI;             // 0xC029
  CP_PA_CPRIM_COUNT_LO             :TCP_PA_CPRIM_COUNT_LO;              // 0xC02A
  CP_PA_CPRIM_COUNT_HI             :TCP_PA_CPRIM_COUNT_HI;              // 0xC02B
  CP_SC_PSINVOC_COUNT0_LO          :TCP_SC_PSINVOC_COUNT0_LO;           // 0xC02C
  CP_SC_PSINVOC_COUNT0_HI          :TCP_SC_PSINVOC_COUNT0_HI;           // 0xC02D
  CP_SC_PSINVOC_COUNT1_LO          :TCP_SC_PSINVOC_COUNT1_LO;           // 0xC02E
  CP_SC_PSINVOC_COUNT1_HI          :TCP_SC_PSINVOC_COUNT1_HI;           // 0xC02F
  CP_VGT_CSINVOC_COUNT_LO          :TCP_VGT_CSINVOC_COUNT_LO;           // 0xC030
  CP_VGT_CSINVOC_COUNT_HI          :TCP_VGT_CSINVOC_COUNT_HI;           // 0xC031
  REG_C032_C03C                    :array[0..10] of DWORD;              // 0xC032
  CP_PIPE_STATS_CONTROL            :TCP_PIPE_STATS_CONTROL;             // 0xC03D
  CP_STREAM_OUT_CONTROL            :TCP_STREAM_OUT_CONTROL;             // 0xC03E
  CP_STRMOUT_CNTL                  :TCP_STRMOUT_CNTL;                   // 0xC03F
  SCRATCH_REG0                     :TSCRATCH_REG0;                      // 0xC040
  SCRATCH_REG1                     :TSCRATCH_REG1;                      // 0xC041
  SCRATCH_REG2                     :TSCRATCH_REG2;                      // 0xC042
  SCRATCH_REG3                     :TSCRATCH_REG3;                      // 0xC043
  SCRATCH_REG4                     :TSCRATCH_REG4;                      // 0xC044
  SCRATCH_REG5                     :TSCRATCH_REG5;                      // 0xC045
  SCRATCH_REG6                     :TSCRATCH_REG6;                      // 0xC046
  SCRATCH_REG7                     :TSCRATCH_REG7;                      // 0xC047
  REG_C048_C04F                    :array[0..7] of DWORD;               // 0xC048
  SCRATCH_UMSK                     :TSCRATCH_UMSK;                      // 0xC050
  SCRATCH_ADDR                     :TSCRATCH_ADDR;                      // 0xC051
  CP_PFP_ATOMIC_PREOP_LO           :TCP_PFP_ATOMIC_PREOP_LO;            // 0xC052
  CP_PFP_ATOMIC_PREOP_HI           :TCP_PFP_ATOMIC_PREOP_HI;            // 0xC053
  CP_PFP_GDS_ATOMIC0_PREOP_LO      :TCP_PFP_GDS_ATOMIC0_PREOP_LO;       // 0xC054
  CP_PFP_GDS_ATOMIC0_PREOP_HI      :TCP_PFP_GDS_ATOMIC0_PREOP_HI;       // 0xC055
  CP_PFP_GDS_ATOMIC1_PREOP_LO      :TCP_PFP_GDS_ATOMIC1_PREOP_LO;       // 0xC056
  CP_PFP_GDS_ATOMIC1_PREOP_HI      :TCP_PFP_GDS_ATOMIC1_PREOP_HI;       // 0xC057
  CP_APPEND_ADDR_LO                :TCP_APPEND_ADDR_LO;                 // 0xC058
  CP_APPEND_ADDR_HI                :TCP_APPEND_ADDR_HI;                 // 0xC059
  CP_APPEND_DATA                   :TCP_APPEND_DATA;                    // 0xC05A
  CP_APPEND_LAST_CS_FENCE          :TCP_APPEND_LAST_CS_FENCE;           // 0xC05B
  CP_APPEND_LAST_PS_FENCE          :TCP_APPEND_LAST_PS_FENCE;           // 0xC05C
  CP_ATOMIC_PREOP_LO               :TCP_ATOMIC_PREOP_LO;                // 0xC05D
  CP_ATOMIC_PREOP_HI               :TCP_ATOMIC_PREOP_HI;                // 0xC05E
  CP_GDS_ATOMIC0_PREOP_LO          :TCP_GDS_ATOMIC0_PREOP_LO;           // 0xC05F
  CP_GDS_ATOMIC0_PREOP_HI          :TCP_GDS_ATOMIC0_PREOP_HI;           // 0xC060
  CP_GDS_ATOMIC1_PREOP_LO          :TCP_GDS_ATOMIC1_PREOP_LO;           // 0xC061
  CP_GDS_ATOMIC1_PREOP_HI          :TCP_GDS_ATOMIC1_PREOP_HI;           // 0xC062
  REG_C063_C068                    :array[0..5] of DWORD;               // 0xC063
  CP_ME_MC_WADDR_LO                :TCP_ME_MC_WADDR_LO;                 // 0xC069
  CP_ME_MC_WADDR_HI                :TCP_ME_MC_WADDR_HI;                 // 0xC06A
  CP_ME_MC_WDATA_LO                :TCP_ME_MC_WDATA_LO;                 // 0xC06B
  CP_ME_MC_WDATA_HI                :TCP_ME_MC_WDATA_HI;                 // 0xC06C
  CP_ME_MC_RADDR_LO                :TCP_ME_MC_RADDR_LO;                 // 0xC06D
  CP_ME_MC_RADDR_HI                :TCP_ME_MC_RADDR_HI;                 // 0xC06E
  CP_SEM_WAIT_TIMER                :TCP_SEM_WAIT_TIMER;                 // 0xC06F
  CP_SIG_SEM_ADDR_LO               :TCP_SIG_SEM_ADDR_LO;                // 0xC070
  CP_SIG_SEM_ADDR_HI               :TCP_SIG_SEM_ADDR_HI;                // 0xC071
  REG_C072_C073                    :array[0..1] of DWORD;               // 0xC072
  CP_WAIT_REG_MEM_TIMEOUT          :TCP_WAIT_REG_MEM_TIMEOUT;           // 0xC074
  CP_WAIT_SEM_ADDR_LO              :TCP_WAIT_SEM_ADDR_LO;               // 0xC075
  CP_WAIT_SEM_ADDR_HI              :TCP_WAIT_SEM_ADDR_HI;               // 0xC076
  CP_DMA_PFP_CONTROL               :TCP_DMA_PFP_CONTROL;                // 0xC077
  CP_DMA_ME_CONTROL                :TCP_DMA_ME_CONTROL;                 // 0xC078
  CP_COHER_BASE_HI                 :TCP_COHER_BASE_HI;                  // 0xC079
  REG_C07A                         :DWORD;                              // 0xC07A
  CP_COHER_START_DELAY             :TCP_COHER_START_DELAY;              // 0xC07B
  CP_COHER_CNTL                    :TCP_COHER_CNTL;                     // 0xC07C
  CP_COHER_SIZE                    :TCP_COHER_SIZE;                     // 0xC07D
  CP_COHER_BASE                    :TCP_COHER_BASE;                     // 0xC07E
  CP_COHER_STATUS                  :TCP_COHER_STATUS;                   // 0xC07F
  CP_DMA_ME_SRC_ADDR               :TCP_DMA_ME_SRC_ADDR;                // 0xC080
  CP_DMA_ME_SRC_ADDR_HI            :TCP_DMA_ME_SRC_ADDR_HI;             // 0xC081
  CP_DMA_ME_DST_ADDR               :TCP_DMA_ME_DST_ADDR;                // 0xC082
  CP_DMA_ME_DST_ADDR_HI            :TCP_DMA_ME_DST_ADDR_HI;             // 0xC083
  CP_DMA_ME_COMMAND                :TCP_DMA_ME_COMMAND;                 // 0xC084
  CP_DMA_PFP_SRC_ADDR              :TCP_DMA_PFP_SRC_ADDR;               // 0xC085
  CP_DMA_PFP_SRC_ADDR_HI           :TCP_DMA_PFP_SRC_ADDR_HI;            // 0xC086
  CP_DMA_PFP_DST_ADDR              :TCP_DMA_PFP_DST_ADDR;               // 0xC087
  CP_DMA_PFP_DST_ADDR_HI           :TCP_DMA_PFP_DST_ADDR_HI;            // 0xC088
  CP_DMA_PFP_COMMAND               :TCP_DMA_PFP_COMMAND;                // 0xC089
  CP_DMA_CNTL                      :TCP_DMA_CNTL;                       // 0xC08A
  CP_DMA_READ_TAGS                 :TCP_DMA_READ_TAGS;                  // 0xC08B
  CP_COHER_SIZE_HI                 :TCP_COHER_SIZE_HI;                  // 0xC08C
  CP_PFP_IB_CONTROL                :TCP_PFP_IB_CONTROL;                 // 0xC08D
  CP_PFP_LOAD_CONTROL              :TCP_PFP_LOAD_CONTROL;               // 0xC08E
  CP_SCRATCH_INDEX                 :TCP_SCRATCH_INDEX;                  // 0xC08F
  CP_SCRATCH_DATA                  :TCP_SCRATCH_DATA;                   // 0xC090
  CP_RB_OFFSET                     :TCP_RB_OFFSET;                      // 0xC091
  CP_IB1_OFFSET                    :TCP_IB1_OFFSET;                     // 0xC092
  CP_IB2_OFFSET                    :TCP_IB2_OFFSET;                     // 0xC093
  CP_IB1_PREAMBLE_BEGIN            :TCP_IB1_PREAMBLE_BEGIN;             // 0xC094
  CP_IB1_PREAMBLE_END              :TCP_IB1_PREAMBLE_END;               // 0xC095
  CP_IB2_PREAMBLE_BEGIN            :TCP_IB2_PREAMBLE_BEGIN;             // 0xC096
  CP_IB2_PREAMBLE_END              :TCP_IB2_PREAMBLE_END;               // 0xC097
  CP_CE_IB1_OFFSET                 :TCP_CE_IB1_OFFSET;                  // 0xC098
  CP_CE_IB2_OFFSET                 :TCP_CE_IB2_OFFSET;                  // 0xC099
  CP_CE_COUNTER                    :TCP_CE_COUNTER;                     // 0xC09A
  CP_CE_RB_OFFSET                  :TCP_CE_RB_OFFSET;                   // 0xC09B
  REG_C09C_C0C2                    :array[0..38] of DWORD;              // 0xC09C
  CP_CE_INIT_BASE_LO               :TCP_CE_INIT_BASE_LO;                // 0xC0C3
  CP_CE_INIT_BASE_HI               :TCP_CE_INIT_BASE_HI;                // 0xC0C4
  CP_CE_INIT_BUFSZ                 :TCP_CE_INIT_BUFSZ;                  // 0xC0C5
  CP_CE_IB1_BASE_LO                :TCP_CE_IB1_BASE_LO;                 // 0xC0C6
  CP_CE_IB1_BASE_HI                :TCP_CE_IB1_BASE_HI;                 // 0xC0C7
  CP_CE_IB1_BUFSZ                  :TCP_CE_IB1_BUFSZ;                   // 0xC0C8
  CP_CE_IB2_BASE_LO                :TCP_CE_IB2_BASE_LO;                 // 0xC0C9
  CP_CE_IB2_BASE_HI                :TCP_CE_IB2_BASE_HI;                 // 0xC0CA
  CP_CE_IB2_BUFSZ                  :TCP_CE_IB2_BUFSZ;                   // 0xC0CB
  CP_IB1_BASE_LO                   :TCP_IB1_BASE_LO;                    // 0xC0CC
  CP_IB1_BASE_HI                   :TCP_IB1_BASE_HI;                    // 0xC0CD
  CP_IB1_BUFSZ                     :TCP_IB1_BUFSZ;                      // 0xC0CE
  CP_IB2_BASE_LO                   :TCP_IB2_BASE_LO;                    // 0xC0CF
  CP_IB2_BASE_HI                   :TCP_IB2_BASE_HI;                    // 0xC0D0
  CP_IB2_BUFSZ                     :TCP_IB2_BUFSZ;                      // 0xC0D1
  CP_ST_BASE_LO                    :TCP_ST_BASE_LO;                     // 0xC0D2
  CP_ST_BASE_HI                    :TCP_ST_BASE_HI;                     // 0xC0D3
  CP_ST_BUFSZ                      :TCP_ST_BUFSZ;                       // 0xC0D4
  CP_EOP_DONE_EVENT_CNTL           :TCP_EOP_DONE_EVENT_CNTL;            // 0xC0D5
  CP_EOP_DONE_DATA_CNTL            :TCP_EOP_DONE_DATA_CNTL;             // 0xC0D6
  CP_EOP_DONE_CNTX_ID              :TCP_EOP_DONE_CNTX_ID;               // 0xC0D7
  REG_C0D8_C0EB                    :array[0..19] of DWORD;              // 0xC0D8
  CP_PFP_COMPLETION_STATUS         :TCP_PFP_COMPLETION_STATUS;          // 0xC0EC
  CP_CE_COMPLETION_STATUS          :TCP_CE_COMPLETION_STATUS;           // 0xC0ED
  CP_PRED_NOT_VISIBLE              :TCP_PRED_NOT_VISIBLE;               // 0xC0EE
  REG_C0EF                         :DWORD;                              // 0xC0EF
  CP_PFP_METADATA_BASE_ADDR        :TCP_PFP_METADATA_BASE_ADDR;         // 0xC0F0
  CP_PFP_METADATA_BASE_ADDR_HI     :TCP_PFP_METADATA_BASE_ADDR_HI;      // 0xC0F1
  CP_CE_METADATA_BASE_ADDR         :TCP_CE_METADATA_BASE_ADDR;          // 0xC0F2
  CP_CE_METADATA_BASE_ADDR_HI      :TCP_CE_METADATA_BASE_ADDR_HI;       // 0xC0F3
  CP_DRAW_INDX_INDR_ADDR           :TCP_DRAW_INDX_INDR_ADDR;            // 0xC0F4
  CP_DRAW_INDX_INDR_ADDR_HI        :TCP_DRAW_INDX_INDR_ADDR_HI;         // 0xC0F5
  CP_DISPATCH_INDR_ADDR            :TCP_DISPATCH_INDR_ADDR;             // 0xC0F6
  CP_DISPATCH_INDR_ADDR_HI         :TCP_DISPATCH_INDR_ADDR_HI;          // 0xC0F7
  CP_INDEX_BASE_ADDR               :TCP_INDEX_BASE_ADDR;                // 0xC0F8
  CP_INDEX_BASE_ADDR_HI            :TCP_INDEX_BASE_ADDR_HI;             // 0xC0F9
  CP_INDEX_TYPE                    :TCP_INDEX_TYPE;                     // 0xC0FA
  CP_GDS_BKUP_ADDR                 :TCP_GDS_BKUP_ADDR;                  // 0xC0FB
  CP_GDS_BKUP_ADDR_HI              :TCP_GDS_BKUP_ADDR_HI;               // 0xC0FC
  CP_SAMPLE_STATUS                 :TCP_SAMPLE_STATUS;                  // 0xC0FD
  REG_C0FE_C1FF                    :array[0..257] of DWORD;             // 0xC0FE
  GRBM_GFX_INDEX                   :TGRBM_GFX_INDEX;                    // 0xC200
  REG_C201_C23F                    :array[0..62] of DWORD;              // 0xC201
  VGT_ESGS_RING_SIZE               :TVGT_ESGS_RING_SIZE;                // 0xC240
  VGT_GSVS_RING_SIZE               :TVGT_GSVS_RING_SIZE;                // 0xC241
  VGT_PRIMITIVE_TYPE               :TVGT_PRIMITIVE_TYPE;                // 0xC242
  VGT_INDEX_TYPE                   :TVGT_INDEX_TYPE;                    // 0xC243
  VGT_STRMOUT_BUFFER_FILLED_SIZE_0 :TVGT_STRMOUT_BUFFER_FILLED_SIZE_0;  // 0xC244
  VGT_STRMOUT_BUFFER_FILLED_SIZE_1 :TVGT_STRMOUT_BUFFER_FILLED_SIZE_1;  // 0xC245
  VGT_STRMOUT_BUFFER_FILLED_SIZE_2 :TVGT_STRMOUT_BUFFER_FILLED_SIZE_2;  // 0xC246
  VGT_STRMOUT_BUFFER_FILLED_SIZE_3 :TVGT_STRMOUT_BUFFER_FILLED_SIZE_3;  // 0xC247
  REG_C248_C24B                    :array[0..3] of DWORD;               // 0xC248
  VGT_NUM_INDICES                  :TVGT_NUM_INDICES;                   // 0xC24C
  VGT_NUM_INSTANCES                :TVGT_NUM_INSTANCES;                 // 0xC24D
  VGT_TF_RING_SIZE                 :TVGT_TF_RING_SIZE;                  // 0xC24E
  VGT_HS_OFFCHIP_PARAM             :TVGT_HS_OFFCHIP_PARAM;              // 0xC24F
  VGT_TF_MEMORY_BASE               :TVGT_TF_MEMORY_BASE;                // 0xC250
  REG_C251_C27F                    :array[0..46] of DWORD;              // 0xC251
  PA_SU_LINE_STIPPLE_VALUE         :TPA_SU_LINE_STIPPLE_VALUE;          // 0xC280
  PA_SC_LINE_STIPPLE_STATE         :TPA_SC_LINE_STIPPLE_STATE;          // 0xC281
  REG_C282_C29F                    :array[0..29] of DWORD;              // 0xC282
  PA_SC_P3D_TRAP_SCREEN_HV_EN      :TPA_SC_P3D_TRAP_SCREEN_HV_EN;       // 0xC2A0
  PA_SC_P3D_TRAP_SCREEN_H          :TPA_SC_P3D_TRAP_SCREEN_H;           // 0xC2A1
  PA_SC_P3D_TRAP_SCREEN_V          :TPA_SC_P3D_TRAP_SCREEN_V;           // 0xC2A2
  PA_SC_P3D_TRAP_SCREEN_OCCURRENCE :TPA_SC_P3D_TRAP_SCREEN_OCCURRENCE;  // 0xC2A3
  PA_SC_P3D_TRAP_SCREEN_COUNT      :TPA_SC_P3D_TRAP_SCREEN_COUNT;       // 0xC2A4
  REG_C2A5_C2A7                    :array[0..2] of DWORD;               // 0xC2A5
  PA_SC_HP3D_TRAP_SCREEN_HV_EN     :TPA_SC_HP3D_TRAP_SCREEN_HV_EN;      // 0xC2A8
  PA_SC_HP3D_TRAP_SCREEN_H         :TPA_SC_HP3D_TRAP_SCREEN_H;          // 0xC2A9
  PA_SC_HP3D_TRAP_SCREEN_V         :TPA_SC_HP3D_TRAP_SCREEN_V;          // 0xC2AA
  PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE:TPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE; // 0xC2AB
  PA_SC_HP3D_TRAP_SCREEN_COUNT     :TPA_SC_HP3D_TRAP_SCREEN_COUNT;      // 0xC2AC
  REG_C2AD_C2AF                    :array[0..2] of DWORD;               // 0xC2AD
  PA_SC_TRAP_SCREEN_HV_EN          :TPA_SC_TRAP_SCREEN_HV_EN;           // 0xC2B0
  PA_SC_TRAP_SCREEN_H              :TPA_SC_TRAP_SCREEN_H;               // 0xC2B1
  PA_SC_TRAP_SCREEN_V              :TPA_SC_TRAP_SCREEN_V;               // 0xC2B2
  PA_SC_TRAP_SCREEN_OCCURRENCE     :TPA_SC_TRAP_SCREEN_OCCURRENCE;      // 0xC2B3
  PA_SC_TRAP_SCREEN_COUNT          :TPA_SC_TRAP_SCREEN_COUNT;           // 0xC2B4
  REG_C2B5_C32F                    :array[0..122] of DWORD;             // 0xC2B5
  SQ_THREAD_TRACE_BASE             :TSQ_THREAD_TRACE_BASE;              // 0xC330
  SQ_THREAD_TRACE_SIZE             :TSQ_THREAD_TRACE_SIZE;              // 0xC331
  SQ_THREAD_TRACE_MASK             :TSQ_THREAD_TRACE_MASK;              // 0xC332
  SQ_THREAD_TRACE_TOKEN_MASK       :TSQ_THREAD_TRACE_TOKEN_MASK;        // 0xC333
  SQ_THREAD_TRACE_PERF_MASK        :TSQ_THREAD_TRACE_PERF_MASK;         // 0xC334
  SQ_THREAD_TRACE_CTRL             :TSQ_THREAD_TRACE_CTRL;              // 0xC335
  SQ_THREAD_TRACE_MODE             :TSQ_THREAD_TRACE_MODE;              // 0xC336
  SQ_THREAD_TRACE_BASE2            :TSQ_THREAD_TRACE_BASE2;             // 0xC337
  SQ_THREAD_TRACE_TOKEN_MASK2      :TSQ_THREAD_TRACE_TOKEN_MASK2;       // 0xC338
  SQ_THREAD_TRACE_WPTR             :TSQ_THREAD_TRACE_WPTR;              // 0xC339
  SQ_THREAD_TRACE_STATUS           :TSQ_THREAD_TRACE_STATUS;            // 0xC33A
  SQ_THREAD_TRACE_HIWATER          :TSQ_THREAD_TRACE_HIWATER;           // 0xC33B
  REG_C33C_C33F                    :array[0..3] of DWORD;               // 0xC33C
  SQ_THREAD_TRACE_USERDATA_0       :TSQ_THREAD_TRACE_USERDATA_0;        // 0xC340
  SQ_THREAD_TRACE_USERDATA_1       :TSQ_THREAD_TRACE_USERDATA_1;        // 0xC341
  SQ_THREAD_TRACE_USERDATA_2       :TSQ_THREAD_TRACE_USERDATA_2;        // 0xC342
  SQ_THREAD_TRACE_USERDATA_3       :TSQ_THREAD_TRACE_USERDATA_3;        // 0xC343
  REG_C344_C347                    :array[0..3] of DWORD;               // 0xC344
  SQC_CACHES                       :TSQC_CACHES;                        // 0xC348
  SQC_WRITEBACK                    :TSQC_WRITEBACK;                     // 0xC349
  REG_C34A_C37F                    :array[0..53] of DWORD;              // 0xC34A
  TA_CS_BC_BASE_ADDR               :TTA_CS_BC_BASE_ADDR;                // 0xC380
  TA_CS_BC_BASE_ADDR_HI            :TTA_CS_BC_BASE_ADDR_HI;             // 0xC381
  REG_C382_C3BF                    :array[0..61] of DWORD;              // 0xC382
  DB_OCCLUSION_COUNT0_LOW          :TDB_OCCLUSION_COUNT0_LOW;           // 0xC3C0
  DB_OCCLUSION_COUNT0_HI           :TDB_OCCLUSION_COUNT0_HI;            // 0xC3C1
  DB_OCCLUSION_COUNT1_LOW          :TDB_OCCLUSION_COUNT1_LOW;           // 0xC3C2
  DB_OCCLUSION_COUNT1_HI           :TDB_OCCLUSION_COUNT1_HI;            // 0xC3C3
  DB_OCCLUSION_COUNT2_LOW          :TDB_OCCLUSION_COUNT2_LOW;           // 0xC3C4
  DB_OCCLUSION_COUNT2_HI           :TDB_OCCLUSION_COUNT2_HI;            // 0xC3C5
  DB_OCCLUSION_COUNT3_LOW          :TDB_OCCLUSION_COUNT3_LOW;           // 0xC3C6
  DB_OCCLUSION_COUNT3_HI           :TDB_OCCLUSION_COUNT3_HI;            // 0xC3C7
  REG_C3C8_C3FD                    :array[0..53] of DWORD;              // 0xC3C8
  DB_ZPASS_COUNT_LOW               :TDB_ZPASS_COUNT_LOW;                // 0xC3FE
  DB_ZPASS_COUNT_HI                :TDB_ZPASS_COUNT_HI;                 // 0xC3FF
  GDS_RD_ADDR                      :TGDS_RD_ADDR;                       // 0xC400
  GDS_RD_DATA                      :TGDS_RD_DATA;                       // 0xC401
  GDS_RD_BURST_ADDR                :TGDS_RD_BURST_ADDR;                 // 0xC402
  GDS_RD_BURST_COUNT               :TGDS_RD_BURST_COUNT;                // 0xC403
  GDS_RD_BURST_DATA                :TGDS_RD_BURST_DATA;                 // 0xC404
  GDS_WR_ADDR                      :TGDS_WR_ADDR;                       // 0xC405
  GDS_WR_DATA                      :TGDS_WR_DATA;                       // 0xC406
  GDS_WR_BURST_ADDR                :TGDS_WR_BURST_ADDR;                 // 0xC407
  GDS_WR_BURST_DATA                :TGDS_WR_BURST_DATA;                 // 0xC408
  GDS_WRITE_COMPLETE               :TGDS_WRITE_COMPLETE;                // 0xC409
  GDS_ATOM_CNTL                    :TGDS_ATOM_CNTL;                     // 0xC40A
  GDS_ATOM_COMPLETE                :TGDS_ATOM_COMPLETE;                 // 0xC40B
  GDS_ATOM_BASE                    :TGDS_ATOM_BASE;                     // 0xC40C
  GDS_ATOM_SIZE                    :TGDS_ATOM_SIZE;                     // 0xC40D
  GDS_ATOM_OFFSET0                 :TGDS_ATOM_OFFSET0;                  // 0xC40E
  GDS_ATOM_OFFSET1                 :TGDS_ATOM_OFFSET1;                  // 0xC40F
  GDS_ATOM_DST                     :TGDS_ATOM_DST;                      // 0xC410
  GDS_ATOM_OP                      :TGDS_ATOM_OP;                       // 0xC411
  GDS_ATOM_SRC0                    :TGDS_ATOM_SRC0;                     // 0xC412
  GDS_ATOM_SRC0_U                  :TGDS_ATOM_SRC0_U;                   // 0xC413
  GDS_ATOM_SRC1                    :TGDS_ATOM_SRC1;                     // 0xC414
  GDS_ATOM_SRC1_U                  :TGDS_ATOM_SRC1_U;                   // 0xC415
  GDS_ATOM_READ0                   :TGDS_ATOM_READ0;                    // 0xC416
  GDS_ATOM_READ0_U                 :TGDS_ATOM_READ0_U;                  // 0xC417
  GDS_ATOM_READ1                   :TGDS_ATOM_READ1;                    // 0xC418
  GDS_ATOM_READ1_U                 :TGDS_ATOM_READ1_U;                  // 0xC419
  GDS_GWS_RESOURCE_CNTL            :TGDS_GWS_RESOURCE_CNTL;             // 0xC41A
  GDS_GWS_RESOURCE                 :TGDS_GWS_RESOURCE;                  // 0xC41B
  GDS_GWS_RESOURCE_CNT             :TGDS_GWS_RESOURCE_CNT;              // 0xC41C
  GDS_OA_CNTL                      :TGDS_OA_CNTL;                       // 0xC41D
  GDS_OA_COUNTER                   :TGDS_OA_COUNTER;                    // 0xC41E
  GDS_OA_ADDRESS                   :TGDS_OA_ADDRESS;                    // 0xC41F
  GDS_OA_INCDEC                    :TGDS_OA_INCDEC;                     // 0xC420
  GDS_OA_RING_SIZE                 :TGDS_OA_RING_SIZE;                  // 0xC421
  REG_C422_CFFF                    :array[0..3037] of DWORD;            // 0xC422
  CPG_PERFCOUNTER1_LO              :TCPG_PERFCOUNTER1_LO;               // 0xD000
  CPG_PERFCOUNTER1_HI              :TCPG_PERFCOUNTER1_HI;               // 0xD001
  CPG_PERFCOUNTER0_LO              :TCPG_PERFCOUNTER0_LO;               // 0xD002
  CPG_PERFCOUNTER0_HI              :TCPG_PERFCOUNTER0_HI;               // 0xD003
  CPC_PERFCOUNTER1_LO              :TCPC_PERFCOUNTER1_LO;               // 0xD004
  CPC_PERFCOUNTER1_HI              :TCPC_PERFCOUNTER1_HI;               // 0xD005
  CPC_PERFCOUNTER0_LO              :TCPC_PERFCOUNTER0_LO;               // 0xD006
  CPC_PERFCOUNTER0_HI              :TCPC_PERFCOUNTER0_HI;               // 0xD007
  CPF_PERFCOUNTER1_LO              :TCPF_PERFCOUNTER1_LO;               // 0xD008
  CPF_PERFCOUNTER1_HI              :TCPF_PERFCOUNTER1_HI;               // 0xD009
  CPF_PERFCOUNTER0_LO              :TCPF_PERFCOUNTER0_LO;               // 0xD00A
  CPF_PERFCOUNTER0_HI              :TCPF_PERFCOUNTER0_HI;               // 0xD00B
  REG_D00C_D03F                    :array[0..51] of DWORD;              // 0xD00C
  GRBM_PERFCOUNTER0_LO             :TGRBM_PERFCOUNTER0_LO;              // 0xD040
  GRBM_PERFCOUNTER0_HI             :TGRBM_PERFCOUNTER0_HI;              // 0xD041
  REG_D042                         :DWORD;                              // 0xD042
  GRBM_PERFCOUNTER1_LO             :TGRBM_PERFCOUNTER1_LO;              // 0xD043
  GRBM_PERFCOUNTER1_HI             :TGRBM_PERFCOUNTER1_HI;              // 0xD044
  GRBM_SE0_PERFCOUNTER_LO          :TGRBM_SE0_PERFCOUNTER_LO;           // 0xD045
  GRBM_SE0_PERFCOUNTER_HI          :TGRBM_SE0_PERFCOUNTER_HI;           // 0xD046
  GRBM_SE1_PERFCOUNTER_LO          :TGRBM_SE1_PERFCOUNTER_LO;           // 0xD047
  GRBM_SE1_PERFCOUNTER_HI          :TGRBM_SE1_PERFCOUNTER_HI;           // 0xD048
  GRBM_SE2_PERFCOUNTER_LO          :TGRBM_SE2_PERFCOUNTER_LO;           // 0xD049
  GRBM_SE2_PERFCOUNTER_HI          :TGRBM_SE2_PERFCOUNTER_HI;           // 0xD04A
  GRBM_SE3_PERFCOUNTER_LO          :TGRBM_SE3_PERFCOUNTER_LO;           // 0xD04B
  GRBM_SE3_PERFCOUNTER_HI          :TGRBM_SE3_PERFCOUNTER_HI;           // 0xD04C
  REG_D04D_D07F                    :array[0..50] of DWORD;              // 0xD04D
  WD_PERFCOUNTER0_LO               :TWD_PERFCOUNTER0_LO;                // 0xD080
  WD_PERFCOUNTER0_HI               :TWD_PERFCOUNTER0_HI;                // 0xD081
  WD_PERFCOUNTER1_LO               :TWD_PERFCOUNTER1_LO;                // 0xD082
  WD_PERFCOUNTER1_HI               :TWD_PERFCOUNTER1_HI;                // 0xD083
  WD_PERFCOUNTER2_LO               :TWD_PERFCOUNTER2_LO;                // 0xD084
  WD_PERFCOUNTER2_HI               :TWD_PERFCOUNTER2_HI;                // 0xD085
  WD_PERFCOUNTER3_LO               :TWD_PERFCOUNTER3_LO;                // 0xD086
  WD_PERFCOUNTER3_HI               :TWD_PERFCOUNTER3_HI;                // 0xD087
  IA_PERFCOUNTER0_LO               :TIA_PERFCOUNTER0_LO;                // 0xD088
  IA_PERFCOUNTER0_HI               :TIA_PERFCOUNTER0_HI;                // 0xD089
  IA_PERFCOUNTER1_LO               :TIA_PERFCOUNTER1_LO;                // 0xD08A
  IA_PERFCOUNTER1_HI               :TIA_PERFCOUNTER1_HI;                // 0xD08B
  IA_PERFCOUNTER2_LO               :TIA_PERFCOUNTER2_LO;                // 0xD08C
  IA_PERFCOUNTER2_HI               :TIA_PERFCOUNTER2_HI;                // 0xD08D
  IA_PERFCOUNTER3_LO               :TIA_PERFCOUNTER3_LO;                // 0xD08E
  IA_PERFCOUNTER3_HI               :TIA_PERFCOUNTER3_HI;                // 0xD08F
  VGT_PERFCOUNTER0_LO              :TVGT_PERFCOUNTER0_LO;               // 0xD090
  VGT_PERFCOUNTER0_HI              :TVGT_PERFCOUNTER0_HI;               // 0xD091
  VGT_PERFCOUNTER1_LO              :TVGT_PERFCOUNTER1_LO;               // 0xD092
  VGT_PERFCOUNTER1_HI              :TVGT_PERFCOUNTER1_HI;               // 0xD093
  VGT_PERFCOUNTER2_LO              :TVGT_PERFCOUNTER2_LO;               // 0xD094
  VGT_PERFCOUNTER2_HI              :TVGT_PERFCOUNTER2_HI;               // 0xD095
  VGT_PERFCOUNTER3_LO              :TVGT_PERFCOUNTER3_LO;               // 0xD096
  VGT_PERFCOUNTER3_HI              :TVGT_PERFCOUNTER3_HI;               // 0xD097
  REG_D098_D0FF                    :array[0..103] of DWORD;             // 0xD098
  PA_SU_PERFCOUNTER0_LO            :TPA_SU_PERFCOUNTER0_LO;             // 0xD100
  PA_SU_PERFCOUNTER0_HI            :TPA_SU_PERFCOUNTER0_HI;             // 0xD101
  PA_SU_PERFCOUNTER1_LO            :TPA_SU_PERFCOUNTER1_LO;             // 0xD102
  PA_SU_PERFCOUNTER1_HI            :TPA_SU_PERFCOUNTER1_HI;             // 0xD103
  PA_SU_PERFCOUNTER2_LO            :TPA_SU_PERFCOUNTER2_LO;             // 0xD104
  PA_SU_PERFCOUNTER2_HI            :TPA_SU_PERFCOUNTER2_HI;             // 0xD105
  PA_SU_PERFCOUNTER3_LO            :TPA_SU_PERFCOUNTER3_LO;             // 0xD106
  PA_SU_PERFCOUNTER3_HI            :TPA_SU_PERFCOUNTER3_HI;             // 0xD107
  REG_D108_D13F                    :array[0..55] of DWORD;              // 0xD108
  PA_SC_PERFCOUNTER0_LO            :TPA_SC_PERFCOUNTER0_LO;             // 0xD140
  PA_SC_PERFCOUNTER0_HI            :TPA_SC_PERFCOUNTER0_HI;             // 0xD141
  PA_SC_PERFCOUNTER1_LO            :TPA_SC_PERFCOUNTER1_LO;             // 0xD142
  PA_SC_PERFCOUNTER1_HI            :TPA_SC_PERFCOUNTER1_HI;             // 0xD143
  PA_SC_PERFCOUNTER2_LO            :TPA_SC_PERFCOUNTER2_LO;             // 0xD144
  PA_SC_PERFCOUNTER2_HI            :TPA_SC_PERFCOUNTER2_HI;             // 0xD145
  PA_SC_PERFCOUNTER3_LO            :TPA_SC_PERFCOUNTER3_LO;             // 0xD146
  PA_SC_PERFCOUNTER3_HI            :TPA_SC_PERFCOUNTER3_HI;             // 0xD147
  PA_SC_PERFCOUNTER4_LO            :TPA_SC_PERFCOUNTER4_LO;             // 0xD148
  PA_SC_PERFCOUNTER4_HI            :TPA_SC_PERFCOUNTER4_HI;             // 0xD149
  PA_SC_PERFCOUNTER5_LO            :TPA_SC_PERFCOUNTER5_LO;             // 0xD14A
  PA_SC_PERFCOUNTER5_HI            :TPA_SC_PERFCOUNTER5_HI;             // 0xD14B
  PA_SC_PERFCOUNTER6_LO            :TPA_SC_PERFCOUNTER6_LO;             // 0xD14C
  PA_SC_PERFCOUNTER6_HI            :TPA_SC_PERFCOUNTER6_HI;             // 0xD14D
  PA_SC_PERFCOUNTER7_LO            :TPA_SC_PERFCOUNTER7_LO;             // 0xD14E
  PA_SC_PERFCOUNTER7_HI            :TPA_SC_PERFCOUNTER7_HI;             // 0xD14F
  REG_D150_D17F                    :array[0..47] of DWORD;              // 0xD150
  SPI_PERFCOUNTER0_HI              :TSPI_PERFCOUNTER0_HI;               // 0xD180
  SPI_PERFCOUNTER0_LO              :TSPI_PERFCOUNTER0_LO;               // 0xD181
  SPI_PERFCOUNTER1_HI              :TSPI_PERFCOUNTER1_HI;               // 0xD182
  SPI_PERFCOUNTER1_LO              :TSPI_PERFCOUNTER1_LO;               // 0xD183
  SPI_PERFCOUNTER2_HI              :TSPI_PERFCOUNTER2_HI;               // 0xD184
  SPI_PERFCOUNTER2_LO              :TSPI_PERFCOUNTER2_LO;               // 0xD185
  SPI_PERFCOUNTER3_HI              :TSPI_PERFCOUNTER3_HI;               // 0xD186
  SPI_PERFCOUNTER3_LO              :TSPI_PERFCOUNTER3_LO;               // 0xD187
  SPI_PERFCOUNTER4_HI              :TSPI_PERFCOUNTER4_HI;               // 0xD188
  SPI_PERFCOUNTER4_LO              :TSPI_PERFCOUNTER4_LO;               // 0xD189
  SPI_PERFCOUNTER5_HI              :TSPI_PERFCOUNTER5_HI;               // 0xD18A
  SPI_PERFCOUNTER5_LO              :TSPI_PERFCOUNTER5_LO;               // 0xD18B
  REG_D18C_D1BF                    :array[0..51] of DWORD;              // 0xD18C
  SQ_PERFCOUNTER0_LO               :TSQ_PERFCOUNTER0_LO;                // 0xD1C0
  SQ_PERFCOUNTER0_HI               :TSQ_PERFCOUNTER0_HI;                // 0xD1C1
  SQ_PERFCOUNTER1_LO               :TSQ_PERFCOUNTER1_LO;                // 0xD1C2
  SQ_PERFCOUNTER1_HI               :TSQ_PERFCOUNTER1_HI;                // 0xD1C3
  SQ_PERFCOUNTER2_LO               :TSQ_PERFCOUNTER2_LO;                // 0xD1C4
  SQ_PERFCOUNTER2_HI               :TSQ_PERFCOUNTER2_HI;                // 0xD1C5
  SQ_PERFCOUNTER3_LO               :TSQ_PERFCOUNTER3_LO;                // 0xD1C6
  SQ_PERFCOUNTER3_HI               :TSQ_PERFCOUNTER3_HI;                // 0xD1C7
  SQ_PERFCOUNTER4_LO               :TSQ_PERFCOUNTER4_LO;                // 0xD1C8
  SQ_PERFCOUNTER4_HI               :TSQ_PERFCOUNTER4_HI;                // 0xD1C9
  SQ_PERFCOUNTER5_LO               :TSQ_PERFCOUNTER5_LO;                // 0xD1CA
  SQ_PERFCOUNTER5_HI               :TSQ_PERFCOUNTER5_HI;                // 0xD1CB
  SQ_PERFCOUNTER6_LO               :TSQ_PERFCOUNTER6_LO;                // 0xD1CC
  SQ_PERFCOUNTER6_HI               :TSQ_PERFCOUNTER6_HI;                // 0xD1CD
  SQ_PERFCOUNTER7_LO               :TSQ_PERFCOUNTER7_LO;                // 0xD1CE
  SQ_PERFCOUNTER7_HI               :TSQ_PERFCOUNTER7_HI;                // 0xD1CF
  SQ_PERFCOUNTER8_LO               :TSQ_PERFCOUNTER8_LO;                // 0xD1D0
  SQ_PERFCOUNTER8_HI               :TSQ_PERFCOUNTER8_HI;                // 0xD1D1
  SQ_PERFCOUNTER9_LO               :TSQ_PERFCOUNTER9_LO;                // 0xD1D2
  SQ_PERFCOUNTER9_HI               :TSQ_PERFCOUNTER9_HI;                // 0xD1D3
  SQ_PERFCOUNTER10_LO              :TSQ_PERFCOUNTER10_LO;               // 0xD1D4
  SQ_PERFCOUNTER10_HI              :TSQ_PERFCOUNTER10_HI;               // 0xD1D5
  SQ_PERFCOUNTER11_LO              :TSQ_PERFCOUNTER11_LO;               // 0xD1D6
  SQ_PERFCOUNTER11_HI              :TSQ_PERFCOUNTER11_HI;               // 0xD1D7
  SQ_PERFCOUNTER12_LO              :TSQ_PERFCOUNTER12_LO;               // 0xD1D8
  SQ_PERFCOUNTER12_HI              :TSQ_PERFCOUNTER12_HI;               // 0xD1D9
  SQ_PERFCOUNTER13_LO              :TSQ_PERFCOUNTER13_LO;               // 0xD1DA
  SQ_PERFCOUNTER13_HI              :TSQ_PERFCOUNTER13_HI;               // 0xD1DB
  SQ_PERFCOUNTER14_LO              :TSQ_PERFCOUNTER14_LO;               // 0xD1DC
  SQ_PERFCOUNTER14_HI              :TSQ_PERFCOUNTER14_HI;               // 0xD1DD
  SQ_PERFCOUNTER15_LO              :TSQ_PERFCOUNTER15_LO;               // 0xD1DE
  SQ_PERFCOUNTER15_HI              :TSQ_PERFCOUNTER15_HI;               // 0xD1DF
  REG_D1E0_D23F                    :array[0..95] of DWORD;              // 0xD1E0
  SX_PERFCOUNTER0_LO               :TSX_PERFCOUNTER0_LO;                // 0xD240
  SX_PERFCOUNTER0_HI               :TSX_PERFCOUNTER0_HI;                // 0xD241
  SX_PERFCOUNTER1_LO               :TSX_PERFCOUNTER1_LO;                // 0xD242
  SX_PERFCOUNTER1_HI               :TSX_PERFCOUNTER1_HI;                // 0xD243
  SX_PERFCOUNTER2_LO               :TSX_PERFCOUNTER2_LO;                // 0xD244
  SX_PERFCOUNTER2_HI               :TSX_PERFCOUNTER2_HI;                // 0xD245
  SX_PERFCOUNTER3_LO               :TSX_PERFCOUNTER3_LO;                // 0xD246
  SX_PERFCOUNTER3_HI               :TSX_PERFCOUNTER3_HI;                // 0xD247
  REG_D248_D27F                    :array[0..55] of DWORD;              // 0xD248
  GDS_PERFCOUNTER0_LO              :TGDS_PERFCOUNTER0_LO;               // 0xD280
  GDS_PERFCOUNTER0_HI              :TGDS_PERFCOUNTER0_HI;               // 0xD281
  GDS_PERFCOUNTER1_LO              :TGDS_PERFCOUNTER1_LO;               // 0xD282
  GDS_PERFCOUNTER1_HI              :TGDS_PERFCOUNTER1_HI;               // 0xD283
  GDS_PERFCOUNTER2_LO              :TGDS_PERFCOUNTER2_LO;               // 0xD284
  GDS_PERFCOUNTER2_HI              :TGDS_PERFCOUNTER2_HI;               // 0xD285
  GDS_PERFCOUNTER3_LO              :TGDS_PERFCOUNTER3_LO;               // 0xD286
  GDS_PERFCOUNTER3_HI              :TGDS_PERFCOUNTER3_HI;               // 0xD287
  REG_D288_D2BF                    :array[0..55] of DWORD;              // 0xD288
  TA_PERFCOUNTER0_LO               :TTA_PERFCOUNTER0_LO;                // 0xD2C0
  TA_PERFCOUNTER0_HI               :TTA_PERFCOUNTER0_HI;                // 0xD2C1
  TA_PERFCOUNTER1_LO               :TTA_PERFCOUNTER1_LO;                // 0xD2C2
  TA_PERFCOUNTER1_HI               :TTA_PERFCOUNTER1_HI;                // 0xD2C3
  REG_D2C4_D2FF                    :array[0..59] of DWORD;              // 0xD2C4
  TD_PERFCOUNTER0_LO               :TTD_PERFCOUNTER0_LO;                // 0xD300
  TD_PERFCOUNTER0_HI               :TTD_PERFCOUNTER0_HI;                // 0xD301
  TD_PERFCOUNTER1_LO               :TTD_PERFCOUNTER1_LO;                // 0xD302
  TD_PERFCOUNTER1_HI               :TTD_PERFCOUNTER1_HI;                // 0xD303
  REG_D304_D33F                    :array[0..59] of DWORD;              // 0xD304
  TCP_PERFCOUNTER0_LO              :TTCP_PERFCOUNTER0_LO;               // 0xD340
  TCP_PERFCOUNTER0_HI              :TTCP_PERFCOUNTER0_HI;               // 0xD341
  TCP_PERFCOUNTER1_LO              :TTCP_PERFCOUNTER1_LO;               // 0xD342
  TCP_PERFCOUNTER1_HI              :TTCP_PERFCOUNTER1_HI;               // 0xD343
  TCP_PERFCOUNTER2_LO              :TTCP_PERFCOUNTER2_LO;               // 0xD344
  TCP_PERFCOUNTER2_HI              :TTCP_PERFCOUNTER2_HI;               // 0xD345
  TCP_PERFCOUNTER3_LO              :TTCP_PERFCOUNTER3_LO;               // 0xD346
  TCP_PERFCOUNTER3_HI              :TTCP_PERFCOUNTER3_HI;               // 0xD347
  REG_D348_D37F                    :array[0..55] of DWORD;              // 0xD348
  TCC_PERFCOUNTER0_LO              :TTCC_PERFCOUNTER0_LO;               // 0xD380
  TCC_PERFCOUNTER0_HI              :TTCC_PERFCOUNTER0_HI;               // 0xD381
  TCC_PERFCOUNTER1_LO              :TTCC_PERFCOUNTER1_LO;               // 0xD382
  TCC_PERFCOUNTER1_HI              :TTCC_PERFCOUNTER1_HI;               // 0xD383
  TCC_PERFCOUNTER2_LO              :TTCC_PERFCOUNTER2_LO;               // 0xD384
  TCC_PERFCOUNTER2_HI              :TTCC_PERFCOUNTER2_HI;               // 0xD385
  TCC_PERFCOUNTER3_LO              :TTCC_PERFCOUNTER3_LO;               // 0xD386
  TCC_PERFCOUNTER3_HI              :TTCC_PERFCOUNTER3_HI;               // 0xD387
  REG_D388_D38F                    :array[0..7] of DWORD;               // 0xD388
  TCA_PERFCOUNTER0_LO              :TTCA_PERFCOUNTER0_LO;               // 0xD390
  TCA_PERFCOUNTER0_HI              :TTCA_PERFCOUNTER0_HI;               // 0xD391
  TCA_PERFCOUNTER1_LO              :TTCA_PERFCOUNTER1_LO;               // 0xD392
  TCA_PERFCOUNTER1_HI              :TTCA_PERFCOUNTER1_HI;               // 0xD393
  TCA_PERFCOUNTER2_LO              :TTCA_PERFCOUNTER2_LO;               // 0xD394
  TCA_PERFCOUNTER2_HI              :TTCA_PERFCOUNTER2_HI;               // 0xD395
  TCA_PERFCOUNTER3_LO              :TTCA_PERFCOUNTER3_LO;               // 0xD396
  TCA_PERFCOUNTER3_HI              :TTCA_PERFCOUNTER3_HI;               // 0xD397
  REG_D398_D405                    :array[0..109] of DWORD;             // 0xD398
  CB_PERFCOUNTER0_LO               :TCB_PERFCOUNTER0_LO;                // 0xD406
  CB_PERFCOUNTER0_HI               :TCB_PERFCOUNTER0_HI;                // 0xD407
  CB_PERFCOUNTER1_LO               :TCB_PERFCOUNTER1_LO;                // 0xD408
  CB_PERFCOUNTER1_HI               :TCB_PERFCOUNTER1_HI;                // 0xD409
  CB_PERFCOUNTER2_LO               :TCB_PERFCOUNTER2_LO;                // 0xD40A
  CB_PERFCOUNTER2_HI               :TCB_PERFCOUNTER2_HI;                // 0xD40B
  CB_PERFCOUNTER3_LO               :TCB_PERFCOUNTER3_LO;                // 0xD40C
  CB_PERFCOUNTER3_HI               :TCB_PERFCOUNTER3_HI;                // 0xD40D
  REG_D40E_D43F                    :array[0..49] of DWORD;              // 0xD40E
  DB_PERFCOUNTER0_LO               :TDB_PERFCOUNTER0_LO;                // 0xD440
  DB_PERFCOUNTER0_HI               :TDB_PERFCOUNTER0_HI;                // 0xD441
  DB_PERFCOUNTER1_LO               :TDB_PERFCOUNTER1_LO;                // 0xD442
  DB_PERFCOUNTER1_HI               :TDB_PERFCOUNTER1_HI;                // 0xD443
  DB_PERFCOUNTER2_LO               :TDB_PERFCOUNTER2_LO;                // 0xD444
  DB_PERFCOUNTER2_HI               :TDB_PERFCOUNTER2_HI;                // 0xD445
  DB_PERFCOUNTER3_LO               :TDB_PERFCOUNTER3_LO;                // 0xD446
  DB_PERFCOUNTER3_HI               :TDB_PERFCOUNTER3_HI;                // 0xD447
  REG_D448_D47F                    :array[0..55] of DWORD;              // 0xD448
  RLC_PERFCOUNTER0_LO              :TRLC_PERFCOUNTER0_LO;               // 0xD480
  RLC_PERFCOUNTER0_HI              :TRLC_PERFCOUNTER0_HI;               // 0xD481
  RLC_PERFCOUNTER1_LO              :TRLC_PERFCOUNTER1_LO;               // 0xD482
  RLC_PERFCOUNTER1_HI              :TRLC_PERFCOUNTER1_HI;               // 0xD483
  REG_D484_D7FF                    :array[0..891] of DWORD;             // 0xD484
  CPG_PERFCOUNTER1_SELECT          :TCPG_PERFCOUNTER1_SELECT;           // 0xD800
  CPG_PERFCOUNTER0_SELECT1         :TCPG_PERFCOUNTER0_SELECT1;          // 0xD801
  CPG_PERFCOUNTER0_SELECT          :TCPG_PERFCOUNTER0_SELECT;           // 0xD802
  CPC_PERFCOUNTER1_SELECT          :TCPC_PERFCOUNTER1_SELECT;           // 0xD803
  CPC_PERFCOUNTER0_SELECT1         :TCPC_PERFCOUNTER0_SELECT1;          // 0xD804
  CPF_PERFCOUNTER1_SELECT          :TCPF_PERFCOUNTER1_SELECT;           // 0xD805
  CPF_PERFCOUNTER0_SELECT1         :TCPF_PERFCOUNTER0_SELECT1;          // 0xD806
  CPF_PERFCOUNTER0_SELECT          :TCPF_PERFCOUNTER0_SELECT;           // 0xD807
  CP_PERFMON_CNTL                  :TCP_PERFMON_CNTL;                   // 0xD808
  CPC_PERFCOUNTER0_SELECT          :TCPC_PERFCOUNTER0_SELECT;           // 0xD809
  REG_D80A_D80F                    :array[0..5] of DWORD;               // 0xD80A
  CP_DRAW_OBJECT                   :TCP_DRAW_OBJECT;                    // 0xD810
  CP_DRAW_OBJECT_COUNTER           :TCP_DRAW_OBJECT_COUNTER;            // 0xD811
  CP_DRAW_WINDOW_MASK_HI           :TCP_DRAW_WINDOW_MASK_HI;            // 0xD812
  CP_DRAW_WINDOW_HI                :TCP_DRAW_WINDOW_HI;                 // 0xD813
  CP_DRAW_WINDOW_LO                :TCP_DRAW_WINDOW_LO;                 // 0xD814
  CP_DRAW_WINDOW_CNTL              :TCP_DRAW_WINDOW_CNTL;               // 0xD815
  REG_D816_D83F                    :array[0..41] of DWORD;              // 0xD816
  GRBM_PERFCOUNTER0_SELECT         :TGRBM_PERFCOUNTER0_SELECT;          // 0xD840
  GRBM_PERFCOUNTER1_SELECT         :TGRBM_PERFCOUNTER1_SELECT;          // 0xD841
  GRBM_SE0_PERFCOUNTER_SELECT      :TGRBM_SE0_PERFCOUNTER_SELECT;       // 0xD842
  GRBM_SE1_PERFCOUNTER_SELECT      :TGRBM_SE1_PERFCOUNTER_SELECT;       // 0xD843
  GRBM_SE2_PERFCOUNTER_SELECT      :TGRBM_SE2_PERFCOUNTER_SELECT;       // 0xD844
  GRBM_SE3_PERFCOUNTER_SELECT      :TGRBM_SE3_PERFCOUNTER_SELECT;       // 0xD845
  REG_D846_D87F                    :array[0..57] of DWORD;              // 0xD846
  WD_PERFCOUNTER0_SELECT           :TWD_PERFCOUNTER0_SELECT;            // 0xD880
  WD_PERFCOUNTER1_SELECT           :TWD_PERFCOUNTER1_SELECT;            // 0xD881
  WD_PERFCOUNTER2_SELECT           :TWD_PERFCOUNTER2_SELECT;            // 0xD882
  WD_PERFCOUNTER3_SELECT           :TWD_PERFCOUNTER3_SELECT;            // 0xD883
  IA_PERFCOUNTER0_SELECT           :TIA_PERFCOUNTER0_SELECT;            // 0xD884
  IA_PERFCOUNTER1_SELECT           :TIA_PERFCOUNTER1_SELECT;            // 0xD885
  IA_PERFCOUNTER2_SELECT           :TIA_PERFCOUNTER2_SELECT;            // 0xD886
  IA_PERFCOUNTER3_SELECT           :TIA_PERFCOUNTER3_SELECT;            // 0xD887
  IA_PERFCOUNTER0_SELECT1          :TIA_PERFCOUNTER0_SELECT1;           // 0xD888
  REG_D889_D88B                    :array[0..2] of DWORD;               // 0xD889
  VGT_PERFCOUNTER0_SELECT          :TVGT_PERFCOUNTER0_SELECT;           // 0xD88C
  VGT_PERFCOUNTER1_SELECT          :TVGT_PERFCOUNTER1_SELECT;           // 0xD88D
  VGT_PERFCOUNTER2_SELECT          :TVGT_PERFCOUNTER2_SELECT;           // 0xD88E
  VGT_PERFCOUNTER3_SELECT          :TVGT_PERFCOUNTER3_SELECT;           // 0xD88F
  VGT_PERFCOUNTER0_SELECT1         :TVGT_PERFCOUNTER0_SELECT1;          // 0xD890
  VGT_PERFCOUNTER1_SELECT1         :TVGT_PERFCOUNTER1_SELECT1;          // 0xD891
  REG_D892_D893                    :array[0..1] of DWORD;               // 0xD892
  VGT_PERFCOUNTER_SEID_MASK        :TVGT_PERFCOUNTER_SEID_MASK;         // 0xD894
  REG_D895_D8FF                    :array[0..106] of DWORD;             // 0xD895
  PA_SU_PERFCOUNTER0_SELECT        :TPA_SU_PERFCOUNTER0_SELECT;         // 0xD900
  PA_SU_PERFCOUNTER0_SELECT1       :TPA_SU_PERFCOUNTER0_SELECT1;        // 0xD901
  PA_SU_PERFCOUNTER1_SELECT        :TPA_SU_PERFCOUNTER1_SELECT;         // 0xD902
  PA_SU_PERFCOUNTER1_SELECT1       :TPA_SU_PERFCOUNTER1_SELECT1;        // 0xD903
  PA_SU_PERFCOUNTER2_SELECT        :TPA_SU_PERFCOUNTER2_SELECT;         // 0xD904
  PA_SU_PERFCOUNTER3_SELECT        :TPA_SU_PERFCOUNTER3_SELECT;         // 0xD905
  REG_D906_D93F                    :array[0..57] of DWORD;              // 0xD906
  PA_SC_PERFCOUNTER0_SELECT        :TPA_SC_PERFCOUNTER0_SELECT;         // 0xD940
  PA_SC_PERFCOUNTER0_SELECT1       :TPA_SC_PERFCOUNTER0_SELECT1;        // 0xD941
  PA_SC_PERFCOUNTER1_SELECT        :TPA_SC_PERFCOUNTER1_SELECT;         // 0xD942
  PA_SC_PERFCOUNTER2_SELECT        :TPA_SC_PERFCOUNTER2_SELECT;         // 0xD943
  PA_SC_PERFCOUNTER3_SELECT        :TPA_SC_PERFCOUNTER3_SELECT;         // 0xD944
  PA_SC_PERFCOUNTER4_SELECT        :TPA_SC_PERFCOUNTER4_SELECT;         // 0xD945
  PA_SC_PERFCOUNTER5_SELECT        :TPA_SC_PERFCOUNTER5_SELECT;         // 0xD946
  PA_SC_PERFCOUNTER6_SELECT        :TPA_SC_PERFCOUNTER6_SELECT;         // 0xD947
  PA_SC_PERFCOUNTER7_SELECT        :TPA_SC_PERFCOUNTER7_SELECT;         // 0xD948
  REG_D949_D97F                    :array[0..54] of DWORD;              // 0xD949
  SPI_PERFCOUNTER0_SELECT          :TSPI_PERFCOUNTER0_SELECT;           // 0xD980
  SPI_PERFCOUNTER1_SELECT          :TSPI_PERFCOUNTER1_SELECT;           // 0xD981
  SPI_PERFCOUNTER2_SELECT          :TSPI_PERFCOUNTER2_SELECT;           // 0xD982
  SPI_PERFCOUNTER3_SELECT          :TSPI_PERFCOUNTER3_SELECT;           // 0xD983
  SPI_PERFCOUNTER0_SELECT1         :TSPI_PERFCOUNTER0_SELECT1;          // 0xD984
  SPI_PERFCOUNTER1_SELECT1         :TSPI_PERFCOUNTER1_SELECT1;          // 0xD985
  SPI_PERFCOUNTER2_SELECT1         :TSPI_PERFCOUNTER2_SELECT1;          // 0xD986
  SPI_PERFCOUNTER3_SELECT1         :TSPI_PERFCOUNTER3_SELECT1;          // 0xD987
  SPI_PERFCOUNTER4_SELECT          :TSPI_PERFCOUNTER4_SELECT;           // 0xD988
  SPI_PERFCOUNTER5_SELECT          :TSPI_PERFCOUNTER5_SELECT;           // 0xD989
  SPI_PERFCOUNTER_BINS             :TSPI_PERFCOUNTER_BINS;              // 0xD98A
  REG_D98B_D9BF                    :array[0..52] of DWORD;              // 0xD98B
  SQ_PERFCOUNTER0_SELECT           :TSQ_PERFCOUNTER0_SELECT;            // 0xD9C0
  SQ_PERFCOUNTER1_SELECT           :TSQ_PERFCOUNTER1_SELECT;            // 0xD9C1
  SQ_PERFCOUNTER2_SELECT           :TSQ_PERFCOUNTER2_SELECT;            // 0xD9C2
  SQ_PERFCOUNTER3_SELECT           :TSQ_PERFCOUNTER3_SELECT;            // 0xD9C3
  SQ_PERFCOUNTER4_SELECT           :TSQ_PERFCOUNTER4_SELECT;            // 0xD9C4
  SQ_PERFCOUNTER5_SELECT           :TSQ_PERFCOUNTER5_SELECT;            // 0xD9C5
  SQ_PERFCOUNTER6_SELECT           :TSQ_PERFCOUNTER6_SELECT;            // 0xD9C6
  SQ_PERFCOUNTER7_SELECT           :TSQ_PERFCOUNTER7_SELECT;            // 0xD9C7
  SQ_PERFCOUNTER8_SELECT           :TSQ_PERFCOUNTER8_SELECT;            // 0xD9C8
  SQ_PERFCOUNTER9_SELECT           :TSQ_PERFCOUNTER9_SELECT;            // 0xD9C9
  SQ_PERFCOUNTER10_SELECT          :TSQ_PERFCOUNTER10_SELECT;           // 0xD9CA
  SQ_PERFCOUNTER11_SELECT          :TSQ_PERFCOUNTER11_SELECT;           // 0xD9CB
  SQ_PERFCOUNTER12_SELECT          :TSQ_PERFCOUNTER12_SELECT;           // 0xD9CC
  SQ_PERFCOUNTER13_SELECT          :TSQ_PERFCOUNTER13_SELECT;           // 0xD9CD
  SQ_PERFCOUNTER14_SELECT          :TSQ_PERFCOUNTER14_SELECT;           // 0xD9CE
  SQ_PERFCOUNTER15_SELECT          :TSQ_PERFCOUNTER15_SELECT;           // 0xD9CF
  REG_D9D0_D9DF                    :array[0..15] of DWORD;              // 0xD9D0
  SQ_PERFCOUNTER_CTRL              :TSQ_PERFCOUNTER_CTRL;               // 0xD9E0
  SQ_PERFCOUNTER_MASK              :TSQ_PERFCOUNTER_MASK;               // 0xD9E1
  SQ_PERFCOUNTER_CTRL2             :TSQ_PERFCOUNTER_CTRL2;              // 0xD9E2
  REG_D9E3_DA3F                    :array[0..92] of DWORD;              // 0xD9E3
  SX_PERFCOUNTER0_SELECT           :TSX_PERFCOUNTER0_SELECT;            // 0xDA40
  SX_PERFCOUNTER1_SELECT           :TSX_PERFCOUNTER1_SELECT;            // 0xDA41
  SX_PERFCOUNTER2_SELECT           :TSX_PERFCOUNTER2_SELECT;            // 0xDA42
  SX_PERFCOUNTER3_SELECT           :TSX_PERFCOUNTER3_SELECT;            // 0xDA43
  SX_PERFCOUNTER0_SELECT1          :TSX_PERFCOUNTER0_SELECT1;           // 0xDA44
  SX_PERFCOUNTER1_SELECT1          :TSX_PERFCOUNTER1_SELECT1;           // 0xDA45
  REG_DA46_DA7F                    :array[0..57] of DWORD;              // 0xDA46
  GDS_PERFCOUNTER0_SELECT          :TGDS_PERFCOUNTER0_SELECT;           // 0xDA80
  GDS_PERFCOUNTER1_SELECT          :TGDS_PERFCOUNTER1_SELECT;           // 0xDA81
  GDS_PERFCOUNTER2_SELECT          :TGDS_PERFCOUNTER2_SELECT;           // 0xDA82
  GDS_PERFCOUNTER3_SELECT          :TGDS_PERFCOUNTER3_SELECT;           // 0xDA83
  GDS_PERFCOUNTER0_SELECT1         :TGDS_PERFCOUNTER0_SELECT1;          // 0xDA84
  REG_DA85_DABF                    :array[0..58] of DWORD;              // 0xDA85
  TA_PERFCOUNTER0_SELECT           :TTA_PERFCOUNTER0_SELECT;            // 0xDAC0
  TA_PERFCOUNTER0_SELECT1          :TTA_PERFCOUNTER0_SELECT1;           // 0xDAC1
  TA_PERFCOUNTER1_SELECT           :TTA_PERFCOUNTER1_SELECT;            // 0xDAC2
  REG_DAC3_DAFF                    :array[0..60] of DWORD;              // 0xDAC3
  TD_PERFCOUNTER0_SELECT           :TTD_PERFCOUNTER0_SELECT;            // 0xDB00
  TD_PERFCOUNTER0_SELECT1          :TTD_PERFCOUNTER0_SELECT1;           // 0xDB01
  TD_PERFCOUNTER1_SELECT           :TTD_PERFCOUNTER1_SELECT;            // 0xDB02
  REG_DB03_DB3F                    :array[0..60] of DWORD;              // 0xDB03
  TCP_PERFCOUNTER0_SELECT          :TTCP_PERFCOUNTER0_SELECT;           // 0xDB40
  TCP_PERFCOUNTER0_SELECT1         :TTCP_PERFCOUNTER0_SELECT1;          // 0xDB41
  TCP_PERFCOUNTER1_SELECT          :TTCP_PERFCOUNTER1_SELECT;           // 0xDB42
  TCP_PERFCOUNTER1_SELECT1         :TTCP_PERFCOUNTER1_SELECT1;          // 0xDB43
  TCP_PERFCOUNTER2_SELECT          :TTCP_PERFCOUNTER2_SELECT;           // 0xDB44
  TCP_PERFCOUNTER3_SELECT          :TTCP_PERFCOUNTER3_SELECT;           // 0xDB45
  REG_DB46_DB7F                    :array[0..57] of DWORD;              // 0xDB46
  TCC_PERFCOUNTER0_SELECT          :TTCC_PERFCOUNTER0_SELECT;           // 0xDB80
  TCC_PERFCOUNTER0_SELECT1         :TTCC_PERFCOUNTER0_SELECT1;          // 0xDB81
  TCC_PERFCOUNTER1_SELECT          :TTCC_PERFCOUNTER1_SELECT;           // 0xDB82
  TCC_PERFCOUNTER1_SELECT1         :TTCC_PERFCOUNTER1_SELECT1;          // 0xDB83
  TCC_PERFCOUNTER2_SELECT          :TTCC_PERFCOUNTER2_SELECT;           // 0xDB84
  TCC_PERFCOUNTER3_SELECT          :TTCC_PERFCOUNTER3_SELECT;           // 0xDB85
  REG_DB86_DB8F                    :array[0..9] of DWORD;               // 0xDB86
  TCA_PERFCOUNTER0_SELECT          :TTCA_PERFCOUNTER0_SELECT;           // 0xDB90
  TCA_PERFCOUNTER0_SELECT1         :TTCA_PERFCOUNTER0_SELECT1;          // 0xDB91
  TCA_PERFCOUNTER1_SELECT          :TTCA_PERFCOUNTER1_SELECT;           // 0xDB92
  TCA_PERFCOUNTER1_SELECT1         :TTCA_PERFCOUNTER1_SELECT1;          // 0xDB93
  TCA_PERFCOUNTER2_SELECT          :TTCA_PERFCOUNTER2_SELECT;           // 0xDB94
  TCA_PERFCOUNTER3_SELECT          :TTCA_PERFCOUNTER3_SELECT;           // 0xDB95
  REG_DB96_DBFF                    :array[0..105] of DWORD;             // 0xDB96
  CB_PERFCOUNTER_FILTER            :TCB_PERFCOUNTER_FILTER;             // 0xDC00
  CB_PERFCOUNTER0_SELECT           :TCB_PERFCOUNTER0_SELECT;            // 0xDC01
  CB_PERFCOUNTER0_SELECT1          :TCB_PERFCOUNTER0_SELECT1;           // 0xDC02
  CB_PERFCOUNTER1_SELECT           :TCB_PERFCOUNTER1_SELECT;            // 0xDC03
  CB_PERFCOUNTER2_SELECT           :TCB_PERFCOUNTER2_SELECT;            // 0xDC04
  CB_PERFCOUNTER3_SELECT           :TCB_PERFCOUNTER3_SELECT;            // 0xDC05
  REG_DC06_DC3F                    :array[0..57] of DWORD;              // 0xDC06
  DB_PERFCOUNTER0_SELECT           :TDB_PERFCOUNTER0_SELECT;            // 0xDC40
  DB_PERFCOUNTER0_SELECT1          :TDB_PERFCOUNTER0_SELECT1;           // 0xDC41
  DB_PERFCOUNTER1_SELECT           :TDB_PERFCOUNTER1_SELECT;            // 0xDC42
  DB_PERFCOUNTER1_SELECT1          :TDB_PERFCOUNTER1_SELECT1;           // 0xDC43
  DB_PERFCOUNTER2_SELECT           :TDB_PERFCOUNTER2_SELECT;            // 0xDC44
  REG_DC45                         :DWORD;                              // 0xDC45
  DB_PERFCOUNTER3_SELECT           :TDB_PERFCOUNTER3_SELECT;            // 0xDC46
 end;


implementation

end.

