unit si_ci_vi_merged_registers;

{$mode objfpc}{$H+}

interface

uses
 bittype;

type
 TLX0=bit32;

 TLX1=bit32;

 TLX2=bit32;

 TLX3=bit32;

 TBIST=bitpacked record
  BIST_COMP:bit4;
  RESERVED0:bit2;
  BIST_STRT:bit1;
  BIST_CAP :bit1;
  RESERVED1:bit24;
 end;

 TEXP0=bit32;

 TEXP1=bit32;

 TEXP2=bit32;

 TEXP3=bit32;

 TEXP4=bit32;

 TEXP5=bit32;

 TEXP6=bit32;

 TEXP7=bit32;

 TATTRX=bitpacked record
  ATTR_IDX       :bit5;
  ATTR_PAL_RW_ENB:bit1;
  RESERVED0      :bit26;
 end;

 TCRT00=bitpacked record
  H_TOTAL  :bit8;
  RESERVED0:bit24;
 end;

 TCRT01=bitpacked record
  H_DISP_END:bit8;
  RESERVED0 :bit24;
 end;

 TCRT02=bitpacked record
  H_BLANK_START:bit8;
  RESERVED0    :bit24;
 end;

 TCRT03=bitpacked record
  H_BLANK_END     :bit5;
  H_DE_SKEW       :bit2;
  CR10CR11_R_DIS_B:bit1;
  RESERVED0       :bit24;
 end;

 TCRT04=bitpacked record
  H_SYNC_START:bit8;
  RESERVED0   :bit24;
 end;

 TCRT05=bitpacked record
  H_SYNC_END    :bit5;
  H_SYNC_SKEW   :bit2;
  H_BLANK_END_B5:bit1;
  RESERVED0     :bit24;
 end;

 TCRT06=bitpacked record
  V_TOTAL  :bit8;
  RESERVED0:bit24;
 end;

 TCRT07=bitpacked record
  V_TOTAL_B8      :bit1;
  V_DISP_END_B8   :bit1;
  V_SYNC_START_B8 :bit1;
  V_BLANK_START_B8:bit1;
  LINE_CMP_B8     :bit1;
  V_TOTAL_B9      :bit1;
  V_DISP_END_B9   :bit1;
  V_SYNC_START_B9 :bit1;
  RESERVED0       :bit24;
 end;

 TCRT08=bitpacked record
  ROW_SCAN_START:bit5;
  BYTE_PAN      :bit2;
  RESERVED0     :bit25;
 end;

 TCRT09=bitpacked record
  MAX_ROW_SCAN      :bit5;
  V_BLANK_START_B9  :bit1;
  LINE_CMP_B9       :bit1;
  DOUBLE_CHAR_HEIGHT:bit1;
  RESERVED0         :bit24;
 end;

 TCRT0A=bitpacked record
  CURSOR_START  :bit5;
  CURSOR_DISABLE:bit1;
  RESERVED0     :bit26;
 end;

 TCRT0B=bitpacked record
  CURSOR_END :bit5;
  CURSOR_SKEW:bit2;
  RESERVED0  :bit25;
 end;

 TCRT0C=bitpacked record
  DISP_START:bit8;
  RESERVED0 :bit24;
 end;

 TCRT0D=bitpacked record
  DISP_START:bit8;
  RESERVED0 :bit24;
 end;

 TCRT0E=bitpacked record
  CURSOR_LOC_HI:bit8;
  RESERVED0    :bit24;
 end;

 TCRT0F=bitpacked record
  CURSOR_LOC_LO:bit8;
  RESERVED0    :bit24;
 end;

 TCRT10=bitpacked record
  V_SYNC_START:bit8;
  RESERVED0   :bit24;
 end;

 TCRT11=bitpacked record
  V_SYNC_END      :bit4;
  V_INTR_CLR      :bit1;
  V_INTR_EN       :bit1;
  SEL5_REFRESH_CYC:bit1;
  C0T7_WR_ONLY    :bit1;
  RESERVED0       :bit24;
 end;

 TCRT12=bitpacked record
  V_DISP_END:bit8;
  RESERVED0 :bit24;
 end;

 TCRT13=bitpacked record
  DISP_PITCH:bit8;
  RESERVED0 :bit24;
 end;

 TCRT14=bitpacked record
  UNDRLN_LOC  :bit5;
  ADDR_CNT_BY4:bit1;
  DOUBLE_WORD :bit1;
  RESERVED0   :bit25;
 end;

 TCRT15=bitpacked record
  V_BLANK_START:bit8;
  RESERVED0    :bit24;
 end;

 TCRT16=bitpacked record
  V_BLANK_END:bit8;
  RESERVED0  :bit24;
 end;

 TCRT17=bitpacked record
  RA0_AS_A13B :bit1;
  RA1_AS_A14B :bit1;
  VCOUNT_BY2  :bit1;
  ADDR_CNT_BY2:bit1;
  RESERVED0   :bit1;
  WRAP_A15TOA0:bit1;
  BYTE_MODE   :bit1;
  CRTC_SYNC_EN:bit1;
  RESERVED1   :bit24;
 end;

 TCRT18=bitpacked record
  LINE_CMP :bit8;
  RESERVED0:bit24;
 end;

 TCRT1E=bitpacked record
  RESERVED0   :bit1;
  GRPH_DEC_RD1:bit1;
  RESERVED1   :bit30;
 end;

 TCRT1F=bitpacked record
  GRPH_DEC_RD0:bit8;
  RESERVED0   :bit24;
 end;

 TCRT22=bitpacked record
  GRPH_LATCH_DATA:bit8;
  RESERVED0      :bit24;
 end;

 TGENS0=bitpacked record
  RESERVED0   :bit4;
  SENSE_SWITCH:bit1;
  RESERVED1   :bit2;
  CRT_INTR    :bit1;
  RESERVED2   :bit24;
 end;

 TGENS1=bitpacked record
  NO_DISPLAY     :bit1;
  RESERVED0      :bit2;
  VGA_VSTATUS    :bit1;
  PIXEL_READ_BACK:bit2;
  RESERVED1      :bit26;
 end;

 TGRA00=bitpacked record
  GRPH_SET_RESET0:bit1;
  GRPH_SET_RESET1:bit1;
  GRPH_SET_RESET2:bit1;
  GRPH_SET_RESET3:bit1;
  RESERVED0      :bit28;
 end;

 TGRA01=bitpacked record
  GRPH_SET_RESET_ENA0:bit1;
  GRPH_SET_RESET_ENA1:bit1;
  GRPH_SET_RESET_ENA2:bit1;
  GRPH_SET_RESET_ENA3:bit1;
  RESERVED0          :bit28;
 end;

 TGRA02=bitpacked record
  GRPH_CCOMP:bit4;
  RESERVED0 :bit28;
 end;

 TGRA03=bitpacked record
  GRPH_ROTATE:bit3;
  GRPH_FN_SEL:bit2;
  RESERVED0  :bit27;
 end;

 TGRA04=bitpacked record
  GRPH_RMAP:bit2;
  RESERVED0:bit30;
 end;

 TGRA05=bitpacked record
  GRPH_WRITE_MODE:bit2;
  RESERVED0      :bit1;
  GRPH_READ1     :bit1;
  CGA_ODDEVEN    :bit1;
  GRPH_OES       :bit1;
  GRPH_PACK      :bit1;
  RESERVED1      :bit25;
 end;

 TGRA06=bitpacked record
  GRPH_GRAPHICS:bit1;
  GRPH_ODDEVEN :bit1;
  GRPH_ADRSEL  :bit2;
  RESERVED0    :bit28;
 end;

 TGRA07=bitpacked record
  GRPH_XCARE0:bit1;
  GRPH_XCARE1:bit1;
  GRPH_XCARE2:bit1;
  GRPH_XCARE3:bit1;
  RESERVED0  :bit28;
 end;

 TGRA08=bitpacked record
  GRPH_BMSK:bit8;
  RESERVED0:bit24;
 end;

 TKHFS0=bit32;

 TKHFS1=bit32;

 TKHFS2=bit32;

 TKHFS3=bit32;

 TKSIG0=bit32;

 TKSIG1=bit32;

 TKSIG2=bit32;

 TKSIG3=bit32;

 TSEQ00=bitpacked record
  SEQ_RST0B:bit1;
  SEQ_RST1B:bit1;
  RESERVED0:bit30;
 end;

 TSEQ01=bitpacked record
  SEQ_DOT8   :bit1;
  RESERVED0  :bit1;
  SEQ_SHIFT2 :bit1;
  SEQ_PCLKBY2:bit1;
  SEQ_SHIFT4 :bit1;
  SEQ_MAXBW  :bit1;
  RESERVED1  :bit26;
 end;

 TSEQ02=bitpacked record
  SEQ_MAP0_EN:bit1;
  SEQ_MAP1_EN:bit1;
  SEQ_MAP2_EN:bit1;
  SEQ_MAP3_EN:bit1;
  RESERVED0  :bit28;
 end;

 TSEQ03=bitpacked record
  SEQ_FONT_B1:bit1;
  SEQ_FONT_B2:bit1;
  SEQ_FONT_A1:bit1;
  SEQ_FONT_A2:bit1;
  SEQ_FONT_B0:bit1;
  SEQ_FONT_A0:bit1;
  RESERVED0  :bit26;
 end;

 TSEQ04=bitpacked record
  RESERVED0  :bit1;
  SEQ_256K   :bit1;
  SEQ_ODDEVEN:bit1;
  SEQ_CHAIN  :bit1;
  RESERVED1  :bit28;
 end;

 TATTR00=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR01=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR02=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR03=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR04=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR05=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR06=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR07=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR08=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR09=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR0A=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR0B=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR0C=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR0D=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR0E=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR0F=bitpacked record
  ATTR_PAL :bit6;
  RESERVED0:bit26;
 end;

 TATTR10=bitpacked record
  ATTR_GRPH_MODE :bit1;
  ATTR_MONO_EN   :bit1;
  ATTR_LGRPH_EN  :bit1;
  ATTR_BLINK_EN  :bit1;
  RESERVED0      :bit1;
  ATTR_PANTOPONLY:bit1;
  ATTR_PCLKBY2   :bit1;
  ATTR_CSEL_EN   :bit1;
  RESERVED1      :bit24;
 end;

 TATTR11=bitpacked record
  ATTR_OVSC:bit8;
  RESERVED0:bit24;
 end;

 TATTR12=bitpacked record
  ATTR_MAP_EN:bit4;
  ATTR_VSMUX :bit2;
  RESERVED0  :bit26;
 end;

 TATTR13=bitpacked record
  ATTR_PPAN:bit4;
  RESERVED0:bit28;
 end;

 TATTR14=bitpacked record
  ATTR_CSEL1:bit2;
  ATTR_CSEL2:bit2;
  RESERVED0 :bit28;
 end;

 TATTRDR=bitpacked record
  ATTR_DATA:bit8;
  RESERVED0:bit24;
 end;

 TATTRDW=bitpacked record
  ATTR_DATA:bit8;
  RESERVED0:bit24;
 end;

 TGENENB=bitpacked record
  BLK_IO_BASE:bit8;
  RESERVED0  :bit24;
 end;

 THEADER=bitpacked record
  HEADER_TYPE:bit7;
  DEVICE_TYPE:bit1;
  RESERVED0  :bit24;
 end;

 TSMC_PC=bitpacked record
  RESERVED0:bit30;
  RESERVED1:bit2;
 end;

 TSQ_CMD=bitpacked record
  CMD       :bit3;
  RESERVED0 :bit1;
  MODE      :bit3;
  CHECK_VMID:bit1;
  DATA      :bit3;
  RESERVED1 :bit5;
  WAVE_ID   :bit4;
  SIMD_ID   :bit2;
  RESERVED2 :bit2;
  QUEUE_ID  :bit3;
  RESERVED3 :bit1;
  VM_ID     :bit4;
 end;

 TSTATUS=bitpacked record
  RESERVED0               :bit3;
  INT_STATUS              :bit1;
  CAP_LIST                :bit1;
  PCI_66_EN               :bit1;
  RESERVED1               :bit1;
  FAST_BACK_CAPABLE       :bit1;
  MASTER_DATA_PARITY_ERROR:bit1;
  DEVSEL_TIMING           :bit2;
  SIGNAL_TARGET_ABORT     :bit1;
  RECEIVED_TARGET_ABORT   :bit1;
  RECEIVED_MASTER_ABORT   :bit1;
  SIGNALED_SYSTEM_ERROR   :bit1;
  PARITY_ERROR_DETECTED   :bit1;
  RESERVED2               :bit16;
 end;

 TWD_QOS=bitpacked record
  DRAW_STALL:bit1;
  RESERVED0 :bit31;
 end;

 TCAP_PTR=bitpacked record
  CAP_PTR  :bit8;
  RESERVED0:bit24;
 end;

 TCM_STAT=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit30;
 end;

 TCOMMAND=bitpacked record
  IO_ACCESS_EN           :bit1;
  MEM_ACCESS_EN          :bit1;
  BUS_MASTER_EN          :bit1;
  SPECIAL_CYCLE_EN       :bit1;
  MEM_WRITE_INVALIDATE_EN:bit1;
  PAL_SNOOP_EN           :bit1;
  PARITY_ERROR_RESPONSE  :bit1;
  AD_STEPPING            :bit1;
  SERR_EN                :bit1;
  FAST_B2B_EN            :bit1;
  INT_DIS                :bit1;
  RESERVED0              :bit21;
 end;

 TCP_CNTL=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit31;
 end;

 TCP_STAT=bitpacked record
  RESERVED0            :bit9;
  ROQ_RING_BUSY        :bit1;
  ROQ_INDIRECT1_BUSY   :bit1;
  ROQ_INDIRECT2_BUSY   :bit1;
  ROQ_STATE_BUSY       :bit1;
  DC_BUSY              :bit1;
  ATCL2IU_BUSY         :bit1;
  PFP_BUSY             :bit1;
  MEQ_BUSY             :bit1;
  ME_BUSY              :bit1;
  QUERY_BUSY           :bit1;
  SEMAPHORE_BUSY       :bit1;
  INTERRUPT_BUSY       :bit1;
  SURFACE_SYNC_BUSY    :bit1;
  DMA_BUSY             :bit1;
  RCIU_BUSY            :bit1;
  SCRATCH_RAM_BUSY     :bit1;
  CPC_CPG_BUSY         :bit1;
  CE_BUSY              :bit1;
  TCIU_BUSY            :bit1;
  ROQ_CE_RING_BUSY     :bit1;
  ROQ_CE_INDIRECT1_BUSY:bit1;
  ROQ_CE_INDIRECT2_BUSY:bit1;
  CP_BUSY              :bit1;
 end;

 TCP_VMID=bitpacked record
  VMID     :bit4;
  RESERVED0:bit28;
 end;

 TDB_EQAA=bitpacked record
  MAX_ANCHOR_SAMPLES            :bit3;
  RESERVED0                     :bit1;
  PS_ITER_SAMPLES               :bit3;
  RESERVED1                     :bit1;
  MASK_EXPORT_NUM_SAMPLES       :bit3;
  RESERVED2                     :bit1;
  ALPHA_TO_MASK_NUM_SAMPLES     :bit3;
  RESERVED3                     :bit1;
  HIGH_QUALITY_INTERSECTIONS    :bit1;
  INCOHERENT_EQAA_READS         :bit1;
  INTERPOLATE_COMP_Z            :bit1;
  INTERPOLATE_SRC_Z             :bit1;
  STATIC_ANCHOR_ASSOCIATIONS    :bit1;
  ALPHA_TO_MASK_EQAA_DISABLE    :bit1;
  RESERVED4                     :bit2;
  OVERRASTERIZATION_AMOUNT      :bit3;
  ENABLE_POSTZ_OVERRASTERIZATION:bit1;
  RESERVED5                     :bit4;
 end;

 TDH_TEST=bitpacked record
  DH_TEST  :bit1;
  RESERVED0:bit31;
 end;

 THDMI_GC=bitpacked record
  HDMI_GC_AVMUTE             :bit1;
  RESERVED0                  :bit1;
  HDMI_GC_AVMUTE_CONT        :bit1;
  RESERVED1                  :bit1;
  HDMI_DEFAULT_PHASE         :bit1;
  RESERVED2                  :bit3;
  HDMI_PACKING_PHASE         :bit4;
  HDMI_PACKING_PHASE_OVERRIDE:bit1;
  RESERVED3                  :bit19;
 end;

 TIH_CNTL=bitpacked record
  ENABLE_INTR          :bit1;
  MC_SWAP              :bit2;
  MC_TRAN              :bit1;
  RPTR_REARM           :bit1;
  RESERVED0            :bit3;
  CLIENT_FIFO_HIGHWATER:bit2;
  MC_FIFO_HIGHWATER    :bit5;
  MC_WRREQ_CREDIT      :bit5;
  MC_WR_CLEAN_CNT      :bit5;
  MC_VMID              :bit4;
  RESERVED1            :bit3;
 end;

 TIT_STAT=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit1;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit1;
  RESERVED13:bit1;
  RESERVED14:bit1;
  RESERVED15:bit1;
  RESERVED16:bit16;
 end;

 TKEFUSE0=bit32;

 TKEFUSE1=bit32;

 TKEFUSE2=bit32;

 TKEFUSE3=bit32;

 TLATENCY=bitpacked record
  LATENCY_TIMER:bit8;
  RESERVED0    :bit24;
 end;

 TMM_DATA=bit32;

 TMP_STAT=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit1;
  RESERVED4:bit4;
  RESERVED5:bit8;
  RESERVED6:bit8;
  RESERVED7:bit8;
 end;

 TOVL_END=bitpacked record
  OVL_Y_END:bit15;
  RESERVED0:bit1;
  OVL_X_END:bit15;
  RESERVED1:bit1;
 end;

 TPMI_CAP=bitpacked record
  VERSION          :bit3;
  PME_CLOCK        :bit1;
  RESERVED0        :bit1;
  DEV_SPECIFIC_INIT:bit1;
  AUX_CURRENT      :bit3;
  D1_SUPPORT       :bit1;
  D2_SUPPORT       :bit1;
  PME_SUPPORT      :bit5;
  RESERVED1        :bit16;
 end;

 TRE_STAT=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit1;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit1;
  RESERVED13:bit19;
 end;

 TSQ_DS_0=bitpacked record
  OFFSET0  :bit8;
  OFFSET1  :bit8;
  GDS      :bit1;
  OP       :bit8;
  RESERVED0:bit1;
  ENCODING :bit6;
 end;

 TSQ_DS_1=bitpacked record
  ADDR :bit8;
  DATA0:bit8;
  DATA1:bit8;
  VDST :bit8;
 end;

 TSQ_INST=bit32;

 TSQ_SOP1=bitpacked record
  SSRC0   :bit8;
  OP      :bit8;
  SDST    :bit7;
  ENCODING:bit9;
 end;

 TSQ_SOP2=bitpacked record
  SSRC0   :bit8;
  SSRC1   :bit8;
  SDST    :bit7;
  OP      :bit7;
  ENCODING:bit2;
 end;

 TSQ_SOPC=bitpacked record
  SSRC0   :bit8;
  SSRC1   :bit8;
  OP      :bit7;
  ENCODING:bit9;
 end;

 TSQ_SOPK=bitpacked record
  SIMM16  :bit16;
  SDST    :bit7;
  OP      :bit5;
  ENCODING:bit4;
 end;

 TSQ_SOPP=bitpacked record
  SIMM16  :bit16;
  OP      :bit7;
  ENCODING:bit9;
 end;

 TSQ_VOP1=bitpacked record
  SRC0    :bit9;
  OP      :bit8;
  VDST    :bit8;
  ENCODING:bit7;
 end;

 TSQ_VOP2=bitpacked record
  SRC0    :bit9;
  VSRC1   :bit8;
  VDST    :bit8;
  OP      :bit6;
  ENCODING:bit1;
 end;

 TSQ_VOPC=bitpacked record
  SRC0    :bit9;
  VSRC1   :bit8;
  OP      :bit8;
  ENCODING:bit7;
 end;

 TTA_CNTL=bitpacked record
  FX_XNACK_CREDIT:bit7;
  RESERVED0      :bit2;
  SQ_XNACK_CREDIT:bit4;
  TC_DATA_CREDIT :bit3;
  ALIGNER_CREDIT :bit5;
  RESERVED1      :bit1;
  TD_FIFO_CREDIT :bit10;
 end;

 TTD_CNTL=bitpacked record
  SYNC_PHASE_SH             :bit2;
  RESERVED0                 :bit2;
  SYNC_PHASE_VC_SMX         :bit2;
  RESERVED1                 :bit2;
  PAD_STALL_EN              :bit1;
  EXTEND_LDS_STALL          :bit2;
  LDS_STALL_PHASE_ADJUST    :bit2;
  RESERVED2                 :bit2;
  PRECISION_COMPATIBILITY   :bit1;
  GATHER4_FLOAT_MODE        :bit1;
  RESERVED3                 :bit1;
  LD_FLOAT_MODE             :bit1;
  GATHER4_DX9_MODE          :bit1;
  DISABLE_POWER_THROTTLE    :bit1;
  ENABLE_ROUND_TO_ZERO      :bit1;
  DISABLE_D16_PACKING       :bit1;
  DISABLE_2BIT_SIGNED_FORMAT:bit1;
  RESERVED4                 :bit8;
 end;

 TVGA_HDP=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit5;
  RESERVED2:bit1;
  RESERVED3:bit6;
  RESERVED4:bit1;
  RESERVED5:bit15;
  RESERVED6:bit1;
  RESERVED7:bit1;
  RESERVED8:bit1;
 end;

 TVGA_REG=bitpacked record
  RESERVED0:bit4;
  RESERVED1:bit4;
  RESERVED2:bit4;
  RESERVED3:bit1;
  RESERVED4:bit1;
  RESERVED5:bit8;
  RESERVED6:bit4;
  RESERVED7:bit1;
  RESERVED8:bit1;
  RESERVED9:bit4;
 end;

 TBUS_CNTL=bitpacked record
  BIOS_ROM_WRT_EN          :bit1;
  BIOS_ROM_DIS             :bit1;
  PMI_IO_DIS               :bit1;
  PMI_MEM_DIS              :bit1;
  PMI_BM_DIS               :bit1;
  PMI_INT_DIS              :bit1;
  VGA_REG_COHERENCY_DIS    :bit1;
  VGA_MEM_COHERENCY_DIS    :bit1;
  BIF_ERR_RTR_BKPRESSURE_EN:bit1;
  RESERVED0                :bit1;
  SET_AZ_TC                :bit3;
  SET_MC_TC                :bit3;
  ZERO_BE_WR_EN            :bit1;
  ZERO_BE_RD_EN            :bit1;
  RD_STALL_IO_WR           :bit1;
  RESERVED1                :bit13;
 end;

 TCNV_MODE=bitpacked record
  RESERVED0                 :bit8;
  CNV_FRAME_CAPTURE_RATE    :bit2;
  RESERVED1                 :bit2;
  CNV_WINDOW_CROP_EN        :bit1;
  CNV_STEREO_TYPE           :bit2;
  CNV_INTERLACED_MODE       :bit1;
  CNV_EYE_SELECTION         :bit2;
  CNV_STEREO_POLARITY       :bit1;
  CNV_INTERLACED_FIELD_ORDER:bit1;
  CNV_STEREO_SPLIT          :bit1;
  RESERVED2                 :bit3;
  CNV_NEW_CONTENT           :bit1;
  RESERVED3                 :bit6;
  CNV_FRAME_CAPTURE_EN      :bit1;
 end;

 TCP_DEBUG=bitpacked record
  RESERVED0 :bit6;
  RESERVED1 :bit1;
  RESERVED2 :bit8;
  RESERVED3 :bit1;
  RESERVED4 :bit3;
  RESERVED5 :bit2;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit1;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit2;
  RESERVED13:bit1;
  RESERVED14:bit1;
  RESERVED15:bit1;
 end;

 TCUR_SIZE=bitpacked record
  CURSOR_HEIGHT:bit7;
  RESERVED0    :bit9;
  CURSOR_WIDTH :bit7;
  RESERVED1    :bit9;
 end;

 TDAC_DATA=bitpacked record
  DAC_DATA :bit6;
  RESERVED0:bit26;
 end;

 TDAC_MASK=bitpacked record
  DAC_MASK :bit8;
  RESERVED0:bit24;
 end;

 TDB_DEBUG=bitpacked record
  DEBUG_STENCIL_COMPRESS_DISABLE       :bit1;
  DEBUG_DEPTH_COMPRESS_DISABLE         :bit1;
  FETCH_FULL_Z_TILE                    :bit1;
  FETCH_FULL_STENCIL_TILE              :bit1;
  FORCE_Z_MODE                         :bit2;
  DEBUG_FORCE_DEPTH_READ               :bit1;
  DEBUG_FORCE_STENCIL_READ             :bit1;
  DEBUG_FORCE_HIZ_ENABLE               :bit2;
  DEBUG_FORCE_HIS_ENABLE0              :bit2;
  DEBUG_FORCE_HIS_ENABLE1              :bit2;
  DEBUG_FAST_Z_DISABLE                 :bit1;
  DEBUG_FAST_STENCIL_DISABLE           :bit1;
  DEBUG_NOOP_CULL_DISABLE              :bit1;
  DISABLE_SUMM_SQUADS                  :bit1;
  DEPTH_CACHE_FORCE_MISS               :bit1;
  DEBUG_FORCE_FULL_Z_RANGE             :bit2;
  NEVER_FREE_Z_ONLY                    :bit1;
  ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS:bit1;
  DISABLE_VPORT_ZPLANE_OPTIMIZATION    :bit1;
  DECOMPRESS_AFTER_N_ZPLANES           :bit4;
  ONE_FREE_IN_FLIGHT                   :bit1;
  FORCE_MISS_IF_NOT_INFLIGHT           :bit1;
  DISABLE_DEPTH_SURFACE_SYNC           :bit1;
  DISABLE_HTILE_SURFACE_SYNC           :bit1;
 end;

 TDP_VID_M=bitpacked record
  DP_VID_M :bit24;
  RESERVED0:bit8;
 end;

 TDP_VID_N=bitpacked record
  DP_VID_N :bit24;
  RESERVED0:bit8;
 end;

 TFBC_CNTL=bitpacked record
  FBC_GRPH_COMP_EN    :bit1;
  FBC_SRC_SEL         :bit3;
  RESERVED0           :bit12;
  FBC_COHERENCY_MODE  :bit2;
  RESERVED1           :bit7;
  FBC_SOFT_COMPRESS_EN:bit1;
  RESERVED2           :bit5;
  FBC_EN              :bit1;
 end;

 TFBC_MISC=bitpacked record
  FBC_DECOMPRESS_ERROR           :bit2;
  FBC_STOP_ON_ERROR              :bit1;
  FBC_INVALIDATE_ON_ERROR        :bit1;
  FBC_ERROR_PIXEL                :bit4;
  FBC_DIVIDE_X                   :bit2;
  FBC_DIVIDE_Y                   :bit1;
  FBC_RSM_WRITE_VALUE            :bit1;
  FBC_RSM_UNCOMP_DATA_IMMEDIATELY:bit1;
  RESERVED0                      :bit3;
  FBC_DECOMPRESS_ERROR_CLEAR     :bit1;
  RESERVED1                      :bit3;
  FBC_RESET_AT_ENABLE            :bit1;
  FBC_RESET_AT_DISABLE           :bit1;
  RESERVED2                      :bit2;
  FBC_SLOW_REQ_INTERVAL          :bit5;
  RESERVED3                      :bit3;
 end;

 TGENFC_RD=bitpacked record
  RESERVED0  :bit3;
  VSYNC_SEL_R:bit1;
  RESERVED1  :bit28;
 end;

 TGENFC_WT=bitpacked record
  RESERVED0  :bit3;
  VSYNC_SEL_W:bit1;
  RESERVED1  :bit28;
 end;

 TGENMO_RD=bitpacked record
  GENMO_MONO_ADDRESS_B:bit1;
  VGA_RAM_EN          :bit1;
  VGA_CKSEL           :bit2;
  RESERVED0           :bit1;
  ODD_EVEN_MD_PGSEL   :bit1;
  VGA_HSYNC_POL       :bit1;
  VGA_VSYNC_POL       :bit1;
  RESERVED1           :bit24;
 end;

 TGENMO_WT=bitpacked record
  GENMO_MONO_ADDRESS_B:bit1;
  VGA_RAM_EN          :bit1;
  VGA_CKSEL           :bit2;
  RESERVED0           :bit1;
  ODD_EVEN_MD_PGSEL   :bit1;
  VGA_HSYNC_POL       :bit1;
  VGA_VSYNC_POL       :bit1;
  RESERVED1           :bit24;
 end;

 THW_DEBUG=bitpacked record
  HW_00_DEBUG:bit1;
  HW_01_DEBUG:bit1;
  HW_02_DEBUG:bit1;
  HW_03_DEBUG:bit1;
  HW_04_DEBUG:bit1;
  HW_05_DEBUG:bit1;
  HW_06_DEBUG:bit1;
  HW_07_DEBUG:bit1;
  HW_08_DEBUG:bit1;
  HW_09_DEBUG:bit1;
  HW_10_DEBUG:bit1;
  HW_11_DEBUG:bit1;
  HW_12_DEBUG:bit1;
  HW_13_DEBUG:bit1;
  HW_14_DEBUG:bit1;
  HW_15_DEBUG:bit1;
  HW_16_DEBUG:bit1;
  HW_17_DEBUG:bit1;
  HW_18_DEBUG:bit1;
  HW_19_DEBUG:bit1;
  HW_20_DEBUG:bit1;
  HW_21_DEBUG:bit1;
  HW_22_DEBUG:bit1;
  HW_23_DEBUG:bit1;
  HW_24_DEBUG:bit1;
  HW_25_DEBUG:bit1;
  HW_26_DEBUG:bit1;
  HW_27_DEBUG:bit1;
  HW_28_DEBUG:bit1;
  HW_29_DEBUG:bit1;
  HW_30_DEBUG:bit1;
  HW_31_DEBUG:bit1;
 end;

 TI2C_DATA=bitpacked record
  RESERVED0:bit8;
  RESERVED1:bit24;
 end;

 TIH_DEBUG=bitpacked record
  RB_FULL_DRAIN_ENABLE   :bit1;
  WPTR_OVERFLOW_ENABLE   :bit1;
  MC_WR_FIFO_BLOCK_ENABLE:bit1;
  RESERVED0              :bit29;
 end;

 TINT_MASK=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit3;
  RESERVED2:bit1;
  RESERVED3:bit25;
  RESERVED4:bit1;
  RESERVED5:bit1;
 end;

 TLB_DEBUG=bit32;

 TLINK_CAP=bitpacked record
  LINK_SPEED                 :bit4;
  LINK_WIDTH                 :bit6;
  PM_SUPPORT                 :bit2;
  L0S_EXIT_LATENCY           :bit3;
  L1_EXIT_LATENCY            :bit3;
  CLOCK_POWER_MANAGEMENT     :bit1;
  SURPRISE_DOWN_ERR_REPORTING:bit1;
  DL_ACTIVE_REPORTING_CAPABLE:bit1;
  LINK_BW_NOTIFICATION_CAP   :bit1;
  ASPM_OPTIONALITY_COMPLIANCE:bit1;
  RESERVED0                  :bit1;
  PORT_NUMBER                :bit8;
 end;

 TMC_RD_CB=bitpacked record
  ENABLE            :bit1;
  PRESCALE          :bit2;
  BLACKOUT_EXEMPT   :bit1;
  STALL_MODE        :bit2;
  STALL_OVERRIDE    :bit1;
  MAX_BURST         :bit4;
  LAZY_TIMER        :bit4;
  STALL_OVERRIDE_WTM:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit15;
 end;

 TMC_RD_DB=bitpacked record
  ENABLE            :bit1;
  PRESCALE          :bit2;
  BLACKOUT_EXEMPT   :bit1;
  STALL_MODE        :bit2;
  STALL_OVERRIDE    :bit1;
  MAX_BURST         :bit4;
  LAZY_TIMER        :bit4;
  STALL_OVERRIDE_WTM:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit15;
 end;

 TMC_WR_CB=bitpacked record
  ENABLE            :bit1;
  PRESCALE          :bit2;
  BLACKOUT_EXEMPT   :bit1;
  STALL_MODE        :bit2;
  STALL_OVERRIDE    :bit1;
  MAX_BURST         :bit4;
  LAZY_TIMER        :bit4;
  STALL_OVERRIDE_WTM:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit15;
 end;

 TMC_WR_DB=bitpacked record
  ENABLE            :bit1;
  PRESCALE          :bit2;
  BLACKOUT_EXEMPT   :bit1;
  STALL_MODE        :bit2;
  STALL_OVERRIDE    :bit1;
  MAX_BURST         :bit4;
  LAZY_TIMER        :bit4;
  STALL_OVERRIDE_WTM:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit15;
 end;

 TMM_INDEX=bitpacked record
  MM_OFFSET:bit31;
  MM_APER  :bit1;
 end;

 TMSI_MASK=bit32;

 TPCIE_CAP=bitpacked record
  VERSION         :bit4;
  DEVICE_TYPE     :bit4;
  SLOT_IMPLEMENTED:bit1;
  INT_MESSAGE_NUM :bit5;
  RESERVED0       :bit1;
  RESERVED1       :bit17;
 end;

 TPLL_CNTL=bitpacked record
  PLL_RESET             :bit1;
  PLL_POWER_DOWN        :bit1;
  PLL_BYPASS_CAL        :bit1;
  PLL_POST_DIV_SRC      :bit1;
  PLL_VCOREF            :bit2;
  PLL_PCIE_REFCLK_SEL   :bit1;
  PLL_ANTIGLITCH_RESETB :bit1;
  PLL_CALREF            :bit2;
  PLL_CAL_BYPASS_REFDIV :bit1;
  PLL_REFCLK_SEL        :bit2;
  PLL_ANTI_GLITCH_RESET :bit1;
  PLL_XOCLK_DRV_R_EN    :bit1;
  RESERVED0             :bit1;
  PLL_REF_DIV_SRC       :bit3;
  PLL_LOCK_FREQ_SEL     :bit1;
  PLL_CALIB_DONE        :bit1;
  PLL_LOCKED            :bit1;
  PLL_REFCLK_RECV_EN    :bit1;
  PLL_REFCLK_RECV_SEL   :bit1;
  PLL_TIMING_MODE_STATUS:bit2;
  PLL_DIG_SPARE         :bit6;
 end;

 TRLC_CNTL=bitpacked record
  RLC_ENABLE_F32       :bit1;
  FORCE_RETRY          :bit1;
  READ_CACHE_DISABLE   :bit1;
  RLC_STEP_F32         :bit1;
  SOFT_RESET_DEBUG_MODE:bit1;
  RESERVED0            :bit3;
  RESERVED             :bit24;
 end;

 TRLC_STAT=bitpacked record
  RLC_BUSY    :bit1;
  RLC_GPM_BUSY:bit1;
  RLC_SPM_BUSY:bit1;
  RLC_SRM_BUSY:bit1;
  RESERVED    :bit28;
 end;

 TRLC_VMID=bitpacked record
  RESERVED0:bit4;
  RESERVED1:bit28;
 end;

 TROM_CNTL=bitpacked record
  RESERVED0                   :bit1;
  SCK_OVERWRITE               :bit1;
  CLOCK_GATING_EN             :bit1;
  RESERVED1                   :bit5;
  CSB_ACTIVE_TO_SCK_SETUP_TIME:bit8;
  CSB_ACTIVE_TO_SCK_HOLD_TIME :bit8;
  SCK_PRESCALE_REFCLK         :bit4;
  SCK_PRESCALE_CRYSTAL_CLK    :bit4;
 end;

 TROM_DATA=bit32;

 TSCL_MODE=bitpacked record
  SCL_MODE   :bit2;
  RESERVED0  :bit2;
  SCL_PSCL_EN:bit1;
  RESERVED1  :bit27;
 end;

 TSDMA0_ID=bitpacked record
  DEVICE_ID:bit8;
  RESERVED0:bit24;
 end;

 TSDMA1_ID=bitpacked record
  DEVICE_ID:bit8;
  RESERVED0:bit24;
 end;

 TSEQ8_IDX=bitpacked record
  SEQ_IDX  :bit3;
  RESERVED0:bit29;
 end;

 TSMC_PC_C=bit32;

 TSQ_EXP_0=bitpacked record
  EN       :bit4;
  TGT      :bit6;
  COMPR    :bit1;
  DONE     :bit1;
  VM       :bit1;
  RESERVED0:bit13;
  ENCODING :bit6;
 end;

 TSQ_EXP_1=bitpacked record
  VSRC0:bit8;
  VSRC1:bit8;
  VSRC2:bit8;
  VSRC3:bit8;
 end;

 TTCA_CTRL=bitpacked record
  HOLE_TIMEOUT:bit4;
  RESERVED0   :bit28;
 end;

 TTCC_CTRL=bitpacked record
  CACHE_SIZE                :bit2;
  RATE                      :bit2;
  WRITEBACK_MARGIN          :bit4;
  METADATA_LATENCY_FIFO_SIZE:bit4;
  SRC_FIFO_SIZE             :bit4;
  LATENCY_FIFO_SIZE         :bit4;
  WB_OR_INV_ALL_VMIDS       :bit1;
  RESERVED0                 :bit3;
  MDC_SIZE                  :bit2;
  MDC_SECTOR_SIZE           :bit2;
  MDC_SIDEBAND_FIFO_SIZE    :bit4;
 end;

 TTCP_CNTL=bitpacked record
  FORCE_HIT             :bit1;
  FORCE_MISS            :bit1;
  L1_SIZE               :bit2;
  FLAT_BUF_HASH_ENABLE  :bit1;
  FLAT_BUF_CACHE_SWIZZLE:bit1;
  RESERVED0             :bit9;
  FORCE_EOW_TOTAL_CNT   :bit6;
  RESERVED1             :bit1;
  FORCE_EOW_TAGRAM_CNT  :bit6;
  DISABLE_Z_MAP         :bit1;
  INV_ALL_VMIDS         :bit1;
  RESERVED2             :bit2;
 end;

 TVGA_CRTC=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit5;
  RESERVED3:bit4;
  RESERVED4:bit11;
  RESERVED5:bit8;
  RESERVED6:bit2;
 end;

 TVGA_MAIN=bitpacked record
  RESERVED0 :bit4;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit2;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit1;
  RESERVED13:bit1;
  RESERVED14:bit1;
  RESERVED15:bit2;
  RESERVED16:bit1;
  RESERVED17:bit1;
  RESERVED18:bit1;
  RESERVED19:bit1;
  RESERVED20:bit1;
  RESERVED21:bit1;
  RESERVED22:bit1;
  RESERVED23:bit1;
  RESERVED24:bit1;
  RESERVED25:bit1;
  RESERVED26:bit1;
 end;

 TVGA_TEXT=bitpacked record
  RESERVED0 :bit4;
  RESERVED1 :bit4;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit2;
  RESERVED8 :bit3;
  RESERVED9 :bit3;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit1;
  RESERVED13:bit1;
  RESERVED14:bit1;
  RESERVED15:bit1;
  RESERVED16:bit1;
  RESERVED17:bit1;
  RESERVED18:bit1;
  RESERVED19:bit1;
  RESERVED20:bit1;
 end;

 TVM_DEBUG=bit32;

 TVM_L2_CG=bitpacked record
  RESERVED0    :bit6;
  OFFDLY       :bit6;
  RESERVED1    :bit6;
  ENABLE       :bit1;
  MEM_LS_ENABLE:bit1;
  _OVERRIDE    :bit1;
  RESERVED2    :bit11;
 end;

 TBACO_CNTL=bitpacked record
  BACO_EN                  :bit1;
  BACO_BCLK_OFF            :bit1;
  BACO_ISO_DIS             :bit1;
  BACO_POWER_OFF           :bit1;
  BACO_RESET_EN            :bit1;
  BACO_HANG_PROTECTION_EN  :bit1;
  BACO_MODE                :bit1;
  BACO_ANA_ISO_DIS         :bit1;
  RCU_BIF_CONFIG_DONE      :bit1;
  PWRGOOD_BF               :bit1;
  PWRGOOD_GPIO             :bit1;
  PWRGOOD_MEM              :bit1;
  PWRGOOD_DVO              :bit1;
  PWRGOOD_IDSC             :bit1;
  RESERVED0                :bit2;
  BACO_POWER_OFF_DRAM      :bit1;
  BACO_BF_MEM_PHY_ISO_CNTRL:bit1;
  BACO_BIF_SCLK_SWITCH     :bit1;
  RESERVED1                :bit13;
 end;

 TBIF_FB_EN=bitpacked record
  FB_READ_EN :bit1;
  FB_WRITE_EN:bit1;
  RESERVED0  :bit30;
 end;

 TCORB_SIZE=bitpacked record
  CORB_SIZE           :bit2;
  RESERVED0           :bit2;
  CORB_SIZE_CAPABILITY:bit4;
  RESERVED1           :bit24;
 end;

 TCP_CONFIG=bitpacked record
  RESERVED0   :bit8;
  CP_RDREQ_URG:bit4;
  RESERVED1   :bit4;
  CP_REQ_TRAN :bit1;
  RESERVED2   :bit15;
 end;

 TCP_PIPEID=bitpacked record
  PIPE_ID  :bit2;
  RESERVED0:bit30;
 end;

 TCP_RINGID=bitpacked record
  RINGID   :bit2;
  RESERVED0:bit30;
 end;

 TCRTC8_IDX=bitpacked record
  VCRTC_IDX:bit6;
  RESERVED0:bit26;
 end;

 TCUR2_SIZE=bitpacked record
  CURSOR2_HEIGHT:bit7;
  RESERVED0     :bit9;
  CURSOR2_WIDTH :bit7;
  RESERVED1     :bit9;
 end;

 TDB_DEBUG2=bitpacked record
  ALLOW_COMPZ_BYTE_MASKING            :bit1;
  DISABLE_TC_ZRANGE_L0_CACHE          :bit1;
  DISABLE_TC_MASK_L0_CACHE            :bit1;
  DTR_ROUND_ROBIN_ARB                 :bit1;
  DTR_PREZ_STALLS_FOR_ETF_ROOM        :bit1;
  DISABLE_PREZL_LPF_STALL             :bit1;
  ENABLE_PREZL_CB_STALL               :bit1;
  DISABLE_PREZL_LPF_STALL_REZ         :bit1;
  DISABLE_PREZL_CB_STALL_REZ          :bit1;
  CLK_OFF_DELAY                       :bit5;
  DISABLE_TILE_COVERED_FOR_PS_ITER    :bit1;
  ENABLE_SUBTILE_GROUPING             :bit1;
  DISABLE_HTILE_PAIRED_PIPES          :bit1;
  DISABLE_NULL_EOT_FORWARDING         :bit1;
  DISABLE_DTT_DATA_FORWARDING         :bit1;
  DISABLE_QUAD_COHERENCY_STALL        :bit1;
  RESERVED0                           :bit8;
  ENABLE_PREZ_OF_REZ_SUMM             :bit1;
  DISABLE_PREZL_VIEWPORT_STALL        :bit1;
  DISABLE_SINGLE_STENCIL_QUAD_SUMM    :bit1;
  DISABLE_WRITE_STALL_ON_RDWR_CONFLICT:bit1;
 end;

 TDB_DEBUG3=bitpacked record
  RESERVED0                               :bit2;
  FORCE_DB_IS_GOOD                        :bit1;
  DISABLE_TL_SSO_NULL_SUPPRESSION         :bit1;
  DISABLE_HIZ_ON_VPORT_CLAMP              :bit1;
  EQAA_INTERPOLATE_COMP_Z                 :bit1;
  EQAA_INTERPOLATE_SRC_Z                  :bit1;
  DISABLE_TCP_CAM_BYPASS                  :bit1;
  DISABLE_ZCMP_DIRTY_SUPPRESSION          :bit1;
  DISABLE_REDUNDANT_PLANE_FLUSHES_OPT     :bit1;
  DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP:bit1;
  ENABLE_INCOHERENT_EQAA_READS            :bit1;
  DISABLE_OP_Z_DATA_FORWARDING            :bit1;
  DISABLE_OP_DF_BYPASS                    :bit1;
  DISABLE_OP_DF_WRITE_COMBINE             :bit1;
  DISABLE_OP_DF_DIRECT_FEEDBACK           :bit1;
  ALLOW_RF2P_RW_COLLISION                 :bit1;
  SLOW_PREZ_TO_A2M_OMASK_RATE             :bit1;
  DISABLE_OP_S_DATA_FORWARDING            :bit1;
  DISABLE_TC_UPDATE_WRITE_COMBINE         :bit1;
  DISABLE_HZ_TC_WRITE_COMBINE             :bit1;
  ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT    :bit1;
  ENABLE_TC_MA_ROUND_ROBIN_ARB            :bit1;
  DISABLE_RAM_READ_SUPPRESION_ON_FWD      :bit1;
  DISABLE_EQAA_A2M_PERF_OPT               :bit1;
  DISABLE_DI_DT_STALL                     :bit1;
  ENABLE_DB_PROCESS_RESET                 :bit1;
  DISABLE_OVERRASTERIZATION_FIX           :bit1;
  DONT_INSERT_CONTEXT_SUSPEND             :bit1;
  DONT_DELETE_CONTEXT_SUSPEND             :bit1;
  DISABLE_4XAA_2P_DELAYED_WRITE           :bit1;
  DISABLE_4XAA_2P_INTERLEAVED_PMASK       :bit1;
 end;

 TDB_DEBUG4=bitpacked record
  DISABLE_QC_Z_MASK_SUMMATION            :bit1;
  DISABLE_QC_STENCIL_MASK_SUMMATION      :bit1;
  DISABLE_RESUMM_TO_SINGLE_STENCIL       :bit1;
  DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL:bit1;
  DISABLE_4XAA_2P_ZD_HOLDOFF             :bit1;
  ENABLE_A2M_DQUAD_OPTIMIZATION          :bit1;
  DB_EXTRA_DEBUG4                        :bit26;
 end;

 TDB_Z_INFO=bitpacked record
  FORMAT                 :bit2;
  NUM_SAMPLES            :bit2;
  RESERVED0              :bit9;
  TILE_SPLIT             :bit3;
  RESERVED1              :bit4;
  TILE_MODE_INDEX        :bit3;
  DECOMPRESS_ON_N_ZPLANES:bit4;
  ALLOW_EXPCLEAR         :bit1;
  READ_SIZE              :bit1;
  TILE_SURFACE_ENABLE    :bit1;
  CLEAR_DISALLOWED       :bit1;
  ZRANGE_PRECISION       :bit1;
 end;

 TDCP_DEBUG=bit32;

 TDEVICE_ID=bitpacked record
  DEVICE_ID:bit16;
  RESERVED0:bit16;
 end;

 TDMCU_CTRL=bitpacked record
  RESET_UC          :bit1;
  IGNORE_PWRMGT     :bit1;
  DISABLE_IRQ_TO_UC :bit1;
  DISABLE_XIRQ_TO_UC:bit1;
  DMCU_ENABLE       :bit1;
  RESERVED0         :bit11;
  UC_REG_RD_TIMEOUT :bit16;
 end;

 TDP_CONFIG=bitpacked record
  DP_UDI_LANES:bit2;
  RESERVED0   :bit30;
 end;

 TGB_GPU_ID=bitpacked record
  GPU_ID   :bit4;
  RESERVED0:bit28;
 end;

 TGPIOPAD_A=bitpacked record
  GPIO_A   :bit31;
  RESERVED0:bit1;
 end;

 TGPIOPAD_Y=bitpacked record
  GPIO_Y   :bit31;
  RESERVED0:bit1;
 end;

 TGRBM_CNTL=bitpacked record
  READ_TIMEOUT     :bit8;
  RESERVED0        :bit23;
  REPORT_LAST_RDERR:bit1;
 end;

 TGRPH8_IDX=bitpacked record
  GRPH_IDX :bit4;
  RESERVED0:bit28;
 end;

 THFS_SEED0=bit32;

 THFS_SEED1=bit32;

 THFS_SEED2=bit32;

 THFS_SEED3=bit32;

 TIH_STATUS=bitpacked record
  IDLE               :bit1;
  INPUT_IDLE         :bit1;
  RB_IDLE            :bit1;
  RB_FULL            :bit1;
  RB_FULL_DRAIN      :bit1;
  RB_OVERFLOW        :bit1;
  MC_WR_IDLE         :bit1;
  MC_WR_STALL        :bit1;
  MC_WR_CLEAN_PENDING:bit1;
  MC_WR_CLEAN_STALL  :bit1;
  BIF_INTERRUPT_LINE :bit1;
  SWITCH_READY       :bit1;
  RESERVED0          :bit20;
 end;

 TIT_INT_EN=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit1;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit1;
  RESERVED13:bit1;
  RESERVED14:bit1;
  RESERVED15:bit1;
  RESERVED16:bit1;
  RESERVED17:bit1;
  RESERVED18:bit1;
  RESERVED19:bit1;
  RESERVED20:bit1;
  RESERVED21:bit1;
  RESERVED22:bit1;
  RESERVED23:bit9;
 end;

 TKSESSION0=bit32;

 TKSESSION1=bit32;

 TKSESSION2=bit32;

 TKSESSION3=bit32;

 TLBV_DEBUG=bit32;

 TLB_DEBUG2=bit32;

 TLB_DEBUG3=bit32;

 TLINK_CAP2=bitpacked record
  RESERVED0           :bit1;
  SUPPORTED_LINK_SPEED:bit7;
  CROSSLINK_SUPPORTED :bit1;
  RESERVED1           :bit23;
 end;

 TLINK_CNTL=bitpacked record
  PM_CONTROL                 :bit2;
  RESERVED0                  :bit1;
  READ_CPL_BOUNDARY          :bit1;
  LINK_DIS                   :bit1;
  RETRAIN_LINK               :bit1;
  COMMON_CLOCK_CFG           :bit1;
  EXTENDED_SYNC              :bit1;
  CLOCK_POWER_MANAGEMENT_EN  :bit1;
  HW_AUTONOMOUS_WIDTH_DISABLE:bit1;
  LINK_BW_MANAGEMENT_INT_EN  :bit1;
  LINK_AUTONOMOUS_BW_INT_EN  :bit1;
  RESERVED1                  :bit20;
 end;

 TMCIF_VMID=bitpacked record
  MCIF_WR_VMID:bit4;
  VIP_WR_VMID :bit4;
  RESERVED0   :bit24;
 end;

 TMC_ARB_CG=bitpacked record
  CG_ARB_REQ :bit8;
  CG_ARB_RESP:bit8;
  RSV_0      :bit8;
  RSV_1      :bit8;
 end;

 TMC_CONFIG=bitpacked record
  MCDW_WR_ENABLE       :bit1;
  MCDX_WR_ENABLE       :bit1;
  MCDY_WR_ENABLE       :bit1;
  MCDZ_WR_ENABLE       :bit1;
  MCDS_WR_ENABLE       :bit1;
  MCDT_WR_ENABLE       :bit1;
  MCDU_WR_ENABLE       :bit1;
  MCDV_WR_ENABLE       :bit1;
  MC_RD_ENABLE         :bit3;
  RESERVED0            :bit20;
  MCC_INDEX_MODE_ENABLE:bit1;
 end;

 TMC_RD_HUB=bitpacked record
  ENABLE            :bit1;
  PRESCALE          :bit2;
  BLACKOUT_EXEMPT   :bit1;
  STALL_MODE        :bit2;
  STALL_OVERRIDE    :bit1;
  MAX_BURST         :bit4;
  LAZY_TIMER        :bit4;
  STALL_OVERRIDE_WTM:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit15;
 end;

 TMC_RD_TC0=bitpacked record
  ENABLE            :bit1;
  PRESCALE          :bit2;
  BLACKOUT_EXEMPT   :bit1;
  STALL_MODE        :bit2;
  STALL_OVERRIDE    :bit1;
  MAX_BURST         :bit4;
  LAZY_TIMER        :bit4;
  STALL_OVERRIDE_WTM:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit15;
 end;

 TMC_RD_TC1=bitpacked record
  ENABLE            :bit1;
  PRESCALE          :bit2;
  BLACKOUT_EXEMPT   :bit1;
  STALL_MODE        :bit2;
  STALL_OVERRIDE    :bit1;
  MAX_BURST         :bit4;
  LAZY_TIMER        :bit4;
  STALL_OVERRIDE_WTM:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit15;
 end;

 TMC_SEQ_CG=bitpacked record
  CG_SEQ_REQ :bit8;
  CG_SEQ_RESP:bit8;
  SEQ_CG_REQ :bit8;
  SEQ_CG_RESP:bit8;
 end;

 TMC_WR_HUB=bitpacked record
  ENABLE            :bit1;
  PRESCALE          :bit2;
  BLACKOUT_EXEMPT   :bit1;
  STALL_MODE        :bit2;
  STALL_OVERRIDE    :bit1;
  MAX_BURST         :bit4;
  LAZY_TIMER        :bit4;
  STALL_OVERRIDE_WTM:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit15;
 end;

 TMC_WR_TC0=bitpacked record
  ENABLE            :bit1;
  PRESCALE          :bit2;
  BLACKOUT_EXEMPT   :bit1;
  STALL_MODE        :bit2;
  STALL_OVERRIDE    :bit1;
  MAX_BURST         :bit4;
  LAZY_TIMER        :bit4;
  STALL_OVERRIDE_WTM:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit15;
 end;

 TMC_WR_TC1=bitpacked record
  ENABLE            :bit1;
  PRESCALE          :bit2;
  BLACKOUT_EXEMPT   :bit1;
  STALL_MODE        :bit2;
  STALL_OVERRIDE    :bit1;
  MAX_BURST         :bit4;
  LAZY_TIMER        :bit4;
  STALL_OVERRIDE_WTM:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit15;
 end;

 TMIN_GRANT=bitpacked record
  MIN_GNT  :bit8;
  RESERVED0:bit24;
 end;

 TMP_INT_EN=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit1;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit1;
  RESERVED13:bit1;
  RESERVED14:bit1;
  RESERVED15:bit1;
  RESERVED16:bit1;
  RESERVED17:bit1;
  RESERVED18:bit1;
  RESERVED19:bit1;
  RESERVED20:bit1;
  RESERVED21:bit1;
  RESERVED22:bit1;
  RESERVED23:bit1;
  RESERVED24:bit8;
 end;

 TMVP_DEBUG=bitpacked record
  MVP_SWAP_LOCK_IN_EN                :bit1;
  MVP_FLOW_CONTROL_IN_EN             :bit1;
  MVP_SWAP_LOCK_IN_SEL               :bit1;
  MVP_FLOW_CONTROL_IN_SEL            :bit1;
  MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP  :bit1;
  MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP    :bit1;
  MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR:bit1;
  MVP_DIS_READ_POINTER_RESET_DELAY   :bit1;
  MVP_DEBUG_BITS                     :bit24;
 end;

 TOVL_ALPHA=bitpacked record
  RESERVED0:bit8;
  RESERVED1:bit24;
 end;

 TOVL_PITCH=bitpacked record
  OVL_PITCH:bit15;
  RESERVED0:bit17;
 end;

 TOVL_START=bitpacked record
  OVL_Y_START:bit14;
  RESERVED0  :bit2;
  OVL_X_START:bit14;
  RESERVED1  :bit2;
 end;

 TPCIE_CNTL=bitpacked record
  HWINIT_WR_LOCK              :bit1;
  LC_HOT_PLUG_DELAY_SEL       :bit3;
  RESERVED0                   :bit3;
  UR_ERR_REPORT_DIS           :bit1;
  PCIE_MALFORM_ATOMIC_OPS     :bit1;
  PCIE_HT_NP_MEM_WRITE        :bit1;
  RX_SB_ADJ_PAYLOAD_SIZE      :bit3;
  RESERVED1                   :bit2;
  RX_RCB_ATS_UC_DIS           :bit1;
  RX_RCB_REORDER_EN           :bit1;
  RX_RCB_INVALID_SIZE_DIS     :bit1;
  RX_RCB_UNEXP_CPL_DIS        :bit1;
  RX_RCB_CPL_TIMEOUT_TEST_MODE:bit1;
  RX_RCB_WRONG_PREFIX_DIS     :bit1;
  RX_RCB_WRONG_ATTR_DIS       :bit1;
  RX_RCB_WRONG_FUNCNUM_DIS    :bit1;
  RX_ATS_TRAN_CPL_SPLIT_DIS   :bit1;
  TX_CPL_DEBUG                :bit6;
  RX_IGNORE_LTR_MSG_UR        :bit1;
  RX_CPL_POSTED_REQ_ORD_EN    :bit1;
 end;

 TPCIE_DATA=bit32;

 TPCIE_FC_P=bitpacked record
  PD_CREDITS:bit8;
  PH_CREDITS:bit8;
  RESERVED0 :bit16;
 end;

 TRIRB_SIZE=bitpacked record
  RIRB_SIZE           :bit2;
  RESERVED0           :bit2;
  RIRB_SIZE_CAPABILITY:bit4;
  RESERVED1           :bit24;
 end;

 TRLC_DEBUG=bit32;

 TROM_INDEX=bitpacked record
  ROM_INDEX:bit24;
  RESERVED0:bit8;
 end;

 TROM_START=bitpacked record
  ROM_START:bit24;
  RESERVED0:bit8;
 end;

 TSCLV_MODE=bitpacked record
  SCL_MODE            :bit1;
  RESERVED0           :bit3;
  SCL_PSCL_EN         :bit1;
  RESERVED1           :bit3;
  SCL_INTERLACE_SOURCE:bit2;
  RESERVED2           :bit22;
 end;

 TSCL_DEBUG=bit32;

 TSEQ8_DATA=bitpacked record
  SEQ_DATA :bit8;
  RESERVED0:bit24;
 end;

 TSQ_CONFIG=bitpacked record
  UNUSED                       :bit8;
  DEBUG_EN                     :bit1;
  DEBUG_SINGLE_MEMOP           :bit1;
  DEBUG_ONE_INST_CLAUSE        :bit1;
  RESERVED0                    :bit1;
  EARLY_TA_DONE_DISABLE        :bit1;
  DUA_FLAT_LOCK_ENABLE         :bit1;
  DUA_LDS_BYPASS_DISABLE       :bit1;
  DUA_FLAT_LDS_PINGPONG_DISABLE:bit1;
  DISABLE_VMEM_SOFT_CLAUSE     :bit1;
  DISABLE_SMEM_SOFT_CLAUSE     :bit1;
  ENABLE_HIPRIO_ON_EXP_RDY_VS  :bit1;
  PRIO_VAL_ON_EXP_RDY_VS       :bit2;
  REPLAY_SLEEP_CNT             :bit4;
  RESERVED1                    :bit7;
 end;

 TSQ_FLAT_0=bitpacked record
  RESERVED0:bit16;
  GLC      :bit1;
  SLC      :bit1;
  OP       :bit7;
  RESERVED1:bit1;
  ENCODING :bit6;
 end;

 TSQ_FLAT_1=bitpacked record
  ADDR     :bit8;
  DATA     :bit8;
  RESERVED0:bit7;
  TFE      :bit1;
  VDST     :bit8;
 end;

 TSQ_MIMG_0=bitpacked record
  RESERVED0:bit8;
  DMASK    :bit4;
  UNORM    :bit1;
  GLC      :bit1;
  DA       :bit1;
  R128     :bit1;
  TFE      :bit1;
  LWE      :bit1;
  OP       :bit7;
  SLC      :bit1;
  ENCODING :bit6;
 end;

 TSQ_MIMG_1=bitpacked record
  VADDR    :bit8;
  VDATA    :bit8;
  SRSRC    :bit5;
  SSAMP    :bit5;
  RESERVED0:bit5;
  D16      :bit1;
 end;

 TSQ_SMEM_0=bitpacked record
  SBASE    :bit6;
  SDATA    :bit7;
  RESERVED0:bit3;
  GLC      :bit1;
  IMM      :bit1;
  OP       :bit8;
  ENCODING :bit6;
 end;

 TSQ_SMEM_1=bitpacked record
  OFFSET   :bit20;
  RESERVED0:bit12;
 end;

 TSQ_VINTRP=bitpacked record
  VSRC    :bit8;
  ATTRCHAN:bit2;
  ATTR    :bit6;
  OP      :bit2;
  VDST    :bit8;
  ENCODING:bit6;
 end;

 TSQ_VOP3_0=bitpacked record
  VDST     :bit8;
  ABS      :bit3;
  RESERVED0:bit4;
  CLAMP    :bit1;
  OP       :bit10;
  ENCODING :bit6;
 end;

 TSQ_VOP3_1=bitpacked record
  SRC0:bit9;
  SRC1:bit9;
  SRC2:bit9;
  OMOD:bit2;
  NEG :bit3;
 end;

 TSRBM_CNTL=bitpacked record
  READ_TIMEOUT          :bit10;
  RESERVED0             :bit6;
  PWR_REQUEST_HALT      :bit1;
  COMBINE_SYSTEM_MC     :bit1;
  REPORT_LAST_RDERR     :bit1;
  PWR_GFX3D_REQUEST_HALT:bit1;
  RESERVED1             :bit12;
 end;

 TSUB_CLASS=bitpacked record
  SUB_CLASS:bit8;
  RESERVED0:bit24;
 end;

 TTA_STATUS=bitpacked record
  RESERVED0      :bit12;
  FG_PFIFO_EMPTYB:bit1;
  FG_LFIFO_EMPTYB:bit1;
  FG_SFIFO_EMPTYB:bit1;
  RESERVED1      :bit1;
  FL_PFIFO_EMPTYB:bit1;
  FL_LFIFO_EMPTYB:bit1;
  FL_SFIFO_EMPTYB:bit1;
  RESERVED2      :bit1;
  FA_PFIFO_EMPTYB:bit1;
  FA_LFIFO_EMPTYB:bit1;
  FA_SFIFO_EMPTYB:bit1;
  RESERVED3      :bit1;
  IN_BUSY        :bit1;
  FG_BUSY        :bit1;
  LA_BUSY        :bit1;
  FL_BUSY        :bit1;
  TA_BUSY        :bit1;
  FA_BUSY        :bit1;
  AL_BUSY        :bit1;
  BUSY           :bit1;
 end;

 TTCP_CNTL2=bitpacked record
  LS_DISABLE_CLOCKS:bit8;
  RESERVED0        :bit24;
 end;

 TTD_STATUS=bitpacked record
  RESERVED0:bit31;
  BUSY     :bit1;
 end;

 TTMDS_CNTL=bitpacked record
  TMDS_SYNC_PHASE    :bit1;
  RESERVED0          :bit3;
  TMDS_PIXEL_ENCODING:bit1;
  RESERVED1          :bit3;
  TMDS_COLOR_FORMAT  :bit2;
  RESERVED2          :bit22;
 end;

 TUNP_DEBUG=bit32;

 TVENDOR_ID=bitpacked record
  VENDOR_ID:bit16;
  RESERVED0:bit16;
 end;

 TV_COUNTER=bitpacked record
  RESERVED0:bit14;
  RESERVED1:bit18;
 end;

 TWB_ENABLE=bitpacked record
  WB_ENABLE:bit1;
  RESERVED0:bit31;
 end;

 TADAPTER_ID=bitpacked record
  SUBSYSTEM_VENDOR_ID:bit16;
  SUBSYSTEM_ID       :bit16;
 end;

 TBASE_CLASS=bitpacked record
  BASE_CLASS:bit8;
  RESERVED0 :bit24;
 end;

 TBLND_DEBUG=bitpacked record
  BLND_CNV_MUX_SELECT:bit1;
  BLND_DEBUG         :bit31;
 end;

 TCACHE_LINE=bitpacked record
  CACHE_LINE_SIZE:bit8;
  RESERVED0      :bit24;
 end;

 TCG_FPS_CNT=bit32;

 TCLIENT0_BM=bit32;

 TCLIENT0_K0=bit32;

 TCLIENT0_K1=bit32;

 TCLIENT0_K2=bit32;

 TCLIENT0_K3=bit32;

 TCLIENT1_BM=bit32;

 TCLIENT1_K0=bit32;

 TCLIENT1_K1=bit32;

 TCLIENT1_K2=bit32;

 TCLIENT1_K3=bit32;

 TCLIENT2_BM=bit32;

 TCLIENT2_K0=bit32;

 TCLIENT2_K1=bit32;

 TCLIENT2_K2=bit32;

 TCLIENT2_K3=bit32;

 TCLIENT3_BM=bit32;

 TCLIENT3_K0=bit32;

 TCLIENT3_K1=bit32;

 TCLIENT3_K2=bit32;

 TCLIENT3_K3=bit32;

 TCLIENT4_BM=bit32;

 TCLIENT4_K0=bit32;

 TCLIENT4_K1=bit32;

 TCLIENT4_K2=bit32;

 TCLIENT4_K3=bit32;

 TCNV_UPDATE=bitpacked record
  CNV_UPDATE_PENDING:bit1;
  RESERVED0         :bit7;
  CNV_UPDATE_TAKEN  :bit1;
  RESERVED1         :bit7;
  CNV_UPDATE_LOCK   :bit1;
  RESERVED2         :bit15;
 end;

 TCP_DFY_CMD=bitpacked record
  OFFSET   :bit9;
  RESERVED0:bit7;
  SIZE     :bit16;
 end;

 TCP_ME_CNTL=bitpacked record
  RESERVED0            :bit4;
  CE_INVALIDATE_ICACHE :bit1;
  RESERVED1            :bit1;
  PFP_INVALIDATE_ICACHE:bit1;
  RESERVED2            :bit1;
  ME_INVALIDATE_ICACHE :bit1;
  RESERVED3            :bit7;
  CE_PIPE0_RESET       :bit1;
  RESERVED4            :bit1;
  PFP_PIPE0_RESET      :bit1;
  RESERVED5            :bit1;
  ME_PIPE0_RESET       :bit1;
  RESERVED6            :bit3;
  CE_HALT              :bit1;
  CE_STEP              :bit1;
  PFP_HALT             :bit1;
  PFP_STEP             :bit1;
  ME_HALT              :bit1;
  ME_STEP              :bit1;
  RESERVED7            :bit2;
 end;

 TCP_RB_BASE=bit32;

 TCP_RB_CNTL=bitpacked record
  RB_BUFSZ      :bit6;
  RESERVED0     :bit2;
  RB_BLKSZ      :bit6;
  RESERVED1     :bit1;
  MTYPE         :bit2;
  BUF_SWAP      :bit2;
  RESERVED2     :bit1;
  MIN_AVAILSZ   :bit2;
  MIN_IB_AVAILSZ:bit2;
  CACHE_POLICY  :bit1;
  RESERVED3     :bit2;
  RB_NO_UPDATE  :bit1;
  RESERVED4     :bit3;
  RB_RPTR_WR_ENA:bit1;
 end;

 TCP_RB_RPTR=bitpacked record
  RB_RPTR  :bit20;
  RESERVED0:bit12;
 end;

 TCP_RB_VMID=bitpacked record
  RB0_VMID :bit4;
  RESERVED0:bit4;
  RB1_VMID :bit4;
  RESERVED1:bit4;
  RB2_VMID :bit4;
  RESERVED2:bit12;
 end;

 TCP_RB_WPTR=bitpacked record
  RB_WPTR  :bit20;
  RESERVED0:bit12;
 end;

 TCRTC8_DATA=bitpacked record
  VCRTC_DATA:bit8;
  RESERVED0 :bit24;
 end;

 TCUR_COLOR1=bitpacked record
  CUR_COLOR1_BLUE :bit8;
  CUR_COLOR1_GREEN:bit8;
  CUR_COLOR1_RED  :bit8;
  RESERVED0       :bit8;
 end;

 TCUR_COLOR2=bitpacked record
  CUR_COLOR2_BLUE :bit8;
  CUR_COLOR2_GREEN:bit8;
  CUR_COLOR2_RED  :bit8;
  RESERVED0       :bit8;
 end;

 TCUR_UPDATE=bitpacked record
  CURSOR_UPDATE_PENDING         :bit1;
  CURSOR_UPDATE_TAKEN           :bit1;
  RESERVED0                     :bit14;
  CURSOR_UPDATE_LOCK            :bit1;
  RESERVED1                     :bit7;
  CURSOR_DISABLE_MULTIPLE_UPDATE:bit1;
  CURSOR_UPDATE_STEREO_MODE     :bit2;
  RESERVED2                     :bit5;
 end;

 TDAC_CRC_EN=bitpacked record
  DAC_CRC_EN     :bit1;
  RESERVED0      :bit15;
  DAC_CRC_CONT_EN:bit1;
  RESERVED1      :bit15;
 end;

 TDAC_ENABLE=bitpacked record
  DAC_ENABLE                  :bit1;
  DAC_RESYNC_FIFO_ENABLE      :bit1;
  DAC_RESYNC_FIFO_POINTER_SKEW:bit2;
  DAC_RESYNC_FIFO_ERROR       :bit1;
  DAC_RESYNC_FIFO_ERROR_ACK   :bit1;
  RESERVED0                   :bit2;
  DAC_RESYNC_FIFO_TVOUT_SIM   :bit1;
  RESERVED1                   :bit23;
 end;

 TDCIO_DEBUG=bit32;

 TDCP_DEBUG2=bit32;

 TDEBUG_DATA=bit32;

 TDEVICE_CAP=bitpacked record
  MAX_PAYLOAD_SUPPORT      :bit3;
  PHANTOM_FUNC             :bit2;
  EXTENDED_TAG             :bit1;
  L0S_ACCEPTABLE_LATENCY   :bit3;
  L1_ACCEPTABLE_LATENCY    :bit3;
  RESERVED0                :bit3;
  ROLE_BASED_ERR_REPORTING :bit1;
  RESERVED1                :bit2;
  CAPTURED_SLOT_POWER_LIMIT:bit8;
  CAPTURED_SLOT_POWER_SCALE:bit2;
  FLR_CAPABLE              :bit1;
  RESERVED2                :bit3;
 end;

 TDPDBG_CNTL=bitpacked record
  DPDBG_ENABLE              :bit1;
  DPDBG_INPUT_ENABLE        :bit1;
  RESERVED0                 :bit2;
  DPDBG_SYMCLK_ON           :bit1;
  RESERVED1                 :bit3;
  DPDBG_ERROR_DETECTION_MODE:bit1;
  RESERVED2                 :bit7;
  DPDBG_LINE_LENGTH         :bit16;
 end;

 TDVO_CRC_EN=bitpacked record
  RESERVED0  :bit16;
  DVO_CRC2_EN:bit1;
  RESERVED1  :bit15;
 end;

 TDVO_ENABLE=bitpacked record
  DVO_ENABLE     :bit1;
  RESERVED0      :bit3;
  DVO_PIXEL_WIDTH:bit2;
  RESERVED1      :bit26;
 end;

 TDVO_OUTPUT=bitpacked record
  DVO_OUTPUT_ENABLE_MODE:bit2;
  RESERVED0             :bit6;
  DVO_CLOCK_MODE        :bit1;
  RESERVED1             :bit23;
 end;

 TFBC_DEBUG0=bitpacked record
  FBC_PERF_MUX0    :bit8;
  FBC_PERF_MUX1    :bit8;
  FBC_COMP_WAKE_DIS:bit1;
  FBC_DEBUG0       :bit7;
  FBC_DEBUG_MUX    :bit8;
 end;

 TFBC_DEBUG1=bit32;

 TFBC_DEBUG2=bit32;

 TFBC_STATUS=bitpacked record
  FBC_ENABLE_STATUS:bit1;
  RESERVED0        :bit31;
 end;

 TFMT_DEBUG0=bit32;

 TFMT_DEBUG1=bit32;

 TFMT_DEBUG2=bit32;

 TGDS_CONFIG=bitpacked record
  RESERVED0        :bit1;
  SH0_GPR_PHASE_SEL:bit2;
  SH1_GPR_PHASE_SEL:bit2;
  SH2_GPR_PHASE_SEL:bit2;
  SH3_GPR_PHASE_SEL:bit2;
  RESERVED1        :bit23;
 end;

 TGDS_OA_DED=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit1;
  UNUSED   :bit28;
 end;

 TGMCON_MASK=bitpacked record
  STCTRL_BUSY_MASK_ACP_RD :bit1;
  STCTRL_BUSY_MASK_ACP_WR :bit1;
  STCTRL_BUSY_MASK_VCE_RD :bit1;
  STCTRL_BUSY_MASK_VCE_WR :bit1;
  STCTRL_SR_HANDSHAKE_MASK:bit8;
  RESERVED0               :bit20;
 end;

 TGMCON_MISC=bitpacked record
  RESERVED0                     :bit10;
  RENG_EXECUTE_NOW_MODE         :bit1;
  RENG_EXECUTE_ON_REG_UPDATE    :bit1;
  RENG_SRBM_CREDITS_MCD         :bit4;
  STCTRL_STUTTER_EN             :bit1;
  STCTRL_GMC_IDLE_THRESHOLD     :bit2;
  STCTRL_SRBM_IDLE_THRESHOLD    :bit2;
  STCTRL_IGNORE_PRE_SR          :bit1;
  STCTRL_IGNORE_ALLOW_STOP      :bit1;
  STCTRL_IGNORE_SR_COMMIT       :bit1;
  STCTRL_IGNORE_PROTECTION_FAULT:bit1;
  STCTRL_DISABLE_ALLOW_SR       :bit1;
  STCTRL_DISABLE_GMC_OFFLINE    :bit1;
  CRITICAL_REGS_LOCK            :bit1;
  ALLOW_DEEP_SLEEP_MODE         :bit3;
  STCTRL_FORCE_ALLOW_SR         :bit1;
 end;

 TGPIOPAD_EN=bitpacked record
  GPIO_EN  :bit31;
  RESERVED0:bit1;
 end;

 TGRBM_DEBUG=bitpacked record
  RESERVED0                :bit1;
  IGNORE_RDY               :bit1;
  RESERVED1                :bit3;
  IGNORE_FAO               :bit1;
  DISABLE_READ_TIMEOUT     :bit1;
  SNAPSHOT_FREE_CNTRS      :bit1;
  HYSTERESIS_GUI_ACTIVE    :bit4;
  GFX_CLOCK_DOMAIN_OVERRIDE:bit1;
  GRBM_TRAP_ENABLE         :bit1;
  RESERVED2                :bit17;
  DEBUG_BUS_FGCG_EN        :bit1;
 end;

 TGRPH8_DATA=bitpacked record
  GRPH_DATA:bit8;
  RESERVED0:bit24;
 end;

 TGRPH_ALPHA=bitpacked record
  RESERVED0:bit8;
  RESERVED1:bit24;
 end;

 TGRPH_PITCH=bitpacked record
  GRPH_PITCH:bit15;
  RESERVED0 :bit17;
 end;

 TGRPH_X_END=bitpacked record
  GRPH_X_END:bit15;
  RESERVED0 :bit17;
 end;

 TGRPH_Y_END=bitpacked record
  GRPH_Y_END:bit15;
  RESERVED0 :bit17;
 end;

 THDP_DEBUG0=bit32;

 THDP_DEBUG1=bit32;

 TIA_ENHANCE=bit32;

 TIH_RB_BASE=bit32;

 TIH_RB_CNTL=bitpacked record
  RB_ENABLE            :bit1;
  RB_SIZE              :bit5;
  RB_FULL_DRAIN_ENABLE :bit1;
  RB_GPU_TS_ENABLE     :bit1;
  WPTR_WRITEBACK_ENABLE:bit1;
  WPTR_WRITEBACK_TIMER :bit5;
  RESERVED0            :bit2;
  WPTR_OVERFLOW_ENABLE :bit1;
  ENABLE_INTR          :bit1;
  MC_SWAP              :bit2;
  RESERVED1            :bit1;
  RPTR_REARM           :bit1;
  RESERVED2            :bit2;
  MC_VMID              :bit4;
  RESERVED3            :bit3;
  WPTR_OVERFLOW_CLEAR  :bit1;
 end;

 TIH_RB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit16;
  RESERVED1:bit14;
 end;

 TIH_RB_WPTR=bitpacked record
  RB_OVERFLOW    :bit1;
  RESERVED0      :bit1;
  OFFSET         :bit16;
  RB_LEFT_NONE   :bit1;
  RB_MAY_OVERFLOW:bit1;
  RESERVED1      :bit12;
 end;

 TIH_VERSION=bitpacked record
  VALUE    :bit12;
  RESERVED0:bit20;
 end;

 TLBV_DEBUG2=bit32;

 TLBV_DEBUG3=bit32;

 TLINK_CNTL2=bitpacked record
  TARGET_LINK_SPEED          :bit4;
  ENTER_COMPLIANCE           :bit1;
  HW_AUTONOMOUS_SPEED_DISABLE:bit1;
  SELECTABLE_DEEMPHASIS      :bit1;
  XMIT_MARGIN                :bit3;
  ENTER_MOD_COMPLIANCE       :bit1;
  COMPLIANCE_SOS             :bit1;
  COMPLIANCE_DEEMPHASIS      :bit4;
  RESERVED0                  :bit16;
 end;

 TLM_CONTROL=bitpacked record
  RESERVED0       :bit1;
  LoopbackSelect  :bit4;
  PRBSPCIeLbSelect:bit1;
  LoopbackHalfRate:bit2;
  LoopbackFifoPtr :bit3;
  RESERVED1       :bit21;
 end;

 TMC_ARB_POP=bitpacked record
  ENABLE_ARB              :bit1;
  SPEC_OPEN               :bit1;
  POP_DEPTH               :bit4;
  WRDATAINDEX_DEPTH       :bit6;
  SKID_DEPTH              :bit3;
  WAIT_AFTER_RFSH         :bit2;
  QUICK_STOP              :bit1;
  ENABLE_TWO_PAGE         :bit1;
  ALLOW_EOB_BY_WRRET_STALL:bit1;
  RESERVED0               :bit12;
 end;

 TMC_PMG_CFG=bitpacked record
  RESERVED0         :bit1;
  RESERVED1         :bit1;
  RESERVED2         :bit1;
  RESERVED3         :bit1;
  RESERVED4         :bit1;
  RESERVED5         :bit1;
  RESERVED6         :bit1;
  RESERVED7         :bit1;
  RESERVED8         :bit1;
  RESERVED9         :bit1;
  RESERVED10        :bit1;
  RESERVED11        :bit1;
  RESERVED12        :bit4;
  RESERVED13        :bit1;
  RESERVED14        :bit1;
  WRITE_DURING_DLOCK:bit1;
  RESERVED15        :bit1;
  RESERVED16        :bit4;
  EARLY_ACK_ACPI    :bit1;
  RESERVED17        :bit1;
  RESERVED18        :bit6;
 end;

 TMC_SEQ_CMD=bitpacked record
  ADR      :bit16;
  RESERVED0:bit4;
  MOP      :bit4;
  _END     :bit1;
  RESERVED1:bit3;
  CHAN0    :bit1;
  CHAN1    :bit1;
  RESERVED2:bit1;
  RESERVED3:bit1;
 end;

 TMP_FPS_CNT=bitpacked record
  FPS_CNT  :bit8;
  RESERVED0:bit24;
 end;

 TOVL_ENABLE=bitpacked record
  OVL_ENABLE:bit1;
  RESERVED0 :bit7;
  OVLSCL_EN :bit1;
  RESERVED1 :bit23;
 end;

 TOVL_UPDATE=bitpacked record
  OVL_UPDATE_PENDING         :bit1;
  OVL_UPDATE_TAKEN           :bit1;
  RESERVED0                  :bit14;
  OVL_UPDATE_LOCK            :bit1;
  RESERVED1                  :bit7;
  OVL_DISABLE_MULTIPLE_UPDATE:bit1;
  RESERVED2                  :bit7;
 end;

 TPCIE_CNTL2=bitpacked record
  TX_ARB_ROUND_ROBIN_EN       :bit1;
  TX_ARB_SLV_LIMIT            :bit5;
  TX_ARB_MST_LIMIT            :bit5;
  TX_BLOCK_TLP_ON_PM_DIS      :bit1;
  TX_NP_MEM_WRITE_SWP_ENCODING:bit1;
  TX_ATOMIC_OPS_DISABLE       :bit1;
  TX_ATOMIC_ORDERING_DIS      :bit1;
  RESERVED0                   :bit1;
  SLV_MEM_LS_EN               :bit1;
  SLV_MEM_AGGRESSIVE_LS_EN    :bit1;
  MST_MEM_LS_EN               :bit1;
  REPLAY_MEM_LS_EN            :bit1;
  SLV_MEM_SD_EN               :bit1;
  SLV_MEM_AGGRESSIVE_SD_EN    :bit1;
  MST_MEM_SD_EN               :bit1;
  REPLAY_MEM_SD_EN            :bit1;
  RX_NP_MEM_WRITE_ENCODING    :bit5;
  SLV_MEM_DS_EN               :bit1;
  MST_MEM_DS_EN               :bit1;
  REPLAY_MEM_DS_EN            :bit1;
 end;

 TPCIE_EFUSE=bit32;

 TPCIE_FC_NP=bitpacked record
  NPD_CREDITS:bit8;
  NPH_CREDITS:bit8;
  RESERVED0  :bit16;
 end;

 TPCIE_INDEX=bit32;

 TPERFMON_HI=bitpacked record
  PERFMON_HI      :bit16;
  RESERVED0       :bit13;
  PERFMON_READ_SEL:bit3;
 end;

 TPLL_ANALOG=bitpacked record
  PLL_CAL_MODE     :bit5;
  PLL_PFD_PULSE_SEL:bit2;
  RESERVED0        :bit1;
  PLL_CP           :bit4;
  PLL_LF_MODE      :bit9;
  PLL_VREG_FB_TRIM :bit3;
  PLL_IBIAS        :bit8;
 end;

 TPLL_FB_DIV=bitpacked record
  PLL_FB_DIV_FRACTION     :bit4;
  PLL_FB_DIV_FRACTION_CNTL:bit2;
  RESERVED0               :bit10;
  PLL_FB_DIV              :bit12;
  RESERVED1               :bit4;
 end;

 TPM_FUSES_1=bitpacked record
  SviLoadLineOffsetVddC:bit8;
  SviLoadLineTrimVddC  :bit8;
  SviLoadLineVddC      :bit8;
  SviLoadLineEn        :bit8;
 end;

 TPM_FUSES_2=bitpacked record
  TDC_MAWt                         :bit8;
  TDC_VDDC_ThrottleReleaseLimitPerc:bit8;
  TDC_VDDC_PkgLimit                :bit16;
 end;

 TPM_FUSES_3=bitpacked record
  Reserved          :bit8;
  LPMLTemperatureMax:bit8;
  LPMLTemperatureMin:bit8;
  TdcWaterfallCtl   :bit8;
 end;

 TPM_FUSES_4=bitpacked record
  LPMLTemperatureScaler_3:bit8;
  LPMLTemperatureScaler_2:bit8;
  LPMLTemperatureScaler_1:bit8;
  LPMLTemperatureScaler_0:bit8;
 end;

 TPM_FUSES_5=bitpacked record
  LPMLTemperatureScaler_7:bit8;
  LPMLTemperatureScaler_6:bit8;
  LPMLTemperatureScaler_5:bit8;
  LPMLTemperatureScaler_4:bit8;
 end;

 TPM_FUSES_6=bitpacked record
  LPMLTemperatureScaler_11:bit8;
  LPMLTemperatureScaler_10:bit8;
  LPMLTemperatureScaler_9 :bit8;
  LPMLTemperatureScaler_8 :bit8;
 end;

 TPM_FUSES_7=bitpacked record
  LPMLTemperatureScaler_15:bit8;
  LPMLTemperatureScaler_14:bit8;
  LPMLTemperatureScaler_13:bit8;
  LPMLTemperatureScaler_12:bit8;
 end;

 TPM_FUSES_8=bitpacked record
  FuzzyFan_ErrorRateSetDelta:bit16;
  FuzzyFan_ErrorSetDelta    :bit16;
 end;

 TPM_FUSES_9=bitpacked record
  Reserved6           :bit16;
  FuzzyFan_PwmSetDelta:bit16;
 end;

 TROM_STATUS=bitpacked record
  ROM_BUSY :bit1;
  RESERVED0:bit31;
 end;

 TSCLV_DEBUG=bit32;

 TSCL_DEBUG2=bitpacked record
  SCL_DEBUG_REQ_MODE:bit1;
  SCL_DEBUG_EOF_MODE:bit2;
  SCL_DEBUG2        :bit29;
 end;

 TSCL_UPDATE=bitpacked record
  SCL_UPDATE_PENDING      :bit1;
  RESERVED0               :bit7;
  SCL_UPDATE_TAKEN        :bit1;
  RESERVED1               :bit7;
  SCL_UPDATE_LOCK         :bit1;
  RESERVED2               :bit7;
  SCL_COEF_UPDATE_COMPLETE:bit1;
  RESERVED3               :bit7;
 end;

 TSDMA0_CNTL=bitpacked record
  TRAP_ENABLE              :bit1;
  ATC_L1_ENABLE            :bit1;
  SEM_WAIT_INT_ENABLE      :bit1;
  DATA_SWAP_ENABLE         :bit1;
  FENCE_SWAP_ENABLE        :bit1;
  MIDCMD_PREEMPT_ENABLE    :bit1;
  RESERVED0                :bit5;
  MC_WRREQ_CREDIT          :bit6;
  MIDCMD_WORLDSWITCH_ENABLE:bit1;
  AUTO_CTXSW_ENABLE        :bit1;
  RESERVED1                :bit1;
  RESERVED2                :bit2;
  MC_RDREQ_CREDIT          :bit6;
  CTXEMPTY_INT_ENABLE      :bit1;
  FROZEN_INT_ENABLE        :bit1;
  IB_PREEMPT_INT_ENABLE    :bit1;
  RESERVED3                :bit1;
 end;

 TSDMA0_HASH=bitpacked record
  CHANNEL_BITS     :bit3;
  RESERVED0        :bit1;
  BANK_BITS        :bit3;
  RESERVED1        :bit1;
  CHANNEL_XOR_COUNT:bit3;
  RESERVED2        :bit1;
  BANK_XOR_COUNT   :bit3;
  RESERVED3        :bit17;
 end;

 TSDMA1_CNTL=bitpacked record
  TRAP_ENABLE              :bit1;
  ATC_L1_ENABLE            :bit1;
  SEM_WAIT_INT_ENABLE      :bit1;
  DATA_SWAP_ENABLE         :bit1;
  FENCE_SWAP_ENABLE        :bit1;
  MIDCMD_PREEMPT_ENABLE    :bit1;
  RESERVED0                :bit5;
  MC_WRREQ_CREDIT          :bit6;
  MIDCMD_WORLDSWITCH_ENABLE:bit1;
  AUTO_CTXSW_ENABLE        :bit1;
  RESERVED1                :bit1;
  RESERVED2                :bit2;
  MC_RDREQ_CREDIT          :bit6;
  CTXEMPTY_INT_ENABLE      :bit1;
  FROZEN_INT_ENABLE        :bit1;
  IB_PREEMPT_INT_ENABLE    :bit1;
  RESERVED3                :bit1;
 end;

 TSDMA1_HASH=bitpacked record
  CHANNEL_BITS     :bit3;
  RESERVED0        :bit1;
  BANK_BITS        :bit3;
  RESERVED1        :bit1;
  CHANNEL_XOR_COUNT:bit3;
  RESERVED2        :bit1;
  BANK_XOR_COUNT   :bit3;
  RESERVED3        :bit17;
 end;

 TSEM_STATUS=bitpacked record
  SEM_IDLE             :bit1;
  SEM_INTERNAL_IDLE    :bit1;
  MC_RDREQ_FIFO_FULL   :bit1;
  MC_WRREQ_FIFO_FULL   :bit1;
  WRITE1_FIFO_FULL     :bit1;
  CHECK0_FIFO_FULL     :bit1;
  MC_RDREQ_PENDING     :bit1;
  MC_WRREQ_PENDING     :bit1;
  SDMA0_MAILBOX_PENDING:bit1;
  SDMA1_MAILBOX_PENDING:bit1;
  UVD_MAILBOX_PENDING  :bit1;
  VCE_MAILBOX_PENDING  :bit1;
  CPG1_MAILBOX_PENDING :bit1;
  CPG2_MAILBOX_PENDING :bit1;
  VCE1_MAILBOX_PENDING :bit1;
  ATC_REQ_PENDING      :bit1;
  RESERVED0            :bit15;
  SWITCH_READY         :bit1;
 end;

 TSMC_RESP_0=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMC_RESP_1=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMC_RESP_2=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMC_RESP_3=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMC_RESP_4=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMC_RESP_5=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMC_RESP_6=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMC_RESP_7=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMC_RESP_8=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMC_RESP_9=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSPMI_RESET=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit30;
  RESERVED2:bit1;
 end;

 TSPMI_SPARE=bit32;

 TSQC_CACHES=bitpacked record
  TARGET_INST:bit1;
  TARGET_DATA:bit1;
  INVALIDATE :bit1;
  WRITEBACK  :bit1;
  VOL        :bit1;
  RESERVED0  :bit11;
  COMPLETE   :bit1;
  RESERVED1  :bit15;
 end;

 TSQC_CONFIG=bitpacked record
  INST_CACHE_SIZE     :bit2;
  DATA_CACHE_SIZE     :bit2;
  MISS_FIFO_DEPTH     :bit2;
  HIT_FIFO_DEPTH      :bit1;
  FORCE_ALWAYS_MISS   :bit1;
  FORCE_IN_ORDER      :bit1;
  IDENTITY_HASH_BANK  :bit1;
  IDENTITY_HASH_SET   :bit1;
  PER_VMID_INV_DISABLE:bit1;
  EVICT_LRU           :bit2;
  FORCE_2_BANK        :bit1;
  FORCE_1_BANK        :bit1;
  LS_DISABLE_CLOCKS   :bit8;
  RESERVED0           :bit8;
 end;

 TSQ_MTBUF_0=bitpacked record
  OFFSET  :bit12;
  OFFEN   :bit1;
  IDXEN   :bit1;
  GLC     :bit1;
  OP      :bit4;
  DFMT    :bit4;
  NFMT    :bit3;
  ENCODING:bit6;
 end;

 TSQ_MTBUF_1=bitpacked record
  VADDR    :bit8;
  VDATA    :bit8;
  SRSRC    :bit5;
  RESERVED0:bit1;
  SLC      :bit1;
  TFE      :bit1;
  SOFFSET  :bit8;
 end;

 TSQ_MUBUF_0=bitpacked record
  OFFSET   :bit12;
  OFFEN    :bit1;
  IDXEN    :bit1;
  GLC      :bit1;
  ADDR64   :bit1;
  LDS      :bit1;
  SLC      :bit1;
  OP       :bit7;
  RESERVED0:bit1;
  ENCODING :bit6;
 end;

 TSQ_MUBUF_1=bitpacked record
  VADDR    :bit8;
  VDATA    :bit8;
  SRSRC    :bit5;
  RESERVED0:bit2;
  TFE      :bit1;
  SOFFSET  :bit8;
 end;

 TSQ_TIME_HI=bit32;

 TSQ_TIME_LO=bit32;

 TSQ_VOP_DPP=bitpacked record
  SRC0      :bit8;
  DPP_CTRL  :bit9;
  RESERVED0 :bit2;
  BOUND_CTRL:bit1;
  SRC0_NEG  :bit1;
  SRC0_ABS  :bit1;
  SRC1_NEG  :bit1;
  SRC1_ABS  :bit1;
  BANK_MASK :bit4;
  ROW_MASK  :bit4;
 end;

 TSQ_WAVE_M0=bit32;

 TSRBM_DEBUG=bitpacked record
  IGNORE_RDY                :bit1;
  DISABLE_READ_TIMEOUT      :bit1;
  SNAPSHOT_FREE_CNTRS       :bit1;
  RESERVED0                 :bit1;
  SYS_CLOCK_DOMAIN_OVERRIDE :bit1;
  VCE_CLOCK_DOMAIN_OVERRIDE :bit1;
  UVD_CLOCK_DOMAIN_OVERRIDE :bit1;
  SDMA_CLOCK_DOMAIN_OVERRIDE:bit1;
  MC_CLOCK_DOMAIN_OVERRIDE  :bit1;
  SAM_CLOCK_DOMAIN_OVERRIDE :bit1;
  ISP_CLOCK_DOMAIN_OVERRIDE :bit1;
  VP8_CLOCK_DOMAIN_OVERRIDE :bit1;
  RESERVED1                 :bit20;
 end;

 TSX_DEBUG_1=bitpacked record
  SX_DB_QUAD_CREDIT              :bit7;
  RESERVED0                      :bit1;
  DISABLE_BLEND_OPT_DONT_RD_DST  :bit1;
  DISABLE_BLEND_OPT_BYPASS       :bit1;
  DISABLE_BLEND_OPT_DISCARD_PIXEL:bit1;
  DISABLE_QUAD_PAIR_OPT          :bit1;
  DISABLE_PIX_EN_ZERO_OPT        :bit1;
  DEBUG_DATA                     :bit19;
 end;

 TTA_SCRATCH=bit32;

 TTCI_CNTL_1=bitpacked record
  WBINVL1_NUM_CYCLES:bit16;
  REQ_FIFO_DEPTH    :bit8;
  WDATA_RAM_DEPTH   :bit8;
 end;

 TTCI_CNTL_2=bitpacked record
  L1_INVAL_ON_WBINVL2:bit1;
  TCA_MAX_CREDIT     :bit8;
  RESERVED0          :bit23;
 end;

 TTCI_STATUS=bitpacked record
  TCI_BUSY :bit1;
  RESERVED0:bit31;
 end;

 TTCP_CREDIT=bitpacked record
  LFIFO_CREDIT   :bit10;
  RESERVED0      :bit6;
  REQ_FIFO_CREDIT:bit7;
  RESERVED1      :bit6;
  TD_CREDIT      :bit3;
 end;

 TTCP_STATUS=bitpacked record
  TCP_BUSY    :bit1;
  INPUT_BUSY  :bit1;
  ADRS_BUSY   :bit1;
  TAGRAMS_BUSY:bit1;
  CNTRL_BUSY  :bit1;
  LFIFO_BUSY  :bit1;
  READ_BUSY   :bit1;
  FORMAT_BUSY :bit1;
  RESERVED0   :bit24;
 end;

 TTDC_STATUS=bitpacked record
  VDD_Boost    :bit8;
  VDD_Throttle :bit8;
  VDDC_Boost   :bit8;
  VDDC_Throttle:bit8;
 end;

 TTD_SCRATCH=bit32;

 TTMDS_DEBUG=bitpacked record
  TMDS_DEBUG_EN      :bit1;
  RESERVED0          :bit7;
  TMDS_DEBUG_HSYNC   :bit1;
  TMDS_DEBUG_HSYNC_EN:bit1;
  RESERVED1          :bit6;
  TMDS_DEBUG_VSYNC   :bit1;
  TMDS_DEBUG_VSYNC_EN:bit1;
  RESERVED2          :bit6;
  TMDS_DEBUG_DE      :bit1;
  TMDS_DEBUG_DE_EN   :bit1;
  RESERVED3          :bit6;
 end;

 TUNP_DEBUG2=bit32;

 TUVD_CONFIG=bitpacked record
  RESERVED0    :bit8;
  UVD_RDREQ_URG:bit4;
  RESERVED1    :bit4;
  UVD_REQ_TRAN :bit1;
  RESERVED2    :bit15;
 end;

 TUVD_STATUS=bitpacked record
  RBC_BUSY   :bit1;
  VCPU_REPORT:bit7;
  RESERVED0  :bit1;
  RESERVED1  :bit1;
  RESERVED2  :bit1;
  RESERVED3  :bit1;
  RESERVED4  :bit1;
  RESERVED5  :bit1;
  RESERVED6  :bit1;
  RESERVED7  :bit1;
  RESERVED8  :bit1;
  RESERVED9  :bit1;
  RESERVED10 :bit13;
  RESERVED11 :bit1;
 end;

 TVCE_CONFIG=bitpacked record
  RESERVED0    :bit8;
  VCE_RDREQ_URG:bit4;
  RESERVED1    :bit4;
  VCE_REQ_TRAN :bit1;
  RESERVED2    :bit15;
 end;

 TVCE_STATUS=bitpacked record
  JOB_BUSY         :bit1;
  VCPU_REPORT      :bit7;
  UENC_BUSY        :bit1;
  RESERVED0        :bit13;
  VCE_CONFIGURATION:bit2;
  VCE_INSTANCE_ID  :bit2;
  RESERVED1        :bit4;
  RESERVED2        :bit1;
  RESERVED3        :bit1;
 end;

 TVGA_STATUS=bitpacked record
  VGA_MEM_ACCESS_STATUS       :bit1;
  VGA_REG_ACCESS_STATUS       :bit1;
  VGA_DISPLAY_SWITCH_STATUS   :bit1;
  VGA_MODE_AUTO_TRIGGER_STATUS:bit1;
  RESERVED0                   :bit28;
 end;

 TVM_L2_CNTL=bitpacked record
  ENABLE_L2_CACHE                         :bit1;
  ENABLE_L2_FRAGMENT_PROCESSING           :bit1;
  L2_CACHE_PTE_ENDIAN_SWAP_MODE           :bit2;
  L2_CACHE_PDE_ENDIAN_SWAP_MODE           :bit2;
  RESERVED0                               :bit2;
  L2_PDE0_CACHE_TAG_GENERATION_MODE       :bit1;
  ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE :bit1;
  ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE:bit1;
  ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY:bit1;
  L2_PDE0_CACHE_SPLIT_MODE                :bit3;
  EFFECTIVE_L2_QUEUE_SIZE                 :bit3;
  PDE_FAULT_CLASSIFICATION                :bit1;
  CONTEXT1_IDENTITY_ACCESS_MODE           :bit2;
  IDENTITY_MODE_FRAGMENT_SIZE             :bit5;
  L2_CACHE_4K_SWAP_TAG_INDEX_LSBS         :bit2;
  L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS       :bit3;
  RESERVED1                               :bit1;
 end;

 TWD_ENHANCE=bit32;

 TAFMT_STATUS=bitpacked record
  RESERVED0               :bit4;
  AFMT_AUDIO_ENABLE       :bit1;
  RESERVED1               :bit3;
  AFMT_AZ_HBR_ENABLE      :bit1;
  RESERVED2               :bit15;
  AFMT_AUDIO_FIFO_OVERFLOW:bit1;
  RESERVED3               :bit5;
  AFMT_AZ_AUDIO_ENABLE_CHG:bit1;
  RESERVED4               :bit1;
 end;

 TATC_L1_CNTL=bitpacked record
  DONT_NEED_ATS_BEHAVIOR:bit2;
  NEED_ATS_BEHAVIOR     :bit1;
  RESERVED0             :bit1;
  NEED_ATS_SNOOP_DEFAULT:bit1;
  RESERVED1             :bit27;
 end;

 TATC_L2_CNTL=bitpacked record
  NUMBER_OF_TRANSLATION_READ_REQUESTS             :bit2;
  RESERVED0                                       :bit2;
  NUMBER_OF_TRANSLATION_WRITE_REQUESTS            :bit2;
  RESERVED1                                       :bit2;
  NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD :bit1;
  NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD:bit1;
  RESERVED2                                       :bit22;
 end;

 TATC_MISC_CG=bitpacked record
  RESERVED0    :bit6;
  OFFDLY       :bit6;
  RESERVED1    :bit6;
  ENABLE       :bit1;
  MEM_LS_ENABLE:bit1;
  RESERVED2    :bit12;
 end;

 TAUXN_IMPCAL=bitpacked record
  AUXN_IMPCAL_ENABLE         :bit1;
  RESERVED0                  :bit7;
  AUXN_IMPCAL_CALOUT         :bit1;
  AUXN_CALOUT_ERROR          :bit1;
  AUXN_CALOUT_ERROR_AK       :bit1;
  RESERVED1                  :bit5;
  AUXN_IMPCAL_VALUE          :bit4;
  AUXN_IMPCAL_STEP_DELAY     :bit4;
  AUXN_IMPCAL_OVERRIDE       :bit4;
  AUXN_IMPCAL_OVERRIDE_ENABLE:bit1;
  RESERVED2                  :bit3;
 end;

 TAUXP_IMPCAL=bitpacked record
  AUXP_IMPCAL_ENABLE         :bit1;
  RESERVED0                  :bit7;
  AUXP_IMPCAL_CALOUT         :bit1;
  AUXP_CALOUT_ERROR          :bit1;
  AUXP_CALOUT_ERROR_AK       :bit1;
  RESERVED1                  :bit5;
  AUXP_IMPCAL_VALUE          :bit4;
  AUXP_IMPCAL_STEP_DELAY     :bit4;
  AUXP_IMPCAL_OVERRIDE       :bit4;
  AUXP_IMPCAL_OVERRIDE_ENABLE:bit1;
  RESERVED2                  :bit3;
 end;

 TAUX_CONTROL=bitpacked record
  AUX_EN               :bit1;
  RESERVED0            :bit7;
  AUX_LS_READ_EN       :bit1;
  RESERVED1            :bit3;
  AUX_LS_UPDATE_DISABLE:bit1;
  RESERVED2            :bit3;
  AUX_IGNORE_HPD_DISCON:bit1;
  RESERVED3            :bit1;
  AUX_MODE_DET_EN      :bit1;
  RESERVED4            :bit1;
  AUX_HPD_SEL          :bit3;
  RESERVED5            :bit1;
  AUX_IMPCAL_REQ_EN    :bit1;
  RESERVED6            :bit3;
  AUX_TEST_MODE        :bit1;
  AUX_DEGLITCH_EN      :bit1;
  SPARE_0              :bit1;
  SPARE_1              :bit1;
 end;

 TAUX_LS_DATA=bitpacked record
  RESERVED0   :bit8;
  AUX_LS_DATA :bit8;
  AUX_LS_INDEX:bit5;
  RESERVED1   :bit11;
 end;

 TAUX_SW_DATA=bitpacked record
  AUX_SW_DATA_RW              :bit1;
  RESERVED0                   :bit7;
  AUX_SW_DATA                 :bit8;
  AUX_SW_INDEX                :bit5;
  RESERVED1                   :bit10;
  AUX_SW_AUTOINCREMENT_DISABLE:bit1;
 end;

 TBASE_ADDR_1=bit32;

 TBASE_ADDR_2=bit32;

 TBASE_ADDR_3=bit32;

 TBASE_ADDR_4=bit32;

 TBASE_ADDR_5=bit32;

 TBASE_ADDR_6=bit32;

 TBIF_RB_BASE=bit32;

 TBIF_RB_CNTL=bitpacked record
  RB_ENABLE            :bit1;
  RB_SIZE              :bit5;
  RESERVED0            :bit2;
  WPTR_WRITEBACK_ENABLE:bit1;
  WPTR_WRITEBACK_TIMER :bit5;
  RESERVED1            :bit3;
  BIF_RB_TRAN          :bit1;
  RESERVED2            :bit13;
  WPTR_OVERFLOW_CLEAR  :bit1;
 end;

 TBIF_RB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit16;
  RESERVED1:bit14;
 end;

 TBIF_RB_WPTR=bitpacked record
  BIF_RB_OVERFLOW:bit1;
  RESERVED0      :bit1;
  OFFSET         :bit16;
  RESERVED1      :bit14;
 end;

 TBIF_XDMA_HI=bitpacked record
  BIF_XDMA_UPPER_BOUND:bit29;
  RESERVED0           :bit3;
 end;

 TBIF_XDMA_LO=bitpacked record
  BIF_XDMA_LOWER_BOUND:bit29;
  RESERVED0           :bit2;
  BIF_XDMA_APER_EN    :bit1;
 end;

 TBLND_UPDATE=bitpacked record
  BLND_UPDATE_PENDING:bit1;
  RESERVED0          :bit7;
  BLND_UPDATE_TAKEN  :bit1;
  RESERVED1          :bit7;
  BLND_UPDATE_LOCK   :bit1;
  RESERVED2          :bit15;
 end;

 TBL_PWM_CNTL=bitpacked record
  BL_ACTIVE_INT_FRAC_CNT:bit16;
  RESERVED0             :bit14;
  BL_PWM_FRACTIONAL_EN  :bit1;
  BL_PWM_EN             :bit1;
 end;

 TBX_RESET_EN=bitpacked record
  COR_RESET_EN            :bit1;
  REG_RESET_EN            :bit1;
  STY_RESET_EN            :bit1;
  RESERVED0               :bit5;
  FLR_TWICE_EN            :bit1;
  FLR_TIMER_SEL           :bit2;
  RESERVED1               :bit4;
  DB_APER_RESET_EN        :bit1;
  RESET_ON_VFENABLE_LOW_EN:bit1;
  PF_FLR_NEWHDL_EN        :bit1;
  RESERVED2               :bit14;
 end;

 TCGTS_RD_REG=bitpacked record
  READ_DATA:bit14;
  RESERVED0:bit18;
 end;

 TCLIENT0_CD0=bit32;

 TCLIENT0_CD1=bit32;

 TCLIENT0_CD2=bit32;

 TCLIENT0_CD3=bit32;

 TCLIENT0_CK0=bit32;

 TCLIENT0_CK1=bit32;

 TCLIENT0_CK2=bit32;

 TCLIENT0_CK3=bit32;

 TCLIENT1_CD0=bit32;

 TCLIENT1_CD1=bit32;

 TCLIENT1_CD2=bit32;

 TCLIENT1_CD3=bit32;

 TCLIENT1_CK0=bit32;

 TCLIENT1_CK1=bit32;

 TCLIENT1_CK2=bit32;

 TCLIENT1_CK3=bit32;

 TCLIENT2_CD0=bit32;

 TCLIENT2_CD1=bit32;

 TCLIENT2_CD2=bit32;

 TCLIENT2_CD3=bit32;

 TCLIENT2_CK0=bit32;

 TCLIENT2_CK1=bit32;

 TCLIENT2_CK2=bit32;

 TCLIENT2_CK3=bit32;

 TCLIENT3_CD0=bit32;

 TCLIENT3_CD1=bit32;

 TCLIENT3_CD2=bit32;

 TCLIENT3_CD3=bit32;

 TCLIENT3_CK0=bit32;

 TCLIENT3_CK1=bit32;

 TCLIENT3_CK2=bit32;

 TCLIENT3_CK3=bit32;

 TCLIENT4_CD0=bit32;

 TCLIENT4_CD1=bit32;

 TCLIENT4_CD2=bit32;

 TCLIENT4_CD3=bit32;

 TCLIENT4_CK0=bit32;

 TCLIENT4_CK1=bit32;

 TCLIENT4_CK2=bit32;

 TCLIENT4_CK3=bit32;

 TCONFIG_CNTL=bitpacked record
  CFG_VGA_RAM_EN      :bit1;
  VGA_DIS             :bit1;
  GENMO_MONO_ADDRESS_B:bit1;
  GRPH_ADRSEL         :bit2;
  RESERVED0           :bit27;
 end;

 TCORB_STATUS=bitpacked record
  CORB_MEMORY_ERROR_INDICATION:bit1;
  RESERVED0                   :bit31;
 end;

 TCPM_CONTROL=bitpacked record
  LCLK_DYN_GATE_ENABLE    :bit1;
  TXCLK_DYN_GATE_ENABLE   :bit1;
  TXCLK_PERM_GATE_ENABLE  :bit1;
  TXCLK_PIF_GATE_ENABLE   :bit1;
  TXCLK_GSKT_GATE_ENABLE  :bit1;
  TXCLK_LCNT_GATE_ENABLE  :bit1;
  TXCLK_REGS_GATE_ENABLE  :bit1;
  TXCLK_PRBS_GATE_ENABLE  :bit1;
  REFCLK_REGS_GATE_ENABLE :bit1;
  LCLK_DYN_GATE_LATENCY   :bit1;
  TXCLK_DYN_GATE_LATENCY  :bit1;
  TXCLK_PERM_GATE_LATENCY :bit1;
  TXCLK_REGS_GATE_LATENCY :bit1;
  REFCLK_REGS_GATE_LATENCY:bit1;
  LCLK_GATE_TXCLK_FREE    :bit1;
  RCVR_DET_CLK_ENABLE     :bit1;
  TXCLK_PERM_GATE_PLL_PDN :bit1;
  FAST_TXCLK_LATENCY      :bit3;
  MASTER_PCIE_PLL_SELECT  :bit1;
  MASTER_PCIE_PLL_AUTO    :bit1;
  REFCLK_XSTCLK_ENABLE    :bit1;
  REFCLK_XSTCLK_LATENCY   :bit1;
  SPARE_REGS              :bit8;
 end;

 TCP_CMD_DATA=bit32;

 TCP_CSF_CNTL=bitpacked record
  FETCH_BUFFER_DEPTH:bit4;
  RESERVED0         :bit28;
 end;

 TCP_CSF_STAT=bitpacked record
  BUFFER_SLOTS_ALLOCATED:bit4;
  RESERVED0             :bit4;
  BUFFER_REQUEST_COUNT  :bit9;
  RESERVED1             :bit15;
 end;

 TCP_DFY_CNTL=bitpacked record
  POLICY    :bit1;
  RESERVED0 :bit1;
  MTYPE     :bit2;
  RESERVED1 :bit23;
  RESERVED2 :bit1;
  LFSR_RESET:bit1;
  MODE      :bit2;
  ENABLE    :bit1;
 end;

 TCP_DFY_STAT=bitpacked record
  BURST_COUNT :bit16;
  TAGS_PENDING:bit9;
  RESERVED0   :bit6;
  BUSY        :bit1;
 end;

 TCP_DMA_CNTL=bitpacked record
  RESERVED0     :bit4;
  MIN_AVAILSZ   :bit2;
  RESERVED1     :bit10;
  BUFFER_DEPTH  :bit4;
  RESERVED2     :bit8;
  PIO_FIFO_EMPTY:bit1;
  PIO_FIFO_FULL :bit1;
  PIO_COUNT     :bit2;
 end;

 TCP_HQD_VMID=bitpacked record
  VMID     :bit4;
  RESERVED0:bit4;
  IB_VMID  :bit4;
  RESERVED1:bit4;
  VQID     :bit10;
  RESERVED2:bit6;
 end;

 TCP_INT_CNTL=bitpacked record
  RESERVED0                    :bit11;
  CP_VM_DOORBELL_WR_INT_ENABLE :bit1;
  RESERVED1                    :bit2;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  RESERVED2                    :bit2;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  CMP_BUSY_INT_ENABLE          :bit1;
  CNTX_BUSY_INT_ENABLE         :bit1;
  CNTX_EMPTY_INT_ENABLE        :bit1;
  GFX_IDLE_INT_ENABLE          :bit1;
  PRIV_INSTR_INT_ENABLE        :bit1;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_MEC_CNTL=bitpacked record
  RESERVED0            :bit4;
  MEC_INVALIDATE_ICACHE:bit1;
  RESERVED1            :bit11;
  MEC_ME1_PIPE0_RESET  :bit1;
  MEC_ME1_PIPE1_RESET  :bit1;
  MEC_ME1_PIPE2_RESET  :bit1;
  MEC_ME1_PIPE3_RESET  :bit1;
  MEC_ME2_PIPE0_RESET  :bit1;
  MEC_ME2_PIPE1_RESET  :bit1;
  RESERVED2            :bit6;
  MEC_ME2_HALT         :bit1;
  MEC_ME2_STEP         :bit1;
  MEC_ME1_HALT         :bit1;
  MEC_ME1_STEP         :bit1;
 end;

 TCP_MEQ_STAT=bitpacked record
  MEQ_RPTR :bit10;
  RESERVED0:bit6;
  MEQ_WPTR :bit10;
  RESERVED1:bit6;
 end;

 TCP_PWR_CNTL=bitpacked record
  GFX_CLK_HALT_ME0_PIPE0:bit1;
  GFX_CLK_HALT_ME0_PIPE1:bit1;
  RESERVED0             :bit6;
  CMP_CLK_HALT_ME1_PIPE0:bit1;
  CMP_CLK_HALT_ME1_PIPE1:bit1;
  CMP_CLK_HALT_ME1_PIPE2:bit1;
  CMP_CLK_HALT_ME1_PIPE3:bit1;
  RESERVED1             :bit4;
  CMP_CLK_HALT_ME2_PIPE0:bit1;
  CMP_CLK_HALT_ME2_PIPE1:bit1;
  CMP_CLK_HALT_ME2_PIPE2:bit1;
  CMP_CLK_HALT_ME2_PIPE3:bit1;
  RESERVED2             :bit12;
 end;

 TCP_RB0_BASE=bit32;

 TCP_RB0_CNTL=bitpacked record
  RB_BUFSZ      :bit6;
  RESERVED0     :bit2;
  RB_BLKSZ      :bit6;
  RESERVED1     :bit1;
  MTYPE         :bit2;
  BUF_SWAP      :bit2;
  RESERVED2     :bit1;
  MIN_AVAILSZ   :bit2;
  MIN_IB_AVAILSZ:bit2;
  CACHE_POLICY  :bit1;
  RESERVED3     :bit2;
  RB_NO_UPDATE  :bit1;
  RESERVED4     :bit3;
  RB_RPTR_WR_ENA:bit1;
 end;

 TCP_RB0_RPTR=bitpacked record
  RB_RPTR  :bit20;
  RESERVED0:bit12;
 end;

 TCP_RB0_WPTR=bitpacked record
  RB_WPTR  :bit20;
  RESERVED0:bit12;
 end;

 TCP_RB1_BASE=bit32;

 TCP_RB1_CNTL=bitpacked record
  RB_BUFSZ      :bit6;
  RESERVED0     :bit2;
  RB_BLKSZ      :bit6;
  RESERVED1     :bit1;
  MTYPE         :bit2;
  RESERVED2     :bit3;
  MIN_AVAILSZ   :bit2;
  MIN_IB_AVAILSZ:bit2;
  CACHE_POLICY  :bit1;
  RESERVED3     :bit2;
  RB_NO_UPDATE  :bit1;
  RESERVED4     :bit3;
  RB_RPTR_WR_ENA:bit1;
 end;

 TCP_RB1_RPTR=bitpacked record
  RB_RPTR  :bit20;
  RESERVED0:bit12;
 end;

 TCP_RB1_WPTR=bitpacked record
  RB_WPTR  :bit20;
  RESERVED0:bit12;
 end;

 TCP_RB2_BASE=bit32;

 TCP_RB2_CNTL=bitpacked record
  RB_BUFSZ      :bit6;
  RESERVED0     :bit2;
  RB_BLKSZ      :bit6;
  RESERVED1     :bit1;
  MTYPE         :bit2;
  RESERVED2     :bit3;
  MIN_AVAILSZ   :bit2;
  MIN_IB_AVAILSZ:bit2;
  CACHE_POLICY  :bit1;
  RESERVED3     :bit2;
  RB_NO_UPDATE  :bit1;
  RESERVED4     :bit3;
  RB_RPTR_WR_ENA:bit1;
 end;

 TCP_RB2_RPTR=bitpacked record
  RB_RPTR  :bit20;
  RESERVED0:bit12;
 end;

 TCP_RB2_WPTR=bitpacked record
  RB_WPTR  :bit20;
  RESERVED0:bit12;
 end;

 TCP_STQ_STAT=bitpacked record
  STQ_RPTR :bit10;
  RESERVED0:bit6;
  RESERVED1:bit10;
  RESERVED2:bit6;
 end;

 TCP_ST_BUFSZ=bitpacked record
  ST_BUFSZ :bit20;
  RESERVED0:bit12;
 end;

 TCRTC_STATUS=bitpacked record
  CRTC_V_BLANK             :bit1;
  CRTC_V_ACTIVE_DISP       :bit1;
  CRTC_V_SYNC_A            :bit1;
  CRTC_V_UPDATE            :bit1;
  CRTC_V_START_LINE        :bit1;
  CRTC_V_BLANK_3D_STRUCTURE:bit1;
  RESERVED0                :bit10;
  CRTC_H_BLANK             :bit1;
  CRTC_H_ACTIVE_DISP       :bit1;
  CRTC_H_SYNC_A            :bit1;
  RESERVED1                :bit13;
 end;

 TCUR2_COLOR1=bitpacked record
  CUR2_COLOR1_BLUE :bit8;
  CUR2_COLOR1_GREEN:bit8;
  CUR2_COLOR1_RED  :bit8;
  RESERVED0        :bit8;
 end;

 TCUR2_COLOR2=bitpacked record
  CUR2_COLOR2_BLUE :bit8;
  CUR2_COLOR2_GREEN:bit8;
  CUR2_COLOR2_RED  :bit8;
  RESERVED0        :bit8;
 end;

 TCUR2_UPDATE=bitpacked record
  CURSOR2_UPDATE_PENDING         :bit1;
  CURSOR2_UPDATE_TAKEN           :bit1;
  RESERVED0                      :bit14;
  CURSOR2_UPDATE_LOCK            :bit1;
  RESERVED1                      :bit7;
  CURSOR2_DISABLE_MULTIPLE_UPDATE:bit1;
  CURSOR2_UPDATE_STEREO_MODE     :bit2;
  RESERVED2                      :bit5;
 end;

 TCUR_CONTROL=bitpacked record
  CURSOR_EN            :bit1;
  RESERVED0            :bit3;
  CUR_INV_TRANS_CLAMP  :bit1;
  RESERVED1            :bit3;
  CURSOR_MODE          :bit2;
  RESERVED2            :bit6;
  CURSOR_2X_MAGNIFY    :bit1;
  RESERVED3            :bit3;
  CURSOR_FORCE_MC_ON   :bit1;
  RESERVED4            :bit3;
  CURSOR_URGENT_CONTROL:bit3;
  RESERVED5            :bit5;
 end;

 TDAC_CONTROL=bitpacked record
  DAC_DFORCE_EN   :bit1;
  RESERVED0       :bit7;
  DAC_TV_ENABLE   :bit1;
  RESERVED1       :bit7;
  DAC_ZSCALE_SHIFT:bit1;
  RESERVED2       :bit15;
 end;

 TDAC_R_INDEX=bitpacked record
  DAC_R_INDEX:bit8;
  RESERVED0  :bit24;
 end;

 TDAC_W_INDEX=bitpacked record
  DAC_W_INDEX:bit8;
  RESERVED0  :bit24;
 end;

 TDATA_FORMAT=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit3;
  RESERVED2 :bit1;
  RESERVED3 :bit3;
  RESERVED4 :bit1;
  RESERVED5 :bit3;
  RESERVED6 :bit1;
  RESERVED7 :bit3;
  RESERVED8 :bit5;
  RESERVED9 :bit3;
  RESERVED10:bit2;
  RESERVED11:bit2;
  RESERVED12:bit1;
  RESERVED13:bit3;
 end;

 TDCIO_DEBUG1=bitpacked record
  DCO_DCIO_MVP_DVOCNTL_A0_REG  :bit2;
  DCO_DCIO_MVP_DVOCNTL_MASK_REG:bit2;
  DCO_DCIO_MVP_DVOCNTL_EN_REG  :bit2;
  DCO_DCIO_MVP_DVOCNTL_A0      :bit2;
  DCO_DCIO_MVP_DVOCNTL_SEL0    :bit2;
  DCO_DCIO_MVP_DVOCNTL_EN      :bit2;
  DCO_DCIO_MVP_DVOCLK_C        :bit1;
  DCO_DCIO_DVOCNTL1_A0_REG     :bit1;
  DCO_DCIO_DVOCNTL1_A0_PREMUX  :bit1;
  DCO_DCIO_DVOCNTL1_A0         :bit1;
  DCO_DCIO_DVOCNTL1_EN_REG     :bit1;
  DCO_DCIO_DVO_HSYNC_TRISTATE  :bit1;
  DCO_DCIO_DVO_CLK_TRISTATE    :bit1;
  DCO_DCIO_DVOCNTL1_EN_PREMUX  :bit1;
  DCO_DCIO_DVOCNTL1_EN         :bit1;
  DCO_DCIO_DVOCNTL1_MUX        :bit1;
  DCO_DCIO_DVOCNTL1_MASK_REG   :bit1;
  DCO_DCIO_DVO_ENABLE          :bit1;
  DCO_DCIO_DVO_VSYNC_TRISTATE  :bit1;
  DCO_DCIO_DVO_RATE_SEL        :bit1;
  DCO_DCIO_DVOCNTL1_SEL0_PREMUX:bit1;
  DCO_DCIO_DVOCNTL1_SEL0       :bit1;
  RESERVED0                    :bit4;
 end;

 TDCIO_DEBUG2=bit32;

 TDCIO_DEBUG3=bit32;

 TDCIO_DEBUG4=bit32;

 TDCIO_DEBUG5=bit32;

 TDCIO_DEBUG6=bit32;

 TDCIO_DEBUG7=bit32;

 TDCIO_DEBUG8=bit32;

 TDCIO_DEBUG9=bit32;

 TDCIO_DEBUGA=bit32;

 TDCIO_DEBUGB=bit32;

 TDCIO_DEBUGC=bit32;

 TDCIO_DEBUGD=bit32;

 TDCIO_DEBUGE=bit32;

 TDCIO_DEBUGF=bit32;

 TDC_GENERICA=bitpacked record
  GENERICA_EN                       :bit1;
  RESERVED0                         :bit6;
  GENERICA_SEL                      :bit5;
  GENERICA_UNIPHY_REFDIV_CLK_SEL    :bit3;
  RESERVED1                         :bit1;
  GENERICA_UNIPHY_FBDIV_CLK_SEL     :bit3;
  RESERVED2                         :bit1;
  GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL :bit3;
  RESERVED3                         :bit1;
  GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL:bit3;
  RESERVED4                         :bit5;
 end;

 TDC_GENERICB=bitpacked record
  GENERICB_EN                       :bit1;
  RESERVED0                         :bit7;
  GENERICB_SEL                      :bit4;
  GENERICB_UNIPHY_REFDIV_CLK_SEL    :bit3;
  RESERVED1                         :bit1;
  GENERICB_UNIPHY_FBDIV_CLK_SEL     :bit3;
  RESERVED2                         :bit1;
  GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL :bit3;
  RESERVED3                         :bit1;
  GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL:bit3;
  RESERVED4                         :bit5;
 end;

 TDC_I2C_DATA=bitpacked record
  DC_I2C_DATA_RW    :bit1;
  RESERVED0         :bit7;
  DC_I2C_DATA       :bit8;
  DC_I2C_INDEX      :bit8;
  RESERVED1         :bit7;
  DC_I2C_INDEX_WRITE:bit1;
 end;

 TDEBUG_INDEX=bitpacked record
  DEBUG_INDEX:bit18;
  RESERVED0  :bit14;
 end;

 TDEVICE_CAP2=bitpacked record
  CPL_TIMEOUT_RANGE_SUPPORTED :bit4;
  CPL_TIMEOUT_DIS_SUPPORTED   :bit1;
  ARI_FORWARDING_SUPPORTED    :bit1;
  ATOMICOP_ROUTING_SUPPORTED  :bit1;
  ATOMICOP_32CMPLT_SUPPORTED  :bit1;
  ATOMICOP_64CMPLT_SUPPORTED  :bit1;
  CAS128_CMPLT_SUPPORTED      :bit1;
  NO_RO_ENABLED_P2P_PASSING   :bit1;
  LTR_SUPPORTED               :bit1;
  TPH_CPLR_SUPPORTED          :bit2;
  RESERVED0                   :bit4;
  OBFF_SUPPORTED              :bit2;
  EXTENDED_FMT_FIELD_SUPPORTED:bit1;
  END_END_TLP_PREFIX_SUPPORTED:bit1;
  MAX_END_END_TLP_PREFIXES    :bit2;
  RESERVED1                   :bit8;
 end;

 TDEVICE_CNTL=bitpacked record
  CORR_ERR_EN          :bit1;
  NON_FATAL_ERR_EN     :bit1;
  FATAL_ERR_EN         :bit1;
  USR_REPORT_EN        :bit1;
  RELAXED_ORD_EN       :bit1;
  MAX_PAYLOAD_SIZE     :bit3;
  EXTENDED_TAG_EN      :bit1;
  PHANTOM_FUNC_EN      :bit1;
  AUX_POWER_PM_EN      :bit1;
  NO_SNOOP_EN          :bit1;
  MAX_READ_REQUEST_SIZE:bit3;
  INITIATE_FLR         :bit1;
  RESERVED0            :bit16;
 end;

 TDIG_BE_CNTL=bitpacked record
  RESERVED0           :bit8;
  DIG_FE_SOURCE_SELECT:bit7;
  RESERVED1           :bit1;
  DIG_MODE            :bit3;
  RESERVED2           :bit9;
  DIG_HPD_SELECT      :bit3;
  RESERVED3           :bit1;
 end;

 TDIG_FE_CNTL=bitpacked record
  DIG_SOURCE_SELECT     :bit3;
  RESERVED0             :bit1;
  DIG_STEREOSYNC_SELECT :bit3;
  RESERVED1             :bit1;
  DIG_STEREOSYNC_GATE_EN:bit1;
  RESERVED2             :bit1;
  DIG_START             :bit1;
  RESERVED3             :bit5;
  DIG_DUAL_LINK_ENABLE  :bit1;
  RESERVED4             :bit1;
  DIG_SWAP              :bit1;
  RESERVED5             :bit1;
  DIG_RB_SWITCH_EN      :bit1;
  RESERVED6             :bit3;
  DIG_SYMCLK_FE_ON      :bit1;
  RESERVED7             :bit7;
 end;

 TDMCU_STATUS=bitpacked record
  UC_IN_RESET    :bit1;
  UC_IN_WAIT_MODE:bit1;
  UC_IN_STOP_MODE:bit1;
  RESERVED0      :bit28;
  RESERVED1      :bit1;
 end;

 TDMIF_P_VMID=bitpacked record
  P_VMID_PIPE0:bit4;
  P_VMID_PIPE1:bit4;
  P_VMID_PIPE2:bit4;
  P_VMID_PIPE3:bit4;
  P_VMID_PIPE4:bit4;
  P_VMID_PIPE5:bit4;
  P_VMID_PIPE6:bit4;
  P_VMID_PIPE7:bit4;
 end;

 TDMIF_STATUS=bitpacked record
  DMIF_MC_SEND_ON_IDLE                  :bit8;
  DMIF_CLEAR_MC_SEND_ON_IDLE            :bit8;
  DMIF_MC_LATENCY_COUNTER_ENABLE        :bit1;
  DMIF_MC_LATENCY_COUNTER_URGENT_ONLY   :bit1;
  RESERVED0                             :bit2;
  DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT :bit3;
  RESERVED1                             :bit1;
  DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT:bit3;
  RESERVED2                             :bit1;
  DMIF_UNDERFLOW                        :bit1;
  RESERVED3                             :bit3;
 end;

 TDPM_TABLE_1=bit32;

 TDPM_TABLE_2=bit32;

 TDPM_TABLE_3=bit32;

 TDPM_TABLE_4=bit32;

 TDPM_TABLE_5=bit32;

 TDPM_TABLE_6=bit32;

 TDPM_TABLE_7=bit32;

 TDPM_TABLE_8=bit32;

 TDPM_TABLE_9=bit32;

 TDP_DPHY_SYM=bitpacked record
  RESERVED0:bit10;
  RESERVED1:bit10;
  RESERVED2:bit12;
 end;

 TDP_MSA_MISC=bitpacked record
  RESERVED0   :bit3;
  DP_MSA_MISC1:bit4;
  RESERVED1   :bit1;
  DP_MSA_MISC2:bit8;
  DP_MSA_MISC3:bit8;
  DP_MSA_MISC4:bit8;
 end;

 TDP_MSE_SAT0=bitpacked record
  DP_MSE_SAT_SRC0       :bit3;
  RESERVED0             :bit1;
  RESERVED1             :bit1;
  RESERVED2             :bit3;
  DP_MSE_SAT_SLOT_COUNT0:bit6;
  RESERVED3             :bit2;
  DP_MSE_SAT_SRC1       :bit3;
  RESERVED4             :bit1;
  RESERVED5             :bit1;
  RESERVED6             :bit3;
  DP_MSE_SAT_SLOT_COUNT1:bit6;
  RESERVED7             :bit2;
 end;

 TDP_MSE_SAT1=bitpacked record
  DP_MSE_SAT_SRC2       :bit3;
  RESERVED0             :bit1;
  RESERVED1             :bit1;
  RESERVED2             :bit3;
  DP_MSE_SAT_SLOT_COUNT2:bit6;
  RESERVED3             :bit2;
  DP_MSE_SAT_SRC3       :bit3;
  RESERVED4             :bit1;
  RESERVED5             :bit1;
  RESERVED6             :bit3;
  DP_MSE_SAT_SLOT_COUNT3:bit6;
  RESERVED7             :bit2;
 end;

 TDP_MSE_SAT2=bitpacked record
  DP_MSE_SAT_SRC4       :bit3;
  RESERVED0             :bit1;
  RESERVED1             :bit1;
  RESERVED2             :bit3;
  DP_MSE_SAT_SLOT_COUNT4:bit6;
  RESERVED3             :bit2;
  DP_MSE_SAT_SRC5       :bit3;
  RESERVED4             :bit1;
  RESERVED5             :bit1;
  RESERVED6             :bit3;
  DP_MSE_SAT_SLOT_COUNT5:bit6;
  RESERVED7             :bit2;
 end;

 TDP_SEC_CNTL=bitpacked record
  DP_SEC_STREAM_ENABLE:bit1;
  RESERVED0           :bit3;
  DP_SEC_ASP_ENABLE   :bit1;
  RESERVED1           :bit3;
  DP_SEC_ATP_ENABLE   :bit1;
  RESERVED2           :bit3;
  DP_SEC_AIP_ENABLE   :bit1;
  RESERVED3           :bit3;
  DP_SEC_ACM_ENABLE   :bit1;
  RESERVED4           :bit3;
  DP_SEC_GSP0_ENABLE  :bit1;
  DP_SEC_GSP1_ENABLE  :bit1;
  DP_SEC_GSP2_ENABLE  :bit1;
  DP_SEC_GSP3_ENABLE  :bit1;
  DP_SEC_AVI_ENABLE   :bit1;
  RESERVED5           :bit3;
  DP_SEC_MPG_ENABLE   :bit1;
  RESERVED6           :bit3;
 end;

 TDVO_CONTROL=bitpacked record
  DVO_RATE_SELECT    :bit1;
  DVO_SDRCLK_SEL     :bit1;
  RESERVED0          :bit2;
  DVO_DVPDATA_WIDTH  :bit2;
  RESERVED1          :bit2;
  DVO_DUAL_CHANNEL_EN:bit1;
  RESERVED2          :bit7;
  DVO_RESET_FIFO     :bit1;
  DVO_SYNC_PHASE     :bit1;
  DVO_INVERT_DVOCLK  :bit1;
  RESERVED3          :bit1;
  DVO_HSYNC_POLARITY :bit1;
  DVO_VSYNC_POLARITY :bit1;
  DVO_DE_POLARITY    :bit1;
  RESERVED4          :bit1;
  DVO_COLOR_FORMAT   :bit2;
  RESERVED5          :bit5;
  DVO_CTL3           :bit1;
 end;

 TFMT_CONTROL=bitpacked record
  FMT_STEREOSYNC_OVERRIDE                  :bit1;
  RESERVED0                                :bit3;
  FMT_STEREOSYNC_OVR_POL                   :bit1;
  RESERVED1                                :bit3;
  FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX     :bit4;
  FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP:bit2;
  RESERVED2                                :bit2;
  FMT_PIXEL_ENCODING                       :bit1;
  FMT_SUBSAMPLING_MODE                     :bit1;
  FMT_SUBSAMPLING_ORDER                    :bit1;
  RESERVED3                                :bit5;
  FMT_SRC_SELECT                           :bit3;
  RESERVED4                                :bit5;
 end;

 TGB_EDC_MODE=bitpacked record
  RESERVED0       :bit16;
  FORCE_SEC_ON_DED:bit1;
  RESERVED1       :bit3;
  DED_MODE        :bit2;
  RESERVED2       :bit7;
  PROP_FED        :bit1;
  RESERVED3       :bit1;
  BYPASS          :bit1;
 end;

 TGDS_ATOM_OP=bitpacked record
  OP    :bit8;
  UNUSED:bit24;
 end;

 TGDS_EDC_CNT=bitpacked record
  DED      :bit8;
  SED      :bit8;
  SEC      :bit8;
  RESERVED0:bit8;
 end;

 TGDS_ENHANCE=bitpacked record
  MISC          :bit16;
  AUTO_INC_INDEX:bit1;
  CGPG_RESTORE  :bit1;
  RESERVED0     :bit14;
 end;

 TGDS_OA_CNTL=bitpacked record
  INDEX    :bit4;
  RESERVED0:bit28;
 end;

 TGDS_RD_ADDR=bit32;

 TGDS_RD_DATA=bit32;

 TGDS_WR_ADDR=bit32;

 TGDS_WR_DATA=bit32;

 TGMCON_DEBUG=bitpacked record
  GFX_STALL            :bit1;
  GFX_CLEAR            :bit1;
  GMCON_DEBUG_RESERVED0:bit1;
  SR_COMMIT_STATE      :bit1;
  STCTRL_ST            :bit4;
  MISC_FLAGS           :bit24;
 end;

 TGMCON_MISC2=bitpacked record
  GMCON_MISC2_RESERVED0        :bit6;
  STCTRL_NONDISP_IDLE_THRESHOLD:bit5;
  RENG_SR_HOLD_THRESHOLD       :bit6;
  GMCON_MISC2_RESERVED1        :bit12;
  STCTRL_IGNORE_ARB_BUSY       :bit1;
  STCTRL_EXTEND_GMC_OFFLINE    :bit1;
  STCTRL_TIMER_PULSE_OVERRIDE  :bit1;
 end;

 TGMCON_MISC3=bitpacked record
  RENG_DISABLE_MCC             :bit8;
  RENG_DISABLE_MCD             :bit8;
  STCTRL_FORCE_PGFSM_CMD_DONE  :bit12;
  STCTRL_IGNORE_ALLOW_STUTTER  :bit1;
  RENG_MEM_LS_ENABLE           :bit1;
  STCTRL_EXCLUDE_NONMEM_CLIENTS:bit1;
  RESERVED0                    :bit1;
 end;

 TGRBM_STATUS=bitpacked record
  ME0PIPE0_CMDFIFO_AVAIL:bit4;
  RESERVED0             :bit1;
  SRBM_RQ_PENDING       :bit1;
  RESERVED1             :bit1;
  ME0PIPE0_CF_RQ_PENDING:bit1;
  ME0PIPE0_PF_RQ_PENDING:bit1;
  GDS_DMA_RQ_PENDING    :bit1;
  RESERVED2             :bit2;
  DB_CLEAN              :bit1;
  CB_CLEAN              :bit1;
  TA_BUSY               :bit1;
  GDS_BUSY              :bit1;
  WD_BUSY_NO_DMA        :bit1;
  VGT_BUSY              :bit1;
  IA_BUSY_NO_DMA        :bit1;
  IA_BUSY               :bit1;
  SX_BUSY               :bit1;
  WD_BUSY               :bit1;
  SPI_BUSY              :bit1;
  BCI_BUSY              :bit1;
  SC_BUSY               :bit1;
  PA_BUSY               :bit1;
  DB_BUSY               :bit1;
  RESERVED3             :bit1;
  CP_COHERENCY_BUSY     :bit1;
  CP_BUSY               :bit1;
  CB_BUSY               :bit1;
  GUI_ACTIVE            :bit1;
 end;

 TGRPH_ENABLE=bitpacked record
  GRPH_ENABLE:bit1;
  RESERVED0  :bit31;
 end;

 TGRPH_UPDATE=bitpacked record
  GRPH_MODE_UPDATE_PENDING            :bit1;
  GRPH_MODE_UPDATE_TAKEN              :bit1;
  GRPH_SURFACE_UPDATE_PENDING         :bit1;
  GRPH_SURFACE_UPDATE_TAKEN           :bit1;
  RESERVED0                           :bit4;
  GRPH_SURFACE_XDMA_PENDING_ENABLE    :bit1;
  RESERVED1                           :bit7;
  GRPH_UPDATE_LOCK                    :bit1;
  RESERVED2                           :bit3;
  GRPH_SURFACE_IGNORE_UPDATE_LOCK     :bit1;
  RESERVED3                           :bit3;
  GRPH_MODE_DISABLE_MULTIPLE_UPDATE   :bit1;
  RESERVED4                           :bit3;
  GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE:bit1;
  RESERVED5                           :bit3;
 end;

 THDMI_STATUS=bitpacked record
  HDMI_ACTIVE_AVMUTE     :bit1;
  RESERVED0              :bit15;
  HDMI_AUDIO_PACKET_ERROR:bit1;
  RESERVED1              :bit3;
  HDMI_VBI_PACKET_ERROR  :bit1;
  RESERVED2              :bit6;
  HDMI_ERROR_INT         :bit1;
  RESERVED3              :bit4;
 end;

 THOST_BUSNUM=bitpacked record
  HOST_ID  :bit16;
  RESERVED0:bit16;
 end;

 THW_ROTATION=bitpacked record
  GRPH_ROTATION_ANGLE:bit3;
  RESERVED0          :bit29;
 end;

 TKEY_CONTROL=bitpacked record
  KEY_SELECT         :bit1;
  KEY_MODE           :bit2;
  RESERVED0          :bit25;
  GRPH_OVL_HALF_BLEND:bit1;
  RESERVED1          :bit3;
 end;

 TLINK_STATUS=bitpacked record
  CURRENT_LINK_SPEED       :bit4;
  NEGOTIATED_LINK_WIDTH    :bit6;
  RESERVED0                :bit1;
  LINK_TRAINING            :bit1;
  SLOT_CLOCK_CFG           :bit1;
  DL_ACTIVE                :bit1;
  LINK_BW_MANAGEMENT_STATUS:bit1;
  LINK_AUTONOMOUS_BW_STATUS:bit1;
  RESERVED1                :bit16;
 end;

 TLNC_BW_WACC=bit32;

 TMAX_LATENCY=bitpacked record
  MAX_LAT  :bit8;
  RESERVED0:bit24;
 end;

 TMC_ARB_GRUB=bitpacked record
  GRUB_WATERMARK    :bit8;
  GRUB_WATERMARK_PRI:bit8;
  GRUB_WATERMARK_MED:bit8;
  REG_WR_EN         :bit2;
  REG_RD_SEL        :bit1;
  RESERVED0         :bit5;
 end;

 TMC_ARB_MISC=bitpacked record
  STICKY_RFSH     :bit1;
  IDLE_RFSH       :bit1;
  STUTTER_RFSH    :bit1;
  CHAN_COUPLE     :bit8;
  HARSHNESS       :bit8;
  SMART_RDWR_SW   :bit1;
  CALI_ENABLE     :bit1;
  CALI_RATES      :bit2;
  DISPURGVLD_NOWRT:bit1;
  DISPURG_NOSW2WR :bit1;
  DISPURG_STALL   :bit1;
  DISPURG_THROTTLE:bit4;
  EXTEND_WEIGHT   :bit1;
  ACPURG_STALL    :bit1;
 end;

 TMC_BIST_CMD=bitpacked record
  RESERVED0 :bit3;
  RESERVED1 :bit1;
  RESERVED2 :bit4;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit2;
  RESERVED8 :bit2;
  RESERVED9 :bit2;
  RESERVED10:bit14;
 end;

 TMC_BIST_DAT=bitpacked record
  RESERVED0:bit4;
  RESERVED1:bit4;
  RESERVED2:bit1;
  RESERVED3:bit1;
  RESERVED4:bit3;
  RESERVED5:bit12;
  RESERVED6:bit7;
 end;

 TMC_RPB_CONF=bitpacked record
  RESERVED0        :bit15;
  XPB_PCIE_ORDER   :bit1;
  RPB_RD_PCIE_ORDER:bit1;
  RPB_WR_PCIE_ORDER:bit1;
  RESERVED1        :bit14;
 end;

 TMC_RPB_DBG1=bitpacked record
  RPB_BIF_OUTSTANDING_RD    :bit8;
  RPB_BIF_OUTSTANDING_RD_32B:bit12;
  DEBUG_BITS                :bit12;
 end;

 TMC_SEQ_CNTL=bitpacked record
  CHANNEL_DISABLE:bit4;
  SAFE_MODE      :bit2;
  DAT_INV        :bit1;
  RET_HOLD_EOP   :bit1;
  BANKGROUP_SIZE :bit1;
  BANKGROUP_ENB  :bit1;
  MSKOFF_DAT_TL  :bit1;
  MSKOFF_DAT_TH  :bit1;
  ARB_REQCMD_WMK :bit4;
  ARB_REQDAT_WMK :bit4;
  ARB_RTDAT_WMK  :bit6;
  RESERVED0      :bit1;
  RESERVED1      :bit1;
  RESERVED2      :bit1;
  RESERVED3      :bit1;
  RESERVED4      :bit1;
  RTR_OVERRIDE   :bit1;
 end;

 TMC_SEQ_DRAM=bitpacked record
  STB_CNT   :bit4;
  CKE_DYN   :bit1;
  CKE_ACT   :bit1;
  DAT_INV   :bit1;
  INV_ACM   :bit1;
  RST_CTL   :bit1;
  RESERVED0 :bit1;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  DQM_ACT   :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit3;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit1;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit8;
 end;

 TMC_XBAR_ARB=bitpacked record
  HUBRD_HIGHEST            :bit1;
  DISABLE_HUB_STALL_HIGHEST:bit1;
  BREAK_BURST_CID_CHANGE   :bit1;
  ACP_RDRET_URG            :bit1;
  HDP_RDRET_URG            :bit1;
  BREAK_BURST_BY_URG       :bit1;
  RESERVED0                :bit26;
 end;

 TMM_INDEX_HI=bit32;

 TMP_INT_STAT=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit1;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit1;
  RESERVED13:bit1;
  RESERVED14:bit1;
  RESERVED15:bit1;
  RESERVED16:bit1;
  RESERVED17:bit1;
  RESERVED18:bit1;
  RESERVED19:bit1;
  RESERVED20:bit1;
  RESERVED21:bit1;
  RESERVED22:bit1;
  RESERVED23:bit1;
  RESERVED24:bit8;
 end;

 TMSI_MASK_64=bit32;

 TMSI_PENDING=bit32;

 TPCIE_DATA_2=bit32;

 TPCIE_EFUSE2=bit32;

 TPCIE_EFUSE3=bit32;

 TPCIE_EFUSE4=bit32;

 TPCIE_EFUSE5=bit32;

 TPCIE_EFUSE6=bitpacked record
  RESERVED0                        :bit1;
  STRAP_BIF_F0_SUPPORTED_PAGE_SIZES:bit16;
  SPARE_15_PCIEFUSE6               :bit15;
 end;

 TPCIE_EFUSE7=bitpacked record
  RESERVED0                      :bit1;
  STRAP_BIF_F0_SRIOV_VF_DEVICE_ID:bit16;
  SPARE_15_PCIEFUSE7             :bit15;
 end;

 TPCIE_FC_CPL=bitpacked record
  CPLD_CREDITS:bit8;
  CPLH_CREDITS:bit8;
  RESERVED0   :bit16;
 end;

 TPCIE_MC_CAP=bitpacked record
  MC_MAX_GROUP      :bit6;
  RESERVED0         :bit2;
  MC_WIN_SIZE_REQ   :bit6;
  RESERVED1         :bit1;
  MC_ECRC_REGEN_SUPP:bit1;
  RESERVED2         :bit16;
 end;

 TPCIE_P_CNTL=bitpacked record
  P_PWRDN_EN             :bit1;
  P_SYMALIGN_MODE        :bit1;
  P_SYMALIGN_HW_DEBUG    :bit1;
  P_ELASTDESKEW_HW_DEBUG :bit1;
  P_IGNORE_CRC_ERR       :bit1;
  P_IGNORE_LEN_ERR       :bit1;
  P_IGNORE_EDB_ERR       :bit1;
  P_IGNORE_IDL_ERR       :bit1;
  P_IGNORE_TOK_ERR       :bit1;
  RESERVED0              :bit3;
  P_BLK_LOCK_MODE        :bit1;
  P_ALWAYS_USE_FAST_TXCLK:bit1;
  P_ELEC_IDLE_MODE       :bit2;
  DLP_IGNORE_IN_L1_EN    :bit1;
  RESERVED1              :bit15;
 end;

 TPCIE_TX_SEQ=bitpacked record
  TX_NEXT_TRANSMIT_SEQ:bit12;
  RESERVED0           :bit4;
  TX_ACKD_SEQ         :bit12;
  RESERVED1           :bit4;
 end;

 TPERFMON_LOW=bit32;

 TPLL_DS_CNTL=bitpacked record
  PLL_DS_FRAC   :bit16;
  PLL_DS_ORDER  :bit2;
  PLL_DS_MODE   :bit1;
  PLL_DS_PRBS_EN:bit1;
  RESERVED0     :bit12;
 end;

 TPLL_REF_DIV=bitpacked record
  PLL_REF_DIV            :bit10;
  RESERVED0              :bit2;
  PLL_CALIBRATION_REF_DIV:bit4;
  RESERVED1              :bit16;
 end;

 TPLL_SS_CNTL=bitpacked record
  PLL_SS_AMOUNT_FBDIV     :bit8;
  PLL_SS_AMOUNT_NFRAC_SLIP:bit4;
  PLL_SS_EN               :bit1;
  PLL_SS_MODE             :bit1;
  RESERVED0               :bit2;
  PLL_SS_STEP_SIZE_DSFRAC :bit16;
 end;

 TPM_FUSES_10=bitpacked record
  GnbLPML_3:bit8;
  GnbLPML_2:bit8;
  GnbLPML_1:bit8;
  GnbLPML_0:bit8;
 end;

 TPM_FUSES_11=bitpacked record
  GnbLPML_7:bit8;
  GnbLPML_6:bit8;
  GnbLPML_5:bit8;
  GnbLPML_4:bit8;
 end;

 TPM_FUSES_12=bitpacked record
  GnbLPML_11:bit8;
  GnbLPML_10:bit8;
  GnbLPML_9 :bit8;
  GnbLPML_8 :bit8;
 end;

 TPM_FUSES_13=bitpacked record
  GnbLPML_15:bit8;
  GnbLPML_14:bit8;
  GnbLPML_13:bit8;
  GnbLPML_12:bit8;
 end;

 TPM_FUSES_14=bitpacked record
  Reserved1_1  :bit8;
  Reserved1_0  :bit8;
  GnbLPMLMinVid:bit8;
  GnbLPMLMaxVid:bit8;
 end;

 TPM_FUSES_15=bitpacked record
  BapmVddCBaseLeakageLoSidd:bit16;
  BapmVddCBaseLeakageHiSidd:bit16;
 end;

 TPPLL_SPARE0=bit32;

 TPPLL_SPARE1=bit32;

 TREFCLK_CNTL=bitpacked record
  REFCLK_CLOCK_EN:bit1;
  REFCLK_SRC_SEL :bit1;
  RESERVED0      :bit30;
 end;

 TREVISION_ID=bitpacked record
  MINOR_REV_ID:bit4;
  MAJOR_REV_ID:bit4;
  RESERVED0   :bit24;
 end;

 TRIRB_STATUS=bitpacked record
  RESPONSE_INTERRUPT               :bit1;
  RESERVED0                        :bit1;
  RESPONSE_OVERRUN_INTERRUPT_STATUS:bit1;
  RESERVED1                        :bit29;
 end;

 TRLC_LB_CNTL=bitpacked record
  LOAD_BALANCE_ENABLE  :bit1;
  LB_CNT_CP_BUSY       :bit1;
  LB_CNT_SPIM_ACTIVE   :bit1;
  LB_CNT_REG_INC       :bit1;
  CU_MASK_USED_OFF_HYST:bit8;
  RESERVED0            :bit20;
 end;

 TRLC_MC_CNTL=bitpacked record
  WRREQ_SWAP    :bit2;
  WRREQ_TRAN    :bit1;
  WRREQ_PRIV    :bit1;
  WRNFO_STALL   :bit1;
  WRNFO_URG     :bit4;
  WRREQ_DW_IMASK:bit4;
  RESERVED_B    :bit7;
  RDNFO_URG     :bit4;
  RDREQ_SWAP    :bit2;
  RDREQ_TRAN    :bit1;
  RDREQ_PRIV    :bit1;
  RDNFO_STALL   :bit1;
  RESERVED      :bit3;
 end;

 TRLC_PG_CNTL=bitpacked record
  GFX_POWER_GATING_ENABLE      :bit1;
  GFX_POWER_GATING_SRC         :bit1;
  DYN_PER_CU_PG_ENABLE         :bit1;
  STATIC_PER_CU_PG_ENABLE      :bit1;
  GFX_PIPELINE_PG_ENABLE       :bit1;
  RESERVED                     :bit9;
  PG_OVERRIDE                  :bit1;
  CP_PG_DISABLE                :bit1;
  CHUB_HANDSHAKE_ENABLE        :bit1;
  SMU_CLK_SLOWDOWN_ON_PU_ENABLE:bit1;
  SMU_CLK_SLOWDOWN_ON_PD_ENABLE:bit1;
  SMU_HANDSHAKE_ENABLE         :bit1;
  RESERVED1                    :bit4;
  PG_ERROR_STATUS              :bit8;
 end;

 TROM_SW_CNTL=bitpacked record
  DATA_SIZE                :bit16;
  COMMAND_SIZE             :bit2;
  ROM_SW_RETURN_DATA_ENABLE:bit1;
  RESERVED0                :bit13;
 end;

 TSCLV_DEBUG2=bitpacked record
  SCL_DEBUG_REQ_MODE:bit1;
  SCL_DEBUG_EOF_MODE:bit2;
  SCL_DEBUG2        :bit29;
 end;

 TSCLV_UPDATE=bitpacked record
  SCL_UPDATE_PENDING      :bit1;
  RESERVED0               :bit7;
  SCL_UPDATE_TAKEN        :bit1;
  RESERVED1               :bit7;
  SCL_UPDATE_LOCK         :bit1;
  RESERVED2               :bit7;
  SCL_COEF_UPDATE_COMPLETE:bit1;
  RESERVED3               :bit7;
 end;

 TSCL_CONTROL=bitpacked record
  SCL_BOUNDARY_MODE :bit1;
  RESERVED0         :bit3;
  SCL_EARLY_EOL_MODE:bit1;
  RESERVED1         :bit27;
 end;

 TSDMA_CONFIG=bitpacked record
  RESERVED0     :bit8;
  SDMA_RDREQ_URG:bit4;
  RESERVED1     :bit4;
  SDMA_REQ_TRAN :bit1;
  RESERVED2     :bit15;
 end;

 TSEM_MAILBOX=bitpacked record
  SIDEPORT      :bit8;
  HOSTPORT      :bit8;
  SIDEPORT_EXTRA:bit8;
  HOSTPORT_EXTRA:bit8;
 end;

 TSMC_RESP_10=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMC_RESP_11=bitpacked record
  SMC_RESP :bit16;
  RESERVED0:bit16;
 end;

 TSMU_CONTROL=bitpacked record
  DISPLAY0_FORCE_VBI  :bit1;
  DISPLAY1_FORCE_VBI  :bit1;
  DISPLAY2_FORCE_VBI  :bit1;
  DISPLAY3_FORCE_VBI  :bit1;
  DISPLAY4_FORCE_VBI  :bit1;
  DISPLAY5_FORCE_VBI  :bit1;
  DISPLAY_V0_FORCE_VBI:bit1;
  RESERVED0           :bit9;
  SMU_DC_INT_CLEAR    :bit1;
  RESERVED1           :bit15;
 end;

 TSMU_EFUSE_0=bit32;

 TSM_CONTROL2=bitpacked record
  SM_MODE                :bit3;
  RESERVED0              :bit1;
  SM_FRAME_ALTERNATE     :bit1;
  SM_FIELD_ALTERNATE     :bit1;
  RESERVED1              :bit2;
  SM_FORCE_NEXT_FRAME_POL:bit2;
  RESERVED2              :bit6;
  SM_FORCE_NEXT_TOP_POL  :bit2;
  RESERVED3              :bit6;
  SM_CURRENT_FRAME_POL   :bit1;
  RESERVED4              :bit7;
 end;

 TSPI_EDC_CNT=bitpacked record
  SED      :bit8;
  RESERVED0:bit24;
 end;

 TSPMI_PATH_0=bitpacked record
  PATH_ENABLE_REQ           :bit1;
  PATH_ENABLE_ACK           :bit1;
  RESERVED0                 :bit2;
  PATH_ENABLE_REQ_auto_clear:bit1;
  RESERVED1                 :bit27;
 end;

 TSQC_EDC_CNT=bitpacked record
  INST_SEC:bit8;
  INST_DED:bit8;
  DATA_SEC:bit8;
  DATA_DED:bit8;
 end;

 TSQ_DSM_CNTL=bitpacked record
  WAVEFRONT_STALL_0           :bit1;
  WAVEFRONT_STALL_1           :bit1;
  SPI_BACKPRESSURE_0          :bit1;
  SPI_BACKPRESSURE_1          :bit1;
  RESERVED0                   :bit4;
  SEL_DSM_SGPR_IRRITATOR_DATA0:bit1;
  SEL_DSM_SGPR_IRRITATOR_DATA1:bit1;
  SGPR_ENABLE_SINGLE_WRITE    :bit1;
  RESERVED1                   :bit5;
  SEL_DSM_LDS_IRRITATOR_DATA0 :bit1;
  SEL_DSM_LDS_IRRITATOR_DATA1 :bit1;
  LDS_ENABLE_SINGLE_WRITE01   :bit1;
  SEL_DSM_LDS_IRRITATOR_DATA2 :bit1;
  SEL_DSM_LDS_IRRITATOR_DATA3 :bit1;
  LDS_ENABLE_SINGLE_WRITE23   :bit1;
  RESERVED2                   :bit2;
  SEL_DSM_SP_IRRITATOR_DATA0  :bit1;
  SEL_DSM_SP_IRRITATOR_DATA1  :bit1;
  SP_ENABLE_SINGLE_WRITE      :bit1;
  RESERVED3                   :bit5;
 end;

 TSQ_EDC_INFO=bitpacked record
  WAVE_ID  :bit4;
  SIMD_ID  :bit2;
  SOURCE   :bit3;
  VM_ID    :bit4;
  RESERVED0:bit19;
 end;

 TSQ_IND_DATA=bit32;

 TSQ_VOP_SDWA=bitpacked record
  SRC0      :bit8;
  DST_SEL   :bit3;
  DST_UNUSED:bit2;
  CLAMP     :bit1;
  RESERVED0 :bit2;
  SRC0_SEL  :bit3;
  SRC0_SEXT :bit1;
  SRC0_NEG  :bit1;
  SRC0_ABS  :bit1;
  RESERVED1 :bit2;
  SRC1_SEL  :bit3;
  SRC1_SEXT :bit1;
  SRC1_NEG  :bit1;
  SRC1_ABS  :bit1;
  RESERVED2 :bit2;
 end;

 TSRBM_STATUS=bitpacked record
  RESERVED0           :bit1;
  UVD_RQ_PENDING      :bit1;
  SAMMSP_RQ_PENDING   :bit1;
  ACP_RQ_PENDING      :bit1;
  SMU_RQ_PENDING      :bit1;
  GRBM_RQ_PENDING     :bit1;
  HI_RQ_PENDING       :bit1;
  RESERVED1           :bit1;
  VMC_BUSY            :bit1;
  MCB_BUSY            :bit1;
  MCB_NON_DISPLAY_BUSY:bit1;
  MCC_BUSY            :bit1;
  MCD_BUSY            :bit1;
  VMC1_BUSY           :bit1;
  SEM_BUSY            :bit1;
  RESERVED2           :bit1;
  ACP_BUSY            :bit1;
  IH_BUSY             :bit1;
  RESERVED3           :bit1;
  UVD_BUSY            :bit1;
  SAMMSP_BUSY         :bit1;
  GCATCL2_BUSY        :bit1;
  OSATCL2_BUSY        :bit1;
  RESERVED4           :bit6;
  BIF_BUSY            :bit1;
  RESERVED5           :bit2;
 end;

 TTA_CNTL_AUX=bitpacked record
  SCOAL_DSWIZZLE_N  :bit1;
  RESERVED          :bit3;
  D16_PACK_DISABLE  :bit1;
  RESERVED0         :bit11;
  ANISO_WEIGHT_MODE :bit1;
  ANISO_RATIO_LUT   :bit1;
  ANISO_TAP         :bit1;
  ANISO_MIP_ADJ_MODE:bit1;
  RESERVED1         :bit12;
 end;

 TTCC_EDC_CNT=bitpacked record
  SEC_COUNT:bit8;
  RESERVED0:bit8;
  DED_COUNT:bit8;
  RESERVED1:bit8;
 end;

 TTCP_EDC_CNT=bitpacked record
  SEC_COUNT      :bit8;
  LFIFO_SED_COUNT:bit8;
  DED_COUNT      :bit8;
  UNUSED         :bit8;
 end;

 TTD_DSM_CNTL=bitpacked record
  FORCE_SEDB_0     :bit1;
  FORCE_SEDB_1     :bit1;
  EN_SINGLE_WR_SEDB:bit1;
  RESERVED0        :bit29;
 end;

 TVCE_RB_RPTR=bitpacked record
  RESERVED0:bit4;
  RB_RPTR  :bit19;
  RESERVED1:bit9;
 end;

 TVCE_RB_SIZE=bitpacked record
  RESERVED0:bit4;
  RB_SIZE  :bit19;
  RESERVED1:bit9;
 end;

 TVCE_RB_WPTR=bitpacked record
  RESERVED0:bit4;
  RB_WPTR  :bit19;
  RESERVED1:bit9;
 end;

 TVGT_ENHANCE=bit32;

 TVGT_GS_MODE=bitpacked record
  MODE              :bit3;
  RESERVED_0        :bit1;
  CUT_MODE          :bit2;
  RESERVED_1        :bit5;
  GS_C_PACK_EN      :bit1;
  RESERVED_2        :bit1;
  ES_PASSTHRU       :bit1;
  COMPUTE_MODE      :bit1;
  FAST_COMPUTE_MODE :bit1;
  ELEMENT_INFO_EN   :bit1;
  PARTIAL_THD_AT_EOI:bit1;
  SUPPRESS_CUTS     :bit1;
  ES_WRITE_OPTIMIZE :bit1;
  GS_WRITE_OPTIMIZE :bit1;
  ONCHIP            :bit2;
  RESERVED0         :bit9;
 end;

 TVM_L2_CNTL2=bitpacked record
  INVALIDATE_ALL_L1_TLBS         :bit1;
  INVALIDATE_L2_CACHE            :bit1;
  RESERVED0                      :bit19;
  DISABLE_INVALIDATE_PER_DOMAIN  :bit1;
  DISABLE_BIGK_CACHE_OPTIMIZATION:bit1;
  L2_CACHE_BIGK_VMID_MODE        :bit3;
  INVALIDATE_CACHE_MODE          :bit2;
  PDE_CACHE_EFFECTIVE_SIZE       :bit3;
  RESERVED1                      :bit1;
 end;

 TVM_L2_CNTL3=bitpacked record
  BANK_SELECT                             :bit6;
  L2_CACHE_UPDATE_MODE                    :bit2;
  L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE:bit5;
  RESERVED0                               :bit2;
  L2_CACHE_BIGK_FRAGMENT_SIZE             :bit5;
  L2_CACHE_BIGK_ASSOCIATIVITY             :bit1;
  L2_CACHE_4K_EFFECTIVE_SIZE              :bit3;
  L2_CACHE_BIGK_EFFECTIVE_SIZE            :bit4;
  L2_CACHE_4K_FORCE_MISS                  :bit1;
  L2_CACHE_BIGK_FORCE_MISS                :bit1;
  PDE_CACHE_FORCE_MISS                    :bit1;
  L2_CACHE_4K_ASSOCIATIVITY               :bit1;
 end;

 TVM_L2_CNTL4=bitpacked record
  L2_CACHE_4K_PARTITION_COUNT:bit6;
  RESERVED0                  :bit1;
  RESERVED1                  :bit1;
  RESERVED2                  :bit1;
  RESERVED3                  :bit1;
  RESERVED4                  :bit1;
  RESERVED5                  :bit1;
  RESERVED6                  :bit20;
 end;

 TVM_PRT_CNTL=bitpacked record
  CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS :bit1;
  TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS :bit1;
  L2_CACHE_STORE_INVALID_ENTRIES           :bit1;
  L1_TLB_STORE_INVALID_ENTRIES             :bit1;
  CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS:bit1;
  TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS:bit1;
  MASK_PDE0_FAULT                          :bit1;
  RESERVED0                                :bit25;
 end;

 TWAKE_ENABLE=bitpacked record
  SDIN_WAKE_ENABLE_FLAG:bit1;
  RESERVED0            :bit31;
 end;

 TWB_DBG_MODE=bitpacked record
  WB_DBG_MODE_EN      :bit1;
  WB_DBG_DIN_FMT      :bit1;
  WB_DBG_36MODE       :bit1;
  WB_DBG_CMAP         :bit1;
  RESERVED0           :bit4;
  WB_DBG_PXLRATE_ERROR:bit1;
  RESERVED1           :bit7;
  WB_DBG_SOURCE_WIDTH :bit15;
  RESERVED2           :bit1;
 end;

 TWB_HW_DEBUG=bit32;

 TADAPTER_ID_W=bitpacked record
  SUBSYSTEM_VENDOR_ID:bit16;
  SUBSYSTEM_ID       :bit16;
 end;

 TAFMT_60958_0=bitpacked record
  AFMT_60958_CS_A                 :bit1;
  AFMT_60958_CS_B                 :bit1;
  AFMT_60958_CS_C                 :bit1;
  AFMT_60958_CS_D                 :bit3;
  AFMT_60958_CS_MODE              :bit2;
  AFMT_60958_CS_CATEGORY_CODE     :bit8;
  AFMT_60958_CS_SOURCE_NUMBER     :bit4;
  AFMT_60958_CS_CHANNEL_NUMBER_L  :bit4;
  AFMT_60958_CS_SAMPLING_FREQUENCY:bit4;
  AFMT_60958_CS_CLOCK_ACCURACY    :bit2;
  RESERVED0                       :bit2;
 end;

 TAFMT_60958_1=bitpacked record
  AFMT_60958_CS_WORD_LENGTH                :bit4;
  AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY:bit4;
  RESERVED0                                :bit8;
  AFMT_60958_VALID_L                       :bit1;
  RESERVED1                                :bit1;
  AFMT_60958_VALID_R                       :bit1;
  RESERVED2                                :bit1;
  AFMT_60958_CS_CHANNEL_NUMBER_R           :bit4;
  RESERVED3                                :bit8;
 end;

 TAFMT_60958_2=bitpacked record
  AFMT_60958_CS_CHANNEL_NUMBER_2:bit4;
  AFMT_60958_CS_CHANNEL_NUMBER_3:bit4;
  AFMT_60958_CS_CHANNEL_NUMBER_4:bit4;
  AFMT_60958_CS_CHANNEL_NUMBER_5:bit4;
  AFMT_60958_CS_CHANNEL_NUMBER_6:bit4;
  AFMT_60958_CS_CHANNEL_NUMBER_7:bit4;
  RESERVED0                     :bit8;
 end;

 TAFMT_ISRC1_0=bitpacked record
  AFMT_ISRC_STATUS  :bit3;
  RESERVED0         :bit3;
  AFMT_ISRC_CONTINUE:bit1;
  AFMT_ISRC_VALID   :bit1;
  RESERVED1         :bit24;
 end;

 TAFMT_ISRC1_1=bitpacked record
  AFMT_UPC_EAN_ISRC0:bit8;
  AFMT_UPC_EAN_ISRC1:bit8;
  AFMT_UPC_EAN_ISRC2:bit8;
  AFMT_UPC_EAN_ISRC3:bit8;
 end;

 TAFMT_ISRC1_2=bitpacked record
  AFMT_UPC_EAN_ISRC4:bit8;
  AFMT_UPC_EAN_ISRC5:bit8;
  AFMT_UPC_EAN_ISRC6:bit8;
  AFMT_UPC_EAN_ISRC7:bit8;
 end;

 TAFMT_ISRC1_3=bitpacked record
  AFMT_UPC_EAN_ISRC8 :bit8;
  AFMT_UPC_EAN_ISRC9 :bit8;
  AFMT_UPC_EAN_ISRC10:bit8;
  AFMT_UPC_EAN_ISRC11:bit8;
 end;

 TAFMT_ISRC1_4=bitpacked record
  AFMT_UPC_EAN_ISRC12:bit8;
  AFMT_UPC_EAN_ISRC13:bit8;
  AFMT_UPC_EAN_ISRC14:bit8;
  AFMT_UPC_EAN_ISRC15:bit8;
 end;

 TAFMT_ISRC2_0=bitpacked record
  AFMT_UPC_EAN_ISRC16:bit8;
  AFMT_UPC_EAN_ISRC17:bit8;
  AFMT_UPC_EAN_ISRC18:bit8;
  AFMT_UPC_EAN_ISRC19:bit8;
 end;

 TAFMT_ISRC2_1=bitpacked record
  AFMT_UPC_EAN_ISRC20:bit8;
  AFMT_UPC_EAN_ISRC21:bit8;
  AFMT_UPC_EAN_ISRC22:bit8;
  AFMT_UPC_EAN_ISRC23:bit8;
 end;

 TAFMT_ISRC2_2=bitpacked record
  AFMT_UPC_EAN_ISRC24:bit8;
  AFMT_UPC_EAN_ISRC25:bit8;
  AFMT_UPC_EAN_ISRC26:bit8;
  AFMT_UPC_EAN_ISRC27:bit8;
 end;

 TAFMT_ISRC2_3=bitpacked record
  AFMT_UPC_EAN_ISRC28:bit8;
  AFMT_UPC_EAN_ISRC29:bit8;
  AFMT_UPC_EAN_ISRC30:bit8;
  AFMT_UPC_EAN_ISRC31:bit8;
 end;

 TATC_ATS_CNTL=bitpacked record
  DISABLE_ATC    :bit1;
  DISABLE_PRI    :bit1;
  DISABLE_PASID  :bit1;
  RESERVED0      :bit5;
  CREDITS_ATS_RPB:bit6;
  RESERVED1      :bit2;
  DEBUG_ECO      :bit4;
  RESERVED2      :bit12;
 end;

 TATC_L2_CNTL2=bitpacked record
  BANK_SELECT                             :bit6;
  L2_CACHE_UPDATE_MODE                    :bit2;
  ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE     :bit1;
  L2_CACHE_SWAP_TAG_INDEX_LSBS            :bit3;
  L2_CACHE_VMID_MODE                      :bit3;
  L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE:bit6;
  RESERVED0                               :bit11;
 end;

 TATC_L2_CNTL3=bitpacked record
  ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING          :bit7;
  ENABLE_FREE_COUNTER                                 :bit1;
  L2_CACHE_EVICTION_THRESHOLD                         :bit5;
  DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION:bit1;
  L2_DELAY_SEND_INVALIDATION_REQUEST                  :bit3;
  RESERVED0                                           :bit15;
 end;

 TATC_L2_DEBUG=bitpacked record
  CREDITS_L2_ATS                :bit6;
  RESERVED0                     :bit1;
  L2_MEM_SELECT                 :bit1;
  CACHE_INDEX                   :bit12;
  RESERVED1                     :bit4;
  CACHE_SELECT                  :bit1;
  CACHE_BANK_SELECT             :bit1;
  RESERVED2                     :bit1;
  CACHE_WAY_SELECT              :bit1;
  RESERVED3                     :bit1;
  CACHE_READ                    :bit1;
  CACHE_INJECT_SOFT_PARITY_ERROR:bit1;
  CACHE_INJECT_HARD_PARITY_ERROR:bit1;
 end;

 TAZALIA_DEBUG=bit32;

 TBIF_CLK_CTRL=bitpacked record
  BIF_XSTCLK_READY         :bit1;
  BACO_XSTCLK_SWITCH_BYPASS:bit1;
  RESERVED0                :bit30;
 end;

 TBIF_SCRATCH0=bit32;

 TBIF_SCRATCH1=bit32;

 TBIF_SMU_DATA=bitpacked record
  RESERVED0   :bit2;
  BIF_SMU_DATA:bit17;
  RESERVED1   :bit13;
 end;

 TBLND_CONTROL=bitpacked record
  BLND_GLOBAL_GAIN    :bit8;
  BLND_MODE           :bit2;
  BLND_STEREO_TYPE    :bit2;
  BLND_STEREO_POLARITY:bit1;
  BLND_FEEDTHROUGH_EN :bit1;
  RESERVED0           :bit2;
  BLND_ALPHA_MODE     :bit2;
  RESERVED1           :bit2;
  BLND_MULTIPLIED_MODE:bit1;
  RESERVED2           :bit3;
  BLND_GLOBAL_ALPHA   :bit8;
 end;

 TBL_PWM_CNTL2=bitpacked record
  BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE:bit16;
  RESERVED0                                  :bit12;
  DBG_BL_PWM_INPUT_REFCLK_SELECT             :bit2;
  BL_PWM_OVERRIDE_BL_OUT_ENABLE              :bit1;
  BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN            :bit1;
 end;

 TCB_BLEND_RED=bit32;

 TCC_RCU_FUSES=bitpacked record
  RESERVED0              :bit1;
  GPU_DIS                :bit1;
  DEBUG_DISABLE          :bit1;
  RESERVED1              :bit1;
  EFUSE_RD_DISABLE       :bit1;
  CG_RST_GLB_REQ_DIS     :bit1;
  DRV_RST_MODE           :bit1;
  ROM_DIS                :bit1;
  JPC_REP_DISABLE        :bit1;
  RCU_BREAK_POINT1       :bit1;
  RCU_BREAK_POINT2       :bit1;
  RESERVED2              :bit1;
  RESERVED3              :bit1;
  RESERVED4              :bit1;
  SMU_IOC_MST_DISABLE    :bit1;
  FCH_LOCKOUT_ENABLE     :bit1;
  FCH_XFIRE_FILTER_ENABLE:bit1;
  XFIRE_DISABLE          :bit1;
  SAMU_FUSE_DISABLE      :bit1;
  BIF_RST_POLLING_DISABLE:bit1;
  RESERVED5              :bit1;
  MEM_HARDREP_EN         :bit1;
  PCIE_INIT_DISABLE      :bit1;
  DSMU_DISABLE           :bit1;
  WRP_FUSE_VALID         :bit1;
  PHY_FUSE_VALID         :bit1;
  RCU_SPARE              :bit6;
 end;

 TCG_ACLK_CNTL=bitpacked record
  ACLK_DIVIDER         :bit7;
  RESERVED0            :bit1;
  ACLK_DIR_CNTL_EN     :bit1;
  ACLK_DIR_CNTL_TOG    :bit1;
  ACLK_DIR_CNTL_DIVIDER:bit7;
  RESERVED1            :bit15;
 end;

 TCG_ACPI_CNTL=bitpacked record
  SCLK_ACPI_DIV   :bit7;
  SCLK_CHANGE_SKIP:bit1;
  RESERVED0       :bit24;
 end;

 TCG_DCLK_CNTL=bitpacked record
  DCLK_DIVIDER         :bit7;
  RESERVED0            :bit1;
  DCLK_DIR_CNTL_EN     :bit1;
  DCLK_DIR_CNTL_TOG    :bit1;
  DCLK_DIR_CNTL_DIVIDER:bit7;
  RESERVED1            :bit15;
 end;

 TCG_ECLK_CNTL=bitpacked record
  ECLK_DIVIDER         :bit7;
  RESERVED0            :bit1;
  ECLK_DIR_CNTL_EN     :bit1;
  ECLK_DIR_CNTL_TOG    :bit1;
  ECLK_DIR_CNTL_DIVIDER:bit7;
  RESERVED1            :bit15;
 end;

 TCG_FDO_CTRL0=bitpacked record
  FDO_STATIC_DUTY:bit8;
  FAN_SPINUP_DUTY:bit8;
  FDO_PWM_MANUAL :bit1;
  FDO_PWM_HYSTER :bit6;
  FDO_PWM_RAMP_EN:bit1;
  FDO_PWM_RAMP   :bit8;
 end;

 TCG_FDO_CTRL1=bitpacked record
  FMAX_DUTY100:bit8;
  FMIN_DUTY   :bit8;
  M           :bit8;
  RESERVED    :bit6;
  FDO_PWRDNB  :bit1;
  RESERVED0   :bit1;
 end;

 TCG_FDO_CTRL2=bitpacked record
  TMIN              :bit8;
  FAN_SPINUP_TIME   :bit3;
  FDO_PWM_MODE      :bit3;
  TMIN_HYSTER       :bit3;
  TMAX              :bit8;
  TACH_PWM_RESP_RATE:bit7;
 end;

 TCG_MCLK_CNTL=bitpacked record
  MCLK_DIVIDER         :bit7;
  RESERVED0            :bit1;
  MCLK_DIR_CNTL_EN     :bit1;
  MCLK_DIR_CNTL_TOG    :bit1;
  MCLK_DIR_CNTL_DIVIDER:bit7;
  RESERVED1            :bit15;
 end;

 TCG_TACH_CTRL=bitpacked record
  EDGE_PER_REV :bit3;
  TARGET_PERIOD:bit29;
 end;

 TCG_VCLK_CNTL=bitpacked record
  VCLK_DIVIDER         :bit7;
  RESERVED0            :bit1;
  VCLK_DIR_CNTL_EN     :bit1;
  VCLK_DIR_CNTL_TOG    :bit1;
  VCLK_DIR_CNTL_DIVIDER:bit7;
  RESERVED1            :bit15;
 end;

 TCOMPUTE_VMID=bitpacked record
  DATA     :bit4;
  RESERVED0:bit28;
 end;

 TCORB_CONTROL=bitpacked record
  CORB_MEMORY_ERROR_INTERRUPT_ENABLE:bit1;
  ENABLE_CORB_DMA_ENGINE            :bit1;
  RESERVED0                         :bit30;
 end;

 TCPC_INT_CNTL=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_ENABLE  :bit1;
  DEQUEUE_REQUEST_INT_ENABLE   :bit1;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  SUA_VIOLATION_INT_ENABLE     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_BUSY_STAT=bitpacked record
  REG_BUS_FIFO_BUSY     :bit1;
  RESERVED0             :bit1;
  RESERVED1             :bit1;
  RESERVED2             :bit1;
  RESERVED3             :bit1;
  RESERVED4             :bit1;
  COHER_CNT_NEQ_ZERO    :bit1;
  PFP_PARSING_PACKETS   :bit1;
  ME_PARSING_PACKETS    :bit1;
  RCIU_PFP_BUSY         :bit1;
  RCIU_ME_BUSY          :bit1;
  RESERVED5             :bit1;
  SEM_CMDFIFO_NOT_EMPTY :bit1;
  SEM_FAILED_AND_HOLDING:bit1;
  SEM_POLLING_FOR_PASS  :bit1;
  GFX_CONTEXT_BUSY      :bit1;
  RESERVED6             :bit1;
  ME_PARSER_BUSY        :bit1;
  EOP_DONE_BUSY         :bit1;
  STRM_OUT_BUSY         :bit1;
  PIPE_STATS_BUSY       :bit1;
  RCIU_CE_BUSY          :bit1;
  CE_PARSING_PACKETS    :bit1;
  RESERVED7             :bit9;
 end;

 TCP_CMD_INDEX=bitpacked record
  CMD_INDEX    :bit11;
  RESERVED0    :bit1;
  CMD_ME_SEL   :bit2;
  RESERVED1    :bit2;
  CMD_QUEUE_SEL:bit3;
  RESERVED2    :bit13;
 end;

 TCP_CNTX_STAT=bitpacked record
  ACTIVE_HP3D_CONTEXTS:bit8;
  CURRENT_HP3D_CONTEXT:bit3;
  RESERVED0           :bit9;
  ACTIVE_GFX_CONTEXTS :bit8;
  CURRENT_GFX_CONTEXT :bit3;
  RESERVED1           :bit1;
 end;

 TCP_DEVICE_ID=bitpacked record
  DEVICE_ID:bit8;
  RESERVED0:bit24;
 end;

 TCP_HQD_ERROR=bitpacked record
  EDC_ERROR_ID:bit4;
  SUA_ERROR   :bit1;
  RESERVED0   :bit27;
 end;

 TCP_IB1_BUFSZ=bitpacked record
  IB1_BUFSZ:bit20;
  RESERVED0:bit12;
 end;

 TCP_IB2_BUFSZ=bitpacked record
  IB2_BUFSZ:bit20;
  RESERVED0:bit12;
 end;

 TCP_MEQ_AVAIL=bitpacked record
  MEQ_CNT  :bit10;
  RESERVED0:bit22;
 end;

 TCP_PQ_STATUS=bitpacked record
  DOORBELL_UPDATED:bit1;
  DOORBELL_ENABLE :bit1;
  RESERVED0       :bit30;
 end;

 TCP_RB_OFFSET=bitpacked record
  RB_OFFSET:bit20;
  RESERVED0:bit12;
 end;

 TCP_ROQ_AVAIL=bitpacked record
  ROQ_CNT_RING:bit11;
  RESERVED0   :bit5;
  ROQ_CNT_IB1 :bit11;
  RESERVED1   :bit5;
 end;

 TCP_STQ_AVAIL=bitpacked record
  STQ_CNT  :bit9;
  RESERVED0:bit23;
 end;

 TCRTC_CONTROL=bitpacked record
  CRTC_MASTER_EN                :bit1;
  RESERVED0                     :bit3;
  CRTC_SYNC_RESET_SEL           :bit1;
  RESERVED1                     :bit3;
  CRTC_DISABLE_POINT_CNTL       :bit2;
  RESERVED2                     :bit2;
  CRTC_START_POINT_CNTL         :bit1;
  CRTC_FIELD_NUMBER_CNTL        :bit1;
  CRTC_FIELD_NUMBER_POLARITY    :bit1;
  RESERVED3                     :bit1;
  CRTC_CURRENT_MASTER_EN_STATE  :bit1;
  RESERVED4                     :bit3;
  CRTC_HBLANK_EARLY_CONTROL     :bit3;
  RESERVED5                     :bit1;
  CRTC_DISP_READ_REQUEST_DISABLE:bit1;
  RESERVED6                     :bit4;
  CRTC_SOF_PULL_EN              :bit1;
  CRTC_AVSYNC_LOCK_SNAPSHOT     :bit1;
  CRTC_AVSYNC_VSYNC_N_HSYNC_MODE:bit1;
 end;

 TCRTC_H_TOTAL=bitpacked record
  CRTC_H_TOTAL:bit14;
  RESERVED0   :bit18;
 end;

 TCRTC_VBI_END=bitpacked record
  CRTC_VBI_V_END:bit14;
  RESERVED0     :bit2;
  CRTC_VBI_H_END:bit14;
  RESERVED1     :bit2;
 end;

 TCRTC_V_TOTAL=bitpacked record
  CRTC_V_TOTAL:bit14;
  RESERVED0   :bit18;
 end;

 TCUR2_CONTROL=bitpacked record
  CURSOR2_EN            :bit1;
  RESERVED0             :bit3;
  CUR2_INV_TRANS_CLAMP  :bit1;
  RESERVED1             :bit3;
  CURSOR2_MODE          :bit2;
  RESERVED2             :bit6;
  CURSOR2_2X_MAGNIFY    :bit1;
  RESERVED3             :bit3;
  CURSOR2_FORCE_MC_ON   :bit1;
  RESERVED4             :bit3;
  CURSOR2_URGENT_CONTROL:bit3;
  RESERVED5             :bit5;
 end;

 TCUR_HOT_SPOT=bitpacked record
  CURSOR_HOT_SPOT_Y:bit7;
  RESERVED0        :bit9;
  CURSOR_HOT_SPOT_X:bit7;
  RESERVED1        :bit9;
 end;

 TCUR_POSITION=bitpacked record
  CURSOR_Y_POSITION:bit14;
  RESERVED0        :bit2;
  CURSOR_X_POSITION:bit14;
  RESERVED1        :bit2;
 end;

 TDAC_PWR_CNTL=bitpacked record
  DAC_BG_MODE:bit2;
  RESERVED0  :bit14;
  DAC_PWRCNTL:bit2;
  RESERVED1  :bit14;
 end;

 TDBG_OUT_CNTL=bitpacked record
  DBG_OUT_PIN_EN   :bit1;
  RESERVED0        :bit3;
  DBG_OUT_PIN_SEL  :bit1;
  RESERVED1        :bit3;
  DBG_OUT_12BIT_SEL:bit2;
  RESERVED2        :bit2;
  DBG_OUT_TEST_DATA:bit12;
  RESERVED3        :bit8;
 end;

 TDCCG_DS_CNTL=bitpacked record
  DCCG_DS_ENABLE           :bit1;
  RESERVED0                :bit7;
  DCCG_DS_HW_CAL_ENABLE    :bit1;
  DCCG_DS_ENABLED_STATUS   :bit1;
  RESERVED1                :bit6;
  DCCG_DS_XTALIN_RATE_DIV  :bit2;
  RESERVED2                :bit6;
  DCCG_DS_JITTER_REMOVE_DIS:bit1;
  DCCG_DS_DELAY_XTAL_SEL   :bit1;
  RESERVED3                :bit6;
 end;

 TDCFE_DBG_SEL=bitpacked record
  DCFE_DBG_SEL:bit4;
  RESERVED0   :bit28;
 end;

 TDCIO_DEBUG10=bit32;

 TDCIO_DEBUG11=bit32;

 TDCIO_DEBUG12=bit32;

 TDCIO_DEBUG13=bit32;

 TDCIO_DEBUG14=bit32;

 TDCIO_DEBUG15=bit32;

 TDCIO_DEBUG16=bit32;

 TDCI_CLK_CNTL=bitpacked record
  DCI_TEST_CLK_SEL          :bit5;
  DISPCLK_R_DCI_GATE_DIS    :bit1;
  DISPCLK_M_GATE_DIS        :bit1;
  SCLK_G_STREAM_AZ_GATE_DIS :bit1;
  SCLK_R_AZ_GATE_DIS        :bit1;
  DISPCLK_G_FBC_GATE_DIS    :bit1;
  RESERVED0                 :bit1;
  DISPCLK_G_VGA_GATE_DIS    :bit1;
  RESERVED1                 :bit1;
  DISPCLK_G_VIP_GATE_DIS    :bit1;
  VPCLK_POL                 :bit1;
  DISPCLK_G_DMCU_GATE_DIS   :bit1;
  DISPCLK_G_DMIF0_GATE_DIS  :bit1;
  DISPCLK_G_DMIF1_GATE_DIS  :bit1;
  DISPCLK_G_DMIF2_GATE_DIS  :bit1;
  DISPCLK_G_DMIF3_GATE_DIS  :bit1;
  DISPCLK_G_DMIF4_GATE_DIS  :bit1;
  DISPCLK_G_DMIF5_GATE_DIS  :bit1;
  SCLK_G_DMIF_GATE_DIS      :bit1;
  SCLK_G_DMIFTRK_GATE_DIS   :bit1;
  SCLK_G_CNTL_AZ_GATE_DIS   :bit1;
  DISPCLK_G_DMIFV_L_GATE_DIS:bit1;
  DISPCLK_G_DMIFV_C_GATE_DIS:bit1;
  DCI_PG_TEST_CLK_SEL       :bit5;
 end;

 TDCO_CLK_CNTL=bitpacked record
  DCO_TEST_CLK_SEL       :bit5;
  DISPCLK_R_DCO_GATE_DIS :bit1;
  DISPCLK_G_ABM_GATE_DIS :bit1;
  DISPCLK_G_DVO_GATE_DIS :bit1;
  DISPCLK_G_DACA_GATE_DIS:bit1;
  DISPCLK_G_DACB_GATE_DIS:bit1;
  REFCLK_R_DCO_GATE_DIS  :bit1;
  RESERVED0              :bit5;
  DISPCLK_G_FMT0_GATE_DIS:bit1;
  DISPCLK_G_FMT1_GATE_DIS:bit1;
  DISPCLK_G_FMT2_GATE_DIS:bit1;
  DISPCLK_G_FMT3_GATE_DIS:bit1;
  DISPCLK_G_FMT4_GATE_DIS:bit1;
  DISPCLK_G_FMT5_GATE_DIS:bit1;
  RESERVED1              :bit2;
  DISPCLK_G_DIGA_GATE_DIS:bit1;
  DISPCLK_G_DIGB_GATE_DIS:bit1;
  DISPCLK_G_DIGC_GATE_DIS:bit1;
  DISPCLK_G_DIGD_GATE_DIS:bit1;
  DISPCLK_G_DIGE_GATE_DIS:bit1;
  DISPCLK_G_DIGF_GATE_DIS:bit1;
  DISPCLK_G_DIGG_GATE_DIS:bit1;
  RESERVED2              :bit1;
 end;

 TDCO_SCRATCH0=bit32;

 TDCO_SCRATCH1=bit32;

 TDCO_SCRATCH2=bit32;

 TDCO_SCRATCH3=bit32;

 TDCO_SCRATCH4=bit32;

 TDCO_SCRATCH5=bit32;

 TDCO_SCRATCH6=bit32;

 TDCO_SCRATCH7=bit32;

 TDCP_CRC_LAST=bit32;

 TDCP_CRC_MASK=bit32;

 TDC_ABM1_CNTL=bitpacked record
  ABM1_EN                       :bit1;
  RESERVED0                     :bit7;
  ABM1_SOURCE_SELECT            :bit3;
  RESERVED1                     :bit20;
  ABM1_BLANK_MODE_SUPPORT_ENABLE:bit1;
 end;

 TDC_PINSTRAPS=bitpacked record
  RESERVED0                :bit10;
  DC_PINSTRAPS_BIF_CEC_DIS :bit1;
  RESERVED1                :bit2;
  DC_PINSTRAPS_SMS_EN_HARD :bit1;
  DC_PINSTRAPS_AUDIO       :bit2;
  DC_PINSTRAPS_CCBYPASS    :bit1;
  DC_PINSTRAPS_CONNECTIVITY:bit3;
  RESERVED2                :bit12;
 end;

 TDEVICE_CNTL2=bitpacked record
  CPL_TIMEOUT_VALUE          :bit4;
  CPL_TIMEOUT_DIS            :bit1;
  ARI_FORWARDING_EN          :bit1;
  ATOMICOP_REQUEST_EN        :bit1;
  ATOMICOP_EGRESS_BLOCKING   :bit1;
  IDO_REQUEST_ENABLE         :bit1;
  IDO_COMPLETION_ENABLE      :bit1;
  LTR_EN                     :bit1;
  RESERVED0                  :bit2;
  OBFF_EN                    :bit2;
  END_END_TLP_PREFIX_BLOCKING:bit1;
  RESERVED1                  :bit16;
 end;

 TDMCU_INT_CNT=bitpacked record
  DMCU_ABM1_HG_READY_INT_CNT :bit8;
  DMCU_ABM1_LS_READY_INT_CNT :bit8;
  DMCU_ABM1_BL_UPDATE_INT_CNT:bit8;
  RESERVED0                  :bit8;
 end;

 TDMIF_CONTROL=bitpacked record
  DMIF_BUFF_SIZE                           :bit2;
  DMIF_GROUP_REQUESTS_IN_CHUNK             :bit1;
  RESERVED0                                :bit1;
  DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT  :bit1;
  RESERVED1                                :bit3;
  DMIF_REQ_BURST_SIZE                      :bit3;
  DMIF_UNDERFLOW_RECOVERY_EN               :bit1;
  DMIF_FORCE_TOTAL_REQ_BURST_SIZE          :bit4;
  DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS:bit6;
  RESERVED2                                :bit2;
  DMIF_DELAY_ARBITRATION                   :bit5;
  DMIF_CHUNK_BUFF_MARGIN                   :bit2;
  RESERVED3                                :bit1;
 end;

 TDMIF_DEBUG02=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit1;
  RESERVED4:bit1;
  RESERVED5:bit1;
  RESERVED6:bit1;
  RESERVED7:bit25;
 end;

 TDMIF_STATUS2=bitpacked record
  DMIF_PIPE0_DISPCLK_STATUS     :bit1;
  DMIF_PIPE1_DISPCLK_STATUS     :bit1;
  DMIF_PIPE2_DISPCLK_STATUS     :bit1;
  DMIF_PIPE3_DISPCLK_STATUS     :bit1;
  DMIF_PIPE4_DISPCLK_STATUS     :bit1;
  DMIF_PIPE5_DISPCLK_STATUS     :bit1;
  RESERVED0                     :bit2;
  DMIF_CHUNK_TRACKER_SCLK_STATUS:bit1;
  DMIF_FBC_TRACKER_SCLK_STATUS  :bit1;
  RESERVED1                     :bit22;
 end;

 TDPM_TABLE_10=bit32;

 TDPM_TABLE_11=bit32;

 TDPM_TABLE_12=bit32;

 TDPM_TABLE_13=bit32;

 TDPM_TABLE_14=bit32;

 TDPM_TABLE_15=bit32;

 TDPM_TABLE_16=bit32;

 TDPM_TABLE_17=bit32;

 TDPM_TABLE_18=bit32;

 TDPM_TABLE_19=bit32;

 TDPM_TABLE_20=bit32;

 TDPM_TABLE_21=bit32;

 TDPM_TABLE_22=bit32;

 TDPM_TABLE_23=bit32;

 TDPM_TABLE_24=bit32;

 TDPM_TABLE_25=bit32;

 TDPM_TABLE_26=bit32;

 TDPM_TABLE_27=bit32;

 TDPM_TABLE_28=bit32;

 TDPM_TABLE_29=bit32;

 TDPM_TABLE_30=bit32;

 TDPM_TABLE_31=bit32;

 TDPM_TABLE_32=bitpacked record
  SmioTable1_Pattern_0_padding:bit8;
  SmioTable1_Pattern_0_Smio   :bit8;
  SmioTable1_Pattern_0_Voltage:bit16;
 end;

 TDPM_TABLE_33=bitpacked record
  SmioTable1_Pattern_1_padding:bit8;
  SmioTable1_Pattern_1_Smio   :bit8;
  SmioTable1_Pattern_1_Voltage:bit16;
 end;

 TDPM_TABLE_34=bitpacked record
  SmioTable1_Pattern_2_padding:bit8;
  SmioTable1_Pattern_2_Smio   :bit8;
  SmioTable1_Pattern_2_Voltage:bit16;
 end;

 TDPM_TABLE_35=bitpacked record
  SmioTable1_Pattern_3_padding:bit8;
  SmioTable1_Pattern_3_Smio   :bit8;
  SmioTable1_Pattern_3_Voltage:bit16;
 end;

 TDPM_TABLE_36=bitpacked record
  SmioTable2_Pattern_0_padding:bit8;
  SmioTable2_Pattern_0_Smio   :bit8;
  SmioTable2_Pattern_0_Voltage:bit16;
 end;

 TDPM_TABLE_37=bitpacked record
  SmioTable2_Pattern_1_padding:bit8;
  SmioTable2_Pattern_1_Smio   :bit8;
  SmioTable2_Pattern_1_Voltage:bit16;
 end;

 TDPM_TABLE_38=bitpacked record
  SmioTable2_Pattern_2_padding:bit8;
  SmioTable2_Pattern_2_Smio   :bit8;
  SmioTable2_Pattern_2_Voltage:bit16;
 end;

 TDPM_TABLE_39=bitpacked record
  SmioTable2_Pattern_3_padding:bit8;
  SmioTable2_Pattern_3_Smio   :bit8;
  SmioTable2_Pattern_3_Voltage:bit16;
 end;

 TDPM_TABLE_40=bit32;

 TDPM_TABLE_41=bit32;

 TDPM_TABLE_42=bit32;

 TDPM_TABLE_43=bit32;

 TDPM_TABLE_44=bitpacked record
  VddcTable_1:bit16;
  VddcTable_0:bit16;
 end;

 TDPM_TABLE_45=bitpacked record
  VddcTable_3:bit16;
  VddcTable_2:bit16;
 end;

 TDPM_TABLE_46=bitpacked record
  VddcTable_5:bit16;
  VddcTable_4:bit16;
 end;

 TDPM_TABLE_47=bitpacked record
  VddcTable_7:bit16;
  VddcTable_6:bit16;
 end;

 TDPM_TABLE_48=bitpacked record
  VddcTable_9:bit16;
  VddcTable_8:bit16;
 end;

 TDPM_TABLE_49=bitpacked record
  VddcTable_11:bit16;
  VddcTable_10:bit16;
 end;

 TDPM_TABLE_50=bitpacked record
  VddcTable_13:bit16;
  VddcTable_12:bit16;
 end;

 TDPM_TABLE_51=bitpacked record
  VddcTable_15:bit16;
  VddcTable_14:bit16;
 end;

 TDPM_TABLE_52=bitpacked record
  VddGfxTable_1:bit16;
  VddGfxTable_0:bit16;
 end;

 TDPM_TABLE_53=bitpacked record
  VddGfxTable_3:bit16;
  VddGfxTable_2:bit16;
 end;

 TDPM_TABLE_54=bitpacked record
  VddGfxTable_5:bit16;
  VddGfxTable_4:bit16;
 end;

 TDPM_TABLE_55=bitpacked record
  VddGfxTable_7:bit16;
  VddGfxTable_6:bit16;
 end;

 TDPM_TABLE_56=bitpacked record
  VddGfxTable_9:bit16;
  VddGfxTable_8:bit16;
 end;

 TDPM_TABLE_57=bitpacked record
  VddGfxTable_11:bit16;
  VddGfxTable_10:bit16;
 end;

 TDPM_TABLE_58=bitpacked record
  VddGfxTable_13:bit16;
  VddGfxTable_12:bit16;
 end;

 TDPM_TABLE_59=bitpacked record
  VddGfxTable_15:bit16;
  VddGfxTable_14:bit16;
 end;

 TDPM_TABLE_60=bitpacked record
  VddciTable_1:bit16;
  VddciTable_0:bit16;
 end;

 TDPM_TABLE_61=bitpacked record
  VddciTable_3:bit16;
  VddciTable_2:bit16;
 end;

 TDPM_TABLE_62=bitpacked record
  VddciTable_5:bit16;
  VddciTable_4:bit16;
 end;

 TDPM_TABLE_63=bitpacked record
  VddciTable_7:bit16;
  VddciTable_6:bit16;
 end;

 TDPM_TABLE_64=bitpacked record
  BapmVddGfxVidHiSidd_3:bit8;
  BapmVddGfxVidHiSidd_2:bit8;
  BapmVddGfxVidHiSidd_1:bit8;
  BapmVddGfxVidHiSidd_0:bit8;
 end;

 TDPM_TABLE_65=bitpacked record
  BapmVddGfxVidHiSidd_7:bit8;
  BapmVddGfxVidHiSidd_6:bit8;
  BapmVddGfxVidHiSidd_5:bit8;
  BapmVddGfxVidHiSidd_4:bit8;
 end;

 TDPM_TABLE_66=bitpacked record
  BapmVddGfxVidHiSidd_11:bit8;
  BapmVddGfxVidHiSidd_10:bit8;
  BapmVddGfxVidHiSidd_9 :bit8;
  BapmVddGfxVidHiSidd_8 :bit8;
 end;

 TDPM_TABLE_67=bitpacked record
  BapmVddGfxVidHiSidd_15:bit8;
  BapmVddGfxVidHiSidd_14:bit8;
  BapmVddGfxVidHiSidd_13:bit8;
  BapmVddGfxVidHiSidd_12:bit8;
 end;

 TDPM_TABLE_68=bitpacked record
  BapmVddGfxVidLoSidd_3:bit8;
  BapmVddGfxVidLoSidd_2:bit8;
  BapmVddGfxVidLoSidd_1:bit8;
  BapmVddGfxVidLoSidd_0:bit8;
 end;

 TDPM_TABLE_69=bitpacked record
  BapmVddGfxVidLoSidd_7:bit8;
  BapmVddGfxVidLoSidd_6:bit8;
  BapmVddGfxVidLoSidd_5:bit8;
  BapmVddGfxVidLoSidd_4:bit8;
 end;

 TDPM_TABLE_70=bitpacked record
  BapmVddGfxVidLoSidd_11:bit8;
  BapmVddGfxVidLoSidd_10:bit8;
  BapmVddGfxVidLoSidd_9 :bit8;
  BapmVddGfxVidLoSidd_8 :bit8;
 end;

 TDPM_TABLE_71=bitpacked record
  BapmVddGfxVidLoSidd_15:bit8;
  BapmVddGfxVidLoSidd_14:bit8;
  BapmVddGfxVidLoSidd_13:bit8;
  BapmVddGfxVidLoSidd_12:bit8;
 end;

 TDPM_TABLE_72=bitpacked record
  BapmVddGfxVidHiSidd2_3:bit8;
  BapmVddGfxVidHiSidd2_2:bit8;
  BapmVddGfxVidHiSidd2_1:bit8;
  BapmVddGfxVidHiSidd2_0:bit8;
 end;

 TDPM_TABLE_73=bitpacked record
  BapmVddGfxVidHiSidd2_7:bit8;
  BapmVddGfxVidHiSidd2_6:bit8;
  BapmVddGfxVidHiSidd2_5:bit8;
  BapmVddGfxVidHiSidd2_4:bit8;
 end;

 TDPM_TABLE_74=bitpacked record
  BapmVddGfxVidHiSidd2_11:bit8;
  BapmVddGfxVidHiSidd2_10:bit8;
  BapmVddGfxVidHiSidd2_9 :bit8;
  BapmVddGfxVidHiSidd2_8 :bit8;
 end;

 TDPM_TABLE_75=bitpacked record
  BapmVddGfxVidHiSidd2_15:bit8;
  BapmVddGfxVidHiSidd2_14:bit8;
  BapmVddGfxVidHiSidd2_13:bit8;
  BapmVddGfxVidHiSidd2_12:bit8;
 end;

 TDPM_TABLE_76=bitpacked record
  BapmVddcVidHiSidd_3:bit8;
  BapmVddcVidHiSidd_2:bit8;
  BapmVddcVidHiSidd_1:bit8;
  BapmVddcVidHiSidd_0:bit8;
 end;

 TDPM_TABLE_77=bitpacked record
  BapmVddcVidHiSidd_7:bit8;
  BapmVddcVidHiSidd_6:bit8;
  BapmVddcVidHiSidd_5:bit8;
  BapmVddcVidHiSidd_4:bit8;
 end;

 TDPM_TABLE_78=bitpacked record
  BapmVddcVidHiSidd_11:bit8;
  BapmVddcVidHiSidd_10:bit8;
  BapmVddcVidHiSidd_9 :bit8;
  BapmVddcVidHiSidd_8 :bit8;
 end;

 TDPM_TABLE_79=bitpacked record
  BapmVddcVidHiSidd_15:bit8;
  BapmVddcVidHiSidd_14:bit8;
  BapmVddcVidHiSidd_13:bit8;
  BapmVddcVidHiSidd_12:bit8;
 end;

 TDPM_TABLE_80=bitpacked record
  BapmVddcVidLoSidd_3:bit8;
  BapmVddcVidLoSidd_2:bit8;
  BapmVddcVidLoSidd_1:bit8;
  BapmVddcVidLoSidd_0:bit8;
 end;

 TDPM_TABLE_81=bitpacked record
  BapmVddcVidLoSidd_7:bit8;
  BapmVddcVidLoSidd_6:bit8;
  BapmVddcVidLoSidd_5:bit8;
  BapmVddcVidLoSidd_4:bit8;
 end;

 TDPM_TABLE_82=bitpacked record
  BapmVddcVidLoSidd_11:bit8;
  BapmVddcVidLoSidd_10:bit8;
  BapmVddcVidLoSidd_9 :bit8;
  BapmVddcVidLoSidd_8 :bit8;
 end;

 TDPM_TABLE_83=bitpacked record
  BapmVddcVidLoSidd_15:bit8;
  BapmVddcVidLoSidd_14:bit8;
  BapmVddcVidLoSidd_13:bit8;
  BapmVddcVidLoSidd_12:bit8;
 end;

 TDPM_TABLE_84=bitpacked record
  BapmVddcVidHiSidd2_3:bit8;
  BapmVddcVidHiSidd2_2:bit8;
  BapmVddcVidHiSidd2_1:bit8;
  BapmVddcVidHiSidd2_0:bit8;
 end;

 TDPM_TABLE_85=bitpacked record
  BapmVddcVidHiSidd2_7:bit8;
  BapmVddcVidHiSidd2_6:bit8;
  BapmVddcVidHiSidd2_5:bit8;
  BapmVddcVidHiSidd2_4:bit8;
 end;

 TDPM_TABLE_86=bitpacked record
  BapmVddcVidHiSidd2_11:bit8;
  BapmVddcVidHiSidd2_10:bit8;
  BapmVddcVidHiSidd2_9 :bit8;
  BapmVddcVidHiSidd2_8 :bit8;
 end;

 TDPM_TABLE_87=bitpacked record
  BapmVddcVidHiSidd2_15:bit8;
  BapmVddcVidHiSidd2_14:bit8;
  BapmVddcVidHiSidd2_13:bit8;
  BapmVddcVidHiSidd2_12:bit8;
 end;

 TDPM_TABLE_88=bitpacked record
  MasterDeepSleepControl:bit8;
  LinkLevelCount        :bit8;
  MemoryDpmLevelCount   :bit8;
  GraphicsDpmLevelCount :bit8;
 end;

 TDPM_TABLE_89=bitpacked record
  SamuLevelCount:bit8;
  AcpLevelCount :bit8;
  VceLevelCount :bit8;
  UvdLevelCount :bit8;
 end;

 TDPM_TABLE_90=bitpacked record
  Reserved_0      :bit8;
  ThermOutMode    :bit8;
  ThermOutPolarity:bit8;
  ThermOutGpio    :bit8;
 end;

 TDPM_TABLE_91=bit32;

 TDPM_TABLE_92=bit32;

 TDPM_TABLE_93=bit32;

 TDPM_TABLE_94=bit32;

 TDPM_TABLE_95=bitpacked record
  GraphicsLevel_0_MinVoltage_Phases:bit8;
  GraphicsLevel_0_MinVoltage_VddGfx:bit8;
  GraphicsLevel_0_MinVoltage_Vddci :bit8;
  GraphicsLevel_0_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_96=bit32;

 TDPM_TABLE_97=bitpacked record
  GraphicsLevel_0_ActivityLevel :bit16;
  GraphicsLevel_0_DeepSleepDivId:bit8;
  GraphicsLevel_0_pcieDpmLevel  :bit8;
 end;

 TDPM_TABLE_98=bit32;

 TDPM_TABLE_99=bit32;

 TDP_DPHY_CNTL=bitpacked record
  DPHY_ATEST_SEL_LANE0:bit1;
  DPHY_ATEST_SEL_LANE1:bit1;
  DPHY_ATEST_SEL_LANE2:bit1;
  DPHY_ATEST_SEL_LANE3:bit1;
  RESERVED0           :bit4;
  RESERVED1           :bit1;
  RESERVED2           :bit7;
  DPHY_BYPASS         :bit1;
  RESERVED3           :bit7;
  DPHY_SKEW_BYPASS    :bit1;
  RESERVED4           :bit7;
 end;

 TDP_DPHY_SYM0=bitpacked record
  DPHY_SYM1:bit10;
  DPHY_SYM2:bit10;
  DPHY_SYM3:bit10;
  RESERVED0:bit2;
 end;

 TDP_DPHY_SYM1=bitpacked record
  DPHY_SYM4:bit10;
  DPHY_SYM5:bit10;
  DPHY_SYM6:bit10;
  RESERVED0:bit2;
 end;

 TDP_DPHY_SYM2=bitpacked record
  DPHY_SYM7:bit10;
  DPHY_SYM8:bit10;
  RESERVED0:bit12;
 end;

 TDP_LINK_CNTL=bitpacked record
  RESERVED0                :bit4;
  DP_LINK_TRAINING_COMPLETE:bit1;
  RESERVED1                :bit3;
  DP_LINK_STATUS           :bit1;
  RESERVED2                :bit8;
  DP_EMBEDDED_PANEL_MODE   :bit1;
  RESERVED3                :bit14;
 end;

 TDP_SEC_AUD_M=bitpacked record
  DP_SEC_AUD_M:bit24;
  RESERVED0   :bit8;
 end;

 TDP_SEC_AUD_N=bitpacked record
  DP_SEC_AUD_N:bit24;
  RESERVED0   :bit4;
  RESERVED1   :bit1;
  RESERVED2   :bit3;
 end;

 TDP_SEC_CNTL1=bitpacked record
  DP_SEC_ISRC_ENABLE:bit1;
  RESERVED0         :bit31;
 end;

 TEFUSE_STATUS=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit14;
  RESERVED3:bit8;
  RESERVED4:bit8;
 end;

 TFBC_IND_LUT0=bitpacked record
  FBC_IND_LUT0:bit24;
  RESERVED0   :bit8;
 end;

 TFBC_IND_LUT1=bitpacked record
  FBC_IND_LUT1:bit24;
  RESERVED0   :bit8;
 end;

 TFBC_IND_LUT2=bitpacked record
  FBC_IND_LUT2:bit24;
  RESERVED0   :bit8;
 end;

 TFBC_IND_LUT3=bitpacked record
  FBC_IND_LUT3:bit24;
  RESERVED0   :bit8;
 end;

 TFBC_IND_LUT4=bitpacked record
  FBC_IND_LUT4:bit24;
  RESERVED0   :bit8;
 end;

 TFBC_IND_LUT5=bitpacked record
  FBC_IND_LUT5:bit24;
  RESERVED0   :bit8;
 end;

 TFBC_IND_LUT6=bitpacked record
  FBC_IND_LUT6:bit24;
  RESERVED0   :bit8;
 end;

 TFBC_IND_LUT7=bitpacked record
  FBC_IND_LUT7:bit24;
  RESERVED0   :bit8;
 end;

 TFBC_IND_LUT8=bitpacked record
  FBC_IND_LUT8:bit24;
  RESERVED0   :bit8;
 end;

 TFBC_IND_LUT9=bitpacked record
  FBC_IND_LUT9:bit24;
  RESERVED0   :bit8;
 end;

 TFMT_CRC_CNTL=bitpacked record
  FMT_CRC_EN                         :bit1;
  FMT_DTMTEST_CRC_EN                 :bit1;
  RESERVED0                          :bit2;
  FMT_CRC_CONT_EN                    :bit1;
  RESERVED1                          :bit3;
  FMT_CRC_ONLY_BLANKB                :bit1;
  RESERVED2                          :bit3;
  FMT_CRC_INTERLACE_MODE             :bit2;
  RESERVED3                          :bit2;
  FMT_CRC_USE_NEW_AND_REPEATED_PIXELS:bit1;
  RESERVED4                          :bit3;
  FMT_CRC_EVEN_ODD_PIX_ENABLE        :bit1;
  RESERVED5                          :bit3;
  FMT_CRC_EVEN_ODD_PIX_SELECT        :bit1;
  RESERVED6                          :bit7;
 end;

 TFMT_DEBUG_ID=bit32;

 TGDS_ATOM_DST=bit32;

 TGDS_DSM_CNTL=bitpacked record
  SEL_DSM_GDS_IRRITATOR_DATA_A_0:bit1;
  SEL_DSM_GDS_IRRITATOR_DATA_A_1:bit1;
  GDS_ENABLE_SINGLE_WRITE_A     :bit1;
  SEL_DSM_GDS_IRRITATOR_DATA_B_0:bit1;
  SEL_DSM_GDS_IRRITATOR_DATA_B_1:bit1;
  GDS_ENABLE_SINGLE_WRITE_B     :bit1;
  UNUSED                        :bit26;
 end;

 TGDS_ENHANCE2=bitpacked record
  MISC     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_RESET=bitpacked record
  RESET    :bit1;
  RESERVED0:bit7;
  PIPE_ID  :bit8;
  RESERVED1:bit16;
 end;

 TGDS_OA_VMID0=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID1=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID2=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID3=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID4=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID5=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID6=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID7=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID8=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID9=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGPIOPAD_MASK=bitpacked record
  GPIO_MASK:bit31;
  RESERVED0:bit1;
 end;

 TGRBM_NOWHERE=bit32;

 TGRBM_STATUS2=bitpacked record
  ME0PIPE1_CMDFIFO_AVAIL:bit4;
  ME0PIPE1_CF_RQ_PENDING:bit1;
  ME0PIPE1_PF_RQ_PENDING:bit1;
  ME1PIPE0_RQ_PENDING   :bit1;
  ME1PIPE1_RQ_PENDING   :bit1;
  ME1PIPE2_RQ_PENDING   :bit1;
  ME1PIPE3_RQ_PENDING   :bit1;
  ME2PIPE0_RQ_PENDING   :bit1;
  ME2PIPE1_RQ_PENDING   :bit1;
  ME2PIPE2_RQ_PENDING   :bit1;
  ME2PIPE3_RQ_PENDING   :bit1;
  RLC_RQ_PENDING        :bit1;
  RESERVED0             :bit9;
  RLC_BUSY              :bit1;
  TC_BUSY               :bit1;
  TCC_CC_RESIDENT       :bit1;
  RESERVED1             :bit1;
  CPF_BUSY              :bit1;
  CPC_BUSY              :bit1;
  CPG_BUSY              :bit1;
  RESERVED2             :bit1;
 end;

 TGRBM_TRAP_OP=bitpacked record
  RW       :bit1;
  RESERVED0:bit31;
 end;

 TGRBM_TRAP_WD=bit32;

 TGRPH_CONTROL=bitpacked record
  GRPH_DEPTH                     :bit2;
  GRPH_NUM_BANKS                 :bit2;
  GRPH_Z                         :bit2;
  GRPH_BANK_WIDTH                :bit2;
  GRPH_FORMAT                    :bit3;
  GRPH_BANK_HEIGHT               :bit2;
  GRPH_TILE_SPLIT                :bit3;
  GRPH_ADDRESS_TRANSLATION_ENABLE:bit1;
  GRPH_PRIVILEGED_ACCESS_ENABLE  :bit1;
  GRPH_MACRO_TILE_ASPECT         :bit2;
  GRPH_ARRAY_MODE                :bit4;
  GRPH_PIPE_CONFIG               :bit5;
  GRPH_MICRO_TILE_MODE           :bit2;
  GRPH_COLOR_EXPANSION_MODE      :bit1;
 end;

 TGRPH_X_START=bitpacked record
  GRPH_X_START:bit14;
  RESERVED0   :bit18;
 end;

 TGRPH_Y_START=bitpacked record
  GRPH_Y_START:bit14;
  RESERVED0   :bit18;
 end;

 TGSKT_CONTROL=bitpacked record
  GSKT_TxFifoBypass:bit1;
  GSKT_TxFifoDelay :bit1;
  GSKT_TxFifoDelay2:bit1;
  GSKT_SpareRegs   :bit5;
  RESERVED0        :bit24;
 end;

 THDMI_CONTROL=bitpacked record
  HDMI_KEEPOUT_MODE      :bit1;
  RESERVED0              :bit3;
  HDMI_PACKET_GEN_VERSION:bit1;
  RESERVED1              :bit3;
  HDMI_ERROR_ACK         :bit1;
  HDMI_ERROR_MASK        :bit1;
  RESERVED2              :bit14;
  HDMI_DEEP_COLOR_ENABLE :bit1;
  RESERVED3              :bit3;
  HDMI_DEEP_COLOR_DEPTH  :bit2;
  RESERVED4              :bit2;
 end;

 THDP_XDP_CHKN=bitpacked record
  CHKN_0_RSVD:bit8;
  CHKN_1_RSVD:bit8;
  CHKN_2_RSVD:bit8;
  CHKN_3_RSVD:bit8;
 end;

 TIH_VF_ENABLE=bitpacked record
  VALUE    :bit1;
  RESERVED0:bit31;
 end;

 TIMPCTL_RESET=bitpacked record
  IMP_SW_RESET:bit1;
  RESERVED0   :bit31;
 end;

 TLB_V_COUNTER=bitpacked record
  V_COUNTER:bit15;
  RESERVED0:bit17;
 end;

 TLINK_STATUS2=bitpacked record
  CUR_DEEMPHASIS_LEVEL       :bit1;
  EQUALIZATION_COMPLETE      :bit1;
  EQUALIZATION_PHASE1_SUCCESS:bit1;
  EQUALIZATION_PHASE2_SUCCESS:bit1;
  EQUALIZATION_PHASE3_SUCCESS:bit1;
  LINK_EQUALIZATION_REQUEST  :bit1;
  RESERVED0                  :bit26;
 end;

 TLNCNT_WEIGHT=bitpacked record
  CFG_LNC_BW_WEIGHT0  :bit16;
  CFG_LNC_CMN_WEIGHT16:bit16;
 end;

 TLNC_CMN_WACC=bit32;

 TMCIF_CONTROL=bitpacked record
  MCIF_BUFF_SIZE                     :bit2;
  RESERVED0                          :bit2;
  ADDRESS_TRANSLATION_ENABLE         :bit1;
  RESERVED1                          :bit3;
  PRIVILEGED_ACCESS_ENABLE           :bit1;
  RESERVED2                          :bit3;
  MCIF_SLOW_REQ_INTERVAL             :bit4;
  LOW_READ_URG_LEVEL                 :bit8;
  MC_CLEAN_DEASSERT_LATENCY          :bit6;
  MCIF_MC_LATENCY_COUNTER_ENABLE     :bit1;
  MCIF_MC_LATENCY_COUNTER_URGENT_ONLY:bit1;
 end;

 TMC_ARB_GECC2=bitpacked record
  ENABLE            :bit1;
  ECC_MODE          :bit2;
  PAGE_BIT0         :bit2;
  EXOR_BANK_SEL     :bit2;
  NO_GECC_CLI       :bit4;
  READ_ERR          :bit3;
  CLOSE_BANK_RMW    :bit1;
  COLFIFO_WATER     :bit6;
  WRADDR_CONV       :bit1;
  RMWRD_UNCOR_POISON:bit1;
  RESERVED0         :bit9;
 end;

 TMC_ARB_GRUB2=bitpacked record
  REALTIME_GRP_RD                     :bit8;
  REALTIME_GRP_WR                     :bit8;
  DISP_RD_STALL_EN                    :bit1;
  ACP_RD_STALL_EN                     :bit1;
  UVD_RD_STALL_EN                     :bit1;
  VCE0_RD_STALL_EN                    :bit1;
  VCE1_RD_STALL_EN                    :bit1;
  REALTIME_RD_WTS                     :bit1;
  REALTIME_WR_WTS                     :bit1;
  URGENT_BY_DISP_STALL                :bit1;
  PROMOTE_BY_DMIF_URG                 :bit1;
  PRIORITY_URGENT_OUTSTANDING_ONLY_RD :bit1;
  PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD:bit1;
  PRIORITY_URGENT_OUTSTANDING_ONLY_WR :bit1;
  PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR:bit1;
  RESERVED0                           :bit3;
 end;

 TMC_ARB_LM_RD=bitpacked record
  STREAK_LIMIT       :bit8;
  STREAK_LIMIT_UBER  :bit8;
  STREAK_BREAK       :bit1;
  STREAK_UBER        :bit1;
  ENABLE_TWO_LIST    :bit1;
  POPIDLE_RST_TWOLIST:bit1;
  SKID1_RST_TWOLIST  :bit1;
  BANKGROUP_CONFIG   :bit3;
  RESERVED0          :bit8;
 end;

 TMC_ARB_LM_WR=bitpacked record
  STREAK_LIMIT       :bit8;
  STREAK_LIMIT_UBER  :bit8;
  STREAK_BREAK       :bit1;
  STREAK_UBER        :bit1;
  ENABLE_TWO_LIST    :bit1;
  POPIDLE_RST_TWOLIST:bit1;
  SKID1_RST_TWOLIST  :bit1;
  BANKGROUP_CONFIG   :bit3;
  MASKWR_LM_EOB      :bit1;
  ATOMIC_LM_EOB      :bit1;
  ATOMIC_RTN_LM_EOB  :bit1;
  RESERVED0          :bit5;
 end;

 TMC_ARB_MISC2=bitpacked record
  RESERVED0                  :bit1;
  RESERVED1                  :bit1;
  RESERVED2                  :bit1;
  RESERVED3                  :bit2;
  TCCDL4_BANKBIT3_XOR_ENABLE :bit1;
  TCCDL4_BANKBIT3_XOR_COLBIT4:bit1;
  TCCDL4_BANKBIT3_XOR_COLBIT5:bit1;
  TCCDL4_BANKBIT3_XOR_COLBIT6:bit1;
  TCCDL4_BANKBIT3_XOR_COLBIT7:bit1;
  TCCDL4_BANKBIT3_XOR_COLBIT8:bit1;
  POP_IDLE_REPLAY            :bit1;
  RDRET_NO_REORDERING        :bit1;
  RDRET_NO_BP                :bit1;
  RDRET_SEQ_SKID             :bit4;
  GECC                       :bit1;
  GECC_RST                   :bit1;
  GECC_STATUS                :bit1;
  TAGFIFO_THRESHOLD          :bit4;
  WCDR_REPLAY_MASKCNT        :bit3;
  REPLAY_DEBUG               :bit1;
  ARB_DEBUG29                :bit1;
  SEQ_RDY_POP_IDLE           :bit1;
  TCCDL4_REPLAY_EOB          :bit1;
 end;

 TMC_ARB_MISC3=bitpacked record
  NO_GECC_EXT_EOB     :bit1;
  CHAN4_EN            :bit1;
  CHAN4_ARB_SEL       :bit1;
  UVD_URG_MODE        :bit1;
  UVD_DMIF_HARSH_WT_EN:bit1;
  TBD_FIELD           :bit27;
 end;

 TMC_ARB_SNOOP=bitpacked record
  TC_GRP_RD     :bit3;
  TC_GRP_RD_EN  :bit1;
  TC_GRP_WR     :bit3;
  TC_GRP_WR_EN  :bit1;
  SDMA_GRP_RD   :bit3;
  SDMA_GRP_RD_EN:bit1;
  SDMA_GRP_WR   :bit3;
  SDMA_GRP_WR_EN:bit1;
  OUTSTANDING_RD:bit8;
  OUTSTANDING_WR:bit8;
 end;

 TMC_BIST_CNTL=bitpacked record
  RESET    :bit1;
  RUN      :bit1;
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit4;
  RESERVED3:bit2;
  RESERVED4:bit1;
  RESERVED5:bit1;
  LOOP_CNT :bit12;
  RESERVED6:bit1;
  RESERVED7:bit1;
  RESERVED8:bit1;
  RESERVED9:bit5;
 end;

 TMC_CG_CONFIG=bitpacked record
  MCDW_WR_ENABLE:bit1;
  MCDX_WR_ENABLE:bit1;
  MCDY_WR_ENABLE:bit1;
  MCDZ_WR_ENABLE:bit1;
  MC_RD_ENABLE  :bit2;
  INDEX         :bit16;
  RESERVED0     :bit10;
 end;

 TMC_CITF_CNTL=bitpacked record
  RESERVED0               :bit2;
  IGNOREPM                :bit1;
  EXEMPTPM                :bit1;
  GFX_IDLE_OVERRIDE       :bit2;
  MCD_SRBM_MASK_ENABLE    :bit1;
  CNTR_CHMAP_MODE         :bit2;
  REMOTE_RB_CONNECT_ENABLE:bit1;
  RESERVED1               :bit22;
 end;

 TMC_SEQ_MISC0=bit32;

 TMC_SEQ_MISC1=bit32;

 TMC_SEQ_MISC3=bit32;

 TMC_SEQ_MISC4=bit32;

 TMC_SEQ_MISC5=bit32;

 TMC_SEQ_MISC6=bit32;

 TMC_SEQ_MISC7=bit32;

 TMC_SEQ_MISC8=bit32;

 TMC_SEQ_MISC9=bit32;

 TMSI_CAP_LIST=bitpacked record
  CAP_ID   :bit8;
  NEXT_PTR :bit8;
  RESERVED0:bit16;
 end;

 TMSI_MSG_CNTL=bitpacked record
  MSI_EN                   :bit1;
  MSI_MULTI_CAP            :bit3;
  MSI_MULTI_EN             :bit3;
  MSI_64BIT                :bit1;
  MSI_PERVECTOR_MASKING_CAP:bit1;
  RESERVED0                :bit23;
 end;

 TMSI_MSG_DATA=bitpacked record
  MSI_DATA :bit16;
  RESERVED0:bit16;
 end;

 TMVP_CONTROL1=bitpacked record
  MVP_EN                                         :bit1;
  RESERVED0                                      :bit3;
  MVP_MIXER_MODE                                 :bit3;
  RESERVED1                                      :bit1;
  MVP_MIXER_SLAVE_SEL                            :bit1;
  MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK   :bit1;
  MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE:bit1;
  RESERVED2                                      :bit1;
  MVP_RATE_CONTROL                               :bit1;
  RESERVED3                                      :bit3;
  MVP_CHANNEL_CONTROL                            :bit1;
  RESERVED4                                      :bit3;
  MVP_GPU_CHAIN_LOCATION                         :bit2;
  RESERVED5                                      :bit2;
  MVP_DISABLE_MSB_EXPAND                         :bit1;
  RESERVED6                                      :bit3;
  MVP_30BPP_EN                                   :bit1;
  RESERVED7                                      :bit1;
  MVP_TERMINATION_CNTL_A                         :bit1;
  MVP_TERMINATION_CNTL_B                         :bit1;
 end;

 TMVP_CONTROL2=bitpacked record
  MVP_MUX_DE_DVOCNTL0_SEL:bit1;
  RESERVED0              :bit3;
  MVP_MUX_DE_DVOCNTL2_SEL:bit1;
  RESERVED1              :bit3;
  MVP_MUXA_CLK_SEL       :bit1;
  RESERVED2              :bit3;
  MVP_MUXB_CLK_SEL       :bit1;
  RESERVED3              :bit3;
  MVP_DVOCNTL_MUX        :bit1;
  RESERVED4              :bit3;
  MVP_FLOW_CONTROL_OUT_EN:bit1;
  RESERVED5              :bit3;
  MVP_SWAP_LOCK_OUT_EN   :bit1;
  RESERVED6              :bit3;
  MVP_SWAP_AB_IN_DC_DDR  :bit1;
  RESERVED7              :bit3;
 end;

 TMVP_CONTROL3=bitpacked record
  MVP_RESET_IN_BETWEEN_FRAMES    :bit1;
  RESERVED0                      :bit3;
  MVP_DDR_SC_AB_SEL              :bit1;
  RESERVED1                      :bit3;
  MVP_DDR_SC_B_START_MODE        :bit1;
  RESERVED2                      :bit3;
  MVP_FLOW_CONTROL_OUT_FORCE_ONE :bit1;
  RESERVED3                      :bit3;
  MVP_FLOW_CONTROL_OUT_FORCE_ZERO:bit1;
  RESERVED4                      :bit3;
  MVP_FLOW_CONTROL_CASCADE_EN    :bit1;
  RESERVED5                      :bit3;
  MVP_SWAP_48BIT_EN              :bit1;
  RESERVED6                      :bit3;
  MVP_FLOW_CONTROL_IN_CAP        :bit1;
  RESERVED7                      :bit3;
 end;

 TMVP_CRC_CNTL=bitpacked record
  MVP_CRC_BLUE_MASK              :bit8;
  MVP_CRC_GREEN_MASK             :bit8;
  MVP_CRC_RED_MASK               :bit8;
  RESERVED0                      :bit4;
  MVP_CRC_EN                     :bit1;
  MVP_CRC_CONT_EN                :bit1;
  MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL:bit1;
  RESERVED1                      :bit1;
 end;

 TMVP_DEBUG_05=bitpacked record
  RESERVED0                  :bit1;
  IDE0_MVP_GPU_CHAIN_LOCATION:bit2;
  RESERVED1                  :bit1;
  RESERVED2                  :bit1;
  RESERVED3                  :bit1;
  RESERVED4                  :bit1;
  RESERVED5                  :bit1;
  RESERVED6                  :bit1;
  RESERVED7                  :bit1;
  RESERVED8                  :bit1;
  RESERVED9                  :bit1;
  RESERVED10                 :bit1;
  RESERVED11                 :bit1;
  RESERVED12                 :bit1;
  RESERVED13                 :bit1;
  RESERVED14                 :bit1;
  RESERVED15                 :bit1;
  RESERVED16                 :bit1;
  RESERVED17                 :bit1;
  RESERVED18                 :bit1;
  RESERVED19                 :bit3;
  RESERVED20                 :bit2;
  RESERVED21                 :bit1;
  RESERVED22                 :bit1;
  RESERVED23                 :bit1;
  RESERVED24                 :bit1;
  RESERVED25                 :bit1;
  RESERVED26                 :bit1;
 end;

 TMVP_DEBUG_09=bitpacked record
  RESERVED0                        :bit1;
  IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION:bit2;
  RESERVED1                        :bit2;
  RESERVED2                        :bit1;
  RESERVED3                        :bit1;
  RESERVED4                        :bit1;
  RESERVED5                        :bit1;
  RESERVED6                        :bit1;
  RESERVED7                        :bit1;
  RESERVED8                        :bit1;
  RESERVED9                        :bit1;
  RESERVED10                       :bit1;
  RESERVED11                       :bit1;
  RESERVED12                       :bit1;
  RESERVED13                       :bit1;
  RESERVED14                       :bit1;
  RESERVED15                       :bit1;
  RESERVED16                       :bit1;
  RESERVED17                       :bit1;
  RESERVED18                       :bit11;
 end;

 TMVP_DEBUG_12=bitpacked record
  IDEC_MVP_DATA_A_H:bit1;
  IDEC_MVP_DATA_A  :bit24;
  RESERVED0        :bit7;
 end;

 TMVP_DEBUG_13=bitpacked record
  IDED_MVP_DATA_B_H        :bit1;
  IDED_MVP_DATA_B          :bit24;
  IDED_START_READ_B        :bit1;
  IDED_READ_FIFO_ENTRY_DE_B:bit1;
  IDED_WRITE_ADD_B         :bit3;
  RESERVED0                :bit2;
 end;

 TMVP_DEBUG_14=bitpacked record
  IDEE_READ_ADD                  :bit3;
  IDEE_WRITE_ADD_A               :bit3;
  IDEE_WRITE_ADD_B               :bit3;
  IDEE_START_READ                :bit1;
  IDEE_START_READ_B              :bit1;
  IDEE_START_INCR_WR_A           :bit1;
  IDEE_START_INCR_WR_B           :bit1;
  IDEE_WRITE2FIFO                :bit1;
  IDEE_READ_FIFO_ENTRY_DE        :bit1;
  IDEE_READ_FIFO_ENTRY_DE_B      :bit1;
  IDEE_READ_FIFO_DE              :bit1;
  IDEE_READ_FIFO_DE_B            :bit1;
  IDEE_READ_FIFO_ENABLE          :bit1;
  IDEE_CRTC1_CNTL_CAPTURE_START_A:bit1;
  IDEE_CRC_PHASE                 :bit1;
  RESERVED0                      :bit11;
 end;

 TMVP_DEBUG_15=bitpacked record
  IDEF_MVP_ASYNC_FIFO_WEN  :bit1;
  RESERVED0                :bit3;
  IDEF_MVP_ASYNC_FIFO_WDATA:bit28;
 end;

 TMVP_DEBUG_16=bitpacked record
  IDCC_MVP_ASYNC_FIFO_READ              :bit1;
  IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL :bit1;
  IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL:bit1;
  IDCC_FLOW_CONTROL_OUT                 :bit1;
  IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES       :bit8;
  IDCC_MVP_ASYNC_FIFO_OVERFLOW          :bit1;
  IDCC_MVP_ASYNC_FIFO_UNDERFLOW         :bit1;
  RESERVED0                             :bit2;
  IDCC_MVP_ASYNC_READ_ADDR              :bit8;
  IDCC_MVP_ASYNC_WRITE_ADDR             :bit8;
 end;

 TMVP_DEBUG_17=bitpacked record
  IDCD_MVP_ASYNC_FIFO_READ     :bit1;
  IDCD_MVP_ASYNC_FIFO_PHASE    :bit1;
  IDCD_MVP_ASYNC_FIFO_READ_DATA:bit30;
 end;

 TOVL_CONTROL1=bitpacked record
  OVL_DEPTH                     :bit2;
  OVL_NUM_BANKS                 :bit2;
  OVL_Z                         :bit2;
  OVL_BANK_WIDTH                :bit2;
  OVL_FORMAT                    :bit3;
  OVL_BANK_HEIGHT               :bit2;
  OVL_TILE_SPLIT                :bit3;
  OVL_ADDRESS_TRANSLATION_ENABLE:bit1;
  OVL_PRIVILEGED_ACCESS_ENABLE  :bit1;
  OVL_MACRO_TILE_ASPECT         :bit2;
  OVL_ARRAY_MODE                :bit4;
  OVL_COLOR_EXPANSION_MODE      :bit1;
  OVL_PIPE_CONFIG               :bit5;
  OVL_MICRO_TILE_MODE           :bit2;
 end;

 TOVL_CONTROL2=bitpacked record
  OVL_HALF_RESOLUTION_ENABLE:bit1;
  RESERVED0                 :bit31;
 end;

 TPB0_HW_DEBUG=bitpacked record
  HW_00_DEBUG:bit1;
  HW_01_DEBUG:bit1;
  HW_02_DEBUG:bit1;
  HW_03_DEBUG:bit1;
  HW_04_DEBUG:bit1;
  HW_05_DEBUG:bit1;
  HW_06_DEBUG:bit1;
  HW_07_DEBUG:bit1;
  HW_08_DEBUG:bit1;
  HW_09_DEBUG:bit1;
  HW_10_DEBUG:bit1;
  HW_11_DEBUG:bit1;
  HW_12_DEBUG:bit1;
  HW_13_DEBUG:bit1;
  HW_14_DEBUG:bit1;
  HW_15_DEBUG:bit1;
  HW_16_DEBUG:bit1;
  HW_17_DEBUG:bit1;
  HW_18_DEBUG:bit1;
  HW_19_DEBUG:bit1;
  HW_20_DEBUG:bit1;
  HW_21_DEBUG:bit1;
  HW_22_DEBUG:bit1;
  HW_23_DEBUG:bit1;
  HW_24_DEBUG:bit1;
  HW_25_DEBUG:bit1;
  HW_26_DEBUG:bit1;
  HW_27_DEBUG:bit1;
  HW_28_DEBUG:bit1;
  HW_29_DEBUG:bit1;
  HW_30_DEBUG:bit1;
  HW_31_DEBUG:bit1;
 end;

 TPB0_PIF_CTRL=bitpacked record
  PIF_PLL_PWRDN_EN          :bit1;
  DTM_FORCE_FREQDIV_X1      :bit1;
  PIF_PLL_HNDSHK_EARLY_ABORT:bit1;
  PIF_PLL_PWRDN_EARLY_EXIT  :bit1;
  PHY_RST_PWROK_VDD         :bit1;
  RESERVED0                 :bit1;
  PIF_PLL_STATUS            :bit2;
  PIF_PLL_DEGRADE_OFF_VOTE  :bit1;
  PIF_PLL_UNUSED_OFF_VOTE   :bit1;
  PIF_PLL_DEGRADE_S2_VOTE   :bit1;
  RESERVED1                 :bit21;
 end;

 TPB1_HW_DEBUG=bitpacked record
  HW_00_DEBUG:bit1;
  HW_01_DEBUG:bit1;
  HW_02_DEBUG:bit1;
  HW_03_DEBUG:bit1;
  HW_04_DEBUG:bit1;
  HW_05_DEBUG:bit1;
  HW_06_DEBUG:bit1;
  HW_07_DEBUG:bit1;
  HW_08_DEBUG:bit1;
  HW_09_DEBUG:bit1;
  HW_10_DEBUG:bit1;
  HW_11_DEBUG:bit1;
  HW_12_DEBUG:bit1;
  HW_13_DEBUG:bit1;
  HW_14_DEBUG:bit1;
  HW_15_DEBUG:bit1;
  HW_16_DEBUG:bit1;
  HW_17_DEBUG:bit1;
  HW_18_DEBUG:bit1;
  HW_19_DEBUG:bit1;
  HW_20_DEBUG:bit1;
  HW_21_DEBUG:bit1;
  HW_22_DEBUG:bit1;
  HW_23_DEBUG:bit1;
  HW_24_DEBUG:bit1;
  HW_25_DEBUG:bit1;
  HW_26_DEBUG:bit1;
  HW_27_DEBUG:bit1;
  HW_28_DEBUG:bit1;
  HW_29_DEBUG:bit1;
  HW_30_DEBUG:bit1;
  HW_31_DEBUG:bit1;
 end;

 TPB1_PIF_CTRL=bitpacked record
  PIF_PLL_PWRDN_EN          :bit1;
  DTM_FORCE_FREQDIV_X1      :bit1;
  PIF_PLL_HNDSHK_EARLY_ABORT:bit1;
  PIF_PLL_PWRDN_EARLY_EXIT  :bit1;
  PHY_RST_PWROK_VDD         :bit1;
  RESERVED0                 :bit1;
  PIF_PLL_STATUS            :bit2;
  PIF_PLL_DEGRADE_OFF_VOTE  :bit1;
  PIF_PLL_UNUSED_OFF_VOTE   :bit1;
  PIF_PLL_DEGRADE_S2_VOTE   :bit1;
  RESERVED1                 :bit21;
 end;

 TPCIE_ACS_CAP=bitpacked record
  SOURCE_VALIDATION         :bit1;
  TRANSLATION_BLOCKING      :bit1;
  P2P_REQUEST_REDIRECT      :bit1;
  P2P_COMPLETION_REDIRECT   :bit1;
  UPSTREAM_FORWARDING       :bit1;
  P2P_EGRESS_CONTROL        :bit1;
  DIRECT_TRANSLATED_P2P     :bit1;
  RESERVED0                 :bit1;
  EGRESS_CONTROL_VECTOR_SIZE:bit8;
  RESERVED1                 :bit16;
 end;

 TPCIE_ARI_CAP=bitpacked record
  ARI_MFVC_FUNC_GROUPS_CAP:bit1;
  ARI_ACS_FUNC_GROUPS_CAP :bit1;
  RESERVED0               :bit6;
  ARI_NEXT_FUNC_NUM       :bit8;
  RESERVED1               :bit16;
 end;

 TPCIE_ATS_CAP=bitpacked record
  INVALIDATE_Q_DEPTH         :bit5;
  PAGE_ALIGNED_REQUEST       :bit1;
  GLOBAL_INVALIDATE_SUPPORTED:bit1;
  RESERVED0                  :bit25;
 end;

 TPCIE_CI_CNTL=bitpacked record
  RESERVED0                         :bit2;
  CI_SLAVE_SPLIT_MODE               :bit1;
  CI_SLAVE_GEN_USR_DIS              :bit1;
  CI_MST_CMPL_DUMMY_DATA            :bit1;
  RESERVED1                         :bit1;
  CI_SLV_RC_RD_REQ_SIZE             :bit2;
  CI_SLV_ORDERING_DIS               :bit1;
  CI_RC_ORDERING_DIS                :bit1;
  CI_SLV_CPL_ALLOC_DIS              :bit1;
  CI_SLV_CPL_ALLOC_MODE             :bit1;
  CI_SLV_CPL_ALLOC_SOR              :bit1;
  CI_MST_IGNORE_PAGE_ALIGNED_REQUEST:bit1;
  RESERVED2                         :bit18;
 end;

 TPCIE_DPA_CAP=bitpacked record
  SUBSTATE_MAX   :bit5;
  RESERVED0      :bit3;
  TRANS_LAT_UNIT :bit2;
  RESERVED1      :bit2;
  PWR_ALLOC_SCALE:bit2;
  RESERVED2      :bit2;
  TRANS_LAT_VAL_0:bit8;
  TRANS_LAT_VAL_1:bit8;
 end;

 TPCIE_INDEX_2=bit32;

 TPCIE_LC_CNTL=bitpacked record
  RESERVED0                 :bit1;
  LC_DONT_ENTER_L23_IN_D0   :bit1;
  LC_RESET_L_IDLE_COUNT_EN  :bit1;
  LC_RESET_LINK             :bit1;
  LC_16X_CLEAR_TX_PIPE      :bit4;
  LC_L0S_INACTIVITY         :bit4;
  LC_L1_INACTIVITY          :bit4;
  LC_PMI_TO_L1_DIS          :bit1;
  LC_INC_N_FTS_EN           :bit1;
  LC_LOOK_FOR_IDLE_IN_L1L23 :bit2;
  LC_FACTOR_IN_EXT_SYNC     :bit1;
  LC_WAIT_FOR_PM_ACK_DIS    :bit1;
  LC_WAKE_FROM_L23          :bit1;
  LC_L1_IMMEDIATE_ACK       :bit1;
  LC_ASPM_TO_L1_DIS         :bit1;
  LC_DELAY_COUNT            :bit2;
  LC_DELAY_L0S_EXIT         :bit1;
  LC_DELAY_L1_EXIT          :bit1;
  LC_EXTEND_WAIT_FOR_EL_IDLE:bit1;
  LC_ESCAPE_L1L23_EN        :bit1;
  LC_GATE_RCVR_IDLE         :bit1;
 end;

 TPCIE_LTR_CAP=bitpacked record
  LTR_MAX_S_LATENCY_VALUE :bit10;
  LTR_MAX_S_LATENCY_SCALE :bit3;
  RESERVED0               :bit3;
  LTR_MAX_NS_LATENCY_VALUE:bit10;
  LTR_MAX_NS_LATENCY_SCALE:bit3;
  RESERVED1               :bit3;
 end;

 TPCIE_MC_CNTL=bitpacked record
  MC_NUM_GROUP:bit6;
  RESERVED0   :bit9;
  MC_ENABLE   :bit1;
  RESERVED1   :bit16;
 end;

 TPCIE_MC_RCV0=bit32;

 TPCIE_MC_RCV1=bit32;

 TPCIE_RX_CNTL=bitpacked record
  RX_IGNORE_IO_ERR          :bit1;
  RX_IGNORE_BE_ERR          :bit1;
  RX_IGNORE_MSG_ERR         :bit1;
  RX_IGNORE_CRC_ERR         :bit1;
  RX_IGNORE_CFG_ERR         :bit1;
  RX_IGNORE_CPL_ERR         :bit1;
  RX_IGNORE_EP_ERR          :bit1;
  RX_IGNORE_LEN_MISMATCH_ERR:bit1;
  RX_IGNORE_MAX_PAYLOAD_ERR :bit1;
  RX_IGNORE_TC_ERR          :bit1;
  RX_IGNORE_CFG_UR          :bit1;
  RX_IGNORE_IO_UR           :bit1;
  RX_IGNORE_AT_ERR          :bit1;
  RX_NAK_IF_FIFO_FULL       :bit1;
  RX_GEN_ONE_NAK            :bit1;
  RX_FC_INIT_FROM_REG       :bit1;
  RX_RCB_CPL_TIMEOUT        :bit3;
  RX_RCB_CPL_TIMEOUT_MODE   :bit1;
  RX_PCIE_CPL_TIMEOUT_DIS   :bit1;
  RX_IGNORE_SHORTPREFIX_ERR :bit1;
  RX_IGNORE_MAXPREFIX_ERR   :bit1;
  RX_IGNORE_CPLPREFIX_ERR   :bit1;
  RX_IGNORE_INVALIDPASID_ERR:bit1;
  RX_IGNORE_NOT_PASID_UR    :bit1;
  RX_TPH_DIS                :bit1;
  RX_RCB_FLR_TIMEOUT_DIS    :bit1;
  RESERVED0                 :bit4;
 end;

 TPCIE_SCRATCH=bit32;

 TPCIE_TX_CNTL=bitpacked record
  RESERVED0               :bit10;
  TX_SNR_OVERRIDE         :bit2;
  TX_RO_OVERRIDE          :bit2;
  TX_PACK_PACKET_DIS      :bit1;
  TX_FLUSH_TLP_DIS        :bit1;
  RESERVED1               :bit4;
  TX_CPL_PASS_P           :bit1;
  TX_NP_PASS_P            :bit1;
  TX_CLEAR_EXTRA_PM_REQS  :bit1;
  TX_FC_UPDATE_TIMEOUT_DIS:bit1;
  TX_F0_TPH_DIS           :bit1;
  TX_F1_TPH_DIS           :bit1;
  TX_F2_TPH_DIS           :bit1;
  RESERVED2               :bit5;
 end;

 TPERFMON_CNTL=bitpacked record
  PERFMON_STATE            :bit2;
  PERFMON_RUN_ENABLE_SEL   :bit6;
  PERFMON_RPT_COUNT        :bit20;
  PERFMON_CNTOFF_AND_OR    :bit1;
  PERFMON_CNTOFF_INT_EN    :bit1;
  PERFMON_CNTOFF_INT_STATUS:bit1;
  PERFMON_CNTOFF_INT_ACK   :bit1;
 end;

 TPHY_AUX_CNTL=bitpacked record
  AUXSLAVE_PAD_SLEWN :bit1;
  AUXSLAVE_PAD_WAKE  :bit1;
  AUXSLAVE_PAD_RXSEL :bit1;
  AUXSLAVE_PAD_MODE  :bit1;
  DDCSLAVE_DATA_PD_EN:bit1;
  DDCSLAVE_DATA_EN   :bit1;
  DDCSLAVE_CLK_PD_EN :bit1;
  DDCSLAVE_CLK_EN    :bit1;
  RESERVED0          :bit4;
  AUX_PAD_SLEWN      :bit1;
  AUXSLAVE_CLK_PD_EN :bit1;
  AUX_PAD_WAKE       :bit1;
  RESERVED1          :bit1;
  AUX_PAD_RXSEL      :bit1;
  RESERVED2          :bit15;
 end;

 TPLL_POST_DIV=bitpacked record
  PLL_POST_DIV_PIXCLK     :bit7;
  PLL_POST_DIV1P5_DISPCLK :bit1;
  PLL_POST_DIV_DVOCLK     :bit7;
  PLL_POST_DIV1P5_DPREFCLK:bit1;
  PLL_POST_DIV_IDCLK      :bit7;
  RESERVED0               :bit9;
 end;

 TPLL_XOR_LOCK=bitpacked record
  PLL_XOR_LOCK                     :bit1;
  PLL_XOR_LOCK_READBACK            :bit1;
  RESERVED0                        :bit6;
  PLL_SPARE                        :bit6;
  RESERVED1                        :bit2;
  PLL_LOCK_COUNT_SEL               :bit4;
  PLL_LOCK_DETECTOR_RESOLUTION_FREF:bit3;
  PLL_LOCK_DETECTOR_RESOLUTION_FFB :bit3;
  PLL_LOCK_DETECTOR_OPAMP_BIAS     :bit2;
  PLL_FAST_LOCK_MODE_EN            :bit1;
  RESERVED2                        :bit3;
 end;

 TPMI_CAP_LIST=bitpacked record
  CAP_ID   :bit8;
  NEXT_PTR :bit8;
  RESERVED0:bit16;
 end;

 TPWR_AVFS_SEL=bitpacked record
  AvfsSel  :bit28;
  RESERVED0:bit4;
 end;

 TPWR_CKS_CNTL=bitpacked record
  CKS_BYPASS              :bit1;
  CKS_PCCEnable           :bit1;
  CKS_TEMP_COMP           :bit1;
  CKS_STRETCH_AMOUNT      :bit4;
  CKS_SKIP_PHASE_BYPASS   :bit1;
  CKS_SAMPLE_SIZE         :bit4;
  CKS_FSM_WAIT_CYCLES     :bit4;
  CKS_USE_FOR_LOW_FREQ    :bit1;
  CKS_NO_EXTRA_COARSE_STEP:bit1;
  CKS_LDO_REFSEL          :bit4;
  DDT_DEBUS_SEL           :bit1;
  CKS_LDO_READY_COUNT_VAL :bit8;
  RESERVED0               :bit1;
 end;

 TRINGOSC_MASK=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TRIRB_CONTROL=bitpacked record
  RESPONSE_INTERRUPT_CONTROL        :bit1;
  RIRB_DMA_ENABLE                   :bit1;
  RESPONSE_OVERRUN_INTERRUPT_CONTROL:bit1;
  RESERVED0                         :bit29;
 end;

 TRLC_GPM_STAT=bitpacked record
  RLC_BUSY                         :bit1;
  GFX_POWER_STATUS                 :bit1;
  GFX_CLOCK_STATUS                 :bit1;
  GFX_LS_STATUS                    :bit1;
  GFX_PIPELINE_POWER_STATUS        :bit1;
  CNTX_IDLE_BEING_PROCESSED        :bit1;
  CNTX_BUSY_BEING_PROCESSED        :bit1;
  GFX_IDLE_BEING_PROCESSED         :bit1;
  CMP_BUSY_BEING_PROCESSED         :bit1;
  SAVING_REGISTERS                 :bit1;
  RESTORING_REGISTERS              :bit1;
  GFX3D_BLOCKS_CHANGING_POWER_STATE:bit1;
  CMP_BLOCKS_CHANGING_POWER_STATE  :bit1;
  STATIC_CU_POWERING_UP            :bit1;
  STATIC_CU_POWERING_DOWN          :bit1;
  DYN_CU_POWERING_UP               :bit1;
  DYN_CU_POWERING_DOWN             :bit1;
  ABORTED_PD_SEQUENCE              :bit1;
  RESERVED                         :bit6;
  PG_ERROR_STATUS                  :bit8;
 end;

 TRLC_GPR_REG1=bit32;

 TRLC_GPR_REG2=bit32;

 TRLC_PG_DELAY=bitpacked record
  POWER_UP_DELAY     :bit8;
  POWER_DOWN_DELAY   :bit8;
  CMD_PROPAGATE_DELAY:bit8;
  MEM_SLEEP_DELAY    :bit8;
 end;

 TRLC_ROM_CNTL=bitpacked record
  USE_ROM         :bit1;
  SLP_MODE_EN     :bit1;
  EFUSE_DISTRIB_EN:bit1;
  HELLOWORLD_EN   :bit1;
  CU_HARVEST_EN   :bit1;
  RESERVED        :bit27;
 end;

 TRLC_SPM_VMID=bitpacked record
  RLC_SPM_VMID:bit4;
  RESERVED0   :bit28;
 end;

 TRLC_SRM_CNTL=bitpacked record
  SRM_ENABLE    :bit1;
  AUTO_INCR_ADDR:bit1;
  RESERVED      :bit30;
 end;

 TRLC_SRM_STAT=bitpacked record
  SRM_STATUS:bit1;
  RESERVED  :bit31;
 end;

 TSCLK_MIN_DIV=bitpacked record
  FRACV    :bit12;
  INTV     :bit7;
  RESERVED0:bit13;
 end;

 TSCLV_CONTROL=bitpacked record
  SCL_BOUNDARY_MODE :bit1;
  RESERVED0         :bit3;
  SCL_EARLY_EOL_MODE:bit1;
  RESERVED1         :bit3;
  SCL_TOTAL_PHASE   :bit1;
  RESERVED2         :bit23;
 end;

 TSCRATCH_ADDR=bit32;

 TSCRATCH_REG0=bit32;

 TSCRATCH_REG1=bit32;

 TSCRATCH_REG2=bit32;

 TSCRATCH_REG3=bit32;

 TSCRATCH_REG4=bit32;

 TSCRATCH_REG5=bit32;

 TSCRATCH_REG6=bit32;

 TSCRATCH_REG7=bit32;

 TSCRATCH_UMSK=bitpacked record
  OBSOLETE_UMSK:bit8;
  RESERVED0    :bit8;
  OBSOLETE_SWAP:bit2;
  RESERVED1    :bit14;
 end;

 TSDMA0_FREEZE=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit3;
  FREEZE    :bit1;
  FROZEN    :bit1;
  F32_FREEZE:bit1;
  RESERVED2 :bit25;
 end;

 TSDMA1_CONFIG=bitpacked record
  RESERVED0     :bit8;
  SDMA_RDREQ_URG:bit4;
  RESERVED1     :bit4;
  SDMA_REQ_TRAN :bit1;
  RESERVED2     :bit15;
 end;

 TSDMA1_FREEZE=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit3;
  FREEZE    :bit1;
  FROZEN    :bit1;
  F32_FREEZE:bit1;
  RESERVED2 :bit25;
 end;

 TSH_MEM_BASES=bitpacked record
  PRIVATE_BASE:bit16;
  SHARED_BASE :bit16;
 end;

 TSMC_IND_DATA=bit32;

 TSMC_SCRATCH9=bit32;

 TSPI_DSM_CNTL=bitpacked record
  Sel_DSM_SPI_Irritator_data0:bit1;
  Sel_DSM_SPI_Irritator_data1:bit1;
  SPI_Enable_Single_Write    :bit1;
  UNUSED                     :bit29;
 end;

 TSPI_GFX_CNTL=bitpacked record
  RESET_COUNTS:bit1;
  RESERVED0   :bit31;
 end;

 TSQC_DSM_CNTL=bitpacked record
  SEL_DATA_ICACHE_BANKA     :bit2;
  EN_SINGLE_WR_ICACHE_BANKA :bit1;
  SEL_DATA_ICACHE_BANKB     :bit2;
  EN_SINGLE_WR_ICACHE_BANKB :bit1;
  SEL_DATA_ICACHE_BANKC     :bit2;
  EN_SINGLE_WR_ICACHE_BANKC :bit1;
  SEL_DATA_ICACHE_BANKD     :bit2;
  EN_SINGLE_WR_ICACHE_BANKD :bit1;
  SEL_DATA_ICACHE_GATCL1    :bit2;
  EN_SINGLE_WR_ICACHE_GATCL1:bit1;
  SEL_DATA_DCACHE_BANKA     :bit2;
  EN_SINGLE_WR_DCACHE_BANKA :bit1;
  SEL_DATA_DCACHE_BANKB     :bit2;
  EN_SINGLE_WR_DCACHE_BANKB :bit1;
  SEL_DATA_DCACHE_BANKC     :bit2;
  EN_SINGLE_WR_DCACHE_BANKC :bit1;
  SEL_DATA_DCACHE_BANKD     :bit2;
  EN_SINGLE_WR_DCACHE_BANKD :bit1;
  SEL_DATA_DCACHE_GATCL1    :bit2;
  EN_SINGLE_WR_DCACHE_GATCL1:bit1;
  RESERVED0                 :bit2;
 end;

 TSQ_IND_INDEX=bitpacked record
  WAVE_ID     :bit4;
  SIMD_ID     :bit2;
  THREAD_ID   :bit6;
  AUTO_INCR   :bit1;
  FORCE_READ  :bit1;
  READ_TIMEOUT:bit1;
  UNINDEXED   :bit1;
  INDEX       :bit16;
 end;

 TSQ_WAVE_MODE=bitpacked record
  FP_ROUND   :bit4;
  FP_DENORM  :bit4;
  DX10_CLAMP :bit1;
  IEEE       :bit1;
  LOD_CLAMPED:bit1;
  DEBUG_EN   :bit1;
  EXCP_EN    :bit9;
  RESERVED0  :bit6;
  GPR_IDX_EN :bit1;
  VSKIP      :bit1;
  CSP        :bit3;
 end;

 TSRBM_INT_ACK=bitpacked record
  RDERR_INT_ACK:bit1;
  RAERR_INT_ACK:bit1;
  RESERVED0    :bit30;
 end;

 TSRBM_STATUS2=bitpacked record
  SDMA_RQ_PENDING  :bit1;
  TST_RQ_PENDING   :bit1;
  SDMA1_RQ_PENDING :bit1;
  VCE0_RQ_PENDING  :bit1;
  VP8_BUSY         :bit1;
  SDMA_BUSY        :bit1;
  SDMA1_BUSY       :bit1;
  VCE0_BUSY        :bit1;
  XDMA_BUSY        :bit1;
  CHUB_BUSY        :bit1;
  SDMA2_BUSY       :bit1;
  SDMA3_BUSY       :bit1;
  SAMSCP_BUSY      :bit1;
  ISP_BUSY         :bit1;
  VCE1_BUSY        :bit1;
  ODE_BUSY         :bit1;
  SDMA2_RQ_PENDING :bit1;
  SDMA3_RQ_PENDING :bit1;
  SAMSCP_RQ_PENDING:bit1;
  ISP_RQ_PENDING   :bit1;
  VCE1_RQ_PENDING  :bit1;
  RESERVED0        :bit11;
 end;

 TSRBM_STATUS3=bitpacked record
  MCC0_BUSY:bit1;
  MCC1_BUSY:bit1;
  MCC2_BUSY:bit1;
  MCC3_BUSY:bit1;
  MCC4_BUSY:bit1;
  MCC5_BUSY:bit1;
  MCC6_BUSY:bit1;
  MCC7_BUSY:bit1;
  MCD0_BUSY:bit1;
  MCD1_BUSY:bit1;
  MCD2_BUSY:bit1;
  MCD3_BUSY:bit1;
  MCD4_BUSY:bit1;
  MCD5_BUSY:bit1;
  MCD6_BUSY:bit1;
  MCD7_BUSY:bit1;
  RESERVED0:bit1;
  RESERVED1:bit15;
 end;

 TTA_CGTT_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TTCC_DSM_CNTL=bitpacked record
  CACHE_RAM_IRRITATOR_DATA_SEL    :bit2;
  CACHE_RAM_IRRITATOR_SINGLE_WRITE:bit1;
  RESERVED0                       :bit29;
 end;

 TTCP_DSM_CNTL=bitpacked record
  CACHE_RAM_IRRITATOR_DATA_SEL    :bit2;
  CACHE_RAM_IRRITATOR_SINGLE_WRITE:bit1;
  LFIFO_RAM_IRRITATOR_DATA_SEL    :bit2;
  LFIFO_RAM_IRRITATOR_SINGLE_WRITE:bit1;
  RESERVED0                       :bit26;
 end;

 TTD_CGTT_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TTHM_CLK_CNTL=bitpacked record
  CMON_CLK_SEL      :bit8;
  TMON_CLK_SEL      :bit8;
  CTF_CLK_SHUTOFF_EN:bit1;
  RESERVED0         :bit15;
 end;

 TUNIPHY_DEBUG=bitpacked record
  RESERVED0:bit12;
  DEBUG0   :bit10;
  DEBUG1   :bit3;
  DBG_SEL  :bit2;
  RESERVED1:bit5;
 end;

 TUNP_CRC_LAST=bit32;

 TUNP_CRC_MASK=bit32;

 TURGENCY_STAT=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit7;
  RESERVED2:bit12;
  RESERVED3:bit12;
 end;

 TUVD_CGC_CTRL=bitpacked record
  DYN_CLOCK_MODE    :bit1;
  JPEG2_MODE        :bit1;
  CLK_GATE_DLY_TIMER:bit4;
  CLK_OFF_DELAY     :bit5;
  UDEC_RE_MODE      :bit1;
  UDEC_CM_MODE      :bit1;
  UDEC_IT_MODE      :bit1;
  UDEC_DB_MODE      :bit1;
  UDEC_MP_MODE      :bit1;
  SYS_MODE          :bit1;
  UDEC_MODE         :bit1;
  MPEG2_MODE        :bit1;
  REGS_MODE         :bit1;
  RBC_MODE          :bit1;
  LMI_MC_MODE       :bit1;
  LMI_UMC_MODE      :bit1;
  IDCT_MODE         :bit1;
  MPRD_MODE         :bit1;
  MPC_MODE          :bit1;
  LBSI_MODE         :bit1;
  LRBBM_MODE        :bit1;
  WCB_MODE          :bit1;
  VCPU_MODE         :bit1;
  SCPU_MODE         :bit1;
  JPEG_MODE         :bit1;
 end;

 TUVD_CGC_GATE=bitpacked record
  SYS      :bit1;
  UDEC     :bit1;
  MPEG2    :bit1;
  REGS     :bit1;
  RBC      :bit1;
  LMI_MC   :bit1;
  LMI_UMC  :bit1;
  IDCT     :bit1;
  MPRD     :bit1;
  MPC      :bit1;
  LBSI     :bit1;
  LRBBM    :bit1;
  UDEC_RE  :bit1;
  UDEC_CM  :bit1;
  UDEC_IT  :bit1;
  UDEC_DB  :bit1;
  UDEC_MP  :bit1;
  WCB      :bit1;
  VCPU     :bit1;
  SCPU     :bit1;
  JPEG     :bit1;
  JPEG2    :bit1;
  RESERVED0:bit10;
 end;

 TUVD_CTX_DATA=bit32;

 TUVD_LMI_CTRL=bitpacked record
  WRITE_CLEAN_TIMER        :bit8;
  WRITE_CLEAN_TIMER_EN     :bit1;
  REQ_MODE                 :bit1;
  RESERVED0                :bit1;
  ASSERT_MC_URGENT         :bit1;
  MASK_MC_URGENT           :bit1;
  DATA_COHERENCY_EN        :bit1;
  CRC_RESET                :bit1;
  CRC_SEL                  :bit5;
  DISABLE_ON_FWV_FAIL      :bit1;
  VCPU_DATA_COHERENCY_EN   :bit1;
  CM_DATA_COHERENCY_EN     :bit1;
  DB_DB_DATA_COHERENCY_EN  :bit1;
  DB_IT_DATA_COHERENCY_EN  :bit1;
  IT_IT_DATA_COHERENCY_EN  :bit1;
  MIF_MIF_DATA_COHERENCY_EN:bit1;
  RFU                      :bit5;
 end;

 TUVD_MPC_CNTL=bitpacked record
  RESERVED0       :bit3;
  REPLACEMENT_MODE:bit3;
  PERF_RST        :bit1;
  RESERVED1       :bit1;
  DBG_MUX         :bit4;
  RESERVED2       :bit4;
  AVE_WEIGHT      :bit2;
  URGENT_EN       :bit1;
  RESERVED3       :bit13;
 end;

 TUVD_SEMA_CMD=bitpacked record
  REQ_CMD  :bit4;
  WR_PHASE :bit2;
  MODE     :bit1;
  VMID_EN  :bit1;
  VMID     :bit4;
  RESERVED0:bit20;
 end;

 TVCE_LMI_CTRL=bitpacked record
  RESERVED0             :bit11;
  RESERVED1             :bit1;
  RESERVED2             :bit1;
  RESERVED3             :bit1;
  RESERVED4             :bit1;
  RESERVED5             :bit5;
  RESERVED6             :bit1;
  VCPU_DATA_COHERENCY_EN:bit1;
  RESERVED7             :bit1;
  RESERVED8             :bit1;
  RESERVED9             :bit1;
  RESERVED10            :bit7;
 end;

 TVCE_RB_RPTR2=bitpacked record
  RESERVED0:bit4;
  RB_RPTR  :bit19;
  RESERVED1:bit9;
 end;

 TVCE_RB_RPTR3=bitpacked record
  RESERVED0:bit4;
  RB_RPTR  :bit19;
  RESERVED1:bit9;
 end;

 TVCE_RB_SIZE2=bitpacked record
  RESERVED0:bit4;
  RB_SIZE  :bit19;
  RESERVED1:bit9;
 end;

 TVCE_RB_SIZE3=bitpacked record
  RESERVED0:bit4;
  RB_SIZE  :bit19;
  RESERVED1:bit9;
 end;

 TVCE_RB_WPTR2=bitpacked record
  RESERVED0:bit4;
  RB_WPTR  :bit19;
  RESERVED1:bit9;
 end;

 TVCE_RB_WPTR3=bitpacked record
  RESERVED0:bit4;
  RB_WPTR  :bit19;
  RESERVED1:bit9;
 end;

 TVGA_HW_DEBUG=bit32;

 TVGT_DMA_BASE=bit32;

 TVGT_DMA_SIZE=bit32;

 TVGT_HOS_CNTL=bitpacked record
  TESS_MODE:bit2;
  RESERVED0:bit30;
 end;

 TVGT_TF_PARAM=bitpacked record
  _TYPE                :bit2;
  PARTITIONING         :bit3;
  TOPOLOGY             :bit3;
  RESERVED0            :bit1;
  DEPRECATED           :bit1;
  NUM_DS_WAVES_PER_SIMD:bit4;
  DISABLE_DONUTS       :bit1;
  RDREQ_POLICY         :bit2;
  DISTRIBUTION_MODE    :bit2;
  MTYPE                :bit2;
  RESERVED1            :bit11;
 end;

 TVLINE_STATUS=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit3;
  RESERVED2:bit1;
  RESERVED3:bit7;
  RESERVED4:bit1;
  RESERVED5:bit3;
  RESERVED6:bit1;
  RESERVED7:bit1;
  RESERVED8:bit14;
 end;

 TVM_L2_STATUS=bitpacked record
  L2_BUSY            :bit1;
  CONTEXT_DOMAIN_BUSY:bit16;
  RESERVED0          :bit15;
 end;

 TWB_EC_CONFIG=bitpacked record
  DISPCLK_R_WB_GATE_DIS    :bit1;
  DISPCLK_G_WB_GATE_DIS    :bit1;
  DISPCLK_G_WBSCL_GATE_DIS :bit1;
  DISPCLK_R_WB_RAMP_DIS    :bit1;
  DISPCLK_G_WB_RAMP_DIS    :bit1;
  DISPCLK_G_WBSCL_RAMP_DIS :bit1;
  WB_LB_LS_DIS             :bit1;
  WB_LB_SD_DIS             :bit1;
  WB_LUT_LS_DIS            :bit1;
  WBSCL_LB_MEM_PWR_MODE_SEL:bit2;
  RESERVED0                :bit1;
  WB_TEST_CLK_SEL          :bit4;
  WBSCL_LB_MEM_PWR_DIS     :bit1;
  WBSCL_LB_MEM_PWR_FORCE   :bit2;
  WBSCL_LB_MEM_PWR_STATE   :bit2;
  RESERVED1                :bit2;
  WB_RAM_PW_SAVE_MODE      :bit1;
  RESERVED2                :bit4;
  LB_MEM_PWR_STATE         :bit2;
  LUT_MEM_PWR_STATE        :bit2;
 end;

 TALPHA_CONTROL=bitpacked record
  ALPHA_ROUND_TRUNC_MODE:bit1;
  CURSOR_ALPHA_BLND_ENA :bit1;
  RESERVED0             :bit30;
 end;

 TATC_ATS_DEBUG=bitpacked record
  INVALIDATE_ALL                                       :bit1;
  IDENT_RETURN                                         :bit1;
  ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS              :bit1;
  RESERVED0                                            :bit2;
  PAGE_REQUESTS_USE_RELAXED_ORDERING                   :bit1;
  PRIV_BIT                                             :bit1;
  EXE_BIT                                              :bit1;
  PAGE_REQUEST_PERMS                                   :bit1;
  UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE                :bit1;
  NUM_REQUESTS_AT_ERR                                  :bit4;
  DISALLOW_ERR_TO_DONE                                 :bit1;
  IGNORE_FED                                           :bit1;
  INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED:bit1;
  DEBUG_BUS_SELECT                                     :bit1;
  DISABLE_INVALIDATE_PER_DOMAIN                        :bit1;
  DISABLE_VMID0_PASID_MAPPING                          :bit1;
  DISABLE_INVALIDATION_ON_WORLD_SWITCH                 :bit1;
  ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT :bit1;
  RESERVED1                                            :bit10;
 end;

 TATC_L2_DEBUG2=bitpacked record
  EFFECTIVE_CACHE_SIZE                  :bit5;
  EFFECTIVE_WORK_QUEUE_SIZE             :bit3;
  FORCE_CACHE_MISS                      :bit1;
  INVALIDATE_ALL                        :bit1;
  DISABLE_2M_CACHE                      :bit1;
  DISABLE_CACHING_SPECULATIVE_RETURNS   :bit1;
  RESERVED0                             :bit2;
  DISABLE_CACHING_FAULT_RETURNS         :bit1;
  DEBUG_BUS_SELECT                      :bit2;
  DEBUG_ECO                             :bit2;
  EFFECTIVE_2M_CACHE_SIZE               :bit4;
  CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD:bit8;
  CLEAR_PARITY_ERROR_INFO               :bit1;
 end;

 TATC_L2_STATUS=bitpacked record
  BUSY             :bit1;
  PARITY_ERROR_INFO:bit29;
  RESERVED0        :bit2;
 end;

 TAUX_LS_STATUS=bitpacked record
  AUX_LS_DONE             :bit1;
  AUX_LS_REQ              :bit1;
  RESERVED0               :bit2;
  AUX_LS_RX_TIMEOUT_STATE :bit3;
  AUX_LS_RX_TIMEOUT       :bit1;
  AUX_LS_RX_OVERFLOW      :bit1;
  AUX_LS_HPD_DISCON       :bit1;
  AUX_LS_RX_PARTIAL_BYTE  :bit1;
  AUX_LS_NON_AUX_MODE     :bit1;
  AUX_LS_RX_MIN_COUNT_VIOL:bit1;
  RESERVED1               :bit1;
  AUX_LS_RX_INVALID_STOP  :bit1;
  RESERVED2               :bit2;
  AUX_LS_RX_SYNC_INVALID_L:bit1;
  AUX_LS_RX_SYNC_INVALID_H:bit1;
  AUX_LS_RX_INVALID_START :bit1;
  AUX_LS_RX_RECV_NO_DET   :bit1;
  RESERVED3               :bit1;
  AUX_LS_RX_RECV_INVALID_H:bit1;
  AUX_LS_RX_RECV_INVALID_L:bit1;
  AUX_LS_REPLY_BYTE_COUNT :bit5;
  AUX_LS_CP_IRQ           :bit1;
  AUX_LS_UPDATED          :bit1;
  AUX_LS_UPDATED_ACK      :bit1;
 end;

 TAUX_SW_STATUS=bitpacked record
  AUX_SW_DONE             :bit1;
  AUX_SW_REQ              :bit1;
  RESERVED0               :bit2;
  AUX_SW_RX_TIMEOUT_STATE :bit3;
  AUX_SW_RX_TIMEOUT       :bit1;
  AUX_SW_RX_OVERFLOW      :bit1;
  AUX_SW_HPD_DISCON       :bit1;
  AUX_SW_RX_PARTIAL_BYTE  :bit1;
  AUX_SW_NON_AUX_MODE     :bit1;
  AUX_SW_RX_MIN_COUNT_VIOL:bit1;
  RESERVED1               :bit1;
  AUX_SW_RX_INVALID_STOP  :bit1;
  RESERVED2               :bit2;
  AUX_SW_RX_SYNC_INVALID_L:bit1;
  AUX_SW_RX_SYNC_INVALID_H:bit1;
  AUX_SW_RX_INVALID_START :bit1;
  AUX_SW_RX_RECV_NO_DET   :bit1;
  RESERVED3               :bit1;
  AUX_SW_RX_RECV_INVALID_H:bit1;
  AUX_SW_RX_RECV_INVALID_L:bit1;
  AUX_SW_REPLY_BYTE_COUNT :bit5;
  RESERVED4               :bit1;
  AUX_ARB_STATUS          :bit2;
 end;

 TBIF_DEBUG_MUX=bitpacked record
  DEBUG_MUX_BLK1:bit6;
  RESERVED0     :bit2;
  DEBUG_MUX_BLK2:bit6;
  RESERVED1     :bit18;
 end;

 TBIF_DEBUG_OUT=bitpacked record
  DEBUG_OUTPUT:bit17;
  RESERVED0   :bit15;
 end;

 TBIF_SMU_INDEX=bitpacked record
  RESERVED0    :bit2;
  BIF_SMU_INDEX:bit17;
  RESERVED1    :bit13;
 end;

 TBLND_CONTROL2=bitpacked record
  PTI_ENABLE             :bit1;
  RESERVED0              :bit3;
  PTI_NEW_PIXEL_GAP      :bit2;
  BLND_NEW_PIXEL_MODE    :bit1;
  BLND_SUPERAA_DEGAMMA_EN:bit1;
  BLND_SUPERAA_REGAMMA_EN:bit1;
  RESERVED1              :bit23;
 end;

 TBX_RESET_CNTL=bitpacked record
  LINK_TRAIN_EN:bit1;
  RESERVED0    :bit31;
 end;

 TCB_BLEND_BLUE=bit32;

 TCB_DCC_CONFIG=bitpacked record
  OVERWRITE_COMBINER_DEPTH         :bit5;
  OVERWRITE_COMBINER_DISABLE       :bit1;
  OVERWRITE_COMBINER_CC_POP_DISABLE:bit1;
  RESERVED0                        :bit1;
  FC_RDLAT_KEYID_FIFO_DEPTH        :bit8;
  READ_RETURN_SKID_FIFO_DEPTH      :bit7;
  RESERVED1                        :bit1;
  DCC_CACHE_EVICT_POINT            :bit4;
  DCC_CACHE_NUM_TAGS               :bit4;
 end;

 TCB_HW_CONTROL=bitpacked record
  CM_CACHE_EVICT_POINT                            :bit4;
  RESERVED0                                       :bit2;
  FC_CACHE_EVICT_POINT                            :bit4;
  RESERVED1                                       :bit2;
  CC_CACHE_EVICT_POINT                            :bit4;
  ALLOW_MRT_WITH_DUAL_SOURCE                      :bit1;
  RESERVED2                                       :bit1;
  DISABLE_INTNORM_LE11BPC_CLAMPING                :bit1;
  FORCE_NEEDS_DST                                 :bit1;
  FORCE_ALWAYS_TOGGLE                             :bit1;
  DISABLE_BLEND_OPT_RESULT_EQ_DEST                :bit1;
  DISABLE_FULL_WRITE_MASK                         :bit1;
  DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG             :bit1;
  DISABLE_BLEND_OPT_DONT_RD_DST                   :bit1;
  DISABLE_BLEND_OPT_BYPASS                        :bit1;
  DISABLE_BLEND_OPT_DISCARD_PIXEL                 :bit1;
  DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED:bit1;
  PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT   :bit1;
  PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT:bit1;
  DISABLE_CC_IB_SERIALIZER_STATE_OPT              :bit1;
  DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE    :bit1;
 end;

 TCNV_TEST_CNTL=bitpacked record
  RESERVED0           :bit4;
  CNV_TEST_CRC_EN     :bit1;
  RESERVED1           :bit3;
  CNV_TEST_CRC_CONT_EN:bit1;
  RESERVED2           :bit7;
  CNV_TEST_CRC_DE_ONLY:bit1;
  RESERVED3           :bit15;
 end;

 TCOMPUTE_DIM_X=bit32;

 TCOMPUTE_DIM_Y=bit32;

 TCOMPUTE_DIM_Z=bit32;

 TCP_CEQ1_AVAIL=bitpacked record
  CEQ_CNT_RING:bit11;
  RESERVED0   :bit5;
  CEQ_CNT_IB1 :bit11;
  RESERVED1   :bit5;
 end;

 TCP_CEQ2_AVAIL=bitpacked record
  CEQ_CNT_IB2:bit11;
  RESERVED0  :bit21;
 end;

 TCP_CE_COUNTER=bit32;

 TCP_COHER_BASE=bit32;

 TCP_COHER_CNTL=bitpacked record
  DEST_BASE_0_ENA         :bit1;
  DEST_BASE_1_ENA         :bit1;
  TC_SD_ACTION_ENA        :bit1;
  TC_NC_ACTION_ENA        :bit1;
  RESERVED0               :bit2;
  CB0_DEST_BASE_ENA       :bit1;
  CB1_DEST_BASE_ENA       :bit1;
  CB2_DEST_BASE_ENA       :bit1;
  CB3_DEST_BASE_ENA       :bit1;
  CB4_DEST_BASE_ENA       :bit1;
  CB5_DEST_BASE_ENA       :bit1;
  CB6_DEST_BASE_ENA       :bit1;
  CB7_DEST_BASE_ENA       :bit1;
  DB_DEST_BASE_ENA        :bit1;
  TCL1_VOL_ACTION_ENA     :bit1;
  TC_VOL_ACTION_ENA       :bit1;
  RESERVED1               :bit1;
  TC_WB_ACTION_ENA        :bit1;
  DEST_BASE_2_ENA         :bit1;
  RESERVED2               :bit1;
  DEST_BASE_3_ENA         :bit1;
  TCL1_ACTION_ENA         :bit1;
  TC_ACTION_ENA           :bit1;
  RESERVED3               :bit1;
  CB_ACTION_ENA           :bit1;
  DB_ACTION_ENA           :bit1;
  SH_KCACHE_ACTION_ENA    :bit1;
  SH_KCACHE_VOL_ACTION_ENA:bit1;
  SH_ICACHE_ACTION_ENA    :bit1;
  SH_KCACHE_WB_ACTION_ENA :bit1;
  SH_SD_ACTION_ENA        :bit1;
 end;

 TCP_COHER_SIZE=bit32;

 TCP_CPC_STATUS=bitpacked record
  MEC1_BUSY       :bit1;
  MEC2_BUSY       :bit1;
  DC0_BUSY        :bit1;
  DC1_BUSY        :bit1;
  RCIU1_BUSY      :bit1;
  RCIU2_BUSY      :bit1;
  ROQ1_BUSY       :bit1;
  ROQ2_BUSY       :bit1;
  MIU_RDREQ_BUSY  :bit1;
  MIU_WRREQ_BUSY  :bit1;
  TCIU_BUSY       :bit1;
  SCRATCH_RAM_BUSY:bit1;
  QU_BUSY         :bit1;
  ATCL2IU_BUSY    :bit1;
  RESERVED0       :bit15;
  CPG_CPC_BUSY    :bit1;
  CPF_CPC_BUSY    :bit1;
  CPC_BUSY        :bit1;
 end;

 TCP_CPF_STATUS=bitpacked record
  POST_WPTR_GFX_BUSY   :bit1;
  CSF_BUSY             :bit1;
  MIU_RDREQ_BUSY       :bit1;
  MIU_WRREQ_BUSY       :bit1;
  ROQ_ALIGN_BUSY       :bit1;
  ROQ_RING_BUSY        :bit1;
  ROQ_INDIRECT1_BUSY   :bit1;
  ROQ_INDIRECT2_BUSY   :bit1;
  ROQ_STATE_BUSY       :bit1;
  ROQ_CE_RING_BUSY     :bit1;
  ROQ_CE_INDIRECT1_BUSY:bit1;
  ROQ_CE_INDIRECT2_BUSY:bit1;
  SEMAPHORE_BUSY       :bit1;
  INTERRUPT_BUSY       :bit1;
  TCIU_BUSY            :bit1;
  HQD_BUSY             :bit1;
  PRT_BUSY             :bit1;
  ATCL2IU_BUSY         :bit1;
  RESERVED0            :bit8;
  CPF_GFX_BUSY         :bit1;
  CPF_CMP_BUSY         :bit1;
  GRBM_CPF_STAT_BUSY   :bit2;
  CPC_CPF_BUSY         :bit1;
  CPF_BUSY             :bit1;
 end;

 TCP_DFY_DATA_0=bit32;

 TCP_DFY_DATA_1=bit32;

 TCP_DFY_DATA_2=bit32;

 TCP_DFY_DATA_3=bit32;

 TCP_DFY_DATA_4=bit32;

 TCP_DFY_DATA_5=bit32;

 TCP_DFY_DATA_6=bit32;

 TCP_DFY_DATA_7=bit32;

 TCP_DFY_DATA_8=bit32;

 TCP_DFY_DATA_9=bit32;

 TCP_HQD_ACTIVE=bitpacked record
  ACTIVE   :bit1;
  BUSY_GATE:bit1;
  RESERVED0:bit30;
 end;

 TCP_IB1_OFFSET=bitpacked record
  IB1_OFFSET:bit20;
  RESERVED0 :bit12;
 end;

 TCP_IB2_OFFSET=bitpacked record
  IB2_OFFSET:bit20;
  RESERVED0 :bit12;
 end;

 TCP_INDEX_TYPE=bitpacked record
  INDEX_TYPE:bit2;
  RESERVED0 :bit30;
 end;

 TCP_INT_STATUS=bitpacked record
  RESERVED0                  :bit11;
  CP_VM_DOORBELL_WR_INT_STAT :bit1;
  RESERVED1                  :bit2;
  CP_ECC_ERROR_INT_STAT      :bit1;
  RESERVED2                  :bit2;
  WRM_POLL_TIMEOUT_INT_STAT  :bit1;
  CMP_BUSY_INT_STAT          :bit1;
  CNTX_BUSY_INT_STAT         :bit1;
  CNTX_EMPTY_INT_STAT        :bit1;
  GFX_IDLE_INT_STAT          :bit1;
  PRIV_INSTR_INT_STAT        :bit1;
  PRIV_REG_INT_STAT          :bit1;
  OPCODE_ERROR_INT_STAT      :bit1;
  RESERVED3                  :bit1;
  TIME_STAMP_INT_STAT        :bit1;
  RESERVED_BIT_ERROR_INT_STAT:bit1;
  RESERVED4                  :bit1;
  GENERIC2_INT_STAT          :bit1;
  GENERIC1_INT_STAT          :bit1;
  GENERIC0_INT_STAT          :bit1;
 end;

 TCP_RB_RPTR_WR=bitpacked record
  RB_RPTR_WR:bit20;
  RESERVED0 :bit12;
 end;

 TCP_ROQ2_AVAIL=bitpacked record
  ROQ_CNT_IB2:bit11;
  RESERVED0  :bit21;
 end;

 TCP_ST_BASE_HI=bitpacked record
  ST_BASE_HI:bit16;
  RESERVED0 :bit16;
 end;

 TCP_ST_BASE_LO=bitpacked record
  RESERVED0 :bit2;
  ST_BASE_LO:bit30;
 end;

 TCP_VMID_RESET=bitpacked record
  RESET_REQUEST:bit16;
  RESET_STATUS :bit16;
 end;

 TCRTC_CRC_CNTL=bitpacked record
  CRTC_CRC_EN                         :bit1;
  RESERVED0                           :bit3;
  CRTC_CRC_CONT_EN                    :bit1;
  RESERVED1                           :bit3;
  CRTC_CRC_STEREO_MODE                :bit2;
  RESERVED2                           :bit2;
  CRTC_CRC_INTERLACE_MODE             :bit2;
  RESERVED3                           :bit2;
  CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS:bit1;
  RESERVED4                           :bit3;
  CRTC_CRC0_SELECT                    :bit3;
  RESERVED5                           :bit1;
  CRTC_CRC1_SELECT                    :bit3;
  RESERVED6                           :bit5;
 end;

 TCRTC_H_SYNC_A=bitpacked record
  CRTC_H_SYNC_A_START:bit14;
  RESERVED0          :bit2;
  CRTC_H_SYNC_A_END  :bit14;
  RESERVED1          :bit2;
 end;

 TCRTC_H_SYNC_B=bitpacked record
  CRTC_H_SYNC_B_START:bit14;
  RESERVED0          :bit2;
  CRTC_H_SYNC_B_END  :bit14;
  RESERVED1          :bit2;
 end;

 TCRTC_V_SYNC_A=bitpacked record
  CRTC_V_SYNC_A_START:bit14;
  RESERVED0          :bit2;
  CRTC_V_SYNC_A_END  :bit14;
  RESERVED1          :bit2;
 end;

 TCRTC_V_SYNC_B=bitpacked record
  CRTC_V_SYNC_B_START:bit14;
  RESERVED0          :bit2;
  CRTC_V_SYNC_B_END  :bit14;
  RESERVED1          :bit2;
 end;

 TCS_COPY_STATE=bitpacked record
  SRC_STATE_ID:bit3;
  RESERVED0   :bit29;
 end;

 TCUR2_HOT_SPOT=bitpacked record
  CURSOR2_HOT_SPOT_Y:bit7;
  RESERVED0         :bit9;
  CURSOR2_HOT_SPOT_X:bit7;
  RESERVED1         :bit9;
 end;

 TCUR2_POSITION=bitpacked record
  CURSOR2_Y_POSITION:bit14;
  RESERVED0         :bit2;
  CURSOR2_X_POSITION:bit14;
  RESERVED1         :bit2;
 end;

 TD1VGA_CONTROL=bitpacked record
  D1VGA_MODE_ENABLE         :bit1;
  RESERVED0                 :bit7;
  D1VGA_TIMING_SELECT       :bit1;
  D1VGA_SYNC_POLARITY_SELECT:bit1;
  RESERVED1                 :bit6;
  D1VGA_OVERSCAN_COLOR_EN   :bit1;
  RESERVED2                 :bit7;
  D1VGA_ROTATE              :bit2;
  RESERVED3                 :bit6;
 end;

 TD2VGA_CONTROL=bitpacked record
  D2VGA_MODE_ENABLE         :bit1;
  RESERVED0                 :bit7;
  D2VGA_TIMING_SELECT       :bit1;
  D2VGA_SYNC_POLARITY_SELECT:bit1;
  RESERVED1                 :bit6;
  D2VGA_OVERSCAN_COLOR_EN   :bit1;
  RESERVED2                 :bit7;
  D2VGA_ROTATE              :bit2;
  RESERVED3                 :bit6;
 end;

 TD3VGA_CONTROL=bitpacked record
  D3VGA_MODE_ENABLE         :bit1;
  RESERVED0                 :bit7;
  D3VGA_TIMING_SELECT       :bit1;
  D3VGA_SYNC_POLARITY_SELECT:bit1;
  RESERVED1                 :bit6;
  D3VGA_OVERSCAN_COLOR_EN   :bit1;
  RESERVED2                 :bit7;
  D3VGA_ROTATE              :bit2;
  RESERVED3                 :bit6;
 end;

 TD4VGA_CONTROL=bitpacked record
  D4VGA_MODE_ENABLE         :bit1;
  RESERVED0                 :bit7;
  D4VGA_TIMING_SELECT       :bit1;
  D4VGA_SYNC_POLARITY_SELECT:bit1;
  RESERVED1                 :bit6;
  D4VGA_OVERSCAN_COLOR_EN   :bit1;
  RESERVED2                 :bit7;
  D4VGA_ROTATE              :bit2;
  RESERVED3                 :bit6;
 end;

 TD5VGA_CONTROL=bitpacked record
  D5VGA_MODE_ENABLE         :bit1;
  RESERVED0                 :bit7;
  D5VGA_TIMING_SELECT       :bit1;
  D5VGA_SYNC_POLARITY_SELECT:bit1;
  RESERVED1                 :bit6;
  D5VGA_OVERSCAN_COLOR_EN   :bit1;
  RESERVED2                 :bit7;
  D5VGA_ROTATE              :bit2;
  RESERVED3                 :bit6;
 end;

 TD6VGA_CONTROL=bitpacked record
  D6VGA_MODE_ENABLE         :bit1;
  RESERVED0                 :bit7;
  D6VGA_TIMING_SELECT       :bit1;
  D6VGA_SYNC_POLARITY_SELECT:bit1;
  RESERVED1                 :bit6;
  D6VGA_OVERSCAN_COLOR_EN   :bit1;
  RESERVED2                 :bit7;
  D6VGA_ROTATE              :bit2;
  RESERVED3                 :bit6;
 end;

 TDAC_POWERDOWN=bitpacked record
  DAC_POWERDOWN      :bit1;
  RESERVED0          :bit7;
  DAC_POWERDOWN_BLUE :bit1;
  RESERVED1          :bit7;
  DAC_POWERDOWN_GREEN:bit1;
  RESERVED2          :bit7;
  DAC_POWERDOWN_RED  :bit1;
  RESERVED3          :bit7;
 end;

 TDB_DEPTH_INFO=bitpacked record
  ADDR5_SWIZZLE_MASK:bit4;
  ARRAY_MODE        :bit4;
  PIPE_CONFIG       :bit5;
  BANK_WIDTH        :bit2;
  BANK_HEIGHT       :bit2;
  MACRO_TILE_ASPECT :bit2;
  NUM_BANKS         :bit2;
  RESERVED0         :bit11;
 end;

 TDB_DEPTH_SIZE=bitpacked record
  PITCH_TILE_MAX :bit11;
  HEIGHT_TILE_MAX:bit11;
  RESERVED0      :bit10;
 end;

 TDB_DEPTH_VIEW=bitpacked record
  SLICE_START      :bit11;
  RESERVED0        :bit2;
  SLICE_MAX        :bit11;
  Z_READ_ONLY      :bit1;
  STENCIL_READ_ONLY:bit1;
  RESERVED1        :bit6;
 end;

 TDB_WATERMARKS=bitpacked record
  DEPTH_FREE           :bit5;
  DEPTH_FLUSH          :bit6;
  FORCE_SUMMARIZE      :bit4;
  DEPTH_PENDING_FREE   :bit5;
  DEPTH_CACHELINE_FREE :bit7;
  EARLY_Z_PANIC_DISABLE:bit1;
  LATE_Z_PANIC_DISABLE :bit1;
  RE_Z_PANIC_DISABLE   :bit1;
  AUTO_FLUSH_HTILE     :bit1;
  AUTO_FLUSH_QUAD      :bit1;
 end;

 TDCCG_GTC_CNTL=bitpacked record
  DCCG_GTC_ENABLE:bit1;
  RESERVED0      :bit31;
 end;

 TDCIO_DEBUG_ID=bit32;

 TDCIO_DPHY_SEL=bitpacked record
  DPHY_LANE0_SEL:bit2;
  DPHY_LANE1_SEL:bit2;
  DPHY_LANE2_SEL:bit2;
  DPHY_LANE3_SEL:bit2;
  RESERVED0     :bit24;
 end;

 TDC_GPIO_DEBUG=bitpacked record
  DC_GPIO_VIP_DEBUG             :bit1;
  RESERVED0                     :bit7;
  DC_GPIO_MACRO_DEBUG           :bit2;
  RESERVED1                     :bit6;
  DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL:bit1;
  DC_GPIO_DEBUG_BUS_FLOP_EN     :bit1;
  RESERVED2                     :bit13;
  DPRX_LOOPBACK_ENABLE          :bit1;
 end;

 TDC_GPIO_HPD_A=bitpacked record
  DC_GPIO_HPD1_A:bit1;
  RESERVED0     :bit7;
  DC_GPIO_HPD2_A:bit1;
  RESERVED1     :bit7;
  DC_GPIO_HPD3_A:bit1;
  RESERVED2     :bit7;
  DC_GPIO_HPD4_A:bit1;
  RESERVED3     :bit1;
  DC_GPIO_HPD5_A:bit1;
  RESERVED4     :bit1;
  DC_GPIO_HPD6_A:bit1;
  RESERVED5     :bit3;
 end;

 TDC_GPIO_HPD_Y=bitpacked record
  DC_GPIO_HPD1_Y:bit1;
  RESERVED0     :bit7;
  DC_GPIO_HPD2_Y:bit1;
  RESERVED1     :bit7;
  DC_GPIO_HPD3_Y:bit1;
  RESERVED2     :bit7;
  DC_GPIO_HPD4_Y:bit1;
  RESERVED3     :bit1;
  DC_GPIO_HPD5_Y:bit1;
  RESERVED4     :bit1;
  DC_GPIO_HPD6_Y:bit1;
  RESERVED5     :bit3;
 end;

 TDEVICE_STATUS=bitpacked record
  CORR_ERR         :bit1;
  NON_FATAL_ERR    :bit1;
  FATAL_ERR        :bit1;
  USR_DETECTED     :bit1;
  AUX_PWR          :bit1;
  TRANSACTIONS_PEND:bit1;
  RESERVED0        :bit26;
 end;

 TDIDT_DB_CTRL0=bitpacked record
  DIDT_CTRL_EN        :bit1;
  USE_REF_CLOCK       :bit1;
  PHASE_OFFSET        :bit2;
  DIDT_CTRL_RST       :bit1;
  DIDT_CLK_EN_OVERRIDE:bit1;
  RESERVED0           :bit6;
  RESERVED1           :bit6;
  UNUSED_0            :bit14;
 end;

 TDIDT_DB_CTRL1=bitpacked record
  MIN_POWER:bit16;
  MAX_POWER:bit16;
 end;

 TDIDT_DB_CTRL2=bitpacked record
  MAX_POWER_DELTA         :bit14;
  RESERVED0               :bit2;
  SHORT_TERM_INTERVAL_SIZE:bit10;
  RESERVED1               :bit1;
  LONG_TERM_INTERVAL_RATIO:bit4;
  RESERVED2               :bit1;
 end;

 TDIDT_IND_DATA=bit32;

 TDIDT_SQ_CTRL0=bitpacked record
  DIDT_CTRL_EN              :bit1;
  USE_REF_CLOCK             :bit1;
  PHASE_OFFSET              :bit2;
  DIDT_CTRL_RST             :bit1;
  DIDT_CLK_EN_OVERRIDE      :bit1;
  DIDT_MAX_STALLS_ALLOWED_HI:bit6;
  DIDT_MAX_STALLS_ALLOWED_LO:bit6;
  UNUSED_0                  :bit14;
 end;

 TDIDT_SQ_CTRL1=bitpacked record
  MIN_POWER:bit16;
  MAX_POWER:bit16;
 end;

 TDIDT_SQ_CTRL2=bitpacked record
  MAX_POWER_DELTA         :bit14;
  RESERVED0               :bit2;
  SHORT_TERM_INTERVAL_SIZE:bit10;
  RESERVED1               :bit1;
  LONG_TERM_INTERVAL_RATIO:bit4;
  RESERVED2               :bit1;
 end;

 TDIDT_TD_CTRL0=bitpacked record
  DIDT_CTRL_EN              :bit1;
  USE_REF_CLOCK             :bit1;
  PHASE_OFFSET              :bit2;
  DIDT_CTRL_RST             :bit1;
  DIDT_CLK_EN_OVERRIDE      :bit1;
  DIDT_MAX_STALLS_ALLOWED_HI:bit6;
  DIDT_MAX_STALLS_ALLOWED_LO:bit6;
  UNUSED_0                  :bit14;
 end;

 TDIDT_TD_CTRL1=bitpacked record
  MIN_POWER:bit16;
  MAX_POWER:bit16;
 end;

 TDIDT_TD_CTRL2=bitpacked record
  MAX_POWER_DELTA         :bit14;
  RESERVED0               :bit2;
  SHORT_TERM_INTERVAL_SIZE:bit10;
  RESERVED1               :bit1;
  LONG_TERM_INTERVAL_RATIO:bit4;
  RESERVED2               :bit1;
 end;

 TDMCU_FW_CS_HI=bit32;

 TDMCU_FW_CS_LO=bit32;

 TDMIF_HW_DEBUG=bit32;

 TDOUT_SCRATCH0=bit32;

 TDOUT_SCRATCH1=bit32;

 TDOUT_SCRATCH2=bit32;

 TDOUT_SCRATCH3=bit32;

 TDOUT_SCRATCH4=bit32;

 TDOUT_SCRATCH5=bit32;

 TDOUT_SCRATCH6=bit32;

 TDOUT_SCRATCH7=bit32;

 TDPM_TABLE_100=bit32;

 TDPM_TABLE_101=bit32;

 TDPM_TABLE_102=bit32;

 TDPM_TABLE_103=bit32;

 TDPM_TABLE_104=bitpacked record
  GraphicsLevel_0_EnabledForThrottle:bit8;
  GraphicsLevel_0_EnabledForActivity:bit8;
  GraphicsLevel_0_DisplayWatermark  :bit8;
  GraphicsLevel_0_SclkDid           :bit8;
 end;

 TDPM_TABLE_105=bitpacked record
  GraphicsLevel_0_PowerThrottle  :bit8;
  GraphicsLevel_0_VoltageDownHyst:bit8;
  GraphicsLevel_0_DownHyst       :bit8;
  GraphicsLevel_0_UpHyst         :bit8;
 end;

 TDPM_TABLE_106=bitpacked record
  GraphicsLevel_1_MinVoltage_Phases:bit8;
  GraphicsLevel_1_MinVoltage_VddGfx:bit8;
  GraphicsLevel_1_MinVoltage_Vddci :bit8;
  GraphicsLevel_1_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_107=bit32;

 TDPM_TABLE_108=bitpacked record
  GraphicsLevel_1_ActivityLevel :bit16;
  GraphicsLevel_1_DeepSleepDivId:bit8;
  GraphicsLevel_1_pcieDpmLevel  :bit8;
 end;

 TDPM_TABLE_109=bit32;

 TDPM_TABLE_110=bit32;

 TDPM_TABLE_111=bit32;

 TDPM_TABLE_112=bit32;

 TDPM_TABLE_113=bit32;

 TDPM_TABLE_114=bit32;

 TDPM_TABLE_115=bitpacked record
  GraphicsLevel_1_EnabledForThrottle:bit8;
  GraphicsLevel_1_EnabledForActivity:bit8;
  GraphicsLevel_1_DisplayWatermark  :bit8;
  GraphicsLevel_1_SclkDid           :bit8;
 end;

 TDPM_TABLE_116=bitpacked record
  GraphicsLevel_1_PowerThrottle  :bit8;
  GraphicsLevel_1_VoltageDownHyst:bit8;
  GraphicsLevel_1_DownHyst       :bit8;
  GraphicsLevel_1_UpHyst         :bit8;
 end;

 TDPM_TABLE_117=bitpacked record
  GraphicsLevel_2_MinVoltage_Phases:bit8;
  GraphicsLevel_2_MinVoltage_VddGfx:bit8;
  GraphicsLevel_2_MinVoltage_Vddci :bit8;
  GraphicsLevel_2_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_118=bit32;

 TDPM_TABLE_119=bitpacked record
  GraphicsLevel_2_ActivityLevel :bit16;
  GraphicsLevel_2_DeepSleepDivId:bit8;
  GraphicsLevel_2_pcieDpmLevel  :bit8;
 end;

 TDPM_TABLE_120=bit32;

 TDPM_TABLE_121=bit32;

 TDPM_TABLE_122=bit32;

 TDPM_TABLE_123=bit32;

 TDPM_TABLE_124=bit32;

 TDPM_TABLE_125=bit32;

 TDPM_TABLE_126=bitpacked record
  GraphicsLevel_2_EnabledForThrottle:bit8;
  GraphicsLevel_2_EnabledForActivity:bit8;
  GraphicsLevel_2_DisplayWatermark  :bit8;
  GraphicsLevel_2_SclkDid           :bit8;
 end;

 TDPM_TABLE_127=bitpacked record
  GraphicsLevel_2_PowerThrottle  :bit8;
  GraphicsLevel_2_VoltageDownHyst:bit8;
  GraphicsLevel_2_DownHyst       :bit8;
  GraphicsLevel_2_UpHyst         :bit8;
 end;

 TDPM_TABLE_128=bitpacked record
  GraphicsLevel_3_MinVoltage_Phases:bit8;
  GraphicsLevel_3_MinVoltage_VddGfx:bit8;
  GraphicsLevel_3_MinVoltage_Vddci :bit8;
  GraphicsLevel_3_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_129=bit32;

 TDPM_TABLE_130=bitpacked record
  GraphicsLevel_3_ActivityLevel :bit16;
  GraphicsLevel_3_DeepSleepDivId:bit8;
  GraphicsLevel_3_pcieDpmLevel  :bit8;
 end;

 TDPM_TABLE_131=bit32;

 TDPM_TABLE_132=bit32;

 TDPM_TABLE_133=bit32;

 TDPM_TABLE_134=bit32;

 TDPM_TABLE_135=bit32;

 TDPM_TABLE_136=bit32;

 TDPM_TABLE_137=bitpacked record
  GraphicsLevel_3_EnabledForThrottle:bit8;
  GraphicsLevel_3_EnabledForActivity:bit8;
  GraphicsLevel_3_DisplayWatermark  :bit8;
  GraphicsLevel_3_SclkDid           :bit8;
 end;

 TDPM_TABLE_138=bitpacked record
  GraphicsLevel_3_PowerThrottle  :bit8;
  GraphicsLevel_3_VoltageDownHyst:bit8;
  GraphicsLevel_3_DownHyst       :bit8;
  GraphicsLevel_3_UpHyst         :bit8;
 end;

 TDPM_TABLE_139=bitpacked record
  GraphicsLevel_4_MinVoltage_Phases:bit8;
  GraphicsLevel_4_MinVoltage_VddGfx:bit8;
  GraphicsLevel_4_MinVoltage_Vddci :bit8;
  GraphicsLevel_4_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_140=bit32;

 TDPM_TABLE_141=bitpacked record
  GraphicsLevel_4_ActivityLevel :bit16;
  GraphicsLevel_4_DeepSleepDivId:bit8;
  GraphicsLevel_4_pcieDpmLevel  :bit8;
 end;

 TDPM_TABLE_142=bit32;

 TDPM_TABLE_143=bit32;

 TDPM_TABLE_144=bit32;

 TDPM_TABLE_145=bit32;

 TDPM_TABLE_146=bit32;

 TDPM_TABLE_147=bit32;

 TDPM_TABLE_148=bitpacked record
  GraphicsLevel_4_EnabledForThrottle:bit8;
  GraphicsLevel_4_EnabledForActivity:bit8;
  GraphicsLevel_4_DisplayWatermark  :bit8;
  GraphicsLevel_4_SclkDid           :bit8;
 end;

 TDPM_TABLE_149=bitpacked record
  GraphicsLevel_4_PowerThrottle  :bit8;
  GraphicsLevel_4_VoltageDownHyst:bit8;
  GraphicsLevel_4_DownHyst       :bit8;
  GraphicsLevel_4_UpHyst         :bit8;
 end;

 TDPM_TABLE_150=bitpacked record
  GraphicsLevel_5_MinVoltage_Phases:bit8;
  GraphicsLevel_5_MinVoltage_VddGfx:bit8;
  GraphicsLevel_5_MinVoltage_Vddci :bit8;
  GraphicsLevel_5_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_151=bit32;

 TDPM_TABLE_152=bitpacked record
  GraphicsLevel_5_ActivityLevel :bit16;
  GraphicsLevel_5_DeepSleepDivId:bit8;
  GraphicsLevel_5_pcieDpmLevel  :bit8;
 end;

 TDPM_TABLE_153=bit32;

 TDPM_TABLE_154=bit32;

 TDPM_TABLE_155=bit32;

 TDPM_TABLE_156=bit32;

 TDPM_TABLE_157=bit32;

 TDPM_TABLE_158=bit32;

 TDPM_TABLE_159=bitpacked record
  GraphicsLevel_5_EnabledForThrottle:bit8;
  GraphicsLevel_5_EnabledForActivity:bit8;
  GraphicsLevel_5_DisplayWatermark  :bit8;
  GraphicsLevel_5_SclkDid           :bit8;
 end;

 TDPM_TABLE_160=bitpacked record
  GraphicsLevel_5_PowerThrottle  :bit8;
  GraphicsLevel_5_VoltageDownHyst:bit8;
  GraphicsLevel_5_DownHyst       :bit8;
  GraphicsLevel_5_UpHyst         :bit8;
 end;

 TDPM_TABLE_161=bitpacked record
  GraphicsLevel_6_MinVoltage_Phases:bit8;
  GraphicsLevel_6_MinVoltage_VddGfx:bit8;
  GraphicsLevel_6_MinVoltage_Vddci :bit8;
  GraphicsLevel_6_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_162=bit32;

 TDPM_TABLE_163=bitpacked record
  GraphicsLevel_6_ActivityLevel :bit16;
  GraphicsLevel_6_DeepSleepDivId:bit8;
  GraphicsLevel_6_pcieDpmLevel  :bit8;
 end;

 TDPM_TABLE_164=bit32;

 TDPM_TABLE_165=bit32;

 TDPM_TABLE_166=bit32;

 TDPM_TABLE_167=bit32;

 TDPM_TABLE_168=bit32;

 TDPM_TABLE_169=bit32;

 TDPM_TABLE_170=bitpacked record
  GraphicsLevel_6_EnabledForThrottle:bit8;
  GraphicsLevel_6_EnabledForActivity:bit8;
  GraphicsLevel_6_DisplayWatermark  :bit8;
  GraphicsLevel_6_SclkDid           :bit8;
 end;

 TDPM_TABLE_171=bitpacked record
  GraphicsLevel_6_PowerThrottle  :bit8;
  GraphicsLevel_6_VoltageDownHyst:bit8;
  GraphicsLevel_6_DownHyst       :bit8;
  GraphicsLevel_6_UpHyst         :bit8;
 end;

 TDPM_TABLE_172=bitpacked record
  GraphicsLevel_7_MinVoltage_Phases:bit8;
  GraphicsLevel_7_MinVoltage_VddGfx:bit8;
  GraphicsLevel_7_MinVoltage_Vddci :bit8;
  GraphicsLevel_7_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_173=bit32;

 TDPM_TABLE_174=bitpacked record
  GraphicsLevel_7_ActivityLevel :bit16;
  GraphicsLevel_7_DeepSleepDivId:bit8;
  GraphicsLevel_7_pcieDpmLevel  :bit8;
 end;

 TDPM_TABLE_175=bit32;

 TDPM_TABLE_176=bit32;

 TDPM_TABLE_177=bit32;

 TDPM_TABLE_178=bit32;

 TDPM_TABLE_179=bit32;

 TDPM_TABLE_180=bit32;

 TDPM_TABLE_181=bitpacked record
  GraphicsLevel_7_EnabledForThrottle:bit8;
  GraphicsLevel_7_EnabledForActivity:bit8;
  GraphicsLevel_7_DisplayWatermark  :bit8;
  GraphicsLevel_7_SclkDid           :bit8;
 end;

 TDPM_TABLE_182=bitpacked record
  GraphicsLevel_7_PowerThrottle  :bit8;
  GraphicsLevel_7_VoltageDownHyst:bit8;
  GraphicsLevel_7_DownHyst       :bit8;
  GraphicsLevel_7_UpHyst         :bit8;
 end;

 TDPM_TABLE_183=bitpacked record
  MemoryACPILevel_MinVoltage_Phases:bit8;
  MemoryACPILevel_MinVoltage_VddGfx:bit8;
  MemoryACPILevel_MinVoltage_Vddci :bit8;
  MemoryACPILevel_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_184=bit32;

 TDPM_TABLE_185=bit32;

 TDPM_TABLE_186=bitpacked record
  MemoryACPILevel_EnabledForActivity:bit8;
  MemoryACPILevel_EnabledForThrottle:bit8;
  MemoryACPILevel_FreqRange         :bit8;
  MemoryACPILevel_StutterEnable     :bit8;
 end;

 TDPM_TABLE_187=bitpacked record
  MemoryACPILevel_padding        :bit8;
  MemoryACPILevel_VoltageDownHyst:bit8;
  MemoryACPILevel_DownHyst       :bit8;
  MemoryACPILevel_UpHyst         :bit8;
 end;

 TDPM_TABLE_188=bitpacked record
  MemoryACPILevel_MclkDivider     :bit8;
  MemoryACPILevel_DisplayWatermark:bit8;
  MemoryACPILevel_ActivityLevel   :bit16;
 end;

 TDPM_TABLE_189=bitpacked record
  MemoryLevel_0_MinVoltage_Phases:bit8;
  MemoryLevel_0_MinVoltage_VddGfx:bit8;
  MemoryLevel_0_MinVoltage_Vddci :bit8;
  MemoryLevel_0_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_190=bit32;

 TDPM_TABLE_191=bit32;

 TDPM_TABLE_192=bitpacked record
  MemoryLevel_0_EnabledForActivity:bit8;
  MemoryLevel_0_EnabledForThrottle:bit8;
  MemoryLevel_0_FreqRange         :bit8;
  MemoryLevel_0_StutterEnable     :bit8;
 end;

 TDPM_TABLE_193=bitpacked record
  MemoryLevel_0_padding        :bit8;
  MemoryLevel_0_VoltageDownHyst:bit8;
  MemoryLevel_0_DownHyst       :bit8;
  MemoryLevel_0_UpHyst         :bit8;
 end;

 TDPM_TABLE_194=bitpacked record
  MemoryLevel_0_MclkDivider     :bit8;
  MemoryLevel_0_DisplayWatermark:bit8;
  MemoryLevel_0_ActivityLevel   :bit16;
 end;

 TDPM_TABLE_195=bitpacked record
  MemoryLevel_1_MinVoltage_Phases:bit8;
  MemoryLevel_1_MinVoltage_VddGfx:bit8;
  MemoryLevel_1_MinVoltage_Vddci :bit8;
  MemoryLevel_1_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_196=bit32;

 TDPM_TABLE_197=bit32;

 TDPM_TABLE_198=bitpacked record
  MemoryLevel_1_EnabledForActivity:bit8;
  MemoryLevel_1_EnabledForThrottle:bit8;
  MemoryLevel_1_FreqRange         :bit8;
  MemoryLevel_1_StutterEnable     :bit8;
 end;

 TDPM_TABLE_199=bitpacked record
  MemoryLevel_1_padding        :bit8;
  MemoryLevel_1_VoltageDownHyst:bit8;
  MemoryLevel_1_DownHyst       :bit8;
  MemoryLevel_1_UpHyst         :bit8;
 end;

 TDPM_TABLE_200=bitpacked record
  MemoryLevel_1_MclkDivider     :bit8;
  MemoryLevel_1_DisplayWatermark:bit8;
  MemoryLevel_1_ActivityLevel   :bit16;
 end;

 TDPM_TABLE_201=bitpacked record
  MemoryLevel_2_MinVoltage_Phases:bit8;
  MemoryLevel_2_MinVoltage_VddGfx:bit8;
  MemoryLevel_2_MinVoltage_Vddci :bit8;
  MemoryLevel_2_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_202=bit32;

 TDPM_TABLE_203=bit32;

 TDPM_TABLE_204=bitpacked record
  MemoryLevel_2_EnabledForActivity:bit8;
  MemoryLevel_2_EnabledForThrottle:bit8;
  MemoryLevel_2_FreqRange         :bit8;
  MemoryLevel_2_StutterEnable     :bit8;
 end;

 TDPM_TABLE_205=bitpacked record
  MemoryLevel_2_padding        :bit8;
  MemoryLevel_2_VoltageDownHyst:bit8;
  MemoryLevel_2_DownHyst       :bit8;
  MemoryLevel_2_UpHyst         :bit8;
 end;

 TDPM_TABLE_206=bitpacked record
  MemoryLevel_2_MclkDivider     :bit8;
  MemoryLevel_2_DisplayWatermark:bit8;
  MemoryLevel_2_ActivityLevel   :bit16;
 end;

 TDPM_TABLE_207=bitpacked record
  MemoryLevel_3_MinVoltage_Phases:bit8;
  MemoryLevel_3_MinVoltage_VddGfx:bit8;
  MemoryLevel_3_MinVoltage_Vddci :bit8;
  MemoryLevel_3_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_208=bit32;

 TDPM_TABLE_209=bit32;

 TDPM_TABLE_210=bitpacked record
  MemoryLevel_3_EnabledForActivity:bit8;
  MemoryLevel_3_EnabledForThrottle:bit8;
  MemoryLevel_3_FreqRange         :bit8;
  MemoryLevel_3_StutterEnable     :bit8;
 end;

 TDPM_TABLE_211=bitpacked record
  MemoryLevel_3_padding        :bit8;
  MemoryLevel_3_VoltageDownHyst:bit8;
  MemoryLevel_3_DownHyst       :bit8;
  MemoryLevel_3_UpHyst         :bit8;
 end;

 TDPM_TABLE_212=bitpacked record
  MemoryLevel_3_MclkDivider     :bit8;
  MemoryLevel_3_DisplayWatermark:bit8;
  MemoryLevel_3_ActivityLevel   :bit16;
 end;

 TDPM_TABLE_213=bitpacked record
  LinkLevel_0_SPC               :bit8;
  LinkLevel_0_EnabledForActivity:bit8;
  LinkLevel_0_PcieLaneCount     :bit8;
  LinkLevel_0_PcieGenSpeed      :bit8;
 end;

 TDPM_TABLE_214=bit32;

 TDPM_TABLE_215=bit32;

 TDPM_TABLE_216=bit32;

 TDPM_TABLE_217=bitpacked record
  LinkLevel_1_SPC               :bit8;
  LinkLevel_1_EnabledForActivity:bit8;
  LinkLevel_1_PcieLaneCount     :bit8;
  LinkLevel_1_PcieGenSpeed      :bit8;
 end;

 TDPM_TABLE_218=bit32;

 TDPM_TABLE_219=bit32;

 TDPM_TABLE_220=bit32;

 TDPM_TABLE_221=bitpacked record
  LinkLevel_2_SPC               :bit8;
  LinkLevel_2_EnabledForActivity:bit8;
  LinkLevel_2_PcieLaneCount     :bit8;
  LinkLevel_2_PcieGenSpeed      :bit8;
 end;

 TDPM_TABLE_222=bit32;

 TDPM_TABLE_223=bit32;

 TDPM_TABLE_224=bit32;

 TDPM_TABLE_225=bitpacked record
  LinkLevel_3_SPC               :bit8;
  LinkLevel_3_EnabledForActivity:bit8;
  LinkLevel_3_PcieLaneCount     :bit8;
  LinkLevel_3_PcieGenSpeed      :bit8;
 end;

 TDPM_TABLE_226=bit32;

 TDPM_TABLE_227=bit32;

 TDPM_TABLE_228=bit32;

 TDPM_TABLE_229=bitpacked record
  LinkLevel_4_SPC               :bit8;
  LinkLevel_4_EnabledForActivity:bit8;
  LinkLevel_4_PcieLaneCount     :bit8;
  LinkLevel_4_PcieGenSpeed      :bit8;
 end;

 TDPM_TABLE_230=bit32;

 TDPM_TABLE_231=bit32;

 TDPM_TABLE_232=bit32;

 TDPM_TABLE_233=bitpacked record
  LinkLevel_5_SPC               :bit8;
  LinkLevel_5_EnabledForActivity:bit8;
  LinkLevel_5_PcieLaneCount     :bit8;
  LinkLevel_5_PcieGenSpeed      :bit8;
 end;

 TDPM_TABLE_234=bit32;

 TDPM_TABLE_235=bit32;

 TDPM_TABLE_236=bit32;

 TDPM_TABLE_237=bitpacked record
  LinkLevel_6_SPC               :bit8;
  LinkLevel_6_EnabledForActivity:bit8;
  LinkLevel_6_PcieLaneCount     :bit8;
  LinkLevel_6_PcieGenSpeed      :bit8;
 end;

 TDPM_TABLE_238=bit32;

 TDPM_TABLE_239=bit32;

 TDPM_TABLE_240=bit32;

 TDPM_TABLE_241=bitpacked record
  LinkLevel_7_SPC               :bit8;
  LinkLevel_7_EnabledForActivity:bit8;
  LinkLevel_7_PcieLaneCount     :bit8;
  LinkLevel_7_PcieGenSpeed      :bit8;
 end;

 TDPM_TABLE_242=bit32;

 TDPM_TABLE_243=bit32;

 TDPM_TABLE_244=bit32;

 TDPM_TABLE_245=bit32;

 TDPM_TABLE_246=bitpacked record
  ACPILevel_MinVoltage_Phases:bit8;
  ACPILevel_MinVoltage_VddGfx:bit8;
  ACPILevel_MinVoltage_Vddci :bit8;
  ACPILevel_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_247=bit32;

 TDPM_TABLE_248=bitpacked record
  ACPILevel_padding         :bit8;
  ACPILevel_DeepSleepDivId  :bit8;
  ACPILevel_DisplayWatermark:bit8;
  ACPILevel_SclkDid         :bit8;
 end;

 TDPM_TABLE_249=bit32;

 TDPM_TABLE_250=bit32;

 TDPM_TABLE_251=bit32;

 TDPM_TABLE_252=bit32;

 TDPM_TABLE_253=bit32;

 TDPM_TABLE_254=bit32;

 TDPM_TABLE_255=bit32;

 TDPM_TABLE_256=bit32;

 TDPM_TABLE_257=bit32;

 TDPM_TABLE_258=bit32;

 TDPM_TABLE_259=bitpacked record
  UvdLevel_0_MinVoltage_Phases:bit8;
  UvdLevel_0_MinVoltage_VddGfx:bit8;
  UvdLevel_0_MinVoltage_Vddci :bit8;
  UvdLevel_0_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_260=bitpacked record
  UvdLevel_0_padding_1  :bit8;
  UvdLevel_0_padding_0  :bit8;
  UvdLevel_0_DclkDivider:bit8;
  UvdLevel_0_VclkDivider:bit8;
 end;

 TDPM_TABLE_261=bit32;

 TDPM_TABLE_262=bit32;

 TDPM_TABLE_263=bitpacked record
  UvdLevel_1_MinVoltage_Phases:bit8;
  UvdLevel_1_MinVoltage_VddGfx:bit8;
  UvdLevel_1_MinVoltage_Vddci :bit8;
  UvdLevel_1_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_264=bitpacked record
  UvdLevel_1_padding_1  :bit8;
  UvdLevel_1_padding_0  :bit8;
  UvdLevel_1_DclkDivider:bit8;
  UvdLevel_1_VclkDivider:bit8;
 end;

 TDPM_TABLE_265=bit32;

 TDPM_TABLE_266=bit32;

 TDPM_TABLE_267=bitpacked record
  UvdLevel_2_MinVoltage_Phases:bit8;
  UvdLevel_2_MinVoltage_VddGfx:bit8;
  UvdLevel_2_MinVoltage_Vddci :bit8;
  UvdLevel_2_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_268=bitpacked record
  UvdLevel_2_padding_1  :bit8;
  UvdLevel_2_padding_0  :bit8;
  UvdLevel_2_DclkDivider:bit8;
  UvdLevel_2_VclkDivider:bit8;
 end;

 TDPM_TABLE_269=bit32;

 TDPM_TABLE_270=bit32;

 TDPM_TABLE_271=bitpacked record
  UvdLevel_3_MinVoltage_Phases:bit8;
  UvdLevel_3_MinVoltage_VddGfx:bit8;
  UvdLevel_3_MinVoltage_Vddci :bit8;
  UvdLevel_3_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_272=bitpacked record
  UvdLevel_3_padding_1  :bit8;
  UvdLevel_3_padding_0  :bit8;
  UvdLevel_3_DclkDivider:bit8;
  UvdLevel_3_VclkDivider:bit8;
 end;

 TDPM_TABLE_273=bit32;

 TDPM_TABLE_274=bit32;

 TDPM_TABLE_275=bitpacked record
  UvdLevel_4_MinVoltage_Phases:bit8;
  UvdLevel_4_MinVoltage_VddGfx:bit8;
  UvdLevel_4_MinVoltage_Vddci :bit8;
  UvdLevel_4_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_276=bitpacked record
  UvdLevel_4_padding_1  :bit8;
  UvdLevel_4_padding_0  :bit8;
  UvdLevel_4_DclkDivider:bit8;
  UvdLevel_4_VclkDivider:bit8;
 end;

 TDPM_TABLE_277=bit32;

 TDPM_TABLE_278=bit32;

 TDPM_TABLE_279=bitpacked record
  UvdLevel_5_MinVoltage_Phases:bit8;
  UvdLevel_5_MinVoltage_VddGfx:bit8;
  UvdLevel_5_MinVoltage_Vddci :bit8;
  UvdLevel_5_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_280=bitpacked record
  UvdLevel_5_padding_1  :bit8;
  UvdLevel_5_padding_0  :bit8;
  UvdLevel_5_DclkDivider:bit8;
  UvdLevel_5_VclkDivider:bit8;
 end;

 TDPM_TABLE_281=bit32;

 TDPM_TABLE_282=bit32;

 TDPM_TABLE_283=bitpacked record
  UvdLevel_6_MinVoltage_Phases:bit8;
  UvdLevel_6_MinVoltage_VddGfx:bit8;
  UvdLevel_6_MinVoltage_Vddci :bit8;
  UvdLevel_6_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_284=bitpacked record
  UvdLevel_6_padding_1  :bit8;
  UvdLevel_6_padding_0  :bit8;
  UvdLevel_6_DclkDivider:bit8;
  UvdLevel_6_VclkDivider:bit8;
 end;

 TDPM_TABLE_285=bit32;

 TDPM_TABLE_286=bit32;

 TDPM_TABLE_287=bitpacked record
  UvdLevel_7_MinVoltage_Phases:bit8;
  UvdLevel_7_MinVoltage_VddGfx:bit8;
  UvdLevel_7_MinVoltage_Vddci :bit8;
  UvdLevel_7_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_288=bitpacked record
  UvdLevel_7_padding_1  :bit8;
  UvdLevel_7_padding_0  :bit8;
  UvdLevel_7_DclkDivider:bit8;
  UvdLevel_7_VclkDivider:bit8;
 end;

 TDPM_TABLE_289=bit32;

 TDPM_TABLE_290=bitpacked record
  VceLevel_0_MinVoltage_Phases:bit8;
  VceLevel_0_MinVoltage_VddGfx:bit8;
  VceLevel_0_MinVoltage_Vddci :bit8;
  VceLevel_0_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_291=bitpacked record
  VceLevel_0_padding_2:bit8;
  VceLevel_0_padding_1:bit8;
  VceLevel_0_padding_0:bit8;
  VceLevel_0_Divider  :bit8;
 end;

 TDPM_TABLE_292=bit32;

 TDPM_TABLE_293=bitpacked record
  VceLevel_1_MinVoltage_Phases:bit8;
  VceLevel_1_MinVoltage_VddGfx:bit8;
  VceLevel_1_MinVoltage_Vddci :bit8;
  VceLevel_1_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_294=bitpacked record
  VceLevel_1_padding_2:bit8;
  VceLevel_1_padding_1:bit8;
  VceLevel_1_padding_0:bit8;
  VceLevel_1_Divider  :bit8;
 end;

 TDPM_TABLE_295=bit32;

 TDPM_TABLE_296=bitpacked record
  VceLevel_2_MinVoltage_Phases:bit8;
  VceLevel_2_MinVoltage_VddGfx:bit8;
  VceLevel_2_MinVoltage_Vddci :bit8;
  VceLevel_2_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_297=bitpacked record
  VceLevel_2_padding_2:bit8;
  VceLevel_2_padding_1:bit8;
  VceLevel_2_padding_0:bit8;
  VceLevel_2_Divider  :bit8;
 end;

 TDPM_TABLE_298=bit32;

 TDPM_TABLE_299=bitpacked record
  VceLevel_3_MinVoltage_Phases:bit8;
  VceLevel_3_MinVoltage_VddGfx:bit8;
  VceLevel_3_MinVoltage_Vddci :bit8;
  VceLevel_3_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_300=bitpacked record
  VceLevel_3_padding_2:bit8;
  VceLevel_3_padding_1:bit8;
  VceLevel_3_padding_0:bit8;
  VceLevel_3_Divider  :bit8;
 end;

 TDPM_TABLE_301=bit32;

 TDPM_TABLE_302=bitpacked record
  VceLevel_4_MinVoltage_Phases:bit8;
  VceLevel_4_MinVoltage_VddGfx:bit8;
  VceLevel_4_MinVoltage_Vddci :bit8;
  VceLevel_4_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_303=bitpacked record
  VceLevel_4_padding_2:bit8;
  VceLevel_4_padding_1:bit8;
  VceLevel_4_padding_0:bit8;
  VceLevel_4_Divider  :bit8;
 end;

 TDPM_TABLE_304=bit32;

 TDPM_TABLE_305=bitpacked record
  VceLevel_5_MinVoltage_Phases:bit8;
  VceLevel_5_MinVoltage_VddGfx:bit8;
  VceLevel_5_MinVoltage_Vddci :bit8;
  VceLevel_5_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_306=bitpacked record
  VceLevel_5_padding_2:bit8;
  VceLevel_5_padding_1:bit8;
  VceLevel_5_padding_0:bit8;
  VceLevel_5_Divider  :bit8;
 end;

 TDPM_TABLE_307=bit32;

 TDPM_TABLE_308=bitpacked record
  VceLevel_6_MinVoltage_Phases:bit8;
  VceLevel_6_MinVoltage_VddGfx:bit8;
  VceLevel_6_MinVoltage_Vddci :bit8;
  VceLevel_6_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_309=bitpacked record
  VceLevel_6_padding_2:bit8;
  VceLevel_6_padding_1:bit8;
  VceLevel_6_padding_0:bit8;
  VceLevel_6_Divider  :bit8;
 end;

 TDPM_TABLE_310=bit32;

 TDPM_TABLE_311=bitpacked record
  VceLevel_7_MinVoltage_Phases:bit8;
  VceLevel_7_MinVoltage_VddGfx:bit8;
  VceLevel_7_MinVoltage_Vddci :bit8;
  VceLevel_7_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_312=bitpacked record
  VceLevel_7_padding_2:bit8;
  VceLevel_7_padding_1:bit8;
  VceLevel_7_padding_0:bit8;
  VceLevel_7_Divider  :bit8;
 end;

 TDPM_TABLE_313=bit32;

 TDPM_TABLE_314=bitpacked record
  AcpLevel_0_MinVoltage_Phases:bit8;
  AcpLevel_0_MinVoltage_VddGfx:bit8;
  AcpLevel_0_MinVoltage_Vddci :bit8;
  AcpLevel_0_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_315=bitpacked record
  AcpLevel_0_padding_2:bit8;
  AcpLevel_0_padding_1:bit8;
  AcpLevel_0_padding_0:bit8;
  AcpLevel_0_Divider  :bit8;
 end;

 TDPM_TABLE_316=bit32;

 TDPM_TABLE_317=bitpacked record
  AcpLevel_1_MinVoltage_Phases:bit8;
  AcpLevel_1_MinVoltage_VddGfx:bit8;
  AcpLevel_1_MinVoltage_Vddci :bit8;
  AcpLevel_1_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_318=bitpacked record
  AcpLevel_1_padding_2:bit8;
  AcpLevel_1_padding_1:bit8;
  AcpLevel_1_padding_0:bit8;
  AcpLevel_1_Divider  :bit8;
 end;

 TDPM_TABLE_319=bit32;

 TDPM_TABLE_320=bitpacked record
  AcpLevel_2_MinVoltage_Phases:bit8;
  AcpLevel_2_MinVoltage_VddGfx:bit8;
  AcpLevel_2_MinVoltage_Vddci :bit8;
  AcpLevel_2_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_321=bitpacked record
  AcpLevel_2_padding_2:bit8;
  AcpLevel_2_padding_1:bit8;
  AcpLevel_2_padding_0:bit8;
  AcpLevel_2_Divider  :bit8;
 end;

 TDPM_TABLE_322=bit32;

 TDPM_TABLE_323=bitpacked record
  AcpLevel_3_MinVoltage_Phases:bit8;
  AcpLevel_3_MinVoltage_VddGfx:bit8;
  AcpLevel_3_MinVoltage_Vddci :bit8;
  AcpLevel_3_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_324=bitpacked record
  AcpLevel_3_padding_2:bit8;
  AcpLevel_3_padding_1:bit8;
  AcpLevel_3_padding_0:bit8;
  AcpLevel_3_Divider  :bit8;
 end;

 TDPM_TABLE_325=bit32;

 TDPM_TABLE_326=bitpacked record
  AcpLevel_4_MinVoltage_Phases:bit8;
  AcpLevel_4_MinVoltage_VddGfx:bit8;
  AcpLevel_4_MinVoltage_Vddci :bit8;
  AcpLevel_4_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_327=bitpacked record
  AcpLevel_4_padding_2:bit8;
  AcpLevel_4_padding_1:bit8;
  AcpLevel_4_padding_0:bit8;
  AcpLevel_4_Divider  :bit8;
 end;

 TDPM_TABLE_328=bit32;

 TDPM_TABLE_329=bitpacked record
  AcpLevel_5_MinVoltage_Phases:bit8;
  AcpLevel_5_MinVoltage_VddGfx:bit8;
  AcpLevel_5_MinVoltage_Vddci :bit8;
  AcpLevel_5_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_330=bitpacked record
  AcpLevel_5_padding_2:bit8;
  AcpLevel_5_padding_1:bit8;
  AcpLevel_5_padding_0:bit8;
  AcpLevel_5_Divider  :bit8;
 end;

 TDPM_TABLE_331=bit32;

 TDPM_TABLE_332=bitpacked record
  AcpLevel_6_MinVoltage_Phases:bit8;
  AcpLevel_6_MinVoltage_VddGfx:bit8;
  AcpLevel_6_MinVoltage_Vddci :bit8;
  AcpLevel_6_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_333=bitpacked record
  AcpLevel_6_padding_2:bit8;
  AcpLevel_6_padding_1:bit8;
  AcpLevel_6_padding_0:bit8;
  AcpLevel_6_Divider  :bit8;
 end;

 TDPM_TABLE_334=bit32;

 TDPM_TABLE_335=bitpacked record
  AcpLevel_7_MinVoltage_Phases:bit8;
  AcpLevel_7_MinVoltage_VddGfx:bit8;
  AcpLevel_7_MinVoltage_Vddci :bit8;
  AcpLevel_7_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_336=bitpacked record
  AcpLevel_7_padding_2:bit8;
  AcpLevel_7_padding_1:bit8;
  AcpLevel_7_padding_0:bit8;
  AcpLevel_7_Divider  :bit8;
 end;

 TDPM_TABLE_337=bit32;

 TDPM_TABLE_338=bitpacked record
  SamuLevel_0_MinVoltage_Phases:bit8;
  SamuLevel_0_MinVoltage_VddGfx:bit8;
  SamuLevel_0_MinVoltage_Vddci :bit8;
  SamuLevel_0_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_339=bitpacked record
  SamuLevel_0_padding_2:bit8;
  SamuLevel_0_padding_1:bit8;
  SamuLevel_0_padding_0:bit8;
  SamuLevel_0_Divider  :bit8;
 end;

 TDPM_TABLE_340=bit32;

 TDPM_TABLE_341=bitpacked record
  SamuLevel_1_MinVoltage_Phases:bit8;
  SamuLevel_1_MinVoltage_VddGfx:bit8;
  SamuLevel_1_MinVoltage_Vddci :bit8;
  SamuLevel_1_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_342=bitpacked record
  SamuLevel_1_padding_2:bit8;
  SamuLevel_1_padding_1:bit8;
  SamuLevel_1_padding_0:bit8;
  SamuLevel_1_Divider  :bit8;
 end;

 TDPM_TABLE_343=bit32;

 TDPM_TABLE_344=bitpacked record
  SamuLevel_2_MinVoltage_Phases:bit8;
  SamuLevel_2_MinVoltage_VddGfx:bit8;
  SamuLevel_2_MinVoltage_Vddci :bit8;
  SamuLevel_2_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_345=bitpacked record
  SamuLevel_2_padding_2:bit8;
  SamuLevel_2_padding_1:bit8;
  SamuLevel_2_padding_0:bit8;
  SamuLevel_2_Divider  :bit8;
 end;

 TDPM_TABLE_346=bit32;

 TDPM_TABLE_347=bitpacked record
  SamuLevel_3_MinVoltage_Phases:bit8;
  SamuLevel_3_MinVoltage_VddGfx:bit8;
  SamuLevel_3_MinVoltage_Vddci :bit8;
  SamuLevel_3_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_348=bitpacked record
  SamuLevel_3_padding_2:bit8;
  SamuLevel_3_padding_1:bit8;
  SamuLevel_3_padding_0:bit8;
  SamuLevel_3_Divider  :bit8;
 end;

 TDPM_TABLE_349=bit32;

 TDPM_TABLE_350=bitpacked record
  SamuLevel_4_MinVoltage_Phases:bit8;
  SamuLevel_4_MinVoltage_VddGfx:bit8;
  SamuLevel_4_MinVoltage_Vddci :bit8;
  SamuLevel_4_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_351=bitpacked record
  SamuLevel_4_padding_2:bit8;
  SamuLevel_4_padding_1:bit8;
  SamuLevel_4_padding_0:bit8;
  SamuLevel_4_Divider  :bit8;
 end;

 TDPM_TABLE_352=bit32;

 TDPM_TABLE_353=bitpacked record
  SamuLevel_5_MinVoltage_Phases:bit8;
  SamuLevel_5_MinVoltage_VddGfx:bit8;
  SamuLevel_5_MinVoltage_Vddci :bit8;
  SamuLevel_5_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_354=bitpacked record
  SamuLevel_5_padding_2:bit8;
  SamuLevel_5_padding_1:bit8;
  SamuLevel_5_padding_0:bit8;
  SamuLevel_5_Divider  :bit8;
 end;

 TDPM_TABLE_355=bit32;

 TDPM_TABLE_356=bitpacked record
  SamuLevel_6_MinVoltage_Phases:bit8;
  SamuLevel_6_MinVoltage_VddGfx:bit8;
  SamuLevel_6_MinVoltage_Vddci :bit8;
  SamuLevel_6_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_357=bitpacked record
  SamuLevel_6_padding_2:bit8;
  SamuLevel_6_padding_1:bit8;
  SamuLevel_6_padding_0:bit8;
  SamuLevel_6_Divider  :bit8;
 end;

 TDPM_TABLE_358=bit32;

 TDPM_TABLE_359=bitpacked record
  SamuLevel_7_MinVoltage_Phases:bit8;
  SamuLevel_7_MinVoltage_VddGfx:bit8;
  SamuLevel_7_MinVoltage_Vddci :bit8;
  SamuLevel_7_MinVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_360=bitpacked record
  SamuLevel_7_padding_2:bit8;
  SamuLevel_7_padding_1:bit8;
  SamuLevel_7_padding_0:bit8;
  SamuLevel_7_Divider  :bit8;
 end;

 TDPM_TABLE_361=bit32;

 TDPM_TABLE_362=bit32;

 TDPM_TABLE_363=bitpacked record
  Ulv_VddcPhase    :bit8;
  Ulv_VddcOffsetVid:bit8;
  Ulv_VddcOffset   :bit16;
 end;

 TDPM_TABLE_364=bit32;

 TDPM_TABLE_365=bit32;

 TDPM_TABLE_366=bit32;

 TDPM_TABLE_367=bit32;

 TDPM_TABLE_368=bit32;

 TDPM_TABLE_369=bit32;

 TDPM_TABLE_370=bit32;

 TDPM_TABLE_371=bit32;

 TDPM_TABLE_372=bit32;

 TDPM_TABLE_373=bit32;

 TDPM_TABLE_374=bit32;

 TDPM_TABLE_375=bit32;

 TDPM_TABLE_376=bit32;

 TDPM_TABLE_377=bit32;

 TDPM_TABLE_378=bit32;

 TDPM_TABLE_379=bit32;

 TDPM_TABLE_380=bit32;

 TDPM_TABLE_381=bit32;

 TDPM_TABLE_382=bit32;

 TDPM_TABLE_383=bit32;

 TDPM_TABLE_384=bit32;

 TDPM_TABLE_385=bit32;

 TDPM_TABLE_386=bit32;

 TDPM_TABLE_387=bit32;

 TDPM_TABLE_388=bit32;

 TDPM_TABLE_389=bit32;

 TDPM_TABLE_390=bit32;

 TDPM_TABLE_391=bit32;

 TDPM_TABLE_392=bit32;

 TDPM_TABLE_393=bit32;

 TDPM_TABLE_394=bit32;

 TDPM_TABLE_395=bit32;

 TDPM_TABLE_396=bit32;

 TDPM_TABLE_397=bit32;

 TDPM_TABLE_398=bitpacked record
  SamuBootLevel:bit8;
  AcpBootLevel :bit8;
  VceBootLevel :bit8;
  UvdBootLevel :bit8;
 end;

 TDPM_TABLE_399=bitpacked record
  GraphicsInterval           :bit8;
  GraphicsThermThrottleEnable:bit8;
  GraphicsVoltageChangeEnable:bit8;
  GraphicsBootLevel          :bit8;
 end;

 TDPM_TABLE_400=bitpacked record
  TemperatureLimitHigh:bit16;
  ThermalInterval     :bit8;
  VoltageInterval     :bit8;
 end;

 TDPM_TABLE_401=bitpacked record
  MemoryVoltageChangeEnable:bit8;
  MemoryBootLevel          :bit8;
  TemperatureLimitLow      :bit16;
 end;

 TDPM_TABLE_402=bitpacked record
  MemoryThermThrottleEnable:bit8;
  MemoryInterval           :bit8;
  BootMVdd                 :bit16;
 end;

 TDPM_TABLE_403=bitpacked record
  PhaseResponseTime  :bit16;
  VoltageResponseTime:bit16;
 end;

 TDPM_TABLE_404=bitpacked record
  DTEMode          :bit8;
  DTEInterval      :bit8;
  PCIeGenInterval  :bit8;
  PCIeBootLinkLevel:bit8;
 end;

 TDPM_TABLE_405=bitpacked record
  ThermGpio :bit8;
  AcDcGpio  :bit8;
  VRHotGpio :bit8;
  SVI2Enable:bit8;
 end;

 TDPM_TABLE_406=bitpacked record
  PPM_TemperatureLimit:bit16;
  PPM_PkgPwrLimit     :bit16;
 end;

 TDPM_TABLE_407=bitpacked record
  TargetTdp :bit16;
  DefaultTdp:bit16;
 end;

 TDPM_TABLE_408=bitpacked record
  FpsLowThreshold :bit16;
  FpsHighThreshold:bit16;
 end;

 TDPM_TABLE_409=bitpacked record
  BAPMTI_R_0_1_0:bit16;
  BAPMTI_R_0_0_0:bit16;
 end;

 TDPM_TABLE_410=bitpacked record
  BAPMTI_R_1_0_0:bit16;
  BAPMTI_R_0_2_0:bit16;
 end;

 TDPM_TABLE_411=bitpacked record
  BAPMTI_R_1_2_0:bit16;
  BAPMTI_R_1_1_0:bit16;
 end;

 TDPM_TABLE_412=bitpacked record
  BAPMTI_R_2_1_0:bit16;
  BAPMTI_R_2_0_0:bit16;
 end;

 TDPM_TABLE_413=bitpacked record
  BAPMTI_R_3_0_0:bit16;
  BAPMTI_R_2_2_0:bit16;
 end;

 TDPM_TABLE_414=bitpacked record
  BAPMTI_R_3_2_0:bit16;
  BAPMTI_R_3_1_0:bit16;
 end;

 TDPM_TABLE_415=bitpacked record
  BAPMTI_R_4_1_0:bit16;
  BAPMTI_R_4_0_0:bit16;
 end;

 TDPM_TABLE_416=bitpacked record
  BAPMTI_RC_0_0_0:bit16;
  BAPMTI_R_4_2_0 :bit16;
 end;

 TDPM_TABLE_417=bitpacked record
  BAPMTI_RC_0_2_0:bit16;
  BAPMTI_RC_0_1_0:bit16;
 end;

 TDPM_TABLE_418=bitpacked record
  BAPMTI_RC_1_1_0:bit16;
  BAPMTI_RC_1_0_0:bit16;
 end;

 TDPM_TABLE_419=bitpacked record
  BAPMTI_RC_2_0_0:bit16;
  BAPMTI_RC_1_2_0:bit16;
 end;

 TDPM_TABLE_420=bitpacked record
  BAPMTI_RC_2_2_0:bit16;
  BAPMTI_RC_2_1_0:bit16;
 end;

 TDPM_TABLE_421=bitpacked record
  BAPMTI_RC_3_1_0:bit16;
  BAPMTI_RC_3_0_0:bit16;
 end;

 TDPM_TABLE_422=bitpacked record
  BAPMTI_RC_4_0_0:bit16;
  BAPMTI_RC_3_2_0:bit16;
 end;

 TDPM_TABLE_423=bitpacked record
  BAPMTI_RC_4_2_0:bit16;
  BAPMTI_RC_4_1_0:bit16;
 end;

 TDPM_TABLE_424=bitpacked record
  GpuTjHyst         :bit8;
  GpuTjMax          :bit8;
  DTETjOffset       :bit8;
  DTEAmbientTempBase:bit8;
 end;

 TDPM_TABLE_425=bitpacked record
  BootVoltage_Phases:bit8;
  BootVoltage_VddGfx:bit8;
  BootVoltage_Vddci :bit8;
  BootVoltage_Vddc  :bit8;
 end;

 TDPM_TABLE_426=bit32;

 TDPM_TABLE_427=bit32;

 TDPM_TABLE_428=bit32;

 TDPM_TABLE_429=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID   :bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID   :bit8;
 end;

 TDPM_TABLE_430=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0:bit8;
 end;

 TDPM_TABLE_431=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4:bit8;
 end;

 TDPM_TABLE_432=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID   :bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID   :bit8;
 end;

 TDPM_TABLE_433=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0:bit8;
 end;

 TDPM_TABLE_434=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4:bit8;
 end;

 TDPM_TABLE_435=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID   :bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID   :bit8;
 end;

 TDPM_TABLE_436=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0:bit8;
 end;

 TDPM_TABLE_437=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4:bit8;
 end;

 TDPM_TABLE_438=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID   :bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID   :bit8;
 end;

 TDPM_TABLE_439=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0:bit8;
 end;

 TDPM_TABLE_440=bitpacked record
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5:bit8;
  ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4:bit8;
 end;

 TDPREFCLK_CNTL=bitpacked record
  DPREFCLK_SRC_SEL :bit3;
  RESERVED0        :bit5;
  UNB_DB_CLK_ENABLE:bit1;
  RESERVED1        :bit23;
 end;

 TDP_DTO0_PHASE=bit32;

 TDP_DTO1_PHASE=bit32;

 TDP_DTO2_PHASE=bit32;

 TDP_DTO3_PHASE=bit32;

 TDP_DTO4_PHASE=bit32;

 TDP_DTO5_PHASE=bit32;

 TDP_STEER_FIFO=bitpacked record
  DP_STEER_FIFO_RESET   :bit1;
  RESERVED0             :bit3;
  DP_STEER_OVERFLOW_FLAG:bit1;
  DP_STEER_OVERFLOW_INT :bit1;
  DP_STEER_OVERFLOW_ACK :bit1;
  DP_STEER_OVERFLOW_MASK:bit1;
  DP_TU_OVERFLOW_FLAG   :bit1;
  RESERVED1             :bit3;
  DP_TU_OVERFLOW_ACK    :bit1;
  RESERVED2             :bit19;
 end;

 TDP_VID_TIMING=bitpacked record
  DP_VID_TIMING_MODE:bit1;
  RESERVED0         :bit7;
  DP_VID_M_N_GEN_EN :bit1;
  RESERVED1         :bit15;
  DP_VID_N_DIV      :bit8;
 end;

 TDVOACLKC_CNTL=bitpacked record
  DVOACLKC_FINE_SKEW_CNTL  :bit3;
  RESERVED0                :bit5;
  DVOACLKC_COARSE_SKEW_CNTL:bit5;
  RESERVED1                :bit3;
  DVOACLKC_FINE_ADJUST_EN  :bit1;
  DVOACLKC_COARSE_ADJUST_EN:bit1;
  DVOACLKC_IN_PHASE        :bit1;
  RESERVED2                :bit13;
 end;

 TDVOACLKD_CNTL=bitpacked record
  DVOACLKD_FINE_SKEW_CNTL  :bit3;
  RESERVED0                :bit5;
  DVOACLKD_COARSE_SKEW_CNTL:bit5;
  RESERVED1                :bit3;
  DVOACLKD_FINE_ADJUST_EN  :bit1;
  DVOACLKD_COARSE_ADJUST_EN:bit1;
  DVOACLKD_IN_PHASE        :bit1;
  RESERVED2                :bit13;
 end;

 TFBC_COMP_CNTL=bitpacked record
  FBC_MIN_COMPRESSION:bit4;
  RESERVED0          :bit12;
  FBC_DEPTH_MONO08_EN:bit1;
  FBC_DEPTH_MONO16_EN:bit1;
  FBC_DEPTH_RGB04_EN :bit1;
  FBC_DEPTH_RGB08_EN :bit1;
  FBC_DEPTH_RGB16_EN :bit1;
  RESERVED1          :bit11;
 end;

 TFBC_COMP_MODE=bitpacked record
  FBC_RLE_EN      :bit1;
  RESERVED0       :bit7;
  FBC_DPCM4_RGB_EN:bit1;
  FBC_DPCM8_RGB_EN:bit1;
  FBC_DPCM4_YUV_EN:bit1;
  FBC_DPCM8_YUV_EN:bit1;
  RESERVED1       :bit4;
  FBC_IND_EN      :bit1;
  RESERVED2       :bit15;
 end;

 TFBC_DEBUG_CSR=bitpacked record
  FBC_DEBUG_CSR_ADDR   :bit10;
  RESERVED0            :bit6;
  FBC_DEBUG_CSR_WR_DATA:bit1;
  FBC_DEBUG_CSR_RD_DATA:bit1;
  RESERVED1            :bit13;
  FBC_DEBUG_CSR_EN     :bit1;
 end;

 TFBC_IDLE_MASK=bit32;

 TFBC_IND_LUT10=bitpacked record
  FBC_IND_LUT10:bit24;
  RESERVED0    :bit8;
 end;

 TFBC_IND_LUT11=bitpacked record
  FBC_IND_LUT11:bit24;
  RESERVED0    :bit8;
 end;

 TFBC_IND_LUT12=bitpacked record
  FBC_IND_LUT12:bit24;
  RESERVED0    :bit8;
 end;

 TFBC_IND_LUT13=bitpacked record
  FBC_IND_LUT13:bit24;
  RESERVED0    :bit8;
 end;

 TFBC_IND_LUT14=bitpacked record
  FBC_IND_LUT14:bit24;
  RESERVED0    :bit8;
 end;

 TFBC_IND_LUT15=bitpacked record
  FBC_IND_LUT15:bit24;
  RESERVED0    :bit8;
 end;

 TGB_TILE_MODE0=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE1=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE2=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE3=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE4=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE5=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE6=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE7=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE8=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE9=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGDS_ATOM_BASE=bitpacked record
  BASE  :bit16;
  UNUSED:bit16;
 end;

 TGDS_ATOM_CNTL=bitpacked record
  AINC     :bit6;
  RESERVED0:bit2;
  DMODE    :bit2;
  RESERVED1:bit22;
 end;

 TGDS_ATOM_SIZE=bitpacked record
  SIZE  :bit16;
  UNUSED:bit16;
 end;

 TGDS_ATOM_SRC0=bit32;

 TGDS_ATOM_SRC1=bit32;

 TGDS_GWS_VMID0=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID1=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID2=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID3=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID4=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID5=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID6=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID7=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID8=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID9=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_OA_INCDEC=bitpacked record
  VALUE :bit31;
  INCDEC:bit1;
 end;

 TGDS_OA_VMID10=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID11=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID12=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID13=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID14=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_OA_VMID15=bitpacked record
  MASK     :bit16;
  RESERVED0:bit16;
 end;

 TGLOBAL_STATUS=bitpacked record
  RESERVED0   :bit1;
  FLUSH_STATUS:bit1;
  RESERVED1   :bit30;
 end;

 TGPIOPAD_PD_EN=bitpacked record
  GPIO_PD_EN:bit31;
  RESERVED0 :bit1;
 end;

 TGPIOPAD_PU_EN=bitpacked record
  GPIO_PU_EN:bit31;
  RESERVED0 :bit1;
 end;

 TGRBM_CAM_DATA=bitpacked record
  CAM_ADDR     :bit16;
  CAM_REMAPADDR:bit16;
 end;

 TGRBM_INT_CNTL=bitpacked record
  RDERR_INT_ENABLE   :bit1;
  RESERVED0          :bit18;
  GUI_IDLE_INT_ENABLE:bit1;
  RESERVED1          :bit12;
 end;

 TGRBM_PWR_CNTL=bitpacked record
  ALL_REQ_TYPE:bit2;
  GFX_REQ_TYPE:bit2;
  ALL_RSP_TYPE:bit2;
  GFX_RSP_TYPE:bit2;
  RESERVED0   :bit6;
  GFX_REQ_EN  :bit1;
  ALL_REQ_EN  :bit1;
  RESERVED1   :bit16;
 end;

 THDMI_ACR_32_0=bitpacked record
  RESERVED0      :bit12;
  HDMI_ACR_CTS_32:bit20;
 end;

 THDMI_ACR_32_1=bitpacked record
  HDMI_ACR_N_32:bit20;
  RESERVED0    :bit12;
 end;

 THDMI_ACR_44_0=bitpacked record
  RESERVED0      :bit12;
  HDMI_ACR_CTS_44:bit20;
 end;

 THDMI_ACR_44_1=bitpacked record
  HDMI_ACR_N_44:bit20;
  RESERVED0    :bit12;
 end;

 THDMI_ACR_48_0=bitpacked record
  RESERVED0      :bit12;
  HDMI_ACR_CTS_48:bit20;
 end;

 THDMI_ACR_48_1=bitpacked record
  HDMI_ACR_N_48:bit20;
  RESERVED0    :bit12;
 end;

 THDP_MISC_CNTL=bitpacked record
  FLUSH_INVALIDATE_CACHE      :bit1;
  VM_ID                       :bit4;
  OUTSTANDING_WRITE_COUNT_1024:bit1;
  MULTIPLE_READS              :bit1;
  HDP_BIF_RDRET_CREDIT        :bit4;
  SIMULTANEOUS_READS_WRITES   :bit1;
  NO_SPLIT_ARRAY_LINEAR       :bit1;
  MC_RDREQ_CREDIT             :bit6;
  READ_CACHE_INVALIDATE       :bit1;
  ADDRLIB_LINEAR_BYPASS       :bit1;
  FED_ENABLE                  :bit1;
  LEGACY_TILING_ENABLE        :bit1;
  LEGACY_SURFACES_ENABLE      :bit1;
  RESERVED0                   :bit8;
 end;

 THDP_VF_ENABLE=bitpacked record
  VF_EN    :bit1;
  RESERVED0:bit15;
  VF_NUM   :bit16;
 end;

 TIA_DEBUG_CNTL=bitpacked record
  IA_DEBUG_INDX     :bit6;
  IA_DEBUG_SEL_BUS_B:bit1;
  RESERVED0         :bit25;
 end;

 TIA_DEBUG_DATA=bit32;

 TIA_DEBUG_REG0=bitpacked record
  ia_busy_extended      :bit1;
  ia_nodma_busy_extended:bit1;
  ia_busy               :bit1;
  ia_nodma_busy         :bit1;
  SPARE0                :bit1;
  dma_req_busy          :bit1;
  dma_busy              :bit1;
  mc_xl8r_busy          :bit1;
  grp_busy              :bit1;
  SPARE1                :bit1;
  dma_grp_valid         :bit1;
  grp_dma_read          :bit1;
  dma_grp_hp_valid      :bit1;
  grp_dma_hp_read       :bit1;
  SPARE2                :bit10;
  reg_clk_busy          :bit1;
  core_clk_busy         :bit1;
  SPARE3                :bit1;
  SPARE4                :bit1;
  sclk_reg_vld          :bit1;
  sclk_core_vld         :bit1;
  SPARE5                :bit1;
  SPARE6                :bit1;
 end;

 TIA_DEBUG_REG1=bitpacked record
  dma_input_fifo_empty :bit1;
  dma_input_fifo_full  :bit1;
  start_new_packet     :bit1;
  dma_rdreq_dr_q       :bit1;
  dma_zero_indices_q   :bit1;
  dma_buf_type_q       :bit2;
  dma_req_path_q       :bit1;
  discard_1st_chunk    :bit1;
  discard_2nd_chunk    :bit1;
  second_tc_ret_data_q :bit1;
  dma_tc_ret_sel_q     :bit1;
  last_rdreq_in_dma_op :bit1;
  dma_mask_fifo_empty  :bit1;
  dma_data_fifo_empty_q:bit1;
  dma_data_fifo_full   :bit1;
  dma_req_fifo_empty   :bit1;
  dma_req_fifo_full    :bit1;
  stage2_dr            :bit1;
  stage2_rtr           :bit1;
  stage3_dr            :bit1;
  stage3_rtr           :bit1;
  stage4_dr            :bit1;
  stage4_rtr           :bit1;
  dma_skid_fifo_empty  :bit1;
  dma_skid_fifo_full   :bit1;
  dma_grp_valid        :bit1;
  grp_dma_read         :bit1;
  current_data_valid   :bit1;
  out_of_range_r2_q    :bit1;
  dma_mask_fifo_we     :bit1;
  dma_ret_data_we_q    :bit1;
 end;

 TIA_DEBUG_REG2=bitpacked record
  hp_dma_input_fifo_empty :bit1;
  hp_dma_input_fifo_full  :bit1;
  hp_start_new_packet     :bit1;
  hp_dma_rdreq_dr_q       :bit1;
  hp_dma_zero_indices_q   :bit1;
  hp_dma_buf_type_q       :bit2;
  hp_dma_req_path_q       :bit1;
  hp_discard_1st_chunk    :bit1;
  hp_discard_2nd_chunk    :bit1;
  hp_second_tc_ret_data_q :bit1;
  hp_dma_tc_ret_sel_q     :bit1;
  hp_last_rdreq_in_dma_op :bit1;
  hp_dma_mask_fifo_empty  :bit1;
  hp_dma_data_fifo_empty_q:bit1;
  hp_dma_data_fifo_full   :bit1;
  hp_dma_req_fifo_empty   :bit1;
  hp_dma_req_fifo_full    :bit1;
  hp_stage2_dr            :bit1;
  hp_stage2_rtr           :bit1;
  hp_stage3_dr            :bit1;
  hp_stage3_rtr           :bit1;
  hp_stage4_dr            :bit1;
  hp_stage4_rtr           :bit1;
  hp_dma_skid_fifo_empty  :bit1;
  hp_dma_skid_fifo_full   :bit1;
  hp_dma_grp_valid        :bit1;
  hp_grp_dma_read         :bit1;
  hp_current_data_valid   :bit1;
  hp_out_of_range_r2_q    :bit1;
  hp_dma_mask_fifo_we     :bit1;
  hp_dma_ret_data_we_q    :bit1;
 end;

 TIA_DEBUG_REG3=bitpacked record
  dma_pipe0_rdreq_valid     :bit1;
  dma_pipe0_rdreq_read      :bit1;
  dma_pipe0_rdreq_null_out  :bit1;
  dma_pipe0_rdreq_eop_out   :bit1;
  dma_pipe0_rdreq_use_tc_out:bit1;
  grp_dma_draw_is_pipe0     :bit1;
  must_service_pipe0_req    :bit1;
  send_pipe1_req            :bit1;
  dma_pipe1_rdreq_valid     :bit1;
  dma_pipe1_rdreq_read      :bit1;
  dma_pipe1_rdreq_null_out  :bit1;
  dma_pipe1_rdreq_eop_out   :bit1;
  dma_pipe1_rdreq_use_tc_out:bit1;
  ia_mc_rdreq_rtr_q         :bit1;
  mc_out_rtr                :bit1;
  dma_rdreq_send_out        :bit1;
  pipe0_dr                  :bit1;
  pipe0_rtr                 :bit1;
  ia_tc_rdreq_rtr_q         :bit1;
  tc_out_rtr                :bit1;
  pair0_valid_p1            :bit1;
  pair1_valid_p1            :bit1;
  pair2_valid_p1            :bit1;
  pair3_valid_p1            :bit1;
  tc_req_count_q            :bit2;
  discard_1st_chunk         :bit1;
  discard_2nd_chunk         :bit1;
  last_tc_req_p1            :bit1;
  IA_TC_rdreq_send_out      :bit1;
  TC_IA_rdret_valid_in      :bit1;
  TAP_IA_rdret_vld_in       :bit1;
 end;

 TIA_DEBUG_REG4=bitpacked record
  pipe0_dr                :bit1;
  pipe1_dr                :bit1;
  pipe2_dr                :bit1;
  pipe3_dr                :bit1;
  pipe4_dr                :bit1;
  pipe5_dr                :bit1;
  grp_se0_fifo_empty      :bit1;
  grp_se0_fifo_full       :bit1;
  pipe0_rtr               :bit1;
  pipe1_rtr               :bit1;
  pipe2_rtr               :bit1;
  pipe3_rtr               :bit1;
  pipe4_rtr               :bit1;
  pipe5_rtr               :bit1;
  ia_vgt_prim_rtr_q       :bit1;
  ia_se1vgt_prim_rtr_q    :bit1;
  di_major_mode_p1_q      :bit1;
  gs_mode_p1_q            :bit3;
  di_event_flag_p1_q      :bit1;
  di_state_sel_p1_q       :bit3;
  draw_opaq_en_p1_q       :bit1;
  draw_opaq_active_q      :bit1;
  di_source_select_p1_q   :bit2;
  ready_to_read_di        :bit1;
  di_first_group_of_draw_q:bit1;
  last_shift_of_draw      :bit1;
  current_shift_is_vect1_q:bit1;
 end;

 TIA_DEBUG_REG5=bitpacked record
  di_index_counter_q_15_0:bit16;
  instanceid_13_0        :bit14;
  draw_input_fifo_full   :bit1;
  draw_input_fifo_empty  :bit1;
 end;

 TIA_DEBUG_REG6=bitpacked record
  current_shift_q     :bit4;
  current_stride_pre  :bit4;
  current_stride_q    :bit5;
  first_group_partial :bit1;
  second_group_partial:bit1;
  curr_prim_partial   :bit1;
  next_stride_q       :bit5;
  next_group_partial  :bit1;
  after_group_partial :bit1;
  extract_group       :bit1;
  grp_shift_debug_data:bit8;
 end;

 TIA_DEBUG_REG7=bitpacked record
  reset_indx_state_q          :bit4;
  shift_vect_valid_p2_q       :bit4;
  shift_vect1_valid_p2_q      :bit4;
  shift_vect0_reset_match_p2_q:bit4;
  shift_vect1_reset_match_p2_q:bit4;
  num_indx_in_group_p2_q      :bit3;
  last_group_of_draw_p2_q     :bit1;
  shift_event_flag_p2_q       :bit1;
  indx_shift_is_one_p2_q      :bit1;
  indx_shift_is_two_p2_q      :bit1;
  indx_stride_is_four_p2_q    :bit1;
  shift_prim1_reset_p3_q      :bit1;
  shift_prim1_partial_p3_q    :bit1;
  shift_prim0_reset_p3_q      :bit1;
  shift_prim0_partial_p3_q    :bit1;
 end;

 TIA_DEBUG_REG8=bitpacked record
  di_prim_type_p1_q            :bit5;
  two_cycle_xfer_p1_q          :bit1;
  two_prim_input_p1_q          :bit1;
  shift_vect_end_of_packet_p5_q:bit1;
  last_group_of_inst_p5_q      :bit1;
  shift_prim1_null_flag_p5_q   :bit1;
  shift_prim0_null_flag_p5_q   :bit1;
  grp_continued                :bit1;
  grp_state_sel                :bit3;
  grp_sub_prim_type            :bit6;
  grp_output_path              :bit3;
  grp_null_primitive           :bit1;
  grp_eop                      :bit1;
  grp_eopg                     :bit1;
  grp_event_flag               :bit1;
  grp_components_valid         :bit4;
 end;

 TIA_DEBUG_REG9=bitpacked record
  send_to_se1_p6               :bit1;
  gfx_se_switch_p6             :bit1;
  null_eoi_xfer_prim1_p6       :bit1;
  null_eoi_xfer_prim0_p6       :bit1;
  prim1_eoi_p6                 :bit1;
  prim0_eoi_p6                 :bit1;
  prim1_valid_eopg_p6          :bit1;
  prim0_valid_eopg_p6          :bit1;
  prim1_to_other_se_p6         :bit1;
  eopg_on_last_prim_p6         :bit1;
  eopg_between_prims_p6        :bit1;
  prim_count_eq_group_size_p6  :bit1;
  prim_count_gt_group_size_p6  :bit1;
  two_prim_output_p5_q         :bit1;
  SPARE0                       :bit1;
  SPARE1                       :bit1;
  shift_vect_end_of_packet_p5_q:bit1;
  prim1_xfer_p6                :bit1;
  grp_se1_fifo_empty           :bit1;
  grp_se1_fifo_full            :bit1;
  prim_counter_q               :bit12;
 end;

 TIH_VMID_0_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_1_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_2_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_3_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_4_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_5_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_6_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_7_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_8_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_9_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TINTERRUPT_PIN=bitpacked record
  INTERRUPT_PIN:bit8;
  RESERVED0    :bit24;
 end;

 TKEY_RANGE_RED=bitpacked record
  KEY_RED_LOW :bit16;
  KEY_RED_HIGH:bit16;
 end;

 TLBV_V_COUNTER=bitpacked record
  V_COUNTER:bit15;
  RESERVED0:bit17;
 end;

 TLCAC_CPL_CNTL=bitpacked record
  CPL_ENABLE   :bit1;
  CPL_THRESHOLD:bit16;
  CPL_BLOCK_ID :bit5;
  CPL_SIGNAL_ID:bit8;
  RESERVED0    :bit2;
 end;

 TLCAC_MC0_CNTL=bitpacked record
  MC0_ENABLE   :bit1;
  MC0_THRESHOLD:bit16;
  MC0_BLOCK_ID :bit5;
  MC0_SIGNAL_ID:bit8;
  RESERVED0    :bit2;
 end;

 TLCAC_MC1_CNTL=bitpacked record
  MC1_ENABLE   :bit1;
  MC1_THRESHOLD:bit16;
  MC1_BLOCK_ID :bit5;
  MC1_SIGNAL_ID:bit8;
  RESERVED0    :bit2;
 end;

 TLCAC_MC2_CNTL=bitpacked record
  MC2_ENABLE   :bit1;
  MC2_THRESHOLD:bit16;
  MC2_BLOCK_ID :bit5;
  MC2_SIGNAL_ID:bit8;
  RESERVED0    :bit2;
 end;

 TLCAC_MC3_CNTL=bitpacked record
  MC3_ENABLE   :bit1;
  MC3_THRESHOLD:bit16;
  MC3_BLOCK_ID :bit5;
  MC3_SIGNAL_ID:bit8;
  RESERVED0    :bit2;
 end;

 TLCAC_MC4_CNTL=bitpacked record
  MC4_ENABLE   :bit1;
  MC4_THRESHOLD:bit16;
  MC4_BLOCK_ID :bit5;
  MC4_SIGNAL_ID:bit8;
  RESERVED0    :bit2;
 end;

 TLCAC_MC5_CNTL=bitpacked record
  MC5_ENABLE   :bit1;
  MC5_THRESHOLD:bit16;
  MC5_BLOCK_ID :bit5;
  MC5_SIGNAL_ID:bit8;
  RESERVED0    :bit2;
 end;

 TLCAC_MC6_CNTL=bitpacked record
  MC6_ENABLE   :bit1;
  MC6_THRESHOLD:bit16;
  MC6_BLOCK_ID :bit5;
  MC6_SIGNAL_ID:bit8;
  RESERVED0    :bit2;
 end;

 TLCAC_MC7_CNTL=bitpacked record
  MC7_ENABLE   :bit1;
  MC7_THRESHOLD:bit16;
  MC7_BLOCK_ID :bit5;
  MC7_SIGNAL_ID:bit8;
  RESERVED0    :bit2;
 end;

 TLM_LANEENABLE=bitpacked record
  LANE_enable:bit16;
  RESERVED0  :bit16;
 end;

 TLM_PCIERXMUX0=bitpacked record
  RXLANE0:bit8;
  RXLANE1:bit8;
  RXLANE2:bit8;
  RXLANE3:bit8;
 end;

 TLM_PCIERXMUX1=bitpacked record
  RXLANE4:bit8;
  RXLANE5:bit8;
  RXLANE6:bit8;
  RXLANE7:bit8;
 end;

 TLM_PCIERXMUX2=bitpacked record
  RXLANE8 :bit8;
  RXLANE9 :bit8;
  RXLANE10:bit8;
  RXLANE11:bit8;
 end;

 TLM_PCIERXMUX3=bitpacked record
  RXLANE12:bit8;
  RXLANE13:bit8;
  RXLANE14:bit8;
  RXLANE15:bit8;
 end;

 TLM_PCIETXMUX0=bitpacked record
  TXLANE0:bit8;
  TXLANE1:bit8;
  TXLANE2:bit8;
  TXLANE3:bit8;
 end;

 TLM_PCIETXMUX1=bitpacked record
  TXLANE4:bit8;
  TXLANE5:bit8;
  TXLANE6:bit8;
  TXLANE7:bit8;
 end;

 TLM_PCIETXMUX2=bitpacked record
  TXLANE8 :bit8;
  TXLANE9 :bit8;
  TXLANE10:bit8;
  TXLANE11:bit8;
 end;

 TLM_PCIETXMUX3=bitpacked record
  TXLANE12:bit8;
  TXLANE13:bit8;
  TXLANE14:bit8;
  TXLANE15:bit8;
 end;

 TLNCNT_CONTROL=bitpacked record
  CFG_LNC_WINDOW_EN0 :bit1;
  CFG_LNC_BW_CNT_EN1 :bit1;
  CFG_LNC_CMN_CNT_EN2:bit1;
  CFG_LNC_OVRD_EN3   :bit1;
  CFG_LNC_OVRD_VAL4  :bit1;
  RESERVED0          :bit27;
 end;

 TMAILBOX_INDEX=bitpacked record
  MAILBOX_INDEX:bit4;
  RESERVED0    :bit28;
 end;

 TMAJOR_VERSION=bitpacked record
  MAJOR_VERSION:bit8;
  RESERVED0    :bit24;
 end;

 TMC_ARB_AGE_RD=bitpacked record
  RATE_GROUP0  :bit2;
  RATE_GROUP1  :bit2;
  RATE_GROUP2  :bit2;
  RATE_GROUP3  :bit2;
  RATE_GROUP4  :bit2;
  RATE_GROUP5  :bit2;
  RATE_GROUP6  :bit2;
  RATE_GROUP7  :bit2;
  ENABLE_GROUP0:bit1;
  ENABLE_GROUP1:bit1;
  ENABLE_GROUP2:bit1;
  ENABLE_GROUP3:bit1;
  ENABLE_GROUP4:bit1;
  ENABLE_GROUP5:bit1;
  ENABLE_GROUP6:bit1;
  ENABLE_GROUP7:bit1;
  DIVIDE_GROUP0:bit1;
  DIVIDE_GROUP1:bit1;
  DIVIDE_GROUP2:bit1;
  DIVIDE_GROUP3:bit1;
  DIVIDE_GROUP4:bit1;
  DIVIDE_GROUP5:bit1;
  DIVIDE_GROUP6:bit1;
  DIVIDE_GROUP7:bit1;
 end;

 TMC_ARB_AGE_WR=bitpacked record
  RATE_GROUP0  :bit2;
  RATE_GROUP1  :bit2;
  RATE_GROUP2  :bit2;
  RATE_GROUP3  :bit2;
  RATE_GROUP4  :bit2;
  RATE_GROUP5  :bit2;
  RATE_GROUP6  :bit2;
  RATE_GROUP7  :bit2;
  ENABLE_GROUP0:bit1;
  ENABLE_GROUP1:bit1;
  ENABLE_GROUP2:bit1;
  ENABLE_GROUP3:bit1;
  ENABLE_GROUP4:bit1;
  ENABLE_GROUP5:bit1;
  ENABLE_GROUP6:bit1;
  ENABLE_GROUP7:bit1;
  DIVIDE_GROUP0:bit1;
  DIVIDE_GROUP1:bit1;
  DIVIDE_GROUP2:bit1;
  DIVIDE_GROUP3:bit1;
  DIVIDE_GROUP4:bit1;
  DIVIDE_GROUP5:bit1;
  DIVIDE_GROUP6:bit1;
  DIVIDE_GROUP7:bit1;
 end;

 TMC_ARB_ATOMIC=bitpacked record
  TC_GRP        :bit3;
  TC_GRP_EN     :bit1;
  SDMA_GRP      :bit3;
  SDMA_GRP_EN   :bit1;
  OUTSTANDING   :bit8;
  ATOMIC_RTN_GRP:bit8;
  RESERVED0     :bit8;
 end;

 TMC_ARB_RAMCFG=bitpacked record
  NOOFBANK  :bit2;
  NOOFRANKS :bit1;
  NOOFROWS  :bit3;
  NOOFCOLS  :bit2;
  CHANSIZE  :bit1;
  RSV_1     :bit1;
  RSV_2     :bit1;
  RSV_3     :bit1;
  NOOFGROUPS:bit1;
  RSV_4     :bit5;
  RESERVED0 :bit14;
 end;

 TMC_ARB_REMREQ=bitpacked record
  RD_WATER              :bit8;
  WR_WATER              :bit8;
  WR_MAXBURST_SIZE      :bit4;
  WR_LAZY_TIMER         :bit4;
  ENABLE_REMOTE_NACK_REQ:bit1;
  RESERVED0             :bit7;
 end;

 TMC_ARB_REPLAY=bitpacked record
  ENABLE_RD             :bit1;
  ENABLE_WR             :bit1;
  WRACK_MODE            :bit1;
  WAW_ENABLE            :bit1;
  RAW_ENABLE            :bit1;
  IGNORE_WR_CDC         :bit1;
  BREAK_ON_STALL        :bit1;
  BOS_ENABLE_WAIT_CYC   :bit1;
  BOS_WAIT_CYC          :bit7;
  NO_PCH_AT_REPLAY_START:bit1;
  RESERVED0             :bit16;
 end;

 TMC_CONFIG_MCD=bitpacked record
  MCD0_WR_ENABLE       :bit1;
  MCD1_WR_ENABLE       :bit1;
  MCD2_WR_ENABLE       :bit1;
  MCD3_WR_ENABLE       :bit1;
  MCD4_WR_ENABLE       :bit1;
  MCD5_WR_ENABLE       :bit1;
  MCD6_WR_ENABLE       :bit1;
  MCD7_WR_ENABLE       :bit1;
  MC_RD_ENABLE         :bit3;
  MC_RD_ENABLE_SUB     :bit1;
  ARB0_WR_ENABLE       :bit1;
  ARB1_WR_ENABLE       :bit1;
  RESERVED0            :bit17;
  MCD_INDEX_MODE_ENABLE:bit1;
 end;

 TMC_HUB_WDP_BP=bitpacked record
  ENABLE   :bit1;
  RDRET    :bit17;
  WRREQ    :bit12;
  RESERVED0:bit2;
 end;

 TMC_HUB_WDP_CP=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit2;
  RESERVED2:bit1;
  RESERVED3:bit2;
  RESERVED4:bit1;
  RESERVED5:bit4;
  RESERVED6:bit4;
  RESERVED7:bit1;
  RESERVED8:bit16;
 end;

 TMC_HUB_WDP_IH=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_RD_GRP_EXT=bitpacked record
  DBSTEN0  :bit4;
  TC0      :bit4;
  RESERVED0:bit24;
 end;

 TMC_RD_GRP_GFX=bitpacked record
  CP   :bit4;
  SH   :bit4;
  IA   :bit4;
  ACPG :bit4;
  ACPO :bit4;
  ISP  :bit4;
  VP8  :bit4;
  XDMAM:bit4;
 end;

 TMC_RD_GRP_LCL=bitpacked record
  RESERVED0:bit12;
  CB0      :bit4;
  CBCMASK0 :bit4;
  CBFMASK0 :bit4;
  DB0      :bit4;
  DBHTILE0 :bit4;
 end;

 TMC_RD_GRP_OTH=bitpacked record
  UVD_EXT0:bit4;
  SDMA0   :bit4;
  HDP     :bit4;
  SEM     :bit4;
  UMC     :bit4;
  UVD     :bit4;
  UVD_EXT1:bit4;
  SAMMSP  :bit4;
 end;

 TMC_RD_GRP_SYS=bitpacked record
  RLC  :bit4;
  VMC  :bit4;
  SDMA1:bit4;
  DMIF :bit4;
  MCIF :bit4;
  SMU  :bit4;
  VCE  :bit4;
  VCEU :bit4;
 end;

 TMC_SEQ_CNTL_2=bitpacked record
  RESERVED0 :bit3;
  RESERVED1 :bit3;
  RESERVED2 :bit3;
  RESERVED3 :bit3;
  RESERVED4 :bit3;
  RESERVED5 :bit3;
  RESERVED6 :bit3;
  RESERVED7 :bit3;
  RESERVED8 :bit3;
  RESERVED9 :bit3;
  RESERVED10:bit2;
 end;

 TMC_SEQ_CNTL_3=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit4;
  RESERVED9 :bit3;
  RESERVED10:bit1;
  RESERVED11:bit8;
  RESERVED12:bit4;
  RESERVED13:bit1;
  RESERVED14:bit3;
 end;

 TMC_SEQ_DRAM_2=bitpacked record
  RESERVED0:bit2;
  PCH_BNK  :bit1;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit1;
  RESERVED4:bit1;
  RESERVED5:bit1;
  WDAT_EDC :bit1;
  RDAT_EDC :bit1;
  RESERVED6:bit4;
  DLL_EST  :bit1;
  RESERVED7:bit1;
  RESERVED8:bit8;
  RESERVED9:bit8;
 end;

 TMC_VM_AGP_BOT=bitpacked record
  AGP_BOT  :bit18;
  RESERVED0:bit14;
 end;

 TMC_VM_AGP_TOP=bitpacked record
  AGP_TOP  :bit18;
  RESERVED0:bit14;
 end;

 TMC_WR_GRP_EXT=bitpacked record
  DBSTEN0  :bit4;
  TC0      :bit4;
  RESERVED0:bit24;
 end;

 TMC_WR_GRP_GFX=bitpacked record
  CP   :bit4;
  SH   :bit4;
  ACPG :bit4;
  ACPO :bit4;
  ISP  :bit4;
  VP8  :bit4;
  XDMA :bit4;
  XDMAM:bit4;
 end;

 TMC_WR_GRP_LCL=bitpacked record
  CB0      :bit4;
  CBCMASK0 :bit4;
  CBFMASK0 :bit4;
  DB0      :bit4;
  DBHTILE0 :bit4;
  SX0      :bit4;
  RESERVED0:bit4;
  CBIMMED0 :bit4;
 end;

 TMC_WR_GRP_OTH=bitpacked record
  UVD_EXT0:bit4;
  SDMA0   :bit4;
  HDP     :bit4;
  SEM     :bit4;
  UMC     :bit4;
  UVD     :bit4;
  XDP     :bit4;
  UVD_EXT1:bit4;
 end;

 TMC_WR_GRP_SYS=bitpacked record
  IH    :bit4;
  MCIF  :bit4;
  RLC   :bit4;
  SAMMSP:bit4;
  SMU   :bit4;
  SDMA1 :bit4;
  VCE   :bit4;
  VCEU  :bit4;
 end;

 TMC_XPB_STICKY=bit32;

 TMEM_TYPE_CNTL=bitpacked record
  BF_MEM_PHY_G5_G3:bit1;
  RESERVED0       :bit31;
 end;

 TMINOR_VERSION=bitpacked record
  MINOR_VERSION:bit8;
  RESERVED0    :bit24;
 end;

 TMISC_CLK_CTRL=bitpacked record
  DEEP_SLEEP_CLK_SEL:bit8;
  ZCLK_SEL          :bit8;
  DFT_SMS_PG_CLK_SEL:bit8;
  RESERVED0         :bit8;
 end;

 TOVL_SWAP_CNTL=bitpacked record
  OVL_ENDIAN_SWAP   :bit2;
  RESERVED0         :bit2;
  OVL_RED_CROSSBAR  :bit2;
  OVL_GREEN_CROSSBAR:bit2;
  OVL_BLUE_CROSSBAR :bit2;
  OVL_ALPHA_CROSSBAR:bit2;
  RESERVED1         :bit20;
 end;

 TPA_CL_ENHANCE=bitpacked record
  CLIP_VTX_REORDER_ENA  :bit1;
  NUM_CLIP_SEQ          :bit2;
  CLIPPED_PRIM_SEQ_STALL:bit1;
  VE_NAN_PROC_DISABLE   :bit1;
  XTRA_DEBUG_REG_SEL    :bit1;
  RESERVED0             :bit22;
  ECO_SPARE3            :bit1;
  ECO_SPARE2            :bit1;
  ECO_SPARE1            :bit1;
  ECO_SPARE0            :bit1;
 end;

 TPA_CL_UCP_0_W=bit32;

 TPA_CL_UCP_0_X=bit32;

 TPA_CL_UCP_0_Y=bit32;

 TPA_CL_UCP_0_Z=bit32;

 TPA_CL_UCP_1_W=bit32;

 TPA_CL_UCP_1_X=bit32;

 TPA_CL_UCP_1_Y=bit32;

 TPA_CL_UCP_1_Z=bit32;

 TPA_CL_UCP_2_W=bit32;

 TPA_CL_UCP_2_X=bit32;

 TPA_CL_UCP_2_Y=bit32;

 TPA_CL_UCP_2_Z=bit32;

 TPA_CL_UCP_3_W=bit32;

 TPA_CL_UCP_3_X=bit32;

 TPA_CL_UCP_3_Y=bit32;

 TPA_CL_UCP_3_Z=bit32;

 TPA_CL_UCP_4_W=bit32;

 TPA_CL_UCP_4_X=bit32;

 TPA_CL_UCP_4_Y=bit32;

 TPA_CL_UCP_4_Z=bit32;

 TPA_CL_UCP_5_W=bit32;

 TPA_CL_UCP_5_X=bit32;

 TPA_CL_UCP_5_Y=bit32;

 TPA_CL_UCP_5_Z=bit32;

 TPA_SC_ENHANCE=bitpacked record
  ENABLE_PA_SC_OUT_OF_ORDER                            :bit1;
  DISABLE_SC_DB_TILE_FIX                               :bit1;
  DISABLE_AA_MASK_FULL_FIX                             :bit1;
  ENABLE_1XMSAA_SAMPLE_LOCATIONS                       :bit1;
  ENABLE_1XMSAA_SAMPLE_LOC_CENTROID                    :bit1;
  DISABLE_SCISSOR_FIX                                  :bit1;
  DISABLE_PW_BUBBLE_COLLAPSE                           :bit2;
  SEND_UNLIT_STILES_TO_PACKER                          :bit1;
  DISABLE_DUALGRAD_PERF_OPTIMIZATION                   :bit1;
  DISABLE_SC_PROCESS_RESET_PRIM                        :bit1;
  DISABLE_SC_PROCESS_RESET_SUPERTILE                   :bit1;
  DISABLE_SC_PROCESS_RESET_TILE                        :bit1;
  DISABLE_PA_SC_GUIDANCE                               :bit1;
  DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS               :bit1;
  ENABLE_MULTICYCLE_BUBBLE_FREEZE                      :bit1;
  DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE                  :bit1;
  ENABLE_OUT_OF_ORDER_POLY_MODE                        :bit1;
  DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST        :bit1;
  DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING             :bit1;
  ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY    :bit1;
  DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING    :bit1;
  DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING   :bit1;
  DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS      :bit1;
  ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID        :bit1;
  DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO:bit1;
  OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT               :bit1;
  OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING            :bit1;
  DISABLE_EOP_LINE_STIPPLE_RESET                       :bit1;
  DISABLE_VPZ_EOP_LINE_STIPPLE_RESET                   :bit1;
  ECO_SPARE1                                           :bit1;
  ECO_SPARE0                                           :bit1;
 end;

 TPCIEP_SCRATCH=bit32;

 TPCIE_ACS_CNTL=bitpacked record
  SOURCE_VALIDATION_EN      :bit1;
  TRANSLATION_BLOCKING_EN   :bit1;
  P2P_REQUEST_REDIRECT_EN   :bit1;
  P2P_COMPLETION_REDIRECT_EN:bit1;
  UPSTREAM_FORWARDING_EN    :bit1;
  P2P_EGRESS_CONTROL_EN     :bit1;
  DIRECT_TRANSLATED_P2P_EN  :bit1;
  RESERVED0                 :bit25;
 end;

 TPCIE_ARI_CNTL=bitpacked record
  ARI_MFVC_FUNC_GROUPS_EN:bit1;
  ARI_ACS_FUNC_GROUPS_EN :bit1;
  RESERVED0              :bit2;
  ARI_FUNCTION_GROUP     :bit3;
  RESERVED1              :bit25;
 end;

 TPCIE_ATS_CNTL=bitpacked record
  STU       :bit5;
  RESERVED0 :bit10;
  ATC_ENABLE:bit1;
  RESERVED1 :bit16;
 end;

 TPCIE_BAR1_CAP=bitpacked record
  RESERVED0         :bit4;
  BAR_SIZE_SUPPORTED:bit20;
  RESERVED1         :bit8;
 end;

 TPCIE_BAR2_CAP=bitpacked record
  RESERVED0         :bit4;
  BAR_SIZE_SUPPORTED:bit20;
  RESERVED1         :bit8;
 end;

 TPCIE_BAR3_CAP=bitpacked record
  RESERVED0         :bit4;
  BAR_SIZE_SUPPORTED:bit20;
  RESERVED1         :bit8;
 end;

 TPCIE_BAR4_CAP=bitpacked record
  RESERVED0         :bit4;
  BAR_SIZE_SUPPORTED:bit20;
  RESERVED1         :bit8;
 end;

 TPCIE_BAR5_CAP=bitpacked record
  RESERVED0         :bit4;
  BAR_SIZE_SUPPORTED:bit20;
  RESERVED1         :bit8;
 end;

 TPCIE_BAR6_CAP=bitpacked record
  RESERVED0         :bit4;
  BAR_SIZE_SUPPORTED:bit20;
  RESERVED1         :bit8;
 end;

 TPCIE_BUS_CNTL=bitpacked record
  RESERVED0        :bit1;
  RESERVED1        :bit5;
  PMI_INT_DIS      :bit1;
  IMMEDIATE_PMI_DIS:bit1;
  RESERVED2        :bit4;
  TRUE_PM_STATUS_EN:bit1;
  RESERVED3        :bit19;
 end;

 TPCIE_CAP_LIST=bitpacked record
  CAP_ID   :bit8;
  NEXT_PTR :bit8;
  RESERVED0:bit16;
 end;

 TPCIE_CFG_CNTL=bitpacked record
  CFG_EN_DEC_TO_HIDDEN_REG     :bit1;
  CFG_EN_DEC_TO_GEN2_HIDDEN_REG:bit1;
  CFG_EN_DEC_TO_GEN3_HIDDEN_REG:bit1;
  RESERVED0                    :bit29;
 end;

 TPCIE_DPA_CNTL=bitpacked record
  SUBSTATE_CNTL:bit5;
  RESERVED0    :bit27;
 end;

 TPCIE_ERR_CNTL=bitpacked record
  ERR_REPORTING_DIS               :bit1;
  STRAP_FIRST_RCVD_ERR_LOG        :bit1;
  RX_DROP_ECRC_FAILURES           :bit1;
  RESERVED0                       :bit1;
  TX_GENERATE_LCRC_ERR            :bit1;
  RX_GENERATE_LCRC_ERR            :bit1;
  TX_GENERATE_ECRC_ERR            :bit1;
  RX_GENERATE_ECRC_ERR            :bit1;
  AER_HDR_LOG_TIMEOUT             :bit3;
  AER_HDR_LOG_F0_TIMER_EXPIRED    :bit1;
  AER_HDR_LOG_F1_TIMER_EXPIRED    :bit1;
  AER_HDR_LOG_F2_TIMER_EXPIRED    :bit1;
  CI_P_SLV_BUF_RD_HALT_STATUS     :bit1;
  CI_NP_SLV_BUF_RD_HALT_STATUS    :bit1;
  CI_SLV_BUF_HALT_RESET           :bit1;
  SEND_ERR_MSG_IMMEDIATELY        :bit1;
  STRAP_POISONED_ADVISORY_NONFATAL:bit1;
  RESERVED1                       :bit13;
 end;

 TPCIE_HDR_LOG0=bit32;

 TPCIE_HDR_LOG1=bit32;

 TPCIE_HDR_LOG2=bit32;

 TPCIE_HDR_LOG3=bit32;

 TPCIE_HW_DEBUG=bitpacked record
  HW_00_DEBUG:bit1;
  HW_01_DEBUG:bit1;
  HW_02_DEBUG:bit1;
  HW_03_DEBUG:bit1;
  HW_04_DEBUG:bit1;
  HW_05_DEBUG:bit1;
  HW_06_DEBUG:bit1;
  HW_07_DEBUG:bit1;
  HW_08_DEBUG:bit1;
  HW_09_DEBUG:bit1;
  HW_10_DEBUG:bit1;
  HW_11_DEBUG:bit1;
  HW_12_DEBUG:bit1;
  HW_13_DEBUG:bit1;
  HW_14_DEBUG:bit1;
  HW_15_DEBUG:bit1;
  RESERVED0  :bit16;
 end;

 TPCIE_INT_CNTL=bitpacked record
  CORR_ERR_INT_EN       :bit1;
  NON_FATAL_ERR_INT_EN  :bit1;
  FATAL_ERR_INT_EN      :bit1;
  USR_DETECTED_INT_EN   :bit1;
  MISC_ERR_INT_EN       :bit1;
  RESERVED0             :bit1;
  POWER_STATE_CHG_INT_EN:bit1;
  LINK_BW_INT_EN        :bit1;
  QUIESCE_RCVD_INT_EN   :bit1;
  RESERVED1             :bit23;
 end;

 TPCIE_LC_CNTL2=bitpacked record
  LC_TIMED_OUT_STATE                 :bit6;
  LC_STATE_TIMED_OUT                 :bit1;
  LC_LOOK_FOR_BW_REDUCTION           :bit1;
  LC_MORE_TS2_EN                     :bit1;
  LC_X12_NEGOTIATION_DIS             :bit1;
  LC_LINK_UP_REVERSAL_EN             :bit1;
  LC_ILLEGAL_STATE                   :bit1;
  LC_ILLEGAL_STATE_RESTART_EN        :bit1;
  LC_WAIT_FOR_OTHER_LANES_MODE       :bit1;
  LC_ELEC_IDLE_MODE                  :bit2;
  LC_DISABLE_INFERRED_ELEC_IDLE_DET  :bit1;
  LC_ALLOW_PDWN_IN_L1                :bit1;
  LC_ALLOW_PDWN_IN_L23               :bit1;
  LC_DEASSERT_RX_EN_IN_L0S           :bit1;
  LC_BLOCK_EL_IDLE_IN_L0             :bit1;
  LC_RCV_L0_TO_RCV_L0S_DIS           :bit1;
  LC_ASSERT_INACTIVE_DURING_HOLD     :bit1;
  LC_WAIT_FOR_LANES_IN_LW_NEG        :bit2;
  LC_PWR_DOWN_NEG_OFF_LANES          :bit1;
  LC_DISABLE_LOST_SYM_LOCK_ARCS      :bit1;
  LC_LINK_BW_NOTIFICATION_DIS        :bit1;
  LC_PMI_L1_WAIT_FOR_SLV_IDLE        :bit1;
  LC_TEST_TIMER_SEL                  :bit2;
  LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI:bit1;
 end;

 TPCIE_LC_CNTL3=bitpacked record
  LC_SELECT_DEEMPHASIS                      :bit1;
  LC_SELECT_DEEMPHASIS_CNTL                 :bit2;
  LC_RCVD_DEEMPHASIS                        :bit1;
  LC_COMP_TO_DETECT                         :bit1;
  LC_RESET_TSX_CNT_IN_RLOCK_EN              :bit1;
  LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED     :bit2;
  LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED       :bit1;
  LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT         :bit1;
  LC_ENHANCED_HOT_PLUG_EN                   :bit1;
  LC_RCVR_DET_EN_OVERRIDE                   :bit1;
  LC_EHP_RX_PHY_CMD                         :bit2;
  LC_EHP_TX_PHY_CMD                         :bit2;
  LC_CHIP_BIF_USB_IDLE_EN                   :bit1;
  LC_L1_BLOCK_RECONFIG_EN                   :bit1;
  LC_AUTO_DISABLE_SPEED_SUPPORT_EN          :bit1;
  LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL:bit2;
  LC_FAST_L1_ENTRY_EXIT_EN                  :bit1;
  LC_RXPHYCMD_INACTIVE_EN_MODE              :bit1;
  LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK       :bit1;
  LC_HW_VOLTAGE_IF_CONTROL                  :bit2;
  LC_VOLTAGE_TIMER_SEL                      :bit4;
  LC_GO_TO_RECOVERY                         :bit1;
  LC_N_EIE_SEL                              :bit1;
 end;

 TPCIE_LC_CNTL4=bitpacked record
  LC_TX_ENABLE_BEHAVIOUR         :bit2;
  LC_DIS_CONTIG_END_SET_CHECK    :bit1;
  LC_DIS_ASPM_L1_IN_SPEED_CHANGE :bit1;
  LC_BYPASS_EQ                   :bit1;
  LC_REDO_EQ                     :bit1;
  LC_EXTEND_EIEOS                :bit1;
  LC_IGNORE_PARITY               :bit1;
  LC_EQ_SEARCH_MODE              :bit2;
  LC_DSC_CHECK_COEFFS_IN_RLOCK   :bit1;
  LC_USC_EQ_NOT_REQD             :bit1;
  LC_USC_GO_TO_EQ                :bit1;
  LC_SET_QUIESCE                 :bit1;
  LC_QUIESCE_RCVD                :bit1;
  LC_UNEXPECTED_COEFFS_RCVD      :bit1;
  LC_BYPASS_EQ_REQ_PHASE         :bit1;
  LC_FORCE_PRESET_IN_EQ_REQ_PHASE:bit1;
  LC_FORCE_PRESET_VALUE          :bit4;
  LC_USC_DELAY_DLLPS             :bit1;
  LC_PCIE_TX_FULL_SWING          :bit1;
  LC_EQ_WAIT_FOR_EVAL_DONE       :bit1;
  LC_8GT_SKIP_ORDER_EN           :bit1;
  LC_WAIT_FOR_MORE_TS_IN_RLOCK   :bit6;
 end;

 TPCIE_LC_CNTL5=bitpacked record
  LC_EQ_FS_0                        :bit6;
  LC_EQ_FS_8                        :bit6;
  LC_EQ_LF_0                        :bit6;
  LC_EQ_LF_8                        :bit6;
  LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS:bit1;
  RESERVED0                         :bit7;
 end;

 TPCIE_LC_CNTL6=bitpacked record
  LC_SPC_MODE_2P5GT:bit1;
  RESERVED0        :bit1;
  LC_SPC_MODE_5GT  :bit1;
  RESERVED1        :bit1;
  LC_SPC_MODE_8GT  :bit1;
  RESERVED2        :bit27;
 end;

 TPCIE_MC_ADDR0=bitpacked record
  MC_INDEX_POS  :bit6;
  RESERVED0     :bit6;
  MC_BASE_ADDR_0:bit20;
 end;

 TPCIE_MC_ADDR1=bit32;

 TPCIE_PRBS_CLR=bitpacked record
  PRBS_CLR                     :bit16;
  PRBS_CHECKER_DEBUG_BUS_SELECT:bit4;
  RESERVED0                    :bit12;
 end;

 TPCIE_RESERVED=bit32;

 TPCIE_RX_CNTL2=bitpacked record
  RX_IGNORE_EP_INVALIDPASID_UR:bit1;
  RX_IGNORE_EP_TRANSMRD_UR    :bit1;
  RX_IGNORE_EP_TRANSMWR_UR    :bit1;
  RX_IGNORE_EP_ATSTRANSREQ_UR :bit1;
  RX_IGNORE_EP_PAGEREQMSG_UR  :bit1;
  RX_IGNORE_EP_INVCPL_UR      :bit1;
  RESERVED0                   :bit2;
  RX_RCB_LATENCY_EN           :bit1;
  RX_RCB_LATENCY_SCALE        :bit3;
  RESERVED1                   :bit4;
  RX_RCB_LATENCY_MAX_COUNT    :bit10;
  RESERVED2                   :bit2;
  FLR_EXTEND_MODE             :bit3;
  RESERVED3                   :bit1;
 end;

 TPCIE_RX_CNTL3=bitpacked record
  RX_IGNORE_RC_TRANSMRDPASID_UR:bit1;
  RX_IGNORE_RC_TRANSMWRPASID_UR:bit1;
  RX_IGNORE_RC_PRGRESPMSG_UR   :bit1;
  RX_IGNORE_RC_INVREQ_UR       :bit1;
  RX_IGNORE_RC_INVCPLPASID_UR  :bit1;
  RESERVED0                    :bit27;
 end;

 TPCIE_STRAP_F0=bitpacked record
  STRAP_F0_EN                        :bit1;
  STRAP_F0_LEGACY_DEVICE_TYPE_EN     :bit1;
  STRAP_F0_MSI_EN                    :bit1;
  STRAP_F0_VC_EN                     :bit1;
  STRAP_F0_DSN_EN                    :bit1;
  STRAP_F0_AER_EN                    :bit1;
  STRAP_F0_ACS_EN                    :bit1;
  STRAP_F0_BAR_EN                    :bit1;
  STRAP_F0_PWR_EN                    :bit1;
  STRAP_F0_DPA_EN                    :bit1;
  STRAP_F0_ATS_EN                    :bit1;
  STRAP_F0_PAGE_REQ_EN               :bit1;
  STRAP_F0_PASID_EN                  :bit1;
  STRAP_F0_ECRC_CHECK_EN             :bit1;
  STRAP_F0_ECRC_GEN_EN               :bit1;
  STRAP_F0_CPL_ABORT_ERR_EN          :bit1;
  STRAP_F0_POISONED_ADVISORY_NONFATAL:bit1;
  STRAP_F0_MC_EN                     :bit1;
  STRAP_F0_ATOMIC_EN                 :bit1;
  STRAP_F0_ATOMIC_64BIT_EN           :bit1;
  STRAP_F0_ATOMIC_ROUTING_EN         :bit1;
  STRAP_F0_MSI_MULTI_CAP             :bit3;
  STRAP_F0_VFn_MSI_MULTI_CAP         :bit3;
  STRAP_F0_MSI_PERVECTOR_MASK_CAP    :bit1;
  STRAP_F0_NO_RO_ENABLED_P2P_PASSING :bit1;
  STRAP_F0_ARI_EN                    :bit1;
  STRAP_F0_SRIOV_EN                  :bit1;
  RESERVED0                          :bit1;
 end;

 TPCIE_STRAP_F1=bitpacked record
  STRAP_F1_EN                        :bit1;
  STRAP_F1_LEGACY_DEVICE_TYPE_EN     :bit1;
  STRAP_F1_MSI_EN                    :bit1;
  STRAP_F1_VC_EN                     :bit1;
  STRAP_F1_DSN_EN                    :bit1;
  STRAP_F1_AER_EN                    :bit1;
  STRAP_F1_ACS_EN                    :bit1;
  STRAP_F1_BAR_EN                    :bit1;
  STRAP_F1_PWR_EN                    :bit1;
  STRAP_F1_DPA_EN                    :bit1;
  STRAP_F1_ATS_EN                    :bit1;
  STRAP_F1_PAGE_REQ_EN               :bit1;
  STRAP_F1_PASID_EN                  :bit1;
  STRAP_F1_ECRC_CHECK_EN             :bit1;
  STRAP_F1_ECRC_GEN_EN               :bit1;
  STRAP_F1_CPL_ABORT_ERR_EN          :bit1;
  STRAP_F1_POISONED_ADVISORY_NONFATAL:bit1;
  RESERVED0                          :bit1;
  STRAP_F1_ATOMIC_EN                 :bit1;
  STRAP_F1_ATOMIC_64BIT_EN           :bit1;
  STRAP_F1_ATOMIC_ROUTING_EN         :bit1;
  STRAP_F1_MSI_MULTI_CAP             :bit3;
  RESERVED1                          :bit3;
  STRAP_F1_MSI_PERVECTOR_MASK_CAP    :bit1;
  RESERVED2                          :bit4;
 end;

 TPCIE_STRAP_F2=bitpacked record
  STRAP_F2_EN                        :bit1;
  STRAP_F2_LEGACY_DEVICE_TYPE_EN     :bit1;
  STRAP_F2_MSI_EN                    :bit1;
  STRAP_F2_VC_EN                     :bit1;
  STRAP_F2_DSN_EN                    :bit1;
  STRAP_F2_AER_EN                    :bit1;
  STRAP_F2_ACS_EN                    :bit1;
  STRAP_F2_BAR_EN                    :bit1;
  STRAP_F2_PWR_EN                    :bit1;
  STRAP_F2_DPA_EN                    :bit1;
  STRAP_F2_ATS_EN                    :bit1;
  STRAP_F2_PAGE_REQ_EN               :bit1;
  STRAP_F2_PASID_EN                  :bit1;
  STRAP_F2_ECRC_CHECK_EN             :bit1;
  STRAP_F2_ECRC_GEN_EN               :bit1;
  STRAP_F2_CPL_ABORT_ERR_EN          :bit1;
  STRAP_F2_POISONED_ADVISORY_NONFATAL:bit1;
  RESERVED0                          :bit1;
  STRAP_F2_ATOMIC_EN                 :bit1;
  STRAP_F2_ATOMIC_64BIT_EN           :bit1;
  STRAP_F2_ATOMIC_ROUTING_EN         :bit1;
  STRAP_F2_MSI_MULTI_CAP             :bit3;
  RESERVED1                          :bit3;
  STRAP_F2_MSI_PERVECTOR_MASK_CAP    :bit1;
  RESERVED2                          :bit4;
 end;

 TPCIE_STRAP_F3=bit32;

 TPCIE_STRAP_F4=bit32;

 TPCIE_STRAP_F5=bit32;

 TPCIE_STRAP_F6=bit32;

 TPCIE_STRAP_F7=bit32;

 TPCIE_STRAP_PI=bitpacked record
  STRAP_QUICKSIM_START     :bit1;
  RESERVED0                :bit1;
  RESERVED1                :bit1;
  RESERVED2                :bit4;
  RESERVED3                :bit4;
  RESERVED4                :bit2;
  RESERVED5                :bit1;
  RESERVED6                :bit1;
  RESERVED7                :bit2;
  RESERVED8                :bit1;
  RESERVED9                :bit2;
  RESERVED10               :bit1;
  RESERVED11               :bit4;
  RESERVED12               :bit1;
  RESERVED13               :bit2;
  STRAP_TEST_TOGGLE_PATTERN:bit1;
  STRAP_TEST_TOGGLE_MODE   :bit1;
  RESERVED14               :bit1;
  RESERVED15               :bit1;
 end;

 TPCIE_WPR_CNTL=bitpacked record
  WPR_RESET_HOT_RST_EN:bit1;
  WPR_RESET_LNK_DWN_EN:bit1;
  WPR_RESET_LNK_DIS_EN:bit1;
  WPR_RESET_COR_EN    :bit1;
  WPR_RESET_REG_EN    :bit1;
  WPR_RESET_STY_EN    :bit1;
  WPR_RESET_PHY_EN    :bit1;
  RESERVED0           :bit25;
 end;

 TPERFMON_CNTL2=bitpacked record
  PERFMON_CNTOFF_INT_TYPE:bit1;
  RESERVED0              :bit31;
 end;

 TPLL_TEST_CNTL=bitpacked record
  TST_SRC_SEL   :bit4;
  TST_REF_SEL   :bit4;
  REF_TEST_COUNT:bit7;
  TST_RESET     :bit1;
  RESERVED0     :bit1;
  TEST_COUNT    :bit15;
 end;

 TPLL_VREG_CNTL=bitpacked record
  PLL_VREG_CNTL   :bit20;
  PLL_BG_VREG_BIAS:bit2;
  RESERVED0       :bit4;
  PLL_VREF_SEL    :bit1;
  RESERVED1       :bit1;
  PLL_VREG_BIAS   :bit4;
 end;

 TPWR_AVFS_CNTL=bitpacked record
  MmBusIn           :bit8;
  MmLclRdEn         :bit1;
  MmLclWrEn         :bit1;
  MmLclSz           :bit2;
  MmState           :bit6;
  PsmScanMode       :bit1;
  PsmGater          :bit1;
  PsmTrst           :bit1;
  PsmEn             :bit1;
  SkipPhaseEn       :bit1;
  Isolate           :bit1;
  AvfsRst           :bit1;
  PccIsolateEn      :bit1;
  DeepSleepIsolateEn:bit1;
  RESERVED0         :bit5;
 end;

 TRBBMIF_STATUS=bitpacked record
  RBBMIF_TIMEOUT_CLIENTS_DEC:bit15;
  RESERVED0                 :bit13;
  RBBMIF_TIMEOUT_OP         :bit1;
  RBBMIF_TIMEOUT_RDWR_STATUS:bit1;
  RBBMIF_TIMEOUT_ACK        :bit1;
  RBBMIF_TIMEOUT_MASK       :bit1;
 end;

 TRCU_MISC_CTRL=bitpacked record
  RESERVED0             :bit1;
  REG_DRV_RST_MODE      :bit1;
  RESERVED1             :bit1;
  REG_RCU_MEMREP_DIS    :bit1;
  REG_CC_FUSE_DISABLE   :bit1;
  REG_SAMU_FUSE_DISABLE :bit1;
  RESERVED2             :bit1;
  RESERVED3             :bit1;
  REG_CC_SRBM_RD_DISABLE:bit1;
  RESERVED4             :bit7;
  BREAK_PT1_DONE        :bit1;
  BREAK_PT2_DONE        :bit1;
  RESERVED5             :bit3;
  RESERVED6             :bit1;
  SAMU_START            :bit1;
  RST_PULSE_WIDTH       :bit9;
 end;

 TRCU_UC_EVENTS=bitpacked record
  RCU_TST_jpc_rep_req        :bit1;
  TST_RCU_jpc_rep_done       :bit1;
  drv_rst_mode               :bit1;
  SMU_DC_efuse_status_invalid:bit1;
  RESERVED0                  :bit2;
  TP_Tester                  :bit1;
  boot_seq_done              :bit1;
  sclk_deep_sleep_exit       :bit1;
  BREAK_PT1_ACTIVE           :bit1;
  BREAK_PT2_ACTIVE           :bit1;
  FCH_HALT                   :bit1;
  RESERVED1                  :bit1;
  RCU_GIO_fch_lockdown       :bit1;
  RESERVED2                  :bit2;
  INTERRUPTS_ENABLED         :bit1;
  RCU_DtmCnt0_Done           :bit1;
  RCU_DtmCnt1_Done           :bit1;
  RCU_DtmCnt2_Done           :bit1;
  RESERVED3                  :bit4;
  RESERVED4                  :bit2;
  RESERVED5                  :bit6;
 end;

 TRLC_CU_STATUS=bit32;

 TRLC_GPM_DEBUG=bit32;

 TRLC_LB_PARAMS=bitpacked record
  SKIP_L2_CHECK          :bit1;
  FIFO_SAMPLES           :bit7;
  PG_IDLE_SAMPLES        :bit8;
  PG_IDLE_SAMPLE_INTERVAL:bit16;
 end;

 TRLC_MAX_PG_CU=bitpacked record
  MAX_POWERED_UP_CU:bit8;
  SPARE            :bit24;
 end;

 TRLC_MGCG_CTRL=bitpacked record
  MGCG_EN             :bit1;
  SILICON_EN          :bit1;
  SIMULATION_EN       :bit1;
  ON_DELAY            :bit4;
  OFF_HYSTERESIS      :bit8;
  GC_CAC_MGCG_CLK_CNTL:bit1;
  SE_CAC_MGCG_CLK_CNTL:bit1;
  SPARE               :bit15;
 end;

 TRLC_SAFE_MODE=bitpacked record
  CMD      :bit1;
  MESSAGE  :bit4;
  RESERVED1:bit3;
  RESPONSE :bit4;
  RESERVED :bit20;
 end;

 TRLC_SPM_DEBUG=bit32;

 TRLC_SRM_DEBUG=bit32;

 TROM_BASE_ADDR=bit32;

 TROM_SW_DATA_1=bit32;

 TROM_SW_DATA_2=bit32;

 TROM_SW_DATA_3=bit32;

 TROM_SW_DATA_4=bit32;

 TROM_SW_DATA_5=bit32;

 TROM_SW_DATA_6=bit32;

 TROM_SW_DATA_7=bit32;

 TROM_SW_DATA_8=bit32;

 TROM_SW_DATA_9=bit32;

 TROM_SW_STATUS=bitpacked record
  ROM_SW_DONE:bit1;
  RESERVED0  :bit31;
 end;

 TSDMA0_PROGRAM=bit32;

 TSDMA0_VERSION=bitpacked record
  VALUE    :bit16;
  RESERVED0:bit16;
 end;

 TSDMA0_VM_CNTL=bitpacked record
  CMD      :bit4;
  RESERVED0:bit28;
 end;

 TSDMA1_PROGRAM=bit32;

 TSDMA1_VERSION=bitpacked record
  VALUE    :bit16;
  RESERVED0:bit16;
 end;

 TSDMA1_VM_CNTL=bitpacked record
  CMD      :bit4;
  RESERVED0:bit28;
 end;

 TSEM_VF_ENABLE=bitpacked record
  VALUE    :bit1;
  RESERVED0:bit31;
 end;

 TSH_MEM_CONFIG=bitpacked record
  ADDRESS_MODE  :bit2;
  PRIVATE_ATC   :bit1;
  ALIGNMENT_MODE:bit2;
  DEFAULT_MTYPE :bit3;
  APE1_MTYPE    :bit3;
  APE1_ATC      :bit1;
  RESERVED0     :bit20;
 end;

 TSMC_IND_INDEX=bit32;

 TSMC_MESSAGE_0=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MESSAGE_1=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MESSAGE_2=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MESSAGE_3=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MESSAGE_4=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MESSAGE_5=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MESSAGE_6=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MESSAGE_7=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MESSAGE_8=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MESSAGE_9=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MSG_ARG_0=bit32;

 TSMC_MSG_ARG_1=bit32;

 TSMC_MSG_ARG_2=bit32;

 TSMC_MSG_ARG_3=bit32;

 TSMC_MSG_ARG_4=bit32;

 TSMC_MSG_ARG_5=bit32;

 TSMC_MSG_ARG_6=bit32;

 TSMC_MSG_ARG_7=bit32;

 TSMC_MSG_ARG_8=bit32;

 TSMC_MSG_ARG_9=bit32;

 TSPMI_SPARE_EX=bit32;

 TSQC_WRITEBACK=bitpacked record
  DWB      :bit1;
  DIRTY    :bit1;
  RESERVED0:bit30;
 end;

 TSQ_FIFO_SIZES=bitpacked record
  INTERRUPT_FIFO_SIZE:bit4;
  RESERVED0          :bit4;
  TTRACE_FIFO_SIZE   :bit4;
  RESERVED1          :bit4;
  EXPORT_BUF_SIZE    :bit2;
  VMEM_DATA_FIFO_SIZE:bit2;
  RESERVED2          :bit12;
 end;

 TSQ_WAVE_HW_ID=bitpacked record
  WAVE_ID  :bit4;
  SIMD_ID  :bit2;
  PIPE_ID  :bit2;
  CU_ID    :bit4;
  SH_ID    :bit1;
  SE_ID    :bit2;
  RESERVED0:bit1;
  TG_ID    :bit4;
  VM_ID    :bit4;
  QUEUE_ID :bit3;
  STATE_ID :bit3;
  ME_ID    :bit2;
 end;

 TSQ_WAVE_PC_HI=bitpacked record
  PC_HI    :bit16;
  RESERVED0:bit16;
 end;

 TSQ_WAVE_PC_LO=bit32;

 TSQ_WAVE_TTMP0=bit32;

 TSQ_WAVE_TTMP1=bit32;

 TSQ_WAVE_TTMP2=bit32;

 TSQ_WAVE_TTMP3=bit32;

 TSQ_WAVE_TTMP4=bit32;

 TSQ_WAVE_TTMP5=bit32;

 TSQ_WAVE_TTMP6=bit32;

 TSQ_WAVE_TTMP7=bit32;

 TSQ_WAVE_TTMP8=bit32;

 TSQ_WAVE_TTMP9=bit32;

 TSRBM_CAM_DATA=bitpacked record
  CAM_ADDR     :bit16;
  CAM_REMAPADDR:bit16;
 end;

 TSRBM_GFX_CNTL=bitpacked record
  PIPEID   :bit2;
  MEID     :bit2;
  VMID     :bit4;
  QUEUEID  :bit3;
  RESERVED0:bit21;
 end;

 TSRBM_INT_CNTL=bitpacked record
  RDERR_INT_MASK:bit1;
  RAERR_INT_MASK:bit1;
  RESERVED0     :bit30;
 end;

 TSX_DEBUG_BUSY=bitpacked record
  POS_FREE_OR_VALIDS:bit1;
  POS_REQUESTER_BUSY:bit1;
  PA_SX_BUSY        :bit1;
  POS_SCBD_BUSY     :bit1;
  POS_BANK3VAL3_BUSY:bit1;
  POS_BANK3VAL2_BUSY:bit1;
  POS_BANK3VAL1_BUSY:bit1;
  POS_BANK3VAL0_BUSY:bit1;
  POS_BANK2VAL3_BUSY:bit1;
  POS_BANK2VAL2_BUSY:bit1;
  POS_BANK2VAL1_BUSY:bit1;
  POS_BANK2VAL0_BUSY:bit1;
  POS_BANK1VAL3_BUSY:bit1;
  POS_BANK1VAL2_BUSY:bit1;
  POS_BANK1VAL1_BUSY:bit1;
  POS_BANK1VAL0_BUSY:bit1;
  POS_BANK0VAL3_BUSY:bit1;
  POS_BANK0VAL2_BUSY:bit1;
  POS_BANK0VAL1_BUSY:bit1;
  POS_BANK0VAL0_BUSY:bit1;
  POS_INMUX_VALID   :bit1;
  WRCTRL1_VALIDQ3   :bit1;
  WRCTRL1_VALIDQ2   :bit1;
  WRCTRL1_VALIDQ1   :bit1;
  WRCTRL0_VALIDQ3   :bit1;
  WRCTRL0_VALIDQ2   :bit1;
  WRCTRL0_VALIDQ1   :bit1;
  PCCMD_VALID       :bit1;
  VDATA1_VALID      :bit1;
  VDATA0_VALID      :bit1;
  CMD_BUSYORVAL     :bit1;
  ADDR_BUSYORVAL    :bit1;
 end;

 TTA_DEBUG_DATA=bit32;

 TTDC_VRM_LIMIT=bitpacked record
  IDD :bit16;
  IDDC:bit16;
 end;

 TTD_DEBUG_DATA=bit32;

 TTMDS_CTL_BITS=bitpacked record
  TMDS_CTL0:bit1;
  RESERVED0:bit7;
  TMDS_CTL1:bit1;
  RESERVED1:bit7;
  TMDS_CTL2:bit1;
  RESERVED2:bit7;
  TMDS_CTL3:bit1;
  RESERVED3:bit7;
 end;

 TUVD_CGC_CTRL2=bitpacked record
  DYN_OCLK_RAMP_EN:bit1;
  DYN_RCLK_RAMP_EN:bit1;
  GATER_DIV_ID    :bit3;
  RESERVED0       :bit27;
 end;

 TUVD_CTX_INDEX=bitpacked record
  INDEX    :bit9;
  RESERVED0:bit23;
 end;

 TUVD_LMI_CTRL2=bitpacked record
  SPH_DIS               :bit1;
  STALL_ARB             :bit1;
  ASSERT_UMC_URGENT     :bit1;
  MASK_UMC_URGENT       :bit1;
  MCIF_WR_WATERMARK     :bit3;
  DRCITF_BUBBLE_FIX_DIS :bit1;
  STALL_ARB_UMC         :bit1;
  MC_READ_ID_SEL        :bit2;
  MC_WRITE_ID_SEL       :bit2;
  VCPU_NC0_EXT_EN       :bit1;
  VCPU_NC1_EXT_EN       :bit1;
  SPU_EXTRA_CID_EN      :bit1;
  RE_OFFLOAD_EN         :bit1;
  RE_OFLD_MIF_WR_REQ_NUM:bit8;
  RESERVED0             :bit7;
 end;

 TUVD_SEMA_CNTL=bitpacked record
  SEMAPHORE_EN     :bit1;
  ADVANCED_MODE_DIS:bit1;
  RESERVED0        :bit30;
 end;

 TUVD_VCPU_CNTL=bitpacked record
  IRQ_ERR                :bit4;
  AXI_MAX_BRST_SIZE_IS_4 :bit1;
  PMB_ED_ENABLE          :bit1;
  PMB_SOFT_RESET         :bit1;
  RBBM_SOFT_RESET        :bit1;
  ABORT_REQ              :bit1;
  CLK_EN                 :bit1;
  TRCE_EN                :bit1;
  TRCE_MUX               :bit2;
  DBG_MUX                :bit3;
  JTAG_EN                :bit1;
  MIF_WR_LOW_THRESHOLD_BP:bit1;
  TIMEOUT_DIS            :bit1;
  SUVD_EN                :bit1;
  PRB_TIMEOUT_VAL        :bit8;
  CABAC_MB_ACC           :bit1;
  RESERVED0              :bit1;
  WMV9_EN                :bit1;
  RE_OFFLOAD_EN          :bit1;
 end;

 TVBLANK_STATUS=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit3;
  RESERVED2:bit1;
  RESERVED3:bit7;
  RESERVED4:bit1;
  RESERVED5:bit3;
  RESERVED6:bit1;
  RESERVED7:bit1;
  RESERVED8:bit14;
 end;

 TVCE_LMI_CTRL2=bitpacked record
  RESERVED0    :bit1;
  STALL_ARB    :bit1;
  RESERVED1    :bit1;
  RESERVED2    :bit1;
  RESERVED3    :bit3;
  RESERVED4    :bit1;
  STALL_ARB_UMC:bit1;
  RESERVED5    :bit2;
  RESERVED6    :bit21;
 end;

 TVCE_VCPU_CNTL=bitpacked record
  CLK_EN         :bit1;
  RESERVED0      :bit1;
  RESERVED1      :bit14;
  RESERVED2      :bit1;
  RESERVED3      :bit1;
  RBBM_SOFT_RESET:bit1;
  RESERVED4      :bit1;
  RESERVED5      :bit1;
  RESERVED6      :bit11;
 end;

 TVGT_ES_PER_GS=bitpacked record
  ES_PER_GS:bit11;
  RESERVED0:bit21;
 end;

 TVGT_GS_PER_ES=bitpacked record
  GS_PER_ES:bit11;
  RESERVED0:bit21;
 end;

 TVGT_GS_PER_VS=bitpacked record
  GS_PER_VS:bit4;
  RESERVED0:bit28;
 end;

 TVGT_REUSE_OFF=bitpacked record
  REUSE_OFF:bit1;
  RESERVED0:bit31;
 end;

 TVIEWPORT_SIZE=bitpacked record
  VIEWPORT_HEIGHT:bit14;
  RESERVED0      :bit2;
  VIEWPORT_WIDTH :bit14;
  RESERVED1      :bit2;
 end;

 TWB_DEBUG_CTRL=bitpacked record
  WB_DEBUG_EN :bit1;
  RESERVED0   :bit5;
  WB_DEBUG_SEL:bit2;
  RESERVED1   :bit24;
 end;

 TWB_SOFT_RESET=bitpacked record
  WB_SOFT_RESET:bit1;
  RESERVED0    :bit31;
 end;

 TWD_DEBUG_CNTL=bitpacked record
  WD_DEBUG_INDX     :bit6;
  WD_DEBUG_SEL_BUS_B:bit1;
  RESERVED0         :bit25;
 end;

 TWD_DEBUG_DATA=bit32;

 TWD_DEBUG_REG0=bitpacked record
  wd_busy_extended      :bit1;
  wd_nodma_busy_extended:bit1;
  wd_busy               :bit1;
  wd_nodma_busy         :bit1;
  rbiu_busy             :bit1;
  spl_dma_busy          :bit1;
  spl_di_busy           :bit1;
  vgt0_active_q         :bit1;
  vgt1_active_q         :bit1;
  spl_dma_p1_busy       :bit1;
  rbiu_dr_p1_fifo_busy  :bit1;
  rbiu_di_p1_fifo_busy  :bit1;
  SPARE2                :bit1;
  rbiu_dr_fifo_busy     :bit1;
  rbiu_spl_dr_valid     :bit1;
  spl_rbiu_dr_read      :bit1;
  SPARE3                :bit1;
  rbiu_di_fifo_busy     :bit1;
  rbiu_spl_di_valid     :bit1;
  spl_rbiu_di_read      :bit1;
  se0_synced_q          :bit1;
  se1_synced_q          :bit1;
  se2_synced_q          :bit1;
  se3_synced_q          :bit1;
  reg_clk_busy          :bit1;
  input_clk_busy        :bit1;
  core_clk_busy         :bit1;
  vgt2_active_q         :bit1;
  sclk_reg_vld          :bit1;
  sclk_input_vld        :bit1;
  sclk_core_vld         :bit1;
  vgt3_active_q         :bit1;
 end;

 TWD_DEBUG_REG1=bitpacked record
  grbm_fifo_empty        :bit1;
  grbm_fifo_full         :bit1;
  grbm_fifo_we           :bit1;
  grbm_fifo_re           :bit1;
  draw_initiator_valid_q :bit1;
  event_initiator_valid_q:bit1;
  event_addr_valid_q     :bit1;
  dma_request_valid_q    :bit1;
  SPARE0                 :bit1;
  min_indx_valid_q       :bit1;
  max_indx_valid_q       :bit1;
  indx_offset_valid_q    :bit1;
  grbm_fifo_rdata_reg_id :bit5;
  grbm_fifo_rdata_state  :bit3;
  free_cnt_q             :bit6;
  rbiu_di_fifo_we        :bit1;
  rbiu_dr_fifo_we        :bit1;
  rbiu_di_fifo_empty     :bit1;
  rbiu_di_fifo_full      :bit1;
  rbiu_dr_fifo_empty     :bit1;
  rbiu_dr_fifo_full      :bit1;
 end;

 TWD_DEBUG_REG2=bitpacked record
  p1_grbm_fifo_empty        :bit1;
  p1_grbm_fifo_full         :bit1;
  p1_grbm_fifo_we           :bit1;
  p1_grbm_fifo_re           :bit1;
  p1_draw_initiator_valid_q :bit1;
  p1_event_initiator_valid_q:bit1;
  p1_event_addr_valid_q     :bit1;
  p1_dma_request_valid_q    :bit1;
  SPARE0                    :bit1;
  p1_min_indx_valid_q       :bit1;
  p1_max_indx_valid_q       :bit1;
  p1_indx_offset_valid_q    :bit1;
  p1_grbm_fifo_rdata_reg_id :bit5;
  p1_grbm_fifo_rdata_state  :bit3;
  p1_free_cnt_q             :bit6;
  p1_rbiu_di_fifo_we        :bit1;
  p1_rbiu_dr_fifo_we        :bit1;
  p1_rbiu_di_fifo_empty     :bit1;
  p1_rbiu_di_fifo_full      :bit1;
  p1_rbiu_dr_fifo_empty     :bit1;
  p1_rbiu_dr_fifo_full      :bit1;
 end;

 TWD_DEBUG_REG3=bitpacked record
  rbiu_spl_dr_valid        :bit1;
  SPARE0                   :bit1;
  pipe0_dr                 :bit1;
  pipe0_rtr                :bit1;
  pipe1_dr                 :bit1;
  pipe1_rtr                :bit1;
  wd_subdma_fifo_empty     :bit1;
  wd_subdma_fifo_full      :bit1;
  dma_buf_type_p0_q        :bit2;
  dma_zero_indices_p0_q    :bit1;
  dma_req_path_p3_q        :bit1;
  dma_not_eop_p1_q         :bit1;
  out_of_range_p4          :bit1;
  last_sub_dma_p3_q        :bit1;
  last_rdreq_of_sub_dma_p4 :bit1;
  WD_IA_dma_send_d         :bit1;
  WD_IA_dma_rtr            :bit1;
  WD_IA1_dma_send_d        :bit1;
  WD_IA1_dma_rtr           :bit1;
  last_inst_of_dma_p2      :bit1;
  last_sd_of_inst_p2       :bit1;
  last_sd_of_dma_p2        :bit1;
  SPARE1                   :bit1;
  WD_IA_dma_busy           :bit1;
  WD_IA1_dma_busy          :bit1;
  send_to_ia1_p3_q         :bit1;
  dma_wd_switch_on_eop_p3_q:bit1;
  pipe3_dr                 :bit1;
  pipe3_rtr                :bit1;
  wd_dma2draw_fifo_empty   :bit1;
  wd_dma2draw_fifo_full    :bit1;
 end;

 TWD_DEBUG_REG4=bitpacked record
  rbiu_spl_di_valid       :bit1;
  spl_rbiu_di_read        :bit1;
  rbiu_spl_p1_di_valid    :bit1;
  spl_rbiu_p1_di_read     :bit1;
  pipe0_dr                :bit1;
  pipe0_rtr               :bit1;
  pipe1_dr                :bit1;
  pipe1_rtr               :bit1;
  pipe2_dr                :bit1;
  pipe2_rtr               :bit1;
  pipe3_ld                :bit1;
  pipe3_rtr               :bit1;
  WD_IA_draw_send_d       :bit1;
  WD_IA_draw_rtr          :bit1;
  di_type_p0              :bit2;
  di_state_sel_p1_q       :bit3;
  di_wd_switch_on_eop_p1_q:bit1;
  rbiu_spl_pipe0_lockout  :bit1;
  last_inst_of_di_p2      :bit1;
  last_sd_of_inst_p2      :bit1;
  last_sd_of_di_p2        :bit1;
  not_eop_wait_p1_q       :bit1;
  not_eop_wait_q          :bit1;
  ext_event_wait_p1_q     :bit1;
  ext_event_wait_q        :bit1;
  WD_IA1_draw_send_d      :bit1;
  WD_IA1_draw_rtr         :bit1;
  send_to_ia1_q           :bit1;
  dual_ia_mode            :bit1;
 end;

 TWD_DEBUG_REG5=bitpacked record
  p1_rbiu_spl_dr_valid        :bit1;
  SPARE0                      :bit1;
  p1_pipe0_dr                 :bit1;
  p1_pipe0_rtr                :bit1;
  p1_pipe1_dr                 :bit1;
  p1_pipe1_rtr                :bit1;
  p1_wd_subdma_fifo_empty     :bit1;
  p1_wd_subdma_fifo_full      :bit1;
  p1_dma_buf_type_p0_q        :bit2;
  p1_dma_zero_indices_p0_q    :bit1;
  p1_dma_req_path_p3_q        :bit1;
  p1_dma_not_eop_p1_q         :bit1;
  p1_out_of_range_p4          :bit1;
  p1_last_sub_dma_p3_q        :bit1;
  p1_last_rdreq_of_sub_dma_p4 :bit1;
  p1_WD_IA_dma_send_d         :bit1;
  p1_WD_IA_dma_rtr            :bit1;
  p1_WD_IA1_dma_send_d        :bit1;
  p1_WD_IA1_dma_rtr           :bit1;
  p1_last_inst_of_dma_p2      :bit1;
  p1_last_sd_of_inst_p2       :bit1;
  p1_last_sd_of_dma_p2        :bit1;
  SPARE1                      :bit1;
  p1_WD_IA_dma_busy           :bit1;
  p1_WD_IA1_dma_busy          :bit1;
  p1_send_to_ia1_p3_q         :bit1;
  p1_dma_wd_switch_on_eop_p3_q:bit1;
  p1_pipe3_dr                 :bit1;
  p1_pipe3_rtr                :bit1;
  p1_wd_dma2draw_fifo_empty   :bit1;
  p1_wd_dma2draw_fifo_full    :bit1;
 end;

 TWD_DEBUG_REG6=bit32;

 TWD_DEBUG_REG7=bitpacked record
  SE0VGT_WD_thdgrp_send_in   :bit1;
  wd_arb_se0_input_fifo_re   :bit1;
  wd_arb_se0_input_fifo_empty:bit1;
  wd_arb_se0_input_fifo_full :bit1;
  SE1VGT_WD_thdgrp_send_in   :bit1;
  wd_arb_se1_input_fifo_re   :bit1;
  wd_arb_se1_input_fifo_empty:bit1;
  wd_arb_se1_input_fifo_full :bit1;
  SPARE1                     :bit4;
  SPARE2                     :bit4;
  te11_arb_state_q           :bit3;
  SPARE5                     :bit1;
  se0_thdgrp_is_event        :bit1;
  se0_thdgrp_eop             :bit1;
  se1_thdgrp_is_event        :bit1;
  se1_thdgrp_eop             :bit1;
  SPARE6                     :bit4;
  tfreq_arb_tgroup_rtr       :bit1;
  arb_tfreq_tgroup_rts       :bit1;
  arb_tfreq_tgroup_event     :bit1;
  te11_arb_busy              :bit1;
 end;

 TWD_DEBUG_REG8=bitpacked record
  pipe0_dr               :bit1;
  pipe1_dr               :bit1;
  pipe0_rtr              :bit1;
  pipe1_rtr              :bit1;
  tfreq_tg_fifo_empty    :bit1;
  tfreq_tg_fifo_full     :bit1;
  tf_data_fifo_busy_q    :bit1;
  tf_data_fifo_rtr_q     :bit1;
  tf_skid_fifo_empty     :bit1;
  tf_skid_fifo_full      :bit1;
  wd_tc_rdreq_rtr_q      :bit1;
  last_req_of_tg_p2      :bit1;
  se0spi_wd_hs_done_cnt_q:bit6;
  event_flag_p1_q        :bit1;
  null_flag_p1_q         :bit1;
  tf_data_fifo_cnt_q     :bit7;
  second_tf_ret_data_q   :bit1;
  first_req_of_tg_p1_q   :bit1;
  WD_TC_rdreq_send_out   :bit1;
  WD_TC_rdnfo_stall_out  :bit1;
  TC_WD_rdret_valid_in   :bit1;
 end;

 TWD_DEBUG_REG9=bitpacked record
  pipe0_dr                :bit1;
  pipec_tf_dr             :bit1;
  pipe2_dr                :bit1;
  event_or_null_flags_p0_q:bit1;
  pipe0_rtr               :bit1;
  pipe1_rtr               :bit1;
  pipec_tf_rtr            :bit1;
  pipe2_rtr               :bit1;
  ttp_patch_fifo_full     :bit1;
  ttp_patch_fifo_empty    :bit1;
  ttp_tf_fifo_empty       :bit1;
  SPARE0                  :bit5;
  tf_fetch_state_q        :bit3;
  last_patch_of_tg        :bit1;
  tf_pointer_p0_q         :bit4;
  dynamic_hs_p0_q         :bit1;
  first_fetch_of_tg_p0_q  :bit1;
  mem_is_even             :bit1;
  SPARE1                  :bit1;
  SPARE2                  :bit2;
  pipe4_dr                :bit1;
  pipe4_rtr               :bit1;
 end;

 TXDMA_PG_WDATA=bit32;

 TXDMA_SLV_CNTL=bitpacked record
  XDMA_SLV_READ_LINES      :bit1;
  RESERVED0                :bit8;
  XDMA_SLV_MEM_READY       :bit1;
  XDMA_SLV_ACTIVE          :bit1;
  RESERVED1                :bit1;
  XDMA_SLV_ALPHA_POSITION  :bit2;
  RESERVED2                :bit2;
  XDMA_SLV_ENABLE          :bit1;
  RESERVED3                :bit2;
  XDMA_SLV_READ_LAT_TEST_EN:bit1;
  XDMA_SLV_SOFT_RESET      :bit1;
  RESERVED4                :bit3;
  XDMA_SLV_REQ_MAXED_OUT   :bit1;
  XDMA_SLV_WB_BURST_RESET  :bit1;
  RESERVED5                :bit6;
 end;

 TAFMT_AVI_INFO0=bitpacked record
  AFMT_AVI_INFO_CHECKSUM:bit8;
  AFMT_AVI_INFO_S       :bit2;
  AFMT_AVI_INFO_B       :bit2;
  AFMT_AVI_INFO_A       :bit1;
  AFMT_AVI_INFO_Y       :bit2;
  AFMT_AVI_INFO_PB1_RSVD:bit1;
  AFMT_AVI_INFO_R       :bit4;
  AFMT_AVI_INFO_M       :bit2;
  AFMT_AVI_INFO_C       :bit2;
  AFMT_AVI_INFO_SC      :bit2;
  AFMT_AVI_INFO_Q       :bit2;
  AFMT_AVI_INFO_EC      :bit3;
  AFMT_AVI_INFO_ITC     :bit1;
 end;

 TAFMT_AVI_INFO1=bitpacked record
  AFMT_AVI_INFO_VIC     :bit7;
  AFMT_AVI_INFO_PB4_RSVD:bit1;
  AFMT_AVI_INFO_PR      :bit4;
  AFMT_AVI_INFO_CN      :bit2;
  AFMT_AVI_INFO_YQ      :bit2;
  AFMT_AVI_INFO_TOP     :bit16;
 end;

 TAFMT_AVI_INFO2=bitpacked record
  AFMT_AVI_INFO_BOTTOM:bit16;
  AFMT_AVI_INFO_LEFT  :bit16;
 end;

 TAFMT_AVI_INFO3=bitpacked record
  AFMT_AVI_INFO_RIGHT  :bit16;
  RESERVED0            :bit8;
  AFMT_AVI_INFO_VERSION:bit8;
 end;

 TAFMT_GENERIC_0=bitpacked record
  AFMT_GENERIC_BYTE0:bit8;
  AFMT_GENERIC_BYTE1:bit8;
  AFMT_GENERIC_BYTE2:bit8;
  AFMT_GENERIC_BYTE3:bit8;
 end;

 TAFMT_GENERIC_1=bitpacked record
  AFMT_GENERIC_BYTE4:bit8;
  AFMT_GENERIC_BYTE5:bit8;
  AFMT_GENERIC_BYTE6:bit8;
  AFMT_GENERIC_BYTE7:bit8;
 end;

 TAFMT_GENERIC_2=bitpacked record
  AFMT_GENERIC_BYTE8 :bit8;
  AFMT_GENERIC_BYTE9 :bit8;
  AFMT_GENERIC_BYTE10:bit8;
  AFMT_GENERIC_BYTE11:bit8;
 end;

 TAFMT_GENERIC_3=bitpacked record
  AFMT_GENERIC_BYTE12:bit8;
  AFMT_GENERIC_BYTE13:bit8;
  AFMT_GENERIC_BYTE14:bit8;
  AFMT_GENERIC_BYTE15:bit8;
 end;

 TAFMT_GENERIC_4=bitpacked record
  AFMT_GENERIC_BYTE16:bit8;
  AFMT_GENERIC_BYTE17:bit8;
  AFMT_GENERIC_BYTE18:bit8;
  AFMT_GENERIC_BYTE19:bit8;
 end;

 TAFMT_GENERIC_5=bitpacked record
  AFMT_GENERIC_BYTE20:bit8;
  AFMT_GENERIC_BYTE21:bit8;
  AFMT_GENERIC_BYTE22:bit8;
  AFMT_GENERIC_BYTE23:bit8;
 end;

 TAFMT_GENERIC_6=bitpacked record
  AFMT_GENERIC_BYTE24:bit8;
  AFMT_GENERIC_BYTE25:bit8;
  AFMT_GENERIC_BYTE26:bit8;
  AFMT_GENERIC_BYTE27:bit8;
 end;

 TAFMT_GENERIC_7=bitpacked record
  AFMT_GENERIC_BYTE28:bit8;
  AFMT_GENERIC_BYTE29:bit8;
  AFMT_GENERIC_BYTE30:bit8;
  AFMT_GENERIC_BYTE31:bit8;
 end;

 TATC_ATS_STATUS=bitpacked record
  BUSY              :bit1;
  CRASHED           :bit1;
  DEADLOCK_DETECTION:bit1;
  RESERVED0         :bit29;
 end;

 TATC_L2_STATUS2=bitpacked record
  CACHE_ADDRESS_MODE:bit3;
  PARITY_ERROR_INFO :bit8;
  RESERVED0         :bit21;
 end;

 TAUX_SW_CONTROL=bitpacked record
  AUX_SW_GO         :bit1;
  RESERVED0         :bit1;
  AUX_LS_READ_TRIG  :bit1;
  RESERVED1         :bit1;
  AUX_SW_START_DELAY:bit4;
  RESERVED2         :bit8;
  AUX_SW_WR_BYTES   :bit5;
  RESERVED3         :bit11;
 end;

 TBACO_CNTL_MISC=bitpacked record
  BIF_ROM_REQ_DIS        :bit1;
  BIF_AZ_REQ_DIS         :bit1;
  BACO_LINK_RST_WIDTH_SEL:bit2;
  BACO_REFCLK_SEL        :bit1;
  RESERVED0              :bit27;
 end;

 TBCI_DEBUG_READ=bitpacked record
  DATA     :bit24;
  RESERVED0:bit8;
 end;

 TBIF_BACO_DEBUG=bitpacked record
  BIF_BACO_SCANDUMP_FLG:bit1;
  RESERVED0            :bit31;
 end;

 TBIF_BME_STATUS=bitpacked record
  DMA_ON_BME_LOW      :bit1;
  RESERVED0           :bit15;
  CLEAR_DMA_ON_BME_LOW:bit1;
  RESERVED1           :bit15;
 end;

 TBIF_DEBUG_CNTL=bitpacked record
  DEBUG_EN          :bit1;
  DEBUG_MULTIBLOCKEN:bit1;
  DEBUG_OUT_EN      :bit1;
  DEBUG_PAD_SEL     :bit1;
  DEBUG_BYTESEL_BLK1:bit1;
  DEBUG_BYTESEL_BLK2:bit1;
  DEBUG_SYNC_EN     :bit1;
  DEBUG_SWAP        :bit1;
  DEBUG_IDSEL_BLK1  :bit5;
  RESERVED0         :bit3;
  DEBUG_IDSEL_BLK2  :bit5;
  RESERVED1         :bit3;
  DEBUG_IDSEL_XSP   :bit1;
  RESERVED2         :bit5;
  DEBUG_SYNC_CLKSEL :bit2;
 end;

 TBIOS_SCRATCH_0=bit32;

 TBIOS_SCRATCH_1=bit32;

 TBIOS_SCRATCH_2=bit32;

 TBIOS_SCRATCH_3=bit32;

 TBIOS_SCRATCH_4=bit32;

 TBIOS_SCRATCH_5=bit32;

 TBIOS_SCRATCH_6=bit32;

 TBIOS_SCRATCH_7=bit32;

 TBIOS_SCRATCH_8=bit32;

 TBIOS_SCRATCH_9=bit32;

 TCB_BLEND_ALPHA=bit32;

 TCB_BLEND_GREEN=bit32;

 TCB_COLOR0_BASE=bit32;

 TCB_COLOR0_INFO=bitpacked record
  ENDIAN                   :bit2;
  FORMAT                   :bit5;
  LINEAR_GENERAL           :bit1;
  NUMBER_TYPE              :bit3;
  COMP_SWAP                :bit2;
  FAST_CLEAR               :bit1;
  COMPRESSION              :bit1;
  BLEND_CLAMP              :bit1;
  BLEND_BYPASS             :bit1;
  SIMPLE_FLOAT             :bit1;
  ROUND_MODE               :bit1;
  CMASK_IS_LINEAR          :bit1;
  BLEND_OPT_DONT_RD_DST    :bit3;
  BLEND_OPT_DISCARD_PIXEL  :bit3;
  FMASK_COMPRESSION_DISABLE:bit1;
  FMASK_COMPRESS_1FRAG_ONLY:bit1;
  DCC_ENABLE               :bit1;
  CMASK_ADDR_TYPE          :bit2;
  ALT_TILE_MODE            :bit1;
 end;

 TCB_COLOR0_VIEW=bitpacked record
  SLICE_START:bit11;
  RESERVED0  :bit2;
  SLICE_MAX  :bit11;
  RESERVED1  :bit8;
 end;

 TCB_COLOR1_BASE=bit32;

 TCB_COLOR1_INFO=bitpacked record
  ENDIAN                   :bit2;
  FORMAT                   :bit5;
  LINEAR_GENERAL           :bit1;
  NUMBER_TYPE              :bit3;
  COMP_SWAP                :bit2;
  FAST_CLEAR               :bit1;
  COMPRESSION              :bit1;
  BLEND_CLAMP              :bit1;
  BLEND_BYPASS             :bit1;
  SIMPLE_FLOAT             :bit1;
  ROUND_MODE               :bit1;
  CMASK_IS_LINEAR          :bit1;
  BLEND_OPT_DONT_RD_DST    :bit3;
  BLEND_OPT_DISCARD_PIXEL  :bit3;
  FMASK_COMPRESSION_DISABLE:bit1;
  FMASK_COMPRESS_1FRAG_ONLY:bit1;
  DCC_ENABLE               :bit1;
  CMASK_ADDR_TYPE          :bit2;
  ALT_TILE_MODE            :bit1;
 end;

 TCB_COLOR1_VIEW=bitpacked record
  SLICE_START:bit11;
  RESERVED0  :bit2;
  SLICE_MAX  :bit11;
  RESERVED1  :bit8;
 end;

 TCB_COLOR2_BASE=bit32;

 TCB_COLOR2_INFO=bitpacked record
  ENDIAN                   :bit2;
  FORMAT                   :bit5;
  LINEAR_GENERAL           :bit1;
  NUMBER_TYPE              :bit3;
  COMP_SWAP                :bit2;
  FAST_CLEAR               :bit1;
  COMPRESSION              :bit1;
  BLEND_CLAMP              :bit1;
  BLEND_BYPASS             :bit1;
  SIMPLE_FLOAT             :bit1;
  ROUND_MODE               :bit1;
  CMASK_IS_LINEAR          :bit1;
  BLEND_OPT_DONT_RD_DST    :bit3;
  BLEND_OPT_DISCARD_PIXEL  :bit3;
  FMASK_COMPRESSION_DISABLE:bit1;
  FMASK_COMPRESS_1FRAG_ONLY:bit1;
  DCC_ENABLE               :bit1;
  CMASK_ADDR_TYPE          :bit2;
  ALT_TILE_MODE            :bit1;
 end;

 TCB_COLOR2_VIEW=bitpacked record
  SLICE_START:bit11;
  RESERVED0  :bit2;
  SLICE_MAX  :bit11;
  RESERVED1  :bit8;
 end;

 TCB_COLOR3_BASE=bit32;

 TCB_COLOR3_INFO=bitpacked record
  ENDIAN                   :bit2;
  FORMAT                   :bit5;
  LINEAR_GENERAL           :bit1;
  NUMBER_TYPE              :bit3;
  COMP_SWAP                :bit2;
  FAST_CLEAR               :bit1;
  COMPRESSION              :bit1;
  BLEND_CLAMP              :bit1;
  BLEND_BYPASS             :bit1;
  SIMPLE_FLOAT             :bit1;
  ROUND_MODE               :bit1;
  CMASK_IS_LINEAR          :bit1;
  BLEND_OPT_DONT_RD_DST    :bit3;
  BLEND_OPT_DISCARD_PIXEL  :bit3;
  FMASK_COMPRESSION_DISABLE:bit1;
  FMASK_COMPRESS_1FRAG_ONLY:bit1;
  DCC_ENABLE               :bit1;
  CMASK_ADDR_TYPE          :bit2;
  ALT_TILE_MODE            :bit1;
 end;

 TCB_COLOR3_VIEW=bitpacked record
  SLICE_START:bit11;
  RESERVED0  :bit2;
  SLICE_MAX  :bit11;
  RESERVED1  :bit8;
 end;

 TCB_COLOR4_BASE=bit32;

 TCB_COLOR4_INFO=bitpacked record
  ENDIAN                   :bit2;
  FORMAT                   :bit5;
  LINEAR_GENERAL           :bit1;
  NUMBER_TYPE              :bit3;
  COMP_SWAP                :bit2;
  FAST_CLEAR               :bit1;
  COMPRESSION              :bit1;
  BLEND_CLAMP              :bit1;
  BLEND_BYPASS             :bit1;
  SIMPLE_FLOAT             :bit1;
  ROUND_MODE               :bit1;
  CMASK_IS_LINEAR          :bit1;
  BLEND_OPT_DONT_RD_DST    :bit3;
  BLEND_OPT_DISCARD_PIXEL  :bit3;
  FMASK_COMPRESSION_DISABLE:bit1;
  FMASK_COMPRESS_1FRAG_ONLY:bit1;
  DCC_ENABLE               :bit1;
  CMASK_ADDR_TYPE          :bit2;
  ALT_TILE_MODE            :bit1;
 end;

 TCB_COLOR4_VIEW=bitpacked record
  SLICE_START:bit11;
  RESERVED0  :bit2;
  SLICE_MAX  :bit11;
  RESERVED1  :bit8;
 end;

 TCB_COLOR5_BASE=bit32;

 TCB_COLOR5_INFO=bitpacked record
  ENDIAN                   :bit2;
  FORMAT                   :bit5;
  LINEAR_GENERAL           :bit1;
  NUMBER_TYPE              :bit3;
  COMP_SWAP                :bit2;
  FAST_CLEAR               :bit1;
  COMPRESSION              :bit1;
  BLEND_CLAMP              :bit1;
  BLEND_BYPASS             :bit1;
  SIMPLE_FLOAT             :bit1;
  ROUND_MODE               :bit1;
  CMASK_IS_LINEAR          :bit1;
  BLEND_OPT_DONT_RD_DST    :bit3;
  BLEND_OPT_DISCARD_PIXEL  :bit3;
  FMASK_COMPRESSION_DISABLE:bit1;
  FMASK_COMPRESS_1FRAG_ONLY:bit1;
  DCC_ENABLE               :bit1;
  CMASK_ADDR_TYPE          :bit2;
  ALT_TILE_MODE            :bit1;
 end;

 TCB_COLOR5_VIEW=bitpacked record
  SLICE_START:bit11;
  RESERVED0  :bit2;
  SLICE_MAX  :bit11;
  RESERVED1  :bit8;
 end;

 TCB_COLOR6_BASE=bit32;

 TCB_COLOR6_INFO=bitpacked record
  ENDIAN                   :bit2;
  FORMAT                   :bit5;
  LINEAR_GENERAL           :bit1;
  NUMBER_TYPE              :bit3;
  COMP_SWAP                :bit2;
  FAST_CLEAR               :bit1;
  COMPRESSION              :bit1;
  BLEND_CLAMP              :bit1;
  BLEND_BYPASS             :bit1;
  SIMPLE_FLOAT             :bit1;
  ROUND_MODE               :bit1;
  CMASK_IS_LINEAR          :bit1;
  BLEND_OPT_DONT_RD_DST    :bit3;
  BLEND_OPT_DISCARD_PIXEL  :bit3;
  FMASK_COMPRESSION_DISABLE:bit1;
  FMASK_COMPRESS_1FRAG_ONLY:bit1;
  DCC_ENABLE               :bit1;
  CMASK_ADDR_TYPE          :bit2;
  ALT_TILE_MODE            :bit1;
 end;

 TCB_COLOR6_VIEW=bitpacked record
  SLICE_START:bit11;
  RESERVED0  :bit2;
  SLICE_MAX  :bit11;
  RESERVED1  :bit8;
 end;

 TCB_COLOR7_BASE=bit32;

 TCB_COLOR7_INFO=bitpacked record
  ENDIAN                   :bit2;
  FORMAT                   :bit5;
  LINEAR_GENERAL           :bit1;
  NUMBER_TYPE              :bit3;
  COMP_SWAP                :bit2;
  FAST_CLEAR               :bit1;
  COMPRESSION              :bit1;
  BLEND_CLAMP              :bit1;
  BLEND_BYPASS             :bit1;
  SIMPLE_FLOAT             :bit1;
  ROUND_MODE               :bit1;
  CMASK_IS_LINEAR          :bit1;
  BLEND_OPT_DONT_RD_DST    :bit3;
  BLEND_OPT_DISCARD_PIXEL  :bit3;
  FMASK_COMPRESSION_DISABLE:bit1;
  FMASK_COMPRESS_1FRAG_ONLY:bit1;
  DCC_ENABLE               :bit1;
  CMASK_ADDR_TYPE          :bit2;
  ALT_TILE_MODE            :bit1;
 end;

 TCB_COLOR7_VIEW=bitpacked record
  SLICE_START:bit11;
  RESERVED0  :bit2;
  SLICE_MAX  :bit11;
  RESERVED1  :bit8;
 end;

 TCB_DCC_CONTROL=bitpacked record
  OVERWRITE_COMBINER_DISABLE            :bit1;
  OVERWRITE_COMBINER_MRT_SHARING_DISABLE:bit1;
  OVERWRITE_COMBINER_WATERMARK          :bit5;
  RESERVED0                             :bit25;
 end;

 TCB_DEBUG_BUS_1=bitpacked record
  CB_BUSY                   :bit1;
  DB_CB_TILE_VALID_READY    :bit1;
  DB_CB_TILE_VALID_READYB   :bit1;
  DB_CB_TILE_VALIDB_READY   :bit1;
  DB_CB_TILE_VALIDB_READYB  :bit1;
  DB_CB_LQUAD_VALID_READY   :bit1;
  DB_CB_LQUAD_VALID_READYB  :bit1;
  DB_CB_LQUAD_VALIDB_READY  :bit1;
  DB_CB_LQUAD_VALIDB_READYB :bit1;
  CB_TAP_WRREQ_VALID_READY  :bit1;
  CB_TAP_WRREQ_VALID_READYB :bit1;
  CB_TAP_WRREQ_VALIDB_READY :bit1;
  CB_TAP_WRREQ_VALIDB_READYB:bit1;
  CB_TAP_RDREQ_VALID_READY  :bit1;
  CB_TAP_RDREQ_VALID_READYB :bit1;
  CB_TAP_RDREQ_VALIDB_READY :bit1;
  CB_TAP_RDREQ_VALIDB_READYB:bit1;
  CM_FC_TILE_VALID_READY    :bit1;
  CM_FC_TILE_VALID_READYB   :bit1;
  CM_FC_TILE_VALIDB_READY   :bit1;
  CM_FC_TILE_VALIDB_READYB  :bit1;
  FC_CLEAR_QUAD_VALID_READY :bit1;
  FC_CLEAR_QUAD_VALID_READYB:bit1;
  FC_CLEAR_QUAD_VALIDB_READY:bit1;
  RESERVED0                 :bit8;
 end;

 TCB_DEBUG_BUS_2=bitpacked record
  FC_CLEAR_QUAD_VALIDB_READYB    :bit1;
  FC_QUAD_RESIDENCY_STALL        :bit1;
  FC_CC_QUADFRAG_VALID_READY     :bit1;
  FC_CC_QUADFRAG_VALID_READYB    :bit1;
  FC_CC_QUADFRAG_VALIDB_READY    :bit1;
  FC_CC_QUADFRAG_VALIDB_READYB   :bit1;
  FOP_IN_VALID_READY             :bit1;
  FOP_IN_VALID_READYB            :bit1;
  FOP_IN_VALIDB_READY            :bit1;
  FOP_IN_VALIDB_READYB           :bit1;
  FOP_FMASK_RAW_STALL            :bit1;
  FOP_FMASK_BYPASS_STALL         :bit1;
  CC_IB_TB_FRAG_VALID_READY      :bit1;
  CC_IB_TB_FRAG_VALID_READYB     :bit1;
  CC_IB_TB_FRAG_VALIDB_READY     :bit1;
  CC_IB_TB_FRAG_VALIDB_READYB    :bit1;
  CC_IB_SR_FRAG_VALID_READY      :bit1;
  CC_IB_SR_FRAG_VALID_READYB     :bit1;
  CC_IB_SR_FRAG_VALIDB_READY     :bit1;
  CC_IB_SR_FRAG_VALIDB_READYB    :bit1;
  CC_RB_BC_EVENFRAG_VALID_READY  :bit1;
  CC_RB_BC_EVENFRAG_VALID_READYB :bit1;
  CC_RB_BC_EVENFRAG_VALIDB_READY :bit1;
  CC_RB_BC_EVENFRAG_VALIDB_READYB:bit1;
  RESERVED0                      :bit8;
 end;

 TCB_SHADER_MASK=bitpacked record
  OUTPUT0_ENABLE:bit4;
  OUTPUT1_ENABLE:bit4;
  OUTPUT2_ENABLE:bit4;
  OUTPUT3_ENABLE:bit4;
  OUTPUT4_ENABLE:bit4;
  OUTPUT5_ENABLE:bit4;
  OUTPUT6_ENABLE:bit4;
  OUTPUT7_ENABLE:bit4;
 end;

 TCB_TARGET_MASK=bitpacked record
  TARGET0_ENABLE:bit4;
  TARGET1_ENABLE:bit4;
  TARGET2_ENABLE:bit4;
  TARGET3_ENABLE:bit4;
  TARGET4_ENABLE:bit4;
  TARGET5_ENABLE:bit4;
  TARGET6_ENABLE:bit4;
  TARGET7_ENABLE:bit4;
 end;

 TCC_DC_PIPE_DIS=bitpacked record
  RESERVED0       :bit1;
  DC_PIPE_DIS     :bit6;
  RESERVED1       :bit1;
  MCIF_WB_URG_OVRD:bit1;
  MCIF_WB_URG_LVL :bit4;
  RESERVED2       :bit19;
 end;

 TCC_FCTRL_FUSES=bitpacked record
  RESERVED0              :bit1;
  EXT_EFUSE_MACRO_PRESENT:bit1;
  RESERVED1              :bit30;
 end;

 TCC_THM_STRAPS0=bitpacked record
  RESERVED0         :bit1;
  TMON0_BGADJ       :bit8;
  TMON1_BGADJ       :bit8;
  TMON_CMON_FUSE_SEL:bit1;
  NUM_ACQ           :bit3;
  TMON_CLK_SEL      :bit3;
  TMON_CONFIG_SOURCE:bit1;
  CTF_DISABLE       :bit1;
  TMON0_DISABLE     :bit1;
  TMON1_DISABLE     :bit1;
  TMON2_DISABLE     :bit1;
  TMON3_DISABLE     :bit1;
  RESERVED1         :bit2;
 end;

 TCFG_LNC_WINDOW=bitpacked record
  CFG_LNC_WINDOW0:bit24;
  RESERVED0      :bit8;
 end;

 TCG_CLKPIN_CNTL=bitpacked record
  RESERVED0    :bit1;
  XTALIN_DIVIDE:bit1;
  BCLK_AS_XCLK :bit1;
  RESERVED1    :bit29;
 end;

 TCG_DCLK_STATUS=bitpacked record
  DCLK_STATUS          :bit1;
  DCLK_DIR_CNTL_DONETOG:bit1;
  RESERVED0            :bit30;
 end;

 TCG_ECLK_STATUS=bitpacked record
  ECLK_STATUS          :bit1;
  ECLK_DIR_CNTL_DONETOG:bit1;
  RESERVED0            :bit30;
 end;

 TCG_MCLK_STATUS=bitpacked record
  MCLK_STATUS          :bit1;
  MCLK_DIR_CNTL_DONETOG:bit1;
  RESERVED0            :bit30;
 end;

 TCG_TACH_STATUS=bit32;

 TCG_THERMAL_INT=bitpacked record
  DIG_THERM_CTF :bit8;
  DIG_THERM_INTH:bit8;
  DIG_THERM_INTL:bit8;
  THERM_INT_MASK:bit4;
  RESERVED0     :bit2;
  RESERVED1     :bit2;
 end;

 TCG_VCLK_STATUS=bitpacked record
  VCLK_STATUS          :bit1;
  VCLK_DIR_CNTL_DONETOG:bit1;
  RESERVED0            :bit30;
 end;

 TCLIENT0_OFFSET=bit32;

 TCLIENT0_STATUS=bit32;

 TCLIENT1_OFFSET=bit32;

 TCLIENT2_OFFSET=bit32;

 TCLIENT2_STATUS=bit32;

 TCLIENT3_OFFSET=bit32;

 TCLIENT3_STATUS=bit32;

 TCLIENT4_OFFSET=bit32;

 TCLIENT4_STATUS=bit32;

 TCOL_MAN_UPDATE=bitpacked record
  COL_MAN_UPDATE_PENDING         :bit1;
  COL_MAN_UPDATE_TAKEN           :bit1;
  RESERVED0                      :bit14;
  COL_MAN_UPDATE_LOCK            :bit1;
  RESERVED1                      :bit7;
  COL_MAN_DISABLE_MULTIPLE_UPDATE:bit1;
  RESERVED2                      :bit7;
 end;

 TCOMPUTE_PGM_HI=bitpacked record
  DATA     :bit8;
  INST_ATC :bit1;
  RESERVED0:bit23;
 end;

 TCOMPUTE_PGM_LO=bit32;

 TCOMPUTE_TBA_HI=bitpacked record
  DATA     :bit8;
  RESERVED0:bit24;
 end;

 TCOMPUTE_TBA_LO=bit32;

 TCOMPUTE_TMA_HI=bitpacked record
  DATA     :bit8;
  RESERVED0:bit24;
 end;

 TCOMPUTE_TMA_LO=bit32;

 TCONFIG_F0_BASE=bit32;

 TCONFIG_MEMSIZE=bit32;

 TCPC_INT_STATUS=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_STATUS  :bit1;
  DEQUEUE_REQUEST_INT_STATUS   :bit1;
  CP_ECC_ERROR_INT_STATUS      :bit1;
  SUA_VIOLATION_INT_STATUS     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_STATUS  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_STATUS          :bit1;
  OPCODE_ERROR_INT_STATUS      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_STATUS        :bit1;
  RESERVED_BIT_ERROR_INT_STATUS:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_STATUS          :bit1;
  GENERIC1_INT_STATUS          :bit1;
  GENERIC0_INT_STATUS          :bit1;
 end;

 TCP_APPEND_DATA=bit32;

 TCP_CE_DE_COUNT=bit32;

 TCP_DE_CE_COUNT=bit32;

 TCP_DE_DE_COUNT=bit32;

 TCP_DFY_ADDR_HI=bit32;

 TCP_DFY_ADDR_LO=bitpacked record
  RESERVED0:bit5;
  ADDR_LO  :bit27;
 end;

 TCP_DFY_DATA_10=bit32;

 TCP_DFY_DATA_11=bit32;

 TCP_DFY_DATA_12=bit32;

 TCP_DFY_DATA_13=bit32;

 TCP_DFY_DATA_14=bit32;

 TCP_DFY_DATA_15=bit32;

 TCP_DRAW_OBJECT=bit32;

 TCP_ENDIAN_SWAP=bitpacked record
  ENDIAN_SWAP:bit2;
  RESERVED0  :bit30;
 end;

 TCP_HPD_STATUS0=bitpacked record
  QUEUE_STATE    :bit5;
  MAPPED_QUEUE   :bit3;
  QUEUE_AVAILABLE:bit8;
  RESERVED0      :bit16;
 end;

 TCP_HQD_IB_RPTR=bitpacked record
  CONSUMED_OFFSET:bit20;
  RESERVED0      :bit12;
 end;

 TCP_HQD_IQ_RPTR=bitpacked record
  OFFSET   :bit6;
  RESERVED0:bit26;
 end;

 TCP_HQD_OFFLOAD=bitpacked record
  DMA_OFFLOAD   :bit1;
  DMA_OFFLOAD_EN:bit1;
  RESERVED0     :bit2;
  EOP_OFFLOAD   :bit1;
  EOP_OFFLOAD_EN:bit1;
  RESERVED1     :bit26;
 end;

 TCP_HQD_PQ_BASE=bit32;

 TCP_HQD_PQ_RPTR=bit32;

 TCP_HQD_PQ_WPTR=bit32;

 TCP_HQD_QUANTUM=bitpacked record
  QUANTUM_EN      :bit1;
  RESERVED0       :bit3;
  QUANTUM_SCALE   :bit1;
  RESERVED1       :bit3;
  QUANTUM_DURATION:bit6;
  RESERVED2       :bit17;
  QUANTUM_ACTIVE  :bit1;
 end;

 TCP_IB1_BASE_HI=bitpacked record
  IB1_BASE_HI:bit16;
  RESERVED0  :bit16;
 end;

 TCP_IB1_BASE_LO=bitpacked record
  RESERVED0  :bit2;
  IB1_BASE_LO:bit30;
 end;

 TCP_IB2_BASE_HI=bitpacked record
  IB2_BASE_HI:bit16;
  RESERVED0  :bit16;
 end;

 TCP_IB2_BASE_LO=bitpacked record
  RESERVED0  :bit2;
  IB2_BASE_LO:bit30;
 end;

 TCP_MAX_CONTEXT=bitpacked record
  MAX_CONTEXT:bit3;
  RESERVED0  :bit29;
 end;

 TCP_ME_RAM_DATA=bit32;

 TCP_MQD_CONTROL=bitpacked record
  VMID             :bit4;
  RESERVED0        :bit4;
  RESERVED1        :bit1;
  RESERVED2        :bit3;
  PROCESSING_MQD   :bit1;
  PROCESSING_MQD_EN:bit1;
  RESERVED3        :bit9;
  MQD_ATC          :bit1;
  CACHE_POLICY     :bit1;
  RESERVED4        :bit2;
  MTYPE            :bit2;
  RESERVED5        :bit3;
 end;

 TCP_RB0_BASE_HI=bitpacked record
  RB_BASE_HI:bit8;
  RESERVED0 :bit24;
 end;

 TCP_RB1_BASE_HI=bitpacked record
  RB_BASE_HI:bit8;
  RESERVED0 :bit24;
 end;

 TCP_ROQ_RB_STAT=bitpacked record
  ROQ_RPTR_PRIMARY:bit10;
  RESERVED0       :bit6;
  ROQ_WPTR_PRIMARY:bit10;
  RESERVED1       :bit6;
 end;

 TCP_STQ_WR_STAT=bitpacked record
  STQ_WPTR :bit10;
  RESERVED0:bit22;
 end;

 TCP_VIRT_STATUS=bit32;

 TCP_VMID_STATUS=bitpacked record
  PREEMPT_DE_STATUS:bit16;
  PREEMPT_CE_STATUS:bit16;
 end;

 TCRTC_MASTER_EN=bitpacked record
  CRTC_MASTER_EN:bit1;
  RESERVED0     :bit31;
 end;

 TCSPRIV_CONNECT=bitpacked record
  DOORBELL_OFFSET:bit21;
  QUEUE_ID       :bit3;
  RESERVED0      :bit2;
  VMID           :bit4;
  RESERVED1      :bit1;
  UNORD_DISP     :bit1;
 end;

 TDAC_CLK_ENABLE=bitpacked record
  DACA_CLK_ENABLE:bit1;
  RESERVED0      :bit3;
  DACB_CLK_ENABLE:bit1;
  RESERVED1      :bit27;
 end;

 TDAC_DFT_CONFIG=bit32;

 TDAC_FORCE_DATA=bitpacked record
  DAC_FORCE_DATA:bit10;
  RESERVED0     :bit22;
 end;

 TDAC_MACRO_CNTL=bitpacked record
  RESERVED0:bit2;
  RESERVED1:bit6;
  RESERVED2:bit6;
  RESERVED3:bit2;
  RESERVED4:bit6;
  RESERVED5:bit2;
  RESERVED6:bit4;
  RESERVED7:bit1;
  RESERVED8:bit3;
 end;

 TDB_DEPTH_CLEAR=bit32;

 TDB_DEPTH_SLICE=bitpacked record
  SLICE_TILE_MAX:bit22;
  RESERVED0     :bit10;
 end;

 TDB_FIFO_DEPTH1=bitpacked record
  MI_RDREQ_FIFO_DEPTH   :bit5;
  MI_WRREQ_FIFO_DEPTH   :bit5;
  MCC_DEPTH             :bit6;
  QC_DEPTH              :bit5;
  LTILE_PROBE_FIFO_DEPTH:bit8;
  RESERVED0             :bit3;
 end;

 TDB_FIFO_DEPTH2=bitpacked record
  EQUAD_FIFO_DEPTH   :bit8;
  ETILE_OP_FIFO_DEPTH:bit7;
  LQUAD_FIFO_DEPTH   :bit10;
  LTILE_OP_FIFO_DEPTH:bit7;
 end;

 TDB_Z_READ_BASE=bit32;

 TDCIO_GSL0_CNTL=bitpacked record
  DCIO_GSL0_VSYNC_SEL        :bit3;
  RESERVED0                  :bit5;
  DCIO_GSL0_TIMING_SYNC_SEL  :bit3;
  RESERVED1                  :bit5;
  DCIO_GSL0_GLOBAL_UNLOCK_SEL:bit3;
  RESERVED2                  :bit13;
 end;

 TDCIO_GSL1_CNTL=bitpacked record
  DCIO_GSL1_VSYNC_SEL        :bit3;
  RESERVED0                  :bit5;
  DCIO_GSL1_TIMING_SYNC_SEL  :bit3;
  RESERVED1                  :bit5;
  DCIO_GSL1_GLOBAL_UNLOCK_SEL:bit3;
  RESERVED2                  :bit13;
 end;

 TDCIO_GSL2_CNTL=bitpacked record
  DCIO_GSL2_VSYNC_SEL        :bit3;
  RESERVED0                  :bit5;
  DCIO_GSL2_TIMING_SYNC_SEL  :bit3;
  RESERVED1                  :bit5;
  DCIO_GSL2_GLOBAL_UNLOCK_SEL:bit3;
  RESERVED2                  :bit13;
 end;

 TDCI_SOFT_RESET=bitpacked record
  VGA_SOFT_RESET      :bit1;
  VIP_SOFT_RESET      :bit1;
  MCIF_SOFT_RESET     :bit1;
  FBC_SOFT_RESET      :bit1;
  DMIF0_SOFT_RESET    :bit1;
  DMIF1_SOFT_RESET    :bit1;
  DMIF2_SOFT_RESET    :bit1;
  DMIF3_SOFT_RESET    :bit1;
  DMIF4_SOFT_RESET    :bit1;
  DMIF5_SOFT_RESET    :bit1;
  DCFEV0_L_SOFT_RESET :bit1;
  DCFEV0_C_SOFT_RESET :bit1;
  DMIFARB_SOFT_RESET  :bit1;
  RESERVED0           :bit3;
  MCIF_DWB_SOFT_RESET :bit1;
  MCIF_CWB0_SOFT_RESET:bit1;
  MCIF_CWB1_SOFT_RESET:bit1;
  RESERVED1           :bit13;
 end;

 TDCO_SOFT_RESET=bitpacked record
  DACA_SOFT_RESET       :bit1;
  RESERVED0             :bit3;
  I2S0_SPDIF0_SOFT_RESET:bit1;
  I2S1_SOFT_RESET       :bit1;
  SPDIF1_SOFT_RESET     :bit1;
  RESERVED1             :bit5;
  DB_CLK_SOFT_RESET     :bit1;
  RESERVED2             :bit3;
  FMT0_SOFT_RESET       :bit1;
  FMT1_SOFT_RESET       :bit1;
  FMT2_SOFT_RESET       :bit1;
  FMT3_SOFT_RESET       :bit1;
  FMT4_SOFT_RESET       :bit1;
  FMT5_SOFT_RESET       :bit1;
  RESERVED3             :bit2;
  MVP_SOFT_RESET        :bit1;
  ABM_SOFT_RESET        :bit1;
  RESERVED4             :bit1;
  DVO_SOFT_RESET        :bit1;
  RESERVED5             :bit4;
 end;

 TDC_GPIO_DDC1_A=bitpacked record
  DC_GPIO_DDC1CLK_A :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC1DATA_A:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC1_Y=bitpacked record
  DC_GPIO_DDC1CLK_Y :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC1DATA_Y:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC2_A=bitpacked record
  DC_GPIO_DDC2CLK_A :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC2DATA_A:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC2_Y=bitpacked record
  DC_GPIO_DDC2CLK_Y :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC2DATA_Y:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC3_A=bitpacked record
  DC_GPIO_DDC3CLK_A :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC3DATA_A:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC3_Y=bitpacked record
  DC_GPIO_DDC3CLK_Y :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC3DATA_Y:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC4_A=bitpacked record
  DC_GPIO_DDC4CLK_A :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC4DATA_A:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC4_Y=bitpacked record
  DC_GPIO_DDC4CLK_Y :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC4DATA_Y:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC5_A=bitpacked record
  DC_GPIO_DDC5CLK_A :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC5DATA_A:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC5_Y=bitpacked record
  DC_GPIO_DDC5CLK_Y :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC5DATA_Y:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC6_A=bitpacked record
  DC_GPIO_DDC6CLK_A :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC6DATA_A:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_DDC6_Y=bitpacked record
  DC_GPIO_DDC6CLK_Y :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DDC6DATA_Y:bit1;
  RESERVED1         :bit23;
 end;

 TDC_GPIO_HPD_EN=bitpacked record
  DC_GPIO_HPD1_EN :bit1;
  HPD1_SCHMEN_PI  :bit1;
  HPD1_SLEWNCORE  :bit1;
  RX_HPD_SCHMEN_PI:bit1;
  RX_HPD_SLEWNCORE:bit1;
  RESERVED0       :bit1;
  HPD1_SEL0       :bit1;
  RX_HPD_SEL0     :bit1;
  DC_GPIO_HPD2_EN :bit1;
  RESERVED1       :bit7;
  DC_GPIO_HPD3_EN :bit1;
  RESERVED2       :bit7;
  DC_GPIO_HPD4_EN :bit1;
  RESERVED3       :bit1;
  DC_GPIO_HPD5_EN :bit1;
  RESERVED4       :bit1;
  DC_GPIO_HPD6_EN :bit1;
  RESERVED5       :bit3;
 end;

 TDC_HPD_CONTROL=bitpacked record
  DC_HPD_CONNECTION_TIMER:bit13;
  RESERVED0              :bit3;
  DC_HPD_RX_INT_TIMER    :bit10;
  RESERVED1              :bit2;
  DC_HPD_EN              :bit1;
  RESERVED2              :bit3;
 end;

 TDC_I2C_CONTROL=bitpacked record
  DC_I2C_GO               :bit1;
  DC_I2C_SOFT_RESET       :bit1;
  DC_I2C_SEND_RESET       :bit1;
  DC_I2C_SW_STATUS_RESET  :bit1;
  RESERVED0               :bit1;
  RESERVED1               :bit1;
  RESERVED2               :bit1;
  RESERVED3               :bit1;
  DC_I2C_DDC_SELECT       :bit3;
  RESERVED4               :bit9;
  DC_I2C_TRANSACTION_COUNT:bit2;
  RESERVED5               :bit9;
  DC_I2C_DBG_REF_SEL      :bit1;
 end;

 TDC_LUT_CONTROL=bitpacked record
  DC_LUT_INC_B                :bit4;
  DC_LUT_DATA_B_SIGNED_EN     :bit1;
  DC_LUT_DATA_B_FLOAT_POINT_EN:bit1;
  DC_LUT_DATA_B_FORMAT        :bit2;
  DC_LUT_INC_G                :bit4;
  DC_LUT_DATA_G_SIGNED_EN     :bit1;
  DC_LUT_DATA_G_FLOAT_POINT_EN:bit1;
  DC_LUT_DATA_G_FORMAT        :bit2;
  DC_LUT_INC_R                :bit4;
  DC_LUT_DATA_R_SIGNED_EN     :bit1;
  DC_LUT_DATA_R_FLOAT_POINT_EN:bit1;
  DC_LUT_DATA_R_FORMAT        :bit2;
  RESERVED0                   :bit8;
 end;

 TDC_LUT_RW_MODE=bitpacked record
  DC_LUT_RW_MODE  :bit1;
  RESERVED0       :bit15;
  DC_LUT_ERROR    :bit1;
  DC_LUT_ERROR_RST:bit1;
  RESERVED1       :bit14;
 end;

 TDENORM_CONTROL=bitpacked record
  DENORM_MODE     :bit3;
  RESERVED0       :bit1;
  DENORM_14BIT_OUT:bit1;
  RESERVED1       :bit27;
 end;

 TDESKTOP_HEIGHT=bitpacked record
  RESERVED0:bit14;
  RESERVED1:bit18;
 end;

 TDEVICE_STATUS2=bitpacked record
  RESERVED :bit16;
  RESERVED0:bit16;
 end;

 TDIDT_DBR_CTRL0=bitpacked record
  DIDT_CTRL_EN        :bit1;
  USE_REF_CLOCK       :bit1;
  PHASE_OFFSET        :bit2;
  DIDT_CTRL_RST       :bit1;
  DIDT_CLK_EN_OVERRIDE:bit1;
  RESERVED0           :bit6;
  RESERVED1           :bit6;
  UNUSED_0            :bit14;
 end;

 TDIDT_DBR_CTRL1=bitpacked record
  MIN_POWER:bit16;
  MAX_POWER:bit16;
 end;

 TDIDT_DBR_CTRL2=bitpacked record
  MAX_POWER_DELTA         :bit14;
  UNUSED_0                :bit2;
  SHORT_TERM_INTERVAL_SIZE:bit10;
  UNUSED_1                :bit1;
  LONG_TERM_INTERVAL_RATIO:bit4;
  UNUSED_2                :bit1;
 end;

 TDIDT_IND_INDEX=bit32;

 TDIDT_TCP_CTRL0=bitpacked record
  DIDT_CTRL_EN              :bit1;
  USE_REF_CLOCK             :bit1;
  PHASE_OFFSET              :bit2;
  DIDT_CTRL_RST             :bit1;
  DIDT_CLK_EN_OVERRIDE      :bit1;
  DIDT_MAX_STALLS_ALLOWED_HI:bit6;
  DIDT_MAX_STALLS_ALLOWED_LO:bit6;
  UNUSED_0                  :bit14;
 end;

 TDIDT_TCP_CTRL1=bitpacked record
  MIN_POWER:bit16;
  MAX_POWER:bit16;
 end;

 TDIDT_TCP_CTRL2=bitpacked record
  MAX_POWER_DELTA         :bit14;
  RESERVED0               :bit2;
  SHORT_TERM_INTERVAL_SIZE:bit10;
  RESERVED1               :bit1;
  LONG_TERM_INTERVAL_RATIO:bit4;
  RESERVED2               :bit1;
 end;

 TDIG_BE_EN_CNTL=bitpacked record
  DIG_ENABLE      :bit1;
  RESERVED0       :bit7;
  DIG_SYMCLK_BE_ON:bit1;
  RESERVED1       :bit23;
 end;

 TDIG_SOFT_RESET=bitpacked record
  DIGA_FE_SOFT_RESET:bit1;
  DIGA_BE_SOFT_RESET:bit1;
  RESERVED0         :bit1;
  RESERVED1         :bit1;
  DIGB_FE_SOFT_RESET:bit1;
  DIGB_BE_SOFT_RESET:bit1;
  RESERVED2         :bit1;
  RESERVED3         :bit1;
  DIGC_FE_SOFT_RESET:bit1;
  DIGC_BE_SOFT_RESET:bit1;
  RESERVED4         :bit1;
  RESERVED5         :bit1;
  DIGD_FE_SOFT_RESET:bit1;
  DIGD_BE_SOFT_RESET:bit1;
  RESERVED6         :bit1;
  RESERVED7         :bit1;
  DIGE_FE_SOFT_RESET:bit1;
  DIGE_BE_SOFT_RESET:bit1;
  RESERVED8         :bit1;
  RESERVED9         :bit1;
  DIGF_FE_SOFT_RESET:bit1;
  DIGF_BE_SOFT_RESET:bit1;
  RESERVED10        :bit1;
  RESERVED11        :bit1;
  DIGG_FE_SOFT_RESET:bit1;
  DIGG_BE_SOFT_RESET:bit1;
  RESERVED12        :bit1;
  RESERVED13        :bit4;
  DPDBG_SOFT_RESET  :bit1;
 end;

 TDMIF_ADDR_CALC=bitpacked record
  RESERVED0                       :bit4;
  ADDR_CONFIG_PIPE_INTERLEAVE_SIZE:bit3;
  RESERVED1                       :bit21;
  ADDR_CONFIG_ROW_SIZE            :bit2;
  RESERVED2                       :bit2;
 end;

 TDPG_HW_DEBUG_A=bit32;

 TDPG_HW_DEBUG_B=bit32;

 TDP_AUX_DEBUG_A=bit32;

 TDP_AUX_DEBUG_B=bit32;

 TDP_AUX_DEBUG_C=bit32;

 TDP_AUX_DEBUG_D=bit32;

 TDP_AUX_DEBUG_E=bit32;

 TDP_AUX_DEBUG_F=bit32;

 TDP_AUX_DEBUG_G=bit32;

 TDP_AUX_DEBUG_H=bit32;

 TDP_AUX_DEBUG_I=bit32;

 TDP_AUX_DEBUG_J=bit32;

 TDP_AUX_DEBUG_K=bit32;

 TDP_AUX_DEBUG_L=bit32;

 TDP_AUX_DEBUG_M=bit32;

 TDP_AUX_DEBUG_N=bit32;

 TDP_AUX_DEBUG_O=bit32;

 TDP_AUX_DEBUG_P=bit32;

 TDP_AUX_DEBUG_Q=bit32;

 TDP_DPHY_CRC_EN=bitpacked record
  DPHY_CRC_EN          :bit1;
  RESERVED0            :bit3;
  DPHY_CRC_CONT_EN     :bit1;
  RESERVED1            :bit3;
  DPHY_CRC_RESULT_VALID:bit1;
  RESERVED2            :bit23;
 end;

 TDP_DTO0_MODULO=bit32;

 TDP_DTO1_MODULO=bit32;

 TDP_DTO2_MODULO=bit32;

 TDP_DTO3_MODULO=bit32;

 TDP_DTO4_MODULO=bit32;

 TDP_DTO5_MODULO=bit32;

 TDVO_CLK_ENABLE=bitpacked record
  DVO_CLK_ENABLE:bit1;
  RESERVED0     :bit31;
 end;

 TFBC_DEBUG_COMP=bitpacked record
  FBC_COMP_SWAP                      :bit2;
  RESERVED0                          :bit1;
  FBC_COMP_RSIZE                     :bit1;
  FBC_COMP_BUSY_HYSTERESIS           :bit4;
  FBC_COMP_CLK_CNTL                  :bit2;
  FBC_COMP_PRIVILEGED_ACCESS_ENABLE  :bit1;
  FBC_COMP_ADDRESS_TRANSLATION_ENABLE:bit1;
  RESERVED1                          :bit20;
 end;

 TFEATURE_STATUS=bitpacked record
  SCLK_DPM_ON          :bit1;
  MCLK_DPM_ON          :bit1;
  LCLK_DPM_ON          :bit1;
  UVD_DPM_ON           :bit1;
  VCE_DPM_ON           :bit1;
  SAMU_DPM_ON          :bit1;
  ACP_DPM_ON           :bit1;
  PCIE_DPM_ON          :bit1;
  BAPM_ON              :bit1;
  LPMX_ON              :bit1;
  NBDPM_ON             :bit1;
  LHTC_ON              :bit1;
  VPC_ON               :bit1;
  VOLTAGE_CONTROLLER_ON:bit1;
  TDC_LIMIT_ON         :bit1;
  GPU_CAC_ON           :bit1;
  AVS_ON               :bit1;
  SPMI_ON              :bit1;
  SCLK_DPM_FORCED      :bit1;
  MCLK_DPM_FORCED      :bit1;
  LCLK_DPM_FORCED      :bit1;
  PCIE_DPM_FORCED      :bit1;
  RESERVED             :bit10;
 end;

 TFIRMWARE_FLAGS=bitpacked record
  INTERRUPTS_ENABLED:bit1;
  RESERVED0         :bit23;
  TEST_COUNT        :bit8;
 end;

 TFMT_CLAMP_CNTL=bitpacked record
  FMT_CLAMP_DATA_EN     :bit1;
  RESERVED0             :bit15;
  FMT_CLAMP_COLOR_FORMAT:bit3;
  RESERVED1             :bit13;
 end;

 TFMT_DEBUG_CNTL=bitpacked record
  FMT_DEBUG_COLOR_SELECT:bit2;
  RESERVED0             :bit30;
 end;

 TGB_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit1;
  NUM_GPUS               :bit3;
  RESERVED5              :bit1;
  MULTI_GPU_TILE_SIZE    :bit2;
  RESERVED6              :bit2;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED7              :bit1;
 end;

 TGB_BACKEND_MAP=bit32;

 TGB_TILE_MODE10=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE11=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE12=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE13=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE14=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE15=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE16=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE17=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE18=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE19=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE20=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE21=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE22=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE23=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE24=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE25=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE26=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE27=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE28=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE29=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE30=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGB_TILE_MODE31=bitpacked record
  MICRO_TILE_MODE    :bit2;
  ARRAY_MODE         :bit4;
  PIPE_CONFIG        :bit5;
  TILE_SPLIT         :bit3;
  BANK_WIDTH         :bit2;
  BANK_HEIGHT        :bit2;
  MACRO_TILE_ASPECT  :bit2;
  NUM_BANKS          :bit2;
  MICRO_TILE_MODE_NEW:bit3;
  SAMPLE_SPLIT       :bit2;
  RESERVED0          :bit5;
 end;

 TGCK_MCLK_FUSES=bitpacked record
  StartupMClkDid:bit7;
  MClkADCA      :bit4;
  MClkDDCA      :bit2;
  MClkDiDtWait  :bit3;
  MClkDiDtFloor :bit2;
  RESERVED0     :bit14;
 end;

 TGC_CAC_ACC_CU0=bit32;

 TGC_CAC_ACC_CU1=bit32;

 TGC_CAC_ACC_CU2=bit32;

 TGC_CAC_ACC_CU3=bit32;

 TGC_CAC_ACC_CU4=bit32;

 TGC_CAC_ACC_CU5=bit32;

 TGC_CAC_ACC_CU6=bit32;

 TGC_CAC_ACC_CU7=bit32;

 TGC_CAC_ACC_CU8=bit32;

 TGC_CAC_ACC_CU9=bit32;

 TGC_CAC_OVRD_CU=bitpacked record
  OVRRD_SELECT:bit16;
  OVRRD_VALUE :bit16;
 end;

 TGDS_ATOM_READ0=bit32;

 TGDS_ATOM_READ1=bit32;

 TGDS_DEBUG_CNTL=bitpacked record
  GDS_DEBUG_INDX:bit5;
  UNUSED        :bit27;
 end;

 TGDS_DEBUG_DATA=bit32;

 TGDS_DEBUG_REG0=bitpacked record
  spare1               :bit6;
  write_buff_valid     :bit1;
  wr_pixel_nxt_ptr     :bit5;
  last_pixel_ptr       :bit1;
  cstate               :bit4;
  buff_write           :bit1;
  flush_request        :bit1;
  wr_buffer_wr_complete:bit1;
  wbuf_fifo_empty      :bit1;
  wbuf_fifo_full       :bit1;
  spare                :bit10;
 end;

 TGDS_DEBUG_REG1=bitpacked record
  tag_hit        :bit1;
  tag_miss       :bit1;
  pixel_addr     :bit15;
  pixel_vld      :bit1;
  data_ready     :bit1;
  awaiting_data  :bit1;
  addr_fifo_full :bit1;
  addr_fifo_empty:bit1;
  buffer_loaded  :bit1;
  buffer_invalid :bit1;
  spare          :bit8;
 end;

 TGDS_DEBUG_REG2=bitpacked record
  ds_full        :bit1;
  ds_credit_avail:bit1;
  ord_idx_free   :bit1;
  cmd_write      :bit1;
  app_sel        :bit4;
  req            :bit15;
  spare          :bit9;
 end;

 TGDS_DEBUG_REG3=bitpacked record
  pipe_num_busy :bit11;
  pipe0_busy_num:bit4;
  spare         :bit17;
 end;

 TGDS_DEBUG_REG4=bitpacked record
  gws_busy           :bit1;
  gws_req            :bit1;
  gws_out_stall      :bit1;
  cur_reso           :bit6;
  cur_reso_head_valid:bit1;
  cur_reso_head_dirty:bit1;
  cur_reso_head_flag :bit1;
  cur_reso_fed       :bit1;
  cur_reso_barrier   :bit1;
  cur_reso_flag      :bit1;
  cur_reso_cnt_gt0   :bit1;
  credit_cnt_gt0     :bit1;
  cmd_write          :bit1;
  grbm_gws_reso_wr   :bit1;
  grbm_gws_reso_rd   :bit1;
  ram_read_busy      :bit1;
  gws_bulkfree       :bit1;
  ram_gws_re         :bit1;
  ram_gws_we         :bit1;
  spare              :bit8;
 end;

 TGDS_DEBUG_REG5=bitpacked record
  write_dis         :bit1;
  dec_error         :bit1;
  alloc_opco_error  :bit1;
  dealloc_opco_error:bit1;
  wrap_opco_error   :bit1;
  spare             :bit3;
  error_ds_address  :bit14;
  spare1            :bit10;
 end;

 TGDS_DEBUG_REG6=bitpacked record
  oa_busy         :bit1;
  counters_enabled:bit4;
  counters_busy   :bit16;
  spare           :bit11;
 end;

 TGDS_EDC_OA_DED=bitpacked record
  ME0_GFXHP3D_PIX_DED:bit1;
  ME0_GFXHP3D_VTX_DED:bit1;
  ME0_CS_DED         :bit1;
  UNUSED0            :bit1;
  ME1_PIPE0_DED      :bit1;
  ME1_PIPE1_DED      :bit1;
  ME1_PIPE2_DED      :bit1;
  ME1_PIPE3_DED      :bit1;
  ME2_PIPE0_DED      :bit1;
  ME2_PIPE1_DED      :bit1;
  ME2_PIPE2_DED      :bit1;
  ME2_PIPE3_DED      :bit1;
  UNUSED1            :bit20;
 end;

 TGDS_GWS_RESET0=bitpacked record
  RESOURCE0_RESET :bit1;
  RESOURCE1_RESET :bit1;
  RESOURCE2_RESET :bit1;
  RESOURCE3_RESET :bit1;
  RESOURCE4_RESET :bit1;
  RESOURCE5_RESET :bit1;
  RESOURCE6_RESET :bit1;
  RESOURCE7_RESET :bit1;
  RESOURCE8_RESET :bit1;
  RESOURCE9_RESET :bit1;
  RESOURCE10_RESET:bit1;
  RESOURCE11_RESET:bit1;
  RESOURCE12_RESET:bit1;
  RESOURCE13_RESET:bit1;
  RESOURCE14_RESET:bit1;
  RESOURCE15_RESET:bit1;
  RESOURCE16_RESET:bit1;
  RESOURCE17_RESET:bit1;
  RESOURCE18_RESET:bit1;
  RESOURCE19_RESET:bit1;
  RESOURCE20_RESET:bit1;
  RESOURCE21_RESET:bit1;
  RESOURCE22_RESET:bit1;
  RESOURCE23_RESET:bit1;
  RESOURCE24_RESET:bit1;
  RESOURCE25_RESET:bit1;
  RESOURCE26_RESET:bit1;
  RESOURCE27_RESET:bit1;
  RESOURCE28_RESET:bit1;
  RESOURCE29_RESET:bit1;
  RESOURCE30_RESET:bit1;
  RESOURCE31_RESET:bit1;
 end;

 TGDS_GWS_RESET1=bitpacked record
  RESOURCE32_RESET:bit1;
  RESOURCE33_RESET:bit1;
  RESOURCE34_RESET:bit1;
  RESOURCE35_RESET:bit1;
  RESOURCE36_RESET:bit1;
  RESOURCE37_RESET:bit1;
  RESOURCE38_RESET:bit1;
  RESOURCE39_RESET:bit1;
  RESOURCE40_RESET:bit1;
  RESOURCE41_RESET:bit1;
  RESOURCE42_RESET:bit1;
  RESOURCE43_RESET:bit1;
  RESOURCE44_RESET:bit1;
  RESOURCE45_RESET:bit1;
  RESOURCE46_RESET:bit1;
  RESOURCE47_RESET:bit1;
  RESOURCE48_RESET:bit1;
  RESOURCE49_RESET:bit1;
  RESOURCE50_RESET:bit1;
  RESOURCE51_RESET:bit1;
  RESOURCE52_RESET:bit1;
  RESOURCE53_RESET:bit1;
  RESOURCE54_RESET:bit1;
  RESOURCE55_RESET:bit1;
  RESOURCE56_RESET:bit1;
  RESOURCE57_RESET:bit1;
  RESOURCE58_RESET:bit1;
  RESOURCE59_RESET:bit1;
  RESOURCE60_RESET:bit1;
  RESOURCE61_RESET:bit1;
  RESOURCE62_RESET:bit1;
  RESOURCE63_RESET:bit1;
 end;

 TGDS_GWS_VMID10=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID11=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID12=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID13=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID14=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_GWS_VMID15=bitpacked record
  BASE     :bit6;
  RESERVED0:bit10;
  SIZE     :bit7;
  RESERVED1:bit9;
 end;

 TGDS_OA_ADDRESS=bitpacked record
  DS_ADDRESS  :bit16;
  CRAWLER     :bit4;
  CRAWLER_TYPE:bit2;
  UNUSED      :bit8;
  NO_ALLOC    :bit1;
  ENABLE      :bit1;
 end;

 TGDS_OA_COUNTER=bit32;

 TGDS_SECDED_CNT=bitpacked record
  SEC:bit16;
  DED:bit16;
 end;

 TGDS_VMID0_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID0_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID1_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID1_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID2_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID2_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID3_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID3_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID4_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID4_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID5_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID5_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID6_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID6_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID7_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID7_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID8_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID8_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID9_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID9_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGENERAL_PWRMGT=bitpacked record
  GLOBAL_PWRMGT_EN       :bit1;
  STATIC_PM_EN           :bit1;
  THERMAL_PROTECTION_DIS :bit1;
  THERMAL_PROTECTION_TYPE:bit1;
  RESERVED0              :bit2;
  SW_SMIO_INDEX          :bit1;
  RESERVED1              :bit1;
  LOW_VOLT_D2_ACPI       :bit1;
  LOW_VOLT_D3_ACPI       :bit1;
  VOLT_PWRMGT_EN         :bit1;
  SPARE11                :bit1;
  RESERVED2              :bit2;
  GPU_COUNTER_ACPI       :bit1;
  GPU_COUNTER_CLK        :bit1;
  GPU_COUNTER_OFF        :bit1;
  GPU_COUNTER_INTF_OFF   :bit1;
  SPARE18                :bit1;
  ACPI_D3_VID            :bit2;
  RESERVED3              :bit2;
  DYN_SPREAD_SPECTRUM_EN :bit1;
  RESERVED4              :bit3;
  SPARE27                :bit1;
  SPARE                  :bit4;
 end;

 TGFX_COPY_STATE=bitpacked record
  SRC_STATE_ID:bit3;
  RESERVED0   :bit29;
 end;

 TGLOBAL_CONTROL=bitpacked record
  CONTROLLER_RESET                  :bit1;
  FLUSH_CONTROL                     :bit1;
  RESERVED0                         :bit6;
  ACCEPT_UNSOLICITED_RESPONSE_ENABLE:bit1;
  RESERVED1                         :bit23;
 end;

 TGPIOPAD_INT_EN=bitpacked record
  GPIO_INT_EN        :bit29;
  RESERVED0          :bit2;
  SW_INITIATED_INT_EN:bit1;
 end;

 TGRBM_CAM_INDEX=bitpacked record
  CAM_INDEX:bit3;
  RESERVED0:bit29;
 end;

 TGRBM_GFX_INDEX=bitpacked record
  INSTANCE_INDEX           :bit8;
  SH_INDEX                 :bit8;
  SE_INDEX                 :bit8;
  RESERVED0                :bit5;
  SH_BROADCAST_WRITES      :bit1;
  INSTANCE_BROADCAST_WRITES:bit1;
  SE_BROADCAST_WRITES      :bit1;
 end;

 TGRBM_SKEW_CNTL=bitpacked record
  SKEW_TOP_THRESHOLD:bit6;
  SKEW_COUNT        :bit6;
  RESERVED0         :bit20;
 end;

 TGRBM_TRAP_ADDR=bitpacked record
  DATA     :bit16;
  RESERVED0:bit16;
 end;

 TGRPH_SWAP_CNTL=bitpacked record
  GRPH_ENDIAN_SWAP   :bit2;
  RESERVED0          :bit2;
  GRPH_RED_CROSSBAR  :bit2;
  GRPH_GREEN_CROSSBAR:bit2;
  GRPH_BLUE_CROSSBAR :bit2;
  GRPH_ALPHA_CROSSBAR:bit2;
  RESERVED1          :bit20;
 end;

 THDP_MEMIO_ADDR=bit32;

 THDP_MEMIO_CNTL=bitpacked record
  MEMIO_SEND        :bit1;
  MEMIO_OP          :bit1;
  MEMIO_BE          :bit4;
  MEMIO_WR_STROBE   :bit1;
  MEMIO_RD_STROBE   :bit1;
  MEMIO_ADDR_UPPER  :bit6;
  MEMIO_CLR_WR_ERROR:bit1;
  MEMIO_CLR_RD_ERROR:bit1;
  MEMIO_VF          :bit1;
  MEMIO_VFID        :bit4;
  RESERVED0         :bit11;
 end;

 THDP_XDP_STICKY=bitpacked record
  STICKY_STS:bit16;
  STICKY_W1C:bit16;
 end;

 TIA_CNTL_STATUS=bitpacked record
  IA_BUSY        :bit1;
  IA_DMA_BUSY    :bit1;
  IA_DMA_REQ_BUSY:bit1;
  IA_GRP_BUSY    :bit1;
  IA_ADC_BUSY    :bit1;
  RESERVED0      :bit27;
 end;

 TIH_VMID_10_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_11_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_12_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_13_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_14_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TIH_VMID_15_LUT=bitpacked record
  PASID    :bit16;
  RESERVED0:bit16;
 end;

 TINTERRUPT_CNTL=bitpacked record
  IH_DUMMY_RD_OVERRIDE  :bit1;
  IH_DUMMY_RD_EN        :bit1;
  RESERVED0             :bit1;
  IH_REQ_NONSNOOP_EN    :bit1;
  IH_INTR_DLY_CNTR      :bit4;
  GEN_IH_INT_EN         :bit1;
  GEN_GPIO_INT_EN       :bit4;
  SELECT_INT_GPIO_OUTPUT:bit2;
  BIF_RB_REQ_NONSNOOP_EN:bit1;
  RESERVED1             :bit16;
 end;

 TINTERRUPT_LINE=bitpacked record
  INTERRUPT_LINE:bit8;
  RESERVED0     :bit24;
 end;

 TKEY_RANGE_BLUE=bitpacked record
  KEY_BLUE_LOW :bit16;
  KEY_BLUE_HIGH:bit16;
 end;

 TLB_DATA_FORMAT=bitpacked record
  PIXEL_DEPTH        :bit2;
  PIXEL_EXPAN_MODE   :bit1;
  INTERLEAVE_EN      :bit1;
  PIXEL_REDUCE_MODE  :bit1;
  DYNAMIC_PIXEL_DEPTH:bit1;
  RESERVED0          :bit6;
  PREFETCH           :bit1;
  RESERVED1          :bit11;
  REQUEST_MODE       :bit1;
  RESERVED2          :bit6;
  ALPHA_EN           :bit1;
 end;

 TLB_MEMORY_CTRL=bitpacked record
  LB_MEMORY_SIZE   :bit12;
  RESERVED0        :bit4;
  LB_NUM_PARTITIONS:bit4;
  LB_MEMORY_CONFIG :bit2;
  RESERVED1        :bit10;
 end;

 TLM_PRBSCONTROL=bitpacked record
  PRBSPCIeSelect:bit16;
  RESERVED0     :bit12;
  LMLaneDegrade0:bit1;
  LMLaneDegrade1:bit1;
  LMLaneDegrade2:bit1;
  LMLaneDegrade3:bit1;
 end;

 TLNC_TOTAL_WACC=bit32;

 TLVDS_DATA_CNTL=bitpacked record
  LVDS_24BIT_ENABLE      :bit1;
  RESERVED0              :bit3;
  LVDS_24BIT_FORMAT      :bit1;
  RESERVED1              :bit3;
  LVDS_2ND_CHAN_DE       :bit1;
  LVDS_2ND_CHAN_VS       :bit1;
  LVDS_2ND_CHAN_HS       :bit1;
  RESERVED2              :bit1;
  LVDS_2ND_LINK_CNTL_BITS:bit3;
  RESERVED3              :bit1;
  LVDS_FP_POL            :bit1;
  LVDS_LP_POL            :bit1;
  LVDS_DTMG_POL          :bit1;
  RESERVED4              :bit13;
 end;

 TMC_ARB_BANKMAP=bitpacked record
  BANK0    :bit4;
  BANK1    :bit4;
  BANK2    :bit4;
  BANK3    :bit4;
  RANK     :bit4;
  RESERVED0:bit12;
 end;

 TMC_ARB_MINCLKS=bitpacked record
  READ_CLKS      :bit8;
  WRITE_CLKS     :bit8;
  ARB_RW_SWITCH  :bit1;
  RW_SWITCH_HARSH:bit2;
  RESERVED0      :bit13;
 end;

 TMC_ARB_PM_CNTL=bitpacked record
  OVERRIDE_CGSTATE:bit2;
  OVRR_CGRFSH     :bit1;
  OVRR_CGSQM      :bit1;
  SRFSH_ON_D1     :bit1;
  BLKOUT_ON_D1    :bit1;
  IDLE_ON_D1      :bit1;
  OVRR_PM         :bit1;
  OVRR_PM_STATE   :bit2;
  OVRR_RD         :bit1;
  OVRR_RD_STATE   :bit1;
  OVRR_WR         :bit1;
  OVRR_WR_STATE   :bit1;
  OVRR_RFSH       :bit1;
  OVRR_RFSH_STATE :bit1;
  OVRR_RD0_BUSY   :bit1;
  OVRR_RD1_BUSY   :bit1;
  IDLE_ON_D2      :bit1;
  IDLE_ON_D3      :bit1;
  IDLE_CNT        :bit4;
  OVRR_WR0_BUSY   :bit1;
  OVRR_WR1_BUSY   :bit1;
  RESERVED0       :bit6;
 end;

 TMC_CG_DATAPORT=bit32;

 TMC_CITF_REMREQ=bitpacked record
  READ_CREDITS  :bit7;
  WRITE_CREDITS :bit7;
  CREDITS_ENABLE:bit1;
  RESERVED0     :bit17;
 end;

 TMC_HUB_WDP_BP2=bitpacked record
  RDRET    :bit16;
  RESERVED0:bit16;
 end;

 TMC_HUB_WDP_ERR=bitpacked record
  MGPU1_TARG_SYS:bit1;
  MGPU2_TARG_SYS:bit1;
  RESERVED0     :bit30;
 end;

 TMC_HUB_WDP_HDP=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_RLC=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_SEM=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_SH0=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_SH1=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_SH2=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_SH3=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_SIP=bitpacked record
  STALL_MODE :bit2;
  ASK_CREDITS:bit7;
  RESERVED0  :bit23;
 end;

 TMC_HUB_WDP_SMU=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_UMC=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_UVD=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  VM_BYPASS                :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit13;
 end;

 TMC_HUB_WDP_VP8=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_XDP=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_PMG_CMD_MRS=bitpacked record
  ADR      :bit16;
  RESERVED0:bit4;
  MOP      :bit4;
  _END     :bit1;
  RESERVED1:bit7;
 end;

 TMC_RPB_IF_CONF=bitpacked record
  RPB_BIF_CREDITS      :bit8;
  OUTSTANDING_WRRET_ASK:bit8;
  RESERVED0            :bit16;
 end;

 TMC_SEQ_SUP_PGM=bit32;

 TMC_VM_AGP_BASE=bitpacked record
  AGP_BASE :bit18;
  RESERVED0:bit14;
 end;

 TMC_VM_STEERING=bitpacked record
  DEFAULT_STEERING:bit2;
  RESERVED0       :bit30;
 end;

 TMC_XBAR_REMOTE=bitpacked record
  WRREQ_EN_GOQ:bit1;
  RDREQ_EN_GOQ:bit1;
  RESERVED0   :bit30;
 end;

 TMC_XBAR_SPARE0=bit32;

 TMC_XBAR_SPARE1=bit32;

 TMC_XPB_CLK_GAT=bitpacked record
  ONDLY        :bit6;
  OFFDLY       :bit6;
  RDYDLY       :bit6;
  ENABLE       :bit1;
  MEM_LS_ENABLE:bit1;
  RESERVED0    :bit12;
 end;

 TMC_XPB_LB_ADDR=bitpacked record
  CMP0 :bit10;
  MASK0:bit10;
  CMP1 :bit6;
  MASK1:bit6;
 end;

 TMC_XPB_WCB_CFG=bitpacked record
  TIMEOUT  :bit16;
  HST_MAX  :bit2;
  SID_MAX  :bit2;
  RESERVED0:bit12;
 end;

 TMC_XPB_WCB_STS=bitpacked record
  PBUF_VLD            :bit16;
  WCB_HST_DATA_BUF_CNT:bit7;
  WCB_SID_DATA_BUF_CNT:bit7;
  RESERVED0           :bit2;
 end;

 TMSI_PENDING_64=bit32;

 TOVL_DFQ_STATUS=bitpacked record
  OVL_DFQ_NUM_ENTRIES          :bit4;
  OVL_SECONDARY_DFQ_NUM_ENTRIES:bit4;
  OVL_DFQ_RESET_FLAG           :bit1;
  OVL_DFQ_RESET_ACK            :bit1;
  RESERVED0                    :bit22;
 end;

 TPA_CL_VTE_CNTL=bitpacked record
  VPORT_X_SCALE_ENA :bit1;
  VPORT_X_OFFSET_ENA:bit1;
  VPORT_Y_SCALE_ENA :bit1;
  VPORT_Y_OFFSET_ENA:bit1;
  VPORT_Z_SCALE_ENA :bit1;
  VPORT_Z_OFFSET_ENA:bit1;
  RESERVED0         :bit2;
  VTX_XY_FMT        :bit1;
  VTX_Z_FMT         :bit1;
  VTX_W0_FMT        :bit1;
  PERFCOUNTER_REF   :bit1;
  RESERVED1         :bit20;
 end;

 TPA_SC_EDGERULE=bitpacked record
  ER_TRI    :bit4;
  ER_POINT  :bit4;
  ER_RECT   :bit4;
  ER_LINE_LR:bit6;
  ER_LINE_RL:bit6;
  ER_LINE_TB:bit4;
  ER_LINE_BT:bit4;
 end;

 TPA_SU_VTX_CNTL=bitpacked record
  PIX_CENTER:bit1;
  ROUND_MODE:bit2;
  QUANT_MODE:bit3;
  RESERVED0 :bit26;
 end;

 TPCIEP_HW_DEBUG=bitpacked record
  HW_00_DEBUG:bit1;
  HW_01_DEBUG:bit1;
  HW_02_DEBUG:bit1;
  HW_03_DEBUG:bit1;
  HW_04_DEBUG:bit1;
  HW_05_DEBUG:bit1;
  HW_06_DEBUG:bit1;
  HW_07_DEBUG:bit1;
  HW_08_DEBUG:bit1;
  HW_09_DEBUG:bit1;
  HW_10_DEBUG:bit1;
  HW_11_DEBUG:bit1;
  HW_12_DEBUG:bit1;
  HW_13_DEBUG:bit1;
  HW_14_DEBUG:bit1;
  HW_15_DEBUG:bit1;
  RESERVED0  :bit16;
 end;

 TPCIEP_RESERVED=bit32;

 TPCIEP_STRAP_LC=bitpacked record
  STRAP_FTS_yTSx_COUNT               :bit2;
  STRAP_LONG_yTSx_COUNT              :bit2;
  STRAP_MED_yTSx_COUNT               :bit2;
  STRAP_SHORT_yTSx_COUNT             :bit2;
  STRAP_SKIP_INTERVAL                :bit3;
  STRAP_BYPASS_RCVR_DET              :bit1;
  STRAP_COMPLIANCE_DIS               :bit1;
  STRAP_FORCE_COMPLIANCE             :bit1;
  STRAP_REVERSE_LC_LANES             :bit1;
  STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS:bit1;
  STRAP_LANE_NEGOTIATION             :bit3;
  RESERVED0                          :bit13;
 end;

 TPCIE_BAR1_CNTL=bitpacked record
  BAR_INDEX    :bit3;
  RESERVED0    :bit2;
  BAR_TOTAL_NUM:bit3;
  BAR_SIZE     :bit5;
  RESERVED1    :bit19;
 end;

 TPCIE_BAR2_CNTL=bitpacked record
  BAR_INDEX    :bit3;
  RESERVED0    :bit2;
  BAR_TOTAL_NUM:bit3;
  BAR_SIZE     :bit5;
  RESERVED1    :bit19;
 end;

 TPCIE_BAR3_CNTL=bitpacked record
  BAR_INDEX    :bit3;
  RESERVED0    :bit2;
  BAR_TOTAL_NUM:bit3;
  BAR_SIZE     :bit5;
  RESERVED1    :bit19;
 end;

 TPCIE_BAR4_CNTL=bitpacked record
  BAR_INDEX    :bit3;
  RESERVED0    :bit2;
  BAR_TOTAL_NUM:bit3;
  BAR_SIZE     :bit5;
  RESERVED1    :bit19;
 end;

 TPCIE_BAR5_CNTL=bitpacked record
  BAR_INDEX    :bit3;
  RESERVED0    :bit2;
  BAR_TOTAL_NUM:bit3;
  BAR_SIZE     :bit5;
  RESERVED1    :bit19;
 end;

 TPCIE_BAR6_CNTL=bitpacked record
  BAR_INDEX    :bit3;
  RESERVED0    :bit2;
  BAR_TOTAL_NUM:bit3;
  BAR_SIZE     :bit5;
  RESERVED1    :bit19;
 end;

 TPCIE_LC_STATE0=bitpacked record
  LC_CURRENT_STATE:bit6;
  RESERVED0       :bit2;
  LC_PREV_STATE1  :bit6;
  RESERVED1       :bit2;
  LC_PREV_STATE2  :bit6;
  RESERVED2       :bit2;
  LC_PREV_STATE3  :bit6;
  RESERVED3       :bit2;
 end;

 TPCIE_LC_STATE1=bitpacked record
  LC_PREV_STATE4:bit6;
  RESERVED0     :bit2;
  LC_PREV_STATE5:bit6;
  RESERVED1     :bit2;
  LC_PREV_STATE6:bit6;
  RESERVED2     :bit2;
  LC_PREV_STATE7:bit6;
  RESERVED3     :bit2;
 end;

 TPCIE_LC_STATE2=bitpacked record
  LC_PREV_STATE8 :bit6;
  RESERVED0      :bit2;
  LC_PREV_STATE9 :bit6;
  RESERVED1      :bit2;
  LC_PREV_STATE10:bit6;
  RESERVED2      :bit2;
  LC_PREV_STATE11:bit6;
  RESERVED3      :bit2;
 end;

 TPCIE_LC_STATE3=bitpacked record
  LC_PREV_STATE12:bit6;
  RESERVED0      :bit2;
  LC_PREV_STATE13:bit6;
  RESERVED1      :bit2;
  LC_PREV_STATE14:bit6;
  RESERVED2      :bit2;
  LC_PREV_STATE15:bit6;
  RESERVED3      :bit2;
 end;

 TPCIE_LC_STATE4=bitpacked record
  LC_PREV_STATE16:bit6;
  RESERVED0      :bit2;
  LC_PREV_STATE17:bit6;
  RESERVED1      :bit2;
  LC_PREV_STATE18:bit6;
  RESERVED2      :bit2;
  LC_PREV_STATE19:bit6;
  RESERVED3      :bit2;
 end;

 TPCIE_LC_STATE5=bitpacked record
  LC_PREV_STATE20:bit6;
  RESERVED0      :bit2;
  LC_PREV_STATE21:bit6;
  RESERVED1      :bit2;
  LC_PREV_STATE22:bit6;
  RESERVED2      :bit2;
  LC_PREV_STATE23:bit6;
  RESERVED3      :bit2;
 end;

 TPCIE_LC_STATE6=bitpacked record
  LC_PREV_STATE24:bit6;
  RESERVED0      :bit2;
  LC_PREV_STATE25:bit6;
  RESERVED1      :bit2;
  LC_PREV_STATE26:bit6;
  RESERVED2      :bit2;
  LC_PREV_STATE27:bit6;
  RESERVED3      :bit2;
 end;

 TPCIE_LC_STATE7=bitpacked record
  LC_PREV_STATE28:bit6;
  RESERVED0      :bit2;
  LC_PREV_STATE29:bit6;
  RESERVED1      :bit2;
  LC_PREV_STATE30:bit6;
  RESERVED2      :bit2;
  LC_PREV_STATE31:bit6;
  RESERVED3      :bit2;
 end;

 TPCIE_LC_STATE8=bitpacked record
  LC_PREV_STATE32:bit6;
  RESERVED0      :bit2;
  LC_PREV_STATE33:bit6;
  RESERVED1      :bit2;
  LC_PREV_STATE34:bit6;
  RESERVED2      :bit2;
  LC_PREV_STATE35:bit6;
  RESERVED3      :bit2;
 end;

 TPCIE_LC_STATE9=bitpacked record
  LC_PREV_STATE36:bit6;
  RESERVED0      :bit2;
  LC_PREV_STATE37:bit6;
  RESERVED1      :bit2;
  LC_PREV_STATE38:bit6;
  RESERVED2      :bit2;
  LC_PREV_STATE39:bit6;
  RESERVED3      :bit2;
 end;

 TPCIE_OBFF_CNTL=bitpacked record
  TX_OBFF_PRIV_DISABLE              :bit1;
  TX_OBFF_WAKE_SIMPLE_MODE_EN       :bit1;
  TX_OBFF_HOSTMEM_TO_ACTIVE         :bit1;
  TX_OBFF_SLVCPL_TO_ACTIVE          :bit1;
  TX_OBFF_WAKE_MAX_PULSE_WIDTH      :bit4;
  TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH:bit4;
  TX_OBFF_WAKE_SAMPLING_PERIOD      :bit4;
  TX_OBFF_INTR_TO_ACTIVE            :bit1;
  TX_OBFF_ERR_TO_ACTIVE             :bit1;
  TX_OBFF_ANY_MSG_TO_ACTIVE         :bit1;
  TX_OBFF_ACCEPT_IN_NOND0           :bit1;
  TX_OBFF_PENDING_REQ_TO_ACTIVE     :bit4;
  RESERVED0                         :bit8;
 end;

 TPCIE_PASID_CAP=bitpacked record
  RESERVED0                     :bit1;
  PASID_EXE_PERMISSION_SUPPORTED:bit1;
  PASID_PRIV_MODE_SUPPORTED     :bit1;
  RESERVED1                     :bit1;
  RESERVED2                     :bit4;
  MAX_PASID_WIDTH               :bit5;
  RESERVED3                     :bit19;
 end;

 TPCIE_PORT_DATA=bit32;

 TPCIE_PRBS_MISC=bitpacked record
  PRBS_EN                 :bit1;
  PRBS_TEST_MODE          :bit3;
  PRBS_USER_PATTERN_TOGGLE:bit1;
  PRBS_8BIT_SEL           :bit1;
  PRBS_COMMA_NUM          :bit2;
  PRBS_LOCK_CNT           :bit5;
  RESERVED0               :bit1;
  PRBS_DATA_RATE          :bit2;
  PRBS_CHK_ERR_MASK       :bit16;
 end;

 TPCIE_SRIOV_CAP=bitpacked record
  SRIOV_VF_MIGRATION_CAP           :bit1;
  SRIOV_ARI_CAP_HIERARCHY_PRESERVED:bit1;
  RESERVED0                        :bit19;
  SRIOV_VF_MIGRATION_INTR_MSG_NUM  :bit11;
 end;

 TPCIE_TX_REPLAY=bitpacked record
  TX_REPLAY_NUM            :bit10;
  RESERVED0                :bit5;
  TX_REPLAY_TIMER_OVERWRITE:bit1;
  TX_REPLAY_TIMER          :bit16;
 end;

 TPCIE_WRAP_MISC=bitpacked record
  RESERVED0                     :bit1;
  STRAP_BIF_HOLD_TRAINING_STICKY:bit1;
  STRAP_BIF_QUICKSIM_START      :bit1;
  RESERVED1                     :bit29;
 end;

 TPLL_DEBUG_CNTL=bitpacked record
  PLL_DEBUG_SIGNALS_ENABLE:bit1;
  RESERVED0               :bit3;
  PLL_DEBUG_MUXOUT_SEL    :bit4;
  PLL_DEBUG_CLK_SEL       :bit5;
  RESERVED1               :bit3;
  PLL_DEBUG_ADC_CNTL      :bit8;
  PLL_DEBUG_ADC_READBACK  :bit3;
  PLL_DEBUG_ADC_EN        :bit1;
  RESERVED2               :bit4;
 end;

 TPLL_IDCLK_CNTL=bitpacked record
  PLL_LTDP_IDCLK_EN       :bit1;
  PLL_LTDP_IDCLK_DIFF_EN  :bit1;
  PLL_TMDP_IDCLK_EN       :bit1;
  PLL_TMDP_IDCLK_DIFF_EN  :bit1;
  PLL_IDCLK_EN            :bit1;
  RESERVED0               :bit3;
  PLL_DIFF_POST_DIV_RESET :bit1;
  RESERVED1               :bit3;
  PLL_DIFF_POST_DIV_SELECT:bit1;
  RESERVED2               :bit3;
  PLL_DIFF_POST_DIV       :bit4;
  PLL_CUR_LTDP            :bit2;
  PLL_CUR_PREDRV          :bit2;
  PLL_CUR_TMDP            :bit2;
  PLL_CML_A_DRVSTR        :bit2;
  PLL_CML_B_DRVSTR        :bit2;
  RESERVED3               :bit2;
 end;

 TPROG_INTERFACE=bitpacked record
  PROG_INTERFACE:bit8;
  RESERVED0     :bit24;
 end;

 TPWR_CKS_ENABLE=bitpacked record
  STRETCH_ENABLE     :bit1;
  masterReset        :bit1;
  staticEnable       :bit1;
  IGNORE_DROOP_DETECT:bit1;
  PCC_HAND_SHAKE_EN  :bit1;
  MET_CTRL_SEL       :bit2;
  DS_HAND_SHAKE_EN   :bit1;
  RESERVED0          :bit24;
 end;

 TRBBMIF_TIMEOUT=bitpacked record
  RBBMIF_TIMEOUT_DELAY:bit20;
  RBBMIF_ACK_HOLD     :bit12;
 end;

 TRLC_PG_DELAY_2=bitpacked record
  SERDES_TIMEOUT_VALUE:bit8;
  SERDES_CMD_DELAY    :bit8;
  PERCU_TIMEOUT_VALUE :bit16;
 end;

 TRLC_PG_DELAY_3=bitpacked record
  CGCG_ACTIVE_BEFORE_CGPG:bit8;
  RESERVED               :bit24;
 end;

 TRLC_UCODE_CNTL=bit32;

 TROM_SW_COMMAND=bitpacked record
  ROM_SW_INSTRUCTION:bit8;
  ROM_SW_ADDRESS    :bit24;
 end;

 TROM_SW_DATA_10=bit32;

 TROM_SW_DATA_11=bit32;

 TROM_SW_DATA_12=bit32;

 TROM_SW_DATA_13=bit32;

 TROM_SW_DATA_14=bit32;

 TROM_SW_DATA_15=bit32;

 TROM_SW_DATA_16=bit32;

 TROM_SW_DATA_17=bit32;

 TROM_SW_DATA_18=bit32;

 TROM_SW_DATA_19=bit32;

 TROM_SW_DATA_20=bit32;

 TROM_SW_DATA_21=bit32;

 TROM_SW_DATA_22=bit32;

 TROM_SW_DATA_23=bit32;

 TROM_SW_DATA_24=bit32;

 TROM_SW_DATA_25=bit32;

 TROM_SW_DATA_26=bit32;

 TROM_SW_DATA_27=bit32;

 TROM_SW_DATA_28=bit32;

 TROM_SW_DATA_29=bit32;

 TROM_SW_DATA_30=bit32;

 TROM_SW_DATA_31=bit32;

 TROM_SW_DATA_32=bit32;

 TROM_SW_DATA_33=bit32;

 TROM_SW_DATA_34=bit32;

 TROM_SW_DATA_35=bit32;

 TROM_SW_DATA_36=bit32;

 TROM_SW_DATA_37=bit32;

 TROM_SW_DATA_38=bit32;

 TROM_SW_DATA_39=bit32;

 TROM_SW_DATA_40=bit32;

 TROM_SW_DATA_41=bit32;

 TROM_SW_DATA_42=bit32;

 TROM_SW_DATA_43=bit32;

 TROM_SW_DATA_44=bit32;

 TROM_SW_DATA_45=bit32;

 TROM_SW_DATA_46=bit32;

 TROM_SW_DATA_47=bit32;

 TROM_SW_DATA_48=bit32;

 TROM_SW_DATA_49=bit32;

 TROM_SW_DATA_50=bit32;

 TROM_SW_DATA_51=bit32;

 TROM_SW_DATA_52=bit32;

 TROM_SW_DATA_53=bit32;

 TROM_SW_DATA_54=bit32;

 TROM_SW_DATA_55=bit32;

 TROM_SW_DATA_56=bit32;

 TROM_SW_DATA_57=bit32;

 TROM_SW_DATA_58=bit32;

 TROM_SW_DATA_59=bit32;

 TROM_SW_DATA_60=bit32;

 TROM_SW_DATA_61=bit32;

 TROM_SW_DATA_62=bit32;

 TROM_SW_DATA_63=bit32;

 TROM_SW_DATA_64=bit32;

 TSDMA0_CLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TSDMA0_F32_CNTL=bitpacked record
  HALT           :bit1;
  STEP           :bit1;
  DBG_SELECT_BITS:bit6;
  RESERVED0      :bit24;
 end;

 TSDMA1_CLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TSDMA1_F32_CNTL=bitpacked record
  HALT           :bit1;
  STEP           :bit1;
  DBG_SELECT_BITS:bit6;
  RESERVED0      :bit24;
 end;

 TSEM_EDC_CONFIG=bitpacked record
  RESERVED0:bit1;
  DIS_EDC  :bit1;
  RESERVED1:bit30;
 end;

 TSMC_IND_DATA_0=bit32;

 TSMC_IND_DATA_1=bit32;

 TSMC_IND_DATA_2=bit32;

 TSMC_IND_DATA_3=bit32;

 TSMC_IND_DATA_4=bit32;

 TSMC_IND_DATA_5=bit32;

 TSMC_IND_DATA_6=bit32;

 TSMC_IND_DATA_7=bit32;

 TSMC_MESSAGE_10=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MESSAGE_11=bitpacked record
  SMC_MSG  :bit16;
  RESERVED0:bit16;
 end;

 TSMC_MSG_ARG_10=bit32;

 TSMC_MSG_ARG_11=bit32;

 TSMU_IND_DATA_0=bit32;

 TSMU_IND_DATA_1=bit32;

 TSMU_IND_DATA_2=bit32;

 TSMU_IND_DATA_3=bit32;

 TSMU_IND_DATA_4=bit32;

 TSMU_IND_DATA_5=bit32;

 TSMU_IND_DATA_6=bit32;

 TSMU_IND_DATA_7=bit32;

 TSPI_BARYC_CNTL=bitpacked record
  PERSP_CENTER_CNTL   :bit1;
  RESERVED0           :bit3;
  PERSP_CENTROID_CNTL :bit1;
  RESERVED1           :bit3;
  LINEAR_CENTER_CNTL  :bit1;
  RESERVED2           :bit3;
  LINEAR_CENTROID_CNTL:bit1;
  RESERVED3           :bit3;
  POS_FLOAT_LOCATION  :bit2;
  RESERVED4           :bit2;
  POS_FLOAT_ULC       :bit1;
  RESERVED5           :bit3;
  FRONT_FACE_ALL_BITS :bit1;
  RESERVED6           :bit7;
 end;

 TSPI_DEBUG_BUSY=bitpacked record
  LS_BUSY         :bit1;
  HS_BUSY         :bit1;
  ES_BUSY         :bit1;
  GS_BUSY         :bit1;
  VS_BUSY         :bit1;
  PS0_BUSY        :bit1;
  PS1_BUSY        :bit1;
  CSG_BUSY        :bit1;
  CS0_BUSY        :bit1;
  CS1_BUSY        :bit1;
  CS2_BUSY        :bit1;
  CS3_BUSY        :bit1;
  CS4_BUSY        :bit1;
  CS5_BUSY        :bit1;
  CS6_BUSY        :bit1;
  CS7_BUSY        :bit1;
  LDS_WR_CTL0_BUSY:bit1;
  LDS_WR_CTL1_BUSY:bit1;
  RSRC_ALLOC0_BUSY:bit1;
  RSRC_ALLOC1_BUSY:bit1;
  PC_DEALLOC_BUSY :bit1;
  EVENT_CLCTR_BUSY:bit1;
  GRBM_BUSY       :bit1;
  SPIS_BUSY       :bit1;
  RESERVED0       :bit8;
 end;

 TSPI_DEBUG_CNTL=bitpacked record
  DEBUG_GRBM_OVERRIDE  :bit1;
  DEBUG_THREAD_TYPE_SEL:bit3;
  DEBUG_GROUP_SEL      :bit6;
  DEBUG_SIMD_SEL       :bit6;
  DEBUG_SH_SEL         :bit1;
  SPI_ECO_SPARE_0      :bit1;
  SPI_ECO_SPARE_1      :bit1;
  SPI_ECO_SPARE_2      :bit1;
  SPI_ECO_SPARE_3      :bit1;
  SPI_ECO_SPARE_4      :bit1;
  SPI_ECO_SPARE_5      :bit1;
  SPI_ECO_SPARE_6      :bit1;
  SPI_ECO_SPARE_7      :bit1;
  DEBUG_PIPE_SEL       :bit3;
  RESERVED0            :bit3;
  DEBUG_REG_EN         :bit1;
 end;

 TSPI_DEBUG_READ=bitpacked record
  DATA     :bit24;
  RESERVED0:bit8;
 end;

 TSPI_LB_CU_MASK=bitpacked record
  CU_MASK  :bit16;
  RESERVED0:bit16;
 end;

 TSPLL_CNTL_MODE=bitpacked record
  SPLL_SW_DIR_CONTROL  :bit1;
  SPLL_LEGACY_PDIV     :bit1;
  SPLL_TEST            :bit1;
  SPLL_FASTEN          :bit1;
  SPLL_ENSAT           :bit1;
  RESERVED0            :bit5;
  SPLL_TEST_CLK_EXT_DIV:bit2;
  SPLL_CTLREQ_DLY_CNT  :bit8;
  RESERVED1            :bit8;
  SPLL_RESET_EN        :bit1;
  SPLL_VCO_MODE        :bit2;
  RESERVED2            :bit1;
 end;

 TSPMI_CONFIG0_0=bitpacked record
  SPMI_ENABLE                   :bit1;
  RESERVED0                     :bit1;
  SPMI_PATH_NUM_TIMING_FLOPS    :bit5;
  SPMI_SIGNALING_DELAY_CYCLES   :bit5;
  SPMI_SIGNALING_HOLD_CYCLES    :bit5;
  SPMI_PATH_ENABLE_DELAY_CYCLES :bit5;
  SPMI_PATH_DISABLE_DELAY_CYCLES:bit5;
  RESERVED1                     :bit5;
 end;

 TSPMI_CONFIG1_0=bitpacked record
  SPMI_SIGNALING_RESET_HOLD_CYCLES:bit5;
  SPMI_CHAIN_SIZE                 :bit11;
  RESERVED0                       :bit16;
 end;

 TSPMI_SRAM_DATA=bit32;

 TSQ_EDC_DED_CNT=bitpacked record
  LDS_DED  :bit8;
  SGPR_DED :bit8;
  VGPR_DED :bit8;
  RESERVED0:bit8;
 end;

 TSQ_EDC_SEC_CNT=bitpacked record
  LDS_SEC  :bit8;
  SGPR_SEC :bit8;
  VGPR_SEC :bit8;
  RESERVED0:bit8;
 end;

 TSQ_LB_CTR_CTRL=bitpacked record
  START    :bit1;
  LOAD     :bit1;
  CLEAR    :bit1;
  RESERVED0:bit29;
 end;

 TSQ_REG_CREDITS=bitpacked record
  SRBM_CREDITS  :bit6;
  RESERVED0     :bit2;
  CMD_CREDITS   :bit4;
  RESERVED1     :bit16;
  REG_BUSY      :bit1;
  SRBM_OVERFLOW :bit1;
  IMMED_OVERFLOW:bit1;
  CMD_OVERFLOW  :bit1;
 end;

 TSQ_WAVE_IB_STS=bitpacked record
  VM_CNT      :bit4;
  EXP_CNT     :bit3;
  RESERVED0   :bit1;
  LGKM_CNT    :bit4;
  VALU_CNT    :bit3;
  FIRST_REPLAY:bit1;
  RCNT        :bit4;
  RESERVED1   :bit12;
 end;

 TSQ_WAVE_STATUS=bitpacked record
  SCC          :bit1;
  SPI_PRIO     :bit2;
  USER_PRIO    :bit2;
  PRIV         :bit1;
  TRAP_EN      :bit1;
  TTRACE_EN    :bit1;
  EXPORT_RDY   :bit1;
  EXECZ        :bit1;
  VCCZ         :bit1;
  IN_TG        :bit1;
  IN_BARRIER   :bit1;
  HALT         :bit1;
  TRAP         :bit1;
  TTRACE_CU_EN :bit1;
  VALID        :bit1;
  ECC_ERR      :bit1;
  SKIP_EXPORT  :bit1;
  PERF_EN      :bit1;
  COND_DBG_USER:bit1;
  COND_DBG_SYS :bit1;
  ALLOW_REPLAY :bit1;
  INST_ATC     :bit1;
  RESERVED0    :bit3;
  MUST_EXPORT  :bit1;
  RESERVED1    :bit4;
 end;

 TSQ_WAVE_TBA_HI=bitpacked record
  ADDR_HI  :bit8;
  RESERVED0:bit24;
 end;

 TSQ_WAVE_TBA_LO=bit32;

 TSQ_WAVE_TMA_HI=bitpacked record
  ADDR_HI  :bit8;
  RESERVED0:bit24;
 end;

 TSQ_WAVE_TMA_LO=bit32;

 TSQ_WAVE_TTMP10=bit32;

 TSQ_WAVE_TTMP11=bit32;

 TSRBM_CAM_INDEX=bitpacked record
  CAM_INDEX:bit3;
  RESERVED0:bit29;
 end;

 TSRBM_READ_CNTL=bitpacked record
  READ_TIMEOUT:bit24;
  RESERVED0   :bit8;
 end;

 TSRBM_VF_ENABLE=bitpacked record
  VF_ENABLE:bit1;
  RESERVED0:bit31;
 end;

 TSRBM_VIRT_CNTL=bitpacked record
  VF_WRITE_ENABLE:bit1;
  RESERVED0      :bit31;
 end;

 TTA_DEBUG_INDEX=bitpacked record
  INDEX    :bit5;
  RESERVED0:bit27;
 end;

 TTCC_REDUNDANCY=bitpacked record
  MC_SEL0  :bit1;
  MC_SEL1  :bit1;
  RESERVED0:bit30;
 end;

 TTCP_INVALIDATE=bitpacked record
  START    :bit1;
  RESERVED0:bit31;
 end;

 TTDC_MV_AVERAGE=bitpacked record
  IDD :bit16;
  IDDC:bit16;
 end;

 TTD_DEBUG_INDEX=bitpacked record
  INDEX    :bit5;
  RESERVED0:bit27;
 end;

 TTHM_TMON2_CTRL=bitpacked record
  POWER_DOWN   :bit1;
  BGADJ        :bit8;
  BGADJ_MODE   :bit1;
  TMON_PAUSE   :bit1;
  INT_MEAS_EN  :bit1;
  DEBUG_MODE   :bit1;
  EN_CFG_SERDES:bit1;
  RESERVED0    :bit18;
 end;

 TUVD_CGC_STATUS=bitpacked record
  SYS_SCLK      :bit1;
  SYS_DCLK      :bit1;
  SYS_VCLK      :bit1;
  UDEC_SCLK     :bit1;
  UDEC_DCLK     :bit1;
  UDEC_VCLK     :bit1;
  MPEG2_SCLK    :bit1;
  MPEG2_DCLK    :bit1;
  MPEG2_VCLK    :bit1;
  REGS_SCLK     :bit1;
  REGS_VCLK     :bit1;
  RBC_SCLK      :bit1;
  LMI_MC_SCLK   :bit1;
  LMI_UMC_SCLK  :bit1;
  IDCT_SCLK     :bit1;
  IDCT_VCLK     :bit1;
  MPRD_SCLK     :bit1;
  MPRD_DCLK     :bit1;
  MPRD_VCLK     :bit1;
  MPC_SCLK      :bit1;
  MPC_DCLK      :bit1;
  LBSI_SCLK     :bit1;
  LBSI_VCLK     :bit1;
  LRBBM_SCLK    :bit1;
  WCB_SCLK      :bit1;
  VCPU_SCLK     :bit1;
  VCPU_VCLK     :bit1;
  SCPU_SCLK     :bit1;
  SCPU_VCLK     :bit1;
  RESERVED0     :bit1;
  JPEG_ACTIVE   :bit1;
  ALL_DEC_ACTIVE:bit1;
 end;

 TUVD_CONTEXT_ID=bit32;

 TUVD_LMI_STATUS=bitpacked record
  READ_CLEAN          :bit1;
  WRITE_CLEAN         :bit1;
  WRITE_CLEAN_RAW     :bit1;
  VCPU_LMI_WRITE_CLEAN:bit1;
  UMC_READ_CLEAN      :bit1;
  UMC_WRITE_CLEAN     :bit1;
  UMC_WRITE_CLEAN_RAW :bit1;
  PENDING_UVD_MC_WRITE:bit1;
  READ_CLEAN_RAW      :bit1;
  UMC_READ_CLEAN_RAW  :bit1;
  UMC_UVD_IDLE        :bit1;
  UMC_AVP_IDLE        :bit1;
  ADP_MC_READ_CLEAN   :bit1;
  ADP_UMC_READ_CLEAN  :bit1;
  RESERVED0           :bit18;
 end;

 TUVD_MASTINT_EN=bitpacked record
  OVERRUN_RST:bit1;
  VCPU_EN    :bit1;
  SYS_EN     :bit1;
  RESERVED0  :bit1;
  INT_OVERRUN:bit19;
  RESERVED1  :bit9;
 end;

 TUVD_SOFT_RESET=bitpacked record
  RBC_SOFT_RESET        :bit1;
  LBSI_SOFT_RESET       :bit1;
  LMI_SOFT_RESET        :bit1;
  VCPU_SOFT_RESET       :bit1;
  UDEC_SOFT_RESET       :bit1;
  CSM_SOFT_RESET        :bit1;
  CXW_SOFT_RESET        :bit1;
  TAP_SOFT_RESET        :bit1;
  MPC_SOFT_RESET        :bit1;
  JPEG_SCLK_RESET_STATUS:bit1;
  IH_SOFT_RESET         :bit1;
  MPRD_SOFT_RESET       :bit1;
  IDCT_SOFT_RESET       :bit1;
  LMI_UMC_SOFT_RESET    :bit1;
  SPH_SOFT_RESET        :bit1;
  MIF_SOFT_RESET        :bit1;
  LCM_SOFT_RESET        :bit1;
  SUVD_SOFT_RESET       :bit1;
  LBSI_VCLK_RESET_STATUS:bit1;
  VCPU_VCLK_RESET_STATUS:bit1;
  UDEC_VCLK_RESET_STATUS:bit1;
  UDEC_DCLK_RESET_STATUS:bit1;
  MPC_DCLK_RESET_STATUS :bit1;
  MPRD_VCLK_RESET_STATUS:bit1;
  MPRD_DCLK_RESET_STATUS:bit1;
  IDCT_VCLK_RESET_STATUS:bit1;
  MIF_DCLK_RESET_STATUS :bit1;
  LCM_DCLK_RESET_STATUS :bit1;
  SUVD_VCLK_RESET_STATUS:bit1;
  SUVD_DCLK_RESET_STATUS:bit1;
  RE_DCLK_RESET_STATUS  :bit1;
  SRE_DCLK_RESET_STATUS :bit1;
 end;

 TVCE_INT_STATUS=bitpacked record
  RESERVED0:bit16;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit1;
  RESERVED4:bit13;
 end;

 TVCE_RB_BASE_HI=bit32;

 TVCE_RB_BASE_LO=bitpacked record
  RESERVED0 :bit6;
  RB_BASE_LO:bit26;
 end;

 TVCE_SOFT_RESET=bitpacked record
  ECPU_SOFT_RESET:bit1;
  RESERVED0      :bit1;
  RESERVED1      :bit1;
  RESERVED2      :bit1;
  RESERVED3      :bit1;
  RESERVED4      :bit1;
  RESERVED5      :bit1;
  RESERVED6      :bit1;
  RESERVED7      :bit1;
  RESERVED8      :bit1;
  RESERVED9      :bit1;
  RESERVED10     :bit1;
  RESERVED11     :bit1;
  RESERVED12     :bit1;
  RESERVED13     :bit1;
  RESERVED14     :bit1;
  RESERVED15     :bit1;
  RESERVED16     :bit1;
  RESERVED17     :bit1;
  RESERVED18     :bit1;
  RESERVED19     :bit1;
  RESERVED20     :bit1;
  RESERVED21     :bit1;
  RESERVED22     :bit9;
 end;

 TVCE_SYS_INT_EN=bitpacked record
  RESERVED0                    :bit1;
  RESERVED1                    :bit2;
  VCE_SYS_INT_TRAP_INTERRUPT_EN:bit1;
  RESERVED2                    :bit1;
  RESERVED3                    :bit6;
  RESERVED4                    :bit1;
  RESERVED5                    :bit1;
  RESERVED6                    :bit1;
  RESERVED7                    :bit1;
  RESERVED8                    :bit1;
  RESERVED9                    :bit1;
  RESERVED10                   :bit1;
  RESERVED11                   :bit14;
 end;

 TVGT_DEBUG_CNTL=bitpacked record
  VGT_DEBUG_INDX     :bit6;
  VGT_DEBUG_SEL_BUS_B:bit1;
  RESERVED0          :bit25;
 end;

 TVGT_DEBUG_DATA=bit32;

 TVGT_DEBUG_REG0=bitpacked record
  vgt_busy_extended     :bit1;
  SPARE9                :bit1;
  vgt_busy              :bit1;
  SPARE8                :bit1;
  SPARE7                :bit1;
  SPARE6                :bit1;
  SPARE5                :bit1;
  SPARE4                :bit1;
  pi_busy               :bit1;
  vr_pi_busy            :bit1;
  pt_pi_busy            :bit1;
  te_pi_busy            :bit1;
  gs_busy               :bit1;
  rcm_busy              :bit1;
  tm_busy               :bit1;
  cm_busy               :bit1;
  gog_busy              :bit1;
  frmt_busy             :bit1;
  SPARE10               :bit1;
  te11_pi_busy          :bit1;
  SPARE3                :bit1;
  combined_out_busy     :bit1;
  spi_vs_interfaces_busy:bit1;
  pa_interfaces_busy    :bit1;
  reg_clk_busy          :bit1;
  SPARE2                :bit1;
  core_clk_busy         :bit1;
  gs_clk_busy           :bit1;
  SPARE1                :bit1;
  sclk_core_vld         :bit1;
  sclk_gs_vld           :bit1;
  SPARE0                :bit1;
 end;

 TVGT_DEBUG_REG1=bitpacked record
  SPARE9            :bit1;
  SPARE8            :bit1;
  SPARE7            :bit1;
  SPARE6            :bit1;
  SPARE5            :bit1;
  SPARE4            :bit1;
  SPARE3            :bit1;
  SPARE2            :bit1;
  SPARE1            :bit1;
  SPARE0            :bit1;
  pi_vr_valid       :bit1;
  vr_pi_read        :bit1;
  pi_pt_valid       :bit1;
  pt_pi_read        :bit1;
  pi_te_valid       :bit1;
  te_grp_read       :bit1;
  vr_out_indx_valid :bit1;
  SPARE12           :bit1;
  vr_out_prim_valid :bit1;
  SPARE11           :bit1;
  pt_out_indx_valid :bit1;
  SPARE10           :bit1;
  pt_out_prim_valid :bit1;
  SPARE23           :bit1;
  te_out_data_valid :bit1;
  SPARE25           :bit1;
  pi_gs_valid       :bit1;
  gs_pi_read        :bit1;
  gog_out_indx_valid:bit1;
  out_indx_read     :bit1;
  gog_out_prim_valid:bit1;
  out_prim_read     :bit1;
 end;

 TVGT_DEBUG_REG2=bitpacked record
  hs_grp_busy           :bit1;
  hs_noif_busy          :bit1;
  tfmmIsBusy            :bit1;
  lsVertIfBusy_0        :bit1;
  te11_hs_tess_input_rtr:bit1;
  lsWaveIfBusy_0        :bit1;
  hs_te11_tess_input_rts:bit1;
  grpModBusy            :bit1;
  lsVertFifoEmpty       :bit1;
  lsWaveFifoEmpty       :bit1;
  hsVertFifoEmpty       :bit1;
  hsWaveFifoEmpty       :bit1;
  hsInputFifoEmpty      :bit1;
  hsTifFifoEmpty        :bit1;
  lsVertFifoFull        :bit1;
  lsWaveFifoFull        :bit1;
  hsVertFifoFull        :bit1;
  hsWaveFifoFull        :bit1;
  hsInputFifoFull       :bit1;
  hsTifFifoFull         :bit1;
  p0_rtr                :bit1;
  p1_rtr                :bit1;
  p0_dr                 :bit1;
  p1_dr                 :bit1;
  p0_rts                :bit1;
  p1_rts                :bit1;
  ls_sh_id              :bit1;
  lsFwaveFlag           :bit1;
  lsWaveSendFlush       :bit1;
  SPARE                 :bit3;
 end;

 TVGT_DEBUG_REG3=bitpacked record
  lsTgRelInd  :bit12;
  lsWaveRelInd:bit6;
  lsPatchCnt  :bit8;
  hsWaveRelInd:bit6;
 end;

 TVGT_DEBUG_REG4=bitpacked record
  hsPatchCnt     :bit8;
  hsPrimId_15_0  :bit16;
  hsCpCnt        :bit5;
  hsWaveSendFlush:bit1;
  hsFwaveFlag    :bit1;
  SPARE          :bit1;
 end;

 TVGT_DEBUG_REG5=bitpacked record
  SPARE4           :bit3;
  hsWaveCreditCnt_0:bit5;
  SPARE3           :bit3;
  hsVertCreditCnt_0:bit5;
  SPARE2           :bit3;
  lsWaveCreditCnt_0:bit5;
  SPARE1           :bit3;
  lsVertCreditCnt_0:bit5;
 end;

 TVGT_DEBUG_REG6=bitpacked record
  debug_BASE:bit16;
  debug_SIZE:bit16;
 end;

 TVGT_DEBUG_REG7=bitpacked record
  debug_tfmmFifoEmpty:bit1;
  debug_tfmmFifoFull :bit1;
  hs_pipe0_dr        :bit1;
  hs_pipe0_rtr       :bit1;
  hs_pipe1_rtr       :bit1;
  SPARE              :bit11;
  TF_addr            :bit16;
 end;

 TVGT_DEBUG_REG8=bitpacked record
  rcm_busy_q            :bit1;
  rcm_noif_busy_q       :bit1;
  r1_inst_rtr           :bit1;
  spi_gsprim_fifo_busy_q:bit1;
  spi_esvert_fifo_busy_q:bit1;
  gs_tbl_valid_r3_q     :bit1;
  valid_r0_q            :bit1;
  valid_r1_q            :bit1;
  valid_r2              :bit1;
  valid_r2_q            :bit1;
  r0_rtr                :bit1;
  r1_rtr                :bit1;
  r2_indx_rtr           :bit1;
  r2_rtr                :bit1;
  es_gs_rtr             :bit1;
  gs_event_fifo_rtr     :bit1;
  tm_rcm_gs_event_rtr   :bit1;
  gs_tbl_r3_rtr         :bit1;
  prim_skid_fifo_empty  :bit1;
  VGT_SPI_gsprim_rtr_q  :bit1;
  tm_rcm_gs_tbl_rtr     :bit1;
  tm_rcm_es_tbl_rtr     :bit1;
  VGT_SPI_esvert_rtr_q  :bit1;
  r2_no_bp_rtr          :bit1;
  hold_for_es_flush     :bit1;
  gs_event_fifo_empty   :bit1;
  gsprim_buff_empty_q   :bit1;
  gsprim_buff_full_q    :bit1;
  te_prim_fifo_empty    :bit1;
  te_prim_fifo_full     :bit1;
  te_vert_fifo_empty    :bit1;
  te_vert_fifo_full     :bit1;
 end;

 TVGT_DEBUG_REG9=bitpacked record
  indices_to_send_r2_q           :bit2;
  valid_indices_r3               :bit1;
  gs_eov_r3                      :bit1;
  eop_indx_r3                    :bit1;
  eop_prim_r3                    :bit1;
  es_eov_r3                      :bit1;
  es_tbl_state_r3_q_0            :bit1;
  pending_es_send_r3_q           :bit1;
  pending_es_flush_r3            :bit1;
  gs_tbl_num_es_per_gs_r3_q_not_0:bit1;
  gs_tbl_prim_cnt_r3_q           :bit7;
  gs_tbl_eop_r3_q                :bit1;
  gs_tbl_state_r3_q              :bit3;
  gs_pending_state_r3_q          :bit1;
  invalidate_rb_roll_over_q      :bit1;
  gs_instancing_state_q          :bit1;
  es_per_gs_vert_cnt_r3_q_not_0  :bit1;
  gs_prim_per_es_ctr_r3_q_not_0  :bit1;
  pre_r0_rtr                     :bit1;
  valid_r3_q                     :bit1;
  valid_pre_r0_q                 :bit1;
  SPARE0                         :bit1;
  off_chip_hs_r2_q               :bit1;
 end;

 TVGT_GROUP_DECR=bitpacked record
  DECR     :bit4;
  RESERVED0:bit28;
 end;

 TVGT_IMMED_DATA=bit32;

 TVGT_INDEX_TYPE=bitpacked record
  INDEX_TYPE:bit2;
  RESERVED0 :bit30;
 end;

 TVGT_SYS_CONFIG=bitpacked record
  DUAL_CORE_EN            :bit1;
  MAX_LS_HS_THDGRP        :bit6;
  ADC_EVENT_FILTER_DISABLE:bit1;
  RESERVED0               :bit24;
 end;

 TVGT_VTX_CNT_EN=bitpacked record
  VTX_CNT_EN:bit1;
  RESERVED0 :bit31;
 end;

 TVIEWPORT_START=bitpacked record
  VIEWPORT_Y_START:bit14;
  RESERVED0       :bit2;
  VIEWPORT_X_START:bit14;
  RESERVED1       :bit2;
 end;

 TVM_INIT_STATUS=bitpacked record
  VM_INIT_STATUS:bit1;
  RESERVED0     :bit31;
 end;

 TWD_CNTL_STATUS=bitpacked record
  WD_BUSY        :bit1;
  WD_SPL_DMA_BUSY:bit1;
  WD_SPL_DI_BUSY :bit1;
  WD_ADC_BUSY    :bit1;
  RESERVED0      :bit28;
 end;

 TWD_DEBUG_REG10=bitpacked record
  ttp_pd_patch_rts          :bit1;
  ttp_pd_is_event           :bit1;
  ttp_pd_eopg               :bit1;
  ttp_pd_eop                :bit1;
  pipe0_dr                  :bit1;
  pipe1_dr                  :bit1;
  pipe0_rtr                 :bit1;
  pipe1_rtr                 :bit1;
  donut_en_p1_q             :bit1;
  donut_se_switch_p2        :bit1;
  patch_se_switch_p2        :bit1;
  last_donut_switch_p2      :bit1;
  last_donut_of_patch_p2    :bit1;
  is_event_p1_q             :bit1;
  eopg_p1_q                 :bit1;
  eop_p1_q                  :bit1;
  patch_accum_q             :bit8;
  wd_te11_out_se0_fifo_full :bit1;
  wd_te11_out_se0_fifo_empty:bit1;
  wd_te11_out_se1_fifo_full :bit1;
  wd_te11_out_se1_fifo_empty:bit1;
  wd_te11_out_se2_fifo_full :bit1;
  wd_te11_out_se2_fifo_empty:bit1;
  wd_te11_out_se3_fifo_full :bit1;
  wd_te11_out_se3_fifo_empty:bit1;
 end;

 TXDMA_IF_STATUS=bitpacked record
  XDMA_MC_PCIEWR_BUSY:bit1;
  RESERVED0          :bit31;
 end;

 TXDMA_INTERRUPT=bitpacked record
  RESERVED0                :bit8;
  XDMA_MSTR_MEM_URGENT_STAT:bit1;
  XDMA_MSTR_MEM_URGENT_MASK:bit1;
  XDMA_MSTR_MEM_URGENT_ACK :bit1;
  RESERVED1                :bit5;
  XDMA_SLV_READ_URGENT_STAT:bit1;
  XDMA_SLV_READ_URGENT_MASK:bit1;
  XDMA_SLV_READ_URGENT_ACK :bit1;
  RESERVED2                :bit1;
  XDMA_PERF_MEAS_STAT      :bit1;
  XDMA_PERF_MEAS_MASK      :bit1;
  XDMA_PERF_MEAS_ACK       :bit1;
  RESERVED3                :bit9;
 end;

 TXDMA_MSTR_CNTL=bitpacked record
  RESERVED0               :bit12;
  XDMA_MSTR_ALPHA_POSITION:bit2;
  XDMA_MSTR_MEM_READY     :bit1;
  RESERVED1               :bit1;
  XDMA_MSTR_ENABLE        :bit1;
  RESERVED2               :bit1;
  XDMA_MSTR_DEBUG_MODE    :bit1;
  RESERVED3               :bit1;
  XDMA_MSTR_SOFT_RESET    :bit1;
  XDMA_MSTR_BIF_STALL_EN  :bit1;
  RESERVED4               :bit10;
 end;

 TXDMA_PG_STATUS=bitpacked record
  XDMA_SERDES_RDATA           :bit24;
  XDMA_PGFSM_READ_READY       :bit1;
  XDMA_SERDES_BUSY            :bit1;
  XDMA_SERDES_SMU_POWER_STATUS:bit1;
  RESERVED0                   :bit5;
 end;

 TAFMT_MPEG_INFO0=bitpacked record
  AFMT_MPEG_INFO_CHECKSUM:bit8;
  AFMT_MPEG_INFO_MB0     :bit8;
  AFMT_MPEG_INFO_MB1     :bit8;
  AFMT_MPEG_INFO_MB2     :bit8;
 end;

 TAFMT_MPEG_INFO1=bitpacked record
  AFMT_MPEG_INFO_MB3:bit8;
  AFMT_MPEG_INFO_MF :bit2;
  RESERVED0         :bit2;
  AFMT_MPEG_INFO_FR :bit1;
  RESERVED1         :bit19;
 end;

 TATC_L1RD_STATUS=bitpacked record
  BUSY              :bit1;
  DEADLOCK_DETECTION:bit1;
  RESERVED0         :bit6;
  BAD_NEED_ATS      :bit1;
  RESERVED1         :bit3;
  CAM_PARITY_ERRORS :bit5;
  CAM_INDEX         :bit5;
  RESERVED2         :bit10;
 end;

 TATC_L1WR_STATUS=bitpacked record
  BUSY              :bit1;
  DEADLOCK_DETECTION:bit1;
  RESERVED0         :bit6;
  BAD_NEED_ATS      :bit1;
  RESERVED1         :bit3;
  CAM_PARITY_ERRORS :bit5;
  CAM_INDEX         :bit5;
  RESERVED2         :bit10;
 end;

 TAUX_ARB_CONTROL=bitpacked record
  AUX_ARB_PRIORITY           :bit2;
  AUX_REG_RW_CNTL_STATUS     :bit2;
  RESERVED0                  :bit4;
  AUX_NO_QUEUED_SW_GO        :bit1;
  RESERVED1                  :bit1;
  AUX_NO_QUEUED_LS_GO        :bit1;
  RESERVED2                  :bit5;
  AUX_SW_USE_AUX_REG_REQ     :bit1;
  AUX_SW_DONE_USING_AUX_REG  :bit1;
  RESERVED3                  :bit6;
  AUX_DMCU_USE_AUX_REG_REQ   :bit1;
  AUX_DMCU_DONE_USING_AUX_REG:bit1;
  RESERVED4                  :bit6;
 end;

 TBF_ANA_ISO_CNTL=bitpacked record
  BF_ANA_ISO_DIS_MASK :bit1;
  BF_VDDC_ISO_DIS_MASK:bit1;
  RESERVED0           :bit30;
 end;

 TBIF_PWDN_STATUS=bitpacked record
  BU_REG_pw_status            :bit1;
  RWREG_RFEWDBIF_REG_pw_status:bit1;
  SMBUS_REG_pw_status         :bit1;
  BX_REG_pw_status            :bit1;
  RESERVED0                   :bit28;
 end;

 TBIF_SLVARB_MODE=bitpacked record
  SLVARB_MODE:bit2;
  RESERVED0  :bit30;
 end;

 TBIOS_SCRATCH_10=bit32;

 TBIOS_SCRATCH_11=bit32;

 TBIOS_SCRATCH_12=bit32;

 TBIOS_SCRATCH_13=bit32;

 TBIOS_SCRATCH_14=bit32;

 TBIOS_SCRATCH_15=bit32;

 TCB_COLOR0_CMASK=bit32;

 TCB_COLOR0_FMASK=bit32;

 TCB_COLOR0_PITCH=bitpacked record
  TILE_MAX      :bit11;
  RESERVED0     :bit9;
  FMASK_TILE_MAX:bit11;
  RESERVED1     :bit1;
 end;

 TCB_COLOR0_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR1_CMASK=bit32;

 TCB_COLOR1_FMASK=bit32;

 TCB_COLOR1_PITCH=bitpacked record
  TILE_MAX      :bit11;
  RESERVED0     :bit9;
  FMASK_TILE_MAX:bit11;
  RESERVED1     :bit1;
 end;

 TCB_COLOR1_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR2_CMASK=bit32;

 TCB_COLOR2_FMASK=bit32;

 TCB_COLOR2_PITCH=bitpacked record
  TILE_MAX      :bit11;
  RESERVED0     :bit9;
  FMASK_TILE_MAX:bit11;
  RESERVED1     :bit1;
 end;

 TCB_COLOR2_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR3_CMASK=bit32;

 TCB_COLOR3_FMASK=bit32;

 TCB_COLOR3_PITCH=bitpacked record
  TILE_MAX      :bit11;
  RESERVED0     :bit9;
  FMASK_TILE_MAX:bit11;
  RESERVED1     :bit1;
 end;

 TCB_COLOR3_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR4_CMASK=bit32;

 TCB_COLOR4_FMASK=bit32;

 TCB_COLOR4_PITCH=bitpacked record
  TILE_MAX      :bit11;
  RESERVED0     :bit9;
  FMASK_TILE_MAX:bit11;
  RESERVED1     :bit1;
 end;

 TCB_COLOR4_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR5_CMASK=bit32;

 TCB_COLOR5_FMASK=bit32;

 TCB_COLOR5_PITCH=bitpacked record
  TILE_MAX      :bit11;
  RESERVED0     :bit9;
  FMASK_TILE_MAX:bit11;
  RESERVED1     :bit1;
 end;

 TCB_COLOR5_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR6_CMASK=bit32;

 TCB_COLOR6_FMASK=bit32;

 TCB_COLOR6_PITCH=bitpacked record
  TILE_MAX      :bit11;
  RESERVED0     :bit9;
  FMASK_TILE_MAX:bit11;
  RESERVED1     :bit1;
 end;

 TCB_COLOR6_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR7_CMASK=bit32;

 TCB_COLOR7_FMASK=bit32;

 TCB_COLOR7_PITCH=bitpacked record
  TILE_MAX      :bit11;
  RESERVED0     :bit9;
  FMASK_TILE_MAX:bit11;
  RESERVED1     :bit1;
 end;

 TCB_COLOR7_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_DEBUG_BUS_13=bitpacked record
  FC_PF_FC_KEYID_RDLAT_FIFO_FULL                :bit1;
  FC_DOC_QTILE_CAM_MISS                         :bit1;
  FC_DOC_QTILE_CAM_HIT                          :bit1;
  FC_DOC_CLINE_CAM_MISS                         :bit1;
  FC_DOC_CLINE_CAM_HIT                          :bit1;
  FC_DOC_OVERWROTE_1_SECTOR                     :bit1;
  FC_DOC_OVERWROTE_2_SECTORS                    :bit1;
  FC_DOC_OVERWROTE_3_SECTORS                    :bit1;
  FC_DOC_OVERWROTE_4_SECTORS                    :bit1;
  FC_PF_DCC_CACHE_HIT                           :bit1;
  FC_PF_DCC_CACHE_TAG_MISS                      :bit1;
  FC_PF_DCC_CACHE_SECTOR_MISS                   :bit1;
  FC_PF_DCC_CACHE_REEVICTION_STALL              :bit1;
  FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  :bit1;
  FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL   :bit1;
  FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL:bit1;
  FC_PF_DCC_CACHE_READ_OUTPUT_STALL             :bit1;
  FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL            :bit1;
  FC_PF_DCC_CACHE_ACK_OUTPUT_STALL              :bit1;
  FC_PF_DCC_CACHE_STALL                         :bit1;
  FC_PF_DCC_CACHE_FLUSH                         :bit1;
  FC_PF_DCC_CACHE_SECTORS_FLUSHED               :bit1;
  FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED         :bit1;
  FC_PF_DCC_CACHE_TAGS_FLUSHED                  :bit1;
  RESERVED0                                     :bit8;
 end;

 TCB_DEBUG_BUS_14=bitpacked record
  FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT:bit11;
  FC_MC_DCC_READ_REQUESTS_IN_FLIGHT :bit11;
  CC_PF_DCC_BEYOND_TILE_SPLIT       :bit1;
  CC_PF_DCC_RDREQ_STALL             :bit1;
  RESERVED0                         :bit8;
 end;

 TCB_DEBUG_BUS_15=bitpacked record
  CC_PF_DCC_COMPRESS_RATIO_2TO1:bit3;
  CC_PF_DCC_COMPRESS_RATIO_4TO1:bit2;
  CC_PF_DCC_COMPRESS_RATIO_4TO2:bit2;
  CC_PF_DCC_COMPRESS_RATIO_4TO3:bit2;
  CC_PF_DCC_COMPRESS_RATIO_6TO1:bit2;
  CC_PF_DCC_COMPRESS_RATIO_6TO2:bit2;
  CC_PF_DCC_COMPRESS_RATIO_6TO3:bit2;
  CC_PF_DCC_COMPRESS_RATIO_6TO4:bit2;
  CC_PF_DCC_COMPRESS_RATIO_6TO5:bit2;
  RESERVED0                    :bit13;
 end;

 TCB_DEBUG_BUS_16=bitpacked record
  CC_PF_DCC_COMPRESS_RATIO_8TO1:bit1;
  CC_PF_DCC_COMPRESS_RATIO_8TO2:bit1;
  CC_PF_DCC_COMPRESS_RATIO_8TO3:bit1;
  CC_PF_DCC_COMPRESS_RATIO_8TO4:bit1;
  CC_PF_DCC_COMPRESS_RATIO_8TO5:bit1;
  CC_PF_DCC_COMPRESS_RATIO_8TO6:bit1;
  CC_PF_DCC_COMPRESS_RATIO_8TO7:bit1;
  RESERVED0                    :bit25;
 end;

 TCB_DEBUG_BUS_17=bitpacked record
  TILE_INTFC_BUSY   :bit1;
  MU_BUSY           :bit1;
  TQ_BUSY           :bit1;
  AC_BUSY           :bit1;
  CRW_BUSY          :bit1;
  CACHE_CTRL_BUSY   :bit1;
  MC_WR_PENDING     :bit1;
  FC_WR_PENDING     :bit1;
  FC_RD_PENDING     :bit1;
  EVICT_PENDING     :bit1;
  LAST_RD_ARB_WINNER:bit1;
  MU_STATE          :bit8;
  RESERVED0         :bit13;
 end;

 TCB_DEBUG_BUS_18=bitpacked record
  TILE_RETIREMENT_BUSY     :bit1;
  FOP_BUSY                 :bit1;
  CLEAR_BUSY               :bit1;
  LAT_BUSY                 :bit1;
  CACHE_CTL_BUSY           :bit1;
  ADDR_BUSY                :bit1;
  MERGE_BUSY               :bit1;
  QUAD_BUSY                :bit1;
  TILE_BUSY                :bit1;
  DCC_BUSY                 :bit1;
  DOC_BUSY                 :bit1;
  DAG_BUSY                 :bit1;
  DOC_STALL                :bit1;
  DOC_QT_CAM_FULL          :bit1;
  DOC_CL_CAM_FULL          :bit1;
  DOC_QUAD_PTR_FIFO_FULL   :bit1;
  DOC_SECTOR_MASK_FIFO_FULL:bit1;
  DCS_READ_WINNER_LAST     :bit1;
  DCS_READ_EV_PENDING      :bit1;
  DCS_WRITE_CC_PENDING     :bit1;
  DCS_READ_CC_PENDING      :bit1;
  DCS_WRITE_MC_PENDING     :bit1;
  RESERVED0                :bit10;
 end;

 TCB_DEBUG_BUS_19=bitpacked record
  SURF_SYNC_STATE    :bit2;
  SURF_SYNC_START    :bit1;
  SF_BUSY            :bit1;
  CS_BUSY            :bit1;
  RB_BUSY            :bit1;
  DS_BUSY            :bit1;
  TB_BUSY            :bit1;
  IB_BUSY            :bit1;
  DRR_BUSY           :bit1;
  DF_BUSY            :bit1;
  DD_BUSY            :bit1;
  DC_BUSY            :bit1;
  DK_BUSY            :bit1;
  DF_SKID_FIFO_EMPTY :bit1;
  DF_CLEAR_FIFO_EMPTY:bit1;
  DD_READY           :bit1;
  DC_FIFO_FULL       :bit1;
  DC_READY           :bit1;
  RESERVED0          :bit13;
 end;

 TCB_DEBUG_BUS_20=bitpacked record
  MC_RDREQ_CREDITS     :bit6;
  MC_WRREQ_CREDITS     :bit6;
  CC_RDREQ_HAD_ITS_TURN:bit1;
  FC_RDREQ_HAD_ITS_TURN:bit1;
  CM_RDREQ_HAD_ITS_TURN:bit1;
  RESERVED0            :bit1;
  CC_WRREQ_HAD_ITS_TURN:bit1;
  FC_WRREQ_HAD_ITS_TURN:bit1;
  CM_WRREQ_HAD_ITS_TURN:bit1;
  RESERVED1            :bit1;
  CC_WRREQ_FIFO_EMPTY  :bit1;
  FC_WRREQ_FIFO_EMPTY  :bit1;
  CM_WRREQ_FIFO_EMPTY  :bit1;
  DCC_WRREQ_FIFO_EMPTY :bit1;
  RESERVED2            :bit8;
 end;

 TCB_DEBUG_BUS_21=bitpacked record
  CM_BUSY      :bit1;
  FC_BUSY      :bit1;
  CC_BUSY      :bit1;
  BB_BUSY      :bit1;
  MA_BUSY      :bit1;
  CORE_SCLK_VLD:bit1;
  REG_SCLK1_VLD:bit1;
  REG_SCLK0_VLD:bit1;
  RESERVED0    :bit24;
 end;

 TCB_DEBUG_BUS_22=bitpacked record
  OUTSTANDING_MC_READS :bit12;
  OUTSTANDING_MC_WRITES:bit12;
  RESERVED0            :bit8;
 end;

 TCB_HW_CONTROL_1=bitpacked record
  CM_CACHE_NUM_TAGS :bit5;
  FC_CACHE_NUM_TAGS :bit6;
  CC_CACHE_NUM_TAGS :bit6;
  CM_TILE_FIFO_DEPTH:bit9;
  CHICKEN_BITS      :bit6;
 end;

 TCB_HW_CONTROL_2=bitpacked record
  CC_EVEN_ODD_FIFO_DEPTH     :bit8;
  FC_RDLAT_TILE_FIFO_DEPTH   :bit7;
  FC_RDLAT_QUAD_FIFO_DEPTH   :bit8;
  RESERVED0                  :bit1;
  DRR_ASSUMED_FIFO_DEPTH_DIV8:bit4;
  CHICKEN_BITS               :bit4;
 end;

 TCB_HW_CONTROL_3=bitpacked record
  DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL           :bit1;
  RAM_ADDRESS_CONFLICTS_DISALLOWED                 :bit1;
  DISABLE_FAST_CLEAR_FETCH_OPT                     :bit1;
  DISABLE_QUAD_MARKER_DROP_STOP                    :bit1;
  DISABLE_OVERWRITE_COMBINER_CAM_CLR               :bit1;
  DISABLE_CC_CACHE_OVWR_STATUS_ACCUM               :bit1;
  DISABLE_CC_CACHE_OVWR_KEY_MOD                    :bit1;
  DISABLE_CC_CACHE_PANIC_GATING                    :bit1;
  DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION:bit1;
  SPLIT_ALL_FAST_MODE_TRANSFERS                    :bit1;
  DISABLE_SHADER_BLEND_OPTS                        :bit1;
  DISABLE_CMASK_LAST_QUAD_INSERTION                :bit1;
  DISABLE_ROP3_FIXES_OF_BUG_511967                 :bit1;
  RESERVED0                                        :bit19;
 end;

 TCG_THERMAL_CTRL=bitpacked record
  DPM_EVENT_SRC   :bit3;
  THERM_INC_CLK   :bit1;
  SPARE           :bit10;
  DIG_THERM_DPM   :bit8;
  RESERVED        :bit3;
  CTF_PAD_POLARITY:bit1;
  CTF_PAD_EN      :bit1;
  RESERVED0       :bit5;
 end;

 TCNB_PWRMGT_CNTL=bitpacked record
  GNB_SLOW_MODE:bit2;
  GNB_SLOW     :bit1;
  FORCE_NB_PS1 :bit1;
  DPM_ENABLED  :bit1;
  SPARE        :bit27;
 end;

 TCNV_CSC_C11_C12=bitpacked record
  CNV_CSC_C11:bit13;
  RESERVED0  :bit3;
  CNV_CSC_C12:bit13;
  RESERVED1  :bit3;
 end;

 TCNV_CSC_C13_C14=bitpacked record
  CNV_CSC_C13:bit13;
  RESERVED0  :bit3;
  CNV_CSC_C14:bit15;
  RESERVED1  :bit1;
 end;

 TCNV_CSC_C21_C22=bitpacked record
  CNV_CSC_C21:bit13;
  RESERVED0  :bit3;
  CNV_CSC_C22:bit13;
  RESERVED1  :bit3;
 end;

 TCNV_CSC_C23_C24=bitpacked record
  CNV_CSC_C23:bit13;
  RESERVED0  :bit3;
  CNV_CSC_C24:bit15;
  RESERVED1  :bit1;
 end;

 TCNV_CSC_C31_C32=bitpacked record
  CNV_CSC_C31:bit13;
  RESERVED0  :bit3;
  CNV_CSC_C32:bit13;
  RESERVED1  :bit3;
 end;

 TCNV_CSC_C33_C34=bitpacked record
  CNV_CSC_C33:bit13;
  RESERVED0  :bit3;
  CNV_CSC_C34:bit15;
  RESERVED1  :bit1;
 end;

 TCNV_CSC_CLAMP_B=bitpacked record
  CNV_CSC_CLAMP_UPPER_B:bit16;
  CNV_CSC_CLAMP_LOWER_B:bit16;
 end;

 TCNV_CSC_CLAMP_G=bitpacked record
  CNV_CSC_CLAMP_UPPER_G:bit16;
  CNV_CSC_CLAMP_LOWER_G:bit16;
 end;

 TCNV_CSC_CLAMP_R=bitpacked record
  CNV_CSC_CLAMP_UPPER_R:bit16;
  CNV_CSC_CLAMP_LOWER_R:bit16;
 end;

 TCNV_CSC_CONTROL=bitpacked record
  CNV_CSC_BYPASS:bit1;
  RESERVED0     :bit31;
 end;

 TCNV_SOURCE_SIZE=bitpacked record
  CNV_SOURCE_WIDTH :bit15;
  RESERVED0        :bit1;
  CNV_SOURCE_HEIGHT:bit15;
  RESERVED1        :bit1;
 end;

 TCNV_WINDOW_SIZE=bitpacked record
  CNV_WINDOW_WIDTH :bit12;
  RESERVED0        :bit4;
  CNV_WINDOW_HEIGHT:bit12;
  RESERVED1        :bit4;
 end;

 TCOMPUTE_NOWHERE=bit32;

 TCOMPUTE_START_X=bit32;

 TCOMPUTE_START_Y=bit32;

 TCOMPUTE_START_Z=bit32;

 TCONFIG_RESERVED=bit32;

 TCPC_INT_CNTX_ID=bitpacked record
  CNTX_ID  :bit28;
  QUEUE_ID :bit3;
  RESERVED0:bit1;
 end;

 TCP_CE_IB1_BUFSZ=bitpacked record
  IB1_BUFSZ:bit20;
  RESERVED0:bit12;
 end;

 TCP_CE_IB2_BUFSZ=bitpacked record
  IB2_BUFSZ:bit20;
  RESERVED0:bit12;
 end;

 TCP_CE_RB_OFFSET=bitpacked record
  RB_OFFSET:bit20;
  RESERVED0:bit12;
 end;

 TCP_COHER_STATUS=bitpacked record
  MATCHING_GFX_CNTX:bit8;
  RESERVED0        :bit16;
  MEID             :bit2;
  RESERVED1        :bit4;
  PHASE1_STATUS    :bit1;
  STATUS           :bit1;
 end;

 TCP_CONTEXT_CNTL=bitpacked record
  ME0PIPE0_MAX_WD_CNTX  :bit3;
  RESERVED0             :bit1;
  ME0PIPE0_MAX_PIPE_CNTX:bit3;
  RESERVED1             :bit9;
  ME0PIPE1_MAX_WD_CNTX  :bit3;
  RESERVED2             :bit1;
  ME0PIPE1_MAX_PIPE_CNTX:bit3;
  RESERVED3             :bit9;
 end;

 TCP_HQD_EOP_RPTR=bitpacked record
  RPTR             :bit13;
  RESERVED0        :bit17;
  RPTR_EQ_CSMD_WPTR:bit1;
  INIT_FETCHER     :bit1;
 end;

 TCP_HQD_EOP_WPTR=bitpacked record
  WPTR     :bit13;
  RESERVED0:bit3;
  EOP_AVAIL:bit13;
  RESERVED1:bit3;
 end;

 TCP_HQD_IQ_TIMER=bitpacked record
  WAIT_TIME       :bit8;
  RETRY_TYPE      :bit3;
  IMMEDIATE_EXPIRE:bit1;
  INTERRUPT_TYPE  :bit2;
  CLOCK_COUNT     :bit2;
  INTERRUPT_SIZE  :bit6;
  QUANTUM_TIMER   :bit1;
  IQ_ATC          :bit1;
  CACHE_POLICY    :bit1;
  RESERVED0       :bit2;
  MTYPE           :bit2;
  PROCESS_IQ_EN   :bit1;
  PROCESSING_IQ   :bit1;
  ACTIVE          :bit1;
 end;

 TCP_HQD_MSG_TYPE=bitpacked record
  ACTION    :bit3;
  RESERVED0 :bit1;
  SAVE_STATE:bit3;
  RESERVED1 :bit25;
 end;

 TCP_HQD_SEMA_CMD=bitpacked record
  RETRY    :bit1;
  RESULT   :bit2;
  RESERVED0:bit29;
 end;

 TCP_MEM_SLP_CNTL=bitpacked record
  CP_MEM_LS_EN          :bit1;
  CP_MEM_DS_EN          :bit1;
  RESERVED              :bit5;
  CP_LS_DS_BUSY_OVERRIDE:bit1;
  CP_MEM_LS_ON_DELAY    :bit8;
  CP_MEM_LS_OFF_DELAY   :bit8;
  RESERVED1             :bit8;
 end;

 TCP_ME_RAM_RADDR=bitpacked record
  ME_RAM_RADDR:bit13;
  RESERVED0   :bit19;
 end;

 TCP_ME_RAM_WADDR=bitpacked record
  ME_RAM_WADDR:bit13;
  RESERVED0   :bit19;
 end;

 TCP_PERFMON_CNTL=bitpacked record
  PERFMON_STATE        :bit4;
  SPM_PERFMON_STATE    :bit4;
  PERFMON_ENABLE_MODE  :bit2;
  PERFMON_SAMPLE_ENABLE:bit1;
  RESERVED0            :bit21;
 end;

 TCP_RB_RPTR_ADDR=bitpacked record
  RB_RPTR_SWAP:bit2;
  RB_RPTR_ADDR:bit30;
 end;

 TCP_ROQ_IB1_STAT=bitpacked record
  ROQ_RPTR_INDIRECT1:bit10;
  RESERVED0         :bit6;
  ROQ_WPTR_INDIRECT1:bit10;
  RESERVED1         :bit6;
 end;

 TCP_ROQ_IB2_STAT=bitpacked record
  ROQ_RPTR_INDIRECT2:bit10;
  RESERVED0         :bit6;
  ROQ_WPTR_INDIRECT2:bit10;
  RESERVED1         :bit6;
 end;

 TCP_SCRATCH_DATA=bit32;

 TCP_STRMOUT_CNTL=bitpacked record
  OFFSET_UPDATE_DONE:bit1;
  RESERVED0         :bit31;
 end;

 TCP_VMID_PREEMPT=bitpacked record
  PREEMPT_REQUEST:bit16;
  VIRT_COMMAND   :bit4;
  RESERVED0      :bit12;
 end;

 TCRTC_GSL_WINDOW=bitpacked record
  CRTC_GSL_WINDOW_START:bit14;
  RESERVED0            :bit2;
  CRTC_GSL_WINDOW_END  :bit14;
  RESERVED1            :bit2;
 end;

 TCRTC_MVP_STATUS=bitpacked record
  CRTC_FLIP_NOW_OCCURRED             :bit1;
  RESERVED0                          :bit3;
  CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED:bit1;
  RESERVED1                          :bit11;
  CRTC_FLIP_NOW_CLEAR                :bit1;
  RESERVED2                          :bit3;
  CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR   :bit1;
  RESERVED3                          :bit11;
 end;

 TCRTC_TRIGA_CNTL=bitpacked record
  CRTC_TRIGA_SOURCE_SELECT           :bit5;
  CRTC_TRIGA_POLARITY_SELECT         :bit3;
  CRTC_TRIGA_RESYNC_BYPASS_EN        :bit1;
  CRTC_TRIGA_INPUT_STATUS            :bit1;
  CRTC_TRIGA_POLARITY_STATUS         :bit1;
  CRTC_TRIGA_OCCURRED                :bit1;
  CRTC_TRIGA_RISING_EDGE_DETECT_CNTL :bit2;
  RESERVED0                          :bit2;
  CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL:bit2;
  RESERVED1                          :bit2;
  CRTC_TRIGA_FREQUENCY_SELECT        :bit2;
  RESERVED2                          :bit2;
  CRTC_TRIGA_DELAY                   :bit5;
  RESERVED3                          :bit2;
  CRTC_TRIGA_CLEAR                   :bit1;
 end;

 TCRTC_TRIGB_CNTL=bitpacked record
  CRTC_TRIGB_SOURCE_SELECT           :bit5;
  CRTC_TRIGB_POLARITY_SELECT         :bit3;
  CRTC_TRIGB_RESYNC_BYPASS_EN        :bit1;
  CRTC_TRIGB_INPUT_STATUS            :bit1;
  CRTC_TRIGB_POLARITY_STATUS         :bit1;
  CRTC_TRIGB_OCCURRED                :bit1;
  CRTC_TRIGB_RISING_EDGE_DETECT_CNTL :bit2;
  RESERVED0                          :bit2;
  CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL:bit2;
  RESERVED1                          :bit2;
  CRTC_TRIGB_FREQUENCY_SELECT        :bit2;
  RESERVED2                          :bit2;
  CRTC_TRIGB_DELAY                   :bit5;
  RESERVED3                          :bit2;
  CRTC_TRIGB_CLEAR                   :bit1;
 end;

 TDAC_CRC_CONTROL=bitpacked record
  DAC_CRC_FIELD      :bit1;
  RESERVED0          :bit7;
  DAC_CRC_ONLY_BLANKB:bit1;
  RESERVED1          :bit23;
 end;

 TDAC_CRC_SIG_RGB=bitpacked record
  DAC_CRC_SIG_BLUE :bit10;
  DAC_CRC_SIG_GREEN:bit10;
  DAC_CRC_SIG_RED  :bit10;
  RESERVED0        :bit2;
 end;

 TDAC_FIFO_STATUS=bitpacked record
  RESERVED0                   :bit1;
  DAC_FIFO_USE_OVERWRITE_LEVEL:bit1;
  DAC_FIFO_OVERWRITE_LEVEL    :bit6;
  RESERVED1                   :bit2;
  DAC_FIFO_CAL_AVERAGE_LEVEL  :bit6;
  DAC_FIFO_MAXIMUM_LEVEL      :bit4;
  RESERVED2                   :bit2;
  DAC_FIFO_MINIMUM_LEVEL      :bit4;
  RESERVED3                   :bit3;
  DAC_FIFO_CALIBRATED         :bit1;
  DAC_FIFO_FORCE_RECAL_AVERAGE:bit1;
  DAC_FIFO_FORCE_RECOMP_MINMAX:bit1;
 end;

 TDB_CREDIT_LIMIT=bitpacked record
  DB_SC_TILE_CREDITS :bit5;
  DB_SC_QUAD_CREDITS :bit5;
  DB_CB_LQUAD_CREDITS:bit3;
  RESERVED0          :bit11;
  DB_CB_TILE_CREDITS :bit7;
  RESERVED1          :bit1;
 end;

 TDB_READ_DEBUG_0=bit32;

 TDB_READ_DEBUG_1=bit32;

 TDB_READ_DEBUG_2=bit32;

 TDB_READ_DEBUG_3=bit32;

 TDB_READ_DEBUG_4=bit32;

 TDB_READ_DEBUG_5=bit32;

 TDB_READ_DEBUG_6=bit32;

 TDB_READ_DEBUG_7=bit32;

 TDB_READ_DEBUG_8=bit32;

 TDB_READ_DEBUG_9=bit32;

 TDB_READ_DEBUG_A=bit32;

 TDB_READ_DEBUG_B=bit32;

 TDB_READ_DEBUG_C=bit32;

 TDB_READ_DEBUG_D=bit32;

 TDB_READ_DEBUG_E=bit32;

 TDB_READ_DEBUG_F=bit32;

 TDB_RING_CONTROL=bitpacked record
  COUNTER_CONTROL:bit2;
  RESERVED0      :bit30;
 end;

 TDB_STENCIL_INFO=bitpacked record
  FORMAT              :bit1;
  RESERVED0           :bit12;
  TILE_SPLIT          :bit3;
  RESERVED1           :bit4;
  TILE_MODE_INDEX     :bit3;
  RESERVED2           :bit4;
  ALLOW_EXPCLEAR      :bit1;
  RESERVED3           :bit1;
  TILE_STENCIL_DISABLE:bit1;
  CLEAR_DISALLOWED    :bit1;
  RESERVED4           :bit1;
 end;

 TDB_Z_WRITE_BASE=bit32;

 TDCCG_CAC_STATUS=bit32;

 TDCCG_SOFT_RESET=bitpacked record
  REFCLK_SOFT_RESET        :bit1;
  PCIE_REFCLK_SOFT_RESET   :bit1;
  SOFT_RESET_DVO           :bit1;
  DVO_ENABLE_RST           :bit1;
  AUDIO_DTO2_CLK_SOFT_RESET:bit1;
  RESERVED0                :bit3;
  DPREFCLK_SOFT_RESET      :bit1;
  RESERVED1                :bit3;
  AMCLK0_SOFT_RESET        :bit1;
  AMCLK1_SOFT_RESET        :bit1;
  P0PLL_CFG_IF_SOFT_RESET  :bit1;
  P1PLL_CFG_IF_SOFT_RESET  :bit1;
  P2PLL_CFG_IF_SOFT_RESET  :bit1;
  A0PLL_CFG_IF_SOFT_RESET  :bit1;
  A1PLL_CFG_IF_SOFT_RESET  :bit1;
  C0PLL_CFG_IF_SOFT_RESET  :bit1;
  C1PLL_CFG_IF_SOFT_RESET  :bit1;
  C2PLL_CFG_IF_SOFT_RESET  :bit1;
  RESERVED2                :bit10;
 end;

 TDCCG_VPCLK_CNTL=bitpacked record
  DCCG_VPCLK_POL:bit1;
  RESERVED0     :bit31;
 end;

 TDCE_VCE_CONTROL=bitpacked record
  DC_VCE_VIDEO_PIPE_SELECT  :bit3;
  RESERVED0                 :bit1;
  DC_VCE_AUDIO_STREAM_SELECT:bit3;
  RESERVED1                 :bit25;
 end;

 TDCFE_DBG_CONFIG=bitpacked record
  DCFE_DBG_EN :bit1;
  RESERVED0   :bit3;
  DCFE_DBG_SEL:bit4;
  RESERVED1   :bit24;
 end;

 TDCFE_SOFT_RESET=bitpacked record
  DCP_PIXPIPE_SOFT_RESET:bit1;
  DCP_REQ_SOFT_RESET    :bit1;
  SCL_ALU_SOFT_RESET    :bit1;
  SCL_SOFT_RESET        :bit1;
  CRTC_SOFT_RESET       :bit1;
  RESERVED0             :bit27;
 end;

 TDCIO_CLOCK_CNTL=bitpacked record
  DCIO_TEST_CLK_SEL      :bit5;
  DISPCLK_R_DCIO_GATE_DIS:bit1;
  RESERVED0              :bit2;
  DISPCLK_R_DCIO_RAMP_DIS:bit1;
  RESERVED1              :bit23;
 end;

 TDCIO_SOFT_RESET=bitpacked record
  UNIPHYA_SOFT_RESET:bit1;
  DSYNCA_SOFT_RESET :bit1;
  UNIPHYB_SOFT_RESET:bit1;
  DSYNCB_SOFT_RESET :bit1;
  UNIPHYC_SOFT_RESET:bit1;
  DSYNCC_SOFT_RESET :bit1;
  UNIPHYD_SOFT_RESET:bit1;
  DSYNCD_SOFT_RESET :bit1;
  UNIPHYE_SOFT_RESET:bit1;
  DSYNCE_SOFT_RESET :bit1;
  UNIPHYF_SOFT_RESET:bit1;
  DSYNCF_SOFT_RESET :bit1;
  UNIPHYG_SOFT_RESET:bit1;
  DSYNCG_SOFT_RESET :bit1;
  RESERVED0         :bit2;
  DACA_SOFT_RESET   :bit1;
  RESERVED1         :bit3;
  DCRXPHY_SOFT_RESET:bit1;
  RESERVED2         :bit3;
  DPHY_SOFT_RESET   :bit1;
  RESERVED3         :bit7;
 end;

 TDCP_CRC_CONTROL=bitpacked record
  DCP_CRC_ENABLE    :bit1;
  RESERVED0         :bit1;
  DCP_CRC_SOURCE_SEL:bit3;
  RESERVED1         :bit3;
  DCP_CRC_LINE_SEL  :bit2;
  RESERVED2         :bit22;
 end;

 TDCP_CRC_CURRENT=bit32;

 TDCP_GSL_CONTROL=bitpacked record
  DCP_GSL0_EN                         :bit1;
  DCP_GSL1_EN                         :bit1;
  DCP_GSL2_EN                         :bit1;
  RESERVED0                           :bit5;
  DCP_GSL_MODE                        :bit2;
  RESERVED1                           :bit2;
  DCP_GSL_HSYNC_FLIP_FORCE_DELAY      :bit4;
  DCP_GSL_MASTER_EN                   :bit1;
  DCP_GSL_XDMA_GROUP                  :bit2;
  DCP_GSL_XDMA_GROUP_UNDERFLOW_EN     :bit1;
  RESERVED2                           :bit4;
  DCP_GSL_SYNC_SOURCE                 :bit2;
  RESERVED3                           :bit1;
  DCP_GSL_DELAY_SURFACE_UPDATE_PENDING:bit1;
  DCP_GSL_HSYNC_FLIP_CHECK_DELAY      :bit4;
 end;

 TDC_DMCU_SCRATCH=bit32;

 TDC_GPIO_DDC1_EN=bitpacked record
  DC_GPIO_DDC1CLK_EN :bit1;
  RESERVED0          :bit7;
  DC_GPIO_DDC1DATA_EN:bit1;
  RESERVED1          :bit23;
 end;

 TDC_GPIO_DDC2_EN=bitpacked record
  DC_GPIO_DDC2CLK_EN :bit1;
  RESERVED0          :bit7;
  DC_GPIO_DDC2DATA_EN:bit1;
  RESERVED1          :bit23;
 end;

 TDC_GPIO_DDC3_EN=bitpacked record
  DC_GPIO_DDC3CLK_EN :bit1;
  RESERVED0          :bit7;
  DC_GPIO_DDC3DATA_EN:bit1;
  RESERVED1          :bit23;
 end;

 TDC_GPIO_DDC4_EN=bitpacked record
  DC_GPIO_DDC4CLK_EN :bit1;
  RESERVED0          :bit7;
  DC_GPIO_DDC4DATA_EN:bit1;
  RESERVED1          :bit23;
 end;

 TDC_GPIO_DDC5_EN=bitpacked record
  DC_GPIO_DDC5CLK_EN :bit1;
  RESERVED0          :bit7;
  DC_GPIO_DDC5DATA_EN:bit1;
  RESERVED1          :bit23;
 end;

 TDC_GPIO_DDC6_EN=bitpacked record
  DC_GPIO_DDC6CLK_EN :bit1;
  RESERVED0          :bit7;
  DC_GPIO_DDC6DATA_EN:bit1;
  RESERVED1          :bit23;
 end;

 TDC_GPIO_GENLK_A=bitpacked record
  DC_GPIO_GENLK_CLK_A  :bit1;
  RESERVED0            :bit7;
  DC_GPIO_GENLK_VSYNC_A:bit1;
  RESERVED1            :bit7;
  DC_GPIO_SWAPLOCK_A_A :bit1;
  RESERVED2            :bit7;
  DC_GPIO_SWAPLOCK_B_A :bit1;
  RESERVED3            :bit7;
 end;

 TDC_GPIO_GENLK_Y=bitpacked record
  DC_GPIO_GENLK_CLK_Y  :bit1;
  RESERVED0            :bit7;
  DC_GPIO_GENLK_VSYNC_Y:bit1;
  RESERVED1            :bit7;
  DC_GPIO_SWAPLOCK_A_Y :bit1;
  RESERVED2            :bit7;
  DC_GPIO_SWAPLOCK_B_Y :bit1;
  RESERVED3            :bit7;
 end;

 TDC_GPIO_SYNCA_A=bitpacked record
  DC_GPIO_HSYNCA_A:bit1;
  RESERVED0       :bit7;
  DC_GPIO_VSYNCA_A:bit1;
  RESERVED1       :bit23;
 end;

 TDC_GPIO_SYNCA_Y=bitpacked record
  DC_GPIO_HSYNCA_Y:bit1;
  RESERVED0       :bit7;
  DC_GPIO_VSYNCA_Y:bit1;
  RESERVED1       :bit23;
 end;

 TDC_HPD1_CONTROL=bitpacked record
  DC_HPD1_CONNECTION_TIMER:bit13;
  RESERVED0               :bit3;
  DC_HPD1_RX_INT_TIMER    :bit10;
  RESERVED1               :bit2;
  DC_HPD1_EN              :bit1;
  RESERVED2               :bit3;
 end;

 TDC_HPD2_CONTROL=bitpacked record
  DC_HPD2_CONNECTION_TIMER:bit13;
  RESERVED0               :bit3;
  DC_HPD2_RX_INT_TIMER    :bit10;
  RESERVED1               :bit2;
  DC_HPD2_EN              :bit1;
  RESERVED2               :bit3;
 end;

 TDC_HPD3_CONTROL=bitpacked record
  DC_HPD3_CONNECTION_TIMER:bit13;
  RESERVED0               :bit3;
  DC_HPD3_RX_INT_TIMER    :bit10;
  RESERVED1               :bit2;
  DC_HPD3_EN              :bit1;
  RESERVED2               :bit3;
 end;

 TDC_HPD4_CONTROL=bitpacked record
  DC_HPD4_CONNECTION_TIMER:bit13;
  RESERVED0               :bit3;
  DC_HPD4_RX_INT_TIMER    :bit10;
  RESERVED1               :bit2;
  DC_HPD4_EN              :bit1;
  RESERVED2               :bit3;
 end;

 TDC_HPD5_CONTROL=bitpacked record
  DC_HPD5_CONNECTION_TIMER:bit13;
  RESERVED0               :bit3;
  DC_HPD5_RX_INT_TIMER    :bit10;
  RESERVED1               :bit2;
  DC_HPD5_EN              :bit1;
  RESERVED2               :bit3;
 end;

 TDC_HPD6_CONTROL=bitpacked record
  DC_HPD6_CONNECTION_TIMER:bit13;
  RESERVED0               :bit3;
  DC_HPD6_RX_INT_TIMER    :bit10;
  RESERVED1               :bit2;
  DC_HPD6_EN              :bit1;
  RESERVED2               :bit3;
 end;

 TDC_LUT_30_COLOR=bitpacked record
  DC_LUT_COLOR_10_BLUE :bit10;
  DC_LUT_COLOR_10_GREEN:bit10;
  DC_LUT_COLOR_10_RED  :bit10;
  RESERVED0            :bit2;
 end;

 TDC_LUT_AUTOFILL=bitpacked record
  DC_LUT_AUTOFILL     :bit1;
  DC_LUT_AUTOFILL_DONE:bit1;
  RESERVED0           :bit30;
 end;

 TDC_LUT_PWL_DATA=bitpacked record
  DC_LUT_BASE :bit16;
  DC_LUT_DELTA:bit16;
 end;

 TDC_LUT_RW_INDEX=bitpacked record
  DC_LUT_RW_INDEX:bit8;
  RESERVED0      :bit24;
 end;

 TDC_REF_CLK_CNTL=bitpacked record
  HSYNCA_OUTPUT_SEL   :bit2;
  RESERVED0           :bit6;
  GENLK_CLK_OUTPUT_SEL:bit2;
  RESERVED1           :bit22;
 end;

 TDEGAMMA_CONTROL=bitpacked record
  GRPH_DEGAMMA_MODE   :bit2;
  RESERVED0           :bit2;
  OVL_DEGAMMA_MODE    :bit2;
  RESERVED1           :bit2;
  CURSOR2_DEGAMMA_MODE:bit2;
  RESERVED2           :bit2;
  CURSOR_DEGAMMA_MODE :bit2;
  RESERVED3           :bit18;
 end;

 TDIG_FIFO_STATUS=bitpacked record
  DIG_FIFO_LEVEL_ERROR        :bit1;
  DIG_FIFO_USE_OVERWRITE_LEVEL:bit1;
  DIG_FIFO_OVERWRITE_LEVEL    :bit6;
  DIG_FIFO_ERROR_ACK          :bit1;
  RESERVED0                   :bit1;
  DIG_FIFO_CAL_AVERAGE_LEVEL  :bit6;
  DIG_FIFO_MAXIMUM_LEVEL      :bit5;
  RESERVED1                   :bit1;
  DIG_FIFO_MINIMUM_LEVEL      :bit4;
  RESERVED2                   :bit3;
  DIG_FIFO_CALIBRATED         :bit1;
  DIG_FIFO_FORCE_RECAL_AVERAGE:bit1;
  DIG_FIFO_FORCE_RECOMP_MINMAX:bit1;
 end;

 TDIG_LANE_ENABLE=bitpacked record
  DIG_LANE0EN:bit1;
  DIG_LANE1EN:bit1;
  DIG_LANE2EN:bit1;
  DIG_LANE3EN:bit1;
  RESERVED0  :bit4;
  DIG_CLK_EN :bit1;
  RESERVED1  :bit23;
 end;

 TDISPPLL_BG_CNTL=bitpacked record
  DISPPLL_BG_PDN:bit1;
  RESERVED0     :bit3;
  DISPPLL_BG_ADJ:bit4;
  RESERVED1     :bit24;
 end;

 TDPDBG_INTERRUPT=bitpacked record
  DPDBG_FIFO_OVERFLOW_INT_MASK  :bit1;
  DPDBG_FIFO_OVERFLOW_INT_TYPE  :bit1;
  RESERVED0                     :bit6;
  DPDBG_FIFO_OVERFLOW_INT_ACK   :bit1;
  RESERVED1                     :bit7;
  DPDBG_FIFO_OVERFLOW_OCCURRED  :bit1;
  RESERVED2                     :bit7;
  DPDBG_FIFO_OVERFLOW_INT_STATUS:bit1;
  RESERVED3                     :bit7;
 end;

 TDPG_HW_DEBUG_11=bitpacked record
  DPG_HW_DEBUG_11:bit1;
  RESERVED0      :bit31;
 end;

 TDP_AUX1_DEBUG_A=bit32;

 TDP_AUX1_DEBUG_B=bit32;

 TDP_AUX1_DEBUG_C=bit32;

 TDP_AUX1_DEBUG_D=bit32;

 TDP_AUX1_DEBUG_E=bit32;

 TDP_AUX1_DEBUG_F=bit32;

 TDP_AUX1_DEBUG_G=bit32;

 TDP_AUX1_DEBUG_H=bit32;

 TDP_AUX1_DEBUG_I=bit32;

 TDP_AUX2_DEBUG_A=bit32;

 TDP_AUX2_DEBUG_B=bit32;

 TDP_AUX2_DEBUG_C=bit32;

 TDP_AUX2_DEBUG_D=bit32;

 TDP_AUX2_DEBUG_E=bit32;

 TDP_AUX2_DEBUG_F=bit32;

 TDP_AUX2_DEBUG_G=bit32;

 TDP_AUX2_DEBUG_H=bit32;

 TDP_AUX2_DEBUG_I=bit32;

 TDP_AUX3_DEBUG_A=bit32;

 TDP_AUX3_DEBUG_B=bit32;

 TDP_AUX3_DEBUG_C=bit32;

 TDP_AUX3_DEBUG_D=bit32;

 TDP_AUX3_DEBUG_E=bit32;

 TDP_AUX3_DEBUG_F=bit32;

 TDP_AUX3_DEBUG_G=bit32;

 TDP_AUX3_DEBUG_H=bit32;

 TDP_AUX3_DEBUG_I=bit32;

 TDP_AUX4_DEBUG_A=bit32;

 TDP_AUX4_DEBUG_B=bit32;

 TDP_AUX4_DEBUG_C=bit32;

 TDP_AUX4_DEBUG_D=bit32;

 TDP_AUX4_DEBUG_E=bit32;

 TDP_AUX4_DEBUG_F=bit32;

 TDP_AUX4_DEBUG_G=bit32;

 TDP_AUX4_DEBUG_H=bit32;

 TDP_AUX4_DEBUG_I=bit32;

 TDP_AUX5_DEBUG_A=bit32;

 TDP_AUX5_DEBUG_B=bit32;

 TDP_AUX5_DEBUG_C=bit32;

 TDP_AUX5_DEBUG_D=bit32;

 TDP_AUX5_DEBUG_E=bit32;

 TDP_AUX5_DEBUG_F=bit32;

 TDP_AUX5_DEBUG_G=bit32;

 TDP_AUX5_DEBUG_H=bit32;

 TDP_AUX5_DEBUG_I=bit32;

 TDP_AUX6_DEBUG_A=bit32;

 TDP_AUX6_DEBUG_B=bit32;

 TDP_AUX6_DEBUG_C=bit32;

 TDP_AUX6_DEBUG_D=bit32;

 TDP_AUX6_DEBUG_E=bit32;

 TDP_AUX6_DEBUG_F=bit32;

 TDP_AUX6_DEBUG_G=bit32;

 TDP_AUX6_DEBUG_H=bit32;

 TDP_AUX6_DEBUG_I=bit32;

 TDP_PIXEL_FORMAT=bitpacked record
  DP_PIXEL_ENCODING :bit3;
  RESERVED0         :bit5;
  DP_DYN_RANGE      :bit1;
  RESERVED1         :bit7;
  DP_YCBCR_RANGE    :bit1;
  RESERVED2         :bit7;
  DP_COMPONENT_DEPTH:bit3;
  RESERVED3         :bit5;
 end;

 TDP_SEC_FRAMING1=bitpacked record
  DP_SEC_FRAME_START_LOCATION :bit12;
  RESERVED0                   :bit4;
  DP_SEC_VBLANK_TRANSMIT_WIDTH:bit16;
 end;

 TDP_SEC_FRAMING2=bitpacked record
  DP_SEC_START_POSITION       :bit16;
  DP_SEC_HBLANK_TRANSMIT_WIDTH:bit16;
 end;

 TDP_SEC_FRAMING3=bitpacked record
  DP_SEC_IDLE_FRAME_SIZE    :bit14;
  RESERVED0                 :bit2;
  DP_SEC_IDLE_TRANSMIT_WIDTH:bit16;
 end;

 TDP_SEC_FRAMING4=bitpacked record
  RESERVED0               :bit20;
  DP_SEC_COLLISION_STATUS :bit1;
  RESERVED1               :bit3;
  DP_SEC_COLLISION_ACK    :bit1;
  RESERVED2               :bit3;
  DP_SEC_AUDIO_MUTE       :bit1;
  DP_SEC_AUDIO_MUTE_STATUS:bit1;
  RESERVED3               :bit2;
 end;

 TDP_VID_MSA_VBID=bitpacked record
  DP_VID_MSA_LOCATION      :bit12;
  RESERVED0                :bit4;
  DP_VID_MSA_TOP_FIELD_MODE:bit1;
  RESERVED1                :bit7;
  DP_VID_VBID_FIELD_POL    :bit1;
  RESERVED2                :bit7;
 end;

 TDVO_SKEW_ADJUST=bit32;

 TGC_CAC_ACC_CU10=bit32;

 TGC_CAC_ACC_CU11=bit32;

 TGC_CAC_ACC_CU12=bit32;

 TGC_CAC_ACC_CU13=bit32;

 TGC_CAC_ACC_CU14=bit32;

 TGC_CAC_ACC_CU15=bit32;

 TGDS_ATOM_SRC0_U=bit32;

 TGDS_ATOM_SRC1_U=bit32;

 TGDS_CNTL_STATUS=bitpacked record
  GDS_BUSY        :bit1;
  GRBM_WBUF_BUSY  :bit1;
  ORD_APP_BUSY    :bit1;
  DS_BANK_CONFLICT:bit1;
  DS_ADDR_CONFLICT:bit1;
  DS_WR_CLAMP     :bit1;
  DS_RD_CLAMP     :bit1;
  GRBM_RBUF_BUSY  :bit1;
  DS_BUSY         :bit1;
  GWS_BUSY        :bit1;
  ORD_FIFO_BUSY   :bit1;
  CREDIT_BUSY0    :bit1;
  CREDIT_BUSY1    :bit1;
  CREDIT_BUSY2    :bit1;
  CREDIT_BUSY3    :bit1;
  RESERVED0       :bit17;
 end;

 TGDS_VMID10_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID10_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID11_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID11_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID12_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID12_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID13_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID13_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID14_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID14_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGDS_VMID15_BASE=bitpacked record
  BASE     :bit16;
  RESERVED0:bit16;
 end;

 TGDS_VMID15_SIZE=bitpacked record
  SIZE     :bit17;
  RESERVED0:bit15;
 end;

 TGRBM_DEBUG_CNTL=bitpacked record
  GRBM_DEBUG_INDEX:bit6;
  RESERVED0       :bit26;
 end;

 TGRBM_DEBUG_DATA=bit32;

 TGRBM_DSM_BYPASS=bitpacked record
  BYPASS_BITS:bit2;
  BYPASS_EN  :bit1;
  RESERVED0  :bit29;
 end;

 TGRBM_READ_ERROR=bitpacked record
  RESERVED0   :bit2;
  READ_ADDRESS:bit16;
  RESERVED1   :bit2;
  READ_PIPEID :bit2;
  READ_MEID   :bit2;
  RESERVED2   :bit7;
  READ_ERROR  :bit1;
 end;

 TGRBM_SOFT_RESET=bitpacked record
  SOFT_RESET_CP :bit1;
  RESERVED0     :bit1;
  SOFT_RESET_RLC:bit1;
  RESERVED1     :bit1;
  RESERVED2     :bit1;
  RESERVED3     :bit1;
  RESERVED4     :bit1;
  RESERVED5     :bit1;
  RESERVED6     :bit1;
  RESERVED7     :bit1;
  RESERVED8     :bit1;
  RESERVED9     :bit1;
  RESERVED10    :bit1;
  RESERVED11    :bit1;
  RESERVED12    :bit1;
  RESERVED13    :bit1;
  SOFT_RESET_GFX:bit1;
  SOFT_RESET_CPF:bit1;
  SOFT_RESET_CPC:bit1;
  SOFT_RESET_CPG:bit1;
  SOFT_RESET_CAC:bit1;
  RESERVED14    :bit11;
 end;

 TGRBM_STATUS_SE0=bitpacked record
  RESERVED0:bit1;
  DB_CLEAN :bit1;
  CB_CLEAN :bit1;
  RESERVED1:bit19;
  BCI_BUSY :bit1;
  VGT_BUSY :bit1;
  PA_BUSY  :bit1;
  TA_BUSY  :bit1;
  SX_BUSY  :bit1;
  SPI_BUSY :bit1;
  RESERVED2:bit1;
  SC_BUSY  :bit1;
  DB_BUSY  :bit1;
  CB_BUSY  :bit1;
 end;

 TGRBM_STATUS_SE1=bitpacked record
  RESERVED0:bit1;
  DB_CLEAN :bit1;
  CB_CLEAN :bit1;
  RESERVED1:bit19;
  BCI_BUSY :bit1;
  VGT_BUSY :bit1;
  PA_BUSY  :bit1;
  TA_BUSY  :bit1;
  SX_BUSY  :bit1;
  SPI_BUSY :bit1;
  RESERVED2:bit1;
  SC_BUSY  :bit1;
  DB_BUSY  :bit1;
  CB_BUSY  :bit1;
 end;

 TGRBM_STATUS_SE2=bitpacked record
  RESERVED0:bit1;
  DB_CLEAN :bit1;
  CB_CLEAN :bit1;
  RESERVED1:bit19;
  BCI_BUSY :bit1;
  VGT_BUSY :bit1;
  PA_BUSY  :bit1;
  TA_BUSY  :bit1;
  SX_BUSY  :bit1;
  SPI_BUSY :bit1;
  RESERVED2:bit1;
  SC_BUSY  :bit1;
  DB_BUSY  :bit1;
  CB_BUSY  :bit1;
 end;

 TGRBM_STATUS_SE3=bitpacked record
  RESERVED0:bit1;
  DB_CLEAN :bit1;
  CB_CLEAN :bit1;
  RESERVED1:bit19;
  BCI_BUSY :bit1;
  VGT_BUSY :bit1;
  PA_BUSY  :bit1;
  TA_BUSY  :bit1;
  SX_BUSY  :bit1;
  SPI_BUSY :bit1;
  RESERVED2:bit1;
  SC_BUSY  :bit1;
  DB_BUSY  :bit1;
  CB_BUSY  :bit1;
 end;

 TGRPH_DFQ_STATUS=bitpacked record
  GRPH_PRIMARY_DFQ_NUM_ENTRIES  :bit4;
  GRPH_SECONDARY_DFQ_NUM_ENTRIES:bit4;
  GRPH_DFQ_RESET_FLAG           :bit1;
  GRPH_DFQ_RESET_ACK            :bit1;
  RESERVED0                     :bit22;
 end;

 THDP_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit1;
  NUM_GPUS               :bit3;
  RESERVED5              :bit1;
  MULTI_GPU_TILE_SIZE    :bit2;
  RESERVED6              :bit2;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED7              :bit1;
 end;

 THDP_XDP_HST_CFG=bitpacked record
  HST_CFG_WR_COMBINE_EN   :bit1;
  HST_CFG_WR_COMBINE_TIMER:bit2;
  RESERVED0               :bit29;
 end;

 THDP_XDP_SID_CFG=bitpacked record
  SID_CFG_WR_COMBINE_EN   :bit1;
  SID_CFG_WR_COMBINE_TIMER:bit2;
  SID_CFG_FLNUM_MSB_SEL   :bit2;
  RESERVED0               :bit27;
 end;

 TIH_LEVEL_STATUS=bitpacked record
  DC_STATUS  :bit1;
  RESERVED0  :bit1;
  ROM_STATUS :bit1;
  SRBM_STATUS:bit1;
  BIF_STATUS :bit1;
  XDMA_STATUS:bit1;
  RESERVED1  :bit26;
 end;

 TIH_PERFMON_CNTL=bitpacked record
  ENABLE0  :bit1;
  CLEAR0   :bit1;
  PERF_SEL0:bit6;
  ENABLE1  :bit1;
  CLEAR1   :bit1;
  PERF_SEL1:bit6;
  RESERVED0:bit16;
 end;

 TIH_VF_RB_STATUS=bitpacked record
  RB_FULL_DRAIN_VF:bit16;
  RB_OVERFLOW_VF  :bit16;
 end;

 TINTERRUPT_CNTL2=bit32;

 TKEY_RANGE_ALPHA=bitpacked record
  KEY_ALPHA_LOW :bit16;
  KEY_ALPHA_HIGH:bit16;
 end;

 TKEY_RANGE_GREEN=bitpacked record
  KEY_GREEN_LOW :bit16;
  KEY_GREEN_HIGH:bit16;
 end;

 TLBV_DATA_FORMAT=bitpacked record
  PIXEL_DEPTH          :bit2;
  PIXEL_EXPAN_MODE     :bit1;
  INTERLEAVE_EN        :bit1;
  PIXEL_REDUCE_MODE    :bit1;
  DYNAMIC_PIXEL_DEPTH  :bit1;
  DITHER_EN            :bit1;
  DOWNSCALE_PREFETCH_EN:bit1;
  RESERVED0            :bit4;
  PREFETCH             :bit1;
  RESERVED1            :bit11;
  REQUEST_MODE         :bit1;
  RESERVED2            :bit6;
  ALPHA_EN             :bit1;
 end;

 TLBV_MEMORY_CTRL=bitpacked record
  LB_MEMORY_SIZE   :bit12;
  RESERVED0        :bit4;
  LB_NUM_PARTITIONS:bit4;
  LB_MEMORY_CONFIG :bit2;
  RESERVED1        :bit10;
 end;

 TLB_VLINE_STATUS=bitpacked record
  VLINE_OCCURRED      :bit1;
  RESERVED0           :bit3;
  VLINE_ACK           :bit1;
  RESERVED1           :bit7;
  VLINE_STAT          :bit1;
  RESERVED2           :bit3;
  VLINE_INTERRUPT     :bit1;
  VLINE_INTERRUPT_TYPE:bit1;
  RESERVED3           :bit14;
 end;

 TLM_POWERCONTROL=bitpacked record
  LMTxPhyCmd0 :bit3;
  LMRxPhyCmd0 :bit3;
  LMLinkSpeed0:bit2;
  LMTxPhyCmd1 :bit3;
  LMRxPhyCmd1 :bit3;
  LMLinkSpeed1:bit2;
  LMTxPhyCmd2 :bit3;
  LMRxPhyCmd2 :bit3;
  LMLinkSpeed2:bit2;
  LMTxPhyCmd3 :bit3;
  LMRxPhyCmd3 :bit3;
  LMLinkSpeed3:bit2;
 end;

 TLNCNT_QUAN_THRD=bitpacked record
  CFG_LNC_BW_QUAN_THRD0 :bit3;
  RESERVED0             :bit1;
  CFG_LNC_CMN_QUAN_THRD4:bit3;
  RESERVED1             :bit25;
 end;

 TMAILBOX_CONTROL=bitpacked record
  TRN_MSG_VALID:bit1;
  TRN_MSG_ACK  :bit1;
  RCV_MSG_VALID:bit1;
  RCV_MSG_ACK  :bit1;
  RESERVED0    :bit28;
 end;

 TMC_ARB_AGE_CNTL=bitpacked record
  RESET_RD_GROUP0 :bit1;
  RESET_RD_GROUP1 :bit1;
  RESET_RD_GROUP2 :bit1;
  RESET_RD_GROUP3 :bit1;
  RESET_RD_GROUP4 :bit1;
  RESET_RD_GROUP5 :bit1;
  RESET_RD_GROUP6 :bit1;
  RESET_RD_GROUP7 :bit1;
  RESET_WR_GROUP0 :bit1;
  RESET_WR_GROUP1 :bit1;
  RESET_WR_GROUP2 :bit1;
  RESET_WR_GROUP3 :bit1;
  RESET_WR_GROUP4 :bit1;
  RESET_WR_GROUP5 :bit1;
  RESET_WR_GROUP6 :bit1;
  RESET_WR_GROUP7 :bit1;
  AGE_LOW_RATE_RD :bit3;
  AGE_LOW_RATE_WR :bit3;
  TIMER_STALL_RD  :bit1;
  TIMER_STALL_WR  :bit1;
  EXTEND_WEIGHT_RD:bit1;
  EXTEND_WEIGHT_WR:bit1;
  RESERVED0       :bit6;
 end;

 TMC_ARB_CAC_CNTL=bitpacked record
  ENABLE        :bit1;
  READ_WEIGHT   :bit6;
  WRITE_WEIGHT  :bit6;
  ALLOW_OVERFLOW:bit1;
  RESERVED0     :bit18;
 end;

 TMC_ARB_FED_CNTL=bitpacked record
  MODE               :bit2;
  WR_ERR             :bit2;
  KEEP_POISON_IN_PAGE:bit1;
  RDRET_PARITY_NACK  :bit1;
  USE_LEGACY_NACK    :bit1;
  DEBUG_RSV          :bit25;
 end;

 TMC_ARB_LAZY0_RD=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_LAZY0_WR=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_LAZY1_RD=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_ARB_LAZY1_WR=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_ARB_PERF_CID=bitpacked record
  CH0      :bit8;
  CH1      :bit8;
  CH0_EN   :bit1;
  CH1_EN   :bit1;
  RESERVED0:bit14;
 end;

 TMC_ARB_RTT_DATA=bitpacked record
  PATTERN  :bit8;
  RESERVED0:bit24;
 end;

 TMC_ARB_SQM_CNTL=bitpacked record
  MIN_PENAL     :bit8;
  DYN_SQM_ENABLE:bit1;
  SQM_RDY16     :bit1;
  SQM_RESERVE   :bit6;
  RATIO         :bit8;
  RATIO_DEBUG   :bit8;
 end;

 TMC_HUB_RDREQ_CP=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit2;
  RESERVED2:bit1;
  RESERVED3:bit2;
  RESERVED4:bit1;
  RESERVED5:bit4;
  RESERVED6:bit4;
  RESERVED7:bit1;
  RESERVED8:bit16;
 end;

 TMC_HUB_WDP_ACPG=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_HUB_WDP_ACPO=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_HUB_WDP_CNTL=bitpacked record
  RESERVED0                 :bit1;
  JUMPAHEAD_GBL0            :bit1;
  JUMPAHEAD_GBL1            :bit1;
  JUMPAHEAD_INTERNAL        :bit1;
  OVERRIDE_STALL_ENABLE     :bit1;
  DEBUG_REG                 :bit8;
  DISABLE_SELF_INIT_GBL0    :bit1;
  DISABLE_SELF_INIT_GBL1    :bit1;
  DISABLE_SELF_INIT_INTERNAL:bit1;
  FAIR_CH_SW                :bit1;
  LCLWRREQ_BYPASS           :bit1;
  DISP_WAIT_EOP             :bit1;
  MCD_WAIT_EOP              :bit1;
  SIP_WAIT_EOP              :bit1;
  UVD_VCE_WRITE_PRI_EN      :bit1;
  WRITE_PRI_EN              :bit1;
  IH_PHYSADDR_ENABLE        :bit1;
  RESERVED1                 :bit8;
 end;

 TMC_HUB_WDP_GBL0=bitpacked record
  MAXBURST           :bit4;
  LAZY_TIMER         :bit4;
  STALL_THRESHOLD    :bit8;
  STALL_MODE         :bit1;
  STALL_THRESHOLD_PRI:bit8;
  STALL_THRESHOLD_URG:bit7;
 end;

 TMC_HUB_WDP_GBL1=bitpacked record
  MAXBURST           :bit4;
  LAZY_TIMER         :bit4;
  STALL_THRESHOLD    :bit8;
  STALL_MODE         :bit1;
  STALL_THRESHOLD_PRI:bit8;
  STALL_THRESHOLD_URG:bit7;
 end;

 TMC_HUB_WDP_MCDS=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  STALL_MODE     :bit1;
  MAXBURST       :bit4;
  ASK_CREDITS    :bit6;
  LAZY_TIMER     :bit4;
  STALL_THRESHOLD:bit7;
  ASK_CREDITS_W  :bit7;
  RESERVED0      :bit1;
 end;

 TMC_HUB_WDP_MCDT=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  STALL_MODE     :bit1;
  MAXBURST       :bit4;
  ASK_CREDITS    :bit6;
  LAZY_TIMER     :bit4;
  STALL_THRESHOLD:bit7;
  ASK_CREDITS_W  :bit7;
  RESERVED0      :bit1;
 end;

 TMC_HUB_WDP_MCDU=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  STALL_MODE     :bit1;
  MAXBURST       :bit4;
  ASK_CREDITS    :bit6;
  LAZY_TIMER     :bit4;
  STALL_THRESHOLD:bit7;
  ASK_CREDITS_W  :bit7;
  RESERVED0      :bit1;
 end;

 TMC_HUB_WDP_MCDV=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  STALL_MODE     :bit1;
  MAXBURST       :bit4;
  ASK_CREDITS    :bit6;
  LAZY_TIMER     :bit4;
  STALL_THRESHOLD:bit7;
  ASK_CREDITS_W  :bit7;
  RESERVED0      :bit1;
 end;

 TMC_HUB_WDP_MCDW=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  STALL_MODE     :bit1;
  MAXBURST       :bit4;
  ASK_CREDITS    :bit6;
  LAZY_TIMER     :bit4;
  STALL_THRESHOLD:bit7;
  ASK_CREDITS_W  :bit7;
  RESERVED0      :bit1;
 end;

 TMC_HUB_WDP_MCDX=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  STALL_MODE     :bit1;
  MAXBURST       :bit4;
  ASK_CREDITS    :bit6;
  LAZY_TIMER     :bit4;
  STALL_THRESHOLD:bit7;
  ASK_CREDITS_W  :bit7;
  RESERVED0      :bit1;
 end;

 TMC_HUB_WDP_MCDY=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  STALL_MODE     :bit1;
  MAXBURST       :bit4;
  ASK_CREDITS    :bit6;
  LAZY_TIMER     :bit4;
  STALL_THRESHOLD:bit7;
  ASK_CREDITS_W  :bit7;
  RESERVED0      :bit1;
 end;

 TMC_HUB_WDP_MCDZ=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  STALL_MODE     :bit1;
  MAXBURST       :bit4;
  ASK_CREDITS    :bit6;
  LAZY_TIMER     :bit4;
  STALL_THRESHOLD:bit7;
  ASK_CREDITS_W  :bit7;
  RESERVED0      :bit1;
 end;

 TMC_HUB_WDP_MCIF=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_VCE0=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  VM_BYPASS                :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit13;
 end;

 TMC_HUB_WDP_VCE1=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  VM_BYPASS                :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit13;
 end;

 TMC_HUB_WDP_VIN0=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_VP8U=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_XDMA=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_MEM_POWER_LS=bitpacked record
  LS_SETUP :bit6;
  LS_HOLD  :bit6;
  RESERVED0:bit20;
 end;

 TMC_PMG_CMD_EMRS=bitpacked record
  ADR      :bit16;
  RESERVED0:bit4;
  MOP      :bit4;
  _END     :bit1;
  RESERVED1:bit7;
 end;

 TMC_PMG_CMD_MRS1=bitpacked record
  ADR      :bit16;
  RESERVED0:bit4;
  MOP      :bit4;
  _END     :bit1;
  RESERVED1:bit7;
 end;

 TMC_PMG_CMD_MRS2=bitpacked record
  ADR      :bit16;
  RESERVED0:bit4;
  MOP      :bit4;
  _END     :bit1;
  RESERVED1:bit7;
 end;

 TMC_RPB_ARB_CNTL=bitpacked record
  WR_SWITCH_NUM :bit8;
  RD_SWITCH_NUM :bit8;
  ATC_SWITCH_NUM:bit8;
  RESERVED0     :bit8;
 end;

 TMC_RPB_BIF_CNTL=bitpacked record
  ARB_SWITCH_NUM:bit8;
  XPB_SWITCH_NUM:bit8;
  RESERVED0     :bit1;
  RESERVED1     :bit15;
 end;

 TMC_RPB_EFF_CNTL=bitpacked record
  WR_LAZY_TIMER:bit8;
  RD_LAZY_TIMER:bit8;
  RESERVED0    :bit16;
 end;

 TMC_RPB_TCI_CNTL=bitpacked record
  TCI_ENABLE     :bit1;
  TCI_POLICY     :bit2;
  TCI_VOL        :bit1;
  TCI_VMID       :bit4;
  TCI_REQ_CREDITS:bit8;
  TCI_MAX_WRITES :bit8;
  TCI_MAX_READS  :bit8;
 end;

 TMC_SEQ_FIFO_CTL=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit1;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit1;
  RESERVED13:bit1;
  RESERVED14:bit2;
  RESERVED15:bit1;
  RESERVED16:bit1;
  RESERVED17:bit1;
  RESERVED18:bit1;
  RESERVED19:bit1;
  RESERVED20:bit1;
  RESERVED21:bit6;
  RESERVED22:bit1;
  RESERVED23:bit1;
  RESERVED24:bit1;
  RESERVED25:bit1;
 end;

 TMC_SEQ_STATUS_M=bitpacked record
  PWRUP_COMPL_D0         :bit1;
  PWRUP_COMPL_D1         :bit1;
  RESERVED0              :bit1;
  RESERVED1              :bit1;
  CMD_RDY_D0             :bit1;
  CMD_RDY_D1             :bit1;
  RESERVED2              :bit1;
  RESERVED3              :bit1;
  SEQ0_ARB_CMD_FIFO_EMPTY:bit1;
  SEQ1_ARB_CMD_FIFO_EMPTY:bit1;
  RESERVED4              :bit1;
  RESERVED5              :bit1;
  SEQ0_RS_DATA_FIFO_FULL :bit1;
  SEQ1_RS_DATA_FIFO_FULL :bit1;
  RESERVED6              :bit1;
  RESERVED7              :bit1;
  SEQ0_BUSY              :bit1;
  SEQ1_BUSY              :bit1;
  RESERVED8              :bit1;
  RESERVED9              :bit1;
  RESERVED10             :bit11;
  RESERVED11             :bit1;
 end;

 TMC_SEQ_STATUS_S=bitpacked record
  SEQ0_ARB_DATA_FIFO_FULL:bit1;
  SEQ1_ARB_DATA_FIFO_FULL:bit1;
  RESERVED0              :bit1;
  RESERVED1              :bit1;
  SEQ0_ARB_CMD_FIFO_FULL :bit1;
  SEQ1_ARB_CMD_FIFO_FULL :bit1;
  RESERVED2              :bit1;
  RESERVED3              :bit1;
  SEQ0_RS_DATA_FIFO_EMPTY:bit1;
  SEQ1_RS_DATA_FIFO_EMPTY:bit1;
  RESERVED4              :bit1;
  RESERVED5              :bit1;
  RESERVED6              :bit20;
 end;

 TMC_SEQ_SUP_CNTL=bitpacked record
  RUN        :bit1;
  SINGLE_STEP:bit1;
  SW_WAKE    :bit1;
  RESET_PC   :bit1;
  PGM_WRITE  :bit1;
  PGM_READ   :bit1;
  FAST_WRITE :bit1;
  BKPT_CLEAR :bit1;
  RESERVED0  :bit16;
  PGM_CHKSUM :bit8;
 end;

 TMC_SEQ_TIMER_RD=bit32;

 TMC_SEQ_TIMER_WR=bit32;

 TMC_SHARED_CHMAP=bitpacked record
  CHAN0    :bit4;
  CHAN1    :bit4;
  CHAN2    :bit4;
  NOOFCHAN :bit4;
  CHAN3    :bit4;
  CHAN4    :bit4;
  RESERVED0:bit8;
 end;

 TMC_VM_FB_OFFSET=bitpacked record
  FB_OFFSET:bit18;
  RESERVED0:bit14;
 end;

 TMC_VM_MARC_CNTL=bitpacked record
  ENABLE_ALL_CLIENTS:bit1;
  RESERVED0         :bit31;
 end;

 TMC_XBAR_TWOCHAN=bitpacked record
  DISABLE_ONEPORT:bit1;
  CH0            :bit2;
  CH1            :bit2;
  RESERVED0      :bit2;
  RESERVED1      :bit2;
  RESERVED2      :bit23;
 end;

 TMC_XPB_CLG_CFG0=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG1=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG2=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG3=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG4=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG5=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG6=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG7=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG8=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG9=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_INTF_CFG=bitpacked record
  RPB_WRREQ_CRD    :bit8;
  MC_WRRET_ASK     :bit8;
  XSP_REQ_CRD      :bit7;
  BIF_REG_SNOOP_SEL:bit1;
  BIF_REG_SNOOP_VAL:bit1;
  BIF_MEM_SNOOP_SEL:bit1;
  BIF_MEM_SNOOP_VAL:bit1;
  XSP_SNOOP_SEL    :bit2;
  XSP_SNOOP_VAL    :bit1;
  XSP_ORDERING_SEL :bit1;
  XSP_ORDERING_VAL :bit1;
 end;

 TMC_XPB_INTF_STS=bitpacked record
  RPB_WRREQ_CRD    :bit8;
  XSP_REQ_CRD      :bit7;
  HOP_DATA_BUF_FULL:bit1;
  HOP_ATTR_BUF_FULL:bit1;
  CNS_BUF_FULL     :bit1;
  CNS_BUF_BUSY     :bit1;
  RPB_RDREQ_CRD    :bit8;
  RESERVED0        :bit5;
 end;

 TMC_XPB_MISC_CFG=bitpacked record
  FIELDNAME0 :bit8;
  FIELDNAME1 :bit8;
  FIELDNAME2 :bit8;
  FIELDNAME3 :bit7;
  TRIGGERNAME:bit1;
 end;

 TMC_XPB_P2P_BAR0=bitpacked record
  HOST_FLUSH  :bit4;
  REG_SYS_BAR :bit4;
  MEM_SYS_BAR :bit4;
  VALID       :bit1;
  SEND_DIS    :bit1;
  COMPRESS_DIS:bit1;
  RESERVED    :bit1;
  ADDRESS     :bit16;
 end;

 TMC_XPB_P2P_BAR1=bitpacked record
  HOST_FLUSH  :bit4;
  REG_SYS_BAR :bit4;
  MEM_SYS_BAR :bit4;
  VALID       :bit1;
  SEND_DIS    :bit1;
  COMPRESS_DIS:bit1;
  RESERVED    :bit1;
  ADDRESS     :bit16;
 end;

 TMC_XPB_P2P_BAR2=bitpacked record
  HOST_FLUSH  :bit4;
  REG_SYS_BAR :bit4;
  MEM_SYS_BAR :bit4;
  VALID       :bit1;
  SEND_DIS    :bit1;
  COMPRESS_DIS:bit1;
  RESERVED    :bit1;
  ADDRESS     :bit16;
 end;

 TMC_XPB_P2P_BAR3=bitpacked record
  HOST_FLUSH  :bit4;
  REG_SYS_BAR :bit4;
  MEM_SYS_BAR :bit4;
  VALID       :bit1;
  SEND_DIS    :bit1;
  COMPRESS_DIS:bit1;
  RESERVED    :bit1;
  ADDRESS     :bit16;
 end;

 TMC_XPB_P2P_BAR4=bitpacked record
  HOST_FLUSH  :bit4;
  REG_SYS_BAR :bit4;
  MEM_SYS_BAR :bit4;
  VALID       :bit1;
  SEND_DIS    :bit1;
  COMPRESS_DIS:bit1;
  RESERVED    :bit1;
  ADDRESS     :bit16;
 end;

 TMC_XPB_P2P_BAR5=bitpacked record
  HOST_FLUSH  :bit4;
  REG_SYS_BAR :bit4;
  MEM_SYS_BAR :bit4;
  VALID       :bit1;
  SEND_DIS    :bit1;
  COMPRESS_DIS:bit1;
  RESERVED    :bit1;
  ADDRESS     :bit16;
 end;

 TMC_XPB_P2P_BAR6=bitpacked record
  HOST_FLUSH  :bit4;
  REG_SYS_BAR :bit4;
  MEM_SYS_BAR :bit4;
  VALID       :bit1;
  SEND_DIS    :bit1;
  COMPRESS_DIS:bit1;
  RESERVED    :bit1;
  ADDRESS     :bit16;
 end;

 TMC_XPB_P2P_BAR7=bitpacked record
  HOST_FLUSH  :bit4;
  REG_SYS_BAR :bit4;
  MEM_SYS_BAR :bit4;
  VALID       :bit1;
  SEND_DIS    :bit1;
  COMPRESS_DIS:bit1;
  RESERVED    :bit1;
  ADDRESS     :bit16;
 end;

 TMC_XPB_PIPE_STS=bitpacked record
  WCB_ANY_PBUF           :bit1;
  WCB_HST_DATA_BUF_CNT   :bit7;
  WCB_SID_DATA_BUF_CNT   :bit7;
  WCB_HST_RD_PTR_BUF_FULL:bit1;
  WCB_SID_RD_PTR_BUF_FULL:bit1;
  WCB_HST_REQ_FIFO_FULL  :bit1;
  WCB_SID_REQ_FIFO_FULL  :bit1;
  WCB_HST_REQ_OBUF_FULL  :bit1;
  WCB_SID_REQ_OBUF_FULL  :bit1;
  WCB_HST_DATA_OBUF_FULL :bit1;
  WCB_SID_DATA_OBUF_FULL :bit1;
  RET_BUF_FULL           :bit1;
  XPB_CLK_BUSY_BITS      :bit8;
 end;

 TMC_XPB_SUB_CTRL=bitpacked record
  WRREQ_BYPASS_XPB      :bit1;
  STALL_CNS_RTR_REQ     :bit1;
  STALL_RTR_RPB_WRREQ   :bit1;
  STALL_RTR_MAP_REQ     :bit1;
  STALL_MAP_WCB_REQ     :bit1;
  STALL_WCB_SID_REQ     :bit1;
  STALL_MC_XSP_REQ_SEND :bit1;
  STALL_WCB_HST_REQ     :bit1;
  STALL_HST_HOP_REQ     :bit1;
  STALL_XPB_RPB_REQ_ATTR:bit1;
  RESET_CNS             :bit1;
  RESET_RTR             :bit1;
  RESET_RET             :bit1;
  RESET_MAP             :bit1;
  RESET_WCB             :bit1;
  RESET_HST             :bit1;
  RESET_HOP             :bit1;
  RESET_SID             :bit1;
  RESET_SRB             :bit1;
  RESET_CGR             :bit1;
  RESERVED0             :bit12;
 end;

 TMM_CFGREGS_CNTL=bitpacked record
  MM_CFG_FUNC_SEL:bit3;
  MM_WR_TO_CFG_EN:bit1;
  RESERVED0      :bit28;
 end;

 TMSI_MSG_ADDR_HI=bit32;

 TMSI_MSG_ADDR_LO=bitpacked record
  RESERVED0      :bit2;
  MSI_MSG_ADDR_LO:bit30;
 end;

 TMSI_MSG_DATA_64=bitpacked record
  MSI_DATA_64:bit16;
  RESERVED0  :bit16;
 end;

 TMVP_BLACK_KEYER=bitpacked record
  MVP_BLACK_KEYER_R:bit10;
  MVP_BLACK_KEYER_G:bit10;
  MVP_BLACK_KEYER_B:bit10;
  RESERVED0        :bit2;
 end;

 TMVP_FIFO_STATUS=bitpacked record
  MVP_FIFO_LEVEL             :bit8;
  MVP_FIFO_OVERFLOW          :bit1;
  RESERVED0                  :bit3;
  MVP_FIFO_OVERFLOW_OCCURRED :bit1;
  RESERVED1                  :bit3;
  MVP_FIFO_OVERFLOW_ACK      :bit1;
  RESERVED2                  :bit3;
  MVP_FIFO_UNDERFLOW         :bit1;
  RESERVED3                  :bit3;
  MVP_FIFO_UNDERFLOW_OCCURRED:bit1;
  RESERVED4                  :bit3;
  MVP_FIFO_UNDERFLOW_ACK     :bit1;
  RESERVED5                  :bit1;
  MVP_FIFO_ERROR_MASK        :bit1;
  MVP_FIFO_ERROR_INT_STATUS  :bit1;
 end;

 TOVL_DFQ_CONTROL=bitpacked record
  OVL_DFQ_RESET           :bit1;
  RESERVED0               :bit3;
  OVL_DFQ_SIZE            :bit3;
  RESERVED1               :bit1;
  OVL_DFQ_MIN_FREE_ENTRIES:bit3;
  RESERVED2               :bit21;
 end;

 TPA_CL_CLIP_CNTL=bitpacked record
  UCP_ENA_0                :bit1;
  UCP_ENA_1                :bit1;
  UCP_ENA_2                :bit1;
  UCP_ENA_3                :bit1;
  UCP_ENA_4                :bit1;
  UCP_ENA_5                :bit1;
  RESERVED0                :bit7;
  PS_UCP_Y_SCALE_NEG       :bit1;
  PS_UCP_MODE              :bit2;
  CLIP_DISABLE             :bit1;
  UCP_CULL_ONLY_ENA        :bit1;
  BOUNDARY_EDGE_FLAG_ENA   :bit1;
  DX_CLIP_SPACE_DEF        :bit1;
  DIS_CLIP_ERR_DETECT      :bit1;
  VTX_KILL_OR              :bit1;
  DX_RASTERIZATION_KILL    :bit1;
  RESERVED1                :bit1;
  DX_LINEAR_ATTR_CLIP_ENA  :bit1;
  VTE_VPORT_PROVOKE_DISABLE:bit1;
  ZCLIP_NEAR_DISABLE       :bit1;
  ZCLIP_FAR_DISABLE        :bit1;
  RESERVED2                :bit4;
 end;

 TPA_SC_AA_CONFIG=bitpacked record
  MSAA_NUM_SAMPLES      :bit3;
  RESERVED0             :bit1;
  AA_MASK_CENTROID_DTMN :bit1;
  RESERVED1             :bit8;
  MAX_SAMPLE_DIST       :bit4;
  RESERVED2             :bit3;
  MSAA_EXPOSED_SAMPLES  :bit3;
  RESERVED3             :bit1;
  DETAIL_TO_EXPOSED_MODE:bit2;
  RESERVED4             :bit6;
 end;

 TPA_SC_FIFO_SIZE=bitpacked record
  SC_FRONTEND_PRIM_FIFO_SIZE:bit6;
  SC_BACKEND_PRIM_FIFO_SIZE :bit9;
  SC_HIZ_TILE_FIFO_SIZE     :bit6;
  RESERVED0                 :bit2;
  SC_EARLYZ_TILE_FIFO_SIZE  :bit9;
 end;

 TPA_SC_LINE_CNTL=bitpacked record
  RESERVED0               :bit9;
  EXPAND_LINE_WIDTH       :bit1;
  LAST_PIXEL              :bit1;
  PERPENDICULAR_ENDCAP_ENA:bit1;
  DX10_DIAMOND_TEST_ENA   :bit1;
  RESERVED1               :bit19;
 end;

 TPA_SU_LINE_CNTL=bitpacked record
  WIDTH    :bit16;
  RESERVED0:bit16;
 end;

 TPB0_PIF_RX_CTRL=bitpacked record
  RXPWR_IN_S2             :bit3;
  RXPWR_IN_SPDCHNG        :bit3;
  RXPWR_IN_OFF            :bit3;
  RXPWR_IN_DEGRADE        :bit3;
  RXPWR_IN_UNUSED         :bit3;
  RXPWR_IN_INIT           :bit3;
  RXPWR_IN_PLL_OFF        :bit3;
  RXPWR_IN_DEGRADE_MODE   :bit1;
  RXPWR_IN_UNUSED_MODE    :bit1;
  RXPWR_GATING_IN_L1      :bit1;
  RXPWR_GATING_IN_UNUSED  :bit1;
  RX_HLD_EIE_COUNT        :bit1;
  RX_EI_DET_IN_PS2_DEGRADE:bit1;
  RESERVED0               :bit5;
 end;

 TPB0_PIF_SCRATCH=bit32;

 TPB0_PIF_STRAP_0=bitpacked record
  RESERVED0                  :bit1;
  STRAP_TX_RDY_XTND_DIS      :bit1;
  STRAP_RX_RDY_XTND_DIS      :bit1;
  STRAP_TX_STATUS_XTND_DIS   :bit1;
  STRAP_RX_STATUS_XTND_DIS   :bit1;
  STRAP_FORCE_OWN_MSTR       :bit1;
  STRAP_PIF_CDR_EN_MODE      :bit2;
  STRAP_RX_EI_FILTER         :bit2;
  STRAP_RX_DIS_HLD_EIE_IN_PS1:bit1;
  STRAP_RX_DIS_HLD_EIE_IN_PS2:bit1;
  STRAP_PIF_BIT_12           :bit1;
  STRAP_PIF_BIT_13           :bit1;
  STRAP_PIF_BIT_14           :bit1;
  STRAP_PIF_BIT_15           :bit1;
  STRAP_PIF_BIT_16           :bit1;
  RESERVED1                  :bit15;
 end;

 TPB0_PIF_TX_CTRL=bitpacked record
  TXPWR_IN_S2          :bit3;
  TXPWR_IN_SPDCHNG     :bit3;
  TXPWR_IN_OFF         :bit3;
  TXPWR_IN_DEGRADE     :bit3;
  TXPWR_IN_UNUSED      :bit3;
  TXPWR_IN_INIT        :bit3;
  TXPWR_IN_PLL_OFF     :bit3;
  TXPWR_IN_DEGRADE_MODE:bit1;
  TXPWR_IN_UNUSED_MODE :bit1;
  RESERVED0            :bit1;
  RESERVED1            :bit1;
  RESERVED2            :bit7;
 end;

 TPB1_PIF_RX_CTRL=bitpacked record
  RXPWR_IN_S2             :bit3;
  RXPWR_IN_SPDCHNG        :bit3;
  RXPWR_IN_OFF            :bit3;
  RXPWR_IN_DEGRADE        :bit3;
  RXPWR_IN_UNUSED         :bit3;
  RXPWR_IN_INIT           :bit3;
  RXPWR_IN_PLL_OFF        :bit3;
  RXPWR_IN_DEGRADE_MODE   :bit1;
  RXPWR_IN_UNUSED_MODE    :bit1;
  RXPWR_GATING_IN_L1      :bit1;
  RXPWR_GATING_IN_UNUSED  :bit1;
  RX_HLD_EIE_COUNT        :bit1;
  RX_EI_DET_IN_PS2_DEGRADE:bit1;
  RESERVED0               :bit5;
 end;

 TPB1_PIF_SCRATCH=bit32;

 TPB1_PIF_STRAP_0=bitpacked record
  RESERVED0                  :bit1;
  STRAP_TX_RDY_XTND_DIS      :bit1;
  STRAP_RX_RDY_XTND_DIS      :bit1;
  STRAP_TX_STATUS_XTND_DIS   :bit1;
  STRAP_RX_STATUS_XTND_DIS   :bit1;
  STRAP_FORCE_OWN_MSTR       :bit1;
  STRAP_PIF_CDR_EN_MODE      :bit2;
  STRAP_RX_EI_FILTER         :bit2;
  STRAP_RX_DIS_HLD_EIE_IN_PS1:bit1;
  STRAP_RX_DIS_HLD_EIE_IN_PS2:bit1;
  STRAP_PIF_BIT_12           :bit1;
  STRAP_PIF_BIT_13           :bit1;
  STRAP_PIF_BIT_14           :bit1;
  STRAP_PIF_BIT_15           :bit1;
  STRAP_PIF_BIT_16           :bit1;
  RESERVED1                  :bit15;
 end;

 TPB1_PIF_TX_CTRL=bitpacked record
  TXPWR_IN_S2          :bit3;
  TXPWR_IN_SPDCHNG     :bit3;
  TXPWR_IN_OFF         :bit3;
  TXPWR_IN_DEGRADE     :bit3;
  TXPWR_IN_UNUSED      :bit3;
  TXPWR_IN_INIT        :bit3;
  TXPWR_IN_PLL_OFF     :bit3;
  TXPWR_IN_DEGRADE_MODE:bit1;
  TXPWR_IN_UNUSED_MODE :bit1;
  RESERVED0            :bit1;
  RESERVED1            :bit1;
  RESERVED2            :bit7;
 end;

 TPCIEP_PORT_CNTL=bitpacked record
  SLV_PORT_REQ_EN                :bit1;
  CI_SNOOP_OVERRIDE              :bit1;
  HOTPLUG_MSG_EN                 :bit1;
  NATIVE_PME_EN                  :bit1;
  PWR_FAULT_EN                   :bit1;
  PMI_BM_DIS                     :bit1;
  SEQNUM_DEBUG_MODE              :bit1;
  RESERVED0                      :bit1;
  CI_SLV_CPL_STATIC_ALLOC_LIMIT_S:bit7;
  RESERVED1                      :bit1;
  CI_MAX_CPL_PAYLOAD_SIZE_MODE   :bit2;
  CI_PRIV_MAX_CPL_PAYLOAD_SIZE   :bit3;
  RESERVED2                      :bit11;
 end;

 TPCIE_DEBUG_CNTL=bitpacked record
  DEBUG_PORT_EN:bit8;
  DEBUG_SELECT :bit1;
  RESERVED0    :bit7;
  DEBUG_LANE_EN:bit16;
 end;

 TPCIE_DPA_STATUS=bitpacked record
  SUBSTATE_STATUS      :bit5;
  RESERVED0            :bit3;
  SUBSTATE_CNTL_ENABLED:bit1;
  RESERVED1            :bit23;
 end;

 TPCIE_F0_DPA_CAP=bitpacked record
  RESERVED0      :bit8;
  TRANS_LAT_UNIT :bit2;
  RESERVED1      :bit2;
  PWR_ALLOC_SCALE:bit2;
  RESERVED2      :bit2;
  TRANS_LAT_VAL_0:bit8;
  TRANS_LAT_VAL_1:bit8;
 end;

 TPCIE_INT_STATUS=bitpacked record
  CORR_ERR_INT_STATUS       :bit1;
  NON_FATAL_ERR_INT_STATUS  :bit1;
  FATAL_ERR_INT_STATUS      :bit1;
  USR_DETECTED_INT_STATUS   :bit1;
  MISC_ERR_INT_STATUS       :bit1;
  RESERVED0                 :bit1;
  POWER_STATE_CHG_INT_STATUS:bit1;
  LINK_BW_INT_STATUS        :bit1;
  QUIESCE_RCVD_INT_STATUS   :bit1;
  RESERVED1                 :bit23;
 end;

 TPCIE_LC_STATE10=bitpacked record
  LC_PREV_STATE40:bit6;
  RESERVED0      :bit2;
  LC_PREV_STATE41:bit6;
  RESERVED1      :bit2;
  LC_PREV_STATE42:bit6;
  RESERVED2      :bit2;
  LC_PREV_STATE43:bit6;
  RESERVED3      :bit2;
 end;

 TPCIE_LC_STATE11=bitpacked record
  LC_PREV_STATE44:bit6;
  RESERVED0      :bit2;
  LC_PREV_STATE45:bit6;
  RESERVED1      :bit2;
  LC_PREV_STATE46:bit6;
  RESERVED2      :bit2;
  LC_PREV_STATE47:bit6;
  RESERVED3      :bit2;
 end;

 TPCIE_LC_STATUS1=bitpacked record
  LC_REVERSE_RCVR        :bit1;
  LC_REVERSE_XMIT        :bit1;
  LC_OPERATING_LINK_WIDTH:bit3;
  LC_DETECTED_LINK_WIDTH :bit3;
  RESERVED0              :bit24;
 end;

 TPCIE_LC_STATUS2=bitpacked record
  LC_TOTAL_INACTIVE_LANES:bit16;
  LC_TURN_ON_LANE        :bit16;
 end;

 TPCIE_LINK_CNTL3=bitpacked record
  PERFORM_EQUALIZATION        :bit1;
  LINK_EQUALIZATION_REQ_INT_EN:bit1;
  RESERVED0                   :bit30;
 end;

 TPCIE_PASID_CNTL=bitpacked record
  PASID_ENABLE                    :bit1;
  PASID_EXE_PERMISSION_ENABLE     :bit1;
  PASID_PRIV_MODE_SUPPORTED_ENABLE:bit1;
  RESERVED0                       :bit29;
 end;

 TPCIE_PORT_INDEX=bitpacked record
  PCIE_INDEX:bit8;
  RESERVED0 :bit24;
 end;

 TPCIE_RX_NUM_NAK=bit32;

 TPCIE_STRAP_MISC=bitpacked record
  STRAP_LINK_CONFIG                      :bit4;
  STRAP_TL_ALT_BUF_EN                    :bit1;
  RESERVED0                              :bit1;
  RESERVED1                              :bit1;
  RESERVED2                              :bit1;
  STRAP_MAX_PASID_WIDTH                  :bit5;
  STRAP_PASID_EXE_PERMISSION_SUPPORTED   :bit1;
  STRAP_PASID_PRIV_MODE_SUPPORTED        :bit1;
  STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED:bit1;
  RESERVED3                              :bit8;
  STRAP_CLK_PM_EN                        :bit1;
  STRAP_ECN1P1_EN                        :bit1;
  STRAP_EXT_VC_COUNT                     :bit1;
  RESERVED4                              :bit1;
  STRAP_REVERSE_ALL                      :bit1;
  STRAP_MST_ADR64_EN                     :bit1;
  STRAP_FLR_EN                           :bit1;
  STRAP_INTERNAL_ERR_EN                  :bit1;
 end;

 TPEER_REG_RANGE0=bitpacked record
  START_ADDR:bit16;
  END_ADDR  :bit16;
 end;

 TPEER_REG_RANGE1=bitpacked record
  START_ADDR:bit16;
  END_ADDR  :bit16;
 end;

 TPIPE0_PG_CONFIG=bitpacked record
  PIPE0_POWER_FORCEON:bit1;
  RESERVED0          :bit31;
 end;

 TPIPE0_PG_ENABLE=bitpacked record
  PIPE0_POWER_GATE:bit1;
  RESERVED0       :bit31;
 end;

 TPIPE0_PG_STATUS=bitpacked record
  PIPE0_PGFSM_READ_DATA    :bit24;
  PIPE0_DEBUG_PWR_STATUS   :bit2;
  RESERVED0                :bit2;
  PIPE0_DESIRED_PWR_STATE  :bit1;
  PIPE0_REQUESTED_PWR_STATE:bit1;
  PIPE0_PGFSM_PWR_STATUS   :bit2;
 end;

 TPIPE1_PG_CONFIG=bitpacked record
  PIPE1_POWER_FORCEON:bit1;
  RESERVED0          :bit31;
 end;

 TPIPE1_PG_ENABLE=bitpacked record
  PIPE1_POWER_GATE:bit1;
  RESERVED0       :bit31;
 end;

 TPIPE1_PG_STATUS=bitpacked record
  PIPE1_PGFSM_READ_DATA    :bit24;
  PIPE1_DEBUG_PWR_STATUS   :bit2;
  RESERVED0                :bit2;
  PIPE1_DESIRED_PWR_STATE  :bit1;
  PIPE1_REQUESTED_PWR_STATE:bit1;
  PIPE1_PGFSM_PWR_STATUS   :bit2;
 end;

 TPIPE2_PG_CONFIG=bitpacked record
  PIPE2_POWER_FORCEON:bit1;
  RESERVED0          :bit31;
 end;

 TPIPE2_PG_ENABLE=bitpacked record
  PIPE2_POWER_GATE:bit1;
  RESERVED0       :bit31;
 end;

 TPIPE2_PG_STATUS=bitpacked record
  PIPE2_PGFSM_READ_DATA    :bit24;
  PIPE2_DEBUG_PWR_STATUS   :bit2;
  RESERVED0                :bit2;
  PIPE2_DESIRED_PWR_STATE  :bit1;
  PIPE2_REQUESTED_PWR_STATE:bit1;
  PIPE2_PGFSM_PWR_STATUS   :bit2;
 end;

 TPIPE3_PG_CONFIG=bitpacked record
  PIPE3_POWER_FORCEON:bit1;
  RESERVED0          :bit31;
 end;

 TPIPE3_PG_ENABLE=bitpacked record
  PIPE3_POWER_GATE:bit1;
  RESERVED0       :bit31;
 end;

 TPIPE3_PG_STATUS=bitpacked record
  PIPE3_PGFSM_READ_DATA    :bit24;
  PIPE3_DEBUG_PWR_STATUS   :bit2;
  RESERVED0                :bit2;
  PIPE3_DESIRED_PWR_STATE  :bit1;
  PIPE3_REQUESTED_PWR_STATE:bit1;
  PIPE3_PGFSM_PWR_STATUS   :bit2;
 end;

 TPIPE4_PG_CONFIG=bitpacked record
  PIPE4_POWER_FORCEON:bit1;
  RESERVED0          :bit31;
 end;

 TPIPE4_PG_ENABLE=bitpacked record
  PIPE4_POWER_GATE:bit1;
  RESERVED0       :bit31;
 end;

 TPIPE4_PG_STATUS=bitpacked record
  PIPE4_PGFSM_READ_DATA    :bit24;
  PIPE4_DEBUG_PWR_STATUS   :bit2;
  RESERVED0                :bit2;
  PIPE4_DESIRED_PWR_STATE  :bit1;
  PIPE4_REQUESTED_PWR_STATE:bit1;
  PIPE4_PGFSM_PWR_STATUS   :bit2;
 end;

 TPIPE5_PG_CONFIG=bitpacked record
  PIPE5_POWER_FORCEON:bit1;
  RESERVED0          :bit31;
 end;

 TPIPE5_PG_ENABLE=bitpacked record
  PIPE5_POWER_GATE:bit1;
  RESERVED0       :bit31;
 end;

 TPIPE5_PG_STATUS=bitpacked record
  PIPE5_PGFSM_READ_DATA    :bit24;
  PIPE5_DEBUG_PWR_STATUS   :bit2;
  RESERVED0                :bit2;
  PIPE5_DESIRED_PWR_STATE  :bit1;
  PIPE5_REQUESTED_PWR_STATE:bit1;
  PIPE5_PGFSM_PWR_STATUS   :bit2;
 end;

 TPLL_ANALOG_CNTL=bitpacked record
  PLL_ANALOG_TEST_EN    :bit1;
  PLL_ANALOG_MUX_CNTL   :bit4;
  PLL_ANALOGOUT_MUX_CNTL:bit4;
  PLL_REGREF_TRIM       :bit5;
  PLL_CALIB_FBDIV       :bit3;
  PLL_CALIB_FASTCAL     :bit1;
  PLL_TEST_SSAMP_EN     :bit1;
  RESERVED0             :bit13;
 end;

 TPLL_UPDATE_CNTL=bitpacked record
  PLL_UPDATE_PENDING    :bit1;
  RESERVED0             :bit7;
  PLL_UPDATE_POINT      :bit1;
  RESERVED1             :bit7;
  PLL_AUTO_RESET_DISABLE:bit1;
  RESERVED2             :bit15;
 end;

 TPLL_UPDATE_LOCK=bitpacked record
  PLL_UPDATE_LOCK:bit1;
  RESERVED0      :bit31;
 end;

 TPMI_STATUS_CNTL=bitpacked record
  POWER_STATE  :bit2;
  RESERVED0    :bit1;
  NO_SOFT_RESET:bit1;
  RESERVED1    :bit4;
  PME_EN       :bit1;
  DATA_SELECT  :bit4;
  DATA_SCALE   :bit2;
  PME_STATUS   :bit1;
  RESERVED2    :bit6;
  B2_B3_SUPPORT:bit1;
  BUS_PWR_EN   :bit1;
  PMI_DATA     :bit8;
 end;

 TPWR_PCC_CONTROL=bitpacked record
  PCC_POLARITY:bit1;
  RESERVED0   :bit31;
 end;

 TREGAMMA_CONTROL=bitpacked record
  GRPH_REGAMMA_MODE:bit3;
  RESERVED0        :bit1;
  OVL_REGAMMA_MODE :bit3;
  RESERVED1        :bit25;
 end;

 TRLC_CSIB_LENGTH=bit32;

 TRLC_LB_CNTR_MAX=bit32;

 TRLC_SMU_COMMAND=bit32;

 TRLC_SMU_MESSAGE=bit32;

 TRLC_SMU_PG_CTRL=bitpacked record
  START_PG:bit1;
  SPARE   :bit31;
 end;

 TSCL_ALU_CONTROL=bitpacked record
  SCL_ALU_DISABLE:bit1;
  RESERVED0      :bit31;
 end;

 TSCL_TAP_CONTROL=bitpacked record
  SCL_V_NUM_OF_TAPS:bit3;
  RESERVED0        :bit5;
  SCL_H_NUM_OF_TAPS:bit4;
  RESERVED1        :bit20;
 end;

 TSDMA0_VF_ENABLE=bitpacked record
  VF_ENABLE:bit1;
  RESERVED0:bit31;
 end;

 TSDMA0_VM_CTX_HI=bit32;

 TSDMA0_VM_CTX_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA1_VF_ENABLE=bitpacked record
  VF_ENABLE:bit1;
  RESERVED0:bit31;
 end;

 TSDMA1_VM_CTX_HI=bit32;

 TSDMA1_VM_CTX_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA_PGFSM_READ=bitpacked record
  VALUE    :bit24;
  RESERVED0:bit8;
 end;

 TSEM_MCIF_CONFIG=bitpacked record
  MC_REQ_SWAP    :bit2;
  MC_WRREQ_CREDIT:bit6;
  MC_RDREQ_CREDIT:bit6;
  RESERVED0      :bit18;
 end;

 TSMBCLK_PAD_CNTL=bitpacked record
  SMBCLK_PAD_A      :bit1;
  SMBCLK_PAD_SEL    :bit1;
  SMBCLK_PAD_MODE   :bit1;
  SMBCLK_PAD_SPARE  :bit2;
  SMBCLK_PAD_SN0    :bit1;
  SMBCLK_PAD_SN1    :bit1;
  SMBCLK_PAD_SN2    :bit1;
  SMBCLK_PAD_SN3    :bit1;
  SMBCLK_PAD_SLEW   :bit1;
  SMBCLK_PAD_WAKE   :bit1;
  SMBCLK_PAD_SCHMEN :bit1;
  SMBCLK_PAD_CNTL_EN:bit1;
  RESERVED0         :bit19;
 end;

 TSMBDAT_PAD_CNTL=bitpacked record
  SMBDAT_PAD_A      :bit1;
  SMBDAT_PAD_SEL    :bit1;
  SMBDAT_PAD_MODE   :bit1;
  SMBDAT_PAD_SPARE  :bit2;
  SMBDAT_PAD_SN0    :bit1;
  SMBDAT_PAD_SN1    :bit1;
  SMBDAT_PAD_SN2    :bit1;
  SMBDAT_PAD_SN3    :bit1;
  SMBDAT_PAD_SLEW   :bit1;
  SMBDAT_PAD_WAKE   :bit1;
  SMBDAT_PAD_SCHMEN :bit1;
  SMBDAT_PAD_CNTL_EN:bit1;
  RESERVED0         :bit19;
 end;

 TSMC_IND_INDEX_0=bit32;

 TSMC_IND_INDEX_1=bit32;

 TSMC_IND_INDEX_2=bit32;

 TSMC_IND_INDEX_3=bit32;

 TSMC_IND_INDEX_4=bit32;

 TSMC_IND_INDEX_5=bit32;

 TSMC_IND_INDEX_6=bit32;

 TSMC_IND_INDEX_7=bit32;

 TSMU_IND_INDEX_0=bit32;

 TSMU_IND_INDEX_1=bit32;

 TSMU_IND_INDEX_2=bit32;

 TSMU_IND_INDEX_3=bit32;

 TSMU_IND_INDEX_4=bit32;

 TSMU_IND_INDEX_5=bit32;

 TSMU_IND_INDEX_6=bit32;

 TSMU_IND_INDEX_7=bit32;

 TSMU_PM_STATUS_0=bit32;

 TSMU_PM_STATUS_1=bit32;

 TSMU_PM_STATUS_2=bit32;

 TSMU_PM_STATUS_3=bit32;

 TSMU_PM_STATUS_4=bit32;

 TSMU_PM_STATUS_5=bit32;

 TSMU_PM_STATUS_6=bit32;

 TSMU_PM_STATUS_7=bit32;

 TSMU_PM_STATUS_8=bit32;

 TSMU_PM_STATUS_9=bit32;

 TSPI_CONFIG_CNTL=bitpacked record
  GPR_WRITE_PRIORITY   :bit21;
  EXP_PRIORITY_ORDER   :bit3;
  ENABLE_SQG_TOP_EVENTS:bit1;
  ENABLE_SQG_BOP_EVENTS:bit1;
  RSRC_MGMT_RESET      :bit1;
  TTRACE_STALL_ALL     :bit1;
  RESERVED0            :bit4;
 end;

 TSPI_GDBG_TBA_HI=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_GDBG_TBA_LO=bit32;

 TSPI_GDBG_TMA_HI=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_GDBG_TMA_LO=bit32;

 TSPI_GDS_CREDITS=bitpacked record
  DS_DATA_CREDITS:bit8;
  DS_CMD_CREDITS :bit8;
  UNUSED         :bit16;
 end;

 TSPI_LB_CTR_CTRL=bitpacked record
  LOAD     :bit1;
  RESERVED0:bit31;
 end;

 TSPI_LB_DATA_REG=bit32;

 TSPI_RESET_DEBUG=bitpacked record
  DISABLE_GFX_RESET         :bit1;
  DISABLE_GFX_RESET_PER_VMID:bit1;
  DISABLE_GFX_RESET_ALL_VMID:bit1;
  DISABLE_GFX_RESET_RESOURCE:bit1;
  DISABLE_GFX_RESET_PRIORITY:bit1;
  RESERVED0                 :bit27;
 end;

 TSPI_START_PHASE=bitpacked record
  VGPR_START_PHASE:bit2;
  SGPR_START_PHASE:bit2;
  WAVE_START_PHASE:bit2;
  RESERVED0       :bit26;
 end;

 TSPMI_C6_STATE_0=bitpacked record
  SPMI_IF_C6_STATE_ENTERED              :bit1;
  SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY:bit1;
  SPMI_IF_COUNTER_ADDRESS_C6            :bit15;
  RESERVED0                             :bit15;
 end;

 TSPMI_FSM_BUSY_0=bitpacked record
  FSM_BUSY :bit1;
  RESERVED0:bit31;
 end;

 TSPU_PORT_STATUS=bit32;

 TSQC_GATCL1_CNTL=bitpacked record
  RESERVED                     :bit18;
  DCACHE_INVALIDATE_ALL_VMID   :bit1;
  DCACHE_FORCE_MISS            :bit1;
  DCACHE_FORCE_IN_ORDER        :bit1;
  DCACHE_REDUCE_FIFO_DEPTH_BY_2:bit2;
  DCACHE_REDUCE_CACHE_SIZE_BY_2:bit2;
  ICACHE_INVALIDATE_ALL_VMID   :bit1;
  ICACHE_FORCE_MISS            :bit1;
  ICACHE_FORCE_IN_ORDER        :bit1;
  ICACHE_REDUCE_FIFO_DEPTH_BY_2:bit2;
  ICACHE_REDUCE_CACHE_SIZE_BY_2:bit2;
 end;

 TSQ_ALU_CLK_CTRL=bitpacked record
  FORCE_CU_ON_SH0:bit16;
  FORCE_CU_ON_SH1:bit16;
 end;

 TSQ_HV_VMID_CTRL=bitpacked record
  DEFAULT_VMID     :bit4;
  ALLOWED_VMID_MASK:bit16;
  RESERVED0        :bit12;
 end;

 TSQ_LDS_CLK_CTRL=bitpacked record
  FORCE_CU_ON_SH0:bit16;
  FORCE_CU_ON_SH1:bit16;
 end;

 TSQ_TEX_CLK_CTRL=bitpacked record
  FORCE_CU_ON_SH0:bit16;
  FORCE_CU_ON_SH1:bit16;
 end;

 TSQ_WAVE_EXEC_HI=bit32;

 TSQ_WAVE_EXEC_LO=bit32;

 TSQ_WAVE_IB_DBG0=bitpacked record
  IBUF_ST         :bit3;
  PC_INVALID      :bit1;
  NEED_NEXT_DW    :bit1;
  NO_PREFETCH_CNT :bit3;
  IBUF_RPTR       :bit2;
  IBUF_WPTR       :bit2;
  RESERVED0       :bit4;
  INST_STR_ST     :bit4;
  MISC_CNT        :bit4;
  ECC_ST          :bit2;
  IS_HYB          :bit1;
  HYB_CNT         :bit2;
  KILL            :bit1;
  NEED_KILL_IFETCH:bit1;
  RESERVED1       :bit1;
 end;

 TSQ_WAVE_IB_DBG1=bitpacked record
  IXNACK       :bit1;
  XNACK        :bit1;
  TA_NEED_RESET:bit1;
  RESERVED0    :bit1;
  XCNT         :bit4;
  QCNT         :bit4;
  RESERVED1    :bit20;
 end;

 TSQ_WAVE_TRAPSTS=bitpacked record
  EXCP      :bit9;
  RESERVED0 :bit1;
  SAVECTX   :bit1;
  RESERVED1 :bit5;
  EXCP_CYCLE:bit6;
  RESERVED2 :bit7;
  DP_RATE   :bit3;
 end;

 TSRBM_DEBUG_CNTL=bitpacked record
  SRBM_DEBUG_INDEX:bit6;
  RESERVED0       :bit26;
 end;

 TSRBM_DEBUG_DATA=bit32;

 TSRBM_INT_STATUS=bitpacked record
  RDERR_INT_STAT:bit1;
  RAERR_INT_STAT:bit1;
  RESERVED0     :bit30;
 end;

 TSRBM_READ_ERROR=bitpacked record
  RESERVED0            :bit2;
  READ_ADDRESS         :bit16;
  READ_REQUESTER_SDMA3 :bit1;
  READ_REQUESTER_SDMA2 :bit1;
  READ_REQUESTER_VCE0  :bit1;
  READ_REQUESTER_SDMA1 :bit1;
  READ_REQUESTER_TST   :bit1;
  READ_REQUESTER_SAMMSP:bit1;
  READ_REQUESTER_HI    :bit1;
  READ_REQUESTER_GRBM  :bit1;
  READ_REQUESTER_SMU   :bit1;
  READ_REQUESTER_SAMSCP:bit1;
  READ_REQUESTER_SDMA  :bit1;
  READ_REQUESTER_UVD   :bit1;
  RESERVED1            :bit1;
  READ_ERROR           :bit1;
 end;

 TSRBM_SOFT_RESET=bitpacked record
  SOFT_RESET_ATCL2 :bit1;
  SOFT_RESET_BIF   :bit1;
  SOFT_RESET_SDMA3 :bit1;
  SOFT_RESET_SDMA2 :bit1;
  SOFT_RESET_GIONB :bit1;
  SOFT_RESET_DC    :bit1;
  SOFT_RESET_SDMA1 :bit1;
  RESERVED0        :bit1;
  SOFT_RESET_GRBM  :bit1;
  SOFT_RESET_HDP   :bit1;
  SOFT_RESET_IH    :bit1;
  SOFT_RESET_MC    :bit1;
  SOFT_RESET_CHUB  :bit1;
  SOFT_RESET_ESRAM :bit1;
  SOFT_RESET_ROM   :bit1;
  SOFT_RESET_SEM   :bit1;
  SOFT_RESET_SMU   :bit1;
  SOFT_RESET_VMC   :bit1;
  SOFT_RESET_UVD   :bit1;
  SOFT_RESET_VP8   :bit1;
  SOFT_RESET_SDMA  :bit1;
  SOFT_RESET_TST   :bit1;
  SOFT_RESET_REGBB :bit1;
  SOFT_RESET_ODE   :bit1;
  SOFT_RESET_VCE0  :bit1;
  SOFT_RESET_XDMA  :bit1;
  SOFT_RESET_ACP   :bit1;
  SOFT_RESET_SAMMSP:bit1;
  SOFT_RESET_SAMSCP:bit1;
  SOFT_RESET_GRN   :bit1;
  SOFT_RESET_ISP   :bit1;
  SOFT_RESET_VCE1  :bit1;
 end;

 TSWRST_COMMAND_0=bitpacked record
  RESERVED0          :bit15;
  BIF_STRAPREG_RESET :bit1;
  BIF0_GLOBAL_RESET  :bit1;
  BIF0_CALIB_RESET   :bit1;
  BIF0_CORE_RESET    :bit1;
  BIF0_REGISTER_RESET:bit1;
  BIF0_PHY_RESET     :bit1;
  BIF0_STICKY_RESET  :bit1;
  BIF0_CONFIG_RESET  :bit1;
  RESERVED1          :bit9;
 end;

 TSWRST_COMMAND_1=bitpacked record
  SWITCHCLK    :bit1;
  RESERVED0    :bit1;
  RESETLANEMUX :bit1;
  RESETWRAPREGS:bit1;
  RESETSRBM0   :bit1;
  RESETSRBM1   :bit1;
  RESETLC      :bit1;
  RESERVED1    :bit1;
  SYNCIDLEPIF0 :bit1;
  SYNCIDLEPIF1 :bit1;
  RESERVED2    :bit3;
  RESETMNTR    :bit1;
  RESETHLTR    :bit1;
  RESETCPM     :bit1;
  RESETPIF0    :bit1;
  RESETPIF1    :bit1;
  RESERVED3    :bit2;
  RESETIMPARB0 :bit1;
  RESETIMPARB1 :bit1;
  RESERVED4    :bit2;
  RESETPHY0    :bit1;
  RESETPHY1    :bit1;
  RESERVED5    :bit2;
  TOGGLESTRAP  :bit1;
  CMDCFGEN     :bit1;
  RESERVED6    :bit2;
 end;

 TSWRST_CONTROL_0=bitpacked record
  RESERVED0              :bit15;
  BIF_STRAPREG_RESETRCEN :bit1;
  BIF0_GLOBAL_RESETRCEN  :bit1;
  BIF0_CALIB_RESETRCEN   :bit1;
  BIF0_CORE_RESETRCEN    :bit1;
  BIF0_REGISTER_RESETRCEN:bit1;
  BIF0_PHY_RESETRCEN     :bit1;
  BIF0_STICKY_RESETRCEN  :bit1;
  BIF0_CONFIG_RESETRCEN  :bit1;
  RESERVED1              :bit9;
 end;

 TSWRST_CONTROL_1=bitpacked record
  SWITCHCLK_RCEN    :bit1;
  RESERVED0         :bit1;
  RESETLANEMUX_RCEN :bit1;
  RESETWRAPREGS_RCEN:bit1;
  RESETSRBM0_RCEN   :bit1;
  RESETSRBM1_RCEN   :bit1;
  RESETLC_RCEN      :bit1;
  RESERVED1         :bit1;
  SYNCIDLEPIF0_RCEN :bit1;
  SYNCIDLEPIF1_RCEN :bit1;
  RESERVED2         :bit3;
  RESETMNTR_RCEN    :bit1;
  RESETHLTR_RCEN    :bit1;
  RESETCPM_RCEN     :bit1;
  RESETPIF0_RCEN    :bit1;
  RESETPIF1_RCEN    :bit1;
  RESERVED3         :bit2;
  RESETIMPARB0_RCEN :bit1;
  RESETIMPARB1_RCEN :bit1;
  RESERVED4         :bit2;
  RESETPHY0_RCEN    :bit1;
  RESETPHY1_RCEN    :bit1;
  RESERVED5         :bit2;
  STRAPVLD_RCEN     :bit1;
  CMDCFG_RCEN       :bit1;
  RESERVED6         :bit2;
 end;

 TSWRST_CONTROL_2=bitpacked record
  RESERVED0              :bit15;
  BIF_STRAPREG_RESETATEN :bit1;
  BIF0_GLOBAL_RESETATEN  :bit1;
  BIF0_CALIB_RESETATEN   :bit1;
  BIF0_CORE_RESETATEN    :bit1;
  BIF0_REGISTER_RESETATEN:bit1;
  BIF0_PHY_RESETATEN     :bit1;
  BIF0_STICKY_RESETATEN  :bit1;
  BIF0_CONFIG_RESETATEN  :bit1;
  RESERVED1              :bit9;
 end;

 TSWRST_CONTROL_3=bitpacked record
  SWITCHCLK_ATEN    :bit1;
  RESERVED0         :bit1;
  RESETLANEMUX_ATEN :bit1;
  RESETWRAPREGS_ATEN:bit1;
  RESETSRBM0_ATEN   :bit1;
  RESETSRBM1_ATEN   :bit1;
  RESETLC_ATEN      :bit1;
  RESERVED1         :bit1;
  SYNCIDLEPIF0_ATEN :bit1;
  SYNCIDLEPIF1_ATEN :bit1;
  RESERVED2         :bit3;
  RESETMNTR_ATEN    :bit1;
  RESETHLTR_ATEN    :bit1;
  RESETCPM_ATEN     :bit1;
  RESETPIF0_ATEN    :bit1;
  RESETPIF1_ATEN    :bit1;
  RESERVED3         :bit2;
  RESETIMPARB0_ATEN :bit1;
  RESETIMPARB1_ATEN :bit1;
  RESERVED4         :bit2;
  RESETPHY0_ATEN    :bit1;
  RESETPHY1_ATEN    :bit1;
  RESERVED5         :bit2;
  STRAPVLD_ATEN     :bit1;
  CMDCFG_ATEN       :bit1;
  RESERVED6         :bit2;
 end;

 TSWRST_CONTROL_4=bitpacked record
  RESERVED0              :bit14;
  BIF_STRAPREG_WRRESETEN :bit1;
  RESERVED1              :bit1;
  BIF0_GLOBAL_WRRESETEN  :bit1;
  BIF0_CALIB_WRRESETEN   :bit1;
  BIF0_CORE_WRRESETEN    :bit1;
  BIF0_REGISTER_WRRESETEN:bit1;
  BIF0_PHY_WRRESETEN     :bit1;
  BIF0_STICKY_WRRESETEN  :bit1;
  BIF0_CONFIG_WRRESETEN  :bit1;
  RESERVED2              :bit9;
 end;

 TSWRST_CONTROL_5=bitpacked record
  WRSWITCHCLK_EN    :bit1;
  RESERVED0         :bit1;
  WRRESETLANEMUX_EN :bit1;
  WRRESETWRAPREGS_EN:bit1;
  WRRESETSRBM0_EN   :bit1;
  WRRESETSRBM1_EN   :bit1;
  WRRESETLC_EN      :bit1;
  RESERVED1         :bit1;
  WRSYNCIDLEPIF0_EN :bit1;
  WRSYNCIDLEPIF1_EN :bit1;
  RESERVED2         :bit3;
  WRRESETMNTR_EN    :bit1;
  WRRESETHLTR_EN    :bit1;
  WRRESETCPM_EN     :bit1;
  WRRESETPIF0_EN    :bit1;
  WRRESETPIF1_EN    :bit1;
  RESERVED3         :bit2;
  WRRESETIMPARB0_EN :bit1;
  WRRESETIMPARB1_EN :bit1;
  RESERVED4         :bit2;
  WRRESETPHY0_EN    :bit1;
  WRRESETPHY1_EN    :bit1;
  RESERVED5         :bit2;
  WRSTRAPVLD_EN     :bit1;
  WRCMDCFG_EN       :bit1;
  RESERVED6         :bit2;
 end;

 TSWRST_CONTROL_6=bitpacked record
  WARMRESET_EN          :bit1;
  RESERVED0             :bit7;
  CONNECTWITHWRAPREGS_EN:bit1;
  RESERVED1             :bit23;
 end;

 TSX_DEBUG_BUSY_2=bitpacked record
  COL_SCBD_BUSY            :bit1;
  COL_REQ3_FREECNT_NE0     :bit1;
  COL_REQ3_IDLE            :bit1;
  COL_REQ3_BUSY            :bit1;
  COL_REQ2_FREECNT_NE0     :bit1;
  COL_REQ2_IDLE            :bit1;
  COL_REQ2_BUSY            :bit1;
  COL_REQ1_FREECNT_NE0     :bit1;
  COL_REQ1_IDLE            :bit1;
  COL_REQ1_BUSY            :bit1;
  COL_REQ0_FREECNT_NE0     :bit1;
  COL_REQ0_IDLE            :bit1;
  COL_REQ0_BUSY            :bit1;
  COL_DBIF3_SENDFREE_BUSY  :bit1;
  COL_DBIF3_FIFO_BUSY      :bit1;
  COL_DBIF3_READ_VALID     :bit1;
  COL_DBIF2_SENDFREE_BUSY  :bit1;
  COL_DBIF2_FIFO_BUSY      :bit1;
  COL_DBIF2_READ_VALID     :bit1;
  COL_DBIF1_SENDFREE_BUSY  :bit1;
  COL_DBIF1_FIFO_BUSY      :bit1;
  COL_DBIF1_READ_VALID     :bit1;
  COL_DBIF0_SENDFREE_BUSY  :bit1;
  COL_DBIF0_FIFO_BUSY      :bit1;
  COL_DBIF0_READ_VALID     :bit1;
  COL_BUFF3_BANK3_VAL3_BUSY:bit1;
  COL_BUFF3_BANK3_VAL2_BUSY:bit1;
  COL_BUFF3_BANK3_VAL1_BUSY:bit1;
  COL_BUFF3_BANK3_VAL0_BUSY:bit1;
  COL_BUFF3_BANK2_VAL3_BUSY:bit1;
  COL_BUFF3_BANK2_VAL2_BUSY:bit1;
  COL_BUFF3_BANK2_VAL1_BUSY:bit1;
 end;

 TSX_DEBUG_BUSY_3=bitpacked record
  COL_BUFF3_BANK2_VAL0_BUSY:bit1;
  COL_BUFF3_BANK1_VAL3_BUSY:bit1;
  COL_BUFF3_BANK1_VAL2_BUSY:bit1;
  COL_BUFF3_BANK1_VAL1_BUSY:bit1;
  COL_BUFF3_BANK1_VAL0_BUSY:bit1;
  COL_BUFF3_BANK0_VAL3_BUSY:bit1;
  COL_BUFF3_BANK0_VAL2_BUSY:bit1;
  COL_BUFF3_BANK0_VAL1_BUSY:bit1;
  COL_BUFF3_BANK0_VAL0_BUSY:bit1;
  COL_BUFF2_BANK3_VAL3_BUSY:bit1;
  COL_BUFF2_BANK3_VAL2_BUSY:bit1;
  COL_BUFF2_BANK3_VAL1_BUSY:bit1;
  COL_BUFF2_BANK3_VAL0_BUSY:bit1;
  COL_BUFF2_BANK2_VAL3_BUSY:bit1;
  COL_BUFF2_BANK2_VAL2_BUSY:bit1;
  COL_BUFF2_BANK2_VAL1_BUSY:bit1;
  COL_BUFF2_BANK2_VAL0_BUSY:bit1;
  COL_BUFF2_BANK1_VAL3_BUSY:bit1;
  COL_BUFF2_BANK1_VAL2_BUSY:bit1;
  COL_BUFF2_BANK1_VAL1_BUSY:bit1;
  COL_BUFF2_BANK1_VAL0_BUSY:bit1;
  COL_BUFF2_BANK0_VAL3_BUSY:bit1;
  COL_BUFF2_BANK0_VAL2_BUSY:bit1;
  COL_BUFF2_BANK0_VAL1_BUSY:bit1;
  COL_BUFF2_BANK0_VAL0_BUSY:bit1;
  COL_BUFF1_BANK3_VAL3_BUSY:bit1;
  COL_BUFF1_BANK3_VAL2_BUSY:bit1;
  COL_BUFF1_BANK3_VAL1_BUSY:bit1;
  COL_BUFF1_BANK3_VAL0_BUSY:bit1;
  COL_BUFF1_BANK2_VAL3_BUSY:bit1;
  COL_BUFF1_BANK2_VAL2_BUSY:bit1;
  COL_BUFF1_BANK2_VAL1_BUSY:bit1;
 end;

 TSX_DEBUG_BUSY_4=bitpacked record
  COL_BUFF1_BANK2_VAL0_BUSY:bit1;
  COL_BUFF1_BANK1_VAL3_BUSY:bit1;
  COL_BUFF1_BANK1_VAL2_BUSY:bit1;
  COL_BUFF1_BANK1_VAL1_BUSY:bit1;
  COL_BUFF1_BANK1_VAL0_BUSY:bit1;
  COL_BUFF1_BANK0_VAL3_BUSY:bit1;
  COL_BUFF1_BANK0_VAL2_BUSY:bit1;
  COL_BUFF1_BANK0_VAL1_BUSY:bit1;
  COL_BUFF1_BANK0_VAL0_BUSY:bit1;
  COL_BUFF0_BANK3_VAL3_BUSY:bit1;
  COL_BUFF0_BANK3_VAL2_BUSY:bit1;
  COL_BUFF0_BANK3_VAL1_BUSY:bit1;
  COL_BUFF0_BANK3_VAL0_BUSY:bit1;
  COL_BUFF0_BANK2_VAL3_BUSY:bit1;
  COL_BUFF0_BANK2_VAL2_BUSY:bit1;
  COL_BUFF0_BANK2_VAL1_BUSY:bit1;
  COL_BUFF0_BANK2_VAL0_BUSY:bit1;
  COL_BUFF0_BANK1_VAL3_BUSY:bit1;
  COL_BUFF0_BANK1_VAL2_BUSY:bit1;
  COL_BUFF0_BANK1_VAL1_BUSY:bit1;
  COL_BUFF0_BANK1_VAL0_BUSY:bit1;
  COL_BUFF0_BANK0_VAL3_BUSY:bit1;
  COL_BUFF0_BANK0_VAL2_BUSY:bit1;
  COL_BUFF0_BANK0_VAL1_BUSY:bit1;
  COL_BUFF0_BANK0_VAL0_BUSY:bit1;
  RESERVED                 :bit7;
 end;

 TTA_BC_BASE_ADDR=bit32;

 TTCC_EXE_DISABLE=bitpacked record
  RESERVED0  :bit1;
  EXE_DISABLE:bit1;
  RESERVED1  :bit30;
 end;

 TTCP_ADDR_CONFIG=bitpacked record
  NUM_TCC_BANKS :bit4;
  NUM_BANKS     :bit2;
  COLHI_WIDTH   :bit3;
  RB_SPLIT_COLHI:bit1;
  RESERVED0     :bit22;
 end;

 TTCP_GATCL1_CNTL=bitpacked record
  RESERVED0             :bit25;
  INVALIDATE_ALL_VMID   :bit1;
  FORCE_MISS            :bit1;
  FORCE_IN_ORDER        :bit1;
  REDUCE_FIFO_DEPTH_BY_2:bit2;
  REDUCE_CACHE_SIZE_BY_2:bit2;
 end;

 TTCP_WATCH0_CNTL=bitpacked record
  MASK :bit24;
  VMID :bit4;
  ATC  :bit1;
  MODE :bit2;
  VALID:bit1;
 end;

 TTCP_WATCH1_CNTL=bitpacked record
  MASK :bit24;
  VMID :bit4;
  ATC  :bit1;
  MODE :bit2;
  VALID:bit1;
 end;

 TTCP_WATCH2_CNTL=bitpacked record
  MASK :bit24;
  VMID :bit4;
  ATC  :bit1;
  MODE :bit2;
  VALID:bit1;
 end;

 TTCP_WATCH3_CNTL=bitpacked record
  MASK :bit24;
  VMID :bit4;
  ATC  :bit1;
  MODE :bit2;
  VALID:bit1;
 end;

 TTHM_TMON0_DEBUG=bitpacked record
  DEBUG_RDI:bit5;
  DEBUG_Z  :bit11;
  RESERVED0:bit16;
 end;

 TTHM_TMON1_DEBUG=bitpacked record
  DEBUG_RDI:bit5;
  DEBUG_Z  :bit11;
  RESERVED0:bit16;
 end;

 TTHM_TMON2_CTRL2=bitpacked record
  RDIL_PRESENT:bit16;
  RDIR_PRESENT:bit16;
 end;

 TTHM_TMON2_DEBUG=bitpacked record
  DEBUG_RDI:bit5;
  DEBUG_Z  :bit11;
  RESERVED0:bit16;
 end;

 TUNIPHY_TPG_SEED=bitpacked record
  UNIPHY_TPG_SEED:bit23;
  RESERVED0      :bit9;
 end;

 TUNP_CRC_CONTROL=bitpacked record
  UNP_CRC_ENABLE    :bit1;
  RESERVED0         :bit1;
  UNP_CRC_SOURCE_SEL:bit3;
  RESERVED1         :bit3;
  UNP_CRC_LINE_SEL  :bit2;
  RESERVED2         :bit22;
 end;

 TUNP_CRC_CURRENT=bit32;

 TUNP_GRPH_ENABLE=bitpacked record
  GRPH_ENABLE:bit1;
  RESERVED0  :bit31;
 end;

 TUNP_GRPH_UPDATE=bitpacked record
  GRPH_MODE_UPDATE_PENDING            :bit1;
  GRPH_MODE_UPDATE_TAKEN              :bit1;
  GRPH_SURFACE_UPDATE_PENDING         :bit1;
  GRPH_SURFACE_UPDATE_TAKEN           :bit1;
  RESERVED0                           :bit12;
  GRPH_UPDATE_LOCK                    :bit1;
  RESERVED1                           :bit3;
  GRPH_SURFACE_IGNORE_UPDATE_LOCK     :bit1;
  RESERVED2                           :bit3;
  GRPH_MODE_DISABLE_MULTIPLE_UPDATE   :bit1;
  RESERVED3                           :bit3;
  GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE:bit1;
  RESERVED4                           :bit3;
 end;

 TUNP_HW_ROTATION=bitpacked record
  ROTATION_ANGLE:bit3;
  RESERVED0     :bit1;
  PIXEL_DROP    :bit1;
  RESERVED1     :bit3;
  BUFFER_MODE   :bit1;
  RESERVED2     :bit23;
 end;

 TUVD_ENGINE_CNTL=bitpacked record
  ENGINE_START     :bit1;
  ENGINE_START_MODE:bit1;
  RESERVED0        :bit30;
 end;

 TUVD_MPC_SET_ALU=bitpacked record
  FUNCT    :bit3;
  RESERVED0:bit1;
  OPERAND  :bit8;
  RESERVED1:bit20;
 end;

 TUVD_MPC_SET_MUX=bitpacked record
  SET_0    :bit3;
  SET_1    :bit3;
  SET_2    :bit3;
  RESERVED0:bit23;
 end;

 TUVD_PGFSM_WRITE=bit32;

 TUVD_RBC_IB_BASE=bitpacked record
  RESERVED0:bit6;
  IB_BASE  :bit26;
 end;

 TUVD_RBC_IB_SIZE=bitpacked record
  RESERVED0:bit4;
  IB_SIZE  :bit19;
  RESERVED1:bit9;
 end;

 TUVD_RBC_RB_BASE=bitpacked record
  RESERVED0:bit6;
  RB_BASE  :bit26;
 end;

 TUVD_RBC_RB_CNTL=bitpacked record
  RB_BUFSZ       :bit5;
  RESERVED0      :bit3;
  RB_BLKSZ       :bit5;
  RESERVED1      :bit3;
  RB_NO_FETCH    :bit1;
  RESERVED2      :bit3;
  RB_WPTR_POLL_EN:bit1;
  RESERVED3      :bit3;
  RB_NO_UPDATE   :bit1;
  RESERVED4      :bit3;
  RB_RPTR_WR_EN  :bit1;
  RESERVED5      :bit3;
 end;

 TUVD_RBC_RB_RPTR=bitpacked record
  RESERVED0:bit4;
  RB_RPTR  :bit19;
  RESERVED1:bit9;
 end;

 TUVD_RBC_RB_WPTR=bitpacked record
  RESERVED0:bit4;
  RB_WPTR  :bit19;
  RESERVED1:bit9;
 end;

 TVCE_OUT_RB_WPTR=bitpacked record
  RESERVED0:bit4;
  RESERVED1:bit19;
  RESERVED2:bit9;
 end;

 TVCE_RB_ARB_CTRL=bitpacked record
  RESERVED0        :bit9;
  RESERVED1        :bit7;
  VCE_CGTT_OVERRIDE:bit1;
  RESERVED2        :bit15;
 end;

 TVCE_RB_BASE_HI2=bit32;

 TVCE_RB_BASE_HI3=bit32;

 TVCE_RB_BASE_LO2=bitpacked record
  RESERVED0 :bit6;
  RB_BASE_LO:bit26;
 end;

 TVCE_RB_BASE_LO3=bitpacked record
  RESERVED0 :bit6;
  RB_BASE_LO:bit26;
 end;

 TVCE_SYS_INT_ACK=bitpacked record
  RESERVED0                     :bit1;
  RESERVED1                     :bit2;
  VCE_SYS_INT_TRAP_INTERRUPT_ACK:bit1;
  RESERVED2                     :bit1;
  RESERVED3                     :bit6;
  RESERVED4                     :bit1;
  RESERVED5                     :bit1;
  RESERVED6                     :bit1;
  RESERVED7                     :bit1;
  RESERVED8                     :bit1;
  RESERVED9                     :bit1;
  RESERVED10                    :bit1;
  RESERVED11                    :bit14;
 end;

 TVENDOR_CAP_LIST=bitpacked record
  CAP_ID   :bit8;
  NEXT_PTR :bit8;
  LENGTH   :bit8;
  RESERVED0:bit8;
 end;

 TVGA_HDP_CONTROL=bitpacked record
  VGA_MEM_PAGE_SELECT_EN:bit1;
  RESERVED0             :bit3;
  VGA_MEMORY_DISABLE    :bit1;
  RESERVED1             :bit3;
  VGA_RBBM_LOCK_DISABLE :bit1;
  RESERVED2             :bit7;
  VGA_SOFT_RESET        :bit1;
  RESERVED3             :bit7;
  VGA_TEST_RESET_CONTROL:bit1;
  RESERVED4             :bit7;
 end;

 TVGT_CNTL_STATUS=bitpacked record
  VGT_BUSY         :bit1;
  VGT_OUT_INDX_BUSY:bit1;
  VGT_OUT_BUSY     :bit1;
  VGT_PT_BUSY      :bit1;
  VGT_TE_BUSY      :bit1;
  VGT_VR_BUSY      :bit1;
  VGT_PI_BUSY      :bit1;
  VGT_GS_BUSY      :bit1;
  VGT_HS_BUSY      :bit1;
  VGT_TE11_BUSY    :bit1;
  RESERVED0        :bit22;
 end;

 TVGT_DEBUG_REG10=bitpacked record
  index_buffer_depth_r1_q   :bit5;
  eopg_r2_q                 :bit1;
  eotg_r2_q                 :bit1;
  onchip_gs_en_r0_q         :bit2;
  SPARE2                    :bit2;
  rcm_mem_gsprim_re_qq      :bit1;
  rcm_mem_gsprim_re_q       :bit1;
  gs_rb_space_avail_r3_q_9_0:bit10;
  es_rb_space_avail_r2_q_8_0:bit9;
 end;

 TVGT_DEBUG_REG11=bitpacked record
  tm_busy_q              :bit1;
  tm_noif_busy_q         :bit1;
  tm_out_busy_q          :bit1;
  es_rb_dealloc_fifo_busy:bit1;
  vs_dealloc_tbl_busy    :bit1;
  SPARE1                 :bit1;
  spi_gsthread_fifo_busy :bit1;
  spi_esthread_fifo_busy :bit1;
  hold_eswave            :bit1;
  es_rb_roll_over_r3     :bit1;
  counters_busy_r0       :bit1;
  counters_avail_r0      :bit1;
  counters_available_r0  :bit1;
  vs_event_fifo_rtr      :bit1;
  VGT_SPI_gsthread_rtr_q :bit1;
  VGT_SPI_esthread_rtr_q :bit1;
  gs_issue_rtr           :bit1;
  tm_pt_event_rtr        :bit1;
  SPARE0                 :bit1;
  gs_r0_rtr              :bit1;
  es_r0_rtr              :bit1;
  gog_tm_vs_event_rtr    :bit1;
  tm_rcm_gs_event_rtr    :bit1;
  tm_rcm_gs_tbl_rtr      :bit1;
  tm_rcm_es_tbl_rtr      :bit1;
  vs_event_fifo_empty    :bit1;
  vs_event_fifo_full     :bit1;
  es_rb_dealloc_fifo_full:bit1;
  vs_dealloc_tbl_full    :bit1;
  send_event_q           :bit1;
  es_tbl_empty           :bit1;
  no_active_states_r0    :bit1;
 end;

 TVGT_DEBUG_REG12=bitpacked record
  gs_state0_r0_q :bit3;
  gs_state1_r0_q :bit3;
  gs_state2_r0_q :bit3;
  gs_state3_r0_q :bit3;
  gs_state4_r0_q :bit3;
  gs_state5_r0_q :bit3;
  gs_state6_r0_q :bit3;
  gs_state7_r0_q :bit3;
  gs_state8_r0_q :bit3;
  gs_state9_r0_q :bit3;
  hold_eswave_eop:bit1;
  SPARE0         :bit1;
 end;

 TVGT_DEBUG_REG13=bitpacked record
  gs_state10_r0_q              :bit3;
  gs_state11_r0_q              :bit3;
  gs_state12_r0_q              :bit3;
  gs_state13_r0_q              :bit3;
  gs_state14_r0_q              :bit3;
  gs_state15_r0_q              :bit3;
  gs_tbl_wrptr_r0_q_3_0        :bit4;
  gsfetch_done_fifo_cnt_q_not_0:bit1;
  gsfetch_done_cnt_q_not_0     :bit1;
  es_tbl_full                  :bit1;
  SPARE1                       :bit1;
  SPARE0                       :bit1;
  active_cm_sm_r0_q            :bit5;
 end;

 TVGT_DEBUG_REG14=bitpacked record
  SPARE3                      :bit4;
  gsfetch_done_fifo_full      :bit1;
  gs_rb_space_avail_r0        :bit1;
  smx_es_done_cnt_r0_q_not_0  :bit1;
  SPARE8                      :bit2;
  vs_done_cnt_q_not_0         :bit1;
  es_flush_cnt_busy_q         :bit1;
  gs_tbl_full_r0              :bit1;
  SPARE2                      :bit9;
  se1spi_gsthread_fifo_busy   :bit1;
  SPARE                       :bit3;
  VGT_SE1SPI_gsthread_rtr_q   :bit1;
  smx1_es_done_cnt_r0_q_not_0 :bit1;
  se1spi_esthread_fifo_busy   :bit1;
  SPARE1                      :bit1;
  gsfetch_done_se1_cnt_q_not_0:bit1;
  SPARE0                      :bit1;
  VGT_SE1SPI_esthread_rtr_q   :bit1;
 end;

 TVGT_DEBUG_REG15=bitpacked record
  cm_busy_q            :bit1;
  counters_busy_q      :bit1;
  output_fifo_empty    :bit1;
  output_fifo_full     :bit1;
  counters_full        :bit1;
  active_sm_q          :bit5;
  entry_rdptr_q        :bit5;
  cntr_tbl_wrptr_q     :bit5;
  SPARE25              :bit6;
  st_cut_mode_q        :bit2;
  gs_done_array_q_not_0:bit1;
  SPARE31              :bit3;
 end;

 TVGT_DEBUG_REG16=bitpacked record
  gog_busy                 :bit1;
  gog_state_q              :bit3;
  r0_rtr                   :bit1;
  r1_rtr                   :bit1;
  r1_upstream_rtr          :bit1;
  r2_vs_tbl_rtr            :bit1;
  r2_prim_rtr              :bit1;
  r2_indx_rtr              :bit1;
  r2_rtr                   :bit1;
  gog_tm_vs_event_rtr      :bit1;
  r3_force_vs_tbl_we_rtr   :bit1;
  indx_valid_r2_q          :bit1;
  prim_valid_r2_q          :bit1;
  valid_r2_q               :bit1;
  prim_valid_r1_q          :bit1;
  indx_valid_r1_q          :bit1;
  valid_r1_q               :bit1;
  indx_valid_r0_q          :bit1;
  prim_valid_r0_q          :bit1;
  valid_r0_q               :bit1;
  send_event_q             :bit1;
  SPARE24                  :bit1;
  vert_seen_since_sopg_r2_q:bit1;
  gog_out_prim_state_sel   :bit3;
  multiple_streams_en_r1_q :bit1;
  vs_vert_count_r2_q_not_0 :bit1;
  num_gs_r2_q_not_0        :bit1;
  new_vs_thread_r2         :bit1;
 end;

 TVGT_DEBUG_REG17=bitpacked record
  gog_out_prim_rel_indx2_5_0:bit6;
  gog_out_prim_rel_indx1_5_0:bit6;
  gog_out_prim_rel_indx0_5_0:bit6;
  gog_out_indx_13_0         :bit14;
 end;

 TVGT_DEBUG_REG18=bitpacked record
  grp_vr_valid               :bit1;
  pipe0_dr                   :bit1;
  pipe1_dr                   :bit1;
  vr_grp_read                :bit1;
  pipe0_rtr                  :bit1;
  pipe1_rtr                  :bit1;
  out_vr_indx_read           :bit1;
  out_vr_prim_read           :bit1;
  indices_to_send_q          :bit3;
  valid_indices              :bit1;
  last_indx_of_prim          :bit1;
  indx0_new_d                :bit1;
  indx1_new_d                :bit1;
  indx2_new_d                :bit1;
  indx2_hit_d                :bit1;
  indx1_hit_d                :bit1;
  indx0_hit_d                :bit1;
  st_vertex_reuse_off_r0_q   :bit1;
  last_group_of_instance_r0_q:bit1;
  null_primitive_r0_q        :bit1;
  eop_r0_q                   :bit1;
  eject_vtx_vect_r1_d        :bit1;
  sub_prim_type_r0_q         :bit3;
  gs_scenario_a_r0_q         :bit1;
  gs_scenario_b_r0_q         :bit1;
  components_valid_r0_q      :bit3;
 end;

 TVGT_DEBUG_REG19=bitpacked record
  separate_out_busy_q         :bit1;
  separate_out_indx_busy_q    :bit1;
  prim_buffer_empty           :bit1;
  prim_buffer_full            :bit1;
  pa_clips_fifo_busy_q        :bit1;
  pa_clipp_fifo_busy_q        :bit1;
  VGT_PA_clips_rtr_q          :bit1;
  VGT_PA_clipp_rtr_q          :bit1;
  spi_vsthread_fifo_busy_q    :bit1;
  spi_vsvert_fifo_busy_q      :bit1;
  pa_clipv_fifo_busy_q        :bit1;
  hold_prim                   :bit1;
  VGT_SPI_vsthread_rtr_q      :bit1;
  VGT_SPI_vsvert_rtr_q        :bit1;
  VGT_PA_clipv_rtr_q          :bit1;
  new_packet_q                :bit1;
  buffered_prim_event         :bit1;
  buffered_prim_null_primitive:bit1;
  buffered_prim_eop           :bit1;
  buffered_prim_eject_vtx_vect:bit1;
  buffered_prim_type_event    :bit6;
  VGT_SE1SPI_vswave_rtr_q     :bit1;
  VGT_SE1SPI_vsvert_rtr_q     :bit1;
  num_new_unique_rel_indx     :bit2;
  null_terminate_vtx_vector   :bit1;
  filter_event                :bit1;
 end;

 TVGT_DEBUG_REG20=bitpacked record
  dbg_VGT_SPI_vsthread_sovertexindex      :bit16;
  dbg_VGT_SPI_vsthread_sovertexcount_not_0:bit1;
  SPARE17                                 :bit1;
  alloc_counter_q                         :bit4;
  curr_dealloc_distance_q                 :bit7;
  new_allocate_q                          :bit1;
  curr_slot_in_vtx_vect_q_not_0           :bit1;
  int_vtx_counter_q_not_0                 :bit1;
 end;

 TVGT_DEBUG_REG21=bitpacked record
  out_indx_fifo_empty     :bit1;
  indx_side_fifo_empty    :bit1;
  pipe0_dr                :bit1;
  pipe1_dr                :bit1;
  pipe2_dr                :bit1;
  vsthread_buff_empty     :bit1;
  out_indx_fifo_full      :bit1;
  indx_side_fifo_full     :bit1;
  pipe0_rtr               :bit1;
  pipe1_rtr               :bit1;
  pipe2_rtr               :bit1;
  vsthread_buff_full      :bit1;
  interfaces_rtr          :bit1;
  indx_count_q_not_0      :bit1;
  wait_for_external_eopg_q:bit1;
  full_state_p1_q         :bit1;
  indx_side_indx_valid    :bit1;
  stateid_p0_q            :bit3;
  is_event_p0_q           :bit1;
  lshs_dealloc_p1         :bit1;
  stream_id_r2_q          :bit1;
  vtx_vect_counter_q_not_0:bit1;
  buff_full_p1            :bit1;
  strmout_valid_p1        :bit1;
  eotg_r2_q               :bit1;
  null_r2_q               :bit1;
  p0_dr                   :bit1;
  p0_rtr                  :bit1;
  eopg_p0_q               :bit1;
  p0_nobp                 :bit1;
 end;

 TVGT_DEBUG_REG22=bitpacked record
  cm_state16:bit2;
  cm_state17:bit2;
  cm_state18:bit2;
  cm_state19:bit2;
  cm_state20:bit2;
  cm_state21:bit2;
  cm_state22:bit2;
  cm_state23:bit2;
  cm_state24:bit2;
  cm_state25:bit2;
  cm_state26:bit2;
  cm_state27:bit2;
  cm_state28:bit2;
  cm_state29:bit2;
  cm_state30:bit2;
  cm_state31:bit2;
 end;

 TVGT_DEBUG_REG23=bitpacked record
  frmt_busy          :bit1;
  rcm_frmt_vert_rtr  :bit1;
  rcm_frmt_prim_rtr  :bit1;
  prim_r3_rtr        :bit1;
  prim_r2_rtr        :bit1;
  vert_r3_rtr        :bit1;
  vert_r2_rtr        :bit1;
  vert_r1_rtr        :bit1;
  vert_r0_rtr        :bit1;
  prim_fifo_empty    :bit1;
  prim_fifo_full     :bit1;
  vert_dr_r2_q       :bit1;
  prim_dr_r2_q       :bit1;
  vert_dr_r1_q       :bit1;
  vert_dr_r0_q       :bit1;
  new_verts_r2_q     :bit2;
  verts_sent_r2_q    :bit4;
  prim_state_sel_r2_q:bit3;
  SPARE              :bit8;
 end;

 TVGT_DEBUG_REG24=bitpacked record
  avail_es_rb_space_r0_q_23_0:bit24;
  dependent_st_cut_mode_q    :bit2;
  SPARE31                    :bit6;
 end;

 TVGT_DEBUG_REG25=bitpacked record
  avail_gs_rb_space_r0_q_25_0:bit26;
  active_sm_r0_q             :bit4;
  add_gs_rb_space_r1_q       :bit1;
  add_gs_rb_space_r0_q       :bit1;
 end;

 TVGT_DEBUG_REG26=bitpacked record
  cm_state0 :bit2;
  cm_state1 :bit2;
  cm_state2 :bit2;
  cm_state3 :bit2;
  cm_state4 :bit2;
  cm_state5 :bit2;
  cm_state6 :bit2;
  cm_state7 :bit2;
  cm_state8 :bit2;
  cm_state9 :bit2;
  cm_state10:bit2;
  cm_state11:bit2;
  cm_state12:bit2;
  cm_state13:bit2;
  cm_state14:bit2;
  cm_state15:bit2;
 end;

 TVGT_DEBUG_REG27=bitpacked record
  pipe0_dr                   :bit1;
  gsc0_dr                    :bit1;
  pipe1_dr                   :bit1;
  tm_pt_event_rtr            :bit1;
  pipe0_rtr                  :bit1;
  gsc0_rtr                   :bit1;
  pipe1_rtr                  :bit1;
  last_indx_of_prim_p1_q     :bit1;
  indices_to_send_p0_q       :bit2;
  event_flag_p1_q            :bit1;
  eop_p1_q                   :bit1;
  gs_out_prim_type_p0_q      :bit2;
  gsc_null_primitive_p0_q    :bit1;
  gsc_eop_p0_q               :bit1;
  gsc_2cycle_output          :bit1;
  gsc_2nd_cycle_p0_q         :bit1;
  last_indx_of_vsprim        :bit1;
  first_vsprim_of_gsprim_p0_q:bit1;
  gsc_indx_count_p0_q        :bit11;
  last_vsprim_of_gsprim      :bit1;
 end;

 TVGT_DEBUG_REG28=bitpacked record
  con_state_q                  :bit4;
  second_cycle_q               :bit1;
  process_tri_middle_p0_q      :bit1;
  process_tri_1st_2nd_half_p0_q:bit1;
  process_tri_center_poly_p0_q :bit1;
  pipe0_patch_dr               :bit1;
  pipe0_edge_dr                :bit1;
  pipe1_dr                     :bit1;
  pipe0_patch_rtr              :bit1;
  pipe0_edge_rtr               :bit1;
  pipe1_rtr                    :bit1;
  outer_parity_p0_q            :bit1;
  parallel_parity_p0_q         :bit1;
  first_ring_of_patch_p0_q     :bit1;
  last_ring_of_patch_p0_q      :bit1;
  last_edge_of_outer_ring_p0_q :bit1;
  last_point_of_outer_ring_p1  :bit1;
  last_point_of_inner_ring_p1  :bit1;
  outer_edge_tf_eq_one_p0_q    :bit1;
  advance_outer_point_p1       :bit1;
  advance_inner_point_p1       :bit1;
  next_ring_is_rect_p0_q       :bit1;
  pipe1_outer1_rtr             :bit1;
  pipe1_outer2_rtr             :bit1;
  pipe1_inner1_rtr             :bit1;
  pipe1_inner2_rtr             :bit1;
  pipe1_patch_rtr              :bit1;
  pipe1_edge_rtr               :bit1;
  use_stored_inner_q_ring2     :bit1;
 end;

 TVGT_DEBUG_REG29=bitpacked record
  con_state_q                  :bit4;
  second_cycle_q               :bit1;
  process_tri_middle_p0_q      :bit1;
  process_tri_1st_2nd_half_p0_q:bit1;
  process_tri_center_poly_p0_q :bit1;
  pipe0_patch_dr               :bit1;
  pipe0_edge_dr                :bit1;
  pipe1_dr                     :bit1;
  pipe0_patch_rtr              :bit1;
  pipe0_edge_rtr               :bit1;
  pipe1_rtr                    :bit1;
  outer_parity_p0_q            :bit1;
  parallel_parity_p0_q         :bit1;
  first_ring_of_patch_p0_q     :bit1;
  last_ring_of_patch_p0_q      :bit1;
  last_edge_of_outer_ring_p0_q :bit1;
  last_point_of_outer_ring_p1  :bit1;
  last_point_of_inner_ring_p1  :bit1;
  outer_edge_tf_eq_one_p0_q    :bit1;
  advance_outer_point_p1       :bit1;
  advance_inner_point_p1       :bit1;
  next_ring_is_rect_p0_q       :bit1;
  pipe1_outer1_rtr             :bit1;
  pipe1_outer2_rtr             :bit1;
  pipe1_inner1_rtr             :bit1;
  pipe1_inner2_rtr             :bit1;
  pipe1_patch_rtr              :bit1;
  pipe1_edge_rtr               :bit1;
  use_stored_inner_q_ring3     :bit1;
 end;

 TVGT_DEBUG_REG30=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit1;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit1;
  RESERVED13:bit1;
  RESERVED14:bit1;
  RESERVED15:bit1;
  RESERVED16:bit1;
  RESERVED17:bit1;
  RESERVED18:bit1;
  RESERVED19:bit1;
  RESERVED20:bit1;
  RESERVED21:bit1;
  RESERVED22:bit1;
  RESERVED23:bit1;
  RESERVED24:bit1;
  RESERVED25:bit1;
  RESERVED26:bit1;
  RESERVED27:bit1;
  RESERVED28:bit1;
  RESERVED29:bit3;
 end;

 TVGT_DEBUG_REG31=bitpacked record
  pipe0_dr                 :bit1;
  pipe0_rtr                :bit1;
  pipe1_outer_dr           :bit1;
  pipe1_inner_dr           :bit1;
  pipe2_outer_dr           :bit1;
  pipe2_inner_dr           :bit1;
  pipe3_outer_dr           :bit1;
  pipe3_inner_dr           :bit1;
  pipe4_outer_dr           :bit1;
  pipe4_inner_dr           :bit1;
  pipe5_outer_dr           :bit1;
  pipe5_inner_dr           :bit1;
  pipe2_outer_rtr          :bit1;
  pipe2_inner_rtr          :bit1;
  pipe3_outer_rtr          :bit1;
  pipe3_inner_rtr          :bit1;
  pipe4_outer_rtr          :bit1;
  pipe4_inner_rtr          :bit1;
  pipe5_outer_rtr          :bit1;
  pipe5_inner_rtr          :bit1;
  pg_con_outer_point1_rts  :bit1;
  pg_con_outer_point2_rts  :bit1;
  pg_con_inner_point1_rts  :bit1;
  pg_con_inner_point2_rts  :bit1;
  pg_patch_fifo_empty      :bit1;
  pg_edge_fifo_empty       :bit1;
  pg_inner3_perp_fifo_empty:bit1;
  pg_patch_fifo_full       :bit1;
  pg_edge_fifo_full        :bit1;
  pg_inner_perp_fifo_full  :bit1;
  outer_ring_done_q        :bit1;
  inner_ring_done_q        :bit1;
 end;

 TVGT_DEBUG_REG32=bitpacked record
  first_ring_of_patch      :bit1;
  last_ring_of_patch       :bit1;
  last_edge_of_outer_ring  :bit1;
  last_point_of_outer_edge :bit1;
  last_edge_of_inner_ring  :bit1;
  last_point_of_inner_edge :bit1;
  last_patch_of_tg_p0_q    :bit1;
  event_null_special_p0_q  :bit1;
  event_flag_p5_q          :bit1;
  first_point_of_patch_p5_q:bit1;
  first_point_of_edge_p5_q :bit1;
  last_patch_of_tg_p5_q    :bit1;
  tess_topology_p5_q       :bit2;
  pipe5_inner3_rtr         :bit1;
  pipe5_inner2_rtr         :bit1;
  pg_edge_fifo3_full       :bit1;
  pg_edge_fifo2_full       :bit1;
  pg_inner3_point_fifo_full:bit1;
  pg_outer3_point_fifo_full:bit1;
  pg_inner2_point_fifo_full:bit1;
  pg_outer2_point_fifo_full:bit1;
  pg_inner_point_fifo_full :bit1;
  pg_outer_point_fifo_full :bit1;
  inner2_fifos_rtr         :bit1;
  inner_fifos_rtr          :bit1;
  outer_fifos_rtr          :bit1;
  fifos_rtr                :bit1;
  SPARE                    :bit4;
 end;

 TVGT_DEBUG_REG33=bitpacked record
  pipe0_patch_dr       :bit1;
  ring3_pipe1_dr       :bit1;
  pipe1_dr             :bit1;
  pipe2_dr             :bit1;
  pipe0_patch_rtr      :bit1;
  ring2_pipe1_dr       :bit1;
  ring1_pipe1_dr       :bit1;
  pipe2_rtr            :bit1;
  pipe3_dr             :bit1;
  pipe3_rtr            :bit1;
  ring2_in_sync_q      :bit1;
  ring1_in_sync_q      :bit1;
  pipe1_patch_rtr      :bit1;
  ring3_in_sync_q      :bit1;
  tm_te11_event_rtr    :bit1;
  first_prim_of_patch_q:bit1;
  con_prim_fifo_full   :bit1;
  con_vert_fifo_full   :bit1;
  con_prim_fifo_empty  :bit1;
  con_vert_fifo_empty  :bit1;
  last_patch_of_tg_p0_q:bit1;
  ring3_valid_p2       :bit1;
  ring2_valid_p2       :bit1;
  ring1_valid_p2       :bit1;
  tess_type_p0_q       :bit2;
  tess_topology_p0_q   :bit2;
  te11_out_vert_gs_en  :bit1;
  con_ring3_busy       :bit1;
  con_ring2_busy       :bit1;
  con_ring1_busy       :bit1;
 end;

 TVGT_DEBUG_REG34=bitpacked record
  con_state_q                  :bit4;
  second_cycle_q               :bit1;
  process_tri_middle_p0_q      :bit1;
  process_tri_1st_2nd_half_p0_q:bit1;
  process_tri_center_poly_p0_q :bit1;
  pipe0_patch_dr               :bit1;
  pipe0_edge_dr                :bit1;
  pipe1_dr                     :bit1;
  pipe0_patch_rtr              :bit1;
  pipe0_edge_rtr               :bit1;
  pipe1_rtr                    :bit1;
  outer_parity_p0_q            :bit1;
  parallel_parity_p0_q         :bit1;
  first_ring_of_patch_p0_q     :bit1;
  last_ring_of_patch_p0_q      :bit1;
  last_edge_of_outer_ring_p0_q :bit1;
  last_point_of_outer_ring_p1  :bit1;
  last_point_of_inner_ring_p1  :bit1;
  outer_edge_tf_eq_one_p0_q    :bit1;
  advance_outer_point_p1       :bit1;
  advance_inner_point_p1       :bit1;
  next_ring_is_rect_p0_q       :bit1;
  pipe1_outer1_rtr             :bit1;
  pipe1_outer2_rtr             :bit1;
  pipe1_inner1_rtr             :bit1;
  pipe1_inner2_rtr             :bit1;
  pipe1_patch_rtr              :bit1;
  pipe1_edge_rtr               :bit1;
  use_stored_inner_q_ring1     :bit1;
 end;

 TVGT_DEBUG_REG35=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit1;
  RESERVED4:bit1;
  RESERVED5:bit11;
  RESERVED6:bit16;
 end;

 TVGT_DEBUG_REG36=bit32;

 TVGT_DMA_BASE_HI=bitpacked record
  BASE_ADDR:bit8;
  RESERVED0:bit24;
 end;

 TVGT_DMA_CONTROL=bitpacked record
  PRIMGROUP_SIZE  :bit16;
  RESERVED0       :bit1;
  IA_SWITCH_ON_EOP:bit1;
  RESERVED1       :bit2;
  WD_SWITCH_ON_EOP:bit1;
  RESERVED2       :bit11;
 end;

 TVGT_FIFO_DEPTHS=bitpacked record
  VS_DEALLOC_TBL_DEPTH:bit7;
  RESERVED0           :bit1;
  CLIPP_FIFO_DEPTH    :bit14;
  HSINPUT_FIFO_DEPTH  :bit6;
  RESERVED1           :bit4;
 end;

 TVGT_INDX_OFFSET=bit32;

 TVGT_MC_LAT_CNTL=bitpacked record
  MC_TIME_STAMP_RES:bit2;
  RESERVED0        :bit30;
 end;

 TVGT_NUM_INDICES=bit32;

 TVGT_RESET_DEBUG=bitpacked record
  GS_DISABLE  :bit1;
  TESS_DISABLE:bit1;
  WD_DISABLE  :bit1;
  RESERVED0   :bit29;
 end;

 TVLINE_START_END=bitpacked record
  RESERVED0:bit14;
  RESERVED1:bit2;
  RESERVED2:bit14;
  RESERVED3:bit1;
  RESERVED4:bit1;
 end;

 TXDMA_MSTR_CACHE=bitpacked record
  XDMA_MSTR_CACHE_PITCH       :bit14;
  RESERVED0                   :bit15;
  XDMA_MSTR_CACHE_TLB_PG_STATE:bit2;
  XDMA_MSTR_CACHE_TLB_PG_TRANS:bit1;
 end;

 TXDMA_PG_CONTROL=bit32;

 TAFMT_AUDIO_INFO0=bitpacked record
  AFMT_AUDIO_INFO_CHECKSUM       :bit8;
  AFMT_AUDIO_INFO_CC             :bit3;
  AFMT_AUDIO_INFO_CT             :bit4;
  RESERVED0                      :bit1;
  AFMT_AUDIO_INFO_CHECKSUM_OFFSET:bit8;
  AFMT_AUDIO_INFO_CXT            :bit5;
  RESERVED1                      :bit3;
 end;

 TAFMT_AUDIO_INFO1=bitpacked record
  AFMT_AUDIO_INFO_CA    :bit8;
  RESERVED0             :bit3;
  AFMT_AUDIO_INFO_LSV   :bit4;
  AFMT_AUDIO_INFO_DM_INH:bit1;
  AFMT_AUDIO_INFO_LFEPBL:bit2;
  RESERVED1             :bit14;
 end;

 TAFMT_GENERIC_HDR=bitpacked record
  AFMT_GENERIC_HB0:bit8;
  AFMT_GENERIC_HB1:bit8;
  AFMT_GENERIC_HB2:bit8;
  AFMT_GENERIC_HB3:bit8;
 end;

 TAZALIA_AUDIO_DTO=bitpacked record
  AZALIA_AUDIO_DTO_PHASE :bit16;
  AZALIA_AUDIO_DTO_MODULE:bit16;
 end;

 TBIF_BUSNUM_CNTL1=bitpacked record
  ID_MASK  :bit8;
  RESERVED0:bit24;
 end;

 TBIF_BUSNUM_CNTL2=bitpacked record
  AUTOUPDATE_SEL         :bit8;
  AUTOUPDATE_EN          :bit1;
  RESERVED0              :bit7;
  HDPREG_CNTL            :bit1;
  ERROR_MULTIPLE_ID_MATCH:bit1;
  RESERVED1              :bit14;
 end;

 TBIF_BUSNUM_LIST0=bitpacked record
  ID0:bit8;
  ID1:bit8;
  ID2:bit8;
  ID3:bit8;
 end;

 TBIF_BUSNUM_LIST1=bitpacked record
  ID4:bit8;
  ID5:bit8;
  ID6:bit8;
  ID7:bit8;
 end;

 TBIF_PERFMON_CNTL=bitpacked record
  PERFCOUNTER_EN    :bit1;
  PERFCOUNTER_RESET0:bit1;
  PERFCOUNTER_RESET1:bit1;
  RESERVED0         :bit5;
  PERF_SEL0         :bit5;
  PERF_SEL1         :bit5;
  RESERVED1         :bit14;
 end;

 TBIF_PWDN_COMMAND=bitpacked record
  REG_BU_pw_cmd            :bit1;
  REG_RWREG_RFEWDBIF_pw_cmd:bit1;
  REG_SMBUS_pw_cmd         :bit1;
  REG_BX_pw_cmd            :bit1;
  RESERVED0                :bit28;
 end;

 TBL1_PWM_ABM_CNTL=bitpacked record
  BL1_PWM_USE_ABM_EN                       :bit1;
  BL1_PWM_USE_AMBIENT_LEVEL_EN             :bit1;
  BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN :bit1;
  BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN    :bit1;
  RESERVED0                                :bit12;
  BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE:bit16;
 end;

 TCB_COLOR0_ATTRIB=bitpacked record
  TILE_MODE_INDEX      :bit5;
  FMASK_TILE_MODE_INDEX:bit5;
  FMASK_BANK_HEIGHT    :bit2;
  NUM_SAMPLES          :bit3;
  NUM_FRAGMENTS        :bit2;
  FORCE_DST_ALPHA_1    :bit1;
  RESERVED0            :bit14;
 end;

 TCB_COLOR1_ATTRIB=bitpacked record
  TILE_MODE_INDEX      :bit5;
  FMASK_TILE_MODE_INDEX:bit5;
  FMASK_BANK_HEIGHT    :bit2;
  NUM_SAMPLES          :bit3;
  NUM_FRAGMENTS        :bit2;
  FORCE_DST_ALPHA_1    :bit1;
  RESERVED0            :bit14;
 end;

 TCB_COLOR2_ATTRIB=bitpacked record
  TILE_MODE_INDEX      :bit5;
  FMASK_TILE_MODE_INDEX:bit5;
  FMASK_BANK_HEIGHT    :bit2;
  NUM_SAMPLES          :bit3;
  NUM_FRAGMENTS        :bit2;
  FORCE_DST_ALPHA_1    :bit1;
  RESERVED0            :bit14;
 end;

 TCB_COLOR3_ATTRIB=bitpacked record
  TILE_MODE_INDEX      :bit5;
  FMASK_TILE_MODE_INDEX:bit5;
  FMASK_BANK_HEIGHT    :bit2;
  NUM_SAMPLES          :bit3;
  NUM_FRAGMENTS        :bit2;
  FORCE_DST_ALPHA_1    :bit1;
  RESERVED0            :bit14;
 end;

 TCB_COLOR4_ATTRIB=bitpacked record
  TILE_MODE_INDEX      :bit5;
  FMASK_TILE_MODE_INDEX:bit5;
  FMASK_BANK_HEIGHT    :bit2;
  NUM_SAMPLES          :bit3;
  NUM_FRAGMENTS        :bit2;
  FORCE_DST_ALPHA_1    :bit1;
  RESERVED0            :bit14;
 end;

 TCB_COLOR5_ATTRIB=bitpacked record
  TILE_MODE_INDEX      :bit5;
  FMASK_TILE_MODE_INDEX:bit5;
  FMASK_BANK_HEIGHT    :bit2;
  NUM_SAMPLES          :bit3;
  NUM_FRAGMENTS        :bit2;
  FORCE_DST_ALPHA_1    :bit1;
  RESERVED0            :bit14;
 end;

 TCB_COLOR6_ATTRIB=bitpacked record
  TILE_MODE_INDEX      :bit5;
  FMASK_TILE_MODE_INDEX:bit5;
  FMASK_BANK_HEIGHT    :bit2;
  NUM_SAMPLES          :bit3;
  NUM_FRAGMENTS        :bit2;
  FORCE_DST_ALPHA_1    :bit1;
  RESERVED0            :bit14;
 end;

 TCB_COLOR7_ATTRIB=bitpacked record
  TILE_MODE_INDEX      :bit5;
  FMASK_TILE_MODE_INDEX:bit5;
  FMASK_BANK_HEIGHT    :bit2;
  NUM_SAMPLES          :bit3;
  NUM_FRAGMENTS        :bit2;
  FORCE_DST_ALPHA_1    :bit1;
  RESERVED0            :bit14;
 end;

 TCB_COLOR_CONTROL=bitpacked record
  DISABLE_DUAL_QUAD:bit1;
  RESERVED0        :bit2;
  DEGAMMA_ENABLE   :bit1;
  MODE             :bit3;
  RESERVED1        :bit9;
  ROP3             :bit8;
  RESERVED2        :bit8;
 end;

 TCC_DRM_ID_STRAPS=bitpacked record
  RESERVED0   :bit1;
  RESERVED1   :bit3;
  DEVICE_ID   :bit16;
  MAJOR_REV_ID:bit4;
  MINOR_REV_ID:bit4;
  ATI_REV_ID  :bit4;
 end;

 TCC_GC_EDC_CONFIG=bitpacked record
  RESERVED0:bit1;
  DIS_EDC  :bit1;
  RESERVED1:bit30;
 end;

 TCC_GIO_IOC_FUSES=bitpacked record
  RESERVED0:bit1;
  IOC_FUSES:bit5;
  RESERVED1:bit26;
 end;

 TCC_HARVEST_FUSES=bitpacked record
  RESERVED0  :bit1;
  VCE_DISABLE:bit2;
  RESERVED1  :bit1;
  UVD_DISABLE:bit1;
  RESERVED2  :bit1;
  ACP_EXISTS :bit1;
  RESERVED3  :bit1;
  DC_DISABLE :bit6;
  RESERVED4  :bit18;
 end;

 TCC_RB_REDUNDANCY=bitpacked record
  RESERVED0     :bit1;
  RESERVED1     :bit7;
  FAILED_RB0    :bit4;
  EN_REDUNDANCY0:bit1;
  RESERVED2     :bit3;
  FAILED_RB1    :bit4;
  EN_REDUNDANCY1:bit1;
  RESERVED3     :bit11;
 end;

 TCC_TST_ID_STRAPS=bitpacked record
  RESERVED0   :bit1;
  RESERVED1   :bit3;
  DEVICE_ID   :bit16;
  MAJOR_REV_ID:bit4;
  MINOR_REV_ID:bit4;
  ATI_REV_ID  :bit4;
 end;

 TCGTS_RD_CTRL_REG=bitpacked record
  ROW_MUX_SEL:bit5;
  RESERVED0  :bit3;
  REG_MUX_SEL:bit5;
  RESERVED1  :bit19;
 end;

 TCGTS_SM_CTRL_REG=bitpacked record
  ON_SEQ_DELAY     :bit4;
  OFF_SEQ_DELAY    :bit8;
  MGCG_ENABLED     :bit1;
  RESERVED0        :bit3;
  BASE_MODE        :bit1;
  SM_MODE          :bit3;
  SM_MODE_ENABLE   :bit1;
  _OVERRIDE        :bit1;
  LS_OVERRIDE      :bit1;
  ON_MONITOR_ADD_EN:bit1;
  ON_MONITOR_ADD   :bit8;
 end;

 TCGTS_TCC_DISABLE=bitpacked record
  RESERVED0  :bit1;
  RESERVED1  :bit15;
  TCC_DISABLE:bit16;
 end;

 TCGTT_CP_CLK_CTRL=bitpacked record
  ON_DELAY             :bit4;
  OFF_HYSTERESIS       :bit8;
  RESERVED0            :bit17;
  SOFT_OVERRIDE_PERFMON:bit1;
  SOFT_OVERRIDE_DYN    :bit1;
  SOFT_OVERRIDE_REG    :bit1;
 end;

 TCGTT_IA_CLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  PERF_ENABLE   :bit1;
  DBG_ENABLE    :bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  CORE_OVERRIDE :bit1;
  REG_OVERRIDE  :bit1;
 end;

 TCGTT_PA_CLK_CTRL=bitpacked record
  ON_DELAY        :bit4;
  OFF_HYSTERESIS  :bit8;
  RESERVED0       :bit12;
  SOFT_OVERRIDE7  :bit1;
  SOFT_OVERRIDE6  :bit1;
  SOFT_OVERRIDE5  :bit1;
  SOFT_OVERRIDE4  :bit1;
  SOFT_OVERRIDE3  :bit1;
  SU_CLK_OVERRIDE :bit1;
  CL_CLK_OVERRIDE :bit1;
  REG_CLK_OVERRIDE:bit1;
 end;

 TCGTT_PC_CLK_CTRL=bitpacked record
  ON_DELAY             :bit4;
  OFF_HYSTERESIS       :bit8;
  RESERVED0            :bit6;
  GRP5_CG_OFF_HYST     :bit6;
  GRP5_CG_OVERRIDE     :bit1;
  BACK_CLK_ON_OVERRIDE :bit1;
  FRONT_CLK_ON_OVERRIDE:bit1;
  CORE3_OVERRIDE       :bit1;
  CORE2_OVERRIDE       :bit1;
  CORE1_OVERRIDE       :bit1;
  CORE0_OVERRIDE       :bit1;
  REG_OVERRIDE         :bit1;
 end;

 TCGTT_SC_CLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCGTT_SQ_CLK_CTRL=bitpacked record
  ON_DELAY        :bit4;
  OFF_HYSTERESIS  :bit8;
  RESERVED0       :bit17;
  PERFMON_OVERRIDE:bit1;
  CORE_OVERRIDE   :bit1;
  REG_OVERRIDE    :bit1;
 end;

 TCGTT_WD_CLK_CTRL=bitpacked record
  ON_DELAY           :bit4;
  OFF_HYSTERESIS     :bit8;
  RESERVED0          :bit12;
  SOFT_OVERRIDE7     :bit1;
  PERF_ENABLE        :bit1;
  DBG_ENABLE         :bit1;
  SOFT_OVERRIDE4     :bit1;
  TESS_OVERRIDE      :bit1;
  CORE_OVERRIDE      :bit1;
  RBIU_INPUT_OVERRIDE:bit1;
  REG_OVERRIDE       :bit1;
 end;

 TCG_CLKPIN_CNTL_2=bitpacked record
  ENABLE_XCLK        :bit1;
  RESERVED0          :bit2;
  FORCE_BIF_REFCLK_EN:bit1;
  RESERVED1          :bit4;
  MUX_TCLK_TO_XCLK   :bit1;
  RESERVED2          :bit5;
  XO_IN_OSCIN_EN     :bit1;
  XO_IN_ICORE_CLK_OE :bit1;
  XO_IN_CML_RXEN     :bit1;
  XO_IN_BIDIR_CML_OE :bit1;
  XO_IN2_OSCIN_EN    :bit1;
  XO_IN2_ICORE_CLK_OE:bit1;
  XO_IN2_CML_RXEN    :bit1;
  XO_IN2_BIDIR_CML_OE:bit1;
  CML_CTRL           :bit2;
  CLK_SPARE          :bit8;
 end;

 TCG_ULV_PARAMETER=bitpacked record
  ULV_THRESHOLD     :bit16;
  ULV_THRESHOLD_UNIT:bit4;
  RESERVED0         :bit12;
 end;

 TCLKREQB_PAD_CNTL=bitpacked record
  CLKREQB_PAD_A             :bit1;
  CLKREQB_PAD_SEL           :bit1;
  CLKREQB_PAD_MODE          :bit1;
  CLKREQB_PAD_SPARE         :bit2;
  CLKREQB_PAD_SN0           :bit1;
  CLKREQB_PAD_SN1           :bit1;
  CLKREQB_PAD_SN2           :bit1;
  CLKREQB_PAD_SN3           :bit1;
  CLKREQB_PAD_SLEWN         :bit1;
  CLKREQB_PAD_WAKE          :bit1;
  CLKREQB_PAD_SCHMEN        :bit1;
  CLKREQB_PAD_CNTL_EN       :bit1;
  CLKREQB_PAD_Y             :bit1;
  RESERVED0                 :bit10;
  CLKREQB_PERF_COUNTER_UPPER:bit8;
 end;

 TCNV_INPUT_SELECT=bitpacked record
  CNV_INPUT_SRC_SELECT :bit2;
  CNV_INPUT_PIPE_SELECT:bit3;
  RESERVED0            :bit27;
 end;

 TCNV_TEST_CRC_RED=bitpacked record
  RESERVED0            :bit4;
  CNV_TEST_CRC_RED_MASK:bit12;
  CNV_TEST_CRC_SIG_RED :bit16;
 end;

 TCNV_WINDOW_START=bitpacked record
  CNV_WINDOW_START_X:bit12;
  RESERVED0         :bit4;
  CNV_WINDOW_START_Y:bit12;
  RESERVED1         :bit4;
 end;

 TCOMPUTE_RELAUNCH=bitpacked record
  PAYLOAD :bit30;
  IS_EVENT:bit1;
  IS_STATE:bit1;
 end;

 TCONFIG_APER_SIZE=bit32;

 TCP_CE_IB1_OFFSET=bitpacked record
  IB1_OFFSET:bit20;
  RESERVED0 :bit12;
 end;

 TCP_CE_IB2_OFFSET=bitpacked record
  IB2_OFFSET:bit20;
  RESERVED0 :bit12;
 end;

 TCP_CE_INIT_BUFSZ=bitpacked record
  INIT_BUFSZ:bit12;
  RESERVED0 :bit20;
 end;

 TCP_CE_UCODE_ADDR=bitpacked record
  UCODE_ADDR:bit12;
  RESERVED0 :bit20;
 end;

 TCP_CE_UCODE_DATA=bit32;

 TCP_COHER_BASE_HI=bitpacked record
  COHER_BASE_HI_256B:bit8;
  RESERVED0         :bit24;
 end;

 TCP_COHER_SIZE_HI=bitpacked record
  COHER_SIZE_HI_256B:bit8;
  RESERVED0         :bit24;
 end;

 TCP_CPC_BUSY_STAT=bitpacked record
  MEC1_LOAD_BUSY         :bit1;
  MEC1_SEMAPOHRE_BUSY    :bit1;
  MEC1_MUTEX_BUSY        :bit1;
  MEC1_MESSAGE_BUSY      :bit1;
  MEC1_EOP_QUEUE_BUSY    :bit1;
  MEC1_IQ_QUEUE_BUSY     :bit1;
  MEC1_IB_QUEUE_BUSY     :bit1;
  MEC1_TC_BUSY           :bit1;
  MEC1_DMA_BUSY          :bit1;
  MEC1_PARTIAL_FLUSH_BUSY:bit1;
  MEC1_PIPE0_BUSY        :bit1;
  MEC1_PIPE1_BUSY        :bit1;
  MEC1_PIPE2_BUSY        :bit1;
  MEC1_PIPE3_BUSY        :bit1;
  RESERVED0              :bit2;
  MEC2_LOAD_BUSY         :bit1;
  MEC2_SEMAPOHRE_BUSY    :bit1;
  MEC2_MUTEX_BUSY        :bit1;
  MEC2_MESSAGE_BUSY      :bit1;
  MEC2_EOP_QUEUE_BUSY    :bit1;
  MEC2_IQ_QUEUE_BUSY     :bit1;
  MEC2_IB_QUEUE_BUSY     :bit1;
  MEC2_TC_BUSY           :bit1;
  MEC2_DMA_BUSY          :bit1;
  MEC2_PARTIAL_FLUSH_BUSY:bit1;
  MEC2_PIPE0_BUSY        :bit1;
  MEC2_PIPE1_BUSY        :bit1;
  MEC2_PIPE2_BUSY        :bit1;
  MEC2_PIPE3_BUSY        :bit1;
  RESERVED1              :bit2;
 end;

 TCP_CPF_BUSY_STAT=bitpacked record
  REG_BUS_FIFO_BUSY        :bit1;
  CSF_RING_BUSY            :bit1;
  CSF_INDIRECT1_BUSY       :bit1;
  CSF_INDIRECT2_BUSY       :bit1;
  CSF_STATE_BUSY           :bit1;
  CSF_CE_INDR1_BUSY        :bit1;
  CSF_CE_INDR2_BUSY        :bit1;
  CSF_ARBITER_BUSY         :bit1;
  CSF_INPUT_BUSY           :bit1;
  OUTSTANDING_READ_TAGS    :bit1;
  RESERVED0                :bit1;
  HPD_PROCESSING_EOP_BUSY  :bit1;
  HQD_DISPATCH_BUSY        :bit1;
  HQD_IQ_TIMER_BUSY        :bit1;
  HQD_DMA_OFFLOAD_BUSY     :bit1;
  HQD_WAIT_SEMAPHORE_BUSY  :bit1;
  HQD_SIGNAL_SEMAPHORE_BUSY:bit1;
  HQD_MESSAGE_BUSY         :bit1;
  HQD_PQ_FETCHER_BUSY      :bit1;
  HQD_IB_FETCHER_BUSY      :bit1;
  HQD_IQ_FETCHER_BUSY      :bit1;
  HQD_EOP_FETCHER_BUSY     :bit1;
  HQD_CONSUMED_RPTR_BUSY   :bit1;
  HQD_FETCHER_ARB_BUSY     :bit1;
  HQD_ROQ_ALIGN_BUSY       :bit1;
  HQD_ROQ_EOP_BUSY         :bit1;
  HQD_ROQ_IQ_BUSY          :bit1;
  HQD_ROQ_PQ_BUSY          :bit1;
  HQD_ROQ_IB_BUSY          :bit1;
  HQD_WPTR_POLL_BUSY       :bit1;
  HQD_PQ_BUSY              :bit1;
  HQD_IB_BUSY              :bit1;
 end;

 TCP_DMA_READ_TAGS=bitpacked record
  DMA_READ_TAG      :bit26;
  RESERVED0         :bit2;
  DMA_READ_TAG_VALID:bit1;
  RESERVED1         :bit3;
 end;

 TCP_GDS_BKUP_ADDR=bit32;

 TCP_HQD_EOP_DONES=bit32;

 TCP_IQ_WAIT_TIME1=bitpacked record
  IB_OFFLOAD    :bit8;
  ATOMIC_OFFLOAD:bit8;
  WRM_OFFLOAD   :bit8;
  GWS           :bit8;
 end;

 TCP_IQ_WAIT_TIME2=bitpacked record
  QUE_SLEEP:bit8;
  SCH_WAVE :bit8;
  SEM_REARM:bit8;
  DEQ_RETRY:bit8;
 end;

 TCP_ME_PREEMPTION=bitpacked record
  OBSOLETE :bit1;
  RESERVED0:bit31;
 end;

 TCP_MQD_BASE_ADDR=bitpacked record
  RESERVED0:bit2;
  BASE_ADDR:bit30;
 end;

 TCP_RB0_RPTR_ADDR=bitpacked record
  RB_RPTR_SWAP:bit2;
  RB_RPTR_ADDR:bit30;
 end;

 TCP_RB1_RPTR_ADDR=bitpacked record
  RB_RPTR_SWAP:bit2;
  RB_RPTR_ADDR:bit30;
 end;

 TCP_RB2_RPTR_ADDR=bitpacked record
  RB_RPTR_SWAP:bit2;
  RB_RPTR_ADDR:bit30;
 end;

 TCP_RB_WPTR_DELAY=bitpacked record
  PRE_WRITE_TIMER:bit28;
  PRE_WRITE_LIMIT:bit4;
 end;

 TCP_SAMPLE_STATUS=bitpacked record
  Z_PASS_ACITVE       :bit1;
  STREAMOUT_ACTIVE    :bit1;
  PIPELINE_ACTIVE     :bit1;
  STIPPLE_ACTIVE      :bit1;
  VGT_BUFFERS_ACTIVE  :bit1;
  SCREEN_EXT_ACTIVE   :bit1;
  DRAW_INDIRECT_ACTIVE:bit1;
  DISP_INDIRECT_ACTIVE:bit1;
  RESERVED0           :bit24;
 end;

 TCP_SCRATCH_INDEX=bitpacked record
  SCRATCH_INDEX:bit8;
  RESERVED0    :bit24;
 end;

 TCP_STALLED_STAT1=bitpacked record
  RBIU_TO_DMA_NOT_RDY_TO_RCV   :bit1;
  RESERVED0                    :bit1;
  RBIU_TO_SEM_NOT_RDY_TO_RCV   :bit1;
  RESERVED1                    :bit1;
  RBIU_TO_MEMWR_NOT_RDY_TO_RCV :bit1;
  RESERVED2                    :bit5;
  ME_HAS_ACTIVE_CE_BUFFER_FLAG :bit1;
  ME_HAS_ACTIVE_DE_BUFFER_FLAG :bit1;
  ME_STALLED_ON_TC_WR_CONFIRM  :bit1;
  ME_STALLED_ON_ATOMIC_RTN_DATA:bit1;
  ME_WAITING_ON_TC_READ_DATA   :bit1;
  ME_WAITING_ON_REG_READ_DATA  :bit1;
  RESERVED3                    :bit7;
  RCIU_WAITING_ON_GDS_FREE     :bit1;
  RCIU_WAITING_ON_GRBM_FREE    :bit1;
  RCIU_WAITING_ON_VGT_FREE     :bit1;
  RCIU_STALLED_ON_ME_READ      :bit1;
  RCIU_STALLED_ON_DMA_READ     :bit1;
  RCIU_STALLED_ON_APPEND_READ  :bit1;
  RCIU_HALTED_BY_REG_VIOLATION :bit1;
  RESERVED4                    :bit2;
 end;

 TCP_STALLED_STAT2=bitpacked record
  PFP_TO_CSF_NOT_RDY_TO_RCV      :bit1;
  PFP_TO_MEQ_NOT_RDY_TO_RCV      :bit1;
  PFP_TO_RCIU_NOT_RDY_TO_RCV     :bit1;
  RESERVED0                      :bit1;
  PFP_TO_VGT_WRITES_PENDING      :bit1;
  PFP_RCIU_READ_PENDING          :bit1;
  PFP_MIU_READ_PENDING           :bit1;
  PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV:bit1;
  PFP_WAITING_ON_BUFFER_DATA     :bit1;
  ME_WAIT_ON_CE_COUNTER          :bit1;
  ME_WAIT_ON_AVAIL_BUFFER        :bit1;
  GFX_CNTX_NOT_AVAIL_TO_ME       :bit1;
  ME_RCIU_NOT_RDY_TO_RCV         :bit1;
  ME_TO_CONST_NOT_RDY_TO_RCV     :bit1;
  ME_WAITING_DATA_FROM_PFP       :bit1;
  ME_WAITING_ON_PARTIAL_FLUSH    :bit1;
  MEQ_TO_ME_NOT_RDY_TO_RCV       :bit1;
  STQ_TO_ME_NOT_RDY_TO_RCV       :bit1;
  ME_WAITING_DATA_FROM_STQ       :bit1;
  PFP_STALLED_ON_TC_WR_CONFIRM   :bit1;
  PFP_STALLED_ON_ATOMIC_RTN_DATA :bit1;
  EOPD_FIFO_NEEDS_SC_EOP_DONE    :bit1;
  EOPD_FIFO_NEEDS_WR_CONFIRM     :bit1;
  STRMO_WR_OF_PRIM_DATA_PENDING  :bit1;
  PIPE_STATS_WR_DATA_PENDING     :bit1;
  APPEND_RDY_WAIT_ON_CS_DONE     :bit1;
  APPEND_RDY_WAIT_ON_PS_DONE     :bit1;
  APPEND_WAIT_ON_WR_CONFIRM      :bit1;
  APPEND_ACTIVE_PARTITION        :bit1;
  APPEND_WAITING_TO_SEND_MEMWRITE:bit1;
  SURF_SYNC_NEEDS_IDLE_CNTXS     :bit1;
  SURF_SYNC_NEEDS_ALL_CLEAN      :bit1;
 end;

 TCP_STALLED_STAT3=bitpacked record
  CE_TO_CSF_NOT_RDY_TO_RCV                :bit1;
  CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV   :bit1;
  CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER:bit1;
  CE_TO_RAM_INIT_NOT_RDY                  :bit1;
  CE_TO_RAM_DUMP_NOT_RDY                  :bit1;
  CE_TO_RAM_WRITE_NOT_RDY                 :bit1;
  CE_TO_INC_FIFO_NOT_RDY_TO_RCV           :bit1;
  CE_TO_WR_FIFO_NOT_RDY_TO_RCV            :bit1;
  CE_TO_MIU_WRITE_NOT_RDY_TO_RCV          :bit1;
  RESERVED0                               :bit1;
  CE_WAITING_ON_BUFFER_DATA               :bit1;
  CE_WAITING_ON_CE_BUFFER_FLAG            :bit1;
  CE_WAITING_ON_DE_COUNTER                :bit1;
  CE_WAITING_ON_DE_COUNTER_UNDERFLOW      :bit1;
  TCIU_WAITING_ON_FREE                    :bit1;
  TCIU_WAITING_ON_TAGS                    :bit1;
  CE_STALLED_ON_TC_WR_CONFIRM             :bit1;
  CE_STALLED_ON_ATOMIC_RTN_DATA           :bit1;
  ATCL2IU_WAITING_ON_FREE                 :bit1;
  ATCL2IU_WAITING_ON_TAGS                 :bit1;
  ATCL1_WAITING_ON_TRANS                  :bit1;
  RESERVED1                               :bit11;
 end;

 TCRTC_BLACK_COLOR=bitpacked record
  CRTC_BLACK_COLOR_B_CB:bit10;
  CRTC_BLACK_COLOR_G_Y :bit10;
  CRTC_BLACK_COLOR_R_CR:bit10;
  RESERVED0            :bit2;
 end;

 TCRTC_COUNT_RESET=bitpacked record
  CRTC_RESET_FRAME_COUNT:bit1;
  RESERVED0             :bit31;
 end;

 TCRTC_CRC0_DATA_B=bitpacked record
  CRC0_B_CB:bit16;
  RESERVED0:bit16;
 end;

 TCRTC_CRC1_DATA_B=bitpacked record
  CRC1_B_CB:bit16;
  RESERVED0:bit16;
 end;

 TCRTC_GSL_CONTROL=bitpacked record
  CRTC_GSL_CHECK_LINE_NUM  :bit14;
  RESERVED0                :bit2;
  CRTC_GSL_FORCE_DELAY     :bit5;
  RESERVED1                :bit7;
  CRTC_GSL_CHECK_ALL_FIELDS:bit1;
  RESERVED2                :bit3;
 end;

 TCRTC_UPDATE_LOCK=bitpacked record
  CRTC_UPDATE_LOCK:bit1;
  RESERVED0       :bit31;
 end;

 TCRTC_V_TOTAL_MAX=bitpacked record
  CRTC_V_TOTAL_MAX                           :bit14;
  RESERVED0                                  :bit2;
  CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING:bit1;
  RESERVED1                                  :bit15;
 end;

 TCRTC_V_TOTAL_MIN=bitpacked record
  CRTC_V_TOTAL_MIN:bit14;
  RESERVED0       :bit18;
 end;

 TDB_ALPHA_TO_MASK=bitpacked record
  ALPHA_TO_MASK_ENABLE :bit1;
  RESERVED0            :bit7;
  ALPHA_TO_MASK_OFFSET0:bit2;
  ALPHA_TO_MASK_OFFSET1:bit2;
  ALPHA_TO_MASK_OFFSET2:bit2;
  ALPHA_TO_MASK_OFFSET3:bit2;
  OFFSET_ROUND         :bit1;
  RESERVED1            :bit15;
 end;

 TDB_COUNT_CONTROL=bitpacked record
  ZPASS_INCREMENT_DISABLE:bit1;
  PERFECT_ZPASS_COUNTS   :bit1;
  RESERVED0              :bit2;
  SAMPLE_RATE            :bit3;
  RESERVED1              :bit1;
  ZPASS_ENABLE           :bit4;
  ZFAIL_ENABLE           :bit4;
  SFAIL_ENABLE           :bit4;
  DBFAIL_ENABLE          :bit4;
  SLICE_EVEN_ENABLE      :bit4;
  SLICE_ODD_ENABLE       :bit4;
 end;

 TDB_DEPTH_CONTROL=bitpacked record
  STENCIL_ENABLE                    :bit1;
  Z_ENABLE                          :bit1;
  Z_WRITE_ENABLE                    :bit1;
  DEPTH_BOUNDS_ENABLE               :bit1;
  ZFUNC                             :bit3;
  BACKFACE_ENABLE                   :bit1;
  STENCILFUNC                       :bit3;
  RESERVED0                         :bit9;
  STENCILFUNC_BF                    :bit3;
  RESERVED1                         :bit7;
  ENABLE_COLOR_WRITES_ON_DEPTH_FAIL :bit1;
  DISABLE_COLOR_WRITES_ON_DEPTH_PASS:bit1;
 end;

 TDB_HTILE_SURFACE=bitpacked record
  LINEAR                 :bit1;
  FULL_CACHE             :bit1;
  HTILE_USES_PRELOAD_WIN :bit1;
  PRELOAD                :bit1;
  PREFETCH_WIDTH         :bit6;
  PREFETCH_HEIGHT        :bit6;
  DST_OUTSIDE_ZERO_TO_ONE:bit1;
  TC_COMPATIBLE          :bit1;
  RESERVED0              :bit14;
 end;

 TDB_STENCIL_CLEAR=bitpacked record
  CLEAR    :bit8;
  RESERVED0:bit24;
 end;

 TDCCG_DS_DTO_INCR=bit32;

 TDCCG_GTC_CURRENT=bit32;

 TDCDEBUG_OUT_CNTL=bitpacked record
  DCDEBUG_BLOCK_SEL       :bit5;
  RESERVED0               :bit1;
  DCDEBUG_OUT_EN          :bit1;
  DCDEBUG_OUT_PIN_SEL     :bit1;
  DCDEBUG_OUT_TEST_DATA_EN:bit1;
  DCDEBUG_OUT_TEST_DATA   :bit12;
  DCDEBUG_OUT_SEL         :bit2;
  DCDEBUG_OUT_24BIT_SEL   :bit1;
  DCDEBUG_CLK_SEL         :bit5;
  RESERVED1               :bit3;
 end;

 TDCDEBUG_OUT_DATA=bit32;

 TDCFEV0_PG_CONFIG=bitpacked record
  DCFEV0_POWER_FORCEON:bit1;
  RESERVED0           :bit31;
 end;

 TDCFEV0_PG_ENABLE=bitpacked record
  DCFEV0_POWER_GATE:bit1;
  RESERVED0        :bit31;
 end;

 TDCFEV0_PG_STATUS=bitpacked record
  DCFEV0_PGFSM_READ_DATA    :bit24;
  DCFEV0_DEBUG_PWR_STATUS   :bit2;
  RESERVED0                 :bit2;
  DCFEV0_DESIRED_PWR_STATE  :bit1;
  DCFEV0_REQUESTED_PWR_STATE:bit1;
  DCFEV0_PGFSM_PWR_STATUS   :bit2;
 end;

 TDCFEV_DBG_CONFIG=bitpacked record
  DCFEV_DBG_EN :bit1;
  RESERVED0    :bit3;
  DCFEV_DBG_SEL:bit4;
  RESERVED1    :bit24;
 end;

 TDCFEV_SOFT_RESET=bitpacked record
  UNP_PIXPIPE_SOFT_RESET:bit1;
  UNP_REQ_SOFT_RESET    :bit1;
  SCLV_ALU_SOFT_RESET   :bit1;
  SCLV_SOFT_RESET       :bit1;
  CRTC_SOFT_RESET       :bit1;
  PSCLV_SOFT_RESET      :bit1;
  COL_MAN_SOFT_RESET    :bit1;
  RESERVED0             :bit25;
 end;

 TDCIO_IMPCAL_CNTL=bitpacked record
  CALR_CNTL_OVERRIDE :bit4;
  RESERVED0          :bit1;
  IMPCAL_SOFT_RESET  :bit1;
  RESERVED1          :bit2;
  IMPCAL_STATUS      :bit2;
  RESERVED2          :bit2;
  IMPCAL_ARB_STATE   :bit3;
  AUX_IMPCAL_INTERVAL:bit4;
  RESERVED3          :bit13;
 end;

 TDCIO_WRCMD_DELAY=bitpacked record
  UNIPHY_DELAY :bit4;
  DAC_DELAY    :bit4;
  DPHY_DELAY   :bit4;
  DCRXPHY_DELAY:bit4;
  RESERVED0    :bit16;
 end;

 TDCI_DEBUG_CONFIG=bitpacked record
  DCI_DBG_EN       :bit1;
  RESERVED0        :bit3;
  DCI_DBG_BLOCK_SEL:bit4;
  DCI_DBG_CLOCK_SEL:bit4;
  RESERVED1        :bit20;
 end;

 TDCI_MEM_PWR_CNTL=bitpacked record
  DMIF_RDREQ_MEM_PWR_FORCE:bit2;
  DMIF_RDREQ_MEM_PWR_DIS  :bit1;
  MCIF_RDREQ_MEM_PWR_FORCE:bit1;
  MCIF_RDREQ_MEM_PWR_DIS  :bit1;
  MCIF_WRREQ_MEM_PWR_FORCE:bit1;
  MCIF_WRREQ_MEM_PWR_DIS  :bit1;
  VGA_MEM_PWR_FORCE       :bit1;
  VGA_MEM_PWR_DIS         :bit1;
  DMCU_ERAM_MEM_PWR_FORCE :bit2;
  DMCU_ERAM_MEM_PWR_DIS   :bit1;
  DMCU_IRAM_MEM_PWR_FORCE :bit1;
  DMCU_IRAM_MEM_PWR_DIS   :bit1;
  FBC_MEM_PWR_FORCE       :bit2;
  FBC_MEM_PWR_DIS         :bit1;
  MCIF_MEM_PWR_FORCE      :bit2;
  MCIF_MEM_PWR_DIS        :bit1;
  MCIF_DWB_MEM_PWR_FORCE  :bit2;
  MCIF_DWB_MEM_PWR_DIS    :bit1;
  MCIF_CWB0_MEM_PWR_FORCE :bit2;
  MCIF_CWB0_MEM_PWR_DIS   :bit1;
  MCIF_CWB1_MEM_PWR_FORCE :bit2;
  MCIF_CWB1_MEM_PWR_DIS   :bit1;
  VIP_MEM_PWR_FORCE       :bit1;
  VIP_MEM_PWR_DIS         :bit1;
  RESERVED0               :bit1;
 end;

 TDCO_MEM_PWR_CTRL=bitpacked record
  I2C_LIGHT_SLEEP_FORCE:bit1;
  I2C_LIGHT_SLEEP_DIS  :bit1;
  TVOUT_LIGHT_SLEEP_DIS:bit1;
  MVP_LIGHT_SLEEP_DIS  :bit1;
  DPA_LIGHT_SLEEP_DIS  :bit1;
  DPB_LIGHT_SLEEP_DIS  :bit1;
  DPC_LIGHT_SLEEP_DIS  :bit1;
  DPD_LIGHT_SLEEP_DIS  :bit1;
  DPE_LIGHT_SLEEP_DIS  :bit1;
  DPF_LIGHT_SLEEP_DIS  :bit1;
  DPG_LIGHT_SLEEP_DIS  :bit1;
  HDMI0_MEM_PWR_FORCE  :bit2;
  HDMI0_MEM_PWR_DIS    :bit1;
  HDMI1_MEM_PWR_FORCE  :bit2;
  HDMI1_MEM_PWR_DIS    :bit1;
  HDMI2_MEM_PWR_FORCE  :bit2;
  HDMI2_MEM_PWR_DIS    :bit1;
  HDMI3_MEM_PWR_FORCE  :bit2;
  HDMI3_MEM_PWR_DIS    :bit1;
  HDMI4_MEM_PWR_FORCE  :bit2;
  HDMI4_MEM_PWR_DIS    :bit1;
  HDMI5_MEM_PWR_FORCE  :bit2;
  HDMI5_MEM_PWR_DIS    :bit1;
  HDMI6_MEM_PWR_FORCE  :bit2;
  HDMI6_MEM_PWR_DIS    :bit1;
 end;

 TDCP_RANDOM_SEEDS=bitpacked record
  DCP_RAND_R_SEED:bit8;
  DCP_RAND_G_SEED:bit8;
  DCP_RAND_B_SEED:bit8;
  RESERVED0      :bit8;
 end;

 TDC_GPIO_DDCVGA_A=bitpacked record
  DC_GPIO_DDCVGACLK_A :bit1;
  RESERVED0           :bit7;
  DC_GPIO_DDCVGADATA_A:bit1;
  RESERVED1           :bit23;
 end;

 TDC_GPIO_DDCVGA_Y=bitpacked record
  DC_GPIO_DDCVGACLK_Y :bit1;
  RESERVED0           :bit7;
  DC_GPIO_DDCVGADATA_Y:bit1;
  RESERVED1           :bit23;
 end;

 TDC_GPIO_GENLK_EN=bitpacked record
  DC_GPIO_GENLK_CLK_EN  :bit1;
  RESERVED0             :bit7;
  DC_GPIO_GENLK_VSYNC_EN:bit1;
  RESERVED1             :bit7;
  DC_GPIO_SWAPLOCK_A_EN :bit1;
  RESERVED2             :bit7;
  DC_GPIO_SWAPLOCK_B_EN :bit1;
  RESERVED3             :bit7;
 end;

 TDC_GPIO_HPD_MASK=bitpacked record
  DC_GPIO_HPD1_MASK    :bit1;
  DC_GPIO_RX_HPD_MASK  :bit1;
  DC_GPIO_RX_HPD_PD_DIS:bit1;
  DC_GPIO_RX_HPD_RX_SEL:bit1;
  DC_GPIO_HPD1_PD_DIS  :bit1;
  RESERVED0            :bit1;
  DC_GPIO_HPD1_RECV    :bit1;
  RESERVED1            :bit1;
  DC_GPIO_HPD2_MASK    :bit1;
  DC_GPIO_HPD2_PD_DIS  :bit1;
  DC_GPIO_HPD2_RECV    :bit1;
  RESERVED2            :bit5;
  DC_GPIO_HPD3_MASK    :bit1;
  DC_GPIO_HPD3_PD_DIS  :bit1;
  DC_GPIO_HPD3_RECV    :bit1;
  RESERVED3            :bit1;
  DC_GPIO_HPD4_MASK    :bit1;
  DC_GPIO_HPD4_PD_DIS  :bit1;
  DC_GPIO_HPD4_RECV    :bit1;
  RESERVED4            :bit1;
  DC_GPIO_HPD5_MASK    :bit1;
  DC_GPIO_HPD5_PD_DIS  :bit1;
  DC_GPIO_HPD5_RECV    :bit1;
  RESERVED5            :bit1;
  DC_GPIO_HPD6_MASK    :bit1;
  DC_GPIO_HPD6_PD_DIS  :bit1;
  DC_GPIO_HPD6_RECV    :bit1;
  RESERVED6            :bit1;
 end;

 TDC_GPIO_I2CPAD_A=bitpacked record
  DC_GPIO_SCL_A:bit1;
  DC_GPIO_SDA_A:bit1;
  RESERVED0    :bit30;
 end;

 TDC_GPIO_I2CPAD_Y=bitpacked record
  DC_GPIO_SCL_Y:bit1;
  DC_GPIO_SDA_Y:bit1;
  RESERVED0    :bit30;
 end;

 TDC_GPIO_PWRSEQ_A=bitpacked record
  DC_GPIO_BLON_A    :bit1;
  RESERVED0         :bit7;
  DC_GPIO_DIGON_A   :bit1;
  RESERVED1         :bit7;
  DC_GPIO_ENA_BL_A  :bit1;
  RESERVED2         :bit7;
  DC_GPIO_VSYNC_IN_A:bit1;
  RESERVED3         :bit6;
  DC_GPIO_HSYNC_IN_A:bit1;
 end;

 TDC_GPIO_PWRSEQ_Y=bitpacked record
  DC_GPIO_BLON_Y  :bit1;
  RESERVED0       :bit7;
  DC_GPIO_DIGON_Y :bit1;
  RESERVED1       :bit7;
  DC_GPIO_ENA_BL_Y:bit1;
  RESERVED2       :bit7;
  DC_GPIO_VSYNC_IN:bit1;
  RESERVED3       :bit6;
  DC_GPIO_HSYNC_IN:bit1;
 end;

 TDC_GPIO_SYNCA_EN=bitpacked record
  DC_GPIO_HSYNCA_EN:bit1;
  RESERVED0        :bit7;
  DC_GPIO_VSYNCA_EN:bit1;
  RESERVED1        :bit23;
 end;

 TDC_I2C_SW_STATUS=bitpacked record
  DC_I2C_SW_STATUS         :bit2;
  DC_I2C_SW_DONE           :bit1;
  RESERVED0                :bit1;
  DC_I2C_SW_ABORTED        :bit1;
  DC_I2C_SW_TIMEOUT        :bit1;
  DC_I2C_SW_INTERRUPTED    :bit1;
  DC_I2C_SW_BUFFER_OVERFLOW:bit1;
  DC_I2C_SW_STOPPED_ON_NACK:bit1;
  RESERVED1                :bit3;
  DC_I2C_SW_NACK0          :bit1;
  DC_I2C_SW_NACK1          :bit1;
  DC_I2C_SW_NACK2          :bit1;
  DC_I2C_SW_NACK3          :bit1;
  RESERVED2                :bit2;
  DC_I2C_SW_REQ            :bit1;
  RESERVED3                :bit13;
 end;

 TDC_LUT_SEQ_COLOR=bitpacked record
  DC_LUT_SEQ_COLOR:bit16;
  RESERVED0       :bit16;
 end;

 TDIDT_DB_CTRL_OCP=bitpacked record
  UNUSED_0     :bit16;
  OCP_MAX_POWER:bit16;
 end;

 TDIDT_SQ_CTRL_OCP=bitpacked record
  UNUSED_0     :bit16;
  OCP_MAX_POWER:bit16;
 end;

 TDIDT_TD_CTRL_OCP=bitpacked record
  UNUSED_0     :bit16;
  OCP_MAX_POWER:bit16;
 end;

 TDIG_TEST_PATTERN=bitpacked record
  DIG_TEST_PATTERN_OUT_EN           :bit1;
  DIG_HALF_CLOCK_PATTERN_SEL        :bit1;
  LVDS_TEST_CLOCK_DATA              :bit1;
  RESERVED0                         :bit1;
  DIG_RANDOM_PATTERN_OUT_EN         :bit1;
  DIG_RANDOM_PATTERN_RESET          :bit1;
  DIG_TEST_PATTERN_EXTERNAL_RESET_EN:bit1;
  RESERVED1                         :bit1;
  LVDS_EYE_PATTERN                  :bit1;
  RESERVED2                         :bit7;
  DIG_STATIC_TEST_PATTERN           :bit10;
  RESERVED3                         :bit6;
 end;

 TDMCU_FW_END_ADDR=bitpacked record
  FW_END_ADDR_LSB:bit8;
  FW_END_ADDR_MSB:bit8;
  RESERVED0      :bit16;
 end;

 TDMIF_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit9;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED5              :bit1;
 end;

 TDP_DPHY_CRC_CNTL=bitpacked record
  DPHY_CRC_FIELD:bit1;
  RESERVED0     :bit3;
  DPHY_CRC_SEL  :bit2;
  RESERVED1     :bit10;
  DPHY_CRC_MASK :bit8;
  RESERVED2     :bit8;
 end;

 TDP_MSE_MISC_CNTL=bitpacked record
  DP_MSE_BLANK_CODE       :bit1;
  RESERVED0               :bit3;
  DP_MSE_TIMESTAMP_MODE   :bit1;
  RESERVED1               :bit3;
  DP_MSE_ZERO_ENCODER     :bit1;
  RESERVED2               :bit7;
  DP_MSE_OUTPUT_DPDBG_DATA:bit1;
  RESERVED3               :bit15;
 end;

 TDP_MSE_RATE_CNTL=bitpacked record
  DP_MSE_RATE_Y:bit26;
  DP_MSE_RATE_X:bit6;
 end;

 TDP_SEC_TIMESTAMP=bitpacked record
  DP_SEC_TIMESTAMP_MODE:bit2;
  RESERVED0            :bit30;
 end;

 TDVO_VREF_CONTROL=bitpacked record
  DVO_VREFPON:bit1;
  DVO_VREFSEL:bit1;
  RESERVED0  :bit2;
  DVO_VREFCAL:bit4;
  RESERVED1  :bit24;
 end;

 TEXTERN_TRIG_CNTL=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit30;
 end;

 TGARLIC_FLUSH_REQ=bitpacked record
  FLUSH_REQ:bit1;
  RESERVED0:bit31;
 end;

 TGCK_SMC_IND_DATA=bit32;

 TGDS_ATOM_OFFSET0=bitpacked record
  OFFSET0:bit8;
  UNUSED :bit24;
 end;

 TGDS_ATOM_OFFSET1=bitpacked record
  OFFSET1:bit8;
  UNUSED :bit24;
 end;

 TGDS_ATOM_READ0_U=bit32;

 TGDS_ATOM_READ1_U=bit32;

 TGDS_EDC_GRBM_CNT=bitpacked record
  DED      :bit8;
  RESERVED0:bit8;
  SEC      :bit8;
  RESERVED1:bit8;
 end;

 TGDS_GWS_RESOURCE=bitpacked record
  FLAG       :bit1;
  COUNTER    :bit12;
  _TYPE      :bit1;
  DED        :bit1;
  RELEASE_ALL:bit1;
  HEAD_QUEUE :bit12;
  HEAD_VALID :bit1;
  HEAD_FLAG  :bit1;
  UNUSED1    :bit2;
 end;

 TGDS_OA_RING_SIZE=bit32;

 TGENERIC_I2C_DATA=bitpacked record
  GENERIC_I2C_DATA_RW    :bit1;
  RESERVED0              :bit7;
  GENERIC_I2C_DATA       :bit8;
  GENERIC_I2C_INDEX      :bit4;
  RESERVED1              :bit11;
  GENERIC_I2C_INDEX_WRITE:bit1;
 end;

 TGFX_PIPE_CONTROL=bitpacked record
  HYSTERESIS_CNT    :bit13;
  RESERVED0         :bit3;
  CONTEXT_SUSPEND_EN:bit1;
  RESERVED1         :bit15;
 end;

 TGMCON_LPT_TARGET=bit32;

 TGMCON_PGFSM_READ=bitpacked record
  READ_VALUE        :bit24;
  PGFSM_SELECT      :bit4;
  SERDES_MASTER_BUSY:bit1;
  RESERVED0         :bit3;
 end;

 TGPIOPAD_INT_STAT=bitpacked record
  GPIO_INT_STAT        :bit29;
  RESERVED0            :bit2;
  SW_INITIATED_INT_STAT:bit1;
 end;

 TGPIOPAD_INT_TYPE=bitpacked record
  GPIO_INT_TYPE        :bit29;
  RESERVED0            :bit2;
  SW_INITIATED_INT_TYPE:bit1;
 end;

 TGPIOPAD_RCVR_SEL=bitpacked record
  GPIO_RCVR_SEL:bit31;
  RESERVED0    :bit1;
 end;

 TGPIOPAD_STRENGTH=bitpacked record
  GPIO_STRENGTH_SN:bit4;
  GPIO_STRENGTH_SP:bit4;
  RESERVED0       :bit24;
 end;

 TGPU_BIST_CONTROL=bitpacked record
  STOP_ON_FAIL_HW     :bit1;
  STOP_ON_FAIL_CU_HARV:bit1;
  CU_HARV_LOOP_COUNT  :bit4;
  RESERVED0           :bit1;
  RESERVED            :bit17;
  GLOBAL_LOOP_COUNT   :bit8;
 end;

 TGRBM_READ_ERROR2=bitpacked record
  RESERVED0                 :bit17;
  READ_REQUESTER_SRBM       :bit1;
  READ_REQUESTER_RLC        :bit1;
  READ_REQUESTER_GDS_DMA    :bit1;
  READ_REQUESTER_ME0PIPE0_CF:bit1;
  READ_REQUESTER_ME0PIPE0_PF:bit1;
  READ_REQUESTER_ME0PIPE1_CF:bit1;
  READ_REQUESTER_ME0PIPE1_PF:bit1;
  READ_REQUESTER_ME1PIPE0   :bit1;
  READ_REQUESTER_ME1PIPE1   :bit1;
  READ_REQUESTER_ME1PIPE2   :bit1;
  READ_REQUESTER_ME1PIPE3   :bit1;
  READ_REQUESTER_ME2PIPE0   :bit1;
  READ_REQUESTER_ME2PIPE1   :bit1;
  READ_REQUESTER_ME2PIPE2   :bit1;
  READ_REQUESTER_ME2PIPE3   :bit1;
 end;

 TGRBM_TRAP_WD_MSK=bit32;

 TGRBM_WRITE_ERROR=bitpacked record
  WRITE_REQUESTER_RLC :bit1;
  WRITE_REQUESTER_SRBM:bit1;
  WRITE_SSRCID        :bit3;
  WRITE_VFID          :bit4;
  RESERVED0           :bit3;
  WRITE_VF            :bit1;
  WRITE_VMID          :bit4;
  RESERVED1           :bit3;
  WRITE_PIPEID        :bit2;
  WRITE_MEID          :bit2;
  RESERVED2           :bit7;
  WRITE_ERROR         :bit1;
 end;

 TGRPH_DFQ_CONTROL=bitpacked record
  GRPH_DFQ_RESET           :bit1;
  RESERVED0                :bit3;
  GRPH_DFQ_SIZE            :bit3;
  RESERVED1                :bit1;
  GRPH_DFQ_MIN_FREE_ENTRIES:bit3;
  RESERVED2                :bit21;
 end;

 THDP_MEMIO_STATUS=bitpacked record
  MEMIO_WR_STATUS:bit1;
  MEMIO_RD_STATUS:bit1;
  MEMIO_WR_ERROR :bit1;
  MEMIO_RD_ERROR :bit1;
  RESERVED0      :bit28;
 end;

 THDP_MEM_POWER_LS=bitpacked record
  LS_ENABLE:bit1;
  LS_SETUP :bit6;
  LS_HOLD  :bit6;
  RESERVED0:bit19;
 end;

 THDP_SW_SEMAPHORE=bit32;

 THDP_XDP_BUSY_STS=bitpacked record
  BUSY_BITS:bit18;
  RESERVED0:bit14;
 end;

 THDP_XDP_DBG_ADDR=bitpacked record
  STS :bit16;
  CTRL:bit16;
 end;

 THDP_XDP_DBG_DATA=bitpacked record
  STS :bit16;
  CTRL:bit16;
 end;

 THDP_XDP_DBG_MASK=bitpacked record
  STS :bit16;
  CTRL:bit16;
 end;

 THDP_XDP_P2P_BAR0=bitpacked record
  ADDR     :bit16;
  FLUSH    :bit4;
  VALID    :bit1;
  RESERVED0:bit11;
 end;

 THDP_XDP_P2P_BAR1=bitpacked record
  ADDR     :bit16;
  FLUSH    :bit4;
  VALID    :bit1;
  RESERVED0:bit11;
 end;

 THDP_XDP_P2P_BAR2=bitpacked record
  ADDR     :bit16;
  FLUSH    :bit4;
  VALID    :bit1;
  RESERVED0:bit11;
 end;

 THDP_XDP_P2P_BAR3=bitpacked record
  ADDR     :bit16;
  FLUSH    :bit4;
  VALID    :bit1;
  RESERVED0:bit11;
 end;

 THDP_XDP_P2P_BAR4=bitpacked record
  ADDR     :bit16;
  FLUSH    :bit4;
  VALID    :bit1;
  RESERVED0:bit11;
 end;

 THDP_XDP_P2P_BAR5=bitpacked record
  ADDR     :bit16;
  FLUSH    :bit4;
  VALID    :bit1;
  RESERVED0:bit11;
 end;

 THDP_XDP_P2P_BAR6=bitpacked record
  ADDR     :bit16;
  FLUSH    :bit4;
  VALID    :bit1;
  RESERVED0:bit11;
 end;

 THDP_XDP_P2P_BAR7=bitpacked record
  ADDR     :bit16;
  FLUSH    :bit4;
  VALID    :bit1;
  RESERVED0:bit11;
 end;

 THDP_XDP_SRBM_CFG=bitpacked record
  SRBM_CFG_REG_CLK_ENABLE_COUNT:bit6;
  SRBM_CFG_REG_CLK_GATING_DIS  :bit1;
  SRBM_CFG_WAKE_DYN_CLK        :bit1;
  RESERVED0                    :bit24;
 end;

 TIH_ACTIVE_FCN_ID=bitpacked record
  VF_ID   :bit4;
  RESERVED:bit27;
  PF_VF   :bit1;
 end;

 TIH_DOORBELL_RPTR=bitpacked record
  OFFSET   :bit21;
  RESERVED0:bit7;
  ENABLE   :bit1;
  RESERVED1:bit1;
  CAPTURED :bit1;
  RESERVED2:bit1;
 end;

 TINTERRUPT_STATUS=bitpacked record
  STREAM_0_INTERRUPT_STATUS  :bit1;
  STREAM_1_INTERRUPT_STATUS  :bit1;
  STREAM_2_INTERRUPT_STATUS  :bit1;
  STREAM_3_INTERRUPT_STATUS  :bit1;
  STREAM_4_INTERRUPT_STATUS  :bit1;
  STREAM_5_INTERRUPT_STATUS  :bit1;
  STREAM_6_INTERRUPT_STATUS  :bit1;
  STREAM_7_INTERRUPT_STATUS  :bit1;
  STREAM_8_INTERRUPT_STATUS  :bit1;
  STREAM_9_INTERRUPT_STATUS  :bit1;
  STREAM_10_INTERRUPT_STATUS :bit1;
  STREAM_11_INTERRUPT_STATUS :bit1;
  STREAM_12_INTERRUPT_STATUS :bit1;
  STREAM_13_INTERRUPT_STATUS :bit1;
  STREAM_14_INTERRUPT_STATUS :bit1;
  STREAM_15_INTERRUPT_STATUS :bit1;
  RESERVED0                  :bit14;
  CONTROLLER_INTERRUPT_STATUS:bit1;
  GLOBAL_INTERRUPT_STATUS    :bit1;
 end;

 TLBV_VLINE_STATUS=bitpacked record
  VLINE_OCCURRED      :bit1;
  RESERVED0           :bit3;
  VLINE_ACK           :bit1;
  RESERVED1           :bit7;
  VLINE_STAT          :bit1;
  RESERVED2           :bit3;
  VLINE_INTERRUPT     :bit1;
  VLINE_INTERRUPT_TYPE:bit1;
  RESERVED3           :bit14;
 end;

 TLB_BUFFER_STATUS=bitpacked record
  LB_BUFFER_EMPTY_MARGIN  :bit4;
  LB_BUFFER_EMPTY_STAT    :bit1;
  RESERVED0               :bit3;
  LB_BUFFER_EMPTY_OCCURRED:bit1;
  RESERVED1               :bit3;
  LB_BUFFER_EMPTY_ACK     :bit1;
  RESERVED2               :bit3;
  LB_BUFFER_FULL_STAT     :bit1;
  RESERVED3               :bit3;
  LB_BUFFER_FULL_OCCURRED :bit1;
  RESERVED4               :bit3;
  LB_BUFFER_FULL_ACK      :bit1;
  RESERVED5               :bit7;
 end;

 TLB_VBLANK_STATUS=bitpacked record
  VBLANK_OCCURRED      :bit1;
  RESERVED0            :bit3;
  VBLANK_ACK           :bit1;
  RESERVED1            :bit7;
  VBLANK_STAT          :bit1;
  RESERVED2            :bit3;
  VBLANK_INTERRUPT     :bit1;
  VBLANK_INTERRUPT_TYPE:bit1;
  RESERVED3            :bit14;
 end;

 TLB_VLINE2_STATUS=bitpacked record
  VLINE2_OCCURRED      :bit1;
  RESERVED0            :bit3;
  VLINE2_ACK           :bit1;
  RESERVED1            :bit7;
  VLINE2_STAT          :bit1;
  RESERVED2            :bit3;
  VLINE2_INTERRUPT     :bit1;
  VLINE2_INTERRUPT_TYPE:bit1;
  RESERVED3            :bit14;
 end;

 TLCAC_CPL_OVR_SEL=bit32;

 TLCAC_CPL_OVR_VAL=bit32;

 TLCAC_MC0_OVR_SEL=bit32;

 TLCAC_MC0_OVR_VAL=bit32;

 TLCAC_MC1_OVR_SEL=bit32;

 TLCAC_MC1_OVR_VAL=bit32;

 TLCAC_MC2_OVR_SEL=bit32;

 TLCAC_MC2_OVR_VAL=bit32;

 TLCAC_MC3_OVR_SEL=bit32;

 TLCAC_MC3_OVR_VAL=bit32;

 TLCAC_MC4_OVR_SEL=bit32;

 TLCAC_MC4_OVR_VAL=bit32;

 TLCAC_MC5_OVR_SEL=bit32;

 TLCAC_MC5_OVR_VAL=bit32;

 TLCAC_MC6_OVR_SEL=bit32;

 TLCAC_MC6_OVR_VAL=bit32;

 TLCAC_MC7_OVR_SEL=bit32;

 TLCAC_MC7_OVR_VAL=bit32;

 TLM_POWERCONTROL1=bitpacked record
  LMTxEn0      :bit1;
  LMTxClkEn0   :bit1;
  LMTxMargin0  :bit3;
  LMSkipBit0   :bit1;
  LMLaneUnused0:bit1;
  LMTxMarginEn0:bit1;
  LMDeemph0    :bit1;
  LMTxEn1      :bit1;
  LMTxClkEn1   :bit1;
  LMTxMargin1  :bit3;
  LMSkipBit1   :bit1;
  LMLaneUnused1:bit1;
  LMTxMarginEn1:bit1;
  LMDeemph1    :bit1;
  LMTxEn2      :bit1;
  LMTxClkEn2   :bit1;
  LMTxMargin2  :bit3;
  LMSkipBit2   :bit1;
  LMLaneUnused2:bit1;
  LMTxMarginEn2:bit1;
  LMDeemph2    :bit1;
  TxCoeffID0   :bit2;
  TxCoeffID1   :bit2;
  RESERVED0    :bit1;
 end;

 TLM_POWERCONTROL2=bitpacked record
  LMTxEn3      :bit1;
  LMTxClkEn3   :bit1;
  LMTxMargin3  :bit3;
  LMSkipBit3   :bit1;
  LMLaneUnused3:bit1;
  LMTxMarginEn3:bit1;
  LMDeemph3    :bit1;
  TxCoeffID2   :bit2;
  TxCoeffID3   :bit2;
  TxCoeff0     :bit6;
  TxCoeff1     :bit6;
  TxCoeff2     :bit6;
  RESERVED0    :bit1;
 end;

 TLM_POWERCONTROL3=bitpacked record
  TxCoeff3 :bit6;
  RxEqCtl0 :bit6;
  RxEqCtl1 :bit6;
  RxEqCtl2 :bit6;
  RxEqCtl3 :bit6;
  RESERVED0:bit2;
 end;

 TLM_POWERCONTROL4=bitpacked record
  LinkNum0:bit3;
  LinkNum1:bit3;
  LinkNum2:bit3;
  LinkNum3:bit3;
  LaneNum0:bit4;
  LaneNum1:bit4;
  LaneNum2:bit4;
  LaneNum3:bit4;
  SpcMode0:bit1;
  SpcMode1:bit1;
  SpcMode2:bit1;
  SpcMode3:bit1;
 end;

 TMAILBOX_INT_CNTL=bitpacked record
  VALID_INT_EN:bit1;
  ACK_INT_EN  :bit1;
  RESERVED0   :bit30;
 end;

 TMCIF_MEM_CONTROL=bitpacked record
  MCIFMEM_CACHE_MODE_DIS:bit1;
  RESERVED0             :bit3;
  MCIFMEM_CACHE_MODE    :bit2;
  RESERVED1             :bit2;
  MCIFMEM_CACHE_SIZE    :bit8;
  MCIFMEM_CACHE_PIPE    :bit3;
  MCIFMEM_CACHE_TYPE    :bit2;
  RESERVED2             :bit11;
 end;

 TMC_ARB_ADDR_HASH=bitpacked record
  BANK_XOR_ENABLE:bit4;
  COL_XOR        :bit8;
  ROW_XOR        :bit16;
  RESERVED0      :bit4;
 end;

 TMC_ARB_GECC2_CLI=bitpacked record
  NO_GECC_CLI0:bit8;
  NO_GECC_CLI1:bit8;
  NO_GECC_CLI2:bit8;
  NO_GECC_CLI3:bit8;
 end;

 TMC_ARB_RFSH_CNTL=bitpacked record
  ENABLE                  :bit1;
  URG0                    :bit5;
  URG1                    :bit5;
  ACCUM                   :bit1;
  SINGLE_BANK             :bit1;
  PUSH_SINGLE_BANK_REFRESH:bit1;
  PENDING_RATE_SEL        :bit3;
  REFSB_PER_PAGE          :bit1;
  RESERVED0               :bit1;
  RESERVED1               :bit13;
 end;

 TMC_ARB_RFSH_RATE=bitpacked record
  POWERMODE0:bit8;
  RESERVED0 :bit8;
  RESERVED1 :bit8;
  RESERVED2 :bit8;
 end;

 TMC_ARB_RTT_CNTL0=bitpacked record
  ENABLE             :bit1;
  START_IDLE         :bit1;
  START_R2W          :bit2;
  FLUSH_ON_ENTER     :bit1;
  HARSH_START        :bit1;
  TPS_HARSH_PRIORITY :bit1;
  TWRT_HARSH_PRIORITY:bit1;
  BREAK_ON_HARSH     :bit1;
  BREAK_ON_URGENTRD  :bit1;
  BREAK_ON_URGENTWR  :bit1;
  TRAIN_PERIOD       :bit3;
  START_R2W_RFSH     :bit1;
  DEBUG_RSV_0        :bit1;
  DEBUG_RSV_1        :bit1;
  DEBUG_RSV_2        :bit1;
  DEBUG_RSV_3        :bit1;
  DEBUG_RSV_4        :bit1;
  DEBUG_RSV_5        :bit1;
  DEBUG_RSV_6        :bit1;
  DEBUG_RSV_7        :bit1;
  DEBUG_RSV_8        :bit1;
  DATA_CNTL          :bit1;
  NEIGHBOR_BIT       :bit1;
  RESERVED0          :bit6;
 end;

 TMC_ARB_RTT_CNTL1=bitpacked record
  WINDOW_SIZE         :bit5;
  WINDOW_UPDATE       :bit1;
  WINDOW_INC_THRESHOLD:bit7;
  WINDOW_DEC_THRESHOLD:bit7;
  WINDOW_SIZE_MAX     :bit5;
  WINDOW_SIZE_MIN     :bit5;
  WINDOW_UPDATE_COUNT :bit2;
 end;

 TMC_ARB_RTT_CNTL2=bitpacked record
  SAMPLE_CNT            :bit6;
  PHASE_ADJUST_THRESHOLD:bit6;
  PHASE_ADJUST_SIZE     :bit1;
  FILTER_CNTL           :bit1;
  RESERVED0             :bit18;
 end;

 TMC_ARB_RTT_DEBUG=bitpacked record
  DEBUG_BYTE_CH0   :bit2;
  DEBUG_BYTE_CH1   :bit2;
  SHIFTED_PHASE_CH0:bit8;
  WINDOW_SIZE_CH0  :bit5;
  SHIFTED_PHASE_CH1:bit8;
  WINDOW_SIZE_CH1  :bit5;
  RESERVED0        :bit2;
 end;

 TMC_CG_CONFIG_MCD=bitpacked record
  MCD0_WR_ENABLE  :bit1;
  MCD1_WR_ENABLE  :bit1;
  MCD2_WR_ENABLE  :bit1;
  MCD3_WR_ENABLE  :bit1;
  MCD4_WR_ENABLE  :bit1;
  MCD5_WR_ENABLE  :bit1;
  MCD6_WR_ENABLE  :bit1;
  MCD7_WR_ENABLE  :bit1;
  MC_RD_ENABLE    :bit3;
  MC_RD_ENABLE_SUB:bit1;
  RESERVED0       :bit1;
  INDEX           :bit16;
  RESERVED1       :bit3;
 end;

 TMC_CITF_DAGB_DLY=bitpacked record
  DLY      :bit6;
  RESERVED0:bit10;
  CLI      :bit6;
  RESERVED1:bit2;
  POS      :bit6;
  RESERVED2:bit2;
 end;

 TMC_CITF_RET_MODE=bitpacked record
  INORDER_RD           :bit1;
  INORDER_WR           :bit1;
  REMPRI_RD            :bit1;
  REMPRI_WR            :bit1;
  LCLPRI_RD            :bit1;
  LCLPRI_WR            :bit1;
  RDRET_STALL_EN       :bit1;
  RDRET_STALL_THRESHOLD:bit8;
  RESERVED0            :bit17;
 end;

 TMC_FUS_DRAM_MODE=bitpacked record
  DCTSELINTLVADDR:bit3;
  DRAMTYPE       :bit3;
  DRAMHOLEOFFSET :bit9;
  RESERVED0      :bit17;
 end;

 TMC_GRUB_FEATURES=bitpacked record
  WR_COMBINE_OFF         :bit1;
  SCLK_CG_DISABLE        :bit1;
  PRB_FILTER_DISABLE     :bit1;
  ARB_NRT_STACK_DISABLE  :bit1;
  ARB_FIXED_PRIORITY     :bit1;
  PRIORITY_UPDATE_DISABLE:bit1;
  RT_BYPASS_OFF          :bit1;
  SYNC_ON_ERROR_DISABLE  :bit1;
  SYNC_REFLECT_DISABLE   :bit1;
  RESERVED0              :bit1;
  ARB_STALL_EN           :bit1;
  CREDIT_STALL_EN        :bit1;
  ARB_STALL_SET_SEL      :bit2;
  ARB_STALL_CLR_SEL      :bit2;
  CREDIT_STALL_SET_SEL   :bit2;
  CREDIT_STALL_CLR_SEL   :bit2;
  WR_REORDER_OFF         :bit1;
  RESERVED1              :bit11;
 end;

 TMC_HUB_RDREQ_HDP=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_RLC=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_SEM=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_SIP=bitpacked record
  ASK_CREDITS    :bit7;
  MED_CREDIT_SEL :bit1;
  DISPLAY_CREDITS:bit7;
  RESERVED0      :bit17;
 end;

 TMC_HUB_RDREQ_SMU=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_TLS=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_UMC=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  VM_BYPASS            :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit14;
 end;

 TMC_HUB_RDREQ_UVD=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  VM_BYPASS            :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit14;
 end;

 TMC_HUB_RDREQ_VMC=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_VP8=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_WDP_SDMA0=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_SDMA1=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_VCEU0=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_VCEU1=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_XDMAM=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_IO_DEBUG_UP_0=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_1=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_2=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_3=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_4=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_5=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_6=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_7=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_8=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_9=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_RPB_TCI_CNTL2=bitpacked record
  TCI_POLICY      :bit1;
  TCI_MTYPE       :bit2;
  TCI_SNOOP       :bit1;
  TCI_PHYSICAL    :bit1;
  TCI_PERF_CNTR_EN:bit1;
  TCI_EXE         :bit1;
  RESERVED0       :bit25;
 end;

 TMC_SEQ_RD_CTL_D0=bitpacked record
  RCV_DLY  :bit3;
  RCV_EXT  :bit5;
  RST_SEL  :bit2;
  RST_HLD  :bit4;
  RESERVED0:bit1;
  RESERVED1:bit1;
  RBS_DLY  :bit5;
  RESERVED2:bit2;
  RESERVED3:bit1;
  RESERVED4:bit8;
 end;

 TMC_SEQ_RD_CTL_D1=bitpacked record
  RCV_DLY  :bit3;
  RCV_EXT  :bit5;
  RST_SEL  :bit2;
  RST_HLD  :bit4;
  RESERVED0:bit1;
  RESERVED1:bit1;
  RBS_DLY  :bit5;
  RESERVED2:bit2;
  RESERVED3:bit1;
  RESERVED4:bit8;
 end;

 TMC_SEQ_RESERVE_M=bit32;

 TMC_SEQ_SREG_READ=bit32;

 TMC_SEQ_SUP_R_PGM=bit32;

 TMC_SEQ_WR_CTL_D0=bitpacked record
  DAT_DLY  :bit5;
  DQS_DLY  :bit5;
  DQS_XTR  :bit1;
  OEN_DLY  :bit5;
  OEN_EXT  :bit4;
  OEN_SEL  :bit2;
  CMD_DLY  :bit1;
  ADR_DLY  :bit1;
  RESERVED0:bit8;
 end;

 TMC_SEQ_WR_CTL_D1=bitpacked record
  DAT_DLY  :bit5;
  DQS_DLY  :bit5;
  DQS_XTR  :bit1;
  OEN_DLY  :bit5;
  OEN_EXT  :bit4;
  OEN_SEL  :bit2;
  CMD_DLY  :bit1;
  ADR_DLY  :bit1;
  RESERVED0:bit8;
 end;

 TMC_VM_NB_PCI_ARB=bitpacked record
  RESERVED0:bit3;
  VGA_HOLE :bit1;
  RESERVED1:bit28;
 end;

 TMC_XBAR_ADDR_DEC=bitpacked record
  NO_DIV_BY_3   :bit1;
  GECC          :bit1;
  RB_SPLIT      :bit1;
  RB_SPLIT_COLHI:bit1;
  RESERVED0     :bit1;
  RESERVED1     :bit1;
  RESERVED2     :bit26;
 end;

 TMC_XPB_CLG_CFG10=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG11=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG12=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG13=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG14=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG15=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG16=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG17=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG18=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG19=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG20=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG21=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG22=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG23=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG24=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG25=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG26=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG27=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG28=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG29=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG30=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG31=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG32=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG33=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG34=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG35=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_CFG36=bitpacked record
  WCB_NUM   :bit4;
  LB_TYPE   :bit3;
  P2P_BAR   :bit3;
  HOST_FLUSH:bit4;
  SIDE_FLUSH:bit4;
  RESERVED0 :bit14;
 end;

 TMC_XPB_CLG_EXTRA=bitpacked record
  CMP0     :bit8;
  MSK0     :bit8;
  VLD0     :bit1;
  CMP1     :bit8;
  VLD1     :bit1;
  RESERVED0:bit6;
 end;

 TMC_XPB_INTF_CFG2=bitpacked record
  RPB_RDREQ_CRD:bit8;
  RESERVED0    :bit24;
 end;

 TMPLL_FUNC_CNTL_2=bitpacked record
  VCTRLADC_EN           :bit1;
  TEST_VCTL_EN          :bit1;
  RESET_EN              :bit1;
  TEST_BYPCLK_EN        :bit1;
  TEST_BYPCLK_SRC       :bit1;
  TEST_FBDIV_FRAC_BYPASS:bit1;
  TEST_BYPMCLK          :bit1;
  MPLL_UNLOCK_CLEAR     :bit1;
  TEST_VCTL_CNTRL       :bit1;
  TEST_FBDIV_SSC_BYPASS :bit1;
  RESET_TIMER           :bit2;
  PFD_RESET_CNTRL       :bit2;
  RESERVED0             :bit3;
  BACKUP_2              :bit3;
  LF_CNTRL              :bit7;
  BACKUP                :bit5;
 end;

 TMVP_FIFO_CONTROL=bitpacked record
  MVP_STOP_SLAVE_WM  :bit8;
  MVP_PAUSE_SLAVE_WM :bit8;
  MVP_PAUSE_SLAVE_CNT:bit8;
  RESERVED0          :bit8;
 end;

 TMVP_SLAVE_STATUS=bitpacked record
  MVP_SLAVE_PIXELS_PER_LINE_RCVED:bit13;
  RESERVED0                      :bit3;
  MVP_SLAVE_LINES_PER_FRAME_RCVED:bit13;
  RESERVED1                      :bit3;
 end;

 TPAGE_MIRROR_CNTL=bitpacked record
  PAGE_MIRROR_BASE_ADDR :bit24;
  PAGE_MIRROR_INVALIDATE:bit1;
  PAGE_MIRROR_ENABLE    :bit1;
  PAGE_MIRROR_USAGE     :bit2;
  RESERVED0             :bit4;
 end;

 TPA_CL_POINT_SIZE=bit32;

 TPA_SC_DEBUG_CNTL=bitpacked record
  SC_DEBUG_INDX:bit6;
  RESERVED0    :bit26;
 end;

 TPA_SC_DEBUG_DATA=bit32;

 TPA_SC_DEBUG_REG0=bitpacked record
  REG0_FIELD0:bit2;
  REG0_FIELD1:bit2;
  RESERVED0  :bit28;
 end;

 TPA_SC_DEBUG_REG1=bitpacked record
  REG1_FIELD0:bit2;
  REG1_FIELD1:bit2;
  RESERVED0  :bit28;
 end;

 TPA_SU_DEBUG_CNTL=bitpacked record
  SU_DEBUG_INDX:bit5;
  RESERVED0    :bit27;
 end;

 TPA_SU_DEBUG_DATA=bit32;

 TPA_SU_POINT_SIZE=bitpacked record
  HEIGHT:bit16;
  WIDTH :bit16;
 end;

 TPB0_PIF_GLB_OVRD=bitpacked record
  RXDETECT_OVERRIDE_VAL_0:bit1;
  RXDETECT_OVERRIDE_VAL_1:bit1;
  RXDETECT_OVERRIDE_VAL_2:bit1;
  RXDETECT_OVERRIDE_VAL_3:bit1;
  RXDETECT_OVERRIDE_VAL_4:bit1;
  RXDETECT_OVERRIDE_VAL_5:bit1;
  RXDETECT_OVERRIDE_VAL_6:bit1;
  RXDETECT_OVERRIDE_VAL_7:bit1;
  RESERVED0              :bit1;
  RESERVED1              :bit1;
  RESERVED2              :bit1;
  RESERVED3              :bit1;
  RESERVED4              :bit1;
  RESERVED5              :bit1;
  RESERVED6              :bit1;
  RESERVED7              :bit1;
  RXDETECT_OVERRIDE_EN   :bit1;
  RESERVED8              :bit15;
 end;

 TPB0_PIF_HW_DEBUG=bitpacked record
  HW_00_DEBUG:bit1;
  HW_01_DEBUG:bit1;
  HW_02_DEBUG:bit1;
  HW_03_DEBUG:bit1;
  HW_04_DEBUG:bit1;
  HW_05_DEBUG:bit1;
  HW_06_DEBUG:bit1;
  HW_07_DEBUG:bit1;
  HW_08_DEBUG:bit1;
  HW_09_DEBUG:bit1;
  HW_10_DEBUG:bit1;
  HW_11_DEBUG:bit1;
  HW_12_DEBUG:bit1;
  HW_13_DEBUG:bit1;
  HW_14_DEBUG:bit1;
  HW_15_DEBUG:bit1;
  RESERVED0  :bit16;
 end;

 TPB0_PIF_RX_CTRL2=bitpacked record
  RX_RDY_DASRT_COUNT     :bit3;
  RX_STATUS_DASRT_COUNT  :bit3;
  RXPHYSTATUS_DELAY      :bit3;
  RESERVED0              :bit7;
  FORCE_CDREN_IN_L0S     :bit1;
  EI_DET_CYCLE_MODE      :bit2;
  EI_DET_ON_TIME         :bit2;
  EI_DET_OFF_TIME        :bit3;
  EI_DET_CYCLE_DIS_IN_PS1:bit1;
  RX_CDR_XTND_MODE       :bit2;
  RX_L0S_TO_L0_DETECT_EI :bit1;
  RESERVED1              :bit4;
 end;

 TPB0_PIF_TX_CTRL2=bitpacked record
  TX_RDY_DASRT_COUNT    :bit3;
  TX_STATUS_DASRT_COUNT :bit3;
  TXPHYSTATUS_DELAY     :bit3;
  RESERVED0             :bit7;
  TX_HIGH_IMP_STAG_MP   :bit1;
  TX_HIGH_IMP_STAG_MODE :bit2;
  RESERVED1             :bit2;
  TX_FORCE_DATA_VALID   :bit1;
  TX_L0_TO_HIZ_DLY      :bit3;
  TX_FIFO_INIT_UPCONFIG :bit1;
  TX_HIZ_TO_L0_DLY      :bit3;
  TX_LINKSPEED_ACK_IN_S2:bit1;
  RESERVED2             :bit2;
 end;

 TPB1_PIF_GLB_OVRD=bitpacked record
  RXDETECT_OVERRIDE_VAL_0:bit1;
  RXDETECT_OVERRIDE_VAL_1:bit1;
  RXDETECT_OVERRIDE_VAL_2:bit1;
  RXDETECT_OVERRIDE_VAL_3:bit1;
  RXDETECT_OVERRIDE_VAL_4:bit1;
  RXDETECT_OVERRIDE_VAL_5:bit1;
  RXDETECT_OVERRIDE_VAL_6:bit1;
  RXDETECT_OVERRIDE_VAL_7:bit1;
  RESERVED0              :bit1;
  RESERVED1              :bit1;
  RESERVED2              :bit1;
  RESERVED3              :bit1;
  RESERVED4              :bit1;
  RESERVED5              :bit1;
  RESERVED6              :bit1;
  RESERVED7              :bit1;
  RXDETECT_OVERRIDE_EN   :bit1;
  RESERVED8              :bit15;
 end;

 TPB1_PIF_HW_DEBUG=bitpacked record
  HW_00_DEBUG:bit1;
  HW_01_DEBUG:bit1;
  HW_02_DEBUG:bit1;
  HW_03_DEBUG:bit1;
  HW_04_DEBUG:bit1;
  HW_05_DEBUG:bit1;
  HW_06_DEBUG:bit1;
  HW_07_DEBUG:bit1;
  HW_08_DEBUG:bit1;
  HW_09_DEBUG:bit1;
  HW_10_DEBUG:bit1;
  HW_11_DEBUG:bit1;
  HW_12_DEBUG:bit1;
  HW_13_DEBUG:bit1;
  HW_14_DEBUG:bit1;
  HW_15_DEBUG:bit1;
  RESERVED0  :bit16;
 end;

 TPB1_PIF_RX_CTRL2=bitpacked record
  RX_RDY_DASRT_COUNT     :bit3;
  RX_STATUS_DASRT_COUNT  :bit3;
  RXPHYSTATUS_DELAY      :bit3;
  RESERVED0              :bit7;
  FORCE_CDREN_IN_L0S     :bit1;
  EI_DET_CYCLE_MODE      :bit2;
  EI_DET_ON_TIME         :bit2;
  EI_DET_OFF_TIME        :bit3;
  EI_DET_CYCLE_DIS_IN_PS1:bit1;
  RX_CDR_XTND_MODE       :bit2;
  RX_L0S_TO_L0_DETECT_EI :bit1;
  RESERVED1              :bit4;
 end;

 TPB1_PIF_TX_CTRL2=bitpacked record
  TX_RDY_DASRT_COUNT    :bit3;
  TX_STATUS_DASRT_COUNT :bit3;
  TXPHYSTATUS_DELAY     :bit3;
  RESERVED0             :bit7;
  TX_HIGH_IMP_STAG_MP   :bit1;
  TX_HIGH_IMP_STAG_MODE :bit2;
  RESERVED1             :bit2;
  TX_FORCE_DATA_VALID   :bit1;
  TX_L0_TO_HIZ_DLY      :bit3;
  TX_FIFO_INIT_UPCONFIG :bit1;
  TX_HIZ_TO_L0_DLY      :bit3;
  TX_LINKSPEED_ACK_IN_S2:bit1;
  RESERVED2             :bit2;
 end;

 TPCIEP_STRAP_MISC=bitpacked record
  STRAP_REVERSE_LANES         :bit1;
  STRAP_E2E_PREFIX_EN         :bit1;
  STRAP_EXTENDED_FMT_SUPPORTED:bit1;
  STRAP_OBFF_SUPPORTED        :bit2;
  STRAP_LTR_SUPPORTED         :bit1;
  RESERVED0                   :bit26;
 end;

 TPCIE_CONFIG_CNTL=bitpacked record
  DYN_CLK_LATENCY              :bit4;
  RESERVED0                    :bit12;
  CI_MAX_PAYLOAD_SIZE_MODE     :bit1;
  CI_PRIV_MAX_PAYLOAD_SIZE     :bit3;
  CI_MAX_READ_REQUEST_SIZE_MODE:bit1;
  CI_PRIV_MAX_READ_REQUEST_SIZE:bit3;
  CI_MAX_READ_SAFE_MODE        :bit1;
  CI_EXTENDED_TAG_EN_OVERRIDE  :bit2;
  RESERVED1                    :bit5;
 end;

 TPCIE_F0_DPA_CNTL=bitpacked record
  SUBSTATE_STATUS    :bit5;
  RESERVED0          :bit3;
  DPA_COMPLIANCE_MODE:bit1;
  RESERVED1          :bit23;
 end;

 TPCIE_LC_CDR_CNTL=bitpacked record
  LC_CDR_TEST_OFF :bit12;
  LC_CDR_TEST_SETS:bit12;
  LC_CDR_SET_TYPE :bit2;
  RESERVED0       :bit6;
 end;

 TPCIE_STRAP_MISC2=bitpacked record
  RESERVED0              :bit1;
  STRAP_GEN2_COMPLIANCE  :bit1;
  STRAP_MSTCPL_TIMEOUT_EN:bit1;
  STRAP_GEN3_COMPLIANCE  :bit1;
  STRAP_TPH_SUPPORTED    :bit1;
  RESERVED1              :bit27;
 end;

 TPCIE_TX_LTR_CNTL=bitpacked record
  LTR_PRIV_S_SHORT_VALUE       :bit3;
  LTR_PRIV_S_LONG_VALUE        :bit3;
  LTR_PRIV_S_REQUIREMENT       :bit1;
  LTR_PRIV_NS_SHORT_VALUE      :bit3;
  LTR_PRIV_NS_LONG_VALUE       :bit3;
  LTR_PRIV_NS_REQUIREMENT      :bit1;
  LTR_PRIV_MSG_DIS_IN_PM_NON_D0:bit1;
  LTR_PRIV_RST_LTR_IN_DL_DOWN  :bit1;
  TX_CHK_FC_FOR_L1             :bit1;
  RESERVED0                    :bit15;
 end;

 TPERFCOUNTER_CNTL=bitpacked record
  PERFCOUNTER_EVENT_SEL         :bit9;
  PERFCOUNTER_CVALUE_SEL        :bit3;
  PERFCOUNTER_INC_MODE          :bit2;
  PERFCOUNTER_HW_CNTL_SEL       :bit1;
  PERFCOUNTER_RUNEN_MODE        :bit1;
  PERFCOUNTER_CNTOFF_SEL        :bit5;
  PERFCOUNTER_CNTOFF_START_DIS  :bit1;
  PERFCOUNTER_RESTART_EN        :bit1;
  PERFCOUNTER_INT_EN            :bit1;
  PERFCOUNTER_OFF_MASK          :bit1;
  PERFCOUNTER_ACTIVE            :bit1;
  PERFCOUNTER_INT_TYPE          :bit1;
  PERFCOUNTER_COUNTED_VALUE_TYPE:bit1;
  RESERVED0                     :bit1;
  PERFCOUNTER_CNTL_SEL          :bit3;
 end;

 TPRESCALE_CONTROL=bitpacked record
  PRESCALE_MODE:bit2;
  RESERVED0    :bit30;
 end;

 TREGAMMA_LUT_DATA=bitpacked record
  REGAMMA_LUT_DATA:bit19;
  RESERVED0       :bit13;
 end;

 TRLC_AUTO_PG_CTRL=bitpacked record
  AUTO_PG_EN                      :bit1;
  AUTO_GRBM_REG_SAVE_ON_IDLE_EN   :bit1;
  AUTO_WAKE_UP_EN                 :bit1;
  GRBM_REG_SAVE_GFX_IDLE_THRESHOLD:bit16;
  PG_AFTER_GRBM_REG_SAVE_THRESHOLD:bit13;
 end;

 TRLC_CP_RESPONSE0=bit32;

 TRLC_CP_RESPONSE1=bit32;

 TRLC_CP_RESPONSE2=bit32;

 TRLC_CP_RESPONSE3=bit32;

 TRLC_CSIB_ADDR_HI=bitpacked record
  ADDRESS  :bit16;
  RESERVED0:bit16;
 end;

 TRLC_CSIB_ADDR_LO=bit32;

 TRLC_DEBUG_SELECT=bitpacked record
  SELECT   :bit8;
  RESERVED0:bit6;
  RESERVED1:bit1;
  RESERVED :bit17;
 end;

 TRLC_GPM_LOG_ADDR=bit32;

 TRLC_GPM_LOG_CONT=bit32;

 TRLC_GPM_LOG_SIZE=bit32;

 TRLC_GPU_CLOCK_32=bit32;

 TRLC_LB_CNTR_INIT=bit32;

 TRLC_MEM_SLP_CNTL=bitpacked record
  RLC_MEM_LS_EN          :bit1;
  RLC_MEM_DS_EN          :bit1;
  RESERVED               :bit5;
  RLC_LS_DS_BUSY_OVERRIDE:bit1;
  RLC_MEM_LS_ON_DELAY    :bit8;
  RLC_MEM_LS_OFF_DELAY   :bit8;
  RESERVED1              :bit8;
 end;

 TRLC_PERFMON_CNTL=bitpacked record
  PERFMON_STATE        :bit3;
  RESERVED0            :bit7;
  PERFMON_SAMPLE_ENABLE:bit1;
  RESERVED1            :bit21;
 end;

 TRLC_RLCV_COMMAND=bitpacked record
  CMD     :bit4;
  RESERVED:bit28;
 end;

 TRLC_SPM_INT_CNTL=bitpacked record
  RLC_SPM_INT_CNTL:bit1;
  RESERVED0       :bit31;
 end;

 TROM_SMC_IND_DATA=bit32;

 TSAM_SAB_RBI_WPTR=bitpacked record
  RESERVED0:bit26;
  RESERVED1:bit6;
 end;

 TSAM_SAB_RBO_WPTR=bitpacked record
  RESERVED0:bit30;
  RESERVED1:bit2;
 end;

 TSCLK_PWRMGT_CNTL=bitpacked record
  SCLK_PWRMGT_OFF        :bit1;
  SCLK_LOW_D1            :bit1;
  DYN_PWR_DOWN_EN        :bit1;
  RESERVED0              :bit1;
  RESET_BUSY_CNT         :bit1;
  RESET_SCLK_CNT         :bit1;
  RESERVED1              :bit1;
  DYN_GFX_CLK_OFF_EN     :bit1;
  GFX_CLK_FORCE_ON       :bit1;
  GFX_CLK_REQUEST_OFF    :bit1;
  GFX_CLK_FORCE_OFF      :bit1;
  GFX_CLK_OFF_ACPI_D1    :bit1;
  GFX_CLK_OFF_ACPI_D2    :bit1;
  GFX_CLK_OFF_ACPI_D3    :bit1;
  DYN_LIGHT_SLEEP_EN     :bit1;
  AUTO_SCLK_PULSE_SKIP   :bit1;
  LIGHT_SLEEP_COUNTER    :bit5;
  DYNAMIC_PM_EN          :bit1;
  DPM_DYN_PWR_DOWN_CNTL  :bit1;
  DPM_DYN_PWR_DOWN_EN    :bit1;
  RESERVED2              :bit1;
  VOLTAGE_UPDATE_EN      :bit1;
  RESERVED3              :bit2;
  FORCE_PM0_INTERRUPT    :bit1;
  FORCE_PM1_INTERRUPT    :bit1;
  GFX_VOLTAGE_CHANGE_EN  :bit1;
  GFX_VOLTAGE_CHANGE_MODE:bit1;
 end;

 TSCLV_ALU_CONTROL=bitpacked record
  SCL_ALU_DISABLE:bit1;
  RESERVED0      :bit31;
 end;

 TSCLV_TAP_CONTROL=bitpacked record
  SCL_V_NUM_OF_TAPS  :bit3;
  RESERVED0          :bit1;
  SCL_H_NUM_OF_TAPS  :bit3;
  RESERVED1          :bit1;
  SCL_V_NUM_OF_TAPS_C:bit3;
  RESERVED2          :bit1;
  SCL_H_NUM_OF_TAPS_C:bit3;
  RESERVED3          :bit17;
 end;

 TSCL_ROUND_OFFSET=bitpacked record
  SCL_ROUND_OFFSET_RGB_Y:bit16;
  SCL_ROUND_OFFSET_CBCR :bit16;
 end;

 TSDMA0_EDC_CONFIG=bitpacked record
  RESERVED0     :bit1;
  DIS_EDC       :bit1;
  ECC_INT_ENABLE:bit1;
  RESERVED1     :bit29;
 end;

 TSDMA0_POWER_CNTL=bitpacked record
  RESERVED0         :bit8;
  MEM_POWER_OVERRIDE:bit1;
  MEM_POWER_LS_EN   :bit1;
  MEM_POWER_DS_EN   :bit1;
  MEM_POWER_SD_EN   :bit1;
  RESERVED1         :bit6;
  RESERVED2         :bit4;
  RESERVED3         :bit10;
 end;

 TSDMA0_STATUS_REG=bitpacked record
  IDLE                     :bit1;
  REG_IDLE                 :bit1;
  RB_EMPTY                 :bit1;
  RB_FULL                  :bit1;
  RB_CMD_IDLE              :bit1;
  RB_CMD_FULL              :bit1;
  IB_CMD_IDLE              :bit1;
  IB_CMD_FULL              :bit1;
  BLOCK_IDLE               :bit1;
  INSIDE_IB                :bit1;
  EX_IDLE                  :bit1;
  EX_IDLE_POLL_TIMER_EXPIRE:bit1;
  PACKET_READY             :bit1;
  MC_WR_IDLE               :bit1;
  SRBM_IDLE                :bit1;
  CONTEXT_EMPTY            :bit1;
  DELTA_RPTR_FULL          :bit1;
  RB_MC_RREQ_IDLE          :bit1;
  IB_MC_RREQ_IDLE          :bit1;
  MC_RD_IDLE               :bit1;
  DELTA_RPTR_EMPTY         :bit1;
  MC_RD_RET_STALL          :bit1;
  MC_RD_NO_POLL_IDLE       :bit1;
  RESERVED0                :bit1;
  RESERVED1                :bit1;
  PREV_CMD_IDLE            :bit1;
  SEM_IDLE                 :bit1;
  SEM_REQ_STALL            :bit1;
  SEM_RESP_STATE           :bit2;
  INT_IDLE                 :bit1;
  INT_REQ_STALL            :bit1;
 end;

 TSDMA0_UCODE_ADDR=bitpacked record
  VALUE    :bit13;
  RESERVED0:bit19;
 end;

 TSDMA0_UCODE_DATA=bit32;

 TSDMA1_EDC_CONFIG=bitpacked record
  RESERVED0     :bit1;
  DIS_EDC       :bit1;
  ECC_INT_ENABLE:bit1;
  RESERVED1     :bit29;
 end;

 TSDMA1_POWER_CNTL=bitpacked record
  RESERVED0         :bit8;
  MEM_POWER_OVERRIDE:bit1;
  MEM_POWER_LS_EN   :bit1;
  MEM_POWER_DS_EN   :bit1;
  MEM_POWER_SD_EN   :bit1;
  RESERVED1         :bit6;
  RESERVED2         :bit4;
  RESERVED3         :bit10;
 end;

 TSDMA1_STATUS_REG=bitpacked record
  IDLE                     :bit1;
  REG_IDLE                 :bit1;
  RB_EMPTY                 :bit1;
  RB_FULL                  :bit1;
  RB_CMD_IDLE              :bit1;
  RB_CMD_FULL              :bit1;
  IB_CMD_IDLE              :bit1;
  IB_CMD_FULL              :bit1;
  BLOCK_IDLE               :bit1;
  INSIDE_IB                :bit1;
  EX_IDLE                  :bit1;
  EX_IDLE_POLL_TIMER_EXPIRE:bit1;
  PACKET_READY             :bit1;
  MC_WR_IDLE               :bit1;
  SRBM_IDLE                :bit1;
  CONTEXT_EMPTY            :bit1;
  DELTA_RPTR_FULL          :bit1;
  RB_MC_RREQ_IDLE          :bit1;
  IB_MC_RREQ_IDLE          :bit1;
  MC_RD_IDLE               :bit1;
  DELTA_RPTR_EMPTY         :bit1;
  MC_RD_RET_STALL          :bit1;
  MC_RD_NO_POLL_IDLE       :bit1;
  RESERVED0                :bit1;
  RESERVED1                :bit1;
  PREV_CMD_IDLE            :bit1;
  SEM_IDLE                 :bit1;
  SEM_REQ_STALL            :bit1;
  SEM_RESP_STATE           :bit2;
  INT_IDLE                 :bit1;
  INT_REQ_STALL            :bit1;
 end;

 TSDMA1_UCODE_ADDR=bitpacked record
  VALUE    :bit13;
  RESERVED0:bit19;
 end;

 TSDMA1_UCODE_DATA=bit32;

 TSDMA_PGFSM_WRITE=bit32;

 TSEM_CHICKEN_BITS=bitpacked record
  VMID_PIPELINE_EN  :bit1;
  ENTRY_PIPELINE_EN :bit1;
  CHECK_COUNTER_EN  :bit1;
  ECC_BEHAVIOR      :bit2;
  SIGNAL_FAIL       :bit1;
  PHY_TRAN_EN       :bit1;
  ADDR_CMP_UNTRAN_EN:bit1;
  IDLE_COUNTER_INDEX:bit4;
  ATCL2_BUS_ID      :bit2;
  RESERVED0         :bit18;
 end;

 TSEM_PERFMON_CNTL=bitpacked record
  PERF_ENABLE0:bit1;
  PERF_CLEAR0 :bit1;
  PERF_SEL0   :bit8;
  PERF_ENABLE1:bit1;
  PERF_CLEAR1 :bit1;
  PERF_SEL1   :bit8;
  RESERVED0   :bit12;
 end;

 TSETUP_DEBUG_REG0=bitpacked record
  su_baryc_cntl_state:bit2;
  su_cntl_state      :bit4;
  RESERVED0          :bit2;
  pmode_state        :bit6;
  ge_stallb          :bit1;
  geom_enable        :bit1;
  su_clip_baryc_free :bit2;
  su_clip_rtr        :bit1;
  pfifo_busy         :bit1;
  su_cntl_busy       :bit1;
  geom_busy          :bit1;
  event_id_gated     :bit6;
  event_gated        :bit1;
  pmode_prim_gated   :bit1;
  su_dyn_sclk_vld    :bit1;
  cl_dyn_sclk_vld    :bit1;
 end;

 TSETUP_DEBUG_REG1=bitpacked record
  y_sort0_gated_23_8:bit16;
  x_sort0_gated_23_8:bit16;
 end;

 TSETUP_DEBUG_REG2=bitpacked record
  y_sort1_gated_23_8:bit16;
  x_sort1_gated_23_8:bit16;
 end;

 TSETUP_DEBUG_REG3=bitpacked record
  y_sort2_gated_23_8:bit16;
  x_sort2_gated_23_8:bit16;
 end;

 TSETUP_DEBUG_REG4=bitpacked record
  attr_indx_sort0_gated:bit14;
  null_prim_gated      :bit1;
  backfacing_gated     :bit1;
  st_indx_gated        :bit3;
  clipped_gated        :bit1;
  dealloc_slot_gated   :bit3;
  xmajor_gated         :bit1;
  diamond_rule_gated   :bit2;
  type_gated           :bit3;
  fpov_gated           :bit2;
  eop_gated            :bit1;
 end;

 TSETUP_DEBUG_REG5=bitpacked record
  attr_indx_sort2_gated:bit14;
  attr_indx_sort1_gated:bit14;
  provoking_vtx_gated  :bit2;
  valid_prim_gated     :bit1;
  pa_reg_sclk_vld      :bit1;
 end;

 TSH_MEM_APE1_BASE=bit32;

 TSLAVE_HANG_ERROR=bitpacked record
  SRBM_HANG_ERROR    :bit1;
  HDP_HANG_ERROR     :bit1;
  VGA_HANG_ERROR     :bit1;
  ROM_HANG_ERROR     :bit1;
  AUDIO_HANG_ERROR   :bit1;
  CEC_HANG_ERROR     :bit1;
  RESERVED0          :bit1;
  XDMA_HANG_ERROR    :bit1;
  DOORBELL_HANG_ERROR:bit1;
  GARLIC_HANG_ERROR  :bit1;
  RESERVED1          :bit22;
 end;

 TSMBUS_BACO_DUMMY=bit32;

 TSMU_PM_STATUS_10=bit32;

 TSMU_PM_STATUS_11=bit32;

 TSMU_PM_STATUS_12=bit32;

 TSMU_PM_STATUS_13=bit32;

 TSMU_PM_STATUS_14=bit32;

 TSMU_PM_STATUS_15=bit32;

 TSMU_PM_STATUS_16=bit32;

 TSMU_PM_STATUS_17=bit32;

 TSMU_PM_STATUS_18=bit32;

 TSMU_PM_STATUS_19=bit32;

 TSMU_PM_STATUS_20=bit32;

 TSMU_PM_STATUS_21=bit32;

 TSMU_PM_STATUS_22=bit32;

 TSMU_PM_STATUS_23=bit32;

 TSMU_PM_STATUS_24=bit32;

 TSMU_PM_STATUS_25=bit32;

 TSMU_PM_STATUS_26=bit32;

 TSMU_PM_STATUS_27=bit32;

 TSMU_PM_STATUS_28=bit32;

 TSMU_PM_STATUS_29=bit32;

 TSMU_PM_STATUS_30=bit32;

 TSMU_PM_STATUS_31=bit32;

 TSMU_PM_STATUS_32=bit32;

 TSMU_PM_STATUS_33=bit32;

 TSMU_PM_STATUS_34=bit32;

 TSMU_PM_STATUS_35=bit32;

 TSMU_PM_STATUS_36=bit32;

 TSMU_PM_STATUS_37=bit32;

 TSMU_PM_STATUS_38=bit32;

 TSMU_PM_STATUS_39=bit32;

 TSMU_PM_STATUS_40=bit32;

 TSMU_PM_STATUS_41=bit32;

 TSMU_PM_STATUS_42=bit32;

 TSMU_PM_STATUS_43=bit32;

 TSMU_PM_STATUS_44=bit32;

 TSMU_PM_STATUS_45=bit32;

 TSMU_PM_STATUS_46=bit32;

 TSMU_PM_STATUS_47=bit32;

 TSMU_PM_STATUS_48=bit32;

 TSMU_PM_STATUS_49=bit32;

 TSMU_PM_STATUS_50=bit32;

 TSMU_PM_STATUS_51=bit32;

 TSMU_PM_STATUS_52=bit32;

 TSMU_PM_STATUS_53=bit32;

 TSMU_PM_STATUS_54=bit32;

 TSMU_PM_STATUS_55=bit32;

 TSMU_PM_STATUS_56=bit32;

 TSMU_PM_STATUS_57=bit32;

 TSMU_PM_STATUS_58=bit32;

 TSMU_PM_STATUS_59=bit32;

 TSMU_PM_STATUS_60=bit32;

 TSMU_PM_STATUS_61=bit32;

 TSMU_PM_STATUS_62=bit32;

 TSMU_PM_STATUS_63=bit32;

 TSMU_PM_STATUS_64=bit32;

 TSMU_PM_STATUS_65=bit32;

 TSMU_PM_STATUS_66=bit32;

 TSMU_PM_STATUS_67=bit32;

 TSMU_PM_STATUS_68=bit32;

 TSMU_PM_STATUS_69=bit32;

 TSMU_PM_STATUS_70=bit32;

 TSMU_PM_STATUS_71=bit32;

 TSMU_PM_STATUS_72=bit32;

 TSMU_PM_STATUS_73=bit32;

 TSMU_PM_STATUS_74=bit32;

 TSMU_PM_STATUS_75=bit32;

 TSMU_PM_STATUS_76=bit32;

 TSMU_PM_STATUS_77=bit32;

 TSMU_PM_STATUS_78=bit32;

 TSMU_PM_STATUS_79=bit32;

 TSMU_PM_STATUS_80=bit32;

 TSMU_PM_STATUS_81=bit32;

 TSMU_PM_STATUS_82=bit32;

 TSMU_PM_STATUS_83=bit32;

 TSMU_PM_STATUS_84=bit32;

 TSMU_PM_STATUS_85=bit32;

 TSMU_PM_STATUS_86=bit32;

 TSMU_PM_STATUS_87=bit32;

 TSMU_PM_STATUS_88=bit32;

 TSMU_PM_STATUS_89=bit32;

 TSMU_PM_STATUS_90=bit32;

 TSMU_PM_STATUS_91=bit32;

 TSMU_PM_STATUS_92=bit32;

 TSMU_PM_STATUS_93=bit32;

 TSMU_PM_STATUS_94=bit32;

 TSMU_PM_STATUS_95=bit32;

 TSMU_PM_STATUS_96=bit32;

 TSMU_PM_STATUS_97=bit32;

 TSMU_PM_STATUS_98=bit32;

 TSMU_PM_STATUS_99=bit32;

 TSMU_RLC_RESPONSE=bit32;

 TSMU_SMC_IND_DATA=bit32;

 TSPI_ARB_CYCLES_0=bitpacked record
  TS0_DURATION:bit16;
  TS1_DURATION:bit16;
 end;

 TSPI_ARB_CYCLES_1=bitpacked record
  TS2_DURATION:bit16;
  TS3_DURATION:bit16;
 end;

 TSPI_ARB_PRIORITY=bitpacked record
  PIPE_ORDER_TS0:bit3;
  PIPE_ORDER_TS1:bit3;
  PIPE_ORDER_TS2:bit3;
  PIPE_ORDER_TS3:bit3;
  TS0_DUR_MULT  :bit2;
  TS1_DUR_MULT  :bit2;
  TS2_DUR_MULT  :bit2;
  TS3_DUR_MULT  :bit2;
  RESERVED0     :bit12;
 end;

 TSPI_CDBG_SYS_CS0=bitpacked record
  PIPE0:bit8;
  PIPE1:bit8;
  PIPE2:bit8;
  PIPE3:bit8;
 end;

 TSPI_CDBG_SYS_CS1=bitpacked record
  PIPE0:bit8;
  PIPE1:bit8;
  PIPE2:bit8;
  PIPE3:bit8;
 end;

 TSPI_CDBG_SYS_GFX=bitpacked record
  PS_EN    :bit1;
  VS_EN    :bit1;
  GS_EN    :bit1;
  ES_EN    :bit1;
  HS_EN    :bit1;
  LS_EN    :bit1;
  CS_EN    :bit1;
  RESERVED0:bit25;
 end;

 TSPI_PS_INPUT_ENA=bitpacked record
  PERSP_SAMPLE_ENA    :bit1;
  PERSP_CENTER_ENA    :bit1;
  PERSP_CENTROID_ENA  :bit1;
  PERSP_PULL_MODEL_ENA:bit1;
  LINEAR_SAMPLE_ENA   :bit1;
  LINEAR_CENTER_ENA   :bit1;
  LINEAR_CENTROID_ENA :bit1;
  LINE_STIPPLE_TEX_ENA:bit1;
  POS_X_FLOAT_ENA     :bit1;
  POS_Y_FLOAT_ENA     :bit1;
  POS_Z_FLOAT_ENA     :bit1;
  POS_W_FLOAT_ENA     :bit1;
  FRONT_FACE_ENA      :bit1;
  ANCILLARY_ENA       :bit1;
  SAMPLE_COVERAGE_ENA :bit1;
  POS_FIXED_PT_ENA    :bit1;
  RESERVED0           :bit16;
 end;

 TSPI_TMPRING_SIZE=bitpacked record
  WAVES    :bit12;
  WAVESIZE :bit13;
  RESERVED0:bit7;
 end;

 TSPMI_JTAG_OVER_0=bitpacked record
  SPMI_IF_JTAG_OVER_HAPPENED:bit1;
  RESERVED0                 :bit31;
 end;

 TSQ_CMD_TIMESTAMP=bitpacked record
  TIMESTAMP:bit8;
  RESERVED0:bit24;
 end;

 TSQ_REG_TIMESTAMP=bitpacked record
  TIMESTAMP:bit8;
  RESERVED0:bit24;
 end;

 TSQ_WAVE_INST_DW0=bit32;

 TSQ_WAVE_INST_DW1=bit32;

 TSRBM_READ_ERROR2=bitpacked record
  READ_REQUESTER_ACP :bit1;
  READ_REQUESTER_ISP :bit1;
  READ_REQUESTER_VCE1:bit1;
  RESERVED0          :bit20;
  READ_VF            :bit1;
  READ_VFID          :bit4;
  RESERVED1          :bit4;
 end;

 TTA_RESERVED_010C=bit32;

 TTHM_TMON0_STATUS=bitpacked record
  CURRENT_RDI:bit5;
  MEAS_DONE  :bit1;
  RESERVED0  :bit26;
 end;

 TTHM_TMON1_STATUS=bitpacked record
  CURRENT_RDI:bit5;
  MEAS_DONE  :bit1;
  RESERVED0  :bit26;
 end;

 TTHM_TMON2_CSR_RD=bitpacked record
  READ_DATA:bit12;
  RESERVED0:bit20;
 end;

 TTHM_TMON2_CSR_WR=bitpacked record
  CSR_WRITE :bit1;
  CSR_READ  :bit1;
  CSR_ADDR  :bit10;
  WRITE_DATA:bit12;
  SPARE     :bit1;
  RESERVED0 :bit7;
 end;

 TTHM_TMON2_STATUS=bitpacked record
  CURRENT_RDI:bit5;
  MEAS_DONE  :bit1;
  RESERVED0  :bit26;
 end;

 TUNIPHY_PLL_FBDIV=bitpacked record
  RESERVED0                :bit2;
  UNIPHY_PLL_FBDIV_FRACTION:bit14;
  UNIPHY_PLL_FBDIV         :bit12;
  RESERVED1                :bit4;
 end;

 TUNP_GRPH_CONTROL=bitpacked record
  GRPH_DEPTH                     :bit2;
  GRPH_NUM_BANKS                 :bit2;
  GRPH_Z                         :bit2;
  GRPH_BANK_WIDTH                :bit2;
  GRPH_FORMAT                    :bit3;
  GRPH_BANK_HEIGHT               :bit2;
  GRPH_TILE_SPLIT                :bit3;
  GRPH_ADDRESS_TRANSLATION_ENABLE:bit1;
  GRPH_PRIVILEGED_ACCESS_ENABLE  :bit1;
  GRPH_MACRO_TILE_ASPECT         :bit2;
  GRPH_ARRAY_MODE                :bit4;
  GRPH_PIPE_CONFIG               :bit5;
  GRPH_MICRO_TILE_MODE           :bit2;
  GRPH_COLOR_EXPANSION_MODE      :bit1;
 end;

 TUNP_GRPH_PITCH_C=bitpacked record
  GRPH_PITCH_C:bit15;
  RESERVED0   :bit17;
 end;

 TUNP_GRPH_PITCH_L=bitpacked record
  GRPH_PITCH_L:bit15;
  RESERVED0   :bit17;
 end;

 TUNP_GRPH_X_END_C=bitpacked record
  GRPH_X_END_C:bit15;
  RESERVED0   :bit17;
 end;

 TUNP_GRPH_X_END_L=bitpacked record
  GRPH_X_END_L:bit15;
  RESERVED0   :bit17;
 end;

 TUNP_GRPH_Y_END_C=bitpacked record
  GRPH_Y_END_C:bit15;
  RESERVED0   :bit17;
 end;

 TUNP_GRPH_Y_END_L=bitpacked record
  GRPH_Y_END_L:bit15;
  RESERVED0   :bit17;
 end;

 TUVD_CGC_MEM_CTRL=bitpacked record
  LMI_MC_LS_EN  :bit1;
  MPC_LS_EN     :bit1;
  MPRD_LS_EN    :bit1;
  WCB_LS_EN     :bit1;
  UDEC_RE_LS_EN :bit1;
  UDEC_CM_LS_EN :bit1;
  UDEC_IT_LS_EN :bit1;
  UDEC_DB_LS_EN :bit1;
  UDEC_MP_LS_EN :bit1;
  SYS_LS_EN     :bit1;
  VCPU_LS_EN    :bit1;
  SCPU_LS_EN    :bit1;
  MIF_LS_EN     :bit1;
  LCM_LS_EN     :bit1;
  JPEG_LS_EN    :bit1;
  JPEG2_LS_EN   :bit1;
  LS_SET_DELAY  :bit4;
  LS_CLEAR_DELAY:bit4;
  RESERVED0     :bit8;
 end;

 TUVD_LMI_ADDR_EXT=bitpacked record
  VCPU_ADDR_EXT    :bit4;
  CM_ADDR_EXT      :bit4;
  IT_ADDR_EXT      :bit4;
  VCPU_VM_ADDR_EXT :bit4;
  RE_ADDR_EXT      :bit4;
  MP_ADDR_EXT      :bit4;
  VCPU_NC0_ADDR_EXT:bit4;
  VCPU_NC1_ADDR_EXT:bit4;
 end;

 TUVD_MP_SWAP_CNTL=bitpacked record
  MP_REF0_MC_SWAP :bit2;
  MP_REF1_MC_SWAP :bit2;
  MP_REF2_MC_SWAP :bit2;
  MP_REF3_MC_SWAP :bit2;
  MP_REF4_MC_SWAP :bit2;
  MP_REF5_MC_SWAP :bit2;
  MP_REF6_MC_SWAP :bit2;
  MP_REF7_MC_SWAP :bit2;
  MP_REF8_MC_SWAP :bit2;
  MP_REF9_MC_SWAP :bit2;
  MP_REF10_MC_SWAP:bit2;
  MP_REF11_MC_SWAP:bit2;
  MP_REF12_MC_SWAP:bit2;
  MP_REF13_MC_SWAP:bit2;
  MP_REF14_MC_SWAP:bit2;
  MP_REF15_MC_SWAP:bit2;
 end;

 TUVD_PGFSM_CONFIG=bitpacked record
  UVD_PGFSM_FSM_ADDR  :bit8;
  UVD_PGFSM_POWER_DOWN:bit1;
  UVD_PGFSM_POWER_UP  :bit1;
  UVD_PGFSM_P1_SELECT :bit1;
  UVD_PGFSM_P2_SELECT :bit1;
  UVD_PGFSM_WRITE     :bit1;
  UVD_PGFSM_READ      :bit1;
  RESERVED0           :bit14;
  UVD_PGFSM_REG_ADDR  :bit4;
 end;

 TUVD_POWER_STATUS=bitpacked record
  UVD_POWER_STATUS        :bit2;
  UVD_PG_MODE             :bit1;
  UVD_STATUS_CHECK_TIMEOUT:bit1;
  PWR_ON_CHECK_TIMEOUT    :bit1;
  PWR_OFF_CHECK_TIMEOUT   :bit1;
  UVD_PGFSM_TIMEOUT_MODE  :bit2;
  UVD_PG_EN               :bit1;
  PAUSE_DPG_REQ           :bit1;
  PAUSE_DPG_ACK           :bit1;
  RESERVED0               :bit21;
 end;

 TVDDGFX_IDLE_EXIT=bitpacked record
  BIF_EXIT_REQ:bit1;
  RESERVED0   :bit31;
 end;

 TVGA_MAIN_CONTROL=bitpacked record
  VGA_CRTC_TIMEOUT                             :bit2;
  RESERVED0                                    :bit1;
  VGA_RENDER_TIMEOUT_COUNT                     :bit2;
  VGA_VIRTUAL_VERTICAL_RETRACE_DURATION        :bit3;
  VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT       :bit2;
  RESERVED1                                    :bit2;
  VGA_MC_WRITE_CLEAN_WAIT_DELAY                :bit4;
  VGA_READBACK_NO_DISPLAY_SOURCE_SELECT        :bit2;
  RESERVED2                                    :bit6;
  VGA_READBACK_CRT_INTR_SOURCE_SELECT          :bit2;
  VGA_READBACK_SENSE_SWITCH_SELECT             :bit1;
  VGA_READ_URGENT_ENABLE                       :bit1;
  VGA_WRITES_URGENT_ENABLE                     :bit1;
  VGA_EXTERNAL_DAC_SENSE                       :bit1;
  RESERVED3                                    :bit1;
  VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT:bit1;
 end;

 TVGA_MODE_CONTROL=bitpacked record
  VGA_ATI_LINEAR             :bit1;
  RESERVED0                  :bit3;
  VGA_LUT_PALETTE_UPDATE_MODE:bit2;
  RESERVED1                  :bit2;
  VGA_128K_APERTURE_PAGING   :bit1;
  RESERVED2                  :bit7;
  VGA_TEXT_132_COLUMNS_EN    :bit1;
  RESERVED3                  :bit15;
 end;

 TVGA_STATUS_CLEAR=bitpacked record
  VGA_MEM_ACCESS_INT_CLEAR       :bit1;
  RESERVED0                      :bit7;
  VGA_REG_ACCESS_INT_CLEAR       :bit1;
  RESERVED1                      :bit7;
  VGA_DISPLAY_SWITCH_INT_CLEAR   :bit1;
  RESERVED2                      :bit7;
  VGA_MODE_AUTO_TRIGGER_INT_CLEAR:bit1;
  RESERVED3                      :bit7;
 end;

 TVGA_TEST_CONTROL=bitpacked record
  VGA_TEST_ENABLE               :bit1;
  RESERVED0                     :bit7;
  VGA_TEST_RENDER_START         :bit1;
  RESERVED1                     :bit7;
  VGA_TEST_RENDER_DONE          :bit1;
  RESERVED2                     :bit7;
  VGA_TEST_RENDER_DISPBUF_SELECT:bit1;
  RESERVED3                     :bit7;
 end;

 TVGT_DMA_MAX_SIZE=bit32;

 TVGT_LS_HS_CONFIG=bitpacked record
  NUM_PATCHES     :bit8;
  HS_NUM_INPUT_CP :bit6;
  HS_NUM_OUTPUT_CP:bit6;
  RESERVED0       :bit12;
 end;

 TVGT_MAX_VTX_INDX=bit32;

 TVGT_MIN_VTX_INDX=bit32;

 TVGT_TF_RING_SIZE=bitpacked record
  SIZE     :bit16;
  RESERVED0:bit16;
 end;

 TVM_CONTEXT0_CNTL=bitpacked record
  ENABLE_CONTEXT                              :bit1;
  PAGE_TABLE_DEPTH                            :bit2;
  RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT     :bit1;
  RANGE_PROTECTION_FAULT_ENABLE_DEFAULT       :bit1;
  RESERVED0                                   :bit1;
  DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT:bit1;
  DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT  :bit1;
  RESERVED1                                   :bit1;
  PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT      :bit1;
  PDE0_PROTECTION_FAULT_ENABLE_DEFAULT        :bit1;
  PDE0_PROTECTION_FAULT_ENABLE_SAVE           :bit1;
  VALID_PROTECTION_FAULT_ENABLE_INTERRUPT     :bit1;
  VALID_PROTECTION_FAULT_ENABLE_DEFAULT       :bit1;
  VALID_PROTECTION_FAULT_ENABLE_SAVE          :bit1;
  READ_PROTECTION_FAULT_ENABLE_INTERRUPT      :bit1;
  READ_PROTECTION_FAULT_ENABLE_DEFAULT        :bit1;
  READ_PROTECTION_FAULT_ENABLE_SAVE           :bit1;
  WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT     :bit1;
  WRITE_PROTECTION_FAULT_ENABLE_DEFAULT       :bit1;
  WRITE_PROTECTION_FAULT_ENABLE_SAVE          :bit1;
  EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT   :bit1;
  EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT     :bit1;
  EXECUTE_PROTECTION_FAULT_ENABLE_SAVE        :bit1;
  PAGE_TABLE_BLOCK_SIZE                       :bit4;
  RESERVED2                                   :bit1;
  RESERVED3                                   :bit1;
  RESERVED4                                   :bit2;
 end;

 TVM_CONTEXT1_CNTL=bitpacked record
  ENABLE_CONTEXT                              :bit1;
  PAGE_TABLE_DEPTH                            :bit2;
  RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT     :bit1;
  RANGE_PROTECTION_FAULT_ENABLE_DEFAULT       :bit1;
  RESERVED0                                   :bit1;
  DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT:bit1;
  DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT  :bit1;
  RESERVED1                                   :bit1;
  PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT      :bit1;
  PDE0_PROTECTION_FAULT_ENABLE_DEFAULT        :bit1;
  PDE0_PROTECTION_FAULT_ENABLE_SAVE           :bit1;
  VALID_PROTECTION_FAULT_ENABLE_INTERRUPT     :bit1;
  VALID_PROTECTION_FAULT_ENABLE_DEFAULT       :bit1;
  VALID_PROTECTION_FAULT_ENABLE_SAVE          :bit1;
  READ_PROTECTION_FAULT_ENABLE_INTERRUPT      :bit1;
  READ_PROTECTION_FAULT_ENABLE_DEFAULT        :bit1;
  READ_PROTECTION_FAULT_ENABLE_SAVE           :bit1;
  WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT     :bit1;
  WRITE_PROTECTION_FAULT_ENABLE_DEFAULT       :bit1;
  WRITE_PROTECTION_FAULT_ENABLE_SAVE          :bit1;
  EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT   :bit1;
  EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT     :bit1;
  EXECUTE_PROTECTION_FAULT_ENABLE_SAVE        :bit1;
  PAGE_TABLE_BLOCK_SIZE                       :bit4;
  RESERVED2                                   :bit1;
  RESERVED3                                   :bit1;
  RESERVED4                                   :bit2;
 end;

 TXDMA_MSTR_HEIGHT=bitpacked record
  XDMA_MSTR_ACTIVE_HEIGHT:bit14;
  RESERVED0              :bit2;
  XDMA_MSTR_FRAME_HEIGHT :bit14;
  RESERVED1              :bit2;
 end;

 TXDMA_MSTR_STATUS=bitpacked record
  XDMA_MSTR_VCOUNT_CURRENT    :bit14;
  RESERVED0                   :bit2;
  XDMA_MSTR_WRITE_LINE_CURRENT:bit12;
  XDMA_MSTR_STATUS_SELECT     :bit3;
  RESERVED1                   :bit1;
 end;

 TAUDIO_DESCRIPTOR0=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR1=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR2=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR3=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR4=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR5=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR6=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR7=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR8=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR9=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUX_GTC_SYNC_DATA=bitpacked record
  AUX_GTC_DATA_RW                    :bit1;
  RESERVED0                          :bit7;
  AUX_GTC_DATA                       :bit8;
  AUX_GTC_INDEX                      :bit6;
  RESERVED1                          :bit9;
  AUX_GTC_INDEX_AUTOINCREMENT_DISABLE:bit1;
 end;

 TBIF_DOORBELL_CNTL=bitpacked record
  SELF_RING_DIS              :bit1;
  TRANS_CHECK_DIS            :bit1;
  UNTRANS_LBACK_EN           :bit1;
  NON_CONSECUTIVE_BE_ZERO_DIS:bit1;
  DOORBELL_MONITOR_EN        :bit1;
  DOORBELL_INTERRUPT_STATUS  :bit1;
  RESERVED0                  :bit10;
  DOORBELL_INTERRUPT_CLEAR   :bit1;
  RESERVED1                  :bit7;
  DB_MNTR_INTGEN_DIS         :bit1;
  DB_MNTR_INTGEN_MODE_0      :bit1;
  DB_MNTR_INTGEN_MODE_1      :bit1;
  DB_MNTR_INTGEN_MODE_2      :bit1;
  RESERVED2                  :bit4;
 end;

 TBIF_IMPCTL_RXCNTL=bitpacked record
  RX_ADJUST          :bit3;
  RX_BIAS_HIGH       :bit1;
  CONT_AFTER_RX_DECT :bit1;
  RESERVED0          :bit1;
  SUSPEND            :bit1;
  FORCE_RST          :bit1;
  LOWER_RX_ADJ_THRESH:bit4;
  LOWER_RX_ADJ       :bit1;
  UPPER_RX_ADJ_THRESH:bit4;
  UPPER_RX_ADJ       :bit1;
  RX_IMP_LOCKED      :bit1;
  RX_IMP_READBACK_SEL:bit1;
  RX_IMP_READBACK    :bit4;
  RESERVED1          :bit4;
  RX_CMP_AMBIG       :bit1;
  CAL_DONE           :bit1;
  RESERVED2          :bit2;
 end;

 TBIF_RFE_SNOOP_REG=bitpacked record
  REG_SNOOP_ARBITER  :bit1;
  REG_SNOOP_ALLMASTER:bit1;
  RESERVED0          :bit30;
 end;

 TBIF_RLC_INTR_CNTL=bitpacked record
  RLC_HVCMD_INTERRUPT:bit1;
  RESERVED0          :bit31;
 end;

 TBIF_VDDGFX_FB_CMP=bitpacked record
  VDDGFX_FB_HDP_CMP_EN   :bit1;
  VDDGFX_FB_HDP_STALL_EN :bit1;
  VDDGFX_FB_XDMA_CMP_EN  :bit1;
  VDDGFX_FB_XDMA_STALL_EN:bit1;
  VDDGFX_FB_VGA_CMP_EN   :bit1;
  VDDGFX_FB_VGA_STALL_EN :bit1;
  RESERVED0              :bit26;
 end;

 TCB_BLEND0_CONTROL=bitpacked record
  COLOR_SRCBLEND      :bit5;
  COLOR_COMB_FCN      :bit3;
  COLOR_DESTBLEND     :bit5;
  RESERVED0           :bit3;
  ALPHA_SRCBLEND      :bit5;
  ALPHA_COMB_FCN      :bit3;
  ALPHA_DESTBLEND     :bit5;
  SEPARATE_ALPHA_BLEND:bit1;
  ENABLE              :bit1;
  DISABLE_ROP3        :bit1;
 end;

 TCB_BLEND1_CONTROL=bitpacked record
  COLOR_SRCBLEND      :bit5;
  COLOR_COMB_FCN      :bit3;
  COLOR_DESTBLEND     :bit5;
  RESERVED0           :bit3;
  ALPHA_SRCBLEND      :bit5;
  ALPHA_COMB_FCN      :bit3;
  ALPHA_DESTBLEND     :bit5;
  SEPARATE_ALPHA_BLEND:bit1;
  ENABLE              :bit1;
  DISABLE_ROP3        :bit1;
 end;

 TCB_BLEND2_CONTROL=bitpacked record
  COLOR_SRCBLEND      :bit5;
  COLOR_COMB_FCN      :bit3;
  COLOR_DESTBLEND     :bit5;
  RESERVED0           :bit3;
  ALPHA_SRCBLEND      :bit5;
  ALPHA_COMB_FCN      :bit3;
  ALPHA_DESTBLEND     :bit5;
  SEPARATE_ALPHA_BLEND:bit1;
  ENABLE              :bit1;
  DISABLE_ROP3        :bit1;
 end;

 TCB_BLEND3_CONTROL=bitpacked record
  COLOR_SRCBLEND      :bit5;
  COLOR_COMB_FCN      :bit3;
  COLOR_DESTBLEND     :bit5;
  RESERVED0           :bit3;
  ALPHA_SRCBLEND      :bit5;
  ALPHA_COMB_FCN      :bit3;
  ALPHA_DESTBLEND     :bit5;
  SEPARATE_ALPHA_BLEND:bit1;
  ENABLE              :bit1;
  DISABLE_ROP3        :bit1;
 end;

 TCB_BLEND4_CONTROL=bitpacked record
  COLOR_SRCBLEND      :bit5;
  COLOR_COMB_FCN      :bit3;
  COLOR_DESTBLEND     :bit5;
  RESERVED0           :bit3;
  ALPHA_SRCBLEND      :bit5;
  ALPHA_COMB_FCN      :bit3;
  ALPHA_DESTBLEND     :bit5;
  SEPARATE_ALPHA_BLEND:bit1;
  ENABLE              :bit1;
  DISABLE_ROP3        :bit1;
 end;

 TCB_BLEND5_CONTROL=bitpacked record
  COLOR_SRCBLEND      :bit5;
  COLOR_COMB_FCN      :bit3;
  COLOR_DESTBLEND     :bit5;
  RESERVED0           :bit3;
  ALPHA_SRCBLEND      :bit5;
  ALPHA_COMB_FCN      :bit3;
  ALPHA_DESTBLEND     :bit5;
  SEPARATE_ALPHA_BLEND:bit1;
  ENABLE              :bit1;
  DISABLE_ROP3        :bit1;
 end;

 TCB_BLEND6_CONTROL=bitpacked record
  COLOR_SRCBLEND      :bit5;
  COLOR_COMB_FCN      :bit3;
  COLOR_DESTBLEND     :bit5;
  RESERVED0           :bit3;
  ALPHA_SRCBLEND      :bit5;
  ALPHA_COMB_FCN      :bit3;
  ALPHA_DESTBLEND     :bit5;
  SEPARATE_ALPHA_BLEND:bit1;
  ENABLE              :bit1;
  DISABLE_ROP3        :bit1;
 end;

 TCB_BLEND7_CONTROL=bitpacked record
  COLOR_SRCBLEND      :bit5;
  COLOR_COMB_FCN      :bit3;
  COLOR_DESTBLEND     :bit5;
  RESERVED0           :bit3;
  ALPHA_SRCBLEND      :bit5;
  ALPHA_COMB_FCN      :bit3;
  ALPHA_DESTBLEND     :bit5;
  SEPARATE_ALPHA_BLEND:bit1;
  ENABLE              :bit1;
  DISABLE_ROP3        :bit1;
 end;

 TCB_CGTT_SCLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCC_GC_PRIM_CONFIG=bitpacked record
  RESERVED0      :bit1;
  RESERVED1      :bit15;
  INACTIVE_IA    :bit2;
  RESERVED2      :bit6;
  INACTIVE_VGT_PA:bit4;
  RESERVED3      :bit4;
 end;

 TCC_MC_MAX_CHANNEL=bitpacked record
  RESERVED0:bit1;
  NOOFCHAN :bit4;
  RESERVED1:bit27;
 end;

 TCC_RB_DAISY_CHAIN=bitpacked record
  RB_0:bit4;
  RB_1:bit4;
  RB_2:bit4;
  RB_3:bit4;
  RB_4:bit4;
  RB_5:bit4;
  RB_6:bit4;
  RB_7:bit4;
 end;

 TCC_SCLK_VID_FUSES=bitpacked record
  SClkVid0:bit8;
  SClkVid1:bit8;
  SClkVid2:bit8;
  SClkVid3:bit8;
 end;

 TCC_SMU_MISC_FUSES=bitpacked record
  RESERVED0         :bit1;
  IOMMU_V2_DISABLE  :bit1;
  MinSClkDid        :bit7;
  MISC_SPARE        :bit2;
  PostResetGnbClkDid:bit7;
  L2IMU_tn2_dtc_half:bit1;
  L2IMU_tn2_ptc_half:bit1;
  L2IMU_tn2_itc_half:bit1;
  L2IMU_tn2_pdc_half:bit1;
  L2IMU_tn2_ptc_dis :bit1;
  L2IMU_tn2_itc_dis :bit1;
  RESERVED1         :bit3;
  VCE_DISABLE       :bit1;
  IOC_IOMMU_DISABLE :bit1;
  GNB_SPARE         :bit2;
  RESERVED2         :bit1;
 end;

 TCGTT_BCI_CLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED      :bit12;
  CORE6_OVERRIDE:bit1;
  CORE5_OVERRIDE:bit1;
  CORE4_OVERRIDE:bit1;
  CORE3_OVERRIDE:bit1;
  CORE2_OVERRIDE:bit1;
  CORE1_OVERRIDE:bit1;
  CORE0_OVERRIDE:bit1;
  REG_OVERRIDE  :bit1;
 end;

 TCGTT_CPC_CLK_CTRL=bitpacked record
  ON_DELAY             :bit4;
  OFF_HYSTERESIS       :bit8;
  RESERVED0            :bit17;
  SOFT_OVERRIDE_PERFMON:bit1;
  SOFT_OVERRIDE_DYN    :bit1;
  SOFT_OVERRIDE_REG    :bit1;
 end;

 TCGTT_CPF_CLK_CTRL=bitpacked record
  ON_DELAY             :bit4;
  OFF_HYSTERESIS       :bit8;
  RESERVED0            :bit17;
  SOFT_OVERRIDE_PERFMON:bit1;
  SOFT_OVERRIDE_DYN    :bit1;
  SOFT_OVERRIDE_REG    :bit1;
 end;

 TCGTT_GDS_CLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCGTT_RLC_CLK_CTRL=bitpacked record
  ON_DELAY         :bit4;
  OFF_HYSTERESIS   :bit8;
  RESERVED0        :bit18;
  SOFT_OVERRIDE_DYN:bit1;
  SOFT_OVERRIDE_REG:bit1;
 end;

 TCGTT_SPI_CLK_CTRL=bitpacked record
  ON_DELAY           :bit4;
  OFF_HYSTERESIS     :bit8;
  RESERVED0          :bit6;
  GRP5_CG_OFF_HYST   :bit6;
  GRP5_CG_OVERRIDE   :bit1;
  RESERVED1          :bit1;
  ALL_CLK_ON_OVERRIDE:bit1;
  GRP3_OVERRIDE      :bit1;
  GRP2_OVERRIDE      :bit1;
  GRP1_OVERRIDE      :bit1;
  GRP0_OVERRIDE      :bit1;
  REG_OVERRIDE       :bit1;
 end;

 TCGTT_SQG_CLK_CTRL=bitpacked record
  ON_DELAY        :bit4;
  OFF_HYSTERESIS  :bit8;
  RESERVED0       :bit16;
  TTRACE_OVERRIDE :bit1;
  PERFMON_OVERRIDE:bit1;
  CORE_OVERRIDE   :bit1;
  REG_OVERRIDE    :bit1;
 end;

 TCGTT_SX_CLK_CTRL0=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED      :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCGTT_SX_CLK_CTRL1=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED      :bit12;
  DBG_EN        :bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCGTT_SX_CLK_CTRL2=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED      :bit12;
  DBG_EN        :bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCGTT_SX_CLK_CTRL3=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED      :bit12;
  DBG_EN        :bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCGTT_SX_CLK_CTRL4=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED      :bit12;
  DBG_EN        :bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCGTT_TCI_CLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCGTT_TCP_CLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCGTT_VGT_CLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  PERF_ENABLE   :bit1;
  DBG_ENABLE    :bit1;
  SOFT_OVERRIDE4:bit1;
  TESS_OVERRIDE :bit1;
  GS_OVERRIDE   :bit1;
  CORE_OVERRIDE :bit1;
  REG_OVERRIDE  :bit1;
 end;

 TCG_CLKPIN_CNTL_DC=bitpacked record
  OSC_EN            :bit1;
  XTL_LOW_GAIN      :bit2;
  RESERVED0         :bit6;
  XTL_XOCLK_DRV_R_EN:bit1;
  XTALIN_SEL        :bit3;
  RESERVED1         :bit19;
 end;

 TCG_SPLL_FUNC_CNTL=bitpacked record
  SPLL_RESET          :bit1;
  SPLL_PWRON          :bit1;
  SPLL_DIVEN          :bit1;
  SPLL_BYPASS_EN      :bit1;
  SPLL_BYPASS_THRU_DFS:bit1;
  SPLL_REF_DIV        :bit6;
  SPLL_PDIV_A_UPDATE  :bit1;
  SPLL_PDIV_A_EN      :bit1;
  SPLL_BG_PWRON       :bit1;
  SPLL_BGADJ          :bit4;
  SPLL_PDIV_A         :bit7;
  SPLL_REG_BIAS       :bit3;
  SPLL_OTEST_LOCK_EN  :bit1;
  RESERVED0           :bit3;
 end;

 TCG_THERMAL_STATUS=bitpacked record
  SPARE       :bit9;
  FDO_PWM_DUTY:bit8;
  THERM_ALERT :bit1;
  GEN_STATUS  :bit4;
  RESERVED0   :bit10;
 end;

 TCLIENT0_OFFSET_HI=bit32;

 TCLIENT1_OFFSET_HI=bit32;

 TCLIENT2_OFFSET_HI=bit32;

 TCLIENT3_OFFSET_HI=bit32;

 TCLIENT4_OFFSET_HI=bit32;

 TCNV_TEST_CRC_BLUE=bitpacked record
  RESERVED0             :bit4;
  CNV_TEST_CRC_BLUE_MASK:bit12;
  CNV_TEST_CRC_SIG_BLUE :bit16;
 end;

 TCOHER_DEST_BASE_0=bit32;

 TCOHER_DEST_BASE_1=bit32;

 TCOHER_DEST_BASE_2=bit32;

 TCOHER_DEST_BASE_3=bit32;

 TCOMPUTE_PGM_RSRC1=bitpacked record
  VGPRS     :bit6;
  SGPRS     :bit4;
  PRIORITY  :bit2;
  FLOAT_MODE:bit8;
  PRIV      :bit1;
  DX10_CLAMP:bit1;
  DEBUG_MODE:bit1;
  IEEE_MODE :bit1;
  BULKY     :bit1;
  CDBG_USER :bit1;
  RESERVED0 :bit6;
 end;

 TCOMPUTE_PGM_RSRC2=bitpacked record
  SCRATCH_EN    :bit1;
  USER_SGPR     :bit5;
  TRAP_PRESENT  :bit1;
  TGID_X_EN     :bit1;
  TGID_Y_EN     :bit1;
  TGID_Z_EN     :bit1;
  TG_SIZE_EN    :bit1;
  TIDIG_COMP_CNT:bit2;
  EXCP_EN_MSB   :bit2;
  LDS_SIZE      :bit9;
  EXCP_EN       :bit7;
  RESERVED0     :bit1;
 end;

 TCOMPUTE_RESTART_X=bit32;

 TCOMPUTE_RESTART_Y=bit32;

 TCOMPUTE_RESTART_Z=bit32;

 TCORB_READ_POINTER=bitpacked record
  CORB_READ_POINTER      :bit8;
  RESERVED0              :bit7;
  CORB_READ_POINTER_RESET:bit1;
  RESERVED1              :bit16;
 end;

 TCP_APPEND_ADDR_HI=bitpacked record
  MEM_ADDR_HI :bit16;
  CS_PS_SEL   :bit1;
  RESERVED0   :bit8;
  CACHE_POLICY:bit1;
  RESERVED1   :bit1;
  MTYPE       :bit2;
  COMMAND     :bit3;
 end;

 TCP_APPEND_ADDR_LO=bitpacked record
  RESERVED0  :bit2;
  MEM_ADDR_LO:bit30;
 end;

 TCP_CE_HEADER_DUMP=bit32;

 TCP_CE_IB1_BASE_HI=bitpacked record
  IB1_BASE_HI:bit16;
  RESERVED0  :bit16;
 end;

 TCP_CE_IB1_BASE_LO=bitpacked record
  RESERVED0  :bit2;
  IB1_BASE_LO:bit30;
 end;

 TCP_CE_IB2_BASE_HI=bitpacked record
  IB2_BASE_HI:bit16;
  RESERVED0  :bit16;
 end;

 TCP_CE_IB2_BASE_LO=bitpacked record
  RESERVED0  :bit2;
  IB2_BASE_LO:bit30;
 end;

 TCP_CE_ROQ_RB_STAT=bitpacked record
  CEQ_RPTR_PRIMARY:bit10;
  RESERVED0       :bit6;
  CEQ_WPTR_PRIMARY:bit10;
  RESERVED1       :bit6;
 end;

 TCP_CPC_IC_BASE_HI=bitpacked record
  IC_BASE_HI:bit16;
  RESERVED0 :bit16;
 end;

 TCP_CPC_IC_BASE_LO=bitpacked record
  RESERVED0 :bit12;
  IC_BASE_LO:bit20;
 end;

 TCP_CPC_IC_OP_CNTL=bitpacked record
  INVALIDATE_CACHE:bit1;
  RESERVED0       :bit3;
  PRIME_ICACHE    :bit1;
  ICACHE_PRIMED   :bit1;
  RESERVED1       :bit26;
 end;

 TCP_DMA_ME_COMMAND=bitpacked record
  BYTE_COUNT:bit21;
  DIS_WC    :bit1;
  SRC_SWAP  :bit2;
  DST_SWAP  :bit2;
  SAS       :bit1;
  DAS       :bit1;
  SAIC      :bit1;
  DAIC      :bit1;
  RAW_WAIT  :bit1;
  RESERVED0 :bit1;
 end;

 TCP_DMA_ME_CONTROL=bitpacked record
  RESERVED0       :bit10;
  SRC_MTYPE       :bit2;
  SRC_ATC         :bit1;
  SRC_CACHE_POLICY:bit1;
  RESERVED1       :bit6;
  DST_SELECT      :bit2;
  DST_MTYPE       :bit2;
  DST_ATC         :bit1;
  DST_CACHE_POLICY:bit1;
  RESERVED2       :bit3;
  SRC_SELECT      :bit2;
  RESERVED3       :bit1;
 end;

 TCP_DRAW_WINDOW_HI=bit32;

 TCP_DRAW_WINDOW_LO=bitpacked record
  MIN:bit16;
  MAX:bit16;
 end;

 TCP_HQD_EOP_EVENTS=bitpacked record
  EVENT_COUNT          :bit12;
  RESERVED0            :bit4;
  CS_PARTIAL_FLUSH_PEND:bit1;
  RESERVED1            :bit15;
 end;

 TCP_HQD_HQ_STATUS0=bitpacked record
  DEQUEUE_STATUS   :bit2;
  DEQUEUE_RETRY_CNT:bit2;
  RSV_6_4          :bit3;
  SCRATCH_RAM_INIT :bit1;
  TCL2_DIRTY       :bit1;
  PG_ACTIVATED     :bit1;
  RSVR_31_10       :bit22;
 end;

 TCP_HQD_HQ_STATUS1=bit32;

 TCP_HQD_IB_CONTROL=bitpacked record
  IB_SIZE          :bit20;
  MIN_IB_AVAIL_SIZE:bit2;
  RESERVED0        :bit1;
  IB_ATC           :bit1;
  IB_CACHE_POLICY  :bit1;
  RESERVED1        :bit2;
  MTYPE            :bit2;
  RESERVED2        :bit1;
  RESERVED3        :bit1;
  PROCESSING_IB    :bit1;
 end;

 TCP_HQD_PQ_BASE_HI=bitpacked record
  ADDR_HI  :bit8;
  RESERVED0:bit24;
 end;

 TCP_HQD_PQ_CONTROL=bitpacked record
  QUEUE_SIZE     :bit6;
  RESERVED0      :bit2;
  RPTR_BLOCK_SIZE:bit6;
  RESERVED1      :bit1;
  MTYPE          :bit2;
  ENDIAN_SWAP    :bit2;
  RESERVED2      :bit1;
  MIN_AVAIL_SIZE :bit2;
  RESERVED3      :bit1;
  PQ_ATC         :bit1;
  CACHE_POLICY   :bit1;
  SLOT_BASED_WPTR:bit2;
  NO_UPDATE_RPTR :bit1;
  UNORD_DISPATCH :bit1;
  ROQ_PQ_IB_FLIP :bit1;
  PRIV_STATE     :bit1;
  KMD_QUEUE      :bit1;
 end;

 TCP_INT_CNTL_RING0=bitpacked record
  RESERVED0                    :bit11;
  CP_VM_DOORBELL_WR_INT_ENABLE :bit1;
  RESERVED1                    :bit2;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  RESERVED2                    :bit2;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  CMP_BUSY_INT_ENABLE          :bit1;
  CNTX_BUSY_INT_ENABLE         :bit1;
  CNTX_EMPTY_INT_ENABLE        :bit1;
  GFX_IDLE_INT_ENABLE          :bit1;
  PRIV_INSTR_INT_ENABLE        :bit1;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_INT_CNTL_RING1=bitpacked record
  RESERVED0                    :bit11;
  CP_VM_DOORBELL_WR_INT_ENABLE :bit1;
  RESERVED1                    :bit2;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  RESERVED2                    :bit2;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  CMP_BUSY_INT_ENABLE          :bit1;
  CNTX_BUSY_INT_ENABLE         :bit1;
  CNTX_EMPTY_INT_ENABLE        :bit1;
  GFX_IDLE_INT_ENABLE          :bit1;
  PRIV_INSTR_INT_ENABLE        :bit1;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_INT_CNTL_RING2=bitpacked record
  RESERVED0                    :bit11;
  CP_VM_DOORBELL_WR_INT_ENABLE :bit1;
  RESERVED1                    :bit2;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  RESERVED2                    :bit2;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  CMP_BUSY_INT_ENABLE          :bit1;
  CNTX_BUSY_INT_ENABLE         :bit1;
  CNTX_EMPTY_INT_ENABLE        :bit1;
  GFX_IDLE_INT_ENABLE          :bit1;
  PRIV_INSTR_INT_ENABLE        :bit1;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_INT_STAT_DEBUG=bitpacked record
  RESERVED0                      :bit11;
  CP_VM_DOORBELL_WR_INT_ASSERTED :bit1;
  RESERVED1                      :bit2;
  CP_ECC_ERROR_INT_ASSERTED      :bit1;
  RESERVED2                      :bit2;
  WRM_POLL_TIMEOUT_INT_ASSERTED  :bit1;
  CMP_BUSY_INT_ASSERTED          :bit1;
  CNTX_BUSY_INT_ASSERTED         :bit1;
  CNTX_EMPTY_INT_ASSERTED        :bit1;
  GFX_IDLE_INT_ASSERTED          :bit1;
  PRIV_INSTR_INT_ASSERTED        :bit1;
  PRIV_REG_INT_ASSERTED          :bit1;
  OPCODE_ERROR_INT_ASSERTED      :bit1;
  RESERVED3                      :bit1;
  TIME_STAMP_INT_ASSERTED        :bit1;
  RESERVED_BIT_ERROR_INT_ASSERTED:bit1;
  RESERVED4                      :bit1;
  GENERIC2_INT_ASSERTED          :bit1;
  GENERIC1_INT_ASSERTED          :bit1;
  GENERIC0_INT_ASSERTED          :bit1;
 end;

 TCP_ME0_PIPE0_VMID=bitpacked record
  VMID     :bit4;
  RESERVED0:bit28;
 end;

 TCP_ME0_PIPE1_VMID=bitpacked record
  VMID     :bit4;
  RESERVED0:bit28;
 end;

 TCP_MEQ_THRESHOLDS=bitpacked record
  MEQ1_START:bit8;
  MEQ2_START:bit8;
  RESERVED0 :bit16;
 end;

 TCP_ME_HEADER_DUMP=bit32;

 TCP_ME_MC_RADDR_HI=bitpacked record
  ME_MC_RADDR_HI:bit16;
  RESERVED0     :bit4;
  MTYPE         :bit2;
  CACHE_POLICY  :bit1;
  RESERVED1     :bit9;
 end;

 TCP_ME_MC_RADDR_LO=bitpacked record
  ME_MC_RADDR_SWAP:bit2;
  ME_MC_RADDR_LO  :bit30;
 end;

 TCP_ME_MC_WADDR_HI=bitpacked record
  ME_MC_WADDR_HI:bit16;
  RESERVED0     :bit4;
  MTYPE         :bit2;
  CACHE_POLICY  :bit1;
  RESERVED1     :bit9;
 end;

 TCP_ME_MC_WADDR_LO=bitpacked record
  ME_MC_WADDR_SWAP:bit2;
  ME_MC_WADDR_LO  :bit30;
 end;

 TCP_ME_MC_WDATA_HI=bit32;

 TCP_ME_MC_WDATA_LO=bit32;

 TCP_PERFCOUNTER_HI=bitpacked record
  RESERVED0:bit16;
  RESERVED1:bit16;
 end;

 TCP_PERFCOUNTER_LO=bit32;

 TCP_PFP_IB_CONTROL=bitpacked record
  IB_EN    :bit8;
  RESERVED0:bit24;
 end;

 TCP_PFP_UCODE_ADDR=bitpacked record
  UCODE_ADDR:bit13;
  RESERVED0 :bit19;
 end;

 TCP_PFP_UCODE_DATA=bit32;

 TCP_RING0_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_RING1_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_RING2_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ROQ_THRESHOLDS=bitpacked record
  IB1_START:bit8;
  IB2_START:bit8;
  RESERVED0:bit16;
 end;

 TCP_SEM_WAIT_TIMER=bit32;

 TCP_STQ_THRESHOLDS=bitpacked record
  STQ0_START:bit8;
  STQ1_START:bit8;
  STQ2_START:bit8;
  RESERVED0 :bit8;
 end;

 TCRTC_CRC0_DATA_RG=bitpacked record
  CRC0_R_CR:bit16;
  CRC0_G_Y :bit16;
 end;

 TCRTC_CRC1_DATA_RG=bitpacked record
  CRC1_R_CR:bit16;
  CRC1_G_Y :bit16;
 end;

 TCRTC_DTMTEST_CNTL=bitpacked record
  CRTC_DTMTEST_CRTC_EN:bit1;
  CRTC_DTMTEST_CLK_DIV:bit4;
  RESERVED0           :bit27;
 end;

 TCRTC_FLOW_CONTROL=bitpacked record
  CRTC_FLOW_CONTROL_SOURCE_SELECT:bit5;
  RESERVED0                      :bit3;
  CRTC_FLOW_CONTROL_POLARITY     :bit1;
  RESERVED1                      :bit7;
  CRTC_FLOW_CONTROL_GRANULARITY  :bit1;
  RESERVED2                      :bit7;
  CRTC_FLOW_CONTROL_INPUT_STATUS :bit1;
  RESERVED3                      :bit7;
 end;

 TDAC_SOURCE_SELECT=bitpacked record
  DAC_SOURCE_SELECT:bit3;
  DAC_TV_SELECT    :bit1;
  RESERVED0        :bit28;
 end;

 TDB_RENDER_CONTROL=bitpacked record
  DEPTH_CLEAR_ENABLE      :bit1;
  STENCIL_CLEAR_ENABLE    :bit1;
  DEPTH_COPY              :bit1;
  STENCIL_COPY            :bit1;
  RESUMMARIZE_ENABLE      :bit1;
  STENCIL_COMPRESS_DISABLE:bit1;
  DEPTH_COMPRESS_DISABLE  :bit1;
  COPY_CENTROID           :bit1;
  COPY_SAMPLE             :bit4;
  DECOMPRESS_ENABLE       :bit1;
  RESERVED0               :bit19;
 end;

 TDB_SHADER_CONTROL=bitpacked record
  Z_EXPORT_ENABLE               :bit1;
  STENCIL_TEST_VAL_EXPORT_ENABLE:bit1;
  STENCIL_OP_VAL_EXPORT_ENABLE  :bit1;
  RESERVED0                     :bit1;
  Z_ORDER                       :bit2;
  KILL_ENABLE                   :bit1;
  COVERAGE_TO_MASK_ENABLE       :bit1;
  MASK_EXPORT_ENABLE            :bit1;
  EXEC_ON_HIER_FAIL             :bit1;
  EXEC_ON_NOOP                  :bit1;
  ALPHA_TO_MASK_DISABLE         :bit1;
  DEPTH_BEFORE_SHADER           :bit1;
  CONSERVATIVE_Z_EXPORT         :bit2;
  DUAL_QUAD_DISABLE             :bit1;
  RESERVED1                     :bit16;
 end;

 TDB_STENCILREFMASK=bitpacked record
  STENCILTESTVAL  :bit8;
  STENCILMASK     :bit8;
  STENCILWRITEMASK:bit8;
  STENCILOPVAL    :bit8;
 end;

 TDB_ZPASS_COUNT_HI=bitpacked record
  COUNT_HI :bit31;
  RESERVED0:bit1;
 end;

 TDCCG_GTC_DTO_INCR=bit32;

 TDCCG_PERFMON_CNTL=bitpacked record
  DCCG_PERF_DISPCLK_ENABLE  :bit1;
  DCCG_PERF_DPREFCLK_ENABLE :bit1;
  DCCG_PERF_PIXCLK1_ENABLE  :bit1;
  DCCG_PERF_PIXCLK2_ENABLE  :bit1;
  DCCG_PERF_PIXCLK0_ENABLE  :bit1;
  DCCG_PERF_RUN             :bit1;
  DCCG_PERF_MODE_VSYNC      :bit1;
  DCCG_PERF_MODE_HSYNC      :bit1;
  DCCG_PERF_CRTC_SEL        :bit3;
  DCCG_PERF_XTALIN_PULSE_DIV:bit21;
 end;

 TDCCG_TEST_CLK_SEL=bitpacked record
  DCCG_TEST_CLK_GENERICA_SEL:bit9;
  RESERVED0                 :bit3;
  DCCG_TEST_CLK_GENERICA_INV:bit1;
  RESERVED1                 :bit3;
  DCCG_TEST_CLK_GENERICB_SEL:bit9;
  RESERVED2                 :bit3;
  DCCG_TEST_CLK_GENERICB_INV:bit1;
  RESERVED3                 :bit3;
 end;

 TDCFE_MEM_PWR_CTRL=bitpacked record
  DCP_LUT_MEM_PWR_FORCE    :bit2;
  DCP_LUT_MEM_PWR_DIS      :bit1;
  DCP_REGAMMA_MEM_PWR_FORCE:bit2;
  DCP_REGAMMA_MEM_PWR_DIS  :bit1;
  SCL_COEFF_MEM_PWR_FORCE  :bit2;
  SCL_COEFF_MEM_PWR_DIS    :bit1;
  DCP_CURSOR_MEM_PWR_FORCE :bit2;
  DCP_CURSOR_MEM_PWR_DIS   :bit1;
  LB0_ALPHA_MEM_PWR_FORCE  :bit2;
  LB0_ALPHA_MEM_PWR_DIS    :bit1;
  LB1_ALPHA_MEM_PWR_FORCE  :bit2;
  LB1_ALPHA_MEM_PWR_DIS    :bit1;
  LB2_ALPHA_MEM_PWR_FORCE  :bit2;
  LB2_ALPHA_MEM_PWR_DIS    :bit1;
  LB0_MEM_PWR_FORCE        :bit2;
  LB0_MEM_PWR_DIS          :bit1;
  LB1_MEM_PWR_FORCE        :bit2;
  LB1_MEM_PWR_DIS          :bit1;
  LB2_MEM_PWR_FORCE        :bit2;
  LB2_MEM_PWR_DIS          :bit1;
  RESERVED0                :bit2;
 end;

 TDCIO_DEBUG_CONFIG=bitpacked record
  DCIO_DBG_EN:bit1;
  RESERVED0  :bit31;
 end;

 TDCI_CLK_RAMP_CNTL=bitpacked record
  DISPCLK_G_MCIF_DWB_GATE_DIS :bit1;
  SCLK_G_MCIF_DWB_GATE_DIS    :bit1;
  DISPCLK_G_MCIF_CWB0_GATE_DIS:bit1;
  SCLK_G_MCIF_CWB0_GATE_DIS   :bit1;
  DISPCLK_G_MCIF_CWB1_GATE_DIS:bit1;
  RESERVED0                   :bit1;
  RESERVED1                   :bit1;
  RESERVED2                   :bit1;
  RESERVED3                   :bit1;
  RESERVED4                   :bit1;
  RESERVED5                   :bit1;
  RESERVED6                   :bit1;
  RESERVED7                   :bit1;
  RESERVED8                   :bit1;
  RESERVED9                   :bit1;
  RESERVED10                  :bit1;
  RESERVED11                  :bit1;
  RESERVED12                  :bit1;
  RESERVED13                  :bit1;
  RESERVED14                  :bit1;
  RESERVED15                  :bit1;
  RESERVED16                  :bit1;
  RESERVED17                  :bit1;
  RESERVED18                  :bit1;
  RESERVED19                  :bit1;
  RESERVED20                  :bit1;
  RESERVED21                  :bit1;
  RESERVED22                  :bit1;
  RESERVED23                  :bit1;
  RESERVED24                  :bit1;
  RESERVED25                  :bit1;
  SCLK_G_MCIF_CWB1_GATE_DIS   :bit1;
 end;

 TDCI_MEM_PWR_CNTL2=bitpacked record
  DMIF0_ASYNC_MEM_PWR_FORCE:bit2;
  DMIF0_ASYNC_MEM_PWR_DIS  :bit1;
  DMIF0_DATA_MEM_PWR_FORCE :bit2;
  DMIF0_DATA_MEM_PWR_DIS   :bit1;
  DMIF0_CHUNK_MEM_PWR_FORCE:bit1;
  DMIF0_CHUNK_MEM_PWR_DIS  :bit1;
  DMIF1_ASYNC_MEM_PWR_FORCE:bit2;
  DMIF1_ASYNC_MEM_PWR_DIS  :bit1;
  DMIF1_DATA_MEM_PWR_FORCE :bit2;
  DMIF1_DATA_MEM_PWR_DIS   :bit1;
  DMIF1_CHUNK_MEM_PWR_FORCE:bit1;
  DMIF1_CHUNK_MEM_PWR_DIS  :bit1;
  DMIF2_ASYNC_MEM_PWR_FORCE:bit2;
  DMIF2_ASYNC_MEM_PWR_DIS  :bit1;
  DMIF2_DATA_MEM_PWR_FORCE :bit2;
  DMIF2_DATA_MEM_PWR_DIS   :bit1;
  DMIF2_CHUNK_MEM_PWR_FORCE:bit1;
  DMIF2_CHUNK_MEM_PWR_DIS  :bit1;
  DMIF3_ASYNC_MEM_PWR_FORCE:bit2;
  DMIF3_ASYNC_MEM_PWR_DIS  :bit1;
  DMIF3_DATA_MEM_PWR_FORCE :bit2;
  DMIF3_DATA_MEM_PWR_DIS   :bit1;
  DMIF3_CHUNK_MEM_PWR_FORCE:bit1;
  DMIF3_CHUNK_MEM_PWR_DIS  :bit1;
 end;

 TDCI_MEM_PWR_CNTL3=bitpacked record
  DMIF4_ASYNC_MEM_PWR_FORCE  :bit2;
  DMIF4_ASYNC_MEM_PWR_DIS    :bit1;
  DMIF4_DATA_MEM_PWR_FORCE   :bit2;
  DMIF4_DATA_MEM_PWR_DIS     :bit1;
  DMIF4_CHUNK_MEM_PWR_FORCE  :bit1;
  DMIF4_CHUNK_MEM_PWR_DIS    :bit1;
  DMIF5_ASYNC_MEM_PWR_FORCE  :bit2;
  DMIF5_ASYNC_MEM_PWR_DIS    :bit1;
  DMIF5_DATA_MEM_PWR_FORCE   :bit2;
  DMIF5_DATA_MEM_PWR_DIS     :bit1;
  DMIF5_CHUNK_MEM_PWR_FORCE  :bit1;
  DMIF5_CHUNK_MEM_PWR_DIS    :bit1;
  DMIF_RDREQ_MEM_PWR_MODE_SEL:bit2;
  DMIF_ASYNC_MEM_PWR_MODE_SEL:bit2;
  DMIF_DATA_MEM_PWR_MODE_SEL :bit2;
  DMCU_ERAM_MEM_PWR_MODE_SEL :bit1;
  FBC_MEM_PWR_MODE_SEL       :bit2;
  MCIF_CWB0_MEM_PWR_MODE_SEL :bit2;
  MCIF_CWB1_MEM_PWR_MODE_SEL :bit2;
  MCIF_DWB_MEM_PWR_MODE_SEL  :bit2;
  RESERVED0                  :bit1;
 end;

 TDCO_CLK_RAMP_CNTL=bitpacked record
  RESERVED0              :bit4;
  REFCLK_R_DCO_RAMP_DIS  :bit1;
  DISPCLK_R_DCO_RAMP_DIS :bit1;
  DISPCLK_G_ABM_RAMP_DIS :bit1;
  DISPCLK_G_DVO_RAMP_DIS :bit1;
  DISPCLK_G_DACA_RAMP_DIS:bit1;
  DISPCLK_G_DACB_RAMP_DIS:bit1;
  RESERVED1              :bit6;
  DISPCLK_G_FMT0_RAMP_DIS:bit1;
  DISPCLK_G_FMT1_RAMP_DIS:bit1;
  DISPCLK_G_FMT2_RAMP_DIS:bit1;
  DISPCLK_G_FMT3_RAMP_DIS:bit1;
  DISPCLK_G_FMT4_RAMP_DIS:bit1;
  DISPCLK_G_FMT5_RAMP_DIS:bit1;
  RESERVED2              :bit2;
  DISPCLK_G_DIGA_RAMP_DIS:bit1;
  DISPCLK_G_DIGB_RAMP_DIS:bit1;
  DISPCLK_G_DIGC_RAMP_DIS:bit1;
  DISPCLK_G_DIGD_RAMP_DIS:bit1;
  DISPCLK_G_DIGE_RAMP_DIS:bit1;
  DISPCLK_G_DIGF_RAMP_DIS:bit1;
  DISPCLK_G_DIGG_RAMP_DIS:bit1;
  RESERVED3              :bit1;
 end;

 TDCO_MEM_PWR_CTRL2=bitpacked record
  HDMI_MEM_PWR_MODE_SEL:bit2;
  RESERVED0            :bit30;
 end;

 TDC_DVODATA_CONFIG=bitpacked record
  RESERVED0           :bit19;
  VIP_MUX_EN          :bit1;
  VIP_ALTER_MAPPING_EN:bit1;
  DVO_ALTER_MAPPING_EN:bit1;
  RESERVED1           :bit10;
 end;

 TDC_GPIO_DDC1_MASK=bitpacked record
  DC_GPIO_DDC1CLK_MASK  :bit1;
  RESERVED0             :bit3;
  DC_GPIO_DDC1CLK_PD_EN :bit1;
  RESERVED1             :bit1;
  DC_GPIO_DDC1CLK_RECV  :bit1;
  RESERVED2             :bit1;
  DC_GPIO_DDC1DATA_MASK :bit1;
  RESERVED3             :bit3;
  DC_GPIO_DDC1DATA_PD_EN:bit1;
  RESERVED4             :bit1;
  DC_GPIO_DDC1DATA_RECV :bit1;
  RESERVED5             :bit1;
  AUX_PAD1_MODE         :bit1;
  RESERVED6             :bit3;
  AUX1_POL              :bit1;
  RESERVED7             :bit1;
  ALLOW_HW_DDC1_PD_EN   :bit1;
  RESERVED8             :bit1;
  DC_GPIO_DDC1CLK_STR   :bit4;
  DC_GPIO_DDC1DATA_STR  :bit4;
 end;

 TDC_GPIO_DDC2_MASK=bitpacked record
  DC_GPIO_DDC2CLK_MASK  :bit1;
  RESERVED0             :bit3;
  DC_GPIO_DDC2CLK_PD_EN :bit1;
  RESERVED1             :bit1;
  DC_GPIO_DDC2CLK_RECV  :bit1;
  RESERVED2             :bit1;
  DC_GPIO_DDC2DATA_MASK :bit1;
  RESERVED3             :bit3;
  DC_GPIO_DDC2DATA_PD_EN:bit1;
  RESERVED4             :bit1;
  DC_GPIO_DDC2DATA_RECV :bit1;
  RESERVED5             :bit1;
  AUX_PAD2_MODE         :bit1;
  RESERVED6             :bit3;
  AUX2_POL              :bit1;
  RESERVED7             :bit1;
  ALLOW_HW_DDC2_PD_EN   :bit1;
  RESERVED8             :bit1;
  DC_GPIO_DDC2CLK_STR   :bit4;
  DC_GPIO_DDC2DATA_STR  :bit4;
 end;

 TDC_GPIO_DDC3_MASK=bitpacked record
  DC_GPIO_DDC3CLK_MASK  :bit1;
  RESERVED0             :bit3;
  DC_GPIO_DDC3CLK_PD_EN :bit1;
  RESERVED1             :bit1;
  DC_GPIO_DDC3CLK_RECV  :bit1;
  RESERVED2             :bit1;
  DC_GPIO_DDC3DATA_MASK :bit1;
  RESERVED3             :bit3;
  DC_GPIO_DDC3DATA_PD_EN:bit1;
  RESERVED4             :bit1;
  DC_GPIO_DDC3DATA_RECV :bit1;
  RESERVED5             :bit1;
  AUX_PAD3_MODE         :bit1;
  RESERVED6             :bit3;
  AUX3_POL              :bit1;
  RESERVED7             :bit1;
  ALLOW_HW_DDC3_PD_EN   :bit1;
  RESERVED8             :bit1;
  DC_GPIO_DDC3CLK_STR   :bit4;
  DC_GPIO_DDC3DATA_STR  :bit4;
 end;

 TDC_GPIO_DDC4_MASK=bitpacked record
  DC_GPIO_DDC4CLK_MASK  :bit1;
  RESERVED0             :bit3;
  DC_GPIO_DDC4CLK_PD_EN :bit1;
  RESERVED1             :bit1;
  DC_GPIO_DDC4CLK_RECV  :bit1;
  RESERVED2             :bit1;
  DC_GPIO_DDC4DATA_MASK :bit1;
  RESERVED3             :bit3;
  DC_GPIO_DDC4DATA_PD_EN:bit1;
  RESERVED4             :bit1;
  DC_GPIO_DDC4DATA_RECV :bit1;
  RESERVED5             :bit1;
  AUX_PAD4_MODE         :bit1;
  RESERVED6             :bit3;
  AUX4_POL              :bit1;
  RESERVED7             :bit1;
  ALLOW_HW_DDC4_PD_EN   :bit1;
  RESERVED8             :bit1;
  DC_GPIO_DDC4CLK_STR   :bit4;
  DC_GPIO_DDC4DATA_STR  :bit4;
 end;

 TDC_GPIO_DDC5_MASK=bitpacked record
  DC_GPIO_DDC5CLK_MASK  :bit1;
  RESERVED0             :bit3;
  DC_GPIO_DDC5CLK_PD_EN :bit1;
  RESERVED1             :bit1;
  DC_GPIO_DDC5CLK_RECV  :bit1;
  RESERVED2             :bit1;
  DC_GPIO_DDC5DATA_MASK :bit1;
  RESERVED3             :bit3;
  DC_GPIO_DDC5DATA_PD_EN:bit1;
  RESERVED4             :bit1;
  DC_GPIO_DDC5DATA_RECV :bit1;
  RESERVED5             :bit1;
  AUX_PAD5_MODE         :bit1;
  RESERVED6             :bit3;
  AUX5_POL              :bit1;
  RESERVED7             :bit1;
  ALLOW_HW_DDC5_PD_EN   :bit1;
  RESERVED8             :bit1;
  DC_GPIO_DDC5CLK_STR   :bit4;
  DC_GPIO_DDC5DATA_STR  :bit4;
 end;

 TDC_GPIO_DDC6_MASK=bitpacked record
  DC_GPIO_DDC6CLK_MASK  :bit1;
  RESERVED0             :bit3;
  DC_GPIO_DDC6CLK_PD_EN :bit1;
  RESERVED1             :bit1;
  DC_GPIO_DDC6CLK_RECV  :bit1;
  RESERVED2             :bit1;
  DC_GPIO_DDC6DATA_MASK :bit1;
  RESERVED3             :bit3;
  DC_GPIO_DDC6DATA_PD_EN:bit1;
  RESERVED4             :bit1;
  DC_GPIO_DDC6DATA_RECV :bit1;
  RESERVED5             :bit1;
  AUX_PAD6_MODE         :bit1;
  RESERVED6             :bit3;
  AUX6_POL              :bit1;
  RESERVED7             :bit1;
  ALLOW_HW_DDC6_PD_EN   :bit1;
  RESERVED8             :bit1;
  DC_GPIO_DDC6CLK_STR   :bit4;
  DC_GPIO_DDC6DATA_STR  :bit4;
 end;

 TDC_GPIO_DDCVGA_EN=bitpacked record
  DC_GPIO_DDCVGACLK_EN :bit1;
  RESERVED0            :bit7;
  DC_GPIO_DDCVGADATA_EN:bit1;
  RESERVED1            :bit23;
 end;

 TDC_GPIO_DVODATA_A=bitpacked record
  DC_GPIO_DVODATA_A    :bit24;
  DC_GPIO_DVOCNTL_A    :bit5;
  DC_GPIO_DVOCLK_A     :bit1;
  DC_GPIO_MVP_DVOCNTL_A:bit2;
 end;

 TDC_GPIO_DVODATA_Y=bitpacked record
  DC_GPIO_DVODATA_Y    :bit24;
  DC_GPIO_DVOCNTL_Y    :bit5;
  DC_GPIO_DVOCLK_Y     :bit1;
  DC_GPIO_MVP_DVOCNTL_Y:bit2;
 end;

 TDC_GPIO_GENERIC_A=bitpacked record
  DC_GPIO_GENERICA_A:bit1;
  RESERVED0         :bit7;
  DC_GPIO_GENERICB_A:bit1;
  RESERVED1         :bit7;
  DC_GPIO_GENERICC_A:bit1;
  RESERVED2         :bit3;
  DC_GPIO_GENERICD_A:bit1;
  DC_GPIO_GENERICE_A:bit1;
  DC_GPIO_GENERICF_A:bit1;
  DC_GPIO_GENERICG_A:bit1;
  RESERVED3         :bit8;
 end;

 TDC_GPIO_GENERIC_Y=bitpacked record
  DC_GPIO_GENERICA_Y:bit1;
  RESERVED0         :bit7;
  DC_GPIO_GENERICB_Y:bit1;
  RESERVED1         :bit7;
  DC_GPIO_GENERICC_Y:bit1;
  RESERVED2         :bit3;
  DC_GPIO_GENERICD_Y:bit1;
  DC_GPIO_GENERICE_Y:bit1;
  DC_GPIO_GENERICF_Y:bit1;
  DC_GPIO_GENERICG_Y:bit1;
  RESERVED3         :bit8;
 end;

 TDC_GPIO_I2CPAD_EN=bitpacked record
  DC_GPIO_SCL_EN:bit1;
  DC_GPIO_SDA_EN:bit1;
  RESERVED0     :bit30;
 end;

 TDC_GPIO_PWRSEQ_EN=bitpacked record
  DC_GPIO_BLON_EN            :bit1;
  DC_GPIO_VARY_BL_GENERICA_EN:bit1;
  RESERVED0                  :bit6;
  DC_GPIO_DIGON_EN           :bit1;
  RESERVED1                  :bit7;
  DC_GPIO_ENA_BL_EN          :bit1;
  RESERVED2                  :bit7;
  DC_GPIO_VSYNC_IN_EN        :bit1;
  RESERVED3                  :bit6;
  DC_GPIO_HSYNC_IN_EN        :bit1;
 end;

 TDC_GPU_TIMER_READ=bit32;

 TDC_HPD_INT_STATUS=bitpacked record
  DC_HPD_INT_STATUS                  :bit1;
  DC_HPD_SENSE                       :bit1;
  RESERVED0                          :bit2;
  DC_HPD_SENSE_DELAYED               :bit1;
  RESERVED1                          :bit3;
  DC_HPD_RX_INT_STATUS               :bit1;
  RESERVED2                          :bit3;
  DC_HPD_TOGGLE_FILT_CON_TIMER_VAL   :bit8;
  RESERVED3                          :bit4;
  DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL:bit8;
 end;

 TDC_I2C_DDC1_SETUP=bitpacked record
  DC_I2C_DDC1_DATA_DRIVE_EN          :bit1;
  DC_I2C_DDC1_DATA_DRIVE_SEL         :bit1;
  RESERVED0                          :bit2;
  DC_I2C_DDC1_EDID_DETECT_ENABLE     :bit1;
  DC_I2C_DDC1_EDID_DETECT_MODE       :bit1;
  DC_I2C_DDC1_ENABLE                 :bit1;
  DC_I2C_DDC1_CLK_DRIVE_EN           :bit1;
  DC_I2C_DDC1_INTRA_BYTE_DELAY       :bit8;
  DC_I2C_DDC1_INTRA_TRANSACTION_DELAY:bit8;
  DC_I2C_DDC1_TIME_LIMIT             :bit8;
 end;

 TDC_I2C_DDC1_SPEED=bitpacked record
  DC_I2C_DDC1_THRESHOLD                  :bit2;
  RESERVED0                              :bit2;
  DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL:bit1;
  RESERVED1                              :bit11;
  DC_I2C_DDC1_PRESCALE                   :bit16;
 end;

 TDC_I2C_DDC2_SETUP=bitpacked record
  DC_I2C_DDC2_DATA_DRIVE_EN          :bit1;
  DC_I2C_DDC2_DATA_DRIVE_SEL         :bit1;
  RESERVED0                          :bit2;
  DC_I2C_DDC2_EDID_DETECT_ENABLE     :bit1;
  DC_I2C_DDC2_EDID_DETECT_MODE       :bit1;
  DC_I2C_DDC2_ENABLE                 :bit1;
  DC_I2C_DDC2_CLK_DRIVE_EN           :bit1;
  DC_I2C_DDC2_INTRA_BYTE_DELAY       :bit8;
  DC_I2C_DDC2_INTRA_TRANSACTION_DELAY:bit8;
  DC_I2C_DDC2_TIME_LIMIT             :bit8;
 end;

 TDC_I2C_DDC2_SPEED=bitpacked record
  DC_I2C_DDC2_THRESHOLD                  :bit2;
  RESERVED0                              :bit2;
  DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL:bit1;
  RESERVED1                              :bit11;
  DC_I2C_DDC2_PRESCALE                   :bit16;
 end;

 TDC_I2C_DDC3_SETUP=bitpacked record
  DC_I2C_DDC3_DATA_DRIVE_EN          :bit1;
  DC_I2C_DDC3_DATA_DRIVE_SEL         :bit1;
  RESERVED0                          :bit2;
  DC_I2C_DDC3_EDID_DETECT_ENABLE     :bit1;
  DC_I2C_DDC3_EDID_DETECT_MODE       :bit1;
  DC_I2C_DDC3_ENABLE                 :bit1;
  DC_I2C_DDC3_CLK_DRIVE_EN           :bit1;
  DC_I2C_DDC3_INTRA_BYTE_DELAY       :bit8;
  DC_I2C_DDC3_INTRA_TRANSACTION_DELAY:bit8;
  DC_I2C_DDC3_TIME_LIMIT             :bit8;
 end;

 TDC_I2C_DDC3_SPEED=bitpacked record
  DC_I2C_DDC3_THRESHOLD                  :bit2;
  RESERVED0                              :bit2;
  DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL:bit1;
  RESERVED1                              :bit11;
  DC_I2C_DDC3_PRESCALE                   :bit16;
 end;

 TDC_I2C_DDC4_SETUP=bitpacked record
  DC_I2C_DDC4_DATA_DRIVE_EN          :bit1;
  DC_I2C_DDC4_DATA_DRIVE_SEL         :bit1;
  RESERVED0                          :bit2;
  DC_I2C_DDC4_EDID_DETECT_ENABLE     :bit1;
  DC_I2C_DDC4_EDID_DETECT_MODE       :bit1;
  DC_I2C_DDC4_ENABLE                 :bit1;
  DC_I2C_DDC4_CLK_DRIVE_EN           :bit1;
  DC_I2C_DDC4_INTRA_BYTE_DELAY       :bit8;
  DC_I2C_DDC4_INTRA_TRANSACTION_DELAY:bit8;
  DC_I2C_DDC4_TIME_LIMIT             :bit8;
 end;

 TDC_I2C_DDC4_SPEED=bitpacked record
  DC_I2C_DDC4_THRESHOLD                  :bit2;
  RESERVED0                              :bit2;
  DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL:bit1;
  RESERVED1                              :bit11;
  DC_I2C_DDC4_PRESCALE                   :bit16;
 end;

 TDC_I2C_DDC5_SETUP=bitpacked record
  DC_I2C_DDC5_DATA_DRIVE_EN          :bit1;
  DC_I2C_DDC5_DATA_DRIVE_SEL         :bit1;
  RESERVED0                          :bit2;
  DC_I2C_DDC5_EDID_DETECT_ENABLE     :bit1;
  DC_I2C_DDC5_EDID_DETECT_MODE       :bit1;
  DC_I2C_DDC5_ENABLE                 :bit1;
  DC_I2C_DDC5_CLK_DRIVE_EN           :bit1;
  DC_I2C_DDC5_INTRA_BYTE_DELAY       :bit8;
  DC_I2C_DDC5_INTRA_TRANSACTION_DELAY:bit8;
  DC_I2C_DDC5_TIME_LIMIT             :bit8;
 end;

 TDC_I2C_DDC5_SPEED=bitpacked record
  DC_I2C_DDC5_THRESHOLD                  :bit2;
  RESERVED0                              :bit2;
  DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL:bit1;
  RESERVED1                              :bit11;
  DC_I2C_DDC5_PRESCALE                   :bit16;
 end;

 TDC_I2C_DDC6_SETUP=bitpacked record
  DC_I2C_DDC6_DATA_DRIVE_EN          :bit1;
  DC_I2C_DDC6_DATA_DRIVE_SEL         :bit1;
  RESERVED0                          :bit2;
  DC_I2C_DDC6_EDID_DETECT_ENABLE     :bit1;
  DC_I2C_DDC6_EDID_DETECT_MODE       :bit1;
  DC_I2C_DDC6_ENABLE                 :bit1;
  DC_I2C_DDC6_CLK_DRIVE_EN           :bit1;
  DC_I2C_DDC6_INTRA_BYTE_DELAY       :bit8;
  DC_I2C_DDC6_INTRA_TRANSACTION_DELAY:bit8;
  DC_I2C_DDC6_TIME_LIMIT             :bit8;
 end;

 TDC_I2C_DDC6_SPEED=bitpacked record
  DC_I2C_DDC6_THRESHOLD                  :bit2;
  RESERVED0                              :bit2;
  DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL:bit1;
  RESERVED1                              :bit11;
  DC_I2C_DDC6_PRESCALE                   :bit16;
 end;

 TDC_MVP_LB_CONTROL=bitpacked record
  MVP_SWAP_LOCK_IN_MODE          :bit2;
  RESERVED0                      :bit6;
  DC_MVP_SWAP_LOCK_OUT_SEL       :bit1;
  RESERVED1                      :bit3;
  DC_MVP_SWAP_LOCK_OUT_FORCE_ONE :bit1;
  RESERVED2                      :bit3;
  DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO:bit1;
  RESERVED3                      :bit3;
  DC_MVP_SWAP_LOCK_STATUS        :bit1;
  RESERVED4                      :bit7;
  DC_MVP_SWAP_LOCK_IN_CAP        :bit1;
  RESERVED5                      :bit2;
  DC_MVP_SPARE_FLOPS             :bit1;
 end;

 TDC_PAD_EXTERN_SIG=bitpacked record
  DC_PAD_EXTERN_SIG_SEL:bit4;
  MVP_PIXEL_SRC_STATUS :bit2;
  RESERVED0            :bit26;
 end;

 TDIDT_DBR_CTRL_OCP=bitpacked record
  UNUSED_0     :bit16;
  OCP_MAX_POWER:bit16;
 end;

 TDIDT_DB_WEIGHT0_3=bitpacked record
  WEIGHT0:bit8;
  WEIGHT1:bit8;
  WEIGHT2:bit8;
  WEIGHT3:bit8;
 end;

 TDIDT_DB_WEIGHT4_7=bitpacked record
  WEIGHT4:bit8;
  WEIGHT5:bit8;
  WEIGHT6:bit8;
  WEIGHT7:bit8;
 end;

 TDIDT_SQ_WEIGHT0_3=bitpacked record
  WEIGHT0:bit8;
  WEIGHT1:bit8;
  WEIGHT2:bit8;
  WEIGHT3:bit8;
 end;

 TDIDT_SQ_WEIGHT4_7=bitpacked record
  WEIGHT4:bit8;
  WEIGHT5:bit8;
  WEIGHT6:bit8;
  WEIGHT7:bit8;
 end;

 TDIDT_TCP_CTRL_OCP=bitpacked record
  UNUSED_0     :bit16;
  OCP_MAX_POWER:bit16;
 end;

 TDIDT_TD_WEIGHT0_3=bitpacked record
  WEIGHT0:bit8;
  WEIGHT1:bit8;
  WEIGHT2:bit8;
  WEIGHT3:bit8;
 end;

 TDIDT_TD_WEIGHT4_7=bitpacked record
  WEIGHT4:bit8;
  WEIGHT5:bit8;
  WEIGHT6:bit8;
  WEIGHT7:bit8;
 end;

 TDIG_CLOCK_PATTERN=bitpacked record
  DIG_CLOCK_PATTERN:bit10;
  RESERVED0        :bit22;
 end;

 TDMCU_ERAM_RD_CTRL=bitpacked record
  ERAM_RD_ADDR     :bit16;
  ERAM_RD_BE       :bit4;
  ERAM_RD_BYTE_MODE:bit1;
  RESERVED0        :bit11;
 end;

 TDMCU_ERAM_RD_DATA=bit32;

 TDMCU_ERAM_WR_CTRL=bitpacked record
  ERAM_WR_ADDR     :bit16;
  ERAM_WR_BE       :bit4;
  ERAM_WR_BYTE_MODE:bit1;
  RESERVED0        :bit11;
 end;

 TDMCU_ERAM_WR_DATA=bit32;

 TDMCU_IRAM_RD_CTRL=bitpacked record
  IRAM_RD_ADDR:bit10;
  RESERVED0   :bit22;
 end;

 TDMCU_IRAM_RD_DATA=bitpacked record
  IRAM_RD_DATA:bit8;
  RESERVED0   :bit24;
 end;

 TDMCU_IRAM_WR_CTRL=bitpacked record
  IRAM_WR_ADDR:bit10;
  RESERVED0   :bit22;
 end;

 TDMCU_IRAM_WR_DATA=bitpacked record
  IRAM_WR_DATA:bit8;
  RESERVED0   :bit24;
 end;

 TDMIF_URG_OVERRIDE=bitpacked record
  DMIF_URG_OVERRIDE_EN   :bit1;
  RESERVED0              :bit3;
  DMIF_URG_OVERRIDE_LEVEL:bit4;
  RESERVED1              :bit24;
 end;

 TDP_DPHY_PRBS_CNTL=bitpacked record
  DPHY_PRBS_EN  :bit1;
  RESERVED0     :bit3;
  DPHY_PRBS_SEL :bit2;
  RESERVED1     :bit2;
  DPHY_PRBS_SEED:bit23;
  RESERVED2     :bit1;
 end;

 TDP_MSE_SAT_UPDATE=bitpacked record
  DP_MSE_SAT_UPDATE    :bit2;
  RESERVED0            :bit6;
  DP_MSE_16_MTP_KEEPOUT:bit1;
  RESERVED1            :bit23;
 end;

 TDVOACLKC_MVP_CNTL=bitpacked record
  DVOACLKC_MVP_FINE_SKEW_CNTL     :bit3;
  RESERVED0                       :bit5;
  DVOACLKC_MVP_COARSE_SKEW_CNTL   :bit5;
  RESERVED1                       :bit3;
  DVOACLKC_MVP_FINE_ADJUST_EN     :bit1;
  DVOACLKC_MVP_COARSE_ADJUST_EN   :bit1;
  DVOACLKC_MVP_IN_PHASE           :bit1;
  RESERVED2                       :bit1;
  DVOACLKC_MVP_SKEW_PHASE_OVERRIDE:bit1;
  RESERVED3                       :bit3;
  MVP_CLK_A_SRC_SEL               :bit2;
  RESERVED4                       :bit2;
  MVP_CLK_B_SRC_SEL               :bit2;
  RESERVED5                       :bit2;
 end;

 TDVO_CRC2_SIG_MASK=bitpacked record
  DVO_CRC2_SIG_MASK:bit27;
  RESERVED0        :bit5;
 end;

 TDVO_SOURCE_SELECT=bitpacked record
  DVO_SOURCE_SELECT    :bit3;
  RESERVED0            :bit13;
  DVO_STEREOSYNC_SELECT:bit3;
  RESERVED1            :bit13;
 end;

 TGARLIC_FLUSH_CNTL=bitpacked record
  CP_RB0_WPTR       :bit1;
  CP_RB1_WPTR       :bit1;
  CP_RB2_WPTR       :bit1;
  UVD_RBC_RB_WPTR   :bit1;
  SDMA0_GFX_RB_WPTR :bit1;
  SDMA1_GFX_RB_WPTR :bit1;
  CP_DMA_ME_COMMAND :bit1;
  CP_DMA_PFP_COMMAND:bit1;
  SAM_SAB_RBI_WPTR  :bit1;
  SAM_SAB_RBO_WPTR  :bit1;
  VCE_OUT_RB_WPTR   :bit1;
  VCE_RB_WPTR2      :bit1;
  VCE_RB_WPTR       :bit1;
  HOST_DOORBELL     :bit1;
  SELFRING_DOORBELL :bit1;
  CP_DMA_PIO_COMMAND:bit1;
  DISPLAY           :bit1;
  SDMA2_GFX_RB_WPTR :bit1;
  SDMA3_GFX_RB_WPTR :bit1;
  RESERVED0         :bit11;
  IGNORE_MC_DISABLE :bit1;
  DISABLE_ALL       :bit1;
 end;

 TGCK_PLL_TEST_CNTL=bitpacked record
  TST_SRC_SEL     :bit5;
  TST_REF_SEL     :bit5;
  REF_TEST_COUNT  :bit7;
  TST_RESET       :bit1;
  TST_CLK_SEL_MODE:bit1;
  RESERVED0       :bit13;
 end;

 TGCK_SMC_IND_INDEX=bit32;

 TGDS_ATOM_COMPLETE=bitpacked record
  COMPLETE:bit1;
  UNUSED  :bit31;
 end;

 TGDS_CS_CTXSW_CNT0=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_CS_CTXSW_CNT1=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_CS_CTXSW_CNT2=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_CS_CTXSW_CNT3=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_OA_RESET_MASK=bitpacked record
  ME0_GFXHP3D_PIX_RESET:bit1;
  ME0_GFXHP3D_VTX_RESET:bit1;
  ME0_CS_RESET         :bit1;
  RESERVED0            :bit1;
  ME1_PIPE0_RESET      :bit1;
  ME1_PIPE1_RESET      :bit1;
  ME1_PIPE2_RESET      :bit1;
  ME1_PIPE3_RESET      :bit1;
  ME2_PIPE0_RESET      :bit1;
  ME2_PIPE1_RESET      :bit1;
  ME2_PIPE2_RESET      :bit1;
  ME2_PIPE3_RESET      :bit1;
  RESERVED1            :bit20;
 end;

 TGDS_RD_BURST_ADDR=bit32;

 TGDS_RD_BURST_DATA=bit32;

 TGDS_VS_CTXSW_CNT0=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_VS_CTXSW_CNT1=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_VS_CTXSW_CNT2=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_VS_CTXSW_CNT3=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_WR_BURST_ADDR=bit32;

 TGDS_WR_BURST_DATA=bit32;

 TGENERIC_I2C_SETUP=bitpacked record
  GENERIC_I2C_DATA_DRIVE_EN   :bit1;
  GENERIC_I2C_DATA_DRIVE_SEL  :bit1;
  RESERVED0                   :bit5;
  GENERIC_I2C_CLK_DRIVE_EN    :bit1;
  GENERIC_I2C_INTRA_BYTE_DELAY:bit8;
  RESERVED1                   :bit8;
  GENERIC_I2C_TIME_LIMIT      :bit8;
 end;

 TGENERIC_I2C_SPEED=bitpacked record
  GENERIC_I2C_THRESHOLD                  :bit2;
  RESERVED0                              :bit2;
  GENERIC_I2C_DISABLE_FILTER_DURING_STALL:bit1;
  RESERVED1                              :bit11;
  GENERIC_I2C_PRESCALE                   :bit16;
 end;

 TGFX_PIPE_PRIORITY=bitpacked record
  HP_PIPE_SELECT:bit1;
  RESERVED0     :bit31;
 end;

 TGMCON_PGFSM_WRITE=bit32;

 TGPIOPAD_PINSTRAPS=bitpacked record
  GPIO_PINSTRAP_0 :bit1;
  GPIO_PINSTRAP_1 :bit1;
  GPIO_PINSTRAP_2 :bit1;
  GPIO_PINSTRAP_3 :bit1;
  GPIO_PINSTRAP_4 :bit1;
  GPIO_PINSTRAP_5 :bit1;
  GPIO_PINSTRAP_6 :bit1;
  GPIO_PINSTRAP_7 :bit1;
  GPIO_PINSTRAP_8 :bit1;
  GPIO_PINSTRAP_9 :bit1;
  GPIO_PINSTRAP_10:bit1;
  GPIO_PINSTRAP_11:bit1;
  GPIO_PINSTRAP_12:bit1;
  GPIO_PINSTRAP_13:bit1;
  GPIO_PINSTRAP_14:bit1;
  GPIO_PINSTRAP_15:bit1;
  GPIO_PINSTRAP_16:bit1;
  GPIO_PINSTRAP_17:bit1;
  GPIO_PINSTRAP_18:bit1;
  GPIO_PINSTRAP_19:bit1;
  GPIO_PINSTRAP_20:bit1;
  GPIO_PINSTRAP_21:bit1;
  GPIO_PINSTRAP_22:bit1;
  GPIO_PINSTRAP_23:bit1;
  GPIO_PINSTRAP_24:bit1;
  GPIO_PINSTRAP_25:bit1;
  GPIO_PINSTRAP_26:bit1;
  GPIO_PINSTRAP_27:bit1;
  GPIO_PINSTRAP_28:bit1;
  GPIO_PINSTRAP_29:bit1;
  GPIO_PINSTRAP_30:bit1;
  RESERVED0       :bit1;
 end;

 TGPU_HDP_FLUSH_REQ=bitpacked record
  CP0      :bit1;
  CP1      :bit1;
  CP2      :bit1;
  CP3      :bit1;
  CP4      :bit1;
  CP5      :bit1;
  CP6      :bit1;
  CP7      :bit1;
  CP8      :bit1;
  CP9      :bit1;
  SDMA0    :bit1;
  SDMA1    :bit1;
  RESERVED0:bit20;
 end;

 TGRBM_HYP_CAM_DATA=bitpacked record
  CAM_ADDR     :bit16;
  CAM_REMAPADDR:bit16;
 end;

 TGRBM_SCRATCH_REG0=bit32;

 TGRBM_SCRATCH_REG1=bit32;

 TGRBM_SCRATCH_REG2=bit32;

 TGRBM_SCRATCH_REG3=bit32;

 TGRBM_SCRATCH_REG4=bit32;

 TGRBM_SCRATCH_REG5=bit32;

 TGRBM_SCRATCH_REG6=bit32;

 TGRBM_SCRATCH_REG7=bit32;

 TGRPH_FLIP_CONTROL=bitpacked record
  GRPH_SURFACE_UPDATE_H_RETRACE_EN:bit1;
  GRPH_XDMA_SUPER_AA_EN           :bit1;
  RESERVED0                       :bit30;
 end;

 THDMI_ACR_STATUS_0=bitpacked record
  RESERVED0   :bit12;
  HDMI_ACR_CTS:bit20;
 end;

 THDMI_ACR_STATUS_1=bitpacked record
  HDMI_ACR_N:bit20;
  RESERVED0 :bit12;
 end;

 THDP_MEMIO_RD_DATA=bit32;

 THDP_MEMIO_WR_DATA=bit32;

 THDP_NONSURF_FLAGS=bitpacked record
  NONSURF_WRITE_FLAG:bit1;
  NONSURF_READ_FLAG :bit1;
  RESERVED0         :bit30;
 end;

 THDP_TILING_CONFIG=bitpacked record
  RESERVED0   :bit1;
  PIPE_TILING :bit3;
  BANK_TILING :bit2;
  GROUP_SIZE  :bit2;
  ROW_TILING  :bit3;
  BANK_SWAPS  :bit3;
  SAMPLE_SPLIT:bit2;
  RESERVED1   :bit16;
 end;

 THDP_XDP_D2H_FLUSH=bitpacked record
  D2H_FLUSH_FLUSH_NUM      :bit4;
  D2H_FLUSH_MBX_ENC_DATA   :bit4;
  D2H_FLUSH_MBX_ADDR_SEL   :bit3;
  D2H_FLUSH_XPB_CLG        :bit5;
  D2H_FLUSH_SEND_HOST      :bit1;
  D2H_FLUSH_SEND_SIDE      :bit1;
  D2H_FLUSH_ALTER_FLUSH_NUM:bit1;
  D2H_FLUSH_RSVD_0         :bit1;
  D2H_FLUSH_RSVD_1         :bit1;
  RESERVED0                :bit11;
 end;

 TIH_VIRT_RESET_REQ=bitpacked record
  VF       :bit16;
  RESERVED0:bit15;
  PF       :bit1;
 end;

 TINPUT_CSC_C11_C12=bitpacked record
  INPUT_CSC_C11:bit16;
  INPUT_CSC_C12:bit16;
 end;

 TINPUT_CSC_C13_C14=bitpacked record
  INPUT_CSC_C13:bit16;
  INPUT_CSC_C14:bit16;
 end;

 TINPUT_CSC_C21_C22=bitpacked record
  INPUT_CSC_C21:bit16;
  INPUT_CSC_C22:bit16;
 end;

 TINPUT_CSC_C23_C24=bitpacked record
  INPUT_CSC_C23:bit16;
  INPUT_CSC_C24:bit16;
 end;

 TINPUT_CSC_C31_C32=bitpacked record
  INPUT_CSC_C31:bit16;
  INPUT_CSC_C32:bit16;
 end;

 TINPUT_CSC_C33_C34=bitpacked record
  INPUT_CSC_C33:bit16;
  INPUT_CSC_C34:bit16;
 end;

 TINPUT_CSC_CONTROL=bitpacked record
  INPUT_CSC_GRPH_MODE:bit2;
  RESERVED0          :bit2;
  INPUT_CSC_OVL_MODE :bit2;
  RESERVED1          :bit26;
 end;

 TINTERRUPT_CONTROL=bitpacked record
  STREAM_0_INTERRUPT_ENABLE  :bit1;
  STREAM_1_INTERRUPT_ENABLE  :bit1;
  STREAM_2_INTERRUPT_ENABLE  :bit1;
  STREAM_3_INTERRUPT_ENABLE  :bit1;
  STREAM_4_INTERRUPT_ENABLE  :bit1;
  STREAM_5_INTERRUPT_ENABLE  :bit1;
  STREAM_6_INTERRUPT_ENABLE  :bit1;
  STREAM_7_INTERRUPT_ENABLE  :bit1;
  STREAM_8_INTERRUPT_ENABLE  :bit1;
  STREAM_9_INTERRUPT_ENABLE  :bit1;
  STREAM_10_INTERRUPT_ENABLE :bit1;
  STREAM_11_INTERRUPT_ENABLE :bit1;
  STREAM_12_INTERRUPT_ENABLE :bit1;
  STREAM_13_INTERRUPT_ENABLE :bit1;
  STREAM_14_INTERRUPT_ENABLE :bit1;
  STREAM_15_INTERRUPT_ENABLE :bit1;
  RESERVED0                  :bit14;
  CONTROLLER_INTERRUPT_ENABLE:bit1;
  GLOBAL_INTERRUPT_ENABLE    :bit1;
 end;

 TLBV_BUFFER_STATUS=bitpacked record
  LB_BUFFER_EMPTY_MARGIN  :bit4;
  LB_BUFFER_EMPTY_STAT    :bit1;
  RESERVED0               :bit3;
  LB_BUFFER_EMPTY_OCCURRED:bit1;
  RESERVED1               :bit3;
  LB_BUFFER_EMPTY_ACK     :bit1;
  RESERVED2               :bit3;
  LB_BUFFER_FULL_STAT     :bit1;
  RESERVED3               :bit3;
  LB_BUFFER_FULL_OCCURRED :bit1;
  RESERVED4               :bit3;
  LB_BUFFER_FULL_ACK      :bit1;
  RESERVED5               :bit7;
 end;

 TLBV_VBLANK_STATUS=bitpacked record
  VBLANK_OCCURRED      :bit1;
  RESERVED0            :bit3;
  VBLANK_ACK           :bit1;
  RESERVED1            :bit7;
  VBLANK_STAT          :bit1;
  RESERVED2            :bit3;
  VBLANK_INTERRUPT     :bit1;
  VBLANK_INTERRUPT_TYPE:bit1;
  RESERVED3            :bit14;
 end;

 TLBV_VLINE2_STATUS=bitpacked record
  VLINE2_OCCURRED      :bit1;
  RESERVED0            :bit3;
  VLINE2_ACK           :bit1;
  RESERVED1            :bit7;
  VLINE2_STAT          :bit1;
  RESERVED2            :bit3;
  VLINE2_INTERRUPT     :bit1;
  VLINE2_INTERRUPT_TYPE:bit1;
  RESERVED3            :bit14;
 end;

 TLB_DESKTOP_HEIGHT=bitpacked record
  DESKTOP_HEIGHT:bit15;
  RESERVED0     :bit17;
 end;

 TLB_INTERRUPT_MASK=bitpacked record
  VBLANK_INTERRUPT_MASK:bit1;
  RESERVED0            :bit3;
  VLINE_INTERRUPT_MASK :bit1;
  RESERVED1            :bit3;
  VLINE2_INTERRUPT_MASK:bit1;
  RESERVED2            :bit23;
 end;

 TLB_SYNC_RESET_SEL=bitpacked record
  LB_SYNC_RESET_SEL  :bit2;
  RESERVED0          :bit2;
  LB_SYNC_RESET_SEL2 :bit1;
  RESERVED1          :bit3;
  LB_SYNC_RESET_DELAY:bit8;
  RESERVED2          :bit6;
  LB_SYNC_DURATION   :bit2;
  RESERVED3          :bit8;
 end;

 TLVTMA_PWRSEQ_CNTL=bitpacked record
  LVTMA_PWRSEQ_EN                             :bit1;
  LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN:bit1;
  RESERVED0                                   :bit1;
  RESERVED1                                   :bit1;
  LVTMA_PWRSEQ_TARGET_STATE                   :bit1;
  RESERVED2                                   :bit1;
  RESERVED3                                   :bit2;
  LVTMA_SYNCEN                                :bit1;
  LVTMA_SYNCEN_OVRD                           :bit1;
  LVTMA_SYNCEN_POL                            :bit1;
  RESERVED4                                   :bit5;
  LVTMA_DIGON                                 :bit1;
  LVTMA_DIGON_OVRD                            :bit1;
  LVTMA_DIGON_POL                             :bit1;
  RESERVED5                                   :bit5;
  LVTMA_BLON                                  :bit1;
  LVTMA_BLON_OVRD                             :bit1;
  LVTMA_BLON_POL                              :bit1;
  RESERVED6                                   :bit5;
 end;

 TMCIF_WB_BUF_PITCH=bitpacked record
  RESERVED0               :bit8;
  MCIF_WB_BUF_LUMA_PITCH  :bit8;
  RESERVED1               :bit8;
  MCIF_WB_BUF_CHROMA_PITCH:bit8;
 end;

 TMC_ARB_ADDR_SWIZ0=bitpacked record
  A8 :bit4;
  A9 :bit4;
  A10:bit4;
  A11:bit4;
  A12:bit4;
  A13:bit4;
  A14:bit4;
  A15:bit4;
 end;

 TMC_ARB_ADDR_SWIZ1=bitpacked record
  A16      :bit4;
  A17      :bit4;
  A18      :bit4;
  A19      :bit4;
  RESERVED0:bit16;
 end;

 TMC_ARB_BURST_TIME=bitpacked record
  STATE0   :bit5;
  STATE1   :bit5;
  STATE2   :bit5;
  STATE3   :bit5;
  RESERVED0:bit12;
 end;

 TMC_ARB_GECC2_MISC=bitpacked record
  STREAK_BREAK              :bit4;
  COL10_HACK                :bit1;
  CWRD_IN_REPLAY            :bit1;
  NO_EOB_ALL_WR_IN_REPLAY   :bit1;
  RMW_LM_WR_STALL           :bit1;
  RMW_STALL_RELEASE         :bit1;
  WR_EDC_MASK_REPLAY        :bit1;
  CWRD_REPLAY_AGAIN         :bit1;
  WRRDWR_REPLAY_AGAIN       :bit1;
  ALLOW_RMW_ERR_AFTER_REPLAY:bit1;
  DEBUG_RSV                 :bit19;
 end;

 TMC_ARB_TM_CNTL_RD=bitpacked record
  GROUPBY_RANK:bit1;
  BANK_SELECT :bit2;
  MATCH_RANK  :bit1;
  MATCH_BANK  :bit1;
  RESERVED0   :bit27;
 end;

 TMC_ARB_TM_CNTL_WR=bitpacked record
  GROUPBY_RANK:bit1;
  BANK_SELECT :bit2;
  MATCH_RANK  :bit1;
  MATCH_BANK  :bit1;
  RESERVED0   :bit27;
 end;

 TMC_CITF_DAGB_CNTL=bitpacked record
  JUMP_AHEAD         :bit1;
  CENTER_RD_MAX_BURST:bit4;
  DISABLE_SELF_INIT  :bit1;
  CENTER_WR_MAX_BURST:bit4;
  RESERVED0          :bit22;
 end;

 TMC_GRUB_PROBE_MAP=bitpacked record
  ADDR0_TO_TC_MAP  :bit2;
  ADDR1_TO_TC_MAP  :bit2;
  ADDR2_TO_TC_MAP  :bit2;
  ADDR3_TO_TC_MAP  :bit2;
  ADDR0_TO_GRUB_MAP:bit1;
  ADDR1_TO_GRUB_MAP:bit1;
  ADDR2_TO_GRUB_MAP:bit1;
  ADDR3_TO_GRUB_MAP:bit1;
  RESERVED0        :bit20;
 end;

 TMC_GRUB_TCB_INDEX=bitpacked record
  INDEX     :bit7;
  RESERVED0 :bit1;
  TCB0_WR_EN:bit1;
  TCB1_WR_EN:bit1;
  RD_EN     :bit1;
  TCB_SEL   :bit1;
  RESERVED1 :bit20;
 end;

 TMC_HUB_MISC_POWER=bitpacked record
  RESERVED0         :bit2;
  SRBM_GATE_OVERRIDE:bit1;
  PM_BLACKOUT_CNTL  :bit2;
  RESERVED1         :bit1;
  RESERVED2         :bit1;
  RESERVED3         :bit25;
 end;

 TMC_HUB_MISC_VM_CG=bitpacked record
  ONDLY        :bit6;
  OFFDLY       :bit6;
  RDYDLY       :bit6;
  ENABLE       :bit1;
  MEM_LS_ENABLE:bit1;
  RESERVED0    :bit12;
 end;

 TMC_HUB_RDREQ_ACPG=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_HUB_RDREQ_ACPO=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_HUB_RDREQ_CNTL=bitpacked record
  REMOTE_BLACKOUT        :bit1;
  RESERVED0              :bit1;
  JUMPAHEAD_GBL0         :bit1;
  JUMPAHEAD_GBL1         :bit1;
  OVERRIDE_STALL_ENABLE  :bit1;
  MCDW_STALL_MODE        :bit1;
  MCDX_STALL_MODE        :bit1;
  MCDY_STALL_MODE        :bit1;
  MCDZ_STALL_MODE        :bit1;
  MCDS_STALL_MODE        :bit1;
  MCDT_STALL_MODE        :bit1;
  MCDU_STALL_MODE        :bit1;
  MCDV_STALL_MODE        :bit1;
  BREAK_HDP_DEADLOCK     :bit1;
  DEBUG_REG              :bit7;
  DISABLE_SELF_INIT_GBL0 :bit1;
  DISABLE_SELF_INIT_GBL1 :bit1;
  PWRXPRESS_MODE         :bit1;
  ACPG_HP_TO_MCD_OVERRIDE:bit1;
  GBL0_PRI_ENABLE        :bit1;
  UVD_TRANSCODE_ENABLE   :bit1;
  DMIF_URG_THRESHOLD     :bit4;
  RESERVED1              :bit1;
 end;

 TMC_HUB_RDREQ_DMIF=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_GBL0=bitpacked record
  STALL_THRESHOLD    :bit8;
  STALL_THRESHOLD_PRI:bit8;
  RESERVED0          :bit16;
 end;

 TMC_HUB_RDREQ_GBL1=bitpacked record
  STALL_THRESHOLD    :bit8;
  STALL_THRESHOLD_PRI:bit8;
  RESERVED0          :bit16;
 end;

 TMC_HUB_RDREQ_MCDS=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  BUS            :bit1;
  MAXBURST       :bit4;
  LAZY_TIMER     :bit4;
  ASK_CREDITS    :bit7;
  DISPLAY_CREDITS:bit7;
  STALL_THRESHOLD:bit7;
 end;

 TMC_HUB_RDREQ_MCDT=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  BUS            :bit1;
  MAXBURST       :bit4;
  LAZY_TIMER     :bit4;
  ASK_CREDITS    :bit7;
  DISPLAY_CREDITS:bit7;
  STALL_THRESHOLD:bit7;
 end;

 TMC_HUB_RDREQ_MCDU=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  BUS            :bit1;
  MAXBURST       :bit4;
  LAZY_TIMER     :bit4;
  ASK_CREDITS    :bit7;
  DISPLAY_CREDITS:bit7;
  STALL_THRESHOLD:bit7;
 end;

 TMC_HUB_RDREQ_MCDV=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  BUS            :bit1;
  MAXBURST       :bit4;
  LAZY_TIMER     :bit4;
  ASK_CREDITS    :bit7;
  DISPLAY_CREDITS:bit7;
  STALL_THRESHOLD:bit7;
 end;

 TMC_HUB_RDREQ_MCDW=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  BUS            :bit1;
  MAXBURST       :bit4;
  LAZY_TIMER     :bit4;
  ASK_CREDITS    :bit7;
  DISPLAY_CREDITS:bit7;
  MED_CREDITS    :bit7;
 end;

 TMC_HUB_RDREQ_MCDX=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  BUS            :bit1;
  MAXBURST       :bit4;
  LAZY_TIMER     :bit4;
  ASK_CREDITS    :bit7;
  DISPLAY_CREDITS:bit7;
  MED_CREDITS    :bit7;
 end;

 TMC_HUB_RDREQ_MCDY=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  BUS            :bit1;
  MAXBURST       :bit4;
  LAZY_TIMER     :bit4;
  ASK_CREDITS    :bit7;
  DISPLAY_CREDITS:bit7;
  MED_CREDITS    :bit7;
 end;

 TMC_HUB_RDREQ_MCDZ=bitpacked record
  ENABLE         :bit1;
  BLACKOUT_EXEMPT:bit1;
  BUS            :bit1;
  MAXBURST       :bit4;
  LAZY_TIMER     :bit4;
  ASK_CREDITS    :bit7;
  DISPLAY_CREDITS:bit7;
  MED_CREDITS    :bit7;
 end;

 TMC_HUB_RDREQ_MCIF=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_VCE0=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  VM_BYPASS            :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit14;
 end;

 TMC_HUB_RDREQ_VCE1=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  VM_BYPASS            :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit14;
 end;

 TMC_HUB_RDREQ_VP8U=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_WDP_SAMMSP=bitpacked record
  ENABLE                   :bit1;
  PRESCALE                 :bit2;
  BLACKOUT_EXEMPT          :bit1;
  STALL_MODE               :bit2;
  STALL_OVERRIDE           :bit1;
  MAXBURST                 :bit4;
  LAZY_TIMER               :bit4;
  STALL_OVERRIDE_WTM       :bit1;
  BYPASS_AVAIL_OVERRIDE    :bit1;
  URG_BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0                :bit14;
 end;

 TMC_HUB_WDP_STATUS=bitpacked record
  SIP_AVAIL            :bit1;
  MCDW_RD_AVAIL        :bit1;
  MCDX_RD_AVAIL        :bit1;
  MCDY_RD_AVAIL        :bit1;
  MCDZ_RD_AVAIL        :bit1;
  MCDS_RD_AVAIL        :bit1;
  MCDT_RD_AVAIL        :bit1;
  MCDU_RD_AVAIL        :bit1;
  MCDV_RD_AVAIL        :bit1;
  MCDW_WR_AVAIL        :bit1;
  MCDX_WR_AVAIL        :bit1;
  MCDY_WR_AVAIL        :bit1;
  MCDZ_WR_AVAIL        :bit1;
  MCDS_WR_AVAIL        :bit1;
  MCDT_WR_AVAIL        :bit1;
  MCDU_WR_AVAIL        :bit1;
  MCDV_WR_AVAIL        :bit1;
  GBL0_VM_FULL         :bit1;
  GBL0_STOR_FULL       :bit1;
  GBL0_BYPASS_STOR_FULL:bit1;
  GBL1_VM_FULL         :bit1;
  GBL1_STOR_FULL       :bit1;
  GBL1_BYPASS_STOR_FULL:bit1;
  RESERVED0            :bit9;
 end;

 TMC_HUB_WRRET_CNTL=bitpacked record
  JUMPAHEAD        :bit1;
  BP               :bit20;
  BP_ENABLE        :bit1;
  DEBUG_REG        :bit8;
  DISABLE_SELF_INIT:bit1;
  FAIR_CH_SW       :bit1;
 end;

 TMC_HUB_WRRET_MCDS=bitpacked record
  STALL_MODE  :bit1;
  CREDIT_COUNT:bit7;
  RESERVED0   :bit24;
 end;

 TMC_HUB_WRRET_MCDT=bitpacked record
  STALL_MODE  :bit1;
  CREDIT_COUNT:bit7;
  RESERVED0   :bit24;
 end;

 TMC_HUB_WRRET_MCDU=bitpacked record
  STALL_MODE  :bit1;
  CREDIT_COUNT:bit7;
  RESERVED0   :bit24;
 end;

 TMC_HUB_WRRET_MCDV=bitpacked record
  STALL_MODE  :bit1;
  CREDIT_COUNT:bit7;
  RESERVED0   :bit24;
 end;

 TMC_HUB_WRRET_MCDW=bitpacked record
  STALL_MODE  :bit1;
  CREDIT_COUNT:bit7;
  RESERVED0   :bit24;
 end;

 TMC_HUB_WRRET_MCDX=bitpacked record
  STALL_MODE  :bit1;
  CREDIT_COUNT:bit7;
  RESERVED0   :bit24;
 end;

 TMC_HUB_WRRET_MCDY=bitpacked record
  STALL_MODE  :bit1;
  CREDIT_COUNT:bit7;
  RESERVED0   :bit24;
 end;

 TMC_HUB_WRRET_MCDZ=bitpacked record
  STALL_MODE  :bit1;
  CREDIT_COUNT:bit7;
  RESERVED0   :bit24;
 end;

 TMC_IO_DEBUG_UP_10=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_11=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_12=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_13=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_14=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_15=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_16=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_17=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_18=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_19=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_20=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_21=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_22=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_23=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_24=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_25=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_26=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_27=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_28=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_29=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_30=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_31=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_32=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_33=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_34=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_35=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_36=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_37=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_38=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_39=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_40=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_41=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_42=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_43=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_44=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_45=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_46=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_47=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_48=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_49=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_50=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_51=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_52=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_53=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_54=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_55=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_56=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_57=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_58=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_59=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_60=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_61=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_62=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_63=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_64=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_65=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_66=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_67=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_68=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_69=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_70=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_71=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_72=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_73=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_74=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_75=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_76=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_77=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_78=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_79=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_80=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_81=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_82=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_83=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_84=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_85=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_86=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_87=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_88=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_89=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_90=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_91=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_92=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_93=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_94=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_95=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_96=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_97=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_98=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_99=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_SEQ_CAS_TIMING=bitpacked record
  TNOPW    :bit2;
  TNOPR    :bit2;
  TR2W     :bit5;
  TCCDL    :bit3;
  TR2R     :bit4;
  TW2R     :bit5;
  TCL      :bit5;
  RESERVED0:bit6;
 end;

 TMC_SEQ_IO_RESERVE=bit32;

 TMC_SEQ_PMG_TIMING=bitpacked record
  TCKSRE     :bit3;
  TCKSRX     :bit3;
  TCKE_PULSE :bit5;
  TCKE       :bit8;
  SEQ_IDLE   :bit3;
  SEQ_IDLE_SS:bit8;
  RESERVED0  :bit2;
 end;

 TMC_SEQ_RAS_TIMING=bitpacked record
  TRCDW    :bit5;
  TRCDWA   :bit5;
  TRCDR    :bit5;
  TRCDRA   :bit5;
  TRRD     :bit4;
  TRC      :bit7;
  RESERVED0:bit1;
 end;

 TMC_SHARED_CHREMAP=bitpacked record
  CHAN0:bit4;
  CHAN1:bit4;
  CHAN2:bit4;
  CHAN3:bit4;
  CHAN4:bit4;
  CHAN5:bit4;
  CHAN6:bit4;
  CHAN7:bit4;
 end;

 TMC_VM_FB_LOCATION=bitpacked record
  FB_BASE:bit16;
  FB_TOP :bit16;
 end;

 TMC_VM_NB_MMIOBASE=bit32;

 TMC_VM_NB_PCI_CTRL=bitpacked record
  RESERVED0 :bit23;
  MMIOENABLE:bit1;
  RESERVED1 :bit8;
 end;

 TMC_XPB_PERF_KNOBS=bitpacked record
  CNS_FIFO_DEPTH    :bit6;
  WCB_HST_FIFO_DEPTH:bit6;
  WCB_SID_FIFO_DEPTH:bit6;
  RESERVED0         :bit14;
 end;

 TMC_XPB_STICKY_W1C=bit32;

 TMVP_AFR_FLIP_MODE=bitpacked record
  MVP_AFR_FLIP_MODE:bit2;
  RESERVED0        :bit30;
 end;

 TOUT_ROUND_CONTROL=bitpacked record
  OUT_ROUND_TRUNC_MODE:bit4;
  RESERVED0           :bit28;
 end;

 TPA_CL_CNTL_STATUS=bitpacked record
  RESERVED0:bit31;
  CL_BUSY  :bit1;
 end;

 TPA_CL_NANINF_CNTL=bitpacked record
  VTE_XY_INF_DISCARD      :bit1;
  VTE_Z_INF_DISCARD       :bit1;
  VTE_W_INF_DISCARD       :bit1;
  VTE_0XNANINF_IS_0       :bit1;
  VTE_XY_NAN_RETAIN       :bit1;
  VTE_Z_NAN_RETAIN        :bit1;
  VTE_W_NAN_RETAIN        :bit1;
  VTE_W_RECIP_NAN_IS_0    :bit1;
  VS_XY_NAN_TO_INF        :bit1;
  VS_XY_INF_RETAIN        :bit1;
  VS_Z_NAN_TO_INF         :bit1;
  VS_Z_INF_RETAIN         :bit1;
  VS_W_NAN_TO_INF         :bit1;
  VS_W_INF_RETAIN         :bit1;
  VS_CLIP_DIST_INF_DISCARD:bit1;
  RESERVED0               :bit5;
  VTE_NO_OUTPUT_NEG_0     :bit1;
  RESERVED1               :bit11;
 end;

 TPA_CL_POINT_X_RAD=bit32;

 TPA_CL_POINT_Y_RAD=bit32;

 TPA_CL_RESET_DEBUG=bitpacked record
  CL_TRIV_DISC_DISABLE:bit1;
  RESERVED0           :bit31;
 end;

 TPA_CL_VS_OUT_CNTL=bitpacked record
  CLIP_DIST_ENA_0           :bit1;
  CLIP_DIST_ENA_1           :bit1;
  CLIP_DIST_ENA_2           :bit1;
  CLIP_DIST_ENA_3           :bit1;
  CLIP_DIST_ENA_4           :bit1;
  CLIP_DIST_ENA_5           :bit1;
  CLIP_DIST_ENA_6           :bit1;
  CLIP_DIST_ENA_7           :bit1;
  CULL_DIST_ENA_0           :bit1;
  CULL_DIST_ENA_1           :bit1;
  CULL_DIST_ENA_2           :bit1;
  CULL_DIST_ENA_3           :bit1;
  CULL_DIST_ENA_4           :bit1;
  CULL_DIST_ENA_5           :bit1;
  CULL_DIST_ENA_6           :bit1;
  CULL_DIST_ENA_7           :bit1;
  USE_VTX_POINT_SIZE        :bit1;
  USE_VTX_EDGE_FLAG         :bit1;
  USE_VTX_RENDER_TARGET_INDX:bit1;
  USE_VTX_VIEWPORT_INDX     :bit1;
  USE_VTX_KILL_FLAG         :bit1;
  VS_OUT_MISC_VEC_ENA       :bit1;
  VS_OUT_CCDIST0_VEC_ENA    :bit1;
  VS_OUT_CCDIST1_VEC_ENA    :bit1;
  VS_OUT_MISC_SIDE_BUS_ENA  :bit1;
  USE_VTX_GS_CUT_FLAG       :bit1;
  USE_VTX_LINE_WIDTH        :bit1;
  RESERVED0                 :bit5;
 end;

 TPA_SC_MODE_CNTL_0=bitpacked record
  MSAA_ENABLE             :bit1;
  VPORT_SCISSOR_ENABLE    :bit1;
  LINE_STIPPLE_ENABLE     :bit1;
  SEND_UNLIT_STILES_TO_PKR:bit1;
  RESERVED0               :bit28;
 end;

 TPA_SC_MODE_CNTL_1=bitpacked record
  WALK_SIZE                              :bit1;
  WALK_ALIGNMENT                         :bit1;
  WALK_ALIGN8_PRIM_FITS_ST               :bit1;
  WALK_FENCE_ENABLE                      :bit1;
  WALK_FENCE_SIZE                        :bit3;
  SUPERTILE_WALK_ORDER_ENABLE            :bit1;
  TILE_WALK_ORDER_ENABLE                 :bit1;
  TILE_COVER_DISABLE                     :bit1;
  TILE_COVER_NO_SCISSOR                  :bit1;
  ZMM_LINE_EXTENT                        :bit1;
  ZMM_LINE_OFFSET                        :bit1;
  ZMM_RECT_EXTENT                        :bit1;
  KILL_PIX_POST_HI_Z                     :bit1;
  KILL_PIX_POST_DETAIL_MASK              :bit1;
  PS_ITER_SAMPLE                         :bit1;
  MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE:bit1;
  MULTI_GPU_SUPERTILE_ENABLE             :bit1;
  GPU_ID_OVERRIDE_ENABLE                 :bit1;
  GPU_ID_OVERRIDE                        :bit4;
  MULTI_GPU_PRIM_DISCARD_ENABLE          :bit1;
  FORCE_EOV_CNTDWN_ENABLE                :bit1;
  FORCE_EOV_REZ_ENABLE                   :bit1;
  OUT_OF_ORDER_PRIMITIVE_ENABLE          :bit1;
  OUT_OF_ORDER_WATER_MARK                :bit3;
  RESERVED0                              :bit1;
 end;

 TPA_SU_CNTL_STATUS=bitpacked record
  RESERVED0:bit31;
  SU_BUSY  :bit1;
 end;

 TPB0_GLB_CTRL_REG0=bitpacked record
  BACKUP            :bit16;
  CFG_IDLEDET_TH    :bit2;
  RESERVED0         :bit2;
  DBG_RX2TXBYP_SEL  :bit3;
  DBG_RXFEBYP_EN    :bit1;
  DBG_RXPRBS_CLR    :bit1;
  DBG_RXTOGGLE_EN   :bit1;
  DBG_TX2RXLBACK_EN :bit1;
  RESERVED1         :bit3;
  TXCFG_CMGOOD_RANGE:bit2;
 end;

 TPB0_GLB_CTRL_REG1=bitpacked record
  RXDBG_CDR_FR_BYP_EN :bit1;
  RXDBG_CDR_FR_BYP_VAL:bit6;
  RXDBG_CDR_PH_BYP_EN :bit1;
  RXDBG_CDR_PH_BYP_VAL:bit6;
  RXDBG_D0TH_BYP_EN   :bit1;
  RXDBG_D0TH_BYP_VAL  :bit7;
  RXDBG_D1TH_BYP_EN   :bit1;
  RXDBG_D1TH_BYP_VAL  :bit7;
  TST_LOSPDTST_EN     :bit1;
  PLL_CFG_DISPCLK_DIV :bit1;
 end;

 TPB0_GLB_CTRL_REG2=bitpacked record
  RXDBG_D2TH_BYP_EN :bit1;
  RXDBG_D2TH_BYP_VAL:bit7;
  RXDBG_D3TH_BYP_EN :bit1;
  RXDBG_D3TH_BYP_VAL:bit7;
  RXDBG_DXTH_BYP_EN :bit1;
  RXDBG_DXTH_BYP_VAL:bit7;
  RXDBG_ETH_BYP_EN  :bit1;
  RXDBG_ETH_BYP_VAL :bit7;
 end;

 TPB0_GLB_CTRL_REG3=bitpacked record
  RXDBG_SEL                       :bit5;
  BG_CFG_LC_REG_VREF0_SEL         :bit2;
  BG_CFG_LC_REG_VREF1_SEL         :bit2;
  BG_CFG_RO_REG_VREF_SEL          :bit2;
  BG_DBG_VREFBYP_EN               :bit1;
  BG_DBG_IREFBYP_EN               :bit1;
  RESERVED0                       :bit1;
  BG_DBG_ANALOG_SEL               :bit3;
  RESERVED1                       :bit1;
  DBG_DLL_CLK_SEL                 :bit3;
  PLL_DISPCLK_CMOS_SEL            :bit1;
  DBG_RXPI_OFFSET_BYP_EN          :bit1;
  DBG_RXPI_OFFSET_BYP_VAL         :bit4;
  DBG_RXSWAPDX_BYP_EN             :bit1;
  DBG_RXSWAPDX_BYP_VAL            :bit3;
  DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE:bit1;
 end;

 TPB0_GLB_CTRL_REG4=bitpacked record
  DBG_RXAPU_INST            :bit16;
  DBG_RXDFEMUX_BYP_VAL      :bit2;
  DBG_RXDFEMUX_BYP_EN       :bit1;
  RESERVED0                 :bit3;
  DBG_RXAPU_EXEC            :bit4;
  DBG_RXDLL_VREG_REF_SEL    :bit1;
  PWRGOOD_OVRD              :bit1;
  DBG_RXRDATA_GATING_DISABLE:bit1;
  RESERVED1                 :bit3;
 end;

 TPB0_GLB_CTRL_REG5=bitpacked record
  DBG_RXAPU_MODE:bit8;
  RESERVED0     :bit24;
 end;

 TPB0_GLB_OVRD_REG0=bitpacked record
  TXPDTERM_VAL_OVRD_VAL:bit16;
  TXPUTERM_VAL_OVRD_VAL:bit16;
 end;

 TPB0_GLB_OVRD_REG1=bitpacked record
  TXPDTERM_VAL_OVRD_EN     :bit1;
  TXPUTERM_VAL_OVRD_EN     :bit1;
  TST_LOSPDTST_RST_OVRD_EN :bit1;
  TST_LOSPDTST_RST_OVRD_VAL:bit1;
  RESERVED0                :bit11;
  RXTERM_VAL_OVRD_EN       :bit1;
  RXTERM_VAL_OVRD_VAL      :bit16;
 end;

 TPB0_GLB_OVRD_REG2=bitpacked record
  BG_PWRON_OVRD_EN             :bit1;
  BG_PWRON_OVRD_VAL            :bit1;
  PLL_DBG_LC_EXT_RESET_OVRD_EN :bit1;
  PLL_DBG_LC_EXT_RESET_OVRD_VAL:bit1;
  PLL_DBG_RO_EXT_RESET_OVRD_EN :bit1;
  PLL_DBG_RO_EXT_RESET_OVRD_VAL:bit1;
  RESERVED0                    :bit26;
 end;

 TPB0_PIF_GLB_OVRD2=bitpacked record
  X2_LANE_1_0_OVRD  :bit1;
  X2_LANE_3_2_OVRD  :bit1;
  X2_LANE_5_4_OVRD  :bit1;
  X2_LANE_7_6_OVRD  :bit1;
  X2_LANE_9_8_OVRD  :bit1;
  X2_LANE_11_10_OVRD:bit1;
  X2_LANE_13_12_OVRD:bit1;
  X2_LANE_15_14_OVRD:bit1;
  X4_LANE_3_0_OVRD  :bit1;
  X4_LANE_7_4_OVRD  :bit1;
  X4_LANE_11_8_OVRD :bit1;
  X4_LANE_15_12_OVRD:bit1;
  RESERVED0         :bit4;
  X8_LANE_7_0_OVRD  :bit1;
  X8_LANE_15_8_OVRD :bit1;
  RESERVED1         :bit2;
  X16_LANE_15_0_OVRD:bit1;
  RESERVED2         :bit11;
 end;

 TPB0_STRAP_RX_REG0=bitpacked record
  RESERVED0                      :bit1;
  STRAP_RX_CFG_TH_LOOP_GAIN      :bit4;
  STRAP_RX_CFG_DLL_FLOCK_DISABLE :bit1;
  STRAP_DBG_RXPI_OFFSET_BYP_EN   :bit1;
  STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS:bit1;
  STRAP_BG_CFG_LC_REG_VREF0_SEL  :bit2;
  STRAP_BG_CFG_LC_REG_VREF1_SEL  :bit2;
  STRAP_RX_CFG_CDR_TIME          :bit4;
  STRAP_RX_CFG_FOM_TIME          :bit4;
  STRAP_RX_CFG_LEQ_TIME          :bit4;
  STRAP_RX_CFG_OC_TIME           :bit4;
  STRAP_TX_CFG_RPTR_RST_VAL      :bit3;
  STRAP_RX_CFG_TERM_MODE         :bit1;
 end;

 TPB0_STRAP_RX_REG1=bitpacked record
  RESERVED0                    :bit1;
  STRAP_RX_CFG_CDR_PI_STPSZ    :bit1;
  STRAP_TX_DEEMPH_PRSHT_STNG   :bit3;
  STRAP_BG_CFG_RO_REG_VREF_SEL :bit2;
  STRAP_RX_CFG_LEQ_POLE_BYP_DIS:bit1;
  STRAP_RX_CFG_LEQ_POLE_BYP_VAL:bit3;
  STRAP_RX_CFG_CDR_PH_GAIN     :bit4;
  STRAP_RX_CFG_ADAPT_MODE      :bit10;
  STRAP_RX_CFG_DFE_TIME        :bit4;
  STRAP_RX_CFG_LEQ_LOOP_GAIN   :bit2;
  STRAP_RX_CFG_LEQ_SHUNT_DIS   :bit1;
 end;

 TPB0_STRAP_TX_REG0=bitpacked record
  RESERVED0                  :bit1;
  STRAP_TX_CFG_DRV0_EN       :bit4;
  STRAP_TX_CFG_DRV0_TAP_SEL  :bit4;
  STRAP_TX_CFG_DRV1_EN       :bit5;
  STRAP_TX_CFG_DRV1_TAP_SEL  :bit5;
  STRAP_TX_CFG_DRV2_EN       :bit4;
  STRAP_TX_CFG_DRV2_TAP_SEL  :bit4;
  STRAP_TX_CFG_DRVX_EN       :bit1;
  STRAP_TX_CFG_DRVX_TAP_SEL  :bit1;
  STRAP_RX_TRK_MODE_1_       :bit1;
  STRAP_TX_CFG_SWING_BOOST_EN:bit1;
  RESERVED1                  :bit1;
 end;

 TPB1_GLB_CTRL_REG0=bitpacked record
  BACKUP            :bit16;
  CFG_IDLEDET_TH    :bit2;
  RESERVED0         :bit2;
  DBG_RX2TXBYP_SEL  :bit3;
  DBG_RXFEBYP_EN    :bit1;
  DBG_RXPRBS_CLR    :bit1;
  DBG_RXTOGGLE_EN   :bit1;
  DBG_TX2RXLBACK_EN :bit1;
  RESERVED1         :bit3;
  TXCFG_CMGOOD_RANGE:bit2;
 end;

 TPB1_GLB_CTRL_REG1=bitpacked record
  RXDBG_CDR_FR_BYP_EN :bit1;
  RXDBG_CDR_FR_BYP_VAL:bit6;
  RXDBG_CDR_PH_BYP_EN :bit1;
  RXDBG_CDR_PH_BYP_VAL:bit6;
  RXDBG_D0TH_BYP_EN   :bit1;
  RXDBG_D0TH_BYP_VAL  :bit7;
  RXDBG_D1TH_BYP_EN   :bit1;
  RXDBG_D1TH_BYP_VAL  :bit7;
  TST_LOSPDTST_EN     :bit1;
  PLL_CFG_DISPCLK_DIV :bit1;
 end;

 TPB1_GLB_CTRL_REG2=bitpacked record
  RXDBG_D2TH_BYP_EN :bit1;
  RXDBG_D2TH_BYP_VAL:bit7;
  RXDBG_D3TH_BYP_EN :bit1;
  RXDBG_D3TH_BYP_VAL:bit7;
  RXDBG_DXTH_BYP_EN :bit1;
  RXDBG_DXTH_BYP_VAL:bit7;
  RXDBG_ETH_BYP_EN  :bit1;
  RXDBG_ETH_BYP_VAL :bit7;
 end;

 TPB1_GLB_CTRL_REG3=bitpacked record
  RXDBG_SEL                       :bit5;
  BG_CFG_LC_REG_VREF0_SEL         :bit2;
  BG_CFG_LC_REG_VREF1_SEL         :bit2;
  BG_CFG_RO_REG_VREF_SEL          :bit2;
  BG_DBG_VREFBYP_EN               :bit1;
  BG_DBG_IREFBYP_EN               :bit1;
  RESERVED0                       :bit1;
  BG_DBG_ANALOG_SEL               :bit3;
  RESERVED1                       :bit1;
  DBG_DLL_CLK_SEL                 :bit3;
  PLL_DISPCLK_CMOS_SEL            :bit1;
  DBG_RXPI_OFFSET_BYP_EN          :bit1;
  DBG_RXPI_OFFSET_BYP_VAL         :bit4;
  DBG_RXSWAPDX_BYP_EN             :bit1;
  DBG_RXSWAPDX_BYP_VAL            :bit3;
  DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE:bit1;
 end;

 TPB1_GLB_CTRL_REG4=bitpacked record
  DBG_RXAPU_INST            :bit16;
  DBG_RXDFEMUX_BYP_VAL      :bit2;
  DBG_RXDFEMUX_BYP_EN       :bit1;
  RESERVED0                 :bit3;
  DBG_RXAPU_EXEC            :bit4;
  DBG_RXDLL_VREG_REF_SEL    :bit1;
  PWRGOOD_OVRD              :bit1;
  DBG_RXRDATA_GATING_DISABLE:bit1;
  RESERVED1                 :bit3;
 end;

 TPB1_GLB_CTRL_REG5=bitpacked record
  DBG_RXAPU_MODE:bit8;
  RESERVED0     :bit24;
 end;

 TPB1_GLB_OVRD_REG0=bitpacked record
  TXPDTERM_VAL_OVRD_VAL:bit16;
  TXPUTERM_VAL_OVRD_VAL:bit16;
 end;

 TPB1_GLB_OVRD_REG1=bitpacked record
  TXPDTERM_VAL_OVRD_EN     :bit1;
  TXPUTERM_VAL_OVRD_EN     :bit1;
  TST_LOSPDTST_RST_OVRD_EN :bit1;
  TST_LOSPDTST_RST_OVRD_VAL:bit1;
  RESERVED0                :bit11;
  RXTERM_VAL_OVRD_EN       :bit1;
  RXTERM_VAL_OVRD_VAL      :bit16;
 end;

 TPB1_GLB_OVRD_REG2=bitpacked record
  BG_PWRON_OVRD_EN             :bit1;
  BG_PWRON_OVRD_VAL            :bit1;
  PLL_DBG_LC_EXT_RESET_OVRD_EN :bit1;
  PLL_DBG_LC_EXT_RESET_OVRD_VAL:bit1;
  PLL_DBG_RO_EXT_RESET_OVRD_EN :bit1;
  PLL_DBG_RO_EXT_RESET_OVRD_VAL:bit1;
  RESERVED0                    :bit26;
 end;

 TPB1_PIF_GLB_OVRD2=bitpacked record
  X2_LANE_1_0_OVRD  :bit1;
  X2_LANE_3_2_OVRD  :bit1;
  X2_LANE_5_4_OVRD  :bit1;
  X2_LANE_7_6_OVRD  :bit1;
  X2_LANE_9_8_OVRD  :bit1;
  X2_LANE_11_10_OVRD:bit1;
  X2_LANE_13_12_OVRD:bit1;
  X2_LANE_15_14_OVRD:bit1;
  X4_LANE_3_0_OVRD  :bit1;
  X4_LANE_7_4_OVRD  :bit1;
  X4_LANE_11_8_OVRD :bit1;
  X4_LANE_15_12_OVRD:bit1;
  RESERVED0         :bit4;
  X8_LANE_7_0_OVRD  :bit1;
  X8_LANE_15_8_OVRD :bit1;
  RESERVED1         :bit2;
  X16_LANE_15_0_OVRD:bit1;
  RESERVED2         :bit11;
 end;

 TPB1_STRAP_RX_REG0=bitpacked record
  RESERVED0                      :bit1;
  STRAP_RX_CFG_TH_LOOP_GAIN      :bit4;
  STRAP_RX_CFG_DLL_FLOCK_DISABLE :bit1;
  STRAP_DBG_RXPI_OFFSET_BYP_EN   :bit1;
  STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS:bit1;
  STRAP_BG_CFG_LC_REG_VREF0_SEL  :bit2;
  STRAP_BG_CFG_LC_REG_VREF1_SEL  :bit2;
  STRAP_RX_CFG_CDR_TIME          :bit4;
  STRAP_RX_CFG_FOM_TIME          :bit4;
  STRAP_RX_CFG_LEQ_TIME          :bit4;
  STRAP_RX_CFG_OC_TIME           :bit4;
  STRAP_TX_CFG_RPTR_RST_VAL      :bit3;
  STRAP_RX_CFG_TERM_MODE         :bit1;
 end;

 TPB1_STRAP_RX_REG1=bitpacked record
  RESERVED0                    :bit1;
  STRAP_RX_CFG_CDR_PI_STPSZ    :bit1;
  STRAP_TX_DEEMPH_PRSHT_STNG   :bit3;
  STRAP_BG_CFG_RO_REG_VREF_SEL :bit2;
  STRAP_RX_CFG_LEQ_POLE_BYP_DIS:bit1;
  STRAP_RX_CFG_LEQ_POLE_BYP_VAL:bit3;
  STRAP_RX_CFG_CDR_PH_GAIN     :bit4;
  STRAP_RX_CFG_ADAPT_MODE      :bit10;
  STRAP_RX_CFG_DFE_TIME        :bit4;
  STRAP_RX_CFG_LEQ_LOOP_GAIN   :bit2;
  STRAP_RX_CFG_LEQ_SHUNT_DIS   :bit1;
 end;

 TPB1_STRAP_TX_REG0=bitpacked record
  RESERVED0                  :bit1;
  STRAP_TX_CFG_DRV0_EN       :bit4;
  STRAP_TX_CFG_DRV0_TAP_SEL  :bit4;
  STRAP_TX_CFG_DRV1_EN       :bit5;
  STRAP_TX_CFG_DRV1_TAP_SEL  :bit5;
  STRAP_TX_CFG_DRV2_EN       :bit4;
  STRAP_TX_CFG_DRV2_TAP_SEL  :bit4;
  STRAP_TX_CFG_DRVX_EN       :bit1;
  STRAP_TX_CFG_DRVX_TAP_SEL  :bit1;
  STRAP_RX_TRK_MODE_1_       :bit1;
  STRAP_TX_CFG_SWING_BOOST_EN:bit1;
  RESERVED1                  :bit1;
 end;

 TPCIE_I2C_REG_DATA=bit32;

 TPCIE_LC_LANE_CNTL=bitpacked record
  LC_CORRUPTED_LANES:bit16;
  LC_LANE_DIS       :bit16;
 end;

 TPCIE_PORT_VC_CNTL=bitpacked record
  LOAD_VC_ARB_TABLE:bit1;
  VC_ARB_SELECT    :bit3;
  RESERVED0        :bit28;
 end;

 TPCIE_PRBS_FREERUN=bitpacked record
  PRBS_FREERUN:bit16;
  RESERVED0   :bit16;
 end;

 TPCIE_PRBS_STATUS1=bitpacked record
  PRBS_ERRSTAT:bit16;
  PRBS_LOCKED :bit16;
 end;

 TPCIE_PRBS_STATUS2=bitpacked record
  PRBS_BITCNT_DONE:bit16;
  RESERVED0       :bit16;
 end;

 TPCIE_P_BUF_STATUS=bitpacked record
  P_OVERFLOW_ERR :bit16;
  P_UNDERFLOW_ERR:bit16;
 end;

 TPCIE_RX_LAST_TLP0=bit32;

 TPCIE_RX_LAST_TLP1=bit32;

 TPCIE_RX_LAST_TLP2=bit32;

 TPCIE_RX_LAST_TLP3=bit32;

 TPCIE_SRIOV_STATUS=bitpacked record
  SRIOV_VF_MIGRATION_STATUS:bit1;
  RESERVED0                :bit31;
 end;

 TPCIE_STRAP_I2C_BD=bitpacked record
  STRAP_BIF_I2C_SLV_ADR:bit7;
  STRAP_BIF_DBG_I2C_EN :bit1;
  RESERVED0            :bit24;
 end;

 TPCIE_TPH_REQR_CAP=bitpacked record
  TPH_REQR_NO_ST_MODE_SUPPORTED   :bit1;
  TPH_REQR_INT_VEC_MODE_SUPPORTED :bit1;
  TPH_REQR_DEV_SPC_MODE_SUPPORTED :bit1;
  RESERVED0                       :bit5;
  TPH_REQR_EXTND_TPH_REQR_SUPPORED:bit1;
  TPH_REQR_ST_TABLE_LOCATION      :bit2;
  RESERVED1                       :bit5;
  TPH_REQR_ST_TABLE_SIZE          :bit11;
  RESERVED2                       :bit5;
 end;

 TPCIE_TX_LAST_TLP0=bit32;

 TPCIE_TX_LAST_TLP1=bit32;

 TPCIE_TX_LAST_TLP2=bit32;

 TPCIE_TX_LAST_TLP3=bit32;

 TPERFCOUNTER_STATE=bitpacked record
  PERFCOUNTER_CNT0_STATE:bit2;
  PERFCOUNTER_STATE_SEL0:bit1;
  RESERVED0             :bit1;
  PERFCOUNTER_CNT1_STATE:bit2;
  PERFCOUNTER_STATE_SEL1:bit1;
  RESERVED1             :bit1;
  PERFCOUNTER_CNT2_STATE:bit2;
  PERFCOUNTER_STATE_SEL2:bit1;
  RESERVED2             :bit1;
  PERFCOUNTER_CNT3_STATE:bit2;
  PERFCOUNTER_STATE_SEL3:bit1;
  RESERVED3             :bit1;
  PERFCOUNTER_CNT4_STATE:bit2;
  PERFCOUNTER_STATE_SEL4:bit1;
  RESERVED4             :bit1;
  PERFCOUNTER_CNT5_STATE:bit2;
  PERFCOUNTER_STATE_SEL5:bit1;
  RESERVED5             :bit1;
  PERFCOUNTER_CNT6_STATE:bit2;
  PERFCOUNTER_STATE_SEL6:bit1;
  RESERVED6             :bit1;
  PERFCOUNTER_CNT7_STATE:bit2;
  PERFCOUNTER_STATE_SEL7:bit1;
  RESERVED7             :bit1;
 end;

 TPPLL_STATUS_DEBUG=bitpacked record
  PLL_DEBUG_BUS        :bit16;
  PLL_UNLOCK           :bit1;
  PLL_CAL_RESULT       :bit4;
  RESERVED0            :bit3;
  PLL_POWERGOOD_ISO_ENB:bit1;
  PLL_POWERGOOD_S      :bit1;
  PLL_POWERGOOD_V      :bit1;
  RESERVED1            :bit5;
 end;

 TPRESCALE_VALUES_B=bitpacked record
  PRESCALE_BIAS_B :bit16;
  PRESCALE_SCALE_B:bit16;
 end;

 TPRESCALE_VALUES_G=bitpacked record
  PRESCALE_BIAS_G :bit16;
  PRESCALE_SCALE_G:bit16;
 end;

 TPRESCALE_VALUES_R=bitpacked record
  PRESCALE_BIAS_R :bit16;
  PRESCALE_SCALE_R:bit16;
 end;

 TRAS_CB_SIGNATURE0=bit32;

 TRAS_DB_SIGNATURE0=bit32;

 TRAS_IA_SIGNATURE0=bit32;

 TRAS_IA_SIGNATURE1=bit32;

 TRAS_PA_SIGNATURE0=bit32;

 TRAS_SC_SIGNATURE0=bit32;

 TRAS_SC_SIGNATURE1=bit32;

 TRAS_SC_SIGNATURE2=bit32;

 TRAS_SC_SIGNATURE3=bit32;

 TRAS_SC_SIGNATURE4=bit32;

 TRAS_SC_SIGNATURE5=bit32;

 TRAS_SC_SIGNATURE6=bit32;

 TRAS_SC_SIGNATURE7=bit32;

 TRAS_SQ_SIGNATURE0=bit32;

 TRAS_SX_SIGNATURE0=bit32;

 TRAS_SX_SIGNATURE1=bit32;

 TRAS_SX_SIGNATURE2=bit32;

 TRAS_SX_SIGNATURE3=bit32;

 TRAS_TA_SIGNATURE0=bit32;

 TRAS_TA_SIGNATURE1=bit32;

 TRAS_TD_SIGNATURE0=bit32;

 TREGAMMA_LUT_INDEX=bitpacked record
  REGAMMA_LUT_INDEX:bit9;
  RESERVED0        :bit23;
 end;

 TRLC_CP_SCHEDULERS=bitpacked record
  scheduler0:bit8;
  scheduler1:bit8;
  scheduler2:bit8;
  scheduler3:bit8;
 end;

 TRLC_DYN_PG_STATUS=bit32;

 TRLC_GPM_GENERAL_0=bit32;

 TRLC_GPM_GENERAL_1=bit32;

 TRLC_GPM_GENERAL_2=bit32;

 TRLC_GPM_GENERAL_3=bit32;

 TRLC_GPM_GENERAL_4=bit32;

 TRLC_GPM_GENERAL_5=bit32;

 TRLC_GPM_GENERAL_6=bit32;

 TRLC_GPM_GENERAL_7=bit32;

 TRLC_GPU_IOV_SCH_0=bit32;

 TRLC_GPU_IOV_SCH_1=bit32;

 TRLC_GPU_IOV_SCH_2=bit32;

 TRLC_GPU_IOV_SCH_3=bit32;

 TRLC_SMU_SAFE_MODE=bitpacked record
  CMD      :bit1;
  MESSAGE  :bit4;
  RESERVED1:bit3;
  RESPONSE :bit4;
  RESERVED :bit20;
 end;

 TRLC_SRM_ARAM_ADDR=bitpacked record
  ADDR    :bit10;
  RESERVED:bit22;
 end;

 TRLC_SRM_ARAM_DATA=bit32;

 TRLC_SRM_DRAM_ADDR=bitpacked record
  ADDR    :bit10;
  RESERVED:bit22;
 end;

 TRLC_SRM_DRAM_DATA=bit32;

 TRLC_SRM_GPM_ABORT=bitpacked record
  ABORT   :bit1;
  RESERVED:bit31;
 end;

 TRLC_THREAD1_DELAY=bitpacked record
  CU_IDEL_DELAY        :bit8;
  LBPW_INNER_LOOP_DELAY:bit8;
  LBPW_OUTER_LOOP_DELAY:bit8;
  SPARE                :bit8;
 end;

 TROM_SMC_IND_INDEX=bit32;

 TSCLV_ROUND_OFFSET=bitpacked record
  SCL_ROUND_OFFSET_RGB_Y:bit16;
  SCL_ROUND_OFFSET_CBCR :bit16;
 end;

 TSDMA0_ATOMIC_CNTL=bitpacked record
  LOOP_TIMER           :bit31;
  ATOMIC_RTN_INT_ENABLE:bit1;
 end;

 TSDMA0_GFX_IB_CNTL=bitpacked record
  IB_ENABLE       :bit1;
  RESERVED0       :bit3;
  IB_SWAP_ENABLE  :bit1;
  RESERVED1       :bit3;
  SWITCH_INSIDE_IB:bit1;
  RESERVED2       :bit7;
  CMD_VMID        :bit4;
  RESERVED3       :bit11;
  RESERVED4       :bit1;
 end;

 TSDMA0_GFX_IB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA0_GFX_IB_SIZE=bitpacked record
  SIZE     :bit20;
  RESERVED0:bit12;
 end;

 TSDMA0_GFX_PREEMPT=bitpacked record
  IB_PREEMPT:bit1;
  RESERVED0 :bit31;
 end;

 TSDMA0_GFX_RB_BASE=bit32;

 TSDMA0_GFX_RB_CNTL=bitpacked record
  RB_ENABLE                 :bit1;
  RB_SIZE                   :bit5;
  RESERVED0                 :bit3;
  RB_SWAP_ENABLE            :bit1;
  RESERVED1                 :bit2;
  RPTR_WRITEBACK_ENABLE     :bit1;
  RPTR_WRITEBACK_SWAP_ENABLE:bit1;
  RESERVED2                 :bit2;
  RPTR_WRITEBACK_TIMER      :bit5;
  RESERVED3                 :bit2;
  RB_PRIV                   :bit1;
  RB_VMID                   :bit4;
  RESERVED4                 :bit4;
 end;

 TSDMA0_GFX_RB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA0_GFX_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA0_STATUS1_REG=bitpacked record
  CE_WREQ_IDLE :bit1;
  CE_WR_IDLE   :bit1;
  CE_SPLIT_IDLE:bit1;
  CE_RREQ_IDLE :bit1;
  CE_OUT_IDLE  :bit1;
  CE_IN_IDLE   :bit1;
  CE_DST_IDLE  :bit1;
  RESERVED0    :bit1;
  RESERVED1    :bit1;
  CE_CMD_IDLE  :bit1;
  CE_AFIFO_FULL:bit1;
  RESERVED2    :bit1;
  RESERVED3    :bit1;
  CE_INFO_FULL :bit1;
  CE_INFO1_FULL:bit1;
  RESERVED4    :bit2;
  CE_RD_STALL  :bit1;
  CE_WR_STALL  :bit1;
  RESERVED5    :bit13;
 end;

 TSDMA0_STATUS2_REG=bitpacked record
  ID           :bit2;
  F32_INSTR_PTR:bit14;
  CMD_OP       :bit16;
 end;

 TSDMA0_VM_CTX_CNTL=bitpacked record
  PRIV     :bit1;
  RESERVED0:bit3;
  VMID     :bit4;
  RESERVED1:bit24;
 end;

 TSDMA1_ATOMIC_CNTL=bitpacked record
  LOOP_TIMER           :bit31;
  ATOMIC_RTN_INT_ENABLE:bit1;
 end;

 TSDMA1_GFX_IB_CNTL=bitpacked record
  IB_ENABLE       :bit1;
  RESERVED0       :bit3;
  IB_SWAP_ENABLE  :bit1;
  RESERVED1       :bit3;
  SWITCH_INSIDE_IB:bit1;
  RESERVED2       :bit7;
  CMD_VMID        :bit4;
  RESERVED3       :bit11;
  RESERVED4       :bit1;
 end;

 TSDMA1_GFX_IB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA1_GFX_IB_SIZE=bitpacked record
  SIZE     :bit20;
  RESERVED0:bit12;
 end;

 TSDMA1_GFX_PREEMPT=bitpacked record
  IB_PREEMPT:bit1;
  RESERVED0 :bit31;
 end;

 TSDMA1_GFX_RB_BASE=bit32;

 TSDMA1_GFX_RB_CNTL=bitpacked record
  RB_ENABLE                 :bit1;
  RB_SIZE                   :bit5;
  RESERVED0                 :bit3;
  RB_SWAP_ENABLE            :bit1;
  RESERVED1                 :bit2;
  RPTR_WRITEBACK_ENABLE     :bit1;
  RPTR_WRITEBACK_SWAP_ENABLE:bit1;
  RESERVED2                 :bit2;
  RPTR_WRITEBACK_TIMER      :bit5;
  RESERVED3                 :bit2;
  RB_PRIV                   :bit1;
  RB_VMID                   :bit4;
  RESERVED4                 :bit4;
 end;

 TSDMA1_GFX_RB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA1_GFX_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA1_STATUS1_REG=bitpacked record
  CE_WREQ_IDLE :bit1;
  CE_WR_IDLE   :bit1;
  CE_SPLIT_IDLE:bit1;
  CE_RREQ_IDLE :bit1;
  CE_OUT_IDLE  :bit1;
  CE_IN_IDLE   :bit1;
  CE_DST_IDLE  :bit1;
  RESERVED0    :bit1;
  RESERVED1    :bit1;
  CE_CMD_IDLE  :bit1;
  CE_AFIFO_FULL:bit1;
  RESERVED2    :bit1;
  RESERVED3    :bit1;
  CE_INFO_FULL :bit1;
  CE_INFO1_FULL:bit1;
  RESERVED4    :bit2;
  CE_RD_STALL  :bit1;
  CE_WR_STALL  :bit1;
  RESERVED5    :bit13;
 end;

 TSDMA1_STATUS2_REG=bitpacked record
  ID           :bit2;
  F32_INSTR_PTR:bit14;
  CMD_OP       :bit16;
 end;

 TSDMA1_VM_CTX_CNTL=bitpacked record
  PRIV     :bit1;
  RESERVED0:bit3;
  VMID     :bit4;
  RESERVED1:bit24;
 end;

 TSDMA_PGFSM_CONFIG=bitpacked record
  FSM_ADDR     :bit8;
  POWER_DOWN   :bit1;
  POWER_UP     :bit1;
  P1_SELECT    :bit1;
  P2_SELECT    :bit1;
  WRITE        :bit1;
  READ         :bit1;
  RESERVED0    :bit13;
  SRBM_OVERRIDE:bit1;
  REG_ADDR     :bit4;
 end;

 TSDMA_POWER_GATING=bitpacked record
  PG_CNTL_ENABLE         :bit1;
  AUTOMATIC_STATUS_ENABLE:bit1;
  PG_STATE_VALID         :bit1;
  RESERVED0              :bit1;
  PG_CNTL_STATUS         :bit2;
  SDMA0_ON_CONDITION     :bit1;
  SDMA1_ON_CONDITION     :bit1;
  POWER_OFF_DELAY        :bit12;
  POWER_ON_DELAY         :bit12;
 end;

 TSEM_ACTIVE_FCN_ID=bitpacked record
  VFID     :bit4;
  RESERVED0:bit27;
  VF       :bit1;
 end;

 TSH_MEM_APE1_LIMIT=bit32;

 TSINK_DESCRIPTION0=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION1=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION2=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION3=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION4=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION5=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION6=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION7=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION8=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION9=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSMU_PM_STATUS_100=bit32;

 TSMU_PM_STATUS_101=bit32;

 TSMU_PM_STATUS_102=bit32;

 TSMU_PM_STATUS_103=bit32;

 TSMU_PM_STATUS_104=bit32;

 TSMU_PM_STATUS_105=bit32;

 TSMU_PM_STATUS_106=bit32;

 TSMU_PM_STATUS_107=bit32;

 TSMU_PM_STATUS_108=bit32;

 TSMU_PM_STATUS_109=bit32;

 TSMU_PM_STATUS_110=bit32;

 TSMU_PM_STATUS_111=bit32;

 TSMU_PM_STATUS_112=bit32;

 TSMU_PM_STATUS_113=bit32;

 TSMU_PM_STATUS_114=bit32;

 TSMU_PM_STATUS_115=bit32;

 TSMU_PM_STATUS_116=bit32;

 TSMU_PM_STATUS_117=bit32;

 TSMU_PM_STATUS_118=bit32;

 TSMU_PM_STATUS_119=bit32;

 TSMU_PM_STATUS_120=bit32;

 TSMU_PM_STATUS_121=bit32;

 TSMU_PM_STATUS_122=bit32;

 TSMU_PM_STATUS_123=bit32;

 TSMU_PM_STATUS_124=bit32;

 TSMU_PM_STATUS_125=bit32;

 TSMU_PM_STATUS_126=bit32;

 TSMU_PM_STATUS_127=bit32;

 TSMU_SMC_IND_INDEX=bit32;

 TSPI_CDBG_SYS_HP3D=bitpacked record
  PS_EN    :bit1;
  VS_EN    :bit1;
  GS_EN    :bit1;
  ES_EN    :bit1;
  HS_EN    :bit1;
  LS_EN    :bit1;
  RESERVED0:bit26;
 end;

 TSPI_CONFIG_CNTL_1=bitpacked record
  VTX_DONE_DELAY           :bit4;
  INTERP_ONE_PRIM_PER_ROW  :bit1;
  RESERVED0                :bit1;
  PC_LIMIT_ENABLE          :bit1;
  PC_LIMIT_STRICT          :bit1;
  CRC_SIMD_ID_WADDR_DISABLE:bit1;
  LBPW_CU_CHK_MODE         :bit1;
  LBPW_CU_CHK_CNT          :bit4;
  RESERVED1                :bit2;
  PC_LIMIT_SIZE            :bit16;
 end;

 TSPI_CONFIG_CNTL_2=bitpacked record
  CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD:bit4;
  CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD  :bit4;
  RESERVED0                               :bit24;
 end;

 TSPI_PS_INPUT_ADDR=bitpacked record
  PERSP_SAMPLE_ENA    :bit1;
  PERSP_CENTER_ENA    :bit1;
  PERSP_CENTROID_ENA  :bit1;
  PERSP_PULL_MODEL_ENA:bit1;
  LINEAR_SAMPLE_ENA   :bit1;
  LINEAR_CENTER_ENA   :bit1;
  LINEAR_CENTROID_ENA :bit1;
  LINE_STIPPLE_TEX_ENA:bit1;
  POS_X_FLOAT_ENA     :bit1;
  POS_Y_FLOAT_ENA     :bit1;
  POS_Z_FLOAT_ENA     :bit1;
  POS_W_FLOAT_ENA     :bit1;
  FRONT_FACE_ENA      :bit1;
  ANCILLARY_ENA       :bit1;
  SAMPLE_COVERAGE_ENA :bit1;
  POS_FIXED_PT_ENA    :bit1;
  RESERVED0           :bit16;
 end;

 TSPI_PS_IN_CONTROL=bitpacked record
  NUM_INTERP         :bit6;
  PARAM_GEN          :bit1;
  RESERVED0          :bit7;
  BC_OPTIMIZE_DISABLE:bit1;
  RESERVED1          :bit1;
  RESERVED2          :bit16;
 end;

 TSPI_VS_OUT_CONFIG=bitpacked record
  RESERVED0      :bit1;
  VS_EXPORT_COUNT:bit5;
  VS_HALF_PACK   :bit1;
  RESERVED1      :bit1;
  RESERVED2      :bit5;
  RESERVED3      :bit19;
 end;

 TSPMI_SRAM_ADDRESS=bit32;

 TSQ_BUF_RSRC_WORD0=bit32;

 TSQ_BUF_RSRC_WORD1=bitpacked record
  BASE_ADDRESS_HI:bit16;
  STRIDE         :bit14;
  CACHE_SWIZZLE  :bit1;
  SWIZZLE_ENABLE :bit1;
 end;

 TSQ_BUF_RSRC_WORD2=bit32;

 TSQ_BUF_RSRC_WORD3=bitpacked record
  DST_SEL_X     :bit3;
  DST_SEL_Y     :bit3;
  DST_SEL_Z     :bit3;
  DST_SEL_W     :bit3;
  NUM_FORMAT    :bit3;
  DATA_FORMAT   :bit4;
  ELEMENT_SIZE  :bit2;
  INDEX_STRIDE  :bit2;
  ADD_TID_ENABLE:bit1;
  ATC           :bit1;
  HASH_ENABLE   :bit1;
  HEAP          :bit1;
  MTYPE         :bit3;
  _TYPE         :bit2;
 end;

 TSQ_IMG_RSRC_WORD0=bit32;

 TSQ_IMG_RSRC_WORD1=bitpacked record
  BASE_ADDRESS_HI:bit8;
  MIN_LOD        :bit12;
  DATA_FORMAT    :bit6;
  NUM_FORMAT     :bit4;
  MTYPE          :bit2;
 end;

 TSQ_IMG_RSRC_WORD2=bitpacked record
  WIDTH     :bit14;
  HEIGHT    :bit14;
  PERF_MOD  :bit3;
  INTERLACED:bit1;
 end;

 TSQ_IMG_RSRC_WORD3=bitpacked record
  DST_SEL_X   :bit3;
  DST_SEL_Y   :bit3;
  DST_SEL_Z   :bit3;
  DST_SEL_W   :bit3;
  BASE_LEVEL  :bit4;
  LAST_LEVEL  :bit4;
  TILING_INDEX:bit5;
  POW2_PAD    :bit1;
  MTYPE       :bit1;
  ATC         :bit1;
  _TYPE       :bit4;
 end;

 TSQ_IMG_RSRC_WORD4=bitpacked record
  DEPTH    :bit13;
  PITCH    :bit14;
  RESERVED0:bit5;
 end;

 TSQ_IMG_RSRC_WORD5=bitpacked record
  BASE_ARRAY:bit13;
  LAST_ARRAY:bit13;
  RESERVED0 :bit6;
 end;

 TSQ_IMG_RSRC_WORD6=bitpacked record
  MIN_LOD_WARN   :bit12;
  COUNTER_BANK_ID:bit8;
  LOD_HDW_CNT_EN :bit1;
  COMPRESSION_EN :bit1;
  ALPHA_IS_ON_MSB:bit1;
  COLOR_TRANSFORM:bit1;
  LOST_ALPHA_BITS:bit4;
  LOST_COLOR_BITS:bit4;
 end;

 TSQ_IMG_RSRC_WORD7=bit32;

 TSQ_IMG_SAMP_WORD0=bitpacked record
  CLAMP_X           :bit3;
  CLAMP_Y           :bit3;
  CLAMP_Z           :bit3;
  MAX_ANISO_RATIO   :bit3;
  DEPTH_COMPARE_FUNC:bit3;
  FORCE_UNNORMALIZED:bit1;
  ANISO_THRESHOLD   :bit3;
  MC_COORD_TRUNC    :bit1;
  FORCE_DEGAMMA     :bit1;
  ANISO_BIAS        :bit6;
  TRUNC_COORD       :bit1;
  DISABLE_CUBE_WRAP :bit1;
  FILTER_MODE       :bit2;
  COMPAT_MODE       :bit1;
 end;

 TSQ_IMG_SAMP_WORD1=bitpacked record
  MIN_LOD :bit12;
  MAX_LOD :bit12;
  PERF_MIP:bit4;
  PERF_Z  :bit4;
 end;

 TSQ_IMG_SAMP_WORD2=bitpacked record
  LOD_BIAS          :bit14;
  LOD_BIAS_SEC      :bit6;
  XY_MAG_FILTER     :bit2;
  XY_MIN_FILTER     :bit2;
  Z_FILTER          :bit2;
  MIP_FILTER        :bit2;
  MIP_POINT_PRECLAMP:bit1;
  DISABLE_LSB_CEIL  :bit1;
  FILTER_PREC_FIX   :bit1;
  ANISO_OVERRIDE    :bit1;
 end;

 TSQ_IMG_SAMP_WORD3=bitpacked record
  BORDER_COLOR_PTR :bit12;
  RESERVED0        :bit18;
  BORDER_COLOR_TYPE:bit2;
 end;

 TSQ_POWER_THROTTLE=bitpacked record
  MIN_POWER   :bit14;
  RESERVED0   :bit2;
  MAX_POWER   :bit14;
  PHASE_OFFSET:bit2;
 end;

 TSQ_WAVE_GPR_ALLOC=bitpacked record
  VGPR_BASE:bit6;
  RESERVED0:bit2;
  VGPR_SIZE:bit6;
  RESERVED1:bit2;
  SGPR_BASE:bit6;
  RESERVED2:bit2;
  SGPR_SIZE:bit4;
  RESERVED3:bit4;
 end;

 TSQ_WAVE_LDS_ALLOC=bitpacked record
  LDS_BASE :bit8;
  RESERVED0:bit4;
  LDS_SIZE :bit9;
  RESERVED1:bit11;
 end;

 TSQ_WREXEC_EXEC_HI=bitpacked record
  ADDR_HI   :bit16;
  RESERVED0 :bit10;
  FIRST_WAVE:bit1;
  ATC       :bit1;
  MTYPE     :bit3;
  MSB       :bit1;
 end;

 TSQ_WREXEC_EXEC_LO=bit32;

 TSRBM_CREDIT_RESET=bitpacked record
  CREDIT_RESET_BIF  :bit1;
  CREDIT_RESET_SMU  :bit1;
  CREDIT_RESET_DC   :bit1;
  CREDIT_RESET_GIONB:bit1;
  CREDIT_RESET_ACP  :bit1;
  CREDIT_RESET_XDMA :bit1;
  CREDIT_RESET_ODE  :bit1;
  CREDIT_RESET_REGBB:bit1;
  CREDIT_RESET_VP8  :bit1;
  CREDIT_RESET_GRBM :bit1;
  CREDIT_RESET_UVD  :bit1;
  CREDIT_RESET_VCE0 :bit1;
  CREDIT_RESET_VCE1 :bit1;
  CREDIT_RESET_ISP  :bit1;
  CREDIT_RESET_SAM  :bit1;
  CREDIT_RESET_MCB  :bit1;
  CREDIT_RESET_MCC0 :bit1;
  CREDIT_RESET_MCC1 :bit1;
  CREDIT_RESET_MCC2 :bit1;
  CREDIT_RESET_MCC3 :bit1;
  CREDIT_RESET_MCC4 :bit1;
  CREDIT_RESET_MCC5 :bit1;
  CREDIT_RESET_MCC6 :bit1;
  CREDIT_RESET_MCC7 :bit1;
  CREDIT_RESET_MCD0 :bit1;
  CREDIT_RESET_MCD1 :bit1;
  CREDIT_RESET_MCD2 :bit1;
  CREDIT_RESET_MCD3 :bit1;
  CREDIT_RESET_MCD4 :bit1;
  CREDIT_RESET_MCD5 :bit1;
  CREDIT_RESET_MCD6 :bit1;
  CREDIT_RESET_MCD7 :bit1;
 end;

 TSRBM_PERFMON_CNTL=bitpacked record
  PERFMON_STATE        :bit4;
  RESERVED0            :bit4;
  PERFMON_ENABLE_MODE  :bit2;
  PERFMON_SAMPLE_ENABLE:bit1;
  RESERVED1            :bit21;
 end;

 TSX_MRT0_BLEND_OPT=bitpacked record
  COLOR_SRC_OPT :bit3;
  RESERVED0     :bit1;
  COLOR_DST_OPT :bit3;
  RESERVED1     :bit1;
  COLOR_COMB_FCN:bit3;
  RESERVED2     :bit5;
  ALPHA_SRC_OPT :bit3;
  RESERVED3     :bit1;
  ALPHA_DST_OPT :bit3;
  RESERVED4     :bit1;
  ALPHA_COMB_FCN:bit3;
  RESERVED5     :bit5;
 end;

 TSX_MRT1_BLEND_OPT=bitpacked record
  COLOR_SRC_OPT :bit3;
  RESERVED0     :bit1;
  COLOR_DST_OPT :bit3;
  RESERVED1     :bit1;
  COLOR_COMB_FCN:bit3;
  RESERVED2     :bit5;
  ALPHA_SRC_OPT :bit3;
  RESERVED3     :bit1;
  ALPHA_DST_OPT :bit3;
  RESERVED4     :bit1;
  ALPHA_COMB_FCN:bit3;
  RESERVED5     :bit5;
 end;

 TSX_MRT2_BLEND_OPT=bitpacked record
  COLOR_SRC_OPT :bit3;
  RESERVED0     :bit1;
  COLOR_DST_OPT :bit3;
  RESERVED1     :bit1;
  COLOR_COMB_FCN:bit3;
  RESERVED2     :bit5;
  ALPHA_SRC_OPT :bit3;
  RESERVED3     :bit1;
  ALPHA_DST_OPT :bit3;
  RESERVED4     :bit1;
  ALPHA_COMB_FCN:bit3;
  RESERVED5     :bit5;
 end;

 TSX_MRT3_BLEND_OPT=bitpacked record
  COLOR_SRC_OPT :bit3;
  RESERVED0     :bit1;
  COLOR_DST_OPT :bit3;
  RESERVED1     :bit1;
  COLOR_COMB_FCN:bit3;
  RESERVED2     :bit5;
  ALPHA_SRC_OPT :bit3;
  RESERVED3     :bit1;
  ALPHA_DST_OPT :bit3;
  RESERVED4     :bit1;
  ALPHA_COMB_FCN:bit3;
  RESERVED5     :bit5;
 end;

 TSX_MRT4_BLEND_OPT=bitpacked record
  COLOR_SRC_OPT :bit3;
  RESERVED0     :bit1;
  COLOR_DST_OPT :bit3;
  RESERVED1     :bit1;
  COLOR_COMB_FCN:bit3;
  RESERVED2     :bit5;
  ALPHA_SRC_OPT :bit3;
  RESERVED3     :bit1;
  ALPHA_DST_OPT :bit3;
  RESERVED4     :bit1;
  ALPHA_COMB_FCN:bit3;
  RESERVED5     :bit5;
 end;

 TSX_MRT5_BLEND_OPT=bitpacked record
  COLOR_SRC_OPT :bit3;
  RESERVED0     :bit1;
  COLOR_DST_OPT :bit3;
  RESERVED1     :bit1;
  COLOR_COMB_FCN:bit3;
  RESERVED2     :bit5;
  ALPHA_SRC_OPT :bit3;
  RESERVED3     :bit1;
  ALPHA_DST_OPT :bit3;
  RESERVED4     :bit1;
  ALPHA_COMB_FCN:bit3;
  RESERVED5     :bit5;
 end;

 TSX_MRT6_BLEND_OPT=bitpacked record
  COLOR_SRC_OPT :bit3;
  RESERVED0     :bit1;
  COLOR_DST_OPT :bit3;
  RESERVED1     :bit1;
  COLOR_COMB_FCN:bit3;
  RESERVED2     :bit5;
  ALPHA_SRC_OPT :bit3;
  RESERVED3     :bit1;
  ALPHA_DST_OPT :bit3;
  RESERVED4     :bit1;
  ALPHA_COMB_FCN:bit3;
  RESERVED5     :bit5;
 end;

 TSX_MRT7_BLEND_OPT=bitpacked record
  COLOR_SRC_OPT :bit3;
  RESERVED0     :bit1;
  COLOR_DST_OPT :bit3;
  RESERVED1     :bit1;
  COLOR_COMB_FCN:bit3;
  RESERVED2     :bit5;
  ALPHA_SRC_OPT :bit3;
  RESERVED3     :bit1;
  ALPHA_DST_OPT :bit3;
  RESERVED4     :bit1;
  ALPHA_COMB_FCN:bit3;
  RESERVED5     :bit5;
 end;

 TSX_PS_DOWNCONVERT=bitpacked record
  MRT0:bit4;
  MRT1:bit4;
  MRT2:bit4;
  MRT3:bit4;
  MRT4:bit4;
  MRT5:bit4;
  MRT6:bit4;
  MRT7:bit4;
 end;

 TTCP_CHAN_STEER_HI=bitpacked record
  CHAN8:bit4;
  CHAN9:bit4;
  CHANA:bit4;
  CHANB:bit4;
  CHANC:bit4;
  CHAND:bit4;
  CHANE:bit4;
  CHANF:bit4;
 end;

 TTCP_CHAN_STEER_LO=bitpacked record
  CHAN0:bit4;
  CHAN1:bit4;
  CHAN2:bit4;
  CHAN3:bit4;
  CHAN4:bit4;
  CHAN5:bit4;
  CHAN6:bit4;
  CHAN7:bit4;
 end;

 TTCP_WATCH0_ADDR_H=bitpacked record
  ADDR     :bit16;
  RESERVED0:bit16;
 end;

 TTCP_WATCH0_ADDR_L=bitpacked record
  RESERVED0:bit6;
  ADDR     :bit26;
 end;

 TTCP_WATCH1_ADDR_H=bitpacked record
  ADDR     :bit16;
  RESERVED0:bit16;
 end;

 TTCP_WATCH1_ADDR_L=bitpacked record
  RESERVED0:bit6;
  ADDR     :bit26;
 end;

 TTCP_WATCH2_ADDR_H=bitpacked record
  ADDR     :bit16;
  RESERVED0:bit16;
 end;

 TTCP_WATCH2_ADDR_L=bitpacked record
  RESERVED0:bit6;
  ADDR     :bit26;
 end;

 TTCP_WATCH3_ADDR_H=bitpacked record
  ADDR     :bit16;
  RESERVED0:bit16;
 end;

 TTCP_WATCH3_ADDR_L=bitpacked record
  RESERVED0:bit6;
  ADDR     :bit26;
 end;

 TTMDS_CONTROL_CHAR=bitpacked record
  TMDS_CONTROL_CHAR0_OUT_EN:bit1;
  TMDS_CONTROL_CHAR1_OUT_EN:bit1;
  TMDS_CONTROL_CHAR2_OUT_EN:bit1;
  TMDS_CONTROL_CHAR3_OUT_EN:bit1;
  RESERVED0                :bit28;
 end;

 TUNIPHYA_LINK_CNTL=bitpacked record
  UNIPHY_PFREQCHG                   :bit1;
  RESERVED0                         :bit3;
  UNIPHY_PIXVLD_RESET               :bit1;
  RESERVED1                         :bit3;
  UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3;
  RESERVED2                         :bit1;
  UNIPHY_CHANNEL0_INVERT            :bit1;
  UNIPHY_CHANNEL1_INVERT            :bit1;
  UNIPHY_CHANNEL2_INVERT            :bit1;
  UNIPHY_CHANNEL3_INVERT            :bit1;
  RESERVED3                         :bit4;
  UNIPHY_LANE_STAGGER_DELAY         :bit3;
  RESERVED4                         :bit1;
  UNIPHY_LINK_ENABLE_HPD_MASK       :bit2;
  RESERVED5                         :bit6;
 end;

 TUNIPHYB_LINK_CNTL=bitpacked record
  UNIPHY_PFREQCHG                   :bit1;
  RESERVED0                         :bit3;
  UNIPHY_PIXVLD_RESET               :bit1;
  RESERVED1                         :bit3;
  UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3;
  RESERVED2                         :bit1;
  UNIPHY_CHANNEL0_INVERT            :bit1;
  UNIPHY_CHANNEL1_INVERT            :bit1;
  UNIPHY_CHANNEL2_INVERT            :bit1;
  UNIPHY_CHANNEL3_INVERT            :bit1;
  RESERVED3                         :bit4;
  UNIPHY_LANE_STAGGER_DELAY         :bit3;
  RESERVED4                         :bit1;
  UNIPHY_LINK_ENABLE_HPD_MASK       :bit2;
  RESERVED5                         :bit6;
 end;

 TUNIPHYC_LINK_CNTL=bitpacked record
  UNIPHY_PFREQCHG                   :bit1;
  RESERVED0                         :bit3;
  UNIPHY_PIXVLD_RESET               :bit1;
  RESERVED1                         :bit3;
  UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3;
  RESERVED2                         :bit1;
  UNIPHY_CHANNEL0_INVERT            :bit1;
  UNIPHY_CHANNEL1_INVERT            :bit1;
  UNIPHY_CHANNEL2_INVERT            :bit1;
  UNIPHY_CHANNEL3_INVERT            :bit1;
  RESERVED3                         :bit4;
  UNIPHY_LANE_STAGGER_DELAY         :bit3;
  RESERVED4                         :bit1;
  UNIPHY_LINK_ENABLE_HPD_MASK       :bit2;
  RESERVED5                         :bit6;
 end;

 TUNIPHYD_LINK_CNTL=bitpacked record
  UNIPHY_PFREQCHG                   :bit1;
  RESERVED0                         :bit3;
  UNIPHY_PIXVLD_RESET               :bit1;
  RESERVED1                         :bit3;
  UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3;
  RESERVED2                         :bit1;
  UNIPHY_CHANNEL0_INVERT            :bit1;
  UNIPHY_CHANNEL1_INVERT            :bit1;
  UNIPHY_CHANNEL2_INVERT            :bit1;
  UNIPHY_CHANNEL3_INVERT            :bit1;
  RESERVED3                         :bit4;
  UNIPHY_LANE_STAGGER_DELAY         :bit3;
  RESERVED4                         :bit1;
  UNIPHY_LINK_ENABLE_HPD_MASK       :bit2;
  RESERVED5                         :bit6;
 end;

 TUNIPHYE_LINK_CNTL=bitpacked record
  UNIPHY_PFREQCHG                   :bit1;
  RESERVED0                         :bit3;
  UNIPHY_PIXVLD_RESET               :bit1;
  RESERVED1                         :bit3;
  UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3;
  RESERVED2                         :bit1;
  UNIPHY_CHANNEL0_INVERT            :bit1;
  UNIPHY_CHANNEL1_INVERT            :bit1;
  UNIPHY_CHANNEL2_INVERT            :bit1;
  UNIPHY_CHANNEL3_INVERT            :bit1;
  RESERVED3                         :bit4;
  UNIPHY_LANE_STAGGER_DELAY         :bit3;
  RESERVED4                         :bit1;
  UNIPHY_LINK_ENABLE_HPD_MASK       :bit2;
  RESERVED5                         :bit6;
 end;

 TUNIPHYF_LINK_CNTL=bitpacked record
  UNIPHY_PFREQCHG                   :bit1;
  RESERVED0                         :bit3;
  UNIPHY_PIXVLD_RESET               :bit1;
  RESERVED1                         :bit3;
  UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3;
  RESERVED2                         :bit1;
  UNIPHY_CHANNEL0_INVERT            :bit1;
  UNIPHY_CHANNEL1_INVERT            :bit1;
  UNIPHY_CHANNEL2_INVERT            :bit1;
  UNIPHY_CHANNEL3_INVERT            :bit1;
  RESERVED3                         :bit4;
  UNIPHY_LANE_STAGGER_DELAY         :bit3;
  RESERVED4                         :bit1;
  UNIPHY_LINK_ENABLE_HPD_MASK       :bit2;
  RESERVED5                         :bit6;
 end;

 TUNIPHYG_LINK_CNTL=bitpacked record
  UNIPHY_PFREQCHG                   :bit1;
  RESERVED0                         :bit3;
  UNIPHY_PIXVLD_RESET               :bit1;
  RESERVED1                         :bit3;
  UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3;
  RESERVED2                         :bit1;
  UNIPHY_CHANNEL0_INVERT            :bit1;
  UNIPHY_CHANNEL1_INVERT            :bit1;
  UNIPHY_CHANNEL2_INVERT            :bit1;
  UNIPHY_CHANNEL3_INVERT            :bit1;
  RESERVED3                         :bit4;
  UNIPHY_LANE_STAGGER_DELAY         :bit3;
  RESERVED4                         :bit1;
  UNIPHY_LINK_ENABLE_HPD_MASK       :bit2;
  RESERVED5                         :bit6;
 end;

 TUVD_LMI_ADDR_EXT2=bitpacked record
  SCPU_ADDR_EXT    :bit4;
  SCPU_VM_ADDR_EXT :bit4;
  SCPU_NC0_ADDR_EXT:bit4;
  SCPU_NC1_ADDR_EXT:bit4;
  RESERVED0        :bit16;
 end;

 TUVD_LMI_SWAP_CNTL=bitpacked record
  RB_MC_SWAP      :bit2;
  IB_MC_SWAP      :bit2;
  RB_RPTR_MC_SWAP :bit2;
  VCPU_R_MC_SWAP  :bit2;
  VCPU_W_MC_SWAP  :bit2;
  CM_MC_SWAP      :bit2;
  IT_MC_SWAP      :bit2;
  DB_R_MC_SWAP    :bit2;
  DB_W_MC_SWAP    :bit2;
  CSM_MC_SWAP     :bit2;
  RESERVED0       :bit2;
  MP_REF16_MC_SWAP:bit2;
  DBW_MC_SWAP     :bit2;
  RB_WR_MC_SWAP   :bit2;
  RE_MC_SWAP      :bit2;
  MP_MC_SWAP      :bit2;
 end;

 TUVD_MPC_SET_MUXA0=bitpacked record
  VARA_0   :bit6;
  VARA_1   :bit6;
  VARA_2   :bit6;
  VARA_3   :bit6;
  VARA_4   :bit6;
  RESERVED0:bit2;
 end;

 TUVD_MPC_SET_MUXA1=bitpacked record
  VARA_5   :bit6;
  VARA_6   :bit6;
  VARA_7   :bit6;
  RESERVED0:bit14;
 end;

 TUVD_MPC_SET_MUXB0=bitpacked record
  VARB_0   :bit6;
  VARB_1   :bit6;
  VARB_2   :bit6;
  VARB_3   :bit6;
  VARB_4   :bit6;
  RESERVED0:bit2;
 end;

 TUVD_MPC_SET_MUXB1=bitpacked record
  VARB_5   :bit6;
  VARB_6   :bit6;
  VARB_7   :bit6;
  RESERVED0:bit14;
 end;

 TUVD_SEMA_ADDR_LOW=bitpacked record
  ADDR_22_3:bit20;
  RESERVED0:bit12;
 end;

 TUVD_SUVD_CGC_CTRL=bitpacked record
  SRE_MODE   :bit1;
  SIT_MODE   :bit1;
  SMP_MODE   :bit1;
  SCM_MODE   :bit1;
  SDB_MODE   :bit1;
  SCLR_MODE  :bit1;
  UVD_SC_MODE:bit1;
  RESERVED0  :bit25;
 end;

 TUVD_SUVD_CGC_GATE=bitpacked record
  SRE      :bit1;
  SIT      :bit1;
  SMP      :bit1;
  SCM      :bit1;
  SDB      :bit1;
  SRE_H264 :bit1;
  SRE_HEVC :bit1;
  SIT_H264 :bit1;
  SIT_HEVC :bit1;
  SCM_H264 :bit1;
  SCM_HEVC :bit1;
  SDB_H264 :bit1;
  SDB_HEVC :bit1;
  SCLR     :bit1;
  UVD_SC   :bit1;
  RESERVED0:bit17;
 end;

 TVCE_LMI_SWAP_CNTL=bitpacked record
  VCPU_W_MC_SWAP:bit2;
  WR_MC_CID_SWAP:bit12;
  RESERVED0     :bit6;
  RESERVED1     :bit6;
  RESERVED2     :bit6;
 end;

 TVGA25_PPLL_ANALOG=bitpacked record
  VGA25_CAL_MODE          :bit5;
  VGA25_PPLL_PFD_PULSE_SEL:bit2;
  RESERVED0               :bit1;
  VGA25_PPLL_CP           :bit4;
  VGA25_PPLL_LF_MODE      :bit9;
  RESERVED1               :bit3;
  VGA25_PPLL_IBIAS        :bit8;
 end;

 TVGA25_PPLL_FB_DIV=bitpacked record
  VGA25_PPLL_FB_DIV_FRACTION     :bit4;
  VGA25_PPLL_FB_DIV_FRACTION_CNTL:bit2;
  RESERVED0                      :bit10;
  VGA25_PPLL_FB_DIV              :bit11;
  RESERVED1                      :bit5;
 end;

 TVGA28_PPLL_ANALOG=bitpacked record
  VGA28_CAL_MODE          :bit5;
  VGA28_PPLL_PFD_PULSE_SEL:bit2;
  RESERVED0               :bit1;
  VGA28_PPLL_CP           :bit4;
  VGA28_PPLL_LF_MODE      :bit9;
  RESERVED1               :bit3;
  VGA28_PPLL_IBIAS        :bit8;
 end;

 TVGA28_PPLL_FB_DIV=bitpacked record
  VGA28_PPLL_FB_DIV_FRACTION     :bit4;
  VGA28_PPLL_FB_DIV_FRACTION_CNTL:bit2;
  RESERVED0                      :bit10;
  VGA28_PPLL_FB_DIV              :bit11;
  RESERVED1                      :bit5;
 end;

 TVGA41_PPLL_ANALOG=bitpacked record
  VGA41_CAL_MODE          :bit5;
  VGA41_PPLL_PFD_PULSE_SEL:bit2;
  RESERVED0               :bit1;
  VGA41_PPLL_CP           :bit4;
  VGA41_PPLL_LF_MODE      :bit9;
  RESERVED1               :bit3;
  VGA41_PPLL_IBIAS        :bit8;
 end;

 TVGA41_PPLL_FB_DIV=bitpacked record
  VGA41_PPLL_FB_DIV_FRACTION     :bit4;
  VGA41_PPLL_FB_DIV_FRACTION_CNTL:bit2;
  RESERVED0                      :bit10;
  VGA41_PPLL_FB_DIV              :bit11;
  RESERVED1                      :bit5;
 end;

 TVGA_CACHE_CONTROL=bitpacked record
  VGA_WRITE_THROUGH_CACHE_DIS:bit1;
  RESERVED0                  :bit7;
  VGA_READ_CACHE_DISABLE     :bit1;
  RESERVED1                  :bit7;
  VGA_READ_BUFFER_INVALIDATE :bit1;
  RESERVED2                  :bit3;
  VGA_DCCIF_W256ONLY         :bit1;
  RESERVED3                  :bit3;
  VGA_DCCIF_WC_TIMEOUT       :bit6;
  RESERVED4                  :bit2;
 end;

 TVGA_SOURCE_SELECT=bitpacked record
  VGA_SOURCE_SEL_A:bit3;
  RESERVED0       :bit5;
  VGA_SOURCE_SEL_B:bit3;
  RESERVED1       :bit21;
 end;

 TVGT_NUM_INSTANCES=bit32;

 TVGT_STRMOUT_DELAY=bitpacked record
  SKIP_DELAY  :bit8;
  SE0_WD_DELAY:bit3;
  SE1_WD_DELAY:bit3;
  SE2_WD_DELAY:bit3;
  SE3_WD_DELAY:bit3;
  RESERVED0   :bit12;
 end;

 TVM_CONTEXT0_CNTL2=bitpacked record
  CLEAR_PROTECTION_FAULT_STATUS_ADDR                               :bit1;
  ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT:bit1;
  ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT    :bit1;
  ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES            :bit1;
  WAIT_FOR_IDLE_WHEN_INVALIDATE                                    :bit1;
  RESERVED0                                                        :bit27;
 end;

 TVM_CONTEXT1_CNTL2=bitpacked record
  CLEAR_PROTECTION_FAULT_STATUS_ADDR                               :bit1;
  ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT:bit1;
  ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT    :bit1;
  ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES            :bit1;
  WAIT_FOR_IDLE_WHEN_INVALIDATE                                    :bit1;
  RESERVED0                                                        :bit27;
 end;

 TAFMT_RAMP_CONTROL0=bitpacked record
  AFMT_RAMP_MAX_COUNT:bit24;
  RESERVED0          :bit7;
  AFMT_RAMP_DATA_SIGN:bit1;
 end;

 TAFMT_RAMP_CONTROL1=bitpacked record
  AFMT_RAMP_MIN_COUNT       :bit24;
  AFMT_AUDIO_TEST_CH_DISABLE:bit8;
 end;

 TAFMT_RAMP_CONTROL2=bitpacked record
  AFMT_RAMP_INC_COUNT:bit24;
  RESERVED0          :bit8;
 end;

 TAFMT_RAMP_CONTROL3=bitpacked record
  AFMT_RAMP_DEC_COUNT:bit24;
  RESERVED0          :bit8;
 end;

 TATC_ATS_FAULT_CNTL=bitpacked record
  FAULT_REGISTER_LOG   :bit9;
  RESERVED0            :bit1;
  FAULT_INTERRUPT_TABLE:bit9;
  RESERVED1            :bit1;
  FAULT_CRASH_TABLE    :bit9;
  RESERVED2            :bit3;
 end;

 TATC_ATS_SMU_STATUS=bitpacked record
  VDDGFX_POWERED_DOWN:bit1;
  RESERVED0          :bit31;
 end;

 TATC_L1RD_DEBUG_TLB=bitpacked record
  DISABLE_FRAGMENTS                  :bit1;
  DISABLE_INVALIDATE_BY_ADDRESS_RANGE:bit1;
  RESERVED0                          :bit2;
  EFFECTIVE_CAM_SIZE                 :bit4;
  EFFECTIVE_WORK_QUEUE_SIZE          :bit3;
  RESERVED1                          :bit1;
  CREDITS_L1_L2                      :bit6;
  RESERVED2                          :bit2;
  CREDITS_L1_RPB                     :bit8;
  DEBUG_ECO                          :bit2;
  INVALIDATE_ALL                     :bit1;
  DISABLE_CACHING_FAULT_RETURNS      :bit1;
 end;

 TATC_L1WR_DEBUG_TLB=bitpacked record
  DISABLE_FRAGMENTS                  :bit1;
  DISABLE_INVALIDATE_BY_ADDRESS_RANGE:bit1;
  RESERVED0                          :bit2;
  EFFECTIVE_CAM_SIZE                 :bit4;
  EFFECTIVE_WORK_QUEUE_SIZE          :bit3;
  RESERVED1                          :bit1;
  CREDITS_L1_L2                      :bit6;
  RESERVED2                          :bit2;
  CREDITS_L1_RPB                     :bit8;
  DEBUG_ECO                          :bit2;
  INVALIDATE_ALL                     :bit1;
  DISABLE_CACHING_FAULT_RETURNS      :bit1;
 end;

 TATC_L2_CACHE_DATA0=bitpacked record
  DATA_REGISTER_VALID      :bit1;
  CACHE_ENTRY_VALID        :bit1;
  CACHED_ATTRIBUTES        :bit18;
  VIRTUAL_PAGE_ADDRESS_HIGH:bit4;
  RESERVED0                :bit8;
 end;

 TATC_L2_CACHE_DATA1=bit32;

 TATC_L2_CACHE_DATA2=bitpacked record
  PHYSICAL_PAGE_ADDRESS_LOW:bit28;
  RESERVED0                :bit4;
 end;

 TATC_PERFCOUNTER_HI=bitpacked record
  COUNTER_HI   :bit16;
  COMPARE_VALUE:bit16;
 end;

 TATC_PERFCOUNTER_LO=bit32;

 TAUDIO_DESCRIPTOR10=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR11=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR12=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUDIO_DESCRIPTOR13=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAUX_DPHY_RX_STATUS=bitpacked record
  AUX_RX_STATE                :bit3;
  RESERVED0                   :bit5;
  AUX_RX_SYNC_VALID_COUNT     :bit5;
  RESERVED1                   :bit3;
  AUX_RX_HALF_SYM_PERIOD_FRACT:bit5;
  AUX_RX_HALF_SYM_PERIOD      :bit9;
  RESERVED2                   :bit2;
 end;

 TAUX_DPHY_TX_STATUS=bitpacked record
  AUX_TX_ACTIVE         :bit1;
  RESERVED0             :bit3;
  AUX_TX_STATE          :bit3;
  RESERVED1             :bit9;
  AUX_TX_HALF_SYM_PERIOD:bit9;
  RESERVED2             :bit7;
 end;

 TAZALIA_CRC0_RESULT=bit32;

 TAZALIA_CRC1_RESULT=bit32;

 TAZALIA_STREAM_DATA=bit32;

 TAZ_TEST_DEBUG_DATA=bit32;

 TBIF_ATOMIC_ERR_LOG=bitpacked record
  UR_ATOMIC_OPCODE         :bit1;
  UR_ATOMIC_REQEN_LOW      :bit1;
  RESERVED0                :bit14;
  CLEAR_UR_ATOMIC_OPCODE   :bit1;
  CLEAR_UR_ATOMIC_REQEN_LOW:bit1;
  RESERVED1                :bit14;
 end;

 TBIF_RFE_MMCFG_CNTL=bitpacked record
  CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN:bit1;
  CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL:bit3;
  CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN:bit1;
  CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL:bit3;
  RESERVED0                           :bit24;
 end;

 TBIF_VIRT_RESET_REQ=bitpacked record
  VIRT_RESET_REQ_VF    :bit16;
  RESERVED0            :bit15;
  VIRT_RESET_REQ_SOFTPF:bit1;
 end;

 TBL1_PWM_USER_LEVEL=bitpacked record
  BL1_PWM_USER_LEVEL:bit17;
  RESERVED0         :bit15;
 end;

 TBLND_V_UPDATE_LOCK=bitpacked record
  BLND_DCP_GRPH_V_UPDATE_LOCK     :bit1;
  BLND_DCP_GRPH_SURF_V_UPDATE_LOCK:bit1;
  RESERVED0                       :bit6;
  BLND_DCP_OVL_V_UPDATE_LOCK      :bit1;
  RESERVED1                       :bit7;
  BLND_DCP_CUR_V_UPDATE_LOCK      :bit1;
  RESERVED2                       :bit7;
  BLND_DCP_CUR2_V_UPDATE_LOCK     :bit1;
  RESERVED3                       :bit3;
  BLND_SCL_V_UPDATE_LOCK          :bit1;
  BLND_BLND_V_UPDATE_LOCK         :bit1;
  RESERVED4                       :bit1;
  BLND_V_UPDATE_LOCK_MODE         :bit1;
 end;

 TBL_PWM_PERIOD_CNTL=bitpacked record
  BL_PWM_PERIOD       :bit16;
  BL_PWM_PERIOD_BITCNT:bit4;
  RESERVED0           :bit12;
 end;

 TCB_COLOR0_DCC_BASE=bit32;

 TCB_COLOR1_DCC_BASE=bit32;

 TCB_COLOR2_DCC_BASE=bit32;

 TCB_COLOR3_DCC_BASE=bit32;

 TCB_COLOR4_DCC_BASE=bit32;

 TCB_COLOR5_DCC_BASE=bit32;

 TCB_COLOR6_DCC_BASE=bit32;

 TCB_COLOR7_DCC_BASE=bit32;

 TCB_PERFCOUNTER0_HI=bit32;

 TCB_PERFCOUNTER0_LO=bit32;

 TCB_PERFCOUNTER1_HI=bit32;

 TCB_PERFCOUNTER1_LO=bit32;

 TCB_PERFCOUNTER2_HI=bit32;

 TCB_PERFCOUNTER2_LO=bit32;

 TCB_PERFCOUNTER3_HI=bit32;

 TCB_PERFCOUNTER3_LO=bit32;

 TCGTT_ROM_CLK_CTRL0=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit18;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TCG_THERMAL_INT_ENA=bitpacked record
  THERM_INTH_SET   :bit1;
  THERM_INTL_SET   :bit1;
  THERM_TRIGGER_SET:bit1;
  THERM_INTH_CLR   :bit1;
  THERM_INTL_CLR   :bit1;
  THERM_TRIGGER_CLR:bit1;
  RESERVED0        :bit26;
 end;

 TCNV_TEST_CRC_GREEN=bitpacked record
  RESERVED0              :bit4;
  CNV_TEST_CRC_GREEN_MASK:bit12;
  CNV_TEST_CRC_SIG_GREEN :bit16;
 end;

 TCORB_WRITE_POINTER=bitpacked record
  CORB_WRITE_POINTER:bit8;
  RESERVED0         :bit24;
 end;

 TCP_ATOMIC_PREOP_HI=bit32;

 TCP_ATOMIC_PREOP_LO=bit32;

 TCP_CE_INIT_BASE_HI=bitpacked record
  INIT_BASE_HI:bit16;
  RESERVED0   :bit16;
 end;

 TCP_CE_INIT_BASE_LO=bitpacked record
  RESERVED0   :bit5;
  INIT_BASE_LO:bit27;
 end;

 TCP_CE_ROQ_IB1_STAT=bitpacked record
  CEQ_RPTR_INDIRECT1:bit10;
  RESERVED0         :bit6;
  CEQ_WPTR_INDIRECT1:bit10;
  RESERVED1         :bit6;
 end;

 TCP_CE_ROQ_IB2_STAT=bitpacked record
  CEQ_RPTR_INDIRECT2:bit10;
  RESERVED0         :bit6;
  CEQ_WPTR_INDIRECT2:bit10;
  RESERVED1         :bit6;
 end;

 TCP_DMA_ME_DST_ADDR=bit32;

 TCP_DMA_ME_SRC_ADDR=bit32;

 TCP_DMA_PFP_COMMAND=bitpacked record
  BYTE_COUNT:bit21;
  DIS_WC    :bit1;
  SRC_SWAP  :bit2;
  DST_SWAP  :bit2;
  SAS       :bit1;
  DAS       :bit1;
  SAIC      :bit1;
  DAIC      :bit1;
  RAW_WAIT  :bit1;
  RESERVED0 :bit1;
 end;

 TCP_DMA_PFP_CONTROL=bitpacked record
  RESERVED0       :bit10;
  SRC_MTYPE       :bit2;
  SRC_ATC         :bit1;
  SRC_CACHE_POLICY:bit1;
  RESERVED1       :bit6;
  DST_SELECT      :bit2;
  DST_MTYPE       :bit2;
  DST_ATC         :bit1;
  DST_CACHE_POLICY:bit1;
  RESERVED2       :bit3;
  SRC_SELECT      :bit2;
  RESERVED3       :bit1;
 end;

 TCP_DMA_PIO_COMMAND=bitpacked record
  RESERVED0:bit21;
  RESERVED1:bit1;
  RESERVED2:bit2;
  RESERVED3:bit2;
  RESERVED4:bit1;
  RESERVED5:bit1;
  RESERVED6:bit1;
  RESERVED7:bit1;
  RESERVED8:bit1;
  RESERVED9:bit1;
 end;

 TCP_GRBM_FREE_COUNT=bitpacked record
  FREE_COUNT    :bit6;
  RESERVED0     :bit2;
  FREE_COUNT_GDS:bit6;
  RESERVED1     :bit2;
  FREE_COUNT_PFP:bit6;
  RESERVED2     :bit10;
 end;

 TCP_HPD_ROQ_OFFSETS=bitpacked record
  IQ_OFFSET:bit3;
  RESERVED0:bit5;
  PQ_OFFSET:bit6;
  RESERVED1:bit2;
  IB_OFFSET:bit6;
  RESERVED2:bit10;
 end;

 TCP_HQD_DMA_OFFLOAD=bitpacked record
  DMA_OFFLOAD:bit1;
  RESERVED0  :bit31;
 end;

 TCP_HQD_EOP_CONTROL=bitpacked record
  EOP_SIZE        :bit6;
  RESERVED0       :bit2;
  PROCESSING_EOP  :bit1;
  RESERVED1       :bit3;
  PROCESS_EOP_EN  :bit1;
  PROCESSING_EOPIB:bit1;
  PROCESS_EOPIB_EN:bit1;
  MTYPE           :bit2;
  RESERVED2       :bit6;
  EOP_ATC         :bit1;
  CACHE_POLICY    :bit1;
  RESERVED3       :bit4;
  SIG_SEM_RESULT  :bit2;
  PEND_SIG_SEM    :bit1;
 end;

 TCP_HQD_HQ_CONTROL0=bit32;

 TCP_HQD_HQ_CONTROL1=bit32;

 TCP_INDEX_BASE_ADDR=bit32;

 TCP_PFP_HEADER_DUMP=bit32;

 TCP_RB_RPTR_ADDR_HI=bitpacked record
  RB_RPTR_ADDR_HI:bit16;
  RESERVED0      :bit16;
 end;

 TCP_ROQ1_THRESHOLDS=bitpacked record
  RB1_START   :bit8;
  RB2_START   :bit8;
  R0_IB1_START:bit8;
  R1_IB1_START:bit8;
 end;

 TCP_ROQ2_THRESHOLDS=bitpacked record
  R2_IB1_START:bit8;
  R0_IB2_START:bit8;
  R1_IB2_START:bit8;
  R2_IB2_START:bit8;
 end;

 TCP_SIG_SEM_ADDR_HI=bitpacked record
  SEM_ADDR_HI    :bit16;
  SEM_USE_MAILBOX:bit1;
  RESERVED0      :bit3;
  SEM_SIGNAL_TYPE:bit1;
  RESERVED1      :bit3;
  SEM_CLIENT_CODE:bit2;
  RESERVED2      :bit3;
  SEM_SELECT     :bit3;
 end;

 TCP_SIG_SEM_ADDR_LO=bitpacked record
  SEM_ADDR_SWAP:bit2;
  RESERVED0    :bit1;
  SEM_ADDR_LO  :bit29;
 end;

 TCRTC_BLANK_CONTROL=bitpacked record
  CRTC_CURRENT_BLANK_STATE:bit1;
  RESERVED0               :bit7;
  CRTC_BLANK_DATA_EN      :bit1;
  RESERVED1               :bit7;
  CRTC_BLANK_DE_MODE      :bit1;
  RESERVED2               :bit15;
 end;

 TCRTC_COUNT_CONTROL=bitpacked record
  CRTC_HORZ_COUNT_BY2_EN    :bit1;
  CRTC_HORZ_REPETITION_COUNT:bit4;
  RESERVED0                 :bit27;
 end;

 TCRTC_GSL_VSYNC_GAP=bitpacked record
  CRTC_GSL_VSYNC_GAP_LIMIT        :bit8;
  CRTC_GSL_VSYNC_GAP_DELAY        :bit8;
  CRTC_GSL_VSYNC_GAP_SOURCE_SEL   :bit1;
  CRTC_GSL_VSYNC_GAP_MODE         :bit2;
  CRTC_GSL_VSYNC_GAP_CLEAR        :bit1;
  CRTC_GSL_VSYNC_GAP_OCCURRED     :bit1;
  RESERVED0                       :bit2;
  CRTC_GSL_VSYNC_GAP_MASTER_FASTER:bit1;
  CRTC_GSL_VSYNC_GAP              :bit8;
 end;

 TCRTC_H_SYNC_A_CNTL=bitpacked record
  CRTC_H_SYNC_A_POL   :bit1;
  RESERVED0           :bit15;
  CRTC_COMP_SYNC_A_EN :bit1;
  CRTC_H_SYNC_A_CUTOFF:bit1;
  RESERVED1           :bit14;
 end;

 TCRTC_H_SYNC_B_CNTL=bitpacked record
  CRTC_H_SYNC_B_POL   :bit1;
  RESERVED0           :bit15;
  CRTC_COMP_SYNC_B_EN :bit1;
  CRTC_H_SYNC_B_CUTOFF:bit1;
  RESERVED1           :bit14;
 end;

 TCRTC_STEREO_STATUS=bitpacked record
  CRTC_STEREO_CURRENT_EYE           :bit1;
  RESERVED0                         :bit7;
  CRTC_STEREO_SYNC_OUTPUT           :bit1;
  RESERVED1                         :bit7;
  CRTC_STEREO_SYNC_SELECT           :bit1;
  RESERVED2                         :bit3;
  CRTC_STEREO_EYE_FLAG              :bit1;
  RESERVED3                         :bit3;
  CRTC_STEREO_FORCE_NEXT_EYE_PENDING:bit2;
  RESERVED4                         :bit6;
 end;

 TCRTC_V_SYNC_A_CNTL=bitpacked record
  CRTC_V_SYNC_A_POL:bit1;
  RESERVED0        :bit31;
 end;

 TCRTC_V_SYNC_B_CNTL=bitpacked record
  CRTC_V_SYNC_B_POL:bit1;
  RESERVED0        :bit31;
 end;

 TCUR_STEREO_CONTROL=bitpacked record
  CURSOR_STEREO_EN        :bit1;
  CURSOR_STEREO_OFFSET_YNX:bit1;
  RESERVED0               :bit2;
  CURSOR_PRIMARY_OFFSET   :bit10;
  RESERVED1               :bit2;
  CURSOR_SECONDARY_OFFSET :bit10;
  RESERVED2               :bit6;
 end;

 TDB_CGTT_CLK_CTRL_0=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED      :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TDB_FREE_CACHELINES=bitpacked record
  FREE_DTILE_DEPTH:bit7;
  FREE_PLANE_DEPTH:bit7;
  FREE_Z_DEPTH    :bit7;
  FREE_HTILE_DEPTH:bit4;
  QUAD_READ_REQS  :bit7;
 end;

 TDB_HTILE_DATA_BASE=bit32;

 TDB_PERFCOUNTER0_HI=bit32;

 TDB_PERFCOUNTER0_LO=bit32;

 TDB_PERFCOUNTER1_HI=bit32;

 TDB_PERFCOUNTER1_LO=bit32;

 TDB_PERFCOUNTER2_HI=bit32;

 TDB_PERFCOUNTER2_LO=bit32;

 TDB_PERFCOUNTER3_HI=bit32;

 TDB_PERFCOUNTER3_LO=bit32;

 TDB_PRELOAD_CONTROL=bitpacked record
  START_X:bit8;
  START_Y:bit8;
  MAX_X  :bit8;
  MAX_Y  :bit8;
 end;

 TDB_RENDER_OVERRIDE=bitpacked record
  FORCE_HIZ_ENABLE       :bit2;
  FORCE_HIS_ENABLE0      :bit2;
  FORCE_HIS_ENABLE1      :bit2;
  FORCE_SHADER_Z_ORDER   :bit1;
  FAST_Z_DISABLE         :bit1;
  FAST_STENCIL_DISABLE   :bit1;
  NOOP_CULL_DISABLE      :bit1;
  FORCE_COLOR_KILL       :bit1;
  FORCE_Z_READ           :bit1;
  FORCE_STENCIL_READ     :bit1;
  FORCE_FULL_Z_RANGE     :bit2;
  FORCE_QC_SMASK_CONFLICT:bit1;
  DISABLE_VIEWPORT_CLAMP :bit1;
  IGNORE_SC_ZRANGE       :bit1;
  DISABLE_FULLY_COVERED  :bit1;
  FORCE_Z_LIMIT_SUMM     :bit2;
  MAX_TILES_IN_DTT       :bit5;
  DISABLE_TILE_RATE_TILES:bit1;
  FORCE_Z_DIRTY          :bit1;
  FORCE_STENCIL_DIRTY    :bit1;
  FORCE_Z_VALID          :bit1;
  FORCE_STENCIL_VALID    :bit1;
  PRESERVE_COMPRESSION   :bit1;
 end;

 TDB_STENCIL_CONTROL=bitpacked record
  STENCILFAIL    :bit4;
  STENCILZPASS   :bit4;
  STENCILZFAIL   :bit4;
  STENCILFAIL_BF :bit4;
  STENCILZPASS_BF:bit4;
  STENCILZFAIL_BF:bit4;
  RESERVED0      :bit8;
 end;

 TDB_SUBTILE_CONTROL=bitpacked record
  MSAA1_X  :bit2;
  MSAA1_Y  :bit2;
  MSAA2_X  :bit2;
  MSAA2_Y  :bit2;
  MSAA4_X  :bit2;
  MSAA4_Y  :bit2;
  MSAA8_X  :bit2;
  MSAA8_Y  :bit2;
  MSAA16_X :bit2;
  MSAA16_Y :bit2;
  RESERVED0:bit12;
 end;

 TDB_ZPASS_COUNT_LOW=bit32;

 TDCCG_DISP_CNTL_REG=bitpacked record
  RESERVED0            :bit8;
  ALLOW_SR_ON_TRANS_REQ:bit1;
  RESERVED1            :bit23;
 end;

 TDCCG_DS_DEBUG_CNTL=bitpacked record
  DCCG_DS_DEBUG_COUNT_ENABLE       :bit1;
  RESERVED0                        :bit3;
  DCCG_DS_DEBUG_COUNT_TRIG_VALUE   :bit9;
  RESERVED1                        :bit3;
  DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED:bit1;
  DCCG_DS_DEBUG_COUNT_TRIG_CLEAR   :bit1;
  RESERVED2                        :bit2;
  DCCG_DS_JITTER_COUNT_ENABLE      :bit1;
  DCCG_DS_JITTER_COUNT_SRC_SEL     :bit1;
  RESERVED3                        :bit2;
  DCCG_DS_JITTER_COUNT             :bit8;
 end;

 TDCCG_DS_DTO_MODULO=bit32;

 TDCCG_PERFMON_CNTL2=bitpacked record
  DCCG_PERF_DSICLK_ENABLE:bit1;
  DCCG_PERF_REFCLK_ENABLE:bit1;
  RESERVED0              :bit30;
 end;

 TDCFE_CLOCK_CONTROL=bitpacked record
  RESERVED0                  :bit4;
  DISPCLK_R_DCFE_GATE_DISABLE:bit1;
  RESERVED1                  :bit3;
  DISPCLK_G_DCP_GATE_DISABLE :bit1;
  RESERVED2                  :bit3;
  DISPCLK_G_SCL_GATE_DISABLE :bit1;
  RESERVED3                  :bit11;
  DCFE_TEST_CLK_SEL          :bit5;
  RESERVED4                  :bit2;
  DCFE_CLOCK_ENABLE          :bit1;
 end;

 TDCFE_MEM_PWR_CTRL2=bitpacked record
  DCP_LUT_MEM_PWR_MODE_SEL    :bit2;
  DCP_REGAMMA_MEM_PWR_MODE_SEL:bit2;
  SCL_COEFF_MEM_PWR_MODE_SEL  :bit2;
  DCP_CURSOR_MEM_PWR_MODE_SEL :bit2;
  LB_ALPHA_MEM_PWR_MODE_SEL   :bit2;
  LB_MEM_PWR_MODE_SEL         :bit2;
  DCP_CURSOR2_MEM_PWR_MODE_SEL:bit2;
  BLND_MEM_PWR_MODE_SEL       :bit2;
  BLND_MEM_PWR_FORCE          :bit2;
  BLND_MEM_PWR_DIS            :bit1;
  OVLSCL_MEM_PWR_FORCE        :bit1;
  OVLSCL_MEM_PWR_DIS          :bit1;
  DCP_CURSOR2_MEM_PWR_FORCE   :bit2;
  DCP_CURSOR2_MEM_PWR_DIS     :bit1;
  RESERVED0                   :bit8;
 end;

 TDCI_MEM_PWR_STATUS=bitpacked record
  DMIF_RDREQ_MEM1_PWR_STATE:bit2;
  DMIF_RDREQ_MEM2_PWR_STATE:bit2;
  MCIF_RDREQ_MEM_PWR_STATE :bit1;
  RESERVED0                :bit1;
  MCIF_WRREQ_MEM_PWR_STATE :bit1;
  RESERVED1                :bit1;
  VGA_MEM_PWR_STATE        :bit1;
  DMCU_ERAM_MEM_PWR_STATE  :bit2;
  DMCU_IRAM_MEM_PWR_STATE  :bit1;
  FBC_MEM_PWR_STATE        :bit2;
  MCIF_MEM_PWR_STATE       :bit2;
  MCIF_DWB_MEM_PWR_STATE   :bit2;
  MCIF_CWB0_MEM_PWR_STATE  :bit2;
  MCIF_CWB1_MEM_PWR_STATE  :bit2;
  VIP_MEM_PWR_STATE        :bit1;
  RESERVED2                :bit1;
  DMIF0_ASYNC_MEM_PWR_STATE:bit2;
  DMIF0_DATA_MEM_PWR_STATE :bit2;
  DMIF0_CHUNK_MEM_PWR_STATE:bit1;
  RESERVED3                :bit3;
 end;

 TDCO_MEM_PWR_STATUS=bitpacked record
  I2C_MEM_PWR_STATE  :bit1;
  TVOUT_MEM_PWR_STATE:bit1;
  MVP_MEM_PWR_STATE  :bit1;
  DPA_MEM_PWR_STATE  :bit1;
  DPB_MEM_PWR_STATE  :bit1;
  DPC_MEM_PWR_STATE  :bit1;
  DPD_MEM_PWR_STATE  :bit1;
  DPE_MEM_PWR_STATE  :bit1;
  DPF_MEM_PWR_STATE  :bit1;
  DPG_MEM_PWR_STATE  :bit1;
  HDMI0_MEM_PWR_STATE:bit2;
  HDMI1_MEM_PWR_STATE:bit2;
  HDMI2_MEM_PWR_STATE:bit2;
  HDMI3_MEM_PWR_STATE:bit2;
  HDMI4_MEM_PWR_STATE:bit2;
  HDMI5_MEM_PWR_STATE:bit2;
  HDMI6_MEM_PWR_STATE:bit2;
  RESERVED0          :bit8;
 end;

 TDCO_STEREOSYNC_SEL=bitpacked record
  GENERICA_STEREOSYNC_SEL:bit3;
  RESERVED0              :bit13;
  GENERICB_STEREOSYNC_SEL:bit3;
  RESERVED1              :bit13;
 end;

 TDC_ABM1_DEBUG_MISC=bitpacked record
  ABM1_HG_FORCE_INTERRUPT:bit1;
  RESERVED0              :bit7;
  ABM1_LS_FORCE_INTERRUPT:bit1;
  RESERVED1              :bit7;
  ABM1_BL_FORCE_INTERRUPT:bit1;
  RESERVED2              :bit15;
 end;

 TDC_GPIO_DVODATA_EN=bitpacked record
  DC_GPIO_DVODATA_EN    :bit24;
  DC_GPIO_DVOCNTL_EN    :bit5;
  DC_GPIO_DVOCLK_EN     :bit1;
  DC_GPIO_MVP_DVOCNTL_EN:bit2;
 end;

 TDC_GPIO_GENERIC_EN=bitpacked record
  DC_GPIO_GENERICA_EN:bit1;
  RESERVED0          :bit7;
  DC_GPIO_GENERICB_EN:bit1;
  RESERVED1          :bit7;
  DC_GPIO_GENERICC_EN:bit1;
  RESERVED2          :bit3;
  DC_GPIO_GENERICD_EN:bit1;
  DC_GPIO_GENERICE_EN:bit1;
  DC_GPIO_GENERICF_EN:bit1;
  DC_GPIO_GENERICG_EN:bit1;
  RESERVED3          :bit8;
 end;

 TDC_GPIO_GENLK_MASK=bitpacked record
  DC_GPIO_GENLK_CLK_MASK    :bit1;
  DC_GPIO_GENLK_CLK_PD_DIS  :bit1;
  DC_GPIO_GENLK_CLK_RECV    :bit1;
  DC_GPIO_GENLK_CLK_PU_EN   :bit1;
  RESERVED0                 :bit4;
  DC_GPIO_GENLK_VSYNC_MASK  :bit1;
  DC_GPIO_GENLK_VSYNC_PD_DIS:bit1;
  DC_GPIO_GENLK_VSYNC_RECV  :bit1;
  DC_GPIO_GENLK_VSYNC_PU_EN :bit1;
  RESERVED1                 :bit4;
  DC_GPIO_SWAPLOCK_A_MASK   :bit1;
  DC_GPIO_SWAPLOCK_A_PD_DIS :bit1;
  DC_GPIO_SWAPLOCK_A_RECV   :bit1;
  DC_GPIO_SWAPLOCK_A_PU_EN  :bit1;
  RESERVED2                 :bit4;
  DC_GPIO_SWAPLOCK_B_MASK   :bit1;
  DC_GPIO_SWAPLOCK_B_PD_DIS :bit1;
  DC_GPIO_SWAPLOCK_B_RECV   :bit1;
  DC_GPIO_SWAPLOCK_B_PU_EN  :bit1;
  RESERVED3                 :bit4;
 end;

 TDC_GPIO_SYNCA_MASK=bitpacked record
  DC_GPIO_HSYNCA_MASK           :bit1;
  RESERVED0                     :bit3;
  DC_GPIO_HSYNCA_PD_DIS         :bit1;
  RESERVED1                     :bit1;
  DC_GPIO_HSYNCA_RECV           :bit1;
  RESERVED2                     :bit1;
  DC_GPIO_VSYNCA_MASK           :bit1;
  RESERVED3                     :bit3;
  DC_GPIO_VSYNCA_PD_DIS         :bit1;
  RESERVED4                     :bit1;
  DC_GPIO_VSYNCA_RECV           :bit1;
  RESERVED5                     :bit9;
  DC_GPIO_HSYNCA_CRTC_HSYNC_MASK:bit3;
  RESERVED6                     :bit1;
  DC_GPIO_VSYNCA_CRTC_VSYNC_MASK:bit3;
  RESERVED7                     :bit1;
 end;

 TDC_HPD1_INT_STATUS=bitpacked record
  DC_HPD1_INT_STATUS   :bit1;
  DC_HPD1_SENSE        :bit1;
  RESERVED0            :bit6;
  DC_HPD1_RX_INT_STATUS:bit1;
  RESERVED1            :bit23;
 end;

 TDC_HPD2_INT_STATUS=bitpacked record
  DC_HPD2_INT_STATUS   :bit1;
  DC_HPD2_SENSE        :bit1;
  RESERVED0            :bit6;
  DC_HPD2_RX_INT_STATUS:bit1;
  RESERVED1            :bit23;
 end;

 TDC_HPD3_INT_STATUS=bitpacked record
  DC_HPD3_INT_STATUS   :bit1;
  DC_HPD3_SENSE        :bit1;
  RESERVED0            :bit6;
  DC_HPD3_RX_INT_STATUS:bit1;
  RESERVED1            :bit23;
 end;

 TDC_HPD4_INT_STATUS=bitpacked record
  DC_HPD4_INT_STATUS   :bit1;
  DC_HPD4_SENSE        :bit1;
  RESERVED0            :bit6;
  DC_HPD4_RX_INT_STATUS:bit1;
  RESERVED1            :bit23;
 end;

 TDC_HPD5_INT_STATUS=bitpacked record
  DC_HPD5_INT_STATUS   :bit1;
  DC_HPD5_SENSE        :bit1;
  RESERVED0            :bit6;
  DC_HPD5_RX_INT_STATUS:bit1;
  RESERVED1            :bit23;
 end;

 TDC_HPD6_INT_STATUS=bitpacked record
  DC_HPD6_INT_STATUS   :bit1;
  DC_HPD6_SENSE        :bit1;
  RESERVED0            :bit6;
  DC_HPD6_RX_INT_STATUS:bit1;
  RESERVED1            :bit23;
 end;

 TDC_HPD_INT_CONTROL=bitpacked record
  DC_HPD_INT_ACK     :bit1;
  RESERVED0          :bit7;
  DC_HPD_INT_POLARITY:bit1;
  RESERVED1          :bit7;
  DC_HPD_INT_EN      :bit1;
  RESERVED2          :bit3;
  DC_HPD_RX_INT_ACK  :bit1;
  RESERVED3          :bit3;
  DC_HPD_RX_INT_EN   :bit1;
  RESERVED4          :bit7;
 end;

 TDC_I2C_ARBITRATION=bitpacked record
  DC_I2C_SW_PRIORITY            :bit2;
  DC_I2C_REG_RW_CNTL_STATUS     :bit2;
  DC_I2C_NO_QUEUED_SW_GO        :bit1;
  RESERVED0                     :bit1;
  RESERVED1                     :bit2;
  DC_I2C_ABORT_HW_XFER          :bit1;
  RESERVED2                     :bit3;
  DC_I2C_ABORT_SW_XFER          :bit1;
  RESERVED3                     :bit7;
  DC_I2C_SW_USE_I2C_REG_REQ     :bit1;
  DC_I2C_SW_DONE_USING_I2C_REG  :bit1;
  RESERVED4                     :bit2;
  DC_I2C_DMCU_USE_I2C_REG_REQ   :bit1;
  DC_I2C_DMCU_DONE_USING_I2C_REG:bit1;
  RESERVED5                     :bit6;
 end;

 TDC_IP_REQUEST_CNTL=bitpacked record
  IP_REQUEST_EN:bit1;
  RESERVED0    :bit31;
 end;

 TDC_PGFSM_WRITE_REG=bit32;

 TDC_TEST_DEBUG_DATA=bit32;

 TDIDT_DBR_WEIGHT0_3=bitpacked record
  WEIGHT0:bit8;
  WEIGHT1:bit8;
  WEIGHT2:bit8;
  WEIGHT3:bit8;
 end;

 TDIDT_DBR_WEIGHT4_7=bitpacked record
  WEIGHT4:bit8;
  WEIGHT5:bit8;
  WEIGHT6:bit8;
  WEIGHT7:bit8;
 end;

 TDIDT_DB_WEIGHT8_11=bitpacked record
  WEIGHT8 :bit8;
  WEIGHT9 :bit8;
  WEIGHT10:bit8;
  WEIGHT11:bit8;
 end;

 TDIDT_SQ_WEIGHT8_11=bitpacked record
  WEIGHT8 :bit8;
  WEIGHT9 :bit8;
  WEIGHT10:bit8;
  WEIGHT11:bit8;
 end;

 TDIDT_TCP_WEIGHT0_3=bitpacked record
  WEIGHT0:bit8;
  WEIGHT1:bit8;
  WEIGHT2:bit8;
  WEIGHT3:bit8;
 end;

 TDIDT_TCP_WEIGHT4_7=bitpacked record
  WEIGHT4:bit8;
  WEIGHT5:bit8;
  WEIGHT6:bit8;
  WEIGHT7:bit8;
 end;

 TDIDT_TD_WEIGHT8_11=bitpacked record
  WEIGHT8 :bit8;
  WEIGHT9 :bit8;
  WEIGHT10:bit8;
  WEIGHT11:bit8;
 end;

 TDISP_TIMER_CONTROL=bitpacked record
  DISP_TIMER_INT_COUNT  :bit25;
  DISP_TIMER_INT_ENABLE :bit1;
  DISP_TIMER_INT_RUNNING:bit1;
  DISP_TIMER_INT_MSK    :bit1;
  DISP_TIMER_INT_STAT   :bit1;
  DISP_TIMER_INT_STAT_AK:bit1;
  DISP_TIMER_INT        :bit1;
  RESERVED0             :bit1;
 end;

 TDMCU_EVENT_TRIGGER=bitpacked record
  GEN_SW_INT_TO_UC           :bit1;
  RESERVED0                  :bit15;
  UC_INTERNAL_INT_CODE       :bit7;
  GEN_UC_INTERNAL_INT_TO_HOST:bit1;
  RESERVED1                  :bit7;
  RESERVED2                  :bit1;
 end;

 TDMCU_FW_START_ADDR=bitpacked record
  FW_START_ADDR_LSB:bit8;
  FW_START_ADDR_MSB:bit8;
  RESERVED0        :bit16;
 end;

 TDMCU_PC_START_ADDR=bitpacked record
  PC_START_ADDR_LSB:bit8;
  PC_START_ADDR_MSB:bit8;
  RESERVED0        :bit16;
 end;

 TDMIF_DEBUG02_CORE0=bitpacked record
  DB_DATA          :bit16;
  MC_RDRET_COUNT_EN:bit1;
  MC_RDRET_COUNTER :bit11;
  RESERVED0        :bit4;
 end;

 TDMIF_DEBUG02_CORE1=bitpacked record
  DB_DATA          :bit16;
  MC_RDRET_COUNT_EN:bit1;
  MC_RDRET_COUNTER :bit11;
  RESERVED0        :bit4;
 end;

 TDP_DPHY_8B10B_CNTL=bitpacked record
  RESERVED0          :bit8;
  DPHY_8B10B_RESET   :bit1;
  RESERVED1          :bit7;
  DPHY_8B10B_EXT_DISP:bit1;
  RESERVED2          :bit7;
  DPHY_8B10B_CUR_DISP:bit1;
  RESERVED3          :bit7;
 end;

 TDP_DPHY_CRC_RESULT=bitpacked record
  DPHY_CRC_RESULT :bit8;
  DPHY_CRC_RESULT1:bit8;
  DPHY_CRC_RESULT2:bit8;
  DPHY_CRC_RESULT3:bit8;
 end;

 TDP_MSA_COLORIMETRY=bitpacked record
  DP_MSA_MISC0_OVERRIDE       :bit8;
  DP_MSA_MISC0_OVERRIDE_ENABLE:bit1;
  RESERVED0                   :bit23;
 end;

 TDP_MSE_LINK_TIMING=bitpacked record
  DP_MSE_LINK_FRAME:bit10;
  RESERVED0        :bit6;
  DP_MSE_LINK_LINE :bit2;
  RESERVED1        :bit14;
 end;

 TDP_MSE_RATE_UPDATE=bitpacked record
  DP_MSE_RATE_UPDATE_PENDING:bit1;
  RESERVED0                 :bit31;
 end;

 TDP_SEC_PACKET_CNTL=bitpacked record
  RESERVED0                        :bit1;
  DP_SEC_ASP_CODING_TYPE           :bit3;
  DP_SEC_ASP_PRIORITY              :bit1;
  RESERVED1                        :bit3;
  DP_SEC_VERSION                   :bit6;
  RESERVED2                        :bit2;
  DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE:bit1;
  RESERVED3                        :bit15;
 end;

 TDP_TEST_DEBUG_DATA=bit32;

 TDP_VID_STREAM_CNTL=bitpacked record
  DP_VID_STREAM_ENABLE        :bit1;
  RESERVED0                   :bit7;
  DP_VID_STREAM_DIS_DEFER     :bit2;
  RESERVED1                   :bit6;
  DP_VID_STREAM_STATUS        :bit1;
  RESERVED2                   :bit3;
  DP_VID_STREAM_CHANGE_KEEPOUT:bit1;
  RESERVED3                   :bit11;
 end;

 TFMT_FORCE_DATA_0_1=bitpacked record
  FMT_FORCE_DATA0:bit16;
  FMT_FORCE_DATA1:bit16;
 end;

 TFMT_FORCE_DATA_2_3=bitpacked record
  FMT_FORCE_DATA2:bit16;
  FMT_FORCE_DATA3:bit16;
 end;

 TGAMMA_CORR_CONTROL=bitpacked record
  GAMMA_CORR_MODE:bit2;
  RESERVED0      :bit30;
 end;

 TGB_MACROTILE_MODE0=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE1=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE2=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE3=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE4=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE5=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE6=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE7=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE8=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE9=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGC_CAC_WEIGHT_CU_0=bitpacked record
  WEIGHT_CU_SIG0:bit16;
  WEIGHT_CU_SIG1:bit16;
 end;

 TGC_CAC_WEIGHT_CU_1=bitpacked record
  WEIGHT_CU_SIG2:bit16;
  WEIGHT_CU_SIG3:bit16;
 end;

 TGC_CAC_WEIGHT_CU_2=bitpacked record
  WEIGHT_CU_SIG4:bit16;
  WEIGHT_CU_SIG5:bit16;
 end;

 TGC_CAC_WEIGHT_CU_3=bitpacked record
  WEIGHT_CU_SIG6:bit16;
  WEIGHT_CU_SIG7:bit16;
 end;

 TGC_CAC_WEIGHT_CU_4=bitpacked record
  WEIGHT_CU_SIG8:bit16;
  WEIGHT_CU_SIG9:bit16;
 end;

 TGC_CAC_WEIGHT_CU_5=bitpacked record
  WEIGHT_CU_SIG10:bit16;
  WEIGHT_CU_SIG11:bit16;
 end;

 TGC_CAC_WEIGHT_CU_6=bitpacked record
  WEIGHT_CU_SIG12:bit16;
  WEIGHT_CU_SIG13:bit16;
 end;

 TGC_CAC_WEIGHT_CU_7=bitpacked record
  WEIGHT_CU_SIG14:bit16;
  WEIGHT_CU_SIG15:bit16;
 end;

 TGDS_PS0_CTXSW_CNT0=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS0_CTXSW_CNT1=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS0_CTXSW_CNT2=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS0_CTXSW_CNT3=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS1_CTXSW_CNT0=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS1_CTXSW_CNT1=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS1_CTXSW_CNT2=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS1_CTXSW_CNT3=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS2_CTXSW_CNT0=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS2_CTXSW_CNT1=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS2_CTXSW_CNT2=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS2_CTXSW_CNT3=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS3_CTXSW_CNT0=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS3_CTXSW_CNT1=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS3_CTXSW_CNT2=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS3_CTXSW_CNT3=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS4_CTXSW_CNT0=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS4_CTXSW_CNT1=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS4_CTXSW_CNT2=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS4_CTXSW_CNT3=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS5_CTXSW_CNT0=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS5_CTXSW_CNT1=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS5_CTXSW_CNT2=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS5_CTXSW_CNT3=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS6_CTXSW_CNT0=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS6_CTXSW_CNT1=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS6_CTXSW_CNT2=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS6_CTXSW_CNT3=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS7_CTXSW_CNT0=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS7_CTXSW_CNT1=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS7_CTXSW_CNT2=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_PS7_CTXSW_CNT3=bitpacked record
  UPDN:bit16;
  PTR :bit16;
 end;

 TGDS_RD_BURST_COUNT=bit32;

 TGDS_WRITE_COMPLETE=bit32;

 TGENERIC_I2C_STATUS=bitpacked record
  GENERIC_I2C_STATUS         :bit4;
  GENERIC_I2C_DONE           :bit1;
  GENERIC_I2C_ABORTED        :bit1;
  GENERIC_I2C_TIMEOUT        :bit1;
  RESERVED0                  :bit2;
  GENERIC_I2C_STOPPED_ON_NACK:bit1;
  GENERIC_I2C_NACK           :bit1;
  RESERVED1                  :bit21;
 end;

 TGMCON_PGFSM_CONFIG=bitpacked record
  FSM_ADDR     :bit8;
  POWER_DOWN   :bit1;
  POWER_UP     :bit1;
  P1_SELECT    :bit1;
  P2_SELECT    :bit1;
  WRITE        :bit1;
  READ         :bit1;
  RSRVD        :bit13;
  SRBM_OVERRIDE:bit1;
  REG_ADDR     :bit4;
 end;

 TGMCON_RENG_EXECUTE=bitpacked record
  RENG_EXECUTE_ON_PWR_UP    :bit1;
  RENG_EXECUTE_NOW          :bit1;
  RENG_EXECUTE_NOW_START_PTR:bit10;
  RENG_EXECUTE_DSP_END_PTR  :bit10;
  RENG_EXECUTE_END_PTR      :bit10;
 end;

 TGPU_HDP_FLUSH_DONE=bitpacked record
  CP0      :bit1;
  CP1      :bit1;
  CP2      :bit1;
  CP3      :bit1;
  CP4      :bit1;
  CP5      :bit1;
  CP6      :bit1;
  CP7      :bit1;
  CP8      :bit1;
  CP9      :bit1;
  SDMA0    :bit1;
  SDMA1    :bit1;
  RESERVED0:bit20;
 end;

 TGRBM_HYP_CAM_INDEX=bitpacked record
  CAM_INDEX:bit3;
  RESERVED0:bit29;
 end;

 TGRBM_TRAP_ADDR_MSK=bitpacked record
  DATA     :bit16;
  RESERVED0:bit16;
 end;

 THDP_HOST_PATH_CNTL=bitpacked record
  BIF_RDRET_CREDIT       :bit3;
  MC_WRREQ_CREDIT        :bit6;
  WR_STALL_TIMER         :bit2;
  RD_STALL_TIMER         :bit2;
  RESERVED0              :bit6;
  WRITE_COMBINE_TIMER    :bit2;
  WRITE_COMBINE_EN       :bit1;
  CACHE_INVALIDATE       :bit1;
  CLOCK_GATING_DIS       :bit1;
  REG_CLK_ENABLE_COUNT   :bit4;
  RESERVED1              :bit1;
  ALL_SURFACES_DIS       :bit1;
  WRITE_THROUGH_CACHE_DIS:bit1;
  LIN_RD_CACHE_DIS       :bit1;
 end;

 THDP_XDP_D2H_RSVD_3=bit32;

 THDP_XDP_D2H_RSVD_4=bit32;

 THDP_XDP_D2H_RSVD_5=bit32;

 THDP_XDP_D2H_RSVD_6=bit32;

 THDP_XDP_D2H_RSVD_7=bit32;

 THDP_XDP_D2H_RSVD_8=bit32;

 THDP_XDP_D2H_RSVD_9=bit32;

 THDP_XDP_HDP_MC_CFG=bitpacked record
  HDP_MC_CFG_HST_TAP_WRREQ_PRIV       :bit1;
  HDP_MC_CFG_HST_TAP_WRREQ_SWAP       :bit2;
  HDP_MC_CFG_HST_TAP_WRREQ_TRAN       :bit1;
  HDP_MC_CFG_SID_TAP_WRREQ_PRIV       :bit1;
  HDP_MC_CFG_SID_TAP_WRREQ_SWAP       :bit2;
  HDP_MC_CFG_SID_TAP_WRREQ_TRAN       :bit1;
  HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE  :bit6;
  HDP_MC_CFG_XDP_HIGHER_PRI_THRESH    :bit6;
  HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK:bit3;
  HDP_MC_CFG_HST_TAP_WRREQ_VMID       :bit4;
  HDP_MC_CFG_SID_TAP_WRREQ_VMID       :bit4;
  RESERVED0                           :bit1;
 end;

 TIA_MULTI_VGT_PARAM=bitpacked record
  PRIMGROUP_SIZE     :bit16;
  PARTIAL_VS_WAVE_ON :bit1;
  SWITCH_ON_EOP      :bit1;
  PARTIAL_ES_WAVE_ON :bit1;
  SWITCH_ON_EOI      :bit1;
  WD_SWITCH_ON_EOP   :bit1;
  RESERVED0          :bit7;
  MAX_PRIMGRP_IN_WAVE:bit4;
 end;

 TIA_PERFCOUNTER0_HI=bit32;

 TIA_PERFCOUNTER0_LO=bit32;

 TIA_PERFCOUNTER1_HI=bit32;

 TIA_PERFCOUNTER1_LO=bit32;

 TIA_PERFCOUNTER2_HI=bit32;

 TIA_PERFCOUNTER2_LO=bit32;

 TIA_PERFCOUNTER3_HI=bit32;

 TIA_PERFCOUNTER3_LO=bit32;

 TIH_LEVEL_INTR_MASK=bitpacked record
  MASK     :bit1;
  RESERVED0:bit31;
 end;

 TIH_RB_WPTR_ADDR_HI=bitpacked record
  ADDR     :bit8;
  RESERVED0:bit24;
 end;

 TIH_RB_WPTR_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TLBV_DESKTOP_HEIGHT=bitpacked record
  DESKTOP_HEIGHT:bit15;
  RESERVED0     :bit17;
 end;

 TLBV_INTERRUPT_MASK=bitpacked record
  VBLANK_INTERRUPT_MASK:bit1;
  RESERVED0            :bit3;
  VLINE_INTERRUPT_MASK :bit1;
  RESERVED1            :bit3;
  VLINE2_INTERRUPT_MASK:bit1;
  RESERVED2            :bit23;
 end;

 TLBV_SYNC_RESET_SEL=bitpacked record
  LB_SYNC_RESET_SEL  :bit2;
  RESERVED0          :bit2;
  LB_SYNC_RESET_SEL2 :bit1;
  RESERVED1          :bit3;
  LB_SYNC_RESET_DELAY:bit8;
  RESERVED2          :bit6;
  LB_SYNC_DURATION   :bit2;
  RESERVED3          :bit8;
 end;

 TLB_BLACK_KEYER_G_Y=bitpacked record
  RESERVED0         :bit4;
  LB_BLACK_KEYER_G_Y:bit12;
  RESERVED1         :bit16;
 end;

 TLB_KEYER_COLOR_G_Y=bitpacked record
  RESERVED0         :bit4;
  LB_KEYER_COLOR_G_Y:bit12;
  RESERVED1         :bit16;
 end;

 TLB_TEST_DEBUG_DATA=bit32;

 TLB_VLINE_START_END=bitpacked record
  VLINE_START:bit14;
  RESERVED0  :bit2;
  VLINE_END  :bit15;
  VLINE_INV  :bit1;
 end;

 TLVTMA_PWRSEQ_STATE=bitpacked record
  LVTMA_PWRSEQ_TARGET_STATE_R:bit1;
  LVTMA_PWRSEQ_DIGON         :bit1;
  LVTMA_PWRSEQ_SYNCEN        :bit1;
  LVTMA_PWRSEQ_BLON          :bit1;
  LVTMA_PWRSEQ_DONE          :bit1;
  RESERVED0                  :bit3;
  LVTMA_PWRSEQ_STATE         :bit4;
  RESERVED1                  :bit20;
 end;

 TMASTER_CREDIT_CNTL=bitpacked record
  BIF_MC_RDRET_CREDIT:bit7;
  RESERVED0          :bit9;
  BIF_AZ_RDRET_CREDIT:bit6;
  RESERVED1          :bit10;
 end;

 TMASTER_UPDATE_LOCK=bitpacked record
  MASTER_UPDATE_LOCK            :bit1;
  RESERVED0                     :bit7;
  GSL_CONTROL_MASTER_UPDATE_LOCK:bit1;
  RESERVED1                     :bit23;
 end;

 TMASTER_UPDATE_MODE=bitpacked record
  MASTER_UPDATE_MODE           :bit3;
  RESERVED0                    :bit13;
  MASTER_UPDATE_INTERLACED_MODE:bit2;
  RESERVED1                    :bit14;
 end;

 TMC_ARB_BUSY_STATUS=bitpacked record
  LM_RD0   :bit1;
  LM_RD1   :bit1;
  LM_WR0   :bit1;
  LM_WR1   :bit1;
  HM_RD0   :bit1;
  HM_RD1   :bit1;
  HM_WR0   :bit1;
  HM_WR1   :bit1;
  WDE_RD0  :bit1;
  WDE_RD1  :bit1;
  WDE_WR0  :bit1;
  WDE_WR1  :bit1;
  POP0     :bit1;
  POP1     :bit1;
  TAGFIFO0 :bit1;
  TAGFIFO1 :bit1;
  REPLAY0  :bit1;
  REPLAY1  :bit1;
  RDRET0   :bit1;
  RDRET1   :bit1;
  GECC2_RD0:bit1;
  GECC2_RD1:bit1;
  GECC2_WR0:bit1;
  GECC2_WR1:bit1;
  WRRET0   :bit1;
  WRRET1   :bit1;
  RTT0     :bit1;
  RTT1     :bit1;
  REM_RD0  :bit1;
  REM_RD1  :bit1;
  REM_WR0  :bit1;
  REM_WR1  :bit1;
 end;

 TMC_ARB_DRAM_TIMING=bitpacked record
  ACTRD    :bit8;
  ACTWR    :bit8;
  RASMACTRD:bit8;
  RASMACTWR:bit8;
 end;

 TMC_ARB_GECC2_DEBUG=bitpacked record
  NUM_ERR_BITS:bit2;
  DIRECTION   :bit1;
  DATA_FIELD  :bit2;
  SW_INJECTION:bit1;
  RESERVED0   :bit26;
 end;

 TMC_ARB_HARSH_EN_RD=bitpacked record
  TX_PRI :bit8;
  BW_PRI :bit8;
  FIX_PRI:bit8;
  ST_PRI :bit8;
 end;

 TMC_ARB_HARSH_EN_WR=bitpacked record
  TX_PRI :bit8;
  BW_PRI :bit8;
  FIX_PRI:bit8;
  ST_PRI :bit8;
 end;

 TMC_ARB_MAX_LAT_CID=bitpacked record
  CID_CH0     :bit8;
  CID_CH1     :bit8;
  WRITE_CH0   :bit1;
  WRITE_CH1   :bit1;
  REALTIME_CH0:bit1;
  REALTIME_CH1:bit1;
  RESERVED0   :bit12;
 end;

 TMC_ARB_WTM_CNTL_RD=bitpacked record
  WTMODE            :bit2;
  HARSH_PRI         :bit1;
  ALLOW_STUTTER_GRP0:bit1;
  ALLOW_STUTTER_GRP1:bit1;
  ALLOW_STUTTER_GRP2:bit1;
  ALLOW_STUTTER_GRP3:bit1;
  ALLOW_STUTTER_GRP4:bit1;
  ALLOW_STUTTER_GRP5:bit1;
  ALLOW_STUTTER_GRP6:bit1;
  ALLOW_STUTTER_GRP7:bit1;
  ACP_HARSH_PRI     :bit1;
  ACP_OVER_DISP     :bit1;
  FORCE_ACP_URG     :bit1;
  RESERVED0         :bit18;
 end;

 TMC_ARB_WTM_CNTL_WR=bitpacked record
  WTMODE            :bit2;
  HARSH_PRI         :bit1;
  ALLOW_STUTTER_GRP0:bit1;
  ALLOW_STUTTER_GRP1:bit1;
  ALLOW_STUTTER_GRP2:bit1;
  ALLOW_STUTTER_GRP3:bit1;
  ALLOW_STUTTER_GRP4:bit1;
  ALLOW_STUTTER_GRP5:bit1;
  ALLOW_STUTTER_GRP6:bit1;
  ALLOW_STUTTER_GRP7:bit1;
  ACP_HARSH_PRI     :bit1;
  ACP_OVER_DISP     :bit1;
  FORCE_ACP_URG     :bit1;
  RESERVED0         :bit18;
 end;

 TMC_BIST_DATA_WORD0=bit32;

 TMC_BIST_DATA_WORD1=bit32;

 TMC_BIST_DATA_WORD2=bit32;

 TMC_BIST_DATA_WORD3=bit32;

 TMC_BIST_DATA_WORD4=bit32;

 TMC_BIST_DATA_WORD5=bit32;

 TMC_BIST_DATA_WORD6=bit32;

 TMC_BIST_DATA_WORD7=bit32;

 TMC_CITF_CREDITS_VM=bitpacked record
  READ_ALL :bit6;
  WRITE_ALL:bit6;
  RESERVED0:bit20;
 end;

 TMC_CITF_MISC_RD_CG=bitpacked record
  ONDLY        :bit6;
  OFFDLY       :bit6;
  RDYDLY       :bit6;
  ENABLE       :bit1;
  MEM_LS_ENABLE:bit1;
  RESERVED0    :bit12;
 end;

 TMC_CITF_MISC_VM_CG=bitpacked record
  ONDLY        :bit6;
  OFFDLY       :bit6;
  RDYDLY       :bit6;
  ENABLE       :bit1;
  MEM_LS_ENABLE:bit1;
  RESERVED0    :bit12;
 end;

 TMC_CITF_MISC_WR_CG=bitpacked record
  ONDLY        :bit6;
  OFFDLY       :bit6;
  RDYDLY       :bit6;
  ENABLE       :bit1;
  MEM_LS_ENABLE:bit1;
  RESERVED0    :bit12;
 end;

 TMC_GRUB_TX_CREDITS=bitpacked record
  SRCTAG_LIMIT     :bit6;
  RESERVED0        :bit2;
  SRCTAG_RT_RESERVE:bit4;
  NPC_RT_RESERVE   :bit4;
  NPD_RT_RESERVE   :bit4;
  TX_FIFO_DEPTH    :bit5;
  RESERVED1        :bit7;
 end;

 TMC_HUB_MISC_HUB_CG=bitpacked record
  ONDLY        :bit6;
  OFFDLY       :bit6;
  RDYDLY       :bit6;
  ENABLE       :bit1;
  MEM_LS_ENABLE:bit1;
  RESERVED0    :bit12;
 end;

 TMC_HUB_MISC_SIP_CG=bitpacked record
  ONDLY        :bit6;
  OFFDLY       :bit6;
  RDYDLY       :bit6;
  ENABLE       :bit1;
  MEM_LS_ENABLE:bit1;
  RESERVED0    :bit12;
 end;

 TMC_HUB_MISC_STATUS=bitpacked record
  OUTSTANDING_READ          :bit1;
  OUTSTANDING_WRITE         :bit1;
  OUTSTANDING_ATOMIC        :bit1;
  OUTSTANDING_HUB_RDREQ     :bit1;
  OUTSTANDING_HUB_RDRET     :bit1;
  OUTSTANDING_HUB_WRREQ     :bit1;
  OUTSTANDING_HUB_WRRET     :bit1;
  OUTSTANDING_HUB_ATOMIC_REQ:bit1;
  OUTSTANDING_HUB_ATOMIC_RET:bit1;
  OUTSTANDING_RPB_READ      :bit1;
  OUTSTANDING_RPB_WRITE     :bit1;
  OUTSTANDING_RPB_ATOMIC    :bit1;
  OUTSTANDING_MCD_READ      :bit1;
  OUTSTANDING_MCD_WRITE     :bit1;
  OUTSTANDING_MCD_ATOMIC    :bit1;
  RPB_BUSY                  :bit1;
  WRITE_DEADLOCK_WARNING    :bit1;
  READ_DEADLOCK_WARNING     :bit1;
  ATOMIC_DEADLOCK_WARNING   :bit1;
  GFX_BUSY                  :bit1;
  RESERVED0                 :bit12;
 end;

 TMC_HUB_RDREQ_SDMA0=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_SDMA1=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_VCEU0=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_VCEU1=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_XDMAM=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_WDP_CREDITS=bitpacked record
  VM0  :bit8;
  VM1  :bit8;
  STOR0:bit8;
  STOR1:bit8;
 end;

 TMC_HUB_WDP_ISP_MPM=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_HUB_WDP_ISP_MPS=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_HUB_WDP_ISP_SPM=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_IO_DEBUG_UP_100=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_101=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_102=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_103=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_104=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_105=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_106=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_107=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_108=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_109=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_110=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_111=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_112=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_113=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_114=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_115=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_116=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_117=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_118=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_119=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_120=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_121=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_122=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_123=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_124=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_125=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_126=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_127=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_128=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_129=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_130=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_131=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_132=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_133=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_134=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_135=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_136=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_137=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_138=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_139=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_140=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_141=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_142=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_143=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_144=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_145=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_146=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_147=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_148=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_149=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_150=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_151=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_152=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_153=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_154=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_155=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_156=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_157=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_158=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_IO_DEBUG_UP_159=bitpacked record
  VALUE0:bit8;
  VALUE1:bit8;
  VALUE2:bit8;
  VALUE3:bit8;
 end;

 TMC_SEQ_MISC_TIMING=bitpacked record
  TRP_WRA  :bit6;
  TRP_RDA  :bit6;
  TRP      :bit5;
  TRFC     :bit7;
  RESERVED0:bit4;
  RESERVED1:bit4;
 end;

 TMC_SEQ_RESERVE_0_S=bit32;

 TMC_SEQ_RESERVE_1_S=bit32;

 TMC_SEQ_SREG_STATUS=bitpacked record
  AVAIL_RTN:bit4;
  RESERVED0:bit4;
  PND_RD   :bit4;
  PND_WR   :bit4;
  RESERVED1:bit16;
 end;

 TMC_SEQ_SUP_IR_STAT=bit32;

 TMC_SHARED_CHREMAP2=bitpacked record
  CHAN8 :bit4;
  CHAN9 :bit4;
  CHAN10:bit4;
  CHAN11:bit4;
  CHAN12:bit4;
  CHAN13:bit4;
  CHAN14:bit4;
  CHAN15:bit4;
 end;

 TMC_VM_NB_MMIOLIMIT=bit32;

 TMC_XBAR_CHTRIREMAP=bitpacked record
  CH0      :bit2;
  CH1      :bit2;
  CH2      :bit2;
  RESERVED0:bit26;
 end;

 TMC_XPB_P2P_BAR_CFG=bitpacked record
  ADDR_SIZE         :bit4;
  SEND_BAR          :bit2;
  SNOOP             :bit1;
  SEND_DIS          :bit1;
  COMPRESS_DIS      :bit1;
  UPDATE_DIS        :bit1;
  REGBAR_FROM_SYSBAR:bit1;
  RD_EN             :bit1;
  ATC_TRANSLATED    :bit1;
  RESERVED0         :bit19;
 end;

 TMPLL_BYPASSCLK_SEL=bitpacked record
  RESERVED0      :bit8;
  MPLL_CLKOUT_SEL:bit8;
  RESERVED1      :bit16;
 end;

 TMVP_CRC_RESULT_RED=bitpacked record
  MVP_CRC_RED_RESULT:bit16;
  RESERVED0         :bit16;
 end;

 TOUTPUT_CSC_C11_C12=bitpacked record
  OUTPUT_CSC_C11:bit16;
  OUTPUT_CSC_C12:bit16;
 end;

 TOUTPUT_CSC_C13_C14=bitpacked record
  OUTPUT_CSC_C13:bit16;
  OUTPUT_CSC_C14:bit16;
 end;

 TOUTPUT_CSC_C21_C22=bitpacked record
  OUTPUT_CSC_C21:bit16;
  OUTPUT_CSC_C22:bit16;
 end;

 TOUTPUT_CSC_C23_C24=bitpacked record
  OUTPUT_CSC_C23:bit16;
  OUTPUT_CSC_C24:bit16;
 end;

 TOUTPUT_CSC_C31_C32=bitpacked record
  OUTPUT_CSC_C31:bit16;
  OUTPUT_CSC_C32:bit16;
 end;

 TOUTPUT_CSC_C33_C34=bitpacked record
  OUTPUT_CSC_C33:bit16;
  OUTPUT_CSC_C34:bit16;
 end;

 TOUTPUT_CSC_CONTROL=bitpacked record
  OUTPUT_CSC_GRPH_MODE:bit3;
  RESERVED0           :bit1;
  OUTPUT_CSC_OVL_MODE :bit3;
  RESERVED1           :bit25;
 end;

 TPA_CL_VPORT_XSCALE=bit32;

 TPA_CL_VPORT_YSCALE=bit32;

 TPA_CL_VPORT_ZSCALE=bit32;

 TPA_SC_IF_FIFO_SIZE=bitpacked record
  SC_DB_TILE_IF_FIFO_SIZE:bit6;
  SC_DB_QUAD_IF_FIFO_SIZE:bit6;
  SC_SPI_IF_FIFO_SIZE    :bit6;
  SC_BCI_IF_FIFO_SIZE    :bit6;
  RESERVED0              :bit8;
 end;

 TPA_SC_LINE_STIPPLE=bitpacked record
  LINE_PATTERN     :bit16;
  REPEAT_COUNT     :bit8;
  RESERVED0        :bit4;
  PATTERN_BIT_ORDER:bit1;
  AUTO_RESET_CNTL  :bit2;
  RESERVED1        :bit1;
 end;

 TPA_SC_VPORT_ZMAX_0=bit32;

 TPA_SC_VPORT_ZMAX_1=bit32;

 TPA_SC_VPORT_ZMAX_2=bit32;

 TPA_SC_VPORT_ZMAX_3=bit32;

 TPA_SC_VPORT_ZMAX_4=bit32;

 TPA_SC_VPORT_ZMAX_5=bit32;

 TPA_SC_VPORT_ZMAX_6=bit32;

 TPA_SC_VPORT_ZMAX_7=bit32;

 TPA_SC_VPORT_ZMAX_8=bit32;

 TPA_SC_VPORT_ZMAX_9=bit32;

 TPA_SC_VPORT_ZMIN_0=bit32;

 TPA_SC_VPORT_ZMIN_1=bit32;

 TPA_SC_VPORT_ZMIN_2=bit32;

 TPA_SC_VPORT_ZMIN_3=bit32;

 TPA_SC_VPORT_ZMIN_4=bit32;

 TPA_SC_VPORT_ZMIN_5=bit32;

 TPA_SC_VPORT_ZMIN_6=bit32;

 TPA_SC_VPORT_ZMIN_7=bit32;

 TPA_SC_VPORT_ZMIN_8=bit32;

 TPA_SC_VPORT_ZMIN_9=bit32;

 TPA_SU_POINT_MINMAX=bitpacked record
  MIN_SIZE:bit16;
  MAX_SIZE:bit16;
 end;

 TPA_SU_SC_MODE_CNTL=bitpacked record
  CULL_FRONT              :bit1;
  CULL_BACK               :bit1;
  FACE                    :bit1;
  POLY_MODE               :bit2;
  POLYMODE_FRONT_PTYPE    :bit3;
  POLYMODE_BACK_PTYPE     :bit3;
  POLY_OFFSET_FRONT_ENABLE:bit1;
  POLY_OFFSET_BACK_ENABLE :bit1;
  POLY_OFFSET_PARA_ENABLE :bit1;
  RESERVED0               :bit2;
  VTX_WINDOW_OFFSET_ENABLE:bit1;
  RESERVED1               :bit2;
  PROVOKING_VTX_LAST      :bit1;
  PERSP_CORR_DIS          :bit1;
  MULTI_PRIM_IB_ENA       :bit1;
  RESERVED2               :bit10;
 end;

 TPB0_PIF_LANE0_OVRD=bitpacked record
  GANGMODE_OVRD_EN_0     :bit1;
  FREQDIV_OVRD_EN_0      :bit1;
  LINKSPEED_OVRD_EN_0    :bit1;
  TWOSYMENABLE_OVRD_EN_0 :bit1;
  TXPWR_OVRD_EN_0        :bit1;
  TXPGENABLE_OVRD_EN_0   :bit1;
  RXPWR_OVRD_EN_0        :bit1;
  RXPGENABLE_OVRD_EN_0   :bit1;
  ELECIDLEDETEN_OVRD_EN_0:bit1;
  ENABLEFOM_OVRD_EN_0    :bit1;
  REQUESTFOM_OVRD_EN_0   :bit1;
  RESPONSEMODE_OVRD_EN_0 :bit1;
  REQUESTTRK_OVRD_EN_0   :bit1;
  REQUESTTRN_OVRD_EN_0   :bit1;
  COEFFICIENTID_OVRD_EN_0:bit1;
  COEFFICIENT_OVRD_EN_0  :bit1;
  CDREN_OVRD_EN_0        :bit1;
  CDREN_OVRD_VAL_0       :bit1;
  RESERVED0              :bit14;
 end;

 TPB0_PIF_LANE1_OVRD=bitpacked record
  GANGMODE_OVRD_EN_1     :bit1;
  FREQDIV_OVRD_EN_1      :bit1;
  LINKSPEED_OVRD_EN_1    :bit1;
  TWOSYMENABLE_OVRD_EN_1 :bit1;
  TXPWR_OVRD_EN_1        :bit1;
  TXPGENABLE_OVRD_EN_1   :bit1;
  RXPWR_OVRD_EN_1        :bit1;
  RXPGENABLE_OVRD_EN_1   :bit1;
  ELECIDLEDETEN_OVRD_EN_1:bit1;
  ENABLEFOM_OVRD_EN_1    :bit1;
  REQUESTFOM_OVRD_EN_1   :bit1;
  RESPONSEMODE_OVRD_EN_1 :bit1;
  REQUESTTRK_OVRD_EN_1   :bit1;
  REQUESTTRN_OVRD_EN_1   :bit1;
  COEFFICIENTID_OVRD_EN_1:bit1;
  COEFFICIENT_OVRD_EN_1  :bit1;
  CDREN_OVRD_EN_1        :bit1;
  CDREN_OVRD_VAL_1       :bit1;
  RESERVED0              :bit14;
 end;

 TPB0_PIF_LANE2_OVRD=bitpacked record
  GANGMODE_OVRD_EN_2     :bit1;
  FREQDIV_OVRD_EN_2      :bit1;
  LINKSPEED_OVRD_EN_2    :bit1;
  TWOSYMENABLE_OVRD_EN_2 :bit1;
  TXPWR_OVRD_EN_2        :bit1;
  TXPGENABLE_OVRD_EN_2   :bit1;
  RXPWR_OVRD_EN_2        :bit1;
  RXPGENABLE_OVRD_EN_2   :bit1;
  ELECIDLEDETEN_OVRD_EN_2:bit1;
  ENABLEFOM_OVRD_EN_2    :bit1;
  REQUESTFOM_OVRD_EN_2   :bit1;
  RESPONSEMODE_OVRD_EN_2 :bit1;
  REQUESTTRK_OVRD_EN_2   :bit1;
  REQUESTTRN_OVRD_EN_2   :bit1;
  COEFFICIENTID_OVRD_EN_2:bit1;
  COEFFICIENT_OVRD_EN_2  :bit1;
  CDREN_OVRD_EN_2        :bit1;
  CDREN_OVRD_VAL_2       :bit1;
  RESERVED0              :bit14;
 end;

 TPB0_PIF_LANE3_OVRD=bitpacked record
  GANGMODE_OVRD_EN_3     :bit1;
  FREQDIV_OVRD_EN_3      :bit1;
  LINKSPEED_OVRD_EN_3    :bit1;
  TWOSYMENABLE_OVRD_EN_3 :bit1;
  TXPWR_OVRD_EN_3        :bit1;
  TXPGENABLE_OVRD_EN_3   :bit1;
  RXPWR_OVRD_EN_3        :bit1;
  RXPGENABLE_OVRD_EN_3   :bit1;
  ELECIDLEDETEN_OVRD_EN_3:bit1;
  ENABLEFOM_OVRD_EN_3    :bit1;
  REQUESTFOM_OVRD_EN_3   :bit1;
  RESPONSEMODE_OVRD_EN_3 :bit1;
  REQUESTTRK_OVRD_EN_3   :bit1;
  REQUESTTRN_OVRD_EN_3   :bit1;
  COEFFICIENTID_OVRD_EN_3:bit1;
  COEFFICIENT_OVRD_EN_3  :bit1;
  CDREN_OVRD_EN_3        :bit1;
  CDREN_OVRD_VAL_3       :bit1;
  RESERVED0              :bit14;
 end;

 TPB0_PIF_LANE4_OVRD=bitpacked record
  GANGMODE_OVRD_EN_4     :bit1;
  FREQDIV_OVRD_EN_4      :bit1;
  LINKSPEED_OVRD_EN_4    :bit1;
  TWOSYMENABLE_OVRD_EN_4 :bit1;
  TXPWR_OVRD_EN_4        :bit1;
  TXPGENABLE_OVRD_EN_4   :bit1;
  RXPWR_OVRD_EN_4        :bit1;
  RXPGENABLE_OVRD_EN_4   :bit1;
  ELECIDLEDETEN_OVRD_EN_4:bit1;
  ENABLEFOM_OVRD_EN_4    :bit1;
  REQUESTFOM_OVRD_EN_4   :bit1;
  RESPONSEMODE_OVRD_EN_4 :bit1;
  REQUESTTRK_OVRD_EN_4   :bit1;
  REQUESTTRN_OVRD_EN_4   :bit1;
  COEFFICIENTID_OVRD_EN_4:bit1;
  COEFFICIENT_OVRD_EN_4  :bit1;
  CDREN_OVRD_EN_4        :bit1;
  CDREN_OVRD_VAL_4       :bit1;
  RESERVED0              :bit14;
 end;

 TPB0_PIF_LANE5_OVRD=bitpacked record
  GANGMODE_OVRD_EN_5     :bit1;
  FREQDIV_OVRD_EN_5      :bit1;
  LINKSPEED_OVRD_EN_5    :bit1;
  TWOSYMENABLE_OVRD_EN_5 :bit1;
  TXPWR_OVRD_EN_5        :bit1;
  TXPGENABLE_OVRD_EN_5   :bit1;
  RXPWR_OVRD_EN_5        :bit1;
  RXPGENABLE_OVRD_EN_5   :bit1;
  ELECIDLEDETEN_OVRD_EN_5:bit1;
  ENABLEFOM_OVRD_EN_5    :bit1;
  REQUESTFOM_OVRD_EN_5   :bit1;
  RESPONSEMODE_OVRD_EN_5 :bit1;
  REQUESTTRK_OVRD_EN_5   :bit1;
  REQUESTTRN_OVRD_EN_5   :bit1;
  COEFFICIENTID_OVRD_EN_5:bit1;
  COEFFICIENT_OVRD_EN_5  :bit1;
  CDREN_OVRD_EN_5        :bit1;
  CDREN_OVRD_VAL_5       :bit1;
  RESERVED0              :bit14;
 end;

 TPB0_PIF_LANE6_OVRD=bitpacked record
  GANGMODE_OVRD_EN_6     :bit1;
  FREQDIV_OVRD_EN_6      :bit1;
  LINKSPEED_OVRD_EN_6    :bit1;
  TWOSYMENABLE_OVRD_EN_6 :bit1;
  TXPWR_OVRD_EN_6        :bit1;
  TXPGENABLE_OVRD_EN_6   :bit1;
  RXPWR_OVRD_EN_6        :bit1;
  RXPGENABLE_OVRD_EN_6   :bit1;
  ELECIDLEDETEN_OVRD_EN_6:bit1;
  ENABLEFOM_OVRD_EN_6    :bit1;
  REQUESTFOM_OVRD_EN_6   :bit1;
  RESPONSEMODE_OVRD_EN_6 :bit1;
  REQUESTTRK_OVRD_EN_6   :bit1;
  REQUESTTRN_OVRD_EN_6   :bit1;
  COEFFICIENTID_OVRD_EN_6:bit1;
  COEFFICIENT_OVRD_EN_6  :bit1;
  CDREN_OVRD_EN_6        :bit1;
  CDREN_OVRD_VAL_6       :bit1;
  RESERVED0              :bit14;
 end;

 TPB0_PIF_LANE7_OVRD=bitpacked record
  GANGMODE_OVRD_EN_7     :bit1;
  FREQDIV_OVRD_EN_7      :bit1;
  LINKSPEED_OVRD_EN_7    :bit1;
  TWOSYMENABLE_OVRD_EN_7 :bit1;
  TXPWR_OVRD_EN_7        :bit1;
  TXPGENABLE_OVRD_EN_7   :bit1;
  RXPWR_OVRD_EN_7        :bit1;
  RXPGENABLE_OVRD_EN_7   :bit1;
  ELECIDLEDETEN_OVRD_EN_7:bit1;
  ENABLEFOM_OVRD_EN_7    :bit1;
  REQUESTFOM_OVRD_EN_7   :bit1;
  RESPONSEMODE_OVRD_EN_7 :bit1;
  REQUESTTRK_OVRD_EN_7   :bit1;
  REQUESTTRN_OVRD_EN_7   :bit1;
  COEFFICIENTID_OVRD_EN_7:bit1;
  COEFFICIENT_OVRD_EN_7  :bit1;
  CDREN_OVRD_EN_7        :bit1;
  CDREN_OVRD_VAL_7       :bit1;
  RESERVED0              :bit14;
 end;

 TPB0_STRAP_GLB_REG0=bitpacked record
  RESERVED0                       :bit1;
  STRAP_QUICK_SIM_START           :bit1;
  STRAP_DFT_RXBSCAN_EN_VAL        :bit1;
  STRAP_DFT_CALIB_BYPASS          :bit1;
  STRAP_FORCE_LC_PLL_ON           :bit1;
  STRAP_CFG_IDLEDET_TH            :bit2;
  STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL :bit5;
  STRAP_RX_CFG_OVR_PWRSF          :bit1;
  STRAP_RX_TRK_MODE_0_            :bit1;
  STRAP_PWRGOOD_OVRD              :bit1;
  STRAP_DBG_RXDLL_VREG_REF_SEL    :bit1;
  STRAP_PLL_CFG_LC_VCO_TUNE       :bit4;
  STRAP_DBG_RXRDATA_GATING_DISABLE:bit1;
  STRAP_DBG_RXPI_OFFSET_BYP_VAL   :bit4;
  RESERVED1                       :bit7;
 end;

 TPB0_STRAP_GLB_REG1=bitpacked record
  RESERVED0                   :bit1;
  STRAP_RX_ADAPT_RST_MODE     :bit2;
  STRAP_RX_L0_ENTRY_MODE      :bit2;
  STRAP_RX_EI_FILTER          :bit2;
  STRAP_RX_ADAPT_RST_SUB_ENTRY:bit1;
  STRAP_RX_PS0_RDY_GEN_MODE   :bit2;
  STRAP_RX_DLL_RESET_IN_SPDCHG:bit1;
  STRAP_RX_ADAPT_TIME_OUT     :bit2;
  RESERVED1                   :bit1;
  RESERVED2                   :bit18;
 end;

 TPB0_STRAP_GLB_REG2=bitpacked record
  RESERVED0                   :bit2;
  STRAP_BPHYC_PLL_RAMP_UP_TIME:bit3;
  STRAP_IMPCAL_SETTLE_TIME    :bit2;
  STRAP_BG_SETTLE_TIME        :bit2;
  STRAP_TX_CMDET_TIME         :bit2;
  STRAP_TX_STARTUP_TIME       :bit2;
  RESERVED1                   :bit15;
  STRAP_B_PCB_DIS0            :bit1;
  STRAP_B_PCB_DIS1            :bit1;
  STRAP_B_PCB_DRV_STR         :bit2;
 end;

 TPB0_STRAP_PIN_REG0=bitpacked record
  RESERVED0          :bit1;
  STRAP_TX_DEEMPH_EN :bit1;
  STRAP_TX_FULL_SWING:bit1;
  RESERVED1          :bit29;
 end;

 TPB0_STRAP_PLL_REG0=bitpacked record
  RESERVED0                           :bit1;
  STRAP_PLL_CFG_LC_BW_CNTRL           :bit3;
  STRAP_PLL_CFG_LC_LF_CNTRL           :bit9;
  STRAP_TX_RXDET_X1_SSF               :bit1;
  RESERVED1                           :bit1;
  STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS:bit1;
  STRAP_PLL_CFG_RO_BW_CNTRL           :bit8;
  STRAP_PLL_STRAP_SEL                 :bit1;
  RESERVED2                           :bit7;
 end;

 TPB1_PIF_LANE0_OVRD=bitpacked record
  GANGMODE_OVRD_EN_0     :bit1;
  FREQDIV_OVRD_EN_0      :bit1;
  LINKSPEED_OVRD_EN_0    :bit1;
  TWOSYMENABLE_OVRD_EN_0 :bit1;
  TXPWR_OVRD_EN_0        :bit1;
  TXPGENABLE_OVRD_EN_0   :bit1;
  RXPWR_OVRD_EN_0        :bit1;
  RXPGENABLE_OVRD_EN_0   :bit1;
  ELECIDLEDETEN_OVRD_EN_0:bit1;
  ENABLEFOM_OVRD_EN_0    :bit1;
  REQUESTFOM_OVRD_EN_0   :bit1;
  RESPONSEMODE_OVRD_EN_0 :bit1;
  REQUESTTRK_OVRD_EN_0   :bit1;
  REQUESTTRN_OVRD_EN_0   :bit1;
  COEFFICIENTID_OVRD_EN_0:bit1;
  COEFFICIENT_OVRD_EN_0  :bit1;
  CDREN_OVRD_EN_0        :bit1;
  CDREN_OVRD_VAL_0       :bit1;
  RESERVED0              :bit14;
 end;

 TPB1_PIF_LANE1_OVRD=bitpacked record
  GANGMODE_OVRD_EN_1     :bit1;
  FREQDIV_OVRD_EN_1      :bit1;
  LINKSPEED_OVRD_EN_1    :bit1;
  TWOSYMENABLE_OVRD_EN_1 :bit1;
  TXPWR_OVRD_EN_1        :bit1;
  TXPGENABLE_OVRD_EN_1   :bit1;
  RXPWR_OVRD_EN_1        :bit1;
  RXPGENABLE_OVRD_EN_1   :bit1;
  ELECIDLEDETEN_OVRD_EN_1:bit1;
  ENABLEFOM_OVRD_EN_1    :bit1;
  REQUESTFOM_OVRD_EN_1   :bit1;
  RESPONSEMODE_OVRD_EN_1 :bit1;
  REQUESTTRK_OVRD_EN_1   :bit1;
  REQUESTTRN_OVRD_EN_1   :bit1;
  COEFFICIENTID_OVRD_EN_1:bit1;
  COEFFICIENT_OVRD_EN_1  :bit1;
  CDREN_OVRD_EN_1        :bit1;
  CDREN_OVRD_VAL_1       :bit1;
  RESERVED0              :bit14;
 end;

 TPB1_PIF_LANE2_OVRD=bitpacked record
  GANGMODE_OVRD_EN_2     :bit1;
  FREQDIV_OVRD_EN_2      :bit1;
  LINKSPEED_OVRD_EN_2    :bit1;
  TWOSYMENABLE_OVRD_EN_2 :bit1;
  TXPWR_OVRD_EN_2        :bit1;
  TXPGENABLE_OVRD_EN_2   :bit1;
  RXPWR_OVRD_EN_2        :bit1;
  RXPGENABLE_OVRD_EN_2   :bit1;
  ELECIDLEDETEN_OVRD_EN_2:bit1;
  ENABLEFOM_OVRD_EN_2    :bit1;
  REQUESTFOM_OVRD_EN_2   :bit1;
  RESPONSEMODE_OVRD_EN_2 :bit1;
  REQUESTTRK_OVRD_EN_2   :bit1;
  REQUESTTRN_OVRD_EN_2   :bit1;
  COEFFICIENTID_OVRD_EN_2:bit1;
  COEFFICIENT_OVRD_EN_2  :bit1;
  CDREN_OVRD_EN_2        :bit1;
  CDREN_OVRD_VAL_2       :bit1;
  RESERVED0              :bit14;
 end;

 TPB1_PIF_LANE3_OVRD=bitpacked record
  GANGMODE_OVRD_EN_3     :bit1;
  FREQDIV_OVRD_EN_3      :bit1;
  LINKSPEED_OVRD_EN_3    :bit1;
  TWOSYMENABLE_OVRD_EN_3 :bit1;
  TXPWR_OVRD_EN_3        :bit1;
  TXPGENABLE_OVRD_EN_3   :bit1;
  RXPWR_OVRD_EN_3        :bit1;
  RXPGENABLE_OVRD_EN_3   :bit1;
  ELECIDLEDETEN_OVRD_EN_3:bit1;
  ENABLEFOM_OVRD_EN_3    :bit1;
  REQUESTFOM_OVRD_EN_3   :bit1;
  RESPONSEMODE_OVRD_EN_3 :bit1;
  REQUESTTRK_OVRD_EN_3   :bit1;
  REQUESTTRN_OVRD_EN_3   :bit1;
  COEFFICIENTID_OVRD_EN_3:bit1;
  COEFFICIENT_OVRD_EN_3  :bit1;
  CDREN_OVRD_EN_3        :bit1;
  CDREN_OVRD_VAL_3       :bit1;
  RESERVED0              :bit14;
 end;

 TPB1_PIF_LANE4_OVRD=bitpacked record
  GANGMODE_OVRD_EN_4     :bit1;
  FREQDIV_OVRD_EN_4      :bit1;
  LINKSPEED_OVRD_EN_4    :bit1;
  TWOSYMENABLE_OVRD_EN_4 :bit1;
  TXPWR_OVRD_EN_4        :bit1;
  TXPGENABLE_OVRD_EN_4   :bit1;
  RXPWR_OVRD_EN_4        :bit1;
  RXPGENABLE_OVRD_EN_4   :bit1;
  ELECIDLEDETEN_OVRD_EN_4:bit1;
  ENABLEFOM_OVRD_EN_4    :bit1;
  REQUESTFOM_OVRD_EN_4   :bit1;
  RESPONSEMODE_OVRD_EN_4 :bit1;
  REQUESTTRK_OVRD_EN_4   :bit1;
  REQUESTTRN_OVRD_EN_4   :bit1;
  COEFFICIENTID_OVRD_EN_4:bit1;
  COEFFICIENT_OVRD_EN_4  :bit1;
  CDREN_OVRD_EN_4        :bit1;
  CDREN_OVRD_VAL_4       :bit1;
  RESERVED0              :bit14;
 end;

 TPB1_PIF_LANE5_OVRD=bitpacked record
  GANGMODE_OVRD_EN_5     :bit1;
  FREQDIV_OVRD_EN_5      :bit1;
  LINKSPEED_OVRD_EN_5    :bit1;
  TWOSYMENABLE_OVRD_EN_5 :bit1;
  TXPWR_OVRD_EN_5        :bit1;
  TXPGENABLE_OVRD_EN_5   :bit1;
  RXPWR_OVRD_EN_5        :bit1;
  RXPGENABLE_OVRD_EN_5   :bit1;
  ELECIDLEDETEN_OVRD_EN_5:bit1;
  ENABLEFOM_OVRD_EN_5    :bit1;
  REQUESTFOM_OVRD_EN_5   :bit1;
  RESPONSEMODE_OVRD_EN_5 :bit1;
  REQUESTTRK_OVRD_EN_5   :bit1;
  REQUESTTRN_OVRD_EN_5   :bit1;
  COEFFICIENTID_OVRD_EN_5:bit1;
  COEFFICIENT_OVRD_EN_5  :bit1;
  CDREN_OVRD_EN_5        :bit1;
  CDREN_OVRD_VAL_5       :bit1;
  RESERVED0              :bit14;
 end;

 TPB1_PIF_LANE6_OVRD=bitpacked record
  GANGMODE_OVRD_EN_6     :bit1;
  FREQDIV_OVRD_EN_6      :bit1;
  LINKSPEED_OVRD_EN_6    :bit1;
  TWOSYMENABLE_OVRD_EN_6 :bit1;
  TXPWR_OVRD_EN_6        :bit1;
  TXPGENABLE_OVRD_EN_6   :bit1;
  RXPWR_OVRD_EN_6        :bit1;
  RXPGENABLE_OVRD_EN_6   :bit1;
  ELECIDLEDETEN_OVRD_EN_6:bit1;
  ENABLEFOM_OVRD_EN_6    :bit1;
  REQUESTFOM_OVRD_EN_6   :bit1;
  RESPONSEMODE_OVRD_EN_6 :bit1;
  REQUESTTRK_OVRD_EN_6   :bit1;
  REQUESTTRN_OVRD_EN_6   :bit1;
  COEFFICIENTID_OVRD_EN_6:bit1;
  COEFFICIENT_OVRD_EN_6  :bit1;
  CDREN_OVRD_EN_6        :bit1;
  CDREN_OVRD_VAL_6       :bit1;
  RESERVED0              :bit14;
 end;

 TPB1_PIF_LANE7_OVRD=bitpacked record
  GANGMODE_OVRD_EN_7     :bit1;
  FREQDIV_OVRD_EN_7      :bit1;
  LINKSPEED_OVRD_EN_7    :bit1;
  TWOSYMENABLE_OVRD_EN_7 :bit1;
  TXPWR_OVRD_EN_7        :bit1;
  TXPGENABLE_OVRD_EN_7   :bit1;
  RXPWR_OVRD_EN_7        :bit1;
  RXPGENABLE_OVRD_EN_7   :bit1;
  ELECIDLEDETEN_OVRD_EN_7:bit1;
  ENABLEFOM_OVRD_EN_7    :bit1;
  REQUESTFOM_OVRD_EN_7   :bit1;
  RESPONSEMODE_OVRD_EN_7 :bit1;
  REQUESTTRK_OVRD_EN_7   :bit1;
  REQUESTTRN_OVRD_EN_7   :bit1;
  COEFFICIENTID_OVRD_EN_7:bit1;
  COEFFICIENT_OVRD_EN_7  :bit1;
  CDREN_OVRD_EN_7        :bit1;
  CDREN_OVRD_VAL_7       :bit1;
  RESERVED0              :bit14;
 end;

 TPB1_STRAP_GLB_REG0=bitpacked record
  RESERVED0                       :bit1;
  STRAP_QUICK_SIM_START           :bit1;
  STRAP_DFT_RXBSCAN_EN_VAL        :bit1;
  STRAP_DFT_CALIB_BYPASS          :bit1;
  STRAP_FORCE_LC_PLL_ON           :bit1;
  STRAP_CFG_IDLEDET_TH            :bit2;
  STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL :bit5;
  STRAP_RX_CFG_OVR_PWRSF          :bit1;
  STRAP_RX_TRK_MODE_0_            :bit1;
  STRAP_PWRGOOD_OVRD              :bit1;
  STRAP_DBG_RXDLL_VREG_REF_SEL    :bit1;
  STRAP_PLL_CFG_LC_VCO_TUNE       :bit4;
  STRAP_DBG_RXRDATA_GATING_DISABLE:bit1;
  STRAP_DBG_RXPI_OFFSET_BYP_VAL   :bit4;
  RESERVED1                       :bit7;
 end;

 TPB1_STRAP_GLB_REG1=bitpacked record
  RESERVED0                   :bit1;
  STRAP_RX_ADAPT_RST_MODE     :bit2;
  STRAP_RX_L0_ENTRY_MODE      :bit2;
  STRAP_RX_EI_FILTER          :bit2;
  STRAP_RX_ADAPT_RST_SUB_ENTRY:bit1;
  STRAP_RX_PS0_RDY_GEN_MODE   :bit2;
  STRAP_RX_DLL_RESET_IN_SPDCHG:bit1;
  STRAP_RX_ADAPT_TIME_OUT     :bit2;
  RESERVED1                   :bit1;
  RESERVED2                   :bit18;
 end;

 TPB1_STRAP_GLB_REG2=bitpacked record
  RESERVED0                   :bit2;
  STRAP_BPHYC_PLL_RAMP_UP_TIME:bit3;
  STRAP_IMPCAL_SETTLE_TIME    :bit2;
  STRAP_BG_SETTLE_TIME        :bit2;
  STRAP_TX_CMDET_TIME         :bit2;
  STRAP_TX_STARTUP_TIME       :bit2;
  RESERVED1                   :bit15;
  STRAP_B_PCB_DIS0            :bit1;
  STRAP_B_PCB_DIS1            :bit1;
  STRAP_B_PCB_DRV_STR         :bit2;
 end;

 TPB1_STRAP_PIN_REG0=bitpacked record
  RESERVED0          :bit1;
  STRAP_TX_DEEMPH_EN :bit1;
  STRAP_TX_FULL_SWING:bit1;
  RESERVED1          :bit29;
 end;

 TPB1_STRAP_PLL_REG0=bitpacked record
  RESERVED0                           :bit1;
  STRAP_PLL_CFG_LC_BW_CNTRL           :bit3;
  STRAP_PLL_CFG_LC_LF_CNTRL           :bit9;
  STRAP_TX_RXDET_X1_SSF               :bit1;
  RESERVED1                           :bit1;
  STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS:bit1;
  STRAP_PLL_CFG_RO_BW_CNTRL           :bit8;
  STRAP_PLL_STRAP_SEL                 :bit1;
  RESERVED2                           :bit7;
 end;

 TPCIEP_BCH_ECC_CNTL=bitpacked record
  STRAP_BCH_ECC_EN       :bit1;
  RESERVED0              :bit7;
  BCH_ECC_ERROR_THRESHOLD:bit8;
  BCH_ECC_ERROR_STATUS   :bit16;
 end;

 TPCIE_CORR_ERR_MASK=bitpacked record
  RCV_ERR_MASK              :bit1;
  RESERVED0                 :bit5;
  BAD_TLP_MASK              :bit1;
  BAD_DLLP_MASK             :bit1;
  REPLAY_NUM_ROLLOVER_MASK  :bit1;
  RESERVED1                 :bit3;
  REPLAY_TIMER_TIMEOUT_MASK :bit1;
  ADVISORY_NONFATAL_ERR_MASK:bit1;
  CORR_INT_ERR_MASK         :bit1;
  HDR_LOG_OVFL_MASK         :bit1;
  RESERVED2                 :bit16;
 end;

 TPCIE_LC_N_FTS_CNTL=bitpacked record
  LC_XMIT_N_FTS              :bit8;
  LC_XMIT_N_FTS_OVERRIDE_EN  :bit1;
  LC_XMIT_FTS_BEFORE_RECOVERY:bit1;
  RESERVED0                  :bit6;
  LC_XMIT_N_FTS_LIMIT        :bit8;
  LC_N_FTS                   :bit8;
 end;

 TPCIE_LC_SPEED_CNTL=bitpacked record
  LC_GEN2_EN_STRAP                    :bit1;
  LC_GEN3_EN_STRAP                    :bit1;
  LC_TARGET_LINK_SPEED_OVERRIDE_EN    :bit1;
  LC_TARGET_LINK_SPEED_OVERRIDE       :bit2;
  LC_FORCE_EN_SW_SPEED_CHANGE         :bit1;
  LC_FORCE_DIS_SW_SPEED_CHANGE        :bit1;
  LC_FORCE_EN_HW_SPEED_CHANGE         :bit1;
  LC_FORCE_DIS_HW_SPEED_CHANGE        :bit1;
  LC_INITIATE_LINK_SPEED_CHANGE       :bit1;
  LC_SPEED_CHANGE_ATTEMPTS_ALLOWED    :bit2;
  LC_SPEED_CHANGE_ATTEMPT_FAILED      :bit1;
  LC_CURRENT_DATA_RATE                :bit2;
  LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS:bit1;
  LC_CLR_FAILED_SPD_CHANGE_CNT        :bit1;
  LC_1_OR_MORE_TS2_SPEED_ARC_EN       :bit1;
  LC_OTHER_SIDE_EVER_SENT_GEN2        :bit1;
  LC_OTHER_SIDE_SUPPORTS_GEN2         :bit1;
  LC_OTHER_SIDE_EVER_SENT_GEN3        :bit1;
  LC_OTHER_SIDE_SUPPORTS_GEN3         :bit1;
  LC_AUTO_RECOVERY_DIS                :bit1;
  LC_SPEED_CHANGE_STATUS              :bit1;
  LC_DATA_RATE_ADVERTISED             :bit2;
  LC_CHECK_DATA_RATE                  :bit1;
  LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN   :bit1;
  LC_INIT_SPEED_NEG_IN_L0s_EN         :bit1;
  LC_INIT_SPEED_NEG_IN_L1_EN          :bit1;
  LC_DONT_CHECK_EQTS_IN_RCFG          :bit1;
  LC_DELAY_COEFF_UPDATE_DIS           :bit1;
 end;

 TPCIE_MC_BLOCK_ALL0=bit32;

 TPCIE_MC_BLOCK_ALL1=bit32;

 TPCIE_PAGE_REQ_CNTL=bitpacked record
  PRI_ENABLE:bit1;
  PRI_RESET :bit1;
  RESERVED0 :bit30;
 end;

 TPCIE_PRBS_ERRCNT_0=bit32;

 TPCIE_PRBS_ERRCNT_1=bit32;

 TPCIE_PRBS_ERRCNT_2=bit32;

 TPCIE_PRBS_ERRCNT_3=bit32;

 TPCIE_PRBS_ERRCNT_4=bit32;

 TPCIE_PRBS_ERRCNT_5=bit32;

 TPCIE_PRBS_ERRCNT_6=bit32;

 TPCIE_PRBS_ERRCNT_7=bit32;

 TPCIE_PRBS_ERRCNT_8=bit32;

 TPCIE_PRBS_ERRCNT_9=bit32;

 TPCIE_P_MISC_STATUS=bitpacked record
  P_DESKEW_ERR   :bit8;
  RESERVED0      :bit8;
  P_SYMUNLOCK_ERR:bit16;
 end;

 TPCIE_SRIOV_CONTROL=bitpacked record
  SRIOV_VF_ENABLE               :bit1;
  SRIOV_VF_MIGRATION_ENABLE     :bit1;
  SRIOV_VF_MIGRATION_INTR_ENABLE:bit1;
  SRIOV_VF_MSE                  :bit1;
  SRIOV_ARI_CAP_HIERARCHY       :bit1;
  RESERVED0                     :bit27;
 end;

 TPCIE_SRIOV_NUM_VFS=bitpacked record
  SRIOV_NUM_VFS:bit16;
  RESERVED0    :bit16;
 end;

 TPCIE_TPH_REQR_CNTL=bitpacked record
  TPH_REQR_ST_MODE_SEL:bit3;
  RESERVED0           :bit5;
  TPH_REQR_EN         :bit2;
  RESERVED1           :bit22;
 end;

 TPCIE_WRAP_DTM_MISC=bitpacked record
  DTM_BULKPHY_FREQDIV_OVERRIDE:bit1;
  RESERVED0                   :bit31;
 end;

 TPCIE_WRAP_PIF_MISC=bitpacked record
  DTM_PIF_DELAY_FI:bit3;
  RESERVED0       :bit1;
  DTM_PIF_DELAY_DI:bit3;
  DTM_PIF_ATSEL_FI:bit1;
  DTM_PIF_ATSEL_DI:bit1;
  RESERVED1       :bit23;
 end;

 TPCIE_WRAP_SCRATCH1=bit32;

 TPCIE_WRAP_SCRATCH2=bit32;

 TPEER0_FB_OFFSET_HI=bitpacked record
  PEER0_FB_OFFSET_HI:bit20;
  RESERVED0         :bit12;
 end;

 TPEER0_FB_OFFSET_LO=bitpacked record
  PEER0_FB_OFFSET_LO:bit20;
  RESERVED0         :bit11;
  PEER0_FB_EN       :bit1;
 end;

 TPEER1_FB_OFFSET_HI=bitpacked record
  PEER1_FB_OFFSET_HI:bit20;
  RESERVED0         :bit12;
 end;

 TPEER1_FB_OFFSET_LO=bitpacked record
  PEER1_FB_OFFSET_LO:bit20;
  RESERVED0         :bit11;
  PEER1_FB_EN       :bit1;
 end;

 TPEER2_FB_OFFSET_HI=bitpacked record
  PEER2_FB_OFFSET_HI:bit20;
  RESERVED0         :bit12;
 end;

 TPEER2_FB_OFFSET_LO=bitpacked record
  PEER2_FB_OFFSET_LO:bit20;
  RESERVED0         :bit11;
  PEER2_FB_EN       :bit1;
 end;

 TPEER3_FB_OFFSET_HI=bitpacked record
  PEER3_FB_OFFSET_HI:bit20;
  RESERVED0         :bit12;
 end;

 TPEER3_FB_OFFSET_LO=bitpacked record
  PEER3_FB_OFFSET_LO:bit20;
  RESERVED0         :bit11;
  PEER3_FB_EN       :bit1;
 end;

 TPERFMON_CVALUE_LOW=bit32;

 TPIPE0_MAX_REQUESTS=bitpacked record
  MAX_REQUESTS:bit10;
  RESERVED0   :bit22;
 end;

 TPIPE1_MAX_REQUESTS=bitpacked record
  MAX_REQUESTS:bit10;
  RESERVED0   :bit22;
 end;

 TPIPE2_MAX_REQUESTS=bitpacked record
  MAX_REQUESTS:bit10;
  RESERVED0   :bit22;
 end;

 TPIPE3_MAX_REQUESTS=bitpacked record
  MAX_REQUESTS:bit10;
  RESERVED0   :bit22;
 end;

 TPIPE4_MAX_REQUESTS=bitpacked record
  MAX_REQUESTS:bit10;
  RESERVED0   :bit22;
 end;

 TPIPE5_MAX_REQUESTS=bitpacked record
  MAX_REQUESTS:bit10;
  RESERVED0   :bit22;
 end;

 TPIPE6_MAX_REQUESTS=bitpacked record
  MAX_REQUESTS:bit10;
  RESERVED0   :bit22;
 end;

 TPIPE7_MAX_REQUESTS=bitpacked record
  MAX_REQUESTS:bit10;
  RESERVED0   :bit22;
 end;

 TRAS_BCI_SIGNATURE0=bit32;

 TRAS_BCI_SIGNATURE1=bit32;

 TRAS_SIGNATURE_MASK=bit32;

 TRAS_SPI_SIGNATURE0=bit32;

 TRAS_SPI_SIGNATURE1=bit32;

 TRAS_VGT_SIGNATURE0=bit32;

 TRBBMIF_STATUS_FLAG=bitpacked record
  RBBMIF_STATE       :bit3;
  RBBMIF_ACK_TIMEOUT :bit1;
  RBBMIF_READ_TIMEOUT:bit1;
  RBBMIF_FIFO_EMPTY  :bit1;
  RBBMIF_FIFO_FULL   :bit1;
  RESERVED0          :bit25;
 end;

 TRBBMIF_TIMEOUT_DIS=bitpacked record
  CLIENT0_TIMEOUT_DIS :bit1;
  CLIENT1_TIMEOUT_DIS :bit1;
  CLIENT2_TIMEOUT_DIS :bit1;
  CLIENT3_TIMEOUT_DIS :bit1;
  CLIENT4_TIMEOUT_DIS :bit1;
  CLIENT5_TIMEOUT_DIS :bit1;
  CLIENT6_TIMEOUT_DIS :bit1;
  CLIENT7_TIMEOUT_DIS :bit1;
  CLIENT8_TIMEOUT_DIS :bit1;
  CLIENT9_TIMEOUT_DIS :bit1;
  CLIENT10_TIMEOUT_DIS:bit1;
  CLIENT11_TIMEOUT_DIS:bit1;
  CLIENT12_TIMEOUT_DIS:bit1;
  CLIENT13_TIMEOUT_DIS:bit1;
  CLIENT14_TIMEOUT_DIS:bit1;
  RESERVED0           :bit17;
 end;

 TRCU_VIRT_RESET_REQ=bitpacked record
  VF       :bit16;
  RESERVED0:bit15;
  PF       :bit1;
 end;

 TRIRB_WRITE_POINTER=bitpacked record
  RIRB_WRITE_POINTER      :bit8;
  RESERVED0               :bit7;
  RIRB_WRITE_POINTER_RESET:bit1;
  RESERVED1               :bit16;
 end;

 TRLC_CGCG_CGLS_CTRL=bitpacked record
  CGCG_EN                 :bit1;
  CGLS_EN                 :bit1;
  CGLS_REP_COMPANSAT_DELAY:bit6;
  CGCG_GFX_IDLE_THRESHOLD :bit19;
  CGCG_CONTROLLER         :bit1;
  CGCG_REG_CTRL           :bit1;
  SLEEP_MODE              :bit2;
  SIM_SILICON_EN          :bit1;
 end;

 TRLC_CGCG_RAMP_CTRL=bitpacked record
  DOWN_DIV_START_UNIT:bit4;
  DOWN_DIV_STEP_UNIT :bit4;
  UP_DIV_START_UNIT  :bit4;
  UP_DIV_STEP_UNIT   :bit4;
  STEP_DELAY_CNT     :bit12;
  STEP_DELAY_UNIT    :bit4;
 end;

 TRLC_DYN_PG_REQUEST=bit32;

 TRLC_GPM_UCODE_ADDR=bitpacked record
  UCODE_ADDR:bit12;
  RESERVED0 :bit20;
 end;

 TRLC_GPM_UCODE_DATA=bit32;

 TRLC_RLCV_SAFE_MODE=bitpacked record
  CMD      :bit1;
  MESSAGE  :bit4;
  RESERVED1:bit3;
  RESPONSE :bit4;
  RESERVED :bit20;
 end;

 TRLC_SERDES_WR_CTRL=bitpacked record
  BPM_ADDR     :bit8;
  POWER_DOWN   :bit1;
  POWER_UP     :bit1;
  P1_SELECT    :bit1;
  P2_SELECT    :bit1;
  WRITE_COMMAND:bit1;
  READ_COMMAND :bit1;
  RDDATA_RESET :bit1;
  SHORT_FORMAT :bit1;
  BPM_DATA     :bit10;
  SRBM_OVERRIDE:bit1;
  RSVD_BPM_ADDR:bit1;
  REG_ADDR     :bit4;
 end;

 TRLC_SERDES_WR_DATA=bit32;

 TRLC_SOFT_RESET_GPU=bitpacked record
  SOFT_RESET_GPU:bit1;
  RESERVED      :bit31;
 end;

 TRLC_SPM_INT_STATUS=bitpacked record
  RLC_SPM_INT_STATUS:bit1;
  RESERVED0         :bit31;
 end;

 TRLC_SPM_RING_RDPTR=bit32;

 TSCLV_VIEWPORT_SIZE=bitpacked record
  VIEWPORT_HEIGHT:bit13;
  RESERVED0      :bit3;
  VIEWPORT_WIDTH :bit13;
  RESERVED1      :bit3;
 end;

 TSCL_BYPASS_CONTROL=bitpacked record
  SCL_BYPASS_MODE:bit2;
  RESERVED0      :bit30;
 end;

 TSDMA0_BA_THRESHOLD=bitpacked record
  READ_THRES :bit10;
  RESERVED0  :bit6;
  WRITE_THRES:bit10;
  RESERVED1  :bit6;
 end;

 TSDMA0_CHICKEN_BITS=bitpacked record
  COPY_EFFICIENCY_ENABLE             :bit1;
  STALL_ON_TRANS_FULL_ENABLE         :bit1;
  STALL_ON_NO_FREE_DATA_BUFFER_ENABLE:bit1;
  RESERVED0                          :bit13;
  COPY_OVERLAP_ENABLE                :bit1;
  RESERVED1                          :bit3;
  SRBM_POLL_RETRYING                 :bit1;
  RESERVED2                          :bit2;
  CG_STATUS_OUTPUT                   :bit1;
  RESERVED3                          :bit2;
  CE_AFIFO_WATERMARK                 :bit2;
  CE_DFIFO_WATERMARK                 :bit2;
  CE_LFIFO_WATERMARK                 :bit2;
 end;

 TSDMA0_GFX_DOORBELL=bitpacked record
  OFFSET   :bit21;
  RESERVED0:bit7;
  ENABLE   :bit1;
  RESERVED1:bit1;
  CAPTURED :bit1;
  RESERVED2:bit1;
 end;

 TSDMA0_PERFMON_CNTL=bitpacked record
  PERF_ENABLE0:bit1;
  PERF_CLEAR0 :bit1;
  PERF_SEL0   :bit6;
  PERF_ENABLE1:bit1;
  PERF_CLEAR1 :bit1;
  PERF_SEL1   :bit6;
  RESERVED0   :bit16;
 end;

 TSDMA0_RLC0_IB_CNTL=bitpacked record
  IB_ENABLE       :bit1;
  RESERVED0       :bit3;
  IB_SWAP_ENABLE  :bit1;
  RESERVED1       :bit3;
  SWITCH_INSIDE_IB:bit1;
  RESERVED2       :bit7;
  CMD_VMID        :bit4;
  RESERVED3       :bit11;
  RESERVED4       :bit1;
 end;

 TSDMA0_RLC0_IB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA0_RLC0_IB_SIZE=bitpacked record
  SIZE     :bit20;
  RESERVED0:bit12;
 end;

 TSDMA0_RLC0_PREEMPT=bitpacked record
  IB_PREEMPT:bit1;
  RESERVED0 :bit31;
 end;

 TSDMA0_RLC0_RB_BASE=bit32;

 TSDMA0_RLC0_RB_CNTL=bitpacked record
  RB_ENABLE                 :bit1;
  RB_SIZE                   :bit5;
  RESERVED0                 :bit3;
  RB_SWAP_ENABLE            :bit1;
  RESERVED1                 :bit2;
  RPTR_WRITEBACK_ENABLE     :bit1;
  RPTR_WRITEBACK_SWAP_ENABLE:bit1;
  RESERVED2                 :bit2;
  RPTR_WRITEBACK_TIMER      :bit5;
  RESERVED3                 :bit2;
  RB_PRIV                   :bit1;
  RB_VMID                   :bit4;
  RESERVED4                 :bit4;
 end;

 TSDMA0_RLC0_RB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA0_RLC0_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA0_RLC1_IB_CNTL=bitpacked record
  IB_ENABLE       :bit1;
  RESERVED0       :bit3;
  IB_SWAP_ENABLE  :bit1;
  RESERVED1       :bit3;
  SWITCH_INSIDE_IB:bit1;
  RESERVED2       :bit7;
  CMD_VMID        :bit4;
  RESERVED3       :bit11;
  RESERVED4       :bit1;
 end;

 TSDMA0_RLC1_IB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA0_RLC1_IB_SIZE=bitpacked record
  SIZE     :bit20;
  RESERVED0:bit12;
 end;

 TSDMA0_RLC1_PREEMPT=bitpacked record
  IB_PREEMPT:bit1;
  RESERVED0 :bit31;
 end;

 TSDMA0_RLC1_RB_BASE=bit32;

 TSDMA0_RLC1_RB_CNTL=bitpacked record
  RB_ENABLE                 :bit1;
  RB_SIZE                   :bit5;
  RESERVED0                 :bit3;
  RB_SWAP_ENABLE            :bit1;
  RESERVED1                 :bit2;
  RPTR_WRITEBACK_ENABLE     :bit1;
  RPTR_WRITEBACK_SWAP_ENABLE:bit1;
  RESERVED2                 :bit2;
  RPTR_WRITEBACK_TIMER      :bit5;
  RESERVED3                 :bit2;
  RB_PRIV                   :bit1;
  RB_VMID                   :bit4;
  RESERVED4                 :bit4;
 end;

 TSDMA0_RLC1_RB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA0_RLC1_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA1_BA_THRESHOLD=bitpacked record
  READ_THRES :bit10;
  RESERVED0  :bit6;
  WRITE_THRES:bit10;
  RESERVED1  :bit6;
 end;

 TSDMA1_CHICKEN_BITS=bitpacked record
  COPY_EFFICIENCY_ENABLE             :bit1;
  STALL_ON_TRANS_FULL_ENABLE         :bit1;
  STALL_ON_NO_FREE_DATA_BUFFER_ENABLE:bit1;
  RESERVED0                          :bit13;
  COPY_OVERLAP_ENABLE                :bit1;
  RESERVED1                          :bit3;
  SRBM_POLL_RETRYING                 :bit1;
  RESERVED2                          :bit2;
  CG_STATUS_OUTPUT                   :bit1;
  RESERVED3                          :bit2;
  CE_AFIFO_WATERMARK                 :bit2;
  CE_DFIFO_WATERMARK                 :bit2;
  CE_LFIFO_WATERMARK                 :bit2;
 end;

 TSDMA1_GFX_DOORBELL=bitpacked record
  OFFSET   :bit21;
  RESERVED0:bit7;
  ENABLE   :bit1;
  RESERVED1:bit1;
  CAPTURED :bit1;
  RESERVED2:bit1;
 end;

 TSDMA1_PERFMON_CNTL=bitpacked record
  PERF_ENABLE0:bit1;
  PERF_CLEAR0 :bit1;
  PERF_SEL0   :bit6;
  PERF_ENABLE1:bit1;
  PERF_CLEAR1 :bit1;
  PERF_SEL1   :bit6;
  RESERVED0   :bit16;
 end;

 TSDMA1_RLC0_IB_CNTL=bitpacked record
  IB_ENABLE       :bit1;
  RESERVED0       :bit3;
  IB_SWAP_ENABLE  :bit1;
  RESERVED1       :bit3;
  SWITCH_INSIDE_IB:bit1;
  RESERVED2       :bit7;
  CMD_VMID        :bit4;
  RESERVED3       :bit11;
  RESERVED4       :bit1;
 end;

 TSDMA1_RLC0_IB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA1_RLC0_IB_SIZE=bitpacked record
  SIZE     :bit20;
  RESERVED0:bit12;
 end;

 TSDMA1_RLC0_PREEMPT=bitpacked record
  IB_PREEMPT:bit1;
  RESERVED0 :bit31;
 end;

 TSDMA1_RLC0_RB_BASE=bit32;

 TSDMA1_RLC0_RB_CNTL=bitpacked record
  RB_ENABLE                 :bit1;
  RB_SIZE                   :bit5;
  RESERVED0                 :bit3;
  RB_SWAP_ENABLE            :bit1;
  RESERVED1                 :bit2;
  RPTR_WRITEBACK_ENABLE     :bit1;
  RPTR_WRITEBACK_SWAP_ENABLE:bit1;
  RESERVED2                 :bit2;
  RPTR_WRITEBACK_TIMER      :bit5;
  RESERVED3                 :bit2;
  RB_PRIV                   :bit1;
  RB_VMID                   :bit4;
  RESERVED4                 :bit4;
 end;

 TSDMA1_RLC0_RB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA1_RLC0_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA1_RLC1_IB_CNTL=bitpacked record
  IB_ENABLE       :bit1;
  RESERVED0       :bit3;
  IB_SWAP_ENABLE  :bit1;
  RESERVED1       :bit3;
  SWITCH_INSIDE_IB:bit1;
  RESERVED2       :bit7;
  CMD_VMID        :bit4;
  RESERVED3       :bit11;
  RESERVED4       :bit1;
 end;

 TSDMA1_RLC1_IB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA1_RLC1_IB_SIZE=bitpacked record
  SIZE     :bit20;
  RESERVED0:bit12;
 end;

 TSDMA1_RLC1_PREEMPT=bitpacked record
  IB_PREEMPT:bit1;
  RESERVED0 :bit31;
 end;

 TSDMA1_RLC1_RB_BASE=bit32;

 TSDMA1_RLC1_RB_CNTL=bitpacked record
  RB_ENABLE                 :bit1;
  RB_SIZE                   :bit5;
  RESERVED0                 :bit3;
  RB_SWAP_ENABLE            :bit1;
  RESERVED1                 :bit2;
  RPTR_WRITEBACK_ENABLE     :bit1;
  RPTR_WRITEBACK_SWAP_ENABLE:bit1;
  RESERVED2                 :bit2;
  RPTR_WRITEBACK_TIMER      :bit5;
  RESERVED3                 :bit2;
  RB_PRIV                   :bit1;
  RB_VMID                   :bit4;
  RESERVED4                 :bit4;
 end;

 TSDMA1_RLC1_RB_RPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA1_RLC1_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSEM_VIRT_RESET_REQ=bitpacked record
  VF       :bit16;
  RESERVED0:bit15;
  PF       :bit1;
 end;

 TSINK_DESCRIPTION10=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION11=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION12=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION13=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION14=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION15=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION16=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSINK_DESCRIPTION17=bitpacked record
  DESCRIPTION:bit8;
  RESERVED0  :bit24;
 end;

 TSLAVE_COMM_CMD_REG=bitpacked record
  SLAVE_COMM_CMD_REG_BYTE0:bit8;
  SLAVE_COMM_CMD_REG_BYTE1:bit8;
  SLAVE_COMM_CMD_REG_BYTE2:bit8;
  SLAVE_COMM_CMD_REG_BYTE3:bit8;
 end;

 TSNAPSHOT_V_COUNTER=bitpacked record
  RESERVED0:bit14;
  RESERVED1:bit18;
 end;

 TSPI_GDBG_TRAP_MASK=bitpacked record
  EXCP_EN  :bit9;
  REPLACE  :bit1;
  RESERVED0:bit22;
 end;

 TSPI_GDBG_WAVE_CNTL=bitpacked record
  STALL_RA  :bit1;
  STALL_VMID:bit16;
  RESERVED0 :bit15;
 end;

 TSPI_PS_MAX_WAVE_ID=bitpacked record
  MAX_WAVE_ID:bit12;
  RESERVED0  :bit20;
 end;

 TSQ_DEBUG_STS_LOCAL=bitpacked record
  BUSY      :bit1;
  RESERVED0 :bit3;
  WAVE_LEVEL:bit6;
  RESERVED1 :bit22;
 end;

 TSQ_M0_GPR_IDX_WORD=bitpacked record
  INDEX    :bit8;
  RESERVED0:bit4;
  VSRC0_REL:bit1;
  VSRC1_REL:bit1;
  VSRC2_REL:bit1;
  VDST_REL :bit1;
  RESERVED1:bit16;
 end;

 TSQ_PERFCOUNTER0_HI=bit32;

 TSQ_PERFCOUNTER0_LO=bit32;

 TSQ_PERFCOUNTER1_HI=bit32;

 TSQ_PERFCOUNTER1_LO=bit32;

 TSQ_PERFCOUNTER2_HI=bit32;

 TSQ_PERFCOUNTER2_LO=bit32;

 TSQ_PERFCOUNTER3_HI=bit32;

 TSQ_PERFCOUNTER3_LO=bit32;

 TSQ_PERFCOUNTER4_HI=bit32;

 TSQ_PERFCOUNTER4_LO=bit32;

 TSQ_PERFCOUNTER5_HI=bit32;

 TSQ_PERFCOUNTER5_LO=bit32;

 TSQ_PERFCOUNTER6_HI=bit32;

 TSQ_PERFCOUNTER6_LO=bit32;

 TSQ_PERFCOUNTER7_HI=bit32;

 TSQ_PERFCOUNTER7_LO=bit32;

 TSQ_PERFCOUNTER8_HI=bit32;

 TSQ_PERFCOUNTER8_LO=bit32;

 TSQ_PERFCOUNTER9_HI=bit32;

 TSQ_PERFCOUNTER9_LO=bit32;

 TSQ_POWER_THROTTLE2=bitpacked record
  MAX_POWER_DELTA         :bit14;
  RESERVED0               :bit2;
  SHORT_TERM_INTERVAL_SIZE:bit10;
  RESERVED1               :bit1;
  LONG_TERM_INTERVAL_RATIO:bit4;
  USE_REF_CLOCK           :bit1;
 end;

 TSQ_RANDOM_WAVE_PRI=bitpacked record
  RET      :bit7;
  RUI      :bit3;
  RNG      :bit11;
  RESERVED0:bit11;
 end;

 TSQ_VOP3_0_SDST_ENC=bitpacked record
  VDST    :bit8;
  SDST    :bit7;
  CLAMP   :bit1;
  OP      :bit10;
  ENCODING:bit6;
 end;

 TSRBM_CHIP_REVISION=bitpacked record
  CHIP_REVISION:bit8;
  RESERVED0    :bit24;
 end;

 TSRBM_GFX_CNTL_DATA=bitpacked record
  PIPEID   :bit2;
  MEID     :bit2;
  VMID     :bit4;
  QUEUEID  :bit3;
  RESERVED0:bit21;
 end;

 TSRBM_MC_CLKEN_CNTL=bitpacked record
  PREFIX_DELAY_CNT:bit4;
  RESERVED0       :bit4;
  POST_DELAY_CNT  :bit5;
  RESERVED1       :bit19;
 end;

 TSWRST_EP_COMMAND_0=bitpacked record
  EP_CFG_RESET_ONLY:bit1;
  EP_SOFT_RESET    :bit1;
  EP_DRV_RESET     :bit1;
  RESERVED0        :bit5;
  EP_HOT_RESET     :bit1;
  EP_LNKDWN_RESET  :bit1;
  EP_LNKDIS_RESET  :bit1;
  RESERVED1        :bit5;
  EP_FLR0_RESET    :bit1;
  EP_FLR1_RESET    :bit1;
  EP_FLR2_RESET    :bit1;
  RESERVED2        :bit13;
 end;

 TSWRST_EP_CONTROL_0=bitpacked record
  EP_CFG_RESET_ONLY_EN  :bit1;
  EP_SOFT_RESET_EN      :bit1;
  EP_DRV_RESET_EN       :bit1;
  RESERVED0             :bit5;
  EP_HOT_RESET_EN       :bit1;
  EP_LNKDWN_RESET_EN    :bit1;
  EP_LNKDIS_RESET_EN    :bit1;
  RESERVED1             :bit5;
  EP_FLR0_RESET_EN      :bit1;
  EP_FLR1_RESET_EN      :bit1;
  EP_FLR2_RESET_EN      :bit1;
  EP_CFG_WR_RESET_EN    :bit1;
  EP_FLR_DISABLE_CFG_RST:bit4;
  RESERVED2             :bit8;
 end;

 TSXIFCCG_DEBUG_REG0=bitpacked record
  position_address            :bit6;
  point_address               :bit3;
  sx_pending_rd_state_var_indx:bit3;
  sx_pending_rd_req_mask      :bit4;
  sx_pending_rd_pci           :bit10;
  sx_pending_rd_aux_sel       :bit2;
  sx_pending_rd_sp_id         :bit2;
  sx_pending_rd_aux_inc       :bit1;
  sx_pending_rd_advance       :bit1;
 end;

 TSXIFCCG_DEBUG_REG1=bitpacked record
  available_positions              :bit7;
  sx_receive_indx                  :bit3;
  sx_pending_fifo_contents         :bit5;
  statevar_bits_vs_out_misc_vec_ena:bit1;
  statevar_bits_disable_sp         :bit4;
  aux_sel                          :bit2;
  sx_to_pa_empty_1                 :bit1;
  sx_to_pa_empty_0                 :bit1;
  pasx_req_cnt_1                   :bit4;
  pasx_req_cnt_0                   :bit4;
 end;

 TSXIFCCG_DEBUG_REG2=bitpacked record
  param_cache_base           :bit7;
  sx_aux                     :bit2;
  sx_request_indx            :bit6;
  req_active_verts_loaded    :bit1;
  req_active_verts           :bit7;
  vgt_to_ccgen_state_var_indx:bit3;
  vgt_to_ccgen_active_verts  :bit6;
 end;

 TSXIFCCG_DEBUG_REG3=bitpacked record
  ALWAYS_ZERO                         :bit8;
  vertex_fifo_entriesavailable        :bit4;
  statevar_bits_vs_out_ccdist1_vec_ena:bit1;
  statevar_bits_vs_out_ccdist0_vec_ena:bit1;
  available_positions                 :bit7;
  current_state                       :bit2;
  vertex_fifo_empty                   :bit1;
  vertex_fifo_full                    :bit1;
  sx0_receive_fifo_empty              :bit1;
  sx0_receive_fifo_full               :bit1;
  vgt_to_ccgen_fifo_empty             :bit1;
  vgt_to_ccgen_fifo_full              :bit1;
  ccgen_to_clipcc_fifo_full           :bit1;
  sx0_receive_fifo_write              :bit1;
  ccgen_to_clipcc_write               :bit1;
 end;

 TSX_PERFCOUNTER0_HI=bit32;

 TSX_PERFCOUNTER0_LO=bit32;

 TSX_PERFCOUNTER1_HI=bit32;

 TSX_PERFCOUNTER1_LO=bit32;

 TSX_PERFCOUNTER2_HI=bit32;

 TSX_PERFCOUNTER2_LO=bit32;

 TSX_PERFCOUNTER3_HI=bit32;

 TSX_PERFCOUNTER3_LO=bit32;

 TTA_BC_BASE_ADDR_HI=bitpacked record
  ADDRESS  :bit8;
  RESERVED0:bit24;
 end;

 TTA_CS_BC_BASE_ADDR=bit32;

 TTA_PERFCOUNTER0_HI=bit32;

 TTA_PERFCOUNTER0_LO=bit32;

 TTA_PERFCOUNTER1_HI=bit32;

 TTA_PERFCOUNTER1_LO=bit32;

 TTCA_CGTT_SCLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TTCC_CGTT_SCLK_CTRL=bitpacked record
  ON_DELAY      :bit4;
  OFF_HYSTERESIS:bit8;
  RESERVED0     :bit12;
  SOFT_OVERRIDE7:bit1;
  SOFT_OVERRIDE6:bit1;
  SOFT_OVERRIDE5:bit1;
  SOFT_OVERRIDE4:bit1;
  SOFT_OVERRIDE3:bit1;
  SOFT_OVERRIDE2:bit1;
  SOFT_OVERRIDE1:bit1;
  SOFT_OVERRIDE0:bit1;
 end;

 TTC_CFG_L1_VOLATILE=bitpacked record
  VOL      :bit4;
  RESERVED0:bit28;
 end;

 TTC_CFG_L2_VOLATILE=bitpacked record
  VOL      :bit4;
  RESERVED0:bit28;
 end;

 TTD_PERFCOUNTER0_HI=bit32;

 TTD_PERFCOUNTER0_LO=bit32;

 TTD_PERFCOUNTER1_HI=bit32;

 TTD_PERFCOUNTER1_LO=bit32;

 TTHM_TMON0_INT_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_INT_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_INT_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TUNIPHY_PLL_SS_CNTL=bitpacked record
  UNIPHY_PLL_SS_STEP_NUM:bit12;
  UNIPHY_PLL_DSMOD_EN   :bit1;
  UNIPHY_PLL_SS_EN      :bit1;
  RESERVED0             :bit18;
 end;

 TUNIPHY_TPG_CONTROL=bitpacked record
  UNIPHY_STATIC_TEST_PATTERN:bit10;
  RESERVED0                 :bit6;
  UNIPHY_TPG_EN             :bit1;
  UNIPHY_TPG_SEL            :bit3;
  RESERVED1                 :bit12;
 end;

 TUNIPHY_TX_CONTROL1=bitpacked record
  UNIPHY_PREMPH_STR0:bit3;
  RESERVED0         :bit1;
  UNIPHY_PREMPH_STR1:bit3;
  RESERVED1         :bit1;
  UNIPHY_PREMPH_STR2:bit3;
  RESERVED2         :bit1;
  UNIPHY_PREMPH_STR3:bit3;
  RESERVED3         :bit1;
  UNIPHY_PREMPH_STR4:bit3;
  RESERVED4         :bit1;
  UNIPHY_TX_VS0     :bit2;
  UNIPHY_TX_VS1     :bit2;
  UNIPHY_TX_VS2     :bit2;
  UNIPHY_TX_VS3     :bit2;
  UNIPHY_TX_VS4     :bit2;
  RESERVED5         :bit2;
 end;

 TUNIPHY_TX_CONTROL2=bitpacked record
  UNIPHY_PREMPH0_PC:bit2;
  RESERVED0        :bit2;
  UNIPHY_PREMPH1_PC:bit2;
  RESERVED1        :bit2;
  UNIPHY_PREMPH2_PC:bit2;
  RESERVED2        :bit2;
  UNIPHY_PREMPH3_PC:bit2;
  RESERVED3        :bit2;
  UNIPHY_PREMPH4_PC:bit2;
  RESERVED4        :bit2;
  UNIPHY_PREMPH_SEL:bit1;
  UNIPHY_RT0_CPSEL :bit2;
  UNIPHY_RT1_CPSEL :bit2;
  UNIPHY_RT2_CPSEL :bit2;
  UNIPHY_RT3_CPSEL :bit2;
  UNIPHY_RT4_CPSEL :bit2;
  RESERVED5        :bit1;
 end;

 TUNIPHY_TX_CONTROL3=bitpacked record
  UNIPHY_PREMPH_PW_CLK :bit2;
  UNIPHY_PREMPH_PW_DAT :bit2;
  UNIPHY_PREMPH_CS_CLK :bit4;
  UNIPHY_PREMPH_CS_DAT :bit4;
  UNIPHY_PREMPH_STR_CLK:bit3;
  RESERVED0            :bit1;
  UNIPHY_PREMPH_STR_DAT:bit3;
  RESERVED1            :bit1;
  UNIPHY_PESEL0        :bit1;
  UNIPHY_PESEL1        :bit1;
  UNIPHY_PESEL2        :bit1;
  UNIPHY_PESEL3        :bit1;
  UNIPHY_TX_VS_ADJ     :bit5;
  RESERVED2            :bit2;
  UNIPHY_LVDS_PULLDWN  :bit1;
 end;

 TUNIPHY_TX_CONTROL4=bitpacked record
  UNIPHY_TX_NVS_CLK:bit5;
  UNIPHY_TX_NVS_DAT:bit5;
  RESERVED0        :bit2;
  UNIPHY_TX_PVS_CLK:bit5;
  UNIPHY_TX_PVS_DAT:bit5;
  RESERVED1        :bit2;
  UNIPHY_TX_OP_CLK :bit3;
  RESERVED2        :bit1;
  UNIPHY_TX_OP_DAT :bit3;
  RESERVED3        :bit1;
 end;

 TUNP_GRPH_SWAP_CNTL=bitpacked record
  GRPH_ENDIAN_SWAP   :bit2;
  RESERVED0          :bit2;
  GRPH_RED_CROSSBAR  :bit2;
  GRPH_GREEN_CROSSBAR:bit2;
  GRPH_BLUE_CROSSBAR :bit2;
  RESERVED1          :bit22;
 end;

 TUNP_GRPH_X_START_C=bitpacked record
  GRPH_X_START_C:bit14;
  RESERVED0     :bit18;
 end;

 TUNP_GRPH_X_START_L=bitpacked record
  GRPH_X_START_L:bit14;
  RESERVED0     :bit18;
 end;

 TUNP_GRPH_Y_START_C=bitpacked record
  GRPH_Y_START_C:bit14;
  RESERVED0     :bit18;
 end;

 TUNP_GRPH_Y_START_L=bitpacked record
  GRPH_Y_START_L:bit14;
  RESERVED0     :bit18;
 end;

 TUVD_GPCOM_VCPU_CMD=bitpacked record
  CMD_SEND  :bit1;
  CMD       :bit30;
  CMD_SOURCE:bit1;
 end;

 TUVD_LMI_CACHE_CTRL=bitpacked record
  IT_EN     :bit1;
  IT_FLUSH  :bit1;
  CM_EN     :bit1;
  CM_FLUSH  :bit1;
  VCPU_EN   :bit1;
  VCPU_FLUSH:bit1;
  RESERVED0 :bit26;
 end;

 TUVD_LMI_EXT40_ADDR=bitpacked record
  ADDR      :bit8;
  RESERVED0 :bit8;
  INDEX     :bit5;
  RESERVED1 :bit10;
  WRITE_ADDR:bit1;
 end;

 TUVD_LMI_SWAP_CNTL2=bitpacked record
  SCPU_R_MC_SWAP:bit2;
  SCPU_W_MC_SWAP:bit2;
  RESERVED0     :bit28;
 end;

 TUVD_SEMA_ADDR_HIGH=bitpacked record
  ADDR_42_23:bit20;
  RESERVED0 :bit12;
 end;

 TVCE_LMI_CACHE_CTRL=bitpacked record
  VCPU_EN  :bit1;
  RESERVED0:bit1;
  RESERVED1:bit30;
 end;

 TVCE_LMI_SWAP_CNTL1=bitpacked record
  VCPU_R_MC_SWAP:bit2;
  RD_MC_CID_SWAP:bit12;
  RESERVED0     :bit6;
  RESERVED1     :bit6;
  RESERVED2     :bit6;
 end;

 TVCE_LMI_SWAP_CNTL2=bitpacked record
  WR_MC_CID_SWAP:bit8;
  RESERVED0     :bit6;
  RESERVED1     :bit4;
  RESERVED2     :bit2;
  RESERVED3     :bit4;
  RESERVED4     :bit2;
  RESERVED5     :bit4;
  RESERVED6     :bit2;
 end;

 TVCE_LMI_SWAP_CNTL3=bitpacked record
  RD_MC_CID_SWAP:bit2;
  RESERVED0     :bit12;
  RESERVED1     :bit1;
  RESERVED2     :bit5;
  RESERVED3     :bit1;
  RESERVED4     :bit5;
  RESERVED5     :bit1;
  RESERVED6     :bit5;
 end;

 TVCE_SYS_INT_STATUS=bitpacked record
  RESERVED0                     :bit1;
  RESERVED1                     :bit2;
  VCE_SYS_INT_TRAP_INTERRUPT_INT:bit1;
  RESERVED2                     :bit1;
  RESERVED3                     :bit6;
  RESERVED4                     :bit1;
  RESERVED5                     :bit1;
  RESERVED6                     :bit1;
  RESERVED7                     :bit1;
  RESERVED8                     :bit1;
  RESERVED9                     :bit1;
  RESERVED10                    :bit1;
  RESERVED11                    :bit14;
 end;

 TVGA25_PPLL_REF_DIV=bitpacked record
  VGA25_PPLL_REF_DIV:bit10;
  RESERVED0         :bit22;
 end;

 TVGA28_PPLL_REF_DIV=bitpacked record
  VGA28_PPLL_REF_DIV:bit10;
  RESERVED0         :bit22;
 end;

 TVGA41_PPLL_REF_DIV=bitpacked record
  VGA41_PPLL_REF_DIV:bit10;
  RESERVED0         :bit22;
 end;

 TVGADCC_DBG_DCCIF_C=bit32;

 TVGA_RENDER_CONTROL=bitpacked record
  VGA_BLINK_RATE                  :bit5;
  VGA_BLINK_MODE                  :bit2;
  VGA_CURSOR_BLINK_INVERT         :bit1;
  VGA_EXTD_ADDR_COUNT_ENABLE      :bit1;
  RESERVED0                       :bit7;
  VGA_VSTATUS_CNTL                :bit2;
  RESERVED1                       :bit6;
  VGA_LOCK_8DOT                   :bit1;
  VGAREG_LINECMP_COMPATIBILITY_SEL:bit1;
  RESERVED2                       :bit6;
 end;

 TVGT_DMA_INDEX_TYPE=bitpacked record
  INDEX_TYPE  :bit2;
  SWAP_MODE   :bit2;
  BUF_TYPE    :bit2;
  RDREQ_POLICY:bit1;
  RESERVED0   :bit2;
  NOT_EOP     :bit1;
  REQ_PATH    :bit1;
  MTYPE       :bit2;
  RESERVED1   :bit19;
 end;

 TVGT_DRAW_INITIATOR=bitpacked record
  SOURCE_SELECT :bit2;
  MAJOR_MODE    :bit2;
  SPRITE_EN_R6XX:bit1;
  NOT_EOP       :bit1;
  USE_OPAQUE    :bit1;
  RESERVED0     :bit25;
 end;

 TVGT_ESGS_RING_SIZE=bit32;

 TVGT_GSVS_RING_SIZE=bit32;

 TVGT_GS_ONCHIP_CNTL=bitpacked record
  ES_VERTS_PER_SUBGRP:bit11;
  GS_PRIMS_PER_SUBGRP:bit11;
  RESERVED0          :bit10;
 end;

 TVGT_PRIMITIVEID_EN=bitpacked record
  PRIMITIVEID_EN      :bit1;
  DISABLE_RESET_ON_EOI:bit1;
  RESERVED0           :bit30;
 end;

 TVGT_PRIMITIVE_TYPE=bitpacked record
  PRIM_TYPE:bit6;
  RESERVED0:bit26;
 end;

 TVGT_STRMOUT_CONFIG=bitpacked record
  STREAMOUT_0_EN      :bit1;
  STREAMOUT_1_EN      :bit1;
  STREAMOUT_2_EN      :bit1;
  STREAMOUT_3_EN      :bit1;
  RAST_STREAM         :bit3;
  RESERVED0           :bit1;
  RAST_STREAM_MASK    :bit4;
  RESERVED1           :bit19;
  USE_RAST_STREAM_MASK:bit1;
 end;

 TVGT_TF_MEMORY_BASE=bit32;

 TVGT_VS_MAX_WAVE_ID=bitpacked record
  MAX_WAVE_ID:bit12;
  RESERVED0  :bit20;
 end;

 TVM_FAULT_CLIENT_ID=bitpacked record
  MEMORY_CLIENT            :bit9;
  MEMORY_CLIENT_MASK       :bit9;
  MEMORY_CLIENT_ID_MSB     :bit1;
  MEMORY_CLIENT_ID_MASK_MSB:bit1;
  RESERVED0                :bit12;
 end;

 TWALL_CLOCK_COUNTER=bit32;

 TWD_PERFCOUNTER0_HI=bit32;

 TWD_PERFCOUNTER0_LO=bit32;

 TWD_PERFCOUNTER1_HI=bit32;

 TWD_PERFCOUNTER1_LO=bit32;

 TWD_PERFCOUNTER2_HI=bit32;

 TWD_PERFCOUNTER2_LO=bit32;

 TWD_PERFCOUNTER3_HI=bit32;

 TWD_PERFCOUNTER3_LO=bit32;

 TXDMA_IF_BIF_STATUS=bitpacked record
  XDMA_IF_BIF_ERROR_STATUS:bit4;
  RESERVED0               :bit4;
  XDMA_IF_BIF_ERROR_CLEAR :bit1;
  RESERVED1               :bit23;
 end;

 TXDMA_SLV_SLS_PITCH=bitpacked record
  XDMA_SLV_SLS_PITCH:bit14;
  RESERVED0         :bit2;
  XDMA_SLV_SLS_WIDTH:bit14;
  RESERVED1         :bit2;
 end;

 TABM_TEST_DEBUG_DATA=bit32;

 TATC_ATS_FAULT_DEBUG=bitpacked record
  CREDITS_ATS_IH                            :bit5;
  RESERVED0                                 :bit3;
  ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES:bit1;
  RESERVED1                                 :bit7;
  CLEAR_FAULT_STATUS_ADDR                   :bit1;
  RESERVED2                                 :bit15;
 end;

 TATC_ATS_VMID_STATUS=bitpacked record
  VMID0_OUTSTANDING :bit1;
  VMID1_OUTSTANDING :bit1;
  VMID2_OUTSTANDING :bit1;
  VMID3_OUTSTANDING :bit1;
  VMID4_OUTSTANDING :bit1;
  VMID5_OUTSTANDING :bit1;
  VMID6_OUTSTANDING :bit1;
  VMID7_OUTSTANDING :bit1;
  VMID8_OUTSTANDING :bit1;
  VMID9_OUTSTANDING :bit1;
  VMID10_OUTSTANDING:bit1;
  VMID11_OUTSTANDING:bit1;
  VMID12_OUTSTANDING:bit1;
  VMID13_OUTSTANDING:bit1;
  VMID14_OUTSTANDING:bit1;
  VMID15_OUTSTANDING:bit1;
  RESERVED0         :bit16;
 end;

 TATC_L1RD_DEBUG2_TLB=bitpacked record
  RESERVED0               :bit10;
  RESERVED1               :bit2;
  INJECT_SOFT_PARITY_ERROR:bit1;
  INJECT_HARD_PARITY_ERROR:bit1;
  CLEAR_CAM_PARITY_ERROR  :bit1;
  CAM_INDEX               :bit5;
  RESERVED2               :bit12;
 end;

 TATC_L1WR_DEBUG2_TLB=bitpacked record
  RESERVED0               :bit10;
  RESERVED1               :bit2;
  INJECT_SOFT_PARITY_ERROR:bit1;
  INJECT_HARD_PARITY_ERROR:bit1;
  CLEAR_CAM_PARITY_ERROR  :bit1;
  CAM_INDEX               :bit5;
  RESERVED2               :bit12;
 end;

 TAUX_DPHY_TX_CONTROL=bitpacked record
  AUX_TX_PRECHARGE_LEN    :bit3;
  RESERVED0               :bit5;
  AUX_TX_PRECHARGE_SYMBOLS:bit6;
  RESERVED1               :bit2;
  AUX_MODE_DET_CHECK_DELAY:bit3;
  RESERVED2               :bit13;
 end;

 TAUX_GTC_SYNC_STATUS=bitpacked record
  AUX_GTC_SYNC_DONE             :bit1;
  AUX_GTC_SYNC_REQ              :bit1;
  RESERVED0                     :bit2;
  AUX_GTC_SYNC_RX_TIMEOUT_STATE :bit3;
  AUX_GTC_SYNC_TIMEOUT          :bit1;
  AUX_GTC_SYNC_RX_OVERFLOW      :bit1;
  AUX_GTC_SYNC_HPD_DISCON       :bit1;
  AUX_GTC_SYNC_RX_PARTIAL_BYTE  :bit1;
  AUX_GTC_SYNC_NON_AUX_MODE     :bit1;
  AUX_GTC_SYNC_RX_MIN_COUNT_VIOL:bit1;
  RESERVED1                     :bit1;
  AUX_GTC_SYNC_RX_INVALID_STOP  :bit1;
  RESERVED2                     :bit2;
  AUX_GTC_SYNC_RX_SYNC_INVALID_L:bit1;
  AUX_GTC_SYNC_RX_SYNC_INVALID_H:bit1;
  AUX_GTC_SYNC_RX_INVALID_START :bit1;
  AUX_GTC_SYNC_RX_RECV_NO_DET   :bit1;
  RESERVED3                     :bit1;
  AUX_GTC_SYNC_RX_RECV_INVALID_H:bit1;
  AUX_GTC_SYNC_RX_RECV_INVALID_L:bit1;
  AUX_GTC_SYNC_REPLY_BYTE_COUNT :bit5;
  AUX_GTC_SYNC_NACKED           :bit1;
  AUX_GTC_MASTER_REQ_BY_RX      :bit1;
  RESERVED4                     :bit1;
 end;

 TAUX_TEST_DEBUG_DATA=bit32;

 TAVSYNC_COUNTER_READ=bit32;

 TAZALIA_MEM_PWR_CTRL=bitpacked record
  AZ_MEM_PWR_FORCE              :bit2;
  AZ_MEM_PWR_DIS                :bit1;
  AZ_INPUT_STREAM0_MEM_PWR_FORCE:bit2;
  AZ_INPUT_STREAM0_MEM_PWR_DIS  :bit1;
  AZ_INPUT_STREAM1_MEM_PWR_FORCE:bit2;
  AZ_INPUT_STREAM1_MEM_PWR_DIS  :bit1;
  AZ_INPUT_STREAM2_MEM_PWR_FORCE:bit2;
  AZ_INPUT_STREAM2_MEM_PWR_DIS  :bit1;
  AZ_INPUT_STREAM3_MEM_PWR_FORCE:bit2;
  AZ_INPUT_STREAM3_MEM_PWR_DIS  :bit1;
  AZ_INPUT_STREAM4_MEM_PWR_FORCE:bit2;
  AZ_INPUT_STREAM4_MEM_PWR_DIS  :bit1;
  AZ_INPUT_STREAM5_MEM_PWR_FORCE:bit2;
  AZ_INPUT_STREAM5_MEM_PWR_DIS  :bit1;
  RESERVED0                     :bit7;
  AZ_MEM_PWR_MODE_SEL           :bit2;
  RESERVED1                     :bit2;
 end;

 TAZALIA_SCLK_CONTROL=bitpacked record
  RESERVED0         :bit2;
  RESERVED1         :bit2;
  AUDIO_SCLK_CONTROL:bit2;
  RESERVED2         :bit26;
 end;

 TAZALIA_STREAM_DEBUG=bit32;

 TAZALIA_STREAM_INDEX=bitpacked record
  AZALIA_STREAM_REG_INDEX   :bit8;
  AZALIA_STREAM_REG_WRITE_EN:bit1;
  RESERVED0                 :bit23;
 end;

 TAZ_TEST_DEBUG_INDEX=bitpacked record
  AZ_TEST_DEBUG_INDEX   :bit8;
  AZ_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0             :bit23;
 end;

 TBIF_BUSY_DELAY_CNTR=bitpacked record
  DELAY_CNT:bit6;
  RESERVED0:bit26;
 end;

 TBIF_IMPCTL_SMPLCNTL=bitpacked record
  FORCE_DONE         :bit1;
  RxPDNB             :bit1;
  TxPDNB_pd          :bit1;
  TxPDNB_pu          :bit1;
  RESERVED0          :bit4;
  SAMPLE_PERIOD      :bit5;
  EXTEND_SAMPLES     :bit1;
  FORCE_ENABLE       :bit1;
  SETUP_TIME         :bit5;
  LOWER_SAMPLE_THRESH:bit6;
  UPPER_SAMPLE_THRESH:bit6;
 end;

 TBIF_RB_WPTR_ADDR_HI=bitpacked record
  ADDR     :bit8;
  RESERVED0:bit24;
 end;

 TBIF_RB_WPTR_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TBIF_RFE_IMPRST_CNTL=bitpacked record
  REG_RST_impEn:bit1;
  RESERVED0    :bit1;
  RESERVED1    :bit30;
 end;

 TCAPTURE_HOST_BUSNUM=bitpacked record
  CHECK_EN :bit1;
  RESERVED0:bit31;
 end;

 TCC_GIO_IOCCFG_FUSES=bitpacked record
  RESERVED0:bit1;
  NB_REV_ID:bit10;
  RESERVED1:bit21;
 end;

 TCC_SQC_BANK_DISABLE=bitpacked record
  RESERVED0        :bit1;
  RESERVED1        :bit15;
  SQC0_BANK_DISABLE:bit4;
  SQC1_BANK_DISABLE:bit4;
  SQC2_BANK_DISABLE:bit4;
  SQC3_BANK_DISABLE:bit4;
 end;

 TCG_DISPLAY_GAP_CNTL=bitpacked record
  DISP_GAP         :bit2;
  RESERVED0        :bit2;
  VBI_TIMER_COUNT  :bit14;
  RESERVED1        :bit2;
  VBI_TIMER_UNIT   :bit3;
  RESERVED2        :bit1;
  DISP_GAP_MCHG    :bit2;
  RESERVED3        :bit2;
  VBI_TIMER_DISABLE:bit1;
  RESERVED4        :bit3;
 end;

 TCG_FREQ_TRAN_VOTING=bitpacked record
  RESERVED0 :bit1;
  RESERVED1 :bit1;
  RESERVED2 :bit1;
  RESERVED3 :bit1;
  RESERVED4 :bit1;
  RESERVED5 :bit1;
  RESERVED6 :bit1;
  RESERVED7 :bit1;
  RESERVED8 :bit1;
  RESERVED9 :bit1;
  RESERVED10:bit1;
  RESERVED11:bit1;
  RESERVED12:bit1;
  RESERVED13:bit1;
  RESERVED14:bit2;
  RESERVED15:bit1;
  RESERVED16:bit1;
  RESERVED17:bit4;
  RESERVED18:bit1;
  RESERVED19:bit1;
  RESERVED20:bit1;
  RESERVED21:bit1;
  RESERVED22:bit1;
  RESERVED23:bit1;
  RESERVED24:bit4;
 end;

 TCG_SPLL_FUNC_CNTL_2=bitpacked record
  SCLK_MUX_SEL        :bit9;
  RESERVED0           :bit2;
  SPLL_CTLREQ         :bit1;
  RESERVED1           :bit10;
  SPLL_BYPASS_CHG     :bit1;
  SPLL_CTLREQ_CHG     :bit1;
  SPLL_RESET_CHG      :bit1;
  SPLL_BABY_STEP_CHG  :bit1;
  SCLK_MUX_UPDATE     :bit1;
  SPLL_UNLOCK_CLEAR   :bit1;
  SPLL_CLKF_UPDATE    :bit1;
  RESERVED2           :bit1;
  SPLL_TEST_UNLOCK_CLR:bit1;
  RESERVED3           :bit1;
 end;

 TCG_SPLL_FUNC_CNTL_3=bitpacked record
  SPLL_FB_DIV:bit26;
  RESERVED0  :bit2;
  SPLL_DITHEN:bit1;
  RESERVED1  :bit3;
 end;

 TCG_SPLL_FUNC_CNTL_4=bitpacked record
  SPLL_SCLK_TEST_SEL :bit4;
  RESERVED0          :bit1;
  SPLL_SCLK_EXT_SEL  :bit2;
  SPLL_SCLK_EN       :bit2;
  SPLL_SSAMP_EN      :bit1;
  SPLL_SPARE         :bit9;
  RESERVED1          :bit2;
  TEST_FRAC_BYPASS   :bit1;
  RESERVED2          :bit1;
  SPLL_ILOCK         :bit1;
  SPLL_FBCLK_SEL     :bit1;
  SPLL_VCTRLADC_EN   :bit1;
  SPLL_SCLK_EXT      :bit2;
  SPLL_SPARE_EXT     :bit3;
  SPLL_VTOI_BIAS_CNTL:bit1;
 end;

 TCG_SPLL_FUNC_CNTL_5=bitpacked record
  FBDIV_SSC_BYPASS:bit1;
  RISEFBVCO_EN    :bit1;
  PFD_RESET_CNTRL :bit2;
  RESET_TIMER     :bit2;
  FAST_LOCK_CNTRL :bit2;
  FAST_LOCK_EN    :bit1;
  RESET_ANTI_MUX  :bit1;
  REFCLK_BYPASS_EN:bit1;
  PLLBYPASS       :bit1;
  RESERVED0       :bit20;
 end;

 TCG_SPLL_FUNC_CNTL_6=bitpacked record
  SCLKMUX0_CLKOFF_CNT:bit8;
  SCLKMUX1_CLKOFF_CNT:bit8;
  SPLL_VCTL_EN       :bit1;
  SPLL_VCTL_CNTRL_IN :bit4;
  SPLL_VCTL_CNTRL_OUT:bit4;
  SPLL_LF_CNTR       :bit7;
 end;

 TCG_SPLL_FUNC_CNTL_7=bitpacked record
  SPLL_BW_CNTRL:bit12;
  RESERVED0    :bit20;
 end;

 TCG_THERMAL_INT_CTRL=bitpacked record
  DIG_THERM_INTH        :bit8;
  DIG_THERM_INTL        :bit8;
  GNB_TEMP_THRESHOLD    :bit8;
  THERM_INTH_MASK       :bit1;
  THERM_INTL_MASK       :bit1;
  THERM_TRIGGER_MASK    :bit1;
  THERM_TRIGGER_CNB_MASK:bit1;
  THERM_GNB_HW_ENA      :bit1;
  RESERVED0             :bit3;
 end;

 TCLIENT1_PORT_STATUS=bit32;

 TCLIPPER_DEBUG_REG00=bitpacked record
  ALWAYS_ZERO                 :bit8;
  clip_ga_bc_fifo_write       :bit1;
  su_clip_baryc_free          :bit2;
  clip_to_ga_fifo_write       :bit1;
  clip_to_ga_fifo_full        :bit1;
  primic_to_clprim_fifo_empty :bit1;
  primic_to_clprim_fifo_full  :bit1;
  clip_to_outsm_fifo_empty    :bit1;
  clip_to_outsm_fifo_full     :bit1;
  vgt_to_clipp_fifo_empty     :bit1;
  vgt_to_clipp_fifo_full      :bit1;
  vgt_to_clips_fifo_empty     :bit1;
  vgt_to_clips_fifo_full      :bit1;
  clipcode_fifo_fifo_empty    :bit1;
  clipcode_fifo_full          :bit1;
  vte_out_clip_fifo_fifo_empty:bit1;
  vte_out_clip_fifo_fifo_full :bit1;
  vte_out_orig_fifo_fifo_empty:bit1;
  vte_out_orig_fifo_fifo_full :bit1;
  ccgen_to_clipcc_fifo_empty  :bit1;
  ccgen_to_clipcc_fifo_full   :bit1;
  clip_to_outsm_fifo_write    :bit1;
  vte_out_orig_fifo_fifo_write:bit1;
  vgt_to_clipp_fifo_write     :bit1;
 end;

 TCLIPPER_DEBUG_REG01=bitpacked record
  ALWAYS_ZERO                             :bit8;
  clip_extra_bc_valid                     :bit3;
  clip_vert_vte_valid                     :bit3;
  clip_to_outsm_vertex_deallocate         :bit3;
  clip_to_outsm_deallocate_slot           :bit3;
  clip_to_outsm_null_primitive            :bit1;
  vte_positions_vte_clip_vte_naninf_kill_2:bit1;
  vte_positions_vte_clip_vte_naninf_kill_1:bit1;
  vte_positions_vte_clip_vte_naninf_kill_0:bit1;
  vte_out_clip_rd_extra_bc_valid          :bit1;
  vte_out_clip_rd_vte_naninf_kill         :bit1;
  vte_out_clip_rd_vertex_store_indx       :bit2;
  clip_ga_bc_fifo_write                   :bit1;
  clip_to_ga_fifo_write                   :bit1;
  vte_out_clip_fifo_fifo_advanceread      :bit1;
  vte_out_clip_fifo_fifo_empty            :bit1;
 end;

 TCLIPPER_DEBUG_REG02=bitpacked record
  clip_extra_bc_valid              :bit3;
  clip_vert_vte_valid              :bit3;
  clip_to_outsm_clip_seq_indx      :bit2;
  clip_to_outsm_vertex_store_indx_2:bit4;
  clip_to_outsm_vertex_store_indx_1:bit4;
  clip_to_outsm_vertex_store_indx_0:bit4;
  clip_to_clipga_extra_bc_coords   :bit1;
  clip_to_clipga_vte_naninf_kill   :bit1;
  clip_to_outsm_end_of_packet      :bit1;
  clip_to_outsm_first_prim_of_slot :bit1;
  clip_to_outsm_clipped_prim       :bit1;
  clip_to_outsm_null_primitive     :bit1;
  clip_ga_bc_fifo_full             :bit1;
  clip_to_ga_fifo_full             :bit1;
  clip_ga_bc_fifo_write            :bit1;
  clip_to_ga_fifo_write            :bit1;
  clip_to_outsm_fifo_advanceread   :bit1;
  clip_to_outsm_fifo_empty         :bit1;
 end;

 TCLIPPER_DEBUG_REG03=bitpacked record
  clipsm0_clprim_to_clip_clip_code_or      :bit14;
  clipsm0_clprim_to_clip_event_id          :bit6;
  clipsm0_clprim_to_clip_state_var_indx    :bit3;
  clipsm0_clprim_to_clip_clip_primitive    :bit1;
  clipsm0_clprim_to_clip_deallocate_slot   :bit3;
  clipsm0_clprim_to_clip_first_prim_of_slot:bit1;
  clipsm0_clprim_to_clip_end_of_packet     :bit1;
  clipsm0_clprim_to_clip_event             :bit1;
  clipsm0_clprim_to_clip_null_primitive    :bit1;
  clipsm0_clprim_to_clip_prim_valid        :bit1;
 end;

 TCLIPPER_DEBUG_REG04=bitpacked record
  RESERVED0                                 :bit1;
  clipsm0_clprim_to_clip_param_cache_indx_0 :bit10;
  clipsm0_clprim_to_clip_vertex_store_indx_2:bit6;
  clipsm0_clprim_to_clip_vertex_store_indx_1:bit6;
  clipsm0_clprim_to_clip_vertex_store_indx_0:bit6;
  clipsm0_clprim_to_clip_event              :bit1;
  clipsm0_clprim_to_clip_null_primitive     :bit1;
  clipsm0_clprim_to_clip_prim_valid         :bit1;
 end;

 TCLIPPER_DEBUG_REG05=bitpacked record
  clipsm1_clprim_to_clip_clip_code_or      :bit14;
  clipsm1_clprim_to_clip_event_id          :bit6;
  clipsm1_clprim_to_clip_state_var_indx    :bit3;
  clipsm1_clprim_to_clip_clip_primitive    :bit1;
  clipsm1_clprim_to_clip_deallocate_slot   :bit3;
  clipsm1_clprim_to_clip_first_prim_of_slot:bit1;
  clipsm1_clprim_to_clip_end_of_packet     :bit1;
  clipsm1_clprim_to_clip_event             :bit1;
  clipsm1_clprim_to_clip_null_primitive    :bit1;
  clipsm1_clprim_to_clip_prim_valid        :bit1;
 end;

 TCLIPPER_DEBUG_REG06=bitpacked record
  RESERVED0                                 :bit1;
  clipsm1_clprim_to_clip_param_cache_indx_0 :bit10;
  clipsm1_clprim_to_clip_vertex_store_indx_2:bit6;
  clipsm1_clprim_to_clip_vertex_store_indx_1:bit6;
  clipsm1_clprim_to_clip_vertex_store_indx_0:bit6;
  clipsm1_clprim_to_clip_event              :bit1;
  clipsm1_clprim_to_clip_null_primitive     :bit1;
  clipsm1_clprim_to_clip_prim_valid         :bit1;
 end;

 TCLIPPER_DEBUG_REG07=bitpacked record
  clipsm2_clprim_to_clip_clip_code_or      :bit14;
  clipsm2_clprim_to_clip_event_id          :bit6;
  clipsm2_clprim_to_clip_state_var_indx    :bit3;
  clipsm2_clprim_to_clip_clip_primitive    :bit1;
  clipsm2_clprim_to_clip_deallocate_slot   :bit3;
  clipsm2_clprim_to_clip_first_prim_of_slot:bit1;
  clipsm2_clprim_to_clip_end_of_packet     :bit1;
  clipsm2_clprim_to_clip_event             :bit1;
  clipsm2_clprim_to_clip_null_primitive    :bit1;
  clipsm2_clprim_to_clip_prim_valid        :bit1;
 end;

 TCLIPPER_DEBUG_REG08=bitpacked record
  RESERVED0                                 :bit1;
  clipsm2_clprim_to_clip_param_cache_indx_0 :bit10;
  clipsm2_clprim_to_clip_vertex_store_indx_2:bit6;
  clipsm2_clprim_to_clip_vertex_store_indx_1:bit6;
  clipsm2_clprim_to_clip_vertex_store_indx_0:bit6;
  clipsm2_clprim_to_clip_event              :bit1;
  clipsm2_clprim_to_clip_null_primitive     :bit1;
  clipsm2_clprim_to_clip_prim_valid         :bit1;
 end;

 TCLIPPER_DEBUG_REG09=bitpacked record
  clipsm3_clprim_to_clip_clip_code_or      :bit14;
  clipsm3_clprim_to_clip_event_id          :bit6;
  clipsm3_clprim_to_clip_state_var_indx    :bit3;
  clipsm3_clprim_to_clip_clip_primitive    :bit1;
  clipsm3_clprim_to_clip_deallocate_slot   :bit3;
  clipsm3_clprim_to_clip_first_prim_of_slot:bit1;
  clipsm3_clprim_to_clip_end_of_packet     :bit1;
  clipsm3_clprim_to_clip_event             :bit1;
  clipsm3_clprim_to_clip_null_primitive    :bit1;
  clipsm3_clprim_to_clip_prim_valid        :bit1;
 end;

 TCLIPPER_DEBUG_REG10=bitpacked record
  RESERVED0                                 :bit1;
  clipsm3_clprim_to_clip_param_cache_indx_0 :bit10;
  clipsm3_clprim_to_clip_vertex_store_indx_2:bit6;
  clipsm3_clprim_to_clip_vertex_store_indx_1:bit6;
  clipsm3_clprim_to_clip_vertex_store_indx_0:bit6;
  clipsm3_clprim_to_clip_event              :bit1;
  clipsm3_clprim_to_clip_null_primitive     :bit1;
  clipsm3_clprim_to_clip_prim_valid         :bit1;
 end;

 TCLIPPER_DEBUG_REG11=bitpacked record
  clipsm3_clip_to_clipga_event                :bit1;
  clipsm2_clip_to_clipga_event                :bit1;
  clipsm1_clip_to_clipga_event                :bit1;
  clipsm0_clip_to_clipga_event                :bit1;
  clipsm3_clip_to_clipga_clip_primitive       :bit1;
  clipsm2_clip_to_clipga_clip_primitive       :bit1;
  clipsm1_clip_to_clipga_clip_primitive       :bit1;
  clipsm0_clip_to_clipga_clip_primitive       :bit1;
  clipsm3_clip_to_clipga_clip_to_outsm_cnt    :bit4;
  clipsm2_clip_to_clipga_clip_to_outsm_cnt    :bit4;
  clipsm1_clip_to_clipga_clip_to_outsm_cnt    :bit4;
  clipsm0_clip_to_clipga_clip_to_outsm_cnt    :bit4;
  clipsm3_clip_to_clipga_prim_valid           :bit1;
  clipsm2_clip_to_clipga_prim_valid           :bit1;
  clipsm1_clip_to_clipga_prim_valid           :bit1;
  clipsm0_clip_to_clipga_prim_valid           :bit1;
  clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt:bit1;
  clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt:bit1;
  clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt:bit1;
  clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt:bit1;
 end;

 TCLIPPER_DEBUG_REG12=bitpacked record
  ALWAYS_ZERO                          :bit8;
  clip_priority_available_vte_out_clip :bit5;
  clip_priority_available_clip_verts   :bit5;
  clip_priority_seq_indx_out           :bit2;
  clip_priority_seq_indx_vert          :bit2;
  clip_priority_seq_indx_load          :bit2;
  clipsm3_clprim_to_clip_clip_primitive:bit1;
  clipsm3_clprim_to_clip_prim_valid    :bit1;
  clipsm2_clprim_to_clip_clip_primitive:bit1;
  clipsm2_clprim_to_clip_prim_valid    :bit1;
  clipsm1_clprim_to_clip_clip_primitive:bit1;
  clipsm1_clprim_to_clip_prim_valid    :bit1;
  clipsm0_clprim_to_clip_clip_primitive:bit1;
  clipsm0_clprim_to_clip_prim_valid    :bit1;
 end;

 TCLIPPER_DEBUG_REG13=bitpacked record
  clprim_in_back_state_var_indx    :bit3;
  point_clip_candidate             :bit1;
  prim_nan_kill                    :bit1;
  clprim_clip_primitive            :bit1;
  clprim_cull_primitive            :bit1;
  prim_back_valid                  :bit1;
  vertval_bits_vertex_cc_next_valid:bit4;
  clipcc_vertex_store_indx         :bit2;
  vte_out_orig_fifo_fifo_empty     :bit1;
  clipcode_fifo_fifo_empty         :bit1;
  ccgen_to_clipcc_fifo_empty       :bit1;
  clip_priority_seq_indx_out_cnt   :bit4;
  outsm_clr_rd_orig_vertices       :bit2;
  outsm_clr_rd_clipsm_wait         :bit1;
  outsm_clr_fifo_contents          :bit5;
  outsm_clr_fifo_full              :bit1;
  outsm_clr_fifo_advanceread       :bit1;
  outsm_clr_fifo_write             :bit1;
 end;

 TCLIPPER_DEBUG_REG14=bitpacked record
  clprim_in_back_vertex_store_indx_2:bit6;
  clprim_in_back_vertex_store_indx_1:bit6;
  clprim_in_back_vertex_store_indx_0:bit6;
  outputclprimtoclip_null_primitive :bit1;
  clprim_in_back_end_of_packet      :bit1;
  clprim_in_back_first_prim_of_slot :bit1;
  clprim_in_back_deallocate_slot    :bit3;
  clprim_in_back_event_id           :bit6;
  clprim_in_back_event              :bit1;
  prim_back_valid                   :bit1;
 end;

 TCLIPPER_DEBUG_REG15=bitpacked record
  vertval_bits_vertex_vertex_store_msb     :bit16;
  primic_to_clprim_fifo_vertex_store_indx_2:bit5;
  primic_to_clprim_fifo_vertex_store_indx_1:bit5;
  primic_to_clprim_fifo_vertex_store_indx_0:bit5;
  primic_to_clprim_valid                   :bit1;
 end;

 TCLIPPER_DEBUG_REG16=bitpacked record
  sm0_prim_end_state                      :bit7;
  sm0_ps_expand                           :bit1;
  sm0_clip_vert_cnt                       :bit5;
  sm0_vertex_clip_cnt                     :bit5;
  sm0_inv_to_clip_data_valid_1            :bit1;
  sm0_inv_to_clip_data_valid_0            :bit1;
  sm0_current_state                       :bit7;
  sm0_clip_to_clipga_clip_to_outsm_cnt_eq0:bit1;
  sm0_clip_to_outsm_fifo_full             :bit1;
  sm0_highest_priority_seq                :bit1;
  sm0_outputcliptoclipga_0                :bit1;
  sm0_clprim_to_clip_prim_valid           :bit1;
 end;

 TCLIPPER_DEBUG_REG17=bitpacked record
  sm1_prim_end_state                      :bit7;
  sm1_ps_expand                           :bit1;
  sm1_clip_vert_cnt                       :bit5;
  sm1_vertex_clip_cnt                     :bit5;
  sm1_inv_to_clip_data_valid_1            :bit1;
  sm1_inv_to_clip_data_valid_0            :bit1;
  sm1_current_state                       :bit7;
  sm1_clip_to_clipga_clip_to_outsm_cnt_eq0:bit1;
  sm1_clip_to_outsm_fifo_full             :bit1;
  sm1_highest_priority_seq                :bit1;
  sm1_outputcliptoclipga_0                :bit1;
  sm1_clprim_to_clip_prim_valid           :bit1;
 end;

 TCLIPPER_DEBUG_REG18=bitpacked record
  sm2_prim_end_state                      :bit7;
  sm2_ps_expand                           :bit1;
  sm2_clip_vert_cnt                       :bit5;
  sm2_vertex_clip_cnt                     :bit5;
  sm2_inv_to_clip_data_valid_1            :bit1;
  sm2_inv_to_clip_data_valid_0            :bit1;
  sm2_current_state                       :bit7;
  sm2_clip_to_clipga_clip_to_outsm_cnt_eq0:bit1;
  sm2_clip_to_outsm_fifo_full             :bit1;
  sm2_highest_priority_seq                :bit1;
  sm2_outputcliptoclipga_0                :bit1;
  sm2_clprim_to_clip_prim_valid           :bit1;
 end;

 TCLIPPER_DEBUG_REG19=bitpacked record
  sm3_prim_end_state                      :bit7;
  sm3_ps_expand                           :bit1;
  sm3_clip_vert_cnt                       :bit5;
  sm3_vertex_clip_cnt                     :bit5;
  sm3_inv_to_clip_data_valid_1            :bit1;
  sm3_inv_to_clip_data_valid_0            :bit1;
  sm3_current_state                       :bit7;
  sm3_clip_to_clipga_clip_to_outsm_cnt_eq0:bit1;
  sm3_clip_to_outsm_fifo_full             :bit1;
  sm3_highest_priority_seq                :bit1;
  sm3_outputcliptoclipga_0                :bit1;
  sm3_clprim_to_clip_prim_valid           :bit1;
 end;

 TCNV_TEST_DEBUG_DATA=bit32;

 TCOMPUTE_DISPATCH_ID=bit32;

 TCOMPUTE_MAX_WAVE_ID=bitpacked record
  RESERVED0:bit12;
  RESERVED1:bit20;
 end;

 TCOMPUTE_USER_DATA_0=bit32;

 TCOMPUTE_USER_DATA_1=bit32;

 TCOMPUTE_USER_DATA_2=bit32;

 TCOMPUTE_USER_DATA_3=bit32;

 TCOMPUTE_USER_DATA_4=bit32;

 TCOMPUTE_USER_DATA_5=bit32;

 TCOMPUTE_USER_DATA_6=bit32;

 TCOMPUTE_USER_DATA_7=bit32;

 TCOMPUTE_USER_DATA_8=bit32;

 TCOMPUTE_USER_DATA_9=bit32;

 TCPC_PERFCOUNTER0_HI=bit32;

 TCPC_PERFCOUNTER0_LO=bit32;

 TCPC_PERFCOUNTER1_HI=bit32;

 TCPC_PERFCOUNTER1_LO=bit32;

 TCPF_PERFCOUNTER0_HI=bit32;

 TCPF_PERFCOUNTER0_LO=bit32;

 TCPF_PERFCOUNTER1_HI=bit32;

 TCPF_PERFCOUNTER1_LO=bit32;

 TCPG_PERFCOUNTER0_HI=bit32;

 TCPG_PERFCOUNTER0_LO=bit32;

 TCPG_PERFCOUNTER1_HI=bit32;

 TCPG_PERFCOUNTER1_LO=bit32;

 TCP_CE_COMPARE_COUNT=bit32;

 TCP_CPC_IC_BASE_CNTL=bitpacked record
  VMID        :bit4;
  RESERVED0   :bit19;
  ATC         :bit1;
  CACHE_POLICY:bit1;
  RESERVED1   :bit2;
  MTYPE       :bit2;
  RESERVED2   :bit3;
 end;

 TCP_CPC_SCRATCH_DATA=bit32;

 TCP_DMA_PFP_DST_ADDR=bit32;

 TCP_DMA_PFP_SRC_ADDR=bit32;

 TCP_DRAW_WINDOW_CNTL=bitpacked record
  DISABLE_DRAW_WINDOW_LO_MAX:bit1;
  DISABLE_DRAW_WINDOW_LO_MIN:bit1;
  DISABLE_DRAW_WINDOW_HI    :bit1;
  RESERVED0                 :bit5;
  MODE                      :bit1;
  RESERVED1                 :bit23;
 end;

 TCP_EOP_DONE_ADDR_HI=bitpacked record
  ADDR_HI  :bit16;
  RESERVED0:bit16;
 end;

 TCP_EOP_DONE_ADDR_LO=bitpacked record
  ADDR_SWAP:bit2;
  ADDR_LO  :bit30;
 end;

 TCP_EOP_DONE_CNTX_ID=bitpacked record
  CNTX_ID  :bit28;
  RESERVED0:bit4;
 end;

 TCP_EOP_DONE_DATA_HI=bit32;

 TCP_EOP_DONE_DATA_LO=bit32;

 TCP_GDS_BKUP_ADDR_HI=bitpacked record
  ADDR_HI  :bit16;
  RESERVED0:bit16;
 end;

 TCP_HQD_EOP_WPTR_MEM=bitpacked record
  WPTR     :bit13;
  RESERVED0:bit19;
 end;

 TCP_HQD_IB_BASE_ADDR=bitpacked record
  RESERVED0   :bit2;
  IB_BASE_ADDR:bit30;
 end;

 TCP_IB1_PREAMBLE_END=bitpacked record
  IB1_PREAMBLE_END:bit20;
  RESERVED0       :bit12;
 end;

 TCP_IB2_PREAMBLE_END=bitpacked record
  IB2_PREAMBLE_END:bit20;
  RESERVED0       :bit12;
 end;

 TCP_INT_STATUS_RING0=bitpacked record
  RESERVED0                  :bit11;
  CP_VM_DOORBELL_WR_INT_STAT :bit1;
  RESERVED1                  :bit2;
  CP_ECC_ERROR_INT_STAT      :bit1;
  RESERVED2                  :bit2;
  WRM_POLL_TIMEOUT_INT_STAT  :bit1;
  CMP_BUSY_INT_STAT          :bit1;
  GCNTX_BUSY_INT_STAT        :bit1;
  CNTX_EMPTY_INT_STAT        :bit1;
  GFX_IDLE_INT_STAT          :bit1;
  PRIV_INSTR_INT_STAT        :bit1;
  PRIV_REG_INT_STAT          :bit1;
  OPCODE_ERROR_INT_STAT      :bit1;
  RESERVED3                  :bit1;
  TIME_STAMP_INT_STAT        :bit1;
  RESERVED_BIT_ERROR_INT_STAT:bit1;
  RESERVED4                  :bit1;
  GENERIC2_INT_STAT          :bit1;
  GENERIC1_INT_STAT          :bit1;
  GENERIC0_INT_STAT          :bit1;
 end;

 TCP_INT_STATUS_RING1=bitpacked record
  RESERVED0                  :bit11;
  CP_VM_DOORBELL_WR_INT_STAT :bit1;
  RESERVED1                  :bit2;
  CP_ECC_ERROR_INT_STAT      :bit1;
  RESERVED2                  :bit2;
  WRM_POLL_TIMEOUT_INT_STAT  :bit1;
  CMP_BUSY_INT_STAT          :bit1;
  CNTX_BUSY_INT_STAT         :bit1;
  CNTX_EMPTY_INT_STAT        :bit1;
  GFX_IDLE_INT_STAT          :bit1;
  PRIV_INSTR_INT_STAT        :bit1;
  PRIV_REG_INT_STAT          :bit1;
  OPCODE_ERROR_INT_STAT      :bit1;
  RESERVED3                  :bit1;
  TIME_STAMP_INT_STAT        :bit1;
  RESERVED_BIT_ERROR_INT_STAT:bit1;
  RESERVED4                  :bit1;
  GENERIC2_INT_STAT          :bit1;
  GENERIC1_INT_STAT          :bit1;
  GENERIC0_INT_STAT          :bit1;
 end;

 TCP_INT_STATUS_RING2=bitpacked record
  RESERVED0                  :bit11;
  CP_VM_DOORBELL_WR_INT_STAT :bit1;
  RESERVED1                  :bit2;
  CP_ECC_ERROR_INT_STAT      :bit1;
  RESERVED2                  :bit2;
  WRM_POLL_TIMEOUT_INT_STAT  :bit1;
  CMP_BUSY_INT_STAT          :bit1;
  CNTX_BUSY_INT_STAT         :bit1;
  CNTX_EMPTY_INT_STAT        :bit1;
  GFX_IDLE_INT_STAT          :bit1;
  PRIV_INSTR_INT_STAT        :bit1;
  PRIV_REG_INT_STAT          :bit1;
  OPCODE_ERROR_INT_STAT      :bit1;
  RESERVED3                  :bit1;
  TIME_STAMP_INT_STAT        :bit1;
  RESERVED_BIT_ERROR_INT_STAT:bit1;
  RESERVED4                  :bit1;
  GENERIC2_INT_STAT          :bit1;
  GENERIC1_INT_STAT          :bit1;
  GENERIC0_INT_STAT          :bit1;
 end;

 TCP_MEC1_F32_INT_DIS=bitpacked record
  EDC_ROQ_FED_INT     :bit1;
  PRIV_REG_INT        :bit1;
  RESERVED_BIT_ERR_INT:bit1;
  EDC_TC_FED_INT      :bit1;
  EDC_GDS_FED_INT     :bit1;
  EDC_SCRATCH_FED_INT :bit1;
  WAVE_RESTORE_INT    :bit1;
  SUA_VIOLATION_INT   :bit1;
  EDC_DMA_FED_INT     :bit1;
  IQ_TIMER_INT        :bit1;
  RESERVED0           :bit22;
 end;

 TCP_MEC2_F32_INT_DIS=bitpacked record
  EDC_ROQ_FED_INT     :bit1;
  PRIV_REG_INT        :bit1;
  RESERVED_BIT_ERR_INT:bit1;
  EDC_TC_FED_INT      :bit1;
  EDC_GDS_FED_INT     :bit1;
  EDC_SCRATCH_FED_INT :bit1;
  WAVE_RESTORE_INT    :bit1;
  SUA_VIOLATION_INT   :bit1;
  EDC_DMA_FED_INT     :bit1;
  IQ_TIMER_INT        :bit1;
  RESERVED0           :bit22;
 end;

 TCP_MQD_BASE_ADDR_HI=bitpacked record
  BASE_ADDR_HI:bit16;
  RESERVED0   :bit16;
 end;

 TCP_PFP_LOAD_CONTROL=bitpacked record
  CONFIG_REG_EN:bit1;
  CNTX_REG_EN  :bit1;
  RESERVED0    :bit14;
  SH_GFX_REG_EN:bit1;
  RESERVED1    :bit7;
  SH_CS_REG_EN :bit1;
  RESERVED2    :bit7;
 end;

 TCP_PRED_NOT_VISIBLE=bitpacked record
  NOT_VISIBLE:bit1;
  RESERVED0  :bit31;
 end;

 TCP_QUEUE_THRESHOLDS=bitpacked record
  ROQ_IB1_START:bit6;
  RESERVED0    :bit2;
  ROQ_IB2_START:bit6;
  RESERVED1    :bit18;
 end;

 TCP_RB0_RPTR_ADDR_HI=bitpacked record
  RB_RPTR_ADDR_HI:bit16;
  RESERVED0      :bit16;
 end;

 TCP_RB1_RPTR_ADDR_HI=bitpacked record
  RB_RPTR_ADDR_HI:bit16;
  RESERVED0      :bit16;
 end;

 TCP_RB2_RPTR_ADDR_HI=bitpacked record
  RB_RPTR_ADDR_HI:bit16;
  RESERVED0      :bit16;
 end;

 TCP_WAIT_SEM_ADDR_HI=bitpacked record
  SEM_ADDR_HI    :bit16;
  SEM_USE_MAILBOX:bit1;
  RESERVED0      :bit3;
  SEM_SIGNAL_TYPE:bit1;
  RESERVED1      :bit3;
  SEM_CLIENT_CODE:bit2;
  RESERVED2      :bit3;
  SEM_SELECT     :bit3;
 end;

 TCP_WAIT_SEM_ADDR_LO=bitpacked record
  SEM_ADDR_SWAP:bit2;
  RESERVED0    :bit1;
  SEM_ADDR_LO  :bit29;
 end;

 TCRTC_AVSYNC_COUNTER=bit32;

 TCRTC_OVERSCAN_COLOR=bitpacked record
  CRTC_OVERSCAN_COLOR_BLUE :bit10;
  CRTC_OVERSCAN_COLOR_GREEN:bit10;
  CRTC_OVERSCAN_COLOR_RED  :bit10;
  RESERVED0                :bit2;
 end;

 TCRTC_SNAPSHOT_FRAME=bitpacked record
  CRTC_SNAPSHOT_FRAME_COUNT:bit24;
  RESERVED0                :bit8;
 end;

 TCRTC_STEREO_CONTROL=bitpacked record
  CRTC_STEREO_SYNC_OUTPUT_LINE_NUM     :bit14;
  RESERVED0                            :bit1;
  CRTC_STEREO_SYNC_OUTPUT_POLARITY     :bit1;
  CRTC_STEREO_SYNC_SELECT_POLARITY     :bit1;
  CRTC_STEREO_EYE_FLAG_POLARITY        :bit1;
  CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP:bit1;
  CRTC_DISABLE_FIELD_NUM               :bit1;
  CRTC_DISABLE_V_BLANK_FOR_DP_FIX      :bit1;
  RESERVED1                            :bit3;
  CRTC_STEREO_EN                       :bit1;
  RESERVED2                            :bit7;
 end;

 TCUR2_STEREO_CONTROL=bitpacked record
  CURSOR2_STEREO_EN        :bit1;
  CURSOR2_STEREO_OFFSET_YNX:bit1;
  RESERVED0                :bit2;
  CURSOR2_PRIMARY_OFFSET   :bit10;
  RESERVED1                :bit2;
  CURSOR2_SECONDARY_OFFSET :bit10;
  RESERVED2                :bit6;
 end;

 TCUR_SURFACE_ADDRESS=bit32;

 TDAC_CRC_SIG_CONTROL=bitpacked record
  DAC_CRC_SIG_CONTROL:bit6;
  RESERVED0          :bit26;
 end;

 TDAC_TEST_DEBUG_DATA=bit32;

 TDB_DEPTH_BOUNDS_MAX=bit32;

 TDB_DEPTH_BOUNDS_MIN=bit32;

 TDB_RENDER_OVERRIDE2=bitpacked record
  PARTIAL_SQUAD_LAUNCH_CONTROL       :bit2;
  PARTIAL_SQUAD_LAUNCH_COUNTDOWN     :bit3;
  DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION:bit1;
  DISABLE_SMEM_EXPCLEAR_OPTIMIZATION :bit1;
  DISABLE_COLOR_ON_VALIDATION        :bit1;
  DECOMPRESS_Z_ON_FLUSH              :bit1;
  DISABLE_REG_SNOOP                  :bit1;
  DEPTH_BOUNDS_HIER_DEPTH_DISABLE    :bit1;
  SEPARATE_HIZS_FUNC_ENABLE          :bit1;
  HIZ_ZFUNC                          :bit3;
  HIS_SFUNC_FF                       :bit3;
  HIS_SFUNC_BF                       :bit3;
  PRESERVE_ZRANGE                    :bit1;
  PRESERVE_SRESULTS                  :bit1;
  DISABLE_FAST_PASS                  :bit1;
  RESERVED0                          :bit8;
 end;

 TDCCG_GTC_DTO_MODULO=bit32;

 TDCFEV_CLOCK_CONTROL=bitpacked record
  RESERVED0                     :bit3;
  DISPCLK_R_DCFEV_GATE_DISABLE  :bit1;
  RESERVED1                     :bit3;
  DISPCLK_G_UNP_GATE_DISABLE    :bit1;
  RESERVED2                     :bit1;
  DISPCLK_G_SCLV_GATE_DISABLE   :bit1;
  RESERVED3                     :bit1;
  DISPCLK_G_COL_MAN_GATE_DISABLE:bit1;
  RESERVED4                     :bit1;
  DISPCLK_G_PSCLV_GATE_DISABLE  :bit1;
  RESERVED5                     :bit1;
  DISPCLK_G_CRTC_GATE_DISABLE   :bit1;
  RESERVED6                     :bit8;
  DCFEV_TEST_CLK_SEL            :bit5;
  RESERVED7                     :bit2;
  DCFEV_CLOCK_ENABLE            :bit1;
 end;

 TDCFE_MEM_PWR_STATUS=bitpacked record
  DCP_LUT_MEM_PWR_STATE    :bit2;
  DCP_REGAMMA_MEM_PWR_STATE:bit2;
  SCL_COEFF_MEM_PWR_STATE  :bit2;
  DCP_CURSOR_MEM_PWR_STATE :bit2;
  DCP_CURSOR2_MEM_PWR_STATE:bit2;
  LB0_ALPHA_MEM_PWR_STATE  :bit2;
  LB1_ALPHA_MEM_PWR_STATE  :bit2;
  LB2_ALPHA_MEM_PWR_STATE  :bit2;
  LB0_MEM_PWR_STATE        :bit2;
  LB1_MEM_PWR_STATE        :bit2;
  LB2_MEM_PWR_STATE        :bit2;
  BLND_MEM_PWR_STATE       :bit2;
  OVLSCL_MEM_PWR_STATE     :bit1;
  RESERVED0                :bit7;
 end;

 TDCIO_IMPCAL_CNTL_AB=bitpacked record
  CALR_CNTL_OVERRIDE:bit4;
  RESERVED0         :bit1;
  IMPCAL_SOFT_RESET :bit1;
  RESERVED1         :bit2;
  IMPCAL_STATUS     :bit2;
  RESERVED2         :bit2;
  IMPCAL_ARB_STATE  :bit3;
  RESERVED3         :bit17;
 end;

 TDCIO_IMPCAL_CNTL_CD=bitpacked record
  CALR_CNTL_OVERRIDE:bit4;
  RESERVED0         :bit1;
  IMPCAL_SOFT_RESET :bit1;
  RESERVED1         :bit2;
  IMPCAL_STATUS     :bit2;
  RESERVED2         :bit2;
  IMPCAL_ARB_STATE  :bit3;
  RESERVED3         :bit17;
 end;

 TDCIO_IMPCAL_CNTL_EF=bitpacked record
  CALR_CNTL_OVERRIDE:bit4;
  RESERVED0         :bit1;
  IMPCAL_SOFT_RESET :bit1;
  RESERVED1         :bit2;
  IMPCAL_STATUS     :bit2;
  RESERVED2         :bit2;
  IMPCAL_ARB_STATE  :bit3;
  RESERVED3         :bit17;
 end;

 TDCI_MEM_PWR_STATUS2=bitpacked record
  DMIF1_ASYNC_MEM_PWR_STATE:bit2;
  DMIF1_DATA_MEM_PWR_STATE :bit2;
  DMIF1_CHUNK_MEM_PWR_STATE:bit1;
  DMIF2_ASYNC_MEM_PWR_STATE:bit2;
  DMIF2_DATA_MEM_PWR_STATE :bit2;
  DMIF2_CHUNK_MEM_PWR_STATE:bit1;
  DMIF3_ASYNC_MEM_PWR_STATE:bit2;
  DMIF3_DATA_MEM_PWR_STATE :bit2;
  DMIF3_CHUNK_MEM_PWR_STATE:bit1;
  DMIF4_ASYNC_MEM_PWR_STATE:bit2;
  DMIF4_DATA_MEM_PWR_STATE :bit2;
  DMIF4_CHUNK_MEM_PWR_STATE:bit1;
  DMIF5_ASYNC_MEM_PWR_STATE:bit2;
  DMIF5_DATA_MEM_PWR_STATE :bit2;
  DMIF5_CHUNK_MEM_PWR_STATE:bit1;
  RESERVED0                :bit7;
 end;

 TDCI_PG_DEBUG_CONFIG=bitpacked record
  DCI_PG_DBG_EN:bit1;
  RESERVED0    :bit31;
 end;

 TDCI_TEST_DEBUG_DATA=bit32;

 TDCO_TEST_DEBUG_DATA=bit32;

 TDCP_TEST_DEBUG_DATA=bit32;

 TDC_ABM1_HG_RESULT_1=bit32;

 TDC_ABM1_HG_RESULT_2=bit32;

 TDC_ABM1_HG_RESULT_3=bit32;

 TDC_ABM1_HG_RESULT_4=bit32;

 TDC_ABM1_HG_RESULT_5=bit32;

 TDC_ABM1_HG_RESULT_6=bit32;

 TDC_ABM1_HG_RESULT_7=bit32;

 TDC_ABM1_HG_RESULT_8=bit32;

 TDC_ABM1_HG_RESULT_9=bit32;

 TDC_GPIO_DDCVGA_MASK=bitpacked record
  DC_GPIO_DDCVGACLK_MASK  :bit1;
  RESERVED0               :bit5;
  DC_GPIO_DDCVGACLK_RECV  :bit1;
  RESERVED1               :bit1;
  DC_GPIO_DDCVGADATA_MASK :bit1;
  RESERVED2               :bit3;
  DC_GPIO_DDCVGADATA_PD_EN:bit1;
  RESERVED3               :bit1;
  DC_GPIO_DDCVGADATA_RECV :bit1;
  RESERVED4               :bit1;
  AUX_PADVGA_MODE         :bit1;
  RESERVED5               :bit3;
  AUXVGA_POL              :bit1;
  RESERVED6               :bit1;
  ALLOW_HW_DDCVGA_PD_EN   :bit1;
  RESERVED7               :bit1;
  DC_GPIO_DDCVGACLK_STR   :bit4;
  DC_GPIO_DDCVGADATA_STR  :bit4;
 end;

 TDC_GPIO_I2CPAD_MASK=bitpacked record
  DC_GPIO_SCL_MASK  :bit1;
  DC_GPIO_SCL_PD_DIS:bit1;
  DC_GPIO_SCL_RECV  :bit1;
  RESERVED0         :bit1;
  DC_GPIO_SDA_MASK  :bit1;
  DC_GPIO_SDA_PD_DIS:bit1;
  DC_GPIO_SDA_RECV  :bit1;
  RESERVED1         :bit25;
 end;

 TDC_GPIO_PWRSEQ_MASK=bitpacked record
  DC_GPIO_BLON_MASK      :bit1;
  RESERVED0              :bit3;
  DC_GPIO_BLON_PD_DIS    :bit1;
  RESERVED1              :bit1;
  DC_GPIO_BLON_RECV      :bit1;
  RESERVED2              :bit1;
  DC_GPIO_DIGON_MASK     :bit1;
  RESERVED3              :bit3;
  DC_GPIO_DIGON_PD_DIS   :bit1;
  RESERVED4              :bit1;
  DC_GPIO_DIGON_RECV     :bit1;
  RESERVED5              :bit1;
  DC_GPIO_ENA_BL_MASK    :bit1;
  RESERVED6              :bit3;
  DC_GPIO_ENA_BL_PD_DIS  :bit1;
  RESERVED7              :bit1;
  DC_GPIO_ENA_BL_RECV    :bit1;
  RESERVED8              :bit1;
  DC_GPIO_VSYNC_IN_MASK  :bit1;
  DC_GPIO_VSYNC_IN_PD_DIS:bit1;
  DC_GPIO_VSYNC_IN_RECV  :bit1;
  RESERVED9              :bit1;
  DC_GPIO_HSYNC_IN_MASK  :bit1;
  DC_GPIO_HSYNC_IN_PD_DIS:bit1;
  DC_GPIO_HSYNC_IN_RECV  :bit1;
  RESERVED10             :bit1;
 end;

 TDC_HPD1_INT_CONTROL=bitpacked record
  DC_HPD1_INT_ACK     :bit1;
  RESERVED0           :bit7;
  DC_HPD1_INT_POLARITY:bit1;
  RESERVED1           :bit7;
  DC_HPD1_INT_EN      :bit1;
  RESERVED2           :bit3;
  DC_HPD1_RX_INT_ACK  :bit1;
  RESERVED3           :bit3;
  DC_HPD1_RX_INT_EN   :bit1;
  RESERVED4           :bit7;
 end;

 TDC_HPD2_INT_CONTROL=bitpacked record
  DC_HPD2_INT_ACK     :bit1;
  RESERVED0           :bit7;
  DC_HPD2_INT_POLARITY:bit1;
  RESERVED1           :bit7;
  DC_HPD2_INT_EN      :bit1;
  RESERVED2           :bit3;
  DC_HPD2_RX_INT_ACK  :bit1;
  RESERVED3           :bit3;
  DC_HPD2_RX_INT_EN   :bit1;
  RESERVED4           :bit7;
 end;

 TDC_HPD3_INT_CONTROL=bitpacked record
  DC_HPD3_INT_ACK     :bit1;
  RESERVED0           :bit7;
  DC_HPD3_INT_POLARITY:bit1;
  RESERVED1           :bit7;
  DC_HPD3_INT_EN      :bit1;
  RESERVED2           :bit3;
  DC_HPD3_RX_INT_ACK  :bit1;
  RESERVED3           :bit3;
  DC_HPD3_RX_INT_EN   :bit1;
  RESERVED4           :bit7;
 end;

 TDC_HPD4_INT_CONTROL=bitpacked record
  DC_HPD4_INT_ACK     :bit1;
  RESERVED0           :bit7;
  DC_HPD4_INT_POLARITY:bit1;
  RESERVED1           :bit7;
  DC_HPD4_INT_EN      :bit1;
  RESERVED2           :bit3;
  DC_HPD4_RX_INT_ACK  :bit1;
  RESERVED3           :bit3;
  DC_HPD4_RX_INT_EN   :bit1;
  RESERVED4           :bit7;
 end;

 TDC_HPD5_INT_CONTROL=bitpacked record
  DC_HPD5_INT_ACK     :bit1;
  RESERVED0           :bit7;
  DC_HPD5_INT_POLARITY:bit1;
  RESERVED1           :bit7;
  DC_HPD5_INT_EN      :bit1;
  RESERVED2           :bit3;
  DC_HPD5_RX_INT_ACK  :bit1;
  RESERVED3           :bit3;
  DC_HPD5_RX_INT_EN   :bit1;
  RESERVED4           :bit7;
 end;

 TDC_HPD6_INT_CONTROL=bitpacked record
  DC_HPD6_INT_ACK     :bit1;
  RESERVED0           :bit7;
  DC_HPD6_INT_POLARITY:bit1;
  RESERVED1           :bit7;
  DC_HPD6_INT_EN      :bit1;
  RESERVED2           :bit3;
  DC_HPD6_RX_INT_ACK  :bit1;
  RESERVED3           :bit3;
  DC_HPD6_RX_INT_EN   :bit1;
  RESERVED4           :bit7;
 end;

 TDC_I2C_DDCVGA_SETUP=bitpacked record
  DC_I2C_DDCVGA_DATA_DRIVE_EN          :bit1;
  DC_I2C_DDCVGA_DATA_DRIVE_SEL         :bit1;
  RESERVED0                            :bit2;
  DC_I2C_DDCVGA_EDID_DETECT_ENABLE     :bit1;
  DC_I2C_DDCVGA_EDID_DETECT_MODE       :bit1;
  DC_I2C_DDCVGA_ENABLE                 :bit1;
  DC_I2C_DDCVGA_CLK_DRIVE_EN           :bit1;
  DC_I2C_DDCVGA_INTRA_BYTE_DELAY       :bit8;
  DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY:bit8;
  DC_I2C_DDCVGA_TIME_LIMIT             :bit8;
 end;

 TDC_I2C_DDCVGA_SPEED=bitpacked record
  DC_I2C_DDCVGA_THRESHOLD                  :bit2;
  RESERVED0                                :bit2;
  DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL:bit1;
  RESERVED1                                :bit11;
  DC_I2C_DDCVGA_PRESCALE                   :bit16;
 end;

 TDC_I2C_TRANSACTION0=bitpacked record
  DC_I2C_RW0          :bit1;
  RESERVED0           :bit7;
  DC_I2C_STOP_ON_NACK0:bit1;
  RESERVED1           :bit3;
  DC_I2C_START0       :bit1;
  DC_I2C_STOP0        :bit1;
  RESERVED2           :bit2;
  DC_I2C_COUNT0       :bit8;
  RESERVED3           :bit8;
 end;

 TDC_I2C_TRANSACTION1=bitpacked record
  DC_I2C_RW1          :bit1;
  RESERVED0           :bit7;
  DC_I2C_STOP_ON_NACK1:bit1;
  RESERVED1           :bit3;
  DC_I2C_START1       :bit1;
  DC_I2C_STOP1        :bit1;
  RESERVED2           :bit2;
  DC_I2C_COUNT1       :bit8;
  RESERVED3           :bit8;
 end;

 TDC_I2C_TRANSACTION2=bitpacked record
  DC_I2C_RW2          :bit1;
  RESERVED0           :bit7;
  DC_I2C_STOP_ON_NACK2:bit1;
  RESERVED1           :bit3;
  DC_I2C_START2       :bit1;
  DC_I2C_STOP2        :bit1;
  RESERVED2           :bit2;
  DC_I2C_COUNT2       :bit8;
  RESERVED3           :bit8;
 end;

 TDC_I2C_TRANSACTION3=bitpacked record
  DC_I2C_RW3          :bit1;
  RESERVED0           :bit7;
  DC_I2C_STOP_ON_NACK3:bit1;
  RESERVED1           :bit3;
  DC_I2C_START3       :bit1;
  DC_I2C_STOP3        :bit1;
  RESERVED2           :bit2;
  DC_I2C_COUNT3       :bit8;
  RESERVED3           :bit8;
 end;

 TDC_PGFSM_CONFIG_REG=bit32;

 TDC_TEST_DEBUG_INDEX=bitpacked record
  DC_TEST_DEBUG_INDEX   :bit8;
  DC_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0             :bit23;
 end;

 TDIDT_DBR_WEIGHT8_11=bitpacked record
  WEIGHT8 :bit8;
  WEIGHT9 :bit8;
  WEIGHT10:bit8;
  WEIGHT11:bit8;
 end;

 TDIDT_TCP_WEIGHT8_11=bitpacked record
  WEIGHT8 :bit8;
  WEIGHT9 :bit8;
  WEIGHT10:bit8;
  WEIGHT11:bit8;
 end;

 TDIG_OUTPUT_CRC_CNTL=bitpacked record
  DIG_OUTPUT_CRC_EN      :bit1;
  RESERVED0              :bit3;
  DIG_OUTPUT_CRC_LINK_SEL:bit1;
  RESERVED1              :bit3;
  DIG_OUTPUT_CRC_DATA_SEL:bit2;
  RESERVED2              :bit22;
 end;

 TDIG_TEST_DEBUG_DATA=bit32;

 TDPG_TEST_DEBUG_DATA=bit32;

 TDP_HBR2_EYE_PATTERN=bitpacked record
  DP_HBR2_EYE_PATTERN_ENABLE:bit1;
  RESERVED0                 :bit31;
 end;

 TDP_TEST_DEBUG_INDEX=bitpacked record
  DP_TEST_DEBUG_INDEX   :bit8;
  DP_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0             :bit23;
 end;

 TDVO_CRC2_SIG_RESULT=bitpacked record
  DVO_CRC2_SIG_RESULT:bit27;
  RESERVED0          :bit5;
 end;

 TDVO_TEST_DEBUG_DATA=bit32;

 TFBC_DEBUG_CSR_RDATA=bit32;

 TFBC_DEBUG_CSR_WDATA=bit32;

 TFBC_TEST_DEBUG_DATA=bit32;

 TFMT_TEST_DEBUG_DATA=bit32;

 TGAMMA_CORR_LUT_DATA=bitpacked record
  GAMMA_CORR_LUT_DATA:bit19;
  RESERVED0          :bit13;
 end;

 TGAMUT_REMAP_C11_C12=bitpacked record
  GAMUT_REMAP_C11:bit16;
  GAMUT_REMAP_C12:bit16;
 end;

 TGAMUT_REMAP_C13_C14=bitpacked record
  GAMUT_REMAP_C13:bit16;
  GAMUT_REMAP_C14:bit16;
 end;

 TGAMUT_REMAP_C21_C22=bitpacked record
  GAMUT_REMAP_C21:bit16;
  GAMUT_REMAP_C22:bit16;
 end;

 TGAMUT_REMAP_C23_C24=bitpacked record
  GAMUT_REMAP_C23:bit16;
  GAMUT_REMAP_C24:bit16;
 end;

 TGAMUT_REMAP_C31_C32=bitpacked record
  GAMUT_REMAP_C31:bit16;
  GAMUT_REMAP_C32:bit16;
 end;

 TGAMUT_REMAP_C33_C34=bitpacked record
  GAMUT_REMAP_C33:bit16;
  GAMUT_REMAP_C34:bit16;
 end;

 TGAMUT_REMAP_CONTROL=bitpacked record
  GRPH_GAMUT_REMAP_MODE:bit2;
  RESERVED0            :bit2;
  OVL_GAMUT_REMAP_MODE :bit2;
  RESERVED1            :bit26;
 end;

 TGB_MACROTILE_MODE10=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE11=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE12=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE13=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE14=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGB_MACROTILE_MODE15=bitpacked record
  BANK_WIDTH       :bit2;
  BANK_HEIGHT      :bit2;
  MACRO_TILE_ASPECT:bit2;
  NUM_BANKS        :bit2;
  RESERVED0        :bit24;
 end;

 TGCK_DFS_BYPASS_CNTL=bitpacked record
  BYPASSECLK        :bit1;
  BYPASSLCLK        :bit1;
  BYPASSEVCLK       :bit1;
  BYPASSDCLK        :bit1;
  BYPASSVCLK        :bit1;
  BYPASSDISPCLK     :bit1;
  BYPASSDPREFCLK    :bit1;
  BYPASSACLK        :bit1;
  BYPASSADIVCLK     :bit1;
  BYPASSPSPCLK      :bit1;
  BYPASSSAMCLK      :bit1;
  BYPASSSCLK        :bit1;
  USE_SPLL_BYPASS_EN:bit1;
  BYPASSMCLK        :bit1;
  RESERVED0         :bit18;
 end;

 TGCK_PLL_TEST_CNTL_2=bitpacked record
  RESERVED0 :bit17;
  TEST_COUNT:bit15;
 end;

 TGC_USER_PRIM_CONFIG=bitpacked record
  RESERVED0      :bit16;
  INACTIVE_IA    :bit2;
  RESERVED1      :bit6;
  INACTIVE_VGT_PA:bit4;
  RESERVED2      :bit4;
 end;

 TGDS_CS_CTXSW_STATUS=bitpacked record
  R     :bit1;
  W     :bit1;
  UNUSED:bit30;
 end;

 TGDS_GRBM_SECDED_CNT=bitpacked record
  SEC:bit16;
  DED:bit16;
 end;

 TGDS_OA_CGPG_RESTORE=bitpacked record
  VMID   :bit8;
  MEID   :bit4;
  PIPEID :bit4;
  QUEUEID:bit4;
  UNUSED :bit12;
 end;

 TGDS_PERFCOUNTER0_HI=bit32;

 TGDS_PERFCOUNTER0_LO=bit32;

 TGDS_PERFCOUNTER1_HI=bit32;

 TGDS_PERFCOUNTER1_LO=bit32;

 TGDS_PERFCOUNTER2_HI=bit32;

 TGDS_PERFCOUNTER2_LO=bit32;

 TGDS_PERFCOUNTER3_HI=bit32;

 TGDS_PERFCOUNTER3_LO=bit32;

 TGENERIC_I2C_CONTROL=bitpacked record
  GENERIC_I2C_GO         :bit1;
  GENERIC_I2C_SOFT_RESET :bit1;
  GENERIC_I2C_SEND_RESET :bit1;
  GENERIC_I2C_ENABLE     :bit1;
  RESERVED0              :bit27;
  GENERIC_I2C_DBG_REF_SEL:bit1;
 end;

 TGLOBAL_CAPABILITIES=bitpacked record
  SIXTY_FOUR_BIT_ADDRESS_SUPPORTED         :bit1;
  NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS     :bit2;
  NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED:bit5;
  NUMBER_OF_INPUT_STREAMS_SUPPORTED        :bit4;
  NUMBER_OF_OUTPUT_STREAMS_SUPPORTED       :bit4;
  RESERVED0                                :bit16;
 end;

 TGMCON_RENG_RAM_DATA=bit32;

 TGPIOPAD_INT_STAT_AK=bitpacked record
  GPIO_INT_STAT_AK_0      :bit1;
  GPIO_INT_STAT_AK_1      :bit1;
  GPIO_INT_STAT_AK_2      :bit1;
  GPIO_INT_STAT_AK_3      :bit1;
  GPIO_INT_STAT_AK_4      :bit1;
  GPIO_INT_STAT_AK_5      :bit1;
  GPIO_INT_STAT_AK_6      :bit1;
  GPIO_INT_STAT_AK_7      :bit1;
  GPIO_INT_STAT_AK_8      :bit1;
  GPIO_INT_STAT_AK_9      :bit1;
  GPIO_INT_STAT_AK_10     :bit1;
  GPIO_INT_STAT_AK_11     :bit1;
  GPIO_INT_STAT_AK_12     :bit1;
  GPIO_INT_STAT_AK_13     :bit1;
  GPIO_INT_STAT_AK_14     :bit1;
  GPIO_INT_STAT_AK_15     :bit1;
  GPIO_INT_STAT_AK_16     :bit1;
  GPIO_INT_STAT_AK_17     :bit1;
  GPIO_INT_STAT_AK_18     :bit1;
  GPIO_INT_STAT_AK_19     :bit1;
  GPIO_INT_STAT_AK_20     :bit1;
  GPIO_INT_STAT_AK_21     :bit1;
  GPIO_INT_STAT_AK_22     :bit1;
  GPIO_INT_STAT_AK_23     :bit1;
  GPIO_INT_STAT_AK_24     :bit1;
  GPIO_INT_STAT_AK_25     :bit1;
  GPIO_INT_STAT_AK_26     :bit1;
  GPIO_INT_STAT_AK_27     :bit1;
  GPIO_INT_STAT_AK_28     :bit1;
  RESERVED0               :bit2;
  SW_INITIATED_INT_STAT_AK:bit1;
 end;

 TGPIOPAD_INT_STAT_EN=bitpacked record
  GPIO_INT_STAT_EN        :bit29;
  RESERVED0               :bit2;
  SW_INITIATED_INT_STAT_EN:bit1;
 end;

 TGPIOPAD_SW_INT_STAT=bitpacked record
  SW_INT_STAT:bit1;
  RESERVED0  :bit31;
 end;

 TGRBM_DEBUG_SNAPSHOT=bitpacked record
  CPF_RDY             :bit1;
  CPG_RDY             :bit1;
  SRBM_RDY            :bit1;
  WD_ME0PIPE0_RDY     :bit1;
  WD_ME0PIPE1_RDY     :bit1;
  GDS_RDY             :bit1;
  SE0SPI_ME0PIPE0_RDY0:bit1;
  SE0SPI_ME0PIPE1_RDY0:bit1;
  SE1SPI_ME0PIPE0_RDY0:bit1;
  SE1SPI_ME0PIPE1_RDY0:bit1;
  SE2SPI_ME0PIPE0_RDY0:bit1;
  SE2SPI_ME0PIPE1_RDY0:bit1;
  SE3SPI_ME0PIPE0_RDY0:bit1;
  SE3SPI_ME0PIPE1_RDY0:bit1;
  SE0SPI_ME0PIPE0_RDY1:bit1;
  SE0SPI_ME0PIPE1_RDY1:bit1;
  SE1SPI_ME0PIPE0_RDY1:bit1;
  SE1SPI_ME0PIPE1_RDY1:bit1;
  SE2SPI_ME0PIPE0_RDY1:bit1;
  SE2SPI_ME0PIPE1_RDY1:bit1;
  SE3SPI_ME0PIPE0_RDY1:bit1;
  SE3SPI_ME0PIPE1_RDY1:bit1;
  RESERVED0           :bit10;
 end;

 TGRBM_GFX_CLKEN_CNTL=bitpacked record
  PREFIX_DELAY_CNT:bit4;
  RESERVED0       :bit4;
  POST_DELAY_CNT  :bit5;
  RESERVED1       :bit19;
 end;

 TGRPH_COMPRESS_PITCH=bitpacked record
  RESERVED0          :bit6;
  GRPH_COMPRESS_PITCH:bit11;
  RESERVED1          :bit15;
 end;

 TGRPH_FLIP_RATE_CNTL=bitpacked record
  GRPH_FLIP_RATE       :bit3;
  GRPH_FLIP_RATE_ENABLE:bit1;
  RESERVED0            :bit28;
 end;

 THDP_NONSURFACE_BASE=bitpacked record
  NONSURF_BASE:bit28;
  RESERVED0   :bit4;
 end;

 THDP_NONSURFACE_INFO=bitpacked record
  NONSURF_ADDR_TYPE         :bit1;
  NONSURF_ARRAY_MODE        :bit4;
  NONSURF_ENDIAN            :bit2;
  NONSURF_PIXEL_SIZE        :bit3;
  NONSURF_SAMPLE_NUM        :bit3;
  NONSURF_SAMPLE_SIZE       :bit2;
  NONSURF_PRIV              :bit1;
  NONSURF_TILE_COMPACT      :bit1;
  NONSURF_TILE_SPLIT        :bit3;
  NONSURF_NUM_BANKS         :bit2;
  NONSURF_BANK_WIDTH        :bit2;
  NONSURF_BANK_HEIGHT       :bit2;
  NONSURF_MACRO_TILE_ASPECT :bit2;
  NONSURF_MICRO_TILE_MODE   :bit3;
  NONSURF_SLICE_TILE_MAX_MSB:bit1;
 end;

 THDP_NONSURFACE_SIZE=bitpacked record
  NONSURF_PITCH_TILE_MAX:bit10;
  NONSURF_SLICE_TILE_MAX:bit20;
  RESERVED0             :bit2;
 end;

 THDP_OUTSTANDING_REQ=bitpacked record
  WRITE_REQ:bit8;
  READ_REQ :bit8;
  RESERVED0:bit16;
 end;

 THDP_XDP_D2H_RSVD_10=bit32;

 THDP_XDP_D2H_RSVD_11=bit32;

 THDP_XDP_D2H_RSVD_12=bit32;

 THDP_XDP_D2H_RSVD_13=bit32;

 THDP_XDP_D2H_RSVD_14=bit32;

 THDP_XDP_D2H_RSVD_15=bit32;

 THDP_XDP_D2H_RSVD_16=bit32;

 THDP_XDP_D2H_RSVD_17=bit32;

 THDP_XDP_D2H_RSVD_18=bit32;

 THDP_XDP_D2H_RSVD_19=bit32;

 THDP_XDP_D2H_RSVD_20=bit32;

 THDP_XDP_D2H_RSVD_21=bit32;

 THDP_XDP_D2H_RSVD_22=bit32;

 THDP_XDP_D2H_RSVD_23=bit32;

 THDP_XDP_D2H_RSVD_24=bit32;

 THDP_XDP_D2H_RSVD_25=bit32;

 THDP_XDP_D2H_RSVD_26=bit32;

 THDP_XDP_D2H_RSVD_27=bit32;

 THDP_XDP_D2H_RSVD_28=bit32;

 THDP_XDP_D2H_RSVD_29=bit32;

 THDP_XDP_D2H_RSVD_30=bit32;

 THDP_XDP_D2H_RSVD_31=bit32;

 THDP_XDP_D2H_RSVD_32=bit32;

 THDP_XDP_D2H_RSVD_33=bit32;

 THDP_XDP_D2H_RSVD_34=bit32;

 THDP_XDP_HDP_IPH_CFG=bitpacked record
  HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE  :bit6;
  HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE  :bit6;
  HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING:bit1;
  HDP_IPH_CFG_P2P_RD_EN                :bit1;
  RESERVED0                            :bit18;
 end;

 THDP_XDP_P2P_BAR_CFG=bitpacked record
  P2P_BAR_CFG_ADDR_SIZE:bit4;
  P2P_BAR_CFG_BAR_FROM :bit2;
  RESERVED0            :bit26;
 end;

 TIH_VF_RB_BIF_STATUS=bitpacked record
  RB_FULL_VF           :bit16;
  BIF_INTERRUPT_LINE_VF:bit16;
 end;

 TINPUT_CSC_C11_C12_A=bitpacked record
  INPUT_CSC_C11_A:bit16;
  INPUT_CSC_C12_A:bit16;
 end;

 TINPUT_CSC_C11_C12_B=bitpacked record
  INPUT_CSC_C11_B:bit16;
  INPUT_CSC_C12_B:bit16;
 end;

 TINPUT_CSC_C13_C14_A=bitpacked record
  INPUT_CSC_C13_A:bit16;
  INPUT_CSC_C14_A:bit16;
 end;

 TINPUT_CSC_C13_C14_B=bitpacked record
  INPUT_CSC_C13_B:bit16;
  INPUT_CSC_C14_B:bit16;
 end;

 TINPUT_CSC_C21_C22_A=bitpacked record
  INPUT_CSC_C21_A:bit16;
  INPUT_CSC_C22_A:bit16;
 end;

 TINPUT_CSC_C21_C22_B=bitpacked record
  INPUT_CSC_C21_B:bit16;
  INPUT_CSC_C22_B:bit16;
 end;

 TINPUT_CSC_C23_C24_A=bitpacked record
  INPUT_CSC_C23_A:bit16;
  INPUT_CSC_C24_A:bit16;
 end;

 TINPUT_CSC_C23_C24_B=bitpacked record
  INPUT_CSC_C23_B:bit16;
  INPUT_CSC_C24_B:bit16;
 end;

 TINPUT_CSC_C31_C32_A=bitpacked record
  INPUT_CSC_C31_A:bit16;
  INPUT_CSC_C32_A:bit16;
 end;

 TINPUT_CSC_C31_C32_B=bitpacked record
  INPUT_CSC_C31_B:bit16;
  INPUT_CSC_C32_B:bit16;
 end;

 TINPUT_CSC_C33_C34_A=bitpacked record
  INPUT_CSC_C33_A:bit16;
  INPUT_CSC_C34_A:bit16;
 end;

 TINPUT_CSC_C33_C34_B=bitpacked record
  INPUT_CSC_C33_B:bit16;
  INPUT_CSC_C34_B:bit16;
 end;

 TINPUT_GAMMA_CONTROL=bitpacked record
  GRPH_INPUT_GAMMA_MODE:bit2;
  RESERVED0            :bit2;
  OVL_INPUT_GAMMA_MODE :bit2;
  RESERVED1            :bit26;
 end;

 TLBV_BLACK_KEYER_G_Y=bitpacked record
  RESERVED0         :bit4;
  LB_BLACK_KEYER_G_Y:bit12;
  RESERVED1         :bit16;
 end;

 TLBV_KEYER_COLOR_G_Y=bitpacked record
  RESERVED0         :bit4;
  LB_KEYER_COLOR_G_Y:bit12;
  RESERVED1         :bit16;
 end;

 TLBV_TEST_DEBUG_DATA=bit32;

 TLBV_VLINE_START_END=bitpacked record
  VLINE_START:bit14;
  RESERVED0  :bit2;
  VLINE_END  :bit15;
  VLINE_INV  :bit1;
 end;

 TLB_BLACK_KEYER_B_CB=bitpacked record
  RESERVED0          :bit4;
  LB_BLACK_KEYER_B_CB:bit12;
  RESERVED1          :bit16;
 end;

 TLB_BLACK_KEYER_R_CR=bitpacked record
  RESERVED0          :bit4;
  LB_BLACK_KEYER_R_CR:bit12;
  RESERVED1          :bit16;
 end;

 TLB_KEYER_COLOR_B_CB=bitpacked record
  RESERVED0          :bit4;
  LB_KEYER_COLOR_B_CB:bit12;
  RESERVED1          :bit16;
 end;

 TLB_KEYER_COLOR_CTRL=bitpacked record
  LB_KEYER_COLOR_EN    :bit1;
  RESERVED0            :bit7;
  LB_KEYER_COLOR_REP_EN:bit1;
  RESERVED1            :bit23;
 end;

 TLB_KEYER_COLOR_R_CR=bitpacked record
  RESERVED0          :bit4;
  LB_KEYER_COLOR_R_CR:bit12;
  RESERVED1          :bit16;
 end;

 TLB_TEST_DEBUG_INDEX=bitpacked record
  LB_TEST_DEBUG_INDEX   :bit8;
  LB_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0             :bit23;
 end;

 TLB_VLINE2_START_END=bitpacked record
  VLINE2_START:bit14;
  RESERVED0   :bit2;
  VLINE2_END  :bit15;
  VLINE2_INV  :bit1;
 end;

 TLVTMA_PWRSEQ_DELAY1=bitpacked record
  LVTMA_PWRUP_DELAY1:bit8;
  LVTMA_PWRUP_DELAY2:bit8;
  LVTMA_PWRDN_DELAY1:bit8;
  LVTMA_PWRDN_DELAY2:bit8;
 end;

 TLVTMA_PWRSEQ_DELAY2=bitpacked record
  LVTMA_PWRDN_MIN_LENGTH   :bit8;
  LVTMA_PWRUP_DELAY3       :bit8;
  LVTMA_PWRDN_DELAY3       :bit8;
  LVTMA_VARY_BL_OVERRIDE_EN:bit1;
  RESERVED0                :bit7;
 end;

 TMASTER_COMM_CMD_REG=bitpacked record
  MASTER_COMM_CMD_REG_BYTE0:bit8;
  MASTER_COMM_CMD_REG_BYTE1:bit8;
  MASTER_COMM_CMD_REG_BYTE2:bit8;
  MASTER_COMM_CMD_REG_BYTE3:bit8;
 end;

 TMC_ARB_DRAM_TIMING2=bitpacked record
  RAS2RAS  :bit8;
  RP       :bit8;
  WRPLUSRP :bit8;
  BUS_TURN :bit5;
  RESERVED0:bit3;
 end;

 TMC_ARB_GDEC_RD_CNTL=bitpacked record
  PAGEBIT0       :bit4;
  PAGEBIT1       :bit4;
  USE_RANK       :bit1;
  USE_RSNO       :bit1;
  REM_DEFAULT_GRP:bit4;
  RESERVED0      :bit18;
 end;

 TMC_ARB_GDEC_WR_CNTL=bitpacked record
  PAGEBIT0       :bit4;
  PAGEBIT1       :bit4;
  USE_RANK       :bit1;
  USE_RSNO       :bit1;
  REM_DEFAULT_GRP:bit4;
  RESERVED0      :bit18;
 end;

 TMC_ARB_GECC2_DEBUG2=bitpacked record
  PERIOD    :bit8;
  ERR0_START:bit8;
  ERR1_START:bit8;
  ERR2_START:bit8;
 end;

 TMC_ARB_GECC2_STATUS=bitpacked record
  CORR_STS0          :bit1;
  UNCORR_STS0        :bit1;
  FED_STS0           :bit1;
  RSVD0              :bit1;
  CORR_STS1          :bit1;
  UNCORR_STS1        :bit1;
  FED_STS1           :bit1;
  RSVD1              :bit1;
  CORR_CLEAR0        :bit1;
  UNCORR_CLEAR0      :bit1;
  FED_CLEAR0         :bit1;
  RSVD2              :bit1;
  CORR_CLEAR1        :bit1;
  UNCORR_CLEAR1      :bit1;
  FED_CLEAR1         :bit1;
  RSVD3              :bit1;
  RMWRD_CORR_STS0    :bit1;
  RMWRD_UNCORR_STS0  :bit1;
  RSVD4              :bit2;
  RMWRD_CORR_STS1    :bit1;
  RMWRD_UNCORR_STS1  :bit1;
  RSVD5              :bit2;
  RMWRD_CORR_CLEAR0  :bit1;
  RMWRD_UNCORR_CLEAR0:bit1;
  RSVD6              :bit2;
  RMWRD_CORR_CLEAR1  :bit1;
  RMWRD_UNCORR_CLEAR1:bit1;
  RESERVED0          :bit2;
 end;

 TMC_ARB_GRUB_PROMOTE=bitpacked record
  URGENT_RD :bit8;
  URGENT_WR :bit8;
  PROMOTE_RD:bit8;
  PROMOTE_WR:bit8;
 end;

 TMC_ARB_HARSH_CTL_RD=bitpacked record
  FORCE_HIGHEST   :bit8;
  HARSH_RR        :bit1;
  BANK_AGE_ONLY   :bit1;
  USE_LEGACY_HARSH:bit1;
  BWCNT_CATCHUP   :bit1;
  ST_MODE         :bit2;
  FORCE_STALL     :bit8;
  PERF_MON_SEL    :bit3;
  RESERVED0       :bit7;
 end;

 TMC_ARB_HARSH_CTL_WR=bitpacked record
  FORCE_HIGHEST   :bit8;
  HARSH_RR        :bit1;
  BANK_AGE_ONLY   :bit1;
  USE_LEGACY_HARSH:bit1;
  BWCNT_CATCHUP   :bit1;
  ST_MODE         :bit2;
  FORCE_STALL     :bit8;
  PERF_MON_SEL    :bit3;
  RESERVED0       :bit7;
 end;

 TMC_ARB_RET_CREDITS2=bitpacked record
  ACP_WR                  :bit8;
  NECKDOWN_CNTR_EN_RD     :bit1;
  NECKDOWN_CNTR_EN_WR     :bit1;
  ACP_RDRET_URG           :bit1;
  HDP_RDRET_URG           :bit1;
  NECKDOWN_CNTR_MONITOR_RD:bit1;
  NECKDOWN_CNTR_MONITOR_WR:bit1;
  DISABLE_DISP_RDY_RD     :bit1;
  DISABLE_ACP_RDY_WR      :bit1;
  RDRET_CREDIT_MED        :bit8;
  RESERVED0               :bit8;
 end;

 TMC_ARB_WTM_GRPWT_RD=bitpacked record
  GRP0     :bit2;
  GRP1     :bit2;
  GRP2     :bit2;
  GRP3     :bit2;
  GRP4     :bit2;
  GRP5     :bit2;
  GRP6     :bit2;
  GRP7     :bit2;
  GRP_EXT  :bit8;
  RESERVED0:bit8;
 end;

 TMC_ARB_WTM_GRPWT_WR=bitpacked record
  GRP0     :bit2;
  GRP1     :bit2;
  GRP2     :bit2;
  GRP3     :bit2;
  GRP4     :bit2;
  GRP5     :bit2;
  GRP6     :bit2;
  GRP7     :bit2;
  GRP_EXT  :bit8;
  RESERVED0:bit8;
 end;

 TMC_BIST_RDATA_WORD0=bit32;

 TMC_BIST_RDATA_WORD1=bit32;

 TMC_BIST_RDATA_WORD2=bit32;

 TMC_BIST_RDATA_WORD3=bit32;

 TMC_BIST_RDATA_WORD4=bit32;

 TMC_BIST_RDATA_WORD5=bit32;

 TMC_BIST_RDATA_WORD6=bit32;

 TMC_BIST_RDATA_WORD7=bit32;

 TMC_CITF_INT_CREDITS=bitpacked record
  REMRDRET      :bit6;
  RESERVED0     :bit6;
  CNTR_RD_HUB_LP:bit6;
  CNTR_RD_HUB_HP:bit6;
  CNTR_RD_LCL   :bit6;
  RESERVED1     :bit2;
 end;

 TMC_CITF_WTM_RD_CNTL=bitpacked record
  GROUP0_DECREMENT:bit3;
  GROUP1_DECREMENT:bit3;
  GROUP2_DECREMENT:bit3;
  GROUP3_DECREMENT:bit3;
  GROUP4_DECREMENT:bit3;
  GROUP5_DECREMENT:bit3;
  GROUP6_DECREMENT:bit3;
  GROUP7_DECREMENT:bit3;
  DISABLE_REMOTE  :bit1;
  DISABLE_LOCAL   :bit1;
  RESERVED0       :bit6;
 end;

 TMC_CITF_WTM_WR_CNTL=bitpacked record
  GROUP0_DECREMENT:bit3;
  GROUP1_DECREMENT:bit3;
  GROUP2_DECREMENT:bit3;
  GROUP3_DECREMENT:bit3;
  GROUP4_DECREMENT:bit3;
  GROUP5_DECREMENT:bit3;
  GROUP6_DECREMENT:bit3;
  GROUP7_DECREMENT:bit3;
  DISABLE_REMOTE  :bit1;
  DISABLE_LOCAL   :bit1;
  RESERVED0       :bit6;
 end;

 TMC_CITF_XTRA_ENABLE=bitpacked record
  CB1_RD             :bit1;
  CB1_WR             :bit1;
  DB1_RD             :bit1;
  DB1_WR             :bit1;
  TC2_RD             :bit1;
  RESERVED0          :bit1;
  RESERVED1          :bit1;
  RESERVED2          :bit1;
  ARB_DBG            :bit4;
  TC2_WR             :bit1;
  CB0_CONNECT_CNTL   :bit2;
  DB0_CONNECT_CNTL   :bit2;
  CB1_CONNECT_CNTL   :bit2;
  DB1_CONNECT_CNTL   :bit2;
  TC0_CONNECT_CNTL   :bit2;
  TC1_CONNECT_CNTL   :bit2;
  CB0_CID_CNTL_ENABLE:bit1;
  DB0_CID_CNTL_ENABLE:bit1;
  CB1_CID_CNTL_ENABLE:bit1;
  DB1_CID_CNTL_ENABLE:bit1;
  TC2_REPAIR_ENABLE  :bit2;
  RESERVED3          :bit1;
 end;

 TMC_GRUB_TCB_DATA_HI=bit32;

 TMC_GRUB_TCB_DATA_LO=bit32;

 TMC_HUB_MISC_FRAMING=bit32;

 TMC_HUB_RDREQ_SAMMSP=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  RESERVED0            :bit15;
 end;

 TMC_HUB_RDREQ_STATUS=bitpacked record
  SIP_AVAIL            :bit1;
  MCDW_RD_AVAIL        :bit1;
  MCDX_RD_AVAIL        :bit1;
  MCDY_RD_AVAIL        :bit1;
  MCDZ_RD_AVAIL        :bit1;
  MCDS_RD_AVAIL        :bit1;
  MCDT_RD_AVAIL        :bit1;
  MCDU_RD_AVAIL        :bit1;
  MCDV_RD_AVAIL        :bit1;
  GBL0_VM_FULL         :bit1;
  GBL0_STOR_FULL       :bit1;
  GBL0_BYPASS_STOR_FULL:bit1;
  GBL1_VM_FULL         :bit1;
  GBL1_STOR_FULL       :bit1;
  GBL1_BYPASS_STOR_FULL:bit1;
  PWRXPRESS_ERR        :bit1;
  RESERVED0            :bit16;
 end;

 TMC_HUB_WDP_CREDITS2=bitpacked record
  STOR0_PRI:bit8;
  STOR1_PRI:bit8;
  VM2      :bit8;
  VM3      :bit8;
 end;

 TMC_HUB_WDP_CREDITS3=bitpacked record
  STOR0_URG:bit8;
  STOR1_URG:bit8;
  RESERVED0:bit16;
 end;

 TMC_HUB_WDP_ISP_CCPU=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_HUB_WDP_WTM_CNTL=bitpacked record
  GROUP0_DECREMENT:bit3;
  GROUP1_DECREMENT:bit3;
  GROUP2_DECREMENT:bit3;
  GROUP3_DECREMENT:bit3;
  GROUP4_DECREMENT:bit3;
  GROUP5_DECREMENT:bit3;
  GROUP6_DECREMENT:bit3;
  GROUP7_DECREMENT:bit3;
  RESERVED0       :bit8;
 end;

 TMC_HUB_WRRET_STATUS=bitpacked record
  MCDW_AVAIL:bit1;
  MCDX_AVAIL:bit1;
  MCDY_AVAIL:bit1;
  MCDZ_AVAIL:bit1;
  MCDS_AVAIL:bit1;
  MCDT_AVAIL:bit1;
  MCDU_AVAIL:bit1;
  MCDV_AVAIL:bit1;
  RESERVED0 :bit24;
 end;

 TMC_RPB_CID_QUEUE_EX=bitpacked record
  START    :bit1;
  OFFSET   :bit5;
  RESERVED0:bit26;
 end;

 TMC_RPB_CID_QUEUE_RD=bitpacked record
  CLIENT_ID  :bit8;
  WRITE_QUEUE:bit2;
  READ_QUEUE :bit2;
  RESERVED0  :bit20;
 end;

 TMC_RPB_CID_QUEUE_WR=bitpacked record
  CLIENT_ID  :bit8;
  UPDATE_MODE:bit1;
  WRITE_QUEUE:bit2;
  READ_QUEUE :bit2;
  UPDATE     :bit1;
  RESERVED0  :bit18;
 end;

 TMC_SEQ_MISC_TIMING2=bitpacked record
  PA2RDATA :bit3;
  PA2WDATA :bit3;
  FAW      :bit5;
  RESERVED0:bit3;
  RESERVED1:bit3;
  T32AW    :bit4;
  TWDATATR :bit4;
  RESERVED2:bit7;
 end;

 TMC_SEQ_RD_CTL_D0_LP=bitpacked record
  RCV_DLY  :bit3;
  RCV_EXT  :bit5;
  RST_SEL  :bit2;
  RST_HLD  :bit4;
  RESERVED0:bit1;
  RESERVED1:bit1;
  RBS_DLY  :bit5;
  RESERVED2:bit2;
  RESERVED3:bit1;
  RESERVED4:bit8;
 end;

 TMC_SEQ_RD_CTL_D1_LP=bitpacked record
  RCV_DLY  :bit3;
  RCV_EXT  :bit5;
  RST_SEL  :bit2;
  RST_HLD  :bit4;
  RESERVED0:bit1;
  RESERVED1:bit1;
  RBS_DLY  :bit5;
  RESERVED2:bit2;
  RESERVED3:bit1;
  RESERVED4:bit8;
 end;

 TMC_SEQ_SUP_DEC_STAT=bit32;

 TMC_SEQ_SUP_GP0_STAT=bit32;

 TMC_SEQ_SUP_GP1_STAT=bit32;

 TMC_SEQ_SUP_GP2_STAT=bit32;

 TMC_SEQ_SUP_GP3_STAT=bit32;

 TMC_SEQ_SUP_PGM_STAT=bit32;

 TMC_SEQ_WR_CTL_D0_LP=bitpacked record
  DAT_DLY  :bit5;
  DQS_DLY  :bit5;
  DQS_XTR  :bit1;
  OEN_DLY  :bit5;
  OEN_EXT  :bit4;
  OEN_SEL  :bit2;
  CMD_DLY  :bit1;
  ADR_DLY  :bit1;
  RESERVED0:bit8;
 end;

 TMC_SEQ_WR_CTL_D1_LP=bitpacked record
  DAT_DLY  :bit5;
  DQS_DLY  :bit5;
  DQS_XTR  :bit1;
  OEN_DLY  :bit5;
  OEN_EXT  :bit4;
  OEN_SEL  :bit2;
  CMD_DLY  :bit1;
  ADR_DLY  :bit1;
  RESERVED0:bit8;
 end;

 TMC_SHARED_VF_ENABLE=bitpacked record
  VF_ENABLE:bit1;
  RESERVED0:bit31;
 end;

 TMC_VM_DC_WRITE_CNTL=bitpacked record
  DC_WRITE_HIT_REGION_0_MODE:bit2;
  DC_WRITE_HIT_REGION_1_MODE:bit2;
  DC_WRITE_HIT_REGION_2_MODE:bit2;
  DC_WRITE_HIT_REGION_3_MODE:bit2;
  DC_MEMORY_WRITE_LOCAL     :bit1;
  DC_MEMORY_WRITE_SYSTEM    :bit1;
  RESERVED0                 :bit22;
 end;

 TMC_VM_MARC_LEN_HI_0=bitpacked record
  MARC_LEN_HI_0:bit20;
  RESERVED0    :bit12;
 end;

 TMC_VM_MARC_LEN_HI_1=bitpacked record
  MARC_LEN_HI_1:bit20;
  RESERVED0    :bit12;
 end;

 TMC_VM_MARC_LEN_HI_2=bitpacked record
  MARC_LEN_HI_2:bit20;
  RESERVED0    :bit12;
 end;

 TMC_VM_MARC_LEN_HI_3=bitpacked record
  MARC_LEN_HI_3:bit20;
  RESERVED0    :bit12;
 end;

 TMC_VM_MARC_LEN_LO_0=bitpacked record
  RESERVED0    :bit12;
  MARC_LEN_LO_0:bit20;
 end;

 TMC_VM_MARC_LEN_LO_1=bitpacked record
  RESERVED0    :bit12;
  MARC_LEN_LO_1:bit20;
 end;

 TMC_VM_MARC_LEN_LO_2=bitpacked record
  RESERVED0    :bit12;
  MARC_LEN_LO_2:bit20;
 end;

 TMC_VM_MARC_LEN_LO_3=bitpacked record
  RESERVED0    :bit12;
  MARC_LEN_LO_3:bit20;
 end;

 TMC_XPB_CLG_EXTRA_RD=bitpacked record
  CMP0     :bit8;
  MSK0     :bit8;
  VLD0     :bit1;
  CMP1     :bit8;
  VLD1     :bit1;
  RESERVED0:bit6;
 end;

 TMVP_INBAND_CNTL_CAP=bitpacked record
  MVP_IGNOR_INBAND_CNTL     :bit1;
  RESERVED0                 :bit3;
  MVP_PASSING_INBAND_CNTL_EN:bit1;
  RESERVED1                 :bit3;
  MVP_INBAND_CNTL_CHAR_CAP  :bit24;
 end;

 TMVP_TEST_DEBUG_DATA=bit32;

 TOVL_STEREOSYNC_FLIP=bitpacked record
  OVL_STEREOSYNC_FLIP_EN       :bit1;
  RESERVED0                    :bit7;
  OVL_STEREOSYNC_FLIP_MODE     :bit2;
  RESERVED1                    :bit6;
  OVL_PRIMARY_SURFACE_PENDING  :bit1;
  OVL_SECONDARY_SURFACE_PENDING:bit1;
  RESERVED2                    :bit10;
  OVL_STEREOSYNC_SELECT_DISABLE:bit1;
  RESERVED3                    :bit3;
 end;

 TOVL_SURFACE_ADDRESS=bitpacked record
  OVL_DFQ_ENABLE     :bit1;
  RESERVED0          :bit7;
  OVL_SURFACE_ADDRESS:bit24;
 end;

 TPA_CL_VPORT_XOFFSET=bit32;

 TPA_CL_VPORT_YOFFSET=bit32;

 TPA_CL_VPORT_ZOFFSET=bit32;

 TPA_SC_CLIPRECT_0_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_CLIPRECT_0_TL=bitpacked record
  TL_X     :bit15;
  RESERVED0:bit1;
  TL_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_CLIPRECT_1_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_CLIPRECT_1_TL=bitpacked record
  TL_X     :bit15;
  RESERVED0:bit1;
  TL_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_CLIPRECT_2_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_CLIPRECT_2_TL=bitpacked record
  TL_X     :bit15;
  RESERVED0:bit1;
  TL_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_CLIPRECT_3_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_CLIPRECT_3_TL=bitpacked record
  TL_X     :bit15;
  RESERVED0:bit1;
  TL_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_CLIPRECT_RULE=bitpacked record
  CLIP_RULE:bit16;
  RESERVED0:bit16;
 end;

 TPA_SC_RASTER_CONFIG=bitpacked record
  RB_MAP_PKR0:bit2;
  RB_MAP_PKR1:bit2;
  RB_XSEL2   :bit2;
  RB_XSEL    :bit1;
  RB_YSEL    :bit1;
  PKR_MAP    :bit2;
  PKR_XSEL   :bit2;
  PKR_YSEL   :bit2;
  PKR_XSEL2  :bit2;
  SC_MAP     :bit2;
  SC_XSEL    :bit2;
  SC_YSEL    :bit2;
  RESERVED0  :bit2;
  SE_MAP     :bit2;
  SE_XSEL    :bit2;
  SE_YSEL    :bit2;
  RESERVED1  :bit2;
 end;

 TPA_SC_TRAP_SCREEN_H=bitpacked record
  X_COORD  :bit14;
  RESERVED0:bit18;
 end;

 TPA_SC_TRAP_SCREEN_V=bitpacked record
  Y_COORD  :bit14;
  RESERVED0:bit18;
 end;

 TPA_SC_VPORT_ZMAX_10=bit32;

 TPA_SC_VPORT_ZMAX_11=bit32;

 TPA_SC_VPORT_ZMAX_12=bit32;

 TPA_SC_VPORT_ZMAX_13=bit32;

 TPA_SC_VPORT_ZMAX_14=bit32;

 TPA_SC_VPORT_ZMAX_15=bit32;

 TPA_SC_VPORT_ZMIN_10=bit32;

 TPA_SC_VPORT_ZMIN_11=bit32;

 TPA_SC_VPORT_ZMIN_12=bit32;

 TPA_SC_VPORT_ZMIN_13=bit32;

 TPA_SC_VPORT_ZMIN_14=bit32;

 TPA_SC_VPORT_ZMIN_15=bit32;

 TPA_SC_WINDOW_OFFSET=bitpacked record
  WINDOW_X_OFFSET:bit16;
  WINDOW_Y_OFFSET:bit16;
 end;

 TPB0_PIF_LANE0_OVRD2=bitpacked record
  GANGMODE_0     :bit3;
  FREQDIV_0      :bit2;
  LINKSPEED_0    :bit2;
  TWOSYMENABLE_0 :bit1;
  TXPWR_0        :bit3;
  TXPGENABLE_0   :bit2;
  RXPWR_0        :bit3;
  RXPGENABLE_0   :bit2;
  ELECIDLEDETEN_0:bit1;
  ENABLEFOM_0    :bit1;
  REQUESTFOM_0   :bit1;
  RESPONSEMODE_0 :bit1;
  REQUESTTRK_0   :bit1;
  REQUESTTRN_0   :bit1;
  COEFFICIENTID_0:bit2;
  COEFFICIENT_0  :bit6;
 end;

 TPB0_PIF_LANE1_OVRD2=bitpacked record
  GANGMODE_1     :bit3;
  FREQDIV_1      :bit2;
  LINKSPEED_1    :bit2;
  TWOSYMENABLE_1 :bit1;
  TXPWR_1        :bit3;
  TXPGENABLE_1   :bit2;
  RXPWR_1        :bit3;
  RXPGENABLE_1   :bit2;
  ELECIDLEDETEN_1:bit1;
  ENABLEFOM_1    :bit1;
  REQUESTFOM_1   :bit1;
  RESPONSEMODE_1 :bit1;
  REQUESTTRK_1   :bit1;
  REQUESTTRN_1   :bit1;
  COEFFICIENTID_1:bit2;
  COEFFICIENT_1  :bit6;
 end;

 TPB0_PIF_LANE2_OVRD2=bitpacked record
  GANGMODE_2     :bit3;
  FREQDIV_2      :bit2;
  LINKSPEED_2    :bit2;
  TWOSYMENABLE_2 :bit1;
  TXPWR_2        :bit3;
  TXPGENABLE_2   :bit2;
  RXPWR_2        :bit3;
  RXPGENABLE_2   :bit2;
  ELECIDLEDETEN_2:bit1;
  ENABLEFOM_2    :bit1;
  REQUESTFOM_2   :bit1;
  RESPONSEMODE_2 :bit1;
  REQUESTTRK_2   :bit1;
  REQUESTTRN_2   :bit1;
  COEFFICIENTID_2:bit2;
  COEFFICIENT_2  :bit6;
 end;

 TPB0_PIF_LANE3_OVRD2=bitpacked record
  GANGMODE_3     :bit3;
  FREQDIV_3      :bit2;
  LINKSPEED_3    :bit2;
  TWOSYMENABLE_3 :bit1;
  TXPWR_3        :bit3;
  TXPGENABLE_3   :bit2;
  RXPWR_3        :bit3;
  RXPGENABLE_3   :bit2;
  ELECIDLEDETEN_3:bit1;
  ENABLEFOM_3    :bit1;
  REQUESTFOM_3   :bit1;
  RESPONSEMODE_3 :bit1;
  REQUESTTRK_3   :bit1;
  REQUESTTRN_3   :bit1;
  COEFFICIENTID_3:bit2;
  COEFFICIENT_3  :bit6;
 end;

 TPB0_PIF_LANE4_OVRD2=bitpacked record
  GANGMODE_4     :bit3;
  FREQDIV_4      :bit2;
  LINKSPEED_4    :bit2;
  TWOSYMENABLE_4 :bit1;
  TXPWR_4        :bit3;
  TXPGENABLE_4   :bit2;
  RXPWR_4        :bit3;
  RXPGENABLE_4   :bit2;
  ELECIDLEDETEN_4:bit1;
  ENABLEFOM_4    :bit1;
  REQUESTFOM_4   :bit1;
  RESPONSEMODE_4 :bit1;
  REQUESTTRK_4   :bit1;
  REQUESTTRN_4   :bit1;
  COEFFICIENTID_4:bit2;
  COEFFICIENT_4  :bit6;
 end;

 TPB0_PIF_LANE5_OVRD2=bitpacked record
  GANGMODE_5     :bit3;
  FREQDIV_5      :bit2;
  LINKSPEED_5    :bit2;
  TWOSYMENABLE_5 :bit1;
  TXPWR_5        :bit3;
  TXPGENABLE_5   :bit2;
  RXPWR_5        :bit3;
  RXPGENABLE_5   :bit2;
  ELECIDLEDETEN_5:bit1;
  ENABLEFOM_5    :bit1;
  REQUESTFOM_5   :bit1;
  RESPONSEMODE_5 :bit1;
  REQUESTTRK_5   :bit1;
  REQUESTTRN_5   :bit1;
  COEFFICIENTID_5:bit2;
  COEFFICIENT_5  :bit6;
 end;

 TPB0_PIF_LANE6_OVRD2=bitpacked record
  GANGMODE_6     :bit3;
  FREQDIV_6      :bit2;
  LINKSPEED_6    :bit2;
  TWOSYMENABLE_6 :bit1;
  TXPWR_6        :bit3;
  TXPGENABLE_6   :bit2;
  RXPWR_6        :bit3;
  RXPGENABLE_6   :bit2;
  ELECIDLEDETEN_6:bit1;
  ENABLEFOM_6    :bit1;
  REQUESTFOM_6   :bit1;
  RESPONSEMODE_6 :bit1;
  REQUESTTRK_6   :bit1;
  REQUESTTRN_6   :bit1;
  COEFFICIENTID_6:bit2;
  COEFFICIENT_6  :bit6;
 end;

 TPB0_PIF_LANE7_OVRD2=bitpacked record
  GANGMODE_7     :bit3;
  FREQDIV_7      :bit2;
  LINKSPEED_7    :bit2;
  TWOSYMENABLE_7 :bit1;
  TXPWR_7        :bit3;
  TXPGENABLE_7   :bit2;
  RXPWR_7        :bit3;
  RXPGENABLE_7   :bit2;
  ELECIDLEDETEN_7:bit1;
  ENABLEFOM_7    :bit1;
  REQUESTFOM_7   :bit1;
  RESPONSEMODE_7 :bit1;
  REQUESTTRK_7   :bit1;
  REQUESTTRN_7   :bit1;
  COEFFICIENTID_7:bit2;
  COEFFICIENT_7  :bit6;
 end;

 TPB1_PIF_LANE0_OVRD2=bitpacked record
  GANGMODE_0     :bit3;
  FREQDIV_0      :bit2;
  LINKSPEED_0    :bit2;
  TWOSYMENABLE_0 :bit1;
  TXPWR_0        :bit3;
  TXPGENABLE_0   :bit2;
  RXPWR_0        :bit3;
  RXPGENABLE_0   :bit2;
  ELECIDLEDETEN_0:bit1;
  ENABLEFOM_0    :bit1;
  REQUESTFOM_0   :bit1;
  RESPONSEMODE_0 :bit1;
  REQUESTTRK_0   :bit1;
  REQUESTTRN_0   :bit1;
  COEFFICIENTID_0:bit2;
  COEFFICIENT_0  :bit6;
 end;

 TPB1_PIF_LANE1_OVRD2=bitpacked record
  GANGMODE_1     :bit3;
  FREQDIV_1      :bit2;
  LINKSPEED_1    :bit2;
  TWOSYMENABLE_1 :bit1;
  TXPWR_1        :bit3;
  TXPGENABLE_1   :bit2;
  RXPWR_1        :bit3;
  RXPGENABLE_1   :bit2;
  ELECIDLEDETEN_1:bit1;
  ENABLEFOM_1    :bit1;
  REQUESTFOM_1   :bit1;
  RESPONSEMODE_1 :bit1;
  REQUESTTRK_1   :bit1;
  REQUESTTRN_1   :bit1;
  COEFFICIENTID_1:bit2;
  COEFFICIENT_1  :bit6;
 end;

 TPB1_PIF_LANE2_OVRD2=bitpacked record
  GANGMODE_2     :bit3;
  FREQDIV_2      :bit2;
  LINKSPEED_2    :bit2;
  TWOSYMENABLE_2 :bit1;
  TXPWR_2        :bit3;
  TXPGENABLE_2   :bit2;
  RXPWR_2        :bit3;
  RXPGENABLE_2   :bit2;
  ELECIDLEDETEN_2:bit1;
  ENABLEFOM_2    :bit1;
  REQUESTFOM_2   :bit1;
  RESPONSEMODE_2 :bit1;
  REQUESTTRK_2   :bit1;
  REQUESTTRN_2   :bit1;
  COEFFICIENTID_2:bit2;
  COEFFICIENT_2  :bit6;
 end;

 TPB1_PIF_LANE3_OVRD2=bitpacked record
  GANGMODE_3     :bit3;
  FREQDIV_3      :bit2;
  LINKSPEED_3    :bit2;
  TWOSYMENABLE_3 :bit1;
  TXPWR_3        :bit3;
  TXPGENABLE_3   :bit2;
  RXPWR_3        :bit3;
  RXPGENABLE_3   :bit2;
  ELECIDLEDETEN_3:bit1;
  ENABLEFOM_3    :bit1;
  REQUESTFOM_3   :bit1;
  RESPONSEMODE_3 :bit1;
  REQUESTTRK_3   :bit1;
  REQUESTTRN_3   :bit1;
  COEFFICIENTID_3:bit2;
  COEFFICIENT_3  :bit6;
 end;

 TPB1_PIF_LANE4_OVRD2=bitpacked record
  GANGMODE_4     :bit3;
  FREQDIV_4      :bit2;
  LINKSPEED_4    :bit2;
  TWOSYMENABLE_4 :bit1;
  TXPWR_4        :bit3;
  TXPGENABLE_4   :bit2;
  RXPWR_4        :bit3;
  RXPGENABLE_4   :bit2;
  ELECIDLEDETEN_4:bit1;
  ENABLEFOM_4    :bit1;
  REQUESTFOM_4   :bit1;
  RESPONSEMODE_4 :bit1;
  REQUESTTRK_4   :bit1;
  REQUESTTRN_4   :bit1;
  COEFFICIENTID_4:bit2;
  COEFFICIENT_4  :bit6;
 end;

 TPB1_PIF_LANE5_OVRD2=bitpacked record
  GANGMODE_5     :bit3;
  FREQDIV_5      :bit2;
  LINKSPEED_5    :bit2;
  TWOSYMENABLE_5 :bit1;
  TXPWR_5        :bit3;
  TXPGENABLE_5   :bit2;
  RXPWR_5        :bit3;
  RXPGENABLE_5   :bit2;
  ELECIDLEDETEN_5:bit1;
  ENABLEFOM_5    :bit1;
  REQUESTFOM_5   :bit1;
  RESPONSEMODE_5 :bit1;
  REQUESTTRK_5   :bit1;
  REQUESTTRN_5   :bit1;
  COEFFICIENTID_5:bit2;
  COEFFICIENT_5  :bit6;
 end;

 TPB1_PIF_LANE6_OVRD2=bitpacked record
  GANGMODE_6     :bit3;
  FREQDIV_6      :bit2;
  LINKSPEED_6    :bit2;
  TWOSYMENABLE_6 :bit1;
  TXPWR_6        :bit3;
  TXPGENABLE_6   :bit2;
  RXPWR_6        :bit3;
  RXPGENABLE_6   :bit2;
  ELECIDLEDETEN_6:bit1;
  ENABLEFOM_6    :bit1;
  REQUESTFOM_6   :bit1;
  RESPONSEMODE_6 :bit1;
  REQUESTTRK_6   :bit1;
  REQUESTTRN_6   :bit1;
  COEFFICIENTID_6:bit2;
  COEFFICIENT_6  :bit6;
 end;

 TPB1_PIF_LANE7_OVRD2=bitpacked record
  GANGMODE_7     :bit3;
  FREQDIV_7      :bit2;
  LINKSPEED_7    :bit2;
  TWOSYMENABLE_7 :bit1;
  TXPWR_7        :bit3;
  TXPGENABLE_7   :bit2;
  RXPWR_7        :bit3;
  RXPGENABLE_7   :bit2;
  ELECIDLEDETEN_7:bit1;
  ENABLEFOM_7    :bit1;
  REQUESTFOM_7   :bit1;
  RESPONSEMODE_7 :bit1;
  REQUESTTRK_7   :bit1;
  REQUESTTRN_7   :bit1;
  COEFFICIENTID_7:bit2;
  COEFFICIENT_7  :bit6;
 end;

 TPCIE_LC_FORCE_COEFF=bitpacked record
  LC_FORCE_COEFF        :bit1;
  LC_FORCE_PRE_CURSOR   :bit6;
  LC_FORCE_CURSOR       :bit6;
  LC_FORCE_POST_CURSOR  :bit6;
  LC_3X3_COEFF_SEARCH_EN:bit1;
  LC_PRESET_10_EN       :bit1;
  RESERVED0             :bit11;
 end;

 TPCIE_PORT_VC_STATUS=bitpacked record
  VC_ARB_TABLE_STATUS:bit1;
  RESERVED0          :bit31;
 end;

 TPCIE_PRBS_ERRCNT_10=bit32;

 TPCIE_PRBS_ERRCNT_11=bit32;

 TPCIE_PRBS_ERRCNT_12=bit32;

 TPCIE_PRBS_ERRCNT_13=bit32;

 TPCIE_PRBS_ERRCNT_14=bit32;

 TPCIE_PRBS_ERRCNT_15=bit32;

 TPCIE_PRBS_HI_BITCNT=bitpacked record
  PRBS_HI_BITCNT:bit8;
  RESERVED0     :bit24;
 end;

 TPCIE_PRBS_LO_BITCNT=bit32;

 TPCIE_PWR_BUDGET_CAP=bitpacked record
  SYSTEM_ALLOCATED:bit1;
  RESERVED0       :bit31;
 end;

 TPCIE_RXDET_OVERRIDE=bitpacked record
  RxDetOvrVal:bit16;
  RxDetOvrEn :bit1;
  RESERVED0  :bit15;
 end;

 TPIXCLK0_RESYNC_CNTL=bitpacked record
  PIXCLK0_RESYNC_ENABLE:bit1;
  RESERVED0            :bit3;
  DCCG_DEEP_COLOR_CNTL0:bit2;
  RESERVED1            :bit26;
 end;

 TPIXCLK1_RESYNC_CNTL=bitpacked record
  PIXCLK1_RESYNC_ENABLE:bit1;
  RESERVED0            :bit3;
  DCCG_DEEP_COLOR_CNTL1:bit2;
  RESERVED1            :bit26;
 end;

 TPIXCLK2_RESYNC_CNTL=bitpacked record
  PIXCLK2_RESYNC_ENABLE:bit1;
  RESERVED0            :bit3;
  DCCG_DEEP_COLOR_CNTL2:bit2;
  RESERVED1            :bit26;
 end;

 TPPLL_DEBUG_MUX_CNTL=bitpacked record
  DEBUG_BUS_MUX_SEL:bit5;
  RESERVED0        :bit27;
 end;

 TPWR_PCC_GPIO_SELECT=bit32;

 TRLC_GPU_IOV_SCH_INT=bit32;

 TRLC_LB_INIT_CU_MASK=bit32;

 TRLC_PERFCOUNTER0_HI=bit32;

 TRLC_PERFCOUNTER0_LO=bit32;

 TRLC_PERFCOUNTER1_HI=bit32;

 TRLC_PERFCOUNTER1_LO=bit32;

 TRLC_SRM_GPM_COMMAND=bitpacked record
  OP            :bit1;
  INDEX_CNTL    :bit1;
  INDEX_CNTL_NUM:bit3;
  SIZE          :bit12;
  START_OFFSET  :bit12;
  RESERVED1     :bit2;
  DEST_MEMORY   :bit1;
 end;

 TSAM_IH_EXT_ERR_INTR=bitpacked record
  UVD      :bit1;
  VCE      :bit1;
  ISP      :bit1;
  RESERVED0:bit29;
 end;

 TSCLV_VIEWPORT_START=bitpacked record
  VIEWPORT_Y_START:bit14;
  RESERVED0       :bit2;
  VIEWPORT_X_START:bit14;
  RESERVED1       :bit2;
 end;

 TSCL_COEF_RAM_SELECT=bitpacked record
  SCL_C_RAM_TAP_PAIR_IDX:bit4;
  RESERVED0             :bit4;
  SCL_C_RAM_PHASE       :bit4;
  RESERVED1             :bit4;
  SCL_C_RAM_FILTER_TYPE :bit3;
  RESERVED2             :bit13;
 end;

 TSCL_F_SHARP_CONTROL=bitpacked record
  SCL_HF_SHARP_SCALE_FACTOR:bit3;
  RESERVED0                :bit1;
  SCL_HF_SHARP_EN          :bit1;
  RESERVED1                :bit3;
  SCL_VF_SHARP_SCALE_FACTOR:bit3;
  RESERVED2                :bit1;
  SCL_VF_SHARP_EN          :bit1;
  RESERVED3                :bit19;
 end;

 TSCL_TEST_DEBUG_DATA=bit32;

 TSDMA0_ACTIVE_FCN_ID=bitpacked record
  VFID     :bit4;
  RESERVED0:bit27;
  VF       :bit1;
 end;

 TSDMA0_GFX_APE1_CNTL=bitpacked record
  BASE :bit16;
  LIMIT:bit16;
 end;

 TSDMA0_GFX_DUMMY_REG=bit32;

 TSDMA0_GFX_IB_OFFSET=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA0_GFX_SKIP_CNTL=bitpacked record
  SKIP_COUNT:bit14;
  RESERVED0 :bit18;
 end;

 TSDMA0_GFX_WATERMARK=bitpacked record
  RD_OUTSTANDING:bit12;
  RESERVED0     :bit4;
  WR_OUTSTANDING:bit9;
  RESERVED1     :bit7;
 end;

 TSDMA0_PUB_REG_TYPE0=bitpacked record
  SDMA0_UCODE_ADDR              :bit1;
  SDMA0_UCODE_DATA              :bit1;
  SDMA0_POWER_CNTL              :bit1;
  SDMA0_CLK_CTRL                :bit1;
  SDMA0_CNTL                    :bit1;
  SDMA0_CHICKEN_BITS            :bit1;
  SDMA0_TILING_CONFIG           :bit1;
  SDMA0_HASH                    :bit1;
  RESERVED0                     :bit1;
  SDMA0_SEM_WAIT_FAIL_TIMER_CNTL:bit1;
  SDMA0_RB_RPTR_FETCH           :bit1;
  SDMA0_IB_OFFSET_FETCH         :bit1;
  SDMA0_PROGRAM                 :bit1;
  SDMA0_STATUS_REG              :bit1;
  SDMA0_STATUS1_REG             :bit1;
  SDMA0_RD_BURST_CNTL           :bit1;
  RESERVED_16                   :bit1;
  RESERVED_17                   :bit1;
  SDMA0_F32_CNTL                :bit1;
  SDMA0_FREEZE                  :bit1;
  SDMA0_PHASE0_QUANTUM          :bit1;
  SDMA0_PHASE1_QUANTUM          :bit1;
  SDMA_POWER_GATING             :bit1;
  SDMA_PGFSM_CONFIG             :bit1;
  SDMA_PGFSM_WRITE              :bit1;
  SDMA_PGFSM_READ               :bit1;
  SDMA0_EDC_CONFIG              :bit1;
  SDMA0_BA_THRESHOLD            :bit1;
  SDMA0_DEVICE_ID               :bit1;
  RESERVED1                     :bit1;
  RESERVED                      :bit2;
 end;

 TSDMA0_PUB_REG_TYPE1=bitpacked record
  SDMA0_VM_CNTL    :bit1;
  SDMA0_VM_CTX_LO  :bit1;
  SDMA0_VM_CTX_HI  :bit1;
  SDMA0_STATUS2_REG:bit1;
  SDMA0_VM_CTX_CNTL:bit1;
  RESERVED         :bit27;
 end;

 TSDMA0_RB_RPTR_FETCH=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA0_RD_BURST_CNTL=bitpacked record
  RD_BURST :bit2;
  RESERVED0:bit30;
 end;

 TSDMA0_RLC0_DOORBELL=bitpacked record
  OFFSET   :bit21;
  RESERVED0:bit7;
  ENABLE   :bit1;
  RESERVED1:bit1;
  CAPTURED :bit1;
  RESERVED2:bit1;
 end;

 TSDMA0_RLC1_DOORBELL=bitpacked record
  OFFSET   :bit21;
  RESERVED0:bit7;
  ENABLE   :bit1;
  RESERVED1:bit1;
  CAPTURED :bit1;
  RESERVED2:bit1;
 end;

 TSDMA0_TILING_CONFIG=bitpacked record
  RESERVED0           :bit4;
  PIPE_INTERLEAVE_SIZE:bit3;
  RESERVED1           :bit25;
 end;

 TSDMA1_ACTIVE_FCN_ID=bitpacked record
  VFID     :bit4;
  RESERVED0:bit27;
  VF       :bit1;
 end;

 TSDMA1_GFX_APE1_CNTL=bitpacked record
  BASE :bit16;
  LIMIT:bit16;
 end;

 TSDMA1_GFX_DUMMY_REG=bit32;

 TSDMA1_GFX_IB_OFFSET=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA1_GFX_SKIP_CNTL=bitpacked record
  SKIP_COUNT:bit14;
  RESERVED0 :bit18;
 end;

 TSDMA1_GFX_WATERMARK=bitpacked record
  RD_OUTSTANDING:bit12;
  RESERVED0     :bit4;
  WR_OUTSTANDING:bit9;
  RESERVED1     :bit7;
 end;

 TSDMA1_PUB_REG_TYPE0=bitpacked record
  SDMA1_UCODE_ADDR              :bit1;
  SDMA1_UCODE_DATA              :bit1;
  SDMA1_POWER_CNTL              :bit1;
  SDMA1_CLK_CTRL                :bit1;
  SDMA1_CNTL                    :bit1;
  SDMA1_CHICKEN_BITS            :bit1;
  SDMA1_TILING_CONFIG           :bit1;
  SDMA1_HASH                    :bit1;
  RESERVED0                     :bit1;
  SDMA1_SEM_WAIT_FAIL_TIMER_CNTL:bit1;
  SDMA1_RB_RPTR_FETCH           :bit1;
  SDMA1_IB_OFFSET_FETCH         :bit1;
  SDMA1_PROGRAM                 :bit1;
  SDMA1_STATUS_REG              :bit1;
  SDMA1_STATUS1_REG             :bit1;
  SDMA1_RD_BURST_CNTL           :bit1;
  RESERVED_16                   :bit1;
  RESERVED_17                   :bit1;
  SDMA1_F32_CNTL                :bit1;
  SDMA1_FREEZE                  :bit1;
  SDMA1_PHASE0_QUANTUM          :bit1;
  SDMA1_PHASE1_QUANTUM          :bit1;
  VOID_REG0                     :bit4;
  SDMA1_EDC_CONFIG              :bit1;
  SDMA1_BA_THRESHOLD            :bit1;
  SDMA1_DEVICE_ID               :bit1;
  RESERVED1                     :bit1;
  RESERVED                      :bit2;
 end;

 TSDMA1_PUB_REG_TYPE1=bitpacked record
  SDMA1_VM_CNTL    :bit1;
  SDMA1_VM_CTX_LO  :bit1;
  SDMA1_VM_CTX_HI  :bit1;
  SDMA1_STATUS2_REG:bit1;
  SDMA1_VM_CTX_CNTL:bit1;
  RESERVED         :bit27;
 end;

 TSDMA1_RB_RPTR_FETCH=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit30;
 end;

 TSDMA1_RD_BURST_CNTL=bitpacked record
  RD_BURST :bit2;
  RESERVED0:bit30;
 end;

 TSDMA1_RLC0_DOORBELL=bitpacked record
  OFFSET   :bit21;
  RESERVED0:bit7;
  ENABLE   :bit1;
  RESERVED1:bit1;
  CAPTURED :bit1;
  RESERVED2:bit1;
 end;

 TSDMA1_RLC1_DOORBELL=bitpacked record
  OFFSET   :bit21;
  RESERVED0:bit7;
  ENABLE   :bit1;
  RESERVED1:bit1;
  CAPTURED :bit1;
  RESERVED2:bit1;
 end;

 TSDMA1_TILING_CONFIG=bitpacked record
  RESERVED0           :bit4;
  PIPE_INTERLEAVE_SIZE:bit3;
  RESERVED1           :bit25;
 end;

 TSEM_MAILBOX_CONTROL=bitpacked record
  SIDEPORT_ENABLE      :bit8;
  HOSTPORT_ENABLE      :bit8;
  SIDEPORT_ENABLE_EXTRA:bit8;
  HOSTPORT_ENABLE_EXTRA:bit8;
 end;

 TSLAVE_COMM_CNTL_REG=bitpacked record
  SLAVE_COMM_INTERRUPT             :bit1;
  RESERVED0                        :bit7;
  COMM_PORT_MSG_TO_HOST_IN_PROGRESS:bit1;
  RESERVED1                        :bit23;
 end;

 TSMC_IND_ACCESS_CNTL=bitpacked record
  AUTO_INCREMENT_IND_0 :bit1;
  AUTO_INCREMENT_IND_1 :bit1;
  AUTO_INCREMENT_IND_2 :bit1;
  AUTO_INCREMENT_IND_3 :bit1;
  AUTO_INCREMENT_IND_4 :bit1;
  AUTO_INCREMENT_IND_5 :bit1;
  AUTO_INCREMENT_IND_6 :bit1;
  AUTO_INCREMENT_IND_7 :bit1;
  AUTO_INCREMENT_IND_8 :bit1;
  AUTO_INCREMENT_IND_9 :bit1;
  AUTO_INCREMENT_IND_10:bit1;
  AUTO_INCREMENT_IND_11:bit1;
  AUTO_INCREMENT_IND_12:bit1;
  AUTO_INCREMENT_IND_13:bit1;
  AUTO_INCREMENT_IND_14:bit1;
  AUTO_INCREMENT_IND_15:bit1;
  RESERVED0            :bit16;
 end;

 TSMU_MP1_RLC2MP_RESP=bit32;

 TSPI_GDBG_TRAP_DATA0=bit32;

 TSPI_GDBG_TRAP_DATA1=bit32;

 TSPI_PERFCOUNTER0_HI=bit32;

 TSPI_PERFCOUNTER0_LO=bit32;

 TSPI_PERFCOUNTER1_HI=bit32;

 TSPI_PERFCOUNTER1_LO=bit32;

 TSPI_PERFCOUNTER2_HI=bit32;

 TSPI_PERFCOUNTER2_LO=bit32;

 TSPI_PERFCOUNTER3_HI=bit32;

 TSPI_PERFCOUNTER3_LO=bit32;

 TSPI_PERFCOUNTER4_HI=bit32;

 TSPI_PERFCOUNTER4_LO=bit32;

 TSPI_PERFCOUNTER5_HI=bit32;

 TSPI_PERFCOUNTER5_LO=bit32;

 TSPI_PS_INPUT_CNTL_0=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_1=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_2=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_3=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_4=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_5=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_6=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_7=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_8=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_9=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_SHADER_Z_FORMAT=bitpacked record
  Z_EXPORT_FORMAT:bit4;
  RESERVED0      :bit28;
 end;

 TSPMI_SRAM_CLK_GATER=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit10;
  RESERVED2:bit21;
 end;

 TSQ_DEBUG_CTRL_LOCAL=bitpacked record
  UNUSED   :bit8;
  RESERVED0:bit24;
 end;

 TSQ_DEBUG_STS_GLOBAL=bitpacked record
  BUSY              :bit1;
  INTERRUPT_MSG_BUSY:bit1;
  RESERVED0         :bit2;
  WAVE_LEVEL_SH0    :bit12;
  WAVE_LEVEL_SH1    :bit12;
  RESERVED1         :bit4;
 end;

 TSQ_PERFCOUNTER10_HI=bit32;

 TSQ_PERFCOUNTER10_LO=bit32;

 TSQ_PERFCOUNTER11_HI=bit32;

 TSQ_PERFCOUNTER11_LO=bit32;

 TSQ_PERFCOUNTER12_HI=bit32;

 TSQ_PERFCOUNTER12_LO=bit32;

 TSQ_PERFCOUNTER13_HI=bit32;

 TSQ_PERFCOUNTER13_LO=bit32;

 TSQ_PERFCOUNTER14_HI=bit32;

 TSQ_PERFCOUNTER14_LO=bit32;

 TSQ_PERFCOUNTER15_HI=bit32;

 TSQ_PERFCOUNTER15_LO=bit32;

 TSQ_PERFCOUNTER_CTRL=bitpacked record
  PS_EN        :bit1;
  VS_EN        :bit1;
  GS_EN        :bit1;
  ES_EN        :bit1;
  HS_EN        :bit1;
  LS_EN        :bit1;
  CS_EN        :bit1;
  RESERVED0    :bit1;
  CNTR_RATE    :bit5;
  DISABLE_FLUSH:bit1;
  RESERVED1    :bit18;
 end;

 TSQ_PERFCOUNTER_MASK=bitpacked record
  SH0_MASK:bit16;
  SH1_MASK:bit16;
 end;

 TSRBM_CREDIT_RECOVER=bitpacked record
  CREDIT_RECOVER_BIF  :bit1;
  CREDIT_RECOVER_SMU  :bit1;
  CREDIT_RECOVER_DC   :bit1;
  CREDIT_RECOVER_GIONB:bit1;
  CREDIT_RECOVER_ACP  :bit1;
  CREDIT_RECOVER_XDMA :bit1;
  CREDIT_RECOVER_ODE  :bit1;
  CREDIT_RECOVER_REGBB:bit1;
  CREDIT_RECOVER_VP8  :bit1;
  CREDIT_RECOVER_GRBM :bit1;
  CREDIT_RECOVER_UVD  :bit1;
  CREDIT_RECOVER_VCE0 :bit1;
  CREDIT_RECOVER_VCE1 :bit1;
  CREDIT_RECOVER_ISP  :bit1;
  CREDIT_RECOVER_SAM  :bit1;
  CREDIT_RECOVER_MCB  :bit1;
  CREDIT_RECOVER_MCC0 :bit1;
  CREDIT_RECOVER_MCC1 :bit1;
  CREDIT_RECOVER_MCC2 :bit1;
  CREDIT_RECOVER_MCC3 :bit1;
  CREDIT_RECOVER_MCC4 :bit1;
  CREDIT_RECOVER_MCC5 :bit1;
  CREDIT_RECOVER_MCC6 :bit1;
  CREDIT_RECOVER_MCC7 :bit1;
  CREDIT_RECOVER_MCD0 :bit1;
  CREDIT_RECOVER_MCD1 :bit1;
  CREDIT_RECOVER_MCD2 :bit1;
  CREDIT_RECOVER_MCD3 :bit1;
  CREDIT_RECOVER_MCD4 :bit1;
  CREDIT_RECOVER_MCD5 :bit1;
  CREDIT_RECOVER_MCD6 :bit1;
  CREDIT_RECOVER_MCD7 :bit1;
 end;

 TSRBM_DEBUG_SNAPSHOT=bitpacked record
  MCB_RDY   :bit1;
  GIONB_RDY :bit1;
  SMU_RDY   :bit1;
  SAMMSP_RDY:bit1;
  ACP_RDY   :bit1;
  GRBM_RDY  :bit1;
  DC_RDY    :bit1;
  BIF_RDY   :bit1;
  XDMA_RDY  :bit1;
  UVD_RDY   :bit1;
  VP8_RDY   :bit1;
  REGBB_RDY :bit1;
  ODE_RDY   :bit1;
  MCD7_RDY  :bit1;
  MCD6_RDY  :bit1;
  MCD5_RDY  :bit1;
  MCD4_RDY  :bit1;
  MCD3_RDY  :bit1;
  MCD2_RDY  :bit1;
  MCD1_RDY  :bit1;
  MCD0_RDY  :bit1;
  MCC7_RDY  :bit1;
  MCC6_RDY  :bit1;
  MCC5_RDY  :bit1;
  MCC4_RDY  :bit1;
  MCC3_RDY  :bit1;
  MCC2_RDY  :bit1;
  MCC1_RDY  :bit1;
  MCC0_RDY  :bit1;
  VCE0_RDY  :bit1;
  SAMSCP_RDY:bit1;
  ISP_RDY   :bit1;
 end;

 TSRBM_DSM_TRIG_CNTL0=bitpacked record
  DSM_TRIG_ADDR:bit16;
  DSM_TRIG_OP  :bit1;
  RESERVED0    :bit15;
 end;

 TSRBM_DSM_TRIG_CNTL1=bit32;

 TSRBM_DSM_TRIG_MASK0=bitpacked record
  DSM_TRIG_ADDR_MASK:bit16;
  DSM_TRIG_OP_MASK  :bit1;
  RESERVED0         :bit15;
 end;

 TSRBM_DSM_TRIG_MASK1=bit32;

 TSRBM_ISP_CLKEN_CNTL=bitpacked record
  PREFIX_DELAY_CNT:bit4;
  RESERVED0       :bit4;
  POST_DELAY_CNT  :bit5;
  RESERVED1       :bit19;
 end;

 TSRBM_SAM_CLKEN_CNTL=bitpacked record
  PREFIX_DELAY_CNT:bit4;
  RESERVED0       :bit4;
  POST_DELAY_CNT  :bit5;
  RESERVED1       :bit19;
 end;

 TSRBM_SYS_CLKEN_CNTL=bitpacked record
  PREFIX_DELAY_CNT:bit4;
  RESERVED0       :bit4;
  POST_DELAY_CNT  :bit5;
  RESERVED1       :bit19;
 end;

 TSRBM_UVD_CLKEN_CNTL=bitpacked record
  PREFIX_DELAY_CNT:bit4;
  RESERVED0       :bit4;
  POST_DELAY_CNT  :bit5;
  RESERVED1       :bit19;
 end;

 TSRBM_VCE_CLKEN_CNTL=bitpacked record
  PREFIX_DELAY_CNT:bit4;
  RESERVED0       :bit4;
  POST_DELAY_CNT  :bit5;
  RESERVED1       :bit19;
 end;

 TSRBM_VIRT_RESET_REQ=bitpacked record
  VF       :bit16;
  RESERVED0:bit15;
  PF       :bit1;
 end;

 TSRBM_VP8_CLKEN_CNTL=bitpacked record
  PREFIX_DELAY_CNT:bit4;
  RESERVED0       :bit4;
  POST_DELAY_CNT  :bit5;
  RESERVED1       :bit19;
 end;

 TSTATE_CHANGE_STATUS=bitpacked record
  STATE_CHANGE_STATUS:bit1;
  RESERVED0          :bit31;
 end;

 TTCA_PERFCOUNTER0_HI=bit32;

 TTCA_PERFCOUNTER0_LO=bit32;

 TTCA_PERFCOUNTER1_HI=bit32;

 TTCA_PERFCOUNTER1_LO=bit32;

 TTCA_PERFCOUNTER2_HI=bit32;

 TTCA_PERFCOUNTER2_LO=bit32;

 TTCA_PERFCOUNTER3_HI=bit32;

 TTCA_PERFCOUNTER3_LO=bit32;

 TTCC_PERFCOUNTER0_HI=bit32;

 TTCC_PERFCOUNTER0_LO=bit32;

 TTCC_PERFCOUNTER1_HI=bit32;

 TTCC_PERFCOUNTER1_LO=bit32;

 TTCC_PERFCOUNTER2_HI=bit32;

 TTCC_PERFCOUNTER2_LO=bit32;

 TTCC_PERFCOUNTER3_HI=bit32;

 TTCC_PERFCOUNTER3_LO=bit32;

 TTCP_GATCL1_DSM_CNTL=bitpacked record
  SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0:bit1;
  SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1:bit1;
  TCP_GATCL1_ENABLE_SINGLE_WRITE_A    :bit1;
  RESERVED0                           :bit29;
 end;

 TTCP_PERFCOUNTER0_HI=bit32;

 TTCP_PERFCOUNTER0_LO=bit32;

 TTCP_PERFCOUNTER1_HI=bit32;

 TTCP_PERFCOUNTER1_LO=bit32;

 TTCP_PERFCOUNTER2_HI=bit32;

 TTCP_PERFCOUNTER2_LO=bit32;

 TTCP_PERFCOUNTER3_HI=bit32;

 TTCP_PERFCOUNTER3_LO=bit32;

 TUNIPHY_IMPCAL_LINKA=bitpacked record
  UNIPHY_IMPCAL_ENABLE_LINKA         :bit1;
  RESERVED0                          :bit7;
  UNIPHY_IMPCAL_CALOUT_LINKA         :bit1;
  UNIPHY_CALOUT_ERROR_LINKA          :bit1;
  UNIPHY_CALOUT_ERROR_LINKA_AK       :bit1;
  RESERVED1                          :bit5;
  UNIPHY_IMPCAL_VALUE_LINKA          :bit4;
  UNIPHY_IMPCAL_STEP_DELAY_LINKA     :bit4;
  UNIPHY_IMPCAL_OVERRIDE_LINKA       :bit4;
  UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA:bit1;
  RESERVED2                          :bit1;
  UNIPHY_IMPCAL_SEL_LINKA            :bit1;
  RESERVED3                          :bit1;
 end;

 TUNIPHY_IMPCAL_LINKB=bitpacked record
  UNIPHY_IMPCAL_ENABLE_LINKB         :bit1;
  RESERVED0                          :bit7;
  UNIPHY_IMPCAL_CALOUT_LINKB         :bit1;
  UNIPHY_CALOUT_ERROR_LINKB          :bit1;
  UNIPHY_CALOUT_ERROR_LINKB_AK       :bit1;
  RESERVED1                          :bit5;
  UNIPHY_IMPCAL_VALUE_LINKB          :bit4;
  UNIPHY_IMPCAL_STEP_DELAY_LINKB     :bit4;
  UNIPHY_IMPCAL_OVERRIDE_LINKB       :bit4;
  UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB:bit1;
  RESERVED2                          :bit1;
  UNIPHY_IMPCAL_SEL_LINKB            :bit1;
  RESERVED3                          :bit1;
 end;

 TUNIPHY_IMPCAL_LINKC=bitpacked record
  UNIPHY_IMPCAL_ENABLE_LINKC         :bit1;
  RESERVED0                          :bit7;
  UNIPHY_IMPCAL_CALOUT_LINKC         :bit1;
  UNIPHY_CALOUT_ERROR_LINKC          :bit1;
  UNIPHY_CALOUT_ERROR_LINKC_AK       :bit1;
  RESERVED1                          :bit5;
  UNIPHY_IMPCAL_VALUE_LINKC          :bit4;
  UNIPHY_IMPCAL_STEP_DELAY_LINKC     :bit4;
  UNIPHY_IMPCAL_OVERRIDE_LINKC       :bit4;
  UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC:bit1;
  RESERVED2                          :bit1;
  UNIPHY_IMPCAL_SEL_LINKC            :bit1;
  RESERVED3                          :bit1;
 end;

 TUNIPHY_IMPCAL_LINKD=bitpacked record
  UNIPHY_IMPCAL_ENABLE_LINKD         :bit1;
  RESERVED0                          :bit7;
  UNIPHY_IMPCAL_CALOUT_LINKD         :bit1;
  UNIPHY_CALOUT_ERROR_LINKD          :bit1;
  UNIPHY_CALOUT_ERROR_LINKD_AK       :bit1;
  RESERVED1                          :bit5;
  UNIPHY_IMPCAL_VALUE_LINKD          :bit4;
  UNIPHY_IMPCAL_STEP_DELAY_LINKD     :bit4;
  UNIPHY_IMPCAL_OVERRIDE_LINKD       :bit4;
  UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD:bit1;
  RESERVED2                          :bit1;
  UNIPHY_IMPCAL_SEL_LINKD            :bit1;
  RESERVED3                          :bit1;
 end;

 TUNIPHY_IMPCAL_LINKE=bitpacked record
  UNIPHY_IMPCAL_ENABLE_LINKE         :bit1;
  RESERVED0                          :bit7;
  UNIPHY_IMPCAL_CALOUT_LINKE         :bit1;
  UNIPHY_CALOUT_ERROR_LINKE          :bit1;
  UNIPHY_CALOUT_ERROR_LINKE_AK       :bit1;
  RESERVED1                          :bit5;
  UNIPHY_IMPCAL_VALUE_LINKE          :bit4;
  UNIPHY_IMPCAL_STEP_DELAY_LINKE     :bit4;
  UNIPHY_IMPCAL_OVERRIDE_LINKE       :bit4;
  UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE:bit1;
  RESERVED2                          :bit1;
  UNIPHY_IMPCAL_SEL_LINKE            :bit1;
  RESERVED3                          :bit1;
 end;

 TUNIPHY_IMPCAL_LINKF=bitpacked record
  UNIPHY_IMPCAL_ENABLE_LINKF         :bit1;
  RESERVED0                          :bit7;
  UNIPHY_IMPCAL_CALOUT_LINKF         :bit1;
  UNIPHY_CALOUT_ERROR_LINKF          :bit1;
  UNIPHY_CALOUT_ERROR_LINKF_AK       :bit1;
  RESERVED1                          :bit5;
  UNIPHY_IMPCAL_VALUE_LINKF          :bit4;
  UNIPHY_IMPCAL_STEP_DELAY_LINKF     :bit4;
  UNIPHY_IMPCAL_OVERRIDE_LINKF       :bit4;
  UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF:bit1;
  RESERVED2                          :bit1;
  UNIPHY_IMPCAL_SEL_LINKF            :bit1;
  RESERVED3                          :bit1;
 end;

 TUNIPHY_PLL_CONTROL1=bitpacked record
  UNIPHY_PLL_ENABLE          :bit1;
  UNIPHY_PLL_RESET           :bit1;
  UNIPHY_PLL_EXT_RESET_EN    :bit1;
  UNIPHY_PLL_CLK_EN          :bit1;
  UNIPHY_PLL_CLKPH_EN        :bit4;
  UNIPHY_PLL_LF_CNTL         :bit7;
  RESERVED0                  :bit1;
  UNIPHY_PLL_BW_CNTL         :bit8;
  UNIPHY_PLL_TEST_BYPCLK_SRC :bit1;
  UNIPHY_PLL_TEST_BYPCLK_EN  :bit1;
  UNIPHY_PLL_TEST_VCTL_ADC_EN:bit1;
  RESERVED1                  :bit1;
  UNIPHY_VCO_MODE            :bit2;
  RESERVED2                  :bit2;
 end;

 TUNIPHY_PLL_CONTROL2=bitpacked record
  UNIPHY_PLL_DISPCLK_MODE          :bit2;
  UNIPHY_DPLLSEL                   :bit2;
  UNIPHY_IDCLK_SEL                 :bit1;
  UNIPHY_IPCIE_REFCLK_SEL          :bit1;
  UNIPHY_IXTALIN_SEL               :bit1;
  RESERVED0                        :bit1;
  UNIPHY_PLL_REFCLK_SRC            :bit3;
  UNIPHY_PCIEREF_CLK_EN            :bit1;
  UNIPHY_IDCLK_EN                  :bit1;
  UNIPHY_CLKINV                    :bit1;
  RESERVED1                        :bit2;
  UNIPHY_PLL_VTOI_BIAS_CNTL        :bit1;
  RESERVED2                        :bit2;
  UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS:bit1;
  UNIPHY_PDIVFRAC_SEL              :bit1;
  RESERVED3                        :bit3;
  UNIPHY_PLL_REFDIV                :bit5;
  UNIPHY_PDIV_SEL                  :bit3;
 end;

 TUNP_GRPH_DFQ_STATUS=bitpacked record
  GRPH_PRIMARY_DFQ_NUM_ENTRIES  :bit4;
  GRPH_SECONDARY_DFQ_NUM_ENTRIES:bit4;
  GRPH_DFQ_RESET_FLAG           :bit1;
  GRPH_DFQ_RESET_ACK            :bit1;
  RESERVED0                     :bit22;
 end;

 TUNP_TEST_DEBUG_DATA=bit32;

 TUVD_CGC_UDEC_STATUS=bitpacked record
  RE_SCLK   :bit1;
  RE_DCLK   :bit1;
  RE_VCLK   :bit1;
  CM_SCLK   :bit1;
  CM_DCLK   :bit1;
  CM_VCLK   :bit1;
  IT_SCLK   :bit1;
  IT_DCLK   :bit1;
  IT_VCLK   :bit1;
  DB_SCLK   :bit1;
  DB_DCLK   :bit1;
  DB_VCLK   :bit1;
  MP_SCLK   :bit1;
  MP_DCLK   :bit1;
  MP_VCLK   :bit1;
  JPEG_VCLK :bit1;
  JPEG_SCLK :bit1;
  JPEG2_VCLK:bit1;
  JPEG2_SCLK:bit1;
  RESERVED0 :bit13;
 end;

 TUVD_LMI_RBC_IB_VMID=bitpacked record
  IB_VMID  :bit4;
  RESERVED0:bit28;
 end;

 TUVD_LMI_RBC_RB_VMID=bitpacked record
  RB_VMID  :bit4;
  RESERVED0:bit28;
 end;

 TUVD_SUVD_CGC_STATUS=bitpacked record
  SRE_VCLK     :bit1;
  SRE_DCLK     :bit1;
  SIT_DCLK     :bit1;
  SMP_DCLK     :bit1;
  SCM_DCLK     :bit1;
  SDB_DCLK     :bit1;
  SRE_H264_VCLK:bit1;
  SRE_HEVC_VCLK:bit1;
  SIT_H264_DCLK:bit1;
  SIT_HEVC_DCLK:bit1;
  SCM_H264_DCLK:bit1;
  SCM_HEVC_DCLK:bit1;
  SDB_H264_DCLK:bit1;
  SDB_HEVC_DCLK:bit1;
  SCLR_DCLK    :bit1;
  UVD_SC       :bit1;
  RESERVED0    :bit16;
 end;

 TVDDGFX_IDLE_CONTROL=bitpacked record
  VDDGFX_IDLE_EN        :bit1;
  VDDGFX_IDLE_DETECT    :bit1;
  FORCE_VDDGFX_IDLE_EXIT:bit1;
  SMC_VDDGFX_IDLE_STATE :bit1;
  RESERVED0             :bit28;
 end;

 TVGA25_PPLL_POST_DIV=bitpacked record
  VGA25_PPLL_POST_DIV_PIXCLK:bit7;
  RESERVED0                 :bit1;
  VGA25_PPLL_POST_DIV_DVOCLK:bit7;
  RESERVED1                 :bit1;
  VGA25_PPLL_POST_DIV_IDCLK :bit7;
  RESERVED2                 :bit9;
 end;

 TVGA28_PPLL_POST_DIV=bitpacked record
  VGA28_PPLL_POST_DIV_PIXCLK:bit7;
  RESERVED0                 :bit1;
  VGA28_PPLL_POST_DIV_DVOCLK:bit7;
  RESERVED1                 :bit1;
  VGA28_PPLL_POST_DIV_IDCLK :bit7;
  RESERVED2                 :bit9;
 end;

 TVGA41_PPLL_POST_DIV=bitpacked record
  VGA41_PPLL_POST_DIV_PIXCLK:bit7;
  RESERVED0                 :bit1;
  VGA41_PPLL_POST_DIV_DVOCLK:bit7;
  RESERVED1                 :bit1;
  VGA41_PPLL_POST_DIV_IDCLK :bit7;
  RESERVED2                 :bit9;
 end;

 TVGA_TEST_DEBUG_DATA=bit32;

 TVGT_EVENT_INITIATOR=bitpacked record
  EVENT_TYPE    :bit6;
  RESERVED0     :bit12;
  ADDRESS_HI    :bit9;
  EXTENDED_EVENT:bit1;
  RESERVED1     :bit4;
 end;

 TVGT_GROUP_PRIM_TYPE=bitpacked record
  PRIM_TYPE   :bit5;
  RESERVED0   :bit9;
  RETAIN_ORDER:bit1;
  RETAIN_QUADS:bit1;
  PRIM_ORDER  :bit3;
  RESERVED1   :bit13;
 end;

 TVGT_GS_INSTANCE_CNT=bitpacked record
  ENABLE   :bit1;
  RESERVED0:bit1;
  CNT      :bit7;
  RESERVED1:bit23;
 end;

 TVGT_GS_MAX_VERT_OUT=bitpacked record
  MAX_VERT_OUT:bit11;
  RESERVED0   :bit21;
 end;

 TVGT_GS_VERTEX_REUSE=bitpacked record
  VERT_REUSE:bit5;
  RESERVED0 :bit27;
 end;

 TVGT_HOS_REUSE_DEPTH=bitpacked record
  REUSE_DEPTH:bit8;
  RESERVED0  :bit24;
 end;

 TVGT_LAST_COPY_STATE=bitpacked record
  SRC_STATE_ID:bit3;
  RESERVED0   :bit13;
  DST_STATE_ID:bit3;
  RESERVED1   :bit13;
 end;

 TVGT_PERFCOUNTER0_HI=bit32;

 TVGT_PERFCOUNTER0_LO=bit32;

 TVGT_PERFCOUNTER1_HI=bit32;

 TVGT_PERFCOUNTER1_LO=bit32;

 TVGT_PERFCOUNTER2_HI=bit32;

 TVGT_PERFCOUNTER2_LO=bit32;

 TVGT_PERFCOUNTER3_HI=bit32;

 TVGT_PERFCOUNTER3_LO=bit32;

 TVM_CONTEXTS_DISABLE=bitpacked record
  DISABLE_CONTEXT_0 :bit1;
  DISABLE_CONTEXT_1 :bit1;
  DISABLE_CONTEXT_2 :bit1;
  DISABLE_CONTEXT_3 :bit1;
  DISABLE_CONTEXT_4 :bit1;
  DISABLE_CONTEXT_5 :bit1;
  DISABLE_CONTEXT_6 :bit1;
  DISABLE_CONTEXT_7 :bit1;
  DISABLE_CONTEXT_8 :bit1;
  DISABLE_CONTEXT_9 :bit1;
  DISABLE_CONTEXT_10:bit1;
  DISABLE_CONTEXT_11:bit1;
  DISABLE_CONTEXT_12:bit1;
  DISABLE_CONTEXT_13:bit1;
  DISABLE_CONTEXT_14:bit1;
  DISABLE_CONTEXT_15:bit1;
  RESERVED0         :bit16;
 end;

 TXDMA_MEM_POWER_CNTL=bitpacked record
  XDMA_MEM_CORE_IDLE_STATE:bit2;
  XDMA_MEM_IF_IDLE_STATE  :bit2;
  RESERVED0               :bit15;
  XDMA_MEM_IF_PCIE_STATE  :bit2;
  XDMA_MEM_IF_PCIE_TRANS  :bit1;
  XDMA_MEM_IF_RD_STATE    :bit2;
  RESERVED1               :bit1;
  XDMA_MEM_IF_RD_TRANS    :bit1;
  XDMA_MEM_IF_WR_STATE    :bit2;
  XDMA_MEM_IF_WR_TRANS    :bit1;
  XDMA_MEM_IF_BIF_STATE   :bit2;
  XDMA_MEM_IF_BIF_TRANS   :bit1;
 end;

 TXDMA_MSTR_PIPE_CNTL=bitpacked record
  XDMA_MSTR_CACHE_LINES       :bit8;
  XDMA_MSTR_READ_REQUEST      :bit1;
  XDMA_MSTR_PIPE_FRAME_MODE   :bit1;
  XDMA_MSTR_PIPE_SOFT_RESET   :bit1;
  XDMA_MSTR_CACHE_INVALIDATE  :bit1;
  XDMA_MSTR_REQUEST_CHANNEL_ID:bit3;
  XDMA_MSTR_FLIP_MODE         :bit1;
  XDMA_MSTR_REQUEST_MIN       :bit8;
  XDMA_MSTR_PIPE_ACTIVE       :bit1;
  XDMA_MSTR_PIPE_FLUSHING     :bit1;
  XDMA_MSTR_PIPE_FLIP_PENDING :bit1;
  XDMA_MSTR_VSYNC_GSL_ENABLE  :bit1;
  XDMA_MSTR_SUPERAA_ENABLE    :bit1;
  XDMA_MSTR_HSYNC_GSL_GROUP   :bit2;
  XDMA_MSTR_GSL_GROUP_MASTER  :bit1;
 end;

 TABM_TEST_DEBUG_INDEX=bitpacked record
  ABM_TEST_DEBUG_INDEX   :bit8;
  ABM_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TATC_PERFCOUNTER0_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TATC_PERFCOUNTER1_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TATC_PERFCOUNTER2_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TATC_PERFCOUNTER3_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TAUX_DPHY_RX_CONTROL0=bitpacked record
  RESERVED0                                :bit4;
  AUX_RX_START_WINDOW                      :bit3;
  RESERVED1                                :bit1;
  AUX_RX_RECEIVE_WINDOW                    :bit3;
  RESERVED2                                :bit1;
  AUX_RX_HALF_SYM_DETECT_LEN               :bit2;
  RESERVED3                                :bit2;
  AUX_RX_TRANSITION_FILTER_EN              :bit1;
  AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT:bit1;
  AUX_RX_ALLOW_BELOW_THRESHOLD_START       :bit1;
  AUX_RX_ALLOW_BELOW_THRESHOLD_STOP        :bit1;
  AUX_RX_PHASE_DETECT_LEN                  :bit2;
  RESERVED4                                :bit2;
  AUX_RX_TIMEOUT_LEN                       :bit3;
  RESERVED5                                :bit1;
  AUX_RX_DETECTION_THRESHOLD               :bit3;
  RESERVED6                                :bit1;
 end;

 TAUX_DPHY_RX_CONTROL1=bitpacked record
  AUX_RX_PRECHARGE_SKIP:bit8;
  RESERVED0            :bit24;
 end;

 TAUX_GTC_SYNC_CONTROL=bitpacked record
  AUX_GTC_SYNC_EN                     :bit1;
  RESERVED0                           :bit3;
  AUX_GTC_SYNC_IMPCAL_EN              :bit1;
  RESERVED1                           :bit3;
  AUX_GTC_SYNC_IMPCAL_INTERVAL        :bit4;
  AUX_GTC_SYNC_LOCK_ACQ_PERIOD        :bit4;
  AUX_GTC_SYNC_LOCK_MAINT_PERIOD      :bit3;
  RESERVED2                           :bit1;
  AUX_GTC_SYNC_BLOCK_REQ              :bit1;
  RESERVED3                           :bit1;
  AUX_GTC_SYNC_INTERVAL_RESET_WINDOW  :bit2;
  AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT:bit2;
  RESERVED4                           :bit2;
  AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT   :bit4;
 end;

 TAUX_TEST_DEBUG_INDEX=bitpacked record
  AUX_TEST_DEBUG_INDEX   :bit8;
  AUX_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TAVSYNC_COUNTER_WRITE=bit32;

 TAZALIA_CRC0_CHANNEL0=bit32;

 TAZALIA_CRC0_CHANNEL1=bit32;

 TAZALIA_CRC0_CHANNEL2=bit32;

 TAZALIA_CRC0_CHANNEL3=bit32;

 TAZALIA_CRC0_CHANNEL4=bit32;

 TAZALIA_CRC0_CHANNEL5=bit32;

 TAZALIA_CRC0_CHANNEL6=bit32;

 TAZALIA_CRC0_CHANNEL7=bit32;

 TAZALIA_CRC0_CONTROL0=bitpacked record
  CRC_EN          :bit1;
  RESERVED0       :bit3;
  CRC_BLOCK_MODE  :bit1;
  RESERVED1       :bit3;
  CRC_INSTANCE_SEL:bit3;
  RESERVED2       :bit1;
  CRC_SOURCE_SEL  :bit1;
  RESERVED3       :bit19;
 end;

 TAZALIA_CRC0_CONTROL1=bit32;

 TAZALIA_CRC0_CONTROL2=bitpacked record
  CRC_BLOCK_ITERATION:bit16;
  RESERVED0          :bit16;
 end;

 TAZALIA_CRC0_CONTROL3=bitpacked record
  CRC_COMPLETE            :bit1;
  RESERVED0               :bit3;
  CRC_BLOCK_COMPLETE_PHASE:bit1;
  RESERVED1               :bit3;
  CRC_CHANNEL_RESULT_SEL  :bit3;
  RESERVED2               :bit21;
 end;

 TAZALIA_CRC1_CHANNEL0=bit32;

 TAZALIA_CRC1_CHANNEL1=bit32;

 TAZALIA_CRC1_CHANNEL2=bit32;

 TAZALIA_CRC1_CHANNEL3=bit32;

 TAZALIA_CRC1_CHANNEL4=bit32;

 TAZALIA_CRC1_CHANNEL5=bit32;

 TAZALIA_CRC1_CHANNEL6=bit32;

 TAZALIA_CRC1_CHANNEL7=bit32;

 TAZALIA_CRC1_CONTROL0=bitpacked record
  CRC_EN          :bit1;
  RESERVED0       :bit3;
  CRC_BLOCK_MODE  :bit1;
  RESERVED1       :bit3;
  CRC_INSTANCE_SEL:bit3;
  RESERVED2       :bit1;
  CRC_SOURCE_SEL  :bit1;
  RESERVED3       :bit19;
 end;

 TAZALIA_CRC1_CONTROL1=bit32;

 TAZALIA_CRC1_CONTROL2=bitpacked record
  CRC_BLOCK_ITERATION:bit16;
  RESERVED0          :bit16;
 end;

 TAZALIA_CRC1_CONTROL3=bitpacked record
  CRC_COMPLETE            :bit1;
  RESERVED0               :bit3;
  CRC_BLOCK_COMPLETE_PHASE:bit1;
  RESERVED1               :bit3;
  CRC_CHANNEL_RESULT_SEL  :bit3;
  RESERVED2               :bit21;
 end;

 TBIF_BACO_DEBUG_LATCH=bitpacked record
  BIF_BACO_LATCH_FLG:bit1;
  RESERVED0         :bit31;
 end;

 TBIF_DEVFUNCNUM_LIST0=bitpacked record
  DEVFUNC_ID0:bit8;
  DEVFUNC_ID1:bit8;
  DEVFUNC_ID2:bit8;
  DEVFUNC_ID3:bit8;
 end;

 TBIF_DEVFUNCNUM_LIST1=bitpacked record
  DEVFUNC_ID4:bit8;
  DEVFUNC_ID5:bit8;
  DEVFUNC_ID6:bit8;
  DEVFUNC_ID7:bit8;
 end;

 TBIF_DOORBELL_APER_EN=bitpacked record
  BIF_DOORBELL_APER_EN:bit1;
  RESERVED0           :bit31;
 end;

 TBIF_IMPCTL_TXCNTL_pd=bitpacked record
  TX_ADJUST_pd          :bit3;
  TX_BIAS_HIGH_pd       :bit1;
  RESERVED0             :bit4;
  LOWER_TX_ADJ_THRESH_pd:bit4;
  LOWER_TX_ADJ_pd       :bit1;
  UPPER_TX_ADJ_THRESH_pd:bit4;
  UPPER_TX_ADJ_pd       :bit1;
  TX_IMP_LOCKED_pd      :bit1;
  TX_IMP_READBACK_SEL_pd:bit1;
  TX_IMP_READBACK_pd    :bit4;
  RESERVED1             :bit4;
  TX_CMP_AMBIG_pd       :bit1;
  RESERVED2             :bit3;
 end;

 TBIF_IMPCTL_TXCNTL_pu=bitpacked record
  TX_ADJUST_pu          :bit3;
  TX_BIAS_HIGH_pu       :bit1;
  RESERVED0             :bit4;
  LOWER_TX_ADJ_THRESH_pu:bit4;
  LOWER_TX_ADJ_pu       :bit1;
  UPPER_TX_ADJ_THRESH_pu:bit4;
  UPPER_TX_ADJ_pu       :bit1;
  TX_IMP_LOCKED_pu      :bit1;
  TX_IMP_READBACK_SEL_pu:bit1;
  TX_IMP_READBACK_pu    :bit4;
  RESERVED1             :bit4;
  TX_CMP_AMBIG_pu       :bit1;
  RESERVED2             :bit3;
 end;

 TBIF_RFE_SOFTRST_CNTL=bitpacked record
  REG_RST_rstTimer     :bit16;
  RESERVED0            :bit14;
  REG_RST_softRstPropEn:bit1;
  SoftRstReg           :bit1;
 end;

 TBIF_RFE_WARMRST_CNTL=bitpacked record
  REG_RST_warmRstRfeEn:bit1;
  REG_RST_warmRstImpEn:bit1;
  RESERVED0           :bit30;
 end;

 TBLND_TEST_DEBUG_DATA=bit32;

 TBL_PWM_GRP1_REG_LOCK=bitpacked record
  BL_PWM_GRP1_REG_LOCK                :bit1;
  RESERVED0                           :bit7;
  BL_PWM_GRP1_REG_UPDATE_PENDING      :bit1;
  RESERVED1                           :bit7;
  BL_PWM_GRP1_UPDATE_AT_FRAME_START   :bit1;
  BL_PWM_GRP1_FRAME_START_DISP_SEL    :bit3;
  RESERVED2                           :bit4;
  BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN:bit1;
  RESERVED3                           :bit6;
  BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN   :bit1;
 end;

 TBPHYC_DAC_MACRO_CNTL=bitpacked record
  BPHYC_DAC_WHITE_LEVEL       :bit2;
  RESERVED0                   :bit6;
  BPHYC_DAC_WHITE_FINE_CONTROL:bit6;
  RESERVED1                   :bit2;
  BPHYC_DAC_BANDGAP_ADJUSTMENT:bit6;
  RESERVED2                   :bit2;
  BPHYC_DAC_ANALOG_MONITOR    :bit4;
  BPHYC_DAC_COREMON           :bit1;
  RESERVED3                   :bit3;
 end;

 TCC_SYS_RB_REDUNDANCY=bitpacked record
  RESERVED0     :bit1;
  RESERVED1     :bit7;
  FAILED_RB0    :bit4;
  EN_REDUNDANCY0:bit1;
  RESERVED2     :bit3;
  FAILED_RB1    :bit4;
  EN_REDUNDANCY1:bit1;
  RESERVED3     :bit11;
 end;

 TCGTS_CU1_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU2_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU3_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU5_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU6_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU7_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU9_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCG_DISPLAY_GAP_CNTL2=bit32;

 TCG_MULT_THERMAL_CTRL=bitpacked record
  TS_FILTER        :bit4;
  UNUSED           :bit5;
  THERMAL_RANGE_RST:bit1;
  RESERVED0        :bit10;
  TEMP_SEL         :bit8;
  THM_READY_CLEAR  :bit1;
  RESERVED1        :bit3;
 end;

 TCLKREQB_PERF_COUNTER=bit32;

 TCNV_TEST_DEBUG_INDEX=bitpacked record
  CNV_TEST_DEBUG_INDEX   :bit8;
  CNV_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TCOHER_DEST_BASE_HI_0=bit32;

 TCOHER_DEST_BASE_HI_1=bit32;

 TCOHER_DEST_BASE_HI_2=bit32;

 TCOHER_DEST_BASE_HI_3=bit32;

 TCOMPUTE_NUM_THREAD_X=bitpacked record
  NUM_THREAD_FULL   :bit16;
  NUM_THREAD_PARTIAL:bit16;
 end;

 TCOMPUTE_NUM_THREAD_Y=bitpacked record
  NUM_THREAD_FULL   :bit16;
  NUM_THREAD_PARTIAL:bit16;
 end;

 TCOMPUTE_NUM_THREAD_Z=bitpacked record
  NUM_THREAD_FULL   :bit16;
  NUM_THREAD_PARTIAL:bit16;
 end;

 TCOMPUTE_TMPRING_SIZE=bitpacked record
  WAVES    :bit12;
  WAVESIZE :bit13;
  RESERVED0:bit7;
 end;

 TCOMPUTE_USER_DATA_10=bit32;

 TCOMPUTE_USER_DATA_11=bit32;

 TCOMPUTE_USER_DATA_12=bit32;

 TCOMPUTE_USER_DATA_13=bit32;

 TCOMPUTE_USER_DATA_14=bit32;

 TCOMPUTE_USER_DATA_15=bit32;

 TCONFIG_REG_APER_SIZE=bitpacked record
  REG_APER_SIZE:bit20;
  RESERVED0    :bit12;
 end;

 TCP_COHER_START_DELAY=bitpacked record
  START_DELAY_COUNT:bit6;
  RESERVED0        :bit26;
 end;

 TCP_CPC_SCRATCH_INDEX=bitpacked record
  SCRATCH_INDEX:bit9;
  RESERVED0    :bit23;
 end;

 TCP_CPC_STALLED_STAT1=bitpacked record
  MIU_RDREQ_FREE_STALL   :bit1;
  MIU_WRREQ_FREE_STALL   :bit1;
  RESERVED0              :bit1;
  RCIU_TX_FREE_STALL     :bit1;
  RCIU_PRIV_VIOLATION    :bit1;
  RESERVED1              :bit1;
  TCIU_TX_FREE_STALL     :bit1;
  RESERVED2              :bit1;
  MEC1_DECODING_PACKET   :bit1;
  MEC1_WAIT_ON_RCIU      :bit1;
  MEC1_WAIT_ON_RCIU_READ :bit1;
  MEC1_WAIT_ON_MC_READ   :bit1;
  MEC1_WAIT_ON_MC_WR_ACK :bit1;
  MEC1_WAIT_ON_ROQ_DATA  :bit1;
  RESERVED3              :bit2;
  MEC2_DECODING_PACKET   :bit1;
  MEC2_WAIT_ON_RCIU      :bit1;
  MEC2_WAIT_ON_RCIU_READ :bit1;
  MEC2_WAIT_ON_MC_READ   :bit1;
  MEC2_WAIT_ON_MC_WR_ACK :bit1;
  MEC2_WAIT_ON_ROQ_DATA  :bit1;
  ATCL2IU_WAITING_ON_FREE:bit1;
  ATCL2IU_WAITING_ON_TAGS:bit1;
  ATCL1_WAITING_ON_TRANS :bit1;
  RESERVED4              :bit7;
 end;

 TCP_CPF_STALLED_STAT1=bitpacked record
  RING_FETCHING_DATA       :bit1;
  INDR1_FETCHING_DATA      :bit1;
  INDR2_FETCHING_DATA      :bit1;
  STATE_FETCHING_DATA      :bit1;
  MIU_WAITING_ON_RDREQ_FREE:bit1;
  TCIU_WAITING_ON_FREE     :bit1;
  TCIU_WAITING_ON_TAGS     :bit1;
  ATCL2IU_WAITING_ON_FREE  :bit1;
  ATCL2IU_WAITING_ON_TAGS  :bit1;
  ATCL1_WAITING_ON_TRANS   :bit1;
  RESERVED0                :bit22;
 end;

 TCP_EOP_LAST_FENCE_HI=bit32;

 TCP_EOP_LAST_FENCE_LO=bit32;

 TCP_HQD_CTX_SAVE_SIZE=bitpacked record
  RESERVED0:bit12;
  SIZE     :bit13;
  RESERVED1:bit7;
 end;

 TCP_HQD_EOP_BASE_ADDR=bit32;

 TCP_HQD_HQ_SCHEDULER0=bit32;

 TCP_HQD_HQ_SCHEDULER1=bit32;

 TCP_HQD_PIPE_PRIORITY=bitpacked record
  PIPE_PRIORITY:bit2;
  RESERVED0    :bit30;
 end;

 TCP_MEQ_STQ_THRESHOLD=bitpacked record
  STQ_START:bit8;
  RESERVED0:bit24;
 end;

 TCP_PA_CPRIM_COUNT_HI=bit32;

 TCP_PA_CPRIM_COUNT_LO=bit32;

 TCP_PERFMON_CNTX_CNTL=bitpacked record
  RESERVED0     :bit31;
  PERFMON_ENABLE:bit1;
 end;

 TCP_PFP_F32_INTERRUPT=bitpacked record
  RESERVED0   :bit1;
  PRIV_REG_INT:bit1;
  RESERVED1   :bit1;
  RESERVED2   :bit1;
  RESERVED3   :bit28;
 end;

 TCP_PQ_WPTR_POLL_CNTL=bitpacked record
  PERIOD     :bit8;
  RESERVED0  :bit22;
  POLL_ACTIVE:bit1;
  EN         :bit1;
 end;

 TCP_RB_WPTR_POLL_CNTL=bitpacked record
  POLL_FREQUENCY :bit16;
  IDLE_POLL_COUNT:bit16;
 end;

 TCRTC_BLACK_COLOR_EXT=bitpacked record
  CRTC_BLACK_COLOR_B_CB_EXT:bit2;
  RESERVED0                :bit6;
  CRTC_BLACK_COLOR_G_Y_EXT :bit2;
  RESERVED1                :bit6;
  CRTC_BLACK_COLOR_R_CR_EXT:bit2;
  RESERVED2                :bit14;
 end;

 TCRTC_SNAPSHOT_STATUS=bitpacked record
  CRTC_SNAPSHOT_OCCURRED      :bit1;
  CRTC_SNAPSHOT_CLEAR         :bit1;
  CRTC_SNAPSHOT_MANUAL_TRIGGER:bit1;
  RESERVED0                   :bit29;
 end;

 TCRTC_STATUS_HV_COUNT=bitpacked record
  CRTC_HV_COUNT:bit30;
  RESERVED0    :bit2;
 end;

 TCRTC_STATUS_POSITION=bitpacked record
  CRTC_VERT_COUNT:bit14;
  RESERVED0      :bit2;
  CRTC_HORZ_COUNT:bit14;
  RESERVED1      :bit2;
 end;

 TCRTC_STATUS_VF_COUNT=bitpacked record
  CRTC_VF_COUNT:bit30;
  RESERVED0    :bit2;
 end;

 TCRTC_TEST_DEBUG_DATA=bit32;

 TCRTC_V_TOTAL_CONTROL=bitpacked record
  CRTC_V_TOTAL_MIN_SEL           :bit1;
  RESERVED0                      :bit3;
  CRTC_V_TOTAL_MAX_SEL           :bit1;
  RESERVED1                      :bit3;
  CRTC_FORCE_LOCK_ON_EVENT       :bit1;
  RESERVED2                      :bit3;
  CRTC_FORCE_LOCK_TO_MASTER_VSYNC:bit1;
  RESERVED3                      :bit2;
  CRTC_SET_V_TOTAL_MIN_MASK_EN   :bit1;
  CRTC_SET_V_TOTAL_MIN_MASK      :bit16;
 end;

 TCUR2_SURFACE_ADDRESS=bit32;

 TDAC_CRC_SIG_RGB_MASK=bitpacked record
  DAC_CRC_SIG_BLUE_MASK :bit10;
  DAC_CRC_SIG_GREEN_MASK:bit10;
  DAC_CRC_SIG_RED_MASK  :bit10;
  RESERVED0             :bit2;
 end;

 TDAC_TEST_DEBUG_INDEX=bitpacked record
  DAC_TEST_DEBUG_INDEX   :bit8;
  DAC_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TDB_STENCILREFMASK_BF=bitpacked record
  STENCILTESTVAL_BF  :bit8;
  STENCILMASK_BF     :bit8;
  STENCILWRITEMASK_BF:bit8;
  STENCILOPVAL_BF    :bit8;
 end;

 TDB_STENCIL_READ_BASE=bit32;

 TDCCG_TEST_DEBUG_DATA=bit32;

 TDCDEBUG_BUS_CLK1_SEL=bit32;

 TDCDEBUG_BUS_CLK2_SEL=bit32;

 TDCDEBUG_BUS_CLK3_SEL=bit32;

 TDCDEBUG_BUS_CLK4_SEL=bit32;

 TDCDEBUG_BUS_CLK5_SEL=bit32;

 TDCIO_TEST_DEBUG_DATA=bit32;

 TDCI_TEST_DEBUG_INDEX=bitpacked record
  DCI_TEST_DEBUG_INDEX   :bit8;
  DCI_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TDCO_TEST_DEBUG_INDEX=bitpacked record
  DCO_TEST_DEBUG_INDEX   :bit8;
  DCO_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TDCPG_TEST_DEBUG_DATA=bit32;

 TDCP_TEST_DEBUG_INDEX=bitpacked record
  DCP_TEST_DEBUG_INDEX   :bit8;
  DCP_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TDC_ABM1_ACE_THRES_12=bitpacked record
  ABM1_ACE_THRES_1:bit10;
  RESERVED0       :bit6;
  ABM1_ACE_THRES_2:bit10;
  RESERVED1       :bit5;
  ABM1_ACE_LOCK   :bit1;
 end;

 TDC_ABM1_ACE_THRES_34=bitpacked record
  ABM1_ACE_THRES_3                 :bit10;
  RESERVED0                        :bit6;
  ABM1_ACE_THRES_4                 :bit10;
  RESERVED1                        :bit2;
  ABM1_ACE_IGNORE_MASTER_LOCK_EN   :bit1;
  ABM1_ACE_READBACK_DB_REG_VALUE_EN:bit1;
  ABM1_ACE_DBUF_REG_UPDATE_PENDING :bit1;
  ABM1_ACE_LOCK                    :bit1;
 end;

 TDC_ABM1_HG_MISC_CTRL=bitpacked record
  ABM1_HG_NUM_OF_BINS_SEL                 :bit2;
  RESERVED0                               :bit6;
  ABM1_HG_VMAX_SEL                        :bit1;
  RESERVED1                               :bit3;
  ABM1_HG_FINE_MODE_BIN_SEL               :bit1;
  RESERVED2                               :bit3;
  ABM1_HG_BIN_BITWIDTH_SIZE_SEL           :bit2;
  RESERVED3                               :bit2;
  ABM1_OVR_SCAN_PIXEL_PROCESS_EN          :bit1;
  RESERVED4                               :bit2;
  ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN :bit1;
  ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL :bit3;
  RESERVED5                               :bit1;
  ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START:bit1;
  ABM1_HGLS_IGNORE_MASTER_LOCK_EN         :bit1;
  ABM1_DBUF_HGLS_REG_UPDATE_PENDING       :bit1;
  ABM1_HGLS_REG_LOCK                      :bit1;
 end;

 TDC_ABM1_HG_RESULT_10=bit32;

 TDC_ABM1_HG_RESULT_11=bit32;

 TDC_ABM1_HG_RESULT_12=bit32;

 TDC_ABM1_HG_RESULT_13=bit32;

 TDC_ABM1_HG_RESULT_14=bit32;

 TDC_ABM1_HG_RESULT_15=bit32;

 TDC_ABM1_HG_RESULT_16=bit32;

 TDC_ABM1_HG_RESULT_17=bit32;

 TDC_ABM1_HG_RESULT_18=bit32;

 TDC_ABM1_HG_RESULT_19=bit32;

 TDC_ABM1_HG_RESULT_20=bit32;

 TDC_ABM1_HG_RESULT_21=bit32;

 TDC_ABM1_HG_RESULT_22=bit32;

 TDC_ABM1_HG_RESULT_23=bit32;

 TDC_ABM1_HG_RESULT_24=bit32;

 TDC_GPIO_DVODATA_MASK=bitpacked record
  DC_GPIO_DVODATA_MASK    :bit24;
  DC_GPIO_DVOCNTL_MASK    :bit5;
  DC_GPIO_DVOCLK_MASK     :bit1;
  DC_GPIO_MVP_DVOCNTL_MASK:bit2;
 end;

 TDC_GPIO_GENERIC_MASK=bitpacked record
  DC_GPIO_GENERICA_MASK  :bit1;
  DC_GPIO_GENERICA_PD_DIS:bit1;
  DC_GPIO_GENERICA_RECV  :bit1;
  RESERVED0              :bit1;
  DC_GPIO_GENERICB_MASK  :bit1;
  DC_GPIO_GENERICB_PD_DIS:bit1;
  DC_GPIO_GENERICB_RECV  :bit1;
  RESERVED1              :bit1;
  DC_GPIO_GENERICC_MASK  :bit1;
  DC_GPIO_GENERICC_PD_DIS:bit1;
  DC_GPIO_GENERICC_RECV  :bit1;
  RESERVED2              :bit1;
  DC_GPIO_GENERICD_MASK  :bit1;
  DC_GPIO_GENERICD_PD_DIS:bit1;
  DC_GPIO_GENERICD_RECV  :bit1;
  RESERVED3              :bit1;
  DC_GPIO_GENERICE_MASK  :bit1;
  DC_GPIO_GENERICE_PD_DIS:bit1;
  DC_GPIO_GENERICE_RECV  :bit1;
  RESERVED4              :bit1;
  DC_GPIO_GENERICF_MASK  :bit1;
  DC_GPIO_GENERICF_PD_DIS:bit1;
  DC_GPIO_GENERICF_RECV  :bit1;
  RESERVED5              :bit1;
  DC_GPIO_GENERICG_MASK  :bit1;
  DC_GPIO_GENERICG_PD_DIS:bit1;
  DC_GPIO_GENERICG_RECV  :bit1;
  RESERVED6              :bit5;
 end;

 TDC_LUT_WRITE_EN_MASK=bitpacked record
  DC_LUT_WRITE_EN_MASK:bit3;
  RESERVED0           :bit29;
 end;

 TDC_PGCNTL_STATUS_REG=bitpacked record
  SWREQ_RWOP_BUSY    :bit1;
  SWREQ_RWOP_FORCE   :bit1;
  IPREQ_IGNORE_STATUS:bit1;
  RESERVED0          :bit13;
  DCPG_ECO_DEBUG     :bit16;
 end;

 TDENORM_CLAMP_CONTROL=bitpacked record
  DENORM_FACTOR:bit2;
  RESERVED0    :bit30;
 end;

 TDENTIST_DISPCLK_CNTL=bitpacked record
  DENTIST_DISPCLK_WDIVIDER :bit7;
  RESERVED0                :bit1;
  DENTIST_DISPCLK_RDIVIDER :bit7;
  DENTIST_DISPCLK_CHG_MODE :bit2;
  DENTIST_DISPCLK_CHGTOG   :bit1;
  DENTIST_DISPCLK_DONETOG  :bit1;
  DENTIST_DISPCLK_CHG_DONE :bit1;
  DENTIST_DPREFCLK_CHG_DONE:bit1;
  DENTIST_DPREFCLK_CHGTOG  :bit1;
  DENTIST_DPREFCLK_DONETOG :bit1;
  RESERVED1                :bit1;
  DENTIST_DPREFCLK_WDIVIDER:bit7;
  RESERVED2                :bit1;
 end;

 TDIG_TEST_DEBUG_INDEX=bitpacked record
  DIG_TEST_DEBUG_INDEX   :bit8;
  DIG_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TDMCU_RAM_ACCESS_CTRL=bitpacked record
  ERAM_WR_ADDR_AUTO_INC   :bit1;
  ERAM_RD_ADDR_AUTO_INC   :bit1;
  IRAM_WR_ADDR_AUTO_INC   :bit1;
  IRAM_RD_ADDR_AUTO_INC   :bit1;
  ERAM_HOST_ACCESS_EN     :bit1;
  IRAM_HOST_ACCESS_EN     :bit1;
  RESERVED0               :bit2;
  UC_RST_RELEASE_DELAY_CNT:bit8;
  RESERVED1               :bit16;
 end;

 TDMCU_TEST_DEBUG_DATA=bit32;

 TDMIF_TEST_DEBUG_DATA=bit32;

 TDOUT_TEST_DEBUG_DATA=bit32;

 TDPG_PIPE_DPM_CONTROL=bitpacked record
  DPM_ENABLE                :bit1;
  RESERVED0                 :bit3;
  MCLK_CHANGE_ENABLE        :bit1;
  RESERVED1                 :bit3;
  MCLK_CHANGE_FORCE_ON      :bit1;
  RESERVED2                 :bit3;
  MCLK_CHANGE_WATERMARK_MASK:bit2;
  RESERVED3                 :bit2;
  MCLK_CHANGE_WATERMARK     :bit16;
 end;

 TDPG_REPEATER_PROGRAM=bitpacked record
  REG_DPG_DMIFRC_REPEATER:bit3;
  RESERVED0              :bit1;
  REG_DMIFRC_DPG_REPEATER:bit3;
  RESERVED1              :bit25;
 end;

 TDPG_TEST_DEBUG_INDEX=bitpacked record
  DPG_TEST_DEBUG_INDEX   :bit8;
  DPG_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TDP_DPHY_CRC_MST_CNTL=bitpacked record
  DPHY_CRC_MST_FIRST_SLOT:bit6;
  RESERVED0              :bit2;
  DPHY_CRC_MST_LAST_SLOT :bit6;
  RESERVED1              :bit18;
 end;

 TDP_LINK_FRAMING_CNTL=bitpacked record
  DP_IDLE_BS_INTERVAL       :bit18;
  RESERVED0                 :bit6;
  DP_VBID_DISABLE           :bit1;
  RESERVED1                 :bit3;
  DP_VID_ENHANCED_FRAME_MODE:bit1;
  RESERVED2                 :bit3;
 end;

 TDVO_STRENGTH_CONTROL=bitpacked record
  DVO_SP                :bit4;
  DVO_SN                :bit4;
  DVOCLK_SP             :bit4;
  DVOCLK_SN             :bit4;
  DVO_DRVSTRENGTH       :bit3;
  RESERVED0             :bit1;
  DVOCLK_DRVSTRENGTH    :bit3;
  RESERVED1             :bit1;
  FLDO_VITNE_DRVSTRENGTH:bit3;
  RESERVED2             :bit1;
  DVO_LSB_VMODE         :bit1;
  DVO_MSB_VMODE         :bit1;
  RESERVED3             :bit2;
 end;

 TDVO_TEST_DEBUG_INDEX=bitpacked record
  DVO_TEST_DEBUG_INDEX   :bit8;
  DVO_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TFBC_START_STOP_DELAY=bitpacked record
  FBC_DECOMP_START_DELAY:bit5;
  RESERVED0             :bit2;
  FBC_DECOMP_STOP_DELAY :bit1;
  FBC_COMP_START_DELAY  :bit5;
  RESERVED1             :bit19;
 end;

 TFBC_TEST_DEBUG_INDEX=bitpacked record
  FBC_TEST_DEBUG_INDEX   :bit8;
  FBC_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TFMT_DYNAMIC_EXP_CNTL=bitpacked record
  FMT_DYNAMIC_EXP_EN  :bit1;
  RESERVED0           :bit3;
  FMT_DYNAMIC_EXP_MODE:bit1;
  RESERVED1           :bit27;
 end;

 TFMT_TEST_DEBUG_INDEX=bitpacked record
  FMT_TEST_DEBUG_INDEX   :bit8;
  FMT_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TGAMMA_CORR_LUT_INDEX=bitpacked record
  GAMMA_CORR_LUT_INDEX:bit9;
  RESERVED0           :bit23;
 end;

 TGC_CAC_CGTT_CLK_CTRL=bitpacked record
  ON_DELAY         :bit4;
  OFF_HYSTERESIS   :bit8;
  RESERVED0        :bit18;
  SOFT_OVERRIDE_DYN:bit1;
  SOFT_OVERRIDE_REG:bit1;
 end;

 TGDS_GFX_CTXSW_STATUS=bitpacked record
  R     :bit1;
  W     :bit1;
  UNUSED:bit30;
 end;

 TGDS_GWS_RESOURCE_CNT=bitpacked record
  RESOURCE_CNT:bit16;
  RESERVED0   :bit16;
 end;

 TGDS_PROTECTION_FAULT=bitpacked record
  WRITE_DIS     :bit1;
  FAULT_DETECTED:bit1;
  GRBM          :bit1;
  SH_ID         :bit3;
  CU_ID         :bit4;
  SIMD_ID       :bit2;
  WAVE_ID       :bit4;
  ADDRESS       :bit16;
 end;

 TGMCON_PERF_MON_CNTL0=bitpacked record
  START_THRESH      :bit12;
  STOP_THRESH       :bit12;
  START_MODE        :bit2;
  STOP_MODE         :bit2;
  ALLOW_WRAP        :bit1;
  THRESH_CNTR_ID_EXT:bit1;
  START_TRIG_ID_EXT :bit1;
  STOP_TRIG_ID_EXT  :bit1;
 end;

 TGMCON_PERF_MON_CNTL1=bitpacked record
  THRESH_CNTR_ID:bit6;
  START_TRIG_ID :bit6;
  STOP_TRIG_ID  :bit6;
  MON0_ID       :bit7;
  MON1_ID       :bit7;
 end;

 TGMCON_PERF_MON_RSLT0=bit32;

 TGMCON_PERF_MON_RSLT1=bit32;

 TGMCON_RENG_RAM_INDEX=bitpacked record
  RENG_RAM_INDEX:bit10;
  RESERVED0     :bit22;
 end;

 TGPIOPAD_INT_POLARITY=bitpacked record
  GPIO_INT_POLARITY        :bit29;
  RESERVED0                :bit2;
  SW_INITIATED_INT_POLARITY:bit1;
 end;

 TGPU_GARLIC_FLUSH_REQ=bitpacked record
  CP0      :bit1;
  CP1      :bit1;
  CP2      :bit1;
  CP3      :bit1;
  CP4      :bit1;
  CP5      :bit1;
  CP6      :bit1;
  CP7      :bit1;
  CP8      :bit1;
  CP9      :bit1;
  SDMA0    :bit1;
  SDMA1    :bit1;
  SDMA2    :bit1;
  SDMA3    :bit1;
  RESERVED0:bit18;
 end;

 TGRBM_PERFCOUNTER0_HI=bit32;

 TGRBM_PERFCOUNTER0_LO=bit32;

 TGRBM_PERFCOUNTER1_HI=bit32;

 TGRBM_PERFCOUNTER1_LO=bit32;

 TGRPH_STEREOSYNC_FLIP=bitpacked record
  GRPH_STEREOSYNC_FLIP_EN       :bit1;
  RESERVED0                     :bit7;
  GRPH_STEREOSYNC_FLIP_MODE     :bit2;
  RESERVED1                     :bit6;
  GRPH_PRIMARY_SURFACE_PENDING  :bit1;
  GRPH_SECONDARY_SURFACE_PENDING:bit1;
  RESERVED2                     :bit10;
  GRPH_STEREOSYNC_SELECT_DISABLE:bit1;
  RESERVED3                     :bit3;
 end;

 THDP_LAST_SURFACE_HIT=bitpacked record
  LAST_SURFACE_HIT:bit6;
  RESERVED0       :bit26;
 end;

 TLBV_BLACK_KEYER_B_CB=bitpacked record
  RESERVED0          :bit4;
  LB_BLACK_KEYER_B_CB:bit12;
  RESERVED1          :bit16;
 end;

 TLBV_BLACK_KEYER_R_CR=bitpacked record
  RESERVED0          :bit4;
  LB_BLACK_KEYER_R_CR:bit12;
  RESERVED1          :bit16;
 end;

 TLBV_KEYER_COLOR_B_CB=bitpacked record
  RESERVED0          :bit4;
  LB_KEYER_COLOR_B_CB:bit12;
  RESERVED1          :bit16;
 end;

 TLBV_KEYER_COLOR_CTRL=bitpacked record
  LB_KEYER_COLOR_EN    :bit1;
  RESERVED0            :bit7;
  LB_KEYER_COLOR_REP_EN:bit1;
  RESERVED1            :bit23;
 end;

 TLBV_KEYER_COLOR_R_CR=bitpacked record
  RESERVED0          :bit4;
  LB_KEYER_COLOR_R_CR:bit12;
  RESERVED1          :bit16;
 end;

 TLBV_TEST_DEBUG_INDEX=bitpacked record
  LB_TEST_DEBUG_INDEX   :bit8;
  LB_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0             :bit23;
 end;

 TLBV_VLINE2_START_END=bitpacked record
  VLINE2_START:bit14;
  RESERVED0   :bit2;
  VLINE2_END  :bit15;
  VLINE2_INV  :bit1;
 end;

 TLBV_V_COUNTER_CHROMA=bitpacked record
  V_COUNTER_CHROMA:bit15;
  RESERVED0       :bit17;
 end;

 TLCLK_DEEP_SLEEP_CNTL=bitpacked record
  DIV_ID    :bit3;
  RAMP_DIS  :bit1;
  HYSTERESIS:bit12;
  RESERVED0 :bit15;
  ENABLE_DS :bit1;
 end;

 TLVTMA_PWRSEQ_REF_DIV=bitpacked record
  LVTMA_PWRSEQ_REF_DIV:bit12;
  RESERVED0           :bit4;
  BL_PWM_REF_DIV      :bit16;
 end;

 TMASTER_COMM_CNTL_REG=bitpacked record
  MASTER_COMM_INTERRUPT:bit1;
  RESERVED0            :bit31;
 end;

 TMCIF_TEST_DEBUG_DATA=bit32;

 TMCIF_WB_BUF_1_ADDR_C=bit32;

 TMCIF_WB_BUF_1_ADDR_Y=bit32;

 TMCIF_WB_BUF_1_STATUS=bitpacked record
  MCIF_WB_BUF_1_ACTIVE            :bit1;
  MCIF_WB_BUF_1_SW_LOCKED         :bit1;
  MCIF_WB_BUF_1_VCE_LOCKED        :bit1;
  MCIF_WB_BUF_1_OVERFLOW          :bit1;
  MCIF_WB_BUF_1_DISABLE           :bit1;
  MCIF_WB_BUF_1_MODE              :bit3;
  MCIF_WB_BUF_1_BUFTAG            :bit4;
  MCIF_WB_BUF_1_NXT_BUF           :bit3;
  MCIF_WB_BUF_1_FIELD             :bit1;
  MCIF_WB_BUF_1_CUR_LINE_L        :bit13;
  MCIF_WB_BUF_1_LONG_LINE_ERROR   :bit1;
  MCIF_WB_BUF_1_SHORT_LINE_ERROR  :bit1;
  MCIF_WB_BUF_1_FRAME_LENGTH_ERROR:bit1;
 end;

 TMCIF_WB_BUF_2_ADDR_C=bit32;

 TMCIF_WB_BUF_2_ADDR_Y=bit32;

 TMCIF_WB_BUF_2_STATUS=bitpacked record
  MCIF_WB_BUF_2_ACTIVE            :bit1;
  MCIF_WB_BUF_2_SW_LOCKED         :bit1;
  MCIF_WB_BUF_2_VCE_LOCKED        :bit1;
  MCIF_WB_BUF_2_OVERFLOW          :bit1;
  MCIF_WB_BUF_2_DISABLE           :bit1;
  MCIF_WB_BUF_2_MODE              :bit3;
  MCIF_WB_BUF_2_BUFTAG            :bit4;
  MCIF_WB_BUF_2_NXT_BUF           :bit3;
  MCIF_WB_BUF_2_FIELD             :bit1;
  MCIF_WB_BUF_2_CUR_LINE_L        :bit13;
  MCIF_WB_BUF_2_LONG_LINE_ERROR   :bit1;
  MCIF_WB_BUF_2_SHORT_LINE_ERROR  :bit1;
  MCIF_WB_BUF_2_FRAME_LENGTH_ERROR:bit1;
 end;

 TMCIF_WB_BUF_3_ADDR_C=bit32;

 TMCIF_WB_BUF_3_ADDR_Y=bit32;

 TMCIF_WB_BUF_3_STATUS=bitpacked record
  MCIF_WB_BUF_3_ACTIVE            :bit1;
  MCIF_WB_BUF_3_SW_LOCKED         :bit1;
  MCIF_WB_BUF_3_VCE_LOCKED        :bit1;
  MCIF_WB_BUF_3_OVERFLOW          :bit1;
  MCIF_WB_BUF_3_DISABLE           :bit1;
  MCIF_WB_BUF_3_MODE              :bit3;
  MCIF_WB_BUF_3_BUFTAG            :bit4;
  MCIF_WB_BUF_3_NXT_BUF           :bit3;
  MCIF_WB_BUF_3_FIELD             :bit1;
  MCIF_WB_BUF_3_CUR_LINE_L        :bit13;
  MCIF_WB_BUF_3_LONG_LINE_ERROR   :bit1;
  MCIF_WB_BUF_3_SHORT_LINE_ERROR  :bit1;
  MCIF_WB_BUF_3_FRAME_LENGTH_ERROR:bit1;
 end;

 TMCIF_WB_BUF_4_ADDR_C=bit32;

 TMCIF_WB_BUF_4_ADDR_Y=bit32;

 TMCIF_WB_BUF_4_STATUS=bitpacked record
  MCIF_WB_BUF_4_ACTIVE            :bit1;
  MCIF_WB_BUF_4_SW_LOCKED         :bit1;
  MCIF_WB_BUF_4_VCE_LOCKED        :bit1;
  MCIF_WB_BUF_4_OVERFLOW          :bit1;
  MCIF_WB_BUF_4_DISABLE           :bit1;
  MCIF_WB_BUF_4_MODE              :bit3;
  MCIF_WB_BUF_4_BUFTAG            :bit4;
  MCIF_WB_BUF_4_NXT_BUF           :bit3;
  MCIF_WB_BUF_4_FIELD             :bit1;
  MCIF_WB_BUF_4_CUR_LINE_L        :bit13;
  MCIF_WB_BUF_4_LONG_LINE_ERROR   :bit1;
  MCIF_WB_BUF_4_SHORT_LINE_ERROR  :bit1;
  MCIF_WB_BUF_4_FRAME_LENGTH_ERROR:bit1;
 end;

 TMC_ARB_DRAM_TIMING_1=bitpacked record
  ACTRD    :bit8;
  ACTWR    :bit8;
  RASMACTRD:bit8;
  RASMACTWR:bit8;
 end;

 TMC_ARB_HARSH_SAT0_RD=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_HARSH_SAT0_WR=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_HARSH_SAT1_RD=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_ARB_HARSH_SAT1_WR=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_ARB_MAX_LAT_RSLT0=bit32;

 TMC_ARB_MAX_LAT_RSLT1=bit32;

 TMC_CITF_CREDITS_XBAR=bitpacked record
  READ_LCL :bit8;
  WRITE_LCL:bit8;
  RESERVED0:bit16;
 end;

 TMC_FUS_DRAM_APER_DEF=bitpacked record
  DEF                  :bit28;
  LOCK_MC_FUS_DRAM_REGS:bit1;
  RESERVED0            :bit3;
 end;

 TMC_FUS_DRAM_APER_TOP=bitpacked record
  TOP      :bit20;
  RESERVED0:bit12;
 end;

 TMC_HUB_MISC_OVERRIDE=bitpacked record
  IDLE     :bit2;
  RESERVED0:bit30;
 end;

 TMC_HUB_RDREQ_CREDITS=bitpacked record
  VM0  :bit8;
  VM1  :bit8;
  STOR0:bit8;
  STOR1:bit8;
 end;

 TMC_HUB_RDREQ_ISP_MPM=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_HUB_RDREQ_ISP_SPM=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_SEQ_CAS_TIMING_LP=bitpacked record
  TNOPW    :bit2;
  TNOPR    :bit2;
  TR2W     :bit5;
  TCCDL    :bit3;
  TR2R     :bit4;
  TW2R     :bit5;
  TCL      :bit5;
  RESERVED0:bit6;
 end;

 TMC_SEQ_IO_DEBUG_DATA=bit32;

 TMC_SEQ_PMG_TIMING_LP=bitpacked record
  TCKSRE     :bit3;
  TCKSRX     :bit3;
  TCKE_PULSE :bit5;
  TCKE       :bit8;
  SEQ_IDLE   :bit3;
  SEQ_IDLE_SS:bit8;
  RESERVED0  :bit2;
 end;

 TMC_SEQ_RAS_TIMING_LP=bitpacked record
  TRCDW    :bit5;
  TRCDWA   :bit5;
  TRCDR    :bit5;
  TRCDRA   :bit5;
  TRRD     :bit4;
  TRC      :bit7;
  RESERVED0:bit1;
 end;

 TMC_SEQ_TRAIN_CAPTURE=bitpacked record
  D0_IDLEH_WAKEUP       :bit1;
  D1_IDLEH_WAKEUP       :bit1;
  RESERVED0             :bit1;
  RESERVED1             :bit1;
  RESERVED2             :bit1;
  RESERVED3             :bit1;
  RESERVED4             :bit1;
  RESERVED5             :bit1;
  SCLK_SRBM_READY_WAKEUP:bit1;
  RESERVED6             :bit1;
  RESERVED7             :bit1;
  RESERVED8             :bit1;
  SOFTWARE_WAKEUP       :bit1;
  RESERVED9             :bit2;
  TIMER_DONE_WAKEUP     :bit1;
  RESERVED10            :bit1;
  RESERVED11            :bit1;
  RESERVED12            :bit1;
  RESERVED13            :bit1;
  RESERVED14            :bit1;
  RESERVED15            :bit1;
  RESERVED16            :bit1;
  RESERVED17            :bit1;
  RESERVED18            :bit1;
  RESERVED19            :bit1;
  RESERVED20            :bit1;
  RESERVED21            :bit1;
  RESERVED22            :bit4;
 end;

 TMC_VM_MARC_BASE_HI_0=bitpacked record
  MARC_BASE_HI_0:bit20;
  RESERVED0     :bit12;
 end;

 TMC_VM_MARC_BASE_HI_1=bitpacked record
  MARC_BASE_HI_1:bit20;
  RESERVED0     :bit12;
 end;

 TMC_VM_MARC_BASE_HI_2=bitpacked record
  MARC_BASE_HI_2:bit20;
  RESERVED0     :bit12;
 end;

 TMC_VM_MARC_BASE_HI_3=bitpacked record
  MARC_BASE_HI_3:bit20;
  RESERVED0     :bit12;
 end;

 TMC_VM_MARC_BASE_LO_0=bitpacked record
  RESERVED0     :bit12;
  MARC_BASE_LO_0:bit20;
 end;

 TMC_VM_MARC_BASE_LO_1=bitpacked record
  RESERVED0     :bit12;
  MARC_BASE_LO_1:bit20;
 end;

 TMC_VM_MARC_BASE_LO_2=bitpacked record
  RESERVED0     :bit12;
  MARC_BASE_LO_2:bit20;
 end;

 TMC_VM_MARC_BASE_LO_3=bitpacked record
  RESERVED0     :bit12;
  MARC_BASE_LO_3:bit20;
 end;

 TMC_VM_MX_L1_TLB_CNTL=bitpacked record
  ENABLE_L1_TLB                  :bit1;
  ENABLE_L1_FRAGMENT_PROCESSING  :bit1;
  RESERVED0                      :bit1;
  SYSTEM_ACCESS_MODE             :bit2;
  SYSTEM_APERTURE_UNMAPPED_ACCESS:bit1;
  ENABLE_ADVANCED_DRIVER_MODEL   :bit1;
  ECO_BITS                       :bit4;
  RESERVED1                      :bit21;
 end;

 TMC_XBAR_RDREQ_CREDIT=bitpacked record
  OUT0:bit8;
  OUT1:bit8;
  OUT2:bit8;
  OUT3:bit8;
 end;

 TMC_XBAR_WRREQ_CREDIT=bitpacked record
  OUT0:bit8;
  OUT1:bit8;
  OUT2:bit8;
  OUT3:bit8;
 end;

 TMC_XPB_P2P_BAR_DEBUG=bitpacked record
  SEL        :bit8;
  HOST_FLUSH :bit4;
  MEM_SYS_BAR:bit4;
  RESERVED0  :bit16;
 end;

 TMC_XPB_P2P_BAR_SETUP=bitpacked record
  SEL         :bit8;
  REG_SYS_BAR :bit4;
  VALID       :bit1;
  SEND_DIS    :bit1;
  COMPRESS_DIS:bit1;
  RESERVED    :bit1;
  ADDRESS     :bit16;
 end;

 TMC_XPB_PEER_SYS_BAR0=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_PEER_SYS_BAR1=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_PEER_SYS_BAR2=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_PEER_SYS_BAR3=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_PEER_SYS_BAR4=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_PEER_SYS_BAR5=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_PEER_SYS_BAR6=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_PEER_SYS_BAR7=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_PEER_SYS_BAR8=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_PEER_SYS_BAR9=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_RTR_DEST_MAP0=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_RTR_DEST_MAP1=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_RTR_DEST_MAP2=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_RTR_DEST_MAP3=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_RTR_DEST_MAP4=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_RTR_DEST_MAP5=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_RTR_DEST_MAP6=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_RTR_DEST_MAP7=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_RTR_DEST_MAP8=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_RTR_DEST_MAP9=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMVP_TEST_DEBUG_INDEX=bitpacked record
  MVP_TEST_DEBUG_INDEX   :bit8;
  MVP_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TOUTPUT_CSC_C11_C12_A=bitpacked record
  OUTPUT_CSC_C11_A:bit16;
  OUTPUT_CSC_C12_A:bit16;
 end;

 TOUTPUT_CSC_C11_C12_B=bitpacked record
  OUTPUT_CSC_C11_B:bit16;
  OUTPUT_CSC_C12_B:bit16;
 end;

 TOUTPUT_CSC_C13_C14_A=bitpacked record
  OUTPUT_CSC_C13_A:bit16;
  OUTPUT_CSC_C14_A:bit16;
 end;

 TOUTPUT_CSC_C13_C14_B=bitpacked record
  OUTPUT_CSC_C13_B:bit16;
  OUTPUT_CSC_C14_B:bit16;
 end;

 TOUTPUT_CSC_C21_C22_A=bitpacked record
  OUTPUT_CSC_C21_A:bit16;
  OUTPUT_CSC_C22_A:bit16;
 end;

 TOUTPUT_CSC_C21_C22_B=bitpacked record
  OUTPUT_CSC_C21_B:bit16;
  OUTPUT_CSC_C22_B:bit16;
 end;

 TOUTPUT_CSC_C23_C24_A=bitpacked record
  OUTPUT_CSC_C23_A:bit16;
  OUTPUT_CSC_C24_A:bit16;
 end;

 TOUTPUT_CSC_C23_C24_B=bitpacked record
  OUTPUT_CSC_C23_B:bit16;
  OUTPUT_CSC_C24_B:bit16;
 end;

 TOUTPUT_CSC_C31_C32_A=bitpacked record
  OUTPUT_CSC_C31_A:bit16;
  OUTPUT_CSC_C32_A:bit16;
 end;

 TOUTPUT_CSC_C31_C32_B=bitpacked record
  OUTPUT_CSC_C31_B:bit16;
  OUTPUT_CSC_C32_B:bit16;
 end;

 TOUTPUT_CSC_C33_C34_A=bitpacked record
  OUTPUT_CSC_C33_A:bit16;
  OUTPUT_CSC_C34_A:bit16;
 end;

 TOUTPUT_CSC_C33_C34_B=bitpacked record
  OUTPUT_CSC_C33_B:bit16;
  OUTPUT_CSC_C34_B:bit16;
 end;

 TOVL_SURFACE_OFFSET_X=bitpacked record
  OVL_SURFACE_OFFSET_X:bit14;
  RESERVED0           :bit18;
 end;

 TOVL_SURFACE_OFFSET_Y=bitpacked record
  OVL_SURFACE_OFFSET_Y:bit14;
  RESERVED0           :bit18;
 end;

 TPA_CL_POINT_CULL_RAD=bit32;

 TPA_CL_VPORT_XSCALE_1=bit32;

 TPA_CL_VPORT_XSCALE_2=bit32;

 TPA_CL_VPORT_XSCALE_3=bit32;

 TPA_CL_VPORT_XSCALE_4=bit32;

 TPA_CL_VPORT_XSCALE_5=bit32;

 TPA_CL_VPORT_XSCALE_6=bit32;

 TPA_CL_VPORT_XSCALE_7=bit32;

 TPA_CL_VPORT_XSCALE_8=bit32;

 TPA_CL_VPORT_XSCALE_9=bit32;

 TPA_CL_VPORT_YSCALE_1=bit32;

 TPA_CL_VPORT_YSCALE_2=bit32;

 TPA_CL_VPORT_YSCALE_3=bit32;

 TPA_CL_VPORT_YSCALE_4=bit32;

 TPA_CL_VPORT_YSCALE_5=bit32;

 TPA_CL_VPORT_YSCALE_6=bit32;

 TPA_CL_VPORT_YSCALE_7=bit32;

 TPA_CL_VPORT_YSCALE_8=bit32;

 TPA_CL_VPORT_YSCALE_9=bit32;

 TPA_CL_VPORT_ZSCALE_1=bit32;

 TPA_CL_VPORT_ZSCALE_2=bit32;

 TPA_CL_VPORT_ZSCALE_3=bit32;

 TPA_CL_VPORT_ZSCALE_4=bit32;

 TPA_CL_VPORT_ZSCALE_5=bit32;

 TPA_CL_VPORT_ZSCALE_6=bit32;

 TPA_CL_VPORT_ZSCALE_7=bit32;

 TPA_CL_VPORT_ZSCALE_8=bit32;

 TPA_CL_VPORT_ZSCALE_9=bit32;

 TPB0_DFT_JIT_INJ_REG0=bitpacked record
  DFT_NUM_STEPS    :bit6;
  RESERVED0        :bit1;
  DFT_DISABLE_ERR  :bit1;
  DFT_CLK_PER_STEP :bit4;
  RESERVED1        :bit8;
  DFT_MODE_CDR_EN  :bit1;
  DFT_EN_RECOVERY  :bit1;
  DFT_INCR_SWP_EN  :bit1;
  DFT_DECR_SWP_EN  :bit1;
  DFT_RECOVERY_TIME:bit8;
 end;

 TPB0_DFT_JIT_INJ_REG1=bitpacked record
  DFT_BYPASS_VALUE:bit8;
  DFT_BYPASS_EN   :bit1;
  RESERVED0       :bit7;
  DFT_BLOCK_EN    :bit1;
  DFT_NUM_OF_TESTS:bit3;
  DFT_CHECK_TIME  :bit4;
  RESERVED1       :bit8;
 end;

 TPB0_DFT_JIT_INJ_REG2=bitpacked record
  DFT_LANE_EN:bit16;
  RESERVED0  :bit16;
 end;

 TPB0_PIF_CMD_BUS_CTRL=bitpacked record
  CMD_BUS_SCHL_MODE    :bit2;
  CMD_BUS_STAG_MODE    :bit2;
  CMD_BUS_STAG_DIS     :bit1;
  CMD_BUS_SCH_REQ_MODE :bit2;
  CMD_BUS_IGNR_PEND_PWR:bit1;
  RESERVED0            :bit24;
 end;

 TPB0_RX_GLB_CTRL_REG0=bitpacked record
  RX_CFG_ADAPT_MODE_GEN1:bit10;
  RX_CFG_ADAPT_MODE_GEN2:bit10;
  RX_CFG_ADAPT_MODE_GEN3:bit10;
  RX_CFG_ADAPT_RST_MODE :bit2;
 end;

 TPB0_RX_GLB_CTRL_REG1=bitpacked record
  RX_CFG_CDR_FR_GAIN_GEN1      :bit4;
  RX_CFG_CDR_FR_GAIN_GEN2      :bit4;
  RX_CFG_CDR_FR_GAIN_GEN3      :bit4;
  RX_CFG_CDR_PH_GAIN_GEN1      :bit4;
  RX_CFG_CDR_PH_GAIN_GEN2      :bit4;
  RX_CFG_CDR_PH_GAIN_GEN3      :bit4;
  RX_CFG_CDR_PI_STPSZ_GEN1     :bit1;
  RX_CFG_CDR_PI_STPSZ_GEN2     :bit1;
  RX_CFG_CDR_PI_STPSZ_GEN3     :bit1;
  RX_CFG_LEQ_DCATTN_BYP_EN_GEN1:bit1;
  RX_CFG_LEQ_DCATTN_BYP_EN_GEN2:bit1;
  RX_CFG_LEQ_DCATTN_BYP_EN_GEN3:bit1;
  RX_ADAPT_HLD_ASRT_TO_DCLK_EN :bit2;
 end;

 TPB0_RX_GLB_CTRL_REG2=bitpacked record
  RESERVED0                   :bit12;
  RX_CFG_CDR_TIME_GEN1        :bit4;
  RX_CFG_CDR_TIME_GEN2        :bit4;
  RX_CFG_CDR_TIME_GEN3        :bit4;
  RX_CFG_LEQ_LOOP_GAIN_GEN1   :bit2;
  RX_CFG_LEQ_LOOP_GAIN_GEN2   :bit2;
  RX_CFG_LEQ_LOOP_GAIN_GEN3   :bit2;
  RX_DCLK_EN_ASRT_TO_ADAPT_HLD:bit2;
 end;

 TPB0_RX_GLB_CTRL_REG3=bitpacked record
  RX_CFG_CDR_FR_EN_GEN1 :bit1;
  RX_CFG_CDR_FR_EN_GEN2 :bit1;
  RX_CFG_CDR_FR_EN_GEN3 :bit1;
  RX_ADAPT_RST_MODE_GEN1:bit2;
  RX_ADAPT_RST_MODE_GEN2:bit2;
  RX_ADAPT_RST_MODE_GEN3:bit2;
  RX_ADAPT_RST_SUB_MODE :bit3;
  RX_L0_ENTRY_MODE_GEN1 :bit2;
  RX_L0_ENTRY_MODE_GEN2 :bit2;
  RX_L0_ENTRY_MODE_GEN3 :bit2;
  RESERVED0             :bit2;
  RX_CFG_DFE_TIME_GEN1  :bit4;
  RX_CFG_DFE_TIME_GEN2  :bit4;
  RX_CFG_DFE_TIME_GEN3  :bit4;
 end;

 TPB0_RX_GLB_CTRL_REG4=bitpacked record
  RX_CFG_FOM_BER_GEN1         :bit3;
  RX_CFG_FOM_BER_GEN2         :bit3;
  RX_CFG_FOM_BER_GEN3         :bit3;
  RX_CFG_LEQ_POLE_BYP_VAL_GEN1:bit3;
  RX_CFG_LEQ_POLE_BYP_VAL_GEN2:bit3;
  RX_CFG_LEQ_POLE_BYP_VAL_GEN3:bit3;
  RESERVED0                   :bit2;
  RX_CFG_FOM_TIME_GEN1        :bit4;
  RX_CFG_FOM_TIME_GEN2        :bit4;
  RX_CFG_FOM_TIME_GEN3        :bit4;
 end;

 TPB0_RX_GLB_CTRL_REG5=bitpacked record
  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1      :bit5;
  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2      :bit5;
  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3      :bit5;
  RX_CFG_LEQ_POLE_BYP_EN_GEN1         :bit1;
  RX_CFG_LEQ_POLE_BYP_EN_GEN2         :bit1;
  RX_CFG_LEQ_POLE_BYP_EN_GEN3         :bit1;
  RX_CFG_LEQ_SHUNT_EN_GEN1            :bit1;
  RX_CFG_LEQ_SHUNT_EN_GEN2            :bit1;
  RX_CFG_LEQ_SHUNT_EN_GEN3            :bit1;
  RESERVED0                           :bit6;
  RX_CFG_TERM_MODE_GEN1               :bit1;
  RX_CFG_TERM_MODE_GEN2               :bit1;
  RX_CFG_TERM_MODE_GEN3               :bit1;
  RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0:bit1;
  RX_ADAPT_AUX_PWRON_MODE             :bit1;
 end;

 TPB0_RX_GLB_CTRL_REG6=bitpacked record
  RX_CFG_LEQ_TIME_GEN1                    :bit4;
  RX_CFG_LEQ_TIME_GEN2                    :bit4;
  RX_CFG_LEQ_TIME_GEN3                    :bit4;
  RX_CFG_OC_TIME_GEN1                     :bit4;
  RX_CFG_OC_TIME_GEN2                     :bit4;
  RX_CFG_OC_TIME_GEN3                     :bit4;
  RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0:bit1;
  RESERVED0                               :bit1;
  RX_FRONTEND_PWRON_LUT_ENTRY_LS2         :bit1;
  RX_AUX_PWRON_LUT_ENTRY_LS2              :bit1;
  RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS         :bit1;
  RX_ADAPT_HLD_L1_DLL_OFF                 :bit1;
  RESERVED1                               :bit2;
 end;

 TPB0_RX_GLB_CTRL_REG7=bitpacked record
  RX_CFG_TH_LOOP_GAIN_GEN1         :bit4;
  RX_CFG_TH_LOOP_GAIN_GEN2         :bit4;
  RX_CFG_TH_LOOP_GAIN_GEN3         :bit4;
  RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0:bit1;
  RX_DCLK_EN_LUT_ENTRY_LS2         :bit1;
  RX_DCLK_EN_AFTER_DLL_LOCK        :bit1;
  RESERVED0                        :bit1;
  RX_DLL_PWRON_LUT_ENTRY_PS3       :bit1;
  RX_DLL_PWRON_LUT_ENTRY_PS2       :bit1;
  RX_CFG_DLL_CPI_SEL_GEN1          :bit3;
  RX_CFG_DLL_CPI_SEL_GEN2          :bit3;
  RX_CFG_DLL_CPI_SEL_GEN3          :bit3;
  RX_CFG_DLL_FLOCK_DISABLE_GEN1    :bit1;
  RX_CFG_DLL_FLOCK_DISABLE_GEN2    :bit1;
  RX_CFG_DLL_FLOCK_DISABLE_GEN3    :bit1;
  RESERVED1                        :bit2;
 end;

 TPB0_RX_GLB_CTRL_REG8=bitpacked record
  RX_DLL_LOCK_TIME             :bit2;
  RX_DLL_SPEEDCHANGE_RESET_TIME:bit2;
  RX_DLL_PWRON_IN_RAMPDOWN     :bit1;
  RX_FSM_L0S_IF_RX_RDY         :bit1;
  RESERVED0                    :bit26;
 end;

 TPB0_RX_GLB_OVRD_REG0=bitpacked record
  RX_ADAPT_HLD_OVRD_VAL        :bit1;
  RX_ADAPT_HLD_OVRD_EN         :bit1;
  RX_ADAPT_RST_OVRD_VAL        :bit1;
  RX_ADAPT_RST_OVRD_EN         :bit1;
  RESERVED0                    :bit2;
  RX_CFG_DCLK_DIV_OVRD_VAL     :bit2;
  RX_CFG_DCLK_DIV_OVRD_EN      :bit1;
  RX_CFG_DLL_FREQ_MODE_OVRD_VAL:bit1;
  RX_CFG_DLL_FREQ_MODE_OVRD_EN :bit1;
  RX_CFG_PLLCLK_SEL_OVRD_VAL   :bit1;
  RX_CFG_PLLCLK_SEL_OVRD_EN    :bit1;
  RX_CFG_RCLK_DIV_OVRD_VAL     :bit1;
  RX_CFG_RCLK_DIV_OVRD_EN      :bit1;
  RX_DCLK_EN_OVRD_VAL          :bit1;
  RX_DCLK_EN_OVRD_EN           :bit1;
  RX_DLL_PWRON_OVRD_VAL        :bit1;
  RX_DLL_PWRON_OVRD_EN         :bit1;
  RX_FRONTEND_PWRON_OVRD_VAL   :bit1;
  RX_FRONTEND_PWRON_OVRD_EN    :bit1;
  RX_IDLEDET_PWRON_OVRD_VAL    :bit1;
  RX_IDLEDET_PWRON_OVRD_EN     :bit1;
  RX_TERM_EN_OVRD_VAL          :bit1;
  RX_TERM_EN_OVRD_EN           :bit1;
  RESERVED1                    :bit3;
  RX_AUX_PWRON_OVRD_VAL        :bit1;
  RX_AUX_PWRON_OVRD_EN         :bit1;
  RX_ADAPT_FOM_OVRD_VAL        :bit1;
  RX_ADAPT_FOM_OVRD_EN         :bit1;
 end;

 TPB0_RX_GLB_OVRD_REG1=bitpacked record
  RX_ADAPT_TRK_OVRD_VAL:bit1;
  RX_ADAPT_TRK_OVRD_EN :bit1;
  RESERVED0            :bit30;
 end;

 TPB0_TX_GLB_CTRL_REG0=bitpacked record
  TX_DRV_DATA_ASRT_DLY_VAL:bit3;
  TX_DRV_DATA_DSRT_DLY_VAL:bit3;
  RESERVED0               :bit2;
  TX_CFG_RPTR_RST_VAL_GEN1:bit3;
  TX_CFG_RPTR_RST_VAL_GEN2:bit3;
  TX_CFG_RPTR_RST_VAL_GEN3:bit3;
  TX_STAGGER_CTRL         :bit2;
  TX_DATA_CLK_GATING      :bit1;
  TX_PRESET_TABLE_BYPASS  :bit1;
  TX_COEFF_ROUND_EN       :bit1;
  TX_COEFF_ROUND_DIR_VER  :bit1;
  TX_DCLK_EN_LSX_ALWAYS_ON:bit1;
  TX_FRONTEND_PWRON_IN_PS4:bit1;
  RESERVED1               :bit7;
 end;

 TPB0_TX_GLB_OVRD_REG0=bitpacked record
  TX_CFG_DCLK_DIV_OVRD_VAL         :bit3;
  TX_CFG_DCLK_DIV_OVRD_EN          :bit1;
  TX_CFG_DRV0_EN_GEN1_OVRD_VAL     :bit4;
  TX_CFG_DRV0_EN_OVRD_EN           :bit1;
  TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL:bit4;
  TX_CFG_DRV0_TAP_SEL_OVRD_EN      :bit1;
  TX_CFG_DRV1_EN_GEN1_OVRD_VAL     :bit5;
  TX_CFG_DRV1_EN_OVRD_EN           :bit1;
  TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL:bit5;
  TX_CFG_DRV1_TAP_SEL_OVRD_EN      :bit1;
  TX_CFG_DRV2_EN_GEN1_OVRD_VAL     :bit4;
  TX_CFG_DRV2_EN_OVRD_EN           :bit1;
  RESERVED0                        :bit1;
 end;

 TPB0_TX_GLB_OVRD_REG1=bitpacked record
  TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL:bit4;
  TX_CFG_DRV2_TAP_SEL_OVRD_EN      :bit1;
  TX_CFG_DRVX_EN_GEN1_OVRD_VAL     :bit1;
  TX_CFG_DRVX_EN_OVRD_EN           :bit1;
  TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL:bit1;
  TX_CFG_DRVX_TAP_SEL_OVRD_EN      :bit1;
  TX_CFG_PLLCLK_SEL_OVRD_VAL       :bit1;
  TX_CFG_PLLCLK_SEL_OVRD_EN        :bit1;
  TX_CFG_TCLK_DIV_OVRD_VAL         :bit1;
  TX_CFG_TCLK_DIV_OVRD_EN          :bit1;
  TX_CMDET_EN_OVRD_VAL             :bit1;
  TX_CMDET_EN_OVRD_EN              :bit1;
  TX_DATA_IN_OVRD_VAL              :bit10;
  TX_DATA_IN_OVRD_EN               :bit1;
  TX_RPTR_RSTN_OVRD_VAL            :bit1;
  TX_RPTR_RSTN_OVRD_EN             :bit1;
  TX_RXDET_EN_OVRD_VAL             :bit1;
  TX_RXDET_EN_OVRD_EN              :bit1;
  TX_WPTR_RSTN_OVRD_VAL            :bit1;
  TX_WPTR_RSTN_OVRD_EN             :bit1;
 end;

 TPB0_TX_GLB_OVRD_REG2=bitpacked record
  TX_WRITE_EN_OVRD_VAL             :bit1;
  TX_WRITE_EN_OVRD_EN              :bit1;
  TX_CFG_GROUPX1_EN_OVRD_VAL       :bit1;
  TX_CFG_GROUPX1_EN_OVRD_EN        :bit1;
  TX_CFG_GROUPX2_EN_OVRD_VAL       :bit1;
  TX_CFG_GROUPX2_EN_OVRD_EN        :bit1;
  TX_CFG_GROUPX4_EN_OVRD_VAL       :bit1;
  TX_CFG_GROUPX4_EN_OVRD_EN        :bit1;
  TX_CFG_GROUPX8_EN_OVRD_VAL       :bit1;
  TX_CFG_GROUPX8_EN_OVRD_EN        :bit1;
  TX_CFG_GROUPX16_EN_OVRD_VAL      :bit1;
  TX_CFG_GROUPX16_EN_OVRD_EN       :bit1;
  TX_CFG_DRV0_EN_GEN2_OVRD_VAL     :bit4;
  TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL:bit4;
  TX_CFG_DRV1_EN_GEN2_OVRD_VAL     :bit5;
  TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL:bit5;
  RESERVED0                        :bit2;
 end;

 TPB0_TX_GLB_OVRD_REG3=bitpacked record
  TX_CFG_DRV2_EN_GEN2_OVRD_VAL     :bit4;
  TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL:bit4;
  TX_CFG_DRVX_EN_GEN2_OVRD_VAL     :bit1;
  TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL:bit1;
  TX_CFG_DRV0_EN_GEN3_OVRD_VAL     :bit4;
  TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL:bit4;
  TX_CFG_DRV1_EN_GEN3_OVRD_VAL     :bit5;
  TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL:bit5;
  TX_CFG_DRV2_EN_GEN3_OVRD_VAL     :bit4;
 end;

 TPB0_TX_GLB_OVRD_REG4=bitpacked record
  TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL:bit4;
  TX_CFG_DRVX_EN_GEN3_OVRD_VAL     :bit1;
  TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL:bit1;
  RESERVED0                        :bit26;
 end;

 TPB1_DFT_JIT_INJ_REG0=bitpacked record
  DFT_NUM_STEPS    :bit6;
  RESERVED0        :bit1;
  DFT_DISABLE_ERR  :bit1;
  DFT_CLK_PER_STEP :bit4;
  RESERVED1        :bit8;
  DFT_MODE_CDR_EN  :bit1;
  DFT_EN_RECOVERY  :bit1;
  DFT_INCR_SWP_EN  :bit1;
  DFT_DECR_SWP_EN  :bit1;
  DFT_RECOVERY_TIME:bit8;
 end;

 TPB1_DFT_JIT_INJ_REG1=bitpacked record
  DFT_BYPASS_VALUE:bit8;
  DFT_BYPASS_EN   :bit1;
  RESERVED0       :bit7;
  DFT_BLOCK_EN    :bit1;
  DFT_NUM_OF_TESTS:bit3;
  DFT_CHECK_TIME  :bit4;
  RESERVED1       :bit8;
 end;

 TPB1_DFT_JIT_INJ_REG2=bitpacked record
  DFT_LANE_EN:bit16;
  RESERVED0  :bit16;
 end;

 TPB1_PIF_CMD_BUS_CTRL=bitpacked record
  CMD_BUS_SCHL_MODE    :bit2;
  CMD_BUS_STAG_MODE    :bit2;
  CMD_BUS_STAG_DIS     :bit1;
  CMD_BUS_SCH_REQ_MODE :bit2;
  CMD_BUS_IGNR_PEND_PWR:bit1;
  RESERVED0            :bit24;
 end;

 TPB1_RX_GLB_CTRL_REG0=bitpacked record
  RX_CFG_ADAPT_MODE_GEN1:bit10;
  RX_CFG_ADAPT_MODE_GEN2:bit10;
  RX_CFG_ADAPT_MODE_GEN3:bit10;
  RX_CFG_ADAPT_RST_MODE :bit2;
 end;

 TPB1_RX_GLB_CTRL_REG1=bitpacked record
  RX_CFG_CDR_FR_GAIN_GEN1      :bit4;
  RX_CFG_CDR_FR_GAIN_GEN2      :bit4;
  RX_CFG_CDR_FR_GAIN_GEN3      :bit4;
  RX_CFG_CDR_PH_GAIN_GEN1      :bit4;
  RX_CFG_CDR_PH_GAIN_GEN2      :bit4;
  RX_CFG_CDR_PH_GAIN_GEN3      :bit4;
  RX_CFG_CDR_PI_STPSZ_GEN1     :bit1;
  RX_CFG_CDR_PI_STPSZ_GEN2     :bit1;
  RX_CFG_CDR_PI_STPSZ_GEN3     :bit1;
  RX_CFG_LEQ_DCATTN_BYP_EN_GEN1:bit1;
  RX_CFG_LEQ_DCATTN_BYP_EN_GEN2:bit1;
  RX_CFG_LEQ_DCATTN_BYP_EN_GEN3:bit1;
  RX_ADAPT_HLD_ASRT_TO_DCLK_EN :bit2;
 end;

 TPB1_RX_GLB_CTRL_REG2=bitpacked record
  RESERVED0                   :bit12;
  RX_CFG_CDR_TIME_GEN1        :bit4;
  RX_CFG_CDR_TIME_GEN2        :bit4;
  RX_CFG_CDR_TIME_GEN3        :bit4;
  RX_CFG_LEQ_LOOP_GAIN_GEN1   :bit2;
  RX_CFG_LEQ_LOOP_GAIN_GEN2   :bit2;
  RX_CFG_LEQ_LOOP_GAIN_GEN3   :bit2;
  RX_DCLK_EN_ASRT_TO_ADAPT_HLD:bit2;
 end;

 TPB1_RX_GLB_CTRL_REG3=bitpacked record
  RX_CFG_CDR_FR_EN_GEN1 :bit1;
  RX_CFG_CDR_FR_EN_GEN2 :bit1;
  RX_CFG_CDR_FR_EN_GEN3 :bit1;
  RX_ADAPT_RST_MODE_GEN1:bit2;
  RX_ADAPT_RST_MODE_GEN2:bit2;
  RX_ADAPT_RST_MODE_GEN3:bit2;
  RX_ADAPT_RST_SUB_MODE :bit3;
  RX_L0_ENTRY_MODE_GEN1 :bit2;
  RX_L0_ENTRY_MODE_GEN2 :bit2;
  RX_L0_ENTRY_MODE_GEN3 :bit2;
  RESERVED0             :bit2;
  RX_CFG_DFE_TIME_GEN1  :bit4;
  RX_CFG_DFE_TIME_GEN2  :bit4;
  RX_CFG_DFE_TIME_GEN3  :bit4;
 end;

 TPB1_RX_GLB_CTRL_REG4=bitpacked record
  RX_CFG_FOM_BER_GEN1         :bit3;
  RX_CFG_FOM_BER_GEN2         :bit3;
  RX_CFG_FOM_BER_GEN3         :bit3;
  RX_CFG_LEQ_POLE_BYP_VAL_GEN1:bit3;
  RX_CFG_LEQ_POLE_BYP_VAL_GEN2:bit3;
  RX_CFG_LEQ_POLE_BYP_VAL_GEN3:bit3;
  RESERVED0                   :bit2;
  RX_CFG_FOM_TIME_GEN1        :bit4;
  RX_CFG_FOM_TIME_GEN2        :bit4;
  RX_CFG_FOM_TIME_GEN3        :bit4;
 end;

 TPB1_RX_GLB_CTRL_REG5=bitpacked record
  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1      :bit5;
  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2      :bit5;
  RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3      :bit5;
  RX_CFG_LEQ_POLE_BYP_EN_GEN1         :bit1;
  RX_CFG_LEQ_POLE_BYP_EN_GEN2         :bit1;
  RX_CFG_LEQ_POLE_BYP_EN_GEN3         :bit1;
  RX_CFG_LEQ_SHUNT_EN_GEN1            :bit1;
  RX_CFG_LEQ_SHUNT_EN_GEN2            :bit1;
  RX_CFG_LEQ_SHUNT_EN_GEN3            :bit1;
  RESERVED0                           :bit6;
  RX_CFG_TERM_MODE_GEN1               :bit1;
  RX_CFG_TERM_MODE_GEN2               :bit1;
  RX_CFG_TERM_MODE_GEN3               :bit1;
  RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0:bit1;
  RX_ADAPT_AUX_PWRON_MODE             :bit1;
 end;

 TPB1_RX_GLB_CTRL_REG6=bitpacked record
  RX_CFG_LEQ_TIME_GEN1                    :bit4;
  RX_CFG_LEQ_TIME_GEN2                    :bit4;
  RX_CFG_LEQ_TIME_GEN3                    :bit4;
  RX_CFG_OC_TIME_GEN1                     :bit4;
  RX_CFG_OC_TIME_GEN2                     :bit4;
  RX_CFG_OC_TIME_GEN3                     :bit4;
  RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0:bit1;
  RESERVED0                               :bit1;
  RX_FRONTEND_PWRON_LUT_ENTRY_LS2         :bit1;
  RX_AUX_PWRON_LUT_ENTRY_LS2              :bit1;
  RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS         :bit1;
  RX_ADAPT_HLD_L1_DLL_OFF                 :bit1;
  RESERVED1                               :bit2;
 end;

 TPB1_RX_GLB_CTRL_REG7=bitpacked record
  RX_CFG_TH_LOOP_GAIN_GEN1         :bit4;
  RX_CFG_TH_LOOP_GAIN_GEN2         :bit4;
  RX_CFG_TH_LOOP_GAIN_GEN3         :bit4;
  RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0:bit1;
  RX_DCLK_EN_LUT_ENTRY_LS2         :bit1;
  RX_DCLK_EN_AFTER_DLL_LOCK        :bit1;
  RESERVED0                        :bit1;
  RX_DLL_PWRON_LUT_ENTRY_PS3       :bit1;
  RX_DLL_PWRON_LUT_ENTRY_PS2       :bit1;
  RX_CFG_DLL_CPI_SEL_GEN1          :bit3;
  RX_CFG_DLL_CPI_SEL_GEN2          :bit3;
  RX_CFG_DLL_CPI_SEL_GEN3          :bit3;
  RX_CFG_DLL_FLOCK_DISABLE_GEN1    :bit1;
  RX_CFG_DLL_FLOCK_DISABLE_GEN2    :bit1;
  RX_CFG_DLL_FLOCK_DISABLE_GEN3    :bit1;
  RESERVED1                        :bit2;
 end;

 TPB1_RX_GLB_CTRL_REG8=bitpacked record
  RX_DLL_LOCK_TIME             :bit2;
  RX_DLL_SPEEDCHANGE_RESET_TIME:bit2;
  RX_DLL_PWRON_IN_RAMPDOWN     :bit1;
  RX_FSM_L0S_IF_RX_RDY         :bit1;
  RESERVED0                    :bit26;
 end;

 TPB1_RX_GLB_OVRD_REG0=bitpacked record
  RX_ADAPT_HLD_OVRD_VAL        :bit1;
  RX_ADAPT_HLD_OVRD_EN         :bit1;
  RX_ADAPT_RST_OVRD_VAL        :bit1;
  RX_ADAPT_RST_OVRD_EN         :bit1;
  RESERVED0                    :bit2;
  RX_CFG_DCLK_DIV_OVRD_VAL     :bit2;
  RX_CFG_DCLK_DIV_OVRD_EN      :bit1;
  RX_CFG_DLL_FREQ_MODE_OVRD_VAL:bit1;
  RX_CFG_DLL_FREQ_MODE_OVRD_EN :bit1;
  RX_CFG_PLLCLK_SEL_OVRD_VAL   :bit1;
  RX_CFG_PLLCLK_SEL_OVRD_EN    :bit1;
  RX_CFG_RCLK_DIV_OVRD_VAL     :bit1;
  RX_CFG_RCLK_DIV_OVRD_EN      :bit1;
  RX_DCLK_EN_OVRD_VAL          :bit1;
  RX_DCLK_EN_OVRD_EN           :bit1;
  RX_DLL_PWRON_OVRD_VAL        :bit1;
  RX_DLL_PWRON_OVRD_EN         :bit1;
  RX_FRONTEND_PWRON_OVRD_VAL   :bit1;
  RX_FRONTEND_PWRON_OVRD_EN    :bit1;
  RX_IDLEDET_PWRON_OVRD_VAL    :bit1;
  RX_IDLEDET_PWRON_OVRD_EN     :bit1;
  RX_TERM_EN_OVRD_VAL          :bit1;
  RX_TERM_EN_OVRD_EN           :bit1;
  RESERVED1                    :bit3;
  RX_AUX_PWRON_OVRD_VAL        :bit1;
  RX_AUX_PWRON_OVRD_EN         :bit1;
  RX_ADAPT_FOM_OVRD_VAL        :bit1;
  RX_ADAPT_FOM_OVRD_EN         :bit1;
 end;

 TPB1_RX_GLB_OVRD_REG1=bitpacked record
  RX_ADAPT_TRK_OVRD_VAL:bit1;
  RX_ADAPT_TRK_OVRD_EN :bit1;
  RESERVED0            :bit30;
 end;

 TPB1_TX_GLB_CTRL_REG0=bitpacked record
  TX_DRV_DATA_ASRT_DLY_VAL:bit3;
  TX_DRV_DATA_DSRT_DLY_VAL:bit3;
  RESERVED0               :bit2;
  TX_CFG_RPTR_RST_VAL_GEN1:bit3;
  TX_CFG_RPTR_RST_VAL_GEN2:bit3;
  TX_CFG_RPTR_RST_VAL_GEN3:bit3;
  TX_STAGGER_CTRL         :bit2;
  TX_DATA_CLK_GATING      :bit1;
  TX_PRESET_TABLE_BYPASS  :bit1;
  TX_COEFF_ROUND_EN       :bit1;
  TX_COEFF_ROUND_DIR_VER  :bit1;
  TX_DCLK_EN_LSX_ALWAYS_ON:bit1;
  TX_FRONTEND_PWRON_IN_PS4:bit1;
  RESERVED1               :bit7;
 end;

 TPB1_TX_GLB_OVRD_REG0=bitpacked record
  TX_CFG_DCLK_DIV_OVRD_VAL         :bit3;
  TX_CFG_DCLK_DIV_OVRD_EN          :bit1;
  TX_CFG_DRV0_EN_GEN1_OVRD_VAL     :bit4;
  TX_CFG_DRV0_EN_OVRD_EN           :bit1;
  TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL:bit4;
  TX_CFG_DRV0_TAP_SEL_OVRD_EN      :bit1;
  TX_CFG_DRV1_EN_GEN1_OVRD_VAL     :bit5;
  TX_CFG_DRV1_EN_OVRD_EN           :bit1;
  TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL:bit5;
  TX_CFG_DRV1_TAP_SEL_OVRD_EN      :bit1;
  TX_CFG_DRV2_EN_GEN1_OVRD_VAL     :bit4;
  TX_CFG_DRV2_EN_OVRD_EN           :bit1;
  RESERVED0                        :bit1;
 end;

 TPB1_TX_GLB_OVRD_REG1=bitpacked record
  TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL:bit4;
  TX_CFG_DRV2_TAP_SEL_OVRD_EN      :bit1;
  TX_CFG_DRVX_EN_GEN1_OVRD_VAL     :bit1;
  TX_CFG_DRVX_EN_OVRD_EN           :bit1;
  TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL:bit1;
  TX_CFG_DRVX_TAP_SEL_OVRD_EN      :bit1;
  TX_CFG_PLLCLK_SEL_OVRD_VAL       :bit1;
  TX_CFG_PLLCLK_SEL_OVRD_EN        :bit1;
  TX_CFG_TCLK_DIV_OVRD_VAL         :bit1;
  TX_CFG_TCLK_DIV_OVRD_EN          :bit1;
  TX_CMDET_EN_OVRD_VAL             :bit1;
  TX_CMDET_EN_OVRD_EN              :bit1;
  TX_DATA_IN_OVRD_VAL              :bit10;
  TX_DATA_IN_OVRD_EN               :bit1;
  TX_RPTR_RSTN_OVRD_VAL            :bit1;
  TX_RPTR_RSTN_OVRD_EN             :bit1;
  TX_RXDET_EN_OVRD_VAL             :bit1;
  TX_RXDET_EN_OVRD_EN              :bit1;
  TX_WPTR_RSTN_OVRD_VAL            :bit1;
  TX_WPTR_RSTN_OVRD_EN             :bit1;
 end;

 TPB1_TX_GLB_OVRD_REG2=bitpacked record
  TX_WRITE_EN_OVRD_VAL             :bit1;
  TX_WRITE_EN_OVRD_EN              :bit1;
  TX_CFG_GROUPX1_EN_OVRD_VAL       :bit1;
  TX_CFG_GROUPX1_EN_OVRD_EN        :bit1;
  TX_CFG_GROUPX2_EN_OVRD_VAL       :bit1;
  TX_CFG_GROUPX2_EN_OVRD_EN        :bit1;
  TX_CFG_GROUPX4_EN_OVRD_VAL       :bit1;
  TX_CFG_GROUPX4_EN_OVRD_EN        :bit1;
  TX_CFG_GROUPX8_EN_OVRD_VAL       :bit1;
  TX_CFG_GROUPX8_EN_OVRD_EN        :bit1;
  TX_CFG_GROUPX16_EN_OVRD_VAL      :bit1;
  TX_CFG_GROUPX16_EN_OVRD_EN       :bit1;
  TX_CFG_DRV0_EN_GEN2_OVRD_VAL     :bit4;
  TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL:bit4;
  TX_CFG_DRV1_EN_GEN2_OVRD_VAL     :bit5;
  TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL:bit5;
  RESERVED0                        :bit2;
 end;

 TPB1_TX_GLB_OVRD_REG3=bitpacked record
  TX_CFG_DRV2_EN_GEN2_OVRD_VAL     :bit4;
  TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL:bit4;
  TX_CFG_DRVX_EN_GEN2_OVRD_VAL     :bit1;
  TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL:bit1;
  TX_CFG_DRV0_EN_GEN3_OVRD_VAL     :bit4;
  TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL:bit4;
  TX_CFG_DRV1_EN_GEN3_OVRD_VAL     :bit5;
  TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL:bit5;
  TX_CFG_DRV2_EN_GEN3_OVRD_VAL     :bit4;
 end;

 TPB1_TX_GLB_OVRD_REG4=bitpacked record
  TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL:bit4;
  TX_CFG_DRVX_EN_GEN3_OVRD_VAL     :bit1;
  TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL:bit1;
  RESERVED0                        :bit26;
 end;

 TPCIE_CORR_ERR_STATUS=bitpacked record
  RCV_ERR_STATUS              :bit1;
  RESERVED0                   :bit5;
  BAD_TLP_STATUS              :bit1;
  BAD_DLLP_STATUS             :bit1;
  REPLAY_NUM_ROLLOVER_STATUS  :bit1;
  RESERVED1                   :bit3;
  REPLAY_TIMER_TIMEOUT_STATUS :bit1;
  ADVISORY_NONFATAL_ERR_STATUS:bit1;
  CORR_INT_ERR_STATUS         :bit1;
  HDR_LOG_OVFL_STATUS         :bit1;
  RESERVED2                   :bit16;
 end;

 TPCIE_HOLD_TRAINING_A=bitpacked record
  HOLD_TRAINING_A:bit1;
  RESERVED0      :bit31;
 end;

 TPCIE_MC_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_PAGE_REQ_STATUS=bitpacked record
  RESPONSE_FAILURE             :bit1;
  UNEXPECTED_PAGE_REQ_GRP_INDEX:bit1;
  RESERVED0                    :bit6;
  STOPPED                      :bit1;
  RESERVED1                    :bit6;
  PRG_RESPONSE_PASID_REQUIRED  :bit1;
  RESERVED2                    :bit16;
 end;

 TPCIE_PERF_CNTL_TXCLK=bitpacked record
  EVENT0_SEL    :bit8;
  EVENT1_SEL    :bit8;
  COUNTER0_UPPER:bit8;
  COUNTER1_UPPER:bit8;
 end;

 TPCIE_PERF_COUNT_CNTL=bitpacked record
  GLOBAL_COUNT_EN   :bit1;
  GLOBAL_SHADOW_WR  :bit1;
  GLOBAL_COUNT_RESET:bit1;
  RESERVED0         :bit29;
 end;

 TPCIE_PWR_BUDGET_DATA=bitpacked record
  BASE_POWER  :bit8;
  DATA_SCALE  :bit2;
  PM_SUB_STATE:bit3;
  PM_STATE    :bit2;
  _TYPE       :bit3;
  POWER_RAIL  :bit3;
  RESERVED0   :bit11;
 end;

 TPCIE_SRIOV_TOTAL_VFS=bitpacked record
  SRIOV_TOTAL_VFS:bit16;
  RESERVED0      :bit16;
 end;

 TPCIE_SRIOV_VF_STRIDE=bitpacked record
  SRIOV_VF_STRIDE:bit16;
  RESERVED0      :bit16;
 end;

 TPCIE_TLP_PREFIX_LOG0=bit32;

 TPCIE_TLP_PREFIX_LOG1=bit32;

 TPCIE_TLP_PREFIX_LOG2=bit32;

 TPCIE_TLP_PREFIX_LOG3=bit32;

 TPCIE_TX_F0_ATTR_CNTL=bitpacked record
  TX_F0_IDO_OVERRIDE_P  :bit2;
  TX_F0_IDO_OVERRIDE_NP :bit2;
  TX_F0_IDO_OVERRIDE_CPL:bit2;
  TX_F0_RO_OVERRIDE_P   :bit2;
  TX_F0_RO_OVERRIDE_NP  :bit2;
  TX_F0_SNR_OVERRIDE_P  :bit2;
  TX_F0_SNR_OVERRIDE_NP :bit2;
  RESERVED0             :bit18;
 end;

 TPCIE_TX_REQUESTER_ID=bitpacked record
  TX_REQUESTER_ID_FUNCTION:bit3;
  TX_REQUESTER_ID_DEVICE  :bit5;
  TX_REQUESTER_ID_BUS     :bit8;
  RESERVED0               :bit16;
 end;

 TPCIE_UNCORR_ERR_MASK=bitpacked record
  RESERVED0                   :bit4;
  DLP_ERR_MASK                :bit1;
  SURPDN_ERR_MASK             :bit1;
  RESERVED1                   :bit6;
  PSN_ERR_MASK                :bit1;
  FC_ERR_MASK                 :bit1;
  CPL_TIMEOUT_MASK            :bit1;
  CPL_ABORT_ERR_MASK          :bit1;
  UNEXP_CPL_MASK              :bit1;
  RCV_OVFL_MASK               :bit1;
  MAL_TLP_MASK                :bit1;
  ECRC_ERR_MASK               :bit1;
  UNSUPP_REQ_ERR_MASK         :bit1;
  ACS_VIOLATION_MASK          :bit1;
  UNCORR_INT_ERR_MASK         :bit1;
  MC_BLOCKED_TLP_MASK         :bit1;
  ATOMICOP_EGRESS_BLOCKED_MASK:bit1;
  TLP_PREFIX_BLOCKED_ERR_MASK :bit1;
  RESERVED2                   :bit6;
 end;

 TPCIE_VC_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPLL_SS_AMOUNT_DSFRAC=bitpacked record
  PLL_SS_AMOUNT_DSFRAC:bit16;
  RESERVED0           :bit16;
 end;

 TPRESCALE_OVL_CONTROL=bitpacked record
  OVL_PRESCALE_SELECT :bit1;
  OVL_PRESCALE_CB_SIGN:bit1;
  OVL_PRESCALE_Y_SIGN :bit1;
  OVL_PRESCALE_CR_SIGN:bit1;
  OVL_PRESCALE_BYPASS :bit1;
  RESERVED0           :bit27;
 end;

 TPWR_DISP_TIMER_DEBUG=bitpacked record
  DISP_TIMER_INT_RUNNING:bit1;
  DISP_TIMER_INT_STAT   :bit1;
  DISP_TIMER_INT        :bit1;
  RESERVED0             :bit4;
  DISP_TIMER_RUN_VAL    :bit25;
 end;

 TRLC_GPM_DEBUG_SELECT=bitpacked record
  SELECT          :bit8;
  F32_DEBUG_SELECT:bit2;
  RESERVED        :bit22;
 end;

 TRLC_GPM_PERF_COUNT_0=bitpacked record
  FEATURE_SEL:bit4;
  SE_INDEX   :bit4;
  SH_INDEX   :bit4;
  CU_INDEX   :bit4;
  EVENT_SEL  :bit2;
  RESERVED0  :bit2;
  ENABLE     :bit1;
  RESERVED1  :bit11;
 end;

 TRLC_GPM_PERF_COUNT_1=bitpacked record
  FEATURE_SEL:bit4;
  SE_INDEX   :bit4;
  SH_INDEX   :bit4;
  CU_INDEX   :bit4;
  EVENT_SEL  :bit2;
  RESERVED0  :bit2;
  ENABLE     :bit1;
  RESERVED1  :bit11;
 end;

 TRLC_GPM_SCRATCH_ADDR=bitpacked record
  ADDR     :bit9;
  RESERVED0:bit23;
 end;

 TRLC_GPM_SCRATCH_DATA=bit32;

 TRLC_GPM_THREAD_RESET=bitpacked record
  THREAD0_RESET:bit1;
  THREAD1_RESET:bit1;
  THREAD2_RESET:bit1;
  THREAD3_RESET:bit1;
  RESERVED     :bit28;
 end;

 TRLC_GPM_VMID_THREAD0=bitpacked record
  RLC_VMID   :bit4;
  RESERVED0  :bit4;
  RLC_QUEUEID:bit3;
  RESERVED1  :bit21;
 end;

 TRLC_GPM_VMID_THREAD1=bitpacked record
  RLC_VMID   :bit4;
  RESERVED0  :bit4;
  RLC_QUEUEID:bit3;
  RESERVED1  :bit21;
 end;

 TRLC_GPM_VMID_THREAD2=bitpacked record
  RLC_VMID   :bit4;
  RESERVED0  :bit4;
  RLC_QUEUEID:bit3;
  RESERVED1  :bit21;
 end;

 TRLC_GPU_IOV_CFG_REG1=bitpacked record
  CMD_TYPE           :bit4;
  CMD_EXECUTE        :bit1;
  CMD_EXECUTE_INTR_EN:bit1;
  RESERVED           :bit2;
  FCN_ID             :bit8;
  NEXT_FCN_ID        :bit8;
  RESERVED1          :bit8;
 end;

 TRLC_GPU_IOV_CFG_REG2=bitpacked record
  CMD_STATUS:bit4;
  RESERVED  :bit28;
 end;

 TRLC_GPU_IOV_CFG_REG6=bitpacked record
  CNTXT_SIZE    :bit7;
  CNTXT_LOCATION:bit1;
  RESERVED      :bit2;
  CNTXT_OFFSET  :bit22;
 end;

 TRLC_GPU_IOV_CFG_REG8=bit32;

 TRLC_GPU_IOV_CFG_REG9=bitpacked record
  ACTIVE_FCN_ID       :bit8;
  ACTIVE_FCN_ID_STATUS:bit4;
  RESERVED            :bit20;
 end;

 TRLC_GPU_IOV_F32_CNTL=bitpacked record
  ENABLE  :bit1;
  RESERVED:bit31;
 end;

 TRLC_PERFMON_CLK_CNTL=bitpacked record
  PERFMON_CLOCK_STATE:bit1;
  RESERVED0          :bit31;
 end;

 TRLC_SERDES_RD_DATA_0=bit32;

 TRLC_SERDES_RD_DATA_1=bit32;

 TRLC_SERDES_RD_DATA_2=bit32;

 TRLC_SPM_DEBUG_SELECT=bitpacked record
  SELECT            :bit8;
  RESERVED0         :bit7;
  RLC_SPM_DEBUG_MODE:bit1;
  RLC_SPM_NUM_SAMPLE:bit16;
 end;

 TRLC_SPM_PERFMON_CNTL=bitpacked record
  RESERVED1              :bit12;
  PERFMON_RING_MODE      :bit2;
  RESERVED0              :bit2;
  PERFMON_SAMPLE_INTERVAL:bit16;
 end;

 TRLC_SRM_DEBUG_SELECT=bitpacked record
  SELECT  :bit8;
  RESERVED:bit24;
 end;

 TRLC_SRM_RLCV_COMMAND=bitpacked record
  OP          :bit1;
  RESERVED    :bit3;
  SIZE        :bit12;
  START_OFFSET:bit12;
  RESERVED1   :bit3;
  DEST_MEMORY :bit1;
 end;

 TRLC_STATIC_PG_STATUS=bit32;

 TSCLK_DEEP_SLEEP_CNTL=bitpacked record
  DIV_ID                :bit3;
  RAMP_DIS              :bit1;
  HYSTERESIS            :bit12;
  SCLK_RUNNING_MASK     :bit1;
  SELF_REFRESH_MASK     :bit1;
  ALLOW_NBPSTATE_MASK   :bit1;
  BIF_BUSY_MASK         :bit1;
  UVD_BUSY_MASK         :bit1;
  MC0SRBM_BUSY_MASK     :bit1;
  MC1SRBM_BUSY_MASK     :bit1;
  MC_ALLOW_MASK         :bit1;
  SMU_BUSY_MASK         :bit1;
  SELF_REFRESH_NLC_MASK :bit1;
  FAST_EXIT_REQ_NBPSTATE:bit1;
  DEEP_SLEEP_ENTRY_MODE :bit1;
  MBUS2_ACTIVE_MASK     :bit1;
  VCE_BUSY_MASK         :bit1;
  AZ_BUSY_MASK          :bit1;
  ENABLE_DS             :bit1;
 end;

 TSCLV_COEF_RAM_SELECT=bitpacked record
  SCL_C_RAM_TAP_PAIR_IDX:bit2;
  RESERVED0             :bit6;
  SCL_C_RAM_PHASE       :bit7;
  RESERVED1             :bit1;
  SCL_C_RAM_FILTER_TYPE :bit2;
  RESERVED2             :bit14;
 end;

 TSCLV_TEST_DEBUG_DATA=bit32;

 TSCLV_VIEWPORT_SIZE_C=bitpacked record
  VIEWPORT_HEIGHT_C:bit13;
  RESERVED0        :bit3;
  VIEWPORT_WIDTH_C :bit13;
  RESERVED1        :bit3;
 end;

 TSCL_HORZ_FILTER_INIT=bitpacked record
  SCL_H_INIT_FRAC:bit24;
  SCL_H_INIT_INT :bit4;
  RESERVED0      :bit4;
 end;

 TSCL_MODE_CHANGE_DET1=bitpacked record
  SCL_MODE_CHANGE      :bit1;
  RESERVED0            :bit3;
  SCL_MODE_CHANGE_ACK  :bit1;
  RESERVED1            :bit2;
  SCL_ALU_H_SCALE_RATIO:bit21;
  RESERVED2            :bit4;
 end;

 TSCL_MODE_CHANGE_DET2=bitpacked record
  SCL_ALU_V_SCALE_RATIO:bit21;
  RESERVED0            :bit11;
 end;

 TSCL_MODE_CHANGE_DET3=bitpacked record
  SCL_ALU_SOURCE_HEIGHT:bit14;
  RESERVED0            :bit2;
  SCL_ALU_SOURCE_WIDTH :bit14;
  RESERVED1            :bit2;
 end;

 TSCL_MODE_CHANGE_MASK=bitpacked record
  SCL_MODE_CHANGE_MASK:bit1;
  RESERVED0           :bit31;
 end;

 TSCL_TEST_DEBUG_INDEX=bitpacked record
  SCL_TEST_DEBUG_INDEX   :bit8;
  SCL_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TSCL_VERT_FILTER_INIT=bitpacked record
  SCL_V_INIT_FRAC:bit24;
  SCL_V_INIT_INT :bit3;
  RESERVED0      :bit5;
 end;

 TSDMA0_GFX_IB_BASE_HI=bit32;

 TSDMA0_GFX_IB_BASE_LO=bitpacked record
  RESERVED0:bit5;
  ADDR     :bit27;
 end;

 TSDMA0_GFX_RB_BASE_HI=bitpacked record
  ADDR     :bit24;
  RESERVED0:bit8;
 end;

 TSDMA0_PERF_REG_TYPE0=bitpacked record
  SDMA0_PERFMON_CNTL       :bit1;
  SDMA0_PERFCOUNTER0_RESULT:bit1;
  SDMA0_PERFCOUNTER1_RESULT:bit1;
  RESERVED_31_3            :bit29;
 end;

 TSDMA0_PHASE0_QUANTUM=bitpacked record
  _UNIT    :bit4;
  RESERVED0:bit4;
  VALUE    :bit16;
  RESERVED1:bit6;
  PREFER   :bit1;
  RESERVED2:bit1;
 end;

 TSDMA0_PHASE1_QUANTUM=bitpacked record
  _UNIT    :bit4;
  RESERVED0:bit4;
  VALUE    :bit16;
  RESERVED1:bit6;
  PREFER   :bit1;
  RESERVED2:bit1;
 end;

 TSDMA0_RLC0_APE1_CNTL=bitpacked record
  BASE :bit16;
  LIMIT:bit16;
 end;

 TSDMA0_RLC0_DUMMY_REG=bit32;

 TSDMA0_RLC0_IB_OFFSET=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA0_RLC0_SKIP_CNTL=bitpacked record
  SKIP_COUNT:bit14;
  RESERVED0 :bit18;
 end;

 TSDMA0_RLC0_WATERMARK=bitpacked record
  RD_OUTSTANDING:bit12;
  RESERVED0     :bit4;
  WR_OUTSTANDING:bit9;
  RESERVED1     :bit7;
 end;

 TSDMA0_RLC1_APE1_CNTL=bitpacked record
  BASE :bit16;
  LIMIT:bit16;
 end;

 TSDMA0_RLC1_DUMMY_REG=bit32;

 TSDMA0_RLC1_IB_OFFSET=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA0_RLC1_SKIP_CNTL=bitpacked record
  SKIP_COUNT:bit14;
  RESERVED0 :bit18;
 end;

 TSDMA0_RLC1_WATERMARK=bitpacked record
  RD_OUTSTANDING:bit12;
  RESERVED0     :bit4;
  WR_OUTSTANDING:bit9;
  RESERVED1     :bit7;
 end;

 TSDMA0_VIRT_RESET_REQ=bitpacked record
  VF       :bit16;
  RESERVED0:bit15;
  PF       :bit1;
 end;

 TSDMA1_GFX_IB_BASE_HI=bit32;

 TSDMA1_GFX_IB_BASE_LO=bitpacked record
  RESERVED0:bit5;
  ADDR     :bit27;
 end;

 TSDMA1_GFX_RB_BASE_HI=bitpacked record
  ADDR     :bit24;
  RESERVED0:bit8;
 end;

 TSDMA1_PERF_REG_TYPE0=bitpacked record
  SDMA1_PERFMON_CNTL       :bit1;
  SDMA1_PERFCOUNTER0_RESULT:bit1;
  SDMA1_PERFCOUNTER1_RESULT:bit1;
  RESERVED_31_3            :bit29;
 end;

 TSDMA1_PHASE0_QUANTUM=bitpacked record
  _UNIT    :bit4;
  RESERVED0:bit4;
  VALUE    :bit16;
  RESERVED1:bit6;
  PREFER   :bit1;
  RESERVED2:bit1;
 end;

 TSDMA1_PHASE1_QUANTUM=bitpacked record
  _UNIT    :bit4;
  RESERVED0:bit4;
  VALUE    :bit16;
  RESERVED1:bit6;
  PREFER   :bit1;
  RESERVED2:bit1;
 end;

 TSDMA1_RLC0_APE1_CNTL=bitpacked record
  BASE :bit16;
  LIMIT:bit16;
 end;

 TSDMA1_RLC0_DUMMY_REG=bit32;

 TSDMA1_RLC0_IB_OFFSET=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA1_RLC0_SKIP_CNTL=bitpacked record
  SKIP_COUNT:bit14;
  RESERVED0 :bit18;
 end;

 TSDMA1_RLC0_WATERMARK=bitpacked record
  RD_OUTSTANDING:bit12;
  RESERVED0     :bit4;
  WR_OUTSTANDING:bit9;
  RESERVED1     :bit7;
 end;

 TSDMA1_RLC1_APE1_CNTL=bitpacked record
  BASE :bit16;
  LIMIT:bit16;
 end;

 TSDMA1_RLC1_DUMMY_REG=bit32;

 TSDMA1_RLC1_IB_OFFSET=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA1_RLC1_SKIP_CNTL=bitpacked record
  SKIP_COUNT:bit14;
  RESERVED0 :bit18;
 end;

 TSDMA1_RLC1_WATERMARK=bitpacked record
  RD_OUTSTANDING:bit12;
  RESERVED0     :bit4;
  WR_OUTSTANDING:bit9;
  RESERVED1     :bit7;
 end;

 TSDMA1_VIRT_RESET_REQ=bitpacked record
  VF       :bit16;
  RESERVED0:bit15;
  PF       :bit1;
 end;

 TSE_CAC_CGTT_CLK_CTRL=bitpacked record
  ON_DELAY         :bit4;
  OFF_HYSTERESIS   :bit8;
  RESERVED0        :bit18;
  SOFT_OVERRIDE_DYN:bit1;
  SOFT_OVERRIDE_REG:bit1;
 end;

 TSH_STATIC_MEM_CONFIG=bitpacked record
  SWIZZLE_ENABLE:bit1;
  ELEMENT_SIZE  :bit2;
  INDEX_STRIDE  :bit2;
  PRIVATE_MTYPE :bit3;
  READ_ONLY_CNTL:bit8;
  RESERVED0     :bit16;
 end;

 TSLAVE_COMM_DATA_REG1=bitpacked record
  SLAVE_COMM_DATA_REG1_BYTE0:bit8;
  SLAVE_COMM_DATA_REG1_BYTE1:bit8;
  SLAVE_COMM_DATA_REG1_BYTE2:bit8;
  SLAVE_COMM_DATA_REG1_BYTE3:bit8;
 end;

 TSLAVE_COMM_DATA_REG2=bitpacked record
  SLAVE_COMM_DATA_REG2_BYTE0:bit8;
  SLAVE_COMM_DATA_REG2_BYTE1:bit8;
  SLAVE_COMM_DATA_REG2_BYTE2:bit8;
  SLAVE_COMM_DATA_REG2_BYTE3:bit8;
 end;

 TSLAVE_COMM_DATA_REG3=bitpacked record
  SLAVE_COMM_DATA_REG3_BYTE0:bit8;
  SLAVE_COMM_DATA_REG3_BYTE1:bit8;
  SLAVE_COMM_DATA_REG3_BYTE2:bit8;
  SLAVE_COMM_DATA_REG3_BYTE3:bit8;
 end;

 TSMC_SYSCON_MISC_CNTL=bitpacked record
  RESERVED0         :bit1;
  dma_no_outstanding:bit1;
  RESERVED1         :bit30;
 end;

 TSMC_SYSCON_MSG_ARG_0=bit32;

 TSMU_MAIN_PLL_OP_FREQ=bit32;

 TSMU_MP1_SRBM2P_MSG_5=bit32;

 TSPI_GDBG_TRAP_CONFIG=bitpacked record
  ME_SEL     :bit2;
  PIPE_SEL   :bit2;
  QUEUE_SEL  :bit3;
  ME_MATCH   :bit1;
  PIPE_MATCH :bit1;
  QUEUE_MATCH:bit1;
  RESERVED0  :bit5;
  TRAP_EN    :bit1;
  VMID_SEL   :bit16;
 end;

 TSPI_INTERP_CONTROL_0=bitpacked record
  FLAT_SHADE_ENA   :bit1;
  PNT_SPRITE_ENA   :bit1;
  PNT_SPRITE_OVRD_X:bit3;
  PNT_SPRITE_OVRD_Y:bit3;
  PNT_SPRITE_OVRD_Z:bit3;
  PNT_SPRITE_OVRD_W:bit3;
  PNT_SPRITE_TOP_1 :bit1;
  RESERVED0        :bit17;
 end;

 TSPI_PERFCOUNTER_BINS=bitpacked record
  BIN0_MIN:bit4;
  BIN0_MAX:bit4;
  BIN1_MIN:bit4;
  BIN1_MAX:bit4;
  BIN2_MIN:bit4;
  BIN2_MAX:bit4;
  BIN3_MIN:bit4;
  BIN3_MAX:bit4;
 end;

 TSPI_PS_INPUT_CNTL_10=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_11=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_12=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_13=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_14=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_15=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_16=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_17=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_18=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_19=bitpacked record
  OFFSET             :bit6;
  RESERVED0          :bit2;
  DEFAULT_VAL        :bit2;
  FLAT_SHADE         :bit1;
  RESERVED1          :bit2;
  CYL_WRAP           :bit4;
  PT_SPRITE_TEX      :bit1;
  DUP                :bit1;
  FP16_INTERP_MODE   :bit1;
  USE_DEFAULT_ATTR1  :bit1;
  DEFAULT_VAL_ATTR1  :bit2;
  PT_SPRITE_TEX_ATTR1:bit1;
  ATTR0_VALID        :bit1;
  ATTR1_VALID        :bit1;
  RESERVED2          :bit6;
 end;

 TSPI_PS_INPUT_CNTL_20=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_21=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_22=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_23=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_24=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_25=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_26=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_27=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_28=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_29=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_30=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_PS_INPUT_CNTL_31=bitpacked record
  OFFSET           :bit6;
  RESERVED0        :bit2;
  DEFAULT_VAL      :bit2;
  FLAT_SHADE       :bit1;
  RESERVED1        :bit7;
  DUP              :bit1;
  FP16_INTERP_MODE :bit1;
  USE_DEFAULT_ATTR1:bit1;
  DEFAULT_VAL_ATTR1:bit2;
  RESERVED2        :bit1;
  ATTR0_VALID      :bit1;
  ATTR1_VALID      :bit1;
  RESERVED3        :bit6;
 end;

 TSPI_SHADER_PGM_HI_ES=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_PGM_HI_GS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_PGM_HI_HS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_PGM_HI_LS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_PGM_HI_PS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_PGM_HI_VS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_PGM_LO_ES=bit32;

 TSPI_SHADER_PGM_LO_GS=bit32;

 TSPI_SHADER_PGM_LO_HS=bit32;

 TSPI_SHADER_PGM_LO_LS=bit32;

 TSPI_SHADER_PGM_LO_PS=bit32;

 TSPI_SHADER_PGM_LO_VS=bit32;

 TSPI_SHADER_TBA_HI_ES=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TBA_HI_GS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TBA_HI_HS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TBA_HI_LS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TBA_HI_PS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TBA_HI_VS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TBA_LO_ES=bit32;

 TSPI_SHADER_TBA_LO_GS=bit32;

 TSPI_SHADER_TBA_LO_HS=bit32;

 TSPI_SHADER_TBA_LO_LS=bit32;

 TSPI_SHADER_TBA_LO_PS=bit32;

 TSPI_SHADER_TBA_LO_VS=bit32;

 TSPI_SHADER_TMA_HI_ES=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TMA_HI_GS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TMA_HI_HS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TMA_HI_LS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TMA_HI_PS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TMA_HI_VS=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_TMA_LO_ES=bit32;

 TSPI_SHADER_TMA_LO_GS=bit32;

 TSPI_SHADER_TMA_LO_HS=bit32;

 TSPI_SHADER_TMA_LO_LS=bit32;

 TSPI_SHADER_TMA_LO_PS=bit32;

 TSPI_SHADER_TMA_LO_VS=bit32;

 TSPI_SLAVE_DEBUG_BUSY=bitpacked record
  LS_VTX_BUSY     :bit1;
  HS_VTX_BUSY     :bit1;
  ES_VTX_BUSY     :bit1;
  GS_VTX_BUSY     :bit1;
  VS_VTX_BUSY     :bit1;
  VGPR_WC00_BUSY  :bit1;
  VGPR_WC01_BUSY  :bit1;
  VGPR_WC10_BUSY  :bit1;
  VGPR_WC11_BUSY  :bit1;
  SGPR_WC00_BUSY  :bit1;
  SGPR_WC01_BUSY  :bit1;
  SGPR_WC02_BUSY  :bit1;
  SGPR_WC03_BUSY  :bit1;
  SGPR_WC10_BUSY  :bit1;
  SGPR_WC11_BUSY  :bit1;
  SGPR_WC12_BUSY  :bit1;
  SGPR_WC13_BUSY  :bit1;
  WAVEBUFFER0_BUSY:bit1;
  WAVEBUFFER1_BUSY:bit1;
  WAVE_WC0_BUSY   :bit1;
  WAVE_WC1_BUSY   :bit1;
  EVENT_CNTL_BUSY :bit1;
  SAVE_CTX_BUSY   :bit1;
  RESERVED0       :bit9;
 end;

 TSPI_WF_LIFETIME_CNTL=bitpacked record
  SAMPLE_PERIOD:bit4;
  EN           :bit1;
  RESERVED0    :bit27;
 end;

 TSQ_DEBUG_STS_GLOBAL2=bitpacked record
  FIFO_LEVEL_GFX0 :bit8;
  FIFO_LEVEL_GFX1 :bit8;
  FIFO_LEVEL_IMMED:bit8;
  FIFO_LEVEL_HOST :bit8;
 end;

 TSQ_DEBUG_STS_GLOBAL3=bitpacked record
  FIFO_LEVEL_HOST_CMD:bit4;
  FIFO_LEVEL_HOST_REG:bit6;
  RESERVED0          :bit22;
 end;

 TSQ_PERFCOUNTER_CTRL2=bitpacked record
  FORCE_EN :bit1;
  RESERVED0:bit31;
 end;

 TSQ_THREAD_TRACE_BASE=bit32;

 TSQ_THREAD_TRACE_CNTR=bit32;

 TSQ_THREAD_TRACE_CTRL=bitpacked record
  RESERVED0   :bit31;
  RESET_BUFFER:bit1;
 end;

 TSQ_THREAD_TRACE_MASK=bitpacked record
  CU_SEL      :bit5;
  SH_SEL      :bit1;
  RESERVED0   :bit1;
  REG_STALL_EN:bit1;
  SIMD_EN     :bit4;
  VM_ID_MASK  :bit2;
  SPI_STALL_EN:bit1;
  SQ_STALL_EN :bit1;
  RANDOM_SEED :bit16;
 end;

 TSQ_THREAD_TRACE_MODE=bitpacked record
  MASK_PS     :bit3;
  MASK_VS     :bit3;
  MASK_GS     :bit3;
  MASK_ES     :bit3;
  MASK_HS     :bit3;
  MASK_LS     :bit3;
  MASK_CS     :bit3;
  MODE        :bit2;
  CAPTURE_MODE:bit2;
  AUTOFLUSH_EN:bit1;
  PRIV        :bit1;
  ISSUE_MASK  :bit2;
  TEST_MODE   :bit1;
  INTERRUPT_EN:bit1;
  WRAP        :bit1;
 end;

 TSQ_THREAD_TRACE_SIZE=bitpacked record
  SIZE     :bit22;
  RESERVED0:bit10;
 end;

 TSQ_THREAD_TRACE_WPTR=bitpacked record
  WPTR       :bit30;
  READ_OFFSET:bit2;
 end;

 TSRBM_DEBUG_SNAPSHOT2=bitpacked record
  VCE1_RDY :bit1;
  RESERVED0:bit31;
 end;

 TSRBM_GFX_CNTL_SELECT=bitpacked record
  SRBM_GFX_CNTL_SEL:bit4;
  RESERVED0        :bit28;
 end;

 TSRBM_MC_DOMAIN_ADDR0=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_MC_DOMAIN_ADDR1=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_MC_DOMAIN_ADDR2=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_MC_DOMAIN_ADDR3=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_MC_DOMAIN_ADDR4=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_MC_DOMAIN_ADDR5=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_MC_DOMAIN_ADDR6=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_PERFCOUNTER0_HI=bit32;

 TSRBM_PERFCOUNTER0_LO=bit32;

 TSRBM_PERFCOUNTER1_HI=bit32;

 TSRBM_PERFCOUNTER1_LO=bit32;

 TSRBM_SDMA_CLKEN_CNTL=bitpacked record
  PREFIX_DELAY_CNT:bit4;
  RESERVED0       :bit4;
  POST_DELAY_CNT  :bit5;
  RESERVED1       :bit19;
 end;

 TSWRST_COMMAND_STATUS=bitpacked record
  RECONFIGURE   :bit1;
  ATOMIC_RESET  :bit1;
  RESERVED0     :bit14;
  RESET_COMPLETE:bit1;
  WAIT_STATE    :bit1;
  RESERVED1     :bit14;
 end;

 TSX_BLEND_OPT_CONTROL=bitpacked record
  MRT0_COLOR_OPT_DISABLE:bit1;
  MRT0_ALPHA_OPT_DISABLE:bit1;
  RESERVED0             :bit2;
  MRT1_COLOR_OPT_DISABLE:bit1;
  MRT1_ALPHA_OPT_DISABLE:bit1;
  RESERVED1             :bit2;
  MRT2_COLOR_OPT_DISABLE:bit1;
  MRT2_ALPHA_OPT_DISABLE:bit1;
  RESERVED2             :bit2;
  MRT3_COLOR_OPT_DISABLE:bit1;
  MRT3_ALPHA_OPT_DISABLE:bit1;
  RESERVED3             :bit2;
  MRT4_COLOR_OPT_DISABLE:bit1;
  MRT4_ALPHA_OPT_DISABLE:bit1;
  RESERVED4             :bit2;
  MRT5_COLOR_OPT_DISABLE:bit1;
  MRT5_ALPHA_OPT_DISABLE:bit1;
  RESERVED5             :bit2;
  MRT6_COLOR_OPT_DISABLE:bit1;
  MRT6_ALPHA_OPT_DISABLE:bit1;
  RESERVED6             :bit2;
  MRT7_COLOR_OPT_DISABLE:bit1;
  MRT7_ALPHA_OPT_DISABLE:bit1;
  RESERVED7             :bit1;
  PIXEN_ZERO_OPT_DISABLE:bit1;
 end;

 TSX_BLEND_OPT_EPSILON=bitpacked record
  MRT0_EPSILON:bit4;
  MRT1_EPSILON:bit4;
  MRT2_EPSILON:bit4;
  MRT3_EPSILON:bit4;
  MRT4_EPSILON:bit4;
  MRT5_EPSILON:bit4;
  MRT6_EPSILON:bit4;
  MRT7_EPSILON:bit4;
 end;

 TSYMCLKA_CLOCK_ENABLE=bitpacked record
  SYMCLKA_CLOCK_ENABLE:bit1;
  RESERVED0           :bit3;
  SYMCLKA_FE_FORCE_EN :bit1;
  RESERVED1           :bit3;
  SYMCLKA_FE_FORCE_SRC:bit3;
  RESERVED2           :bit21;
 end;

 TSYMCLKB_CLOCK_ENABLE=bitpacked record
  SYMCLKB_CLOCK_ENABLE:bit1;
  RESERVED0           :bit3;
  SYMCLKB_FE_FORCE_EN :bit1;
  RESERVED1           :bit3;
  SYMCLKB_FE_FORCE_SRC:bit3;
  RESERVED2           :bit21;
 end;

 TSYMCLKC_CLOCK_ENABLE=bitpacked record
  SYMCLKC_CLOCK_ENABLE:bit1;
  RESERVED0           :bit3;
  SYMCLKC_FE_FORCE_EN :bit1;
  RESERVED1           :bit3;
  SYMCLKC_FE_FORCE_SRC:bit3;
  RESERVED2           :bit21;
 end;

 TSYMCLKD_CLOCK_ENABLE=bitpacked record
  SYMCLKD_CLOCK_ENABLE:bit1;
  RESERVED0           :bit3;
  SYMCLKD_FE_FORCE_EN :bit1;
  RESERVED1           :bit3;
  SYMCLKD_FE_FORCE_SRC:bit3;
  RESERVED2           :bit21;
 end;

 TSYMCLKE_CLOCK_ENABLE=bitpacked record
  SYMCLKE_CLOCK_ENABLE:bit1;
  RESERVED0           :bit3;
  SYMCLKE_FE_FORCE_EN :bit1;
  RESERVED1           :bit3;
  SYMCLKE_FE_FORCE_SRC:bit3;
  RESERVED2           :bit21;
 end;

 TSYMCLKF_CLOCK_ENABLE=bitpacked record
  SYMCLKF_CLOCK_ENABLE:bit1;
  RESERVED0           :bit3;
  SYMCLKF_FE_FORCE_EN :bit1;
  RESERVED1           :bit3;
  SYMCLKF_FE_FORCE_SRC:bit3;
  RESERVED2           :bit21;
 end;

 TSYMCLKG_CLOCK_ENABLE=bitpacked record
  SYMCLKG_CLOCK_ENABLE:bit1;
  RESERVED0           :bit3;
  SYMCLKG_FE_FORCE_EN :bit1;
  RESERVED1           :bit3;
  SYMCLKG_FE_FORCE_SRC:bit3;
  RESERVED2           :bit21;
 end;

 TTHM_TMON0_RDIL0_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL1_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL2_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL3_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL4_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL5_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL6_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL7_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL8_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL9_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR0_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR1_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR2_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR3_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR4_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR5_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR6_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR7_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR8_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR9_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL0_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL1_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL2_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL3_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL4_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL5_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL6_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL7_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL8_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL9_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR0_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR1_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR2_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR3_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR4_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR5_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR6_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR7_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR8_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR9_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL0_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL1_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL2_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL3_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL4_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL5_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL6_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL7_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL8_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL9_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR0_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR1_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR2_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR3_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR4_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR5_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR6_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR7_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR8_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR9_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTMDS_CTL0_1_GEN_CNTL=bitpacked record
  TMDS_CTL0_DATA_SEL         :bit4;
  TMDS_CTL0_DATA_DELAY       :bit3;
  TMDS_CTL0_DATA_INVERT      :bit1;
  TMDS_CTL0_DATA_MODULATION  :bit2;
  TMDS_CTL0_USE_FEEDBACK_PATH:bit1;
  TMDS_CTL0_FB_SYNC_CONT     :bit1;
  TMDS_CTL0_PATTERN_OUT_EN   :bit1;
  RESERVED0                  :bit3;
  TMDS_CTL1_DATA_SEL         :bit4;
  TMDS_CTL1_DATA_DELAY       :bit3;
  TMDS_CTL1_DATA_INVERT      :bit1;
  TMDS_CTL1_DATA_MODULATION  :bit2;
  TMDS_CTL1_USE_FEEDBACK_PATH:bit1;
  TMDS_CTL1_FB_SYNC_CONT     :bit1;
  TMDS_CTL1_PATTERN_OUT_EN   :bit1;
  RESERVED1                  :bit2;
  TMDS_2BIT_COUNTER_EN       :bit1;
 end;

 TTMDS_CTL2_3_GEN_CNTL=bitpacked record
  TMDS_CTL2_DATA_SEL         :bit4;
  TMDS_CTL2_DATA_DELAY       :bit3;
  TMDS_CTL2_DATA_INVERT      :bit1;
  TMDS_CTL2_DATA_MODULATION  :bit2;
  TMDS_CTL2_USE_FEEDBACK_PATH:bit1;
  TMDS_CTL2_FB_SYNC_CONT     :bit1;
  TMDS_CTL2_PATTERN_OUT_EN   :bit1;
  RESERVED0                  :bit3;
  TMDS_CTL3_DATA_SEL         :bit4;
  TMDS_CTL3_DATA_DELAY       :bit3;
  TMDS_CTL3_DATA_INVERT      :bit1;
  TMDS_CTL3_DATA_MODULATION  :bit2;
  TMDS_CTL3_USE_FEEDBACK_PATH:bit1;
  TMDS_CTL3_FB_SYNC_CONT     :bit1;
  TMDS_CTL3_PATTERN_OUT_EN   :bit1;
  RESERVED1                  :bit3;
 end;

 TUNIPHY_ANG_BIST_CNTL=bitpacked record
  UNIPHY_TEST_RX_EN    :bit1;
  UNIPHY_ANG_BIST_RESET:bit1;
  RESERVED0            :bit6;
  UNIPHY_RX_BIAS       :bit4;
  RESERVED1            :bit4;
  UNIPHY_ANG_BIST_ERROR:bit5;
  RESERVED2            :bit3;
  UNIPHY_PRESETB       :bit1;
  UNIPHY_BIST_EN       :bit1;
  UNIPHY_CLK_CH_EN4_DFT:bit1;
  RESERVED3            :bit5;
 end;

 TUNIPHY_IMPCAL_PERIOD=bit32;

 TUNIPHY_IMPCAL_PSW_AB=bitpacked record
  UNIPHY_IMPCAL_PSW_LINKA:bit15;
  RESERVED0              :bit1;
  UNIPHY_IMPCAL_PSW_LINKB:bit15;
  RESERVED1              :bit1;
 end;

 TUNIPHY_IMPCAL_PSW_CD=bitpacked record
  UNIPHY_IMPCAL_PSW_LINKC:bit15;
  RESERVED0              :bit1;
  UNIPHY_IMPCAL_PSW_LINKD:bit15;
  RESERVED1              :bit1;
 end;

 TUNIPHY_IMPCAL_PSW_EF=bitpacked record
  UNIPHY_IMPCAL_PSW_LINKE:bit15;
  RESERVED0              :bit1;
  UNIPHY_IMPCAL_PSW_LINKF:bit15;
  RESERVED1              :bit1;
 end;

 TUNIPHY_POWER_CONTROL=bitpacked record
  UNIPHY_BGPDN      :bit1;
  UNIPHY_RST_LOGIC  :bit1;
  UNIPHY_BIASREF_SEL:bit1;
  RESERVED0         :bit5;
  UNIPHY_BGADJ1P00  :bit4;
  UNIPHY_BGADJ1P25  :bit4;
  UNIPHY_BGADJ0P45  :bit4;
  RESERVED1         :bit12;
 end;

 TUNP_GRPH_CONTROL_EXP=bitpacked record
  VIDEO_FORMAT:bit3;
  RESERVED0   :bit29;
 end;

 TUNP_GRPH_DFQ_CONTROL=bitpacked record
  GRPH_DFQ_RESET           :bit1;
  RESERVED0                :bit3;
  GRPH_DFQ_SIZE            :bit3;
  RESERVED1                :bit1;
  GRPH_DFQ_MIN_FREE_ENTRIES:bit3;
  RESERVED2                :bit21;
 end;

 TUNP_TEST_DEBUG_INDEX=bitpacked record
  UNP_TEST_DEBUG_INDEX   :bit8;
  UNP_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TUVD_GPCOM_VCPU_DATA0=bit32;

 TUVD_GPCOM_VCPU_DATA1=bit32;

 TUVD_JPEG_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit1;
  NUM_GPUS               :bit3;
  RESERVED5              :bit1;
  MULTI_GPU_TILE_SIZE    :bit2;
  RESERVED6              :bit2;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED7              :bit1;
 end;

 TUVD_PGFSM_READ_TILE1=bitpacked record
  UVD_PGFSM_READ_TILE1_VALUE:bit24;
  RESERVED0                 :bit8;
 end;

 TUVD_PGFSM_READ_TILE2=bitpacked record
  UVD_PGFSM_READ_TILE2_VALUE:bit24;
  RESERVED0                 :bit8;
 end;

 TUVD_PGFSM_READ_TILE3=bitpacked record
  UVD_PGFSM_READ_TILE3_VALUE:bit24;
  RESERVED0                 :bit8;
 end;

 TUVD_PGFSM_READ_TILE4=bitpacked record
  UVD_PGFSM_READ_TILE4_VALUE:bit24;
  RESERVED0                 :bit8;
 end;

 TUVD_PGFSM_READ_TILE5=bitpacked record
  UVD_PGFSM_READ_TILE5_VALUE:bit24;
  RESERVED0                 :bit8;
 end;

 TUVD_PGFSM_READ_TILE6=bitpacked record
  UVD_PGFSM_READ_TILE6_VALUE:bit24;
  RESERVED0                 :bit8;
 end;

 TUVD_PGFSM_READ_TILE7=bitpacked record
  UVD_PGFSM_READ_TILE7_VALUE:bit24;
  RESERVED0                 :bit8;
 end;

 TUVD_RBC_RB_RPTR_ADDR=bit32;

 TUVD_UDEC_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit1;
  NUM_GPUS               :bit3;
  RESERVED5              :bit1;
  MULTI_GPU_TILE_SIZE    :bit2;
  RESERVED6              :bit2;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED7              :bit1;
 end;

 TUVD_VCPU_CACHE_SIZE0=bitpacked record
  CACHE_SIZE0:bit21;
  RESERVED0  :bit11;
 end;

 TUVD_VCPU_CACHE_SIZE1=bitpacked record
  CACHE_SIZE1:bit21;
  RESERVED0  :bit11;
 end;

 TUVD_VCPU_CACHE_SIZE2=bitpacked record
  CACHE_SIZE2:bit21;
  RESERVED0  :bit11;
 end;

 TVCE_VCPU_CACHE_SIZE0=bitpacked record
  SIZE     :bit24;
  RESERVED0:bit8;
 end;

 TVCE_VCPU_CACHE_SIZE1=bitpacked record
  SIZE     :bit24;
  RESERVED0:bit8;
 end;

 TVCE_VCPU_CACHE_SIZE2=bitpacked record
  SIZE     :bit24;
  RESERVED0:bit8;
 end;

 TVGA_INTERRUPT_STATUS=bitpacked record
  VGA_MEM_ACCESS_INT_STATUS       :bit1;
  VGA_REG_ACCESS_INT_STATUS       :bit1;
  VGA_DISPLAY_SWITCH_INT_STATUS   :bit1;
  VGA_MODE_AUTO_TRIGGER_INT_STATUS:bit1;
  RESERVED0                       :bit28;
 end;

 TVGA_TEST_DEBUG_INDEX=bitpacked record
  VGA_TEST_DEBUG_INDEX   :bit8;
  VGA_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TVGT_DMA_LS_HS_CONFIG=bitpacked record
  RESERVED0      :bit8;
  HS_NUM_INPUT_CP:bit6;
  RESERVED1      :bit18;
 end;

 TVGT_GROUP_FIRST_DECR=bitpacked record
  FIRST_DECR:bit4;
  RESERVED0 :bit28;
 end;

 TVGT_GS_OUT_PRIM_TYPE=bitpacked record
  OUTPRIM_TYPE          :bit6;
  RESERVED0             :bit2;
  OUTPRIM_TYPE_1        :bit6;
  RESERVED1             :bit2;
  OUTPRIM_TYPE_2        :bit6;
  OUTPRIM_TYPE_3        :bit6;
  RESERVED2             :bit3;
  UNIQUE_TYPE_PER_STREAM:bit1;
 end;

 TVGT_GS_VERT_ITEMSIZE=bitpacked record
  ITEMSIZE :bit15;
  RESERVED0:bit17;
 end;

 TVGT_HS_OFFCHIP_PARAM=bitpacked record
  OFFCHIP_BUFFERING  :bit9;
  OFFCHIP_GRANULARITY:bit2;
  RESERVED0          :bit21;
 end;

 TVGT_OUTPUT_PATH_CNTL=bitpacked record
  PATH_SELECT:bit3;
  RESERVED0  :bit29;
 end;

 TVGT_OUT_DEALLOC_CNTL=bitpacked record
  DEALLOC_DIST:bit7;
  RESERVED0   :bit25;
 end;

 TVGT_SHADER_STAGES_EN=bitpacked record
  LS_EN              :bit2;
  HS_EN              :bit1;
  ES_EN              :bit2;
  GS_EN              :bit1;
  VS_EN              :bit2;
  DYNAMIC_HS         :bit1;
  DISPATCH_DRAW_EN   :bit1;
  DIS_DEALLOC_ACCUM_0:bit1;
  DIS_DEALLOC_ACCUM_1:bit1;
  VS_WAVE_ID_EN      :bit1;
  RESERVED0          :bit19;
 end;

 TXDMA_TEST_DEBUG_DATA=bit32;

 TAFMT_AUDIO_CRC_RESULT=bitpacked record
  AFMT_AUDIO_CRC_DONE:bit1;
  RESERVED0          :bit7;
  AFMT_AUDIO_CRC     :bit24;
 end;

 TATC_L1_ADDRESS_OFFSET=bit32;

 TATC_VM_APERTURE0_CNTL=bitpacked record
  ATS_ACCESS_MODE:bit2;
  RESERVED0      :bit30;
 end;

 TATC_VM_APERTURE1_CNTL=bitpacked record
  ATS_ACCESS_MODE:bit2;
  RESERVED0      :bit30;
 end;

 TAUX_INTERRUPT_CONTROL=bitpacked record
  AUX_SW_DONE_INT                :bit1;
  AUX_SW_DONE_ACK                :bit1;
  AUX_SW_DONE_MASK               :bit1;
  RESERVED0                      :bit1;
  AUX_LS_DONE_INT                :bit1;
  AUX_LS_DONE_ACK                :bit1;
  AUX_LS_DONE_MASK               :bit1;
  RESERVED1                      :bit1;
  AUX_GTC_SYNC_LOCK_DONE_INT     :bit1;
  AUX_GTC_SYNC_LOCK_DONE_ACK     :bit1;
  AUX_GTC_SYNC_LOCK_DONE_INT_MASK:bit1;
  RESERVED2                      :bit1;
  AUX_GTC_SYNC_ERROR_INT         :bit1;
  AUX_GTC_SYNC_ERROR_ACK         :bit1;
  AUX_GTC_SYNC_ERROR_INT_MASK    :bit1;
  RESERVED3                      :bit17;
 end;

 TAZALIA_F0_CODEC_DEBUG=bitpacked record
  DISABLE_FORMAT_COMPARISON:bit6;
  CODEC_DEBUG              :bit26;
 end;

 TAZALIA_MEM_PWR_STATUS=bitpacked record
  AZ_MEM_PWR_STATE              :bit2;
  AZ_INPUT_STREAM0_MEM_PWR_STATE:bit2;
  AZ_INPUT_STREAM1_MEM_PWR_STATE:bit2;
  AZ_INPUT_STREAM2_MEM_PWR_STATE:bit2;
  AZ_INPUT_STREAM3_MEM_PWR_STATE:bit2;
  AZ_INPUT_STREAM4_MEM_PWR_STATE:bit2;
  AZ_INPUT_STREAM5_MEM_PWR_STATE:bit2;
  RESERVED0                     :bit18;
 end;

 TBIF_MM_INDACCESS_CNTL=bitpacked record
  RESERVED0       :bit1;
  MM_INDACCESS_DIS:bit1;
  RESERVED1       :bit30;
 end;

 TBIF_MST_TRANS_PENDING=bit32;

 TBIF_SLV_TRANS_PENDING=bit32;

 TBIF_VDDGFX_GFX0_LOWER=bitpacked record
  RESERVED0               :bit2;
  VDDGFX_GFX0_REG_LOWER   :bit16;
  RESERVED1               :bit12;
  VDDGFX_GFX0_REG_CMP_EN  :bit1;
  VDDGFX_GFX0_REG_STALL_EN:bit1;
 end;

 TBIF_VDDGFX_GFX0_UPPER=bitpacked record
  RESERVED0            :bit2;
  VDDGFX_GFX0_REG_UPPER:bit16;
  RESERVED1            :bit14;
 end;

 TBIF_VDDGFX_GFX1_LOWER=bitpacked record
  RESERVED0               :bit2;
  VDDGFX_GFX1_REG_LOWER   :bit16;
  RESERVED1               :bit12;
  VDDGFX_GFX1_REG_CMP_EN  :bit1;
  VDDGFX_GFX1_REG_STALL_EN:bit1;
 end;

 TBIF_VDDGFX_GFX1_UPPER=bitpacked record
  RESERVED0            :bit2;
  VDDGFX_GFX1_REG_UPPER:bit16;
  RESERVED1            :bit14;
 end;

 TBIF_VDDGFX_GFX2_LOWER=bitpacked record
  RESERVED0               :bit2;
  VDDGFX_GFX2_REG_LOWER   :bit16;
  RESERVED1               :bit12;
  VDDGFX_GFX2_REG_CMP_EN  :bit1;
  VDDGFX_GFX2_REG_STALL_EN:bit1;
 end;

 TBIF_VDDGFX_GFX2_UPPER=bitpacked record
  RESERVED0            :bit2;
  VDDGFX_GFX2_REG_UPPER:bit16;
  RESERVED1            :bit14;
 end;

 TBIF_VDDGFX_GFX3_LOWER=bitpacked record
  RESERVED0               :bit2;
  VDDGFX_GFX3_REG_LOWER   :bit16;
  RESERVED1               :bit12;
  VDDGFX_GFX3_REG_CMP_EN  :bit1;
  VDDGFX_GFX3_REG_STALL_EN:bit1;
 end;

 TBIF_VDDGFX_GFX3_UPPER=bitpacked record
  RESERVED0            :bit2;
  VDDGFX_GFX3_REG_UPPER:bit16;
  RESERVED1            :bit14;
 end;

 TBIF_VDDGFX_GFX4_LOWER=bitpacked record
  RESERVED0               :bit2;
  VDDGFX_GFX4_REG_LOWER   :bit16;
  RESERVED1               :bit12;
  VDDGFX_GFX4_REG_CMP_EN  :bit1;
  VDDGFX_GFX4_REG_STALL_EN:bit1;
 end;

 TBIF_VDDGFX_GFX4_UPPER=bitpacked record
  RESERVED0            :bit2;
  VDDGFX_GFX4_REG_UPPER:bit16;
  RESERVED1            :bit14;
 end;

 TBIF_VDDGFX_GFX5_LOWER=bitpacked record
  RESERVED0               :bit2;
  VDDGFX_GFX5_REG_LOWER   :bit16;
  RESERVED1               :bit12;
  VDDGFX_GFX5_REG_CMP_EN  :bit1;
  VDDGFX_GFX5_REG_STALL_EN:bit1;
 end;

 TBIF_VDDGFX_GFX5_UPPER=bitpacked record
  RESERVED0            :bit2;
  VDDGFX_GFX5_REG_UPPER:bit16;
  RESERVED1            :bit14;
 end;

 TBIF_VDDGFX_RSV1_LOWER=bitpacked record
  RESERVED0               :bit2;
  VDDGFX_RSV1_REG_LOWER   :bit16;
  RESERVED1               :bit12;
  VDDGFX_RSV1_REG_CMP_EN  :bit1;
  VDDGFX_RSV1_REG_STALL_EN:bit1;
 end;

 TBIF_VDDGFX_RSV1_UPPER=bitpacked record
  RESERVED0            :bit2;
  VDDGFX_RSV1_REG_UPPER:bit16;
  RESERVED1            :bit14;
 end;

 TBIF_VDDGFX_RSV2_LOWER=bitpacked record
  RESERVED0               :bit2;
  VDDGFX_RSV2_REG_LOWER   :bit16;
  RESERVED1               :bit12;
  VDDGFX_RSV2_REG_CMP_EN  :bit1;
  VDDGFX_RSV2_REG_STALL_EN:bit1;
 end;

 TBIF_VDDGFX_RSV2_UPPER=bitpacked record
  RESERVED0            :bit2;
  VDDGFX_RSV2_REG_UPPER:bit16;
  RESERVED1            :bit14;
 end;

 TBIF_VDDGFX_RSV3_LOWER=bitpacked record
  RESERVED0               :bit2;
  VDDGFX_RSV3_REG_LOWER   :bit16;
  RESERVED1               :bit12;
  VDDGFX_RSV3_REG_CMP_EN  :bit1;
  VDDGFX_RSV3_REG_STALL_EN:bit1;
 end;

 TBIF_VDDGFX_RSV3_UPPER=bitpacked record
  RESERVED0            :bit2;
  VDDGFX_RSV3_REG_UPPER:bit16;
  RESERVED1            :bit14;
 end;

 TBIF_VDDGFX_RSV4_LOWER=bitpacked record
  RESERVED0               :bit2;
  VDDGFX_RSV4_REG_LOWER   :bit16;
  RESERVED1               :bit12;
  VDDGFX_RSV4_REG_CMP_EN  :bit1;
  VDDGFX_RSV4_REG_STALL_EN:bit1;
 end;

 TBIF_VDDGFX_RSV4_UPPER=bitpacked record
  RESERVED0            :bit2;
  VDDGFX_RSV4_REG_UPPER:bit16;
  RESERVED1            :bit14;
 end;

 TBL1_PWM_GRP2_REG_LOCK=bitpacked record
  BL1_PWM_GRP2_REG_LOCK                :bit1;
  RESERVED0                            :bit7;
  BL1_PWM_GRP2_REG_UPDATE_PENDING      :bit1;
  RESERVED1                            :bit7;
  BL1_PWM_GRP2_UPDATE_AT_FRAME_START   :bit1;
  BL1_PWM_GRP2_FRAME_START_DISP_SEL    :bit3;
  RESERVED2                            :bit4;
  BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN:bit1;
  RESERVED3                            :bit6;
  BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN   :bit1;
 end;

 TBLND_TEST_DEBUG_INDEX=bitpacked record
  BLND_TEST_DEBUG_INDEX   :bit8;
  BLND_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0               :bit23;
 end;

 TCB_COLOR0_CLEAR_WORD0=bit32;

 TCB_COLOR0_CLEAR_WORD1=bit32;

 TCB_COLOR0_CMASK_SLICE=bitpacked record
  TILE_MAX :bit14;
  RESERVED0:bit18;
 end;

 TCB_COLOR0_DCC_CONTROL=bitpacked record
  OVERWRITE_COMBINER_DISABLE :bit1;
  KEY_CLEAR_ENABLE           :bit1;
  MAX_UNCOMPRESSED_BLOCK_SIZE:bit2;
  MIN_COMPRESSED_BLOCK_SIZE  :bit1;
  MAX_COMPRESSED_BLOCK_SIZE  :bit2;
  COLOR_TRANSFORM            :bit2;
  INDEPENDENT_64B_BLOCKS     :bit1;
  LOSSY_RGB_PRECISION        :bit4;
  LOSSY_ALPHA_PRECISION      :bit4;
  RESERVED0                  :bit14;
 end;

 TCB_COLOR0_FMASK_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR1_CLEAR_WORD0=bit32;

 TCB_COLOR1_CLEAR_WORD1=bit32;

 TCB_COLOR1_CMASK_SLICE=bitpacked record
  TILE_MAX :bit14;
  RESERVED0:bit18;
 end;

 TCB_COLOR1_DCC_CONTROL=bitpacked record
  OVERWRITE_COMBINER_DISABLE :bit1;
  KEY_CLEAR_ENABLE           :bit1;
  MAX_UNCOMPRESSED_BLOCK_SIZE:bit2;
  MIN_COMPRESSED_BLOCK_SIZE  :bit1;
  MAX_COMPRESSED_BLOCK_SIZE  :bit2;
  COLOR_TRANSFORM            :bit2;
  INDEPENDENT_64B_BLOCKS     :bit1;
  LOSSY_RGB_PRECISION        :bit4;
  LOSSY_ALPHA_PRECISION      :bit4;
  RESERVED0                  :bit14;
 end;

 TCB_COLOR1_FMASK_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR2_CLEAR_WORD0=bit32;

 TCB_COLOR2_CLEAR_WORD1=bit32;

 TCB_COLOR2_CMASK_SLICE=bitpacked record
  TILE_MAX :bit14;
  RESERVED0:bit18;
 end;

 TCB_COLOR2_DCC_CONTROL=bitpacked record
  OVERWRITE_COMBINER_DISABLE :bit1;
  KEY_CLEAR_ENABLE           :bit1;
  MAX_UNCOMPRESSED_BLOCK_SIZE:bit2;
  MIN_COMPRESSED_BLOCK_SIZE  :bit1;
  MAX_COMPRESSED_BLOCK_SIZE  :bit2;
  COLOR_TRANSFORM            :bit2;
  INDEPENDENT_64B_BLOCKS     :bit1;
  LOSSY_RGB_PRECISION        :bit4;
  LOSSY_ALPHA_PRECISION      :bit4;
  RESERVED0                  :bit14;
 end;

 TCB_COLOR2_FMASK_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR3_CLEAR_WORD0=bit32;

 TCB_COLOR3_CLEAR_WORD1=bit32;

 TCB_COLOR3_CMASK_SLICE=bitpacked record
  TILE_MAX :bit14;
  RESERVED0:bit18;
 end;

 TCB_COLOR3_DCC_CONTROL=bitpacked record
  OVERWRITE_COMBINER_DISABLE :bit1;
  KEY_CLEAR_ENABLE           :bit1;
  MAX_UNCOMPRESSED_BLOCK_SIZE:bit2;
  MIN_COMPRESSED_BLOCK_SIZE  :bit1;
  MAX_COMPRESSED_BLOCK_SIZE  :bit2;
  COLOR_TRANSFORM            :bit2;
  INDEPENDENT_64B_BLOCKS     :bit1;
  LOSSY_RGB_PRECISION        :bit4;
  LOSSY_ALPHA_PRECISION      :bit4;
  RESERVED0                  :bit14;
 end;

 TCB_COLOR3_FMASK_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR4_CLEAR_WORD0=bit32;

 TCB_COLOR4_CLEAR_WORD1=bit32;

 TCB_COLOR4_CMASK_SLICE=bitpacked record
  TILE_MAX :bit14;
  RESERVED0:bit18;
 end;

 TCB_COLOR4_DCC_CONTROL=bitpacked record
  OVERWRITE_COMBINER_DISABLE :bit1;
  KEY_CLEAR_ENABLE           :bit1;
  MAX_UNCOMPRESSED_BLOCK_SIZE:bit2;
  MIN_COMPRESSED_BLOCK_SIZE  :bit1;
  MAX_COMPRESSED_BLOCK_SIZE  :bit2;
  COLOR_TRANSFORM            :bit2;
  INDEPENDENT_64B_BLOCKS     :bit1;
  LOSSY_RGB_PRECISION        :bit4;
  LOSSY_ALPHA_PRECISION      :bit4;
  RESERVED0                  :bit14;
 end;

 TCB_COLOR4_FMASK_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR5_CLEAR_WORD0=bit32;

 TCB_COLOR5_CLEAR_WORD1=bit32;

 TCB_COLOR5_CMASK_SLICE=bitpacked record
  TILE_MAX :bit14;
  RESERVED0:bit18;
 end;

 TCB_COLOR5_DCC_CONTROL=bitpacked record
  OVERWRITE_COMBINER_DISABLE :bit1;
  KEY_CLEAR_ENABLE           :bit1;
  MAX_UNCOMPRESSED_BLOCK_SIZE:bit2;
  MIN_COMPRESSED_BLOCK_SIZE  :bit1;
  MAX_COMPRESSED_BLOCK_SIZE  :bit2;
  COLOR_TRANSFORM            :bit2;
  INDEPENDENT_64B_BLOCKS     :bit1;
  LOSSY_RGB_PRECISION        :bit4;
  LOSSY_ALPHA_PRECISION      :bit4;
  RESERVED0                  :bit14;
 end;

 TCB_COLOR5_FMASK_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR6_CLEAR_WORD0=bit32;

 TCB_COLOR6_CLEAR_WORD1=bit32;

 TCB_COLOR6_CMASK_SLICE=bitpacked record
  TILE_MAX :bit14;
  RESERVED0:bit18;
 end;

 TCB_COLOR6_DCC_CONTROL=bitpacked record
  OVERWRITE_COMBINER_DISABLE :bit1;
  KEY_CLEAR_ENABLE           :bit1;
  MAX_UNCOMPRESSED_BLOCK_SIZE:bit2;
  MIN_COMPRESSED_BLOCK_SIZE  :bit1;
  MAX_COMPRESSED_BLOCK_SIZE  :bit2;
  COLOR_TRANSFORM            :bit2;
  INDEPENDENT_64B_BLOCKS     :bit1;
  LOSSY_RGB_PRECISION        :bit4;
  LOSSY_ALPHA_PRECISION      :bit4;
  RESERVED0                  :bit14;
 end;

 TCB_COLOR6_FMASK_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_COLOR7_CLEAR_WORD0=bit32;

 TCB_COLOR7_CLEAR_WORD1=bit32;

 TCB_COLOR7_CMASK_SLICE=bitpacked record
  TILE_MAX :bit14;
  RESERVED0:bit18;
 end;

 TCB_COLOR7_DCC_CONTROL=bitpacked record
  OVERWRITE_COMBINER_DISABLE :bit1;
  KEY_CLEAR_ENABLE           :bit1;
  MAX_UNCOMPRESSED_BLOCK_SIZE:bit2;
  MIN_COMPRESSED_BLOCK_SIZE  :bit1;
  MAX_COMPRESSED_BLOCK_SIZE  :bit2;
  COLOR_TRANSFORM            :bit2;
  INDEPENDENT_64B_BLOCKS     :bit1;
  LOSSY_RGB_PRECISION        :bit4;
  LOSSY_ALPHA_PRECISION      :bit4;
  RESERVED0                  :bit14;
 end;

 TCB_COLOR7_FMASK_SLICE=bitpacked record
  TILE_MAX :bit22;
  RESERVED0:bit10;
 end;

 TCB_PERFCOUNTER_FILTER=bitpacked record
  OP_FILTER_ENABLE           :bit1;
  OP_FILTER_SEL              :bit3;
  FORMAT_FILTER_ENABLE       :bit1;
  FORMAT_FILTER_SEL          :bit5;
  CLEAR_FILTER_ENABLE        :bit1;
  CLEAR_FILTER_SEL           :bit1;
  MRT_FILTER_ENABLE          :bit1;
  MRT_FILTER_SEL             :bit3;
  RESERVED0                  :bit1;
  NUM_SAMPLES_FILTER_ENABLE  :bit1;
  NUM_SAMPLES_FILTER_SEL     :bit3;
  NUM_FRAGMENTS_FILTER_ENABLE:bit1;
  NUM_FRAGMENTS_FILTER_SEL   :bit2;
  RESERVED1                  :bit8;
 end;

 TCC_RB_BACKEND_DISABLE=bitpacked record
  RESERVED0      :bit1;
  RESERVED1      :bit15;
  BACKEND_DISABLE:bit8;
  RESERVED2      :bit8;
 end;

 TCGTS_CU0_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU0_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU10_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU11_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU13_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU14_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU15_TA_CTRL_REG=bitpacked record
  TA                  :bit7;
  TA_OVERRIDE         :bit1;
  TA_BUSY_OVERRIDE    :bit2;
  TA_LS_OVERRIDE      :bit1;
  TA_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0           :bit20;
 end;

 TCGTS_CU1_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU1_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU2_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU2_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU3_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU3_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU4_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU4_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU5_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU5_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU6_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU6_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU7_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU7_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU8_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU8_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU9_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU9_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_USER_TCC_DISABLE=bitpacked record
  RESERVED0  :bit16;
  TCC_DISABLE:bit16;
 end;

 TCG_FREQ_TRAN_VOTING_0=bitpacked record
  BIF_FREQ_THROTTLING_VOTE_EN    :bit1;
  HDP_FREQ_THROTTLING_VOTE_EN    :bit1;
  ROM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1;
  PDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  DRM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IDCT_FREQ_THROTTLING_VOTE_EN   :bit1;
  ACP_FREQ_THROTTLING_VOTE_EN    :bit1;
  SDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  UVD_FREQ_THROTTLING_VOTE_EN    :bit1;
  VCE_FREQ_THROTTLING_VOTE_EN    :bit1;
  DC_AZ_FREQ_THROTTLING_VOTE_EN  :bit1;
  SAM_FREQ_THROTTLING_VOTE_EN    :bit1;
  AVP_FREQ_THROTTLING_VOTE_EN    :bit1;
  GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1;
  RLC_FREQ_THROTTLING_VOTE_EN    :bit1;
  RESERVED0                      :bit1;
 end;

 TCG_FREQ_TRAN_VOTING_1=bitpacked record
  BIF_FREQ_THROTTLING_VOTE_EN    :bit1;
  HDP_FREQ_THROTTLING_VOTE_EN    :bit1;
  ROM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1;
  PDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  DRM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IDCT_FREQ_THROTTLING_VOTE_EN   :bit1;
  ACP_FREQ_THROTTLING_VOTE_EN    :bit1;
  SDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  UVD_FREQ_THROTTLING_VOTE_EN    :bit1;
  VCE_FREQ_THROTTLING_VOTE_EN    :bit1;
  DC_AZ_FREQ_THROTTLING_VOTE_EN  :bit1;
  SAM_FREQ_THROTTLING_VOTE_EN    :bit1;
  AVP_FREQ_THROTTLING_VOTE_EN    :bit1;
  GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1;
  RLC_FREQ_THROTTLING_VOTE_EN    :bit1;
  RESERVED0                      :bit1;
 end;

 TCG_FREQ_TRAN_VOTING_2=bitpacked record
  BIF_FREQ_THROTTLING_VOTE_EN    :bit1;
  HDP_FREQ_THROTTLING_VOTE_EN    :bit1;
  ROM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1;
  PDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  DRM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IDCT_FREQ_THROTTLING_VOTE_EN   :bit1;
  ACP_FREQ_THROTTLING_VOTE_EN    :bit1;
  SDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  UVD_FREQ_THROTTLING_VOTE_EN    :bit1;
  VCE_FREQ_THROTTLING_VOTE_EN    :bit1;
  DC_AZ_FREQ_THROTTLING_VOTE_EN  :bit1;
  SAM_FREQ_THROTTLING_VOTE_EN    :bit1;
  AVP_FREQ_THROTTLING_VOTE_EN    :bit1;
  GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1;
  RLC_FREQ_THROTTLING_VOTE_EN    :bit1;
  RESERVED0                      :bit1;
 end;

 TCG_FREQ_TRAN_VOTING_3=bitpacked record
  BIF_FREQ_THROTTLING_VOTE_EN    :bit1;
  HDP_FREQ_THROTTLING_VOTE_EN    :bit1;
  ROM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1;
  PDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  DRM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IDCT_FREQ_THROTTLING_VOTE_EN   :bit1;
  ACP_FREQ_THROTTLING_VOTE_EN    :bit1;
  SDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  UVD_FREQ_THROTTLING_VOTE_EN    :bit1;
  VCE_FREQ_THROTTLING_VOTE_EN    :bit1;
  DC_AZ_FREQ_THROTTLING_VOTE_EN  :bit1;
  SAM_FREQ_THROTTLING_VOTE_EN    :bit1;
  AVP_FREQ_THROTTLING_VOTE_EN    :bit1;
  GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1;
  RLC_FREQ_THROTTLING_VOTE_EN    :bit1;
  RESERVED0                      :bit1;
 end;

 TCG_FREQ_TRAN_VOTING_4=bitpacked record
  BIF_FREQ_THROTTLING_VOTE_EN    :bit1;
  HDP_FREQ_THROTTLING_VOTE_EN    :bit1;
  ROM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1;
  PDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  DRM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IDCT_FREQ_THROTTLING_VOTE_EN   :bit1;
  ACP_FREQ_THROTTLING_VOTE_EN    :bit1;
  SDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  UVD_FREQ_THROTTLING_VOTE_EN    :bit1;
  VCE_FREQ_THROTTLING_VOTE_EN    :bit1;
  DC_AZ_FREQ_THROTTLING_VOTE_EN  :bit1;
  SAM_FREQ_THROTTLING_VOTE_EN    :bit1;
  AVP_FREQ_THROTTLING_VOTE_EN    :bit1;
  GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1;
  RLC_FREQ_THROTTLING_VOTE_EN    :bit1;
  RESERVED0                      :bit1;
 end;

 TCG_FREQ_TRAN_VOTING_5=bitpacked record
  BIF_FREQ_THROTTLING_VOTE_EN    :bit1;
  HDP_FREQ_THROTTLING_VOTE_EN    :bit1;
  ROM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1;
  PDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  DRM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IDCT_FREQ_THROTTLING_VOTE_EN   :bit1;
  ACP_FREQ_THROTTLING_VOTE_EN    :bit1;
  SDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  UVD_FREQ_THROTTLING_VOTE_EN    :bit1;
  VCE_FREQ_THROTTLING_VOTE_EN    :bit1;
  DC_AZ_FREQ_THROTTLING_VOTE_EN  :bit1;
  SAM_FREQ_THROTTLING_VOTE_EN    :bit1;
  AVP_FREQ_THROTTLING_VOTE_EN    :bit1;
  GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1;
  RLC_FREQ_THROTTLING_VOTE_EN    :bit1;
  RESERVED0                      :bit1;
 end;

 TCG_FREQ_TRAN_VOTING_6=bitpacked record
  BIF_FREQ_THROTTLING_VOTE_EN    :bit1;
  HDP_FREQ_THROTTLING_VOTE_EN    :bit1;
  ROM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1;
  PDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  DRM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IDCT_FREQ_THROTTLING_VOTE_EN   :bit1;
  ACP_FREQ_THROTTLING_VOTE_EN    :bit1;
  SDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  UVD_FREQ_THROTTLING_VOTE_EN    :bit1;
  VCE_FREQ_THROTTLING_VOTE_EN    :bit1;
  DC_AZ_FREQ_THROTTLING_VOTE_EN  :bit1;
  SAM_FREQ_THROTTLING_VOTE_EN    :bit1;
  AVP_FREQ_THROTTLING_VOTE_EN    :bit1;
  GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1;
  RLC_FREQ_THROTTLING_VOTE_EN    :bit1;
  RESERVED0                      :bit1;
 end;

 TCG_FREQ_TRAN_VOTING_7=bitpacked record
  BIF_FREQ_THROTTLING_VOTE_EN    :bit1;
  HDP_FREQ_THROTTLING_VOTE_EN    :bit1;
  ROM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1;
  PDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  DRM_FREQ_THROTTLING_VOTE_EN    :bit1;
  IDCT_FREQ_THROTTLING_VOTE_EN   :bit1;
  ACP_FREQ_THROTTLING_VOTE_EN    :bit1;
  SDMA_FREQ_THROTTLING_VOTE_EN   :bit1;
  UVD_FREQ_THROTTLING_VOTE_EN    :bit1;
  VCE_FREQ_THROTTLING_VOTE_EN    :bit1;
  DC_AZ_FREQ_THROTTLING_VOTE_EN  :bit1;
  SAM_FREQ_THROTTLING_VOTE_EN    :bit1;
  AVP_FREQ_THROTTLING_VOTE_EN    :bit1;
  GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1;
  GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1;
  GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1;
  RLC_FREQ_THROTTLING_VOTE_EN    :bit1;
  RESERVED0                      :bit1;
 end;

 TCG_THERMAL_INT_STATUS=bitpacked record
  THERM_INTH_DETECT       :bit1;
  THERM_INTL_DETECT       :bit1;
  THERM_TRIGGER_DETECT    :bit1;
  THERM_TRIGGER_CNB_DETECT:bit1;
  RESERVED0               :bit28;
 end;

 TCOL_MAN_DEBUG_CONTROL=bitpacked record
  COL_MAN_GLOBAL_PASSTHROUGH_ENABLE:bit1;
  RESERVED0                        :bit31;
 end;

 TCOMPUTE_MISC_RESERVED=bitpacked record
  SEND_SEID   :bit2;
  RESERVED0   :bit3;
  WAVE_ID_BASE:bit12;
  RESERVED1   :bit15;
 end;

 TCP_CPC_MGCG_SYNC_CNTL=bitpacked record
  COOLDOWN_PERIOD:bit8;
  WARMUP_PERIOD  :bit8;
  RESERVED0      :bit16;
 end;

 TCP_DISPATCH_INDR_ADDR=bit32;

 TCP_DMA_ME_DST_ADDR_HI=bitpacked record
  DST_ADDR_HI:bit16;
  RESERVED0  :bit16;
 end;

 TCP_DMA_ME_SRC_ADDR_HI=bitpacked record
  SRC_ADDR_HI:bit16;
  RESERVED0  :bit4;
  RESERVED1  :bit2;
  RESERVED2  :bit7;
  RESERVED3  :bit2;
  RESERVED4  :bit1;
 end;

 TCP_EOP_DONE_DATA_CNTL=bitpacked record
  CNTX_ID  :bit16;
  DST_SEL  :bit2;
  RESERVED0:bit6;
  INT_SEL  :bit3;
  RESERVED1:bit2;
  DATA_SEL :bit3;
 end;

 TCP_HQD_QUEUE_PRIORITY=bitpacked record
  PRIORITY_LEVEL:bit4;
  RESERVED0     :bit28;
 end;

 TCP_IB1_PREAMBLE_BEGIN=bitpacked record
  IB1_PREAMBLE_BEGIN:bit20;
  RESERVED0         :bit12;
 end;

 TCP_IB2_PREAMBLE_BEGIN=bitpacked record
  IB2_PREAMBLE_BEGIN:bit20;
  RESERVED0         :bit12;
 end;

 TCP_INDEX_BASE_ADDR_HI=bitpacked record
  ADDR_HI  :bit16;
  RESERVED0:bit16;
 end;

 TCP_ME0_PIPE0_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ME0_PIPE1_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ME0_PIPE2_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ME1_INT_STAT_DEBUG=bitpacked record
  RESERVED0                      :bit12;
  CMP_QUERY_STATUS_INT_ASSERTED  :bit1;
  DEQUEUE_REQUEST_INT_ASSERTED   :bit1;
  CP_ECC_ERROR_INT_ASSERTED      :bit1;
  SUA_VIOLATION_INT_STATUS       :bit1;
  RESERVED1                      :bit1;
  WRM_POLL_TIMEOUT_INT_ASSERTED  :bit1;
  RESERVED2                      :bit5;
  PRIV_REG_INT_ASSERTED          :bit1;
  OPCODE_ERROR_INT_ASSERTED      :bit1;
  RESERVED3                      :bit1;
  TIME_STAMP_INT_ASSERTED        :bit1;
  RESERVED_BIT_ERROR_INT_ASSERTED:bit1;
  RESERVED4                      :bit1;
  GENERIC2_INT_ASSERTED          :bit1;
  GENERIC1_INT_ASSERTED          :bit1;
  GENERIC0_INT_ASSERTED          :bit1;
 end;

 TCP_ME1_PIPE0_INT_CNTL=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_ENABLE  :bit1;
  DEQUEUE_REQUEST_INT_ENABLE   :bit1;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  SUA_VIOLATION_INT_ENABLE     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_ME1_PIPE0_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ME1_PIPE1_INT_CNTL=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_ENABLE  :bit1;
  DEQUEUE_REQUEST_INT_ENABLE   :bit1;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  SUA_VIOLATION_INT_ENABLE     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_ME1_PIPE1_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ME1_PIPE2_INT_CNTL=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_ENABLE  :bit1;
  DEQUEUE_REQUEST_INT_ENABLE   :bit1;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  SUA_VIOLATION_INT_ENABLE     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_ME1_PIPE2_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ME1_PIPE3_INT_CNTL=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_ENABLE  :bit1;
  DEQUEUE_REQUEST_INT_ENABLE   :bit1;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  SUA_VIOLATION_INT_ENABLE     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_ME1_PIPE3_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ME2_INT_STAT_DEBUG=bitpacked record
  RESERVED0                      :bit12;
  CMP_QUERY_STATUS_INT_ASSERTED  :bit1;
  DEQUEUE_REQUEST_INT_ASSERTED   :bit1;
  CP_ECC_ERROR_INT_ASSERTED      :bit1;
  SUA_VIOLATION_INT_STATUS       :bit1;
  RESERVED1                      :bit1;
  WRM_POLL_TIMEOUT_INT_ASSERTED  :bit1;
  RESERVED2                      :bit5;
  PRIV_REG_INT_ASSERTED          :bit1;
  OPCODE_ERROR_INT_ASSERTED      :bit1;
  RESERVED3                      :bit1;
  TIME_STAMP_INT_ASSERTED        :bit1;
  RESERVED_BIT_ERROR_INT_ASSERTED:bit1;
  RESERVED4                      :bit1;
  GENERIC2_INT_ASSERTED          :bit1;
  GENERIC1_INT_ASSERTED          :bit1;
  GENERIC0_INT_ASSERTED          :bit1;
 end;

 TCP_ME2_PIPE0_INT_CNTL=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_ENABLE  :bit1;
  DEQUEUE_REQUEST_INT_ENABLE   :bit1;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  SUA_VIOLATION_INT_ENABLE     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_ME2_PIPE0_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ME2_PIPE1_INT_CNTL=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_ENABLE  :bit1;
  DEQUEUE_REQUEST_INT_ENABLE   :bit1;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  SUA_VIOLATION_INT_ENABLE     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_ME2_PIPE1_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ME2_PIPE2_INT_CNTL=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_ENABLE  :bit1;
  DEQUEUE_REQUEST_INT_ENABLE   :bit1;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  SUA_VIOLATION_INT_ENABLE     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_ME2_PIPE2_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_ME2_PIPE3_INT_CNTL=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_ENABLE  :bit1;
  DEQUEUE_REQUEST_INT_ENABLE   :bit1;
  CP_ECC_ERROR_INT_ENABLE      :bit1;
  SUA_VIOLATION_INT_ENABLE     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_ENABLE  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_ENABLE          :bit1;
  OPCODE_ERROR_INT_ENABLE      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_ENABLE        :bit1;
  RESERVED_BIT_ERROR_INT_ENABLE:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_ENABLE          :bit1;
  GENERIC1_INT_ENABLE          :bit1;
  GENERIC0_INT_ENABLE          :bit1;
 end;

 TCP_ME2_PIPE3_PRIORITY=bitpacked record
  PRIORITY :bit2;
  RESERVED0:bit30;
 end;

 TCP_MEC1_F32_INTERRUPT=bitpacked record
  RESERVED0   :bit1;
  PRIV_REG_INT:bit1;
  RESERVED1   :bit1;
  RESERVED2   :bit1;
  RESERVED3   :bit1;
  RESERVED4   :bit1;
  RESERVED5   :bit1;
  RESERVED6   :bit1;
  RESERVED7   :bit1;
  RESERVED8   :bit1;
  RESERVED9   :bit22;
 end;

 TCP_MEC2_F32_INTERRUPT=bitpacked record
  RESERVED0   :bit1;
  PRIV_REG_INT:bit1;
  RESERVED1   :bit1;
  RESERVED2   :bit1;
  RESERVED3   :bit1;
  RESERVED4   :bit1;
  RESERVED5   :bit1;
  RESERVED6   :bit1;
  RESERVED7   :bit1;
  RESERVED8   :bit1;
  RESERVED9   :bit22;
 end;

 TCP_MEC_ME1_UCODE_ADDR=bitpacked record
  UCODE_ADDR:bit17;
  RESERVED0 :bit15;
 end;

 TCP_MEC_ME1_UCODE_DATA=bit32;

 TCP_MEC_ME2_UCODE_ADDR=bitpacked record
  UCODE_ADDR:bit17;
  RESERVED0 :bit15;
 end;

 TCP_MEC_ME2_UCODE_DATA=bit32;

 TCP_ME_ATOMIC_PREOP_HI=bit32;

 TCP_ME_ATOMIC_PREOP_LO=bit32;

 TCP_PA_CINVOC_COUNT_HI=bit32;

 TCP_PA_CINVOC_COUNT_LO=bit32;

 TCP_PERFCOUNTER_SELECT=bitpacked record
  RESERVED0:bit6;
  RESERVED1:bit26;
 end;

 TCP_PIPE_STATS_ADDR_HI=bitpacked record
  PIPE_STATS_ADDR_HI:bit16;
  RESERVED0         :bit16;
 end;

 TCP_PIPE_STATS_ADDR_LO=bitpacked record
  PIPE_STATS_ADDR_SWAP:bit2;
  PIPE_STATS_ADDR_LO  :bit30;
 end;

 TCP_PIPE_STATS_CONTROL=bitpacked record
  RESERVED0    :bit25;
  CACHE_CONTROL:bit1;
  RESERVED1    :bit1;
  MTYPE        :bit2;
  RESERVED2    :bit3;
 end;

 TCP_PQ_WPTR_POLL_CNTL1=bit32;

 TCP_RING_PRIORITY_CNTS=bitpacked record
  PRIORITY1_CNT :bit8;
  PRIORITY2A_CNT:bit8;
  PRIORITY2B_CNT:bit8;
  PRIORITY3_CNT :bit8;
 end;

 TCP_STREAM_OUT_ADDR_HI=bitpacked record
  STREAM_OUT_ADDR_HI:bit16;
  RESERVED0         :bit16;
 end;

 TCP_STREAM_OUT_ADDR_LO=bitpacked record
  STREAM_OUT_ADDR_SWAP:bit2;
  STREAM_OUT_ADDR_LO  :bit30;
 end;

 TCP_STREAM_OUT_CONTROL=bitpacked record
  RESERVED0    :bit25;
  CACHE_CONTROL:bit1;
  RESERVED1    :bit1;
  MTYPE        :bit2;
  RESERVED2    :bit3;
 end;

 TCRTC0_PIXEL_RATE_CNTL=bitpacked record
  CRTC0_PIXEL_RATE_SOURCE  :bit2;
  RESERVED0                :bit2;
  DP_DTO0_ENABLE           :bit1;
  DP_DTO0_DS_DISABLE       :bit1;
  RESERVED1                :bit2;
  CRTC0_ADD_PIXEL          :bit1;
  CRTC0_DROP_PIXEL         :bit1;
  RESERVED2                :bit4;
  CRTC0_DISPOUT_FIFO_ERROR :bit2;
  CRTC0_DISPOUT_ERROR_COUNT:bit12;
  RESERVED3                :bit4;
 end;

 TCRTC1_PIXEL_RATE_CNTL=bitpacked record
  CRTC1_PIXEL_RATE_SOURCE  :bit2;
  RESERVED0                :bit2;
  DP_DTO1_ENABLE           :bit1;
  DP_DTO1_DS_DISABLE       :bit1;
  RESERVED1                :bit2;
  CRTC1_ADD_PIXEL          :bit1;
  CRTC1_DROP_PIXEL         :bit1;
  RESERVED2                :bit4;
  CRTC1_DISPOUT_FIFO_ERROR :bit2;
  CRTC1_DISPOUT_ERROR_COUNT:bit12;
  RESERVED3                :bit4;
 end;

 TCRTC2_PIXEL_RATE_CNTL=bitpacked record
  CRTC2_PIXEL_RATE_SOURCE  :bit2;
  RESERVED0                :bit2;
  DP_DTO2_ENABLE           :bit1;
  DP_DTO2_DS_DISABLE       :bit1;
  RESERVED1                :bit2;
  CRTC2_ADD_PIXEL          :bit1;
  CRTC2_DROP_PIXEL         :bit1;
  RESERVED2                :bit4;
  CRTC2_DISPOUT_FIFO_ERROR :bit2;
  CRTC2_DISPOUT_ERROR_COUNT:bit12;
  RESERVED3                :bit4;
 end;

 TCRTC3_PIXEL_RATE_CNTL=bitpacked record
  CRTC3_PIXEL_RATE_SOURCE  :bit2;
  RESERVED0                :bit2;
  DP_DTO3_ENABLE           :bit1;
  DP_DTO3_DS_DISABLE       :bit1;
  RESERVED1                :bit2;
  CRTC3_ADD_PIXEL          :bit1;
  CRTC3_DROP_PIXEL         :bit1;
  RESERVED2                :bit4;
  CRTC3_DISPOUT_FIFO_ERROR :bit2;
  CRTC3_DISPOUT_ERROR_COUNT:bit12;
  RESERVED3                :bit4;
 end;

 TCRTC4_PIXEL_RATE_CNTL=bitpacked record
  CRTC4_PIXEL_RATE_SOURCE  :bit2;
  RESERVED0                :bit2;
  DP_DTO4_ENABLE           :bit1;
  DP_DTO4_DS_DISABLE       :bit1;
  RESERVED1                :bit2;
  CRTC4_ADD_PIXEL          :bit1;
  CRTC4_DROP_PIXEL         :bit1;
  RESERVED2                :bit4;
  CRTC4_DISPOUT_FIFO_ERROR :bit2;
  CRTC4_DISPOUT_ERROR_COUNT:bit12;
  RESERVED3                :bit4;
 end;

 TCRTC5_PIXEL_RATE_CNTL=bitpacked record
  CRTC5_PIXEL_RATE_SOURCE  :bit2;
  RESERVED0                :bit2;
  DP_DTO5_ENABLE           :bit1;
  DP_DTO5_DS_DISABLE       :bit1;
  RESERVED1                :bit2;
  CRTC5_ADD_PIXEL          :bit1;
  CRTC5_DROP_PIXEL         :bit1;
  RESERVED2                :bit4;
  CRTC5_DISPOUT_FIFO_ERROR :bit2;
  CRTC5_DISPOUT_ERROR_COUNT:bit12;
  RESERVED3                :bit4;
 end;

 TCRTC_BLANK_DATA_COLOR=bitpacked record
  CRTC_BLANK_DATA_COLOR_BLUE_CB:bit10;
  CRTC_BLANK_DATA_COLOR_GREEN_Y:bit10;
  CRTC_BLANK_DATA_COLOR_RED_CR :bit10;
  RESERVED0                    :bit2;
 end;

 TCRTC_INTERLACE_STATUS=bitpacked record
  CRTC_INTERLACE_CURRENT_FIELD:bit1;
  CRTC_INTERLACE_NEXT_FIELD   :bit1;
  RESERVED0                   :bit30;
 end;

 TCRTC_SNAPSHOT_CONTROL=bitpacked record
  CRTC_AUTO_SNAPSHOT_TRIG_SEL:bit2;
  RESERVED0                  :bit30;
 end;

 TCRTC_TEST_DEBUG_INDEX=bitpacked record
  CRTC_TEST_DEBUG_INDEX   :bit8;
  CRTC_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0               :bit23;
 end;

 TDAC_AUTODETECT_STATUS=bitpacked record
  DAC_AUTODETECT_STATUS     :bit1;
  RESERVED0                 :bit3;
  DAC_AUTODETECT_CONNECT    :bit1;
  RESERVED1                 :bit3;
  DAC_AUTODETECT_RED_SENSE  :bit2;
  RESERVED2                 :bit6;
  DAC_AUTODETECT_GREEN_SENSE:bit2;
  RESERVED3                 :bit6;
  DAC_AUTODETECT_BLUE_SENSE :bit2;
  RESERVED4                 :bit6;
 end;

 TDAC_COMPARATOR_ENABLE=bitpacked record
  DAC_COMP_DDET_REF_EN:bit1;
  RESERVED0           :bit7;
  DAC_COMP_SDET_REF_EN:bit1;
  RESERVED1           :bit7;
  DAC_R_ASYNC_ENABLE  :bit1;
  DAC_G_ASYNC_ENABLE  :bit1;
  DAC_B_ASYNC_ENABLE  :bit1;
  RESERVED2           :bit13;
 end;

 TDAC_COMPARATOR_OUTPUT=bitpacked record
  DAC_COMPARATOR_OUTPUT      :bit1;
  DAC_COMPARATOR_OUTPUT_BLUE :bit1;
  DAC_COMPARATOR_OUTPUT_GREEN:bit1;
  DAC_COMPARATOR_OUTPUT_RED  :bit1;
  RESERVED0                  :bit28;
 end;

 TDAC_FORCE_OUTPUT_CNTL=bitpacked record
  DAC_FORCE_DATA_EN            :bit1;
  RESERVED0                    :bit7;
  DAC_FORCE_DATA_SEL           :bit3;
  RESERVED1                    :bit13;
  DAC_FORCE_DATA_ON_BLANKB_ONLY:bit1;
  RESERVED2                    :bit7;
 end;

 TDAC_STEREOSYNC_SELECT=bitpacked record
  DAC_STEREOSYNC_SELECT:bit3;
  RESERVED0            :bit29;
 end;

 TDB_STENCIL_WRITE_BASE=bit32;

 TDCCG_AUDIO_DTO0_PHASE=bit32;

 TDCCG_AUDIO_DTO1_PHASE=bit32;

 TDCCG_AUDIO_DTO_SOURCE=bitpacked record
  DCCG_AUDIO_DTO0_SOURCE_SEL    :bit3;
  RESERVED0                     :bit1;
  DCCG_AUDIO_DTO_SEL            :bit2;
  RESERVED1                     :bit6;
  DCCG_AUDIO_DTO2_SOURCE_SEL    :bit2;
  RESERVED2                     :bit2;
  DCCG_AUDIO_DTO2_CLOCK_EN      :bit1;
  RESERVED3                     :bit3;
  DCCG_AUDIO_DTO2_USE_512FBR_DTO:bit1;
  RESERVED4                     :bit3;
  DCCG_AUDIO_DTO0_USE_512FBR_DTO:bit1;
  RESERVED5                     :bit3;
  DCCG_AUDIO_DTO1_USE_512FBR_DTO:bit1;
  RESERVED6                     :bit3;
 end;

 TDCCG_CBUS_WRCMD_DELAY=bitpacked record
  CBUS_PLL_WRCMD_DELAY:bit4;
  RESERVED0           :bit28;
 end;

 TDCCG_TEST_DEBUG_INDEX=bitpacked record
  DCCG_TEST_DEBUG_INDEX   :bit8;
  DCCG_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0               :bit23;
 end;

 TDCIO_TEST_DEBUG_INDEX=bitpacked record
  DCIO_TEST_DEBUG_INDEX   :bit8;
  DCIO_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0               :bit23;
 end;

 TDCPG_TEST_DEBUG_INDEX=bitpacked record
  DCPG_TEST_DEBUG_INDEX   :bit8;
  DCPG_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0               :bit23;
 end;

 TDC_ABM1_ACE_CNTL_MISC=bitpacked record
  ABM1_ACE_REG_WR_MISSED_FRAME      :bit1;
  RESERVED0                         :bit7;
  ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR:bit1;
  RESERVED1                         :bit23;
 end;

 TDC_I2C_DDC1_HW_STATUS=bitpacked record
  DC_I2C_DDC1_HW_STATUS                  :bit2;
  RESERVED0                              :bit1;
  DC_I2C_DDC1_HW_DONE                    :bit1;
  RESERVED1                              :bit12;
  DC_I2C_DDC1_HW_REQ                     :bit1;
  DC_I2C_DDC1_HW_URG                     :bit1;
  RESERVED2                              :bit2;
  DC_I2C_DDC1_EDID_DETECT_STATUS         :bit1;
  RESERVED3                              :bit3;
  DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES:bit4;
  DC_I2C_DDC1_EDID_DETECT_STATE          :bit3;
  RESERVED4                              :bit1;
 end;

 TDC_I2C_DDC2_HW_STATUS=bitpacked record
  DC_I2C_DDC2_HW_STATUS                  :bit2;
  RESERVED0                              :bit1;
  DC_I2C_DDC2_HW_DONE                    :bit1;
  RESERVED1                              :bit12;
  DC_I2C_DDC2_HW_REQ                     :bit1;
  DC_I2C_DDC2_HW_URG                     :bit1;
  RESERVED2                              :bit2;
  DC_I2C_DDC2_EDID_DETECT_STATUS         :bit1;
  RESERVED3                              :bit3;
  DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES:bit4;
  DC_I2C_DDC2_EDID_DETECT_STATE          :bit3;
  RESERVED4                              :bit1;
 end;

 TDC_I2C_DDC3_HW_STATUS=bitpacked record
  DC_I2C_DDC3_HW_STATUS                  :bit2;
  RESERVED0                              :bit1;
  DC_I2C_DDC3_HW_DONE                    :bit1;
  RESERVED1                              :bit12;
  DC_I2C_DDC3_HW_REQ                     :bit1;
  DC_I2C_DDC3_HW_URG                     :bit1;
  RESERVED2                              :bit2;
  DC_I2C_DDC3_EDID_DETECT_STATUS         :bit1;
  RESERVED3                              :bit3;
  DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES:bit4;
  DC_I2C_DDC3_EDID_DETECT_STATE          :bit3;
  RESERVED4                              :bit1;
 end;

 TDC_I2C_DDC4_HW_STATUS=bitpacked record
  DC_I2C_DDC4_HW_STATUS                  :bit2;
  RESERVED0                              :bit1;
  DC_I2C_DDC4_HW_DONE                    :bit1;
  RESERVED1                              :bit12;
  DC_I2C_DDC4_HW_REQ                     :bit1;
  DC_I2C_DDC4_HW_URG                     :bit1;
  RESERVED2                              :bit2;
  DC_I2C_DDC4_EDID_DETECT_STATUS         :bit1;
  RESERVED3                              :bit3;
  DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES:bit4;
  DC_I2C_DDC4_EDID_DETECT_STATE          :bit3;
  RESERVED4                              :bit1;
 end;

 TDC_I2C_DDC5_HW_STATUS=bitpacked record
  DC_I2C_DDC5_HW_STATUS                  :bit2;
  RESERVED0                              :bit1;
  DC_I2C_DDC5_HW_DONE                    :bit1;
  RESERVED1                              :bit12;
  DC_I2C_DDC5_HW_REQ                     :bit1;
  DC_I2C_DDC5_HW_URG                     :bit1;
  RESERVED2                              :bit2;
  DC_I2C_DDC5_EDID_DETECT_STATUS         :bit1;
  RESERVED3                              :bit3;
  DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES:bit4;
  DC_I2C_DDC5_EDID_DETECT_STATE          :bit3;
  RESERVED4                              :bit1;
 end;

 TDC_I2C_DDC6_HW_STATUS=bitpacked record
  DC_I2C_DDC6_HW_STATUS                  :bit2;
  RESERVED0                              :bit1;
  DC_I2C_DDC6_HW_DONE                    :bit1;
  RESERVED1                              :bit12;
  DC_I2C_DDC6_HW_REQ                     :bit1;
  DC_I2C_DDC6_HW_URG                     :bit1;
  RESERVED2                              :bit2;
  DC_I2C_DDC6_EDID_DETECT_STATUS         :bit1;
  RESERVED3                              :bit3;
  DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES:bit4;
  DC_I2C_DDC6_EDID_DETECT_STATE          :bit3;
  RESERVED4                              :bit1;
 end;

 TDIG_OUTPUT_CRC_RESULT=bitpacked record
  DIG_OUTPUT_CRC_RESULT:bit30;
  RESERVED0            :bit2;
 end;

 TDISP_INTERRUPT_STATUS=bitpacked record
  SCL_DISP1_MODE_CHANGE_INTERRUPT         :bit1;
  D1BLND_DATA_UNDERFLOW_INTERRUPT         :bit1;
  LB_D1_VLINE_INTERRUPT                   :bit1;
  LB_D1_VBLANK_INTERRUPT                  :bit1;
  CRTC1_SNAPSHOT_INTERRUPT                :bit1;
  CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT   :bit1;
  CRTC1_FORCE_COUNT_NOW_INTERRUPT         :bit1;
  CRTC1_TRIGA_INTERRUPT                   :bit1;
  CRTC1_TRIGB_INTERRUPT                   :bit1;
  CRTC1_VSYNC_NOM_INTERRUPT               :bit1;
  CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1;
  RESERVED0                               :bit1;
  RESERVED1                               :bit1;
  RESERVED2                               :bit1;
  RESERVED3                               :bit1;
  DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1;
  DIGA_DP_VID_STREAM_DISABLE_INTERRUPT    :bit1;
  DC_HPD1_INTERRUPT                       :bit1;
  DC_HPD1_RX_INTERRUPT                    :bit1;
  AUX1_SW_DONE_INTERRUPT                  :bit1;
  AUX1_LS_DONE_INTERRUPT                  :bit1;
  DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT   :bit1;
  DACA_AUTODETECT_INTERRUPT               :bit1;
  DACB_AUTODETECT_INTERRUPT               :bit1;
  DC_I2C_SW_DONE_INTERRUPT                :bit1;
  DC_I2C_HW_DONE_INTERRUPT                :bit1;
  DMCU_UC_INTERNAL_INT                    :bit1;
  DMCU_SCP_INT                            :bit1;
  ABM1_HG_READY_INT                       :bit1;
  ABM1_LS_READY_INT                       :bit1;
  ABM1_BL_UPDATE_INT                      :bit1;
  DISP_INTERRUPT_STATUS_CONTINUE          :bit1;
 end;

 TDMCU_INTERRUPT_STATUS=bitpacked record
  ABM1_HG_READY_INT_OCCURRED            :bit1;
  ABM1_LS_READY_INT_OCCURRED            :bit1;
  ABM1_BL_UPDATE_INT_OCCURRED           :bit1;
  MCP_INT_OCCURRED                      :bit1;
  DCPG_IHC_DSI_POWER_UP_INT_OCCURRED    :bit1;
  DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED  :bit1;
  RESERVED0                             :bit2;
  EXTERNAL_SW_INT_OCCURRED              :bit1;
  SCP_INT_OCCURRED                      :bit1;
  UC_INTERNAL_INT_OCCURRED              :bit1;
  UC_REG_RD_TIMEOUT_INT_OCCURRED        :bit1;
  DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED  :bit1;
  DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED  :bit1;
  DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED  :bit1;
  DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED  :bit1;
  DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED  :bit1;
  DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED  :bit1;
  DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED:bit1;
  DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED:bit1;
  DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED:bit1;
  DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED:bit1;
  DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED:bit1;
  DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED:bit1;
  VBLANK1_INT_OCCURRED                  :bit1;
  VBLANK2_INT_OCCURRED                  :bit1;
  VBLANK3_INT_OCCURRED                  :bit1;
  VBLANK4_INT_OCCURRED                  :bit1;
  VBLANK5_INT_OCCURRED                  :bit1;
  VBLANK6_INT_OCCURRED                  :bit1;
  RESERVED1                             :bit2;
 end;

 TDMCU_TEST_DEBUG_INDEX=bitpacked record
  DMCU_TEST_DEBUG_INDEX   :bit8;
  DMCU_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0               :bit23;
 end;

 TDMIF_TEST_DEBUG_INDEX=bitpacked record
  DMIF_TEST_DEBUG_INDEX   :bit8;
  DMIF_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0               :bit23;
 end;

 TDOUT_TEST_DEBUG_INDEX=bitpacked record
  DOUT_TEST_DEBUG_INDEX   :bit8;
  DOUT_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0               :bit23;
 end;

 TDP_DPHY_FAST_TRAINING=bitpacked record
  DPHY_RX_FAST_TRAINING_CAPABLE           :bit1;
  DPHY_SW_FAST_TRAINING_START             :bit1;
  DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN:bit1;
  RESERVED0                               :bit5;
  DPHY_FAST_TRAINING_TP1_TIME             :bit12;
  DPHY_FAST_TRAINING_TP2_TIME             :bit12;
 end;

 TDP_FE_TEST_DEBUG_DATA=bit32;

 TDP_SEC_AUD_M_READBACK=bitpacked record
  DP_SEC_AUD_M_READBACK:bit24;
  RESERVED0            :bit8;
 end;

 TDP_SEC_AUD_N_READBACK=bitpacked record
  DP_SEC_AUD_N_READBACK:bit24;
  RESERVED0            :bit8;
 end;

 TDP_VID_INTERRUPT_CNTL=bitpacked record
  DP_VID_STREAM_DISABLE_INT :bit1;
  DP_VID_STREAM_DISABLE_ACK :bit1;
  DP_VID_STREAM_DISABLE_MASK:bit1;
  RESERVED0                 :bit29;
 end;

 TDVO_FIFO_ERROR_STATUS=bitpacked record
  DVO_FIFO_LEVEL_ERROR        :bit1;
  DVO_FIFO_USE_OVERWRITE_LEVEL:bit1;
  DVO_FIFO_OVERWRITE_LEVEL    :bit6;
  DVO_FIFO_ERROR_ACK          :bit1;
  RESERVED0                   :bit1;
  DVO_FIFO_CAL_AVERAGE_LEVEL  :bit6;
  DVO_FIFO_MAXIMUM_LEVEL      :bit4;
  RESERVED1                   :bit2;
  DVO_FIFO_MINIMUM_LEVEL      :bit4;
  RESERVED2                   :bit3;
  DVO_FIFO_CALIBRATED         :bit1;
  DVO_FIFO_FORCE_RECAL_AVERAGE:bit1;
  DVO_FIFO_FORCE_RECOMP_MINMAX:bit1;
 end;

 TENTITY_TEMPERATURES_1=bit32;

 TFMT_BIT_DEPTH_CONTROL=bitpacked record
  FMT_TRUNCATE_EN           :bit1;
  FMT_TRUNCATE_MODE         :bit1;
  RESERVED0                 :bit2;
  FMT_TRUNCATE_DEPTH        :bit2;
  RESERVED1                 :bit2;
  FMT_SPATIAL_DITHER_EN     :bit1;
  FMT_SPATIAL_DITHER_MODE   :bit2;
  FMT_SPATIAL_DITHER_DEPTH  :bit2;
  FMT_FRAME_RANDOM_ENABLE   :bit1;
  FMT_RGB_RANDOM_ENABLE     :bit1;
  FMT_HIGHPASS_RANDOM_ENABLE:bit1;
  FMT_TEMPORAL_DITHER_EN    :bit1;
  FMT_TEMPORAL_DITHER_DEPTH :bit2;
  RESERVED2                 :bit2;
  FMT_TEMPORAL_DITHER_OFFSET:bit2;
  RESERVED3                 :bit1;
  FMT_TEMPORAL_LEVEL        :bit1;
  FMT_TEMPORAL_DITHER_RESET :bit1;
  FMT_25FRC_SEL             :bit2;
  FMT_50FRC_SEL             :bit2;
  FMT_75FRC_SEL             :bit2;
 end;

 TFMT_CLAMP_COMPONENT_B=bitpacked record
  FMT_CLAMP_LOWER_B:bit16;
  FMT_CLAMP_UPPER_B:bit16;
 end;

 TFMT_CLAMP_COMPONENT_G=bitpacked record
  FMT_CLAMP_LOWER_G:bit16;
  FMT_CLAMP_UPPER_G:bit16;
 end;

 TFMT_CLAMP_COMPONENT_R=bitpacked record
  FMT_CLAMP_LOWER_R:bit16;
  FMT_CLAMP_UPPER_R:bit16;
 end;

 TFMT_CRC_SIG_RED_GREEN=bitpacked record
  FMT_CRC_SIG_RED  :bit16;
  FMT_CRC_SIG_GREEN:bit16;
 end;

 TFMT_FORCE_OUTPUT_CNTL=bitpacked record
  FMT_FORCE_DATA_EN            :bit1;
  RESERVED0                    :bit7;
  FMT_FORCE_DATA_SEL_COLOR     :bit3;
  RESERVED1                    :bit1;
  FMT_FORCE_DATA_SEL_SLOT      :bit4;
  FMT_FORCE_DATA_ON_BLANKB_ONLY:bit1;
  RESERVED2                    :bit15;
 end;

 TGC_CAC_LKG_AGGR_LOWER=bit32;

 TGC_CAC_LKG_AGGR_UPPER=bit32;

 TGC_USER_RB_REDUNDANCY=bitpacked record
  RESERVED0     :bit8;
  FAILED_RB0    :bit4;
  EN_REDUNDANCY0:bit1;
  RESERVED1     :bit3;
  FAILED_RB1    :bit4;
  EN_REDUNDANCY1:bit1;
  RESERVED2     :bit11;
 end;

 TGDS_GWS_RESOURCE_CNTL=bitpacked record
  INDEX :bit6;
  UNUSED:bit26;
 end;

 TGENERIC_I2C_PIN_DEBUG=bitpacked record
  GENERIC_I2C_SCL_OUTPUT:bit1;
  GENERIC_I2C_SCL_INPUT :bit1;
  GENERIC_I2C_SCL_EN    :bit1;
  RESERVED0             :bit1;
  GENERIC_I2C_SDA_OUTPUT:bit1;
  GENERIC_I2C_SDA_INPUT :bit1;
  GENERIC_I2C_SDA_EN    :bit1;
  RESERVED1             :bit25;
 end;

 TGPU_GARLIC_FLUSH_DONE=bitpacked record
  CP0      :bit1;
  CP1      :bit1;
  CP2      :bit1;
  CP3      :bit1;
  CP4      :bit1;
  CP5      :bit1;
  CP6      :bit1;
  CP7      :bit1;
  CP8      :bit1;
  CP9      :bit1;
  SDMA0    :bit1;
  SDMA1    :bit1;
  SDMA2    :bit1;
  SDMA3    :bit1;
  RESERVED0:bit18;
 end;

 TGRBM_WAIT_IDLE_CLOCKS=bitpacked record
  WAIT_IDLE_CLOCKS:bit8;
  RESERVED0       :bit24;
 end;

 TGRPH_INTERRUPT_STATUS=bitpacked record
  GRPH_PFLIP_INT_OCCURRED:bit1;
  RESERVED0              :bit7;
  GRPH_PFLIP_INT_CLEAR   :bit1;
  RESERVED1              :bit23;
 end;

 TGRPH_LUT_10BIT_BYPASS=bitpacked record
  RESERVED0                       :bit8;
  GRPH_LUT_10BIT_BYPASS_EN        :bit1;
  RESERVED1                       :bit7;
  GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN:bit1;
  RESERVED2                       :bit15;
 end;

 TGRPH_SURFACE_OFFSET_X=bitpacked record
  GRPH_SURFACE_OFFSET_X:bit14;
  RESERVED0            :bit18;
 end;

 TGRPH_SURFACE_OFFSET_Y=bitpacked record
  GRPH_SURFACE_OFFSET_Y:bit14;
  RESERVED0            :bit18;
 end;

 THDP_NONSURF_FLAGS_CLR=bitpacked record
  NONSURF_WRITE_FLAG_CLR:bit1;
  NONSURF_READ_FLAG_CLR :bit1;
  RESERVED0             :bit30;
 end;

 THDP_XDP_CGTT_BLK_CTRL=bitpacked record
  CGTT_BLK_CTRL_0_ON_DELAY          :bit4;
  CGTT_BLK_CTRL_1_OFF_DELAY         :bit8;
  CGTT_BLK_CTRL_2_RSVD              :bit18;
  CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE:bit1;
  CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE :bit1;
 end;

 THDP_XDP_P2P_MBX_ADDR0=bitpacked record
  VALID     :bit1;
  ADDR      :bit20;
  ADDR_39_36:bit4;
  RESERVED0 :bit7;
 end;

 THDP_XDP_P2P_MBX_ADDR1=bitpacked record
  VALID     :bit1;
  ADDR      :bit20;
  ADDR_39_36:bit4;
  RESERVED0 :bit7;
 end;

 THDP_XDP_P2P_MBX_ADDR2=bitpacked record
  VALID     :bit1;
  ADDR      :bit20;
  ADDR_39_36:bit4;
  RESERVED0 :bit7;
 end;

 THDP_XDP_P2P_MBX_ADDR3=bitpacked record
  VALID     :bit1;
  ADDR      :bit20;
  ADDR_39_36:bit4;
  RESERVED0 :bit7;
 end;

 THDP_XDP_P2P_MBX_ADDR4=bitpacked record
  VALID     :bit1;
  ADDR      :bit20;
  ADDR_39_36:bit4;
  RESERVED0 :bit7;
 end;

 THDP_XDP_P2P_MBX_ADDR5=bitpacked record
  VALID     :bit1;
  ADDR      :bit20;
  ADDR_39_36:bit4;
  RESERVED0 :bit7;
 end;

 THDP_XDP_P2P_MBX_ADDR6=bitpacked record
  VALID     :bit1;
  ADDR      :bit20;
  ADDR_39_36:bit4;
  RESERVED0 :bit7;
 end;

 TIDDCCIF02_DBG_DCCIF_C=bit32;

 TIDDCCIF04_DBG_DCCIF_E=bit32;

 TIDDCCIF05_DBG_DCCIF_F=bit32;

 TLB_MEMORY_SIZE_STATUS=bitpacked record
  LB_MEMORY_SIZE_STATUS:bit12;
  RESERVED0            :bit20;
 end;

 TLB_SNAPSHOT_V_COUNTER=bitpacked record
  SNAPSHOT_V_COUNTER:bit15;
  RESERVED0         :bit17;
 end;

 TLCLK_DEEP_SLEEP_CNTL2=bitpacked record
  RFE_BUSY_MASK          :bit1;
  BIF_CG_LCLK_BUSY_MASK  :bit1;
  L1IMU_SMU_IDLE_MASK    :bit1;
  RESERVED0              :bit1;
  SCLK_RUNNING_MASK      :bit1;
  SMU_BUSY_MASK          :bit1;
  PCIE_LCLK_IDLE1_MASK   :bit1;
  PCIE_LCLK_IDLE2_MASK   :bit1;
  PCIE_LCLK_IDLE3_MASK   :bit1;
  PCIE_LCLK_IDLE4_MASK   :bit1;
  L1IMUGPP_IDLE_MASK     :bit1;
  L1IMUGPPSB_IDLE_MASK   :bit1;
  L1IMUBIF_IDLE_MASK     :bit1;
  L1IMUINTGEN_IDLE_MASK  :bit1;
  L2IMU_IDLE_MASK        :bit1;
  ORB_IDLE_MASK          :bit1;
  ON_INB_WAKE_MASK       :bit1;
  ON_INB_WAKE_ACK_MASK   :bit1;
  ON_OUTB_WAKE_MASK      :bit1;
  ON_OUTB_WAKE_ACK_MASK  :bit1;
  DMAACTIVE_MASK         :bit1;
  RLC_SMU_GFXCLK_OFF_MASK:bit1;
  RESERVED               :bit10;
 end;

 TMASTER_COMM_DATA_REG1=bitpacked record
  MASTER_COMM_DATA_REG1_BYTE0:bit8;
  MASTER_COMM_DATA_REG1_BYTE1:bit8;
  MASTER_COMM_DATA_REG1_BYTE2:bit8;
  MASTER_COMM_DATA_REG1_BYTE3:bit8;
 end;

 TMASTER_COMM_DATA_REG2=bitpacked record
  MASTER_COMM_DATA_REG2_BYTE0:bit8;
  MASTER_COMM_DATA_REG2_BYTE1:bit8;
  MASTER_COMM_DATA_REG2_BYTE2:bit8;
  MASTER_COMM_DATA_REG2_BYTE3:bit8;
 end;

 TMASTER_COMM_DATA_REG3=bitpacked record
  MASTER_COMM_DATA_REG3_BYTE0:bit8;
  MASTER_COMM_DATA_REG3_BYTE1:bit8;
  MASTER_COMM_DATA_REG3_BYTE2:bit8;
  MASTER_COMM_DATA_REG3_BYTE3:bit8;
 end;

 TMCIF_TEST_DEBUG_INDEX=bitpacked record
  MCIF_TEST_DEBUG_INDEX   :bit8;
  MCIF_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0               :bit23;
 end;

 TMCIF_WB_BUFMGR_STATUS=bitpacked record
  MCIF_WB_BUFMGR_VCE_INT_STATUS:bit1;
  MCIF_WB_BUFMGR_SW_INT_STATUS :bit1;
  RESERVED0                    :bit2;
  MCIF_WB_BUFMGR_CUR_BUF       :bit3;
  MCIF_WB_BUF_DUALSIZE_STATUS  :bit1;
  MCIF_WB_BUFMGR_BUFTAG        :bit4;
  MCIF_WB_BUFMGR_CUR_LINE_L    :bit13;
  RESERVED1                    :bit3;
  MCIF_WB_BUFMGR_NEXT_BUF      :bit3;
  RESERVED2                    :bit1;
 end;

 TMCIF_WB_BUF_1_STATUS2=bitpacked record
  MCIF_WB_BUF_1_CUR_LINE_R :bit13;
  MCIF_WB_BUF_1_NEW_CONTENT:bit1;
  MCIF_WB_BUF_1_COLOR_DEPTH:bit1;
  RESERVED0                :bit17;
 end;

 TMCIF_WB_BUF_2_STATUS2=bitpacked record
  MCIF_WB_BUF_2_CUR_LINE_R :bit13;
  MCIF_WB_BUF_2_NEW_CONTENT:bit1;
  MCIF_WB_BUF_2_COLOR_DEPTH:bit1;
  RESERVED0                :bit17;
 end;

 TMCIF_WB_BUF_3_STATUS2=bitpacked record
  MCIF_WB_BUF_3_CUR_LINE_R :bit13;
  MCIF_WB_BUF_3_NEW_CONTENT:bit1;
  MCIF_WB_BUF_3_COLOR_DEPTH:bit1;
  RESERVED0                :bit17;
 end;

 TMCIF_WB_BUF_4_STATUS2=bitpacked record
  MCIF_WB_BUF_4_CUR_LINE_R :bit13;
  MCIF_WB_BUF_4_NEW_CONTENT:bit1;
  MCIF_WB_BUF_4_COLOR_DEPTH:bit1;
  RESERVED0                :bit17;
 end;

 TMC_ARB_DRAM_TIMING2_1=bitpacked record
  RAS2RAS  :bit8;
  RP       :bit8;
  WRPLUSRP :bit8;
  BUS_TURN :bit5;
  RESERVED0:bit3;
 end;

 TMC_ARB_PERFCOUNTER_HI=bitpacked record
  COUNTER_HI   :bit16;
  COMPARE_VALUE:bit16;
 end;

 TMC_ARB_PERFCOUNTER_LO=bit32;

 TMC_ARB_PERF_MON_CNTL0=bitpacked record
  RESERVED0:bit12;
  RESERVED1:bit12;
  RESERVED2:bit2;
  RESERVED3:bit2;
  RESERVED4:bit1;
  RESERVED5:bit3;
 end;

 TMC_ARB_RET_CREDITS_RD=bitpacked record
  LCL          :bit8;
  HUB          :bit8;
  DISP         :bit8;
  RETURN_CREDIT:bit8;
 end;

 TMC_ARB_RET_CREDITS_WR=bitpacked record
  LCL           :bit8;
  HUB           :bit8;
  RETURN_CREDIT :bit8;
  WRRET_SEQ_SKID:bit4;
  WRRET_BP      :bit1;
  RESERVED0     :bit3;
 end;

 TMC_BIST_MISMATCH_ADDR=bitpacked record
  COL      :bit8;
  ROW      :bit16;
  BANK     :bit4;
  RESERVED0:bit4;
 end;

 TMC_FUS_DRAM0_CS0_BASE=bitpacked record
  CSENABLE     :bit1;
  RESERVED0    :bit4;
  BASEADDR21_11:bit11;
  RESERVED1    :bit3;
  BASEADDR38_27:bit12;
  RESERVED2    :bit1;
 end;

 TMC_FUS_DRAM0_CS1_BASE=bitpacked record
  CSENABLE     :bit1;
  RESERVED0    :bit4;
  BASEADDR21_11:bit11;
  RESERVED1    :bit3;
  BASEADDR38_27:bit12;
  RESERVED2    :bit1;
 end;

 TMC_FUS_DRAM0_CS2_BASE=bitpacked record
  CSENABLE     :bit1;
  RESERVED0    :bit4;
  BASEADDR21_11:bit11;
  RESERVED1    :bit3;
  BASEADDR38_27:bit12;
  RESERVED2    :bit1;
 end;

 TMC_FUS_DRAM0_CS3_BASE=bitpacked record
  CSENABLE     :bit1;
  RESERVED0    :bit4;
  BASEADDR21_11:bit11;
  RESERVED1    :bit3;
  BASEADDR38_27:bit12;
  RESERVED2    :bit1;
 end;

 TMC_FUS_DRAM0_CTL_BASE=bitpacked record
  DCTSEL     :bit3;
  DCTINTLVEN :bit4;
  DCTBASEADDR:bit21;
  DCTOFFSETEN:bit1;
  RESERVED0  :bit1;
  RESERVED1  :bit2;
 end;

 TMC_FUS_DRAM1_CS0_BASE=bitpacked record
  CSENABLE     :bit1;
  RESERVED0    :bit4;
  BASEADDR21_11:bit11;
  RESERVED1    :bit3;
  BASEADDR38_27:bit12;
  RESERVED2    :bit1;
 end;

 TMC_FUS_DRAM1_CS1_BASE=bitpacked record
  CSENABLE     :bit1;
  RESERVED0    :bit4;
  BASEADDR21_11:bit11;
  RESERVED1    :bit3;
  BASEADDR38_27:bit12;
  RESERVED2    :bit1;
 end;

 TMC_FUS_DRAM1_CS2_BASE=bitpacked record
  CSENABLE     :bit1;
  RESERVED0    :bit4;
  BASEADDR21_11:bit11;
  RESERVED1    :bit3;
  BASEADDR38_27:bit12;
  RESERVED2    :bit1;
 end;

 TMC_FUS_DRAM1_CS3_BASE=bitpacked record
  CSENABLE     :bit1;
  RESERVED0    :bit4;
  BASEADDR21_11:bit11;
  RESERVED1    :bit3;
  BASEADDR38_27:bit12;
  RESERVED2    :bit1;
 end;

 TMC_FUS_DRAM1_CTL_BASE=bitpacked record
  DCTSEL     :bit3;
  DCTINTLVEN :bit4;
  DCTBASEADDR:bit21;
  DCTOFFSETEN:bit1;
  RESERVED0  :bit1;
  RESERVED1  :bit2;
 end;

 TMC_FUS_DRAM_APER_BASE=bitpacked record
  BASE     :bit20;
  RESERVED0:bit12;
 end;

 TMC_GRUB_PROBE_CREDITS=bitpacked record
  CREDITS_LIMIT_LO     :bit6;
  RESERVED0            :bit2;
  CREDITS_LIMIT_HI     :bit6;
  RESERVED1            :bit1;
  INTPRB_FIFO_LEVEL    :bit1;
  INTPRB_TIMEOUT_THRESH:bit3;
  RESERVED2            :bit1;
  MEM_TIMEOUT_THRESH   :bit3;
  RESERVED3            :bit9;
 end;

 TMC_HUB_PERFCOUNTER_HI=bitpacked record
  COUNTER_HI   :bit16;
  COMPARE_VALUE:bit16;
 end;

 TMC_HUB_PERFCOUNTER_LO=bit32;

 TMC_HUB_RDREQ_CREDITS2=bitpacked record
  STOR0_PRI:bit8;
  STOR1_PRI:bit8;
  RESERVED0:bit16;
 end;

 TMC_HUB_RDREQ_ISP_CCPU=bitpacked record
  ENABLE               :bit1;
  PRESCALE             :bit2;
  BLACKOUT_EXEMPT      :bit1;
  STALL_MODE           :bit2;
  STALL_OVERRIDE       :bit1;
  MAXBURST             :bit4;
  LAZY_TIMER           :bit4;
  STALL_OVERRIDE_WTM   :bit1;
  BYPASS_AVAIL_OVERRIDE:bit1;
  PRIORITY_DISABLE     :bit1;
  STALL_FILTER_ENABLE  :bit1;
  STALL_THRESHOLD      :bit6;
  RESERVED0            :bit7;
 end;

 TMC_HUB_RDREQ_WTM_CNTL=bitpacked record
  GROUP0_DECREMENT:bit3;
  GROUP1_DECREMENT:bit3;
  GROUP2_DECREMENT:bit3;
  GROUP3_DECREMENT:bit3;
  GROUP4_DECREMENT:bit3;
  GROUP5_DECREMENT:bit3;
  GROUP6_DECREMENT:bit3;
  GROUP7_DECREMENT:bit3;
  RESERVED0       :bit8;
 end;

 TMC_RPB_PERFCOUNTER_HI=bitpacked record
  COUNTER_HI   :bit16;
  COMPARE_VALUE:bit16;
 end;

 TMC_RPB_PERFCOUNTER_LO=bit32;

 TMC_RPB_RD_SWITCH_CNTL=bitpacked record
  QUEUE0_SWITCH_NUM:bit8;
  QUEUE1_SWITCH_NUM:bit8;
  QUEUE2_SWITCH_NUM:bit8;
  QUEUE3_SWITCH_NUM:bit8;
 end;

 TMC_RPB_WR_SWITCH_CNTL=bitpacked record
  QUEUE0_SWITCH_NUM:bit8;
  QUEUE1_SWITCH_NUM:bit8;
  QUEUE2_SWITCH_NUM:bit8;
  QUEUE3_SWITCH_NUM:bit8;
 end;

 TMC_SEQ_IO_DEBUG_INDEX=bitpacked record
  IO_DEBUG_INDEX:bit9;
  RESERVED0     :bit23;
 end;

 TMC_SEQ_MISC_TIMING_LP=bitpacked record
  TRP_WRA  :bit6;
  TRP_RDA  :bit6;
  TRP      :bit5;
  TRFC     :bit7;
  RESERVED0:bit4;
  RESERVED1:bit4;
 end;

 TMC_VM_MARC_RELOC_HI_0=bitpacked record
  MARC_RELOC_HI_0:bit20;
  RESERVED0      :bit12;
 end;

 TMC_VM_MARC_RELOC_HI_1=bitpacked record
  MARC_RELOC_HI_1:bit20;
  RESERVED0      :bit12;
 end;

 TMC_VM_MARC_RELOC_HI_2=bitpacked record
  MARC_RELOC_HI_2:bit20;
  RESERVED0      :bit12;
 end;

 TMC_VM_MARC_RELOC_HI_3=bitpacked record
  MARC_RELOC_HI_3:bit20;
  RESERVED0      :bit12;
 end;

 TMC_VM_MARC_RELOC_LO_0=bitpacked record
  MARC_ENABLE_0  :bit1;
  MARC_READONLY_0:bit1;
  RESERVED0      :bit10;
  MARC_RELOC_LO_0:bit20;
 end;

 TMC_VM_MARC_RELOC_LO_1=bitpacked record
  MARC_ENABLE_1  :bit1;
  MARC_READONLY_1:bit1;
  RESERVED0      :bit10;
  MARC_RELOC_LO_1:bit20;
 end;

 TMC_VM_MARC_RELOC_LO_2=bitpacked record
  MARC_ENABLE_2  :bit1;
  MARC_READONLY_2:bit1;
  RESERVED0      :bit10;
  MARC_RELOC_LO_2:bit20;
 end;

 TMC_VM_MARC_RELOC_LO_3=bitpacked record
  MARC_ENABLE_3  :bit1;
  MARC_READONLY_3:bit1;
  RESERVED0      :bit10;
  MARC_RELOC_LO_3:bit20;
 end;

 TMC_VM_NB_TOP_OF_DRAM3=bitpacked record
  TOM3_LIMIT :bit30;
  RESERVED0  :bit1;
  TOM3_ENABLE:bit1;
 end;

 TMC_XBAR_ARB_MAX_BURST=bitpacked record
  RD_PORT0:bit4;
  RD_PORT1:bit4;
  RD_PORT2:bit4;
  RD_PORT3:bit4;
  WR_PORT0:bit4;
  WR_PORT1:bit4;
  WR_PORT2:bit4;
  WR_PORT3:bit4;
 end;

 TMC_XBAR_RDRET_CREDIT1=bitpacked record
  OUT0:bit8;
  OUT1:bit8;
  OUT2:bit8;
  OUT3:bit8;
 end;

 TMC_XBAR_RDRET_CREDIT2=bitpacked record
  OUT4             :bit8;
  OUT5             :bit8;
  HUB_LP_RDRET_SKID:bit8;
  RESERVED0        :bit8;
 end;

 TMC_XBAR_WRRET_CREDIT1=bitpacked record
  OUT0:bit8;
  OUT1:bit8;
  OUT2:bit8;
  OUT3:bit8;
 end;

 TMC_XBAR_WRRET_CREDIT2=bitpacked record
  OUT4     :bit8;
  OUT5     :bit8;
  RESERVED0:bit16;
 end;

 TMC_XPB_RTR_SRC_APRTR0=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_RTR_SRC_APRTR1=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_RTR_SRC_APRTR2=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_RTR_SRC_APRTR3=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_RTR_SRC_APRTR4=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_RTR_SRC_APRTR5=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_RTR_SRC_APRTR6=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_RTR_SRC_APRTR7=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_RTR_SRC_APRTR8=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_RTR_SRC_APRTR9=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_UNC_THRESH_HST=bitpacked record
  CHANGE_PREF:bit6;
  STRONG_PREF:bit6;
  USE_UNFULL :bit6;
  RESERVED0  :bit14;
 end;

 TMC_XPB_UNC_THRESH_SID=bitpacked record
  CHANGE_PREF:bit6;
  STRONG_PREF:bit6;
  USE_UNFULL :bit6;
  RESERVED0  :bit14;
 end;

 TMVP_RECEIVE_CNT_CNTL1=bitpacked record
  MVP_SLAVE_PIXEL_ERROR_CNT:bit13;
  RESERVED0                :bit3;
  MVP_SLAVE_LINE_ERROR_CNT :bit13;
  RESERVED1                :bit2;
  MVP_SLAVE_DATA_CHK_EN    :bit1;
 end;

 TMVP_RECEIVE_CNT_CNTL2=bitpacked record
  MVP_SLAVE_FRAME_ERROR_CNT      :bit13;
  RESERVED0                      :bit18;
  MVP_SLAVE_FRAME_ERROR_CNT_RESET:bit1;
 end;

 TOUT_CLAMP_CONTROL_G_Y=bitpacked record
  OUT_CLAMP_MAX_G_Y:bit14;
  RESERVED0        :bit2;
  OUT_CLAMP_MIN_G_Y:bit14;
  RESERVED1        :bit2;
 end;

 TPA_CL_VPORT_XOFFSET_1=bit32;

 TPA_CL_VPORT_XOFFSET_2=bit32;

 TPA_CL_VPORT_XOFFSET_3=bit32;

 TPA_CL_VPORT_XOFFSET_4=bit32;

 TPA_CL_VPORT_XOFFSET_5=bit32;

 TPA_CL_VPORT_XOFFSET_6=bit32;

 TPA_CL_VPORT_XOFFSET_7=bit32;

 TPA_CL_VPORT_XOFFSET_8=bit32;

 TPA_CL_VPORT_XOFFSET_9=bit32;

 TPA_CL_VPORT_XSCALE_10=bit32;

 TPA_CL_VPORT_XSCALE_11=bit32;

 TPA_CL_VPORT_XSCALE_12=bit32;

 TPA_CL_VPORT_XSCALE_13=bit32;

 TPA_CL_VPORT_XSCALE_14=bit32;

 TPA_CL_VPORT_XSCALE_15=bit32;

 TPA_CL_VPORT_YOFFSET_1=bit32;

 TPA_CL_VPORT_YOFFSET_2=bit32;

 TPA_CL_VPORT_YOFFSET_3=bit32;

 TPA_CL_VPORT_YOFFSET_4=bit32;

 TPA_CL_VPORT_YOFFSET_5=bit32;

 TPA_CL_VPORT_YOFFSET_6=bit32;

 TPA_CL_VPORT_YOFFSET_7=bit32;

 TPA_CL_VPORT_YOFFSET_8=bit32;

 TPA_CL_VPORT_YOFFSET_9=bit32;

 TPA_CL_VPORT_YSCALE_10=bit32;

 TPA_CL_VPORT_YSCALE_11=bit32;

 TPA_CL_VPORT_YSCALE_12=bit32;

 TPA_CL_VPORT_YSCALE_13=bit32;

 TPA_CL_VPORT_YSCALE_14=bit32;

 TPA_CL_VPORT_YSCALE_15=bit32;

 TPA_CL_VPORT_ZOFFSET_1=bit32;

 TPA_CL_VPORT_ZOFFSET_2=bit32;

 TPA_CL_VPORT_ZOFFSET_3=bit32;

 TPA_CL_VPORT_ZOFFSET_4=bit32;

 TPA_CL_VPORT_ZOFFSET_5=bit32;

 TPA_CL_VPORT_ZOFFSET_6=bit32;

 TPA_CL_VPORT_ZOFFSET_7=bit32;

 TPA_CL_VPORT_ZOFFSET_8=bit32;

 TPA_CL_VPORT_ZOFFSET_9=bit32;

 TPA_CL_VPORT_ZSCALE_10=bit32;

 TPA_CL_VPORT_ZSCALE_11=bit32;

 TPA_CL_VPORT_ZSCALE_12=bit32;

 TPA_CL_VPORT_ZSCALE_13=bit32;

 TPA_CL_VPORT_ZSCALE_14=bit32;

 TPA_CL_VPORT_ZSCALE_15=bit32;

 TPA_SC_FIFO_DEPTH_CNTL=bitpacked record
  DEPTH    :bit10;
  RESERVED0:bit22;
 end;

 TPA_SC_PERFCOUNTER0_HI=bit32;

 TPA_SC_PERFCOUNTER0_LO=bit32;

 TPA_SC_PERFCOUNTER1_HI=bit32;

 TPA_SC_PERFCOUNTER1_LO=bit32;

 TPA_SC_PERFCOUNTER2_HI=bit32;

 TPA_SC_PERFCOUNTER2_LO=bit32;

 TPA_SC_PERFCOUNTER3_HI=bit32;

 TPA_SC_PERFCOUNTER3_LO=bit32;

 TPA_SC_PERFCOUNTER4_HI=bit32;

 TPA_SC_PERFCOUNTER4_LO=bit32;

 TPA_SC_PERFCOUNTER5_HI=bit32;

 TPA_SC_PERFCOUNTER5_LO=bit32;

 TPA_SC_PERFCOUNTER6_HI=bit32;

 TPA_SC_PERFCOUNTER6_LO=bit32;

 TPA_SC_PERFCOUNTER7_HI=bit32;

 TPA_SC_PERFCOUNTER7_LO=bit32;

 TPA_SC_RASTER_CONFIG_1=bitpacked record
  SE_PAIR_MAP :bit2;
  SE_PAIR_XSEL:bit2;
  SE_PAIR_YSEL:bit2;
  RESERVED0   :bit26;
 end;

 TPA_SU_PERFCOUNTER0_HI=bitpacked record
  PERFCOUNTER_HI:bit16;
  RESERVED0     :bit16;
 end;

 TPA_SU_PERFCOUNTER0_LO=bit32;

 TPA_SU_PERFCOUNTER1_HI=bitpacked record
  PERFCOUNTER_HI:bit16;
  RESERVED0     :bit16;
 end;

 TPA_SU_PERFCOUNTER1_LO=bit32;

 TPA_SU_PERFCOUNTER2_HI=bitpacked record
  PERFCOUNTER_HI:bit16;
  RESERVED0     :bit16;
 end;

 TPA_SU_PERFCOUNTER2_LO=bit32;

 TPA_SU_PERFCOUNTER3_HI=bitpacked record
  PERFCOUNTER_HI:bit16;
  RESERVED0     :bit16;
 end;

 TPA_SU_PERFCOUNTER3_LO=bit32;

 TPB0_PLL_LC0_CTRL_REG0=bitpacked record
  PLL_DBG_LC_ANALOG_SEL_0  :bit2;
  PLL_DBG_LC_EXT_RESET_EN_0:bit1;
  PLL_DBG_LC_VCTL_ADC_EN_0 :bit1;
  PLL_TST_LC_USAMPLE_EN_0  :bit1;
  RESERVED0                :bit27;
 end;

 TPB0_PLL_LC0_OVRD_REG0=bitpacked record
  PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0   :bit3;
  PLL_CFG_LC_BW_CNTRL_OVRD_EN_0    :bit1;
  PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0:bit3;
  PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 :bit1;
  PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 :bit1;
  PLL_CFG_LC_CORECLK_EN_OVRD_EN_0  :bit1;
  PLL_CFG_LC_FBDIV_OVRD_VAL_0      :bit8;
  PLL_CFG_LC_FBDIV_OVRD_EN_0       :bit1;
  PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0   :bit9;
  PLL_CFG_LC_LF_CNTRL_OVRD_EN_0    :bit1;
  PLL_CFG_LC_REFDIV_OVRD_VAL_0     :bit2;
  PLL_CFG_LC_REFDIV_OVRD_EN_0      :bit1;
 end;

 TPB0_PLL_LC0_OVRD_REG1=bitpacked record
  PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0:bit3;
  PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 :bit1;
  PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 :bit1;
  PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0  :bit1;
  PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0:bit1;
  PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 :bit1;
  PLL_LC_PWRON_OVRD_VAL_0         :bit1;
  PLL_LC_PWRON_OVRD_EN_0          :bit1;
  RESERVED0                       :bit4;
  PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0  :bit4;
  PLL_CFG_LC_VCO_TUNE_OVRD_EN_0   :bit1;
  RESERVED1                       :bit13;
 end;

 TPB0_PLL_RO0_CTRL_REG0=bitpacked record
  PLL_DBG_RO_ANALOG_SEL_0  :bit2;
  PLL_DBG_RO_EXT_RESET_EN_0:bit1;
  PLL_DBG_RO_VCTL_ADC_EN_0 :bit1;
  PLL_DBG_RO_LF_CNTRL_0    :bit7;
  PLL_TST_RO_USAMPLE_EN_0  :bit1;
  RESERVED0                :bit20;
 end;

 TPB0_PLL_RO0_OVRD_REG0=bitpacked record
  PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0       :bit8;
  PLL_CFG_RO_BW_CNTRL_OVRD_EN_0        :bit1;
  PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0    :bit3;
  PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0     :bit1;
  PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0     :bit1;
  PLL_CFG_RO_CORECLK_EN_OVRD_EN_0      :bit1;
  PLL_CFG_RO_FBDIV_OVRD_VAL_0          :bit13;
  PLL_CFG_RO_FBDIV_OVRD_EN_0           :bit1;
  RESERVED0                            :bit1;
  PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0:bit1;
  PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 :bit1;
 end;

 TPB0_PLL_RO0_OVRD_REG1=bitpacked record
  PLL_CFG_RO_REFDIV_OVRD_VAL_0    :bit5;
  PLL_CFG_RO_REFDIV_OVRD_EN_0     :bit1;
  PLL_CFG_RO_VCO_MODE_OVRD_VAL_0  :bit2;
  PLL_CFG_RO_VCO_MODE_OVRD_EN_0   :bit1;
  PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 :bit1;
  PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0  :bit1;
  PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0:bit1;
  PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 :bit1;
  PLL_RO_PWRON_OVRD_VAL_0         :bit1;
  PLL_RO_PWRON_OVRD_EN_0          :bit1;
  RESERVED0                       :bit4;
  PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0:bit3;
  PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 :bit1;
  RESERVED1                       :bit9;
 end;

 TPB1_PLL_LC0_CTRL_REG0=bitpacked record
  PLL_DBG_LC_ANALOG_SEL_0  :bit2;
  PLL_DBG_LC_EXT_RESET_EN_0:bit1;
  PLL_DBG_LC_VCTL_ADC_EN_0 :bit1;
  PLL_TST_LC_USAMPLE_EN_0  :bit1;
  RESERVED0                :bit27;
 end;

 TPB1_PLL_LC0_OVRD_REG0=bitpacked record
  PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0   :bit3;
  PLL_CFG_LC_BW_CNTRL_OVRD_EN_0    :bit1;
  PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0:bit3;
  PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 :bit1;
  PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 :bit1;
  PLL_CFG_LC_CORECLK_EN_OVRD_EN_0  :bit1;
  PLL_CFG_LC_FBDIV_OVRD_VAL_0      :bit8;
  PLL_CFG_LC_FBDIV_OVRD_EN_0       :bit1;
  PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0   :bit9;
  PLL_CFG_LC_LF_CNTRL_OVRD_EN_0    :bit1;
  PLL_CFG_LC_REFDIV_OVRD_VAL_0     :bit2;
  PLL_CFG_LC_REFDIV_OVRD_EN_0      :bit1;
 end;

 TPB1_PLL_LC0_OVRD_REG1=bitpacked record
  PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0:bit3;
  PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 :bit1;
  PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 :bit1;
  PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0  :bit1;
  PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0:bit1;
  PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 :bit1;
  PLL_LC_PWRON_OVRD_VAL_0         :bit1;
  PLL_LC_PWRON_OVRD_EN_0          :bit1;
  RESERVED0                       :bit4;
  PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0  :bit4;
  PLL_CFG_LC_VCO_TUNE_OVRD_EN_0   :bit1;
  RESERVED1                       :bit13;
 end;

 TPB1_PLL_RO0_CTRL_REG0=bitpacked record
  PLL_DBG_RO_ANALOG_SEL_0  :bit2;
  PLL_DBG_RO_EXT_RESET_EN_0:bit1;
  PLL_DBG_RO_VCTL_ADC_EN_0 :bit1;
  PLL_DBG_RO_LF_CNTRL_0    :bit7;
  PLL_TST_RO_USAMPLE_EN_0  :bit1;
  RESERVED0                :bit20;
 end;

 TPB1_PLL_RO0_OVRD_REG0=bitpacked record
  PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0       :bit8;
  PLL_CFG_RO_BW_CNTRL_OVRD_EN_0        :bit1;
  PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0    :bit3;
  PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0     :bit1;
  PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0     :bit1;
  PLL_CFG_RO_CORECLK_EN_OVRD_EN_0      :bit1;
  PLL_CFG_RO_FBDIV_OVRD_VAL_0          :bit13;
  PLL_CFG_RO_FBDIV_OVRD_EN_0           :bit1;
  RESERVED0                            :bit1;
  PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0:bit1;
  PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 :bit1;
 end;

 TPB1_PLL_RO0_OVRD_REG1=bitpacked record
  PLL_CFG_RO_REFDIV_OVRD_VAL_0    :bit5;
  PLL_CFG_RO_REFDIV_OVRD_EN_0     :bit1;
  PLL_CFG_RO_VCO_MODE_OVRD_VAL_0  :bit2;
  PLL_CFG_RO_VCO_MODE_OVRD_EN_0   :bit1;
  PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 :bit1;
  PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0  :bit1;
  PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0:bit1;
  PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 :bit1;
  PLL_RO_PWRON_OVRD_VAL_0         :bit1;
  PLL_RO_PWRON_OVRD_EN_0          :bit1;
  RESERVED0                       :bit4;
  PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0:bit3;
  PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 :bit1;
  RESERVED1                       :bit9;
 end;

 TPCIEP_SRIOV_PRIV_CTRL=bitpacked record
  RX_SRIOV_VF_MAPPING_MODE      :bit2;
  SRIOV_SAVE_VFS_ON_VFENABLE_CLR:bit2;
  RESERVED0                     :bit28;
 end;

 TPCIE_ACS_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_ADV_ERR_CAP_CNTL=bitpacked record
  FIRST_ERR_PTR         :bit5;
  ECRC_GEN_CAP          :bit1;
  ECRC_GEN_EN           :bit1;
  ECRC_CHECK_CAP        :bit1;
  ECRC_CHECK_EN         :bit1;
  MULTI_HDR_RECD_CAP    :bit1;
  MULTI_HDR_RECD_EN     :bit1;
  TLP_PREFIX_LOG_PRESENT:bit1;
  RESERVED0             :bit20;
 end;

 TPCIE_ARI_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_ATS_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_BAR_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_DPA_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_LC_TRAINING_CNTL=bitpacked record
  LC_TRAINING_CNTL                 :bit4;
  LC_COMPLIANCE_RECEIVE            :bit1;
  LC_LOOK_FOR_MORE_NON_MATCHING_TS1:bit1;
  LC_L0S_L1_TRAINING_CNTL_EN       :bit1;
  LC_L1_LONG_WAKE_FIX_EN           :bit1;
  LC_POWER_STATE                   :bit3;
  LC_DONT_GO_TO_L0S_IF_L1_ARMED    :bit1;
  LC_INIT_SPD_CHG_WITH_CSR_EN      :bit1;
  LC_DISABLE_TRAINING_BIT_ARCH     :bit1;
  LC_WAIT_FOR_SETS_IN_RCFG         :bit1;
  LC_HOT_RESET_QUICK_EXIT_EN       :bit1;
  LC_EXTEND_WAIT_FOR_SKP           :bit1;
  LC_AUTONOMOUS_CHANGE_OFF         :bit1;
  LC_UPCONFIGURE_CAP_OFF           :bit1;
  LC_HW_LINK_DIS_EN                :bit1;
  LC_LINK_DIS_BY_HW                :bit1;
  LC_STATIC_TX_PIPE_COUNT_EN       :bit1;
  LC_ASPM_L1_NAK_TIMER_SEL         :bit2;
  LC_DONT_DEASSERT_RX_EN_IN_R_SPEED:bit1;
  LC_DONT_DEASSERT_RX_EN_IN_TEST   :bit1;
  LC_RESET_ASPM_L1_NAK_TIMER       :bit1;
  LC_SHORT_RCFG_TIMEOUT            :bit1;
  LC_ALLOW_TX_L1_CONTROL           :bit1;
  LC_WAIT_FOR_FOM_VALID_AFTER_TRACK:bit1;
  LC_EXTEND_EQ_REQ_TIME            :bit2;
 end;

 TPCIE_LTR_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_PERF_CNTL_TXCLK2=bitpacked record
  EVENT0_SEL    :bit8;
  EVENT1_SEL    :bit8;
  COUNTER0_UPPER:bit8;
  COUNTER1_UPPER:bit8;
 end;

 TPCIE_PORT_VC_CAP_REG1=bitpacked record
  EXT_VC_COUNT             :bit3;
  RESERVED0                :bit1;
  LOW_PRIORITY_EXT_VC_COUNT:bit3;
  RESERVED1                :bit1;
  REF_CLK                  :bit2;
  PORT_ARB_TABLE_ENTRY_SIZE:bit2;
  RESERVED2                :bit20;
 end;

 TPCIE_PORT_VC_CAP_REG2=bitpacked record
  VC_ARB_CAP         :bit8;
  RESERVED0          :bit16;
  VC_ARB_TABLE_OFFSET:bit8;
 end;

 TPCIE_P_DECODER_STATUS=bitpacked record
  P_DECODE_ERR:bit16;
  RESERVED0   :bit16;
 end;

 TPCIE_VC0_RESOURCE_CAP=bitpacked record
  PORT_ARB_CAP         :bit8;
  RESERVED0            :bit7;
  REJECT_SNOOP_TRANS   :bit1;
  MAX_TIME_SLOTS       :bit6;
  RESERVED1            :bit2;
  PORT_ARB_TABLE_OFFSET:bit8;
 end;

 TPCIE_VC1_RESOURCE_CAP=bitpacked record
  PORT_ARB_CAP         :bit8;
  RESERVED0            :bit7;
  REJECT_SNOOP_TRANS   :bit1;
  MAX_TIME_SLOTS       :bit6;
  RESERVED1            :bit2;
  PORT_ARB_TABLE_OFFSET:bit8;
 end;

 TPCIE_VENDOR_SPECIFIC1=bit32;

 TPCIE_VENDOR_SPECIFIC2=bit32;

 TPPLL_DIV_UPDATE_DEBUG=bitpacked record
  PLL_REF_DIV_CHANGED     :bit1;
  PLL_FB_DIV_CHANGED      :bit1;
  PLL_UPDATE_PENDING      :bit1;
  PLL_UPDATE_CURRENT_STATE:bit2;
  PLL_UPDATE_ENABLE       :bit1;
  PLL_UPDATE_REQ          :bit1;
  PLL_UPDATE_ACK          :bit1;
  RESERVED0               :bit24;
 end;

 TPRESCALE_GRPH_CONTROL=bitpacked record
  GRPH_PRESCALE_SELECT:bit1;
  GRPH_PRESCALE_R_SIGN:bit1;
  GRPH_PRESCALE_G_SIGN:bit1;
  GRPH_PRESCALE_B_SIGN:bit1;
  GRPH_PRESCALE_BYPASS:bit1;
  RESERVED0           :bit27;
 end;

 TPRESCALE_VALUES_OVL_Y=bitpacked record
  OVL_PRESCALE_BIAS_Y :bit16;
  OVL_PRESCALE_SCALE_Y:bit16;
 end;

 TPWR_AVFS0_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS1_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS2_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS3_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS4_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS5_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS6_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS7_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS8_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS9_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_DISP_TIMER2_DEBUG=bitpacked record
  DISP_TIMER_INT_RUNNING:bit1;
  DISP_TIMER_INT_STAT   :bit1;
  DISP_TIMER_INT        :bit1;
  RESERVED0             :bit4;
  DISP_TIMER_RUN_VAL    :bit25;
 end;

 TRAS_SIGNATURE_CONTROL=bitpacked record
  ENABLE   :bit1;
  RESERVED0:bit31;
 end;

 TRLC_GPM_CU_PD_TIMEOUT=bit32;

 TRLC_GPM_INT_FORCE_TH0=bit32;

 TRLC_GPM_INT_FORCE_TH1=bit32;

 TRLC_GPM_THREAD_ENABLE=bitpacked record
  THREAD0_ENABLE:bit1;
  THREAD1_ENABLE:bit1;
  THREAD2_ENABLE:bit1;
  THREAD3_ENABLE:bit1;
  RESERVED0     :bit28;
 end;

 TRLC_GPU_IOV_CFG_REG10=bitpacked record
  TIME_QUANTA_PF:bit16;
  RESERVED      :bit16;
 end;

 TRLC_GPU_IOV_CFG_REG11=bit32;

 TRLC_GPU_IOV_CFG_REG12=bitpacked record
  TIME_QUANTA_VF0:bit8;
  TIME_QUANTA_VF1:bit8;
  TIME_QUANTA_VF2:bit8;
  TIME_QUANTA_VF3:bit8;
 end;

 TRLC_GPU_IOV_CFG_REG13=bitpacked record
  TIME_QUANTA_VF4:bit8;
  TIME_QUANTA_VF5:bit8;
  TIME_QUANTA_VF6:bit8;
  TIME_QUANTA_VF7:bit8;
 end;

 TRLC_GPU_IOV_CFG_REG14=bitpacked record
  TIME_QUANTA_VF8 :bit8;
  TIME_QUANTA_VF9 :bit8;
  TIME_QUANTA_VF10:bit8;
  TIME_QUANTA_VF11:bit8;
 end;

 TRLC_GPU_IOV_CFG_REG15=bitpacked record
  TIME_QUANTA_VF12:bit8;
  TIME_QUANTA_VF13:bit8;
  TIME_QUANTA_VF14:bit8;
  TIME_QUANTA_VF15:bit8;
 end;

 TRLC_GPU_IOV_F32_RESET=bitpacked record
  RESET   :bit1;
  RESERVED:bit31;
 end;

 TRLC_GPU_IOV_INT_FORCE=bit32;

 TRLC_GPU_IOV_VF_ENABLE=bitpacked record
  VF_ENABLE:bit1;
  RESERVED :bit15;
  VF_NUM   :bit16;
 end;

 TRLC_LOAD_BALANCE_CNTR=bit32;

 TSCLK_DEEP_SLEEP_CNTL2=bitpacked record
  RLC_BUSY_MASK                    :bit1;
  HDP_BUSY_MASK                    :bit1;
  ROM_BUSY_MASK                    :bit1;
  IH_SEM_BUSY_MASK                 :bit1;
  PDMA_BUSY_MASK                   :bit1;
  RESERVED0                        :bit1;
  IDCT_BUSY_MASK                   :bit1;
  SDMA_BUSY_MASK                   :bit1;
  DC_AZ_BUSY_MASK                  :bit1;
  ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK:bit1;
  UVD_CG_MC_STAT_BUSY_MASK         :bit1;
  VCE_CG_MC_STAT_BUSY_MASK         :bit1;
  SAM_CG_MC_STAT_BUSY_MASK         :bit1;
  SAM_CG_STATUS_BUSY_MASK          :bit1;
  RLC_SMU_GFXCLK_OFF_MASK          :bit1;
  RESERVED1                        :bit5;
  RESERVED2                        :bit1;
  SHALLOW_DIV_ID                   :bit3;
  INOUT_CUSHION                    :bit8;
 end;

 TSCLK_DEEP_SLEEP_CNTL3=bitpacked record
  GRBM_0_SMU_BUSY_MASK :bit1;
  GRBM_1_SMU_BUSY_MASK :bit1;
  GRBM_2_SMU_BUSY_MASK :bit1;
  GRBM_3_SMU_BUSY_MASK :bit1;
  GRBM_4_SMU_BUSY_MASK :bit1;
  GRBM_5_SMU_BUSY_MASK :bit1;
  GRBM_6_SMU_BUSY_MASK :bit1;
  GRBM_7_SMU_BUSY_MASK :bit1;
  GRBM_8_SMU_BUSY_MASK :bit1;
  GRBM_9_SMU_BUSY_MASK :bit1;
  GRBM_10_SMU_BUSY_MASK:bit1;
  GRBM_11_SMU_BUSY_MASK:bit1;
  GRBM_12_SMU_BUSY_MASK:bit1;
  GRBM_13_SMU_BUSY_MASK:bit1;
  GRBM_14_SMU_BUSY_MASK:bit1;
  GRBM_15_SMU_BUSY_MASK:bit1;
  RESERVED0            :bit16;
 end;

 TSCLV_HORZ_FILTER_INIT=bitpacked record
  SCL_H_INIT_FRAC:bit24;
  SCL_H_INIT_INT :bit4;
  RESERVED0      :bit4;
 end;

 TSCLV_MODE_CHANGE_DET1=bitpacked record
  SCL_MODE_CHANGE      :bit1;
  RESERVED0            :bit3;
  SCL_MODE_CHANGE_ACK  :bit1;
  RESERVED1            :bit2;
  SCL_ALU_H_SCALE_RATIO:bit21;
  RESERVED2            :bit4;
 end;

 TSCLV_MODE_CHANGE_DET2=bitpacked record
  SCL_ALU_V_SCALE_RATIO:bit21;
  RESERVED0            :bit11;
 end;

 TSCLV_MODE_CHANGE_DET3=bitpacked record
  SCL_ALU_SOURCE_HEIGHT:bit14;
  RESERVED0            :bit2;
  SCL_ALU_SOURCE_WIDTH :bit14;
  RESERVED1            :bit2;
 end;

 TSCLV_MODE_CHANGE_MASK=bitpacked record
  SCL_MODE_CHANGE_MASK:bit1;
  RESERVED0           :bit31;
 end;

 TSCLV_TEST_DEBUG_INDEX=bitpacked record
  SCL_TEST_DEBUG_INDEX   :bit8;
  SCL_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0              :bit23;
 end;

 TSCLV_VERT_FILTER_INIT=bitpacked record
  SCL_V_INIT_FRAC:bit24;
  SCL_V_INIT_INT :bit3;
  RESERVED0      :bit5;
 end;

 TSCLV_VIEWPORT_START_C=bitpacked record
  VIEWPORT_Y_START_C:bit14;
  RESERVED0         :bit2;
  VIEWPORT_X_START_C:bit14;
  RESERVED1         :bit2;
 end;

 TSCL_COEF_RAM_TAP_DATA=bitpacked record
  SCL_C_RAM_EVEN_TAP_COEF   :bit14;
  RESERVED0                 :bit1;
  SCL_C_RAM_EVEN_TAP_COEF_EN:bit1;
  SCL_C_RAM_ODD_TAP_COEF    :bit14;
  RESERVED1                 :bit1;
  SCL_C_RAM_ODD_TAP_COEF_EN :bit1;
 end;

 TSDMA0_ATOMIC_PREOP_HI=bit32;

 TSDMA0_ATOMIC_PREOP_LO=bit32;

 TSDMA0_GFX_CSA_ADDR_HI=bit32;

 TSDMA0_GFX_CSA_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA0_GFX_MIDCMD_CNTL=bitpacked record
  DATA_VALID   :bit1;
  COPY_MODE    :bit1;
  RESERVED0    :bit2;
  SPLIT_STATE  :bit4;
  ALLOW_PREEMPT:bit1;
  RESERVED1    :bit23;
 end;

 TSDMA0_IB_OFFSET_FETCH=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA0_POWER_CNTL_IDLE=bitpacked record
  DELAY1:bit16;
  DELAY2:bit16;
 end;

 TSDMA0_RLC0_IB_BASE_HI=bit32;

 TSDMA0_RLC0_IB_BASE_LO=bitpacked record
  RESERVED0:bit5;
  ADDR     :bit27;
 end;

 TSDMA0_RLC0_RB_BASE_HI=bitpacked record
  ADDR     :bit24;
  RESERVED0:bit8;
 end;

 TSDMA0_RLC1_IB_BASE_HI=bit32;

 TSDMA0_RLC1_IB_BASE_LO=bitpacked record
  RESERVED0:bit5;
  ADDR     :bit27;
 end;

 TSDMA0_RLC1_RB_BASE_HI=bitpacked record
  ADDR     :bit24;
  RESERVED0:bit8;
 end;

 TSDMA1_ATOMIC_PREOP_HI=bit32;

 TSDMA1_ATOMIC_PREOP_LO=bit32;

 TSDMA1_GFX_CSA_ADDR_HI=bit32;

 TSDMA1_GFX_CSA_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA1_GFX_MIDCMD_CNTL=bitpacked record
  DATA_VALID   :bit1;
  COPY_MODE    :bit1;
  RESERVED0    :bit2;
  SPLIT_STATE  :bit4;
  ALLOW_PREEMPT:bit1;
  RESERVED1    :bit23;
 end;

 TSDMA1_IB_OFFSET_FETCH=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit20;
  RESERVED1:bit10;
 end;

 TSDMA1_POWER_CNTL_IDLE=bitpacked record
  DELAY1:bit16;
  DELAY2:bit16;
 end;

 TSDMA1_RLC0_IB_BASE_HI=bit32;

 TSDMA1_RLC0_IB_BASE_LO=bitpacked record
  RESERVED0:bit5;
  ADDR     :bit27;
 end;

 TSDMA1_RLC0_RB_BASE_HI=bitpacked record
  ADDR     :bit24;
  RESERVED0:bit8;
 end;

 TSDMA1_RLC1_IB_BASE_HI=bit32;

 TSDMA1_RLC1_IB_BASE_LO=bitpacked record
  RESERVED0:bit5;
  ADDR     :bit27;
 end;

 TSDMA1_RLC1_RB_BASE_HI=bitpacked record
  ADDR     :bit24;
  RESERVED0:bit8;
 end;

 TSLAVE_REQ_CREDIT_CNTL=bitpacked record
  BIF_SRBM_REQ_CREDIT:bit5;
  BIF_VGA_REQ_CREDIT :bit4;
  RESERVED0          :bit1;
  BIF_HDP_REQ_CREDIT :bit5;
  BIF_ROM_REQ_CREDIT :bit1;
  RESERVED1          :bit4;
  BIF_AZ_REQ_CREDIT  :bit1;
  RESERVED2          :bit4;
  BIF_XDMA_REQ_CREDIT:bit6;
  RESERVED3          :bit1;
 end;

 TSMU_INTERRUPT_CONTROL=bitpacked record
  DC_SMU_INT_ENABLE:bit1;
  RESERVED0        :bit3;
  DC_SMU_INT_STATUS:bit1;
  RESERVED1        :bit11;
  DC_SMU_INT_EVENT :bit16;
 end;

 TSPI_SHADER_COL_FORMAT=bitpacked record
  COL0_EXPORT_FORMAT:bit4;
  COL1_EXPORT_FORMAT:bit4;
  COL2_EXPORT_FORMAT:bit4;
  COL3_EXPORT_FORMAT:bit4;
  COL4_EXPORT_FORMAT:bit4;
  COL5_EXPORT_FORMAT:bit4;
  COL6_EXPORT_FORMAT:bit4;
  COL7_EXPORT_FORMAT:bit4;
 end;

 TSPI_SHADER_POS_FORMAT=bitpacked record
  POS0_EXPORT_FORMAT:bit4;
  POS1_EXPORT_FORMAT:bit4;
  POS2_EXPORT_FORMAT:bit4;
  POS3_EXPORT_FORMAT:bit4;
  RESERVED0         :bit16;
 end;

 TSPI_WF_LIFETIME_DEBUG=bitpacked record
  START_VALUE:bit31;
  OVERRIDE_EN:bit1;
 end;

 TSQ_FLAT_SCRATCH_WORD0=bitpacked record
  SIZE     :bit19;
  RESERVED0:bit13;
 end;

 TSQ_FLAT_SCRATCH_WORD1=bitpacked record
  OFFSET   :bit24;
  RESERVED0:bit8;
 end;

 TSQ_INTERRUPT_MSG_CTRL=bitpacked record
  STALL    :bit1;
  RESERVED0:bit31;
 end;

 TSQ_INTERRUPT_WORD_CMN=bitpacked record
  RESERVED0:bit24;
  SE_ID    :bit2;
  ENCODING :bit2;
  RESERVED1:bit4;
 end;

 TSQ_LB_DATA_ALU_CYCLES=bit32;

 TSQ_LB_DATA_ALU_STALLS=bit32;

 TSQ_LB_DATA_TEX_CYCLES=bit32;

 TSQ_LB_DATA_TEX_STALLS=bit32;

 TSQ_THREAD_TRACE_BASE2=bitpacked record
  ADDR_HI  :bit4;
  ATC      :bit1;
  RESERVED0:bit27;
 end;

 TSRBM_ISP_DOMAIN_ADDR0=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_ISP_DOMAIN_ADDR1=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_ISP_DOMAIN_ADDR2=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SAM_DOMAIN_ADDR0=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SAM_DOMAIN_ADDR1=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SAM_DOMAIN_ADDR2=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SYS_DOMAIN_ADDR0=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SYS_DOMAIN_ADDR1=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SYS_DOMAIN_ADDR2=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SYS_DOMAIN_ADDR3=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SYS_DOMAIN_ADDR4=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SYS_DOMAIN_ADDR5=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SYS_DOMAIN_ADDR6=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_UVD_DOMAIN_ADDR0=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_UVD_DOMAIN_ADDR1=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_UVD_DOMAIN_ADDR2=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_VCE_DOMAIN_ADDR0=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_VCE_DOMAIN_ADDR1=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_VCE_DOMAIN_ADDR2=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_VP8_DOMAIN_ADDR0=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSWRST_GENERAL_CONTROL=bitpacked record
  RECONFIGURE_EN    :bit1;
  ATOMIC_RESET_EN   :bit1;
  RESET_PERIOD      :bit3;
  RESERVED0         :bit3;
  WAIT_LINKUP       :bit1;
  FORCE_REGIDLE     :bit1;
  BLOCK_ON_IDLE     :bit1;
  RESERVED1         :bit1;
  CONFIG_XFER_MODE  :bit1;
  MUXSEL_XFER_MODE  :bit1;
  HLDTRAIN_XFER_MODE:bit1;
  RESERVED2         :bit1;
  BYPASS_HOLD       :bit1;
  BYPASS_PIF_HOLD   :bit1;
  RESERVED3         :bit10;
  EP_COMPLT_CHK_EN  :bit1;
  EP_COMPLT_WAIT_TMR:bit2;
  RESERVED4         :bit1;
 end;

 TTA_CS_BC_BASE_ADDR_HI=bitpacked record
  ADDRESS  :bit8;
  RESERVED0:bit24;
 end;

 TTHM_TMON0_RDIL10_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL11_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL12_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL13_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL14_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIL15_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR10_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR11_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR12_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR13_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR14_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON0_RDIR15_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL10_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL11_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL12_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL13_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL14_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIL15_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR10_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR11_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR12_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR13_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR14_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON1_RDIR15_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL10_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL11_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL12_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL13_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL14_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIL15_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR10_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR11_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR12_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR13_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR14_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TTHM_TMON2_RDIR15_DATA=bitpacked record
  Z        :bit11;
  VALID    :bit1;
  TEMP     :bit12;
  RESERVED0:bit8;
 end;

 TUSER_SQC_BANK_DISABLE=bitpacked record
  RESERVED0        :bit16;
  SQC0_BANK_DISABLE:bit4;
  SQC1_BANK_DISABLE:bit4;
  SQC2_BANK_DISABLE:bit4;
  SQC3_BANK_DISABLE:bit4;
 end;

 TUVD_LMI_VMID_INTERNAL=bitpacked record
  VCPU_NC0_VMID:bit4;
  VCPU_NC1_VMID:bit4;
  DPB_VMID     :bit4;
  DBW_VMID     :bit4;
  LBSI_VMID    :bit4;
  IDCT_VMID    :bit4;
  JPEG_VMID    :bit4;
  JPEG2_VMID   :bit4;
 end;

 TVDDGFX_IDLE_PARAMETER=bitpacked record
  VDDGFX_IDLE_THRESHOLD     :bit16;
  VDDGFX_IDLE_THRESHOLD_UNIT:bit4;
  RESERVED0                 :bit12;
 end;

 TVGA_INTERRUPT_CONTROL=bitpacked record
  VGA_MEM_ACCESS_INT_MASK       :bit1;
  RESERVED0                     :bit7;
  VGA_REG_ACCESS_INT_MASK       :bit1;
  RESERVED1                     :bit7;
  VGA_DISPLAY_SWITCH_INT_MASK   :bit1;
  RESERVED2                     :bit7;
  VGA_MODE_AUTO_TRIGGER_INT_MASK:bit1;
  RESERVED3                     :bit7;
 end;

 TVGT_DMA_NUM_INSTANCES=bit32;

 TVGT_EVENT_ADDRESS_REG=bitpacked record
  ADDRESS_LOW:bit28;
  RESERVED0  :bit4;
 end;

 TVGT_GROUP_VECT_0_CNTL=bitpacked record
  COMP_X_EN:bit1;
  COMP_Y_EN:bit1;
  COMP_Z_EN:bit1;
  COMP_W_EN:bit1;
  RESERVED0:bit4;
  STRIDE   :bit8;
  SHIFT    :bit8;
  RESERVED1:bit8;
 end;

 TVGT_GROUP_VECT_1_CNTL=bitpacked record
  COMP_X_EN:bit1;
  COMP_Y_EN:bit1;
  COMP_Z_EN:bit1;
  COMP_W_EN:bit1;
  RESERVED0:bit4;
  STRIDE   :bit8;
  SHIFT    :bit8;
  RESERVED1:bit8;
 end;

 TVGT_PRIMITIVEID_RESET=bit32;

 TVGT_TESS_DISTRIBUTION=bitpacked record
  ACCUM_ISOLINE:bit8;
  ACCUM_TRI    :bit8;
  ACCUM_QUAD   :bit8;
  DONUT_SPLIT  :bit5;
  TRAP_SPLIT   :bit3;
 end;

 TVM_INVALIDATE_REQUEST=bitpacked record
  INVALIDATE_DOMAIN_0 :bit1;
  INVALIDATE_DOMAIN_1 :bit1;
  INVALIDATE_DOMAIN_2 :bit1;
  INVALIDATE_DOMAIN_3 :bit1;
  INVALIDATE_DOMAIN_4 :bit1;
  INVALIDATE_DOMAIN_5 :bit1;
  INVALIDATE_DOMAIN_6 :bit1;
  INVALIDATE_DOMAIN_7 :bit1;
  INVALIDATE_DOMAIN_8 :bit1;
  INVALIDATE_DOMAIN_9 :bit1;
  INVALIDATE_DOMAIN_10:bit1;
  INVALIDATE_DOMAIN_11:bit1;
  INVALIDATE_DOMAIN_12:bit1;
  INVALIDATE_DOMAIN_13:bit1;
  INVALIDATE_DOMAIN_14:bit1;
  INVALIDATE_DOMAIN_15:bit1;
  RESERVED0           :bit16;
 end;

 TXDMA_MSTR_CHANNEL_DIM=bitpacked record
  XDMA_MSTR_CHANNEL_WIDTH :bit14;
  RESERVED0               :bit2;
  XDMA_MSTR_CHANNEL_HEIGHT:bit14;
  RESERVED1               :bit2;
 end;

 TXDMA_PERF_MEAS_STATUS=bitpacked record
  XDMA_PERF_MEAS_STATUS:bit8;
  RESERVED0            :bit24;
 end;

 TXDMA_RBBMIF_RDWR_CNTL=bitpacked record
  XDMA_RBBMIF_RDWR_DELAY      :bit3;
  XDMA_RBBMIF_RDWR_TIMEOUT_DIS:bit1;
  RESERVED0                   :bit11;
  XDMA_RBBMIF_TIMEOUT_DELAY   :bit17;
 end;

 TXDMA_SLV_CHANNEL_CNTL=bitpacked record
  XDMA_SLV_CHANNEL_WEIGHT    :bit9;
  RESERVED0                  :bit7;
  XDMA_SLV_STOP_TRANSFER     :bit1;
  XDMA_SLV_CHANNEL_SOFT_RESET:bit1;
  RESERVED1                  :bit6;
  XDMA_SLV_CHANNEL_ACTIVE    :bit1;
  RESERVED2                  :bit7;
 end;

 TXDMA_SLV_FLIP_PENDING=bitpacked record
  XDMA_SLV_FLIP_PENDING:bit1;
  RESERVED0            :bit31;
 end;

 TXDMA_SLV_WB_RATE_CNTL=bitpacked record
  XDMA_SLV_WB_BURST_SIZE  :bit9;
  RESERVED0               :bit7;
  XDMA_SLV_WB_BURST_PERIOD:bit16;
 end;

 TXDMA_TEST_DEBUG_INDEX=bitpacked record
  XDMA_TEST_DEBUG_INDEX   :bit8;
  XDMA_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0               :bit23;
 end;

 TAFMT_AUDIO_CRC_CONTROL=bitpacked record
  AFMT_AUDIO_CRC_EN    :bit1;
  RESERVED0            :bit3;
  AFMT_AUDIO_CRC_CONT  :bit1;
  RESERVED1            :bit3;
  AFMT_AUDIO_CRC_SOURCE:bit1;
  RESERVED2            :bit3;
  AFMT_AUDIO_CRC_CH_SEL:bit4;
  AFMT_AUDIO_CRC_COUNT :bit16;
 end;

 TAFMT_AUDIO_SRC_CONTROL=bitpacked record
  AFMT_AUDIO_SRC_SELECT:bit3;
  RESERVED0            :bit29;
 end;

 TATC_VM_APERTURE0_CNTL2=bitpacked record
  VMIDS_USING_RANGE:bit16;
  RESERVED0        :bit16;
 end;

 TATC_VM_APERTURE1_CNTL2=bitpacked record
  VMIDS_USING_RANGE:bit16;
  RESERVED0        :bit16;
 end;

 TAVSYNC_COUNTER_CONTROL=bitpacked record
  AVSYNC_COUNTER_ENABLE:bit1;
  RESERVED0            :bit31;
 end;

 TAZALIA_BDL_DMA_CONTROL=bitpacked record
  BDL_DMA_NON_SNOOP        :bit2;
  INPUT_BDL_DMA_NON_SNOOP  :bit2;
  BDL_DMA_ISOCHRONOUS      :bit2;
  INPUT_BDL_DMA_ISOCHRONOUS:bit2;
  RESERVED0                :bit24;
 end;

 TBLND_REG_UPDATE_STATUS=bitpacked record
  DCP_BLNDC_GRPH_UPDATE_PENDING     :bit1;
  DCP_BLNDO_GRPH_UPDATE_PENDING     :bit1;
  DCP_BLNDC_GRPH_SURF_UPDATE_PENDING:bit1;
  DCP_BLNDO_GRPH_SURF_UPDATE_PENDING:bit1;
  DCP_BLNDC_OVL_UPDATE_PENDING      :bit1;
  DCP_BLNDO_OVL_UPDATE_PENDING      :bit1;
  DCP_BLNDC_CUR_UPDATE_PENDING      :bit1;
  DCP_BLNDO_CUR_UPDATE_PENDING      :bit1;
  SCL_BLNDC_UPDATE_PENDING          :bit1;
  SCL_BLNDO_UPDATE_PENDING          :bit1;
  BLND_BLNDC_UPDATE_PENDING         :bit1;
  BLND_BLNDO_UPDATE_PENDING         :bit1;
  RESERVED0                         :bit20;
 end;

 TCB_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL  :bit9;
  RESERVED0 :bit1;
  PERF_SEL1 :bit9;
  RESERVED1 :bit1;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TCB_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL :bit9;
  RESERVED0:bit19;
  PERF_MODE:bit4;
 end;

 TCB_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL :bit9;
  RESERVED0:bit19;
  PERF_MODE:bit4;
 end;

 TCB_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL :bit9;
  RESERVED0:bit19;
  PERF_MODE:bit4;
 end;

 TCC_SMU_TST_EFUSE1_MISC=bitpacked record
  RESERVED0          :bit1;
  RF_RM_6_2          :bit5;
  RME                :bit1;
  MBIST_DISABLE      :bit1;
  HARD_REPAIR_DISABLE:bit1;
  SOFT_REPAIR_DISABLE:bit1;
  GPU_DIS            :bit1;
  SMS_PWRDWN_DISABLE :bit1;
  CRBBMP1500_DISA    :bit1;
  CRBBMP1500_DISB    :bit1;
  RM_RF8             :bit1;
  RESERVED1          :bit7;
  DFT_SPARE1         :bit1;
  DFT_SPARE2         :bit1;
  DFT_SPARE3         :bit1;
  VCE_DISABLE        :bit1;
  DCE_SCAN_DISABLE   :bit1;
  RESERVED2          :bit5;
 end;

 TCGTS_CU10_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU10_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU11_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU11_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU12_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU12_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU13_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU13_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU14_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU14_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU15_SP0_CTRL_REG=bitpacked record
  SP00                  :bit7;
  SP00_OVERRIDE         :bit1;
  SP00_BUSY_OVERRIDE    :bit2;
  SP00_LS_OVERRIDE      :bit1;
  SP00_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP01                  :bit7;
  SP01_OVERRIDE         :bit1;
  SP01_BUSY_OVERRIDE    :bit2;
  SP01_LS_OVERRIDE      :bit1;
  SP01_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCGTS_CU15_SP1_CTRL_REG=bitpacked record
  SP10                  :bit7;
  SP10_OVERRIDE         :bit1;
  SP10_BUSY_OVERRIDE    :bit2;
  SP10_LS_OVERRIDE      :bit1;
  SP10_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0             :bit4;
  SP11                  :bit7;
  SP11_OVERRIDE         :bit1;
  SP11_BUSY_OVERRIDE    :bit2;
  SP11_LS_OVERRIDE      :bit1;
  SP11_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1             :bit4;
 end;

 TCG_MULT_THERMAL_STATUS=bitpacked record
  ASIC_MAX_TEMP:bit9;
  CTF_TEMP     :bit9;
  RESERVED0    :bit14;
 end;

 TCNV_CSC_ROUND_OFFSET_B=bitpacked record
  CNV_CSC_ROUND_OFFSET_B:bit16;
  RESERVED0             :bit16;
 end;

 TCNV_CSC_ROUND_OFFSET_G=bitpacked record
  CNV_CSC_ROUND_OFFSET_G:bit16;
  RESERVED0             :bit16;
 end;

 TCNV_CSC_ROUND_OFFSET_R=bitpacked record
  CNV_CSC_ROUND_OFFSET_R:bit16;
  RESERVED0             :bit16;
 end;

 TCOMPUTE_THREADGROUP_ID=bit32;

 TCP_CE_PRGRM_CNTR_START=bitpacked record
  IP_START :bit11;
  RESERVED0:bit21;
 end;

 TCP_CPC_GRBM_FREE_COUNT=bitpacked record
  FREE_COUNT:bit6;
  RESERVED0 :bit26;
 end;

 TCP_CPC_HALT_HYST_COUNT=bitpacked record
  COUNT    :bit4;
  RESERVED0:bit28;
 end;

 TCP_DE_LAST_INVAL_COUNT=bit32;

 TCP_DMA_PFP_DST_ADDR_HI=bitpacked record
  DST_ADDR_HI:bit16;
  RESERVED0  :bit16;
 end;

 TCP_DMA_PFP_SRC_ADDR_HI=bitpacked record
  SRC_ADDR_HI:bit16;
  RESERVED0  :bit4;
  RESERVED1  :bit2;
  RESERVED2  :bit7;
  RESERVED3  :bit2;
  RESERVED4  :bit1;
 end;

 TCP_DRAW_INDX_INDR_ADDR=bit32;

 TCP_DRAW_OBJECT_COUNTER=bitpacked record
  COUNT    :bit16;
  RESERVED0:bit16;
 end;

 TCP_DRAW_WINDOW_MASK_HI=bit32;

 TCP_ECC_FIRSTOCCURRENCE=bitpacked record
  _INTERFACE:bit2;
  RESERVED0 :bit2;
  CLIENT    :bit4;
  ME        :bit2;
  PIPE      :bit2;
  QUEUE     :bit3;
  RESERVED1 :bit1;
  VMID      :bit4;
  RESERVED2 :bit12;
 end;

 TCP_EOP_DONE_EVENT_CNTL=bitpacked record
  WBINV_TC_OP     :bit7;
  RESERVED0       :bit5;
  WBINV_ACTION_ENA:bit6;
  RESERVED1       :bit7;
  CACHE_CONTROL   :bit1;
  RESERVED2       :bit1;
  MTYPE           :bit2;
  RESERVED3       :bit3;
 end;

 TCP_HQD_CNTL_STACK_SIZE=bitpacked record
  RESERVED0:bit12;
  SIZE     :bit3;
  RESERVED1:bit17;
 end;

 TCP_HQD_DEQUEUE_REQUEST=bitpacked record
  DEQUEUE_REQ   :bit3;
  RESERVED0     :bit1;
  IQ_REQ_PEND   :bit1;
  RESERVED1     :bit3;
  DEQUEUE_INT   :bit1;
  IQ_REQ_PEND_EN:bit1;
  DEQUEUE_REQ_EN:bit1;
  RESERVED2     :bit21;
 end;

 TCP_HQD_IB_BASE_ADDR_HI=bitpacked record
  IB_BASE_ADDR_HI:bit16;
  RESERVED0      :bit16;
 end;

 TCP_HQD_WG_STATE_OFFSET=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit23;
  RESERVED1:bit7;
 end;

 TCP_MEC_ME1_HEADER_DUMP=bit32;

 TCP_MEC_ME2_HEADER_DUMP=bit32;

 TCP_ME_PRGRM_CNTR_START=bitpacked record
  IP_START :bit12;
  RESERVED0:bit20;
 end;

 TCP_PFP_ATOMIC_PREOP_HI=bit32;

 TCP_PFP_ATOMIC_PREOP_LO=bit32;

 TCP_PRT_LOD_STATS_CNTL0=bit32;

 TCP_PRT_LOD_STATS_CNTL1=bit32;

 TCP_PRT_LOD_STATS_CNTL2=bitpacked record
  BASE_HI         :bit2;
  INTERVAL        :bit8;
  RESET_CNT       :bit8;
  RESET_FORCE     :bit1;
  REPORT_AND_RESET:bit1;
  MC_ENDIAN_SWAP  :bit2;
  RESERVED0       :bit1;
  MC_VMID         :bit4;
  RESERVED1       :bit1;
  CACHE_POLICY    :bit1;
  RESERVED2       :bit1;
  MTYPE           :bit2;
 end;

 TCP_RB_DOORBELL_CONTROL=bitpacked record
  RESERVED0      :bit2;
  DOORBELL_OFFSET:bit21;
  RESERVED1      :bit7;
  DOORBELL_EN    :bit1;
  DOORBELL_HIT   :bit1;
 end;

 TCP_VGT_GSPRIM_COUNT_HI=bit32;

 TCP_VGT_GSPRIM_COUNT_LO=bit32;

 TCP_VGT_IAPRIM_COUNT_HI=bit32;

 TCP_VGT_IAPRIM_COUNT_LO=bit32;

 TCP_VGT_IAVERT_COUNT_HI=bit32;

 TCP_VGT_IAVERT_COUNT_LO=bit32;

 TCRTC_H_BLANK_EARLY_NUM=bitpacked record
  CRTC_H_BLANK_EARLY_NUM    :bit10;
  RESERVED0                 :bit6;
  CRTC_H_BLANK_EARLY_NUM_DIS:bit1;
  RESERVED1                 :bit15;
 end;

 TCRTC_H_BLANK_START_END=bitpacked record
  CRTC_H_BLANK_START:bit14;
  RESERVED0         :bit2;
  CRTC_H_BLANK_END  :bit14;
  RESERVED1         :bit2;
 end;

 TCRTC_INTERLACE_CONTROL=bitpacked record
  CRTC_INTERLACE_ENABLE          :bit1;
  RESERVED0                      :bit15;
  CRTC_INTERLACE_FORCE_NEXT_FIELD:bit2;
  RESERVED1                      :bit14;
 end;

 TCRTC_INTERRUPT_CONTROL=bitpacked record
  CRTC_SNAPSHOT_INT_MSK              :bit1;
  CRTC_SNAPSHOT_INT_TYPE             :bit1;
  RESERVED0                          :bit2;
  CRTC_V_UPDATE_INT_MSK              :bit1;
  CRTC_V_UPDATE_INT_TYPE             :bit1;
  RESERVED1                          :bit2;
  CRTC_FORCE_COUNT_NOW_INT_MSK       :bit1;
  CRTC_FORCE_COUNT_NOW_INT_TYPE      :bit1;
  RESERVED2                          :bit6;
  CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK :bit1;
  CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE:bit1;
  RESERVED3                          :bit6;
  CRTC_TRIGA_INT_MSK                 :bit1;
  CRTC_TRIGB_INT_MSK                 :bit1;
  CRTC_TRIGA_INT_TYPE                :bit1;
  CRTC_TRIGB_INT_TYPE                :bit1;
  CRTC_VSYNC_NOM_INT_MSK             :bit1;
  CRTC_VSYNC_NOM_INT_TYPE            :bit1;
  CRTC_GSL_VSYNC_GAP_INT_MSK         :bit1;
  CRTC_GSL_VSYNC_GAP_INT_TYPE        :bit1;
 end;

 TCRTC_NOM_VERT_POSITION=bitpacked record
  CRTC_VERT_COUNT_NOM:bit14;
  RESERVED0          :bit18;
 end;

 TCRTC_SNAPSHOT_POSITION=bitpacked record
  CRTC_SNAPSHOT_VERT_COUNT:bit14;
  RESERVED0               :bit2;
  CRTC_SNAPSHOT_HORZ_COUNT:bit14;
  RESERVED1               :bit2;
 end;

 TCRTC_TRIGA_MANUAL_TRIG=bitpacked record
  CRTC_TRIGA_MANUAL_TRIG:bit1;
  RESERVED0             :bit31;
 end;

 TCRTC_TRIGB_MANUAL_TRIG=bitpacked record
  CRTC_TRIGB_MANUAL_TRIG:bit1;
  RESERVED0             :bit31;
 end;

 TCRTC_VERT_SYNC_CONTROL=bitpacked record
  CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED:bit1;
  RESERVED0                          :bit7;
  CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR   :bit1;
  RESERVED1                          :bit7;
  CRTC_AUTO_FORCE_VSYNC_MODE         :bit2;
  RESERVED2                          :bit14;
 end;

 TCRTC_V_BLANK_START_END=bitpacked record
  CRTC_V_BLANK_START:bit14;
  RESERVED0         :bit2;
  CRTC_V_BLANK_END  :bit14;
  RESERVED1         :bit2;
 end;

 TDAC_AUTODETECT_CONTROL=bitpacked record
  DAC_AUTODETECT_MODE              :bit2;
  RESERVED0                        :bit6;
  DAC_AUTODETECT_FRAME_TIME_COUNTER:bit8;
  DAC_AUTODETECT_CHECK_MASK        :bit3;
  RESERVED1                        :bit13;
 end;

 TDAC_AUTO_CALIB_CONTROL=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit1;
  RESERVED4:bit10;
  RESERVED5:bit6;
  RESERVED6:bit3;
  RESERVED7:bit5;
  RESERVED8:bit1;
  RESERVED9:bit3;
 end;

 TDB_OCCLUSION_COUNT0_HI=bitpacked record
  COUNT_HI :bit31;
  RESERVED0:bit1;
 end;

 TDB_OCCLUSION_COUNT1_HI=bitpacked record
  COUNT_HI :bit31;
  RESERVED0:bit1;
 end;

 TDB_OCCLUSION_COUNT2_HI=bitpacked record
  COUNT_HI :bit31;
  RESERVED0:bit1;
 end;

 TDB_OCCLUSION_COUNT3_HI=bitpacked record
  COUNT_HI :bit31;
  RESERVED0:bit1;
 end;

 TDB_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TDB_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TDB_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TDB_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TDCCG_AUDIO_DTO0_MODULE=bit32;

 TDCCG_AUDIO_DTO1_MODULE=bit32;

 TDCCG_GATE_DISABLE_CNTL=bitpacked record
  DISPCLK_DCCG_GATE_DISABLE   :bit1;
  DISPCLK_R_DCCG_GATE_DISABLE :bit1;
  SCLK_GATE_DISABLE           :bit1;
  DPREFCLK_GATE_DISABLE       :bit1;
  DACACLK_GATE_DISABLE        :bit1;
  DACBCLK_GATE_DISABLE        :bit1;
  DVOACLK_GATE_DISABLE        :bit1;
  DPDBG_CLK_GATE_DISABLE      :bit1;
  DPREFCLK_R_DCCG_GATE_DISABLE:bit1;
  RESERVED0                   :bit7;
  PCLK_TV_GATE_DISABLE        :bit1;
  AOMCLK0_GATE_DISABLE        :bit1;
  AOMCLK1_GATE_DISABLE        :bit1;
  AOMCLK2_GATE_DISABLE        :bit1;
  DISPCLK_R_DCCG_RAMP_DISABLE :bit1;
  AUDIO_DTO2_CLK_GATE_DISABLE :bit1;
  DPREFCLK_GTC_GATE_DISABLE   :bit1;
  UNB_DB_CLK_GATE_DISABLE     :bit1;
  RESERVED1                   :bit2;
  REFCLK_GATE_DISABLE         :bit1;
  REFCLK_R_DIG_GATE_DISABLE   :bit1;
  DSICLK_GATE_DISABLE         :bit1;
  BYTECLK_GATE_DISABLE        :bit1;
  ESCCLK_GATE_DISABLE         :bit1;
  RESERVED2                   :bit1;
 end;

 TDCP_FP_CONVERTED_FIELD=bitpacked record
  DCP_FP_CONVERTED_FIELD_DATA :bit18;
  RESERVED0                   :bit2;
  DCP_FP_CONVERTED_FIELD_INDEX:bit7;
  RESERVED1                   :bit5;
 end;

 TDC_ABM1_BL_MASTER_LOCK=bitpacked record
  RESERVED0          :bit31;
  ABM1_BL_MASTER_LOCK:bit1;
 end;

 TDC_ABM1_HG_SAMPLE_RATE=bitpacked record
  ABM1_HG_SAMPLE_RATE_COUNT_EN                      :bit1;
  ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER           :bit1;
  RESERVED0                                         :bit6;
  ABM1_HG_SAMPLE_RATE_FRAME_COUNT                   :bit8;
  ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET:bit8;
  RESERVED1                                         :bit7;
  ABM1_HGLS_REG_LOCK                                :bit1;
 end;

 TDC_ABM1_LS_PIXEL_COUNT=bitpacked record
  ABM1_LS_PIXEL_COUNT:bit24;
  RESERVED0          :bit8;
 end;

 TDC_ABM1_LS_SAMPLE_RATE=bitpacked record
  ABM1_LS_SAMPLE_RATE_COUNT_EN                      :bit1;
  ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER           :bit1;
  RESERVED0                                         :bit6;
  ABM1_LS_SAMPLE_RATE_FRAME_COUNT                   :bit8;
  ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET:bit8;
  RESERVED1                                         :bit7;
  ABM1_HGLS_REG_LOCK                                :bit1;
 end;

 TDC_ABM1_LS_SUM_OF_LUMA=bit32;

 TDC_GPIO_PAD_STRENGTH_1=bitpacked record
  GENLK_STRENGTH_SN :bit4;
  GENLK_STRENGTH_SP :bit4;
  RX_HPD_STRENGTH_SN:bit4;
  RX_HPD_STRENGTH_SP:bit4;
  RESERVED0         :bit8;
  SYNC_STRENGTH_SN  :bit4;
  SYNC_STRENGTH_SP  :bit4;
 end;

 TDC_GPIO_PAD_STRENGTH_2=bitpacked record
  STRENGTH_SN          :bit4;
  STRENGTH_SP          :bit4;
  EXT_RESET_DRVSTRENGTH:bit3;
  RESERVED0            :bit1;
  REF_27_DRVSTRENGTH   :bit3;
  RESERVED1            :bit1;
  PWRSEQ_STRENGTH_SN   :bit4;
  PWRSEQ_STRENGTH_SP   :bit4;
  RESERVED2            :bit6;
  REF_27_SRC_SEL       :bit2;
 end;

 TDC_GPU_TIMER_READ_CNTL=bitpacked record
  DC_GPU_TIMER_READ_SELECT                :bit6;
  RESERVED0                               :bit2;
  DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM:bit3;
  DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM:bit3;
  DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM:bit3;
  DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM:bit3;
  DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM:bit3;
  DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM:bit3;
  RESERVED1                               :bit6;
 end;

 TDC_HPD_FAST_TRAIN_CNTL=bitpacked record
  DC_HPD_CONNECT_AUX_TX_DELAY    :bit8;
  RESERVED0                      :bit4;
  DC_HPD_CONNECT_FAST_TRAIN_DELAY:bit8;
  RESERVED1                      :bit4;
  DC_HPD_CONNECT_AUX_TX_EN       :bit1;
  RESERVED2                      :bit3;
  DC_HPD_CONNECT_FAST_TRAIN_EN   :bit1;
  RESERVED3                      :bit3;
 end;

 TDENORM_CLAMP_RANGE_G_Y=bitpacked record
  RANGE_CLAMP_MAX_G_Y:bit12;
  RANGE_CLAMP_MIN_G_Y:bit12;
  RESERVED0          :bit8;
 end;

 TDIG_FE_TEST_DEBUG_DATA=bit32;

 TDMCU_FW_ISR_START_ADDR=bitpacked record
  FW_ISR_START_ADDR_LSB:bit8;
  FW_ISR_START_ADDR_MSB:bit8;
  RESERVED0            :bit16;
 end;

 TDP_DPHY_CRC_MST_STATUS=bitpacked record
  DPHY_CRC_MST_PHASE_LOCK     :bit1;
  RESERVED0                   :bit7;
  DPHY_CRC_MST_PHASE_ERROR    :bit1;
  RESERVED1                   :bit7;
  DPHY_CRC_MST_PHASE_ERROR_ACK:bit1;
  RESERVED2                   :bit15;
 end;

 TDP_FE_TEST_DEBUG_INDEX=bitpacked record
  DP_FE_TEST_DEBUG_INDEX   :bit8;
  DP_FE_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0                :bit23;
 end;

 TFBC_CLIENT_REGION_MASK=bitpacked record
  RESERVED0             :bit16;
  FBC_MEMORY_REGION_MASK:bit4;
  RESERVED1             :bit12;
 end;

 TFBC_DEBUG_CSR_RDATA_HI=bitpacked record
  FBC_DEBUG_CSR_RDATA_HI:bit8;
  RESERVED0             :bit24;
 end;

 TFBC_DEBUG_CSR_WDATA_HI=bitpacked record
  FBC_DEBUG_CSR_WDATA_HI:bit8;
  RESERVED0             :bit24;
 end;

 TFMT_DITHER_RAND_B_SEED=bitpacked record
  FMT_RAND_B_SEED:bit8;
  RESERVED0      :bit8;
  FMT_OFFSET_B_CB:bit16;
 end;

 TFMT_DITHER_RAND_G_SEED=bitpacked record
  FMT_RAND_G_SEED:bit8;
  RESERVED0      :bit8;
  FMT_OFFSET_G_Y :bit16;
 end;

 TFMT_DITHER_RAND_R_SEED=bitpacked record
  FMT_RAND_R_SEED:bit8;
  RESERVED0      :bit8;
  FMT_OFFSET_R_CR:bit16;
 end;

 TGDS_GWS_RESOURCE_RESET=bitpacked record
  RESET      :bit1;
  RESERVED0  :bit7;
  RESOURCE_ID:bit8;
  RESERVED1  :bit16;
 end;

 TGRPH_INTERRUPT_CONTROL=bitpacked record
  GRPH_PFLIP_INT_MASK:bit1;
  RESERVED0          :bit7;
  GRPH_PFLIP_INT_TYPE:bit1;
  RESERVED1          :bit23;
 end;

 THDP_SC_MULTI_CHIP_CNTL=bitpacked record
  LOG2_NUM_CHIPS      :bit3;
  MULTI_CHIP_TILE_SIZE:bit2;
  RESERVED0           :bit27;
 end;

 THDP_XDP_D2H_BAR_UPDATE=bitpacked record
  D2H_BAR_UPDATE_ADDR     :bit16;
  D2H_BAR_UPDATE_FLUSH_NUM:bit4;
  D2H_BAR_UPDATE_BAR_NUM  :bit3;
  RESERVED0               :bit9;
 end;

 THDP_XDP_HDP_MBX_MC_CFG=bitpacked record
  HDP_MBX_MC_CFG_TAP_WRREQ_PRIV:bit1;
  HDP_MBX_MC_CFG_TAP_WRREQ_SWAP:bit2;
  HDP_MBX_MC_CFG_TAP_WRREQ_TRAN:bit1;
  HDP_MBX_MC_CFG_TAP_WRREQ_VMID:bit4;
  RESERVED0                    :bit24;
 end;

 THDP_XDP_P2P_MBX_OFFSET=bitpacked record
  P2P_MBX_OFFSET:bit14;
  RESERVED0     :bit18;
 end;

 TIA_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TIA_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit20;
  PERF_MODE:bit4;
 end;

 TIA_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit20;
  PERF_MODE:bit4;
 end;

 TIA_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit20;
  PERF_MODE:bit4;
 end;

 TIH_PERFCOUNTER0_RESULT=bit32;

 TIH_PERFCOUNTER1_RESULT=bit32;

 TLBV_MEMORY_SIZE_STATUS=bitpacked record
  LB_MEMORY_SIZE_STATUS:bit12;
  RESERVED0            :bit20;
 end;

 TLBV_SNAPSHOT_V_COUNTER=bitpacked record
  SNAPSHOT_V_COUNTER:bit15;
  RESERVED0         :bit17;
 end;

 TLB_BUFFER_LEVEL_STATUS=bitpacked record
  REQ_FIFO_LEVEL     :bit6;
  RESERVED0          :bit4;
  REQ_FIFO_FULL_CNTL :bit6;
  DATA_BUFFER_LEVEL  :bit12;
  DATA_FIFO_FULL_CNTL:bit4;
 end;

 TLB_BUFFER_URGENCY_CTRL=bitpacked record
  LB_BUFFER_URGENCY_MARK_ON :bit12;
  RESERVED0                 :bit4;
  LB_BUFFER_URGENCY_MARK_OFF:bit12;
  RESERVED1                 :bit4;
 end;

 TLB_KEYER_COLOR_REP_G_Y=bitpacked record
  RESERVED0             :bit4;
  LB_KEYER_COLOR_REP_G_Y:bit12;
  RESERVED1             :bit16;
 end;

 TMAILBOX_MSGBUF_RCV_DW0=bit32;

 TMAILBOX_MSGBUF_RCV_DW1=bit32;

 TMAILBOX_MSGBUF_RCV_DW2=bit32;

 TMAILBOX_MSGBUF_RCV_DW3=bit32;

 TMAILBOX_MSGBUF_TRN_DW0=bit32;

 TMAILBOX_MSGBUF_TRN_DW1=bit32;

 TMAILBOX_MSGBUF_TRN_DW2=bit32;

 TMAILBOX_MSGBUF_TRN_DW3=bit32;

 TMCIF_WB_HVVMID_CONTROL=bitpacked record
  RESERVED0                :bit8;
  MCIF_WB_DEFAULT_VMID     :bit4;
  RESERVED1                :bit4;
  MCIF_WB_ALLOWED_VMID_MASK:bit16;
 end;

 TMC_ARB_HARSH_BWCNT0_RD=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_HARSH_BWCNT0_WR=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_HARSH_BWCNT1_RD=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_ARB_HARSH_BWCNT1_WR=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_ARB_HARSH_TX_HI0_RD=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_HARSH_TX_HI0_WR=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_HARSH_TX_HI1_RD=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_ARB_HARSH_TX_HI1_WR=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_ARB_HARSH_TX_LO0_RD=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_HARSH_TX_LO0_WR=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_HARSH_TX_LO1_RD=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_ARB_HARSH_TX_LO1_WR=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_CITF_CREDITS_ARB_RD=bitpacked record
  READ_LCL :bit8;
  READ_HUB :bit8;
  READ_PRI :bit8;
  LCL_PRI  :bit1;
  HUB_PRI  :bit1;
  RESERVED0:bit6;
 end;

 TMC_CITF_CREDITS_ARB_WR=bitpacked record
  WRITE_LCL:bit8;
  WRITE_HUB:bit8;
  WRITE_PRI:bit8;
  HUB_PRI  :bit1;
  LCL_PRI  :bit1;
  RESERVED0:bit6;
 end;

 TMC_CITF_INT_CREDITS_WR=bitpacked record
  CNTR_WR_HUB:bit6;
  CNTR_WR_LCL:bit6;
  RESERVED0  :bit20;
 end;

 TMC_CITF_PERFCOUNTER_HI=bitpacked record
  COUNTER_HI   :bit16;
  COMPARE_VALUE:bit16;
 end;

 TMC_CITF_PERFCOUNTER_LO=bit32;

 TMC_CITF_PERF_MON_CNTL2=bitpacked record
  CID      :bit9;
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit1;
  RESERVED4:bit1;
  RESERVED5:bit18;
 end;

 TMC_CITF_PERF_MON_RSLT2=bitpacked record
  RESERVED0    :bit1;
  CB_RD_BUSY   :bit1;
  DB_RD_BUSY   :bit1;
  TC0_RD_BUSY  :bit1;
  VC0_RD_BUSY  :bit1;
  TC1_RD_BUSY  :bit1;
  VC1_RD_BUSY  :bit1;
  CB_WR_BUSY   :bit1;
  DB_WR_BUSY   :bit1;
  SX_WR_BUSY   :bit1;
  TC2_RD_BUSY  :bit1;
  TC0_WR_BUSY  :bit1;
  TC1_WR_BUSY  :bit1;
  TC2_WR_BUSY  :bit1;
  TC0_ATOM_BUSY:bit1;
  TC1_ATOM_BUSY:bit1;
  TC2_ATOM_BUSY:bit1;
  CB_ATOM_BUSY :bit1;
  DB_ATOM_BUSY :bit1;
  RESERVED1    :bit13;
 end;

 TMC_FUS_ARB_GARLIC_CNTL=bitpacked record
  RX_RDRESP_FIFO_PTR_INIT_VALUE:bit8;
  RX_WRRESP_FIFO_PTR_INIT_VALUE:bit7;
  EN_64_BYTE_WRITE             :bit1;
  EDC_RESPONSE_ENABLE          :bit1;
  OUTSTANDING_RDRESP_LIMIT     :bit9;
  OUTSTANDING_WRRESP_LIMIT     :bit6;
 end;

 TMC_FUS_DRAM0_CTL_LIMIT=bitpacked record
  DCTLIMITADDR :bit21;
  DRAMHOLEVALID:bit1;
  RESERVED0    :bit10;
 end;

 TMC_FUS_DRAM1_CTL_LIMIT=bitpacked record
  DCTLIMITADDR :bit21;
  DRAMHOLEVALID:bit1;
  RESERVED0    :bit10;
 end;

 TMC_GRUB_PERFCOUNTER_HI=bitpacked record
  COUNTER_HI   :bit16;
  COMPARE_VALUE:bit16;
 end;

 TMC_GRUB_PERFCOUNTER_LO=bit32;

 TMC_HUB_SHARED_DAGB_DLY=bitpacked record
  DLY      :bit6;
  RESERVED0:bit10;
  CLI      :bit6;
  RESERVED1:bit2;
  POS      :bit5;
  RESERVED2:bit3;
 end;

 TMC_HUB_WDP_BYPASS_GBL0=bitpacked record
  ENABLE           :bit1;
  CID1             :bit8;
  CID2             :bit8;
  HDP_PRIORITY_TIME:bit7;
  OTH_PRIORITY_TIME:bit7;
  RESERVED0        :bit1;
 end;

 TMC_HUB_WDP_BYPASS_GBL1=bitpacked record
  ENABLE           :bit1;
  CID1             :bit8;
  CID2             :bit8;
  HDP_PRIORITY_TIME:bit7;
  OTH_PRIORITY_TIME:bit7;
  RESERVED0        :bit1;
 end;

 TMC_IO_RXCNTL1_DPHY0_D0=bitpacked record
  VREFCAL1_MSB:bit4;
  VREFCAL2_MSB:bit4;
  VREFCAL3    :bit8;
  VREFSEL2    :bit1;
  VREFSEL3    :bit1;
  VREFPDNB_1  :bit1;
  RESERVED0   :bit1;
  RESERVED1   :bit1;
  RESERVED2   :bit1;
  RESERVED3   :bit1;
  RESERVED4   :bit1;
  RESERVED5   :bit1;
  PMD_LOOPBACK:bit3;
  DLL_RSV     :bit4;
 end;

 TMC_IO_RXCNTL1_DPHY0_D1=bitpacked record
  VREFCAL1_MSB:bit4;
  VREFCAL2_MSB:bit4;
  VREFCAL3    :bit8;
  VREFSEL2    :bit1;
  VREFSEL3    :bit1;
  VREFPDNB_1  :bit1;
  RESERVED0   :bit1;
  RESERVED1   :bit1;
  RESERVED2   :bit1;
  RESERVED3   :bit1;
  RESERVED4   :bit1;
  RESERVED5   :bit1;
  PMD_LOOPBACK:bit3;
  DLL_RSV     :bit4;
 end;

 TMC_IO_RXCNTL1_DPHY1_D0=bitpacked record
  VREFCAL1_MSB:bit4;
  VREFCAL2_MSB:bit4;
  VREFCAL3    :bit8;
  VREFSEL2    :bit1;
  VREFSEL3    :bit1;
  VREFPDNB_1  :bit1;
  RESERVED0   :bit1;
  RESERVED1   :bit1;
  RESERVED2   :bit1;
  RESERVED3   :bit1;
  RESERVED4   :bit1;
  RESERVED5   :bit1;
  PMD_LOOPBACK:bit3;
  DLL_RSV     :bit4;
 end;

 TMC_IO_RXCNTL1_DPHY1_D1=bitpacked record
  VREFCAL1_MSB:bit4;
  VREFCAL2_MSB:bit4;
  VREFCAL3    :bit8;
  VREFSEL2    :bit1;
  VREFSEL3    :bit1;
  VREFPDNB_1  :bit1;
  RESERVED0   :bit1;
  RESERVED1   :bit1;
  RESERVED2   :bit1;
  RESERVED3   :bit1;
  RESERVED4   :bit1;
  RESERVED5   :bit1;
  PMD_LOOPBACK:bit3;
  DLL_RSV     :bit4;
 end;

 TMC_RPB_WR_COMBINE_CNTL=bitpacked record
  WC_ENABLE         :bit1;
  WC_MAX_PACKET_SIZE:bit2;
  WC_FLUSH_TIMER    :bit4;
  WC_ALIGN          :bit1;
  RESERVED0         :bit24;
 end;

 TMC_SEQ_MISC_TIMING2_LP=bitpacked record
  PA2RDATA :bit3;
  PA2WDATA :bit3;
  FAW      :bit5;
  RESERVED0:bit3;
  RESERVED1:bit3;
  RESERVED2:bit4;
  TWDATATR :bit4;
  RESERVED3:bit7;
 end;

 TMC_VM_MB_L1_TLB0_DEBUG=bitpacked record
  INVALIDATE_L1_TLB      :bit1;
  RESERVED0              :bit7;
  SEND_FREE_AT_RTN       :bit1;
  EFFECTIVE_L1_TLB_SIZE  :bit3;
  EFFECTIVE_L1_QUEUE_SIZE:bit3;
  L1_TLB_DEBUG           :bit4;
  L1_TLB_FORCE_MISS      :bit1;
  RESERVED1              :bit12;
 end;

 TMC_VM_MB_L1_TLB1_DEBUG=bitpacked record
  INVALIDATE_L1_TLB      :bit1;
  RESERVED0              :bit7;
  SEND_FREE_AT_RTN       :bit1;
  EFFECTIVE_L1_TLB_SIZE  :bit3;
  EFFECTIVE_L1_QUEUE_SIZE:bit3;
  L1_TLB_DEBUG           :bit4;
  L1_TLB_FORCE_MISS      :bit1;
  RESERVED1              :bit12;
 end;

 TMC_VM_MB_L1_TLB2_DEBUG=bitpacked record
  INVALIDATE_L1_TLB      :bit1;
  RESERVED0              :bit7;
  SEND_FREE_AT_RTN       :bit1;
  EFFECTIVE_L1_TLB_SIZE  :bit3;
  EFFECTIVE_L1_QUEUE_SIZE:bit3;
  L1_TLB_DEBUG           :bit4;
  L1_TLB_FORCE_MISS      :bit1;
  RESERVED1              :bit12;
 end;

 TMC_VM_MB_L1_TLB3_DEBUG=bitpacked record
  INVALIDATE_L1_TLB      :bit1;
  RESERVED0              :bit7;
  SEND_FREE_AT_RTN       :bit1;
  EFFECTIVE_L1_TLB_SIZE  :bit3;
  EFFECTIVE_L1_QUEUE_SIZE:bit3;
  L1_TLB_DEBUG           :bit4;
  L1_TLB_FORCE_MISS      :bit1;
  RESERVED1              :bit12;
 end;

 TMC_VM_MB_L1_TLS0_CNTL0=bitpacked record
  REQ_STREAM_ID:bit9;
  RESERVED0    :bit3;
  EN           :bit1;
  PREFETCH_DONE:bit1;
  RESERVED1    :bit18;
 end;

 TMC_VM_MB_L1_TLS0_CNTL1=bitpacked record
  REQ_STREAM_ID:bit9;
  RESERVED0    :bit3;
  EN           :bit1;
  PREFETCH_DONE:bit1;
  RESERVED1    :bit18;
 end;

 TMC_VM_MB_L1_TLS0_CNTL2=bitpacked record
  REQ_STREAM_ID:bit9;
  RESERVED0    :bit3;
  EN           :bit1;
  PREFETCH_DONE:bit1;
  RESERVED1    :bit18;
 end;

 TMC_VM_MB_L1_TLS0_CNTL3=bitpacked record
  REQ_STREAM_ID:bit9;
  RESERVED0    :bit3;
  EN           :bit1;
  PREFETCH_DONE:bit1;
  RESERVED1    :bit18;
 end;

 TMC_VM_MB_L1_TLS0_CNTL4=bitpacked record
  REQ_STREAM_ID:bit9;
  RESERVED0    :bit3;
  EN           :bit1;
  PREFETCH_DONE:bit1;
  RESERVED1    :bit18;
 end;

 TMC_VM_MB_L1_TLS0_CNTL5=bitpacked record
  REQ_STREAM_ID:bit9;
  RESERVED0    :bit3;
  EN           :bit1;
  PREFETCH_DONE:bit1;
  RESERVED1    :bit18;
 end;

 TMC_VM_MB_L1_TLS0_CNTL6=bitpacked record
  REQ_STREAM_ID:bit9;
  RESERVED0    :bit3;
  EN           :bit1;
  PREFETCH_DONE:bit1;
  RESERVED1    :bit18;
 end;

 TMC_VM_MB_L1_TLS0_CNTL7=bitpacked record
  REQ_STREAM_ID:bit9;
  RESERVED0    :bit3;
  EN           :bit1;
  PREFETCH_DONE:bit1;
  RESERVED1    :bit18;
 end;

 TMC_VM_MB_L1_TLS0_CNTL8=bitpacked record
  REQ_STREAM_ID:bit9;
  RESERVED0    :bit3;
  EN           :bit1;
  PREFETCH_DONE:bit1;
  RESERVED1    :bit18;
 end;

 TMC_VM_MD_L1_TLB0_DEBUG=bitpacked record
  INVALIDATE_L1_TLB      :bit1;
  RESERVED0              :bit7;
  SEND_FREE_AT_RTN       :bit1;
  EFFECTIVE_L1_TLB_SIZE  :bit3;
  EFFECTIVE_L1_QUEUE_SIZE:bit3;
  L1_TLB_DEBUG           :bit4;
  L1_TLB_FORCE_MISS      :bit1;
  RESERVED1              :bit12;
 end;

 TMC_VM_MD_L1_TLB1_DEBUG=bitpacked record
  INVALIDATE_L1_TLB      :bit1;
  RESERVED0              :bit7;
  SEND_FREE_AT_RTN       :bit1;
  EFFECTIVE_L1_TLB_SIZE  :bit3;
  EFFECTIVE_L1_QUEUE_SIZE:bit3;
  L1_TLB_DEBUG           :bit4;
  L1_TLB_FORCE_MISS      :bit1;
  RESERVED1              :bit12;
 end;

 TMC_VM_MD_L1_TLB2_DEBUG=bitpacked record
  INVALIDATE_L1_TLB      :bit1;
  RESERVED0              :bit7;
  SEND_FREE_AT_RTN       :bit1;
  EFFECTIVE_L1_TLB_SIZE  :bit3;
  EFFECTIVE_L1_QUEUE_SIZE:bit3;
  L1_TLB_DEBUG           :bit4;
  L1_TLB_FORCE_MISS      :bit1;
  RESERVED1              :bit12;
 end;

 TMC_VM_MD_L1_TLB3_DEBUG=bitpacked record
  INVALIDATE_L1_TLB      :bit1;
  RESERVED0              :bit7;
  SEND_FREE_AT_RTN       :bit1;
  EFFECTIVE_L1_TLB_SIZE  :bit3;
  EFFECTIVE_L1_QUEUE_SIZE:bit3;
  L1_TLB_DEBUG           :bit4;
  L1_TLB_FORCE_MISS      :bit1;
  RESERVED1              :bit12;
 end;

 TMC_XBAR_FIFO_MON_CNTL0=bitpacked record
  START_THRESH:bit12;
  STOP_THRESH :bit12;
  START_MODE  :bit2;
  STOP_MODE   :bit2;
  ALLOW_WRAP  :bit1;
  RESERVED0   :bit3;
 end;

 TMC_XBAR_FIFO_MON_CNTL1=bitpacked record
  THRESH_CNTR_ID:bit8;
  START_TRIG_ID :bit8;
  STOP_TRIG_ID  :bit8;
  RESERVED0     :bit8;
 end;

 TMC_XBAR_FIFO_MON_CNTL2=bitpacked record
  MON0_ID:bit8;
  MON1_ID:bit8;
  MON2_ID:bit8;
  MON3_ID:bit8;
 end;

 TMC_XBAR_FIFO_MON_RSLT0=bit32;

 TMC_XBAR_FIFO_MON_RSLT1=bit32;

 TMC_XBAR_FIFO_MON_RSLT2=bit32;

 TMC_XBAR_FIFO_MON_RSLT3=bit32;

 TMVP_AFR_FLIP_FIFO_CNTL=bitpacked record
  MVP_AFR_FLIP_FIFO_NUM_ENTRIES:bit4;
  MVP_AFR_FLIP_FIFO_RESET      :bit1;
  RESERVED0                    :bit3;
  MVP_AFR_FLIP_FIFO_RESET_FLAG :bit1;
  RESERVED1                    :bit3;
  MVP_AFR_FLIP_FIFO_RESET_ACK  :bit1;
  RESERVED2                    :bit19;
 end;

 TOUT_CLAMP_CONTROL_B_CB=bitpacked record
  OUT_CLAMP_MAX_B_CB:bit14;
  RESERVED0         :bit2;
  OUT_CLAMP_MIN_B_CB:bit14;
  RESERVED1         :bit2;
 end;

 TOUT_CLAMP_CONTROL_R_CR=bitpacked record
  OUT_CLAMP_MAX_R_CR:bit14;
  RESERVED0         :bit2;
  OUT_CLAMP_MIN_R_CR:bit14;
  RESERVED1         :bit2;
 end;

 TOVLSCL_EDGE_PIXEL_CNTL=bitpacked record
  OVLSCL_BLACK_COLOR_BCB:bit10;
  OVLSCL_BLACK_COLOR_GY :bit10;
  OVLSCL_BLACK_COLOR_RCR:bit10;
  RESERVED0             :bit1;
  OVLSCL_EDGE_PIXEL_SEL :bit1;
 end;

 TPA_CL_GB_HORZ_CLIP_ADJ=bit32;

 TPA_CL_GB_HORZ_DISC_ADJ=bit32;

 TPA_CL_GB_VERT_CLIP_ADJ=bit32;

 TPA_CL_GB_VERT_DISC_ADJ=bit32;

 TPA_CL_VPORT_XOFFSET_10=bit32;

 TPA_CL_VPORT_XOFFSET_11=bit32;

 TPA_CL_VPORT_XOFFSET_12=bit32;

 TPA_CL_VPORT_XOFFSET_13=bit32;

 TPA_CL_VPORT_XOFFSET_14=bit32;

 TPA_CL_VPORT_XOFFSET_15=bit32;

 TPA_CL_VPORT_YOFFSET_10=bit32;

 TPA_CL_VPORT_YOFFSET_11=bit32;

 TPA_CL_VPORT_YOFFSET_12=bit32;

 TPA_CL_VPORT_YOFFSET_13=bit32;

 TPA_CL_VPORT_YOFFSET_14=bit32;

 TPA_CL_VPORT_YOFFSET_15=bit32;

 TPA_CL_VPORT_ZOFFSET_10=bit32;

 TPA_CL_VPORT_ZOFFSET_11=bit32;

 TPA_CL_VPORT_ZOFFSET_12=bit32;

 TPA_CL_VPORT_ZOFFSET_13=bit32;

 TPA_CL_VPORT_ZOFFSET_14=bit32;

 TPA_CL_VPORT_ZOFFSET_15=bit32;

 TPA_SU_PRIM_FILTER_CNTL=bitpacked record
  TRIANGLE_FILTER_DISABLE :bit1;
  LINE_FILTER_DISABLE     :bit1;
  POINT_FILTER_DISABLE    :bit1;
  RECTANGLE_FILTER_DISABLE:bit1;
  TRIANGLE_EXPAND_ENA     :bit1;
  LINE_EXPAND_ENA         :bit1;
  POINT_EXPAND_ENA        :bit1;
  RECTANGLE_EXPAND_ENA    :bit1;
  PRIM_EXPAND_CONSTANT    :bit8;
  RESERVED0               :bit14;
  XMAX_RIGHT_EXCLUSION    :bit1;
  YMAX_BOTTOM_EXCLUSION   :bit1;
 end;

 TPB0_PIF_BIF_CMD_STATUS=bitpacked record
  TXPHYSTATUS_0:bit1;
  TXPHYSTATUS_1:bit1;
  TXPHYSTATUS_2:bit1;
  TXPHYSTATUS_3:bit1;
  TXPHYSTATUS_4:bit1;
  TXPHYSTATUS_5:bit1;
  TXPHYSTATUS_6:bit1;
  TXPHYSTATUS_7:bit1;
  RESERVED0    :bit1;
  RESERVED1    :bit1;
  RESERVED2    :bit1;
  RESERVED3    :bit1;
  RESERVED4    :bit1;
  RESERVED5    :bit1;
  RESERVED6    :bit1;
  RESERVED7    :bit1;
  RXPHYSTATUS_0:bit1;
  RXPHYSTATUS_1:bit1;
  RXPHYSTATUS_2:bit1;
  RXPHYSTATUS_3:bit1;
  RXPHYSTATUS_4:bit1;
  RXPHYSTATUS_5:bit1;
  RXPHYSTATUS_6:bit1;
  RXPHYSTATUS_7:bit1;
  RESERVED8    :bit1;
  RESERVED9    :bit1;
  RESERVED10   :bit1;
  RESERVED11   :bit1;
  RESERVED12   :bit1;
  RESERVED13   :bit1;
  RESERVED14   :bit1;
  RESERVED15   :bit1;
 end;

 TPB0_RX_LANE0_CTRL_REG0=bitpacked record
  RX_BACKUP_0        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_0:bit2;
  RX_TST_BSCAN_EN_0  :bit1;
  RX_CFG_OVR_PWRSF_0 :bit1;
  RX_TERM_EN_0       :bit1;
  RESERVED1          :bit17;
 end;

 TPB0_RX_LANE1_CTRL_REG0=bitpacked record
  RX_BACKUP_1        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_1:bit2;
  RX_TST_BSCAN_EN_1  :bit1;
  RX_CFG_OVR_PWRSF_1 :bit1;
  RX_TERM_EN_1       :bit1;
  RESERVED1          :bit17;
 end;

 TPB0_RX_LANE2_CTRL_REG0=bitpacked record
  RX_BACKUP_2        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_2:bit2;
  RX_TST_BSCAN_EN_2  :bit1;
  RX_CFG_OVR_PWRSF_2 :bit1;
  RX_TERM_EN_2       :bit1;
  RESERVED1          :bit17;
 end;

 TPB0_RX_LANE3_CTRL_REG0=bitpacked record
  RX_BACKUP_3        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_3:bit2;
  RX_TST_BSCAN_EN_3  :bit1;
  RX_CFG_OVR_PWRSF_3 :bit1;
  RX_TERM_EN_3       :bit1;
  RESERVED1          :bit17;
 end;

 TPB0_RX_LANE4_CTRL_REG0=bitpacked record
  RX_BACKUP_4        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_4:bit2;
  RX_TST_BSCAN_EN_4  :bit1;
  RX_CFG_OVR_PWRSF_4 :bit1;
  RX_TERM_EN_4       :bit1;
  RESERVED1          :bit17;
 end;

 TPB0_RX_LANE5_CTRL_REG0=bitpacked record
  RX_BACKUP_5        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_5:bit2;
  RX_TST_BSCAN_EN_5  :bit1;
  RX_CFG_OVR_PWRSF_5 :bit1;
  RX_TERM_EN_5       :bit1;
  RESERVED1          :bit17;
 end;

 TPB0_RX_LANE6_CTRL_REG0=bitpacked record
  RX_BACKUP_6        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_6:bit2;
  RX_TST_BSCAN_EN_6  :bit1;
  RX_CFG_OVR_PWRSF_6 :bit1;
  RX_TERM_EN_6       :bit1;
  RESERVED1          :bit17;
 end;

 TPB0_RX_LANE7_CTRL_REG0=bitpacked record
  RX_BACKUP_7        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_7:bit2;
  RX_TST_BSCAN_EN_7  :bit1;
  RX_CFG_OVR_PWRSF_7 :bit1;
  RX_TERM_EN_7       :bit1;
  RESERVED1          :bit17;
 end;

 TPB0_RX_LANE8_CTRL_REG0=bitpacked record
  RX_BACKUP_8        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_8:bit2;
  RX_TST_BSCAN_EN_8  :bit1;
  RX_CFG_OVR_PWRSF_8 :bit1;
  RX_TERM_EN_8       :bit1;
  RESERVED1          :bit17;
 end;

 TPB0_RX_LANE9_CTRL_REG0=bitpacked record
  RX_BACKUP_9        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_9:bit2;
  RX_TST_BSCAN_EN_9  :bit1;
  RX_CFG_OVR_PWRSF_9 :bit1;
  RX_TERM_EN_9       :bit1;
  RESERVED1          :bit17;
 end;

 TPB0_TX_LANE0_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_0  :bit1;
  TX_CFG_INV_DATA_0      :bit1;
  TX_CFG_SWING_BOOST_EN_0:bit1;
  TX_DBG_PRBS_EN_0       :bit1;
  RESERVED0              :bit28;
 end;

 TPB0_TX_LANE0_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_0       :bit1;
  TX_DCLK_EN_OVRD_EN_0        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_0   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_0    :bit1;
  TX_DRV_PWRON_OVRD_VAL_0     :bit1;
  TX_DRV_PWRON_OVRD_EN_0      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_0:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_0 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB0_TX_LANE1_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_1  :bit1;
  TX_CFG_INV_DATA_1      :bit1;
  TX_CFG_SWING_BOOST_EN_1:bit1;
  TX_DBG_PRBS_EN_1       :bit1;
  RESERVED0              :bit28;
 end;

 TPB0_TX_LANE1_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_1       :bit1;
  TX_DCLK_EN_OVRD_EN_1        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_1   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_1    :bit1;
  TX_DRV_PWRON_OVRD_VAL_1     :bit1;
  TX_DRV_PWRON_OVRD_EN_1      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_1:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_1 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB0_TX_LANE2_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_2  :bit1;
  TX_CFG_INV_DATA_2      :bit1;
  TX_CFG_SWING_BOOST_EN_2:bit1;
  TX_DBG_PRBS_EN_2       :bit1;
  RESERVED0              :bit28;
 end;

 TPB0_TX_LANE2_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_2       :bit1;
  TX_DCLK_EN_OVRD_EN_2        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_2   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_2    :bit1;
  TX_DRV_PWRON_OVRD_VAL_2     :bit1;
  TX_DRV_PWRON_OVRD_EN_2      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_2:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_2 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB0_TX_LANE3_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_3  :bit1;
  TX_CFG_INV_DATA_3      :bit1;
  TX_CFG_SWING_BOOST_EN_3:bit1;
  TX_DBG_PRBS_EN_3       :bit1;
  RESERVED0              :bit28;
 end;

 TPB0_TX_LANE3_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_3       :bit1;
  TX_DCLK_EN_OVRD_EN_3        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_3   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_3    :bit1;
  TX_DRV_PWRON_OVRD_VAL_3     :bit1;
  TX_DRV_PWRON_OVRD_EN_3      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_3:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_3 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB0_TX_LANE4_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_4  :bit1;
  TX_CFG_INV_DATA_4      :bit1;
  TX_CFG_SWING_BOOST_EN_4:bit1;
  TX_DBG_PRBS_EN_4       :bit1;
  RESERVED0              :bit28;
 end;

 TPB0_TX_LANE4_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_4       :bit1;
  TX_DCLK_EN_OVRD_EN_4        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_4   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_4    :bit1;
  TX_DRV_PWRON_OVRD_VAL_4     :bit1;
  TX_DRV_PWRON_OVRD_EN_4      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_4:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_4 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB0_TX_LANE5_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_5  :bit1;
  TX_CFG_INV_DATA_5      :bit1;
  TX_CFG_SWING_BOOST_EN_5:bit1;
  TX_DBG_PRBS_EN_5       :bit1;
  RESERVED0              :bit28;
 end;

 TPB0_TX_LANE5_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_5       :bit1;
  TX_DCLK_EN_OVRD_EN_5        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_5   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_5    :bit1;
  TX_DRV_PWRON_OVRD_VAL_5     :bit1;
  TX_DRV_PWRON_OVRD_EN_5      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_5:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_5 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB0_TX_LANE6_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_6  :bit1;
  TX_CFG_INV_DATA_6      :bit1;
  TX_CFG_SWING_BOOST_EN_6:bit1;
  TX_DBG_PRBS_EN_6       :bit1;
  RESERVED0              :bit28;
 end;

 TPB0_TX_LANE6_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_6       :bit1;
  TX_DCLK_EN_OVRD_EN_6        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_6   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_6    :bit1;
  TX_DRV_PWRON_OVRD_VAL_6     :bit1;
  TX_DRV_PWRON_OVRD_EN_6      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_6:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_6 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB0_TX_LANE7_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_7  :bit1;
  TX_CFG_INV_DATA_7      :bit1;
  TX_CFG_SWING_BOOST_EN_7:bit1;
  TX_DBG_PRBS_EN_7       :bit1;
  RESERVED0              :bit28;
 end;

 TPB0_TX_LANE7_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_7       :bit1;
  TX_DCLK_EN_OVRD_EN_7        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_7   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_7    :bit1;
  TX_DRV_PWRON_OVRD_VAL_7     :bit1;
  TX_DRV_PWRON_OVRD_EN_7      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_7:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_7 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB0_TX_LANE8_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_8  :bit1;
  TX_CFG_INV_DATA_8      :bit1;
  TX_CFG_SWING_BOOST_EN_8:bit1;
  TX_DBG_PRBS_EN_8       :bit1;
  RESERVED0              :bit28;
 end;

 TPB0_TX_LANE8_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_8       :bit1;
  TX_DCLK_EN_OVRD_EN_8        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_8   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_8    :bit1;
  TX_DRV_PWRON_OVRD_VAL_8     :bit1;
  TX_DRV_PWRON_OVRD_EN_8      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_8:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_8 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB0_TX_LANE9_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_9  :bit1;
  TX_CFG_INV_DATA_9      :bit1;
  TX_CFG_SWING_BOOST_EN_9:bit1;
  TX_DBG_PRBS_EN_9       :bit1;
  RESERVED0              :bit28;
 end;

 TPB0_TX_LANE9_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_9       :bit1;
  TX_DCLK_EN_OVRD_EN_9        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_9   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_9    :bit1;
  TX_DRV_PWRON_OVRD_VAL_9     :bit1;
  TX_DRV_PWRON_OVRD_EN_9      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_9:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_9 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB1_PIF_BIF_CMD_STATUS=bitpacked record
  TXPHYSTATUS_0:bit1;
  TXPHYSTATUS_1:bit1;
  TXPHYSTATUS_2:bit1;
  TXPHYSTATUS_3:bit1;
  TXPHYSTATUS_4:bit1;
  TXPHYSTATUS_5:bit1;
  TXPHYSTATUS_6:bit1;
  TXPHYSTATUS_7:bit1;
  RESERVED0    :bit1;
  RESERVED1    :bit1;
  RESERVED2    :bit1;
  RESERVED3    :bit1;
  RESERVED4    :bit1;
  RESERVED5    :bit1;
  RESERVED6    :bit1;
  RESERVED7    :bit1;
  RXPHYSTATUS_0:bit1;
  RXPHYSTATUS_1:bit1;
  RXPHYSTATUS_2:bit1;
  RXPHYSTATUS_3:bit1;
  RXPHYSTATUS_4:bit1;
  RXPHYSTATUS_5:bit1;
  RXPHYSTATUS_6:bit1;
  RXPHYSTATUS_7:bit1;
  RESERVED8    :bit1;
  RESERVED9    :bit1;
  RESERVED10   :bit1;
  RESERVED11   :bit1;
  RESERVED12   :bit1;
  RESERVED13   :bit1;
  RESERVED14   :bit1;
  RESERVED15   :bit1;
 end;

 TPB1_RX_LANE0_CTRL_REG0=bitpacked record
  RX_BACKUP_0        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_0:bit2;
  RX_TST_BSCAN_EN_0  :bit1;
  RX_CFG_OVR_PWRSF_0 :bit1;
  RX_TERM_EN_0       :bit1;
  RESERVED1          :bit17;
 end;

 TPB1_RX_LANE1_CTRL_REG0=bitpacked record
  RX_BACKUP_1        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_1:bit2;
  RX_TST_BSCAN_EN_1  :bit1;
  RX_CFG_OVR_PWRSF_1 :bit1;
  RX_TERM_EN_1       :bit1;
  RESERVED1          :bit17;
 end;

 TPB1_RX_LANE2_CTRL_REG0=bitpacked record
  RX_BACKUP_2        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_2:bit2;
  RX_TST_BSCAN_EN_2  :bit1;
  RX_CFG_OVR_PWRSF_2 :bit1;
  RX_TERM_EN_2       :bit1;
  RESERVED1          :bit17;
 end;

 TPB1_RX_LANE3_CTRL_REG0=bitpacked record
  RX_BACKUP_3        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_3:bit2;
  RX_TST_BSCAN_EN_3  :bit1;
  RX_CFG_OVR_PWRSF_3 :bit1;
  RX_TERM_EN_3       :bit1;
  RESERVED1          :bit17;
 end;

 TPB1_RX_LANE4_CTRL_REG0=bitpacked record
  RX_BACKUP_4        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_4:bit2;
  RX_TST_BSCAN_EN_4  :bit1;
  RX_CFG_OVR_PWRSF_4 :bit1;
  RX_TERM_EN_4       :bit1;
  RESERVED1          :bit17;
 end;

 TPB1_RX_LANE5_CTRL_REG0=bitpacked record
  RX_BACKUP_5        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_5:bit2;
  RX_TST_BSCAN_EN_5  :bit1;
  RX_CFG_OVR_PWRSF_5 :bit1;
  RX_TERM_EN_5       :bit1;
  RESERVED1          :bit17;
 end;

 TPB1_RX_LANE6_CTRL_REG0=bitpacked record
  RX_BACKUP_6        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_6:bit2;
  RX_TST_BSCAN_EN_6  :bit1;
  RX_CFG_OVR_PWRSF_6 :bit1;
  RX_TERM_EN_6       :bit1;
  RESERVED1          :bit17;
 end;

 TPB1_RX_LANE7_CTRL_REG0=bitpacked record
  RX_BACKUP_7        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_7:bit2;
  RX_TST_BSCAN_EN_7  :bit1;
  RX_CFG_OVR_PWRSF_7 :bit1;
  RX_TERM_EN_7       :bit1;
  RESERVED1          :bit17;
 end;

 TPB1_RX_LANE8_CTRL_REG0=bitpacked record
  RX_BACKUP_8        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_8:bit2;
  RX_TST_BSCAN_EN_8  :bit1;
  RX_CFG_OVR_PWRSF_8 :bit1;
  RX_TERM_EN_8       :bit1;
  RESERVED1          :bit17;
 end;

 TPB1_RX_LANE9_CTRL_REG0=bitpacked record
  RX_BACKUP_9        :bit8;
  RESERVED0          :bit2;
  RX_DBG_ANALOG_SEL_9:bit2;
  RX_TST_BSCAN_EN_9  :bit1;
  RX_CFG_OVR_PWRSF_9 :bit1;
  RX_TERM_EN_9       :bit1;
  RESERVED1          :bit17;
 end;

 TPB1_TX_LANE0_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_0  :bit1;
  TX_CFG_INV_DATA_0      :bit1;
  TX_CFG_SWING_BOOST_EN_0:bit1;
  TX_DBG_PRBS_EN_0       :bit1;
  RESERVED0              :bit28;
 end;

 TPB1_TX_LANE0_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_0       :bit1;
  TX_DCLK_EN_OVRD_EN_0        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_0   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_0    :bit1;
  TX_DRV_PWRON_OVRD_VAL_0     :bit1;
  TX_DRV_PWRON_OVRD_EN_0      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_0:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_0 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB1_TX_LANE1_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_1  :bit1;
  TX_CFG_INV_DATA_1      :bit1;
  TX_CFG_SWING_BOOST_EN_1:bit1;
  TX_DBG_PRBS_EN_1       :bit1;
  RESERVED0              :bit28;
 end;

 TPB1_TX_LANE1_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_1       :bit1;
  TX_DCLK_EN_OVRD_EN_1        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_1   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_1    :bit1;
  TX_DRV_PWRON_OVRD_VAL_1     :bit1;
  TX_DRV_PWRON_OVRD_EN_1      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_1:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_1 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB1_TX_LANE2_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_2  :bit1;
  TX_CFG_INV_DATA_2      :bit1;
  TX_CFG_SWING_BOOST_EN_2:bit1;
  TX_DBG_PRBS_EN_2       :bit1;
  RESERVED0              :bit28;
 end;

 TPB1_TX_LANE2_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_2       :bit1;
  TX_DCLK_EN_OVRD_EN_2        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_2   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_2    :bit1;
  TX_DRV_PWRON_OVRD_VAL_2     :bit1;
  TX_DRV_PWRON_OVRD_EN_2      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_2:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_2 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB1_TX_LANE3_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_3  :bit1;
  TX_CFG_INV_DATA_3      :bit1;
  TX_CFG_SWING_BOOST_EN_3:bit1;
  TX_DBG_PRBS_EN_3       :bit1;
  RESERVED0              :bit28;
 end;

 TPB1_TX_LANE3_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_3       :bit1;
  TX_DCLK_EN_OVRD_EN_3        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_3   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_3    :bit1;
  TX_DRV_PWRON_OVRD_VAL_3     :bit1;
  TX_DRV_PWRON_OVRD_EN_3      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_3:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_3 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB1_TX_LANE4_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_4  :bit1;
  TX_CFG_INV_DATA_4      :bit1;
  TX_CFG_SWING_BOOST_EN_4:bit1;
  TX_DBG_PRBS_EN_4       :bit1;
  RESERVED0              :bit28;
 end;

 TPB1_TX_LANE4_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_4       :bit1;
  TX_DCLK_EN_OVRD_EN_4        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_4   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_4    :bit1;
  TX_DRV_PWRON_OVRD_VAL_4     :bit1;
  TX_DRV_PWRON_OVRD_EN_4      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_4:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_4 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB1_TX_LANE5_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_5  :bit1;
  TX_CFG_INV_DATA_5      :bit1;
  TX_CFG_SWING_BOOST_EN_5:bit1;
  TX_DBG_PRBS_EN_5       :bit1;
  RESERVED0              :bit28;
 end;

 TPB1_TX_LANE5_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_5       :bit1;
  TX_DCLK_EN_OVRD_EN_5        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_5   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_5    :bit1;
  TX_DRV_PWRON_OVRD_VAL_5     :bit1;
  TX_DRV_PWRON_OVRD_EN_5      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_5:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_5 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB1_TX_LANE6_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_6  :bit1;
  TX_CFG_INV_DATA_6      :bit1;
  TX_CFG_SWING_BOOST_EN_6:bit1;
  TX_DBG_PRBS_EN_6       :bit1;
  RESERVED0              :bit28;
 end;

 TPB1_TX_LANE6_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_6       :bit1;
  TX_DCLK_EN_OVRD_EN_6        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_6   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_6    :bit1;
  TX_DRV_PWRON_OVRD_VAL_6     :bit1;
  TX_DRV_PWRON_OVRD_EN_6      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_6:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_6 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB1_TX_LANE7_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_7  :bit1;
  TX_CFG_INV_DATA_7      :bit1;
  TX_CFG_SWING_BOOST_EN_7:bit1;
  TX_DBG_PRBS_EN_7       :bit1;
  RESERVED0              :bit28;
 end;

 TPB1_TX_LANE7_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_7       :bit1;
  TX_DCLK_EN_OVRD_EN_7        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_7   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_7    :bit1;
  TX_DRV_PWRON_OVRD_VAL_7     :bit1;
  TX_DRV_PWRON_OVRD_EN_7      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_7:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_7 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB1_TX_LANE8_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_8  :bit1;
  TX_CFG_INV_DATA_8      :bit1;
  TX_CFG_SWING_BOOST_EN_8:bit1;
  TX_DBG_PRBS_EN_8       :bit1;
  RESERVED0              :bit28;
 end;

 TPB1_TX_LANE8_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_8       :bit1;
  TX_DCLK_EN_OVRD_EN_8        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_8   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_8    :bit1;
  TX_DRV_PWRON_OVRD_VAL_8     :bit1;
  TX_DRV_PWRON_OVRD_EN_8      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_8:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_8 :bit1;
  RESERVED0                   :bit24;
 end;

 TPB1_TX_LANE9_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_9  :bit1;
  TX_CFG_INV_DATA_9      :bit1;
  TX_CFG_SWING_BOOST_EN_9:bit1;
  TX_DBG_PRBS_EN_9       :bit1;
  RESERVED0              :bit28;
 end;

 TPB1_TX_LANE9_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_9       :bit1;
  TX_DCLK_EN_OVRD_EN_9        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_9   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_9    :bit1;
  TX_DRV_PWRON_OVRD_VAL_9     :bit1;
  TX_DRV_PWRON_OVRD_EN_9      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_9:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_9 :bit1;
  RESERVED0                   :bit24;
 end;

 TPCIE_LANE_ERROR_STATUS=bitpacked record
  LANE_ERROR_STATUS_BITS:bit16;
  RESERVED0             :bit16;
 end;

 TPCIE_LC_BW_CHANGE_CNTL=bitpacked record
  LC_BW_CHANGE_INT_EN                :bit1;
  LC_HW_INIT_SPEED_CHANGE            :bit1;
  LC_SW_INIT_SPEED_CHANGE            :bit1;
  LC_OTHER_INIT_SPEED_CHANGE         :bit1;
  LC_RELIABILITY_SPEED_CHANGE        :bit1;
  LC_FAILED_SPEED_NEG                :bit1;
  LC_LONG_LW_CHANGE                  :bit1;
  LC_SHORT_LW_CHANGE                 :bit1;
  LC_LW_CHANGE_OTHER                 :bit1;
  LC_LW_CHANGE_FAILED                :bit1;
  LC_LINK_BW_NOTIFICATION_DETECT_MODE:bit1;
  RESERVED0                          :bit21;
 end;

 TPCIE_PERF_COUNT0_TXCLK=bit32;

 TPCIE_PERF_COUNT1_TXCLK=bit32;

 TPCIE_PRBS_USER_PATTERN=bitpacked record
  PRBS_USER_PATTERN:bit30;
  RESERVED0        :bit2;
 end;

 TPCIE_P_RCV_L0S_FTS_DET=bitpacked record
  P_RCV_L0S_FTS_DET_MIN:bit8;
  P_RCV_L0S_FTS_DET_MAX:bit8;
  RESERVED0            :bit16;
 end;

 TPCIE_SRIOV_INITIAL_VFS=bitpacked record
  SRIOV_INITIAL_VFS:bit16;
  RESERVED0        :bit16;
 end;

 TPCIE_TX_CREDITS_ADVT_P=bitpacked record
  TX_CREDITS_ADVT_PD:bit12;
  RESERVED0         :bit4;
  TX_CREDITS_ADVT_PH:bit8;
  RESERVED1         :bit8;
 end;

 TPCIE_TX_CREDITS_INIT_P=bitpacked record
  TX_CREDITS_INIT_PD:bit12;
  RESERVED0         :bit4;
  TX_CREDITS_INIT_PH:bit8;
  RESERVED1         :bit8;
 end;

 TPCIE_TX_CREDITS_STATUS=bitpacked record
  TX_CREDITS_ERR_PD         :bit1;
  TX_CREDITS_ERR_PH         :bit1;
  TX_CREDITS_ERR_NPD        :bit1;
  TX_CREDITS_ERR_NPH        :bit1;
  TX_CREDITS_ERR_CPLD       :bit1;
  TX_CREDITS_ERR_CPLH       :bit1;
  RESERVED0                 :bit10;
  TX_CREDITS_CUR_STATUS_PD  :bit1;
  TX_CREDITS_CUR_STATUS_PH  :bit1;
  TX_CREDITS_CUR_STATUS_NPD :bit1;
  TX_CREDITS_CUR_STATUS_NPH :bit1;
  TX_CREDITS_CUR_STATUS_CPLD:bit1;
  TX_CREDITS_CUR_STATUS_CPLH:bit1;
  RESERVED1                 :bit10;
 end;

 TPCIE_UNCORR_ERR_STATUS=bitpacked record
  RESERVED0                     :bit4;
  DLP_ERR_STATUS                :bit1;
  SURPDN_ERR_STATUS             :bit1;
  RESERVED1                     :bit6;
  PSN_ERR_STATUS                :bit1;
  FC_ERR_STATUS                 :bit1;
  CPL_TIMEOUT_STATUS            :bit1;
  CPL_ABORT_ERR_STATUS          :bit1;
  UNEXP_CPL_STATUS              :bit1;
  RCV_OVFL_STATUS               :bit1;
  MAL_TLP_STATUS                :bit1;
  ECRC_ERR_STATUS               :bit1;
  UNSUPP_REQ_ERR_STATUS         :bit1;
  ACS_VIOLATION_STATUS          :bit1;
  UNCORR_INT_ERR_STATUS         :bit1;
  MC_BLOCKED_TLP_STATUS         :bit1;
  ATOMICOP_EGRESS_BLOCKED_STATUS:bit1;
  TLP_PREFIX_BLOCKED_ERR_STATUS :bit1;
  RESERVED2                     :bit6;
 end;

 TPCIE_VC0_RESOURCE_CNTL=bitpacked record
  TC_VC_MAP_TC0      :bit1;
  TC_VC_MAP_TC1_7    :bit7;
  RESERVED0          :bit8;
  LOAD_PORT_ARB_TABLE:bit1;
  PORT_ARB_SELECT    :bit3;
  RESERVED1          :bit4;
  VC_ID              :bit3;
  RESERVED2          :bit4;
  VC_ENABLE          :bit1;
 end;

 TPCIE_VC1_RESOURCE_CNTL=bitpacked record
  TC_VC_MAP_TC0      :bit1;
  TC_VC_MAP_TC1_7    :bit7;
  RESERVED0          :bit8;
  LOAD_PORT_ARB_TABLE:bit1;
  PORT_ARB_SELECT    :bit3;
  RESERVED1          :bit4;
  VC_ID              :bit3;
  RESERVED2          :bit4;
  VC_ENABLE          :bit1;
 end;

 TPLL_UNLOCK_DETECT_CNTL=bitpacked record
  PLL_UNLOCK_DETECT_ENABLE         :bit1;
  PLL_UNLOCK_DET_RES100_SELECT     :bit1;
  PLL_UNLOCK_STICKY_STATUS         :bit1;
  RESERVED0                        :bit1;
  PLL_UNLOCK_DET_COUNT             :bit3;
  PLL_UNLOCKED_STICKY_RST_TEST     :bit1;
  PLL_UNLOCKED_STICKY_TEST_READBACK:bit1;
  RESERVED1                        :bit23;
 end;

 TPRESCALE_VALUES_GRPH_B=bitpacked record
  GRPH_PRESCALE_BIAS_B :bit16;
  GRPH_PRESCALE_SCALE_B:bit16;
 end;

 TPRESCALE_VALUES_GRPH_G=bitpacked record
  GRPH_PRESCALE_BIAS_G :bit16;
  GRPH_PRESCALE_SCALE_G:bit16;
 end;

 TPRESCALE_VALUES_GRPH_R=bitpacked record
  GRPH_PRESCALE_BIAS_R :bit16;
  GRPH_PRESCALE_SCALE_R:bit16;
 end;

 TPRESCALE_VALUES_OVL_CB=bitpacked record
  OVL_PRESCALE_BIAS_CB :bit16;
  OVL_PRESCALE_SCALE_CB:bit16;
 end;

 TPRESCALE_VALUES_OVL_CR=bitpacked record
  OVL_PRESCALE_BIAS_CR :bit16;
  OVL_PRESCALE_SCALE_CR:bit16;
 end;

 TPWR_AVFS10_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS11_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS12_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS13_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS14_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS15_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS16_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS17_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS18_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS19_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS20_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS21_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS22_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS23_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS24_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS25_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS26_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_AVFS27_CNTL_STATUS=bitpacked record
  MmDatOut :bit8;
  PsmTdo   :bit1;
  AlarmFlag:bit1;
  RESERVED0:bit22;
 end;

 TPWR_DISP_TIMER_CONTROL=bitpacked record
  DISP_TIMER_INT_COUNT  :bit25;
  DISP_TIMER_INT_ENABLE :bit1;
  DISP_TIMER_INT_DISABLE:bit1;
  DISP_TIMER_INT_MASK   :bit1;
  DISP_TIMER_INT_STAT_AK:bit1;
  DISP_TIMER_INT_TYPE   :bit1;
  DISP_TIMER_INT_MODE   :bit1;
  RESERVED0             :bit1;
 end;

 TREG_ADAPT_pif0_CONTROL=bitpacked record
  ACCESS_MODE_pif0:bit1;
  RESERVED0       :bit31;
 end;

 TRLC_CGTT_MGCG_OVERRIDE=bit32;

 TRLC_GPU_IOV_UCODE_ADDR=bitpacked record
  UCODE_ADDR:bit12;
  RESERVED  :bit20;
 end;

 TRLC_GPU_IOV_UCODE_DATA=bit32;

 TRLC_HYP_GPM_UCODE_ADDR=bitpacked record
  UCODE_ADDR:bit12;
  RESERVED  :bit20;
 end;

 TRLC_HYP_GPM_UCODE_DATA=bit32;

 TRLC_JUMP_TABLE_RESTORE=bit32;

 TRLC_SPM_SE_MUXSEL_ADDR=bit32;

 TRLC_SPM_SE_MUXSEL_DATA=bit32;

 TSCLK_CGTT_BLK_CTRL_REG=bitpacked record
  SCLK_TURN_ON_DELAY :bit4;
  SCLK_TURN_OFF_DELAY:bit8;
  CGTT_SCLK_OVERRIDE :bit1;
  RESERVED0          :bit19;
 end;

 TSCLV_COEF_RAM_TAP_DATA=bitpacked record
  SCL_C_RAM_EVEN_TAP_COEF   :bit14;
  RESERVED0                 :bit1;
  SCL_C_RAM_EVEN_TAP_COEF_EN:bit1;
  SCL_C_RAM_ODD_TAP_COEF    :bit14;
  RESERVED1                 :bit1;
  SCL_C_RAM_ODD_TAP_COEF_EN :bit1;
 end;

 TSDMA0_GFX_CONTEXT_CNTL=bitpacked record
  RESERVED0  :bit16;
  RESUME_CTX :bit1;
  RESERVED1  :bit7;
  SESSION_SEL:bit4;
  RESERVED2  :bit4;
 end;

 TSDMA0_GFX_DOORBELL_LOG=bitpacked record
  BE_ERROR :bit1;
  RESERVED0:bit1;
  DATA     :bit30;
 end;

 TSDMA0_GFX_MIDCMD_DATA0=bit32;

 TSDMA0_GFX_MIDCMD_DATA1=bit32;

 TSDMA0_GFX_MIDCMD_DATA2=bit32;

 TSDMA0_GFX_MIDCMD_DATA3=bit32;

 TSDMA0_GFX_MIDCMD_DATA4=bit32;

 TSDMA0_GFX_MIDCMD_DATA5=bit32;

 TSDMA0_GFX_VIRTUAL_ADDR=bitpacked record
  ATC        :bit1;
  INVAL      :bit1;
  RESERVED0  :bit2;
  PTR32      :bit1;
  RESERVED1  :bit3;
  SHARED_BASE:bit3;
  RESERVED2  :bit19;
  VM_HOLE    :bit1;
  RESERVED3  :bit1;
 end;

 TSDMA0_RLC0_CSA_ADDR_HI=bit32;

 TSDMA0_RLC0_CSA_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA0_RLC0_MIDCMD_CNTL=bitpacked record
  DATA_VALID   :bit1;
  COPY_MODE    :bit1;
  RESERVED0    :bit2;
  SPLIT_STATE  :bit4;
  ALLOW_PREEMPT:bit1;
  RESERVED1    :bit23;
 end;

 TSDMA0_RLC1_CSA_ADDR_HI=bit32;

 TSDMA0_RLC1_CSA_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA0_RLC1_MIDCMD_CNTL=bitpacked record
  DATA_VALID   :bit1;
  COPY_MODE    :bit1;
  RESERVED0    :bit2;
  SPLIT_STATE  :bit4;
  ALLOW_PREEMPT:bit1;
  RESERVED1    :bit23;
 end;

 TSDMA1_GFX_CONTEXT_CNTL=bitpacked record
  RESERVED0  :bit16;
  RESUME_CTX :bit1;
  RESERVED1  :bit7;
  SESSION_SEL:bit4;
  RESERVED2  :bit4;
 end;

 TSDMA1_GFX_DOORBELL_LOG=bitpacked record
  BE_ERROR :bit1;
  RESERVED0:bit1;
  DATA     :bit30;
 end;

 TSDMA1_GFX_MIDCMD_DATA0=bit32;

 TSDMA1_GFX_MIDCMD_DATA1=bit32;

 TSDMA1_GFX_MIDCMD_DATA2=bit32;

 TSDMA1_GFX_MIDCMD_DATA3=bit32;

 TSDMA1_GFX_MIDCMD_DATA4=bit32;

 TSDMA1_GFX_MIDCMD_DATA5=bit32;

 TSDMA1_GFX_VIRTUAL_ADDR=bitpacked record
  ATC        :bit1;
  INVAL      :bit1;
  RESERVED0  :bit2;
  PTR32      :bit1;
  RESERVED1  :bit3;
  SHARED_BASE:bit3;
  RESERVED2  :bit19;
  VM_HOLE    :bit1;
  RESERVED3  :bit1;
 end;

 TSDMA1_RLC0_CSA_ADDR_HI=bit32;

 TSDMA1_RLC0_CSA_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA1_RLC0_MIDCMD_CNTL=bitpacked record
  DATA_VALID   :bit1;
  COPY_MODE    :bit1;
  RESERVED0    :bit2;
  SPLIT_STATE  :bit4;
  ALLOW_PREEMPT:bit1;
  RESERVED1    :bit23;
 end;

 TSDMA1_RLC1_CSA_ADDR_HI=bit32;

 TSDMA1_RLC1_CSA_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA1_RLC1_MIDCMD_CNTL=bitpacked record
  DATA_VALID   :bit1;
  COPY_MODE    :bit1;
  RESERVED0    :bit2;
  SPLIT_STATE  :bit4;
  ALLOW_PREEMPT:bit1;
  RESERVED1    :bit23;
 end;

 TSOFT_REGISTERS_TABLE_1=bit32;

 TSOFT_REGISTERS_TABLE_2=bit32;

 TSOFT_REGISTERS_TABLE_3=bit32;

 TSOFT_REGISTERS_TABLE_4=bit32;

 TSOFT_REGISTERS_TABLE_5=bit32;

 TSOFT_REGISTERS_TABLE_6=bit32;

 TSOFT_REGISTERS_TABLE_7=bit32;

 TSOFT_REGISTERS_TABLE_8=bit32;

 TSOFT_REGISTERS_TABLE_9=bit32;

 TSQC_ATC_EDC_GATCL1_CNT=bitpacked record
  ICACHE_DATA_SEC:bit8;
  RESERVED0      :bit8;
  DCACHE_DATA_SEC:bit8;
  RESERVED1      :bit8;
 end;

 TSQ_INTERRUPT_AUTO_MASK=bitpacked record
  MASK     :bit24;
  RESERVED0:bit8;
 end;

 TSQ_INTERRUPT_WORD_AUTO=bitpacked record
  THREAD_TRACE         :bit1;
  WLT                  :bit1;
  THREAD_TRACE_BUF_FULL:bit1;
  REG_TIMESTAMP        :bit1;
  CMD_TIMESTAMP        :bit1;
  HOST_CMD_OVERFLOW    :bit1;
  HOST_REG_OVERFLOW    :bit1;
  IMMED_OVERFLOW       :bit1;
  RESERVED0            :bit16;
  SE_ID                :bit2;
  ENCODING             :bit2;
  RESERVED1            :bit4;
 end;

 TSQ_INTERRUPT_WORD_WAVE=bitpacked record
  DATA     :bit8;
  SH_ID    :bit1;
  PRIV     :bit1;
  VM_ID    :bit4;
  WAVE_ID  :bit4;
  SIMD_ID  :bit2;
  CU_ID    :bit4;
  SE_ID    :bit2;
  ENCODING :bit2;
  RESERVED0:bit4;
 end;

 TSQ_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER4_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER5_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER6_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER7_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER8_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER9_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_THREAD_TRACE_STATUS=bitpacked record
  FINISH_PENDING:bit10;
  RESERVED0     :bit6;
  FINISH_DONE   :bit10;
  RESERVED1     :bit3;
  NEW_BUF       :bit1;
  BUSY          :bit1;
  FULL          :bit1;
 end;

 TSRBM_SDMA_DOMAIN_ADDR0=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SDMA_DOMAIN_ADDR1=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SDMA_DOMAIN_ADDR2=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSRBM_SDMA_DOMAIN_ADDR3=bitpacked record
  ADDR_LO:bit16;
  ADDR_HI:bit16;
 end;

 TSTREAM_SYNCHRONIZATION=bitpacked record
  STREAM_0_SYNCHRONIZATION :bit1;
  STREAM_1_SYNCHRONIZATION :bit1;
  STREAM_2_SYNCHRONIZATION :bit1;
  STREAM_3_SYNCHRONIZATION :bit1;
  STREAM_4_SYNCHRONIZATION :bit1;
  STREAM_5_SYNCHRONIZATION :bit1;
  STREAM_6_SYNCHRONIZATION :bit1;
  STREAM_7_SYNCHRONIZATION :bit1;
  STREAM_8_SYNCHRONIZATION :bit1;
  STREAM_9_SYNCHRONIZATION :bit1;
  STREAM_10_SYNCHRONIZATION:bit1;
  STREAM_11_SYNCHRONIZATION:bit1;
  STREAM_12_SYNCHRONIZATION:bit1;
  STREAM_13_SYNCHRONIZATION:bit1;
  STREAM_14_SYNCHRONIZATION:bit1;
  STREAM_15_SYNCHRONIZATION:bit1;
  RESERVED0                :bit16;
 end;

 TSX_PERFCOUNTER0_SELECT=bitpacked record
  PERFCOUNTER_SELECT :bit10;
  PERFCOUNTER_SELECT1:bit10;
  CNTR_MODE          :bit4;
  RESERVED0          :bit8;
 end;

 TSX_PERFCOUNTER1_SELECT=bitpacked record
  PERFCOUNTER_SELECT :bit10;
  PERFCOUNTER_SELECT1:bit10;
  CNTR_MODE          :bit4;
  RESERVED0          :bit8;
 end;

 TSX_PERFCOUNTER2_SELECT=bitpacked record
  PERFCOUNTER_SELECT :bit10;
  PERFCOUNTER_SELECT1:bit10;
  CNTR_MODE          :bit4;
  RESERVED0          :bit8;
 end;

 TSX_PERFCOUNTER3_SELECT=bitpacked record
  PERFCOUNTER_SELECT :bit10;
  PERFCOUNTER_SELECT1:bit10;
  CNTR_MODE          :bit4;
  RESERVED0          :bit8;
 end;

 TTA_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL  :bit8;
  RESERVED0 :bit2;
  PERF_SEL1 :bit8;
  RESERVED1 :bit2;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TTA_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL  :bit8;
  RESERVED0 :bit2;
  PERF_SEL1 :bit8;
  RESERVED1 :bit2;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TTCP_ATC_EDC_GATCL1_CNT=bitpacked record
  DATA_SEC :bit8;
  RESERVED0:bit24;
 end;

 TTC_CFG_L1_LOAD_POLICY0=bitpacked record
  POLICY_0 :bit2;
  POLICY_1 :bit2;
  POLICY_2 :bit2;
  POLICY_3 :bit2;
  POLICY_4 :bit2;
  POLICY_5 :bit2;
  POLICY_6 :bit2;
  POLICY_7 :bit2;
  POLICY_8 :bit2;
  POLICY_9 :bit2;
  POLICY_10:bit2;
  POLICY_11:bit2;
  POLICY_12:bit2;
  POLICY_13:bit2;
  POLICY_14:bit2;
  POLICY_15:bit2;
 end;

 TTC_CFG_L1_LOAD_POLICY1=bitpacked record
  POLICY_16:bit2;
  POLICY_17:bit2;
  POLICY_18:bit2;
  POLICY_19:bit2;
  POLICY_20:bit2;
  POLICY_21:bit2;
  POLICY_22:bit2;
  POLICY_23:bit2;
  POLICY_24:bit2;
  POLICY_25:bit2;
  POLICY_26:bit2;
  POLICY_27:bit2;
  POLICY_28:bit2;
  POLICY_29:bit2;
  POLICY_30:bit2;
  POLICY_31:bit2;
 end;

 TTC_CFG_L1_STORE_POLICY=bitpacked record
  POLICY_0 :bit1;
  POLICY_1 :bit1;
  POLICY_2 :bit1;
  POLICY_3 :bit1;
  POLICY_4 :bit1;
  POLICY_5 :bit1;
  POLICY_6 :bit1;
  POLICY_7 :bit1;
  POLICY_8 :bit1;
  POLICY_9 :bit1;
  POLICY_10:bit1;
  POLICY_11:bit1;
  POLICY_12:bit1;
  POLICY_13:bit1;
  POLICY_14:bit1;
  POLICY_15:bit1;
  POLICY_16:bit1;
  POLICY_17:bit1;
  POLICY_18:bit1;
  POLICY_19:bit1;
  POLICY_20:bit1;
  POLICY_21:bit1;
  POLICY_22:bit1;
  POLICY_23:bit1;
  POLICY_24:bit1;
  POLICY_25:bit1;
  POLICY_26:bit1;
  POLICY_27:bit1;
  POLICY_28:bit1;
  POLICY_29:bit1;
  POLICY_30:bit1;
  POLICY_31:bit1;
 end;

 TTC_CFG_L2_LOAD_POLICY0=bitpacked record
  POLICY_0 :bit2;
  POLICY_1 :bit2;
  POLICY_2 :bit2;
  POLICY_3 :bit2;
  POLICY_4 :bit2;
  POLICY_5 :bit2;
  POLICY_6 :bit2;
  POLICY_7 :bit2;
  POLICY_8 :bit2;
  POLICY_9 :bit2;
  POLICY_10:bit2;
  POLICY_11:bit2;
  POLICY_12:bit2;
  POLICY_13:bit2;
  POLICY_14:bit2;
  POLICY_15:bit2;
 end;

 TTC_CFG_L2_LOAD_POLICY1=bitpacked record
  POLICY_16:bit2;
  POLICY_17:bit2;
  POLICY_18:bit2;
  POLICY_19:bit2;
  POLICY_20:bit2;
  POLICY_21:bit2;
  POLICY_22:bit2;
  POLICY_23:bit2;
  POLICY_24:bit2;
  POLICY_25:bit2;
  POLICY_26:bit2;
  POLICY_27:bit2;
  POLICY_28:bit2;
  POLICY_29:bit2;
  POLICY_30:bit2;
  POLICY_31:bit2;
 end;

 TTD_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL  :bit8;
  RESERVED0 :bit2;
  PERF_SEL1 :bit8;
  RESERVED1 :bit2;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TTD_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL  :bit8;
  RESERVED0 :bit2;
  PERF_SEL1 :bit8;
  RESERVED1 :bit2;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TTMDS_CONTROL0_FEEDBACK=bitpacked record
  TMDS_CONTROL0_FEEDBACK_SELECT:bit2;
  RESERVED0                    :bit6;
  TMDS_CONTROL0_FEEDBACK_DELAY :bit2;
  RESERVED1                    :bit22;
 end;

 TUNIPHY_REG_TEST_OUTPUT=bitpacked record
  UNIPHY_TEST_CNTL             :bit5;
  UNIPHY_PLL_TEST_VCTL         :bit4;
  UNIPHY_PLL_TEST_SSAMP_EN     :bit1;
  UNIPHY_PLL_TEST_UNLOCK_CLR   :bit1;
  RESERVED0                    :bit4;
  UNIPHY_DIG_BIST_RESET        :bit1;
  UNIPHY_DIG_BIST_SEL          :bit1;
  UNIPHY_TEST_VCTL_EN          :bit1;
  RESERVED1                    :bit2;
  UNIPHY_DIG_BIST_ERROR        :bit5;
  UNIPHY_PLL_TEST_VCTL_ADC     :bit3;
  UNIPHY_PLL_TEST_FREQ_LOCK    :bit1;
  UNIPHY_PLL_INTRESET          :bit1;
  UNIPHY_PLL_TEST_UNLOCK_STICKY:bit1;
  UNIPHY_PLL_TEST_LOCK         :bit1;
 end;

 TUVD_LMI_VMID_INTERNAL2=bitpacked record
  MIF_GPGPU_VMID   :bit4;
  MIF_CURR_VMID    :bit4;
  MIF_REF_VMID     :bit4;
  MIF_DBW_VMID     :bit4;
  MIF_CM_COLOC_VMID:bit4;
  MIF_BSD_VMID     :bit4;
  MIF_BSP_VMID     :bit4;
  VDMA_VMID        :bit4;
 end;

 TUVD_LMI_VMID_INTERNAL3=bitpacked record
  MIF_GEN_RD0_VMID:bit4;
  MIF_GEN_RD1_VMID:bit4;
  MIF_GEN_WR0_VMID:bit4;
  MIF_GEN_WR1_VMID:bit4;
  MIF_SCLR_VMID   :bit4;
  RESERVED0       :bit12;
 end;

 TUVD_VCPU_CACHE_OFFSET0=bitpacked record
  CACHE_OFFSET0:bit25;
  RESERVED0    :bit7;
 end;

 TUVD_VCPU_CACHE_OFFSET1=bitpacked record
  CACHE_OFFSET1:bit25;
  RESERVED0    :bit7;
 end;

 TUVD_VCPU_CACHE_OFFSET2=bitpacked record
  CACHE_OFFSET2:bit25;
  RESERVED0    :bit7;
 end;

 TVCE_UENC_DMA_DCLK_CTRL=bitpacked record
  WRDMCLK_FORCEON:bit1;
  RDDMCLK_FORCEON:bit1;
  REGCLK_FORCEON :bit1;
  RESERVED0      :bit1;
  RESERVED1      :bit1;
  RESERVED2      :bit1;
  RESERVED3      :bit1;
  RESERVED4      :bit1;
  RESERVED5      :bit1;
  RESERVED6      :bit1;
  RESERVED7      :bit1;
  RESERVED8      :bit1;
  RESERVED9      :bit1;
  RESERVED10     :bit1;
  RESERVED11     :bit18;
 end;

 TVCE_VCPU_CACHE_OFFSET0=bitpacked record
  OFFSET   :bit28;
  RESERVED0:bit4;
 end;

 TVCE_VCPU_CACHE_OFFSET1=bitpacked record
  OFFSET   :bit28;
  RESERVED0:bit4;
 end;

 TVCE_VCPU_CACHE_OFFSET2=bitpacked record
  OFFSET   :bit28;
  RESERVED0:bit4;
 end;

 TVGA_MEM_READ_PAGE_ADDR=bitpacked record
  VGA_MEM_READ_PAGE0_ADDR:bit10;
  RESERVED0              :bit6;
  VGA_MEM_READ_PAGE1_ADDR:bit10;
  RESERVED1              :bit6;
 end;

 TVGT_CACHE_INVALIDATION=bitpacked record
  CACHE_INVALIDATION  :bit2;
  RESERVED0           :bit2;
  DIS_INSTANCING_OPT  :bit1;
  VS_NO_EXTRA_BUFFER  :bit1;
  AUTO_INVLD_EN       :bit2;
  RESERVED1           :bit1;
  USE_GS_DONE         :bit1;
  RESERVED2           :bit1;
  DIS_RANGE_FULL_INVLD:bit1;
  GS_LATE_ALLOC_EN    :bit1;
  STREAMOUT_FULL_FLUSH:bit1;
  RESERVED3           :bit2;
  ES_LIMIT            :bit5;
  RESERVED4           :bit11;
 end;

 TVGT_DMA_PRIMITIVE_TYPE=bitpacked record
  PRIM_TYPE:bit6;
  RESERVED0:bit26;
 end;

 TVGT_DMA_REQ_FIFO_DEPTH=bitpacked record
  DMA_REQ_FIFO_DEPTH:bit6;
  RESERVED0         :bit26;
 end;

 TVGT_ESGS_RING_ITEMSIZE=bitpacked record
  ITEMSIZE :bit15;
  RESERVED0:bit17;
 end;

 TVGT_GSVS_RING_ITEMSIZE=bitpacked record
  ITEMSIZE :bit15;
  RESERVED0:bit17;
 end;

 TVGT_GSVS_RING_OFFSET_1=bitpacked record
  OFFSET   :bit15;
  RESERVED0:bit17;
 end;

 TVGT_GSVS_RING_OFFSET_2=bitpacked record
  OFFSET   :bit15;
  RESERVED0:bit17;
 end;

 TVGT_GSVS_RING_OFFSET_3=bitpacked record
  OFFSET   :bit15;
  RESERVED0:bit17;
 end;

 TVGT_GS_VERT_ITEMSIZE_1=bitpacked record
  ITEMSIZE :bit15;
  RESERVED0:bit17;
 end;

 TVGT_GS_VERT_ITEMSIZE_2=bitpacked record
  ITEMSIZE :bit15;
  RESERVED0:bit17;
 end;

 TVGT_GS_VERT_ITEMSIZE_3=bitpacked record
  ITEMSIZE :bit15;
  RESERVED0:bit17;
 end;

 TVGT_HOS_MAX_TESS_LEVEL=bit32;

 TVGT_HOS_MIN_TESS_LEVEL=bit32;

 TVGT_VTX_VECT_EJECT_REG=bitpacked record
  PRIM_COUNT:bit10;
  RESERVED0 :bit22;
 end;

 TVM_INVALIDATE_RESPONSE=bitpacked record
  DOMAIN_INVALIDATED_0 :bit1;
  DOMAIN_INVALIDATED_1 :bit1;
  DOMAIN_INVALIDATED_2 :bit1;
  DOMAIN_INVALIDATED_3 :bit1;
  DOMAIN_INVALIDATED_4 :bit1;
  DOMAIN_INVALIDATED_5 :bit1;
  DOMAIN_INVALIDATED_6 :bit1;
  DOMAIN_INVALIDATED_7 :bit1;
  DOMAIN_INVALIDATED_8 :bit1;
  DOMAIN_INVALIDATED_9 :bit1;
  DOMAIN_INVALIDATED_10:bit1;
  DOMAIN_INVALIDATED_11:bit1;
  DOMAIN_INVALIDATED_12:bit1;
  DOMAIN_INVALIDATED_13:bit1;
  DOMAIN_INVALIDATED_14:bit1;
  DOMAIN_INVALIDATED_15:bit1;
  RESERVED0            :bit16;
 end;

 TWD_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit20;
  PERF_MODE:bit4;
 end;

 TWD_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit20;
  PERF_MODE:bit4;
 end;

 TWD_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit20;
  PERF_MODE:bit4;
 end;

 TWD_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit20;
  PERF_MODE:bit4;
 end;

 TXDMA_CLOCK_GATING_CNTL=bitpacked record
  XDMA_SCLK_TURN_ON_DELAY         :bit4;
  XDMA_SCLK_TURN_OFF_DELAY        :bit8;
  RESERVED0                       :bit3;
  XDMA_SCLK_GATE_DIS              :bit1;
  XDMA_SCLK_REG_GATE_DIS          :bit1;
  XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0:bit1;
  XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1:bit1;
  XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2:bit1;
  XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3:bit1;
  XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4:bit1;
  XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5:bit1;
  XDMA_SCLK_G_SDYN_GATE_DIS       :bit1;
  XDMA_SCLK_G_MSTAT_GATE_DIS      :bit1;
  XDMA_SCLK_G_SSTAT_GATE_DIS      :bit1;
  RESERVED1                       :bit6;
 end;

 TXDMA_MSTR_READ_COMMAND=bitpacked record
  XDMA_MSTR_REQUEST_SIZE    :bit14;
  RESERVED0                 :bit2;
  XDMA_MSTR_REQUEST_PREFETCH:bit14;
  RESERVED1                 :bit2;
 end;

 TAFMT_AUDIO_DBG_DTO_CNTL=bitpacked record
  AFMT_AUDIO_DTO_FS_DIV_SEL:bit3;
  RESERVED0                :bit5;
  AFMT_AUDIO_DTO_DBG_BASE  :bit1;
  RESERVED1                :bit3;
  AFMT_AUDIO_DTO_DBG_MULTI :bit3;
  RESERVED2                :bit1;
  AFMT_AUDIO_DTO_DBG_DIV   :bit3;
  RESERVED3                :bit13;
 end;

 TAFMT_INFOFRAME_CONTROL0=bitpacked record
  RESERVED0             :bit6;
  AFMT_AUDIO_INFO_SOURCE:bit1;
  AFMT_AUDIO_INFO_UPDATE:bit1;
  RESERVED1             :bit2;
  AFMT_MPEG_INFO_UPDATE :bit1;
  RESERVED2             :bit21;
 end;

 TAFMT_VBI_PACKET_CONTROL=bitpacked record
  RESERVED0           :bit2;
  AFMT_GENERIC0_UPDATE:bit1;
  AFMT_GENERIC2_UPDATE:bit1;
  RESERVED1           :bit9;
  RESERVED2           :bit1;
  RESERVED3           :bit16;
  AFMT_GENERIC_INDEX  :bit2;
 end;

 TATC_VMID0_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID1_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID2_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID3_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID4_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID5_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID6_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID7_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID8_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID9_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TAUX_DPHY_TX_REF_CONTROL=bitpacked record
  AUX_TX_REF_SEL:bit1;
  RESERVED0     :bit3;
  AUX_TX_RATE   :bit2;
  RESERVED1     :bit10;
  AUX_TX_REF_DIV:bit9;
  RESERVED2     :bit7;
 end;

 TAZALIA_CONTROLLER_DEBUG=bit32;

 TAZALIA_CORB_DMA_CONTROL=bitpacked record
  CORB_DMA_NON_SNOOP  :bit1;
  RESERVED0           :bit3;
  CORB_DMA_ISOCHRONOUS:bit1;
  RESERVED1           :bit27;
 end;

 TAZALIA_DATA_DMA_CONTROL=bitpacked record
  DATA_DMA_NON_SNOOP          :bit2;
  INPUT_DATA_DMA_NON_SNOOP    :bit2;
  DATA_DMA_ISOCHRONOUS        :bit2;
  INPUT_DATA_DMA_ISOCHRONOUS  :bit2;
  RESERVED0                   :bit6;
  RESERVED1                   :bit1;
  RESERVED2                   :bit1;
  AZALIA_IOC_GENERATION_METHOD:bit1;
  AZALIA_UNDERFLOW_CONTROL    :bit1;
  RESERVED3                   :bit14;
 end;

 TBIF_IOV_FUNC_IDENTIFIER=bitpacked record
  FUNC_IDENTIFIER:bit1;
  RESERVED0      :bit30;
  IOV_ENABLE     :bit1;
 end;

 TBIF_PERFCOUNTER0_RESULT=bit32;

 TBIF_PERFCOUNTER1_RESULT=bit32;

 TCB_PERFCOUNTER0_SELECT0=bitpacked record
  RESERVED0:bit8;
  RESERVED1:bit1;
  RESERVED2:bit3;
  RESERVED3:bit1;
  RESERVED4:bit5;
  RESERVED5:bit14;
 end;

 TCB_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2 :bit9;
  RESERVED0 :bit1;
  PERF_SEL3 :bit9;
  RESERVED1 :bit5;
  PERF_MODE3:bit4;
  PERF_MODE2:bit4;
 end;

 TCB_PERFCOUNTER1_SELECT0=bitpacked record
  RESERVED0:bit8;
  RESERVED1:bit1;
  RESERVED2:bit3;
  RESERVED3:bit1;
  RESERVED4:bit5;
  RESERVED5:bit14;
 end;

 TCB_PERFCOUNTER1_SELECT1=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit4;
  RESERVED4:bit1;
  RESERVED5:bit3;
  RESERVED6:bit1;
  RESERVED7:bit2;
  RESERVED8:bit18;
 end;

 TCB_PERFCOUNTER2_SELECT0=bitpacked record
  RESERVED0:bit8;
  RESERVED1:bit1;
  RESERVED2:bit3;
  RESERVED3:bit1;
  RESERVED4:bit5;
  RESERVED5:bit14;
 end;

 TCB_PERFCOUNTER2_SELECT1=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit4;
  RESERVED4:bit1;
  RESERVED5:bit3;
  RESERVED6:bit1;
  RESERVED7:bit2;
  RESERVED8:bit18;
 end;

 TCB_PERFCOUNTER3_SELECT0=bitpacked record
  RESERVED0:bit8;
  RESERVED1:bit1;
  RESERVED2:bit3;
  RESERVED3:bit1;
  RESERVED4:bit5;
  RESERVED5:bit14;
 end;

 TCB_PERFCOUNTER3_SELECT1=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit1;
  RESERVED3:bit4;
  RESERVED4:bit1;
  RESERVED5:bit3;
  RESERVED6:bit1;
  RESERVED7:bit2;
  RESERVED8:bit18;
 end;

 TCG_SPLL_SPREAD_SPECTRUM=bitpacked record
  SSEN     :bit2;
  RESERVED0:bit2;
  CLKS     :bit12;
  RESERVED1:bit12;
  RESERVED2:bit4;
 end;

 TCHUB_ATC_PERFCOUNTER_HI=bitpacked record
  COUNTER_HI   :bit16;
  COMPARE_VALUE:bit16;
 end;

 TCHUB_ATC_PERFCOUNTER_LO=bit32;

 TCOL_MAN_TEST_DEBUG_DATA=bit32;

 TCOMPUTE_RESOURCE_LIMITS=bitpacked record
  WAVES_PER_SH   :bit10;
  RESERVED0      :bit2;
  TG_PER_CU      :bit4;
  LOCK_THRESHOLD :bit6;
  SIMD_DEST_CNTL :bit1;
  FORCE_SIMD_DIST:bit1;
  CU_GROUP_COUNT :bit3;
  RESERVED1      :bit5;
 end;

 TCORB_LOWER_BASE_ADDRESS=bitpacked record
  CORB_LOWER_BASE_UNIMPLEMENTED_BITS:bit7;
  CORB_LOWER_BASE_ADDRESS           :bit25;
 end;

 TCORB_UPPER_BASE_ADDRESS=bit32;

 TCPC_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL :bit6;
  RESERVED0:bit4;
  PERF_SEL1:bit6;
  RESERVED1:bit4;
  CNTR_MODE:bit4;
  RESERVED2:bit8;
 end;

 TCPC_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL :bit6;
  RESERVED0:bit26;
 end;

 TCPF_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL :bit6;
  RESERVED0:bit4;
  PERF_SEL1:bit6;
  RESERVED1:bit4;
  CNTR_MODE:bit4;
  RESERVED2:bit8;
 end;

 TCPF_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL :bit6;
  RESERVED0:bit26;
 end;

 TCPG_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL :bit6;
  RESERVED0:bit4;
  PERF_SEL1:bit6;
  RESERVED1:bit4;
  CNTR_MODE:bit4;
  RESERVED2:bit8;
 end;

 TCPG_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL :bit6;
  RESERVED0:bit26;
 end;

 TCP_APPEND_LAST_CS_FENCE=bit32;

 TCP_APPEND_LAST_PS_FENCE=bit32;

 TCP_CE_COMPLETION_STATUS=bitpacked record
  STATUS   :bit2;
  RESERVED0:bit30;
 end;

 TCP_GDS_ATOMIC0_PREOP_HI=bit32;

 TCP_GDS_ATOMIC0_PREOP_LO=bit32;

 TCP_GDS_ATOMIC1_PREOP_HI=bit32;

 TCP_GDS_ATOMIC1_PREOP_LO=bit32;

 TCP_HQD_ATOMIC0_PREOP_HI=bit32;

 TCP_HQD_ATOMIC0_PREOP_LO=bit32;

 TCP_HQD_ATOMIC1_PREOP_HI=bit32;

 TCP_HQD_ATOMIC1_PREOP_LO=bit32;

 TCP_HQD_CTX_SAVE_CONTROL=bitpacked record
  ATC      :bit1;
  MTYPE    :bit2;
  POLICY   :bit1;
  RESERVED0:bit28;
 end;

 TCP_HQD_EOP_BASE_ADDR_HI=bitpacked record
  BASE_ADDR_HI:bit8;
  RESERVED0   :bit24;
 end;

 TCP_HQD_PERSISTENT_STATE=bitpacked record
  PRELOAD_REQ   :bit1;
  RESERVED0     :bit7;
  PRELOAD_SIZE  :bit10;
  RESERVED1     :bit10;
  RESTORE_ACTIVE:bit1;
  RELAUNCH_WAVES:bit1;
  QSWITCH_MODE  :bit1;
  DISP_ACTIVE   :bit1;
 end;

 TCP_ME1_PIPE0_INT_STATUS=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_STATUS  :bit1;
  DEQUEUE_REQUEST_INT_STATUS   :bit1;
  CP_ECC_ERROR_INT_STATUS      :bit1;
  SUA_VIOLATION_INT_STATUS     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_STATUS  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_STATUS          :bit1;
  OPCODE_ERROR_INT_STATUS      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_STATUS        :bit1;
  RESERVED_BIT_ERROR_INT_STATUS:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_STATUS          :bit1;
  GENERIC1_INT_STATUS          :bit1;
  GENERIC0_INT_STATUS          :bit1;
 end;

 TCP_ME1_PIPE1_INT_STATUS=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_STATUS  :bit1;
  DEQUEUE_REQUEST_INT_STATUS   :bit1;
  CP_ECC_ERROR_INT_STATUS      :bit1;
  SUA_VIOLATION_INT_STATUS     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_STATUS  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_STATUS          :bit1;
  OPCODE_ERROR_INT_STATUS      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_STATUS        :bit1;
  RESERVED_BIT_ERROR_INT_STATUS:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_STATUS          :bit1;
  GENERIC1_INT_STATUS          :bit1;
  GENERIC0_INT_STATUS          :bit1;
 end;

 TCP_ME1_PIPE2_INT_STATUS=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_STATUS  :bit1;
  DEQUEUE_REQUEST_INT_STATUS   :bit1;
  CP_ECC_ERROR_INT_STATUS      :bit1;
  SUA_VIOLATION_INT_STATUS     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_STATUS  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_STATUS          :bit1;
  OPCODE_ERROR_INT_STATUS      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_STATUS        :bit1;
  RESERVED_BIT_ERROR_INT_STATUS:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_STATUS          :bit1;
  GENERIC1_INT_STATUS          :bit1;
  GENERIC0_INT_STATUS          :bit1;
 end;

 TCP_ME1_PIPE3_INT_STATUS=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_STATUS  :bit1;
  DEQUEUE_REQUEST_INT_STATUS   :bit1;
  CP_ECC_ERROR_INT_STATUS      :bit1;
  SUA_VIOLATION_INT_STATUS     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_STATUS  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_STATUS          :bit1;
  OPCODE_ERROR_INT_STATUS      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_STATUS        :bit1;
  RESERVED_BIT_ERROR_INT_STATUS:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_STATUS          :bit1;
  GENERIC1_INT_STATUS          :bit1;
  GENERIC0_INT_STATUS          :bit1;
 end;

 TCP_ME2_PIPE0_INT_STATUS=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_STATUS  :bit1;
  DEQUEUE_REQUEST_INT_STATUS   :bit1;
  CP_ECC_ERROR_INT_STATUS      :bit1;
  SUA_VIOLATION_INT_STATUS     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_STATUS  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_STATUS          :bit1;
  OPCODE_ERROR_INT_STATUS      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_STATUS        :bit1;
  RESERVED_BIT_ERROR_INT_STATUS:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_STATUS          :bit1;
  GENERIC1_INT_STATUS          :bit1;
  GENERIC0_INT_STATUS          :bit1;
 end;

 TCP_ME2_PIPE1_INT_STATUS=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_STATUS  :bit1;
  DEQUEUE_REQUEST_INT_STATUS   :bit1;
  CP_ECC_ERROR_INT_STATUS      :bit1;
  SUA_VIOLATION_INT_STATUS     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_STATUS  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_STATUS          :bit1;
  OPCODE_ERROR_INT_STATUS      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_STATUS        :bit1;
  RESERVED_BIT_ERROR_INT_STATUS:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_STATUS          :bit1;
  GENERIC1_INT_STATUS          :bit1;
  GENERIC0_INT_STATUS          :bit1;
 end;

 TCP_ME2_PIPE2_INT_STATUS=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_STATUS  :bit1;
  DEQUEUE_REQUEST_INT_STATUS   :bit1;
  CP_ECC_ERROR_INT_STATUS      :bit1;
  SUA_VIOLATION_INT_STATUS     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_STATUS  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_STATUS          :bit1;
  OPCODE_ERROR_INT_STATUS      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_STATUS        :bit1;
  RESERVED_BIT_ERROR_INT_STATUS:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_STATUS          :bit1;
  GENERIC1_INT_STATUS          :bit1;
  GENERIC0_INT_STATUS          :bit1;
 end;

 TCP_ME2_PIPE3_INT_STATUS=bitpacked record
  RESERVED0                    :bit12;
  CMP_QUERY_STATUS_INT_STATUS  :bit1;
  DEQUEUE_REQUEST_INT_STATUS   :bit1;
  CP_ECC_ERROR_INT_STATUS      :bit1;
  SUA_VIOLATION_INT_STATUS     :bit1;
  RESERVED1                    :bit1;
  WRM_POLL_TIMEOUT_INT_STATUS  :bit1;
  RESERVED2                    :bit5;
  PRIV_REG_INT_STATUS          :bit1;
  OPCODE_ERROR_INT_STATUS      :bit1;
  RESERVED3                    :bit1;
  TIME_STAMP_INT_STATUS        :bit1;
  RESERVED_BIT_ERROR_INT_STATUS:bit1;
  RESERVED4                    :bit1;
  GENERIC2_INT_STATUS          :bit1;
  GENERIC1_INT_STATUS          :bit1;
  GENERIC0_INT_STATUS          :bit1;
 end;

 TCP_PFP_PRGRM_CNTR_START=bitpacked record
  IP_START :bit12;
  RESERVED0:bit20;
 end;

 TCP_RB_WPTR_POLL_ADDR_HI=bitpacked record
  RB_WPTR_POLL_ADDR_HI:bit8;
  RESERVED0           :bit24;
 end;

 TCP_RB_WPTR_POLL_ADDR_LO=bitpacked record
  RESERVED0           :bit2;
  RB_WPTR_POLL_ADDR_LO:bit30;
 end;

 TCP_SC_PSINVOC_COUNT0_HI=bit32;

 TCP_SC_PSINVOC_COUNT0_LO=bit32;

 TCP_SC_PSINVOC_COUNT1_HI=bit32;

 TCP_SC_PSINVOC_COUNT1_LO=bit32;

 TCP_VGT_CSINVOC_COUNT_HI=bit32;

 TCP_VGT_CSINVOC_COUNT_LO=bit32;

 TCP_VGT_DSINVOC_COUNT_HI=bit32;

 TCP_VGT_DSINVOC_COUNT_LO=bit32;

 TCP_VGT_GSINVOC_COUNT_HI=bit32;

 TCP_VGT_GSINVOC_COUNT_LO=bit32;

 TCP_VGT_HSINVOC_COUNT_HI=bit32;

 TCP_VGT_HSINVOC_COUNT_LO=bit32;

 TCP_VGT_VSINVOC_COUNT_HI=bit32;

 TCP_VGT_VSINVOC_COUNT_LO=bit32;

 TCP_WAIT_REG_MEM_TIMEOUT=bit32;

 TCRTC_DCFE_CLOCK_CONTROL=bitpacked record
  RESERVED0                       :bit4;
  CRTC_DISPCLK_R_DCFE_GATE_DISABLE:bit1;
  RESERVED1                       :bit3;
  CRTC_DISPCLK_G_DCP_GATE_DISABLE :bit1;
  RESERVED2                       :bit3;
  CRTC_DISPCLK_G_SCL_GATE_DISABLE :bit1;
  RESERVED3                       :bit11;
  CRTC_DCFE_TEST_CLK_SEL          :bit5;
  RESERVED4                       :bit2;
  CRTC_DCFE_CLOCK_ENABLE          :bit1;
 end;

 TCRTC_OVERSCAN_COLOR_EXT=bitpacked record
  CRTC_OVERSCAN_COLOR_BLUE_EXT :bit2;
  RESERVED0                    :bit6;
  CRTC_OVERSCAN_COLOR_GREEN_EXT:bit2;
  RESERVED1                    :bit6;
  CRTC_OVERSCAN_COLOR_RED_EXT  :bit2;
  RESERVED2                    :bit14;
 end;

 TCRTC_START_LINE_CONTROL=bitpacked record
  CRTC_PROGRESSIVE_START_LINE_EARLY:bit1;
  RESERVED0                        :bit7;
  CRTC_INTERLACE_START_LINE_EARLY  :bit1;
  RESERVED1                        :bit3;
  CRTC_ADVANCED_START_LINE_POSITION:bit8;
  CRTC_LEGACY_REQUESTOR_EN         :bit1;
  RESERVED2                        :bit7;
  CRTC_PREFETCH_EN                 :bit1;
  RESERVED3                        :bit3;
 end;

 TCRTC_STATUS_FRAME_COUNT=bitpacked record
  CRTC_FRAME_COUNT:bit24;
  RESERVED0       :bit8;
 end;

 TCRTC_TEST_PATTERN_COLOR=bitpacked record
  CRTC_TEST_PATTERN_DATA:bit16;
  CRTC_TEST_PATTERN_MASK:bit6;
  RESERVED0             :bit10;
 end;

 TCRTC_V_TOTAL_INT_STATUS=bitpacked record
  CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED    :bit1;
  RESERVED0                             :bit3;
  CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT:bit1;
  RESERVED1                             :bit3;
  CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK:bit1;
  RESERVED2                             :bit3;
  CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK:bit1;
  RESERVED3                             :bit19;
 end;

 TCSPRIV_THREAD_TRACE_TG0=bit32;

 TCSPRIV_THREAD_TRACE_TG1=bit32;

 TCSPRIV_THREAD_TRACE_TG2=bit32;

 TCSPRIV_THREAD_TRACE_TG3=bitpacked record
  WAVE_ID_BASE    :bit12;
  THREADS_IN_GROUP:bit12;
  PARTIAL_X_FLAG  :bit1;
  PARTIAL_Y_FLAG  :bit1;
  PARTIAL_Z_FLAG  :bit1;
  LAST_TG         :bit1;
  FIRST_TG        :bit1;
  RESERVED0       :bit3;
 end;

 TCUR_REQUEST_FILTER_CNTL=bitpacked record
  CUR_REQUEST_FILTER_DIS:bit1;
  RESERVED0             :bit31;
 end;

 TDAC_AUTODETECT_CONTROL2=bitpacked record
  DAC_AUTODETECT_POWERUP_COUNTER:bit8;
  DAC_AUTODETECT_TESTMODE       :bit1;
  RESERVED0                     :bit23;
 end;

 TDAC_AUTODETECT_CONTROL3=bitpacked record
  DAC_AUTODET_COMPARATOR_IN_DELAY :bit8;
  DAC_AUTODET_COMPARATOR_OUT_DELAY:bit8;
  RESERVED0                       :bit16;
 end;

 TDB_OCCLUSION_COUNT0_LOW=bit32;

 TDB_OCCLUSION_COUNT1_LOW=bit32;

 TDB_OCCLUSION_COUNT2_LOW=bit32;

 TDB_OCCLUSION_COUNT3_LOW=bit32;

 TDB_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE3:bit4;
  PERF_MODE2:bit4;
 end;

 TDB_PERFCOUNTER1_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE3:bit4;
  PERF_MODE2:bit4;
 end;

 TDCCG_DS_HW_CAL_INTERVAL=bit32;

 TDCIO_GSL_GENLK_PAD_CNTL=bitpacked record
  DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL  :bit2;
  RESERVED0                           :bit2;
  DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL    :bit2;
  RESERVED1                           :bit2;
  DCIO_GENLK_CLK_GSL_MASK             :bit2;
  RESERVED2                           :bit6;
  DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL:bit2;
  RESERVED3                           :bit2;
  DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL  :bit2;
  RESERVED4                           :bit2;
  DCIO_GENLK_VSYNC_GSL_MASK           :bit2;
  RESERVED5                           :bit6;
 end;

 TDCO_DCFE_EXT_VSYNC_CNTL=bitpacked record
  DCO_DCFE0_EXT_VSYNC_MUX     :bit3;
  RESERVED0                   :bit1;
  DCO_DCFE1_EXT_VSYNC_MUX     :bit3;
  RESERVED1                   :bit1;
  DCO_DCFE2_EXT_VSYNC_MUX     :bit3;
  RESERVED2                   :bit1;
  DCO_DCFE3_EXT_VSYNC_MUX     :bit3;
  RESERVED3                   :bit1;
  DCO_DCFE4_EXT_VSYNC_MUX     :bit3;
  RESERVED4                   :bit1;
  DCO_DCFE5_EXT_VSYNC_MUX     :bit3;
  RESERVED5                   :bit1;
  DCO_SWAPLOCKB_EXT_VSYNC_MASK:bit3;
  RESERVED6                   :bit1;
  DCO_GENERICB_EXT_VSYNC_MASK :bit3;
  DCO_CRTC_MANUAL_FLOW_CONTROL:bit1;
 end;

 TDCP_SPATIAL_DITHER_CNTL=bitpacked record
  DCP_SPATIAL_DITHER_EN     :bit1;
  RESERVED0                 :bit3;
  DCP_SPATIAL_DITHER_MODE   :bit2;
  DCP_SPATIAL_DITHER_DEPTH  :bit2;
  DCP_FRAME_RANDOM_ENABLE   :bit1;
  DCP_RGB_RANDOM_ENABLE     :bit1;
  DCP_HIGHPASS_RANDOM_ENABLE:bit1;
  RESERVED1                 :bit21;
 end;

 TDC_ABM1_IPCSC_COEFF_SEL=bitpacked record
  ABM1_IPCSC_COEFF_SEL_B:bit4;
  RESERVED0             :bit4;
  ABM1_IPCSC_COEFF_SEL_G:bit4;
  RESERVED1             :bit4;
  ABM1_IPCSC_COEFF_SEL_R:bit4;
  RESERVED2             :bit11;
  ABM1_HGLS_REG_LOCK    :bit1;
 end;

 TDC_ABM1_LS_MIN_MAX_LUMA=bitpacked record
  ABM1_LS_MIN_LUMA:bit10;
  RESERVED0       :bit6;
  ABM1_LS_MAX_LUMA:bit10;
  RESERVED1       :bit6;
 end;

 TDC_ABM1_LS_OVR_SCAN_BIN=bitpacked record
  ABM1_LS_OVR_SCAN_BIN:bit24;
  RESERVED0           :bit8;
 end;

 TDC_GPIO_I2CPAD_STRENGTH=bitpacked record
  I2C_STRENGTH_SN:bit4;
  I2C_STRENGTH_SP:bit4;
  RESERVED0      :bit24;
 end;

 TDC_HPD_TOGGLE_FILT_CNTL=bitpacked record
  DC_HPD_CONNECT_INT_DELAY   :bit8;
  RESERVED0                  :bit12;
  DC_HPD_DISCONNECT_INT_DELAY:bit8;
  RESERVED1                  :bit4;
 end;

 TDC_I2C_DDCVGA_HW_STATUS=bitpacked record
  DC_I2C_DDCVGA_HW_STATUS                  :bit2;
  RESERVED0                                :bit1;
  DC_I2C_DDCVGA_HW_DONE                    :bit1;
  RESERVED1                                :bit12;
  DC_I2C_DDCVGA_HW_REQ                     :bit1;
  DC_I2C_DDCVGA_HW_URG                     :bit1;
  RESERVED2                                :bit2;
  DC_I2C_DDCVGA_EDID_DETECT_STATUS         :bit1;
  RESERVED3                                :bit3;
  DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES:bit4;
  DC_I2C_DDCVGA_EDID_DETECT_STATE          :bit3;
  RESERVED4                                :bit1;
 end;

 TDC_I2C_EDID_DETECT_CTRL=bitpacked record
  DC_I2C_EDID_DETECT_WAIT_TIME            :bit16;
  RESERVED0                               :bit4;
  DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID:bit4;
  RESERVED1                               :bit4;
  DC_I2C_EDID_DETECT_SEND_RESET           :bit1;
  RESERVED2                               :bit3;
 end;

 TDC_LUT_BLACK_OFFSET_RED=bitpacked record
  DC_LUT_BLACK_OFFSET_RED:bit16;
  RESERVED0              :bit16;
 end;

 TDC_LUT_WHITE_OFFSET_RED=bitpacked record
  DC_LUT_WHITE_OFFSET_RED:bit16;
  RESERVED0              :bit16;
 end;

 TDENORM_CLAMP_RANGE_B_CB=bitpacked record
  RANGE_CLAMP_MAX_B_CB:bit12;
  RANGE_CLAMP_MIN_B_CB:bit12;
  RESERVED0           :bit8;
 end;

 TDENORM_CLAMP_RANGE_R_CR=bitpacked record
  RANGE_CLAMP_MAX_R_CR:bit12;
  RANGE_CLAMP_MIN_R_CR:bit12;
  RESERVED0           :bit8;
 end;

 TDIG_DISPCLK_SWITCH_CNTL=bitpacked record
  DIG_DISPCLK_SWITCH_POINT:bit1;
  RESERVED0               :bit31;
 end;

 TDIG_FE_TEST_DEBUG_INDEX=bitpacked record
  DIG_FE_TEST_DEBUG_INDEX   :bit8;
  DIG_FE_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0                 :bit23;
 end;

 TDIG_RANDOM_PATTERN_SEED=bitpacked record
  DIG_RANDOM_PATTERN_SEED   :bit24;
  DIG_RAN_PAT_DURING_DE_ONLY:bit1;
  RESERVED0                 :bit7;
 end;

 TDMCU_SMU_INTERRUPT_CNTL=bitpacked record
  DMCU_SMU_STATIC_SCREEN_INT   :bit1;
  RESERVED0                    :bit15;
  DMCU_SMU_STATIC_SCREEN_STATUS:bit16;
 end;

 TDMCU_UC_CLK_GATING_CNTL=bitpacked record
  UC_IRAM_RD_DELAY        :bit3;
  RESERVED0               :bit5;
  UC_ERAM_RD_DELAY        :bit3;
  RESERVED1               :bit5;
  UC_RBBM_RD_CLK_GATING_EN:bit1;
  RESERVED2               :bit15;
 end;

 TDPDBG_CLK_FORCE_CONTROL=bitpacked record
  RESERVED0          :bit4;
  DPDBG_CLK_FORCE_EN :bit1;
  RESERVED1          :bit3;
  DPDBG_CLK_FORCE_SRC:bit3;
  RESERVED2          :bit21;
 end;

 TEXT_OVERSCAN_LEFT_RIGHT=bitpacked record
  EXT_OVERSCAN_RIGHT:bit13;
  RESERVED0         :bit3;
  EXT_OVERSCAN_LEFT :bit13;
  RESERVED1         :bit3;
 end;

 TEXT_OVERSCAN_TOP_BOTTOM=bitpacked record
  EXT_OVERSCAN_BOTTOM:bit13;
  RESERVED0          :bit3;
  EXT_OVERSCAN_TOP   :bit13;
  RESERVED1          :bit3;
 end;

 TGARLIC_COHE_CP_RB0_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_CP_RB1_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_CP_RB2_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_VCE_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_FLUSH_ADDR_END_0=bitpacked record
  RESERVED0:bit2;
  ADDR_END :bit30;
 end;

 TGARLIC_FLUSH_ADDR_END_1=bitpacked record
  RESERVED0:bit2;
  ADDR_END :bit30;
 end;

 TGARLIC_FLUSH_ADDR_END_2=bitpacked record
  RESERVED0:bit2;
  ADDR_END :bit30;
 end;

 TGARLIC_FLUSH_ADDR_END_3=bitpacked record
  RESERVED0:bit2;
  ADDR_END :bit30;
 end;

 TGARLIC_FLUSH_ADDR_END_4=bitpacked record
  RESERVED0:bit2;
  ADDR_END :bit30;
 end;

 TGARLIC_FLUSH_ADDR_END_5=bitpacked record
  RESERVED0:bit2;
  ADDR_END :bit30;
 end;

 TGARLIC_FLUSH_ADDR_END_6=bitpacked record
  RESERVED0:bit2;
  ADDR_END :bit30;
 end;

 TGARLIC_FLUSH_ADDR_END_7=bitpacked record
  RESERVED0:bit2;
  ADDR_END :bit30;
 end;

 TGDS_COMPUTE_MAX_WAVE_ID=bitpacked record
  MAX_WAVE_ID:bit12;
  RESERVED0  :bit20;
 end;

 TGDS_PERFCOUNTER0_SELECT=bitpacked record
  PERFCOUNTER_SELECT :bit10;
  PERFCOUNTER_SELECT1:bit10;
  CNTR_MODE          :bit4;
  RESERVED0          :bit8;
 end;

 TGDS_PERFCOUNTER1_SELECT=bitpacked record
  PERFCOUNTER_SELECT :bit10;
  PERFCOUNTER_SELECT1:bit10;
  CNTR_MODE          :bit4;
  RESERVED0          :bit8;
 end;

 TGDS_PERFCOUNTER2_SELECT=bitpacked record
  PERFCOUNTER_SELECT :bit10;
  PERFCOUNTER_SELECT1:bit10;
  CNTR_MODE          :bit4;
  RESERVED0          :bit8;
 end;

 TGDS_PERFCOUNTER3_SELECT=bitpacked record
  PERFCOUNTER_SELECT :bit10;
  PERFCOUNTER_SELECT1:bit10;
  CNTR_MODE          :bit4;
  RESERVED0          :bit8;
 end;

 TGDS_VM_PROTECTION_FAULT=bitpacked record
  WRITE_DIS     :bit1;
  FAULT_DETECTED:bit1;
  GWS           :bit1;
  OA            :bit1;
  GRBM          :bit1;
  RESERVED0     :bit3;
  VMID          :bit4;
  RESERVED1     :bit4;
  ADDRESS       :bit16;
 end;

 TGENERIC_I2C_TRANSACTION=bitpacked record
  GENERIC_I2C_RW          :bit1;
  RESERVED0               :bit7;
  GENERIC_I2C_STOP_ON_NACK:bit1;
  GENERIC_I2C_ACK_ON_READ :bit1;
  RESERVED1               :bit2;
  GENERIC_I2C_START       :bit1;
  GENERIC_I2C_STOP        :bit1;
  RESERVED2               :bit2;
  GENERIC_I2C_COUNT       :bit4;
  RESERVED3               :bit12;
 end;

 TGRBM_SE0_PERFCOUNTER_HI=bit32;

 TGRBM_SE0_PERFCOUNTER_LO=bit32;

 TGRBM_SE1_PERFCOUNTER_HI=bit32;

 TGRBM_SE1_PERFCOUNTER_LO=bit32;

 TGRBM_SE2_PERFCOUNTER_HI=bit32;

 TGRBM_SE2_PERFCOUNTER_LO=bit32;

 TGRBM_SE3_PERFCOUNTER_HI=bit32;

 TGRBM_SE3_PERFCOUNTER_LO=bit32;

 THDMI_ACR_PACKET_CONTROL=bitpacked record
  HDMI_ACR_SEND          :bit1;
  HDMI_ACR_CONT          :bit1;
  RESERVED0              :bit2;
  HDMI_ACR_SELECT        :bit2;
  RESERVED1              :bit2;
  HDMI_ACR_SOURCE        :bit1;
  RESERVED2              :bit3;
  HDMI_ACR_AUTO_SEND     :bit1;
  RESERVED3              :bit3;
  HDMI_ACR_N_MULTIPLE    :bit3;
  RESERVED4              :bit12;
  HDMI_ACR_AUDIO_PRIORITY:bit1;
 end;

 THDMI_INFOFRAME_CONTROL0=bitpacked record
  HDMI_AVI_INFO_SEND  :bit1;
  HDMI_AVI_INFO_CONT  :bit1;
  RESERVED0           :bit2;
  HDMI_AUDIO_INFO_SEND:bit1;
  HDMI_AUDIO_INFO_CONT:bit1;
  RESERVED1           :bit2;
  HDMI_MPEG_INFO_SEND :bit1;
  HDMI_MPEG_INFO_CONT :bit1;
  RESERVED2           :bit22;
 end;

 THDMI_INFOFRAME_CONTROL1=bitpacked record
  HDMI_AVI_INFO_LINE  :bit6;
  RESERVED0           :bit2;
  HDMI_AUDIO_INFO_LINE:bit6;
  RESERVED1           :bit2;
  HDMI_MPEG_INFO_LINE :bit6;
  RESERVED2           :bit10;
 end;

 THDMI_VBI_PACKET_CONTROL=bitpacked record
  HDMI_NULL_SEND:bit1;
  RESERVED0     :bit3;
  HDMI_GC_SEND  :bit1;
  HDMI_GC_CONT  :bit1;
  RESERVED1     :bit2;
  HDMI_ISRC_SEND:bit1;
  HDMI_ISRC_CONT:bit1;
  RESERVED2     :bit2;
  RESERVED3     :bit1;
  RESERVED4     :bit3;
  HDMI_ISRC_LINE:bit6;
  RESERVED5     :bit2;
  RESERVED6     :bit6;
  RESERVED7     :bit2;
 end;

 THDP_NONSURFACE_PREFETCH=bitpacked record
  NONSURF_PREFETCH_PRI  :bit3;
  NONSURF_PREFETCH_DIR  :bit3;
  NONSURF_PREFETCH_NUM  :bit3;
  NONSURF_PREFETCH_MAX_Z:bit11;
  RESERVED0             :bit7;
  NONSURF_PIPE_CONFIG   :bit5;
 end;

 THDP_XDP_BARS_ADDR_39_36=bitpacked record
  BAR0_ADDR_39_36:bit4;
  BAR1_ADDR_39_36:bit4;
  BAR2_ADDR_39_36:bit4;
  BAR3_ADDR_39_36:bit4;
  BAR4_ADDR_39_36:bit4;
  BAR5_ADDR_39_36:bit4;
  BAR6_ADDR_39_36:bit4;
  BAR7_ADDR_39_36:bit4;
 end;

 THDP_XDP_DIRECT2HDP_LAST=bit32;

 THDP_XDP_FLUSH_ARMED_STS=bit32;

 THDP_XDP_FLUSH_CNTR0_STS=bitpacked record
  FLUSH_CNTR0_STS:bit26;
  RESERVED0      :bit6;
 end;

 TIA_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE3:bit4;
  PERF_MODE2:bit4;
 end;

 TLBV_BUFFER_LEVEL_STATUS=bitpacked record
  REQ_FIFO_LEVEL     :bit6;
  RESERVED0          :bit4;
  REQ_FIFO_FULL_CNTL :bit6;
  DATA_BUFFER_LEVEL  :bit12;
  DATA_FIFO_FULL_CNTL:bit4;
 end;

 TLBV_BUFFER_URGENCY_CTRL=bitpacked record
  LB_BUFFER_URGENCY_MARK_ON :bit12;
  RESERVED0                 :bit4;
  LB_BUFFER_URGENCY_MARK_OFF:bit12;
  RESERVED1                 :bit4;
 end;

 TLBV_KEYER_COLOR_REP_G_Y=bitpacked record
  RESERVED0             :bit4;
  LB_KEYER_COLOR_REP_G_Y:bit12;
  RESERVED1             :bit16;
 end;

 TLB_KEYER_COLOR_REP_B_CB=bitpacked record
  RESERVED0              :bit4;
  LB_KEYER_COLOR_REP_B_CB:bit12;
  RESERVED1              :bit16;
 end;

 TLB_KEYER_COLOR_REP_R_CR=bitpacked record
  RESERVED0              :bit4;
  LB_KEYER_COLOR_REP_R_CR:bit12;
  RESERVED1              :bit16;
 end;

 TMCIF_WB_TEST_DEBUG_DATA=bit32;

 TMC_ARB_GRUB_REALTIME_RD=bitpacked record
  CB0      :bit1;
  CBCMASK0 :bit1;
  CBFMASK0 :bit1;
  DB0      :bit1;
  DBHTILE0 :bit1;
  DBSTEN0  :bit1;
  TC0      :bit1;
  IA       :bit1;
  ACPG     :bit1;
  ACPO     :bit1;
  DMIF     :bit1;
  DMIF_EXT0:bit1;
  DMIF_EXT1:bit1;
  DMIF_TW  :bit1;
  MCIF     :bit1;
  RLC      :bit1;
  VMC      :bit1;
  SDMA1    :bit1;
  SMU      :bit1;
  VCE      :bit1;
  RESERVED0:bit1;
  XDMAM    :bit1;
  SDMA0    :bit1;
  HDP      :bit1;
  UMC      :bit1;
  UVD      :bit1;
  UVD_EXT0 :bit1;
  UVD_EXT1 :bit1;
  SEM      :bit1;
  SAMMSP   :bit1;
  VP8      :bit1;
  ISP      :bit1;
 end;

 TMC_ARB_GRUB_REALTIME_WR=bitpacked record
  CB0      :bit1;
  CBCMASK0 :bit1;
  CBFMASK0 :bit1;
  CBIMMED0 :bit1;
  DB0      :bit1;
  DBHTILE0 :bit1;
  DBSTEN0  :bit1;
  TC0      :bit1;
  SH       :bit1;
  ACPG     :bit1;
  ACPO     :bit1;
  MCIF     :bit1;
  RLC      :bit1;
  SDMA1    :bit1;
  SMU      :bit1;
  VCE      :bit1;
  RESERVED0:bit1;
  SAMMSP   :bit1;
  XDMA     :bit1;
  XDMAM    :bit1;
  SDMA0    :bit1;
  HDP      :bit1;
  UMC      :bit1;
  UVD      :bit1;
  UVD_EXT0 :bit1;
  UVD_EXT1 :bit1;
  XDP      :bit1;
  SEM      :bit1;
  IH       :bit1;
  VP8      :bit1;
  ISP      :bit1;
  RESERVED1:bit1;
 end;

 TMC_ARB_PERFCOUNTER0_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_ARB_PERFCOUNTER1_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_ARB_PERFCOUNTER2_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_ARB_PERFCOUNTER3_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_CITF_CREDITS_ARB_RD2=bitpacked record
  READ_MED :bit8;
  RESERVED0:bit24;
 end;

 TMC_FUS_DRAM_CTL_HIGH_01=bitpacked record
  DCTHIGHADDROFF0:bit12;
  DCTHIGHADDROFF1:bit12;
  RESERVED0      :bit8;
 end;

 TMC_FUS_DRAM_CTL_HIGH_23=bitpacked record
  DCTHIGHADDROFF2:bit12;
  DCTHIGHADDROFF3:bit12;
  RESERVED0      :bit8;
 end;

 TMC_HUB_MISC_IDLE_STATUS=bitpacked record
  OUTSTANDING_GFX_READ    :bit1;
  OUTSTANDING_GFX_WRITE   :bit1;
  OUTSTANDING_RLC_READ    :bit1;
  OUTSTANDING_RLC_WRITE   :bit1;
  OUTSTANDING_SDMA0_READ  :bit1;
  OUTSTANDING_SDMA0_WRITE :bit1;
  OUTSTANDING_SDMA1_READ  :bit1;
  OUTSTANDING_SDMA1_WRITE :bit1;
  OUTSTANDING_DISP_READ   :bit1;
  OUTSTANDING_DISP_WRITE  :bit1;
  OUTSTANDING_UVD_READ    :bit1;
  OUTSTANDING_UVD_WRITE   :bit1;
  OUTSTANDING_SMU_READ    :bit1;
  OUTSTANDING_SMU_WRITE   :bit1;
  OUTSTANDING_HDP_READ    :bit1;
  OUTSTANDING_HDP_WRITE   :bit1;
  OUTSTANDING_OTH_READ    :bit1;
  OUTSTANDING_OTH_WRITE   :bit1;
  OUTSTANDING_VMC_READ    :bit1;
  OUTSTANDING_VMC_WRITE   :bit1;
  OUTSTANDING_VCE_READ    :bit1;
  OUTSTANDING_VCE_WRITE   :bit1;
  OUTSTANDING_ACP_READ    :bit1;
  OUTSTANDING_ACP_WRITE   :bit1;
  OUTSTANDING_SAMMSP_READ :bit1;
  OUTSTANDING_SAMMSP_WRITE:bit1;
  OUTSTANDING_XDMA_READ   :bit1;
  OUTSTANDING_XDMA_WRITE  :bit1;
  OUTSTANDING_ISP_READ    :bit1;
  OUTSTANDING_ISP_WRITE   :bit1;
  OUTSTANDING_VP8_READ    :bit1;
  OUTSTANDING_VP8_WRITE   :bit1;
 end;

 TMC_HUB_PERFCOUNTER0_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_HUB_PERFCOUNTER1_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_HUB_PERFCOUNTER2_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_HUB_PERFCOUNTER3_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_HUB_RDREQ_ACPG_LIMIT=bitpacked record
  ENABLE     :bit2;
  LIMIT_COUNT:bit5;
  RESERVED0  :bit25;
 end;

 TMC_HUB_RDREQ_DMIF_LIMIT=bitpacked record
  ENABLE     :bit2;
  LIMIT_COUNT:bit5;
  RESERVED0  :bit25;
 end;

 TMC_HUB_WDP_CREDITS_MCDS=bitpacked record
  WR_PRI                :bit7;
  WR_PRI_STALL_THRESHOLD:bit7;
  WR_URG                :bit7;
  WR_URG_STALL_THRESHOLD:bit7;
  RESERVED0             :bit4;
 end;

 TMC_HUB_WDP_CREDITS_MCDT=bitpacked record
  WR_PRI                :bit7;
  WR_PRI_STALL_THRESHOLD:bit7;
  WR_URG                :bit7;
  WR_URG_STALL_THRESHOLD:bit7;
  RESERVED0             :bit4;
 end;

 TMC_HUB_WDP_CREDITS_MCDU=bitpacked record
  WR_PRI                :bit7;
  WR_PRI_STALL_THRESHOLD:bit7;
  WR_URG                :bit7;
  WR_URG_STALL_THRESHOLD:bit7;
  RESERVED0             :bit4;
 end;

 TMC_HUB_WDP_CREDITS_MCDV=bitpacked record
  WR_PRI                :bit7;
  WR_PRI_STALL_THRESHOLD:bit7;
  WR_URG                :bit7;
  WR_URG_STALL_THRESHOLD:bit7;
  RESERVED0             :bit4;
 end;

 TMC_HUB_WDP_CREDITS_MCDW=bitpacked record
  WR_PRI                :bit7;
  WR_PRI_STALL_THRESHOLD:bit7;
  WR_URG                :bit7;
  WR_URG_STALL_THRESHOLD:bit7;
  RESERVED0             :bit4;
 end;

 TMC_HUB_WDP_CREDITS_MCDX=bitpacked record
  WR_PRI                :bit7;
  WR_PRI_STALL_THRESHOLD:bit7;
  WR_URG                :bit7;
  WR_URG_STALL_THRESHOLD:bit7;
  RESERVED0             :bit4;
 end;

 TMC_HUB_WDP_CREDITS_MCDY=bitpacked record
  WR_PRI                :bit7;
  WR_PRI_STALL_THRESHOLD:bit7;
  WR_URG                :bit7;
  WR_URG_STALL_THRESHOLD:bit7;
  RESERVED0             :bit4;
 end;

 TMC_HUB_WDP_CREDITS_MCDZ=bitpacked record
  WR_PRI                :bit7;
  WR_PRI_STALL_THRESHOLD:bit7;
  WR_URG                :bit7;
  WR_URG_STALL_THRESHOLD:bit7;
  RESERVED0             :bit4;
 end;

 TMC_MCBVM_PERFCOUNTER_HI=bitpacked record
  COUNTER_HI   :bit16;
  COMPARE_VALUE:bit16;
 end;

 TMC_MCBVM_PERFCOUNTER_LO=bit32;

 TMC_MCDVM_PERFCOUNTER_HI=bitpacked record
  COUNTER_HI   :bit16;
  COMPARE_VALUE:bit16;
 end;

 TMC_MCDVM_PERFCOUNTER_LO=bit32;

 TMC_RPB_PERFCOUNTER0_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_RPB_PERFCOUNTER1_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_RPB_PERFCOUNTER2_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_RPB_PERFCOUNTER3_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_SHARED_ACTIVE_FCN_ID=bitpacked record
  VFID     :bit4;
  RESERVED0:bit27;
  VF       :bit1;
 end;

 TMC_SHARED_BLACKOUT_CNTL=bitpacked record
  BLACKOUT_MODE         :bit3;
  BLACKOUT_SEQ_FREE     :bit1;
  BLACKOUT_MCD_NUM      :bit8;
  FREE_TIE_HIGH         :bit1;
  SRBM_DUMMY_READ_RETURN:bit1;
  RESERVED0             :bit18;
 end;

 TMC_VM_L2_PERFCOUNTER_HI=bitpacked record
  COUNTER_HI   :bit16;
  COMPARE_VALUE:bit16;
 end;

 TMC_VM_L2_PERFCOUNTER_LO=bit32;

 TMC_VM_MB_L1_TLB0_STATUS=bitpacked record
  BUSY     :bit1;
  RESERVED0:bit31;
 end;

 TMC_VM_MB_L1_TLB1_STATUS=bitpacked record
  BUSY     :bit1;
  RESERVED0:bit31;
 end;

 TMC_VM_MB_L1_TLB2_STATUS=bitpacked record
  BUSY     :bit1;
  RESERVED0:bit31;
 end;

 TMC_VM_MB_L1_TLB3_STATUS=bitpacked record
  BUSY     :bit1;
  RESERVED0:bit31;
 end;

 TMC_VM_MD_L1_TLB0_STATUS=bitpacked record
  BUSY     :bit1;
  RESERVED0:bit31;
 end;

 TMC_VM_MD_L1_TLB1_STATUS=bitpacked record
  BUSY     :bit1;
  RESERVED0:bit31;
 end;

 TMC_VM_MD_L1_TLB2_STATUS=bitpacked record
  BUSY     :bit1;
  RESERVED0:bit31;
 end;

 TMC_VM_MD_L1_TLB3_STATUS=bitpacked record
  BUSY     :bit1;
  RESERVED0:bit31;
 end;

 TPA_SC_AA_MASK_X0Y0_X1Y0=bitpacked record
  AA_MASK_X0Y0:bit16;
  AA_MASK_X1Y0:bit16;
 end;

 TPA_SC_AA_MASK_X0Y1_X1Y1=bitpacked record
  AA_MASK_X0Y1:bit16;
  AA_MASK_X1Y1:bit16;
 end;

 TPA_SC_P3D_TRAP_SCREEN_H=bitpacked record
  X_COORD  :bit14;
  RESERVED0:bit18;
 end;

 TPA_SC_P3D_TRAP_SCREEN_V=bitpacked record
  Y_COORD  :bit14;
  RESERVED0:bit18;
 end;

 TPA_SC_SCREEN_SCISSOR_BR=bitpacked record
  BR_X:bit16;
  BR_Y:bit16;
 end;

 TPA_SC_SCREEN_SCISSOR_TL=bitpacked record
  TL_X:bit16;
  TL_Y:bit16;
 end;

 TPA_SC_TRAP_SCREEN_COUNT=bitpacked record
  COUNT    :bit16;
  RESERVED0:bit16;
 end;

 TPA_SC_TRAP_SCREEN_HV_EN=bitpacked record
  ENABLE_HV_PRE_SHADER       :bit1;
  FORCE_PRE_SHADER_ALL_PIXELS:bit1;
  RESERVED0                  :bit30;
 end;

 TPA_SC_WINDOW_SCISSOR_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_WINDOW_SCISSOR_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SU_LINE_STIPPLE_CNTL=bitpacked record
  LINE_STIPPLE_RESET:bit2;
  EXPAND_FULL_LENGTH:bit1;
  FRACTIONAL_ACCUM  :bit1;
  DIAMOND_ADJUST    :bit1;
  RESERVED0         :bit27;
 end;

 TPA_SU_POLY_OFFSET_CLAMP=bit32;

 TPB0_DFT_DEBUG_CTRL_REG0=bitpacked record
  DFT_PHY_DEBUG_EN  :bit1;
  DFT_PHY_DEBUG_MODE:bit5;
  RESERVED0         :bit26;
 end;

 TPB0_RX_LANE10_CTRL_REG0=bitpacked record
  RX_BACKUP_10        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_10:bit2;
  RX_TST_BSCAN_EN_10  :bit1;
  RX_CFG_OVR_PWRSF_10 :bit1;
  RX_TERM_EN_10       :bit1;
  RESERVED1           :bit17;
 end;

 TPB0_RX_LANE11_CTRL_REG0=bitpacked record
  RX_BACKUP_11        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_11:bit2;
  RX_TST_BSCAN_EN_11  :bit1;
  RX_CFG_OVR_PWRSF_11 :bit1;
  RX_TERM_EN_11       :bit1;
  RESERVED1           :bit17;
 end;

 TPB0_RX_LANE12_CTRL_REG0=bitpacked record
  RX_BACKUP_12        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_12:bit2;
  RX_TST_BSCAN_EN_12  :bit1;
  RX_CFG_OVR_PWRSF_12 :bit1;
  RX_TERM_EN_12       :bit1;
  RESERVED1           :bit17;
 end;

 TPB0_RX_LANE13_CTRL_REG0=bitpacked record
  RX_BACKUP_13        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_13:bit2;
  RX_TST_BSCAN_EN_13  :bit1;
  RX_CFG_OVR_PWRSF_13 :bit1;
  RX_TERM_EN_13       :bit1;
  RESERVED1           :bit17;
 end;

 TPB0_RX_LANE14_CTRL_REG0=bitpacked record
  RX_BACKUP_14        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_14:bit2;
  RX_TST_BSCAN_EN_14  :bit1;
  RX_CFG_OVR_PWRSF_14 :bit1;
  RX_TERM_EN_14       :bit1;
  RESERVED1           :bit17;
 end;

 TPB0_RX_LANE15_CTRL_REG0=bitpacked record
  RX_BACKUP_15        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_15:bit2;
  RX_TST_BSCAN_EN_15  :bit1;
  RX_CFG_OVR_PWRSF_15 :bit1;
  RX_TERM_EN_15       :bit1;
  RESERVED1           :bit17;
 end;

 TPB0_TX_LANE10_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_10  :bit1;
  TX_CFG_INV_DATA_10      :bit1;
  TX_CFG_SWING_BOOST_EN_10:bit1;
  TX_DBG_PRBS_EN_10       :bit1;
  RESERVED0               :bit28;
 end;

 TPB0_TX_LANE10_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_10       :bit1;
  TX_DCLK_EN_OVRD_EN_10        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_10   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_10    :bit1;
  TX_DRV_PWRON_OVRD_VAL_10     :bit1;
  TX_DRV_PWRON_OVRD_EN_10      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_10:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_10 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB0_TX_LANE11_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_11  :bit1;
  TX_CFG_INV_DATA_11      :bit1;
  TX_CFG_SWING_BOOST_EN_11:bit1;
  TX_DBG_PRBS_EN_11       :bit1;
  RESERVED0               :bit28;
 end;

 TPB0_TX_LANE11_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_11       :bit1;
  TX_DCLK_EN_OVRD_EN_11        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_11   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_11    :bit1;
  TX_DRV_PWRON_OVRD_VAL_11     :bit1;
  TX_DRV_PWRON_OVRD_EN_11      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_11:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_11 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB0_TX_LANE12_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_12  :bit1;
  TX_CFG_INV_DATA_12      :bit1;
  TX_CFG_SWING_BOOST_EN_12:bit1;
  TX_DBG_PRBS_EN_12       :bit1;
  RESERVED0               :bit28;
 end;

 TPB0_TX_LANE12_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_12       :bit1;
  TX_DCLK_EN_OVRD_EN_12        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_12   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_12    :bit1;
  TX_DRV_PWRON_OVRD_VAL_12     :bit1;
  TX_DRV_PWRON_OVRD_EN_12      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_12:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_12 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB0_TX_LANE13_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_13  :bit1;
  TX_CFG_INV_DATA_13      :bit1;
  TX_CFG_SWING_BOOST_EN_13:bit1;
  TX_DBG_PRBS_EN_13       :bit1;
  RESERVED0               :bit28;
 end;

 TPB0_TX_LANE13_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_13       :bit1;
  TX_DCLK_EN_OVRD_EN_13        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_13   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_13    :bit1;
  TX_DRV_PWRON_OVRD_VAL_13     :bit1;
  TX_DRV_PWRON_OVRD_EN_13      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_13:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_13 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB0_TX_LANE14_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_14  :bit1;
  TX_CFG_INV_DATA_14      :bit1;
  TX_CFG_SWING_BOOST_EN_14:bit1;
  TX_DBG_PRBS_EN_14       :bit1;
  RESERVED0               :bit28;
 end;

 TPB0_TX_LANE14_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_14       :bit1;
  TX_DCLK_EN_OVRD_EN_14        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_14   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_14    :bit1;
  TX_DRV_PWRON_OVRD_VAL_14     :bit1;
  TX_DRV_PWRON_OVRD_EN_14      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_14:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_14 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB0_TX_LANE15_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_15  :bit1;
  TX_CFG_INV_DATA_15      :bit1;
  TX_CFG_SWING_BOOST_EN_15:bit1;
  TX_DBG_PRBS_EN_15       :bit1;
  RESERVED0               :bit28;
 end;

 TPB0_TX_LANE15_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_15       :bit1;
  TX_DCLK_EN_OVRD_EN_15        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_15   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_15    :bit1;
  TX_DRV_PWRON_OVRD_VAL_15     :bit1;
  TX_DRV_PWRON_OVRD_EN_15      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_15:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_15 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB1_DFT_DEBUG_CTRL_REG0=bitpacked record
  DFT_PHY_DEBUG_EN  :bit1;
  DFT_PHY_DEBUG_MODE:bit5;
  RESERVED0         :bit26;
 end;

 TPB1_RX_LANE10_CTRL_REG0=bitpacked record
  RX_BACKUP_10        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_10:bit2;
  RX_TST_BSCAN_EN_10  :bit1;
  RX_CFG_OVR_PWRSF_10 :bit1;
  RX_TERM_EN_10       :bit1;
  RESERVED1           :bit17;
 end;

 TPB1_RX_LANE11_CTRL_REG0=bitpacked record
  RX_BACKUP_11        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_11:bit2;
  RX_TST_BSCAN_EN_11  :bit1;
  RX_CFG_OVR_PWRSF_11 :bit1;
  RX_TERM_EN_11       :bit1;
  RESERVED1           :bit17;
 end;

 TPB1_RX_LANE12_CTRL_REG0=bitpacked record
  RX_BACKUP_12        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_12:bit2;
  RX_TST_BSCAN_EN_12  :bit1;
  RX_CFG_OVR_PWRSF_12 :bit1;
  RX_TERM_EN_12       :bit1;
  RESERVED1           :bit17;
 end;

 TPB1_RX_LANE13_CTRL_REG0=bitpacked record
  RX_BACKUP_13        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_13:bit2;
  RX_TST_BSCAN_EN_13  :bit1;
  RX_CFG_OVR_PWRSF_13 :bit1;
  RX_TERM_EN_13       :bit1;
  RESERVED1           :bit17;
 end;

 TPB1_RX_LANE14_CTRL_REG0=bitpacked record
  RX_BACKUP_14        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_14:bit2;
  RX_TST_BSCAN_EN_14  :bit1;
  RX_CFG_OVR_PWRSF_14 :bit1;
  RX_TERM_EN_14       :bit1;
  RESERVED1           :bit17;
 end;

 TPB1_RX_LANE15_CTRL_REG0=bitpacked record
  RX_BACKUP_15        :bit8;
  RESERVED0           :bit2;
  RX_DBG_ANALOG_SEL_15:bit2;
  RX_TST_BSCAN_EN_15  :bit1;
  RX_CFG_OVR_PWRSF_15 :bit1;
  RX_TERM_EN_15       :bit1;
  RESERVED1           :bit17;
 end;

 TPB1_TX_LANE10_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_10  :bit1;
  TX_CFG_INV_DATA_10      :bit1;
  TX_CFG_SWING_BOOST_EN_10:bit1;
  TX_DBG_PRBS_EN_10       :bit1;
  RESERVED0               :bit28;
 end;

 TPB1_TX_LANE10_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_10       :bit1;
  TX_DCLK_EN_OVRD_EN_10        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_10   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_10    :bit1;
  TX_DRV_PWRON_OVRD_VAL_10     :bit1;
  TX_DRV_PWRON_OVRD_EN_10      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_10:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_10 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB1_TX_LANE11_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_11  :bit1;
  TX_CFG_INV_DATA_11      :bit1;
  TX_CFG_SWING_BOOST_EN_11:bit1;
  TX_DBG_PRBS_EN_11       :bit1;
  RESERVED0               :bit28;
 end;

 TPB1_TX_LANE11_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_11       :bit1;
  TX_DCLK_EN_OVRD_EN_11        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_11   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_11    :bit1;
  TX_DRV_PWRON_OVRD_VAL_11     :bit1;
  TX_DRV_PWRON_OVRD_EN_11      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_11:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_11 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB1_TX_LANE12_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_12  :bit1;
  TX_CFG_INV_DATA_12      :bit1;
  TX_CFG_SWING_BOOST_EN_12:bit1;
  TX_DBG_PRBS_EN_12       :bit1;
  RESERVED0               :bit28;
 end;

 TPB1_TX_LANE12_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_12       :bit1;
  TX_DCLK_EN_OVRD_EN_12        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_12   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_12    :bit1;
  TX_DRV_PWRON_OVRD_VAL_12     :bit1;
  TX_DRV_PWRON_OVRD_EN_12      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_12:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_12 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB1_TX_LANE13_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_13  :bit1;
  TX_CFG_INV_DATA_13      :bit1;
  TX_CFG_SWING_BOOST_EN_13:bit1;
  TX_DBG_PRBS_EN_13       :bit1;
  RESERVED0               :bit28;
 end;

 TPB1_TX_LANE13_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_13       :bit1;
  TX_DCLK_EN_OVRD_EN_13        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_13   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_13    :bit1;
  TX_DRV_PWRON_OVRD_VAL_13     :bit1;
  TX_DRV_PWRON_OVRD_EN_13      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_13:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_13 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB1_TX_LANE14_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_14  :bit1;
  TX_CFG_INV_DATA_14      :bit1;
  TX_CFG_SWING_BOOST_EN_14:bit1;
  TX_DBG_PRBS_EN_14       :bit1;
  RESERVED0               :bit28;
 end;

 TPB1_TX_LANE14_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_14       :bit1;
  TX_DCLK_EN_OVRD_EN_14        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_14   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_14    :bit1;
  TX_DRV_PWRON_OVRD_VAL_14     :bit1;
  TX_DRV_PWRON_OVRD_EN_14      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_14:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_14 :bit1;
  RESERVED0                    :bit24;
 end;

 TPB1_TX_LANE15_CTRL_REG0=bitpacked record
  TX_CFG_DISPCLK_MODE_15  :bit1;
  TX_CFG_INV_DATA_15      :bit1;
  TX_CFG_SWING_BOOST_EN_15:bit1;
  TX_DBG_PRBS_EN_15       :bit1;
  RESERVED0               :bit28;
 end;

 TPB1_TX_LANE15_OVRD_REG0=bitpacked record
  TX_DCLK_EN_OVRD_VAL_15       :bit1;
  TX_DCLK_EN_OVRD_EN_15        :bit1;
  TX_DRV_DATA_EN_OVRD_VAL_15   :bit1;
  TX_DRV_DATA_EN_OVRD_EN_15    :bit1;
  TX_DRV_PWRON_OVRD_VAL_15     :bit1;
  TX_DRV_PWRON_OVRD_EN_15      :bit1;
  TX_FRONTEND_PWRON_OVRD_VAL_15:bit1;
  TX_FRONTEND_PWRON_OVRD_EN_15 :bit1;
  RESERVED0                    :bit24;
 end;

 TPCIE_DEV_SERIAL_NUM_DW1=bit32;

 TPCIE_DEV_SERIAL_NUM_DW2=bit32;

 TPCIE_LC_LINK_WIDTH_CNTL=bitpacked record
  LC_LINK_WIDTH                 :bit3;
  RESERVED0                     :bit1;
  LC_LINK_WIDTH_RD              :bit3;
  LC_RECONFIG_ARC_MISSING_ESCAPE:bit1;
  LC_RECONFIG_NOW               :bit1;
  LC_RENEGOTIATION_SUPPORT      :bit1;
  LC_RENEGOTIATE_EN             :bit1;
  LC_SHORT_RECONFIG_EN          :bit1;
  LC_UPCONFIGURE_SUPPORT        :bit1;
  LC_UPCONFIGURE_DIS            :bit1;
  LC_UPCFG_WAIT_FOR_RCVR_DIS    :bit1;
  LC_UPCFG_TIMER_SEL            :bit1;
  LC_DEASSERT_TX_PDNB           :bit1;
  LC_L1_RECONFIG_EN             :bit1;
  LC_DYNLINK_MST_EN             :bit1;
  LC_DUAL_END_RECONFIG_EN       :bit1;
  LC_UPCONFIGURE_CAPABLE        :bit1;
  LC_DYN_LANES_PWR_STATE        :bit2;
  LC_EQ_REVERSAL_LOGIC_EN       :bit1;
  LC_MULT_REVERSE_ATTEMP_EN     :bit1;
  LC_RESET_TSX_CNT_IN_RCONFIG_EN:bit1;
  LC_WAIT_FOR_L_IDLE_IN_R_IDLE  :bit1;
  RESERVED1                     :bit5;
 end;

 TPCIE_PASID_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_PERF_COUNT0_TXCLK2=bit32;

 TPCIE_PERF_COUNT1_TXCLK2=bit32;

 TPCIE_P_PORT_LANE_STATUS=bitpacked record
  PORT_LANE_REVERSAL:bit1;
  PHY_LINK_WIDTH    :bit6;
  RESERVED0         :bit25;
 end;

 TPCIE_RX_EXPECTED_SEQNUM=bitpacked record
  RX_EXPECTED_SEQNUM:bit12;
  RESERVED0         :bit20;
 end;

 TPCIE_RX_VENDOR_SPECIFIC=bitpacked record
  RX_VENDOR_DATA  :bit24;
  RX_VENDOR_STATUS:bit1;
  RESERVED0       :bit7;
 end;

 TPCIE_SRIOV_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_SRIOV_VF_DEVICE_ID=bitpacked record
  SRIOV_VF_DEVICE_ID:bit16;
  RESERVED0         :bit16;
 end;

 TPCIE_TX_CREDITS_ADVT_NP=bitpacked record
  TX_CREDITS_ADVT_NPD:bit12;
  RESERVED0          :bit4;
  TX_CREDITS_ADVT_NPH:bit8;
  RESERVED1          :bit8;
 end;

 TPCIE_TX_CREDITS_INIT_NP=bitpacked record
  TX_CREDITS_INIT_NPD:bit12;
  RESERVED0          :bit4;
  TX_CREDITS_INIT_NPH:bit8;
  RESERVED1          :bit8;
 end;

 TPCIE_TX_F1_F2_ATTR_CNTL=bitpacked record
  TX_F1_IDO_OVERRIDE_P  :bit2;
  TX_F1_IDO_OVERRIDE_NP :bit2;
  TX_F1_IDO_OVERRIDE_CPL:bit2;
  TX_F1_RO_OVERRIDE_P   :bit2;
  TX_F1_RO_OVERRIDE_NP  :bit2;
  TX_F1_SNR_OVERRIDE_P  :bit2;
  TX_F1_SNR_OVERRIDE_NP :bit2;
  RESERVED0             :bit2;
  TX_F2_IDO_OVERRIDE_P  :bit2;
  TX_F2_IDO_OVERRIDE_NP :bit2;
  TX_F2_IDO_OVERRIDE_CPL:bit2;
  TX_F2_RO_OVERRIDE_P   :bit2;
  TX_F2_RO_OVERRIDE_NP  :bit2;
  TX_F2_SNR_OVERRIDE_P  :bit2;
  TX_F2_SNR_OVERRIDE_NP :bit2;
  RESERVED1             :bit2;
 end;

 TPCIE_TX_VENDOR_SPECIFIC=bitpacked record
  TX_VENDOR_DATA:bit24;
  RESERVED0     :bit8;
 end;

 TPCIE_WRAP_REG_TARG_MISC=bitpacked record
  CLKEN_MASK:bit1;
  RESERVED0 :bit31;
 end;

 TPERFMON_CVALUE_INT_MISC=bitpacked record
  PERFCOUNTER_INT0_STATUS:bit1;
  PERFCOUNTER_INT1_STATUS:bit1;
  PERFCOUNTER_INT2_STATUS:bit1;
  PERFCOUNTER_INT3_STATUS:bit1;
  PERFCOUNTER_INT4_STATUS:bit1;
  PERFCOUNTER_INT5_STATUS:bit1;
  PERFCOUNTER_INT6_STATUS:bit1;
  PERFCOUNTER_INT7_STATUS:bit1;
  PERFCOUNTER_INT0_ACK   :bit1;
  PERFCOUNTER_INT1_ACK   :bit1;
  PERFCOUNTER_INT2_ACK   :bit1;
  PERFCOUNTER_INT3_ACK   :bit1;
  PERFCOUNTER_INT4_ACK   :bit1;
  PERFCOUNTER_INT5_ACK   :bit1;
  PERFCOUNTER_INT6_ACK   :bit1;
  PERFCOUNTER_INT7_ACK   :bit1;
  PERFMON_CVALUE_HI      :bit16;
 end;

 TPERFMON_TEST_DEBUG_DATA=bit32;

 TPWR_DISP_TIMER2_CONTROL=bitpacked record
  DISP_TIMER_INT_COUNT  :bit25;
  DISP_TIMER_INT_ENABLE :bit1;
  DISP_TIMER_INT_DISABLE:bit1;
  DISP_TIMER_INT_MASK   :bit1;
  DISP_TIMER_INT_STAT_AK:bit1;
  DISP_TIMER_INT_TYPE   :bit1;
  DISP_TIMER_INT_MODE   :bit1;
  RESERVED0             :bit1;
 end;

 TPWR_DISP_TIMER_CONTROL2=bitpacked record
  DISP_TIMER_PULSE_WIDTH:bit10;
  RESERVED0             :bit22;
 end;

 TREGAMMA_CNTLA_END_CNTL1=bitpacked record
  REGAMMA_CNTLA_EXP_REGION_END:bit16;
  RESERVED0                   :bit16;
 end;

 TREGAMMA_CNTLA_END_CNTL2=bitpacked record
  REGAMMA_CNTLA_EXP_REGION_END_SLOPE:bit16;
  REGAMMA_CNTLA_EXP_REGION_END_BASE :bit16;
 end;

 TREGAMMA_CNTLB_END_CNTL1=bitpacked record
  REGAMMA_CNTLB_EXP_REGION_END:bit16;
  RESERVED0                   :bit16;
 end;

 TREGAMMA_CNTLB_END_CNTL2=bitpacked record
  REGAMMA_CNTLB_EXP_REGION_END_SLOPE:bit16;
  REGAMMA_CNTLB_EXP_REGION_END_BASE :bit16;
 end;

 TRIRB_LOWER_BASE_ADDRESS=bitpacked record
  RIRB_LOWER_BASE_UNIMPLEMENTED_BITS:bit7;
  RIRB_LOWER_BASE_ADDRESS           :bit25;
 end;

 TRIRB_UPPER_BASE_ADDRESS=bit32;

 TRLC_DRIVER_CPDMA_STATUS=bitpacked record
  DRIVER_REQUEST:bit1;
  RESERVED1     :bit3;
  DRIVER_ACK    :bit1;
  RESERVED      :bit27;
 end;

 TRLC_GPM_INT_DISABLE_TH0=bit32;

 TRLC_GPM_INT_DISABLE_TH1=bit32;

 TRLC_GPM_THREAD_PRIORITY=bitpacked record
  THREAD0_PRIORITY:bit8;
  THREAD1_PRIORITY:bit8;
  THREAD2_PRIORITY:bit8;
  THREAD3_PRIORITY:bit8;
 end;

 TRLC_GPU_CLOCK_COUNT_LSB=bit32;

 TRLC_GPU_CLOCK_COUNT_MSB=bit32;

 TRLC_GPU_IOV_INT_DISABLE=bit32;

 TRLC_PERFCOUNTER0_SELECT=bitpacked record
  PERFCOUNTER_SELECT:bit8;
  RESERVED0         :bit24;
 end;

 TRLC_PERFCOUNTER1_SELECT=bitpacked record
  PERFCOUNTER_SELECT:bit8;
  RESERVED0         :bit24;
 end;

 TRLC_SMU_PG_WAKE_UP_CTRL=bitpacked record
  START_PG_WAKE_UP:bit1;
  SPARE           :bit31;
 end;

 TSCLV_HORZ_FILTER_INIT_C=bitpacked record
  SCL_H_INIT_FRAC_C:bit24;
  SCL_H_INIT_INT_C :bit4;
  RESERVED0        :bit4;
 end;

 TSCLV_VERT_FILTER_INIT_C=bitpacked record
  SCL_V_INIT_FRAC_C:bit24;
  SCL_V_INIT_INT_C :bit3;
  RESERVED0        :bit5;
 end;

 TSCL_HORZ_FILTER_CONTROL=bitpacked record
  SCL_H_FILTER_PICK_NEAREST  :bit1;
  RESERVED0                  :bit7;
  SCL_H_2TAP_HARDCODE_COEF_EN:bit1;
  RESERVED1                  :bit23;
 end;

 TSCL_VERT_FILTER_CONTROL=bitpacked record
  SCL_V_FILTER_PICK_NEAREST  :bit1;
  RESERVED0                  :bit7;
  SCL_V_2TAP_HARDCODE_COEF_EN:bit1;
  RESERVED1                  :bit23;
 end;

 TSDMA0_CONTEXT_REG_TYPE0=bitpacked record
  SDMA0_GFX_RB_CNTL             :bit1;
  SDMA0_GFX_RB_BASE             :bit1;
  SDMA0_GFX_RB_BASE_HI          :bit1;
  SDMA0_GFX_RB_RPTR             :bit1;
  SDMA0_GFX_RB_WPTR             :bit1;
  SDMA0_GFX_RB_WPTR_POLL_CNTL   :bit1;
  SDMA0_GFX_RB_WPTR_POLL_ADDR_HI:bit1;
  SDMA0_GFX_RB_WPTR_POLL_ADDR_LO:bit1;
  SDMA0_GFX_RB_RPTR_ADDR_HI     :bit1;
  SDMA0_GFX_RB_RPTR_ADDR_LO     :bit1;
  SDMA0_GFX_IB_CNTL             :bit1;
  SDMA0_GFX_IB_RPTR             :bit1;
  SDMA0_GFX_IB_OFFSET           :bit1;
  SDMA0_GFX_IB_BASE_LO          :bit1;
  SDMA0_GFX_IB_BASE_HI          :bit1;
  SDMA0_GFX_IB_SIZE             :bit1;
  SDMA0_GFX_SKIP_CNTL           :bit1;
  SDMA0_GFX_CONTEXT_STATUS      :bit1;
  SDMA0_GFX_DOORBELL            :bit1;
  SDMA0_GFX_CONTEXT_CNTL        :bit1;
  RESERVED0                     :bit1;
  RESERVED1                     :bit1;
  RESERVED2                     :bit1;
  RESERVED3                     :bit1;
  RESERVED4                     :bit1;
  RESERVED5                     :bit1;
  RESERVED6                     :bit1;
  RESERVED7                     :bit1;
  RESERVED8                     :bit1;
  RESERVED9                     :bit1;
  RESERVED10                    :bit1;
  RESERVED11                    :bit1;
 end;

 TSDMA0_CONTEXT_REG_TYPE1=bitpacked record
  RESERVED0              :bit1;
  RESERVED1              :bit1;
  RESERVED2              :bit1;
  RESERVED3              :bit1;
  RESERVED4              :bit1;
  RESERVED5              :bit1;
  RESERVED6              :bit1;
  SDMA0_GFX_VIRTUAL_ADDR :bit1;
  SDMA0_GFX_APE1_CNTL    :bit1;
  SDMA0_GFX_DOORBELL_LOG :bit1;
  SDMA0_GFX_WATERMARK    :bit1;
  VOID_REG1              :bit1;
  SDMA0_GFX_CSA_ADDR_LO  :bit1;
  SDMA0_GFX_CSA_ADDR_HI  :bit1;
  VOID_REG2              :bit1;
  SDMA0_GFX_IB_SUB_REMAIN:bit1;
  SDMA0_GFX_PREEMPT      :bit1;
  SDMA0_GFX_DUMMY_REG    :bit1;
  RESERVED               :bit14;
 end;

 TSDMA0_CONTEXT_REG_TYPE2=bitpacked record
  SDMA0_GFX_MIDCMD_DATA0:bit1;
  SDMA0_GFX_MIDCMD_DATA1:bit1;
  SDMA0_GFX_MIDCMD_DATA2:bit1;
  SDMA0_GFX_MIDCMD_DATA3:bit1;
  SDMA0_GFX_MIDCMD_DATA4:bit1;
  SDMA0_GFX_MIDCMD_DATA5:bit1;
  SDMA0_GFX_MIDCMD_CNTL :bit1;
  RESERVED              :bit25;
 end;

 TSDMA0_GFX_IB_SUB_REMAIN=bitpacked record
  SIZE     :bit14;
  RESERVED0:bit18;
 end;

 TSDMA0_RLC0_DOORBELL_LOG=bitpacked record
  BE_ERROR :bit1;
  RESERVED0:bit1;
  DATA     :bit30;
 end;

 TSDMA0_RLC0_MIDCMD_DATA0=bit32;

 TSDMA0_RLC0_MIDCMD_DATA1=bit32;

 TSDMA0_RLC0_MIDCMD_DATA2=bit32;

 TSDMA0_RLC0_MIDCMD_DATA3=bit32;

 TSDMA0_RLC0_MIDCMD_DATA4=bit32;

 TSDMA0_RLC0_MIDCMD_DATA5=bit32;

 TSDMA0_RLC0_VIRTUAL_ADDR=bitpacked record
  ATC        :bit1;
  INVAL      :bit1;
  RESERVED0  :bit2;
  PTR32      :bit1;
  RESERVED1  :bit3;
  SHARED_BASE:bit3;
  RESERVED2  :bit19;
  VM_HOLE    :bit1;
  RESERVED3  :bit1;
 end;

 TSDMA0_RLC1_DOORBELL_LOG=bitpacked record
  BE_ERROR :bit1;
  RESERVED0:bit1;
  DATA     :bit30;
 end;

 TSDMA0_RLC1_MIDCMD_DATA0=bit32;

 TSDMA0_RLC1_MIDCMD_DATA1=bit32;

 TSDMA0_RLC1_MIDCMD_DATA2=bit32;

 TSDMA0_RLC1_MIDCMD_DATA3=bit32;

 TSDMA0_RLC1_MIDCMD_DATA4=bit32;

 TSDMA0_RLC1_MIDCMD_DATA5=bit32;

 TSDMA0_RLC1_VIRTUAL_ADDR=bitpacked record
  ATC        :bit1;
  INVAL      :bit1;
  RESERVED0  :bit2;
  PTR32      :bit1;
  RESERVED1  :bit3;
  SHARED_BASE:bit3;
  RESERVED2  :bit19;
  VM_HOLE    :bit1;
  RESERVED3  :bit1;
 end;

 TSDMA1_CONTEXT_REG_TYPE0=bitpacked record
  SDMA1_GFX_RB_CNTL             :bit1;
  SDMA1_GFX_RB_BASE             :bit1;
  SDMA1_GFX_RB_BASE_HI          :bit1;
  SDMA1_GFX_RB_RPTR             :bit1;
  SDMA1_GFX_RB_WPTR             :bit1;
  SDMA1_GFX_RB_WPTR_POLL_CNTL   :bit1;
  SDMA1_GFX_RB_WPTR_POLL_ADDR_HI:bit1;
  SDMA1_GFX_RB_WPTR_POLL_ADDR_LO:bit1;
  SDMA1_GFX_RB_RPTR_ADDR_HI     :bit1;
  SDMA1_GFX_RB_RPTR_ADDR_LO     :bit1;
  SDMA1_GFX_IB_CNTL             :bit1;
  SDMA1_GFX_IB_RPTR             :bit1;
  SDMA1_GFX_IB_OFFSET           :bit1;
  SDMA1_GFX_IB_BASE_LO          :bit1;
  SDMA1_GFX_IB_BASE_HI          :bit1;
  SDMA1_GFX_IB_SIZE             :bit1;
  SDMA1_GFX_SKIP_CNTL           :bit1;
  SDMA1_GFX_CONTEXT_STATUS      :bit1;
  SDMA1_GFX_DOORBELL            :bit1;
  SDMA1_GFX_CONTEXT_CNTL        :bit1;
  RESERVED                      :bit12;
 end;

 TSDMA1_CONTEXT_REG_TYPE1=bitpacked record
  VOID_REG0              :bit7;
  SDMA1_GFX_VIRTUAL_ADDR :bit1;
  SDMA1_GFX_APE1_CNTL    :bit1;
  SDMA1_GFX_DOORBELL_LOG :bit1;
  SDMA1_GFX_WATERMARK    :bit1;
  VOID_REG2              :bit1;
  SDMA1_GFX_CSA_ADDR_LO  :bit1;
  SDMA1_GFX_CSA_ADDR_HI  :bit1;
  VOID_REG3              :bit1;
  SDMA1_GFX_IB_SUB_REMAIN:bit1;
  SDMA1_GFX_PREEMPT      :bit1;
  SDMA1_GFX_DUMMY_REG    :bit1;
  RESERVED               :bit14;
 end;

 TSDMA1_CONTEXT_REG_TYPE2=bitpacked record
  SDMA1_GFX_MIDCMD_DATA0:bit1;
  SDMA1_GFX_MIDCMD_DATA1:bit1;
  SDMA1_GFX_MIDCMD_DATA2:bit1;
  SDMA1_GFX_MIDCMD_DATA3:bit1;
  SDMA1_GFX_MIDCMD_DATA4:bit1;
  SDMA1_GFX_MIDCMD_DATA5:bit1;
  SDMA1_GFX_MIDCMD_CNTL :bit1;
  RESERVED              :bit25;
 end;

 TSDMA1_GFX_IB_SUB_REMAIN=bitpacked record
  SIZE     :bit14;
  RESERVED0:bit18;
 end;

 TSDMA1_RLC0_DOORBELL_LOG=bitpacked record
  BE_ERROR :bit1;
  RESERVED0:bit1;
  DATA     :bit30;
 end;

 TSDMA1_RLC0_MIDCMD_DATA0=bit32;

 TSDMA1_RLC0_MIDCMD_DATA1=bit32;

 TSDMA1_RLC0_MIDCMD_DATA2=bit32;

 TSDMA1_RLC0_MIDCMD_DATA3=bit32;

 TSDMA1_RLC0_MIDCMD_DATA4=bit32;

 TSDMA1_RLC0_MIDCMD_DATA5=bit32;

 TSDMA1_RLC0_VIRTUAL_ADDR=bitpacked record
  ATC        :bit1;
  INVAL      :bit1;
  RESERVED0  :bit2;
  PTR32      :bit1;
  RESERVED1  :bit3;
  SHARED_BASE:bit3;
  RESERVED2  :bit19;
  VM_HOLE    :bit1;
  RESERVED3  :bit1;
 end;

 TSDMA1_RLC1_DOORBELL_LOG=bitpacked record
  BE_ERROR :bit1;
  RESERVED0:bit1;
  DATA     :bit30;
 end;

 TSDMA1_RLC1_MIDCMD_DATA0=bit32;

 TSDMA1_RLC1_MIDCMD_DATA1=bit32;

 TSDMA1_RLC1_MIDCMD_DATA2=bit32;

 TSDMA1_RLC1_MIDCMD_DATA3=bit32;

 TSDMA1_RLC1_MIDCMD_DATA4=bit32;

 TSDMA1_RLC1_MIDCMD_DATA5=bit32;

 TSDMA1_RLC1_VIRTUAL_ADDR=bitpacked record
  ATC        :bit1;
  INVAL      :bit1;
  RESERVED0  :bit2;
  PTR32      :bit1;
  RESERVED1  :bit3;
  SHARED_BASE:bit3;
  RESERVED2  :bit19;
  VM_HOLE    :bit1;
  RESERVED3  :bit1;
 end;

 TSEM_PERFCOUNTER0_RESULT=bit32;

 TSEM_PERFCOUNTER1_RESULT=bit32;

 TSOFT_REGISTERS_TABLE_10=bit32;

 TSOFT_REGISTERS_TABLE_11=bit32;

 TSOFT_REGISTERS_TABLE_12=bit32;

 TSOFT_REGISTERS_TABLE_13=bit32;

 TSOFT_REGISTERS_TABLE_14=bitpacked record
  DisplayPhy4Config:bit8;
  DisplayPhy3Config:bit8;
  DisplayPhy2Config:bit8;
  DisplayPhy1Config:bit8;
 end;

 TSOFT_REGISTERS_TABLE_15=bitpacked record
  DisplayPhy8Config:bit8;
  DisplayPhy7Config:bit8;
  DisplayPhy6Config:bit8;
  DisplayPhy5Config:bit8;
 end;

 TSOFT_REGISTERS_TABLE_16=bit32;

 TSOFT_REGISTERS_TABLE_17=bit32;

 TSOFT_REGISTERS_TABLE_18=bit32;

 TSOFT_REGISTERS_TABLE_19=bitpacked record
  PCIeDpmEnabledLevels:bit8;
  LClkDpmEnabledLevels:bit8;
  MClkDpmEnabledLevels:bit8;
  SClkDpmEnabledLevels:bit8;
 end;

 TSOFT_REGISTERS_TABLE_20=bitpacked record
  VCEDpmEnabledLevels :bit8;
  ACPDpmEnabledLevels :bit8;
  SAMUDpmEnabledLevels:bit8;
  UVDDpmEnabledLevels :bit8;
 end;

 TSOFT_REGISTERS_TABLE_21=bit32;

 TSOFT_REGISTERS_TABLE_22=bit32;

 TSOFT_REGISTERS_TABLE_23=bit32;

 TSOFT_REGISTERS_TABLE_24=bit32;

 TSOFT_REGISTERS_TABLE_25=bit32;

 TSOFT_REGISTERS_TABLE_26=bit32;

 TSOFT_REGISTERS_TABLE_27=bit32;

 TSOFT_REGISTERS_TABLE_28=bit32;

 TSOFT_REGISTERS_TABLE_29=bit32;

 TSOFT_REGISTERS_TABLE_30=bit32;

 TSPI_COMPUTE_QUEUE_RESET=bitpacked record
  RESET    :bit1;
  RESERVED0:bit31;
 end;

 TSPI_COMPUTE_WF_CTX_SAVE=bitpacked record
  INITIATE         :bit1;
  GDS_INTERRUPT_EN :bit1;
  DONE_INTERRUPT_EN:bit1;
  RESERVED0        :bit27;
  GDS_REQ_BUSY     :bit1;
  SAVE_BUSY        :bit1;
 end;

 TSPI_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL :bit10;
  PERF_SEL1:bit10;
  CNTR_MODE:bit4;
  RESERVED0:bit8;
 end;

 TSPI_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL :bit10;
  PERF_SEL1:bit10;
  CNTR_MODE:bit4;
  RESERVED0:bit8;
 end;

 TSPI_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL :bit10;
  PERF_SEL1:bit10;
  CNTR_MODE:bit4;
  RESERVED0:bit8;
 end;

 TSPI_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL :bit10;
  PERF_SEL1:bit10;
  CNTR_MODE:bit4;
  RESERVED0:bit8;
 end;

 TSPI_PERFCOUNTER4_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit24;
 end;

 TSPI_PERFCOUNTER5_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit24;
 end;

 TSPI_SHADER_PGM_RSRC1_ES=bitpacked record
  VGPRS          :bit6;
  SGPRS          :bit4;
  PRIORITY       :bit2;
  FLOAT_MODE     :bit8;
  PRIV           :bit1;
  DX10_CLAMP     :bit1;
  DEBUG_MODE     :bit1;
  IEEE_MODE      :bit1;
  VGPR_COMP_CNT  :bit2;
  CU_GROUP_ENABLE:bit1;
  CACHE_CTL      :bit3;
  CDBG_USER      :bit1;
  RESERVED0      :bit1;
 end;

 TSPI_SHADER_PGM_RSRC1_GS=bitpacked record
  VGPRS          :bit6;
  SGPRS          :bit4;
  PRIORITY       :bit2;
  FLOAT_MODE     :bit8;
  PRIV           :bit1;
  DX10_CLAMP     :bit1;
  DEBUG_MODE     :bit1;
  IEEE_MODE      :bit1;
  CU_GROUP_ENABLE:bit1;
  CACHE_CTL      :bit3;
  CDBG_USER      :bit1;
  RESERVED0      :bit3;
 end;

 TSPI_SHADER_PGM_RSRC1_HS=bitpacked record
  VGPRS     :bit6;
  SGPRS     :bit4;
  PRIORITY  :bit2;
  FLOAT_MODE:bit8;
  PRIV      :bit1;
  DX10_CLAMP:bit1;
  DEBUG_MODE:bit1;
  IEEE_MODE :bit1;
  CACHE_CTL :bit3;
  CDBG_USER :bit1;
  RESERVED0 :bit4;
 end;

 TSPI_SHADER_PGM_RSRC1_LS=bitpacked record
  VGPRS        :bit6;
  SGPRS        :bit4;
  PRIORITY     :bit2;
  FLOAT_MODE   :bit8;
  PRIV         :bit1;
  DX10_CLAMP   :bit1;
  DEBUG_MODE   :bit1;
  IEEE_MODE    :bit1;
  VGPR_COMP_CNT:bit2;
  CACHE_CTL    :bit3;
  CDBG_USER    :bit1;
  RESERVED0    :bit2;
 end;

 TSPI_SHADER_PGM_RSRC1_PS=bitpacked record
  VGPRS           :bit6;
  SGPRS           :bit4;
  PRIORITY        :bit2;
  FLOAT_MODE      :bit8;
  PRIV            :bit1;
  DX10_CLAMP      :bit1;
  DEBUG_MODE      :bit1;
  IEEE_MODE       :bit1;
  CU_GROUP_DISABLE:bit1;
  CACHE_CTL       :bit3;
  CDBG_USER       :bit1;
  RESERVED0       :bit3;
 end;

 TSPI_SHADER_PGM_RSRC1_VS=bitpacked record
  VGPRS          :bit6;
  SGPRS          :bit4;
  PRIORITY       :bit2;
  FLOAT_MODE     :bit8;
  PRIV           :bit1;
  DX10_CLAMP     :bit1;
  DEBUG_MODE     :bit1;
  IEEE_MODE      :bit1;
  VGPR_COMP_CNT  :bit2;
  CU_GROUP_ENABLE:bit1;
  CACHE_CTL      :bit3;
  CDBG_USER      :bit1;
  RESERVED0      :bit1;
 end;

 TSPI_SHADER_PGM_RSRC2_ES=bitpacked record
  SCRATCH_EN  :bit1;
  USER_SGPR   :bit5;
  TRAP_PRESENT:bit1;
  OC_LDS_EN   :bit1;
  EXCP_EN     :bit9;
  RESERVED0   :bit3;
  LDS_SIZE    :bit9;
  RESERVED1   :bit3;
 end;

 TSPI_SHADER_PGM_RSRC2_GS=bitpacked record
  SCRATCH_EN  :bit1;
  USER_SGPR   :bit5;
  TRAP_PRESENT:bit1;
  EXCP_EN     :bit9;
  RESERVED0   :bit16;
 end;

 TSPI_SHADER_PGM_RSRC2_HS=bitpacked record
  SCRATCH_EN  :bit1;
  USER_SGPR   :bit5;
  TRAP_PRESENT:bit1;
  OC_LDS_EN   :bit1;
  TG_SIZE_EN  :bit1;
  EXCP_EN     :bit9;
  RESERVED0   :bit14;
 end;

 TSPI_SHADER_PGM_RSRC2_LS=bitpacked record
  SCRATCH_EN  :bit1;
  USER_SGPR   :bit5;
  TRAP_PRESENT:bit1;
  LDS_SIZE    :bit9;
  EXCP_EN     :bit9;
  RESERVED0   :bit7;
 end;

 TSPI_SHADER_PGM_RSRC2_PS=bitpacked record
  SCRATCH_EN    :bit1;
  USER_SGPR     :bit5;
  TRAP_PRESENT  :bit1;
  WAVE_CNT_EN   :bit1;
  EXTRA_LDS_SIZE:bit8;
  EXCP_EN       :bit9;
  RESERVED0     :bit7;
 end;

 TSPI_SHADER_PGM_RSRC2_VS=bitpacked record
  SCRATCH_EN      :bit1;
  USER_SGPR       :bit5;
  TRAP_PRESENT    :bit1;
  OC_LDS_EN       :bit1;
  SO_BASE0_EN     :bit1;
  SO_BASE1_EN     :bit1;
  SO_BASE2_EN     :bit1;
  SO_BASE3_EN     :bit1;
  SO_EN           :bit1;
  EXCP_EN         :bit9;
  RESERVED0       :bit2;
  DISPATCH_DRAW_EN:bit1;
  RESERVED1       :bit7;
 end;

 TSPI_SHADER_PGM_RSRC3_ES=bitpacked record
  CU_EN             :bit16;
  WAVE_LIMIT        :bit6;
  LOCK_LOW_THRESHOLD:bit4;
  GROUP_FIFO_DEPTH  :bit6;
 end;

 TSPI_SHADER_PGM_RSRC3_GS=bitpacked record
  CU_EN             :bit16;
  WAVE_LIMIT        :bit6;
  LOCK_LOW_THRESHOLD:bit4;
  GROUP_FIFO_DEPTH  :bit6;
 end;

 TSPI_SHADER_PGM_RSRC3_HS=bitpacked record
  WAVE_LIMIT        :bit6;
  LOCK_LOW_THRESHOLD:bit4;
  GROUP_FIFO_DEPTH  :bit6;
  RESERVED0         :bit16;
 end;

 TSPI_SHADER_PGM_RSRC3_LS=bitpacked record
  CU_EN             :bit16;
  WAVE_LIMIT        :bit6;
  LOCK_LOW_THRESHOLD:bit4;
  GROUP_FIFO_DEPTH  :bit6;
 end;

 TSPI_SHADER_PGM_RSRC3_PS=bitpacked record
  CU_EN             :bit16;
  WAVE_LIMIT        :bit6;
  LOCK_LOW_THRESHOLD:bit4;
  RESERVED0         :bit6;
 end;

 TSPI_SHADER_PGM_RSRC3_VS=bitpacked record
  CU_EN             :bit16;
  WAVE_LIMIT        :bit6;
  LOCK_LOW_THRESHOLD:bit4;
  RESERVED0         :bit6;
 end;

 TSPI_WF_LIFETIME_LIMIT_0=bitpacked record
  MAX_CNT:bit31;
  EN_WARN:bit1;
 end;

 TSPI_WF_LIFETIME_LIMIT_1=bitpacked record
  MAX_CNT:bit31;
  EN_WARN:bit1;
 end;

 TSPI_WF_LIFETIME_LIMIT_2=bitpacked record
  MAX_CNT:bit31;
  EN_WARN:bit1;
 end;

 TSPI_WF_LIFETIME_LIMIT_3=bitpacked record
  MAX_CNT:bit31;
  EN_WARN:bit1;
 end;

 TSPI_WF_LIFETIME_LIMIT_4=bitpacked record
  MAX_CNT:bit31;
  EN_WARN:bit1;
 end;

 TSPI_WF_LIFETIME_LIMIT_5=bitpacked record
  MAX_CNT:bit31;
  EN_WARN:bit1;
 end;

 TSPI_WF_LIFETIME_LIMIT_6=bitpacked record
  MAX_CNT:bit31;
  EN_WARN:bit1;
 end;

 TSPI_WF_LIFETIME_LIMIT_7=bitpacked record
  MAX_CNT:bit31;
  EN_WARN:bit1;
 end;

 TSPI_WF_LIFETIME_LIMIT_8=bitpacked record
  MAX_CNT:bit31;
  EN_WARN:bit1;
 end;

 TSPI_WF_LIFETIME_LIMIT_9=bitpacked record
  MAX_CNT:bit31;
  EN_WARN:bit1;
 end;

 TSPMI_FORCE_CLOCK_GATERS=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit7;
  RESERVED2:bit1;
  RESERVED3:bit23;
 end;

 TSPMI_FSM_READ_TRIGGER_0=bitpacked record
  FSM_READ_TRIGGER:bit1;
  RESERVED0       :bit31;
 end;

 TSQ_PERFCOUNTER10_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER11_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER12_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER13_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER14_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_PERFCOUNTER15_SELECT=bitpacked record
  PERF_SEL       :bit9;
  RESERVED0      :bit3;
  SQC_BANK_MASK  :bit4;
  SQC_CLIENT_MASK:bit4;
  SPM_MODE       :bit4;
  SIMD_MASK      :bit4;
  PERF_MODE      :bit4;
 end;

 TSQ_THREAD_TRACE_HIWATER=bitpacked record
  HIWATER  :bit3;
  RESERVED0:bit29;
 end;

 TSRBM_FIREWALL_ERROR_SRC=bitpacked record
  ACCESS_REQUESTER_BIF           :bit1;
  ACCESS_REQUESTER_ACP           :bit1;
  ACCESS_REQUESTER_SAMSCP        :bit1;
  ACCESS_REQUESTER_SAMMSP        :bit1;
  RESERVED0                      :bit1;
  ACCESS_REQUESTER_TST           :bit1;
  ACCESS_REQUESTER_SDMA3         :bit1;
  ACCESS_REQUESTER_SDMA2         :bit1;
  ACCESS_REQUESTER_SDMA1         :bit1;
  ACCESS_REQUESTER_SDMA0         :bit1;
  ACCESS_REQUESTER_UVD           :bit1;
  ACCESS_REQUESTER_VCE0          :bit1;
  ACCESS_REQUESTER_GRBM          :bit1;
  ACCESS_REQUESTER_SMU           :bit1;
  ACCESS_REQUESTER_PEER          :bit1;
  ACCESS_REQUESTER_CPU           :bit1;
  ACCESS_REQUESTER_ISP           :bit1;
  ACCESS_REQUESTER_VCE1          :bit1;
  ACCESS_REQUESTER_RLCHYP        :bit1;
  ACCESS_REQUESTER_SMUHYP        :bit1;
  ACCESS_REQUESTER_BIFHYP        :bit1;
  RESERVED1                      :bit3;
  RAERR_FIREWALL_VIOLATION       :bit1;
  RAERR_HAR_REGIONSIZE_OVERFLOW  :bit1;
  RAERR_BIF_ADDR_OVERFLOW        :bit1;
  RAERR_P2SRP_REGIONSIZE_OVERFLOW:bit1;
  RAERR_P2SRP_FIREWALL_VIOLATION :bit1;
  RESERVED2                      :bit3;
 end;

 TSX_PERFCOUNTER0_SELECT1=bitpacked record
  PERFCOUNTER_SELECT2:bit10;
  PERFCOUNTER_SELECT3:bit10;
  RESERVED0          :bit12;
 end;

 TSX_PERFCOUNTER1_SELECT1=bitpacked record
  PERFCOUNTER_SELECT2:bit10;
  PERFCOUNTER_SELECT3:bit10;
  RESERVED0          :bit12;
 end;

 TSYS_GRBM_GFX_INDEX_DATA=bitpacked record
  INSTANCE_INDEX           :bit8;
  SH_INDEX                 :bit8;
  SE_INDEX                 :bit8;
  RESERVED0                :bit5;
  SH_BROADCAST_WRITES      :bit1;
  INSTANCE_BROADCAST_WRITES:bit1;
  SE_BROADCAST_WRITES      :bit1;
 end;

 TTA_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2 :bit8;
  RESERVED0 :bit2;
  PERF_SEL3 :bit8;
  RESERVED1 :bit6;
  PERF_MODE3:bit4;
  PERF_MODE2:bit4;
 end;

 TTCA_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TTCA_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TTCA_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit10;
  CNTR_MODE:bit4;
  RESERVED1:bit4;
  PERF_MODE:bit4;
 end;

 TTCA_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit10;
  CNTR_MODE:bit4;
  RESERVED1:bit4;
  PERF_MODE:bit4;
 end;

 TTCC_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TTCC_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TTCC_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit10;
  CNTR_MODE:bit4;
  RESERVED1:bit4;
  PERF_MODE:bit4;
 end;

 TTCC_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit10;
  CNTR_MODE:bit4;
  RESERVED1:bit4;
  PERF_MODE:bit4;
 end;

 TTCP_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TTCP_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TTCP_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit10;
  CNTR_MODE:bit4;
  RESERVED1:bit4;
  PERF_MODE:bit4;
 end;

 TTCP_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit10;
  CNTR_MODE:bit4;
  RESERVED1:bit4;
  PERF_MODE:bit4;
 end;

 TTC_CFG_L2_ATOMIC_POLICY=bitpacked record
  POLICY_0 :bit2;
  POLICY_1 :bit2;
  POLICY_2 :bit2;
  POLICY_3 :bit2;
  POLICY_4 :bit2;
  POLICY_5 :bit2;
  POLICY_6 :bit2;
  POLICY_7 :bit2;
  POLICY_8 :bit2;
  POLICY_9 :bit2;
  POLICY_10:bit2;
  POLICY_11:bit2;
  POLICY_12:bit2;
  POLICY_13:bit2;
  POLICY_14:bit2;
  POLICY_15:bit2;
 end;

 TTC_CFG_L2_STORE_POLICY0=bitpacked record
  POLICY_0 :bit2;
  POLICY_1 :bit2;
  POLICY_2 :bit2;
  POLICY_3 :bit2;
  POLICY_4 :bit2;
  POLICY_5 :bit2;
  POLICY_6 :bit2;
  POLICY_7 :bit2;
  POLICY_8 :bit2;
  POLICY_9 :bit2;
  POLICY_10:bit2;
  POLICY_11:bit2;
  POLICY_12:bit2;
  POLICY_13:bit2;
  POLICY_14:bit2;
  POLICY_15:bit2;
 end;

 TTC_CFG_L2_STORE_POLICY1=bitpacked record
  POLICY_16:bit2;
  POLICY_17:bit2;
  POLICY_18:bit2;
  POLICY_19:bit2;
  POLICY_20:bit2;
  POLICY_21:bit2;
  POLICY_22:bit2;
  POLICY_23:bit2;
  POLICY_24:bit2;
  POLICY_25:bit2;
  POLICY_26:bit2;
  POLICY_27:bit2;
  POLICY_28:bit2;
  POLICY_29:bit2;
  POLICY_30:bit2;
  POLICY_31:bit2;
 end;

 TTD_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2 :bit8;
  RESERVED0 :bit2;
  PERF_SEL3 :bit8;
  RESERVED1 :bit6;
  PERF_MODE3:bit4;
  PERF_MODE2:bit4;
 end;

 TTMDS_DCBALANCER_CONTROL=bitpacked record
  TMDS_DCBALANCER_EN     :bit1;
  RESERVED0              :bit3;
  TMDS_SYNC_DCBAL_EN     :bit3;
  RESERVED1              :bit1;
  TMDS_DCBALANCER_TEST_EN:bit1;
  RESERVED2              :bit7;
  TMDS_DCBALANCER_TEST_IN:bit4;
  RESERVED3              :bit4;
  TMDS_DCBALANCER_FORCE  :bit1;
  RESERVED4              :bit7;
 end;

 TTMDS_STEREOSYNC_CTL_SEL=bitpacked record
  TMDS_STEREOSYNC_CTL_SEL:bit2;
  RESERVED0              :bit30;
 end;

 TUNIPHY_PLL_SS_STEP_SIZE=bitpacked record
  UNIPHY_PLL_SS_STEP_SIZE:bit26;
  RESERVED0              :bit6;
 end;

 TUNIPHY_REG_TEST_OUTPUT2=bitpacked record
  UNIPHY_TX:bit16;
  RESERVED0:bit16;
 end;

 TUNP_GRPH_FLIP_RATE_CNTL=bitpacked record
  GRPH_FLIP_RATE       :bit3;
  GRPH_FLIP_RATE_ENABLE:bit1;
  RESERVED0            :bit28;
 end;

 TUVD_MIF_REF_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit1;
  NUM_GPUS               :bit3;
  RESERVED5              :bit1;
  MULTI_GPU_TILE_SIZE    :bit2;
  RESERVED6              :bit2;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED7              :bit1;
 end;

 TUVD_SEMA_TIMEOUT_STATUS=bitpacked record
  SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT  :bit1;
  SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT       :bit1;
  SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT:bit1;
  SEMAPHORE_TIMEOUT_CLEAR                 :bit1;
  RESERVED0                               :bit28;
 end;

 TUVD_UDEC_DB_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit1;
  NUM_GPUS               :bit3;
  RESERVED5              :bit1;
  MULTI_GPU_TILE_SIZE    :bit2;
  RESERVED6              :bit2;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED7              :bit1;
 end;

 TVGA_DEBUG_READBACK_DATA=bit32;

 TVGA_MEMORY_BASE_ADDRESS=bit32;

 TVGA_MEM_WRITE_PAGE_ADDR=bitpacked record
  VGA_MEM_WRITE_PAGE0_ADDR:bit10;
  RESERVED0               :bit6;
  VGA_MEM_WRITE_PAGE1_ADDR:bit10;
  RESERVED1               :bit6;
 end;

 TVGT_DISPATCH_DRAW_INDEX=bit32;

 TVGT_DMA_DATA_FIFO_DEPTH=bitpacked record
  DMA_DATA_FIFO_DEPTH:bit9;
  DMA2DRAW_FIFO_DEPTH:bit10;
  RESERVED0          :bit13;
 end;

 TVGT_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TVGT_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL  :bit10;
  PERF_SEL1 :bit10;
  CNTR_MODE :bit4;
  PERF_MODE1:bit4;
  PERF_MODE :bit4;
 end;

 TVGT_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit20;
  PERF_MODE:bit4;
 end;

 TVGT_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL :bit8;
  RESERVED0:bit20;
  PERF_MODE:bit4;
 end;

 TVM_L2_BANK_SELECT_MASKA=bitpacked record
  BANK_SELECT_MASK:bit28;
  RESERVED0       :bit4;
 end;

 TVM_L2_BANK_SELECT_MASKB=bitpacked record
  BANK_SELECT_MASK:bit9;
  RESERVED0       :bit23;
 end;

 TXDMA_MSTR_CHANNEL_START=bitpacked record
  XDMA_MSTR_CHANNEL_START_X:bit14;
  RESERVED0                :bit2;
  XDMA_MSTR_CHANNEL_START_Y:bit14;
  RESERVED1                :bit2;
 end;

 TXDMA_MSTR_PERFMEAS_CNTL=bitpacked record
  XDMA_MSTR_CACHE_BW_MEAS_ITER  :bit12;
  XDMA_MSTR_CACHE_BW_SEGID_SEL  :bit5;
  XDMA_MSTR_CACHE_BW_COUNTER_RST:bit1;
  RESERVED0                     :bit1;
  XDMA_MSTR_LT_MEAS_ITER        :bit12;
  XDMA_MSTR_LT_COUNTER_RST      :bit1;
 end;

 TATC_ATS_DEFAULT_PAGE_LOW=bitpacked record
  DEFAULT_PAGE:bit28;
  RESERVED0   :bit4;
 end;

 TATC_VMID10_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID11_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID12_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID13_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID14_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TATC_VMID15_PASID_MAPPING=bitpacked record
  PASID          :bit16;
  RESERVED0      :bit14;
  NO_INVALIDATION:bit1;
  VALID          :bit1;
 end;

 TAZALIA_AUDIO_DTO_CONTROL=bitpacked record
  RESERVED0             :bit8;
  AZALIA_AUDIO_FORCE_DTO:bit2;
  RESERVED1             :bit22;
 end;

 TAZALIA_FIFO_SIZE_CONTROL=bitpacked record
  MIN_FIFO_SIZE      :bit7;
  RESERVED0          :bit1;
  MAX_FIFO_SIZE      :bit7;
  RESERVED1          :bit1;
  MAX_LATENCY_SUPPORT:bit8;
  RESERVED2          :bit8;
 end;

 TAZALIA_INPUT_CRC0_RESULT=bit32;

 TAZALIA_INPUT_CRC1_RESULT=bit32;

 TBIF_RFE_MST_BU_CMDSTATUS=bitpacked record
  REG_BU_clkGate_timer :bit8;
  REG_BU_clkSetup_timer:bit4;
  RESERVED0            :bit4;
  REG_BU_timeout_timer :bit8;
  BU_RFE_mstTimeout    :bit1;
  RESERVED1            :bit7;
 end;

 TBIF_RFE_MST_BX_CMDSTATUS=bitpacked record
  REG_BX_clkGate_timer :bit8;
  REG_BX_clkSetup_timer:bit4;
  RESERVED0            :bit4;
  REG_BX_timeout_timer :bit8;
  BX_RFE_mstTimeout    :bit1;
  RESERVED1            :bit7;
 end;

 TBIF_RFE_MST_TMOUT_STATUS=bitpacked record
  MstTmoutStatus:bit1;
  RESERVED0     :bit31;
 end;

 TBL1_PWM_FINAL_DUTY_CYCLE=bitpacked record
  BL1_PWM_FINAL_DUTY_CYCLE:bit17;
  RESERVED0               :bit15;
 end;

 TBL1_PWM_TARGET_ABM_LEVEL=bitpacked record
  BL1_PWM_TARGET_ABM_LEVEL:bit17;
  RESERVED0               :bit15;
 end;

 TBLND_UNDERFLOW_INTERRUPT=bitpacked record
  BLND_UNDERFLOW_INT_OCCURED   :bit1;
  RESERVED0                    :bit7;
  BLND_UNDERFLOW_INT_ACK       :bit1;
  RESERVED1                    :bit3;
  BLND_UNDERFLOW_INT_MASK      :bit1;
  RESERVED2                    :bit3;
  BLND_UNDERFLOW_INT_PIPE_INDEX:bit2;
  RESERVED3                    :bit14;
 end;

 TCC_GC_SHADER_RATE_CONFIG=bitpacked record
  RESERVED0          :bit1;
  DPFP_RATE          :bit2;
  SQC_BALANCE_DISABLE:bit1;
  HALF_LDS           :bit1;
  RESERVED1          :bit27;
 end;

 TCGTS_CU0_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU0_TA_SQC_CTRL_REG=bitpacked record
  TA                   :bit7;
  TA_OVERRIDE          :bit1;
  TA_BUSY_OVERRIDE     :bit2;
  TA_LS_OVERRIDE       :bit1;
  TA_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  SQC                  :bit7;
  SQC_OVERRIDE         :bit1;
  SQC_BUSY_OVERRIDE    :bit2;
  SQC_LS_OVERRIDE      :bit1;
  SQC_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU0_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU1_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU1_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU2_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU2_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU3_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU3_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU4_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU4_TA_SQC_CTRL_REG=bitpacked record
  TA                   :bit7;
  TA_OVERRIDE          :bit1;
  TA_BUSY_OVERRIDE     :bit2;
  TA_LS_OVERRIDE       :bit1;
  TA_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  SQC                  :bit7;
  SQC_OVERRIDE         :bit1;
  SQC_BUSY_OVERRIDE    :bit2;
  SQC_LS_OVERRIDE      :bit1;
  SQC_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU4_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU5_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU5_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU6_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU6_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU7_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU7_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU8_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU8_TA_SQC_CTRL_REG=bitpacked record
  TA                   :bit7;
  TA_OVERRIDE          :bit1;
  TA_BUSY_OVERRIDE     :bit2;
  TA_LS_OVERRIDE       :bit1;
  TA_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  SQC                  :bit7;
  SQC_OVERRIDE         :bit1;
  SQC_BUSY_OVERRIDE    :bit2;
  SQC_LS_OVERRIDE      :bit1;
  SQC_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU8_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU9_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU9_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCOL_MAN_TEST_DEBUG_INDEX=bitpacked record
  COL_MAN_TEST_DEBUG_INDEX   :bit8;
  COL_MAN_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0                  :bit23;
 end;

 TCOMPUTE_PERFCOUNT_ENABLE=bitpacked record
  PERFCOUNT_ENABLE:bit1;
  RESERVED0       :bit31;
 end;

 TCPC_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2:bit6;
  RESERVED0:bit4;
  PERF_SEL3:bit6;
  RESERVED1:bit16;
 end;

 TCPF_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2:bit6;
  RESERVED0:bit4;
  PERF_SEL3:bit6;
  RESERVED1:bit16;
 end;

 TCPG_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2:bit6;
  RESERVED0:bit4;
  PERF_SEL3:bit6;
  RESERVED1:bit16;
 end;

 TCP_CE_INTR_ROUTINE_START=bitpacked record
  IR_START :bit11;
  RESERVED0:bit21;
 end;

 TCP_CE_METADATA_BASE_ADDR=bit32;

 TCP_DISPATCH_INDR_ADDR_HI=bitpacked record
  ADDR_HI  :bit16;
  RESERVED0:bit16;
 end;

 TCP_HQD_CNTL_STACK_OFFSET=bitpacked record
  RESERVED0:bit2;
  OFFSET   :bit13;
  RESERVED1:bit17;
 end;

 TCP_HQD_PQ_WPTR_POLL_ADDR=bitpacked record
  RESERVED0:bit2;
  WPTR_ADDR:bit30;
 end;

 TCP_MEC1_PRGRM_CNTR_START=bitpacked record
  IP_START :bit16;
  RESERVED0:bit16;
 end;

 TCP_MEC2_PRGRM_CNTR_START=bitpacked record
  IP_START :bit16;
  RESERVED0:bit16;
 end;

 TCP_ME_INTR_ROUTINE_START=bitpacked record
  IR_START :bit12;
  RESERVED0:bit20;
 end;

 TCP_PFP_COMPLETION_STATUS=bitpacked record
  STATUS   :bit2;
  RESERVED0:bit30;
 end;

 TCRTC_PIXEL_DATA_READBACK=bitpacked record
  RESERVED0:bit10;
  RESERVED1:bit10;
  RESERVED2:bit10;
  RESERVED3:bit2;
 end;

 TCRTC_V_UPDATE_INT_STATUS=bitpacked record
  CRTC_V_UPDATE_INT_OCCURRED:bit1;
  RESERVED0                 :bit7;
  CRTC_V_UPDATE_INT_CLEAR   :bit1;
  RESERVED1                 :bit23;
 end;

 TCUR_SURFACE_ADDRESS_HIGH=bitpacked record
  CURSOR_SURFACE_ADDRESS_HIGH:bit8;
  RESERVED0                  :bit24;
 end;

 TDAC_CRC_SIG_CONTROL_MASK=bitpacked record
  DAC_CRC_SIG_CONTROL_MASK:bit6;
  RESERVED0               :bit26;
 end;

 TDAC_MACRO_CNTL_RESERVED0=bit32;

 TDAC_MACRO_CNTL_RESERVED1=bit32;

 TDAC_MACRO_CNTL_RESERVED2=bit32;

 TDAC_MACRO_CNTL_RESERVED3=bit32;

 TDCDEBUG_OUT_PIN_OVERRIDE=bitpacked record
  DCDEBUG_OUT_OVERRIDE1_PIN_SEL   :bit5;
  DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL:bit5;
  RESERVED0                       :bit2;
  DCDEBUG_OUT_OVERRIDE1_EN        :bit1;
  RESERVED1                       :bit2;
  DCDEBUG_OUT_OVERRIDE2_PIN_SEL   :bit5;
  DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL:bit5;
  RESERVED2                       :bit3;
  DCDEBUG_OUT_OVERRIDE2_EN        :bit1;
  RESERVED3                       :bit3;
 end;

 TDCFEV_DMIFV_MEM_PWR_CTRL=bitpacked record
  DMIFV_MEM_PWR_SEL           :bit2;
  DMIFV_MEM_PWR_LUMA_0_FORCE  :bit1;
  DMIFV_MEM_PWR_LUMA_1_FORCE  :bit1;
  DMIFV_MEM_PWR_LUMA_2_FORCE  :bit1;
  DMIFV_MEM_PWR_LUMA_3_FORCE  :bit1;
  DMIFV_MEM_PWR_LUMA_4_FORCE  :bit1;
  DMIFV_MEM_PWR_CHROMA_0_FORCE:bit1;
  DMIFV_MEM_PWR_CHROMA_1_FORCE:bit1;
  DMIFV_MEM_PWR_CHROMA_2_FORCE:bit1;
  DMIFV_MEM_PWR_CHROMA_3_FORCE:bit1;
  DMIFV_MEM_PWR_CHROMA_4_FORCE:bit1;
  RESERVED0                   :bit20;
 end;

 TDC_I2C_INTERRUPT_CONTROL=bitpacked record
  DC_I2C_SW_DONE_INT        :bit1;
  DC_I2C_SW_DONE_ACK        :bit1;
  DC_I2C_SW_DONE_MASK       :bit1;
  RESERVED0                 :bit1;
  DC_I2C_DDC1_HW_DONE_INT   :bit1;
  DC_I2C_DDC1_HW_DONE_ACK   :bit1;
  DC_I2C_DDC1_HW_DONE_MASK  :bit1;
  RESERVED1                 :bit1;
  DC_I2C_DDC2_HW_DONE_INT   :bit1;
  DC_I2C_DDC2_HW_DONE_ACK   :bit1;
  DC_I2C_DDC2_HW_DONE_MASK  :bit1;
  RESERVED2                 :bit1;
  DC_I2C_DDC3_HW_DONE_INT   :bit1;
  DC_I2C_DDC3_HW_DONE_ACK   :bit1;
  DC_I2C_DDC3_HW_DONE_MASK  :bit1;
  RESERVED3                 :bit1;
  DC_I2C_DDC4_HW_DONE_INT   :bit1;
  DC_I2C_DDC4_HW_DONE_ACK   :bit1;
  DC_I2C_DDC4_HW_DONE_MASK  :bit1;
  RESERVED4                 :bit1;
  DC_I2C_DDC5_HW_DONE_INT   :bit1;
  DC_I2C_DDC5_HW_DONE_ACK   :bit1;
  DC_I2C_DDC5_HW_DONE_MASK  :bit1;
  RESERVED5                 :bit1;
  DC_I2C_DDC6_HW_DONE_INT   :bit1;
  DC_I2C_DDC6_HW_DONE_ACK   :bit1;
  DC_I2C_DDC6_HW_DONE_MASK  :bit1;
  DC_I2C_DDCVGA_HW_DONE_INT :bit1;
  DC_I2C_DDCVGA_HW_DONE_ACK :bit1;
  DC_I2C_DDCVGA_HW_DONE_MASK:bit1;
  RESERVED6                 :bit2;
 end;

 TDC_LUT_BLACK_OFFSET_BLUE=bitpacked record
  DC_LUT_BLACK_OFFSET_BLUE:bit16;
  RESERVED0               :bit16;
 end;

 TDC_LUT_VGA_ACCESS_ENABLE=bitpacked record
  DC_LUT_VGA_ACCESS_ENABLE:bit1;
  RESERVED0               :bit31;
 end;

 TDC_LUT_WHITE_OFFSET_BLUE=bitpacked record
  DC_LUT_WHITE_OFFSET_BLUE:bit16;
  RESERVED0               :bit16;
 end;

 TDISPCLK_FREQ_CHANGE_CNTL=bitpacked record
  DISPCLK_STEP_DELAY          :bit14;
  RESERVED0                   :bit2;
  DISPCLK_STEP_SIZE           :bit4;
  DISPCLK_FREQ_RAMP_DONE      :bit1;
  RESERVED1                   :bit4;
  DISPCLK_MAX_ERRDET_CYCLES   :bit3;
  DCCG_FIFO_ERRDET_RESET      :bit1;
  DCCG_FIFO_ERRDET_STATE      :bit1;
  DCCG_FIFO_ERRDET_OVR_EN     :bit1;
  DISPCLK_CHG_FWD_CORR_DISABLE:bit1;
 end;

 TDMIF_ARBITRATION_CONTROL=bitpacked record
  DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD:bit16;
  PIPE_SWITCH_EFFICIENCY_WEIGHT          :bit16;
 end;

 TDPG_PIPE_STUTTER_CONTROL=bitpacked record
  STUTTER_ENABLE                     :bit1;
  RESERVED0                          :bit3;
  STUTTER_IGNORE_CURSOR              :bit1;
  STUTTER_IGNORE_ICON                :bit1;
  STUTTER_IGNORE_VGA                 :bit1;
  STUTTER_IGNORE_FBC                 :bit1;
  STUTTER_WM_HIGH_FORCE_ON           :bit1;
  STUTTER_WM_HIGH_EXCLUDES_VBLANK    :bit1;
  STUTTER_URGENT_IN_NOT_SELF_REFRESH :bit1;
  STUTTER_SELF_REFRESH_FORCE_ON      :bit1;
  RESERVED1                          :bit4;
  STUTTER_EXIT_SELF_REFRESH_WATERMARK:bit16;
 end;

 TDPG_PIPE_URGENCY_CONTROL=bitpacked record
  URGENCY_LOW_WATERMARK :bit16;
  URGENCY_HIGH_WATERMARK:bit16;
 end;

 TFBC_CSM_REGION_OFFSET_01=bitpacked record
  FBC_CSM_REGION_OFFSET_0:bit10;
  RESERVED0              :bit6;
  FBC_CSM_REGION_OFFSET_1:bit10;
  RESERVED1              :bit6;
 end;

 TFBC_CSM_REGION_OFFSET_23=bitpacked record
  FBC_CSM_REGION_OFFSET_2:bit10;
  RESERVED0              :bit6;
  FBC_CSM_REGION_OFFSET_3:bit10;
  RESERVED1              :bit6;
 end;

 TFMT_CRC_SIG_BLUE_CONTROL=bitpacked record
  FMT_CRC_SIG_BLUE   :bit16;
  FMT_CRC_SIG_CONTROL:bit16;
 end;

 TGARLIC_COHE_VCE_RB_WPTR2=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGDS_PERFCOUNTER0_SELECT1=bitpacked record
  PERFCOUNTER_SELECT2:bit10;
  PERFCOUNTER_SELECT3:bit10;
  RESERVED0          :bit12;
 end;

 TGPIOPAD_EXTERN_TRIG_CNTL=bitpacked record
  EXTERN_TRIG_SEL :bit5;
  EXTERN_TRIG_CLR :bit1;
  EXTERN_TRIG_READ:bit1;
  RESERVED0       :bit25;
 end;

 TGRBM_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL                   :bit6;
  RESERVED0                  :bit4;
  DB_CLEAN_USER_DEFINED_MASK :bit1;
  CB_CLEAN_USER_DEFINED_MASK :bit1;
  VGT_BUSY_USER_DEFINED_MASK :bit1;
  TA_BUSY_USER_DEFINED_MASK  :bit1;
  SX_BUSY_USER_DEFINED_MASK  :bit1;
  RESERVED1                  :bit1;
  SPI_BUSY_USER_DEFINED_MASK :bit1;
  SC_BUSY_USER_DEFINED_MASK  :bit1;
  PA_BUSY_USER_DEFINED_MASK  :bit1;
  GRBM_BUSY_USER_DEFINED_MASK:bit1;
  DB_BUSY_USER_DEFINED_MASK  :bit1;
  CB_BUSY_USER_DEFINED_MASK  :bit1;
  CP_BUSY_USER_DEFINED_MASK  :bit1;
  IA_BUSY_USER_DEFINED_MASK  :bit1;
  GDS_BUSY_USER_DEFINED_MASK :bit1;
  BCI_BUSY_USER_DEFINED_MASK :bit1;
  RLC_BUSY_USER_DEFINED_MASK :bit1;
  TC_BUSY_USER_DEFINED_MASK  :bit1;
  WD_BUSY_USER_DEFINED_MASK  :bit1;
  RESERVED2                  :bit3;
 end;

 TGRBM_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL                   :bit6;
  RESERVED0                  :bit4;
  DB_CLEAN_USER_DEFINED_MASK :bit1;
  CB_CLEAN_USER_DEFINED_MASK :bit1;
  VGT_BUSY_USER_DEFINED_MASK :bit1;
  TA_BUSY_USER_DEFINED_MASK  :bit1;
  SX_BUSY_USER_DEFINED_MASK  :bit1;
  RESERVED1                  :bit1;
  SPI_BUSY_USER_DEFINED_MASK :bit1;
  SC_BUSY_USER_DEFINED_MASK  :bit1;
  PA_BUSY_USER_DEFINED_MASK  :bit1;
  GRBM_BUSY_USER_DEFINED_MASK:bit1;
  DB_BUSY_USER_DEFINED_MASK  :bit1;
  CB_BUSY_USER_DEFINED_MASK  :bit1;
  CP_BUSY_USER_DEFINED_MASK  :bit1;
  IA_BUSY_USER_DEFINED_MASK  :bit1;
  GDS_BUSY_USER_DEFINED_MASK :bit1;
  BCI_BUSY_USER_DEFINED_MASK :bit1;
  RLC_BUSY_USER_DEFINED_MASK :bit1;
  TC_BUSY_USER_DEFINED_MASK  :bit1;
  WD_BUSY_USER_DEFINED_MASK  :bit1;
  RESERVED2                  :bit3;
 end;

 THDP_XDP_DIRECT2HDP_FIRST=bit32;

 TIMMEDIATE_COMMAND_STATUS=bitpacked record
  IMMEDIATE_COMMAND_BUSY:bit1;
  IMMEDIATE_RESULT_VALID:bit1;
  RESERVED0             :bit30;
 end;

 TINPUT_PAYLOAD_CAPABILITY=bitpacked record
  INPUT_PAYLOAD_CAPABILITY:bit16;
  RESERVED0               :bit16;
 end;

 TLBV_KEYER_COLOR_REP_B_CB=bitpacked record
  RESERVED0              :bit4;
  LB_KEYER_COLOR_REP_B_CB:bit12;
  RESERVED1              :bit16;
 end;

 TLBV_KEYER_COLOR_REP_R_CR=bitpacked record
  RESERVED0              :bit4;
  LB_KEYER_COLOR_REP_R_CR:bit12;
  RESERVED1              :bit16;
 end;

 TLB_BUFFER_URGENCY_STATUS=bitpacked record
  LB_BUFFER_URGENCY_LEVEL:bit12;
  RESERVED0              :bit4;
  LB_BUFFER_URGENCY_STAT :bit1;
  RESERVED1              :bit15;
 end;

 TLOW_POWER_TILING_CONTROL=bitpacked record
  LOW_POWER_TILING_ENABLE              :bit1;
  RESERVED0                            :bit2;
  LOW_POWER_TILING_MODE                :bit2;
  LOW_POWER_TILING_NUM_PIPES           :bit3;
  LOW_POWER_TILING_NUM_BANKS           :bit3;
  LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE:bit1;
  LOW_POWER_TILING_ROW_SIZE            :bit3;
  RESERVED1                            :bit1;
  LOW_POWER_TILING_ROWS_PER_CHAN       :bit12;
  RESERVED2                            :bit4;
 end;

 TMCIF_WB_TEST_DEBUG_INDEX=bitpacked record
  MCIF_WB_TEST_DEBUG_INDEX   :bit8;
  MCIF_WB_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0                  :bit23;
 end;

 TMC_ARB_GRUB_PRIORITY1_RD=bitpacked record
  CB0      :bit2;
  CBCMASK0 :bit2;
  CBFMASK0 :bit2;
  DB0      :bit2;
  DBHTILE0 :bit2;
  DBSTEN0  :bit2;
  TC0      :bit2;
  ACPG     :bit2;
  ACPO     :bit2;
  DMIF     :bit2;
  DMIF_EXT0:bit2;
  DMIF_EXT1:bit2;
  DMIF_TW  :bit2;
  MCIF     :bit2;
  RLC      :bit2;
  VMC      :bit2;
 end;

 TMC_ARB_GRUB_PRIORITY1_WR=bitpacked record
  CB0     :bit2;
  CBCMASK0:bit2;
  CBFMASK0:bit2;
  CBIMMED0:bit2;
  DB0     :bit2;
  DBHTILE0:bit2;
  DBSTEN0 :bit2;
  TC0     :bit2;
  SH      :bit2;
  ACPG    :bit2;
  ACPO    :bit2;
  MCIF    :bit2;
  RLC     :bit2;
  SDMA1   :bit2;
  SMU     :bit2;
  VCE     :bit2;
 end;

 TMC_ARB_GRUB_PRIORITY2_RD=bitpacked record
  SDMA1    :bit2;
  SMU      :bit2;
  VCE      :bit2;
  RESERVED0:bit2;
  XDMAM    :bit2;
  SDMA0    :bit2;
  HDP      :bit2;
  UMC      :bit2;
  UVD      :bit2;
  UVD_EXT0 :bit2;
  UVD_EXT1 :bit2;
  SEM      :bit2;
  SAMMSP   :bit2;
  VP8      :bit2;
  ISP      :bit2;
  RSV2     :bit2;
 end;

 TMC_ARB_GRUB_PRIORITY2_WR=bitpacked record
  RESERVED0:bit2;
  SAMMSP   :bit2;
  XDMA     :bit2;
  XDMAM    :bit2;
  SDMA0    :bit2;
  HDP      :bit2;
  UMC      :bit2;
  UVD      :bit2;
  UVD_EXT0 :bit2;
  UVD_EXT1 :bit2;
  XDP      :bit2;
  SEM      :bit2;
  IH       :bit2;
  VP8      :bit2;
  ISP      :bit2;
  RESERVED1:bit2;
 end;

 TMC_CITF_PERFCOUNTER0_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_CITF_PERFCOUNTER1_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_CITF_PERFCOUNTER2_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_CITF_PERFCOUNTER3_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_FUS_ARB_GARLIC_WR_PRI=bitpacked record
  CB_WR_PRI  :bit2;
  DB_WR_PRI  :bit2;
  TC_WR_PRI  :bit2;
  CP_WR_PRI  :bit2;
  HDP_WR_PRI :bit2;
  XDP_WR_PRI :bit2;
  UMC_WR_PRI :bit2;
  UVD_WR_PRI :bit2;
  RLC_WR_PRI :bit2;
  IH_WR_PRI  :bit2;
  SDMA_WR_PRI:bit2;
  SEM_WR_PRI :bit2;
  SH_WR_PRI  :bit2;
  MCIF_WR_PRI:bit2;
  VCE_WR_PRI :bit2;
  VCEU_WR_PRI:bit2;
 end;

 TMC_GRUB_PERFCOUNTER0_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_GRUB_PERFCOUNTER1_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_GRUB_POST_PROBE_DELAY=bitpacked record
  REQ_TO_RSP_DELAY   :bit5;
  RESERVED0          :bit3;
  REQLCL_TO_RET_DELAY:bit5;
  RESERVED1          :bit3;
  REQREM_TO_RET_DELAY:bit5;
  RESERVED2          :bit11;
 end;

 TMC_HUB_RDREQ_BYPASS_GBL0=bitpacked record
  ENABLE   :bit1;
  CID1     :bit8;
  CID2     :bit8;
  RESERVED0:bit15;
 end;

 TMC_RPB_CID_QUEUE_EX_DATA=bitpacked record
  WRITE_ENTRIES:bit16;
  READ_ENTRIES :bit16;
 end;

 TMC_RPB_PERF_COUNTER_CNTL=bitpacked record
  PERF_COUNTER_SELECT        :bit2;
  CLEAR_SELECTED_PERF_COUNTER:bit1;
  CLEAR_ALL_PERF_COUNTERS    :bit1;
  STOP_ON_COUNTER_SATURATION :bit1;
  ENABLE_PERF_COUNTERS       :bit4;
  PERF_COUNTER_ASSIGN_0      :bit5;
  PERF_COUNTER_ASSIGN_1      :bit5;
  PERF_COUNTER_ASSIGN_2      :bit5;
  PERF_COUNTER_ASSIGN_3      :bit5;
  RESERVED0                  :bit3;
 end;

 TMC_SEQ_TRAIN_WAKEUP_CNTL=bitpacked record
  RESERVED0                :bit1;
  RESERVED1                :bit1;
  RESERVED2                :bit1;
  RESERVED3                :bit1;
  RESERVED4                :bit1;
  RESERVED5                :bit1;
  AUTO_REFRESH_WAKEUP_EARLY:bit1;
  SW_WAKEUP                :bit1;
  BLOCK_ARB_RD_D0          :bit1;
  BLOCK_ARB_RD_D1          :bit1;
  RESERVED6                :bit1;
  RESERVED7                :bit1;
  BLOCK_ARB_WR_D0          :bit1;
  BLOCK_ARB_WR_D1          :bit1;
  RESERVED8                :bit1;
  RESERVED9                :bit1;
  RESERVED10               :bit1;
  RESERVED11               :bit1;
  RESERVED12               :bit1;
  RESERVED13               :bit1;
  TRAIN_DONE_D0            :bit1;
  TRAIN_DONE_D1            :bit1;
  RESERVED14               :bit1;
  RESERVED15               :bit1;
  RESERVED16               :bit8;
 end;

 TMC_SEQ_TRAIN_WAKEUP_EDGE=bitpacked record
  D0_IDLEH_WAKEUP       :bit1;
  D1_IDLEH_WAKEUP       :bit1;
  RESERVED0             :bit1;
  RESERVED1             :bit1;
  RESERVED2             :bit1;
  RESERVED3             :bit1;
  RESERVED4             :bit1;
  RESERVED5             :bit1;
  SCLK_SRBM_READY_WAKEUP:bit1;
  RESERVED6             :bit1;
  RESERVED7             :bit1;
  RESERVED8             :bit1;
  SOFTWARE_WAKEUP       :bit1;
  RESERVED9             :bit1;
  RESERVED10            :bit1;
  TIMER_DONE_WAKEUP     :bit1;
  RESERVED11            :bit1;
  RESERVED12            :bit1;
  RESERVED13            :bit1;
  RESERVED14            :bit1;
  RESERVED15            :bit1;
  RESERVED16            :bit1;
  RESERVED17            :bit1;
  RESERVED18            :bit1;
  RESERVED19            :bit1;
  RESERVED20            :bit1;
  RESERVED21            :bit1;
  RESERVED22            :bit1;
  RESERVED23            :bit4;
 end;

 TMC_SEQ_TRAIN_WAKEUP_MASK=bitpacked record
  D0_IDLEH_WAKEUP       :bit1;
  D1_IDLEH_WAKEUP       :bit1;
  RESERVED0             :bit1;
  RESERVED1             :bit1;
  RESERVED2             :bit1;
  RESERVED3             :bit1;
  RESERVED4             :bit1;
  RESERVED5             :bit1;
  SCLK_SRBM_READY_WAKEUP:bit1;
  RESERVED6             :bit1;
  RESERVED7             :bit1;
  RESERVED8             :bit1;
  SOFTWARE_WAKEUP       :bit1;
  RESERVED9             :bit1;
  RESERVED10            :bit1;
  TIMER_DONE_WAKEUP     :bit1;
  RESERVED11            :bit1;
  RESERVED12            :bit1;
  RESERVED13            :bit1;
  RESERVED14            :bit1;
  RESERVED15            :bit1;
  RESERVED16            :bit1;
  RESERVED17            :bit1;
  RESERVED18            :bit1;
  RESERVED19            :bit1;
  RESERVED20            :bit1;
  RESERVED21            :bit1;
  RESERVED22            :bit1;
  RESERVED23            :bit4;
 end;

 TMC_SHARED_VIRT_RESET_REQ=bitpacked record
  VF       :bit16;
  RESERVED0:bit15;
  PF       :bit1;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF0=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF1=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF2=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF3=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF4=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF5=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF6=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF7=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF8=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF9=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_XBAR_RDREQ_PRI_CREDIT=bitpacked record
  OUT0:bit8;
  OUT1:bit8;
  OUT2:bit8;
  OUT3:bit8;
 end;

 TMVP_FLIP_LINE_NUM_INSERT=bitpacked record
  MVP_FLIP_LINE_NUM_INSERT_MODE:bit2;
  RESERVED0                    :bit6;
  MVP_FLIP_LINE_NUM_INSERT     :bit15;
  RESERVED1                    :bit1;
  MVP_FLIP_LINE_NUM_OFFSET     :bit6;
  MVP_FLIP_AUTO_ENABLE         :bit1;
  RESERVED2                    :bit1;
 end;

 TOVL_SURFACE_ADDRESS_HIGH=bitpacked record
  OVL_SURFACE_ADDRESS_HIGH:bit8;
  RESERVED0               :bit24;
 end;

 TPA_SC_FORCE_EOV_MAX_CNTS=bitpacked record
  FORCE_EOV_MAX_CLK_CNT:bit16;
  FORCE_EOV_MAX_REZ_CNT:bit16;
 end;

 TPA_SC_GENERIC_SCISSOR_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_GENERIC_SCISSOR_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_HP3D_TRAP_SCREEN_H=bitpacked record
  X_COORD  :bit14;
  RESERVED0:bit18;
 end;

 TPA_SC_HP3D_TRAP_SCREEN_V=bitpacked record
  Y_COORD  :bit14;
  RESERVED0:bit18;
 end;

 TPA_SC_LINE_STIPPLE_STATE=bitpacked record
  CURRENT_PTR  :bit4;
  RESERVED0    :bit4;
  CURRENT_COUNT:bit8;
  RESERVED1    :bit16;
 end;

 TPA_SC_VPORT_SCISSOR_0_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_0_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_1_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_1_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_2_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_2_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_3_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_3_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_4_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_4_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_5_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_5_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_6_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_6_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_7_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_7_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_8_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_8_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_9_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_9_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SU_LINE_STIPPLE_SCALE=bit32;

 TPA_SU_LINE_STIPPLE_VALUE=bitpacked record
  LINE_STIPPLE_VALUE:bit24;
  RESERVED0         :bit8;
 end;

 TPB0_PIF_CMD_BUS_GLB_OVRD=bitpacked record
  TXMARG_OVRD_EN       :bit1;
  DEEMPH_OVRD_EN       :bit1;
  PLLFREQ_OVRD_EN      :bit1;
  TXMARG               :bit3;
  DEEMPH               :bit1;
  PLLFREQ              :bit2;
  RESPONSEMODE_PIF_OVRD:bit1;
  RESERVED0            :bit6;
  CMD_BUS_LANE_DIS_0   :bit1;
  CMD_BUS_LANE_DIS_1   :bit1;
  CMD_BUS_LANE_DIS_2   :bit1;
  CMD_BUS_LANE_DIS_3   :bit1;
  CMD_BUS_LANE_DIS_4   :bit1;
  CMD_BUS_LANE_DIS_5   :bit1;
  CMD_BUS_LANE_DIS_6   :bit1;
  CMD_BUS_LANE_DIS_7   :bit1;
  RESERVED1            :bit1;
  RESERVED2            :bit1;
  RESERVED3            :bit1;
  RESERVED4            :bit1;
  RESERVED5            :bit1;
  RESERVED6            :bit1;
  RESERVED7            :bit1;
  RESERVED8            :bit1;
 end;

 TPB0_PLL_RO_GLB_CTRL_REG0=bitpacked record
  PLL_TST_LOSPDTST_SRC               :bit1;
  PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 :bit1;
  PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 :bit1;
  PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 :bit1;
  PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0:bit1;
  PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1:bit1;
  PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2:bit1;
  PLL_RO_PWRON_LUT_ENTRY_LS2         :bit1;
  PLL_LC_PWRON_LUT_ENTRY_LS2         :bit1;
  PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 :bit1;
  PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 :bit1;
  PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 :bit1;
  PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0:bit1;
  PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1:bit1;
  PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2:bit1;
  PLL_RO_HSCLK_LEFT_EN_GATING_EN     :bit1;
  PLL_RO_HSCLK_RIGHT_EN_GATING_EN    :bit1;
  PLL_LC_HSCLK_LEFT_EN_GATING_EN     :bit1;
  PLL_LC_HSCLK_RIGHT_EN_GATING_EN    :bit1;
  RESERVED0                          :bit13;
 end;

 TPB1_PIF_CMD_BUS_GLB_OVRD=bitpacked record
  TXMARG_OVRD_EN       :bit1;
  DEEMPH_OVRD_EN       :bit1;
  PLLFREQ_OVRD_EN      :bit1;
  TXMARG               :bit3;
  DEEMPH               :bit1;
  PLLFREQ              :bit2;
  RESPONSEMODE_PIF_OVRD:bit1;
  RESERVED0            :bit6;
  CMD_BUS_LANE_DIS_0   :bit1;
  CMD_BUS_LANE_DIS_1   :bit1;
  CMD_BUS_LANE_DIS_2   :bit1;
  CMD_BUS_LANE_DIS_3   :bit1;
  CMD_BUS_LANE_DIS_4   :bit1;
  CMD_BUS_LANE_DIS_5   :bit1;
  CMD_BUS_LANE_DIS_6   :bit1;
  CMD_BUS_LANE_DIS_7   :bit1;
  RESERVED1            :bit1;
  RESERVED2            :bit1;
  RESERVED3            :bit1;
  RESERVED4            :bit1;
  RESERVED5            :bit1;
  RESERVED6            :bit1;
  RESERVED7            :bit1;
  RESERVED8            :bit1;
 end;

 TPB1_PLL_RO_GLB_CTRL_REG0=bitpacked record
  PLL_TST_LOSPDTST_SRC               :bit1;
  PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 :bit1;
  PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 :bit1;
  PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 :bit1;
  PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0:bit1;
  PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1:bit1;
  PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2:bit1;
  PLL_RO_PWRON_LUT_ENTRY_LS2         :bit1;
  PLL_LC_PWRON_LUT_ENTRY_LS2         :bit1;
  PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 :bit1;
  PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 :bit1;
  PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 :bit1;
  PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0:bit1;
  PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1:bit1;
  PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2:bit1;
  PLL_RO_HSCLK_LEFT_EN_GATING_EN     :bit1;
  PLL_RO_HSCLK_RIGHT_EN_GATING_EN    :bit1;
  PLL_LC_HSCLK_LEFT_EN_GATING_EN     :bit1;
  PLL_LC_HSCLK_RIGHT_EN_GATING_EN    :bit1;
  RESERVED0                          :bit13;
 end;

 TPCIE_I2C_REG_ADDR_EXPAND=bitpacked record
  I2C_REG_ADDR:bit17;
  RESERVED0   :bit4;
  RESERVED1   :bit4;
  RESERVED2   :bit7;
 end;

 TPCIE_LC_BEST_EQ_SETTINGS=bitpacked record
  LC_BEST_PRESET    :bit4;
  LC_BEST_PRECURSOR :bit6;
  LC_BEST_CURSOR    :bit6;
  LC_BEST_POSTCURSOR:bit6;
  LC_BEST_FOM       :bit8;
  RESERVED0         :bit2;
 end;

 TPCIE_PERF_CNTL_MST_C_CLK=bitpacked record
  EVENT0_SEL    :bit8;
  EVENT1_SEL    :bit8;
  COUNTER0_UPPER:bit8;
  COUNTER1_UPPER:bit8;
 end;

 TPCIE_PERF_CNTL_MST_R_CLK=bitpacked record
  EVENT0_SEL    :bit8;
  EVENT1_SEL    :bit8;
  COUNTER0_UPPER:bit8;
  COUNTER1_UPPER:bit8;
 end;

 TPCIE_PERF_CNTL_SLV_R_CLK=bitpacked record
  EVENT0_SEL    :bit8;
  EVENT1_SEL    :bit8;
  COUNTER0_UPPER:bit8;
  COUNTER1_UPPER:bit8;
 end;

 TPCIE_SRIOV_FUNC_DEP_LINK=bitpacked record
  SRIOV_FUNC_DEP_LINK:bit8;
  RESERVED0          :bit24;
 end;

 TPCIE_TX_CREDITS_ADVT_CPL=bitpacked record
  TX_CREDITS_ADVT_CPLD:bit12;
  RESERVED0           :bit4;
  TX_CREDITS_ADVT_CPLH:bit8;
  RESERVED1           :bit8;
 end;

 TPCIE_TX_CREDITS_INIT_CPL=bitpacked record
  TX_CREDITS_INIT_CPLD:bit12;
  RESERVED0           :bit4;
  TX_CREDITS_INIT_CPLH:bit8;
  RESERVED1           :bit8;
 end;

 TPCIE_TX_REQUEST_NUM_CNTL=bitpacked record
  RESERVED0                   :bit6;
  RESERVED1                   :bit1;
  RESERVED2                   :bit1;
  RESERVED3                   :bit6;
  RESERVED4                   :bit1;
  RESERVED5                   :bit1;
  RESERVED6                   :bit6;
  RESERVED7                   :bit1;
  RESERVED8                   :bit1;
  TX_NUM_OUTSTANDING_NP       :bit6;
  TX_NUM_OUTSTANDING_NP_VC1_EN:bit1;
  TX_NUM_OUTSTANDING_NP_EN    :bit1;
 end;

 TPCIE_UNCORR_ERR_SEVERITY=bitpacked record
  RESERVED0                       :bit4;
  DLP_ERR_SEVERITY                :bit1;
  SURPDN_ERR_SEVERITY             :bit1;
  RESERVED1                       :bit6;
  PSN_ERR_SEVERITY                :bit1;
  FC_ERR_SEVERITY                 :bit1;
  CPL_TIMEOUT_SEVERITY            :bit1;
  CPL_ABORT_ERR_SEVERITY          :bit1;
  UNEXP_CPL_SEVERITY              :bit1;
  RCV_OVFL_SEVERITY               :bit1;
  MAL_TLP_SEVERITY                :bit1;
  ECRC_ERR_SEVERITY               :bit1;
  UNSUPP_REQ_ERR_SEVERITY         :bit1;
  ACS_VIOLATION_SEVERITY          :bit1;
  UNCORR_INT_ERR_SEVERITY         :bit1;
  MC_BLOCKED_TLP_SEVERITY         :bit1;
  ATOMICOP_EGRESS_BLOCKED_SEVERITY:bit1;
  TLP_PREFIX_BLOCKED_ERR_SEVERITY :bit1;
  RESERVED2                       :bit6;
 end;

 TPCIE_VC0_RESOURCE_STATUS=bitpacked record
  PORT_ARB_TABLE_STATUS :bit1;
  VC_NEGOTIATION_PENDING:bit1;
  RESERVED0             :bit30;
 end;

 TPCIE_VC1_RESOURCE_STATUS=bitpacked record
  PORT_ARB_TABLE_STATUS :bit1;
  VC_NEGOTIATION_PENDING:bit1;
  RESERVED0             :bit30;
 end;

 TPCIE_VENDOR_SPECIFIC_HDR=bitpacked record
  VSEC_ID    :bit16;
  VSEC_REV   :bit4;
  VSEC_LENGTH:bit12;
 end;

 TPERFMON_TEST_DEBUG_INDEX=bitpacked record
  PERFMON_TEST_DEBUG_INDEX   :bit8;
  PERFMON_TEST_DEBUG_WRITE_EN:bit1;
  RESERVED0                  :bit23;
 end;

 TPLL_MACRO_CNTL_RESERVED0=bit32;

 TPLL_MACRO_CNTL_RESERVED1=bit32;

 TPLL_MACRO_CNTL_RESERVED2=bit32;

 TPLL_MACRO_CNTL_RESERVED3=bit32;

 TPLL_MACRO_CNTL_RESERVED4=bit32;

 TPLL_MACRO_CNTL_RESERVED5=bit32;

 TPLL_MACRO_CNTL_RESERVED6=bit32;

 TPLL_MACRO_CNTL_RESERVED7=bit32;

 TPLL_MACRO_CNTL_RESERVED8=bit32;

 TPLL_MACRO_CNTL_RESERVED9=bit32;

 TREFCLK_CGTT_BLK_CTRL_REG=bitpacked record
  REFCLK_TURN_ON_DELAY :bit4;
  REFCLK_TURN_OFF_DELAY:bit8;
  RESERVED0            :bit20;
 end;

 TREGAMMA_CNTLA_REGION_0_1=bitpacked record
  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET  :bit9;
  RESERVED0                             :bit3;
  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS:bit3;
  RESERVED1                             :bit1;
  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET  :bit9;
  RESERVED2                             :bit3;
  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS:bit3;
  RESERVED3                             :bit1;
 end;

 TREGAMMA_CNTLA_REGION_2_3=bitpacked record
  REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET  :bit9;
  RESERVED0                             :bit3;
  REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS:bit3;
  RESERVED1                             :bit1;
  REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET  :bit9;
  RESERVED2                             :bit3;
  REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS:bit3;
  RESERVED3                             :bit1;
 end;

 TREGAMMA_CNTLA_REGION_4_5=bitpacked record
  REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET  :bit9;
  RESERVED0                             :bit3;
  REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS:bit3;
  RESERVED1                             :bit1;
  REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET  :bit9;
  RESERVED2                             :bit3;
  REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS:bit3;
  RESERVED3                             :bit1;
 end;

 TREGAMMA_CNTLA_REGION_6_7=bitpacked record
  REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET  :bit9;
  RESERVED0                             :bit3;
  REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS:bit3;
  RESERVED1                             :bit1;
  REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET  :bit9;
  RESERVED2                             :bit3;
  REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS:bit3;
  RESERVED3                             :bit1;
 end;

 TREGAMMA_CNTLA_REGION_8_9=bitpacked record
  REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET  :bit9;
  RESERVED0                             :bit3;
  REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS:bit3;
  RESERVED1                             :bit1;
  REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET  :bit9;
  RESERVED2                             :bit3;
  REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS:bit3;
  RESERVED3                             :bit1;
 end;

 TREGAMMA_CNTLA_SLOPE_CNTL=bitpacked record
  REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE:bit18;
  RESERVED0                            :bit14;
 end;

 TREGAMMA_CNTLA_START_CNTL=bitpacked record
  REGAMMA_CNTLA_EXP_REGION_START        :bit18;
  RESERVED0                             :bit2;
  REGAMMA_CNTLA_EXP_REGION_START_SEGMENT:bit7;
  RESERVED1                             :bit5;
 end;

 TREGAMMA_CNTLB_REGION_0_1=bitpacked record
  REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET  :bit9;
  RESERVED0                             :bit3;
  REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS:bit3;
  RESERVED1                             :bit1;
  REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET  :bit9;
  RESERVED2                             :bit3;
  REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS:bit3;
  RESERVED3                             :bit1;
 end;

 TREGAMMA_CNTLB_REGION_2_3=bitpacked record
  REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET  :bit9;
  RESERVED0                             :bit3;
  REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS:bit3;
  RESERVED1                             :bit1;
  REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET  :bit9;
  RESERVED2                             :bit3;
  REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS:bit3;
  RESERVED3                             :bit1;
 end;

 TREGAMMA_CNTLB_REGION_4_5=bitpacked record
  REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET  :bit9;
  RESERVED0                             :bit3;
  REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS:bit3;
  RESERVED1                             :bit1;
  REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET  :bit9;
  RESERVED2                             :bit3;
  REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS:bit3;
  RESERVED3                             :bit1;
 end;

 TREGAMMA_CNTLB_REGION_6_7=bitpacked record
  REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET  :bit9;
  RESERVED0                             :bit3;
  REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS:bit3;
  RESERVED1                             :bit1;
  REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET  :bit9;
  RESERVED2                             :bit3;
  REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS:bit3;
  RESERVED3                             :bit1;
 end;

 TREGAMMA_CNTLB_REGION_8_9=bitpacked record
  REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET  :bit9;
  RESERVED0                             :bit3;
  REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS:bit3;
  RESERVED1                             :bit1;
  REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET  :bit9;
  RESERVED2                             :bit3;
  REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS:bit3;
  RESERVED3                             :bit1;
 end;

 TREGAMMA_CNTLB_SLOPE_CNTL=bitpacked record
  REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE:bit18;
  RESERVED0                            :bit14;
 end;

 TREGAMMA_CNTLB_START_CNTL=bitpacked record
  REGAMMA_CNTLB_EXP_REGION_START        :bit18;
  RESERVED0                             :bit2;
  REGAMMA_CNTLB_EXP_REGION_START_SEGMENT:bit7;
  RESERVED1                             :bit5;
 end;

 TREG_ADAPT_pwregr_CONTROL=bitpacked record
  ACCESS_MODE_pwregr:bit1;
  RESERVED0         :bit31;
 end;

 TREG_ADAPT_pwregt_CONTROL=bitpacked record
  ACCESS_MODE_pwregt:bit1;
  RESERVED0         :bit31;
 end;

 TREMAP_HDP_MEM_FLUSH_CNTL=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TREMAP_HDP_REG_FLUSH_CNTL=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TRESPONSE_INTERRUPT_COUNT=bitpacked record
  N_RESPONSE_INTERRUPT_COUNT:bit8;
  RESERVED0                 :bit24;
 end;

 TRLC_GPU_CLOCK_32_RES_SEL=bitpacked record
  RES_SEL :bit6;
  RESERVED:bit26;
 end;

 TRLC_GPU_IOV_RLC_RESPONSE=bit32;

 TRLC_GPU_IOV_SCRATCH_ADDR=bitpacked record
  ADDR    :bit9;
  RESERVED:bit23;
 end;

 TRLC_GPU_IOV_SCRATCH_DATA=bit32;

 TRLC_GPU_IOV_SDMA0_STATUS=bitpacked record
  PREEMPTED:bit1;
  RESERVED :bit7;
  SAVED    :bit1;
  RESERVED1:bit3;
  RESTORED :bit1;
  RESERVED2:bit19;
 end;

 TRLC_GPU_IOV_SDMA1_STATUS=bitpacked record
  PREEMPTED:bit1;
  RESERVED :bit7;
  SAVED    :bit1;
  RESERVED1:bit3;
  RESTORED :bit1;
  RESERVED2:bit19;
 end;

 TRLC_GPU_IOV_SMU_RESPONSE=bit32;

 TRLC_PG_ALWAYS_ON_CU_MASK=bit32;

 TSCLV_HORZ_FILTER_CONTROL=bitpacked record
  RESERVED0                  :bit8;
  SCL_H_2TAP_HARDCODE_COEF_EN:bit1;
  RESERVED1                  :bit23;
 end;

 TSCLV_VERT_FILTER_CONTROL=bitpacked record
  RESERVED0                  :bit8;
  SCL_V_2TAP_HARDCODE_COEF_EN:bit1;
  RESERVED1                  :bit23;
 end;

 TSCL_VERT_FILTER_INIT_BOT=bitpacked record
  SCL_V_INIT_FRAC_BOT:bit24;
  SCL_V_INIT_INT_BOT :bit3;
  RESERVED0          :bit5;
 end;

 TSDMA0_GFX_CONTEXT_STATUS=bitpacked record
  SELECTED       :bit1;
  RESERVED0      :bit1;
  IDLE           :bit1;
  EXPIRED        :bit1;
  EXCEPTION      :bit3;
  CTXSW_ABLE     :bit1;
  CTXSW_READY    :bit1;
  PREEMPTED      :bit1;
  PREEMPT_DISABLE:bit1;
  RESERVED1      :bit21;
 end;

 TSDMA0_RLC0_IB_SUB_REMAIN=bitpacked record
  SIZE     :bit14;
  RESERVED0:bit18;
 end;

 TSDMA0_RLC1_IB_SUB_REMAIN=bitpacked record
  SIZE     :bit14;
  RESERVED0:bit18;
 end;

 TSDMA1_GFX_CONTEXT_STATUS=bitpacked record
  SELECTED       :bit1;
  RESERVED0      :bit1;
  IDLE           :bit1;
  EXPIRED        :bit1;
  EXCEPTION      :bit3;
  CTXSW_ABLE     :bit1;
  CTXSW_READY    :bit1;
  PREEMPTED      :bit1;
  PREEMPT_DISABLE:bit1;
  RESERVED1      :bit21;
 end;

 TSDMA1_RLC0_IB_SUB_REMAIN=bitpacked record
  SIZE     :bit14;
  RESERVED0:bit18;
 end;

 TSDMA1_RLC1_IB_SUB_REMAIN=bitpacked record
  SIZE     :bit14;
  RESERVED0:bit18;
 end;

 TSEM_MAILBOX_CLIENTCONFIG=bitpacked record
  CP_CLIENT0   :bit3;
  CP_CLIENT1   :bit3;
  CP_CLIENT2   :bit3;
  CP_CLIENT3   :bit3;
  SDMA_CLIENT0 :bit3;
  UVD_CLIENT0  :bit3;
  SDMA1_CLIENT0:bit3;
  VCE_CLIENT0  :bit3;
  RESERVED0    :bit8;
 end;

 TSPI_CSQ_WF_ACTIVE_STATUS=bit32;

 TSPI_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2:bit10;
  PERF_SEL3:bit10;
  RESERVED0:bit12;
 end;

 TSPI_PERFCOUNTER1_SELECT1=bitpacked record
  PERF_SEL2:bit10;
  PERF_SEL3:bit10;
  RESERVED0:bit12;
 end;

 TSPI_PERFCOUNTER2_SELECT1=bitpacked record
  PERF_SEL2:bit10;
  PERF_SEL3:bit10;
  RESERVED0:bit12;
 end;

 TSPI_PERFCOUNTER3_SELECT1=bitpacked record
  PERF_SEL2:bit10;
  PERF_SEL3:bit10;
  RESERVED0:bit12;
 end;

 TSPI_SHADER_LATE_ALLOC_VS=bitpacked record
  LIMIT    :bit6;
  RESERVED0:bit26;
 end;

 TSPI_STATIC_THREAD_MGMT_1=bitpacked record
  RESERVED0:bit16;
  RESERVED1:bit16;
 end;

 TSPI_STATIC_THREAD_MGMT_2=bitpacked record
  RESERVED0:bit16;
  RESERVED1:bit16;
 end;

 TSPI_STATIC_THREAD_MGMT_3=bitpacked record
  LSHS_CU_EN:bit16;
  RESERVED0 :bit16;
 end;

 TSPI_WCL_PIPE_PERCENT_CS0=bitpacked record
  VALUE    :bit7;
  RESERVED0:bit25;
 end;

 TSPI_WCL_PIPE_PERCENT_CS1=bitpacked record
  VALUE    :bit7;
  RESERVED0:bit25;
 end;

 TSPI_WCL_PIPE_PERCENT_CS2=bitpacked record
  VALUE    :bit7;
  RESERVED0:bit25;
 end;

 TSPI_WCL_PIPE_PERCENT_CS3=bitpacked record
  VALUE    :bit7;
  RESERVED0:bit25;
 end;

 TSPI_WCL_PIPE_PERCENT_CS4=bitpacked record
  VALUE    :bit7;
  RESERVED0:bit25;
 end;

 TSPI_WCL_PIPE_PERCENT_CS5=bitpacked record
  VALUE    :bit7;
  RESERVED0:bit25;
 end;

 TSPI_WCL_PIPE_PERCENT_CS6=bitpacked record
  VALUE    :bit7;
  RESERVED0:bit25;
 end;

 TSPI_WCL_PIPE_PERCENT_CS7=bitpacked record
  VALUE    :bit7;
  RESERVED0:bit25;
 end;

 TSPI_WCL_PIPE_PERCENT_GFX=bitpacked record
  VALUE       :bit7;
  LS_GRP_VALUE:bit5;
  HS_GRP_VALUE:bit5;
  ES_GRP_VALUE:bit5;
  GS_GRP_VALUE:bit5;
  RESERVED0   :bit5;
 end;

 TSPI_WF_LIFETIME_STATUS_0=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_1=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_2=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_3=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_4=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_5=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_6=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_7=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_8=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_9=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPMI_FSM_RESET_TRIGGER_0=bitpacked record
  FSM_RESET_TRIGGER:bit1;
  RESERVED0        :bit31;
 end;

 TSPMI_FSM_WRITE_TRIGGER_0=bitpacked record
  FSM_WRITE_TRIGGER:bit1;
  RESERVED0        :bit31;
 end;

 TSQ_THREAD_TRACE_WORD_CMN=bitpacked record
  TOKEN_TYPE:bit4;
  TIME_DELTA:bit1;
  RESERVED0 :bit27;
 end;

 TSRBM_CREDIT_RECOVER_CNTL=bitpacked record
  CREDIT_RECOVER_TIME  :bit12;
  RESERVED0            :bit19;
  CREDIT_RECOVER_ENABLE:bit1;
 end;

 TSRBM_FIREWALL_ERROR_ADDR=bitpacked record
  RESERVED0         :bit2;
  ACCESS_ADDRESS    :bit16;
  RESERVED1         :bit1;
  ACCESS_VF         :bit1;
  ACCESS_VFID       :bit4;
  RESERVED2         :bit7;
  FIREWALL_VIOLATION:bit1;
 end;

 TSRBM_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL :bit6;
  RESERVED0:bit26;
 end;

 TSRBM_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL :bit6;
  RESERVED0:bit26;
 end;

 TTCA_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE2:bit4;
  PERF_MODE3:bit4;
 end;

 TTCA_PERFCOUNTER1_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE2:bit4;
  PERF_MODE3:bit4;
 end;

 TTCC_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE2:bit4;
  PERF_MODE3:bit4;
 end;

 TTCC_PERFCOUNTER1_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE2:bit4;
  PERF_MODE3:bit4;
 end;

 TTCP_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE3:bit4;
  PERF_MODE2:bit4;
 end;

 TTCP_PERFCOUNTER1_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE3:bit4;
  PERF_MODE2:bit4;
 end;

 TUNP_GRPH_STEREOSYNC_FLIP=bitpacked record
  GRPH_STEREOSYNC_FLIP_EN              :bit1;
  RESERVED0                            :bit3;
  GRPH_STEREOSYNC_FLIP_MODE            :bit2;
  RESERVED1                            :bit2;
  GRPH_STACK_INTERLACE_FLIP_EN         :bit1;
  RESERVED2                            :bit3;
  GRPH_STACK_INTERLACE_FLIP_MODE       :bit2;
  RESERVED3                            :bit2;
  GRPH_PRIMARY_SURFACE_PENDING         :bit1;
  GRPH_SECONDARY_SURFACE_PENDING       :bit1;
  GRPH_PRIMARY_BOTTOM_SURFACE_PENDING  :bit1;
  GRPH_SECONDARY_BOTTOM_SURFACE_PENDING:bit1;
  RESERVED4                            :bit8;
  GRPH_STEREOSYNC_SELECT_DISABLE       :bit1;
  RESERVED5                            :bit3;
 end;

 TUVD_MIF_CURR_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit1;
  NUM_GPUS               :bit3;
  RESERVED5              :bit1;
  MULTI_GPU_TILE_SIZE    :bit2;
  RESERVED6              :bit2;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED7              :bit1;
 end;

 TUVD_MIF_SCLR_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit1;
  NUM_GPUS               :bit3;
  RESERVED5              :bit1;
  MULTI_GPU_TILE_SIZE    :bit2;
  RESERVED6              :bit2;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED7              :bit1;
 end;

 TUVD_UDEC_DBW_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit1;
  NUM_GPUS               :bit3;
  RESERVED5              :bit1;
  MULTI_GPU_TILE_SIZE    :bit2;
  RESERVED6              :bit2;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED7              :bit1;
 end;

 TVGA_DEBUG_READBACK_INDEX=bitpacked record
  VGA_DEBUG_READBACK_INDEX:bit8;
  RESERVED0               :bit24;
 end;

 TVGA_SURFACE_PITCH_SELECT=bitpacked record
  VGA_SURFACE_PITCH_SELECT :bit2;
  RESERVED0                :bit6;
  VGA_SURFACE_HEIGHT_SELECT:bit2;
  RESERVED1                :bit22;
 end;

 TVGT_DRAW_INIT_FIFO_DEPTH=bitpacked record
  DRAW_INIT_FIFO_DEPTH:bit6;
  RESERVED0           :bit26;
 end;

 TVGT_INSTANCE_STEP_RATE_0=bit32;

 TVGT_INSTANCE_STEP_RATE_1=bit32;

 TVGT_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE3:bit4;
  PERF_MODE2:bit4;
 end;

 TVGT_PERFCOUNTER1_SELECT1=bitpacked record
  PERF_SEL2 :bit10;
  PERF_SEL3 :bit10;
  RESERVED0 :bit4;
  PERF_MODE3:bit4;
  PERF_MODE2:bit4;
 end;

 TVGT_STRMOUT_VTX_STRIDE_0=bitpacked record
  STRIDE   :bit10;
  RESERVED0:bit22;
 end;

 TVGT_STRMOUT_VTX_STRIDE_1=bitpacked record
  STRIDE   :bit10;
  RESERVED0:bit22;
 end;

 TVGT_STRMOUT_VTX_STRIDE_2=bitpacked record
  STRIDE   :bit10;
  RESERVED0:bit22;
 end;

 TVGT_STRMOUT_VTX_STRIDE_3=bitpacked record
  STRIDE   :bit10;
  RESERVED0:bit22;
 end;

 TVIEWPORT_START_SECONDARY=bitpacked record
  VIEWPORT_Y_START_SECONDARY:bit14;
  RESERVED0                 :bit2;
  VIEWPORT_X_START_SECONDARY:bit14;
  RESERVED1                 :bit2;
 end;

 TVM_DUMMY_PAGE_FAULT_ADDR=bitpacked record
  DUMMY_PAGE_ADDR:bit28;
  RESERVED0      :bit4;
 end;

 TVM_DUMMY_PAGE_FAULT_CNTL=bitpacked record
  DUMMY_PAGE_FAULT_ENABLE   :bit1;
  DUMMY_PAGE_ADDRESS_LOGICAL:bit1;
  DUMMY_PAGE_COMPARE_MASK   :bit2;
  RESERVED0                 :bit28;
 end;

 TWALL_CLOCK_COUNTER_ALIAS=bit32;

 TXDMA_AON_TEST_DEBUG_DATA=bit32;

 TXDMA_SLV_MEM_NACK_STATUS=bitpacked record
  XDMA_SLV_MEM_NACK_TAG:bit16;
  XDMA_SLV_MEM_NACK    :bit2;
  RESERVED0            :bit13;
  XDMA_SLV_MEM_NACK_CLR:bit1;
 end;

 TAFMT_AUDIO_PACKET_CONTROL=bitpacked record
  AFMT_AUDIO_SAMPLE_SEND         :bit1;
  RESERVED0                      :bit10;
  AFMT_RESET_FIFO_WHEN_AUDIO_DIS :bit1;
  AFMT_AUDIO_TEST_EN             :bit1;
  RESERVED1                      :bit1;
  AFMT_AUDIO_TEST_MODE           :bit1;
  RESERVED2                      :bit8;
  AFMT_AUDIO_FIFO_OVERFLOW_ACK   :bit1;
  AFMT_AUDIO_CHANNEL_SWAP        :bit1;
  RESERVED3                      :bit1;
  AFMT_60958_CS_UPDATE           :bit1;
  RESERVED4                      :bit3;
  AFMT_AZ_AUDIO_ENABLE_CHG_ACK   :bit1;
  AFMT_BLANK_TEST_DATA_ON_ENC_ENB:bit1;
 end;

 TATC_ATS_DEFAULT_PAGE_CNTL=bitpacked record
  SEND_DEFAULT_PAGE:bit1;
  RESERVED0        :bit1;
  DEFAULT_PAGE_HIGH:bit4;
  RESERVED1        :bit26;
 end;

 TATC_ATS_FAULT_STATUS_ADDR=bit32;

 TATC_ATS_FAULT_STATUS_INFO=bitpacked record
  FAULT_TYPE    :bit9;
  RESERVED0     :bit1;
  VMID          :bit5;
  EXTRA_INFO    :bit1;
  EXTRA_INFO2   :bit1;
  INVALIDATION  :bit1;
  PAGE_REQUEST  :bit1;
  STATUS        :bit5;
  PAGE_ADDR_HIGH:bit4;
  RESERVED1     :bit4;
 end;

 TATC_PERFCOUNTER_RSLT_CNTL=bitpacked record
  PERF_COUNTER_SELECT :bit4;
  RESERVED0           :bit4;
  START_TRIGGER       :bit8;
  STOP_TRIGGER        :bit8;
  ENABLE_ANY          :bit1;
  CLEAR_ALL           :bit1;
  STOP_ALL_ON_SATURATE:bit1;
  RESERVED1           :bit5;
 end;

 TATC_VM_APERTURE0_LOW_ADDR=bitpacked record
  VIRTUAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TATC_VM_APERTURE1_LOW_ADDR=bitpacked record
  VIRTUAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TAZALIA_CYCLIC_BUFFER_SYNC=bitpacked record
  CYCLIC_BUFFER_SYNC_ENABLE:bit1;
  RESERVED0                :bit31;
 end;

 TBIF_FEATURES_CONTROL_MISC=bitpacked record
  MST_BIF_REQ_EP_DIS                  :bit1;
  SLV_BIF_CPL_EP_DIS                  :bit1;
  BIF_SLV_REQ_EP_DIS                  :bit1;
  BIF_MST_CPL_EP_DIS                  :bit1;
  UR_PSN_PKT_REPORT_POISON_DIS        :bit1;
  POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS :bit1;
  POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS:bit1;
  PLL_SWITCH_IMPCTL_CAL_DONE_DIS      :bit1;
  IGNORE_BE_CHECK_GASKET_COMB_DIS     :bit1;
  MC_BIF_REQ_ID_ROUTING_DIS           :bit1;
  AZ_BIF_REQ_ID_ROUTING_DIS           :bit1;
  ATC_PRG_RESP_PASID_UR_EN            :bit1;
  BIF_RB_SET_OVERFLOW_EN              :bit1;
  ATOMIC_ERR_INT_DIS                  :bit1;
  RESERVED0                           :bit1;
  BME_HDL_NONVIR_EN                   :bit1;
  INIT_PFFLR_CRS_RET_DIS              :bit1;
  FLR_MST_PEND_CHK_DIS                :bit1;
  FLR_SLV_PEND_CHK_DIS                :bit1;
  SOFT_PF_FLR_UR_CFG_EN               :bit1;
  FLR_OSTD_UR_DIS                     :bit1;
  FLR_OSTD_HDL_DIS                    :bit1;
  FLR_NEWREQ_HDL_DIS                  :bit1;
  FLR_CRS_CFG_DIS                     :bit1;
  RESERVED1                           :bit8;
 end;

 TBIF_GPUIOV_VM_INIT_STATUS=bit32;

 TBL1_PWM_CURRENT_ABM_LEVEL=bitpacked record
  BL1_PWM_CURRENT_ABM_LEVEL:bit17;
  RESERVED0                :bit15;
 end;

 TCC_GC_SHADER_ARRAY_CONFIG=bitpacked record
  RESERVED0          :bit1;
  DPFP_RATE          :bit2;
  SQC_BALANCE_DISABLE:bit1;
  HALF_LDS           :bit1;
  RESERVED1          :bit11;
  INACTIVE_CUS       :bit16;
 end;

 TCC_SYS_RB_BACKEND_DISABLE=bitpacked record
  RESERVED0      :bit1;
  RESERVED1      :bit15;
  BACKEND_DISABLE:bit8;
  RESERVED2      :bit8;
 end;

 TCGTS_CU10_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU10_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU11_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU11_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU12_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU12_TA_SQC_CTRL_REG=bitpacked record
  TA                   :bit7;
  TA_OVERRIDE          :bit1;
  TA_BUSY_OVERRIDE     :bit2;
  TA_LS_OVERRIDE       :bit1;
  TA_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  SQC                  :bit7;
  SQC_OVERRIDE         :bit1;
  SQC_BUSY_OVERRIDE    :bit2;
  SQC_LS_OVERRIDE      :bit1;
  SQC_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU12_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU13_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU13_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU14_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU14_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU15_LDS_SQ_CTRL_REG=bitpacked record
  LDS                  :bit7;
  LDS_OVERRIDE         :bit1;
  LDS_BUSY_OVERRIDE    :bit2;
  LDS_LS_OVERRIDE      :bit1;
  LDS_SIMDBUSY_OVERRIDE:bit1;
  RESERVED0            :bit4;
  SQ                   :bit7;
  SQ_OVERRIDE          :bit1;
  SQ_BUSY_OVERRIDE     :bit2;
  SQ_LS_OVERRIDE       :bit1;
  SQ_SIMDBUSY_OVERRIDE :bit1;
  RESERVED1            :bit4;
 end;

 TCGTS_CU15_TD_TCP_CTRL_REG=bitpacked record
  TD                   :bit7;
  TD_OVERRIDE          :bit1;
  TD_BUSY_OVERRIDE     :bit2;
  TD_LS_OVERRIDE       :bit1;
  TD_SIMDBUSY_OVERRIDE :bit1;
  RESERVED0            :bit4;
  TCP                  :bit7;
  TCP_OVERRIDE         :bit1;
  TCP_BUSY_OVERRIDE    :bit2;
  TCP_LS_OVERRIDE      :bit1;
  TCP_SIMDBUSY_OVERRIDE:bit1;
  RESERVED1            :bit4;
 end;

 TCG_SPLL_SPREAD_SPECTRUM_2=bitpacked record
  CLKV     :bit26;
  RESERVED0:bit6;
 end;

 TCHUB_ATC_PERFCOUNTER0_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TCHUB_ATC_PERFCOUNTER1_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TCOL_MAN_INPUT_CSC_CONTROL=bitpacked record
  INPUT_CSC_MODE           :bit2;
  INPUT_CSC_INPUT_TYPE     :bit2;
  INPUT_CSC_CONVERSION_MODE:bit1;
  RESERVED0                :bit27;
 end;

 TCPLL_MACRO_CNTL_RESERVED0=bit32;

 TCPLL_MACRO_CNTL_RESERVED1=bit32;

 TCPLL_MACRO_CNTL_RESERVED2=bit32;

 TCPLL_MACRO_CNTL_RESERVED3=bit32;

 TCPLL_MACRO_CNTL_RESERVED4=bit32;

 TCPLL_MACRO_CNTL_RESERVED5=bit32;

 TCPLL_MACRO_CNTL_RESERVED6=bit32;

 TCPLL_MACRO_CNTL_RESERVED7=bit32;

 TCPLL_MACRO_CNTL_RESERVED8=bit32;

 TCPLL_MACRO_CNTL_RESERVED9=bit32;

 TCP_DRAW_INDX_INDR_ADDR_HI=bitpacked record
  ADDR_HI  :bit16;
  RESERVED0:bit16;
 end;

 TCP_HQD_GDS_RESOURCE_STATE=bitpacked record
  OA_REQUIRED:bit1;
  OA_ACQUIRED:bit1;
  RESERVED0  :bit2;
  GWS_SIZE   :bit6;
  RESERVED1  :bit2;
  GWS_PNTR   :bit6;
  RESERVED2  :bit14;
 end;

 TCP_ME0_PIPE_PRIORITY_CNTS=bitpacked record
  PRIORITY1_CNT :bit8;
  PRIORITY2A_CNT:bit8;
  PRIORITY2B_CNT:bit8;
  PRIORITY3_CNT :bit8;
 end;

 TCP_ME1_PIPE_PRIORITY_CNTS=bitpacked record
  PRIORITY1_CNT :bit8;
  PRIORITY2A_CNT:bit8;
  PRIORITY2B_CNT:bit8;
  PRIORITY3_CNT :bit8;
 end;

 TCP_ME2_PIPE_PRIORITY_CNTS=bitpacked record
  PRIORITY1_CNT :bit8;
  PRIORITY2A_CNT:bit8;
  PRIORITY2B_CNT:bit8;
  PRIORITY3_CNT :bit8;
 end;

 TCP_PFP_INTR_ROUTINE_START=bitpacked record
  IR_START :bit12;
  RESERVED0:bit20;
 end;

 TCP_PFP_METADATA_BASE_ADDR=bit32;

 TCRTC_3D_STRUCTURE_CONTROL=bitpacked record
  CRTC_3D_STRUCTURE_EN                   :bit1;
  RESERVED0                              :bit3;
  CRTC_3D_STRUCTURE_EN_DB                :bit1;
  RESERVED1                              :bit3;
  CRTC_3D_STRUCTURE_V_UPDATE_MODE        :bit2;
  RESERVED2                              :bit2;
  CRTC_3D_STRUCTURE_STEREO_SEL_OVR       :bit1;
  RESERVED3                              :bit3;
  CRTC_3D_STRUCTURE_F_COUNT_RESET        :bit1;
  CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING:bit1;
  CRTC_3D_STRUCTURE_F_COUNT              :bit2;
  RESERVED4                              :bit12;
 end;

 TCRTC_ALLOW_STOP_OFF_V_CNT=bitpacked record
  CRTC_ALLOW_STOP_OFF_V_CNT        :bit8;
  RESERVED0                        :bit8;
  CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT:bit1;
  RESERVED1                        :bit15;
 end;

 TCRTC_BLANK_DATA_COLOR_EXT=bitpacked record
  CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT:bit2;
  RESERVED0                        :bit6;
  CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT:bit2;
  RESERVED1                        :bit6;
  CRTC_BLANK_DATA_COLOR_RED_CR_EXT :bit2;
  RESERVED2                        :bit14;
 end;

 TCRTC_FORCE_COUNT_NOW_CNTL=bitpacked record
  CRTC_FORCE_COUNT_NOW_MODE    :bit2;
  RESERVED0                    :bit2;
  CRTC_FORCE_COUNT_NOW_CHECK   :bit1;
  RESERVED1                    :bit3;
  CRTC_FORCE_COUNT_NOW_TRIG_SEL:bit1;
  RESERVED2                    :bit7;
  CRTC_FORCE_COUNT_NOW_OCCURRED:bit1;
  RESERVED3                    :bit7;
  CRTC_FORCE_COUNT_NOW_CLEAR   :bit1;
  RESERVED4                    :bit7;
 end;

 TCRTC_PIXEL_DATA_READBACK0=bitpacked record
  CRTC_PIXEL_DATA_BLUE_CB:bit12;
  RESERVED0              :bit4;
  CRTC_PIXEL_DATA_GREEN_Y:bit12;
  RESERVED1              :bit4;
 end;

 TCRTC_PIXEL_DATA_READBACK1=bitpacked record
  CRTC_PIXEL_DATA_RED_CR:bit12;
  RESERVED0             :bit20;
 end;

 TCRTC_TEST_PATTERN_CONTROL=bitpacked record
  CRTC_TEST_PATTERN_EN           :bit1;
  RESERVED0                      :bit7;
  CRTC_TEST_PATTERN_MODE         :bit3;
  RESERVED1                      :bit5;
  CRTC_TEST_PATTERN_DYNAMIC_RANGE:bit1;
  RESERVED2                      :bit7;
  CRTC_TEST_PATTERN_COLOR_FORMAT :bit8;
 end;

 TCRTC_VSYNC_NOM_INT_STATUS=bitpacked record
  CRTC_VSYNC_NOM          :bit1;
  RESERVED0               :bit3;
  CRTC_VSYNC_NOM_INT_CLEAR:bit1;
  RESERVED1               :bit27;
 end;

 TCSPRIV_THREAD_TRACE_EVENT=bitpacked record
  EVENT_ID :bit5;
  RESERVED0:bit27;
 end;

 TCUR2_SURFACE_ADDRESS_HIGH=bitpacked record
  CURSOR2_SURFACE_ADDRESS_HIGH:bit8;
  RESERVED0                   :bit24;
 end;

 TDAC_SYNC_TRISTATE_CONTROL=bitpacked record
  DAC_HSYNCA_TRISTATE:bit1;
  RESERVED0          :bit7;
  DAC_VSYNCA_TRISTATE:bit1;
  RESERVED1          :bit7;
  DAC_SYNCA_TRISTATE :bit1;
  RESERVED2          :bit15;
 end;

 TDCFEV_DMIFV_CLOCK_CONTROL=bitpacked record
  RESERVED0                      :bit3;
  DMIFV_SCLK_G_DMIFTRK_GATE_DIS  :bit1;
  DMIFV_DISPCLK_G_DMIFVL_GATE_DIS:bit1;
  DMIFV_DISPCLK_G_DMIFVC_GATE_DIS:bit1;
  DMIFV_SOFT_RESET               :bit1;
  RESERVED1                      :bit17;
  DMIFV_TEST_CLK_SEL             :bit5;
  RESERVED2                      :bit2;
  DMIFV_BUFFER_MODE              :bit1;
 end;

 TDCO_POWER_MANAGEMENT_CNTL=bitpacked record
  PM_ASSERT_RESET:bit1;
  RESERVED0      :bit7;
  PM_ALL_BUSY_OFF:bit1;
  RESERVED1      :bit23;
 end;

 TDC_LUT_BLACK_OFFSET_GREEN=bitpacked record
  DC_LUT_BLACK_OFFSET_GREEN:bit16;
  RESERVED0                :bit16;
 end;

 TDC_LUT_WHITE_OFFSET_GREEN=bitpacked record
  DC_LUT_WHITE_OFFSET_GREEN:bit16;
  RESERVED0                :bit16;
 end;

 TDIG_DISPCLK_SWITCH_STATUS=bitpacked record
  DIG_DISPCLK_SWITCH_ALLOWED         :bit1;
  RESERVED0                          :bit3;
  DIG_DISPCLK_SWITCH_ALLOWED_INT     :bit1;
  RESERVED1                          :bit3;
  DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK :bit1;
  RESERVED2                          :bit3;
  DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK:bit1;
  RESERVED3                          :bit19;
 end;

 TDISPCLK_CGTT_BLK_CTRL_REG=bitpacked record
  DISPCLK_TURN_ON_DELAY :bit4;
  DISPCLK_TURN_OFF_DELAY:bit8;
  CGTT_DISPCLK_OVERRIDE :bit1;
  RESERVED0             :bit19;
 end;

 TDPHY_MACRO_CNTL_RESERVED0=bit32;

 TDPHY_MACRO_CNTL_RESERVED1=bit32;

 TDPHY_MACRO_CNTL_RESERVED2=bit32;

 TDPHY_MACRO_CNTL_RESERVED3=bit32;

 TDPHY_MACRO_CNTL_RESERVED4=bit32;

 TDPHY_MACRO_CNTL_RESERVED5=bit32;

 TDPHY_MACRO_CNTL_RESERVED6=bit32;

 TDPHY_MACRO_CNTL_RESERVED7=bit32;

 TDPHY_MACRO_CNTL_RESERVED8=bit32;

 TDPHY_MACRO_CNTL_RESERVED9=bit32;

 TDP_MSA_V_TIMING_OVERRIDE1=bitpacked record
  DP_MSA_V_TIMING_OVERRIDE_EN:bit1;
  RESERVED0                  :bit3;
  DP_MSA_V_TOTAL_OVERRIDE    :bit14;
  RESERVED1                  :bit14;
 end;

 TDP_MSA_V_TIMING_OVERRIDE2=bitpacked record
  DP_MSA_V_BLANK_START_OVERRIDE:bit14;
  RESERVED0                    :bit2;
  DP_MSA_V_BLANK_END_OVERRIDE  :bit14;
  RESERVED1                    :bit2;
 end;

 TFBC_IDLE_FORCE_CLEAR_MASK=bit32;

 TGARLIC_FLUSH_ADDR_START_0=bitpacked record
  ENABLE    :bit1;
  MODE      :bit1;
  ADDR_START:bit30;
 end;

 TGARLIC_FLUSH_ADDR_START_1=bitpacked record
  ENABLE    :bit1;
  MODE      :bit1;
  ADDR_START:bit30;
 end;

 TGARLIC_FLUSH_ADDR_START_2=bitpacked record
  ENABLE    :bit1;
  MODE      :bit1;
  ADDR_START:bit30;
 end;

 TGARLIC_FLUSH_ADDR_START_3=bitpacked record
  ENABLE    :bit1;
  MODE      :bit1;
  ADDR_START:bit30;
 end;

 TGARLIC_FLUSH_ADDR_START_4=bitpacked record
  ENABLE    :bit1;
  MODE      :bit1;
  ADDR_START:bit30;
 end;

 TGARLIC_FLUSH_ADDR_START_5=bitpacked record
  ENABLE    :bit1;
  MODE      :bit1;
  ADDR_START:bit30;
 end;

 TGARLIC_FLUSH_ADDR_START_6=bitpacked record
  ENABLE    :bit1;
  MODE      :bit1;
  ADDR_START:bit30;
 end;

 TGARLIC_FLUSH_ADDR_START_7=bitpacked record
  ENABLE    :bit1;
  MODE      :bit1;
  ADDR_START:bit30;
 end;

 TGCK_ADFS_CLK_BYPASS_CNTL1=bitpacked record
  ECLK_BYPASS_CNTL    :bit3;
  SCLK_BYPASS_CNTL    :bit3;
  LCLK_BYPASS_CNTL    :bit3;
  DCLK_BYPASS_CNTL    :bit3;
  VCLK_BYPASS_CNTL    :bit3;
  DISPCLK_BYPASS_CNTL :bit3;
  DRREFCLK_BYPASS_CNTL:bit3;
  ACLK_BYPASS_CNTL    :bit3;
  SAMCLK_BYPASS_CNTL  :bit3;
  ACLK_DIV_BYPASS_CNTL:bit3;
  RESERVED0           :bit2;
 end;

 TGENERIC_I2C_PIN_SELECTION=bitpacked record
  GENERIC_I2C_SCL_PIN_SEL:bit7;
  RESERVED0              :bit1;
  GENERIC_I2C_SDA_PIN_SEL:bit7;
  RESERVED1              :bit17;
 end;

 THDMI_AUDIO_PACKET_CONTROL=bitpacked record
  RESERVED0                  :bit4;
  HDMI_AUDIO_DELAY_EN        :bit2;
  RESERVED1                  :bit2;
  HDMI_AUDIO_SEND_MAX_PACKETS:bit1;
  RESERVED2                  :bit7;
  HDMI_AUDIO_PACKETS_PER_LINE:bit5;
  RESERVED3                  :bit11;
 end;

 TIH_DSM_MATCH_DATA_CONTROL=bitpacked record
  VALUE    :bit28;
  RESERVED0:bit4;
 end;

 TLBV_BUFFER_URGENCY_STATUS=bitpacked record
  LB_BUFFER_URGENCY_LEVEL:bit12;
  RESERVED0              :bit4;
  LB_BUFFER_URGENCY_STAT :bit1;
  RESERVED1              :bit15;
 end;

 TMCARB_DRAM_TIMING_TABLE_1=bit32;

 TMCARB_DRAM_TIMING_TABLE_2=bit32;

 TMCARB_DRAM_TIMING_TABLE_3=bitpacked record
  entries_0_0_padding_2     :bit8;
  entries_0_0_padding_1     :bit8;
  entries_0_0_padding_0     :bit8;
  entries_0_0_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_4=bit32;

 TMCARB_DRAM_TIMING_TABLE_5=bit32;

 TMCARB_DRAM_TIMING_TABLE_6=bitpacked record
  entries_0_1_padding_2     :bit8;
  entries_0_1_padding_1     :bit8;
  entries_0_1_padding_0     :bit8;
  entries_0_1_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_7=bit32;

 TMCARB_DRAM_TIMING_TABLE_8=bit32;

 TMCARB_DRAM_TIMING_TABLE_9=bitpacked record
  entries_0_2_padding_2     :bit8;
  entries_0_2_padding_1     :bit8;
  entries_0_2_padding_0     :bit8;
  entries_0_2_McArbBurstTime:bit8;
 end;

 TMCIF_WB_BUFMGR_CUR_LINE_R=bitpacked record
  MCIF_WB_BUFMGR_CUR_LINE_R:bit13;
  RESERVED0                :bit19;
 end;

 TMCIF_WB_BUFMGR_SW_CONTROL=bitpacked record
  MCIF_WB_BUFMGR_ENABLE         :bit1;
  MCIF_WB_BUF_DUALSIZE_REQ      :bit1;
  RESERVED0                     :bit2;
  MCIF_WB_BUFMGR_SW_INT_EN      :bit1;
  MCIF_WB_BUFMGR_SW_INT_ACK     :bit1;
  MCIF_WB_BUFMGR_SW_SLICE_INT_EN:bit1;
  RESERVED1                     :bit1;
  MCIF_WB_BUFMGR_SW_LOCK        :bit4;
  RESERVED2                     :bit4;
  MCIF_WB_P_VMID                :bit4;
  RESERVED3                     :bit12;
 end;

 TMCIF_WB_URGENCY_WATERMARK=bitpacked record
  MCIF_WB_CLIENT0_URGENCY_WATERMARK:bit16;
  MCIF_WB_CLIENT1_URGENCY_WATERMARK:bit16;
 end;

 TMC_ARB_HARSH_BWPERIOD0_RD=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_HARSH_BWPERIOD0_WR=bitpacked record
  GROUP0:bit8;
  GROUP1:bit8;
  GROUP2:bit8;
  GROUP3:bit8;
 end;

 TMC_ARB_HARSH_BWPERIOD1_RD=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_ARB_HARSH_BWPERIOD1_WR=bitpacked record
  GROUP4:bit8;
  GROUP5:bit8;
  GROUP6:bit8;
  GROUP7:bit8;
 end;

 TMC_FUS_ARB_GARLIC_WR_PRI2=bitpacked record
  SMU_WR_PRI:bit2;
  SAM_WR_PRI:bit2;
  ACP_WR_PRI:bit2;
  RESERVED0 :bit26;
 end;

 TMC_MCBVM_PERFCOUNTER0_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_MCBVM_PERFCOUNTER1_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_MCBVM_PERFCOUNTER2_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_MCBVM_PERFCOUNTER3_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_MCDVM_PERFCOUNTER0_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_MCDVM_PERFCOUNTER1_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_MCDVM_PERFCOUNTER2_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_MCDVM_PERFCOUNTER3_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_SEQ_TRAIN_WAKEUP_CLEAR=bitpacked record
  D0_IDLEH_WAKEUP       :bit1;
  D1_IDLEH_WAKEUP       :bit1;
  RESERVED0             :bit1;
  RESERVED1             :bit1;
  RESERVED2             :bit1;
  RESERVED3             :bit1;
  RESERVED4             :bit1;
  RESERVED5             :bit1;
  SCLK_SRBM_READY_WAKEUP:bit1;
  RESERVED6             :bit1;
  RESERVED7             :bit1;
  RESERVED8             :bit1;
  SOFTWARE_WAKEUP       :bit1;
  RESERVED9             :bit2;
  TIMER_DONE_WAKEUP     :bit1;
  CLEARALL              :bit1;
  RESERVED10            :bit1;
  RESERVED11            :bit1;
  RESERVED12            :bit1;
  RESERVED13            :bit1;
  RESERVED14            :bit1;
  RESERVED15            :bit1;
  RESERVED16            :bit1;
  RESERVED17            :bit1;
  RESERVED18            :bit1;
  RESERVED19            :bit1;
  RESERVED20            :bit1;
  RESERVED21            :bit4;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF10=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF11=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF12=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF13=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF14=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_FB_SIZE_OFFSET_VF15=bitpacked record
  VF_FB_SIZE  :bit16;
  VF_FB_OFFSET:bit16;
 end;

 TMC_VM_L2_PERFCOUNTER0_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_VM_L2_PERFCOUNTER1_CFG=bitpacked record
  PERF_SEL    :bit8;
  PERF_SEL_END:bit8;
  RESERVED0   :bit8;
  PERF_MODE   :bit4;
  ENABLE      :bit1;
  CLEAR       :bit1;
  RESERVED1   :bit2;
 end;

 TMC_XBAR_FIFO_MON_MAX_THSH=bitpacked record
  MON0:bit8;
  MON1:bit8;
  MON2:bit8;
  MON3:bit8;
 end;

 TMC_XBAR_RDRET_PRI_CREDIT1=bitpacked record
  OUT0:bit8;
  OUT1:bit8;
  OUT2:bit8;
  OUT3:bit8;
 end;

 TMC_XBAR_RDRET_PRI_CREDIT2=bitpacked record
  OUT4     :bit8;
  OUT5     :bit8;
  RESERVED0:bit16;
 end;

 TMC_XPB_XDMA_PEER_SYS_BAR0=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_XDMA_PEER_SYS_BAR1=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_XDMA_PEER_SYS_BAR2=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_XDMA_PEER_SYS_BAR3=bitpacked record
  VALID    :bit1;
  SIDE_OK  :bit1;
  ADDR     :bit25;
  RESERVED0:bit5;
 end;

 TMC_XPB_XDMA_RTR_DEST_MAP0=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_XDMA_RTR_DEST_MAP1=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_XDMA_RTR_DEST_MAP2=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMC_XPB_XDMA_RTR_DEST_MAP3=bitpacked record
  NMR         :bit1;
  DEST_OFFSET :bit19;
  DEST_SEL    :bit4;
  DEST_SEL_RPB:bit1;
  SIDE_OK     :bit1;
  APRTR_SIZE  :bit5;
  RESERVED0   :bit1;
 end;

 TMICROSECOND_TIME_BASE_DIV=bitpacked record
  MICROSECOND_TIME_BASE_DIV             :bit7;
  RESERVED0                             :bit1;
  XTAL_REF_DIV                          :bit7;
  RESERVED1                             :bit1;
  XTAL_REF_SEL                          :bit1;
  XTAL_REF_CLOCK_SOURCE_SEL             :bit1;
  RESERVED2                             :bit2;
  MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL:bit1;
  RESERVED3                             :bit3;
  RESERVED4                             :bit1;
  RESERVED5                             :bit3;
  RESERVED6                             :bit1;
  RESERVED7                             :bit3;
 end;

 TMILLISECOND_TIME_BASE_DIV=bitpacked record
  MILLISECOND_TIME_BASE_DIV             :bit17;
  RESERVED0                             :bit3;
  MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL:bit1;
  RESERVED1                             :bit11;
 end;

 TMVP_CRC_RESULT_BLUE_GREEN=bitpacked record
  MVP_CRC_BLUE_RESULT :bit16;
  MVP_CRC_GREEN_RESULT:bit16;
 end;

 TOUTPUT_PAYLOAD_CAPABILITY=bitpacked record
  OUTPUT_PAYLOAD_CAPABILITY:bit16;
  RESERVED0                :bit16;
 end;

 TOVL_SURFACE_ADDRESS_INUSE=bitpacked record
  RESERVED0                :bit8;
  OVL_SURFACE_ADDRESS_INUSE:bit24;
 end;

 TPA_SC_CENTROID_PRIORITY_0=bitpacked record
  DISTANCE_0:bit4;
  DISTANCE_1:bit4;
  DISTANCE_2:bit4;
  DISTANCE_3:bit4;
  DISTANCE_4:bit4;
  DISTANCE_5:bit4;
  DISTANCE_6:bit4;
  DISTANCE_7:bit4;
 end;

 TPA_SC_CENTROID_PRIORITY_1=bitpacked record
  DISTANCE_8 :bit4;
  DISTANCE_9 :bit4;
  DISTANCE_10:bit4;
  DISTANCE_11:bit4;
  DISTANCE_12:bit4;
  DISTANCE_13:bit4;
  DISTANCE_14:bit4;
  DISTANCE_15:bit4;
 end;

 TPA_SC_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL :bit10;
  PERF_SEL1:bit10;
  CNTR_MODE:bit4;
  RESERVED0:bit8;
 end;

 TPA_SC_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit22;
 end;

 TPA_SC_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit22;
 end;

 TPA_SC_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit22;
 end;

 TPA_SC_PERFCOUNTER4_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit22;
 end;

 TPA_SC_PERFCOUNTER5_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit22;
 end;

 TPA_SC_PERFCOUNTER6_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit22;
 end;

 TPA_SC_PERFCOUNTER7_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit22;
 end;

 TPA_SC_TRAP_SCREEN_HV_LOCK=bitpacked record
  DISABLE_NON_PRIV_WRITES:bit1;
  RESERVED0              :bit31;
 end;

 TPA_SC_VPORT_SCISSOR_10_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_10_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_11_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_11_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_12_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_12_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_13_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_13_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_14_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_14_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_15_BR=bitpacked record
  BR_X     :bit15;
  RESERVED0:bit1;
  BR_Y     :bit15;
  RESERVED1:bit1;
 end;

 TPA_SC_VPORT_SCISSOR_15_TL=bitpacked record
  TL_X                 :bit15;
  RESERVED0            :bit1;
  TL_Y                 :bit15;
  WINDOW_OFFSET_DISABLE:bit1;
 end;

 TPA_SU_PERFCOUNTER0_SELECT=bitpacked record
  PERF_SEL :bit10;
  PERF_SEL1:bit10;
  CNTR_MODE:bit4;
  RESERVED0:bit8;
 end;

 TPA_SU_PERFCOUNTER1_SELECT=bitpacked record
  PERF_SEL :bit10;
  PERF_SEL1:bit10;
  CNTR_MODE:bit4;
  RESERVED0:bit8;
 end;

 TPA_SU_PERFCOUNTER2_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit10;
  CNTR_MODE:bit4;
  RESERVED1:bit8;
 end;

 TPA_SU_PERFCOUNTER3_SELECT=bitpacked record
  PERF_SEL :bit10;
  RESERVED0:bit10;
  CNTR_MODE:bit4;
  RESERVED1:bit8;
 end;

 TPB0_DFT_JIT_INJ_STAT_REG0=bitpacked record
  DFT_STAT_DECR    :bit8;
  DFT_STAT_INCR    :bit8;
  DFT_STAT_FINISHED:bit1;
  RESERVED0        :bit15;
 end;

 TPB0_TX_GLB_LANE_SKEW_CTRL=bitpacked record
  TX_CFG_GROUPX1_EN_0     :bit1;
  TX_CFG_GROUPX1_EN_1     :bit1;
  TX_CFG_GROUPX1_EN_2     :bit1;
  TX_CFG_GROUPX1_EN_3     :bit1;
  TX_CFG_GROUPX1_EN_4     :bit1;
  TX_CFG_GROUPX1_EN_5     :bit1;
  TX_CFG_GROUPX1_EN_6     :bit1;
  TX_CFG_GROUPX1_EN_7     :bit1;
  TX_CFG_GROUPX1_EN_8     :bit1;
  TX_CFG_GROUPX1_EN_9     :bit1;
  TX_CFG_GROUPX1_EN_10    :bit1;
  TX_CFG_GROUPX1_EN_11    :bit1;
  TX_CFG_GROUPX1_EN_12    :bit1;
  TX_CFG_GROUPX1_EN_13    :bit1;
  TX_CFG_GROUPX1_EN_14    :bit1;
  TX_CFG_GROUPX1_EN_15    :bit1;
  TX_CFG_GROUPX2_EN_L0T1  :bit1;
  TX_CFG_GROUPX2_EN_L2T3  :bit1;
  TX_CFG_GROUPX2_EN_L4T5  :bit1;
  TX_CFG_GROUPX2_EN_L6T7  :bit1;
  TX_CFG_GROUPX2_EN_L8T9  :bit1;
  TX_CFG_GROUPX2_EN_L10T11:bit1;
  TX_CFG_GROUPX2_EN_L12T13:bit1;
  TX_CFG_GROUPX2_EN_L14T15:bit1;
  TX_CFG_GROUPX4_EN_L0T3  :bit1;
  TX_CFG_GROUPX4_EN_L4T7  :bit1;
  TX_CFG_GROUPX4_EN_L8T11 :bit1;
  TX_CFG_GROUPX4_EN_L12T15:bit1;
  TX_CFG_GROUPX8_EN_L0T7  :bit1;
  TX_CFG_GROUPX8_EN_L8T15 :bit1;
  TX_CFG_GROUPX16_EN_L0T15:bit1;
  RESERVED0               :bit1;
 end;

 TPB1_DFT_JIT_INJ_STAT_REG0=bitpacked record
  DFT_STAT_DECR    :bit8;
  DFT_STAT_INCR    :bit8;
  DFT_STAT_FINISHED:bit1;
  RESERVED0        :bit15;
 end;

 TPB1_TX_GLB_LANE_SKEW_CTRL=bitpacked record
  TX_CFG_GROUPX1_EN_0     :bit1;
  TX_CFG_GROUPX1_EN_1     :bit1;
  TX_CFG_GROUPX1_EN_2     :bit1;
  TX_CFG_GROUPX1_EN_3     :bit1;
  TX_CFG_GROUPX1_EN_4     :bit1;
  TX_CFG_GROUPX1_EN_5     :bit1;
  TX_CFG_GROUPX1_EN_6     :bit1;
  TX_CFG_GROUPX1_EN_7     :bit1;
  TX_CFG_GROUPX1_EN_8     :bit1;
  TX_CFG_GROUPX1_EN_9     :bit1;
  TX_CFG_GROUPX1_EN_10    :bit1;
  TX_CFG_GROUPX1_EN_11    :bit1;
  TX_CFG_GROUPX1_EN_12    :bit1;
  TX_CFG_GROUPX1_EN_13    :bit1;
  TX_CFG_GROUPX1_EN_14    :bit1;
  TX_CFG_GROUPX1_EN_15    :bit1;
  TX_CFG_GROUPX2_EN_L0T1  :bit1;
  TX_CFG_GROUPX2_EN_L2T3  :bit1;
  TX_CFG_GROUPX2_EN_L4T5  :bit1;
  TX_CFG_GROUPX2_EN_L6T7  :bit1;
  TX_CFG_GROUPX2_EN_L8T9  :bit1;
  TX_CFG_GROUPX2_EN_L10T11:bit1;
  TX_CFG_GROUPX2_EN_L12T13:bit1;
  TX_CFG_GROUPX2_EN_L14T15:bit1;
  TX_CFG_GROUPX4_EN_L0T3  :bit1;
  TX_CFG_GROUPX4_EN_L4T7  :bit1;
  TX_CFG_GROUPX4_EN_L8T11 :bit1;
  TX_CFG_GROUPX4_EN_L12T15:bit1;
  TX_CFG_GROUPX8_EN_L0T7  :bit1;
  TX_CFG_GROUPX8_EN_L8T15 :bit1;
  TX_CFG_GROUPX16_EN_L0T15:bit1;
  RESERVED0               :bit1;
 end;

 TPCIE_RX_NUM_NAK_GENERATED=bit32;

 TPCIE_SRIOV_VF_BASE_ADDR_0=bit32;

 TPCIE_SRIOV_VF_BASE_ADDR_1=bit32;

 TPCIE_SRIOV_VF_BASE_ADDR_2=bit32;

 TPCIE_SRIOV_VF_BASE_ADDR_3=bit32;

 TPCIE_SRIOV_VF_BASE_ADDR_4=bit32;

 TPCIE_SRIOV_VF_BASE_ADDR_5=bit32;

 TPCIE_TX_ACK_LATENCY_LIMIT=bitpacked record
  TX_ACK_LATENCY_LIMIT          :bit12;
  TX_ACK_LATENCY_LIMIT_OVERWRITE:bit1;
  RESERVED0                     :bit19;
 end;

 TPIPE0_DMIF_BUFFER_CONTROL=bitpacked record
  DMIF_BUFFERS_ALLOCATED           :bit3;
  RESERVED0                        :bit1;
  DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1;
  RESERVED1                        :bit27;
 end;

 TPIPE1_DMIF_BUFFER_CONTROL=bitpacked record
  DMIF_BUFFERS_ALLOCATED           :bit3;
  RESERVED0                        :bit1;
  DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1;
  RESERVED1                        :bit27;
 end;

 TPIPE2_DMIF_BUFFER_CONTROL=bitpacked record
  DMIF_BUFFERS_ALLOCATED           :bit3;
  RESERVED0                        :bit1;
  DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1;
  RESERVED1                        :bit27;
 end;

 TPIPE3_DMIF_BUFFER_CONTROL=bitpacked record
  DMIF_BUFFERS_ALLOCATED           :bit3;
  RESERVED0                        :bit1;
  DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1;
  RESERVED1                        :bit27;
 end;

 TPIPE4_DMIF_BUFFER_CONTROL=bitpacked record
  DMIF_BUFFERS_ALLOCATED           :bit3;
  RESERVED0                        :bit1;
  DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1;
  RESERVED1                        :bit27;
 end;

 TPIPE5_DMIF_BUFFER_CONTROL=bitpacked record
  DMIF_BUFFERS_ALLOCATED           :bit3;
  RESERVED0                        :bit1;
  DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1;
  RESERVED1                        :bit27;
 end;

 TPLL_MACRO_CNTL_RESERVED10=bit32;

 TPLL_MACRO_CNTL_RESERVED11=bit32;

 TPLL_MACRO_CNTL_RESERVED12=bit32;

 TPLL_MACRO_CNTL_RESERVED13=bit32;

 TPLL_MACRO_CNTL_RESERVED14=bit32;

 TPLL_MACRO_CNTL_RESERVED15=bit32;

 TPLL_MACRO_CNTL_RESERVED16=bit32;

 TPLL_MACRO_CNTL_RESERVED17=bit32;

 TPLL_MACRO_CNTL_RESERVED18=bit32;

 TPLL_MACRO_CNTL_RESERVED19=bit32;

 TPLL_MACRO_CNTL_RESERVED20=bit32;

 TPLL_MACRO_CNTL_RESERVED21=bit32;

 TPLL_MACRO_CNTL_RESERVED22=bit32;

 TPLL_MACRO_CNTL_RESERVED23=bit32;

 TPLL_MACRO_CNTL_RESERVED24=bit32;

 TPLL_MACRO_CNTL_RESERVED25=bit32;

 TPLL_MACRO_CNTL_RESERVED26=bit32;

 TPLL_MACRO_CNTL_RESERVED27=bit32;

 TPLL_MACRO_CNTL_RESERVED28=bit32;

 TPLL_MACRO_CNTL_RESERVED29=bit32;

 TPLL_MACRO_CNTL_RESERVED30=bit32;

 TPLL_MACRO_CNTL_RESERVED31=bit32;

 TPLL_MACRO_CNTL_RESERVED32=bit32;

 TPLL_MACRO_CNTL_RESERVED33=bit32;

 TPLL_MACRO_CNTL_RESERVED34=bit32;

 TPLL_MACRO_CNTL_RESERVED35=bit32;

 TPLL_MACRO_CNTL_RESERVED36=bit32;

 TPLL_MACRO_CNTL_RESERVED37=bit32;

 TPLL_MACRO_CNTL_RESERVED38=bit32;

 TPLL_MACRO_CNTL_RESERVED39=bit32;

 TPLL_MACRO_CNTL_RESERVED40=bit32;

 TPLL_MACRO_CNTL_RESERVED41=bit32;

 TREGAMMA_LUT_WRITE_EN_MASK=bitpacked record
  REGAMMA_LUT_WRITE_EN_MASK:bit3;
  RESERVED0                :bit29;
 end;

 TRLC_GPU_IOV_ACTIVE_FCN_ID=bitpacked record
  VF_ID   :bit4;
  RESERVED:bit27;
  PF_VF   :bit1;
 end;

 TRLC_SAVE_AND_RESTORE_BASE=bit32;

 TRLC_SERDES_CU_MASTER_BUSY=bit32;

 TRLC_SPM_PERFMON_RING_SIZE=bit32;

 TRLC_SPM_SEGMENT_THRESHOLD=bit32;

 TRLC_SRM_INDEX_CNTL_ADDR_0=bitpacked record
  ADDRESS :bit16;
  RESERVED:bit16;
 end;

 TRLC_SRM_INDEX_CNTL_ADDR_1=bitpacked record
  ADDRESS :bit16;
  RESERVED:bit16;
 end;

 TRLC_SRM_INDEX_CNTL_ADDR_2=bitpacked record
  ADDRESS :bit16;
  RESERVED:bit16;
 end;

 TRLC_SRM_INDEX_CNTL_ADDR_3=bitpacked record
  ADDRESS :bit16;
  RESERVED:bit16;
 end;

 TRLC_SRM_INDEX_CNTL_ADDR_4=bitpacked record
  ADDRESS :bit16;
  RESERVED:bit16;
 end;

 TRLC_SRM_INDEX_CNTL_ADDR_5=bitpacked record
  ADDRESS :bit16;
  RESERVED:bit16;
 end;

 TRLC_SRM_INDEX_CNTL_ADDR_6=bitpacked record
  ADDRESS :bit16;
  RESERVED:bit16;
 end;

 TRLC_SRM_INDEX_CNTL_ADDR_7=bitpacked record
  ADDRESS :bit16;
  RESERVED:bit16;
 end;

 TRLC_SRM_INDEX_CNTL_DATA_0=bit32;

 TRLC_SRM_INDEX_CNTL_DATA_1=bit32;

 TRLC_SRM_INDEX_CNTL_DATA_2=bit32;

 TRLC_SRM_INDEX_CNTL_DATA_3=bit32;

 TRLC_SRM_INDEX_CNTL_DATA_4=bit32;

 TRLC_SRM_INDEX_CNTL_DATA_5=bit32;

 TRLC_SRM_INDEX_CNTL_DATA_6=bit32;

 TRLC_SRM_INDEX_CNTL_DATA_7=bit32;

 TSCLK_DEEP_SLEEP_MISC_CNTL=bitpacked record
  DPM_DS_DIV_ID:bit3;
  DPM_SS_DIV_ID:bit3;
  RESERVED0    :bit10;
  OCP_ENABLE   :bit1;
  OCP_DS_DIV_ID:bit3;
  OCP_SS_DIV_ID:bit3;
  RESERVED1    :bit9;
 end;

 TSCLV_VERT_FILTER_INIT_BOT=bitpacked record
  SCL_V_INIT_FRAC_BOT:bit24;
  SCL_V_INIT_INT_BOT :bit3;
  RESERVED0          :bit5;
 end;

 TSDMA0_GFX_RB_RPTR_ADDR_HI=bit32;

 TSDMA0_GFX_RB_RPTR_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA0_PERFCOUNTER0_RESULT=bit32;

 TSDMA0_PERFCOUNTER1_RESULT=bit32;

 TSDMA0_RLC0_CONTEXT_STATUS=bitpacked record
  SELECTED       :bit1;
  RESERVED0      :bit1;
  IDLE           :bit1;
  EXPIRED        :bit1;
  EXCEPTION      :bit3;
  CTXSW_ABLE     :bit1;
  CTXSW_READY    :bit1;
  PREEMPTED      :bit1;
  PREEMPT_DISABLE:bit1;
  RESERVED1      :bit21;
 end;

 TSDMA0_RLC1_CONTEXT_STATUS=bitpacked record
  SELECTED       :bit1;
  RESERVED0      :bit1;
  IDLE           :bit1;
  EXPIRED        :bit1;
  EXCEPTION      :bit3;
  CTXSW_ABLE     :bit1;
  CTXSW_READY    :bit1;
  PREEMPTED      :bit1;
  PREEMPT_DISABLE:bit1;
  RESERVED1      :bit21;
 end;

 TSDMA1_GFX_RB_RPTR_ADDR_HI=bit32;

 TSDMA1_GFX_RB_RPTR_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA1_PERFCOUNTER0_RESULT=bit32;

 TSDMA1_PERFCOUNTER1_RESULT=bit32;

 TSDMA1_RLC0_CONTEXT_STATUS=bitpacked record
  SELECTED       :bit1;
  RESERVED0      :bit1;
  IDLE           :bit1;
  EXPIRED        :bit1;
  EXCEPTION      :bit3;
  CTXSW_ABLE     :bit1;
  CTXSW_READY    :bit1;
  PREEMPTED      :bit1;
  PREEMPT_DISABLE:bit1;
  RESERVED1      :bit21;
 end;

 TSDMA1_RLC1_CONTEXT_STATUS=bitpacked record
  SELECTED       :bit1;
  RESERVED0      :bit1;
  IDLE           :bit1;
  EXPIRED        :bit1;
  EXCEPTION      :bit3;
  CTXSW_ABLE     :bit1;
  CTXSW_READY    :bit1;
  PREEMPTED      :bit1;
  PREEMPT_DISABLE:bit1;
  RESERVED1      :bit21;
 end;

 TSMU_BIF_VDDGFX_PWR_STATUS=bitpacked record
  VDDGFX_GFX_PWR_OFF:bit1;
  RESERVED0         :bit31;
 end;

 TSPI_CSQ_WF_ACTIVE_COUNT_0=bitpacked record
  COUNT    :bit11;
  RESERVED0:bit21;
 end;

 TSPI_CSQ_WF_ACTIVE_COUNT_1=bitpacked record
  COUNT    :bit11;
  RESERVED0:bit21;
 end;

 TSPI_CSQ_WF_ACTIVE_COUNT_2=bitpacked record
  COUNT    :bit11;
  RESERVED0:bit21;
 end;

 TSPI_CSQ_WF_ACTIVE_COUNT_3=bitpacked record
  COUNT    :bit11;
  RESERVED0:bit21;
 end;

 TSPI_CSQ_WF_ACTIVE_COUNT_4=bitpacked record
  COUNT    :bit11;
  RESERVED0:bit21;
 end;

 TSPI_CSQ_WF_ACTIVE_COUNT_5=bitpacked record
  COUNT    :bit11;
  RESERVED0:bit21;
 end;

 TSPI_CSQ_WF_ACTIVE_COUNT_6=bitpacked record
  COUNT    :bit11;
  RESERVED0:bit21;
 end;

 TSPI_CSQ_WF_ACTIVE_COUNT_7=bitpacked record
  COUNT    :bit11;
  RESERVED0:bit21;
 end;

 TSPI_RESOURCE_RESERVE_CU_0=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_1=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_2=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_3=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_4=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_5=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_6=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_7=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_8=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_9=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_SHADER_USER_DATA_ES_0=bit32;

 TSPI_SHADER_USER_DATA_ES_1=bit32;

 TSPI_SHADER_USER_DATA_ES_2=bit32;

 TSPI_SHADER_USER_DATA_ES_3=bit32;

 TSPI_SHADER_USER_DATA_ES_4=bit32;

 TSPI_SHADER_USER_DATA_ES_5=bit32;

 TSPI_SHADER_USER_DATA_ES_6=bit32;

 TSPI_SHADER_USER_DATA_ES_7=bit32;

 TSPI_SHADER_USER_DATA_ES_8=bit32;

 TSPI_SHADER_USER_DATA_ES_9=bit32;

 TSPI_SHADER_USER_DATA_GS_0=bit32;

 TSPI_SHADER_USER_DATA_GS_1=bit32;

 TSPI_SHADER_USER_DATA_GS_2=bit32;

 TSPI_SHADER_USER_DATA_GS_3=bit32;

 TSPI_SHADER_USER_DATA_GS_4=bit32;

 TSPI_SHADER_USER_DATA_GS_5=bit32;

 TSPI_SHADER_USER_DATA_GS_6=bit32;

 TSPI_SHADER_USER_DATA_GS_7=bit32;

 TSPI_SHADER_USER_DATA_GS_8=bit32;

 TSPI_SHADER_USER_DATA_GS_9=bit32;

 TSPI_SHADER_USER_DATA_HS_0=bit32;

 TSPI_SHADER_USER_DATA_HS_1=bit32;

 TSPI_SHADER_USER_DATA_HS_2=bit32;

 TSPI_SHADER_USER_DATA_HS_3=bit32;

 TSPI_SHADER_USER_DATA_HS_4=bit32;

 TSPI_SHADER_USER_DATA_HS_5=bit32;

 TSPI_SHADER_USER_DATA_HS_6=bit32;

 TSPI_SHADER_USER_DATA_HS_7=bit32;

 TSPI_SHADER_USER_DATA_HS_8=bit32;

 TSPI_SHADER_USER_DATA_HS_9=bit32;

 TSPI_SHADER_USER_DATA_LS_0=bit32;

 TSPI_SHADER_USER_DATA_LS_1=bit32;

 TSPI_SHADER_USER_DATA_LS_2=bit32;

 TSPI_SHADER_USER_DATA_LS_3=bit32;

 TSPI_SHADER_USER_DATA_LS_4=bit32;

 TSPI_SHADER_USER_DATA_LS_5=bit32;

 TSPI_SHADER_USER_DATA_LS_6=bit32;

 TSPI_SHADER_USER_DATA_LS_7=bit32;

 TSPI_SHADER_USER_DATA_LS_8=bit32;

 TSPI_SHADER_USER_DATA_LS_9=bit32;

 TSPI_SHADER_USER_DATA_PS_0=bit32;

 TSPI_SHADER_USER_DATA_PS_1=bit32;

 TSPI_SHADER_USER_DATA_PS_2=bit32;

 TSPI_SHADER_USER_DATA_PS_3=bit32;

 TSPI_SHADER_USER_DATA_PS_4=bit32;

 TSPI_SHADER_USER_DATA_PS_5=bit32;

 TSPI_SHADER_USER_DATA_PS_6=bit32;

 TSPI_SHADER_USER_DATA_PS_7=bit32;

 TSPI_SHADER_USER_DATA_PS_8=bit32;

 TSPI_SHADER_USER_DATA_PS_9=bit32;

 TSPI_SHADER_USER_DATA_VS_0=bit32;

 TSPI_SHADER_USER_DATA_VS_1=bit32;

 TSPI_SHADER_USER_DATA_VS_2=bit32;

 TSPI_SHADER_USER_DATA_VS_3=bit32;

 TSPI_SHADER_USER_DATA_VS_4=bit32;

 TSPI_SHADER_USER_DATA_VS_5=bit32;

 TSPI_SHADER_USER_DATA_VS_6=bit32;

 TSPI_SHADER_USER_DATA_VS_7=bit32;

 TSPI_SHADER_USER_DATA_VS_8=bit32;

 TSPI_SHADER_USER_DATA_VS_9=bit32;

 TSPI_WCL_PIPE_PERCENT_HP3D=bitpacked record
  VALUE       :bit7;
  LS_GRP_VALUE:bit5;
  HS_GRP_VALUE:bit5;
  ES_GRP_VALUE:bit5;
  GS_GRP_VALUE:bit5;
  RESERVED0   :bit5;
 end;

 TSPI_WF_LIFETIME_STATUS_10=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_11=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_12=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_13=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_14=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_15=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_16=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_17=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_18=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_19=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSPI_WF_LIFETIME_STATUS_20=bitpacked record
  MAX_CNT :bit31;
  INT_SENT:bit1;
 end;

 TSQ_THREAD_TRACE_PERF_MASK=bitpacked record
  SH0_MASK:bit16;
  SH1_MASK:bit16;
 end;

 TSQ_THREAD_TRACE_WORD_INST=bitpacked record
  TOKEN_TYPE:bit4;
  TIME_DELTA:bit1;
  WAVE_ID   :bit4;
  SIMD_ID   :bit2;
  INST_TYPE :bit5;
  RESERVED0 :bit16;
 end;

 TSQ_THREAD_TRACE_WORD_MISC=bitpacked record
  TOKEN_TYPE     :bit4;
  TIME_DELTA     :bit8;
  SH_ID          :bit1;
  MISC_TOKEN_TYPE:bit3;
  RESERVED0      :bit16;
 end;

 TSQ_THREAD_TRACE_WORD_TIME=bitpacked record
  RESERVED0:bit4;
  RESERVED1:bit10;
  RESERVED2:bit1;
  RESERVED3:bit1;
  RESERVED4:bit16;
 end;

 TSQ_THREAD_TRACE_WORD_WAVE=bitpacked record
  TOKEN_TYPE:bit4;
  TIME_DELTA:bit1;
  SH_ID     :bit1;
  CU_ID     :bit4;
  WAVE_ID   :bit4;
  SIMD_ID   :bit2;
  RESERVED0 :bit16;
 end;

 TSYS_GRBM_GFX_INDEX_SELECT=bitpacked record
  SYS_GRBM_GFX_INDEX_SEL:bit4;
  RESERVED0             :bit28;
 end;

 TTCP_BUFFER_ADDR_HASH_CNTL=bitpacked record
  CHANNEL_BITS     :bit3;
  RESERVED0        :bit5;
  BANK_BITS        :bit3;
  RESERVED1        :bit5;
  CHANNEL_XOR_COUNT:bit3;
  RESERVED2        :bit5;
  BANK_XOR_COUNT   :bit3;
  RESERVED3        :bit5;
 end;

 TUNIPHYA_CHANNEL_XBAR_CNTL=bitpacked record
  UNIPHY_CHANNEL0_XBAR_SOURCE:bit2;
  RESERVED0                  :bit6;
  UNIPHY_CHANNEL1_XBAR_SOURCE:bit2;
  RESERVED1                  :bit6;
  UNIPHY_CHANNEL2_XBAR_SOURCE:bit2;
  RESERVED2                  :bit6;
  UNIPHY_CHANNEL3_XBAR_SOURCE:bit2;
  RESERVED3                  :bit2;
  UNIPHY_LINK_ENABLE         :bit1;
  RESERVED4                  :bit3;
 end;

 TUNIPHYB_CHANNEL_XBAR_CNTL=bitpacked record
  UNIPHY_CHANNEL0_XBAR_SOURCE:bit2;
  RESERVED0                  :bit6;
  UNIPHY_CHANNEL1_XBAR_SOURCE:bit2;
  RESERVED1                  :bit6;
  UNIPHY_CHANNEL2_XBAR_SOURCE:bit2;
  RESERVED2                  :bit6;
  UNIPHY_CHANNEL3_XBAR_SOURCE:bit2;
  RESERVED3                  :bit2;
  UNIPHY_LINK_ENABLE         :bit1;
  RESERVED4                  :bit3;
 end;

 TUNIPHYC_CHANNEL_XBAR_CNTL=bitpacked record
  UNIPHY_CHANNEL0_XBAR_SOURCE:bit2;
  RESERVED0                  :bit6;
  UNIPHY_CHANNEL1_XBAR_SOURCE:bit2;
  RESERVED1                  :bit6;
  UNIPHY_CHANNEL2_XBAR_SOURCE:bit2;
  RESERVED2                  :bit6;
  UNIPHY_CHANNEL3_XBAR_SOURCE:bit2;
  RESERVED3                  :bit2;
  UNIPHY_LINK_ENABLE         :bit1;
  RESERVED4                  :bit3;
 end;

 TUNIPHYD_CHANNEL_XBAR_CNTL=bitpacked record
  UNIPHY_CHANNEL0_XBAR_SOURCE:bit2;
  RESERVED0                  :bit6;
  UNIPHY_CHANNEL1_XBAR_SOURCE:bit2;
  RESERVED1                  :bit6;
  UNIPHY_CHANNEL2_XBAR_SOURCE:bit2;
  RESERVED2                  :bit6;
  UNIPHY_CHANNEL3_XBAR_SOURCE:bit2;
  RESERVED3                  :bit2;
  UNIPHY_LINK_ENABLE         :bit1;
  RESERVED4                  :bit3;
 end;

 TUNIPHYE_CHANNEL_XBAR_CNTL=bitpacked record
  UNIPHY_CHANNEL0_XBAR_SOURCE:bit2;
  RESERVED0                  :bit6;
  UNIPHY_CHANNEL1_XBAR_SOURCE:bit2;
  RESERVED1                  :bit6;
  UNIPHY_CHANNEL2_XBAR_SOURCE:bit2;
  RESERVED2                  :bit6;
  UNIPHY_CHANNEL3_XBAR_SOURCE:bit2;
  RESERVED3                  :bit2;
  UNIPHY_LINK_ENABLE         :bit1;
  RESERVED4                  :bit3;
 end;

 TUNIPHYF_CHANNEL_XBAR_CNTL=bitpacked record
  UNIPHY_CHANNEL0_XBAR_SOURCE:bit2;
  RESERVED0                  :bit6;
  UNIPHY_CHANNEL1_XBAR_SOURCE:bit2;
  RESERVED1                  :bit6;
  UNIPHY_CHANNEL2_XBAR_SOURCE:bit2;
  RESERVED2                  :bit6;
  UNIPHY_CHANNEL3_XBAR_SOURCE:bit2;
  RESERVED3                  :bit2;
  UNIPHY_LINK_ENABLE         :bit1;
  RESERVED4                  :bit3;
 end;

 TUNIPHYG_CHANNEL_XBAR_CNTL=bitpacked record
  UNIPHY_CHANNEL0_XBAR_SOURCE:bit2;
  RESERVED0                  :bit6;
  UNIPHY_CHANNEL1_XBAR_SOURCE:bit2;
  RESERVED1                  :bit6;
  UNIPHY_CHANNEL2_XBAR_SOURCE:bit2;
  RESERVED2                  :bit6;
  UNIPHY_CHANNEL3_XBAR_SOURCE:bit2;
  RESERVED3                  :bit2;
  UNIPHY_LINK_ENABLE         :bit1;
  RESERVED4                  :bit3;
 end;

 TUNP_GRPH_INTERRUPT_STATUS=bitpacked record
  GRPH_PFLIP_INT_OCCURRED:bit1;
  RESERVED0              :bit7;
  GRPH_PFLIP_INT_CLEAR   :bit1;
  RESERVED1              :bit23;
 end;

 TVGA_DISPBUF1_SURFACE_ADDR=bitpacked record
  VGA_DISPBUF1_SURFACE_ADDR:bit25;
  RESERVED0                :bit7;
 end;

 TVGA_DISPBUF2_SURFACE_ADDR=bitpacked record
  VGA_DISPBUF2_SURFACE_ADDR:bit25;
  RESERVED0                :bit7;
 end;

 TVGT_GROUP_VECT_0_FMT_CNTL=bitpacked record
  X_CONV  :bit4;
  X_OFFSET:bit4;
  Y_CONV  :bit4;
  Y_OFFSET:bit4;
  Z_CONV  :bit4;
  Z_OFFSET:bit4;
  W_CONV  :bit4;
  W_OFFSET:bit4;
 end;

 TVGT_GROUP_VECT_1_FMT_CNTL=bitpacked record
  X_CONV  :bit4;
  X_OFFSET:bit4;
  Y_CONV  :bit4;
  Y_OFFSET:bit4;
  Z_CONV  :bit4;
  Z_OFFSET:bit4;
  W_CONV  :bit4;
  W_OFFSET:bit4;
 end;

 TVGT_PERFCOUNTER_SEID_MASK=bitpacked record
  PERF_SEID_IGNORE_MASK:bit8;
  RESERVED0            :bit24;
 end;

 TVGT_STRMOUT_BUFFER_CONFIG=bitpacked record
  STREAM_0_BUFFER_EN:bit4;
  STREAM_1_BUFFER_EN:bit4;
  STREAM_2_BUFFER_EN:bit4;
  STREAM_3_BUFFER_EN:bit4;
  RESERVED0         :bit16;
 end;

 TVGT_STRMOUT_BUFFER_SIZE_0=bit32;

 TVGT_STRMOUT_BUFFER_SIZE_1=bit32;

 TVGT_STRMOUT_BUFFER_SIZE_2=bit32;

 TVGT_STRMOUT_BUFFER_SIZE_3=bit32;

 TVM_PRT_APERTURE0_LOW_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TVM_PRT_APERTURE1_LOW_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TVM_PRT_APERTURE2_LOW_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TVM_PRT_APERTURE3_LOW_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TXDMA_AON_TEST_DEBUG_INDEX=bitpacked record
  XDMA_AON_TEST_DEBUG_INDEX   :bit8;
  XDMA_AON_TEST_DEBUG_WRITE_EN:bit1;
  XDMA_DEBUG_SEL              :bit1;
  XDMA_DEBUG_OUT_EN           :bit1;
  RESERVED0                   :bit21;
 end;

 TXDMA_MSTR_CACHE_BASE_ADDR=bit32;

 TXDMA_MSTR_CMD_URGENT_CNTL=bitpacked record
  XDMA_MSTR_CMD_CLIENT_STALL:bit1;
  RESERVED0                 :bit7;
  XDMA_MSTR_CMD_URGENT_LEVEL:bit4;
  XDMA_MSTR_CMD_STALL_DELAY :bit4;
  RESERVED1                 :bit16;
 end;

 TXDMA_MSTR_MEM_NACK_STATUS=bitpacked record
  XDMA_MSTR_MEM_NACK_TAG:bit10;
  RESERVED0             :bit2;
  XDMA_MSTR_MEM_NACK    :bit2;
  RESERVED1             :bit2;
  XDMA_MSTR_MEM_NACK_CLR:bit1;
  RESERVED2             :bit15;
 end;

 TXDMA_MSTR_MEM_URGENT_CNTL=bitpacked record
  XDMA_MSTR_MEM_CLIENT_STALL:bit1;
  RESERVED0                 :bit3;
  XDMA_MSTR_MEM_URGENT_LIMIT:bit4;
  XDMA_MSTR_MEM_URGENT_LEVEL:bit4;
  XDMA_MSTR_MEM_STALL_DELAY :bit4;
  XDMA_MSTR_MEM_URGENT_TIMER:bit16;
 end;

 TXDMA_MSTR_PERFMEAS_STATUS=bitpacked record
  XDMA_MSTR_PERFMEAS_DATA      :bit24;
  XDMA_MSTR_PERFMEAS_INDEX     :bit3;
  RESERVED0                    :bit3;
  XDMA_MSTR_PERFMEAS_INDEX_MODE:bit2;
 end;

 TXDMA_MSTR_VSYNC_GSL_CHECK=bitpacked record
  XDMA_MSTR_VSYNC_GSL_CHECK_SEL    :bit3;
  RESERVED0                        :bit5;
  XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT:bit14;
  RESERVED1                        :bit10;
 end;

 TXDMA_SLV_PCIE_NACK_STATUS=bitpacked record
  XDMA_SLV_PCIE_NACK_TAG:bit10;
  RESERVED0             :bit2;
  XDMA_SLV_PCIE_NACK    :bit2;
  RESERVED1             :bit2;
  XDMA_SLV_PCIE_NACK_CLR:bit1;
  RESERVED2             :bit15;
 end;

 TXDMA_SLV_RDRET_BUF_STATUS=bitpacked record
  XDMA_SLV_RDRET_FREE_ENTRIES:bit10;
  RESERVED0                  :bit2;
  XDMA_SLV_RDRET_BUF_SIZE    :bit10;
  XDMA_SLV_RDRET_PG_STATE    :bit2;
  XDMA_SLV_RDRET_PG_TRANS    :bit1;
  RESERVED1                  :bit7;
 end;

 TXDMA_SLV_READ_LATENCY_AVE=bitpacked record
  XDMA_SLV_READ_LATENCY_ACC  :bit20;
  XDMA_SLV_READ_LATENCY_COUNT:bit12;
 end;

 TXDMA_SLV_READ_URGENT_CNTL=bitpacked record
  XDMA_SLV_READ_CLIENT_STALL:bit1;
  RESERVED0                 :bit3;
  XDMA_SLV_READ_URGENT_LIMIT:bit4;
  XDMA_SLV_READ_URGENT_LEVEL:bit4;
  XDMA_SLV_READ_STALL_DELAY :bit4;
  XDMA_SLV_READ_URGENT_TIMER:bit16;
 end;

 TAFMT_AUDIO_PACKET_CONTROL2=bitpacked record
  AFMT_AUDIO_LAYOUT_OVRD   :bit1;
  AFMT_AUDIO_LAYOUT_SELECT :bit1;
  RESERVED0                :bit6;
  AFMT_AUDIO_CHANNEL_ENABLE:bit8;
  AFMT_DP_AUDIO_STREAM_ID  :bit8;
  AFMT_HBR_ENABLE_OVRD     :bit1;
  RESERVED1                :bit3;
  AFMT_60958_OSF_OVRD      :bit1;
  RESERVED2                :bit3;
 end;

 TATC_ATS_FAULT_STATUS_INFO2=bitpacked record
  VF       :bit1;
  VFID     :bit5;
  RESERVED0:bit3;
  L1_ID    :bit8;
  RESERVED1:bit15;
 end;

 TATC_VM_APERTURE0_HIGH_ADDR=bitpacked record
  VIRTUAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TATC_VM_APERTURE1_HIGH_ADDR=bitpacked record
  VIRTUAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TAUX_GTC_SYNC_ERROR_CONTROL=bitpacked record
  AUX_GTC_POTENTIAL_ERROR_THRESHOLD    :bit5;
  RESERVED0                            :bit3;
  AUX_GTC_DEFINITE_ERROR_THRESHOLD     :bit5;
  RESERVED1                            :bit3;
  AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN    :bit2;
  RESERVED2                            :bit2;
  AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT:bit2;
  RESERVED3                            :bit10;
 end;

 TAZALIA_GLOBAL_CAPABILITIES=bitpacked record
  RESERVED0                           :bit1;
  NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS:bit2;
  RESERVED1                           :bit29;
 end;

 TAZALIA_INPUT_CRC0_CHANNEL0=bit32;

 TAZALIA_INPUT_CRC0_CHANNEL1=bit32;

 TAZALIA_INPUT_CRC0_CHANNEL2=bit32;

 TAZALIA_INPUT_CRC0_CHANNEL3=bit32;

 TAZALIA_INPUT_CRC0_CHANNEL4=bit32;

 TAZALIA_INPUT_CRC0_CHANNEL5=bit32;

 TAZALIA_INPUT_CRC0_CHANNEL6=bit32;

 TAZALIA_INPUT_CRC0_CHANNEL7=bit32;

 TAZALIA_INPUT_CRC0_CONTROL0=bitpacked record
  INPUT_CRC_EN          :bit1;
  RESERVED0             :bit3;
  INPUT_CRC_BLOCK_MODE  :bit1;
  RESERVED1             :bit3;
  INPUT_CRC_INSTANCE_SEL:bit3;
  RESERVED2             :bit21;
 end;

 TAZALIA_INPUT_CRC0_CONTROL1=bit32;

 TAZALIA_INPUT_CRC0_CONTROL2=bitpacked record
  INPUT_CRC_BLOCK_ITERATION:bit16;
  RESERVED0                :bit16;
 end;

 TAZALIA_INPUT_CRC0_CONTROL3=bitpacked record
  INPUT_CRC_COMPLETE            :bit1;
  RESERVED0                     :bit3;
  INPUT_CRC_BLOCK_COMPLETE_PHASE:bit1;
  RESERVED1                     :bit3;
  INPUT_CRC_CHANNEL_RESULT_SEL  :bit3;
  RESERVED2                     :bit21;
 end;

 TAZALIA_INPUT_CRC1_CHANNEL0=bit32;

 TAZALIA_INPUT_CRC1_CHANNEL1=bit32;

 TAZALIA_INPUT_CRC1_CHANNEL2=bit32;

 TAZALIA_INPUT_CRC1_CHANNEL3=bit32;

 TAZALIA_INPUT_CRC1_CHANNEL4=bit32;

 TAZALIA_INPUT_CRC1_CHANNEL5=bit32;

 TAZALIA_INPUT_CRC1_CHANNEL6=bit32;

 TAZALIA_INPUT_CRC1_CHANNEL7=bit32;

 TAZALIA_INPUT_CRC1_CONTROL0=bitpacked record
  INPUT_CRC_EN          :bit1;
  RESERVED0             :bit3;
  INPUT_CRC_BLOCK_MODE  :bit1;
  RESERVED1             :bit3;
  INPUT_CRC_INSTANCE_SEL:bit3;
  RESERVED2             :bit21;
 end;

 TAZALIA_INPUT_CRC1_CONTROL1=bit32;

 TAZALIA_INPUT_CRC1_CONTROL2=bitpacked record
  INPUT_CRC_BLOCK_ITERATION:bit16;
  RESERVED0                :bit16;
 end;

 TAZALIA_INPUT_CRC1_CONTROL3=bitpacked record
  INPUT_CRC_COMPLETE            :bit1;
  RESERVED0                     :bit3;
  INPUT_CRC_BLOCK_COMPLETE_PHASE:bit1;
  RESERVED1                     :bit3;
  INPUT_CRC_CHANNEL_RESULT_SEL  :bit3;
  RESERVED2                     :bit21;
 end;

 TAZALIA_RIRB_AND_DP_CONTROL=bitpacked record
  RIRB_NON_SNOOP        :bit1;
  RESERVED0             :bit3;
  DP_DMA_NON_SNOOP      :bit1;
  DP_UPDATE_FREQ_DIVIDER:bit4;
  RESERVED1             :bit23;
 end;

 TBL1_PWM_MINIMUM_DUTY_CYCLE=bitpacked record
  BL1_PWM_MINIMUM_DUTY_CYCLE:bit17;
  RESERVED0                 :bit15;
 end;

 TCG_STATIC_SCREEN_PARAMETER=bitpacked record
  STATIC_SCREEN_THRESHOLD     :bit16;
  STATIC_SCREEN_THRESHOLD_UNIT:bit4;
  RESERVED0                   :bit12;
 end;

 TCOL_MAN_FP_CONVERTED_FIELD=bitpacked record
  COL_MAN_FP_CONVERTED_FIELD_DATA :bit18;
  RESERVED0                       :bit2;
  COL_MAN_FP_CONVERTED_FIELD_INDEX:bit6;
  RESERVED1                       :bit6;
 end;

 TCOL_MAN_OUTPUT_CSC_CONTROL=bitpacked record
  OUTPUT_CSC_MODE:bit3;
  RESERVED0      :bit29;
 end;

 TCOMM_MATRIXA_TRANS_C11_C12=bitpacked record
  COMM_MATRIXA_TRANS_C11:bit16;
  COMM_MATRIXA_TRANS_C12:bit16;
 end;

 TCOMM_MATRIXA_TRANS_C13_C14=bitpacked record
  COMM_MATRIXA_TRANS_C13:bit16;
  COMM_MATRIXA_TRANS_C14:bit16;
 end;

 TCOMM_MATRIXA_TRANS_C21_C22=bitpacked record
  COMM_MATRIXA_TRANS_C21:bit16;
  COMM_MATRIXA_TRANS_C22:bit16;
 end;

 TCOMM_MATRIXA_TRANS_C23_C24=bitpacked record
  COMM_MATRIXA_TRANS_C23:bit16;
  COMM_MATRIXA_TRANS_C24:bit16;
 end;

 TCOMM_MATRIXA_TRANS_C31_C32=bitpacked record
  COMM_MATRIXA_TRANS_C31:bit16;
  COMM_MATRIXA_TRANS_C32:bit16;
 end;

 TCOMM_MATRIXA_TRANS_C33_C34=bitpacked record
  COMM_MATRIXA_TRANS_C33:bit16;
  COMM_MATRIXA_TRANS_C34:bit16;
 end;

 TCOMM_MATRIXB_TRANS_C11_C12=bitpacked record
  COMM_MATRIXB_TRANS_C11:bit16;
  COMM_MATRIXB_TRANS_C12:bit16;
 end;

 TCOMM_MATRIXB_TRANS_C13_C14=bitpacked record
  COMM_MATRIXB_TRANS_C13:bit16;
  COMM_MATRIXB_TRANS_C14:bit16;
 end;

 TCOMM_MATRIXB_TRANS_C21_C22=bitpacked record
  COMM_MATRIXB_TRANS_C21:bit16;
  COMM_MATRIXB_TRANS_C22:bit16;
 end;

 TCOMM_MATRIXB_TRANS_C23_C24=bitpacked record
  COMM_MATRIXB_TRANS_C23:bit16;
  COMM_MATRIXB_TRANS_C24:bit16;
 end;

 TCOMM_MATRIXB_TRANS_C31_C32=bitpacked record
  COMM_MATRIXB_TRANS_C31:bit16;
  COMM_MATRIXB_TRANS_C32:bit16;
 end;

 TCOMM_MATRIXB_TRANS_C33_C34=bitpacked record
  COMM_MATRIXB_TRANS_C33:bit16;
  COMM_MATRIXB_TRANS_C34:bit16;
 end;

 TCOMPUTE_DISPATCH_INITIATOR=bitpacked record
  COMPUTE_SHADER_EN    :bit1;
  PARTIAL_TG_EN        :bit1;
  FORCE_START_AT_000   :bit1;
  ORDERED_APPEND_ENBL  :bit1;
  ORDERED_APPEND_MODE  :bit1;
  USE_THREAD_DIMENSIONS:bit1;
  ORDER_MODE           :bit1;
  DISPATCH_CACHE_CNTL  :bit3;
  SCALAR_L1_INV_VOL    :bit1;
  VECTOR_L1_INV_VOL    :bit1;
  DATA_ATC             :bit1;
  RESERVED0            :bit1;
  RESTORE              :bit1;
  RESERVED1            :bit17;
 end;

 TCPLL_MACRO_CNTL_RESERVED10=bit32;

 TCPLL_MACRO_CNTL_RESERVED11=bit32;

 TCP_HQD_PQ_DOORBELL_CONTROL=bitpacked record
  DOORBELL_MODE      :bit1;
  DOORBELL_BIF_DROP  :bit1;
  DOORBELL_OFFSET    :bit21;
  DOORBELL_CARRY_BITS:bit3;
  RESERVED0          :bit2;
  DOORBELL_SOURCE    :bit1;
  DOORBELL_SCHD_HIT  :bit1;
  DOORBELL_EN        :bit1;
  DOORBELL_HIT       :bit1;
 end;

 TCP_HQD_PQ_RPTR_REPORT_ADDR=bitpacked record
  RESERVED0       :bit2;
  RPTR_REPORT_ADDR:bit30;
 end;

 TCP_MEC1_INTR_ROUTINE_START=bitpacked record
  IR_START :bit16;
  RESERVED0:bit16;
 end;

 TCP_MEC2_INTR_ROUTINE_START=bitpacked record
  IR_START :bit16;
  RESERVED0:bit16;
 end;

 TCP_ME_GDS_ATOMIC0_PREOP_HI=bit32;

 TCP_ME_GDS_ATOMIC0_PREOP_LO=bit32;

 TCP_ME_GDS_ATOMIC1_PREOP_HI=bit32;

 TCP_ME_GDS_ATOMIC1_PREOP_LO=bit32;

 TCP_RB_DOORBELL_RANGE_LOWER=bitpacked record
  RESERVED0           :bit2;
  DOORBELL_RANGE_LOWER:bit21;
  RESERVED1           :bit9;
 end;

 TCP_RB_DOORBELL_RANGE_UPPER=bitpacked record
  RESERVED0           :bit2;
  DOORBELL_RANGE_UPPER:bit21;
  RESERVED1           :bit9;
 end;

 TCRTC_DOUBLE_BUFFER_CONTROL=bitpacked record
  CRTC_UPDATE_PENDING             :bit1;
  RESERVED0                       :bit7;
  CRTC_UPDATE_INSTANTLY           :bit1;
  RESERVED1                       :bit7;
  CRTC_BLANK_DATA_DOUBLE_BUFFER_EN:bit1;
  RESERVED2                       :bit15;
 end;

 TCRTC_STATIC_SCREEN_CONTROL=bitpacked record
  CRTC_STATIC_SCREEN_EVENT_MASK :bit16;
  CRTC_STATIC_SCREEN_FRAME_COUNT:bit8;
  CRTC_CPU_SS_INT_ENABLE        :bit1;
  CRTC_SS_STATUS                :bit1;
  CRTC_CPU_SS_INT_STATUS        :bit1;
  CRTC_CPU_SS_INT_CLEAR         :bit1;
  CRTC_CPU_SS_INT_TYPE          :bit1;
  RESERVED0                     :bit3;
 end;

 TCRTC_STEREO_FORCE_NEXT_EYE=bitpacked record
  CRTC_STEREO_FORCE_NEXT_EYE:bit2;
  RESERVED0                 :bit6;
  CRTC_AVSYNC_FRAME_COUNTER :bit8;
  CRTC_AVSYNC_LINE_COUNTER  :bit13;
  RESERVED1                 :bit3;
 end;

 TDAC_AUTODETECT_INT_CONTROL=bitpacked record
  DAC_AUTODETECT_ACK       :bit1;
  RESERVED0                :bit15;
  DAC_AUTODETECT_INT_ENABLE:bit1;
  RESERVED1                :bit15;
 end;

 TDBG_SMB_BYPASS_SRBM_ACCESS=bitpacked record
  DBG_SMB_BYPASS_SRBM_EN:bit1;
  RESERVED0             :bit4;
  RESERVED1             :bit27;
 end;

 TDB_SRESULTS_COMPARE_STATE0=bitpacked record
  COMPAREFUNC0 :bit3;
  RESERVED0    :bit1;
  COMPAREVALUE0:bit8;
  COMPAREMASK0 :bit8;
  RESERVED1    :bit4;
  ENABLE0      :bit1;
  RESERVED2    :bit7;
 end;

 TDB_SRESULTS_COMPARE_STATE1=bitpacked record
  COMPAREFUNC1 :bit3;
  RESERVED0    :bit1;
  COMPAREVALUE1:bit8;
  COMPAREMASK1 :bit8;
  RESERVED1    :bit4;
  ENABLE1      :bit1;
  RESERVED2    :bit7;
 end;

 TDCFEV_DMIFV_MEM_PWR_STATUS=bitpacked record
  DMIFV_MEM_PWR_LUMA_0_STATE  :bit2;
  DMIFV_MEM_PWR_LUMA_1_STATE  :bit2;
  DMIFV_MEM_PWR_LUMA_2_STATE  :bit2;
  DMIFV_MEM_PWR_LUMA_3_STATE  :bit2;
  DMIFV_MEM_PWR_LUMA_4_STATE  :bit2;
  DMIFV_MEM_PWR_CHROMA_0_STATE:bit2;
  DMIFV_MEM_PWR_CHROMA_1_STATE:bit2;
  DMIFV_MEM_PWR_CHROMA_2_STATE:bit2;
  DMIFV_MEM_PWR_CHROMA_3_STATE:bit2;
  DMIFV_MEM_PWR_CHROMA_4_STATE:bit2;
  RESERVED0                   :bit12;
 end;

 TDCIO_GSL_SWAPLOCK_PAD_CNTL=bitpacked record
  DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL:bit2;
  RESERVED0                          :bit2;
  DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL  :bit2;
  RESERVED1                          :bit2;
  DCIO_SWAPLOCK_A_GSL_MASK           :bit2;
  RESERVED2                          :bit6;
  DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL:bit2;
  RESERVED3                          :bit2;
  DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL  :bit2;
  RESERVED4                          :bit2;
  DCIO_SWAPLOCK_B_GSL_MASK           :bit2;
  RESERVED5                          :bit6;
 end;

 TDC_ABM1_ACE_OFFSET_SLOPE_0=bitpacked record
  ABM1_ACE_SLOPE_0 :bit15;
  RESERVED0        :bit1;
  ABM1_ACE_OFFSET_0:bit11;
  RESERVED1        :bit4;
  ABM1_ACE_LOCK    :bit1;
 end;

 TDC_ABM1_ACE_OFFSET_SLOPE_1=bitpacked record
  ABM1_ACE_SLOPE_1 :bit15;
  RESERVED0        :bit1;
  ABM1_ACE_OFFSET_1:bit11;
  RESERVED1        :bit4;
  ABM1_ACE_LOCK    :bit1;
 end;

 TDC_ABM1_ACE_OFFSET_SLOPE_2=bitpacked record
  ABM1_ACE_SLOPE_2 :bit15;
  RESERVED0        :bit1;
  ABM1_ACE_OFFSET_2:bit11;
  RESERVED1        :bit4;
  ABM1_ACE_LOCK    :bit1;
 end;

 TDC_ABM1_ACE_OFFSET_SLOPE_3=bitpacked record
  ABM1_ACE_SLOPE_3 :bit15;
  RESERVED0        :bit1;
  ABM1_ACE_OFFSET_3:bit11;
  RESERVED1        :bit4;
  ABM1_ACE_LOCK    :bit1;
 end;

 TDC_ABM1_ACE_OFFSET_SLOPE_4=bitpacked record
  ABM1_ACE_SLOPE_4 :bit15;
  RESERVED0        :bit1;
  ABM1_ACE_OFFSET_4:bit11;
  RESERVED1        :bit4;
  ABM1_ACE_LOCK    :bit1;
 end;

 TDC_MEM_GLOBAL_PWR_REQ_CNTL=bitpacked record
  DC_MEM_GLOBAL_PWR_REQ_DIS:bit1;
  RESERVED0                :bit31;
 end;

 TDOUT_POWER_MANAGEMENT_CNTL=bitpacked record
  RESERVED0      :bit1;
  RESERVED1      :bit3;
  RESERVED2      :bit1;
  RESERVED3      :bit1;
  RESERVED4      :bit2;
  RESERVED5      :bit1;
  RESERVED6      :bit1;
  RESERVED7      :bit2;
  RESERVED8      :bit1;
  RESERVED9      :bit3;
  RESERVED10     :bit1;
  RESERVED11     :bit1;
  RESERVED12     :bit2;
  RESERVED13     :bit1;
  PM_ASSERT_RESET:bit1;
  RESERVED14     :bit1;
  RESERVED15     :bit1;
  RESERVED16     :bit1;
  RESERVED17     :bit3;
  RESERVED18     :bit4;
 end;

 TDPG_WATERMARK_MASK_CONTROL=bitpacked record
  STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK:bit2;
  RESERVED0                               :bit6;
  URGENCY_WATERMARK_MASK                  :bit2;
  RESERVED1                               :bit6;
  NB_PSTATE_CHANGE_WATERMARK_MASK         :bit2;
  RESERVED2                               :bit14;
 end;

 TDPHY_MACRO_CNTL_RESERVED10=bit32;

 TDPHY_MACRO_CNTL_RESERVED11=bit32;

 TDPHY_MACRO_CNTL_RESERVED12=bit32;

 TDPHY_MACRO_CNTL_RESERVED13=bit32;

 TDPHY_MACRO_CNTL_RESERVED14=bit32;

 TDPHY_MACRO_CNTL_RESERVED15=bit32;

 TDPHY_MACRO_CNTL_RESERVED16=bit32;

 TDPHY_MACRO_CNTL_RESERVED17=bit32;

 TDPHY_MACRO_CNTL_RESERVED18=bit32;

 TDPHY_MACRO_CNTL_RESERVED19=bit32;

 TDPHY_MACRO_CNTL_RESERVED20=bit32;

 TDPHY_MACRO_CNTL_RESERVED21=bit32;

 TDPHY_MACRO_CNTL_RESERVED22=bit32;

 TDPHY_MACRO_CNTL_RESERVED23=bit32;

 TDPHY_MACRO_CNTL_RESERVED24=bit32;

 TDPHY_MACRO_CNTL_RESERVED25=bit32;

 TDPHY_MACRO_CNTL_RESERVED26=bit32;

 TDPHY_MACRO_CNTL_RESERVED27=bit32;

 TDPHY_MACRO_CNTL_RESERVED28=bit32;

 TDPHY_MACRO_CNTL_RESERVED29=bit32;

 TDPHY_MACRO_CNTL_RESERVED30=bit32;

 TDPHY_MACRO_CNTL_RESERVED31=bit32;

 TDPHY_MACRO_CNTL_RESERVED32=bit32;

 TDPHY_MACRO_CNTL_RESERVED33=bit32;

 TDPHY_MACRO_CNTL_RESERVED34=bit32;

 TDPHY_MACRO_CNTL_RESERVED35=bit32;

 TDPHY_MACRO_CNTL_RESERVED36=bit32;

 TDPHY_MACRO_CNTL_RESERVED37=bit32;

 TDPHY_MACRO_CNTL_RESERVED38=bit32;

 TDPHY_MACRO_CNTL_RESERVED39=bit32;

 TDPHY_MACRO_CNTL_RESERVED40=bit32;

 TDPHY_MACRO_CNTL_RESERVED41=bit32;

 TDPHY_MACRO_CNTL_RESERVED42=bit32;

 TDPHY_MACRO_CNTL_RESERVED43=bit32;

 TDPHY_MACRO_CNTL_RESERVED44=bit32;

 TDPHY_MACRO_CNTL_RESERVED45=bit32;

 TDPHY_MACRO_CNTL_RESERVED46=bit32;

 TDPHY_MACRO_CNTL_RESERVED47=bit32;

 TDPHY_MACRO_CNTL_RESERVED48=bit32;

 TDPHY_MACRO_CNTL_RESERVED49=bit32;

 TDPHY_MACRO_CNTL_RESERVED50=bit32;

 TDPHY_MACRO_CNTL_RESERVED51=bit32;

 TDPHY_MACRO_CNTL_RESERVED52=bit32;

 TDPHY_MACRO_CNTL_RESERVED53=bit32;

 TDPHY_MACRO_CNTL_RESERVED54=bit32;

 TDPHY_MACRO_CNTL_RESERVED55=bit32;

 TDPHY_MACRO_CNTL_RESERVED56=bit32;

 TDPHY_MACRO_CNTL_RESERVED57=bit32;

 TDPHY_MACRO_CNTL_RESERVED58=bit32;

 TDPHY_MACRO_CNTL_RESERVED59=bit32;

 TDPHY_MACRO_CNTL_RESERVED60=bit32;

 TDPHY_MACRO_CNTL_RESERVED61=bit32;

 TDPHY_MACRO_CNTL_RESERVED62=bit32;

 TDPHY_MACRO_CNTL_RESERVED63=bit32;

 TDPREFCLK_CGTT_BLK_CTRL_REG=bitpacked record
  DPREFCLK_TURN_ON_DELAY :bit4;
  DPREFCLK_TURN_OFF_DELAY:bit8;
  RESERVED0              :bit20;
 end;

 TFMT_CRC_SIG_RED_GREEN_MASK=bitpacked record
  FMT_CRC_SIG_RED_MASK  :bit16;
  FMT_CRC_SIG_GREEN_MASK:bit16;
 end;

 TGAMMA_CORR_CNTLA_END_CNTL1=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION_END:bit16;
  RESERVED0                      :bit16;
 end;

 TGAMMA_CORR_CNTLA_END_CNTL2=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE:bit16;
  GAMMA_CORR_CNTLA_EXP_REGION_END_BASE :bit16;
 end;

 TGAMMA_CORR_CNTLB_END_CNTL1=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION_END:bit16;
  RESERVED0                      :bit16;
 end;

 TGAMMA_CORR_CNTLB_END_CNTL2=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE:bit16;
  GAMMA_CORR_CNTLB_EXP_REGION_END_BASE :bit16;
 end;

 TGC_USER_RB_BACKEND_DISABLE=bitpacked record
  RESERVED0      :bit16;
  BACKEND_DISABLE:bit8;
  RESERVED1      :bit8;
 end;

 TGC_USER_SHADER_RATE_CONFIG=bitpacked record
  RESERVED0          :bit1;
  DPFP_RATE          :bit2;
  SQC_BALANCE_DISABLE:bit1;
  HALF_LDS           :bit1;
  RESERVED1          :bit27;
 end;

 TGRPH_SURFACE_ADDRESS_INUSE=bitpacked record
  RESERVED0                 :bit8;
  GRPH_SURFACE_ADDRESS_INUSE:bit24;
 end;

 TIH_DSM_MATCH_FIELD_CONTROL=bitpacked record
  SRC_EN      :bit1;
  FCNID_EN    :bit1;
  TIMESTAMP_EN:bit1;
  RINGID_EN   :bit1;
  VMID_EN     :bit1;
  PASID_EN    :bit1;
  RESERVED0   :bit26;
 end;

 TMCARB_DRAM_TIMING_TABLE_10=bit32;

 TMCARB_DRAM_TIMING_TABLE_11=bit32;

 TMCARB_DRAM_TIMING_TABLE_12=bitpacked record
  entries_0_3_padding_2     :bit8;
  entries_0_3_padding_1     :bit8;
  entries_0_3_padding_0     :bit8;
  entries_0_3_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_13=bit32;

 TMCARB_DRAM_TIMING_TABLE_14=bit32;

 TMCARB_DRAM_TIMING_TABLE_15=bitpacked record
  entries_1_0_padding_2     :bit8;
  entries_1_0_padding_1     :bit8;
  entries_1_0_padding_0     :bit8;
  entries_1_0_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_16=bit32;

 TMCARB_DRAM_TIMING_TABLE_17=bit32;

 TMCARB_DRAM_TIMING_TABLE_18=bitpacked record
  entries_1_1_padding_2     :bit8;
  entries_1_1_padding_1     :bit8;
  entries_1_1_padding_0     :bit8;
  entries_1_1_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_19=bit32;

 TMCARB_DRAM_TIMING_TABLE_20=bit32;

 TMCARB_DRAM_TIMING_TABLE_21=bitpacked record
  entries_1_2_padding_2     :bit8;
  entries_1_2_padding_1     :bit8;
  entries_1_2_padding_0     :bit8;
  entries_1_2_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_22=bit32;

 TMCARB_DRAM_TIMING_TABLE_23=bit32;

 TMCARB_DRAM_TIMING_TABLE_24=bitpacked record
  entries_1_3_padding_2     :bit8;
  entries_1_3_padding_1     :bit8;
  entries_1_3_padding_0     :bit8;
  entries_1_3_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_25=bit32;

 TMCARB_DRAM_TIMING_TABLE_26=bit32;

 TMCARB_DRAM_TIMING_TABLE_27=bitpacked record
  entries_2_0_padding_2     :bit8;
  entries_2_0_padding_1     :bit8;
  entries_2_0_padding_0     :bit8;
  entries_2_0_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_28=bit32;

 TMCARB_DRAM_TIMING_TABLE_29=bit32;

 TMCARB_DRAM_TIMING_TABLE_30=bitpacked record
  entries_2_1_padding_2     :bit8;
  entries_2_1_padding_1     :bit8;
  entries_2_1_padding_0     :bit8;
  entries_2_1_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_31=bit32;

 TMCARB_DRAM_TIMING_TABLE_32=bit32;

 TMCARB_DRAM_TIMING_TABLE_33=bitpacked record
  entries_2_2_padding_2     :bit8;
  entries_2_2_padding_1     :bit8;
  entries_2_2_padding_0     :bit8;
  entries_2_2_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_34=bit32;

 TMCARB_DRAM_TIMING_TABLE_35=bit32;

 TMCARB_DRAM_TIMING_TABLE_36=bitpacked record
  entries_2_3_padding_2     :bit8;
  entries_2_3_padding_1     :bit8;
  entries_2_3_padding_0     :bit8;
  entries_2_3_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_37=bit32;

 TMCARB_DRAM_TIMING_TABLE_38=bit32;

 TMCARB_DRAM_TIMING_TABLE_39=bitpacked record
  entries_3_0_padding_2     :bit8;
  entries_3_0_padding_1     :bit8;
  entries_3_0_padding_0     :bit8;
  entries_3_0_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_40=bit32;

 TMCARB_DRAM_TIMING_TABLE_41=bit32;

 TMCARB_DRAM_TIMING_TABLE_42=bitpacked record
  entries_3_1_padding_2     :bit8;
  entries_3_1_padding_1     :bit8;
  entries_3_1_padding_0     :bit8;
  entries_3_1_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_43=bit32;

 TMCARB_DRAM_TIMING_TABLE_44=bit32;

 TMCARB_DRAM_TIMING_TABLE_45=bitpacked record
  entries_3_2_padding_2     :bit8;
  entries_3_2_padding_1     :bit8;
  entries_3_2_padding_0     :bit8;
  entries_3_2_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_46=bit32;

 TMCARB_DRAM_TIMING_TABLE_47=bit32;

 TMCARB_DRAM_TIMING_TABLE_48=bitpacked record
  entries_3_3_padding_2     :bit8;
  entries_3_3_padding_1     :bit8;
  entries_3_3_padding_0     :bit8;
  entries_3_3_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_49=bit32;

 TMCARB_DRAM_TIMING_TABLE_50=bit32;

 TMCARB_DRAM_TIMING_TABLE_51=bitpacked record
  entries_4_0_padding_2     :bit8;
  entries_4_0_padding_1     :bit8;
  entries_4_0_padding_0     :bit8;
  entries_4_0_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_52=bit32;

 TMCARB_DRAM_TIMING_TABLE_53=bit32;

 TMCARB_DRAM_TIMING_TABLE_54=bitpacked record
  entries_4_1_padding_2     :bit8;
  entries_4_1_padding_1     :bit8;
  entries_4_1_padding_0     :bit8;
  entries_4_1_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_55=bit32;

 TMCARB_DRAM_TIMING_TABLE_56=bit32;

 TMCARB_DRAM_TIMING_TABLE_57=bitpacked record
  entries_4_2_padding_2     :bit8;
  entries_4_2_padding_1     :bit8;
  entries_4_2_padding_0     :bit8;
  entries_4_2_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_58=bit32;

 TMCARB_DRAM_TIMING_TABLE_59=bit32;

 TMCARB_DRAM_TIMING_TABLE_60=bitpacked record
  entries_4_3_padding_2     :bit8;
  entries_4_3_padding_1     :bit8;
  entries_4_3_padding_0     :bit8;
  entries_4_3_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_61=bit32;

 TMCARB_DRAM_TIMING_TABLE_62=bit32;

 TMCARB_DRAM_TIMING_TABLE_63=bitpacked record
  entries_5_0_padding_2     :bit8;
  entries_5_0_padding_1     :bit8;
  entries_5_0_padding_0     :bit8;
  entries_5_0_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_64=bit32;

 TMCARB_DRAM_TIMING_TABLE_65=bit32;

 TMCARB_DRAM_TIMING_TABLE_66=bitpacked record
  entries_5_1_padding_2     :bit8;
  entries_5_1_padding_1     :bit8;
  entries_5_1_padding_0     :bit8;
  entries_5_1_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_67=bit32;

 TMCARB_DRAM_TIMING_TABLE_68=bit32;

 TMCARB_DRAM_TIMING_TABLE_69=bitpacked record
  entries_5_2_padding_2     :bit8;
  entries_5_2_padding_1     :bit8;
  entries_5_2_padding_0     :bit8;
  entries_5_2_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_70=bit32;

 TMCARB_DRAM_TIMING_TABLE_71=bit32;

 TMCARB_DRAM_TIMING_TABLE_72=bitpacked record
  entries_5_3_padding_2     :bit8;
  entries_5_3_padding_1     :bit8;
  entries_5_3_padding_0     :bit8;
  entries_5_3_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_73=bit32;

 TMCARB_DRAM_TIMING_TABLE_74=bit32;

 TMCARB_DRAM_TIMING_TABLE_75=bitpacked record
  entries_6_0_padding_2     :bit8;
  entries_6_0_padding_1     :bit8;
  entries_6_0_padding_0     :bit8;
  entries_6_0_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_76=bit32;

 TMCARB_DRAM_TIMING_TABLE_77=bit32;

 TMCARB_DRAM_TIMING_TABLE_78=bitpacked record
  entries_6_1_padding_2     :bit8;
  entries_6_1_padding_1     :bit8;
  entries_6_1_padding_0     :bit8;
  entries_6_1_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_79=bit32;

 TMCARB_DRAM_TIMING_TABLE_80=bit32;

 TMCARB_DRAM_TIMING_TABLE_81=bitpacked record
  entries_6_2_padding_2     :bit8;
  entries_6_2_padding_1     :bit8;
  entries_6_2_padding_0     :bit8;
  entries_6_2_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_82=bit32;

 TMCARB_DRAM_TIMING_TABLE_83=bit32;

 TMCARB_DRAM_TIMING_TABLE_84=bitpacked record
  entries_6_3_padding_2     :bit8;
  entries_6_3_padding_1     :bit8;
  entries_6_3_padding_0     :bit8;
  entries_6_3_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_85=bit32;

 TMCARB_DRAM_TIMING_TABLE_86=bit32;

 TMCARB_DRAM_TIMING_TABLE_87=bitpacked record
  entries_7_0_padding_2     :bit8;
  entries_7_0_padding_1     :bit8;
  entries_7_0_padding_0     :bit8;
  entries_7_0_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_88=bit32;

 TMCARB_DRAM_TIMING_TABLE_89=bit32;

 TMCARB_DRAM_TIMING_TABLE_90=bitpacked record
  entries_7_1_padding_2     :bit8;
  entries_7_1_padding_1     :bit8;
  entries_7_1_padding_0     :bit8;
  entries_7_1_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_91=bit32;

 TMCARB_DRAM_TIMING_TABLE_92=bit32;

 TMCARB_DRAM_TIMING_TABLE_93=bitpacked record
  entries_7_2_padding_2     :bit8;
  entries_7_2_padding_1     :bit8;
  entries_7_2_padding_0     :bit8;
  entries_7_2_McArbBurstTime:bit8;
 end;

 TMCARB_DRAM_TIMING_TABLE_94=bit32;

 TMCARB_DRAM_TIMING_TABLE_95=bit32;

 TMCARB_DRAM_TIMING_TABLE_96=bitpacked record
  entries_7_3_padding_2     :bit8;
  entries_7_3_padding_1     :bit8;
  entries_7_3_padding_0     :bit8;
  entries_7_3_McArbBurstTime:bit8;
 end;

 TMCIF_WB_BUFMGR_VCE_CONTROL=bitpacked record
  MCIF_WB_BUFMGR_VCE_LOCK_IGNORE :bit1;
  RESERVED0                      :bit3;
  MCIF_WB_BUFMGR_VCE_INT_EN      :bit1;
  MCIF_WB_BUFMGR_VCE_INT_ACK     :bit1;
  MCIF_WB_BUFMGR_VCE_SLICE_INT_EN:bit1;
  RESERVED1                      :bit1;
  MCIF_WB_BUFMGR_VCE_LOCK        :bit4;
  RESERVED2                      :bit4;
  MCIF_WB_BUFMGR_SLICE_SIZE      :bit13;
  RESERVED3                      :bit3;
 end;

 TMCIF_WRITE_COMBINE_CONTROL=bitpacked record
  MCIF_WRITE_COMBINE_TIMEOUT:bit8;
  VIP_WRITE_COMBINE_TIMEOUT :bit8;
  RESERVED0                 :bit16;
 end;

 TMC_FUS_ARB_GARLIC_ISOC_PRI=bitpacked record
  DMIF_RD_TOKURG_EN    :bit1;
  UVD_RD_TOKURG_EN     :bit1;
  VCE_RD_TOKURG_EN     :bit1;
  ACP_RD_TOKURG_EN     :bit1;
  DMIF_RD_PRIURG_EN    :bit1;
  UVD_RD_PRIURG_EN     :bit1;
  VCE_RD_PRIURG_EN     :bit1;
  ACP_RD_PRIURG_EN     :bit1;
  DMIF_RD_ISOC_EN      :bit1;
  UVD_RD_ISOC_EN       :bit1;
  VCE_RD_ISOC_EN       :bit1;
  MCIF_RD_ISOC_EN      :bit1;
  UMC_RD_ISOC_EN       :bit1;
  VCEU_RD_ISOC_EN      :bit1;
  ACP_RD_ISOC_EN       :bit1;
  REQPRI_OVERRIDE_EN   :bit1;
  REQPRI_OVERRIDE_VAL  :bit2;
  PRIPRMTE_OVERRIDE_EN :bit1;
  TOKURG_OVERRIDE_EN   :bit1;
  PRIURG_OVERRIDE_EN   :bit1;
  PRIPRMTE_OVERRIDE_VAL:bit1;
  TOKURG_OVERRIDE_VAL  :bit1;
  PRIURG_OVERRIDE_VAL  :bit1;
  GARLIC_REQ_CREDITS   :bit5;
  MM_REL_LATE          :bit1;
  RESERVED0            :bit2;
 end;

 TMC_RPB_PERF_COUNTER_STATUS=bit32;

 TMC_VM_MB_L1_TLS0_END_ADDR0=bitpacked record
  END_ADDR :bit28;
  RESERVED0:bit4;
 end;

 TMC_VM_MB_L1_TLS0_END_ADDR1=bitpacked record
  END_ADDR :bit28;
  RESERVED0:bit4;
 end;

 TMC_VM_MB_L1_TLS0_END_ADDR2=bitpacked record
  END_ADDR :bit28;
  RESERVED0:bit4;
 end;

 TMC_VM_MB_L1_TLS0_END_ADDR3=bitpacked record
  END_ADDR :bit28;
  RESERVED0:bit4;
 end;

 TMC_VM_MB_L1_TLS0_END_ADDR4=bitpacked record
  END_ADDR :bit28;
  RESERVED0:bit4;
 end;

 TMC_VM_MB_L1_TLS0_END_ADDR5=bitpacked record
  END_ADDR :bit28;
  RESERVED0:bit4;
 end;

 TMC_VM_MB_L1_TLS0_END_ADDR6=bitpacked record
  END_ADDR :bit28;
  RESERVED0:bit4;
 end;

 TMC_VM_MB_L1_TLS0_END_ADDR7=bitpacked record
  END_ADDR :bit28;
  RESERVED0:bit4;
 end;

 TMC_VM_MB_L1_TLS0_END_ADDR8=bitpacked record
  END_ADDR :bit28;
  RESERVED0:bit4;
 end;

 TMC_VM_NB_TOP_OF_DRAM_SLOT1=bitpacked record
  RESERVED0  :bit23;
  TOP_OF_DRAM:bit9;
 end;

 TMC_XPB_P2P_BAR_DELTA_ABOVE=bitpacked record
  EN       :bit8;
  DELTA    :bit20;
  RESERVED0:bit4;
 end;

 TMC_XPB_P2P_BAR_DELTA_BELOW=bitpacked record
  EN       :bit8;
  DELTA    :bit20;
  RESERVED0:bit4;
 end;

 TMC_XPB_XDMA_RTR_SRC_APRTR0=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_XDMA_RTR_SRC_APRTR1=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_XDMA_RTR_SRC_APRTR2=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TMC_XPB_XDMA_RTR_SRC_APRTR3=bitpacked record
  BASE_ADDR:bit25;
  RESERVED0:bit7;
 end;

 TPA_SC_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2:bit10;
  PERF_SEL3:bit10;
  RESERVED0:bit12;
 end;

 TPA_SU_PERFCOUNTER0_SELECT1=bitpacked record
  PERF_SEL2:bit10;
  PERF_SEL3:bit10;
  RESERVED0:bit12;
 end;

 TPA_SU_PERFCOUNTER1_SELECT1=bitpacked record
  PERF_SEL2:bit10;
  PERF_SEL3:bit10;
  RESERVED0:bit12;
 end;

 TPB0_GLB_SCI_STAT_OVRD_REG0=bitpacked record
  IGNR_ALL_CBI_UPDT_L0T3     :bit1;
  IGNR_ALL_CBI_UPDT_L4T7     :bit1;
  IGNR_ALL_CBI_UPDT_L8T11    :bit1;
  IGNR_ALL_CBI_UPDT_L12T15   :bit1;
  IGNR_IMPCAL_ACTIVE_CBI_UPDT:bit1;
  RESERVED0                  :bit3;
  TXNIMP                     :bit4;
  TXPIMP                     :bit4;
  RXIMP                      :bit4;
  IMPCAL_ACTIVE              :bit1;
  RESERVED1                  :bit11;
 end;

 TPB0_GLB_SCI_STAT_OVRD_REG1=bitpacked record
  IGNR_LINKSPEED_CBI_UPDT_L0T3:bit1;
  IGNR_FREQDIV_CBI_UPDT_L0T3  :bit1;
  IGNR_DLL_LOCK_CBI_UPDT_L0T3 :bit1;
  RESERVED0                   :bit9;
  DLL_LOCK_0                  :bit1;
  DLL_LOCK_1                  :bit1;
  DLL_LOCK_2                  :bit1;
  DLL_LOCK_3                  :bit1;
  LINKSPEED_0                 :bit2;
  FREQDIV_0                   :bit2;
  LINKSPEED_1                 :bit2;
  FREQDIV_1                   :bit2;
  LINKSPEED_2                 :bit2;
  FREQDIV_2                   :bit2;
  LINKSPEED_3                 :bit2;
  FREQDIV_3                   :bit2;
 end;

 TPB0_GLB_SCI_STAT_OVRD_REG2=bitpacked record
  IGNR_LINKSPEED_CBI_UPDT_L4T7:bit1;
  IGNR_FREQDIV_CBI_UPDT_L4T7  :bit1;
  IGNR_DLL_LOCK_CBI_UPDT_L4T7 :bit1;
  RESERVED0                   :bit9;
  DLL_LOCK_4                  :bit1;
  DLL_LOCK_5                  :bit1;
  DLL_LOCK_6                  :bit1;
  DLL_LOCK_7                  :bit1;
  LINKSPEED_4                 :bit2;
  FREQDIV_4                   :bit2;
  LINKSPEED_5                 :bit2;
  FREQDIV_5                   :bit2;
  LINKSPEED_6                 :bit2;
  FREQDIV_6                   :bit2;
  LINKSPEED_7                 :bit2;
  FREQDIV_7                   :bit2;
 end;

 TPB0_GLB_SCI_STAT_OVRD_REG3=bitpacked record
  IGNR_LINKSPEED_CBI_UPDT_L8T11:bit1;
  IGNR_FREQDIV_CBI_UPDT_L8T11  :bit1;
  IGNR_DLL_LOCK_CBI_UPDT_L8T11 :bit1;
  RESERVED0                    :bit9;
  DLL_LOCK_8                   :bit1;
  DLL_LOCK_9                   :bit1;
  DLL_LOCK_10                  :bit1;
  DLL_LOCK_11                  :bit1;
  LINKSPEED_8                  :bit2;
  FREQDIV_8                    :bit2;
  LINKSPEED_9                  :bit2;
  FREQDIV_9                    :bit2;
  LINKSPEED_10                 :bit2;
  FREQDIV_10                   :bit2;
  LINKSPEED_11                 :bit2;
  FREQDIV_11                   :bit2;
 end;

 TPB0_GLB_SCI_STAT_OVRD_REG4=bitpacked record
  IGNR_LINKSPEED_CBI_UPDT_L12T15:bit1;
  IGNR_FREQDIV_CBI_UPDT_L12T15  :bit1;
  IGNR_DLL_LOCK_CBI_UPDT_L12T15 :bit1;
  RESERVED0                     :bit9;
  DLL_LOCK_12                   :bit1;
  DLL_LOCK_13                   :bit1;
  DLL_LOCK_14                   :bit1;
  DLL_LOCK_15                   :bit1;
  LINKSPEED_12                  :bit2;
  FREQDIV_12                    :bit2;
  LINKSPEED_13                  :bit2;
  FREQDIV_13                    :bit2;
  LINKSPEED_14                  :bit2;
  FREQDIV_14                    :bit2;
  LINKSPEED_15                  :bit2;
  FREQDIV_15                    :bit2;
 end;

 TPB1_GLB_SCI_STAT_OVRD_REG0=bitpacked record
  IGNR_ALL_CBI_UPDT_L0T3     :bit1;
  IGNR_ALL_CBI_UPDT_L4T7     :bit1;
  IGNR_ALL_CBI_UPDT_L8T11    :bit1;
  IGNR_ALL_CBI_UPDT_L12T15   :bit1;
  IGNR_IMPCAL_ACTIVE_CBI_UPDT:bit1;
  RESERVED0                  :bit3;
  TXNIMP                     :bit4;
  TXPIMP                     :bit4;
  RXIMP                      :bit4;
  IMPCAL_ACTIVE              :bit1;
  RESERVED1                  :bit11;
 end;

 TPB1_GLB_SCI_STAT_OVRD_REG1=bitpacked record
  IGNR_LINKSPEED_CBI_UPDT_L0T3:bit1;
  IGNR_FREQDIV_CBI_UPDT_L0T3  :bit1;
  IGNR_DLL_LOCK_CBI_UPDT_L0T3 :bit1;
  RESERVED0                   :bit9;
  DLL_LOCK_0                  :bit1;
  DLL_LOCK_1                  :bit1;
  DLL_LOCK_2                  :bit1;
  DLL_LOCK_3                  :bit1;
  LINKSPEED_0                 :bit2;
  FREQDIV_0                   :bit2;
  LINKSPEED_1                 :bit2;
  FREQDIV_1                   :bit2;
  LINKSPEED_2                 :bit2;
  FREQDIV_2                   :bit2;
  LINKSPEED_3                 :bit2;
  FREQDIV_3                   :bit2;
 end;

 TPB1_GLB_SCI_STAT_OVRD_REG2=bitpacked record
  IGNR_LINKSPEED_CBI_UPDT_L4T7:bit1;
  IGNR_FREQDIV_CBI_UPDT_L4T7  :bit1;
  IGNR_DLL_LOCK_CBI_UPDT_L4T7 :bit1;
  RESERVED0                   :bit9;
  DLL_LOCK_4                  :bit1;
  DLL_LOCK_5                  :bit1;
  DLL_LOCK_6                  :bit1;
  DLL_LOCK_7                  :bit1;
  LINKSPEED_4                 :bit2;
  FREQDIV_4                   :bit2;
  LINKSPEED_5                 :bit2;
  FREQDIV_5                   :bit2;
  LINKSPEED_6                 :bit2;
  FREQDIV_6                   :bit2;
  LINKSPEED_7                 :bit2;
  FREQDIV_7                   :bit2;
 end;

 TPB1_GLB_SCI_STAT_OVRD_REG3=bitpacked record
  IGNR_LINKSPEED_CBI_UPDT_L8T11:bit1;
  IGNR_FREQDIV_CBI_UPDT_L8T11  :bit1;
  IGNR_DLL_LOCK_CBI_UPDT_L8T11 :bit1;
  RESERVED0                    :bit9;
  DLL_LOCK_8                   :bit1;
  DLL_LOCK_9                   :bit1;
  DLL_LOCK_10                  :bit1;
  DLL_LOCK_11                  :bit1;
  LINKSPEED_8                  :bit2;
  FREQDIV_8                    :bit2;
  LINKSPEED_9                  :bit2;
  FREQDIV_9                    :bit2;
  LINKSPEED_10                 :bit2;
  FREQDIV_10                   :bit2;
  LINKSPEED_11                 :bit2;
  FREQDIV_11                   :bit2;
 end;

 TPB1_GLB_SCI_STAT_OVRD_REG4=bitpacked record
  IGNR_LINKSPEED_CBI_UPDT_L12T15:bit1;
  IGNR_FREQDIV_CBI_UPDT_L12T15  :bit1;
  IGNR_DLL_LOCK_CBI_UPDT_L12T15 :bit1;
  RESERVED0                     :bit9;
  DLL_LOCK_12                   :bit1;
  DLL_LOCK_13                   :bit1;
  DLL_LOCK_14                   :bit1;
  DLL_LOCK_15                   :bit1;
  LINKSPEED_12                  :bit2;
  FREQDIV_12                    :bit2;
  LINKSPEED_13                  :bit2;
  FREQDIV_13                    :bit2;
  LINKSPEED_14                  :bit2;
  FREQDIV_14                    :bit2;
  LINKSPEED_15                  :bit2;
  FREQDIV_15                    :bit2;
 end;

 TPCIE_DPA_LATENCY_INDICATOR=bitpacked record
  TRANS_LAT_INDICATOR_BITS:bit8;
  RESERVED0               :bit24;
 end;

 TPCIE_LC_FORCE_EQ_REQ_COEFF=bitpacked record
  LC_FORCE_COEFF_IN_EQ_REQ_PHASE:bit1;
  LC_FORCE_PRE_CURSOR_REQ       :bit6;
  LC_FORCE_CURSOR_REQ           :bit6;
  LC_FORCE_POST_CURSOR_REQ      :bit6;
  LC_FS_OTHER_END               :bit6;
  LC_LF_OTHER_END               :bit6;
  RESERVED0                     :bit1;
 end;

 TPCIE_PAGE_REQ_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_PERF_CNTL_SLV_S_C_CLK=bitpacked record
  EVENT0_SEL    :bit8;
  EVENT1_SEL    :bit8;
  COUNTER0_UPPER:bit8;
  COUNTER1_UPPER:bit8;
 end;

 TPCIE_PERF_COUNT0_MST_C_CLK=bit32;

 TPCIE_PERF_COUNT0_MST_R_CLK=bit32;

 TPCIE_PERF_COUNT0_SLV_R_CLK=bit32;

 TPCIE_PERF_COUNT1_MST_C_CLK=bit32;

 TPCIE_PERF_COUNT1_MST_R_CLK=bit32;

 TPCIE_PERF_COUNT1_SLV_R_CLK=bit32;

 TPCIE_SRIOV_FIRST_VF_OFFSET=bitpacked record
  SRIOV_FIRST_VF_OFFSET:bit16;
  RESERVED0            :bit16;
 end;

 TPCIE_TPH_REQR_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPIPE0_ARBITRATION_CONTROL3=bitpacked record
  EFFICIENCY_WEIGHT:bit16;
  RESERVED0        :bit16;
 end;

 TPIPE1_ARBITRATION_CONTROL3=bitpacked record
  EFFICIENCY_WEIGHT:bit16;
  RESERVED0        :bit16;
 end;

 TPIPE2_ARBITRATION_CONTROL3=bitpacked record
  EFFICIENCY_WEIGHT:bit16;
  RESERVED0        :bit16;
 end;

 TPIPE3_ARBITRATION_CONTROL3=bitpacked record
  EFFICIENCY_WEIGHT:bit16;
  RESERVED0        :bit16;
 end;

 TPIPE4_ARBITRATION_CONTROL3=bitpacked record
  EFFICIENCY_WEIGHT:bit16;
  RESERVED0        :bit16;
 end;

 TPIPE5_ARBITRATION_CONTROL3=bitpacked record
  EFFICIENCY_WEIGHT:bit16;
  RESERVED0        :bit16;
 end;

 TPIPE6_ARBITRATION_CONTROL3=bitpacked record
  EFFICIENCY_WEIGHT:bit16;
  RESERVED0        :bit16;
 end;

 TPIPE7_ARBITRATION_CONTROL3=bitpacked record
  EFFICIENCY_WEIGHT:bit16;
  RESERVED0        :bit16;
 end;

 TREGAMMA_CNTLA_REGION_10_11=bitpacked record
  REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET  :bit9;
  RESERVED0                              :bit3;
  REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS:bit3;
  RESERVED1                              :bit1;
  REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET  :bit9;
  RESERVED2                              :bit3;
  REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS:bit3;
  RESERVED3                              :bit1;
 end;

 TREGAMMA_CNTLA_REGION_12_13=bitpacked record
  REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET  :bit9;
  RESERVED0                              :bit3;
  REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS:bit3;
  RESERVED1                              :bit1;
  REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET  :bit9;
  RESERVED2                              :bit3;
  REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS:bit3;
  RESERVED3                              :bit1;
 end;

 TREGAMMA_CNTLA_REGION_14_15=bitpacked record
  REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET  :bit9;
  RESERVED0                              :bit3;
  REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS:bit3;
  RESERVED1                              :bit1;
  REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET  :bit9;
  RESERVED2                              :bit3;
  REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS:bit3;
  RESERVED3                              :bit1;
 end;

 TREGAMMA_CNTLB_REGION_10_11=bitpacked record
  REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET  :bit9;
  RESERVED0                              :bit3;
  REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS:bit3;
  RESERVED1                              :bit1;
  REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET  :bit9;
  RESERVED2                              :bit3;
  REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS:bit3;
  RESERVED3                              :bit1;
 end;

 TREGAMMA_CNTLB_REGION_12_13=bitpacked record
  REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET  :bit9;
  RESERVED0                              :bit3;
  REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS:bit3;
  RESERVED1                              :bit1;
  REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET  :bit9;
  RESERVED2                              :bit3;
  REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS:bit3;
  RESERVED3                              :bit1;
 end;

 TREGAMMA_CNTLB_REGION_14_15=bitpacked record
  REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET  :bit9;
  RESERVED0                              :bit3;
  REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS:bit3;
  RESERVED1                              :bit1;
  REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET  :bit9;
  RESERVED2                              :bit3;
  REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS:bit3;
  RESERVED3                              :bit1;
 end;

 TRLC_GPU_IOV_VIRT_RESET_REQ=bitpacked record
  VF_FLR     :bit16;
  RESERVED   :bit15;
  SOFT_PF_FLR:bit1;
 end;

 TRLC_SERDES_RD_MASTER_INDEX=bitpacked record
  CU_ID      :bit4;
  SH_ID      :bit2;
  SE_ID      :bit3;
  SE_NONCU_ID:bit1;
  SE_NONCU   :bit1;
  NON_SE     :bit4;
  DATA_REG_ID:bit2;
  SPARE      :bit15;
 end;

 TRLC_SMU_GRBM_REG_SAVE_CTRL=bitpacked record
  START_GRBM_REG_SAVE:bit1;
  SPARE              :bit31;
 end;

 TRLC_SPM_GLOBAL_MUXSEL_ADDR=bit32;

 TRLC_SPM_GLOBAL_MUXSEL_DATA=bit32;

 TRLC_SRM_GPM_COMMAND_STATUS=bitpacked record
  FIFO_EMPTY:bit1;
  FIFO_FULL :bit1;
  RESERVED  :bit30;
 end;

 TSAM_IH_EXT_ERR_INTR_STATUS=bitpacked record
  UVD      :bit1;
  VCE      :bit1;
  ISP      :bit1;
  RESERVED0:bit29;
 end;

 TSCL_AUTOMATIC_MODE_CONTROL=bitpacked record
  SCL_V_CALC_AUTO_RATIO_EN:bit1;
  RESERVED0               :bit15;
  SCL_H_CALC_AUTO_RATIO_EN:bit1;
  RESERVED1               :bit15;
 end;

 TSDMA0_RLC0_RB_RPTR_ADDR_HI=bit32;

 TSDMA0_RLC0_RB_RPTR_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA0_RLC1_RB_RPTR_ADDR_HI=bit32;

 TSDMA0_RLC1_RB_RPTR_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA1_RLC0_RB_RPTR_ADDR_HI=bit32;

 TSDMA1_RLC0_RB_RPTR_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA1_RLC1_RB_RPTR_ADDR_HI=bit32;

 TSDMA1_RLC1_RB_RPTR_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSLAVE_HANG_PROTECTION_CNTL=bitpacked record
  RESERVED0                :bit1;
  HANG_PROTECTION_TIMER_SEL:bit3;
  RESERVED1                :bit28;
 end;

 TSPI_P0_TRAP_SCREEN_GPR_MIN=bitpacked record
  VGPR_MIN :bit6;
  SGPR_MIN :bit4;
  RESERVED0:bit22;
 end;

 TSPI_P0_TRAP_SCREEN_PSBA_HI=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_P0_TRAP_SCREEN_PSBA_LO=bit32;

 TSPI_P0_TRAP_SCREEN_PSMA_HI=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_P0_TRAP_SCREEN_PSMA_LO=bit32;

 TSPI_P1_TRAP_SCREEN_GPR_MIN=bitpacked record
  VGPR_MIN :bit6;
  SGPR_MIN :bit4;
  RESERVED0:bit22;
 end;

 TSPI_P1_TRAP_SCREEN_PSBA_HI=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_P1_TRAP_SCREEN_PSBA_LO=bit32;

 TSPI_P1_TRAP_SCREEN_PSMA_HI=bitpacked record
  MEM_BASE :bit8;
  RESERVED0:bit24;
 end;

 TSPI_P1_TRAP_SCREEN_PSMA_LO=bit32;

 TSPI_RESOURCE_RESERVE_CU_10=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_11=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_12=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_13=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_14=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_RESOURCE_RESERVE_CU_15=bitpacked record
  VGPR     :bit4;
  SGPR     :bit4;
  LDS      :bit4;
  WAVES    :bit3;
  BARRIERS :bit4;
  RESERVED0:bit13;
 end;

 TSPI_SHADER_PGM_RSRC2_ES_GS=bitpacked record
  SCRATCH_EN  :bit1;
  USER_SGPR   :bit5;
  TRAP_PRESENT:bit1;
  OC_LDS_EN   :bit1;
  EXCP_EN     :bit9;
  RESERVED0   :bit3;
  LDS_SIZE    :bit9;
  RESERVED1   :bit3;
 end;

 TSPI_SHADER_PGM_RSRC2_ES_VS=bitpacked record
  SCRATCH_EN  :bit1;
  USER_SGPR   :bit5;
  TRAP_PRESENT:bit1;
  OC_LDS_EN   :bit1;
  EXCP_EN     :bit9;
  RESERVED0   :bit3;
  LDS_SIZE    :bit9;
  RESERVED1   :bit3;
 end;

 TSPI_SHADER_PGM_RSRC2_LS_ES=bitpacked record
  SCRATCH_EN  :bit1;
  USER_SGPR   :bit5;
  TRAP_PRESENT:bit1;
  LDS_SIZE    :bit9;
  EXCP_EN     :bit9;
  RESERVED0   :bit7;
 end;

 TSPI_SHADER_PGM_RSRC2_LS_HS=bitpacked record
  SCRATCH_EN  :bit1;
  USER_SGPR   :bit5;
  TRAP_PRESENT:bit1;
  LDS_SIZE    :bit9;
  EXCP_EN     :bit9;
  RESERVED0   :bit7;
 end;

 TSPI_SHADER_PGM_RSRC2_LS_VS=bitpacked record
  SCRATCH_EN  :bit1;
  USER_SGPR   :bit5;
  TRAP_PRESENT:bit1;
  LDS_SIZE    :bit9;
  EXCP_EN     :bit9;
  RESERVED0   :bit7;
 end;

 TSPI_SHADER_USER_DATA_ES_10=bit32;

 TSPI_SHADER_USER_DATA_ES_11=bit32;

 TSPI_SHADER_USER_DATA_ES_12=bit32;

 TSPI_SHADER_USER_DATA_ES_13=bit32;

 TSPI_SHADER_USER_DATA_ES_14=bit32;

 TSPI_SHADER_USER_DATA_ES_15=bit32;

 TSPI_SHADER_USER_DATA_GS_10=bit32;

 TSPI_SHADER_USER_DATA_GS_11=bit32;

 TSPI_SHADER_USER_DATA_GS_12=bit32;

 TSPI_SHADER_USER_DATA_GS_13=bit32;

 TSPI_SHADER_USER_DATA_GS_14=bit32;

 TSPI_SHADER_USER_DATA_GS_15=bit32;

 TSPI_SHADER_USER_DATA_HS_10=bit32;

 TSPI_SHADER_USER_DATA_HS_11=bit32;

 TSPI_SHADER_USER_DATA_HS_12=bit32;

 TSPI_SHADER_USER_DATA_HS_13=bit32;

 TSPI_SHADER_USER_DATA_HS_14=bit32;

 TSPI_SHADER_USER_DATA_HS_15=bit32;

 TSPI_SHADER_USER_DATA_LS_10=bit32;

 TSPI_SHADER_USER_DATA_LS_11=bit32;

 TSPI_SHADER_USER_DATA_LS_12=bit32;

 TSPI_SHADER_USER_DATA_LS_13=bit32;

 TSPI_SHADER_USER_DATA_LS_14=bit32;

 TSPI_SHADER_USER_DATA_LS_15=bit32;

 TSPI_SHADER_USER_DATA_PS_10=bit32;

 TSPI_SHADER_USER_DATA_PS_11=bit32;

 TSPI_SHADER_USER_DATA_PS_12=bit32;

 TSPI_SHADER_USER_DATA_PS_13=bit32;

 TSPI_SHADER_USER_DATA_PS_14=bit32;

 TSPI_SHADER_USER_DATA_PS_15=bit32;

 TSPI_SHADER_USER_DATA_VS_10=bit32;

 TSPI_SHADER_USER_DATA_VS_11=bit32;

 TSPI_SHADER_USER_DATA_VS_12=bit32;

 TSPI_SHADER_USER_DATA_VS_13=bit32;

 TSPI_SHADER_USER_DATA_VS_14=bit32;

 TSPI_SHADER_USER_DATA_VS_15=bit32;

 TSPI_SX_EXPORT_BUFFER_SIZES=bitpacked record
  COLOR_BUFFER_SIZE   :bit16;
  POSITION_BUFFER_SIZE:bit16;
 end;

 TSQ_THREAD_TRACE_TOKEN_MASK=bitpacked record
  TOKEN_MASK       :bit16;
  REG_MASK         :bit8;
  REG_DROP_ON_STALL:bit1;
  RESERVED0        :bit7;
 end;

 TSQ_THREAD_TRACE_USERDATA_0=bit32;

 TSQ_THREAD_TRACE_USERDATA_1=bit32;

 TSQ_THREAD_TRACE_USERDATA_2=bit32;

 TSQ_THREAD_TRACE_USERDATA_3=bit32;

 TSQ_THREAD_TRACE_WORD_EVENT=bitpacked record
  TOKEN_TYPE:bit4;
  TIME_DELTA:bit1;
  SH_ID     :bit1;
  STAGE     :bit3;
  RESERVED0 :bit1;
  EVENT_TYPE:bit6;
  RESERVED1 :bit16;
 end;

 TSQ_THREAD_TRACE_WORD_ISSUE=bitpacked record
  TOKEN_TYPE:bit4;
  TIME_DELTA:bit1;
  SIMD_ID   :bit2;
  RESERVED0 :bit1;
  INST0     :bit2;
  INST1     :bit2;
  INST2     :bit2;
  INST3     :bit2;
  INST4     :bit2;
  INST5     :bit2;
  INST6     :bit2;
  INST7     :bit2;
  INST8     :bit2;
  INST9     :bit2;
  RESERVED1 :bit4;
 end;

 TTMDS_SYNC_CHAR_PATTERN_0_1=bitpacked record
  TMDS_SYNC_CHAR_PATTERN0:bit10;
  RESERVED0              :bit6;
  TMDS_SYNC_CHAR_PATTERN1:bit10;
  RESERVED1              :bit6;
 end;

 TTMDS_SYNC_CHAR_PATTERN_2_3=bitpacked record
  TMDS_SYNC_CHAR_PATTERN2:bit10;
  RESERVED0              :bit6;
  TMDS_SYNC_CHAR_PATTERN3:bit10;
  RESERVED1              :bit6;
 end;

 TUNP_GRPH_INTERRUPT_CONTROL=bitpacked record
  GRPH_PFLIP_INT_MASK:bit1;
  RESERVED0          :bit7;
  GRPH_PFLIP_INT_TYPE:bit1;
  RESERVED1          :bit23;
 end;

 TUVD_MIF_RECON1_ADDR_CONFIG=bitpacked record
  NUM_PIPES              :bit3;
  RESERVED0              :bit1;
  PIPE_INTERLEAVE_SIZE   :bit3;
  RESERVED1              :bit1;
  BANK_INTERLEAVE_SIZE   :bit3;
  RESERVED2              :bit1;
  NUM_SHADER_ENGINES     :bit2;
  RESERVED3              :bit2;
  SHADER_ENGINE_TILE_SIZE:bit3;
  RESERVED4              :bit1;
  NUM_GPUS               :bit3;
  RESERVED5              :bit1;
  MULTI_GPU_TILE_SIZE    :bit2;
  RESERVED6              :bit2;
  ROW_SIZE               :bit2;
  NUM_LOWER_PIPES        :bit1;
  RESERVED7              :bit1;
 end;

 TVGT_MULTI_PRIM_IB_RESET_EN=bitpacked record
  RESET_EN :bit1;
  RESERVED0:bit31;
 end;

 TVM_PRT_APERTURE0_HIGH_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TVM_PRT_APERTURE1_HIGH_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TVM_PRT_APERTURE2_HIGH_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TVM_PRT_APERTURE3_HIGH_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TXDMA_LOCAL_SURFACE_TILING1=bitpacked record
  XDMA_LOCAL_ARRAY_MODE       :bit4;
  XDMA_LOCAL_TILE_SPLIT       :bit3;
  RESERVED0                   :bit1;
  XDMA_LOCAL_BANK_WIDTH       :bit2;
  XDMA_LOCAL_BANK_HEIGHT      :bit2;
  XDMA_LOCAL_MACRO_TILE_ASPECT:bit2;
  RESERVED1                   :bit6;
  XDMA_LOCAL_NUM_BANKS        :bit2;
  RESERVED2                   :bit10;
 end;

 TXDMA_LOCAL_SURFACE_TILING2=bitpacked record
  XDMA_LOCAL_PIPE_INTERLEAVE_SIZE:bit3;
  RESERVED0                      :bit17;
  XDMA_LOCAL_MICRO_TILE_MODE     :bit3;
  RESERVED1                      :bit4;
  XDMA_LOCAL_PIPE_CONFIG         :bit5;
 end;

 TXDMA_MC_PCIE_CLIENT_CONFIG=bitpacked record
  RESERVED0        :bit8;
  XDMA_MC_PCIE_SWAP:bit2;
  RESERVED1        :bit2;
  XDMA_MC_PCIE_VMID:bit4;
  XDMA_MC_PCIE_PRIV:bit1;
  RESERVED2        :bit15;
 end;

 TXDMA_MSTR_PCIE_NACK_STATUS=bitpacked record
  XDMA_MSTR_PCIE_NACK_TAG:bit10;
  RESERVED0              :bit2;
  XDMA_MSTR_PCIE_NACK    :bit2;
  RESERVED1              :bit2;
  XDMA_MSTR_PCIE_NACK_CLR:bit1;
  RESERVED2              :bit15;
 end;

 TXDMA_SLV_MEM_CLIENT_CONFIG=bitpacked record
  RESERVED0               :bit8;
  XDMA_SLV_MEM_CLIENT_SWAP:bit2;
  RESERVED1               :bit2;
  XDMA_SLV_MEM_CLIENT_VMID:bit4;
  XDMA_SLV_MEM_CLIENT_PRIV:bit1;
  RESERVED2               :bit15;
 end;

 TXDMA_SLV_WRITE_URGENT_CNTL=bitpacked record
  XDMA_SLV_WRITE_STALL       :bit1;
  RESERVED0                  :bit7;
  XDMA_SLV_WRITE_URGENT_LEVEL:bit4;
  XDMA_SLV_WRITE_STALL_DELAY :bit4;
  RESERVED1                  :bit16;
 end;

 TAZALIA_F0_GTC_GROUP_OFFSET0=bit32;

 TAZALIA_F0_GTC_GROUP_OFFSET1=bit32;

 TAZALIA_F0_GTC_GROUP_OFFSET2=bit32;

 TAZALIA_F0_GTC_GROUP_OFFSET3=bit32;

 TAZALIA_F0_GTC_GROUP_OFFSET4=bit32;

 TAZALIA_F0_GTC_GROUP_OFFSET5=bit32;

 TAZALIA_F0_GTC_GROUP_OFFSET6=bit32;

 TBIF_CC_RFE_IMP_OVERRIDECNTL=bitpacked record
  RESERVED0                    :bit1;
  STRAP_PLL_RX_IMPVAL          :bit4;
  STRAP_PLL_RX_IMPVAL_EN       :bit1;
  STRAP_PLL_TX_IMPVAL_PD       :bit4;
  STRAP_PLL_TX_IMPVAL_EN_PD    :bit1;
  STRAP_PLL_TX_IMPVAL_PU       :bit4;
  STRAP_PLL_TX_IMPVAL_EN_PU    :bit1;
  STRAP_PLL_IMP_DBG_ANALOG_EN  :bit1;
  STRAP_PLL_IMP_IGNORE_QUICKSIM:bit1;
  RESERVED1                    :bit14;
 end;

 TBIF_DOORBELL_GBLAPER1_LOWER=bitpacked record
  RESERVED0              :bit2;
  DOORBELL_GBLAPER1_LOWER:bit10;
  RESERVED1              :bit19;
  DOORBELL_GBLAPER1_EN   :bit1;
 end;

 TBIF_DOORBELL_GBLAPER1_UPPER=bitpacked record
  RESERVED0              :bit2;
  DOORBELL_GBLAPER1_UPPER:bit10;
  RESERVED1              :bit20;
 end;

 TBIF_DOORBELL_GBLAPER2_LOWER=bitpacked record
  RESERVED0              :bit2;
  DOORBELL_GBLAPER2_LOWER:bit10;
  RESERVED1              :bit19;
  DOORBELL_GBLAPER2_EN   :bit1;
 end;

 TBIF_DOORBELL_GBLAPER2_UPPER=bitpacked record
  RESERVED0              :bit2;
  DOORBELL_GBLAPER2_UPPER:bit10;
  RESERVED1              :bit20;
 end;

 TBIF_GPUIOV_FB_TOTAL_FB_INFO=bitpacked record
  TOTAL_FB_AVAILABLE:bit16;
  TOTAL_FB_CONSUMED :bit16;
 end;

 TBIF_RFE_MST_SMBUS_CMDSTATUS=bitpacked record
  REG_SMBUS_clkGate_timer :bit8;
  REG_SMBUS_clkSetup_timer:bit4;
  RESERVED0               :bit4;
  REG_SMBUS_timeout_timer :bit8;
  SMBUS_RFE_mstTimeout    :bit1;
  RESERVED1               :bit7;
 end;

 TBL1_PWM_AMBIENT_LIGHT_LEVEL=bitpacked record
  BL1_PWM_AMBIENT_LIGHT_LEVEL:bit17;
  RESERVED0                  :bit15;
 end;

 TCOMPUTE_PIPELINESTAT_ENABLE=bitpacked record
  PIPELINESTAT_ENABLE:bit1;
  RESERVED0          :bit31;
 end;

 TCOMPUTE_THREAD_TRACE_ENABLE=bitpacked record
  THREAD_TRACE_ENABLE:bit1;
  RESERVED0          :bit31;
 end;

 TCP_CE_METADATA_BASE_ADDR_HI=bitpacked record
  ADDR_HI  :bit16;
  RESERVED0:bit16;
 end;

 TCP_HQD_PQ_WPTR_POLL_ADDR_HI=bitpacked record
  WPTR_ADDR_HI:bit16;
  RESERVED0   :bit16;
 end;

 TCP_MEC_DOORBELL_RANGE_LOWER=bitpacked record
  RESERVED0           :bit2;
  DOORBELL_RANGE_LOWER:bit21;
  RESERVED1           :bit9;
 end;

 TCP_MEC_DOORBELL_RANGE_UPPER=bitpacked record
  RESERVED0           :bit2;
  DOORBELL_RANGE_UPPER:bit21;
  RESERVED1           :bit9;
 end;

 TCP_PFP_GDS_ATOMIC0_PREOP_HI=bit32;

 TCP_PFP_GDS_ATOMIC0_PREOP_LO=bit32;

 TCP_PFP_GDS_ATOMIC1_PREOP_HI=bit32;

 TCP_PFP_GDS_ATOMIC1_PREOP_LO=bit32;

 TCRTC_CRC0_WINDOWA_X_CONTROL=bitpacked record
  CRTC_CRC0_WINDOWA_X_START:bit14;
  RESERVED0                :bit2;
  CRTC_CRC0_WINDOWA_X_END  :bit14;
  RESERVED1                :bit2;
 end;

 TCRTC_CRC0_WINDOWA_Y_CONTROL=bitpacked record
  CRTC_CRC0_WINDOWA_Y_START:bit14;
  RESERVED0                :bit2;
  CRTC_CRC0_WINDOWA_Y_END  :bit14;
  RESERVED1                :bit2;
 end;

 TCRTC_CRC0_WINDOWB_X_CONTROL=bitpacked record
  CRTC_CRC0_WINDOWB_X_START:bit14;
  RESERVED0                :bit2;
  CRTC_CRC0_WINDOWB_X_END  :bit14;
  RESERVED1                :bit2;
 end;

 TCRTC_CRC0_WINDOWB_Y_CONTROL=bitpacked record
  CRTC_CRC0_WINDOWB_Y_START:bit14;
  RESERVED0                :bit2;
  CRTC_CRC0_WINDOWB_Y_END  :bit14;
  RESERVED1                :bit2;
 end;

 TCRTC_CRC1_WINDOWA_X_CONTROL=bitpacked record
  CRTC_CRC1_WINDOWA_X_START:bit14;
  RESERVED0                :bit2;
  CRTC_CRC1_WINDOWA_X_END  :bit14;
  RESERVED1                :bit2;
 end;

 TCRTC_CRC1_WINDOWA_Y_CONTROL=bitpacked record
  CRTC_CRC1_WINDOWA_Y_START:bit14;
  RESERVED0                :bit2;
  CRTC_CRC1_WINDOWA_Y_END  :bit14;
  RESERVED1                :bit2;
 end;

 TCRTC_CRC1_WINDOWB_X_CONTROL=bitpacked record
  CRTC_CRC1_WINDOWB_X_START:bit14;
  RESERVED0                :bit2;
  CRTC_CRC1_WINDOWB_X_END  :bit14;
  RESERVED1                :bit2;
 end;

 TCRTC_CRC1_WINDOWB_Y_CONTROL=bitpacked record
  CRTC_CRC1_WINDOWB_Y_START:bit14;
  RESERVED0                :bit2;
  CRTC_CRC1_WINDOWB_Y_END  :bit14;
  RESERVED1                :bit2;
 end;

 TCRTC_MVP_INBAND_CNTL_INSERT=bitpacked record
  CRTC_MVP_INBAND_OUT_MODE        :bit2;
  RESERVED0                       :bit6;
  CRTC_MVP_INBAND_CNTL_CHAR_INSERT:bit24;
 end;

 TDCFEV0_CRTC_PIXEL_RATE_CNTL=bitpacked record
  DCFEV0_CRTC_PIXEL_RATE_SOURCE:bit2;
  RESERVED0                    :bit30;
 end;

 TDC_GPU_TIMER_START_POSITION=bitpacked record
  RESERVED0:bit3;
  RESERVED1:bit13;
  RESERVED2:bit3;
  RESERVED3:bit13;
 end;

 TDMCU_DPRX_INTERRUPT_STATUS1=bitpacked record
  DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED                        :bit1;
  DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED      :bit1;
  DPRX_SD0P0_VERTICAL_INT0_OCCURRED                           :bit1;
  DPRX_SD0P0_VERTICAL_INT1_OCCURRED                           :bit1;
  DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED                        :bit1;
  DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED                        :bit1;
  DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED      :bit1;
  DPRX_SD1P0_VERTICAL_INT0_OCCURRED                           :bit1;
  DPRX_SD1P0_VERTICAL_INT1_OCCURRED                           :bit1;
  DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED                        :bit1;
  DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED :bit1;
  DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED :bit1;
  DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED      :bit1;
  DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED   :bit1;
  DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED    :bit1;
  DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED:bit1;
  DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED         :bit1;
  DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED                    :bit1;
  DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED                     :bit1;
  DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED                    :bit1;
  DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED                   :bit1;
  DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED              :bit1;
  DPRX_AUX_P0_AUX_INT_OCCURRED                                :bit1;
  DPRX_AUX_P0_I2C_INT_OCCURRED                                :bit1;
  DPRX_AUX_P0_CPU_INT_OCCURRED                                :bit1;
  DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED                       :bit1;
  DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED                       :bit1;
  DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED                       :bit1;
  DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED                       :bit1;
  RESERVED0                                                   :bit1;
  RESERVED1                                                   :bit1;
  RESERVED2                                                   :bit1;
 end;

 TDMCU_UC_INTERNAL_INT_STATUS=bitpacked record
  UC_INT_IRQ_N_PIN                             :bit1;
  UC_INT_XIRQ_N_PIN                            :bit1;
  UC_INT_SOFTWARE_INTERRUPT                    :bit1;
  UC_INT_ILLEGAL_OPCODE_TRAP                   :bit1;
  UC_INT_TIMER_OUTPUT_COMPARE_4                :bit1;
  UC_INT_TIMER_OUTPUT_COMPARE_3                :bit1;
  UC_INT_TIMER_OUTPUT_COMPARE_2                :bit1;
  UC_INT_TIMER_OUTPUT_COMPARE_1                :bit1;
  UC_INT_TIMER_OVERFLOW                        :bit1;
  UC_INT_REAL_TIME_INTERRUPT                   :bit1;
  UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5:bit1;
  UC_INT_TIMER_INPUT_CAPTURE_3                 :bit1;
  UC_INT_TIMER_INPUT_CAPTURE_2                 :bit1;
  UC_INT_TIMER_INPUT_CAPTURE_1                 :bit1;
  UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE          :bit1;
  UC_INT_PULSE_ACCUMULATOR_OVERFLOW            :bit1;
  RESERVED0                                    :bit16;
 end;

 TGAMMA_CORR_CNTLA_REGION_0_1=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET  :bit8;
  RESERVED0                                :bit3;
  GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS:bit3;
  RESERVED1                                :bit1;
  GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET  :bit8;
  RESERVED2                                :bit4;
  GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS:bit3;
  RESERVED3                                :bit2;
 end;

 TGAMMA_CORR_CNTLA_REGION_2_3=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET  :bit8;
  RESERVED0                                :bit3;
  GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS:bit3;
  RESERVED1                                :bit1;
  GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET  :bit8;
  RESERVED2                                :bit4;
  GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS:bit3;
  RESERVED3                                :bit2;
 end;

 TGAMMA_CORR_CNTLA_REGION_4_5=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET  :bit8;
  RESERVED0                                :bit3;
  GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS:bit3;
  RESERVED1                                :bit1;
  GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET  :bit8;
  RESERVED2                                :bit4;
  GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS:bit3;
  RESERVED3                                :bit2;
 end;

 TGAMMA_CORR_CNTLA_REGION_6_7=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET  :bit8;
  RESERVED0                                :bit3;
  GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS:bit3;
  RESERVED1                                :bit1;
  GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET  :bit8;
  RESERVED2                                :bit4;
  GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS:bit3;
  RESERVED3                                :bit2;
 end;

 TGAMMA_CORR_CNTLA_REGION_8_9=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET  :bit8;
  RESERVED0                                :bit3;
  GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS:bit3;
  RESERVED1                                :bit1;
  GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET  :bit8;
  RESERVED2                                :bit4;
  GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS:bit3;
  RESERVED3                                :bit2;
 end;

 TGAMMA_CORR_CNTLA_SLOPE_CNTL=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE:bit18;
  RESERVED0                               :bit14;
 end;

 TGAMMA_CORR_CNTLA_START_CNTL=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION_START        :bit18;
  RESERVED0                                :bit2;
  GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT:bit7;
  RESERVED1                                :bit5;
 end;

 TGAMMA_CORR_CNTLB_REGION_0_1=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET  :bit8;
  RESERVED0                                :bit3;
  GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS:bit3;
  RESERVED1                                :bit1;
  GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET  :bit8;
  RESERVED2                                :bit4;
  GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS:bit3;
  RESERVED3                                :bit2;
 end;

 TGAMMA_CORR_CNTLB_REGION_2_3=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET  :bit8;
  RESERVED0                                :bit3;
  GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS:bit3;
  RESERVED1                                :bit1;
  GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET  :bit8;
  RESERVED2                                :bit4;
  GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS:bit3;
  RESERVED3                                :bit2;
 end;

 TGAMMA_CORR_CNTLB_REGION_4_5=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET  :bit8;
  RESERVED0                                :bit3;
  GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS:bit3;
  RESERVED1                                :bit1;
  GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET  :bit8;
  RESERVED2                                :bit4;
  GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS:bit3;
  RESERVED3                                :bit2;
 end;

 TGAMMA_CORR_CNTLB_REGION_6_7=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET  :bit8;
  RESERVED0                                :bit3;
  GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS:bit3;
  RESERVED1                                :bit1;
  GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET  :bit8;
  RESERVED2                                :bit4;
  GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS:bit3;
  RESERVED3                                :bit2;
 end;

 TGAMMA_CORR_CNTLB_REGION_8_9=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET  :bit8;
  RESERVED0                                :bit3;
  GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS:bit3;
  RESERVED1                                :bit1;
  GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET  :bit8;
  RESERVED2                                :bit4;
  GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS:bit3;
  RESERVED3                                :bit2;
 end;

 TGAMMA_CORR_CNTLB_SLOPE_CNTL=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE:bit18;
  RESERVED0                               :bit14;
 end;

 TGAMMA_CORR_CNTLB_START_CNTL=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION_START        :bit18;
  RESERVED0                                :bit2;
  GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT:bit7;
  RESERVED1                                :bit5;
 end;

 TGARLIC_COHE_UVD_RBC_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_VCE_OUT_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGC_USER_SHADER_ARRAY_CONFIG=bitpacked record
  RESERVED0   :bit16;
  INACTIVE_CUS:bit16;
 end;

 TGRBM_SE0_PERFCOUNTER_SELECT=bitpacked record
  PERF_SEL                  :bit6;
  RESERVED0                 :bit4;
  DB_CLEAN_USER_DEFINED_MASK:bit1;
  CB_CLEAN_USER_DEFINED_MASK:bit1;
  TA_BUSY_USER_DEFINED_MASK :bit1;
  SX_BUSY_USER_DEFINED_MASK :bit1;
  RESERVED1                 :bit1;
  SPI_BUSY_USER_DEFINED_MASK:bit1;
  SC_BUSY_USER_DEFINED_MASK :bit1;
  DB_BUSY_USER_DEFINED_MASK :bit1;
  CB_BUSY_USER_DEFINED_MASK :bit1;
  VGT_BUSY_USER_DEFINED_MASK:bit1;
  PA_BUSY_USER_DEFINED_MASK :bit1;
  BCI_BUSY_USER_DEFINED_MASK:bit1;
  RESERVED2                 :bit10;
 end;

 TGRBM_SE1_PERFCOUNTER_SELECT=bitpacked record
  PERF_SEL                  :bit6;
  RESERVED0                 :bit4;
  DB_CLEAN_USER_DEFINED_MASK:bit1;
  CB_CLEAN_USER_DEFINED_MASK:bit1;
  TA_BUSY_USER_DEFINED_MASK :bit1;
  SX_BUSY_USER_DEFINED_MASK :bit1;
  RESERVED1                 :bit1;
  SPI_BUSY_USER_DEFINED_MASK:bit1;
  SC_BUSY_USER_DEFINED_MASK :bit1;
  DB_BUSY_USER_DEFINED_MASK :bit1;
  CB_BUSY_USER_DEFINED_MASK :bit1;
  VGT_BUSY_USER_DEFINED_MASK:bit1;
  PA_BUSY_USER_DEFINED_MASK :bit1;
  BCI_BUSY_USER_DEFINED_MASK:bit1;
  RESERVED2                 :bit10;
 end;

 TGRBM_SE2_PERFCOUNTER_SELECT=bitpacked record
  PERF_SEL                  :bit6;
  RESERVED0                 :bit4;
  DB_CLEAN_USER_DEFINED_MASK:bit1;
  CB_CLEAN_USER_DEFINED_MASK:bit1;
  TA_BUSY_USER_DEFINED_MASK :bit1;
  SX_BUSY_USER_DEFINED_MASK :bit1;
  RESERVED1                 :bit1;
  SPI_BUSY_USER_DEFINED_MASK:bit1;
  SC_BUSY_USER_DEFINED_MASK :bit1;
  DB_BUSY_USER_DEFINED_MASK :bit1;
  CB_BUSY_USER_DEFINED_MASK :bit1;
  VGT_BUSY_USER_DEFINED_MASK:bit1;
  PA_BUSY_USER_DEFINED_MASK :bit1;
  BCI_BUSY_USER_DEFINED_MASK:bit1;
  RESERVED2                 :bit10;
 end;

 TGRBM_SE3_PERFCOUNTER_SELECT=bitpacked record
  PERF_SEL                  :bit6;
  RESERVED0                 :bit4;
  DB_CLEAN_USER_DEFINED_MASK:bit1;
  CB_CLEAN_USER_DEFINED_MASK:bit1;
  TA_BUSY_USER_DEFINED_MASK :bit1;
  SX_BUSY_USER_DEFINED_MASK :bit1;
  RESERVED1                 :bit1;
  SPI_BUSY_USER_DEFINED_MASK:bit1;
  SC_BUSY_USER_DEFINED_MASK :bit1;
  DB_BUSY_USER_DEFINED_MASK :bit1;
  CB_BUSY_USER_DEFINED_MASK :bit1;
  VGT_BUSY_USER_DEFINED_MASK:bit1;
  PA_BUSY_USER_DEFINED_MASK :bit1;
  BCI_BUSY_USER_DEFINED_MASK:bit1;
  RESERVED2                 :bit10;
 end;

 THDMI_GENERIC_PACKET_CONTROL=bitpacked record
  RESERVED0:bit1;
  RESERVED1:bit1;
  RESERVED2:bit2;
  RESERVED3:bit1;
  RESERVED4:bit1;
  RESERVED5:bit10;
  RESERVED6:bit6;
  RESERVED7:bit2;
  RESERVED8:bit6;
  RESERVED9:bit2;
 end;

 TIH_DSM_MATCH_VALUE_BIT_31_0=bit32;

 TMCIF_WB_ARBITRATION_CONTROL=bitpacked record
  MCIF_WB_CLIENT_ARBITRATION_SLICE:bit2;
  RESERVED0                       :bit24;
  MCIF_WB_TIME_PER_PIXEL          :bit6;
 end;

 TMCIF_WB_BUF_1_ADDR_C_OFFSET=bitpacked record
  MCIF_WB_BUF_1_ADDR_C_OFFSET:bit18;
  RESERVED0                  :bit14;
 end;

 TMCIF_WB_BUF_1_ADDR_Y_OFFSET=bitpacked record
  MCIF_WB_BUF_1_ADDR_Y_OFFSET:bit18;
  RESERVED0                  :bit14;
 end;

 TMCIF_WB_BUF_2_ADDR_C_OFFSET=bitpacked record
  MCIF_WB_BUF_2_ADDR_C_OFFSET:bit18;
  RESERVED0                  :bit14;
 end;

 TMCIF_WB_BUF_2_ADDR_Y_OFFSET=bitpacked record
  MCIF_WB_BUF_2_ADDR_Y_OFFSET:bit18;
  RESERVED0                  :bit14;
 end;

 TMCIF_WB_BUF_3_ADDR_C_OFFSET=bitpacked record
  MCIF_WB_BUF_3_ADDR_C_OFFSET:bit18;
  RESERVED0                  :bit14;
 end;

 TMCIF_WB_BUF_3_ADDR_Y_OFFSET=bitpacked record
  MCIF_WB_BUF_3_ADDR_Y_OFFSET:bit18;
  RESERVED0                  :bit14;
 end;

 TMCIF_WB_BUF_4_ADDR_C_OFFSET=bitpacked record
  MCIF_WB_BUF_4_ADDR_C_OFFSET:bit18;
  RESERVED0                  :bit14;
 end;

 TMCIF_WB_BUF_4_ADDR_Y_OFFSET=bitpacked record
  MCIF_WB_BUF_4_ADDR_Y_OFFSET:bit18;
  RESERVED0                  :bit14;
 end;

 TMC_DC_INTERFACE_NACK_STATUS=bitpacked record
  DMIF_RDRET_NACK_OCCURRED:bit1;
  RESERVED0               :bit3;
  DMIF_RDRET_NACK_CLEAR   :bit1;
  RESERVED1               :bit3;
  VIP_WRRET_NACK_OCCURRED :bit1;
  RESERVED2               :bit3;
  VIP_WRRET_NACK_CLEAR    :bit1;
  RESERVED3               :bit3;
  MCIF_RDRET_NACK_OCCURRED:bit1;
  RESERVED4               :bit3;
  MCIF_RDRET_NACK_CLEAR   :bit1;
  RESERVED5               :bit3;
  MCIF_WRRET_NACK_OCCURRED:bit1;
  RESERVED6               :bit3;
  MCIF_WRRET_NACK_CLEAR   :bit1;
  RESERVED7               :bit3;
 end;

 TMC_VM_NB_LOWER_TOP_OF_DRAM2=bitpacked record
  ENABLE    :bit1;
  RESERVED0 :bit22;
  LOWER_TOM2:bit9;
 end;

 TMC_VM_NB_UPPER_TOP_OF_DRAM2=bitpacked record
  UPPER_TOM2:bit8;
  RESERVED0 :bit24;
 end;

 TPA_SC_P3D_TRAP_SCREEN_COUNT=bitpacked record
  COUNT    :bit16;
  RESERVED0:bit16;
 end;

 TPA_SC_P3D_TRAP_SCREEN_HV_EN=bitpacked record
  ENABLE_HV_PRE_SHADER       :bit1;
  FORCE_PRE_SHADER_ALL_PIXELS:bit1;
  RESERVED0                  :bit30;
 end;

 TPCIEP_ERROR_INJECT_PHYSICAL=bitpacked record
  ERROR_INJECT_PL_LANE_ERR           :bit2;
  ERROR_INJECT_PL_FRAMING_ERR        :bit2;
  ERROR_INJECT_PL_BAD_PARITY_IN_SKP  :bit2;
  ERROR_INJECT_PL_BAD_LFSR_IN_SKP    :bit2;
  ERROR_INJECT_PL_LOOPBACK_UFLOW     :bit2;
  ERROR_INJECT_PL_LOOPBACK_OFLOW     :bit2;
  ERROR_INJECT_PL_DESKEW_ERR         :bit2;
  ERROR_INJECT_PL_8B10B_DISPARITY_ERR:bit2;
  ERROR_INJECT_PL_8B10B_DECODE_ERR   :bit2;
  ERROR_INJECT_PL_SKP_OS_ERROR       :bit2;
  ERROR_INJECT_PL_INV_OS_IDENTIFIER  :bit2;
  ERROR_INJECT_PL_BAD_SYNC_HEADER    :bit2;
  RESERVED0                          :bit8;
 end;

 TPCIE_PERF_CNTL_SLV_NS_C_CLK=bitpacked record
  EVENT0_SEL    :bit8;
  EVENT1_SEL    :bit8;
  COUNTER0_UPPER:bit8;
  COUNTER1_UPPER:bit8;
 end;

 TPCIE_PWR_BUDGET_DATA_SELECT=bitpacked record
  DATA_SELECT:bit8;
  RESERVED0  :bit24;
 end;

 TPCIE_RX_CREDITS_ALLOCATED_P=bitpacked record
  RX_CREDITS_ALLOCATED_PD:bit12;
  RESERVED0              :bit4;
  RX_CREDITS_ALLOCATED_PH:bit8;
  RESERVED1              :bit8;
 end;

 TPCIE_SECONDARY_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_SRIOV_SYSTEM_PAGE_SIZE=bit32;

 TREG_ADAPT_pciecore0_CONTROL=bitpacked record
  ACCESS_MODE_pciecore0:bit1;
  RESERVED0            :bit31;
 end;

 TRLC_CAPTURE_GPU_CLOCK_COUNT=bitpacked record
  CAPTURE :bit1;
  RESERVED:bit31;
 end;

 TRLC_SRM_RLCV_COMMAND_STATUS=bitpacked record
  FIFO_EMPTY:bit1;
  FIFO_FULL :bit1;
  RESERVED  :bit30;
 end;

 TSCLV_AUTOMATIC_MODE_CONTROL=bitpacked record
  SCL_V_CALC_AUTO_RATIO_EN:bit1;
  RESERVED0               :bit15;
  SCL_H_CALC_AUTO_RATIO_EN:bit1;
  RESERVED1               :bit15;
 end;

 TSCLV_VERT_FILTER_INIT_BOT_C=bitpacked record
  SCL_V_INIT_FRAC_BOT_C:bit24;
  SCL_V_INIT_INT_BOT_C :bit3;
  RESERVED0            :bit5;
 end;

 TSCL_HORZ_FILTER_SCALE_RATIO=bitpacked record
  SCL_H_SCALE_RATIO:bit26;
  RESERVED0        :bit6;
 end;

 TSCL_VERT_FILTER_SCALE_RATIO=bitpacked record
  SCL_V_SCALE_RATIO:bit26;
  RESERVED0        :bit6;
 end;

 TSDMA0_GFX_RB_WPTR_POLL_CNTL=bitpacked record
  ENABLE         :bit1;
  SWAP_ENABLE    :bit1;
  F32_POLL_ENABLE:bit1;
  RESERVED0      :bit1;
  FREQUENCY      :bit12;
  IDLE_POLL_COUNT:bit16;
 end;

 TSDMA1_GFX_RB_WPTR_POLL_CNTL=bitpacked record
  ENABLE         :bit1;
  SWAP_ENABLE    :bit1;
  F32_POLL_ENABLE:bit1;
  RESERVED0      :bit1;
  FREQUENCY      :bit12;
  IDLE_POLL_COUNT:bit16;
 end;

 TSH_HIDDEN_PRIVATE_BASE_VMID=bit32;

 TSQ_THREAD_TRACE_TOKEN_MASK2=bit32;

 TUNIPHY_DATA_SYNCHRONIZATION=bitpacked record
  UNIPHY_DSYNSEL        :bit1;
  RESERVED0             :bit3;
  UNIPHY_DSYN_LEVEL     :bit2;
  UNIPHY_DSYN_ERROR     :bit1;
  RESERVED1             :bit1;
  UNIPHY_SOURCE_SELECT  :bit1;
  RESERVED2             :bit7;
  UNIPHY_DUAL_LINK_PHASE:bit1;
  RESERVED3             :bit15;
 end;

 TUNIPHY_MACRO_CNTL_RESERVED0=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED1=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED2=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED3=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED4=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED5=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED6=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED7=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED8=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED9=bit32;

 TUNP_GRPH_SURFACE_OFFSET_X_C=bitpacked record
  GRPH_SURFACE_OFFSET_X_C:bit14;
  RESERVED0              :bit18;
 end;

 TUNP_GRPH_SURFACE_OFFSET_X_L=bitpacked record
  GRPH_SURFACE_OFFSET_X_L:bit14;
  RESERVED0              :bit18;
 end;

 TUNP_GRPH_SURFACE_OFFSET_Y_C=bitpacked record
  GRPH_SURFACE_OFFSET_Y_C:bit14;
  RESERVED0              :bit18;
 end;

 TUNP_GRPH_SURFACE_OFFSET_Y_L=bitpacked record
  GRPH_SURFACE_OFFSET_Y_L:bit14;
  RESERVED0              :bit18;
 end;

 TVGA_SEQUENCER_RESET_CONTROL=bitpacked record
  D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET       :bit1;
  D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET       :bit1;
  D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET       :bit1;
  D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET       :bit1;
  D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET       :bit1;
  D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET       :bit1;
  RESERVED0                                   :bit2;
  D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1;
  D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1;
  D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1;
  D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1;
  D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1;
  D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1;
  RESERVED1                                   :bit2;
  VGA_MODE_AUTO_TRIGGER_ENABLE                :bit1;
  VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT       :bit1;
  VGA_MODE_AUTO_TRIGGER_INDEX_SELECT          :bit6;
  RESERVED2                                   :bit8;
 end;

 TVGT_STRMOUT_BUFFER_OFFSET_0=bit32;

 TVGT_STRMOUT_BUFFER_OFFSET_1=bit32;

 TVGT_STRMOUT_BUFFER_OFFSET_2=bit32;

 TVGT_STRMOUT_BUFFER_OFFSET_3=bit32;

 TVGT_VERTEX_REUSE_BLOCK_CNTL=bitpacked record
  VTX_REUSE_DEPTH:bit8;
  RESERVED0      :bit24;
 end;

 TXDMA_MSTR_MEM_CLIENT_CONFIG=bitpacked record
  RESERVED0                :bit8;
  XDMA_MSTR_MEM_CLIENT_SWAP:bit2;
  RESERVED1                :bit2;
  XDMA_MSTR_MEM_CLIENT_VMID:bit4;
  XDMA_MSTR_MEM_CLIENT_PRIV:bit1;
  RESERVED2                :bit15;
 end;

 TXDMA_SLV_READ_LATENCY_TIMER=bitpacked record
  XDMA_SLV_READ_LATENCY_TIMER:bit16;
  RESERVED0                  :bit16;
 end;

 TXDMA_SLV_REMOTE_GPU_ADDRESS=bit32;

 TBPHYC_DAC_AUTO_CALIB_CONTROL=bitpacked record
  BPHYC_DAC_CAL_INITB      :bit1;
  BPHYC_DAC_CAL_EN         :bit1;
  BPHYC_DAC_CAL_DACADJ_EN  :bit1;
  RESERVED0                :bit1;
  BPHYC_DAC_CAL_WAIT_ADJUST:bit10;
  RESERVED1                :bit6;
  BPHYC_DAC_CAL_MASK       :bit3;
  RESERVED2                :bit5;
  BPHYC_DAC_CAL_COMPLETE   :bit1;
  RESERVED3                :bit3;
 end;

 TCOMPUTE_WAVE_RESTORE_ADDR_HI=bitpacked record
  ADDR     :bit16;
  RESERVED0:bit16;
 end;

 TCOMPUTE_WAVE_RESTORE_ADDR_LO=bit32;

 TCOMPUTE_WAVE_RESTORE_CONTROL=bitpacked record
  ATC      :bit1;
  MTYPE    :bit2;
  RESERVED0:bit29;
 end;

 TCP_ECC_FIRSTOCCURRENCE_RING0=bit32;

 TCP_ECC_FIRSTOCCURRENCE_RING1=bit32;

 TCP_ECC_FIRSTOCCURRENCE_RING2=bit32;

 TCP_HQD_CTX_SAVE_BASE_ADDR_HI=bitpacked record
  ADDR_HI  :bit16;
  RESERVED0:bit16;
 end;

 TCP_HQD_CTX_SAVE_BASE_ADDR_LO=bitpacked record
  RESERVED0:bit12;
  ADDR     :bit20;
 end;

 TCP_NUM_PRIM_NEEDED_COUNT0_HI=bit32;

 TCP_NUM_PRIM_NEEDED_COUNT0_LO=bit32;

 TCP_NUM_PRIM_NEEDED_COUNT1_HI=bit32;

 TCP_NUM_PRIM_NEEDED_COUNT1_LO=bit32;

 TCP_NUM_PRIM_NEEDED_COUNT2_HI=bit32;

 TCP_NUM_PRIM_NEEDED_COUNT2_LO=bit32;

 TCP_NUM_PRIM_NEEDED_COUNT3_HI=bit32;

 TCP_NUM_PRIM_NEEDED_COUNT3_LO=bit32;

 TCP_PFP_METADATA_BASE_ADDR_HI=bitpacked record
  ADDR_HI  :bit16;
  RESERVED0:bit16;
 end;

 TCRTC_DTMTEST_STATUS_POSITION=bitpacked record
  CRTC_DTMTEST_VERT_COUNT:bit14;
  RESERVED0              :bit2;
  CRTC_DTMTEST_HORZ_COUNT:bit14;
  RESERVED1              :bit2;
 end;

 TCRTC_EXT_TIMING_SYNC_CONTROL=bitpacked record
  CRTC_EXT_TIMING_SYNC_ENABLE                 :bit2;
  RESERVED0                                   :bit1;
  CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE     :bit1;
  CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE:bit1;
  CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW:bit2;
  RESERVED1                                   :bit1;
  CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE          :bit1;
  CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE          :bit1;
  RESERVED2                                   :bit2;
  CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY         :bit1;
  CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY         :bit1;
  CRTC_EXT_TIMING_SYNC_INTERLACE_MODE         :bit1;
  RESERVED3                                   :bit9;
  CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE      :bit3;
  RESERVED4                                   :bit1;
  CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE       :bit3;
  RESERVED5                                   :bit1;
 end;

 TCRTC_TEST_PATTERN_PARAMETERS=bitpacked record
  CRTC_TEST_PATTERN_INC0        :bit4;
  CRTC_TEST_PATTERN_INC1        :bit4;
  CRTC_TEST_PATTERN_VRES        :bit4;
  CRTC_TEST_PATTERN_HRES        :bit4;
  CRTC_TEST_PATTERN_RAMP0_OFFSET:bit16;
 end;

 TDC_ABM1_OVERSCAN_PIXEL_VALUE=bitpacked record
  ABM1_OVERSCAN_R_PIXEL_VALUE:bit10;
  ABM1_OVERSCAN_G_PIXEL_VALUE:bit10;
  ABM1_OVERSCAN_B_PIXEL_VALUE:bit10;
  RESERVED0                  :bit2;
 end;

 TDMCU_INTERRUPT_TO_UC_EN_MASK=bitpacked record
  ABM1_HG_READY_INT_TO_UC_EN            :bit1;
  ABM1_LS_READY_INT_TO_UC_EN            :bit1;
  ABM1_BL_UPDATE_INT_TO_UC_EN           :bit1;
  MCP_INT_TO_UC_EN                      :bit1;
  DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN    :bit1;
  DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN  :bit1;
  STATIC_SCREEN1_INT_TO_UC_EN           :bit1;
  STATIC_SCREEN2_INT_TO_UC_EN           :bit1;
  EXTERNAL_SW_INT_TO_UC_EN              :bit1;
  STATIC_SCREEN3_INT_TO_UC_EN           :bit1;
  STATIC_SCREEN4_INT_TO_UC_EN           :bit1;
  STATIC_SCREEN5_INT_TO_UC_EN           :bit1;
  DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN  :bit1;
  DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN  :bit1;
  DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN  :bit1;
  DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN  :bit1;
  DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN  :bit1;
  DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN  :bit1;
  DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN:bit1;
  DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN:bit1;
  DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN:bit1;
  DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN:bit1;
  DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN:bit1;
  DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN:bit1;
  VBLANK1_INT_TO_UC_EN                  :bit1;
  VBLANK2_INT_TO_UC_EN                  :bit1;
  VBLANK3_INT_TO_UC_EN                  :bit1;
  VBLANK4_INT_TO_UC_EN                  :bit1;
  VBLANK5_INT_TO_UC_EN                  :bit1;
  VBLANK6_INT_TO_UC_EN                  :bit1;
  STATIC_SCREEN6_INT_TO_UC_EN           :bit1;
  RESERVED0                             :bit1;
 end;

 TDP_DPHY_FAST_TRAINING_STATUS=bitpacked record
  DPHY_FAST_TRAINING_STATE            :bit3;
  RESERVED0                           :bit1;
  DPHY_FAST_TRAINING_COMPLETE_OCCURRED:bit1;
  RESERVED1                           :bit3;
  DPHY_FAST_TRAINING_COMPLETE_MASK    :bit1;
  RESERVED2                           :bit3;
  DPHY_FAST_TRAINING_COMPLETE_ACK     :bit1;
  RESERVED3                           :bit19;
 end;

 TDP_DPHY_TRAINING_PATTERN_SEL=bitpacked record
  DPHY_TRAINING_PATTERN_SEL:bit2;
  RESERVED0                :bit30;
 end;

 TGAMMA_CORR_LUT_WRITE_EN_MASK=bitpacked record
  GAMMA_CORR_LUT_WRITE_EN_MASK:bit3;
  RESERVED0                   :bit29;
 end;

 TGARLIC_COHE_GARLIC_FLUSH_REQ=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_SAM_SAB_RBI_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_SAM_SAB_RBO_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGRPH_PRIMARY_SURFACE_ADDRESS=bitpacked record
  GRPH_PRIMARY_DFQ_ENABLE     :bit1;
  RESERVED0                   :bit7;
  GRPH_PRIMARY_SURFACE_ADDRESS:bit24;
 end;

 THDMI_GENERIC_PACKET_CONTROL0=bitpacked record
  HDMI_GENERIC0_SEND:bit1;
  HDMI_GENERIC0_CONT:bit1;
  RESERVED0         :bit2;
  HDMI_GENERIC1_SEND:bit1;
  HDMI_GENERIC1_CONT:bit1;
  RESERVED1         :bit10;
  HDMI_GENERIC0_LINE:bit6;
  RESERVED2         :bit2;
  HDMI_GENERIC1_LINE:bit6;
  RESERVED3         :bit2;
 end;

 THDMI_GENERIC_PACKET_CONTROL1=bitpacked record
  HDMI_GENERIC2_SEND:bit1;
  HDMI_GENERIC2_CONT:bit1;
  RESERVED0         :bit2;
  HDMI_GENERIC3_SEND:bit1;
  HDMI_GENERIC3_CONT:bit1;
  RESERVED1         :bit10;
  HDMI_GENERIC2_LINE:bit6;
  RESERVED2         :bit2;
  HDMI_GENERIC3_LINE:bit6;
  RESERVED3         :bit2;
 end;

 THDP_MEM_COHERENCY_FLUSH_CNTL=bitpacked record
  HDP_MEM_FLUSH_ADDR:bit1;
  RESERVED0         :bit31;
 end;

 THDP_REG_COHERENCY_FLUSH_CNTL=bitpacked record
  HDP_REG_FLUSH_ADDR:bit1;
  RESERVED0         :bit31;
 end;

 TIH_DSM_MATCH_VALUE_BIT_63_32=bit32;

 TIH_DSM_MATCH_VALUE_BIT_95_64=bit32;

 TIH_RESET_INCOMPLETE_INT_CNTL=bitpacked record
  CG            :bit1;
  DC            :bit1;
  RESERVED0     :bit1;
  SAMMSP        :bit1;
  RLC           :bit1;
  ROM           :bit1;
  SRBM          :bit1;
  VMC           :bit1;
  UVD           :bit1;
  BIF           :bit1;
  SDMA0         :bit1;
  SDMA1         :bit1;
  ISP           :bit1;
  VCE0          :bit1;
  VCE1          :bit1;
  ATC           :bit1;
  XDMA          :bit1;
  ACP           :bit1;
  SH            :bit1;
  SH1           :bit1;
  SH2           :bit1;
  SH3           :bit1;
  RESET_ENABLE  :bit1;
  RESERVED1     :bit1;
  INCOMPLETE_CNT:bit4;
  RESERVED2     :bit4;
 end;

 TLB_NO_OUTSTANDING_REQ_STATUS=bitpacked record
  LB_NO_OUTSTANDING_REQ_STAT:bit1;
  RESERVED0                 :bit31;
 end;

 TMC_ARB_PERFCOUNTER_RSLT_CNTL=bitpacked record
  PERF_COUNTER_SELECT :bit4;
  RESERVED0           :bit4;
  START_TRIGGER       :bit8;
  STOP_TRIGGER        :bit8;
  ENABLE_ANY          :bit1;
  CLEAR_ALL           :bit1;
  STOP_ALL_ON_SATURATE:bit1;
  RESERVED1           :bit5;
 end;

 TMC_HUB_PERFCOUNTER_RSLT_CNTL=bitpacked record
  PERF_COUNTER_SELECT :bit4;
  RESERVED0           :bit4;
  START_TRIGGER       :bit8;
  STOP_TRIGGER        :bit8;
  ENABLE_ANY          :bit1;
  CLEAR_ALL           :bit1;
  STOP_ALL_ON_SATURATE:bit1;
  RESERVED1           :bit5;
 end;

 TMC_RPB_PERFCOUNTER_RSLT_CNTL=bitpacked record
  PERF_COUNTER_SELECT :bit4;
  RESERVED0           :bit4;
  START_TRIGGER       :bit8;
  STOP_TRIGGER        :bit8;
  ENABLE_ANY          :bit1;
  CLEAR_ALL           :bit1;
  STOP_ALL_ON_SATURATE:bit1;
  RESERVED1           :bit5;
 end;

 TMC_VM_MB_L1_TLS0_START_ADDR0=bitpacked record
  START_ADDR:bit28;
  RESERVED0 :bit4;
 end;

 TMC_VM_MB_L1_TLS0_START_ADDR1=bitpacked record
  START_ADDR:bit28;
  RESERVED0 :bit4;
 end;

 TMC_VM_MB_L1_TLS0_START_ADDR2=bitpacked record
  START_ADDR:bit28;
  RESERVED0 :bit4;
 end;

 TMC_VM_MB_L1_TLS0_START_ADDR3=bitpacked record
  START_ADDR:bit28;
  RESERVED0 :bit4;
 end;

 TMC_VM_MB_L1_TLS0_START_ADDR4=bitpacked record
  START_ADDR:bit28;
  RESERVED0 :bit4;
 end;

 TMC_VM_MB_L1_TLS0_START_ADDR5=bitpacked record
  START_ADDR:bit28;
  RESERVED0 :bit4;
 end;

 TMC_VM_MB_L1_TLS0_START_ADDR6=bitpacked record
  START_ADDR:bit28;
  RESERVED0 :bit4;
 end;

 TMC_VM_MB_L1_TLS0_START_ADDR7=bitpacked record
  START_ADDR:bit28;
  RESERVED0 :bit4;
 end;

 TMC_VM_MB_L1_TLS0_START_ADDR8=bitpacked record
  START_ADDR:bit28;
  RESERVED0 :bit4;
 end;

 TPA_SC_HP3D_TRAP_SCREEN_COUNT=bitpacked record
  COUNT    :bit16;
  RESERVED0:bit16;
 end;

 TPA_SC_HP3D_TRAP_SCREEN_HV_EN=bitpacked record
  ENABLE_HV_PRE_SHADER       :bit1;
  FORCE_PRE_SHADER_ALL_PIXELS:bit1;
  RESERVED0                  :bit30;
 end;

 TPA_SC_TRAP_SCREEN_OCCURRENCE=bitpacked record
  COUNT    :bit16;
  RESERVED0:bit16;
 end;

 TPA_SU_HARDWARE_SCREEN_OFFSET=bitpacked record
  HW_SCREEN_OFFSET_X:bit9;
  RESERVED0         :bit7;
  HW_SCREEN_OFFSET_Y:bit9;
  RESERVED1         :bit7;
 end;

 TPA_SU_POLY_OFFSET_BACK_SCALE=bit32;

 TPCIE_MC_BLOCK_UNTRANSLATED_0=bit32;

 TPCIE_MC_BLOCK_UNTRANSLATED_1=bit32;

 TPCIE_OUTSTAND_PAGE_REQ_ALLOC=bit32;

 TPCIE_PERF_COUNT0_SLV_S_C_CLK=bit32;

 TPCIE_PERF_COUNT1_SLV_S_C_CLK=bit32;

 TPCIE_PWR_BUDGET_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_RX_CREDITS_ALLOCATED_NP=bitpacked record
  RX_CREDITS_ALLOCATED_NPD:bit12;
  RESERVED0               :bit4;
  RX_CREDITS_ALLOCATED_NPH:bit8;
  RESERVED1               :bit8;
 end;

 TRLC_LB_ALWAYS_ACTIVE_CU_MASK=bit32;

 TRLC_SERDES_NONCU_MASTER_BUSY=bitpacked record
  SE_MASTER_BUSY    :bit16;
  GC_MASTER_BUSY    :bit1;
  GC_GFX_MASTER_BUSY:bit1;
  TC0_MASTER_BUSY   :bit1;
  TC1_MASTER_BUSY   :bit1;
  SPARE0_MASTER_BUSY:bit1;
  SPARE1_MASTER_BUSY:bit1;
  SPARE2_MASTER_BUSY:bit1;
  SPARE3_MASTER_BUSY:bit1;
  RESERVED          :bit8;
 end;

 TRLC_SERDES_WR_CU_MASTER_MASK=bit32;

 TRLC_SPM_PERFMON_RING_BASE_HI=bitpacked record
  RING_BASE_HI:bit16;
  RESERVED0   :bit16;
 end;

 TRLC_SPM_PERFMON_RING_BASE_LO=bit32;

 TRLC_SPM_PERFMON_SEGMENT_SIZE=bitpacked record
  PERFMON_SEGMENT_SIZE:bit8;
  RESERVED0           :bit3;
  GLOBAL_NUM_LINE     :bit5;
  SE0_NUM_LINE        :bit5;
  SE1_NUM_LINE        :bit5;
  SE2_NUM_LINE        :bit5;
  RESERVED1           :bit1;
 end;

 TSCLV_EXT_OVERSCAN_LEFT_RIGHT=bitpacked record
  EXT_OVERSCAN_RIGHT:bit13;
  RESERVED0         :bit3;
  EXT_OVERSCAN_LEFT :bit13;
  RESERVED1         :bit3;
 end;

 TSCLV_EXT_OVERSCAN_TOP_BOTTOM=bitpacked record
  EXT_OVERSCAN_BOTTOM:bit13;
  RESERVED0          :bit3;
  EXT_OVERSCAN_TOP   :bit13;
  RESERVED1          :bit3;
 end;

 TSCLV_HORZ_FILTER_SCALE_RATIO=bitpacked record
  SCL_H_SCALE_RATIO:bit26;
  RESERVED0        :bit6;
 end;

 TSCLV_VERT_FILTER_SCALE_RATIO=bitpacked record
  SCL_V_SCALE_RATIO:bit26;
  RESERVED0        :bit6;
 end;

 TSCL_COEF_RAM_CONFLICT_STATUS=bitpacked record
  SCL_HOST_CONFLICT_FLAG      :bit1;
  RESERVED0                   :bit7;
  SCL_HOST_CONFLICT_ACK       :bit1;
  RESERVED1                   :bit3;
  SCL_HOST_CONFLICT_MASK      :bit1;
  RESERVED2                   :bit3;
  SCL_HOST_CONFLICT_INT_STATUS:bit1;
  RESERVED3                   :bit15;
 end;

 TSCL_MANUAL_REPLICATE_CONTROL=bitpacked record
  SCL_V_MANUAL_REPLICATE_FACTOR:bit4;
  RESERVED0                    :bit4;
  SCL_H_MANUAL_REPLICATE_FACTOR:bit4;
  RESERVED1                    :bit20;
 end;

 TSDMA0_RLC0_RB_WPTR_POLL_CNTL=bitpacked record
  ENABLE         :bit1;
  SWAP_ENABLE    :bit1;
  F32_POLL_ENABLE:bit1;
  RESERVED0      :bit1;
  FREQUENCY      :bit12;
  IDLE_POLL_COUNT:bit16;
 end;

 TSDMA0_RLC1_RB_WPTR_POLL_CNTL=bitpacked record
  ENABLE         :bit1;
  SWAP_ENABLE    :bit1;
  F32_POLL_ENABLE:bit1;
  RESERVED0      :bit1;
  FREQUENCY      :bit12;
  IDLE_POLL_COUNT:bit16;
 end;

 TSDMA1_RLC0_RB_WPTR_POLL_CNTL=bitpacked record
  ENABLE         :bit1;
  SWAP_ENABLE    :bit1;
  F32_POLL_ENABLE:bit1;
  RESERVED0      :bit1;
  FREQUENCY      :bit12;
  IDLE_POLL_COUNT:bit16;
 end;

 TSDMA1_RLC1_RB_WPTR_POLL_CNTL=bitpacked record
  ENABLE         :bit1;
  SWAP_ENABLE    :bit1;
  F32_POLL_ENABLE:bit1;
  RESERVED0      :bit1;
  FREQUENCY      :bit12;
  IDLE_POLL_COUNT:bit16;
 end;

 TSPI_PG_ENABLE_STATIC_CU_MASK=bitpacked record
  CU_MASK  :bit16;
  RESERVED0:bit16;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_0=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_1=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_2=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_3=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_4=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_5=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_6=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_7=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_8=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_9=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TUNIPHY_MACRO_CNTL_RESERVED10=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED11=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED12=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED13=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED14=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED15=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED16=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED17=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED18=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED19=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED20=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED21=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED22=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED23=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED24=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED25=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED26=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED27=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED28=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED29=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED30=bit32;

 TUNIPHY_MACRO_CNTL_RESERVED31=bit32;

 TUVD_LMI_RBC_IB_64BIT_BAR_LOW=bit32;

 TUVD_LMI_RBC_RB_64BIT_BAR_LOW=bit32;

 TVCE_LMI_VCPU_CACHE_40BIT_BAR=bit32;

 TVGA_MEMORY_BASE_ADDRESS_HIGH=bitpacked record
  VGA_MEMORY_BASE_ADDRESS_HIGH:bit8;
  RESERVED0                   :bit24;
 end;

 TVGT_MULTI_PRIM_IB_RESET_INDX=bit32;

 TXDMA_MSTR_REMOTE_GPU_ADDRESS=bit32;

 TXDMA_SLV_READ_LATENCY_MINMAX=bitpacked record
  XDMA_SLV_READ_LATENCY_MIN:bit16;
  XDMA_SLV_READ_LATENCY_MAX:bit16;
 end;

 TAZALIA_F0_AUDIO_ENABLE_STATUS=bitpacked record
  AUDIO_ENABLE_STATUS:bit1;
  RESERVED0          :bit31;
 end;

 TAZALIA_F0_CODEC_ENDPOINT_DATA=bit32;

 TBIF_GPUIOV_RESET_NOTIFICATION=bitpacked record
  RESET_NOTIFICATION:bit17;
  RESERVED0         :bit15;
 end;

 TBL1_PWM_BL_UPDATE_SAMPLE_RATE=bitpacked record
  BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN                      :bit1;
  BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER           :bit1;
  RESERVED0                                                   :bit6;
  BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT                   :bit8;
  BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET:bit8;
  RESERVED1                                                   :bit7;
  ABM1_HGLS_REG_LOCK                                          :bit1;
 end;

 TCP_HQD_PQ_RPTR_REPORT_ADDR_HI=bitpacked record
  RPTR_REPORT_ADDR_HI:bit16;
  RESERVED0          :bit16;
 end;

 TCP_NUM_PRIM_WRITTEN_COUNT0_HI=bit32;

 TCP_NUM_PRIM_WRITTEN_COUNT0_LO=bit32;

 TCP_NUM_PRIM_WRITTEN_COUNT1_HI=bit32;

 TCP_NUM_PRIM_WRITTEN_COUNT1_LO=bit32;

 TCP_NUM_PRIM_WRITTEN_COUNT2_HI=bit32;

 TCP_NUM_PRIM_WRITTEN_COUNT2_LO=bit32;

 TCP_NUM_PRIM_WRITTEN_COUNT3_HI=bit32;

 TCP_NUM_PRIM_WRITTEN_COUNT3_LO=bit32;

 TCRTC_FIELD_INDICATION_CONTROL=bitpacked record
  CRTC_FIELD_INDICATION_OUTPUT_POLARITY:bit1;
  CRTC_FIELD_ALIGNMENT                 :bit1;
  RESERVED0                            :bit30;
 end;

 TDCP_LB_DATA_GAP_BETWEEN_CHUNK=bitpacked record
  DCP_LB_GAP_BETWEEN_CHUNK_20BPP:bit4;
  DCP_LB_GAP_BETWEEN_CHUNK_30BPP:bit5;
  RESERVED0                     :bit23;
 end;

 TDCRX_PHY_MACRO_CNTL_RESERVED0=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED1=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED2=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED3=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED4=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED5=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED6=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED7=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED8=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED9=bit32;

 TDMCU_SS_INTERRUPT_CNTL_STATUS=bitpacked record
  RESERVED0                  :bit13;
  STATIC_SCREEN1_INT_STATUS  :bit1;
  STATIC_SCREEN1_INT_OCCURRED:bit1;
  STATIC_SCREEN2_INT_STATUS  :bit1;
  STATIC_SCREEN2_INT_OCCURRED:bit1;
  STATIC_SCREEN3_INT_STATUS  :bit1;
  STATIC_SCREEN3_INT_OCCURRED:bit1;
  STATIC_SCREEN4_INT_STATUS  :bit1;
  STATIC_SCREEN4_INT_OCCURRED:bit1;
  STATIC_SCREEN5_INT_STATUS  :bit1;
  STATIC_SCREEN5_INT_OCCURRED:bit1;
  STATIC_SCREEN6_INT_STATUS  :bit1;
  STATIC_SCREEN6_INT_OCCURRED:bit1;
  RESERVED1                  :bit7;
 end;

 TDPG_PIPE_ARBITRATION_CONTROL1=bitpacked record
  PIXEL_DURATION:bit16;
  BASE_WEIGHT   :bit16;
 end;

 TDPG_PIPE_ARBITRATION_CONTROL2=bitpacked record
  TIME_WEIGHT   :bit16;
  URGENCY_WEIGHT:bit16;
 end;

 TFMT_CRC_SIG_BLUE_CONTROL_MASK=bitpacked record
  FMT_CRC_SIG_BLUE_MASK   :bit16;
  FMT_CRC_SIG_CONTROL_MASK:bit16;
 end;

 TGAMMA_CORR_CNTLA_REGION_10_11=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET  :bit8;
  RESERVED0                                 :bit3;
  GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS:bit3;
  RESERVED1                                 :bit1;
  GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET  :bit8;
  RESERVED2                                 :bit4;
  GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS:bit3;
  RESERVED3                                 :bit2;
 end;

 TGAMMA_CORR_CNTLA_REGION_12_13=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET  :bit8;
  RESERVED0                                 :bit3;
  GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS:bit3;
  RESERVED1                                 :bit1;
  GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET  :bit8;
  RESERVED2                                 :bit4;
  GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS:bit3;
  RESERVED3                                 :bit2;
 end;

 TGAMMA_CORR_CNTLA_REGION_14_15=bitpacked record
  GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET  :bit8;
  RESERVED0                                 :bit3;
  GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS:bit3;
  RESERVED1                                 :bit1;
  GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET  :bit8;
  RESERVED2                                 :bit4;
  GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS:bit3;
  RESERVED3                                 :bit2;
 end;

 TGAMMA_CORR_CNTLB_REGION_10_11=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET  :bit8;
  RESERVED0                                 :bit3;
  GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS:bit3;
  RESERVED1                                 :bit1;
  GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET  :bit8;
  RESERVED2                                 :bit4;
  GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS:bit3;
  RESERVED3                                 :bit2;
 end;

 TGAMMA_CORR_CNTLB_REGION_12_13=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET  :bit8;
  RESERVED0                                 :bit3;
  GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS:bit3;
  RESERVED1                                 :bit1;
  GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET  :bit8;
  RESERVED2                                 :bit4;
  GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS:bit3;
  RESERVED3                                 :bit2;
 end;

 TGAMMA_CORR_CNTLB_REGION_14_15=bitpacked record
  GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET  :bit8;
  RESERVED0                                 :bit3;
  GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS:bit3;
  RESERVED1                                 :bit1;
  GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET  :bit8;
  RESERVED2                                 :bit4;
  GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS:bit3;
  RESERVED3                                 :bit2;
 end;

 TGARLIC_COHE_CP_DMA_ME_COMMAND=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_SDMA0_GFX_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_SDMA1_GFX_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_SDMA2_GFX_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_SDMA3_GFX_RB_WPTR=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGENERIC_I2C_INTERRUPT_CONTROL=bitpacked record
  GENERIC_I2C_DONE_INT :bit1;
  GENERIC_I2C_DONE_ACK :bit1;
  GENERIC_I2C_DONE_MASK:bit1;
  RESERVED0            :bit29;
 end;

 TGRPH_COMPRESS_SURFACE_ADDRESS=bitpacked record
  RESERVED0                    :bit8;
  GRPH_COMPRESS_SURFACE_ADDRESS:bit24;
 end;

 TLBV_NO_OUTSTANDING_REQ_STATUS=bitpacked record
  LB_NO_OUTSTANDING_REQ_STAT:bit1;
  RESERVED0                 :bit31;
 end;

 TLBV_SNAPSHOT_V_COUNTER_CHROMA=bitpacked record
  SNAPSHOT_V_COUNTER_CHROMA:bit15;
  RESERVED0                :bit17;
 end;

 TMC_CITF_PERFCOUNTER_RSLT_CNTL=bitpacked record
  PERF_COUNTER_SELECT :bit4;
  RESERVED0           :bit4;
  START_TRIGGER       :bit8;
  STOP_TRIGGER        :bit8;
  ENABLE_ANY          :bit1;
  CLEAR_ALL           :bit1;
  STOP_ALL_ON_SATURATE:bit1;
  RESERVED1           :bit5;
 end;

 TMC_GRUB_PERFCOUNTER_RSLT_CNTL=bitpacked record
  PERF_COUNTER_SELECT :bit4;
  RESERVED0           :bit4;
  START_TRIGGER       :bit8;
  STOP_TRIGGER        :bit8;
  ENABLE_ANY          :bit1;
  CLEAR_ALL           :bit1;
  STOP_ALL_ON_SATURATE:bit1;
  RESERVED1           :bit5;
 end;

 TMC_VM_MB_L2ARBITER_L2_CREDITS=bitpacked record
  L2_IF_CREDITS:bit6;
  RESERVED0    :bit26;
 end;

 TMC_VM_MD_L2ARBITER_L2_CREDITS=bitpacked record
  L2_IF_CREDITS:bit6;
  RESERVED0    :bit26;
 end;

 TOVL_SECONDARY_SURFACE_ADDRESS=bitpacked record
  OVL_SECONDARY_DFQ_ENABLE     :bit1;
  RESERVED0                    :bit7;
  OVL_SECONDARY_SURFACE_ADDRESS:bit24;
 end;

 TPA_SC_P3D_TRAP_SCREEN_HV_LOCK=bitpacked record
  DISABLE_NON_PRIV_WRITES:bit1;
  RESERVED0              :bit31;
 end;

 TPA_SU_POLY_OFFSET_BACK_OFFSET=bit32;

 TPA_SU_POLY_OFFSET_DB_FMT_CNTL=bitpacked record
  POLY_OFFSET_NEG_NUM_DB_BITS:bit8;
  POLY_OFFSET_DB_IS_FLOAT_FMT:bit1;
  RESERVED0                  :bit23;
 end;

 TPA_SU_POLY_OFFSET_FRONT_SCALE=bit32;

 TPB0_RX_GLB_SCI_STAT_OVRD_REG0=bitpacked record
  IGNR_RXPWR_CBI_UPDT_L0T3          :bit1;
  IGNR_RXPWR_CBI_UPDT_L4T7          :bit1;
  IGNR_RXPWR_CBI_UPDT_L8T11         :bit1;
  IGNR_RXPWR_CBI_UPDT_L12T15        :bit1;
  IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3  :bit1;
  IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7  :bit1;
  IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11 :bit1;
  IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15:bit1;
  IGNR_REQUESTTRK_CBI_UPDT_L0T3     :bit1;
  IGNR_REQUESTTRK_CBI_UPDT_L4T7     :bit1;
  IGNR_REQUESTTRK_CBI_UPDT_L8T11    :bit1;
  IGNR_REQUESTTRK_CBI_UPDT_L12T15   :bit1;
  IGNR_ENABLEFOM_CBI_UPDT_L0T3      :bit1;
  IGNR_ENABLEFOM_CBI_UPDT_L4T7      :bit1;
  IGNR_ENABLEFOM_CBI_UPDT_L8T11     :bit1;
  IGNR_ENABLEFOM_CBI_UPDT_L12T15    :bit1;
  IGNR_REQUESTFOM_CBI_UPDT_L0T3     :bit1;
  IGNR_REQUESTFOM_CBI_UPDT_L4T7     :bit1;
  IGNR_REQUESTFOM_CBI_UPDT_L8T11    :bit1;
  IGNR_REQUESTFOM_CBI_UPDT_L12T15   :bit1;
  IGNR_RESPONSEMODE_CBI_UPDT_L0T3   :bit1;
  IGNR_RESPONSEMODE_CBI_UPDT_L4T7   :bit1;
  IGNR_RESPONSEMODE_CBI_UPDT_L8T11  :bit1;
  IGNR_RESPONSEMODE_CBI_UPDT_L12T15 :bit1;
  RESERVED0                         :bit8;
 end;

 TPB0_TX_GLB_SCI_STAT_OVRD_REG0=bitpacked record
  IGNR_TXPWR_CBI_UPDT_L0T3          :bit1;
  IGNR_TXPWR_CBI_UPDT_L4T7          :bit1;
  IGNR_TXPWR_CBI_UPDT_L8T11         :bit1;
  IGNR_TXPWR_CBI_UPDT_L12T15        :bit1;
  RESERVED0                         :bit4;
  IGNR_COEFFICIENTID_CBI_UPDT_L0T3  :bit1;
  IGNR_COEFFICIENTID_CBI_UPDT_L4T7  :bit1;
  IGNR_COEFFICIENTID_CBI_UPDT_L8T11 :bit1;
  IGNR_COEFFICIENTID_CBI_UPDT_L12T15:bit1;
  IGNR_COEFFICIENT_CBI_UPDT_L0T3    :bit1;
  IGNR_COEFFICIENT_CBI_UPDT_L4T7    :bit1;
  IGNR_COEFFICIENT_CBI_UPDT_L8T11   :bit1;
  IGNR_COEFFICIENT_CBI_UPDT_L12T15  :bit1;
  RESERVED1                         :bit16;
 end;

 TPB1_RX_GLB_SCI_STAT_OVRD_REG0=bitpacked record
  IGNR_RXPWR_CBI_UPDT_L0T3          :bit1;
  IGNR_RXPWR_CBI_UPDT_L4T7          :bit1;
  IGNR_RXPWR_CBI_UPDT_L8T11         :bit1;
  IGNR_RXPWR_CBI_UPDT_L12T15        :bit1;
  IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3  :bit1;
  IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7  :bit1;
  IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11 :bit1;
  IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15:bit1;
  IGNR_REQUESTTRK_CBI_UPDT_L0T3     :bit1;
  IGNR_REQUESTTRK_CBI_UPDT_L4T7     :bit1;
  IGNR_REQUESTTRK_CBI_UPDT_L8T11    :bit1;
  IGNR_REQUESTTRK_CBI_UPDT_L12T15   :bit1;
  IGNR_ENABLEFOM_CBI_UPDT_L0T3      :bit1;
  IGNR_ENABLEFOM_CBI_UPDT_L4T7      :bit1;
  IGNR_ENABLEFOM_CBI_UPDT_L8T11     :bit1;
  IGNR_ENABLEFOM_CBI_UPDT_L12T15    :bit1;
  IGNR_REQUESTFOM_CBI_UPDT_L0T3     :bit1;
  IGNR_REQUESTFOM_CBI_UPDT_L4T7     :bit1;
  IGNR_REQUESTFOM_CBI_UPDT_L8T11    :bit1;
  IGNR_REQUESTFOM_CBI_UPDT_L12T15   :bit1;
  IGNR_RESPONSEMODE_CBI_UPDT_L0T3   :bit1;
  IGNR_RESPONSEMODE_CBI_UPDT_L4T7   :bit1;
  IGNR_RESPONSEMODE_CBI_UPDT_L8T11  :bit1;
  IGNR_RESPONSEMODE_CBI_UPDT_L12T15 :bit1;
  RESERVED0                         :bit8;
 end;

 TPB1_TX_GLB_SCI_STAT_OVRD_REG0=bitpacked record
  IGNR_TXPWR_CBI_UPDT_L0T3          :bit1;
  IGNR_TXPWR_CBI_UPDT_L4T7          :bit1;
  IGNR_TXPWR_CBI_UPDT_L8T11         :bit1;
  IGNR_TXPWR_CBI_UPDT_L12T15        :bit1;
  RESERVED0                         :bit4;
  IGNR_COEFFICIENTID_CBI_UPDT_L0T3  :bit1;
  IGNR_COEFFICIENTID_CBI_UPDT_L4T7  :bit1;
  IGNR_COEFFICIENTID_CBI_UPDT_L8T11 :bit1;
  IGNR_COEFFICIENTID_CBI_UPDT_L12T15:bit1;
  IGNR_COEFFICIENT_CBI_UPDT_L0T3    :bit1;
  IGNR_COEFFICIENT_CBI_UPDT_L4T7    :bit1;
  IGNR_COEFFICIENT_CBI_UPDT_L8T11   :bit1;
  IGNR_COEFFICIENT_CBI_UPDT_L12T15  :bit1;
  RESERVED1                         :bit16;
 end;

 TPCIE_ADV_ERR_RPT_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_DPA_SUBSTATE_PWR_ALLOC_0=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_DPA_SUBSTATE_PWR_ALLOC_1=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_DPA_SUBSTATE_PWR_ALLOC_2=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_DPA_SUBSTATE_PWR_ALLOC_3=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_DPA_SUBSTATE_PWR_ALLOC_4=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_DPA_SUBSTATE_PWR_ALLOC_5=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_DPA_SUBSTATE_PWR_ALLOC_6=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_DPA_SUBSTATE_PWR_ALLOC_7=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_F0_DPA_LATENCY_INDICATOR=bitpacked record
  TRANS_LAT_INDICATOR_BITS:bit8;
  RESERVED0               :bit24;
 end;

 TPCIE_LANE_0_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_1_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_2_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_3_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_4_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_5_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_6_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_7_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_8_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_9_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_PERF_COUNT0_SLV_NS_C_CLK=bit32;

 TPCIE_PERF_COUNT1_SLV_NS_C_CLK=bit32;

 TPCIE_RX_CREDITS_ALLOCATED_CPL=bitpacked record
  RX_CREDITS_ALLOCATED_CPLD:bit12;
  RESERVED0                :bit4;
  RX_CREDITS_ALLOCATED_CPLH:bit8;
  RESERVED1                :bit8;
 end;

 TPCIE_TX_CREDITS_FCU_THRESHOLD=bitpacked record
  TX_FCU_THRESHOLD_P_VC0  :bit3;
  RESERVED0               :bit1;
  TX_FCU_THRESHOLD_NP_VC0 :bit3;
  RESERVED1               :bit1;
  TX_FCU_THRESHOLD_CPL_VC0:bit3;
  RESERVED2               :bit5;
  TX_FCU_THRESHOLD_P_VC1  :bit3;
  RESERVED3               :bit1;
  TX_FCU_THRESHOLD_NP_VC1 :bit3;
  RESERVED4               :bit1;
  TX_FCU_THRESHOLD_CPL_VC1:bit3;
  RESERVED5               :bit5;
 end;

 TRLC_GPU_IOV_SDMA0_BUSY_STATUS=bit32;

 TRLC_GPU_IOV_SDMA1_BUSY_STATUS=bit32;

 TSCLV_MANUAL_REPLICATE_CONTROL=bitpacked record
  SCL_V_MANUAL_REPLICATE_FACTOR:bit4;
  RESERVED0                    :bit4;
  SCL_H_MANUAL_REPLICATE_FACTOR:bit4;
  RESERVED1                    :bit20;
 end;

 TSCLV_VIEWPORT_START_SECONDARY=bitpacked record
  VIEWPORT_Y_START_SECONDARY:bit14;
  RESERVED0                 :bit2;
  VIEWPORT_X_START_SECONDARY:bit14;
  RESERVED1                 :bit2;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_10=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_11=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_12=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_13=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_14=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TSPI_RESOURCE_RESERVE_EN_CU_15=bitpacked record
  EN                :bit1;
  TYPE_MASK         :bit15;
  QUEUE_MASK        :bit8;
  RESERVE_SPACE_ONLY:bit1;
  RESERVED0         :bit7;
 end;

 TUNP_LB_DATA_GAP_BETWEEN_CHUNK=bitpacked record
  RESERVED0               :bit4;
  UNP_LB_GAP_BETWEEN_CHUNK:bit5;
  RESERVED1               :bit23;
 end;

 TUVD_LMI_RBC_IB_64BIT_BAR_HIGH=bit32;

 TUVD_LMI_RBC_RB_64BIT_BAR_HIGH=bit32;

 TXDMA_MSTR_LOCAL_SURFACE_PITCH=bitpacked record
  XDMA_MSTR_LOCAL_SURFACE_PITCH:bit14;
  RESERVED0                    :bit18;
 end;

 TXDMA_MSTR_REMOTE_SURFACE_BASE=bit32;

 TAUX_GTC_SYNC_CONTROLLER_STATUS=bitpacked record
  AUX_GTC_SYNC_LOCK_ACQ_COMPLETE            :bit1;
  RESERVED0                                 :bit3;
  AUX_GTC_SYNC_LOCK_LOST                    :bit1;
  RESERVED1                                 :bit3;
  AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED    :bit1;
  AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE       :bit4;
  RESERVED2                                 :bit3;
  AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL       :bit1;
  RESERVED3                                 :bit3;
  AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED        :bit1;
  AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK    :bit1;
  AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED    :bit1;
  AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK:bit1;
  AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED     :bit1;
  AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK :bit1;
  RESERVED4                                 :bit2;
  AUX_GTC_SYNC_CTRL_STATE                   :bit4;
 end;

 TAZALIA_CONTROLLER_CLOCK_GATING=bitpacked record
  ENABLE_CLOCK_GATING:bit1;
  RESERVED0          :bit3;
  CLOCK_ON_STATE     :bit1;
  RESERVED1          :bit27;
 end;

 TAZALIA_F0_CODEC_ENDPOINT_INDEX=bitpacked record
  AZALIA_ENDPOINT_REG_INDEX:bit14;
  RESERVED0                :bit18;
 end;

 TAZALIA_LATENCY_COUNTER_CONTROL=bitpacked record
  AZALIA_LATENCY_COUNTER_RESET:bit1;
  RESERVED0                   :bit31;
 end;

 TAZALIA_UNDERFLOW_FILLER_SAMPLE=bit32;

 TAZALIA_WORSTCASE_LATENCY_COUNT=bit32;

 TBIF_RFE_CLIENT_SOFTRST_TRIGGER=bitpacked record
  CLIENT0_RFE_RFEWDBIF_rst:bit1;
  CLIENT1_RFE_RFEWDBIF_rst:bit1;
  RESERVED0               :bit30;
 end;

 TBIF_RFE_MASTER_SOFTRST_TRIGGER=bitpacked record
  BU_rst            :bit1;
  RWREG_RFEWDBIF_rst:bit1;
  SMBUS_rst         :bit1;
  BX_rst            :bit1;
  RESERVED0         :bit28;
 end;

 TCHUB_ATC_PERFCOUNTER_RSLT_CNTL=bitpacked record
  PERF_COUNTER_SELECT :bit4;
  RESERVED0           :bit4;
  START_TRIGGER       :bit8;
  STOP_TRIGGER        :bit8;
  ENABLE_ANY          :bit1;
  CLEAR_ALL           :bit1;
  STOP_ALL_ON_SATURATE:bit1;
  RESERVED1           :bit5;
 end;

 TCOMPUTE_STATIC_THREAD_MGMT_SE0=bitpacked record
  SH0_CU_EN:bit16;
  SH1_CU_EN:bit16;
 end;

 TCOMPUTE_STATIC_THREAD_MGMT_SE1=bitpacked record
  SH0_CU_EN:bit16;
  SH1_CU_EN:bit16;
 end;

 TCOMPUTE_STATIC_THREAD_MGMT_SE2=bitpacked record
  SH0_CU_EN:bit16;
  SH1_CU_EN:bit16;
 end;

 TCOMPUTE_STATIC_THREAD_MGMT_SE3=bitpacked record
  SH0_CU_EN:bit16;
  SH1_CU_EN:bit16;
 end;

 TDCRX_PHY_MACRO_CNTL_RESERVED10=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED11=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED12=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED13=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED14=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED15=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED16=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED17=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED18=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED19=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED20=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED21=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED22=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED23=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED24=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED25=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED26=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED27=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED28=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED29=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED30=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED31=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED32=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED33=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED34=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED35=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED36=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED37=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED38=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED39=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED40=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED41=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED42=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED43=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED44=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED45=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED46=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED47=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED48=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED49=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED50=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED51=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED52=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED53=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED54=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED55=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED56=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED57=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED58=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED59=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED60=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED61=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED62=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED63=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED64=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED65=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED66=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED67=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED68=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED69=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED70=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED71=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED72=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED73=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED74=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED75=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED76=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED77=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED78=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED79=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED80=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED81=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED82=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED83=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED84=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED85=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED86=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED87=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED88=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED89=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED90=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED91=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED92=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED93=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED94=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED95=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED96=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED97=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED98=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED99=bit32;

 TDC_ABM1_HGLS_REG_READ_PROGRESS=bitpacked record
  ABM1_HG_REG_READ_IN_PROGRESS       :bit1;
  ABM1_LS_REG_READ_IN_PROGRESS       :bit1;
  ABM1_BL_REG_READ_IN_PROGRESS       :bit1;
  RESERVED0                          :bit5;
  ABM1_HG_REG_READ_MISSED_FRAME      :bit1;
  ABM1_LS_REG_READ_MISSED_FRAME      :bit1;
  ABM1_BL_REG_READ_MISSED_FRAME      :bit1;
  RESERVED1                          :bit5;
  ABM1_HG_REG_READ_MISSED_FRAME_CLEAR:bit1;
  RESERVED2                          :bit7;
  ABM1_LS_REG_READ_MISSED_FRAME_CLEAR:bit1;
  RESERVED3                          :bit6;
  ABM1_BL_REG_READ_MISSED_FRAME_CLEAR:bit1;
 end;

 TDC_ABM1_HG_BIN_1_32_SHIFT_FLAG=bit32;

 TDC_ABM1_HG_BIN_1_8_SHIFT_INDEX=bit32;

 TDISP_INTERRUPT_STATUS_CONTINUE=bitpacked record
  SCL_DISP2_MODE_CHANGE_INTERRUPT         :bit1;
  D2BLND_DATA_UNDERFLOW_INTERRUPT         :bit1;
  LB_D2_VLINE_INTERRUPT                   :bit1;
  LB_D2_VBLANK_INTERRUPT                  :bit1;
  CRTC2_SNAPSHOT_INTERRUPT                :bit1;
  CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT   :bit1;
  CRTC2_FORCE_COUNT_NOW_INTERRUPT         :bit1;
  CRTC2_TRIGA_INTERRUPT                   :bit1;
  CRTC2_TRIGB_INTERRUPT                   :bit1;
  CRTC2_VSYNC_NOM_INTERRUPT               :bit1;
  CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1;
  RESERVED0                               :bit1;
  RESERVED1                               :bit1;
  RESERVED2                               :bit1;
  RESERVED3                               :bit1;
  DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1;
  DIGB_DP_VID_STREAM_DISABLE_INTERRUPT    :bit1;
  DC_HPD2_INTERRUPT                       :bit1;
  DC_HPD2_RX_INTERRUPT                    :bit1;
  AUX2_SW_DONE_INTERRUPT                  :bit1;
  AUX2_LS_DONE_INTERRUPT                  :bit1;
  LB_D1_VLINE2_INTERRUPT                  :bit1;
  LB_D2_VLINE2_INTERRUPT                  :bit1;
  LB_D3_VLINE2_INTERRUPT                  :bit1;
  RESERVED4                               :bit1;
  CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT    :bit1;
  CRTC1_EXT_TIMING_SYNC_INTERRUPT         :bit1;
  CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT  :bit1;
  CRTC1_VERTICAL_INTERRUPT0               :bit1;
  CRTC1_VERTICAL_INTERRUPT1               :bit1;
  CRTC1_VERTICAL_INTERRUPT2               :bit1;
  DISP_INTERRUPT_STATUS_CONTINUE2         :bit1;
 end;

 TDMCU_FW_CHECKSUM_SMPL_BYTE_POS=bitpacked record
  DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS:bit2;
  DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS:bit2;
  RESERVED0                        :bit28;
 end;

 TDMCU_INTERRUPT_TO_HOST_EN_MASK=bitpacked record
  ABM1_HG_READY_INT_MASK            :bit1;
  ABM1_LS_READY_INT_MASK            :bit1;
  ABM1_BL_UPDATE_INT_MASK           :bit1;
  RESERVED0                         :bit1;
  DCPG_IHC_DSI_POWER_UP_INT_MASK    :bit1;
  DCPG_IHC_DSI_POWER_DOWN_INT_MASK  :bit1;
  RESERVED1                         :bit3;
  SCP_INT_MASK                      :bit1;
  UC_INTERNAL_INT_MASK              :bit1;
  UC_REG_RD_TIMEOUT_INT_MASK        :bit1;
  DCPG_IHC_DCFE0_POWER_UP_INT_MASK  :bit1;
  DCPG_IHC_DCFE1_POWER_UP_INT_MASK  :bit1;
  DCPG_IHC_DCFE2_POWER_UP_INT_MASK  :bit1;
  DCPG_IHC_DCFE3_POWER_UP_INT_MASK  :bit1;
  DCPG_IHC_DCFE4_POWER_UP_INT_MASK  :bit1;
  DCPG_IHC_DCFE5_POWER_UP_INT_MASK  :bit1;
  DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK:bit1;
  DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK:bit1;
  DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK:bit1;
  DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK:bit1;
  DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK:bit1;
  DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK:bit1;
  RESERVED2                         :bit8;
 end;

 TDMCU_PERFMON_INTERRUPT_STATUS1=bitpacked record
  DCI_PERFMON_COUNTER0_INT_OCCURRED    :bit1;
  DCI_PERFMON_COUNTER1_INT_OCCURRED    :bit1;
  DCI_PERFMON_COUNTER2_INT_OCCURRED    :bit1;
  DCI_PERFMON_COUNTER3_INT_OCCURRED    :bit1;
  DCI_PERFMON_COUNTER4_INT_OCCURRED    :bit1;
  DCI_PERFMON_COUNTER5_INT_OCCURRED    :bit1;
  DCI_PERFMON_COUNTER6_INT_OCCURRED    :bit1;
  DCI_PERFMON_COUNTER7_INT_OCCURRED    :bit1;
  DCO_PERFMON_COUNTER0_INT_OCCURRED    :bit1;
  DCO_PERFMON_COUNTER1_INT_OCCURRED    :bit1;
  DCO_PERFMON_COUNTER2_INT_OCCURRED    :bit1;
  DCO_PERFMON_COUNTER3_INT_OCCURRED    :bit1;
  DCO_PERFMON_COUNTER4_INT_OCCURRED    :bit1;
  DCO_PERFMON_COUNTER5_INT_OCCURRED    :bit1;
  DCO_PERFMON_COUNTER6_INT_OCCURRED    :bit1;
  DCO_PERFMON_COUNTER7_INT_OCCURRED    :bit1;
  DCCG_PERFMON_COUNTER0_INT_OCCURRED   :bit1;
  DCCG_PERFMON_COUNTER1_INT_OCCURRED   :bit1;
  DCCG_PERFMON_COUNTER2_INT_OCCURRED   :bit1;
  DCCG_PERFMON_COUNTER3_INT_OCCURRED   :bit1;
  DCCG_PERFMON_COUNTER4_INT_OCCURRED   :bit1;
  DCCG_PERFMON_COUNTER5_INT_OCCURRED   :bit1;
  DCCG_PERFMON_COUNTER6_INT_OCCURRED   :bit1;
  DCCG_PERFMON_COUNTER7_INT_OCCURRED   :bit1;
  DCI_PERFMON_COUNTER_OFF_INT_OCCURRED :bit1;
  DCO_PERFMON_COUNTER_OFF_INT_OCCURRED :bit1;
  DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1;
  RESERVED0                            :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_STATUS2=bitpacked record
  DCFE0_PERFMON_COUNTER0_INT_OCCURRED   :bit1;
  DCFE0_PERFMON_COUNTER1_INT_OCCURRED   :bit1;
  DCFE0_PERFMON_COUNTER2_INT_OCCURRED   :bit1;
  DCFE0_PERFMON_COUNTER3_INT_OCCURRED   :bit1;
  DCFE0_PERFMON_COUNTER4_INT_OCCURRED   :bit1;
  DCFE0_PERFMON_COUNTER5_INT_OCCURRED   :bit1;
  DCFE0_PERFMON_COUNTER6_INT_OCCURRED   :bit1;
  DCFE0_PERFMON_COUNTER7_INT_OCCURRED   :bit1;
  DCFE1_PERFMON_COUNTER0_INT_OCCURRED   :bit1;
  DCFE1_PERFMON_COUNTER1_INT_OCCURRED   :bit1;
  DCFE1_PERFMON_COUNTER2_INT_OCCURRED   :bit1;
  DCFE1_PERFMON_COUNTER3_INT_OCCURRED   :bit1;
  DCFE1_PERFMON_COUNTER4_INT_OCCURRED   :bit1;
  DCFE1_PERFMON_COUNTER5_INT_OCCURRED   :bit1;
  DCFE1_PERFMON_COUNTER6_INT_OCCURRED   :bit1;
  DCFE1_PERFMON_COUNTER7_INT_OCCURRED   :bit1;
  DCFE2_PERFMON_COUNTER0_INT_OCCURRED   :bit1;
  DCFE2_PERFMON_COUNTER1_INT_OCCURRED   :bit1;
  DCFE2_PERFMON_COUNTER2_INT_OCCURRED   :bit1;
  DCFE2_PERFMON_COUNTER3_INT_OCCURRED   :bit1;
  DCFE2_PERFMON_COUNTER4_INT_OCCURRED   :bit1;
  DCFE2_PERFMON_COUNTER5_INT_OCCURRED   :bit1;
  DCFE2_PERFMON_COUNTER6_INT_OCCURRED   :bit1;
  DCFE2_PERFMON_COUNTER7_INT_OCCURRED   :bit1;
  DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1;
  DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1;
  DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1;
  RESERVED0                             :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_STATUS3=bitpacked record
  DCFE3_PERFMON_COUNTER0_INT_OCCURRED   :bit1;
  DCFE3_PERFMON_COUNTER1_INT_OCCURRED   :bit1;
  DCFE3_PERFMON_COUNTER2_INT_OCCURRED   :bit1;
  DCFE3_PERFMON_COUNTER3_INT_OCCURRED   :bit1;
  DCFE3_PERFMON_COUNTER4_INT_OCCURRED   :bit1;
  DCFE3_PERFMON_COUNTER5_INT_OCCURRED   :bit1;
  DCFE3_PERFMON_COUNTER6_INT_OCCURRED   :bit1;
  DCFE3_PERFMON_COUNTER7_INT_OCCURRED   :bit1;
  DCFE4_PERFMON_COUNTER0_INT_OCCURRED   :bit1;
  DCFE4_PERFMON_COUNTER1_INT_OCCURRED   :bit1;
  DCFE4_PERFMON_COUNTER2_INT_OCCURRED   :bit1;
  DCFE4_PERFMON_COUNTER3_INT_OCCURRED   :bit1;
  DCFE4_PERFMON_COUNTER4_INT_OCCURRED   :bit1;
  DCFE4_PERFMON_COUNTER5_INT_OCCURRED   :bit1;
  DCFE4_PERFMON_COUNTER6_INT_OCCURRED   :bit1;
  DCFE4_PERFMON_COUNTER7_INT_OCCURRED   :bit1;
  DCFE5_PERFMON_COUNTER0_INT_OCCURRED   :bit1;
  DCFE5_PERFMON_COUNTER1_INT_OCCURRED   :bit1;
  DCFE5_PERFMON_COUNTER2_INT_OCCURRED   :bit1;
  DCFE5_PERFMON_COUNTER3_INT_OCCURRED   :bit1;
  DCFE5_PERFMON_COUNTER4_INT_OCCURRED   :bit1;
  DCFE5_PERFMON_COUNTER5_INT_OCCURRED   :bit1;
  DCFE5_PERFMON_COUNTER6_INT_OCCURRED   :bit1;
  DCFE5_PERFMON_COUNTER7_INT_OCCURRED   :bit1;
  DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1;
  DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1;
  DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1;
  RESERVED0                             :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_STATUS4=bitpacked record
  WB_PERFMON_COUNTER0_INT_OCCURRED     :bit1;
  WB_PERFMON_COUNTER1_INT_OCCURRED     :bit1;
  WB_PERFMON_COUNTER2_INT_OCCURRED     :bit1;
  WB_PERFMON_COUNTER3_INT_OCCURRED     :bit1;
  WB_PERFMON_COUNTER4_INT_OCCURRED     :bit1;
  WB_PERFMON_COUNTER5_INT_OCCURRED     :bit1;
  WB_PERFMON_COUNTER6_INT_OCCURRED     :bit1;
  WB_PERFMON_COUNTER7_INT_OCCURRED     :bit1;
  DCRX_PERFMON_COUNTER0_INT_OCCURRED   :bit1;
  DCRX_PERFMON_COUNTER1_INT_OCCURRED   :bit1;
  DCRX_PERFMON_COUNTER2_INT_OCCURRED   :bit1;
  DCRX_PERFMON_COUNTER3_INT_OCCURRED   :bit1;
  DCRX_PERFMON_COUNTER4_INT_OCCURRED   :bit1;
  DCRX_PERFMON_COUNTER5_INT_OCCURRED   :bit1;
  DCRX_PERFMON_COUNTER6_INT_OCCURRED   :bit1;
  DCRX_PERFMON_COUNTER7_INT_OCCURRED   :bit1;
  RESERVED0                            :bit8;
  WB_PERFMON_COUNTER_OFF_INT_OCCURRED  :bit1;
  DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1;
  RESERVED1                            :bit6;
 end;

 TDMCU_PERFMON_INTERRUPT_STATUS5=bitpacked record
  DCFEV_PERFMON_COUNTER0_INT_OCCURRED   :bit1;
  DCFEV_PERFMON_COUNTER1_INT_OCCURRED   :bit1;
  DCFEV_PERFMON_COUNTER2_INT_OCCURRED   :bit1;
  DCFEV_PERFMON_COUNTER3_INT_OCCURRED   :bit1;
  DCFEV_PERFMON_COUNTER4_INT_OCCURRED   :bit1;
  DCFEV_PERFMON_COUNTER5_INT_OCCURRED   :bit1;
  DCFEV_PERFMON_COUNTER6_INT_OCCURRED   :bit1;
  DCFEV_PERFMON_COUNTER7_INT_OCCURRED   :bit1;
  DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1;
  RESERVED0                             :bit23;
 end;

 TGARLIC_COHE_CP_DMA_PFP_COMMAND=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGARLIC_COHE_CP_DMA_PIO_COMMAND=bitpacked record
  RESERVED0:bit2;
  ADDRESS  :bit17;
  RESERVED1:bit13;
 end;

 TGC_USER_SYS_RB_BACKEND_DISABLE=bitpacked record
  RESERVED0      :bit16;
  BACKEND_DISABLE:bit8;
  RESERVED1      :bit8;
 end;

 TGRPH_SECONDARY_SURFACE_ADDRESS=bitpacked record
  GRPH_SECONDARY_DFQ_ENABLE     :bit1;
  RESERVED0                     :bit7;
  GRPH_SECONDARY_SURFACE_ADDRESS:bit24;
 end;

 TMC_FUS_DRAM0_BANK_ADDR_MAPPING=bitpacked record
  DIMM0ADDRMAP   :bit4;
  DIMM1ADDRMAP   :bit4;
  BANKSWIZZLEMODE:bit1;
  BANKSWAP       :bit1;
  RESERVED0      :bit22;
 end;

 TMC_FUS_DRAM1_BANK_ADDR_MAPPING=bitpacked record
  DIMM0ADDRMAP   :bit4;
  DIMM1ADDRMAP   :bit4;
  BANKSWIZZLEMODE:bit1;
  BANKSWAP       :bit1;
  RESERVED0      :bit22;
 end;

 TMC_HUB_MISC_ATOMIC_IDLE_STATUS=bitpacked record
  OUTSTANDING_GFX_ATOMIC   :bit1;
  OUTSTANDING_RLC_ATOMIC   :bit1;
  OUTSTANDING_SDMA0_ATOMIC :bit1;
  OUTSTANDING_SDMA1_ATOMIC :bit1;
  OUTSTANDING_DISP_ATOMIC  :bit1;
  OUTSTANDING_UVD_ATOMIC   :bit1;
  OUTSTANDING_SMU_ATOMIC   :bit1;
  OUTSTANDING_HDP_ATOMIC   :bit1;
  OUTSTANDING_OTH_ATOMIC   :bit1;
  OUTSTANDING_VMC_ATOMIC   :bit1;
  OUTSTANDING_VCE_ATOMIC   :bit1;
  OUTSTANDING_ACP_ATOMIC   :bit1;
  OUTSTANDING_SAMMSP_ATOMIC:bit1;
  OUTSTANDING_XDMA_ATOMIC  :bit1;
  OUTSTANDING_ISP_ATOMIC   :bit1;
  OUTSTANDING_VP8_ATOMIC   :bit1;
  OUTSTANDING_VIN0_READ    :bit1;
  OUTSTANDING_VIN0_WRITE   :bit1;
  OUTSTANDING_VIN0_ATOMIC  :bit1;
  OUTSTANDING_TLS_READ     :bit1;
  OUTSTANDING_TLS_WRITE    :bit1;
  OUTSTANDING_TLS_ATOMIC   :bit1;
  RESERVED0                :bit10;
 end;

 TMC_MCBVM_PERFCOUNTER_RSLT_CNTL=bitpacked record
  PERF_COUNTER_SELECT :bit4;
  RESERVED0           :bit4;
  START_TRIGGER       :bit8;
  STOP_TRIGGER        :bit8;
  ENABLE_ANY          :bit1;
  CLEAR_ALL           :bit1;
  STOP_ALL_ON_SATURATE:bit1;
  RESERVED1           :bit5;
 end;

 TMC_MCDVM_PERFCOUNTER_RSLT_CNTL=bitpacked record
  PERF_COUNTER_SELECT :bit4;
  RESERVED0           :bit4;
  START_TRIGGER       :bit8;
  STOP_TRIGGER        :bit8;
  ENABLE_ANY          :bit1;
  CLEAR_ALL           :bit1;
  STOP_ALL_ON_SATURATE:bit1;
  RESERVED1           :bit5;
 end;

 TMC_VM_L2_PERFCOUNTER_RSLT_CNTL=bitpacked record
  PERF_COUNTER_SELECT :bit4;
  RESERVED0           :bit4;
  START_TRIGGER       :bit8;
  STOP_TRIGGER        :bit8;
  ENABLE_ANY          :bit1;
  CLEAR_ALL           :bit1;
  STOP_ALL_ON_SATURATE:bit1;
  RESERVED1           :bit5;
 end;

 TMC_VM_SYSTEM_APERTURE_LOW_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TOVL_SURFACE_ADDRESS_HIGH_INUSE=bitpacked record
  OVL_SURFACE_ADDRESS_HIGH_INUSE:bit8;
  RESERVED0                     :bit24;
 end;

 TPA_SC_HP3D_TRAP_SCREEN_HV_LOCK=bitpacked record
  DISABLE_NON_PRIV_WRITES:bit1;
  RESERVED0              :bit31;
 end;

 TPA_SU_POLY_OFFSET_FRONT_OFFSET=bit32;

 TPB0_PLL_LC0_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_LC0_IGNR_PLLPWR_CBI_UPDT:bit1;
  RESERVED0                   :bit3;
  PLL_LC0_PLLPWR              :bit3;
  RESERVED1                   :bit25;
 end;

 TPB0_PLL_LC1_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_LC1_IGNR_PLLPWR_CBI_UPDT:bit1;
  RESERVED0                   :bit3;
  PLL_LC1_PLLPWR              :bit3;
  RESERVED1                   :bit25;
 end;

 TPB0_PLL_LC2_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_LC2_IGNR_PLLPWR_CBI_UPDT:bit1;
  RESERVED0                   :bit3;
  PLL_LC2_PLLPWR              :bit3;
  RESERVED1                   :bit25;
 end;

 TPB0_PLL_LC3_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_LC3_IGNR_PLLPWR_CBI_UPDT:bit1;
  RESERVED0                   :bit3;
  PLL_LC3_PLLPWR              :bit3;
  RESERVED1                   :bit25;
 end;

 TPB0_PLL_RO0_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_RO0_IGNR_PLLPWR_CBI_UPDT :bit1;
  PLL_RO0_IGNR_PLLFREQ_CBI_UPDT:bit1;
  RESERVED0                    :bit2;
  PLL_RO0_PLLPWR               :bit3;
  RESERVED1                    :bit1;
  PLL_RO0_PLLFREQ              :bit2;
  RESERVED2                    :bit22;
 end;

 TPB0_PLL_RO1_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_RO1_IGNR_PLLPWR_CBI_UPDT :bit1;
  PLL_RO1_IGNR_PLLFREQ_CBI_UPDT:bit1;
  RESERVED0                    :bit2;
  PLL_RO1_PLLPWR               :bit3;
  RESERVED1                    :bit1;
  PLL_RO1_PLLFREQ              :bit2;
  RESERVED2                    :bit22;
 end;

 TPB0_PLL_RO2_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_RO2_IGNR_PLLPWR_CBI_UPDT :bit1;
  PLL_RO2_IGNR_PLLFREQ_CBI_UPDT:bit1;
  RESERVED0                    :bit2;
  PLL_RO2_PLLPWR               :bit3;
  RESERVED1                    :bit1;
  PLL_RO2_PLLFREQ              :bit2;
  RESERVED2                    :bit22;
 end;

 TPB0_PLL_RO3_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_RO3_IGNR_PLLPWR_CBI_UPDT :bit1;
  PLL_RO3_IGNR_PLLFREQ_CBI_UPDT:bit1;
  RESERVED0                    :bit2;
  PLL_RO3_PLLPWR               :bit3;
  RESERVED1                    :bit1;
  PLL_RO3_PLLFREQ              :bit2;
  RESERVED2                    :bit22;
 end;

 TPB1_PLL_LC0_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_LC0_IGNR_PLLPWR_CBI_UPDT:bit1;
  RESERVED0                   :bit3;
  PLL_LC0_PLLPWR              :bit3;
  RESERVED1                   :bit25;
 end;

 TPB1_PLL_LC1_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_LC1_IGNR_PLLPWR_CBI_UPDT:bit1;
  RESERVED0                   :bit3;
  PLL_LC1_PLLPWR              :bit3;
  RESERVED1                   :bit25;
 end;

 TPB1_PLL_LC2_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_LC2_IGNR_PLLPWR_CBI_UPDT:bit1;
  RESERVED0                   :bit3;
  PLL_LC2_PLLPWR              :bit3;
  RESERVED1                   :bit25;
 end;

 TPB1_PLL_LC3_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_LC3_IGNR_PLLPWR_CBI_UPDT:bit1;
  RESERVED0                   :bit3;
  PLL_LC3_PLLPWR              :bit3;
  RESERVED1                   :bit25;
 end;

 TPB1_PLL_RO0_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_RO0_IGNR_PLLPWR_CBI_UPDT :bit1;
  PLL_RO0_IGNR_PLLFREQ_CBI_UPDT:bit1;
  RESERVED0                    :bit2;
  PLL_RO0_PLLPWR               :bit3;
  RESERVED1                    :bit1;
  PLL_RO0_PLLFREQ              :bit2;
  RESERVED2                    :bit22;
 end;

 TPB1_PLL_RO1_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_RO1_IGNR_PLLPWR_CBI_UPDT :bit1;
  PLL_RO1_IGNR_PLLFREQ_CBI_UPDT:bit1;
  RESERVED0                    :bit2;
  PLL_RO1_PLLPWR               :bit3;
  RESERVED1                    :bit1;
  PLL_RO1_PLLFREQ              :bit2;
  RESERVED2                    :bit22;
 end;

 TPB1_PLL_RO2_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_RO2_IGNR_PLLPWR_CBI_UPDT :bit1;
  PLL_RO2_IGNR_PLLFREQ_CBI_UPDT:bit1;
  RESERVED0                    :bit2;
  PLL_RO2_PLLPWR               :bit3;
  RESERVED1                    :bit1;
  PLL_RO2_PLLFREQ              :bit2;
  RESERVED2                    :bit22;
 end;

 TPB1_PLL_RO3_SCI_STAT_OVRD_REG0=bitpacked record
  PLL_RO3_IGNR_PLLPWR_CBI_UPDT :bit1;
  PLL_RO3_IGNR_PLLFREQ_CBI_UPDT:bit1;
  RESERVED0                    :bit2;
  PLL_RO3_PLLPWR               :bit3;
  RESERVED1                    :bit1;
  PLL_RO3_PLLFREQ              :bit2;
  RESERVED2                    :bit22;
 end;

 TPCIEP_ERROR_INJECT_TRANSACTION=bitpacked record
  ERROR_INJECT_TL_FLOW_CTL_ERR       :bit2;
  ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER:bit2;
  ERROR_INJECT_TL_BAD_DLLP           :bit2;
  ERROR_INJECT_TL_BAD_TLP            :bit2;
  ERROR_INJECT_TL_UNSUPPORTED_REQ    :bit2;
  ERROR_INJECT_TL_ECRC_ERROR         :bit2;
  ERROR_INJECT_TL_MALFORMED_TLP      :bit2;
  ERROR_INJECT_TL_UNEXPECTED_CMPLT   :bit2;
  ERROR_INJECT_TL_COMPLETER_ABORT    :bit2;
  ERROR_INJECT_TL_COMPLETION_TIMEOUT :bit2;
  RESERVED0                          :bit12;
 end;

 TPCIE_LANE_10_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_11_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_12_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_13_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_14_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_LANE_15_EQUALIZATION_CNTL=bitpacked record
  DOWNSTREAM_PORT_TX_PRESET     :bit4;
  DOWNSTREAM_PORT_RX_PRESET_HINT:bit3;
  RESERVED0                     :bit1;
  UPSTREAM_PORT_TX_PRESET       :bit4;
  UPSTREAM_PORT_RX_PRESET_HINT  :bit3;
  RESERVED1                     :bit17;
 end;

 TPCIE_PERF_CNTL_EVENT0_PORT_SEL=bitpacked record
  PERF0_PORT_SEL_TXCLK       :bit4;
  PERF0_PORT_SEL_MST_R_CLK   :bit4;
  PERF0_PORT_SEL_MST_C_CLK   :bit4;
  PERF0_PORT_SEL_SLV_R_CLK   :bit4;
  PERF0_PORT_SEL_SLV_S_C_CLK :bit4;
  PERF0_PORT_SEL_SLV_NS_C_CLK:bit4;
  PERF0_PORT_SEL_TXCLK2      :bit4;
  RESERVED0                  :bit4;
 end;

 TPCIE_PERF_CNTL_EVENT1_PORT_SEL=bitpacked record
  PERF1_PORT_SEL_TXCLK       :bit4;
  PERF1_PORT_SEL_MST_R_CLK   :bit4;
  PERF1_PORT_SEL_MST_C_CLK   :bit4;
  PERF1_PORT_SEL_SLV_R_CLK   :bit4;
  PERF1_PORT_SEL_SLV_S_C_CLK :bit4;
  PERF1_PORT_SEL_SLV_NS_C_CLK:bit4;
  PERF1_PORT_SEL_TXCLK2      :bit4;
  RESERVED0                  :bit4;
 end;

 TPCIE_SRIOV_SUPPORTED_PAGE_SIZE=bit32;

 TSCLV_HORZ_FILTER_SCALE_RATIO_C=bitpacked record
  SCL_H_SCALE_RATIO_C:bit26;
  RESERVED0          :bit6;
 end;

 TSCLV_VERT_FILTER_SCALE_RATIO_C=bitpacked record
  SCL_V_SCALE_RATIO_C:bit26;
  RESERVED0          :bit6;
 end;

 TSDMA0_GFX_RB_WPTR_POLL_ADDR_HI=bit32;

 TSDMA0_GFX_RB_WPTR_POLL_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA0_SEM_WAIT_FAIL_TIMER_CNTL=bit32;

 TSDMA1_GFX_RB_WPTR_POLL_ADDR_HI=bit32;

 TSDMA1_GFX_RB_WPTR_POLL_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA1_SEM_WAIT_FAIL_TIMER_CNTL=bit32;

 TSEM_MAILBOX_CLIENTCONFIG_EXTRA=bitpacked record
  VCE1_CLIENT0:bit5;
  RESERVED0   :bit27;
 end;

 TSPI_SX_SCOREBOARD_BUFFER_SIZES=bitpacked record
  COLOR_SCOREBOARD_SIZE   :bit16;
  POSITION_SCOREBOARD_SIZE:bit16;
 end;

 TVGT_STRMOUT_DRAW_OPAQUE_OFFSET=bit32;

 TVM_L2_BANK_SELECT_RESERVED_CID=bitpacked record
  RESERVED_READ_CLIENT_ID            :bit9;
  RESERVED0                          :bit1;
  RESERVED_WRITE_CLIENT_ID           :bit9;
  RESERVED1                          :bit1;
  ENABLE                             :bit1;
  RESERVED2                          :bit3;
  RESERVED_CACHE_INVALIDATION_MODE   :bit1;
  RESERVED_CACHE_PRIVATE_INVALIDATION:bit1;
  RESERVED3                          :bit6;
 end;

 TXDMA_MSTR_CACHE_BASE_ADDR_HIGH=bitpacked record
  XDMA_MSTR_CACHE_BASE_ADDR_HIGH:bit8;
  RESERVED0                     :bit24;
 end;

 TAZALIA_CUMULATIVE_LATENCY_COUNT=bit32;

 TAZALIA_CUMULATIVE_REQUEST_COUNT=bit32;

 TAZALIA_F2_CODEC_PIN_CONTROL_HBR=bitpacked record
  HBR_CAPABLE:bit1;
  RESERVED0  :bit3;
  HBR_ENABLE :bit1;
  RESERVED1  :bit27;
 end;

 TAZALIA_INPUT_PAYLOAD_CAPABILITY=bitpacked record
  INPUT_PAYLOAD_CAPABILITY:bit16;
  INSTRMPAY               :bit16;
 end;

 TCRTC_EXT_TIMING_SYNC_WINDOW_END=bitpacked record
  CRTC_EXT_TIMING_SYNC_WINDOW_END_X:bit14;
  RESERVED0                        :bit2;
  CRTC_EXT_TIMING_SYNC_WINDOW_END_Y:bit14;
  RESERVED1                        :bit2;
 end;

 TCRTC_VGA_PARAMETER_CAPTURE_MODE=bitpacked record
  CRTC_VGA_PARAMETER_CAPTURE_MODE:bit1;
  RESERVED0                      :bit31;
 end;

 TDCRX_PHY_MACRO_CNTL_RESERVED100=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED101=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED102=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED103=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED104=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED105=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED106=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED107=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED108=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED109=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED110=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED111=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED112=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED113=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED114=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED115=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED116=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED117=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED118=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED119=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED120=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED121=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED122=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED123=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED124=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED125=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED126=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED127=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED128=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED129=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED130=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED131=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED132=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED133=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED134=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED135=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED136=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED137=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED138=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED139=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED140=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED141=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED142=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED143=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED144=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED145=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED146=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED147=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED148=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED149=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED150=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED151=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED152=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED153=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED154=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED155=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED156=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED157=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED158=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED159=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED160=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED161=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED162=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED163=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED164=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED165=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED166=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED167=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED168=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED169=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED170=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED171=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED172=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED173=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED174=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED175=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED176=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED177=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED178=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED179=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED180=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED181=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED182=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED183=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED184=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED185=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED186=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED187=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED188=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED189=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED190=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED191=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED192=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED193=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED194=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED195=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED196=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED197=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED198=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED199=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED200=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED201=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED202=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED203=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED204=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED205=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED206=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED207=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED208=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED209=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED210=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED211=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED212=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED213=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED214=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED215=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED216=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED217=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED218=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED219=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED220=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED221=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED222=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED223=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED224=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED225=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED226=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED227=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED228=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED229=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED230=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED231=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED232=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED233=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED234=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED235=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED236=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED237=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED238=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED239=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED240=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED241=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED242=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED243=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED244=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED245=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED246=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED247=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED248=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED249=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED250=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED251=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED252=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED253=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED254=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED255=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED256=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED257=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED258=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED259=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED260=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED261=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED262=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED263=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED264=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED265=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED266=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED267=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED268=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED269=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED270=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED271=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED272=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED273=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED274=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED275=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED276=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED277=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED278=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED279=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED280=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED281=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED282=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED283=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED284=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED285=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED286=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED287=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED288=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED289=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED290=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED291=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED292=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED293=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED294=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED295=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED296=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED297=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED298=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED299=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED300=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED301=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED302=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED303=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED304=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED305=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED306=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED307=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED308=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED309=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED310=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED311=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED312=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED313=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED314=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED315=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED316=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED317=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED318=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED319=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED320=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED321=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED322=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED323=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED324=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED325=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED326=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED327=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED328=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED329=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED330=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED331=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED332=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED333=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED334=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED335=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED336=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED337=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED338=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED339=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED340=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED341=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED342=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED343=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED344=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED345=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED346=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED347=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED348=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED349=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED350=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED351=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED352=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED353=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED354=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED355=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED356=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED357=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED358=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED359=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED360=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED361=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED362=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED363=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED364=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED365=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED366=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED367=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED368=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED369=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED370=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED371=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED372=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED373=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED374=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED375=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED376=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED377=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED378=bit32;

 TDCRX_PHY_MACRO_CNTL_RESERVED379=bit32;

 TDC_ABM1_HG_BIN_9_16_SHIFT_INDEX=bit32;

 TDISP_INTERRUPT_STATUS_CONTINUE2=bitpacked record
  SCL_DISP3_MODE_CHANGE_INTERRUPT         :bit1;
  D3BLND_DATA_UNDERFLOW_INTERRUPT         :bit1;
  LB_D3_VLINE_INTERRUPT                   :bit1;
  LB_D3_VBLANK_INTERRUPT                  :bit1;
  CRTC3_SNAPSHOT_INTERRUPT                :bit1;
  CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT   :bit1;
  CRTC3_FORCE_COUNT_NOW_INTERRUPT         :bit1;
  CRTC3_TRIGA_INTERRUPT                   :bit1;
  CRTC3_TRIGB_INTERRUPT                   :bit1;
  CRTC3_VSYNC_NOM_INTERRUPT               :bit1;
  CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1;
  RESERVED0                               :bit1;
  RESERVED1                               :bit1;
  RESERVED2                               :bit1;
  RESERVED3                               :bit1;
  DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1;
  DIGC_DP_VID_STREAM_DISABLE_INTERRUPT    :bit1;
  DC_HPD3_INTERRUPT                       :bit1;
  DC_HPD3_RX_INTERRUPT                    :bit1;
  AUX3_SW_DONE_INTERRUPT                  :bit1;
  AUX3_LS_DONE_INTERRUPT                  :bit1;
  LB_D4_VLINE2_INTERRUPT                  :bit1;
  LB_D5_VLINE2_INTERRUPT                  :bit1;
  LB_D6_VLINE2_INTERRUPT                  :bit1;
  RESERVED4                               :bit1;
  CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT    :bit1;
  CRTC2_EXT_TIMING_SYNC_INTERRUPT         :bit1;
  CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT  :bit1;
  CRTC2_VERTICAL_INTERRUPT0               :bit1;
  CRTC2_VERTICAL_INTERRUPT1               :bit1;
  CRTC2_VERTICAL_INTERRUPT2               :bit1;
  DISP_INTERRUPT_STATUS_CONTINUE3         :bit1;
 end;

 TDISP_INTERRUPT_STATUS_CONTINUE3=bitpacked record
  SCL_DISP4_MODE_CHANGE_INTERRUPT         :bit1;
  D4BLND_DATA_UNDERFLOW_INTERRUPT         :bit1;
  LB_D4_VLINE_INTERRUPT                   :bit1;
  LB_D4_VBLANK_INTERRUPT                  :bit1;
  CRTC4_SNAPSHOT_INTERRUPT                :bit1;
  CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT   :bit1;
  CRTC4_FORCE_COUNT_NOW_INTERRUPT         :bit1;
  CRTC4_TRIGA_INTERRUPT                   :bit1;
  CRTC4_TRIGB_INTERRUPT                   :bit1;
  CRTC4_VSYNC_NOM_INTERRUPT               :bit1;
  CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1;
  RESERVED0                               :bit1;
  RESERVED1                               :bit1;
  RESERVED2                               :bit1;
  RESERVED3                               :bit1;
  DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1;
  DIGD_DP_VID_STREAM_DISABLE_INTERRUPT    :bit1;
  DC_HPD4_INTERRUPT                       :bit1;
  DC_HPD4_RX_INTERRUPT                    :bit1;
  AUX4_SW_DONE_INTERRUPT                  :bit1;
  AUX4_LS_DONE_INTERRUPT                  :bit1;
  BUFMGR_IHIF_INTERRUPT                   :bit1;
  WBSCL_HOST_CONFLICT_INTERRUPT           :bit1;
  WBSCL_DATA_OVERFLOW_INTERRUPT           :bit1;
  RESERVED4                               :bit1;
  CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT    :bit1;
  CRTC3_EXT_TIMING_SYNC_INTERRUPT         :bit1;
  CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT  :bit1;
  CRTC3_VERTICAL_INTERRUPT0               :bit1;
  CRTC3_VERTICAL_INTERRUPT1               :bit1;
  CRTC3_VERTICAL_INTERRUPT2               :bit1;
  DISP_INTERRUPT_STATUS_CONTINUE4         :bit1;
 end;

 TDISP_INTERRUPT_STATUS_CONTINUE4=bitpacked record
  SCL_DISP5_MODE_CHANGE_INTERRUPT         :bit1;
  D5BLND_DATA_UNDERFLOW_INTERRUPT         :bit1;
  LB_D5_VLINE_INTERRUPT                   :bit1;
  LB_D5_VBLANK_INTERRUPT                  :bit1;
  CRTC5_SNAPSHOT_INTERRUPT                :bit1;
  CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT   :bit1;
  CRTC5_FORCE_COUNT_NOW_INTERRUPT         :bit1;
  CRTC5_TRIGA_INTERRUPT                   :bit1;
  CRTC5_TRIGB_INTERRUPT                   :bit1;
  CRTC5_VSYNC_NOM_INTERRUPT               :bit1;
  CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1;
  RESERVED0                               :bit1;
  RESERVED1                               :bit1;
  RESERVED2                               :bit1;
  RESERVED3                               :bit1;
  DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1;
  DIGE_DP_VID_STREAM_DISABLE_INTERRUPT    :bit1;
  DC_HPD5_INTERRUPT                       :bit1;
  DC_HPD5_RX_INTERRUPT                    :bit1;
  AUX5_SW_DONE_INTERRUPT                  :bit1;
  AUX5_LS_DONE_INTERRUPT                  :bit1;
  RESERVED4                               :bit1;
  CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT    :bit1;
  CRTC4_EXT_TIMING_SYNC_INTERRUPT         :bit1;
  CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT  :bit1;
  CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT    :bit1;
  CRTC5_EXT_TIMING_SYNC_INTERRUPT         :bit1;
  CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT  :bit1;
  CRTC4_VERTICAL_INTERRUPT0               :bit1;
  CRTC4_VERTICAL_INTERRUPT1               :bit1;
  CRTC4_VERTICAL_INTERRUPT2               :bit1;
  DISP_INTERRUPT_STATUS_CONTINUE5         :bit1;
 end;

 TDISP_INTERRUPT_STATUS_CONTINUE5=bitpacked record
  SCL_DISP6_MODE_CHANGE_INTERRUPT         :bit1;
  D6BLND_DATA_UNDERFLOW_INTERRUPT         :bit1;
  LB_D6_VLINE_INTERRUPT                   :bit1;
  LB_D6_VBLANK_INTERRUPT                  :bit1;
  CRTC6_SNAPSHOT_INTERRUPT                :bit1;
  CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT   :bit1;
  CRTC6_FORCE_COUNT_NOW_INTERRUPT         :bit1;
  CRTC6_TRIGA_INTERRUPT                   :bit1;
  CRTC6_TRIGB_INTERRUPT                   :bit1;
  CRTC6_VSYNC_NOM_INTERRUPT               :bit1;
  CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1;
  RESERVED0                               :bit1;
  RESERVED1                               :bit1;
  RESERVED2                               :bit1;
  RESERVED3                               :bit1;
  DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1;
  DIGF_DP_VID_STREAM_DISABLE_INTERRUPT    :bit1;
  DC_HPD6_INTERRUPT                       :bit1;
  DC_HPD6_RX_INTERRUPT                    :bit1;
  AUX6_SW_DONE_INTERRUPT                  :bit1;
  AUX6_LS_DONE_INTERRUPT                  :bit1;
  RESERVED4                               :bit1;
  CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT    :bit1;
  CRTC6_EXT_TIMING_SYNC_INTERRUPT         :bit1;
  CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT  :bit1;
  CRTC5_VERTICAL_INTERRUPT0               :bit1;
  CRTC5_VERTICAL_INTERRUPT1               :bit1;
  CRTC5_VERTICAL_INTERRUPT2               :bit1;
  CRTC6_VERTICAL_INTERRUPT0               :bit1;
  CRTC6_VERTICAL_INTERRUPT1               :bit1;
  CRTC6_VERTICAL_INTERRUPT2               :bit1;
  DISP_INTERRUPT_STATUS_CONTINUE6         :bit1;
 end;

 TDISP_INTERRUPT_STATUS_CONTINUE6=bitpacked record
  DCRX_PERFMON_COUNTER0_INTERRUPT         :bit1;
  DCRX_PERFMON_COUNTER1_INTERRUPT         :bit1;
  DCRX_PERFMON_COUNTER2_INTERRUPT         :bit1;
  DCRX_PERFMON_COUNTER3_INTERRUPT         :bit1;
  DCRX_PERFMON_COUNTER4_INTERRUPT         :bit1;
  DCRX_PERFMON_COUNTER5_INTERRUPT         :bit1;
  DCRX_PERFMON_COUNTER6_INTERRUPT         :bit1;
  DCRX_PERFMON_COUNTER7_INTERRUPT         :bit1;
  DCRX_PERFMON_COUNTER_OFF_INTERRUPT      :bit1;
  BUFMGR_CWB0_IHIF_INTERRUPT              :bit1;
  BUFMGR_CWB1_IHIF_INTERRUPT              :bit1;
  RESERVED0                               :bit1;
  RESERVED1                               :bit1;
  RESERVED2                               :bit1;
  RESERVED3                               :bit1;
  DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1;
  DIGG_DP_VID_STREAM_DISABLE_INTERRUPT    :bit1;
  AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT       :bit1;
  AUX1_GTC_SYNC_ERROR_INTERRUPT           :bit1;
  AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT       :bit1;
  AUX2_GTC_SYNC_ERROR_INTERRUPT           :bit1;
  AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT       :bit1;
  AUX3_GTC_SYNC_ERROR_INTERRUPT           :bit1;
  AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT       :bit1;
  AUX4_GTC_SYNC_ERROR_INTERRUPT           :bit1;
  AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT       :bit1;
  AUX5_GTC_SYNC_ERROR_INTERRUPT           :bit1;
  AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT       :bit1;
  AUX6_GTC_SYNC_ERROR_INTERRUPT           :bit1;
  RESERVED4                               :bit2;
  DISP_INTERRUPT_STATUS_CONTINUE7         :bit1;
 end;

 TDISP_INTERRUPT_STATUS_CONTINUE7=bitpacked record
  DCCG_PERFMON_COUNTER0_INTERRUPT   :bit1;
  DCCG_PERFMON_COUNTER1_INTERRUPT   :bit1;
  DCCG_PERFMON_COUNTER2_INTERRUPT   :bit1;
  DCCG_PERFMON_COUNTER3_INTERRUPT   :bit1;
  DCCG_PERFMON_COUNTER4_INTERRUPT   :bit1;
  DCCG_PERFMON_COUNTER5_INTERRUPT   :bit1;
  DCCG_PERFMON_COUNTER6_INTERRUPT   :bit1;
  DCCG_PERFMON_COUNTER7_INTERRUPT   :bit1;
  DCCG_PERFMON_COUNTER_OFF_INTERRUPT:bit1;
  DCI_PERFMON_COUNTER0_INTERRUPT    :bit1;
  DCI_PERFMON_COUNTER1_INTERRUPT    :bit1;
  DCI_PERFMON_COUNTER2_INTERRUPT    :bit1;
  DCI_PERFMON_COUNTER3_INTERRUPT    :bit1;
  DCI_PERFMON_COUNTER4_INTERRUPT    :bit1;
  DCI_PERFMON_COUNTER5_INTERRUPT    :bit1;
  DCI_PERFMON_COUNTER6_INTERRUPT    :bit1;
  DCI_PERFMON_COUNTER7_INTERRUPT    :bit1;
  DCI_PERFMON_COUNTER_OFF_INTERRUPT :bit1;
  DCO_PERFMON_COUNTER0_INTERRUPT    :bit1;
  DCO_PERFMON_COUNTER1_INTERRUPT    :bit1;
  DCO_PERFMON_COUNTER2_INTERRUPT    :bit1;
  DCO_PERFMON_COUNTER3_INTERRUPT    :bit1;
  DCO_PERFMON_COUNTER4_INTERRUPT    :bit1;
  DCO_PERFMON_COUNTER5_INTERRUPT    :bit1;
  DCO_PERFMON_COUNTER6_INTERRUPT    :bit1;
  DCO_PERFMON_COUNTER7_INTERRUPT    :bit1;
  DCO_PERFMON_COUNTER_OFF_INTERRUPT :bit1;
  WB_PERFMON_COUNTER0_INTERRUPT     :bit1;
  WB_PERFMON_COUNTER1_INTERRUPT     :bit1;
  WB_PERFMON_COUNTER2_INTERRUPT     :bit1;
  WB_PERFMON_COUNTER3_INTERRUPT     :bit1;
  DISP_INTERRUPT_STATUS_CONTINUE8   :bit1;
 end;

 TDISP_INTERRUPT_STATUS_CONTINUE8=bitpacked record
  DCFE0_PERFMON_COUNTER0_INTERRUPT   :bit1;
  DCFE0_PERFMON_COUNTER1_INTERRUPT   :bit1;
  DCFE0_PERFMON_COUNTER2_INTERRUPT   :bit1;
  DCFE0_PERFMON_COUNTER3_INTERRUPT   :bit1;
  DCFE0_PERFMON_COUNTER4_INTERRUPT   :bit1;
  DCFE0_PERFMON_COUNTER5_INTERRUPT   :bit1;
  DCFE0_PERFMON_COUNTER6_INTERRUPT   :bit1;
  DCFE0_PERFMON_COUNTER7_INTERRUPT   :bit1;
  DCFE0_PERFMON_COUNTER_OFF_INTERRUPT:bit1;
  DCFE1_PERFMON_COUNTER0_INTERRUPT   :bit1;
  DCFE1_PERFMON_COUNTER1_INTERRUPT   :bit1;
  DCFE1_PERFMON_COUNTER2_INTERRUPT   :bit1;
  DCFE1_PERFMON_COUNTER3_INTERRUPT   :bit1;
  DCFE1_PERFMON_COUNTER4_INTERRUPT   :bit1;
  DCFE1_PERFMON_COUNTER5_INTERRUPT   :bit1;
  DCFE1_PERFMON_COUNTER6_INTERRUPT   :bit1;
  DCFE1_PERFMON_COUNTER7_INTERRUPT   :bit1;
  DCFE1_PERFMON_COUNTER_OFF_INTERRUPT:bit1;
  DCFE2_PERFMON_COUNTER0_INTERRUPT   :bit1;
  DCFE2_PERFMON_COUNTER1_INTERRUPT   :bit1;
  DCFE2_PERFMON_COUNTER2_INTERRUPT   :bit1;
  DCFE2_PERFMON_COUNTER3_INTERRUPT   :bit1;
  DCFE2_PERFMON_COUNTER4_INTERRUPT   :bit1;
  DCFE2_PERFMON_COUNTER5_INTERRUPT   :bit1;
  DCFE2_PERFMON_COUNTER6_INTERRUPT   :bit1;
  DCFE2_PERFMON_COUNTER7_INTERRUPT   :bit1;
  DCFE2_PERFMON_COUNTER_OFF_INTERRUPT:bit1;
  WB_PERFMON_COUNTER4_INTERRUPT      :bit1;
  WB_PERFMON_COUNTER5_INTERRUPT      :bit1;
  WB_PERFMON_COUNTER6_INTERRUPT      :bit1;
  WB_PERFMON_COUNTER7_INTERRUPT      :bit1;
  DISP_INTERRUPT_STATUS_CONTINUE9    :bit1;
 end;

 TDISP_INTERRUPT_STATUS_CONTINUE9=bitpacked record
  DCFE3_PERFMON_COUNTER0_INTERRUPT   :bit1;
  DCFE3_PERFMON_COUNTER1_INTERRUPT   :bit1;
  DCFE3_PERFMON_COUNTER2_INTERRUPT   :bit1;
  DCFE3_PERFMON_COUNTER3_INTERRUPT   :bit1;
  DCFE3_PERFMON_COUNTER4_INTERRUPT   :bit1;
  DCFE3_PERFMON_COUNTER5_INTERRUPT   :bit1;
  DCFE3_PERFMON_COUNTER6_INTERRUPT   :bit1;
  DCFE3_PERFMON_COUNTER7_INTERRUPT   :bit1;
  DCFE3_PERFMON_COUNTER_OFF_INTERRUPT:bit1;
  DCFE4_PERFMON_COUNTER0_INTERRUPT   :bit1;
  DCFE4_PERFMON_COUNTER1_INTERRUPT   :bit1;
  DCFE4_PERFMON_COUNTER2_INTERRUPT   :bit1;
  DCFE4_PERFMON_COUNTER3_INTERRUPT   :bit1;
  DCFE4_PERFMON_COUNTER4_INTERRUPT   :bit1;
  DCFE4_PERFMON_COUNTER5_INTERRUPT   :bit1;
  DCFE4_PERFMON_COUNTER6_INTERRUPT   :bit1;
  DCFE4_PERFMON_COUNTER7_INTERRUPT   :bit1;
  DCFE4_PERFMON_COUNTER_OFF_INTERRUPT:bit1;
  DCFE5_PERFMON_COUNTER0_INTERRUPT   :bit1;
  DCFE5_PERFMON_COUNTER1_INTERRUPT   :bit1;
  DCFE5_PERFMON_COUNTER2_INTERRUPT   :bit1;
  DCFE5_PERFMON_COUNTER3_INTERRUPT   :bit1;
  DCFE5_PERFMON_COUNTER4_INTERRUPT   :bit1;
  DCFE5_PERFMON_COUNTER5_INTERRUPT   :bit1;
  DCFE5_PERFMON_COUNTER6_INTERRUPT   :bit1;
  DCFE5_PERFMON_COUNTER7_INTERRUPT   :bit1;
  DCFE5_PERFMON_COUNTER_OFF_INTERRUPT:bit1;
  WB_PERFMON_COUNTER_OFF_INTERRUPT   :bit1;
  RESERVED0                          :bit4;
 end;

 TDMA_POSITION_LOWER_BASE_ADDRESS=bitpacked record
  DMA_POSITION_BUFFER_ENABLE                :bit1;
  DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS:bit6;
  DMA_POSITION_LOWER_BASE_ADDRESS           :bit25;
 end;

 TDMA_POSITION_UPPER_BASE_ADDRESS=bit32;

 TGRPH_SURFACE_ADDRESS_HIGH_INUSE=bitpacked record
  GRPH_SURFACE_ADDRESS_HIGH_INUSE:bit8;
  RESERVED0                      :bit24;
 end;

 TINPUT_STREAM_PAYLOAD_CAPABILITY=bitpacked record
  INSTRMPAY:bit16;
  RESERVED0:bit16;
 end;

 TMC_VM_SYSTEM_APERTURE_HIGH_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TMC_XPB_MAP_INVERT_FLUSH_NUM_LSB=bitpacked record
  ALTER_FLUSH_NUM:bit16;
  RESERVED0      :bit16;
 end;

 TOUTPUT_STREAM_DESCRIPTOR_FORMAT=bitpacked record
  NUMBER_OF_CHANNELS  :bit4;
  BITS_PER_SAMPLE     :bit3;
  RESERVED0           :bit1;
  SAMPLE_BASE_DIVISOR :bit3;
  SAMPLE_BASE_MULTIPLE:bit3;
  SAMPLE_BASE_RATE    :bit1;
  RESERVED1           :bit17;
 end;

 TPB0_RX_LANE0_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_0        :bit3;
  ELECIDLEDETEN_0:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_0   :bit1;
  ENABLEFOM_0    :bit1;
  REQUESTFOM_0   :bit1;
  RESPONSEMODE_0 :bit1;
  RXEYEFOM_0     :bit8;
  RESERVED1      :bit14;
 end;

 TPB0_RX_LANE1_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_1        :bit3;
  ELECIDLEDETEN_1:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_1   :bit1;
  ENABLEFOM_1    :bit1;
  REQUESTFOM_1   :bit1;
  RESPONSEMODE_1 :bit1;
  RXEYEFOM_1     :bit8;
  RESERVED1      :bit14;
 end;

 TPB0_RX_LANE2_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_2        :bit3;
  ELECIDLEDETEN_2:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_2   :bit1;
  ENABLEFOM_2    :bit1;
  REQUESTFOM_2   :bit1;
  RESPONSEMODE_2 :bit1;
  RXEYEFOM_2     :bit8;
  RESERVED1      :bit14;
 end;

 TPB0_RX_LANE3_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_3        :bit3;
  ELECIDLEDETEN_3:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_3   :bit1;
  ENABLEFOM_3    :bit1;
  REQUESTFOM_3   :bit1;
  RESPONSEMODE_3 :bit1;
  RXEYEFOM_3     :bit8;
  RESERVED1      :bit14;
 end;

 TPB0_RX_LANE4_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_4        :bit3;
  ELECIDLEDETEN_4:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_4   :bit1;
  ENABLEFOM_4    :bit1;
  REQUESTFOM_4   :bit1;
  RESPONSEMODE_4 :bit1;
  RXEYEFOM_4     :bit8;
  RESERVED1      :bit14;
 end;

 TPB0_RX_LANE5_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_5        :bit3;
  ELECIDLEDETEN_5:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_5   :bit1;
  ENABLEFOM_5    :bit1;
  REQUESTFOM_5   :bit1;
  RESPONSEMODE_5 :bit1;
  RXEYEFOM_5     :bit8;
  RESERVED1      :bit14;
 end;

 TPB0_RX_LANE6_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_6        :bit3;
  ELECIDLEDETEN_6:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_6   :bit1;
  ENABLEFOM_6    :bit1;
  REQUESTFOM_6   :bit1;
  RESPONSEMODE_6 :bit1;
  RXEYEFOM_6     :bit8;
  RESERVED1      :bit14;
 end;

 TPB0_RX_LANE7_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_7        :bit3;
  ELECIDLEDETEN_7:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_7   :bit1;
  ENABLEFOM_7    :bit1;
  REQUESTFOM_7   :bit1;
  RESPONSEMODE_7 :bit1;
  RXEYEFOM_7     :bit8;
  RESERVED1      :bit14;
 end;

 TPB0_RX_LANE8_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_8        :bit3;
  ELECIDLEDETEN_8:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_8   :bit1;
  ENABLEFOM_8    :bit1;
  REQUESTFOM_8   :bit1;
  RESPONSEMODE_8 :bit1;
  RXEYEFOM_8     :bit8;
  RESERVED1      :bit14;
 end;

 TPB0_RX_LANE9_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_9        :bit3;
  ELECIDLEDETEN_9:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_9   :bit1;
  ENABLEFOM_9    :bit1;
  REQUESTFOM_9   :bit1;
  RESPONSEMODE_9 :bit1;
  RXEYEFOM_9     :bit8;
  RESERVED1      :bit14;
 end;

 TPB0_TX_LANE0_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_0        :bit3;
  INCOHERENTCK_0 :bit1;
  TXMARG_0       :bit3;
  DEEMPH_0       :bit1;
  COEFFICIENTID_0:bit2;
  COEFFICIENT_0  :bit6;
  RESERVED0      :bit16;
 end;

 TPB0_TX_LANE1_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_1        :bit3;
  INCOHERENTCK_1 :bit1;
  TXMARG_1       :bit3;
  DEEMPH_1       :bit1;
  COEFFICIENTID_1:bit2;
  COEFFICIENT_1  :bit6;
  RESERVED0      :bit16;
 end;

 TPB0_TX_LANE2_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_2        :bit3;
  INCOHERENTCK_2 :bit1;
  TXMARG_2       :bit3;
  DEEMPH_2       :bit1;
  COEFFICIENTID_2:bit2;
  COEFFICIENT_2  :bit6;
  RESERVED0      :bit16;
 end;

 TPB0_TX_LANE3_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_3        :bit3;
  INCOHERENTCK_3 :bit1;
  TXMARG_3       :bit3;
  DEEMPH_3       :bit1;
  COEFFICIENTID_3:bit2;
  COEFFICIENT_3  :bit6;
  RESERVED0      :bit16;
 end;

 TPB0_TX_LANE4_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_4        :bit3;
  INCOHERENTCK_4 :bit1;
  TXMARG_4       :bit3;
  DEEMPH_4       :bit1;
  COEFFICIENTID_4:bit2;
  COEFFICIENT_4  :bit6;
  RESERVED0      :bit16;
 end;

 TPB0_TX_LANE5_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_5        :bit3;
  INCOHERENTCK_5 :bit1;
  TXMARG_5       :bit3;
  DEEMPH_5       :bit1;
  COEFFICIENTID_5:bit2;
  COEFFICIENT_5  :bit6;
  RESERVED0      :bit16;
 end;

 TPB0_TX_LANE6_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_6        :bit3;
  INCOHERENTCK_6 :bit1;
  TXMARG_6       :bit3;
  DEEMPH_6       :bit1;
  COEFFICIENTID_6:bit2;
  COEFFICIENT_6  :bit6;
  RESERVED0      :bit16;
 end;

 TPB0_TX_LANE7_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_7        :bit3;
  INCOHERENTCK_7 :bit1;
  TXMARG_7       :bit3;
  DEEMPH_7       :bit1;
  COEFFICIENTID_7:bit2;
  COEFFICIENT_7  :bit6;
  RESERVED0      :bit16;
 end;

 TPB0_TX_LANE8_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_8        :bit3;
  INCOHERENTCK_8 :bit1;
  TXMARG_8       :bit3;
  DEEMPH_8       :bit1;
  COEFFICIENTID_8:bit2;
  COEFFICIENT_8  :bit6;
  RESERVED0      :bit16;
 end;

 TPB0_TX_LANE9_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_9        :bit3;
  INCOHERENTCK_9 :bit1;
  TXMARG_9       :bit3;
  DEEMPH_9       :bit1;
  COEFFICIENTID_9:bit2;
  COEFFICIENT_9  :bit6;
  RESERVED0      :bit16;
 end;

 TPB1_RX_LANE0_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_0        :bit3;
  ELECIDLEDETEN_0:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_0   :bit1;
  ENABLEFOM_0    :bit1;
  REQUESTFOM_0   :bit1;
  RESPONSEMODE_0 :bit1;
  RXEYEFOM_0     :bit8;
  RESERVED1      :bit14;
 end;

 TPB1_RX_LANE1_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_1        :bit3;
  ELECIDLEDETEN_1:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_1   :bit1;
  ENABLEFOM_1    :bit1;
  REQUESTFOM_1   :bit1;
  RESPONSEMODE_1 :bit1;
  RXEYEFOM_1     :bit8;
  RESERVED1      :bit14;
 end;

 TPB1_RX_LANE2_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_2        :bit3;
  ELECIDLEDETEN_2:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_2   :bit1;
  ENABLEFOM_2    :bit1;
  REQUESTFOM_2   :bit1;
  RESPONSEMODE_2 :bit1;
  RXEYEFOM_2     :bit8;
  RESERVED1      :bit14;
 end;

 TPB1_RX_LANE3_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_3        :bit3;
  ELECIDLEDETEN_3:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_3   :bit1;
  ENABLEFOM_3    :bit1;
  REQUESTFOM_3   :bit1;
  RESPONSEMODE_3 :bit1;
  RXEYEFOM_3     :bit8;
  RESERVED1      :bit14;
 end;

 TPB1_RX_LANE4_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_4        :bit3;
  ELECIDLEDETEN_4:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_4   :bit1;
  ENABLEFOM_4    :bit1;
  REQUESTFOM_4   :bit1;
  RESPONSEMODE_4 :bit1;
  RXEYEFOM_4     :bit8;
  RESERVED1      :bit14;
 end;

 TPB1_RX_LANE5_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_5        :bit3;
  ELECIDLEDETEN_5:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_5   :bit1;
  ENABLEFOM_5    :bit1;
  REQUESTFOM_5   :bit1;
  RESPONSEMODE_5 :bit1;
  RXEYEFOM_5     :bit8;
  RESERVED1      :bit14;
 end;

 TPB1_RX_LANE6_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_6        :bit3;
  ELECIDLEDETEN_6:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_6   :bit1;
  ENABLEFOM_6    :bit1;
  REQUESTFOM_6   :bit1;
  RESPONSEMODE_6 :bit1;
  RXEYEFOM_6     :bit8;
  RESERVED1      :bit14;
 end;

 TPB1_RX_LANE7_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_7        :bit3;
  ELECIDLEDETEN_7:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_7   :bit1;
  ENABLEFOM_7    :bit1;
  REQUESTFOM_7   :bit1;
  RESPONSEMODE_7 :bit1;
  RXEYEFOM_7     :bit8;
  RESERVED1      :bit14;
 end;

 TPB1_RX_LANE8_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_8        :bit3;
  ELECIDLEDETEN_8:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_8   :bit1;
  ENABLEFOM_8    :bit1;
  REQUESTFOM_8   :bit1;
  RESPONSEMODE_8 :bit1;
  RXEYEFOM_8     :bit8;
  RESERVED1      :bit14;
 end;

 TPB1_RX_LANE9_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_9        :bit3;
  ELECIDLEDETEN_9:bit1;
  RESERVED0      :bit2;
  REQUESTTRK_9   :bit1;
  ENABLEFOM_9    :bit1;
  REQUESTFOM_9   :bit1;
  RESPONSEMODE_9 :bit1;
  RXEYEFOM_9     :bit8;
  RESERVED1      :bit14;
 end;

 TPB1_TX_LANE0_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_0        :bit3;
  INCOHERENTCK_0 :bit1;
  TXMARG_0       :bit3;
  DEEMPH_0       :bit1;
  COEFFICIENTID_0:bit2;
  COEFFICIENT_0  :bit6;
  RESERVED0      :bit16;
 end;

 TPB1_TX_LANE1_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_1        :bit3;
  INCOHERENTCK_1 :bit1;
  TXMARG_1       :bit3;
  DEEMPH_1       :bit1;
  COEFFICIENTID_1:bit2;
  COEFFICIENT_1  :bit6;
  RESERVED0      :bit16;
 end;

 TPB1_TX_LANE2_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_2        :bit3;
  INCOHERENTCK_2 :bit1;
  TXMARG_2       :bit3;
  DEEMPH_2       :bit1;
  COEFFICIENTID_2:bit2;
  COEFFICIENT_2  :bit6;
  RESERVED0      :bit16;
 end;

 TPB1_TX_LANE3_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_3        :bit3;
  INCOHERENTCK_3 :bit1;
  TXMARG_3       :bit3;
  DEEMPH_3       :bit1;
  COEFFICIENTID_3:bit2;
  COEFFICIENT_3  :bit6;
  RESERVED0      :bit16;
 end;

 TPB1_TX_LANE4_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_4        :bit3;
  INCOHERENTCK_4 :bit1;
  TXMARG_4       :bit3;
  DEEMPH_4       :bit1;
  COEFFICIENTID_4:bit2;
  COEFFICIENT_4  :bit6;
  RESERVED0      :bit16;
 end;

 TPB1_TX_LANE5_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_5        :bit3;
  INCOHERENTCK_5 :bit1;
  TXMARG_5       :bit3;
  DEEMPH_5       :bit1;
  COEFFICIENTID_5:bit2;
  COEFFICIENT_5  :bit6;
  RESERVED0      :bit16;
 end;

 TPB1_TX_LANE6_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_6        :bit3;
  INCOHERENTCK_6 :bit1;
  TXMARG_6       :bit3;
  DEEMPH_6       :bit1;
  COEFFICIENTID_6:bit2;
  COEFFICIENT_6  :bit6;
  RESERVED0      :bit16;
 end;

 TPB1_TX_LANE7_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_7        :bit3;
  INCOHERENTCK_7 :bit1;
  TXMARG_7       :bit3;
  DEEMPH_7       :bit1;
  COEFFICIENTID_7:bit2;
  COEFFICIENT_7  :bit6;
  RESERVED0      :bit16;
 end;

 TPB1_TX_LANE8_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_8        :bit3;
  INCOHERENTCK_8 :bit1;
  TXMARG_8       :bit3;
  DEEMPH_8       :bit1;
  COEFFICIENTID_8:bit2;
  COEFFICIENT_8  :bit6;
  RESERVED0      :bit16;
 end;

 TPB1_TX_LANE9_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_9        :bit3;
  INCOHERENTCK_9 :bit1;
  TXMARG_9       :bit3;
  DEEMPH_9       :bit1;
  COEFFICIENTID_9:bit2;
  COEFFICIENT_9  :bit6;
  RESERVED0      :bit16;
 end;

 TPCIE_OUTSTAND_PAGE_REQ_CAPACITY=bit32;

 TPCIE_VENDOR_SPECIFIC_HDR_GPUIOV=bitpacked record
  VSEC_ID    :bit16;
  VSEC_REV   :bit4;
  VSEC_LENGTH:bit12;
 end;

 TPCIE_WRAP_TURNAROUND_DAISYCHAIN=bitpacked record
  END_BIFCORE_REGISTER_DAISYCHAIN:bit1;
  END_WRAPPER_REGISTER_DAISYCHAIN:bit1;
  RESERVED0                      :bit30;
 end;

 TRLC_SERDES_WR_NONCU_MASTER_MASK=bitpacked record
  SE_MASTER_MASK    :bit16;
  GC_MASTER_MASK    :bit1;
  GC_GFX_MASTER_MASK:bit1;
  TC0_MASTER_MASK   :bit1;
  TC1_MASTER_MASK   :bit1;
  SPARE0_MASTER_MASK:bit1;
  SPARE1_MASTER_MASK:bit1;
  SPARE2_MASTER_MASK:bit1;
  SPARE3_MASTER_MASK:bit1;
  RESERVED          :bit8;
 end;

 TRLC_SPM_CB_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_DB_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_IA_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_PA_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_SC_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_SX_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_TA_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_TD_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TSCLV_VIEWPORT_START_SECONDARY_C=bitpacked record
  VIEWPORT_Y_START_SECONDARY_C:bit14;
  RESERVED0                   :bit2;
  VIEWPORT_X_START_SECONDARY_C:bit14;
  RESERVED1                   :bit2;
 end;

 TSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI=bit32;

 TSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI=bit32;

 TSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI=bit32;

 TSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI=bit32;

 TSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO=bitpacked record
  RESERVED0:bit2;
  ADDR     :bit30;
 end;

 TSQ_THREAD_TRACE_WORD_REG_1_OF_2=bitpacked record
  TOKEN_TYPE      :bit4;
  TIME_DELTA      :bit1;
  PIPE_ID         :bit2;
  ME_ID           :bit2;
  REG_DROPPED_PREV:bit1;
  REG_TYPE        :bit3;
  RESERVED0       :bit1;
  REG_PRIV        :bit1;
  REG_OP          :bit1;
  REG_ADDR        :bit16;
 end;

 TSQ_THREAD_TRACE_WORD_REG_2_OF_2=bit32;

 TSQ_THREAD_TRACE_WORD_WAVE_START=bitpacked record
  TOKEN_TYPE            :bit4;
  TIME_DELTA            :bit1;
  SH_ID                 :bit1;
  CU_ID                 :bit4;
  WAVE_ID               :bit4;
  SIMD_ID               :bit2;
  DISPATCHER            :bit5;
  VS_NO_ALLOC_OR_GROUPED:bit1;
  COUNT                 :bit7;
  TG_ID                 :bit3;
 end;

 TVM_CONTEXT0_PAGE_TABLE_END_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TVM_CONTEXT1_PAGE_TABLE_END_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TVM_L2_BANK_SELECT_RESERVED_CID2=bitpacked record
  RESERVED_READ_CLIENT_ID            :bit9;
  RESERVED0                          :bit1;
  RESERVED_WRITE_CLIENT_ID           :bit9;
  RESERVED1                          :bit1;
  ENABLE                             :bit1;
  RESERVED2                          :bit3;
  RESERVED_CACHE_INVALIDATION_MODE   :bit1;
  RESERVED_CACHE_PRIVATE_INVALIDATION:bit1;
  RESERVED3                          :bit6;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_LPIB=bit32;

 TAZALIA_F2_CODEC_PIN_CONTROL_LPIB=bit32;

 TAZALIA_OUTPUT_PAYLOAD_CAPABILITY=bitpacked record
  OUTPUT_PAYLOAD_CAPABILITY:bit16;
  OUTSTRMPAY               :bit16;
 end;

 TCRTC_VERTICAL_INTERRUPT0_CONTROL=bitpacked record
  RESERVED0                               :bit4;
  CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY:bit1;
  RESERVED1                               :bit3;
  CRTC_VERTICAL_INTERRUPT0_INT_ENABLE     :bit1;
  RESERVED2                               :bit3;
  CRTC_VERTICAL_INTERRUPT0_STATUS         :bit1;
  RESERVED3                               :bit3;
  CRTC_VERTICAL_INTERRUPT0_INT_STATUS     :bit1;
  RESERVED4                               :bit3;
  CRTC_VERTICAL_INTERRUPT0_CLEAR          :bit1;
  RESERVED5                               :bit3;
  CRTC_VERTICAL_INTERRUPT0_INT_TYPE       :bit1;
  RESERVED6                               :bit7;
 end;

 TCRTC_VERTICAL_INTERRUPT1_CONTROL=bitpacked record
  RESERVED0                          :bit8;
  CRTC_VERTICAL_INTERRUPT1_INT_ENABLE:bit1;
  RESERVED1                          :bit3;
  CRTC_VERTICAL_INTERRUPT1_STATUS    :bit1;
  RESERVED2                          :bit3;
  CRTC_VERTICAL_INTERRUPT1_INT_STATUS:bit1;
  RESERVED3                          :bit3;
  CRTC_VERTICAL_INTERRUPT1_CLEAR     :bit1;
  RESERVED4                          :bit3;
  CRTC_VERTICAL_INTERRUPT1_INT_TYPE  :bit1;
  RESERVED5                          :bit7;
 end;

 TCRTC_VERTICAL_INTERRUPT2_CONTROL=bitpacked record
  RESERVED0                          :bit8;
  CRTC_VERTICAL_INTERRUPT2_INT_ENABLE:bit1;
  RESERVED1                          :bit3;
  CRTC_VERTICAL_INTERRUPT2_STATUS    :bit1;
  RESERVED2                          :bit3;
  CRTC_VERTICAL_INTERRUPT2_INT_STATUS:bit1;
  RESERVED3                          :bit3;
  CRTC_VERTICAL_INTERRUPT2_CLEAR     :bit1;
  RESERVED4                          :bit3;
  CRTC_VERTICAL_INTERRUPT2_INT_TYPE  :bit1;
  RESERVED5                          :bit7;
 end;

 TDC_ABM1_HG_BIN_17_24_SHIFT_INDEX=bit32;

 TDC_ABM1_HG_BIN_25_32_SHIFT_INDEX=bit32;

 TDC_ABM1_LS_FILTERED_MIN_MAX_LUMA=bitpacked record
  ABM1_LS_FILTERED_MIN_LUMA:bit10;
  RESERVED0                :bit6;
  ABM1_LS_FILTERED_MAX_LUMA:bit10;
  RESERVED1                :bit6;
 end;

 TDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT=bitpacked record
  ABM1_LS_MAX_PIXEL_VALUE_COUNT:bit24;
  RESERVED0                    :bit8;
 end;

 TDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT=bitpacked record
  ABM1_LS_MIN_PIXEL_VALUE_COUNT:bit24;
  RESERVED0                    :bit8;
 end;

 TOUTPUT_STREAM_PAYLOAD_CAPABILITY=bitpacked record
  OUTSTRMPAY:bit16;
  RESERVED0 :bit16;
 end;

 TPA_SC_P3D_TRAP_SCREEN_OCCURRENCE=bitpacked record
  COUNT    :bit16;
  RESERVED0:bit16;
 end;

 TPB0_RX_LANE10_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_10        :bit3;
  ELECIDLEDETEN_10:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_10   :bit1;
  ENABLEFOM_10    :bit1;
  REQUESTFOM_10   :bit1;
  RESPONSEMODE_10 :bit1;
  RXEYEFOM_10     :bit8;
  RESERVED1       :bit14;
 end;

 TPB0_RX_LANE11_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_11        :bit3;
  ELECIDLEDETEN_11:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_11   :bit1;
  ENABLEFOM_11    :bit1;
  REQUESTFOM_11   :bit1;
  RESPONSEMODE_11 :bit1;
  RXEYEFOM_11     :bit8;
  RESERVED1       :bit14;
 end;

 TPB0_RX_LANE12_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_12        :bit3;
  ELECIDLEDETEN_12:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_12   :bit1;
  ENABLEFOM_12    :bit1;
  REQUESTFOM_12   :bit1;
  RESPONSEMODE_12 :bit1;
  RXEYEFOM_12     :bit8;
  RESERVED1       :bit14;
 end;

 TPB0_RX_LANE13_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_13        :bit3;
  ELECIDLEDETEN_13:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_13   :bit1;
  ENABLEFOM_13    :bit1;
  REQUESTFOM_13   :bit1;
  RESPONSEMODE_13 :bit1;
  RXEYEFOM_13     :bit8;
  RESERVED1       :bit14;
 end;

 TPB0_RX_LANE14_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_14        :bit3;
  ELECIDLEDETEN_14:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_14   :bit1;
  ENABLEFOM_14    :bit1;
  REQUESTFOM_14   :bit1;
  RESPONSEMODE_14 :bit1;
  RXEYEFOM_14     :bit8;
  RESERVED1       :bit14;
 end;

 TPB0_RX_LANE15_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_15        :bit3;
  ELECIDLEDETEN_15:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_15   :bit1;
  ENABLEFOM_15    :bit1;
  REQUESTFOM_15   :bit1;
  RESPONSEMODE_15 :bit1;
  RXEYEFOM_15     :bit8;
  RESERVED1       :bit14;
 end;

 TPB0_TX_LANE10_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_10        :bit3;
  INCOHERENTCK_10 :bit1;
  TXMARG_10       :bit3;
  DEEMPH_10       :bit1;
  COEFFICIENTID_10:bit2;
  COEFFICIENT_10  :bit6;
  RESERVED0       :bit16;
 end;

 TPB0_TX_LANE11_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_11        :bit3;
  INCOHERENTCK_11 :bit1;
  TXMARG_11       :bit3;
  DEEMPH_11       :bit1;
  COEFFICIENTID_11:bit2;
  COEFFICIENT_11  :bit6;
  RESERVED0       :bit16;
 end;

 TPB0_TX_LANE12_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_12        :bit3;
  INCOHERENTCK_12 :bit1;
  TXMARG_12       :bit3;
  DEEMPH_12       :bit1;
  COEFFICIENTID_12:bit2;
  COEFFICIENT_12  :bit6;
  RESERVED0       :bit16;
 end;

 TPB0_TX_LANE13_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_13        :bit3;
  INCOHERENTCK_13 :bit1;
  TXMARG_13       :bit3;
  DEEMPH_13       :bit1;
  COEFFICIENTID_13:bit2;
  COEFFICIENT_13  :bit6;
  RESERVED0       :bit16;
 end;

 TPB0_TX_LANE14_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_14        :bit3;
  INCOHERENTCK_14 :bit1;
  TXMARG_14       :bit3;
  DEEMPH_14       :bit1;
  COEFFICIENTID_14:bit2;
  COEFFICIENT_14  :bit6;
  RESERVED0       :bit16;
 end;

 TPB0_TX_LANE15_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_15        :bit3;
  INCOHERENTCK_15 :bit1;
  TXMARG_15       :bit3;
  DEEMPH_15       :bit1;
  COEFFICIENTID_15:bit2;
  COEFFICIENT_15  :bit6;
  RESERVED0       :bit16;
 end;

 TPB1_RX_LANE10_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_10        :bit3;
  ELECIDLEDETEN_10:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_10   :bit1;
  ENABLEFOM_10    :bit1;
  REQUESTFOM_10   :bit1;
  RESPONSEMODE_10 :bit1;
  RXEYEFOM_10     :bit8;
  RESERVED1       :bit14;
 end;

 TPB1_RX_LANE11_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_11        :bit3;
  ELECIDLEDETEN_11:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_11   :bit1;
  ENABLEFOM_11    :bit1;
  REQUESTFOM_11   :bit1;
  RESPONSEMODE_11 :bit1;
  RXEYEFOM_11     :bit8;
  RESERVED1       :bit14;
 end;

 TPB1_RX_LANE12_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_12        :bit3;
  ELECIDLEDETEN_12:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_12   :bit1;
  ENABLEFOM_12    :bit1;
  REQUESTFOM_12   :bit1;
  RESPONSEMODE_12 :bit1;
  RXEYEFOM_12     :bit8;
  RESERVED1       :bit14;
 end;

 TPB1_RX_LANE13_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_13        :bit3;
  ELECIDLEDETEN_13:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_13   :bit1;
  ENABLEFOM_13    :bit1;
  REQUESTFOM_13   :bit1;
  RESPONSEMODE_13 :bit1;
  RXEYEFOM_13     :bit8;
  RESERVED1       :bit14;
 end;

 TPB1_RX_LANE14_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_14        :bit3;
  ELECIDLEDETEN_14:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_14   :bit1;
  ENABLEFOM_14    :bit1;
  REQUESTFOM_14   :bit1;
  RESPONSEMODE_14 :bit1;
  RXEYEFOM_14     :bit8;
  RESERVED1       :bit14;
 end;

 TPB1_RX_LANE15_SCI_STAT_OVRD_REG0=bitpacked record
  RXPWR_15        :bit3;
  ELECIDLEDETEN_15:bit1;
  RESERVED0       :bit2;
  REQUESTTRK_15   :bit1;
  ENABLEFOM_15    :bit1;
  REQUESTFOM_15   :bit1;
  RESPONSEMODE_15 :bit1;
  RXEYEFOM_15     :bit8;
  RESERVED1       :bit14;
 end;

 TPB1_TX_LANE10_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_10        :bit3;
  INCOHERENTCK_10 :bit1;
  TXMARG_10       :bit3;
  DEEMPH_10       :bit1;
  COEFFICIENTID_10:bit2;
  COEFFICIENT_10  :bit6;
  RESERVED0       :bit16;
 end;

 TPB1_TX_LANE11_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_11        :bit3;
  INCOHERENTCK_11 :bit1;
  TXMARG_11       :bit3;
  DEEMPH_11       :bit1;
  COEFFICIENTID_11:bit2;
  COEFFICIENT_11  :bit6;
  RESERVED0       :bit16;
 end;

 TPB1_TX_LANE12_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_12        :bit3;
  INCOHERENTCK_12 :bit1;
  TXMARG_12       :bit3;
  DEEMPH_12       :bit1;
  COEFFICIENTID_12:bit2;
  COEFFICIENT_12  :bit6;
  RESERVED0       :bit16;
 end;

 TPB1_TX_LANE13_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_13        :bit3;
  INCOHERENTCK_13 :bit1;
  TXMARG_13       :bit3;
  DEEMPH_13       :bit1;
  COEFFICIENTID_13:bit2;
  COEFFICIENT_13  :bit6;
  RESERVED0       :bit16;
 end;

 TPB1_TX_LANE14_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_14        :bit3;
  INCOHERENTCK_14 :bit1;
  TXMARG_14       :bit3;
  DEEMPH_14       :bit1;
  COEFFICIENTID_14:bit2;
  COEFFICIENT_14  :bit6;
  RESERVED0       :bit16;
 end;

 TPB1_TX_LANE15_SCI_STAT_OVRD_REG0=bitpacked record
  TXPWR_15        :bit3;
  INCOHERENTCK_15 :bit1;
  TXMARG_15       :bit3;
  DEEMPH_15       :bit1;
  COEFFICIENTID_15:bit2;
  COEFFICIENT_15  :bit6;
  RESERVED0       :bit16;
 end;

 TPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7=bitpacked record
  SUBSTATE_PWR_ALLOC:bit8;
  RESERVED0         :bit24;
 end;

 TRLC_SPM_CPC_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_CPF_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_CPG_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_GDS_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_SPI_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_SQG_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_TCA_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_TCC_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_TCP_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TRLC_SPM_VGT_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED0           :bit24;
 end;

 TSQ_THREAD_TRACE_WORD_PERF_1_OF_2=bitpacked record
  TOKEN_TYPE:bit4;
  TIME_DELTA:bit1;
  SH_ID     :bit1;
  CU_ID     :bit4;
  CNTR_BANK :bit2;
  CNTR0     :bit13;
  CNTR1_LO  :bit7;
 end;

 TSQ_THREAD_TRACE_WORD_PERF_2_OF_2=bitpacked record
  CNTR1_HI:bit6;
  CNTR2   :bit13;
  CNTR3   :bit13;
 end;

 TTARGET_AND_CURRENT_PROFILE_INDEX=bitpacked record
  TARGET_STATE   :bit4;
  CURRENT_STATE  :bit4;
  CURR_MCLK_INDEX:bit4;
  TARG_MCLK_INDEX:bit4;
  CURR_SCLK_INDEX:bit5;
  TARG_SCLK_INDEX:bit5;
  CURR_LCLK_INDEX:bit3;
  TARG_LCLK_INDEX:bit3;
 end;

 TUNP_GRPH_SURFACE_ADDRESS_INUSE_C=bitpacked record
  RESERVED0                   :bit8;
  GRPH_SURFACE_ADDRESS_INUSE_C:bit24;
 end;

 TUNP_GRPH_SURFACE_ADDRESS_INUSE_L=bitpacked record
  RESERVED0                   :bit8;
  GRPH_SURFACE_ADDRESS_INUSE_L:bit24;
 end;

 TUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW=bit32;

 TUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=bitpacked record
  WAIT_FAULT_EN   :bit1;
  WAIT_FAULT_COUNT:bit20;
  RESERVED0       :bit3;
  RESEND_TIMER    :bit3;
  RESERVED1       :bit5;
 end;

 TVGT_STRMOUT_BUFFER_FILLED_SIZE_0=bit32;

 TVGT_STRMOUT_BUFFER_FILLED_SIZE_1=bit32;

 TVGT_STRMOUT_BUFFER_FILLED_SIZE_2=bit32;

 TVGT_STRMOUT_BUFFER_FILLED_SIZE_3=bit32;

 TVM_CONTEXT0_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT1_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT2_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT3_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT4_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT5_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT6_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT7_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT8_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT9_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH=bitpacked record
  XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH:bit8;
  RESERVED0                       :bit24;
 end;

 TCC_RCU_DC_AUDIO_PORT_CONNECTIVITY=bitpacked record
  PORT_CONNECTIVITY                :bit3;
  RESERVED0                        :bit1;
  PORT_CONNECTIVITY_OVERRIDE_ENABLE:bit1;
  RESERVED1                        :bit27;
 end;

 TCRTC_EXT_TIMING_SYNC_WINDOW_START=bitpacked record
  CRTC_EXT_TIMING_SYNC_WINDOW_START_X:bit14;
  RESERVED0                          :bit2;
  CRTC_EXT_TIMING_SYNC_WINDOW_START_Y:bit14;
  RESERVED1                          :bit2;
 end;

 TCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE=bitpacked record
  CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE:bit1;
  RESERVED0                        :bit31;
 end;

 TCRTC_MVP_INBAND_CNTL_INSERT_TIMER=bitpacked record
  CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER:bit8;
  RESERVED0                             :bit24;
 end;

 TCRTC_VERTICAL_INTERRUPT0_POSITION=bitpacked record
  CRTC_VERTICAL_INTERRUPT0_LINE_START:bit14;
  RESERVED0                          :bit2;
  CRTC_VERTICAL_INTERRUPT0_LINE_END  :bit14;
  RESERVED1                          :bit2;
 end;

 TCRTC_VERTICAL_INTERRUPT1_POSITION=bitpacked record
  CRTC_VERTICAL_INTERRUPT1_LINE_START:bit14;
  RESERVED0                          :bit18;
 end;

 TCRTC_VERTICAL_INTERRUPT2_POSITION=bitpacked record
  CRTC_VERTICAL_INTERRUPT2_LINE_START:bit14;
  RESERVED0                          :bit18;
 end;

 TDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL=bitpacked record
  ABM1_HG_READY_INT_XIRQ_IRQ_SEL            :bit1;
  ABM1_LS_READY_INT_XIRQ_IRQ_SEL            :bit1;
  ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL           :bit1;
  MCP_INT_XIRQ_IRQ_SEL                      :bit1;
  DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL    :bit1;
  DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL  :bit1;
  STATIC_SCREEN1_INT_XIRQ_IRQ_SEL           :bit1;
  STATIC_SCREEN2_INT_XIRQ_IRQ_SEL           :bit1;
  EXTERNAL_SW_INT_XIRQ_IRQ_SEL              :bit1;
  STATIC_SCREEN3_INT_XIRQ_IRQ_SEL           :bit1;
  STATIC_SCREEN4_INT_XIRQ_IRQ_SEL           :bit1;
  STATIC_SCREEN5_INT_XIRQ_IRQ_SEL           :bit1;
  DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL  :bit1;
  DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL  :bit1;
  DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL  :bit1;
  DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL  :bit1;
  DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL  :bit1;
  DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL  :bit1;
  DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1;
  DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1;
  DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1;
  DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1;
  DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1;
  DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1;
  VBLANK1_INT_XIRQ_IRQ_SEL                  :bit1;
  VBLANK2_INT_XIRQ_IRQ_SEL                  :bit1;
  VBLANK3_INT_XIRQ_IRQ_SEL                  :bit1;
  VBLANK4_INT_XIRQ_IRQ_SEL                  :bit1;
  VBLANK5_INT_XIRQ_IRQ_SEL                  :bit1;
  VBLANK6_INT_XIRQ_IRQ_SEL                  :bit1;
  STATIC_SCREEN6_INT_XIRQ_IRQ_SEL           :bit1;
  RESERVED0                                 :bit1;
 end;

 TDPG_PIPE_NB_PSTATE_CHANGE_CONTROL=bitpacked record
  NB_PSTATE_CHANGE_ENABLE                         :bit1;
  RESERVED0                                       :bit3;
  NB_PSTATE_CHANGE_URGENT_DURING_REQUEST          :bit1;
  RESERVED1                                       :bit3;
  NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST:bit1;
  NB_PSTATE_CHANGE_FORCE_ON                       :bit1;
  NB_PSTATE_ALLOW_FOR_URGENT                      :bit1;
  RESERVED2                                       :bit5;
  NB_PSTATE_CHANGE_WATERMARK                      :bit16;
 end;

 TDPG_PIPE_STUTTER_CONTROL_NONLPTCH=bitpacked record
  STUTTER_ENABLE_NONLPTCH                    :bit1;
  RESERVED0                                  :bit3;
  STUTTER_IGNORE_CURSOR_NONLPTCH             :bit1;
  STUTTER_IGNORE_ICON_NONLPTCH               :bit1;
  STUTTER_IGNORE_VGA_NONLPTCH                :bit1;
  STUTTER_IGNORE_FBC_NONLPTCH                :bit1;
  STUTTER_WM_HIGH_FORCE_ON_NONLPTCH          :bit1;
  STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH   :bit1;
  STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH:bit1;
  STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH     :bit1;
  RESERVED1                                  :bit20;
 end;

 TGMCON_STCTRL_REGISTER_SAVE_RANGE0=bitpacked record
  STCTRL_REGISTER_SAVE_BASE0 :bit16;
  STCTRL_REGISTER_SAVE_LIMIT0:bit16;
 end;

 TGMCON_STCTRL_REGISTER_SAVE_RANGE1=bitpacked record
  STCTRL_REGISTER_SAVE_BASE1 :bit16;
  STCTRL_REGISTER_SAVE_LIMIT1:bit16;
 end;

 TGMCON_STCTRL_REGISTER_SAVE_RANGE2=bitpacked record
  STCTRL_REGISTER_SAVE_BASE2 :bit16;
  STCTRL_REGISTER_SAVE_LIMIT2:bit16;
 end;

 TGRPH_PRIMARY_SURFACE_ADDRESS_HIGH=bitpacked record
  GRPH_PRIMARY_SURFACE_ADDRESS_HIGH:bit8;
  RESERVED0                        :bit24;
 end;

 TIH_CLIENT_MAY_SEND_INCOMPLETE_INT=bitpacked record
  CG       :bit1;
  DC       :bit1;
  RESERVED0:bit1;
  SAMMSP   :bit1;
  RLC      :bit1;
  ROM      :bit1;
  SRBM     :bit1;
  VMC      :bit1;
  UVD      :bit1;
  BIF      :bit1;
  SDMA0    :bit1;
  SDMA1    :bit1;
  ISP      :bit1;
  VCE0     :bit1;
  VCE1     :bit1;
  ATC      :bit1;
  XDMA     :bit1;
  ACP      :bit1;
  SH       :bit1;
  SH1      :bit1;
  SH2      :bit1;
  SH3      :bit1;
  RESERVED1:bit10;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0=bitpacked record
  S0_X:bit4;
  S0_Y:bit4;
  S1_X:bit4;
  S1_Y:bit4;
  S2_X:bit4;
  S2_Y:bit4;
  S3_X:bit4;
  S3_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1=bitpacked record
  S4_X:bit4;
  S4_Y:bit4;
  S5_X:bit4;
  S5_Y:bit4;
  S6_X:bit4;
  S6_Y:bit4;
  S7_X:bit4;
  S7_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2=bitpacked record
  S8_X :bit4;
  S8_Y :bit4;
  S9_X :bit4;
  S9_Y :bit4;
  S10_X:bit4;
  S10_Y:bit4;
  S11_X:bit4;
  S11_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3=bitpacked record
  S12_X:bit4;
  S12_Y:bit4;
  S13_X:bit4;
  S13_Y:bit4;
  S14_X:bit4;
  S14_Y:bit4;
  S15_X:bit4;
  S15_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0=bitpacked record
  S0_X:bit4;
  S0_Y:bit4;
  S1_X:bit4;
  S1_Y:bit4;
  S2_X:bit4;
  S2_Y:bit4;
  S3_X:bit4;
  S3_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1=bitpacked record
  S4_X:bit4;
  S4_Y:bit4;
  S5_X:bit4;
  S5_Y:bit4;
  S6_X:bit4;
  S6_Y:bit4;
  S7_X:bit4;
  S7_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2=bitpacked record
  S8_X :bit4;
  S8_Y :bit4;
  S9_X :bit4;
  S9_Y :bit4;
  S10_X:bit4;
  S10_Y:bit4;
  S11_X:bit4;
  S11_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3=bitpacked record
  S12_X:bit4;
  S12_Y:bit4;
  S13_X:bit4;
  S13_Y:bit4;
  S14_X:bit4;
  S14_Y:bit4;
  S15_X:bit4;
  S15_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0=bitpacked record
  S0_X:bit4;
  S0_Y:bit4;
  S1_X:bit4;
  S1_Y:bit4;
  S2_X:bit4;
  S2_Y:bit4;
  S3_X:bit4;
  S3_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1=bitpacked record
  S4_X:bit4;
  S4_Y:bit4;
  S5_X:bit4;
  S5_Y:bit4;
  S6_X:bit4;
  S6_Y:bit4;
  S7_X:bit4;
  S7_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2=bitpacked record
  S8_X :bit4;
  S8_Y :bit4;
  S9_X :bit4;
  S9_Y :bit4;
  S10_X:bit4;
  S10_Y:bit4;
  S11_X:bit4;
  S11_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3=bitpacked record
  S12_X:bit4;
  S12_Y:bit4;
  S13_X:bit4;
  S13_Y:bit4;
  S14_X:bit4;
  S14_Y:bit4;
  S15_X:bit4;
  S15_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0=bitpacked record
  S0_X:bit4;
  S0_Y:bit4;
  S1_X:bit4;
  S1_Y:bit4;
  S2_X:bit4;
  S2_Y:bit4;
  S3_X:bit4;
  S3_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1=bitpacked record
  S4_X:bit4;
  S4_Y:bit4;
  S5_X:bit4;
  S5_Y:bit4;
  S6_X:bit4;
  S6_Y:bit4;
  S7_X:bit4;
  S7_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2=bitpacked record
  S8_X :bit4;
  S8_Y :bit4;
  S9_X :bit4;
  S9_Y :bit4;
  S10_X:bit4;
  S10_Y:bit4;
  S11_X:bit4;
  S11_Y:bit4;
 end;

 TPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3=bitpacked record
  S12_X:bit4;
  S12_Y:bit4;
  S13_X:bit4;
  S13_Y:bit4;
  S14_X:bit4;
  S14_Y:bit4;
  S15_X:bit4;
  S15_Y:bit4;
 end;

 TPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE=bitpacked record
  COUNT    :bit16;
  RESERVED0:bit16;
 end;

 TPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED            :bit24;
 end;

 TRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED            :bit24;
 end;

 TRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED            :bit24;
 end;

 TRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY=bitpacked record
  PERFMON_SAMPLE_DELAY:bit8;
  RESERVED            :bit24;
 end;

 TUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH=bit32;

 TVM_CONTEXT0_PAGE_TABLE_START_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TVM_CONTEXT0_PROTECTION_FAULT_ADDR=bitpacked record
  LOGICAL_PAGE_ADDR:bit28;
  RESERVED0        :bit4;
 end;

 TVM_CONTEXT10_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT11_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT12_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT13_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT14_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT15_PAGE_TABLE_BASE_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TVM_CONTEXT1_PAGE_TABLE_START_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TVM_CONTEXT1_PROTECTION_FAULT_ADDR=bitpacked record
  LOGICAL_PAGE_ADDR:bit28;
  RESERVED0        :bit4;
 end;

 TXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR=bit32;

 TXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH=bitpacked record
  XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH:bit8;
  RESERVED0                        :bit24;
 end;

 TAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE=bitpacked record
  AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN   :bit1;
  RESERVED0                               :bit3;
  AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE:bit16;
  RESERVED1                               :bit12;
 end;

 TAZALIA_F0_AUDIO_ENABLED_INT_STATUS=bitpacked record
  AUDIO_ENABLED_FLAG:bit1;
  RESERVED0         :bit3;
  AUDIO_ENABLED_MASK:bit1;
  RESERVED1         :bit3;
  AUDIO_ENABLED_TYPE:bit1;
  RESERVED2         :bit23;
 end;

 TDC_GPU_TIMER_START_POSITION_P_FLIP=bitpacked record
  DC_GPU_TIMER_START_POSITION_D1_P_FLIP:bit3;
  RESERVED0                            :bit1;
  DC_GPU_TIMER_START_POSITION_D2_P_FLIP:bit3;
  RESERVED1                            :bit1;
  DC_GPU_TIMER_START_POSITION_D3_P_FLIP:bit3;
  RESERVED2                            :bit1;
  DC_GPU_TIMER_START_POSITION_D4_P_FLIP:bit3;
  RESERVED3                            :bit1;
  DC_GPU_TIMER_START_POSITION_D5_P_FLIP:bit3;
  RESERVED4                            :bit1;
  DC_GPU_TIMER_START_POSITION_D6_P_FLIP:bit3;
  RESERVED5                            :bit9;
 end;

 TDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1=bitpacked record
  DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN                        :bit1;
  DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN      :bit1;
  DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN                           :bit1;
  DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN                           :bit1;
  DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN                        :bit1;
  DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN                        :bit1;
  DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN      :bit1;
  DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN                           :bit1;
  DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN                           :bit1;
  DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN                        :bit1;
  DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN :bit1;
  DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN :bit1;
  DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN      :bit1;
  DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN   :bit1;
  DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN    :bit1;
  DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN:bit1;
  DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN         :bit1;
  DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN                    :bit1;
  DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN                     :bit1;
  DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN                    :bit1;
  DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN                   :bit1;
  DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN              :bit1;
  DPRX_AUX_P0_AUX_INT_TO_UC_EN                                :bit1;
  DPRX_AUX_P0_I2C_INT_TO_UC_EN                                :bit1;
  DPRX_AUX_P0_CPU_INT_TO_UC_EN                                :bit1;
  DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN                       :bit1;
  DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN                       :bit1;
  DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN                       :bit1;
  DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN                       :bit1;
  RESERVED0                                                   :bit1;
  RESERVED1                                                   :bit1;
  RESERVED2                                                   :bit1;
 end;

 TGRPH_COMPRESS_SURFACE_ADDRESS_HIGH=bitpacked record
  GRPH_COMPRESS_SURFACE_ADDRESS_HIGH:bit8;
  RESERVED0                         :bit24;
 end;

 TGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL=bitpacked record
  GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN   :bit1;
  GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE :bit1;
  RESERVED0                          :bit2;
  GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT:bit13;
  RESERVED1                          :bit15;
 end;

 TGRPH_XDMA_RECOVERY_SURFACE_ADDRESS=bitpacked record
  RESERVED0                         :bit8;
  GRPH_XDMA_RECOVERY_SURFACE_ADDRESS:bit24;
 end;

 TIMMEDIATE_COMMAND_OUTPUT_INTERFACE=bitpacked record
  IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD:bit28;
  IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS   :bit4;
 end;

 TIMMEDIATE_RESPONSE_INPUT_INTERFACE=bit32;

 TMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=bitpacked record
  PHYSICAL_PAGE_NUMBER:bit28;
  RESERVED0           :bit4;
 end;

 TOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE=bitpacked record
  FIFO_SIZE:bit16;
  RESERVED0:bit16;
 end;

 TOVL_SECONDARY_SURFACE_ADDRESS_HIGH=bitpacked record
  OVL_SECONDARY_SURFACE_ADDRESS_HIGH:bit8;
  RESERVED0                         :bit24;
 end;

 TPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0=bitpacked record
  ACCEPT_ENTRY_0 :bit1;
  ACCEPT_ENTRY_1 :bit1;
  ACCEPT_ENTRY_2 :bit1;
  ACCEPT_ENTRY_3 :bit1;
  ACCEPT_ENTRY_4 :bit1;
  ACCEPT_ENTRY_5 :bit1;
  ACCEPT_ENTRY_6 :bit1;
  ACCEPT_ENTRY_7 :bit1;
  ACCEPT_ENTRY_8 :bit1;
  ACCEPT_ENTRY_9 :bit1;
  ACCEPT_ENTRY_10:bit1;
  ACCEPT_ENTRY_11:bit1;
  ACCEPT_ENTRY_12:bit1;
  ACCEPT_ENTRY_13:bit1;
  ACCEPT_ENTRY_14:bit1;
  ACCEPT_ENTRY_15:bit1;
  ACCEPT_ENTRY_16:bit1;
  ACCEPT_ENTRY_17:bit1;
  ACCEPT_ENTRY_18:bit1;
  ACCEPT_ENTRY_19:bit1;
  ACCEPT_ENTRY_20:bit1;
  ACCEPT_ENTRY_21:bit1;
  ACCEPT_ENTRY_22:bit1;
  ACCEPT_ENTRY_23:bit1;
  ACCEPT_ENTRY_24:bit1;
  ACCEPT_ENTRY_25:bit1;
  ACCEPT_ENTRY_26:bit1;
  ACCEPT_ENTRY_27:bit1;
  ACCEPT_ENTRY_28:bit1;
  ACCEPT_ENTRY_29:bit1;
  ACCEPT_ENTRY_30:bit1;
  ACCEPT_ENTRY_31:bit1;
 end;

 TPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1=bitpacked record
  ACCEPT_ENTRY_32:bit1;
  ACCEPT_ENTRY_33:bit1;
  ACCEPT_ENTRY_34:bit1;
  ACCEPT_ENTRY_35:bit1;
  ACCEPT_ENTRY_36:bit1;
  ACCEPT_ENTRY_37:bit1;
  ACCEPT_ENTRY_38:bit1;
  ACCEPT_ENTRY_39:bit1;
  ACCEPT_ENTRY_40:bit1;
  ACCEPT_ENTRY_41:bit1;
  ACCEPT_ENTRY_42:bit1;
  ACCEPT_ENTRY_43:bit1;
  ACCEPT_ENTRY_44:bit1;
  ACCEPT_ENTRY_45:bit1;
  ACCEPT_ENTRY_46:bit1;
  ACCEPT_ENTRY_47:bit1;
  ACCEPT_ENTRY_48:bit1;
  ACCEPT_ENTRY_49:bit1;
  ACCEPT_ENTRY_50:bit1;
  ACCEPT_ENTRY_51:bit1;
  ACCEPT_ENTRY_52:bit1;
  ACCEPT_ENTRY_53:bit1;
  ACCEPT_ENTRY_54:bit1;
  ACCEPT_ENTRY_55:bit1;
  ACCEPT_ENTRY_56:bit1;
  ACCEPT_ENTRY_57:bit1;
  ACCEPT_ENTRY_58:bit1;
  ACCEPT_ENTRY_59:bit1;
  ACCEPT_ENTRY_60:bit1;
  ACCEPT_ENTRY_61:bit1;
  ACCEPT_ENTRY_62:bit1;
  ACCEPT_ENTRY_63:bit1;
 end;

 TPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2=bitpacked record
  ACCEPT_ENTRY_64:bit1;
  ACCEPT_ENTRY_65:bit1;
  ACCEPT_ENTRY_66:bit1;
  ACCEPT_ENTRY_67:bit1;
  ACCEPT_ENTRY_68:bit1;
  ACCEPT_ENTRY_69:bit1;
  ACCEPT_ENTRY_70:bit1;
  ACCEPT_ENTRY_71:bit1;
  ACCEPT_ENTRY_72:bit1;
  ACCEPT_ENTRY_73:bit1;
  ACCEPT_ENTRY_74:bit1;
  ACCEPT_ENTRY_75:bit1;
  ACCEPT_ENTRY_76:bit1;
  ACCEPT_ENTRY_77:bit1;
  ACCEPT_ENTRY_78:bit1;
  ACCEPT_ENTRY_79:bit1;
  ACCEPT_ENTRY_80:bit1;
  ACCEPT_ENTRY_81:bit1;
  ACCEPT_ENTRY_82:bit1;
  ACCEPT_ENTRY_83:bit1;
  ACCEPT_ENTRY_84:bit1;
  ACCEPT_ENTRY_85:bit1;
  ACCEPT_ENTRY_86:bit1;
  ACCEPT_ENTRY_87:bit1;
  ACCEPT_ENTRY_88:bit1;
  ACCEPT_ENTRY_89:bit1;
  ACCEPT_ENTRY_90:bit1;
  ACCEPT_ENTRY_91:bit1;
  ACCEPT_ENTRY_92:bit1;
  ACCEPT_ENTRY_93:bit1;
  ACCEPT_ENTRY_94:bit1;
  ACCEPT_ENTRY_95:bit1;
 end;

 TPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3=bitpacked record
  ACCEPT_ENTRY_96 :bit1;
  ACCEPT_ENTRY_97 :bit1;
  ACCEPT_ENTRY_98 :bit1;
  ACCEPT_ENTRY_99 :bit1;
  ACCEPT_ENTRY_100:bit1;
  ACCEPT_ENTRY_101:bit1;
  ACCEPT_ENTRY_102:bit1;
  ACCEPT_ENTRY_103:bit1;
  ACCEPT_ENTRY_104:bit1;
  ACCEPT_ENTRY_105:bit1;
  ACCEPT_ENTRY_106:bit1;
  ACCEPT_ENTRY_107:bit1;
  ACCEPT_ENTRY_108:bit1;
  ACCEPT_ENTRY_109:bit1;
  RESERVED0       :bit18;
 end;

 TPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0=bitpacked record
  ACCEPT_ENTRY_0 :bit1;
  ACCEPT_ENTRY_1 :bit1;
  ACCEPT_ENTRY_2 :bit1;
  ACCEPT_ENTRY_3 :bit1;
  ACCEPT_ENTRY_4 :bit1;
  ACCEPT_ENTRY_5 :bit1;
  ACCEPT_ENTRY_6 :bit1;
  ACCEPT_ENTRY_7 :bit1;
  ACCEPT_ENTRY_8 :bit1;
  ACCEPT_ENTRY_9 :bit1;
  ACCEPT_ENTRY_10:bit1;
  ACCEPT_ENTRY_11:bit1;
  ACCEPT_ENTRY_12:bit1;
  ACCEPT_ENTRY_13:bit1;
  ACCEPT_ENTRY_14:bit1;
  ACCEPT_ENTRY_15:bit1;
  ACCEPT_ENTRY_16:bit1;
  ACCEPT_ENTRY_17:bit1;
  ACCEPT_ENTRY_18:bit1;
  ACCEPT_ENTRY_19:bit1;
  ACCEPT_ENTRY_20:bit1;
  ACCEPT_ENTRY_21:bit1;
  ACCEPT_ENTRY_22:bit1;
  ACCEPT_ENTRY_23:bit1;
  ACCEPT_ENTRY_24:bit1;
  ACCEPT_ENTRY_25:bit1;
  ACCEPT_ENTRY_26:bit1;
  ACCEPT_ENTRY_27:bit1;
  ACCEPT_ENTRY_28:bit1;
  ACCEPT_ENTRY_29:bit1;
  ACCEPT_ENTRY_30:bit1;
  ACCEPT_ENTRY_31:bit1;
 end;

 TPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1=bitpacked record
  ACCEPT_ENTRY_32:bit1;
  ACCEPT_ENTRY_33:bit1;
  ACCEPT_ENTRY_34:bit1;
  ACCEPT_ENTRY_35:bit1;
  ACCEPT_ENTRY_36:bit1;
  ACCEPT_ENTRY_37:bit1;
  ACCEPT_ENTRY_38:bit1;
  ACCEPT_ENTRY_39:bit1;
  ACCEPT_ENTRY_40:bit1;
  ACCEPT_ENTRY_41:bit1;
  ACCEPT_ENTRY_42:bit1;
  ACCEPT_ENTRY_43:bit1;
  ACCEPT_ENTRY_44:bit1;
  ACCEPT_ENTRY_45:bit1;
  ACCEPT_ENTRY_46:bit1;
  ACCEPT_ENTRY_47:bit1;
  ACCEPT_ENTRY_48:bit1;
  ACCEPT_ENTRY_49:bit1;
  ACCEPT_ENTRY_50:bit1;
  ACCEPT_ENTRY_51:bit1;
  ACCEPT_ENTRY_52:bit1;
  ACCEPT_ENTRY_53:bit1;
  ACCEPT_ENTRY_54:bit1;
  ACCEPT_ENTRY_55:bit1;
  ACCEPT_ENTRY_56:bit1;
  ACCEPT_ENTRY_57:bit1;
  ACCEPT_ENTRY_58:bit1;
  ACCEPT_ENTRY_59:bit1;
  ACCEPT_ENTRY_60:bit1;
  ACCEPT_ENTRY_61:bit1;
  ACCEPT_ENTRY_62:bit1;
  ACCEPT_ENTRY_63:bit1;
 end;

 TPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2=bitpacked record
  ACCEPT_ENTRY_64:bit1;
  ACCEPT_ENTRY_65:bit1;
  ACCEPT_ENTRY_66:bit1;
  ACCEPT_ENTRY_67:bit1;
  ACCEPT_ENTRY_68:bit1;
  ACCEPT_ENTRY_69:bit1;
  ACCEPT_ENTRY_70:bit1;
  ACCEPT_ENTRY_71:bit1;
  ACCEPT_ENTRY_72:bit1;
  ACCEPT_ENTRY_73:bit1;
  ACCEPT_ENTRY_74:bit1;
  ACCEPT_ENTRY_75:bit1;
  ACCEPT_ENTRY_76:bit1;
  ACCEPT_ENTRY_77:bit1;
  ACCEPT_ENTRY_78:bit1;
  ACCEPT_ENTRY_79:bit1;
  ACCEPT_ENTRY_80:bit1;
  ACCEPT_ENTRY_81:bit1;
  ACCEPT_ENTRY_82:bit1;
  ACCEPT_ENTRY_83:bit1;
  ACCEPT_ENTRY_84:bit1;
  ACCEPT_ENTRY_85:bit1;
  ACCEPT_ENTRY_86:bit1;
  ACCEPT_ENTRY_87:bit1;
  ACCEPT_ENTRY_88:bit1;
  ACCEPT_ENTRY_89:bit1;
  ACCEPT_ENTRY_90:bit1;
  ACCEPT_ENTRY_91:bit1;
  ACCEPT_ENTRY_92:bit1;
  ACCEPT_ENTRY_93:bit1;
  ACCEPT_ENTRY_94:bit1;
  ACCEPT_ENTRY_95:bit1;
 end;

 TPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3=bitpacked record
  ACCEPT_ENTRY_96 :bit1;
  ACCEPT_ENTRY_97 :bit1;
  ACCEPT_ENTRY_98 :bit1;
  ACCEPT_ENTRY_99 :bit1;
  ACCEPT_ENTRY_100:bit1;
  ACCEPT_ENTRY_101:bit1;
  ACCEPT_ENTRY_102:bit1;
  ACCEPT_ENTRY_103:bit1;
  ACCEPT_ENTRY_104:bit1;
  ACCEPT_ENTRY_105:bit1;
  ACCEPT_ENTRY_106:bit1;
  ACCEPT_ENTRY_107:bit1;
  ACCEPT_ENTRY_108:bit1;
  ACCEPT_ENTRY_109:bit1;
  RESERVED0       :bit18;
 end;

 TSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2=bitpacked record
  TOKEN_TYPE:bit4;
  TIME_DELTA:bit1;
  PIPE_ID   :bit2;
  ME_ID     :bit2;
  REG_ADDR  :bit7;
  DATA_LO   :bit16;
 end;

 TSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2=bitpacked record
  DATA_HI  :bit16;
  RESERVED0:bit16;
 end;

 TTARGET_AND_CURRENT_PROFILE_INDEX_1=bitpacked record
  CURR_VDDCI_INDEX:bit4;
  TARG_VDDCI_INDEX:bit4;
  CURR_MVDD_INDEX :bit4;
  TARG_MVDD_INDEX :bit4;
  CURR_VDDC_INDEX :bit4;
  TARG_VDDC_INDEX :bit4;
  CURR_PCIE_INDEX :bit4;
  TARG_PCIE_INDEX :bit4;
 end;

 TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C=bitpacked record
  GRPH_PRIMARY_DFQ_ENABLE_C     :bit1;
  RESERVED0                     :bit7;
  GRPH_PRIMARY_SURFACE_ADDRESS_C:bit24;
 end;

 TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L=bitpacked record
  GRPH_PRIMARY_DFQ_ENABLE_L     :bit1;
  RESERVED0                     :bit7;
  GRPH_PRIMARY_SURFACE_ADDRESS_L:bit24;
 end;

 TXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH=bitpacked record
  XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH:bit8;
  RESERVED0                         :bit24;
 end;

 TAZALIA_F0_AUDIO_DISABLED_INT_STATUS=bitpacked record
  AUDIO_DISABLED_FLAG:bit1;
  RESERVED0          :bit3;
  AUDIO_DISABLED_MASK:bit1;
  RESERVED1          :bit3;
  AUDIO_DISABLED_TYPE:bit1;
  RESERVED2          :bit23;
 end;

 TAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG=bit32;

 TAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA=bit32;

 TAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL=bitpacked record
  RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW:bit6;
  RESERVED0                         :bit26;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC=bitpacked record
  VIDEO_LIPSYNC:bit8;
  AUDIO_LIPSYNC:bit8;
  RESERVED0    :bit16;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_PORTID0=bit32;

 TAZALIA_F2_CODEC_PIN_CONTROL_PORTID1=bit32;

 TFMT_TEMPORAL_DITHER_PATTERN_CONTROL=bitpacked record
  FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT   :bit1;
  RESERVED0                                         :bit3;
  FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0:bit1;
  RESERVED1                                         :bit27;
 end;

 TGRPH_SECONDARY_SURFACE_ADDRESS_HIGH=bitpacked record
  GRPH_SECONDARY_SURFACE_ADDRESS_HIGH:bit8;
  RESERVED0                          :bit24;
 end;

 TSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2=bitpacked record
  TOKEN_TYPE:bit4;
  TIME_DELTA:bit1;
  WAVE_ID   :bit4;
  SIMD_ID   :bit2;
  RESERVED0 :bit5;
  PC_LO     :bit16;
 end;

 TSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2=bitpacked record
  PC_HI    :bit24;
  RESERVED0:bit8;
 end;

 TVM_CONTEXT0_PROTECTION_FAULT_STATUS=bitpacked record
  PROTECTIONS     :bit8;
  RESERVED0       :bit4;
  MEMORY_CLIENT_ID:bit9;
  RESERVED1       :bit3;
  MEMORY_CLIENT_RW:bit1;
  VMID            :bit4;
  ATOMIC          :bit1;
  RESERVED2       :bit2;
 end;

 TVM_CONTEXT1_PROTECTION_FAULT_STATUS=bitpacked record
  PROTECTIONS     :bit8;
  RESERVED0       :bit4;
  MEMORY_CLIENT_ID:bit9;
  RESERVED1       :bit3;
  MEMORY_CLIENT_RW:bit1;
  VMID            :bit4;
  ATOMIC          :bit1;
  RESERVED2       :bit2;
 end;

 TATC_VMID_PASID_MAPPING_UPDATE_STATUS=bitpacked record
  VMID0_REMAPPING_FINISHED :bit1;
  VMID1_REMAPPING_FINISHED :bit1;
  VMID2_REMAPPING_FINISHED :bit1;
  VMID3_REMAPPING_FINISHED :bit1;
  VMID4_REMAPPING_FINISHED :bit1;
  VMID5_REMAPPING_FINISHED :bit1;
  VMID6_REMAPPING_FINISHED :bit1;
  VMID7_REMAPPING_FINISHED :bit1;
  VMID8_REMAPPING_FINISHED :bit1;
  VMID9_REMAPPING_FINISHED :bit1;
  VMID10_REMAPPING_FINISHED:bit1;
  VMID11_REMAPPING_FINISHED:bit1;
  VMID12_REMAPPING_FINISHED:bit1;
  VMID13_REMAPPING_FINISHED:bit1;
  VMID14_REMAPPING_FINISHED:bit1;
  VMID15_REMAPPING_FINISHED:bit1;
  RESERVED0                :bit16;
 end;

 TAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=bitpacked record
  AZALIA_INPUT_ENDPOINT_REG_INDEX:bit14;
  RESERVED0                      :bit18;
 end;

 TAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO=bit32;

 TAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO=bit32;

 TAZALIA_OUTPUT_STREAM_ARBITER_CONTROL=bitpacked record
  LATENCY_HIDING_LEVEL      :bit8;
  SYS_MEM_ACTIVE_ENABLE     :bit1;
  RESERVED0                 :bit7;
  INPUT_LATENCY_HIDING_LEVEL:bit8;
  RESERVED1                 :bit8;
 end;

 TBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS=bitpacked record
  REG_RWREG_RFEWDBIF_clkGate_timer :bit8;
  REG_RWREG_RFEWDBIF_clkSetup_timer:bit4;
  RESERVED0                        :bit4;
  REG_RWREG_RFEWDBIF_timeout_timer :bit8;
  RWREG_RFEWDBIF_RFE_mstTimeout    :bit1;
  RESERVED1                        :bit7;
 end;

 TDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES=bitpacked record
  ABM1_LS_MIN_PIXEL_VALUE_THRES:bit10;
  RESERVED0                    :bit6;
  ABM1_LS_MAX_PIXEL_VALUE_THRES:bit10;
  RESERVED1                    :bit5;
  ABM1_HGLS_REG_LOCK           :bit1;
 end;

 TDC_GPU_TIMER_START_POSITION_V_UPDATE=bitpacked record
  DC_GPU_TIMER_START_POSITION_D1_V_UPDATE:bit3;
  RESERVED0                              :bit1;
  DC_GPU_TIMER_START_POSITION_D2_V_UPDATE:bit3;
  RESERVED1                              :bit1;
  DC_GPU_TIMER_START_POSITION_D3_V_UPDATE:bit3;
  RESERVED2                              :bit1;
  DC_GPU_TIMER_START_POSITION_D4_V_UPDATE:bit3;
  RESERVED3                              :bit1;
  DC_GPU_TIMER_START_POSITION_D5_V_UPDATE:bit3;
  RESERVED4                              :bit1;
  DC_GPU_TIMER_START_POSITION_D6_V_UPDATE:bit3;
  RESERVED5                              :bit9;
 end;

 TGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0=bitpacked record
  STCTRL_REGISTER_SAVE_EXCL0:bit16;
  STCTRL_REGISTER_SAVE_EXCL1:bit16;
 end;

 TGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1=bitpacked record
  STCTRL_REGISTER_SAVE_EXCL2:bit16;
  STCTRL_REGISTER_SAVE_EXCL3:bit16;
 end;

 TGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS=bitpacked record
  GRPH_XDMA_CACHE_UNDERFLOW_CNT       :bit20;
  RESERVED0                           :bit4;
  GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS:bit1;
  GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK:bit1;
  GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK :bit1;
  RESERVED1                           :bit1;
  GRPH_XDMA_CACHE_UNDERFLOW_INT       :bit1;
  GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK  :bit1;
  GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK   :bit1;
  RESERVED2                           :bit1;
 end;

 TMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR=bitpacked record
  PHYSICAL_ADDRESS:bit28;
  RESERVED0       :bit4;
 end;

 TMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR=bitpacked record
  PHYSICAL_ADDRESS:bit28;
  RESERVED0       :bit4;
 end;

 TMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR=bitpacked record
  PHYSICAL_ADDRESS:bit28;
  RESERVED0       :bit4;
 end;

 TMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR=bitpacked record
  PHYSICAL_ADDRESS:bit28;
  RESERVED0       :bit4;
 end;

 TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C=bitpacked record
  GRPH_SECONDARY_DFQ_ENABLE_C     :bit1;
  RESERVED0                       :bit7;
  GRPH_SECONDARY_SURFACE_ADDRESS_C:bit24;
 end;

 TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L=bitpacked record
  GRPH_SECONDARY_DFQ_ENABLE_L     :bit1;
  RESERVED0                       :bit7;
  GRPH_SECONDARY_SURFACE_ADDRESS_L:bit24;
 end;

 TAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL=bitpacked record
  HBR_CHANNEL_COUNT       :bit3;
  RESERVED0               :bit1;
  COMPRESSED_CHANNEL_COUNT:bit3;
  RESERVED1               :bit25;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR=bitpacked record
  HBR_CAPABLE:bit1;
  RESERVED0  :bit3;
  HBR_ENABLE :bit1;
  RESERVED1  :bit27;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1=bitpacked record
  DCI_PERFMON_COUNTER0_INT_TO_UC_EN    :bit1;
  DCI_PERFMON_COUNTER1_INT_TO_UC_EN    :bit1;
  DCI_PERFMON_COUNTER2_INT_TO_UC_EN    :bit1;
  DCI_PERFMON_COUNTER3_INT_TO_UC_EN    :bit1;
  DCI_PERFMON_COUNTER4_INT_TO_UC_EN    :bit1;
  DCI_PERFMON_COUNTER5_INT_TO_UC_EN    :bit1;
  DCI_PERFMON_COUNTER6_INT_TO_UC_EN    :bit1;
  DCI_PERFMON_COUNTER7_INT_TO_UC_EN    :bit1;
  DCO_PERFMON_COUNTER0_INT_TO_UC_EN    :bit1;
  DCO_PERFMON_COUNTER1_INT_TO_UC_EN    :bit1;
  DCO_PERFMON_COUNTER2_INT_TO_UC_EN    :bit1;
  DCO_PERFMON_COUNTER3_INT_TO_UC_EN    :bit1;
  DCO_PERFMON_COUNTER4_INT_TO_UC_EN    :bit1;
  DCO_PERFMON_COUNTER5_INT_TO_UC_EN    :bit1;
  DCO_PERFMON_COUNTER6_INT_TO_UC_EN    :bit1;
  DCO_PERFMON_COUNTER7_INT_TO_UC_EN    :bit1;
  DCCG_PERFMON_COUNTER0_INT_TO_UC_EN   :bit1;
  DCCG_PERFMON_COUNTER1_INT_TO_UC_EN   :bit1;
  DCCG_PERFMON_COUNTER2_INT_TO_UC_EN   :bit1;
  DCCG_PERFMON_COUNTER3_INT_TO_UC_EN   :bit1;
  DCCG_PERFMON_COUNTER4_INT_TO_UC_EN   :bit1;
  DCCG_PERFMON_COUNTER5_INT_TO_UC_EN   :bit1;
  DCCG_PERFMON_COUNTER6_INT_TO_UC_EN   :bit1;
  DCCG_PERFMON_COUNTER7_INT_TO_UC_EN   :bit1;
  DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN :bit1;
  DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN :bit1;
  DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1;
  RESERVED0                            :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2=bitpacked record
  DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN   :bit1;
  DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN   :bit1;
  DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN   :bit1;
  DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN   :bit1;
  DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN   :bit1;
  DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN   :bit1;
  DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN   :bit1;
  DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN   :bit1;
  DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN   :bit1;
  DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN   :bit1;
  DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN   :bit1;
  DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN   :bit1;
  DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN   :bit1;
  DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN   :bit1;
  DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN   :bit1;
  DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN   :bit1;
  DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN   :bit1;
  DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN   :bit1;
  DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN   :bit1;
  DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN   :bit1;
  DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN   :bit1;
  DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN   :bit1;
  DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN   :bit1;
  DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN   :bit1;
  DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1;
  DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1;
  DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1;
  RESERVED0                             :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3=bitpacked record
  DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN   :bit1;
  DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN   :bit1;
  DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN   :bit1;
  DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN   :bit1;
  DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN   :bit1;
  DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN   :bit1;
  DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN   :bit1;
  DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN   :bit1;
  DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN   :bit1;
  DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN   :bit1;
  DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN   :bit1;
  DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN   :bit1;
  DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN   :bit1;
  DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN   :bit1;
  DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN   :bit1;
  DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN   :bit1;
  DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN   :bit1;
  DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN   :bit1;
  DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN   :bit1;
  DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN   :bit1;
  DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN   :bit1;
  DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN   :bit1;
  DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN   :bit1;
  DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN   :bit1;
  DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1;
  DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1;
  DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1;
  RESERVED0                             :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4=bitpacked record
  WB_PERFMON_COUNTER0_INT_TO_UC_EN     :bit1;
  WB_PERFMON_COUNTER1_INT_TO_UC_EN     :bit1;
  WB_PERFMON_COUNTER2_INT_TO_UC_EN     :bit1;
  WB_PERFMON_COUNTER3_INT_TO_UC_EN     :bit1;
  WB_PERFMON_COUNTER4_INT_TO_UC_EN     :bit1;
  WB_PERFMON_COUNTER5_INT_TO_UC_EN     :bit1;
  WB_PERFMON_COUNTER6_INT_TO_UC_EN     :bit1;
  WB_PERFMON_COUNTER7_INT_TO_UC_EN     :bit1;
  DCRX_PERFMON_COUNTER0_INT_TO_UC_EN   :bit1;
  DCRX_PERFMON_COUNTER1_INT_TO_UC_EN   :bit1;
  DCRX_PERFMON_COUNTER2_INT_TO_UC_EN   :bit1;
  DCRX_PERFMON_COUNTER3_INT_TO_UC_EN   :bit1;
  DCRX_PERFMON_COUNTER4_INT_TO_UC_EN   :bit1;
  DCRX_PERFMON_COUNTER5_INT_TO_UC_EN   :bit1;
  DCRX_PERFMON_COUNTER6_INT_TO_UC_EN   :bit1;
  DCRX_PERFMON_COUNTER7_INT_TO_UC_EN   :bit1;
  RESERVED0                            :bit8;
  WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN  :bit1;
  DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1;
  RESERVED1                            :bit6;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5=bitpacked record
  DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN   :bit1;
  DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN   :bit1;
  DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN   :bit1;
  DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN   :bit1;
  DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN   :bit1;
  DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN   :bit1;
  DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN   :bit1;
  DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN   :bit1;
  DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1;
  RESERVED0                             :bit23;
 end;

 TMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR=bitpacked record
  PHYSICAL_ADDRESS:bit28;
  RESERVED0       :bit4;
 end;

 TMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR=bitpacked record
  PHYSICAL_ADDRESS:bit28;
  RESERVED0       :bit4;
 end;

 TMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR=bitpacked record
  PHYSICAL_ADDRESS:bit28;
  RESERVED0       :bit4;
 end;

 TMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR=bitpacked record
  PHYSICAL_ADDRESS:bit28;
  RESERVED0       :bit4;
 end;

 TSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2=bitpacked record
  TOKEN_TYPE:bit4;
  RESERVED0 :bit12;
  TIME_LO   :bit16;
 end;

 TSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2=bit32;

 TUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C=bitpacked record
  GRPH_SURFACE_ADDRESS_HIGH_INUSE_C:bit8;
  RESERVED0                        :bit24;
 end;

 TUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L=bitpacked record
  GRPH_SURFACE_ADDRESS_HIGH_INUSE_L:bit8;
  RESERVED0                        :bit24;
 end;

 TUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=bitpacked record
  WAIT_INCOMPLETE_EN   :bit1;
  WAIT_INCOMPLETE_COUNT:bit20;
  RESERVED0            :bit3;
  RESEND_TIMER         :bit3;
  RESERVED1            :bit5;
 end;

 TVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE=bitpacked record
  VERTEX_STRIDE:bit9;
  RESERVED0    :bit23;
 end;

 TVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT=bit32;

 TVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT=bit32;

 TAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET=bitpacked record
  CODEC_RESET:bit1;
  RESERVED0  :bit31;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB=bit32;

 TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0=bitpacked record
  MANUFACTURER_ID:bit16;
  PRODUCT_ID     :bit16;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1=bitpacked record
  SINK_DESCRIPTION_LEN:bit8;
  RESERVED0           :bit24;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2=bit32;

 TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3=bit32;

 TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4=bitpacked record
  DESCRIPTION0:bit8;
  DESCRIPTION1:bit8;
  DESCRIPTION2:bit8;
  DESCRIPTION3:bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5=bitpacked record
  DESCRIPTION4:bit8;
  DESCRIPTION5:bit8;
  DESCRIPTION6:bit8;
  DESCRIPTION7:bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6=bitpacked record
  DESCRIPTION8 :bit8;
  DESCRIPTION9 :bit8;
  DESCRIPTION10:bit8;
  DESCRIPTION11:bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7=bitpacked record
  DESCRIPTION12:bit8;
  DESCRIPTION13:bit8;
  DESCRIPTION14:bit8;
  DESCRIPTION15:bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8=bitpacked record
  DESCRIPTION16:bit8;
  DESCRIPTION17:bit8;
  RESERVED0    :bit16;
 end;

 TAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET=bitpacked record
  CODEC_RESET:bit1;
  RESERVED0  :bit31;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB=bit32;

 TAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID=bitpacked record
  PRODUCT_ID:bit16;
  RESERVED0 :bit16;
 end;

 TCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL=bitpacked record
  CRTC_EXT_TIMING_SYNC_INT_ENABLE:bit1;
  RESERVED0                      :bit3;
  CRTC_EXT_TIMING_SYNC_STATUS    :bit1;
  RESERVED1                      :bit3;
  CRTC_EXT_TIMING_SYNC_INT_STATUS:bit1;
  RESERVED2                      :bit7;
  CRTC_EXT_TIMING_SYNC_CLEAR     :bit1;
  RESERVED3                      :bit3;
  CRTC_EXT_TIMING_SYNC_INT_TYPE  :bit1;
  RESERVED4                      :bit11;
 end;

 TMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR=bitpacked record
  LOGICAL_PAGE_ADDR:bit28;
  RESERVED0        :bit4;
 end;

 TVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=bitpacked record
  PHYSICAL_PAGE_OFFSET:bit28;
  RESERVED0           :bit4;
 end;

 TXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH=bitpacked record
  XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH:bit8;
  RESERVED0                             :bit24;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE=bitpacked record
  CODING_TYPE:bit8;
  RESERVED0  :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE=bitpacked record
  CODING_TYPE:bit8;
  RESERVED0  :bit24;
 end;

 TCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY=bitpacked record
  INPUT_PORT_CONNECTIVITY                :bit3;
  RESERVED0                              :bit1;
  INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE:bit1;
  RESERVED1                              :bit27;
 end;

 TDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1=bitpacked record
  DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL                        :bit1;
  DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL      :bit1;
  DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL                           :bit1;
  DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL                           :bit1;
  DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL                        :bit1;
  DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL                        :bit1;
  DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL      :bit1;
  DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL                           :bit1;
  DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL                           :bit1;
  DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL                        :bit1;
  DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL :bit1;
  DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL :bit1;
  DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL      :bit1;
  DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL   :bit1;
  DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL    :bit1;
  DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL:bit1;
  DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL         :bit1;
  DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL                    :bit1;
  DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL                     :bit1;
  DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL                    :bit1;
  DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL                   :bit1;
  DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL              :bit1;
  DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL                                :bit1;
  DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL                                :bit1;
  DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL                                :bit1;
  DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL                       :bit1;
  DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL                       :bit1;
  DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL                       :bit1;
  DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL                       :bit1;
  RESERVED0                                                       :bit1;
  RESERVED1                                                       :bit1;
  RESERVED2                                                       :bit1;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1=bitpacked record
  DCI_PERFMON_COUNTER0_INT_MASK    :bit1;
  DCI_PERFMON_COUNTER1_INT_MASK    :bit1;
  DCI_PERFMON_COUNTER2_INT_MASK    :bit1;
  DCI_PERFMON_COUNTER3_INT_MASK    :bit1;
  DCI_PERFMON_COUNTER4_INT_MASK    :bit1;
  DCI_PERFMON_COUNTER5_INT_MASK    :bit1;
  DCI_PERFMON_COUNTER6_INT_MASK    :bit1;
  DCI_PERFMON_COUNTER7_INT_MASK    :bit1;
  DCO_PERFMON_COUNTER0_INT_MASK    :bit1;
  DCO_PERFMON_COUNTER1_INT_MASK    :bit1;
  DCO_PERFMON_COUNTER2_INT_MASK    :bit1;
  DCO_PERFMON_COUNTER3_INT_MASK    :bit1;
  DCO_PERFMON_COUNTER4_INT_MASK    :bit1;
  DCO_PERFMON_COUNTER5_INT_MASK    :bit1;
  DCO_PERFMON_COUNTER6_INT_MASK    :bit1;
  DCO_PERFMON_COUNTER7_INT_MASK    :bit1;
  DCCG_PERFMON_COUNTER0_INT_MASK   :bit1;
  DCCG_PERFMON_COUNTER1_INT_MASK   :bit1;
  DCCG_PERFMON_COUNTER2_INT_MASK   :bit1;
  DCCG_PERFMON_COUNTER3_INT_MASK   :bit1;
  DCCG_PERFMON_COUNTER4_INT_MASK   :bit1;
  DCCG_PERFMON_COUNTER5_INT_MASK   :bit1;
  DCCG_PERFMON_COUNTER6_INT_MASK   :bit1;
  DCCG_PERFMON_COUNTER7_INT_MASK   :bit1;
  DCI_PERFMON_COUNTER_OFF_INT_MASK :bit1;
  DCO_PERFMON_COUNTER_OFF_INT_MASK :bit1;
  DCCG_PERFMON_COUNTER_OFF_INT_MASK:bit1;
  RESERVED0                        :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2=bitpacked record
  DCFE0_PERFMON_COUNTER0_INT_MASK   :bit1;
  DCFE0_PERFMON_COUNTER1_INT_MASK   :bit1;
  DCFE0_PERFMON_COUNTER2_INT_MASK   :bit1;
  DCFE0_PERFMON_COUNTER3_INT_MASK   :bit1;
  DCFE0_PERFMON_COUNTER4_INT_MASK   :bit1;
  DCFE0_PERFMON_COUNTER5_INT_MASK   :bit1;
  DCFE0_PERFMON_COUNTER6_INT_MASK   :bit1;
  DCFE0_PERFMON_COUNTER7_INT_MASK   :bit1;
  DCFE1_PERFMON_COUNTER0_INT_MASK   :bit1;
  DCFE1_PERFMON_COUNTER1_INT_MASK   :bit1;
  DCFE1_PERFMON_COUNTER2_INT_MASK   :bit1;
  DCFE1_PERFMON_COUNTER3_INT_MASK   :bit1;
  DCFE1_PERFMON_COUNTER4_INT_MASK   :bit1;
  DCFE1_PERFMON_COUNTER5_INT_MASK   :bit1;
  DCFE1_PERFMON_COUNTER6_INT_MASK   :bit1;
  DCFE1_PERFMON_COUNTER7_INT_MASK   :bit1;
  DCFE2_PERFMON_COUNTER0_INT_MASK   :bit1;
  DCFE2_PERFMON_COUNTER1_INT_MASK   :bit1;
  DCFE2_PERFMON_COUNTER2_INT_MASK   :bit1;
  DCFE2_PERFMON_COUNTER3_INT_MASK   :bit1;
  DCFE2_PERFMON_COUNTER4_INT_MASK   :bit1;
  DCFE2_PERFMON_COUNTER5_INT_MASK   :bit1;
  DCFE2_PERFMON_COUNTER6_INT_MASK   :bit1;
  DCFE2_PERFMON_COUNTER7_INT_MASK   :bit1;
  DCFE0_PERFMON_COUNTER_OFF_INT_MASK:bit1;
  DCFE1_PERFMON_COUNTER_OFF_INT_MASK:bit1;
  DCFE2_PERFMON_COUNTER_OFF_INT_MASK:bit1;
  RESERVED0                         :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3=bitpacked record
  DCFE3_PERFMON_COUNTER0_INT_MASK   :bit1;
  DCFE3_PERFMON_COUNTER1_INT_MASK   :bit1;
  DCFE3_PERFMON_COUNTER2_INT_MASK   :bit1;
  DCFE3_PERFMON_COUNTER3_INT_MASK   :bit1;
  DCFE3_PERFMON_COUNTER4_INT_MASK   :bit1;
  DCFE3_PERFMON_COUNTER5_INT_MASK   :bit1;
  DCFE3_PERFMON_COUNTER6_INT_MASK   :bit1;
  DCFE3_PERFMON_COUNTER7_INT_MASK   :bit1;
  DCFE4_PERFMON_COUNTER0_INT_MASK   :bit1;
  DCFE4_PERFMON_COUNTER1_INT_MASK   :bit1;
  DCFE4_PERFMON_COUNTER2_INT_MASK   :bit1;
  DCFE4_PERFMON_COUNTER3_INT_MASK   :bit1;
  DCFE4_PERFMON_COUNTER4_INT_MASK   :bit1;
  DCFE4_PERFMON_COUNTER5_INT_MASK   :bit1;
  DCFE4_PERFMON_COUNTER6_INT_MASK   :bit1;
  DCFE4_PERFMON_COUNTER7_INT_MASK   :bit1;
  DCFE5_PERFMON_COUNTER0_INT_MASK   :bit1;
  DCFE5_PERFMON_COUNTER1_INT_MASK   :bit1;
  DCFE5_PERFMON_COUNTER2_INT_MASK   :bit1;
  DCFE5_PERFMON_COUNTER3_INT_MASK   :bit1;
  DCFE5_PERFMON_COUNTER4_INT_MASK   :bit1;
  DCFE5_PERFMON_COUNTER5_INT_MASK   :bit1;
  DCFE5_PERFMON_COUNTER6_INT_MASK   :bit1;
  DCFE5_PERFMON_COUNTER7_INT_MASK   :bit1;
  DCFE3_PERFMON_COUNTER_OFF_INT_MASK:bit1;
  DCFE4_PERFMON_COUNTER_OFF_INT_MASK:bit1;
  DCFE5_PERFMON_COUNTER_OFF_INT_MASK:bit1;
  RESERVED0                         :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4=bitpacked record
  WB_PERFMON_COUNTER0_INT_MASK     :bit1;
  WB_PERFMON_COUNTER1_INT_MASK     :bit1;
  WB_PERFMON_COUNTER2_INT_MASK     :bit1;
  WB_PERFMON_COUNTER3_INT_MASK     :bit1;
  WB_PERFMON_COUNTER4_INT_MASK     :bit1;
  WB_PERFMON_COUNTER5_INT_MASK     :bit1;
  WB_PERFMON_COUNTER6_INT_MASK     :bit1;
  WB_PERFMON_COUNTER7_INT_MASK     :bit1;
  DCRX_PERFMON_COUNTER0_INT_MASK   :bit1;
  DCRX_PERFMON_COUNTER1_INT_MASK   :bit1;
  DCRX_PERFMON_COUNTER2_INT_MASK   :bit1;
  DCRX_PERFMON_COUNTER3_INT_MASK   :bit1;
  DCRX_PERFMON_COUNTER4_INT_MASK   :bit1;
  DCRX_PERFMON_COUNTER5_INT_MASK   :bit1;
  DCRX_PERFMON_COUNTER6_INT_MASK   :bit1;
  DCRX_PERFMON_COUNTER7_INT_MASK   :bit1;
  RESERVED0                        :bit8;
  WB_PERFMON_COUNTER_OFF_INT_MASK  :bit1;
  DCRX_PERFMON_COUNTER_OFF_INT_MASK:bit1;
  RESERVED1                        :bit6;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5=bitpacked record
  DCFEV_PERFMON_COUNTER0_INT_MASK   :bit1;
  DCFEV_PERFMON_COUNTER1_INT_MASK   :bit1;
  DCFEV_PERFMON_COUNTER2_INT_MASK   :bit1;
  DCFEV_PERFMON_COUNTER3_INT_MASK   :bit1;
  DCFEV_PERFMON_COUNTER4_INT_MASK   :bit1;
  DCFEV_PERFMON_COUNTER5_INT_MASK   :bit1;
  DCFEV_PERFMON_COUNTER6_INT_MASK   :bit1;
  DCFEV_PERFMON_COUNTER7_INT_MASK   :bit1;
  DCFEV_PERFMON_COUNTER_OFF_INT_MASK:bit1;
  RESERVED0                         :bit23;
 end;

 TGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH=bitpacked record
  GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH:bit8;
  RESERVED0                              :bit24;
 end;

 TIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA=bit32;

 TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C=bitpacked record
  GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C:bit8;
  RESERVED0                          :bit24;
 end;

 TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L=bitpacked record
  GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L:bit8;
  RESERVED0                          :bit24;
 end;

 TUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=bitpacked record
  SIGNAL_INCOMPLETE_EN   :bit1;
  SIGNAL_INCOMPLETE_COUNT:bit20;
  RESERVED0              :bit3;
  RESEND_TIMER           :bit3;
  RESERVED1              :bit5;
 end;

 TAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL=bitpacked record
  STRIPE_CONTROL   :bit2;
  RESERVED0        :bit18;
  STRIPE_CAPABILITY:bit3;
  RESERVED1        :bit9;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR=bitpacked record
  HBR_CAPABLE:bit1;
  RESERVED0  :bit3;
  HBR_ENABLE :bit1;
  RESERVED1  :bit27;
 end;

 TAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL=bitpacked record
  STRIPE_CONTROL   :bit2;
  RESERVED0        :bit18;
  STRIPE_CAPABILITY:bit3;
  RESERVED1        :bit9;
 end;

 TBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD=bit32;

 TIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX=bitpacked record
  IMMEDIATE_COMMAND_WRITE:bit16;
  RESERVED0              :bit16;
 end;

 TMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS=bitpacked record
  PROTECTIONS     :bit8;
  RESERVED0       :bit4;
  MEMORY_CLIENT_ID:bit9;
  RESERVED1       :bit3;
  MEMORY_CLIENT_RW:bit1;
  VMID            :bit4;
  ATOMIC          :bit1;
  RESERVED2       :bit2;
 end;

 TPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV=bitpacked record
  CAP_ID  :bit16;
  CAP_VER :bit4;
  NEXT_PTR:bit12;
 end;

 TAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS=bitpacked record
  AUDIO_FORMAT_CHANGED_FLAG:bit1;
  RESERVED0                :bit3;
  AUDIO_FORMAT_CHANGED_MASK:bit1;
  RESERVED1                :bit3;
  AUDIO_FORMAT_CHANGED_TYPE:bit1;
  RESERVED2                :bit23;
 end;

 TAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG=bit32;

 TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0=bitpacked record
  IEC_60958_CS_MODE         :bit2;
  IEC_60958_CS_SOURCE_NUMBER:bit4;
  RESERVED0                 :bit26;
 end;

 TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1=bitpacked record
  IEC_60958_CS_CLOCK_ACCURACY         :bit2;
  IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN:bit1;
  IEC_60958_CS_WORD_LENGTH            :bit4;
  IEC_60958_CS_WORD_LENGTH_OVRRD_EN   :bit1;
  RESERVED0                           :bit24;
 end;

 TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2=bitpacked record
  IEC_60958_CS_SAMPLING_FREQUENCY         :bit6;
  IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN:bit1;
  RESERVED0                               :bit25;
 end;

 TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3=bitpacked record
  IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY         :bit4;
  IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN:bit1;
  RESERVED0                                        :bit27;
 end;

 TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4=bitpacked record
  IEC_60958_CS_SAMPLING_FREQUENCY_COEFF:bit4;
  IEC_60958_CS_MPEG_SURROUND_INFO      :bit1;
  IEC_60958_CS_CGMS_A                  :bit2;
  IEC_60958_CS_CGMS_A_VALID            :bit1;
  RESERVED0                            :bit24;
 end;

 TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5=bitpacked record
  IEC_60958_CS_CHANNEL_NUMBER_L:bit4;
  IEC_60958_CS_CHANNEL_NUMBER_R:bit4;
  RESERVED0                    :bit24;
 end;

 TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6=bitpacked record
  IEC_60958_CS_CHANNEL_NUMBER_2:bit4;
  IEC_60958_CS_CHANNEL_NUMBER_3:bit4;
  RESERVED0                    :bit24;
 end;

 TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7=bitpacked record
  IEC_60958_CS_CHANNEL_NUMBER_4:bit4;
  IEC_60958_CS_CHANNEL_NUMBER_5:bit4;
  RESERVED0                    :bit24;
 end;

 TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8=bitpacked record
  IEC_60958_CS_CHANNEL_NUMBER_6:bit4;
  IEC_60958_CS_CHANNEL_NUMBER_7:bit4;
  RESERVED0                    :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO=bitpacked record
  LFE_PLAYBACK_LEVEL:bit2;
  RESERVED0         :bit1;
  LEVEL_SHIFT       :bit4;
  DOWN_MIX_INHIBIT  :bit1;
  RESERVED1         :bit24;
 end;

 TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0=bitpacked record
  IEC_60958_CS_MODE         :bit2;
  IEC_60958_CS_SOURCE_NUMBER:bit4;
  RESERVED0                 :bit26;
 end;

 TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1=bitpacked record
  IEC_60958_CS_CLOCK_ACCURACY         :bit2;
  IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN:bit1;
  IEC_60958_CS_WORD_LENGTH            :bit4;
  IEC_60958_CS_WORD_LENGTH_OVRRD_EN   :bit1;
  RESERVED0                           :bit24;
 end;

 TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2=bitpacked record
  IEC_60958_CS_SAMPLING_FREQUENCY         :bit6;
  IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN:bit1;
  RESERVED0                               :bit25;
 end;

 TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3=bitpacked record
  IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY         :bit4;
  IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN:bit1;
  RESERVED0                                        :bit27;
 end;

 TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4=bitpacked record
  IEC_60958_CS_SAMPLING_FREQUENCY_COEFF:bit4;
  IEC_60958_CS_MPEG_SURROUND_INFO      :bit1;
  IEC_60958_CS_CGMS_A                  :bit2;
  IEC_60958_CS_CGMS_A_VALID            :bit1;
  RESERVED0                            :bit24;
 end;

 TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5=bitpacked record
  IEC_60958_CS_CHANNEL_NUMBER_L:bit4;
  IEC_60958_CS_CHANNEL_NUMBER_R:bit4;
  RESERVED0                    :bit24;
 end;

 TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6=bitpacked record
  IEC_60958_CS_CHANNEL_NUMBER_2:bit4;
  IEC_60958_CS_CHANNEL_NUMBER_3:bit4;
  RESERVED0                    :bit24;
 end;

 TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7=bitpacked record
  IEC_60958_CS_CHANNEL_NUMBER_4:bit4;
  IEC_60958_CS_CHANNEL_NUMBER_5:bit4;
  RESERVED0                    :bit24;
 end;

 TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8=bitpacked record
  IEC_60958_CS_CHANNEL_NUMBER_6:bit4;
  IEC_60958_CS_CHANNEL_NUMBER_7:bit4;
  RESERVED0                    :bit24;
 end;

 TOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX=bitpacked record
  LAST_VALID_INDEX:bit8;
  RESERVED0       :bit24;
 end;

 TSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2=bitpacked record
  TOKEN_TYPE:bit4;
  TIME_DELTA:bit1;
  SH_ID     :bit1;
  CU_ID     :bit4;
  WAVE_ID   :bit4;
  SIMD_ID   :bit2;
  DATA_LO   :bit16;
 end;

 TSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2=bitpacked record
  DATA_HI  :bit16;
  RESERVED0:bit16;
 end;

 TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C=bitpacked record
  GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C     :bit1;
  RESERVED0                            :bit7;
  GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C:bit24;
 end;

 TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L=bitpacked record
  GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L     :bit1;
  RESERVED0                            :bit7;
  GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L:bit24;
 end;

 TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C=bitpacked record
  GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C:bit8;
  RESERVED0                            :bit24;
 end;

 TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L=bitpacked record
  GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L:bit8;
  RESERVED0                            :bit24;
 end;

 TVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=bitpacked record
  PHYSICAL_PAGE_ADDR:bit28;
  RESERVED0         :bit4;
 end;

 TVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=bitpacked record
  PHYSICAL_PAGE_ADDR:bit28;
  RESERVED0         :bit4;
 end;

 TVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED=bitpacked record
  FORMAT_CHANGED              :bit1;
  FORMAT_CHANGED_ACK_UR_ENABLE:bit1;
  RESERVED0                   :bit6;
  FORMAT_CHANGE_REASON        :bit8;
  FORMAT_CHANGE_RESPONSE      :bit8;
  RESERVED1                   :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL=bitpacked record
  RESERVED0 :bit6;
  OUT_ENABLE:bit1;
  RESERVED1 :bit25;
 end;

 TAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES=bitpacked record
  IMPEDANCE_SENSE_CAPABLE  :bit1;
  TRIGGER_REQUIRED         :bit1;
  JACK_DETECTION_CAPABILITY:bit1;
  HEADPHONE_DRIVE_CAPABLE  :bit1;
  OUTPUT_CAPABLE           :bit1;
  INPUT_CAPABLE            :bit1;
  BALANCED_I_O_PINS        :bit1;
  HDMI                     :bit1;
  VREF_CONTROL             :bit8;
  EAPD_CAPABLE             :bit1;
  RESERVED0                :bit7;
  DP                       :bit1;
  RESERVED1                :bit7;
 end;

 TAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID=bit32;

 TAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED=bitpacked record
  FORMAT_CHANGED              :bit1;
  FORMAT_CHANGED_ACK_UR_ENABLE:bit1;
  RESERVED0                   :bit6;
  FORMAT_CHANGE_REASON        :bit8;
  FORMAT_CHANGE_RESPONSE      :bit8;
  RESERVED1                   :bit8;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL=bitpacked record
  RESERVED0 :bit6;
  OUT_ENABLE:bit1;
  RESERVED1 :bit25;
 end;

 TAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES=bitpacked record
  IMPEDANCE_SENSE_CAPABLE  :bit1;
  TRIGGER_REQUIRED         :bit1;
  JACK_DETECTION_CAPABILITY:bit1;
  HEADPHONE_DRIVE_CAPABLE  :bit1;
  OUTPUT_CAPABLE           :bit1;
  INPUT_CAPABLE            :bit1;
  BALANCED_I_O_PINS        :bit1;
  HDMI                     :bit1;
  VREF_CONTROL             :bit8;
  EAPD_CAPABLE             :bit1;
  RESERVED0                :bit7;
  DP                       :bit1;
  RESERVED1                :bit7;
 end;

 TAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID=bit32;

 TDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1=bitpacked record
  DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL    :bit1;
  DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL    :bit1;
  DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL    :bit1;
  DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL    :bit1;
  DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL    :bit1;
  DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL    :bit1;
  DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL    :bit1;
  DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL    :bit1;
  DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL    :bit1;
  DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL    :bit1;
  DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL    :bit1;
  DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL    :bit1;
  DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL    :bit1;
  DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL    :bit1;
  DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL    :bit1;
  DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL    :bit1;
  DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL   :bit1;
  DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL   :bit1;
  DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL   :bit1;
  DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL   :bit1;
  DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL   :bit1;
  DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL   :bit1;
  DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL   :bit1;
  DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL   :bit1;
  DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL :bit1;
  DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL :bit1;
  DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1;
  RESERVED0                                :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2=bitpacked record
  DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1;
  DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1;
  DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1;
  RESERVED0                                 :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3=bitpacked record
  DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL   :bit1;
  DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1;
  DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1;
  DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1;
  RESERVED0                                 :bit5;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4=bitpacked record
  WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL     :bit1;
  WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL     :bit1;
  WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL     :bit1;
  WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL     :bit1;
  WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL     :bit1;
  WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL     :bit1;
  WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL     :bit1;
  WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL     :bit1;
  DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL   :bit1;
  DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL   :bit1;
  DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL   :bit1;
  DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL   :bit1;
  DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL   :bit1;
  DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL   :bit1;
  DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL   :bit1;
  DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL   :bit1;
  RESERVED0                                :bit8;
  WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL  :bit1;
  DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1;
  RESERVED1                                :bit6;
 end;

 TDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5=bitpacked record
  DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL   :bit1;
  DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL   :bit1;
  DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL   :bit1;
  DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL   :bit1;
  DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL   :bit1;
  DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL   :bit1;
  DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL   :bit1;
  DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL   :bit1;
  DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1;
  RESERVED0                                 :bit23;
 end;

 TPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET=bit32;

 TVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE=bit32;

 TVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=bitpacked record
  LOGICAL_PAGE_NUMBER:bit28;
  RESERVED0          :bit4;
 end;

 TAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE=bitpacked record
  RAMP_RATE:bit8;
  RESERVED0:bit24;
 end;

 TAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA=bit32;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME=bitpacked record
  CHANNEL_COUNT     :bit3;
  RESERVED0         :bit5;
  CHANNEL_ALLOCATION:bit8;
  INFOFRAME_BYTE_5  :bit8;
  RESERVED1         :bit7;
  INFOFRAME_VALID   :bit1;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER=bitpacked record
  SPEAKER_ALLOCATION   :bit7;
  RESERVED0            :bit1;
  CHANNEL_ALLOCATION   :bit8;
  HDMI_CONNECTION      :bit1;
  DP_CONNECTION        :bit1;
  EXTRA_CONNECTION_INFO:bit6;
  LFE_PLAYBACK_LEVEL   :bit2;
  RESERVED1            :bit1;
  LEVEL_SHIFT          :bit4;
  DOWN_MIX_INHIBIT     :bit1;
 end;

 TAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE=bitpacked record
  RAMP_RATE:bit8;
  RESERVED0:bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME=bitpacked record
  CHANNEL_COUNT     :bit3;
  RESERVED0         :bit5;
  CHANNEL_ALLOCATION:bit8;
  INFOFRAME_BYTE_5  :bit8;
  RESERVED1         :bit7;
  INFOFRAME_VALID   :bit1;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID=bitpacked record
  MANUFACTURER_ID:bit16;
  RESERVED0      :bit16;
 end;

 TCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL=bitpacked record
  CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE :bit1;
  RESERVED0                            :bit3;
  CRTC_EXT_TIMING_SYNC_LOSS_STATUS     :bit1;
  RESERVED1                            :bit3;
  CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS :bit1;
  RESERVED2                            :bit7;
  CRTC_EXT_TIMING_SYNC_LOSS_CLEAR      :bit1;
  RESERVED3                            :bit3;
  CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE   :bit1;
  RESERVED4                            :bit8;
  CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT:bit3;
 end;

 TOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS=bitpacked record
  STREAM_RESET                      :bit1;
  STREAM_RUN                        :bit1;
  INTERRUPT_ON_COMPLETION_ENABLE    :bit1;
  FIFO_ERROR_INTERRUPT_ENABLE       :bit1;
  DESCRIPTOR_ERROR_INTERRUPT_ENABLE :bit1;
  RESERVED0                         :bit11;
  STRIPE_CONTROL                    :bit2;
  TRAFFIC_PRIORITY                  :bit1;
  RESERVED1                         :bit1;
  STREAM_NUMBER                     :bit4;
  RESERVED2                         :bit2;
  BUFFER_COMPLETION_INTERRUPT_STATUS:bit1;
  FIFO_ERROR                        :bit1;
  DESCRIPTOR_ERROR                  :bit1;
  FIFO_READY                        :bit1;
  RESERVED3                         :bit2;
 end;

 TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C=bitpacked record
  GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C     :bit1;
  RESERVED0                              :bit7;
  GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C:bit24;
 end;

 TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L=bitpacked record
  GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L     :bit1;
  RESERVED0                              :bit7;
  GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L:bit24;
 end;

 TAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER=bit32;

 TAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE=bitpacked record
  POWER_STATE_SET           :bit4;
  POWER_STATE_ACT           :bit4;
  RESERVED0                 :bit1;
  CLKSTOPOK                 :bit1;
  POWER_STATE_SETTINGS_RESET:bit1;
  RESERVED1                 :bit21;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL=bitpacked record
  CLOCK_GATING_DISABLE:bit1;
  RESERVED0           :bit3;
  CLOCK_ON_STATE      :bit1;
  RESERVED1           :bit26;
  AUDIO_ENABLED       :bit1;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE=bitpacked record
  REMOTE_KEEP_ALIVE_ENABLE    :bit1;
  RESERVED0                   :bit3;
  REMOTE_KEEP_ALIVE_CAPABILITY:bit1;
  RESERVED1                   :bit27;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC=bitpacked record
  VIDEO_LIPSYNC:bit8;
  AUDIO_LIPSYNC:bit8;
  RESERVED0    :bit16;
 end;

 TAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE=bitpacked record
  POWER_STATE_SET           :bit4;
  POWER_STATE_ACT           :bit4;
  RESERVED0                 :bit1;
  CLKSTOPOK                 :bit1;
  POWER_STATE_SETTINGS_RESET:bit1;
  RESERVED1                 :bit21;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR=bitpacked record
  MAX_CHANNELS                :bit3;
  FORMAT_CODE                 :bit4;
  RESERVED0                   :bit1;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE=bitpacked record
  REMOTE_KEEP_ALIVE_ENABLE    :bit1;
  RESERVED0                   :bit3;
  REMOTE_KEEP_ALIVE_CAPABILITY:bit1;
  RESERVED1                   :bit27;
 end;

 TAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE=bit32;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0=bitpacked record
  MAX_CHANNELS                :bit3;
  RESERVED0                   :bit5;
  SUPPORTED_FREQUENCIES       :bit8;
  DESCRIPTOR_BYTE_2           :bit8;
  SUPPORTED_FREQUENCIES_STEREO:bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE=bitpacked record
  MULTICHANNEL_MODE:bit1;
  RESERVED0        :bit31;
 end;

 TAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE=bit32;

 TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE=bitpacked record
  MULTICHANNEL_MODE:bit1;
  RESERVED0        :bit31;
 end;

 TCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL=bitpacked record
  CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE:bit1;
  RESERVED0                             :bit3;
  CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS    :bit1;
  RESERVED1                             :bit3;
  CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS:bit1;
  RESERVED2                             :bit7;
  CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR     :bit1;
  RESERVED3                             :bit3;
  CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE  :bit1;
  RESERVED4                             :bit11;
 end;

 TOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH=bit32;

 TPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL=bitpacked record
  SOFT_PF_FLR:bit1;
  RESERVED0  :bit31;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR=bitpacked record
  HBR_CAPABLE:bit1;
  RESERVED0  :bit3;
  HBR_ENABLE :bit1;
  RESERVED1  :bit27;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13=bitpacked record
  MAX_CHANNELS         :bit3;
  RESERVED0            :bit5;
  SUPPORTED_FREQUENCIES:bit8;
  DESCRIPTOR_BYTE_2    :bit8;
  RESERVED1            :bit8;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE=bitpacked record
  IMPEDANCE_SENSE:bit31;
  RESERVED0      :bit1;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION=bitpacked record
  CHANNEL_ALLOCATION:bit8;
  RESERVED0         :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE=bitpacked record
  IMPEDANCE_SENSE:bit31;
  PRESENCE_DETECT:bit1;
 end;

 TAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA=bit32;

 TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C=bitpacked record
  GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C:bit8;
  RESERVED0                                 :bit24;
 end;

 TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L=bitpacked record
  GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L:bit8;
  RESERVED0                                 :bit24;
 end;

 TAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING=bitpacked record
  PRESENTATION_TIME_EMBEDDING_ENABLE:bit1;
  PRESENTATION_TIME_OFFSET_CHANGED  :bit1;
  CLEAR_GTC_COUNTER_MIN_MAX_DELTA   :bit1;
  RESERVED0                         :bit1;
  PRESENTATION_TIME_EMBEDDING_GROUP :bit3;
  RESERVED1                         :bit25;
 end;

 TAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX=bit32;

 TAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN=bit32;

 TAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES=bitpacked record
  AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES:bit30;
  CLKSTOP                                     :bit1;
  EPSS                                        :bit1;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT=bit32;

 TAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE=bitpacked record
  MULTICHANNEL01_ENABLE    :bit1;
  MULTICHANNEL01_MUTE      :bit1;
  RESERVED0                :bit2;
  MULTICHANNEL01_CHANNEL_ID:bit4;
  MULTICHANNEL23_ENABLE    :bit1;
  MULTICHANNEL23_MUTE      :bit1;
  RESERVED1                :bit2;
  MULTICHANNEL23_CHANNEL_ID:bit4;
  MULTICHANNEL45_ENABLE    :bit1;
  MULTICHANNEL45_MUTE      :bit1;
  RESERVED2                :bit2;
  MULTICHANNEL45_CHANNEL_ID:bit4;
  MULTICHANNEL67_ENABLE    :bit1;
  MULTICHANNEL67_MUTE      :bit1;
  RESERVED3                :bit2;
  MULTICHANNEL67_CHANNEL_ID:bit4;
 end;

 TAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING=bitpacked record
  PRESENTATION_TIME_EMBEDDING_ENABLE:bit1;
  PRESENTATION_TIME_OFFSET_CHANGED  :bit1;
  RESERVED0                         :bit2;
  PRESENTATION_TIME_EMBEDDING_GROUP :bit3;
  RESERVED1                         :bit25;
 end;

 TAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES=bitpacked record
  AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES:bit30;
  CLKSTOP                                     :bit1;
  EPSS                                        :bit1;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT=bit32;

 TAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX=bitpacked record
  IMMEDIATE_COMMAND_WRITE:bit17;
  RESERVED0              :bit15;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL=bitpacked record
  RESERVED0:bit5;
  IN_ENABLE:bit1;
  RESERVED1:bit26;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES=bitpacked record
  IMPEDANCE_SENSE_CAPABLE  :bit1;
  TRIGGER_REQUIRED         :bit1;
  JACK_DETECTION_CAPABILITY:bit1;
  HEADPHONE_DRIVE_CAPABLE  :bit1;
  OUTPUT_CAPABLE           :bit1;
  INPUT_CAPABLE            :bit1;
  BALANCED_I_O_PINS        :bit1;
  HDMI                     :bit1;
  VREF_CONTROL             :bit8;
  EAPD_CAPABLE             :bit1;
  RESERVED0                :bit7;
  DP                       :bit1;
  RESERVED1                :bit7;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2=bitpacked record
  MULTICHANNEL1_ENABLE    :bit1;
  MULTICHANNEL1_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL1_CHANNEL_ID:bit4;
  MULTICHANNEL3_ENABLE    :bit1;
  MULTICHANNEL3_MUTE      :bit1;
  RESERVED1               :bit2;
  MULTICHANNEL3_CHANNEL_ID:bit4;
  MULTICHANNEL5_ENABLE    :bit1;
  MULTICHANNEL5_MUTE      :bit1;
  RESERVED2               :bit2;
  MULTICHANNEL5_CHANNEL_ID:bit4;
  MULTICHANNEL7_ENABLE    :bit1;
  MULTICHANNEL7_MUTE      :bit1;
  RESERVED3               :bit2;
  MULTICHANNEL7_CHANNEL_ID:bit4;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE=bitpacked record
  TAG      :bit6;
  RESERVED0:bit1;
  ENABLE   :bit1;
  RESERVED1:bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL=bitpacked record
  RESERVED0:bit5;
  IN_ENABLE:bit1;
  RESERVED1:bit26;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES=bitpacked record
  IMPEDANCE_SENSE_CAPABLE  :bit1;
  TRIGGER_REQUIRED         :bit1;
  JACK_DETECTION_CAPABILITY:bit1;
  HEADPHONE_DRIVE_CAPABLE  :bit1;
  OUTPUT_CAPABLE           :bit1;
  INPUT_CAPABLE            :bit1;
  BALANCED_I_O_PINS        :bit1;
  HDMI                     :bit1;
  VREF_CONTROL             :bit8;
  EAPD_CAPABLE             :bit1;
  RESERVED0                :bit7;
  DP                       :bit1;
  RESERVED1                :bit7;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA=bit32;

 TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE=bitpacked record
  MULTICHANNEL1_ENABLE    :bit1;
  MULTICHANNEL1_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL1_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE=bitpacked record
  MULTICHANNEL3_ENABLE    :bit1;
  MULTICHANNEL3_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL3_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE=bitpacked record
  MULTICHANNEL5_ENABLE    :bit1;
  MULTICHANNEL5_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL5_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE=bitpacked record
  MULTICHANNEL7_ENABLE    :bit1;
  MULTICHANNEL7_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL7_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN=bitpacked record
  SINK_DESCRIPTION_LEN:bit8;
  RESERVED0           :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE=bitpacked record
  TAG      :bit6;
  RESERVED0:bit1;
  ENABLE   :bit1;
  RESERVED1:bit24;
 end;

 TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C=bitpacked record
  GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C:bit8;
  RESERVED0                                   :bit24;
 end;

 TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L=bitpacked record
  GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L:bit8;
  RESERVED0                                   :bit24;
 end;

 TAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS=bit32;

 TAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS=bitpacked record
  OUTPUT_ACTIVE:bit1;
  RESERVED0    :bit31;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL=bitpacked record
  LPIB_SNAPSHOT_LOCK      :bit1;
  RESERVED0               :bit7;
  CYCLIC_BUFFER_WRAP_COUNT:bit8;
  RESERVED1               :bit16;
 end;

 TAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS=bit32;

 TAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA=bit32;

 TAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX=bitpacked record
  SINK_INFO_INDEX:bit8;
  RESERVED0      :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS=bitpacked record
  OUTPUT_ACTIVE:bit1;
  RESERVED0    :bit31;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL=bitpacked record
  LPIB_SNAPSHOT_LOCK      :bit1;
  RESERVED0               :bit7;
  CYCLIC_BUFFER_WRAP_COUNT:bit8;
  RESERVED1               :bit16;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE=bitpacked record
  MULTICHANNEL01_ENABLE    :bit1;
  MULTICHANNEL01_MUTE      :bit1;
  RESERVED0                :bit2;
  MULTICHANNEL01_CHANNEL_ID:bit4;
  RESERVED1                :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE=bitpacked record
  MULTICHANNEL23_ENABLE    :bit1;
  MULTICHANNEL23_MUTE      :bit1;
  RESERVED0                :bit2;
  MULTICHANNEL23_CHANNEL_ID:bit4;
  RESERVED1                :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE=bitpacked record
  MULTICHANNEL45_ENABLE    :bit1;
  MULTICHANNEL45_MUTE      :bit1;
  RESERVED0                :bit2;
  MULTICHANNEL45_CHANNEL_ID:bit4;
  RESERVED1                :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE=bitpacked record
  MULTICHANNEL67_ENABLE    :bit1;
  MULTICHANNEL67_MUTE      :bit1;
  RESERVED0                :bit2;
  MULTICHANNEL67_CHANNEL_ID:bit4;
  RESERVED1                :bit24;
 end;

 TAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA=bit32;

 TFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX=bit32;

 TFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX=bit32;

 TAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT=bitpacked record
  NUMBER_OF_CHANNELS  :bit4;
  BITS_PER_SAMPLE     :bit3;
  RESERVED0           :bit1;
  SAMPLE_BASE_DIVISOR :bit3;
  SAMPLE_BASE_MULTIPLE:bit3;
  SAMPLE_BASE_RATE    :bit1;
  STREAM_TYPE         :bit1;
  RESERVED1           :bit16;
 end;

 TAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG=bit32;

 TAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS=bit32;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL=bitpacked record
  CLOCK_GATING_DISABLE:bit1;
  RESERVED0           :bit3;
  CLOCK_ON_STATE      :bit1;
  RESERVED1           :bit26;
  AUDIO_ENABLED       :bit1;
 end;

 TAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT=bitpacked record
  NUMBER_OF_CHANNELS  :bit4;
  BITS_PER_SAMPLE     :bit3;
  RESERVED0           :bit1;
  SAMPLE_BASE_DIVISOR :bit3;
  SAMPLE_BASE_MULTIPLE:bit3;
  SAMPLE_BASE_RATE    :bit1;
  STREAM_TYPE         :bit1;
  RESERVED1           :bit16;
 end;

 TAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS=bit32;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H=bit32;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L=bit32;

 TAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX=bitpacked record
  IMMEDIATE_COMMAND_WRITE:bit17;
  RESERVED0              :bit15;
 end;

 TAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA=bit32;

 TAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID=bitpacked record
  CHANNEL_ID:bit4;
  STREAM_ID :bit4;
  RESERVED0 :bit24;
 end;

 TAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER=bitpacked record
  DIGEN    :bit1;
  V        :bit1;
  VCFG     :bit1;
  PRE      :bit1;
  COPY     :bit1;
  NON_AUDIO:bit1;
  PRO      :bit1;
  L        :bit1;
  CC       :bit7;
  RESERVED0:bit8;
  KEEPALIVE:bit1;
  RESERVED1:bit8;
 end;

 TAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID=bit32;

 TAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID=bitpacked record
  CHANNEL_ID:bit4;
  STREAM_ID :bit4;
  RESERVED0 :bit24;
 end;

 TAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER=bitpacked record
  DIGEN    :bit1;
  V        :bit1;
  VCFG     :bit1;
  PRE      :bit1;
  COPY     :bit1;
  NON_AUDIO:bit1;
  PRO      :bit1;
  L        :bit1;
  CC       :bit7;
  RESERVED0:bit8;
  KEEPALIVE:bit1;
  RESERVED1:bit8;
 end;

 TAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID=bit32;

 TAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX=bitpacked record
  IMMEDIATE_COMMAND_WRITE:bit17;
  RESERVED0              :bit15;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION=bitpacked record
  CHANNEL_ALLOCATION:bit8;
  RESERVED0         :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION=bitpacked record
  CHANNEL_ALLOCATION:bit8;
  RESERVED0         :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE=bitpacked record
  IMPEDANCE_SENSE:bit31;
  PRESENCE_DETECT:bit1;
 end;

 TAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH=bit32;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT=bit32;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE=bitpacked record
  MULTICHANNEL0_ENABLE    :bit1;
  MULTICHANNEL0_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL0_CHANNEL_ID:bit4;
  MULTICHANNEL1_ENABLE    :bit1;
  MULTICHANNEL1_MUTE      :bit1;
  RESERVED1               :bit2;
  MULTICHANNEL1_CHANNEL_ID:bit4;
  MULTICHANNEL2_ENABLE    :bit1;
  MULTICHANNEL2_MUTE      :bit1;
  RESERVED2               :bit2;
  MULTICHANNEL2_CHANNEL_ID:bit4;
  MULTICHANNEL3_ENABLE    :bit1;
  MULTICHANNEL3_MUTE      :bit1;
  RESERVED3               :bit2;
  MULTICHANNEL3_CHANNEL_ID:bit4;
 end;

 TAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2=bitpacked record
  CC       :bit7;
  RESERVED0:bit25;
 end;

 TAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3=bitpacked record
  RESERVED0:bit7;
  KEEPALIVE:bit1;
  RESERVED1:bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT=bit32;

 TAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT=bit32;

 TAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID=bitpacked record
  SUBSYSTEM_ID_BYTE0:bit8;
  SUBSYSTEM_ID_BYTE1:bit8;
  SUBSYSTEM_ID_BYTE2:bit8;
  SUBSYSTEM_ID_BYTE3:bit8;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL=bitpacked record
  INPUT_ACTIVITY                        :bit1;
  CHANNEL_LAYOUT                        :bit2;
  RESERVED0                             :bit1;
  INPUT_ACTIVITY_UR_ENABLE              :bit1;
  INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE:bit1;
  RESERVED1                             :bit26;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2=bitpacked record
  MULTICHANNEL4_ENABLE    :bit1;
  MULTICHANNEL4_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL4_CHANNEL_ID:bit4;
  MULTICHANNEL5_ENABLE    :bit1;
  MULTICHANNEL5_MUTE      :bit1;
  RESERVED1               :bit2;
  MULTICHANNEL5_CHANNEL_ID:bit4;
  MULTICHANNEL6_ENABLE    :bit1;
  MULTICHANNEL6_MUTE      :bit1;
  RESERVED2               :bit2;
  MULTICHANNEL6_CHANNEL_ID:bit4;
  MULTICHANNEL7_ENABLE    :bit1;
  MULTICHANNEL7_MUTE      :bit1;
  RESERVED3               :bit2;
  MULTICHANNEL7_CHANNEL_ID:bit4;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE=bitpacked record
  TAG      :bit6;
  RESERVED0:bit1;
  ENABLE   :bit1;
  RESERVED1:bit24;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE=bitpacked record
  UNSOLICITED_RESPONSE_PAYLOAD:bit26;
  RESERVED0                   :bit2;
  UNSOLICITED_RESPONSE_FORCE  :bit1;
  RESERVED1                   :bit3;
 end;

 TAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID=bitpacked record
  SUBSYSTEM_ID_BYTE0:bit8;
  SUBSYSTEM_ID_BYTE1:bit8;
  SUBSYSTEM_ID_BYTE2:bit8;
  SUBSYSTEM_ID_BYTE3:bit8;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL=bitpacked record
  INPUT_ACTIVITY                        :bit1;
  CHANNEL_LAYOUT                        :bit2;
  RESERVED0                             :bit1;
  INPUT_ACTIVITY_UR_ENABLE              :bit1;
  INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE:bit1;
  RESERVED1                             :bit26;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE=bitpacked record
  MULTICHANNEL0_ENABLE    :bit1;
  MULTICHANNEL0_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL0_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE=bitpacked record
  MULTICHANNEL1_ENABLE    :bit1;
  MULTICHANNEL1_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL1_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE=bitpacked record
  MULTICHANNEL2_ENABLE    :bit1;
  MULTICHANNEL2_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL2_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE=bitpacked record
  MULTICHANNEL3_ENABLE    :bit1;
  MULTICHANNEL3_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL3_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE=bitpacked record
  MULTICHANNEL4_ENABLE    :bit1;
  MULTICHANNEL4_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL4_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE=bitpacked record
  MULTICHANNEL5_ENABLE    :bit1;
  MULTICHANNEL5_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL5_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE=bitpacked record
  MULTICHANNEL6_ENABLE    :bit1;
  MULTICHANNEL6_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL6_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE=bitpacked record
  MULTICHANNEL7_ENABLE    :bit1;
  MULTICHANNEL7_MUTE      :bit1;
  RESERVED0               :bit2;
  MULTICHANNEL7_CHANNEL_ID:bit4;
  RESERVED1               :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE=bitpacked record
  TAG      :bit6;
  RESERVED0:bit1;
  ENABLE   :bit1;
  RESERVED1:bit24;
 end;

 TAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record
  AUDIO_RATE_CAPABILITIES:bit12;
  RESERVED0              :bit4;
  AUDIO_BIT_CAPABILITIES :bit5;
  RESERVED1              :bit11;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL=bitpacked record
  LPIB_SNAPSHOT_LOCK      :bit1;
  RESERVED0               :bit7;
  CYCLIC_BUFFER_WRAP_COUNT:bit8;
  RESERVED1               :bit16;
 end;

 TAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record
  AUDIO_CHANNEL_CAPABILITIES     :bit1;
  INPUT_AMPLIFIER_PRESENT        :bit1;
  OUTPUT_AMPLIFIER_PRESENT       :bit1;
  AMPLIFIER_PARAMETER_OVERRIDE   :bit1;
  RESERVED0                      :bit1;
  STRIPE                         :bit1;
  PROCESSING_WIDGET              :bit1;
  UNSOLICITED_RESPONSE_CAPABILITY:bit1;
  CONNECTION_LIST                :bit1;
  DIGITAL                        :bit1;
  POWER_CONTROL                  :bit1;
  LR_SWAP                        :bit1;
  RESERVED1                      :bit4;
  AUDIO_WIDGET_CAPABILITIES_DELAY:bit4;
  _TYPE                          :bit4;
  RESERVED2                      :bit8;
 end;

 TAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record
  AUDIO_RATE_CAPABILITIES:bit12;
  RESERVED0              :bit4;
  AUDIO_BIT_CAPABILITIES :bit5;
  RESERVED1              :bit11;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL=bitpacked record
  LPIB_SNAPSHOT_LOCK      :bit1;
  RESERVED0               :bit7;
  CYCLIC_BUFFER_WRAP_COUNT:bit8;
  RESERVED1               :bit16;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION=bitpacked record
  SPEAKER_ALLOCATION   :bit7;
  RESERVED0            :bit1;
  HDMI_CONNECTION      :bit1;
  DP_CONNECTION        :bit1;
  EXTRA_CONNECTION_INFO:bit6;
  RESERVED1            :bit16;
 end;

 TAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record
  AUDIO_CHANNEL_CAPABILITIES     :bit1;
  INPUT_AMPLIFIER_PRESENT        :bit1;
  OUTPUT_AMPLIFIER_PRESENT       :bit1;
  AMPLIFIER_PARAMETER_OVERRIDE   :bit1;
  RESERVED0                      :bit1;
  STRIPE                         :bit1;
  PROCESSING_WIDGET              :bit1;
  UNSOLICITED_RESPONSE_CAPABILITY:bit1;
  CONNECTION_LIST                :bit1;
  DIGITAL                        :bit1;
  POWER_CONTROL                  :bit1;
  LR_SWAP                        :bit1;
  RESERVED1                      :bit4;
  AUDIO_WIDGET_CAPABILITIES_DELAY:bit4;
  _TYPE                          :bit4;
  RESERVED2                      :bit8;
 end;

 TOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS=bitpacked record
  BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS:bit7;
  BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS                   :bit25;
 end;

 TOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS=bit32;

 TAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record
  AUDIO_RATE_CAPABILITIES:bit12;
  RESERVED0              :bit4;
  AUDIO_BIT_CAPABILITIES :bit5;
  RESERVED1              :bit11;
 end;

 TAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT=bitpacked record
  NUMBER_OF_CHANNELS  :bit4;
  BITS_PER_SAMPLE     :bit3;
  RESERVED0           :bit1;
  SAMPLE_BASE_DIVISOR :bit3;
  SAMPLE_BASE_MULTIPLE:bit3;
  SAMPLE_BASE_RATE    :bit1;
  STREAM_TYPE         :bit1;
  RESERVED1           :bit16;
 end;

 TAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS=bit32;

 TAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record
  AUDIO_RATE_CAPABILITIES:bit12;
  RESERVED0              :bit4;
  AUDIO_BIT_CAPABILITIES :bit5;
  RESERVED1              :bit11;
 end;

 TAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2=bitpacked record
  SUBSYSTEM_ID_BYTE1:bit8;
  RESERVED0         :bit24;
 end;

 TAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3=bitpacked record
  SUBSYSTEM_ID_BYTE2:bit8;
  RESERVED0         :bit24;
 end;

 TAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4=bitpacked record
  SUBSYSTEM_ID_BYTE3:bit8;
  RESERVED0         :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT=bitpacked record
  NUMBER_OF_CHANNELS  :bit4;
  BITS_PER_SAMPLE     :bit3;
  RESERVED0           :bit1;
  SAMPLE_BASE_DIVISOR :bit3;
  SAMPLE_BASE_MULTIPLE:bit3;
  SAMPLE_BASE_RATE    :bit1;
  STREAM_TYPE         :bit1;
  RESERVED1           :bit16;
 end;

 TAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS=bit32;

 TOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER=bit32;

 TAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID=bitpacked record
  CHANNEL_ID:bit4;
  STREAM_ID :bit4;
  RESERVED0 :bit24;
 end;

 TAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER=bitpacked record
  DIGEN    :bit1;
  V        :bit1;
  VCFG     :bit1;
  PRE      :bit1;
  COPY     :bit1;
  NON_AUDIO:bit1;
  PRO      :bit1;
  L        :bit1;
  CC       :bit7;
  RESERVED0:bit8;
  KEEPALIVE:bit1;
  RESERVED1:bit8;
 end;

 TAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT=bit32;

 TAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID=bitpacked record
  CHANNEL_ID:bit4;
  STREAM_ID :bit4;
  RESERVED0 :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER=bitpacked record
  DIGEN    :bit1;
  V        :bit1;
  VCFG     :bit1;
  PRE      :bit1;
  COPY     :bit1;
  NON_AUDIO:bit1;
  PRO      :bit1;
  L        :bit1;
  CC       :bit7;
  RESERVED0:bit8;
  KEEPALIVE:bit1;
  RESERVED1:bit8;
 end;

 TAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION=bitpacked record
  CONVERTER_SYNCHRONIZATION:bit7;
  RESERVED0                :bit25;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE=bitpacked record
  IMPEDANCE_SENSE:bit31;
  PRESENCE_DETECT:bit1;
 end;

 TAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT=bitpacked record
  SEQUENCE           :bit4;
  DEFAULT_ASSOCIATION:bit4;
  MISC               :bit4;
  COLOR              :bit4;
  CONNECTION_TYPE    :bit4;
  DEFAULT_DEVICE     :bit4;
  LOCATION           :bit6;
  PORT_CONNECTIVITY  :bit2;
 end;

 TAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION=bitpacked record
  CONVERTER_SYNCHRONIZATION:bit7;
  RESERVED0                :bit25;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT=bitpacked record
  SEQUENCE           :bit4;
  DEFAULT_ASSOCIATION:bit4;
  MISC               :bit4;
  COLOR              :bit4;
  CONNECTION_TYPE    :bit4;
  DEFAULT_DEVICE     :bit4;
  LOCATION           :bit6;
  PORT_CONNECTIVITY  :bit2;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY=bit32;

 TAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION=bitpacked record
  WIRELESS_DISPLAY_IDENTIFICATION:bit2;
  RESERVED0                      :bit30;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION=bitpacked record
  WIRELESS_DISPLAY_IDENTIFICATION:bit2;
  RESERVED0                      :bit30;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE=bitpacked record
  UNSOLICITED_RESPONSE_PAYLOAD:bit26;
  RESERVED0                   :bit2;
  UNSOLICITED_RESPONSE_FORCE  :bit1;
  RESERVED1                   :bit3;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2=bitpacked record
  MISC     :bit4;
  COLOR    :bit4;
  RESERVED0:bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3=bitpacked record
  CONNECTION_TYPE:bit4;
  DEFAULT_DEVICE :bit4;
  RESERVED0      :bit24;
 end;

 TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4=bitpacked record
  LOCATION         :bit6;
  PORT_CONNECTIVITY:bit2;
  RESERVED0        :bit24;
 end;

 TAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record
  AUDIO_CHANNEL_CAPABILITIES     :bit1;
  INPUT_AMPLIFIER_PRESENT        :bit1;
  OUTPUT_AMPLIFIER_PRESENT       :bit1;
  AMPLIFIER_PARAMETER_OVERRIDE   :bit1;
  FORMAT_OVERRIDE                :bit1;
  STRIPE                         :bit1;
  PROCESSING_WIDGET              :bit1;
  UNSOLICITED_RESPONSE_CAPABILITY:bit1;
  CONNECTION_LIST                :bit1;
  DIGITAL                        :bit1;
  POWER_CONTROL                  :bit1;
  LR_SWAP                        :bit1;
  RESERVED0                      :bit4;
  AUDIO_WIDGET_CAPABILITIES_DELAY:bit4;
  _TYPE                          :bit4;
  RESERVED1                      :bit8;
 end;

 TAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record
  AUDIO_CHANNEL_CAPABILITIES     :bit1;
  INPUT_AMPLIFIER_PRESENT        :bit1;
  OUTPUT_AMPLIFIER_PRESENT       :bit1;
  AMPLIFIER_PARAMETER_OVERRIDE   :bit1;
  RESERVED0                      :bit1;
  STRIPE                         :bit1;
  PROCESSING_WIDGET              :bit1;
  UNSOLICITED_RESPONSE_CAPABILITY:bit1;
  CONNECTION_LIST                :bit1;
  DIGITAL                        :bit1;
  POWER_CONTROL                  :bit1;
  LR_SWAP                        :bit1;
  RESERVED1                      :bit4;
  AUDIO_WIDGET_CAPABILITIES_DELAY:bit4;
  _TYPE                          :bit4;
  RESERVED2                      :bit8;
 end;

 TAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record
  AUDIO_CHANNEL_CAPABILITIES     :bit1;
  INPUT_AMPLIFIER_PRESENT        :bit1;
  OUTPUT_AMPLIFIER_PRESENT       :bit1;
  AMPLIFIER_PARAMETER_OVERRIDE   :bit1;
  FORMAT_OVERRIDE                :bit1;
  STRIPE                         :bit1;
  PROCESSING_WIDGET              :bit1;
  UNSOLICITED_RESPONSE_CAPABILITY:bit1;
  CONNECTION_LIST                :bit1;
  DIGITAL                        :bit1;
  POWER_CONTROL                  :bit1;
  LR_SWAP                        :bit1;
  RESERVED0                      :bit4;
  AUDIO_WIDGET_CAPABILITIES_DELAY:bit4;
  _TYPE                          :bit4;
  RESERVED1                      :bit8;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record
  AUDIO_CHANNEL_CAPABILITIES     :bit1;
  INPUT_AMPLIFIER_PRESENT        :bit1;
  OUTPUT_AMPLIFIER_PRESENT       :bit1;
  AMPLIFIER_PARAMETER_OVERRIDE   :bit1;
  RESERVED0                      :bit1;
  STRIPE                         :bit1;
  PROCESSING_WIDGET              :bit1;
  UNSOLICITED_RESPONSE_CAPABILITY:bit1;
  CONNECTION_LIST                :bit1;
  DIGITAL                        :bit1;
  POWER_CONTROL                  :bit1;
  LR_SWAP                        :bit1;
  RESERVED1                      :bit4;
  AUDIO_WIDGET_CAPABILITIES_DELAY:bit4;
  _TYPE                          :bit4;
  RESERVED2                      :bit8;
 end;

 TAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record
  AUDIO_RATE_CAPABILITIES:bit12;
  RESERVED0              :bit4;
  AUDIO_BIT_CAPABILITIES :bit5;
  RESERVED1              :bit11;
 end;

 TAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record
  AUDIO_RATE_CAPABILITIES:bit12;
  RESERVED0              :bit4;
  AUDIO_BIT_CAPABILITIES :bit5;
  RESERVED1              :bit11;
 end;

 TOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS=bit32;

 TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT=bitpacked record
  SEQUENCE           :bit4;
  DEFAULT_ASSOCIATION:bit4;
  MISC               :bit4;
  COLOR              :bit4;
  CONNECTION_TYPE    :bit4;
  DEFAULT_DEVICE     :bit4;
  LOCATION           :bit6;
  PORT_CONNECTIVITY  :bit2;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT=bitpacked record
  SEQUENCE           :bit4;
  DEFAULT_ASSOCIATION:bit4;
  MISC               :bit4;
  COLOR              :bit4;
  CONNECTION_TYPE    :bit4;
  DEFAULT_DEVICE     :bit4;
  LOCATION           :bit6;
  PORT_CONNECTIVITY  :bit2;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2=bitpacked record
  MISC     :bit4;
  COLOR    :bit4;
  RESERVED0:bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3=bitpacked record
  CONNECTION_TYPE:bit4;
  DEFAULT_DEVICE :bit4;
  RESERVED0      :bit24;
 end;

 TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4=bitpacked record
  LOCATION         :bit6;
  PORT_CONNECTIVITY:bit2;
  RESERVED0        :bit24;
 end;

 TAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record
  AUDIO_CHANNEL_CAPABILITIES     :bit1;
  INPUT_AMPLIFIER_PRESENT        :bit1;
  OUTPUT_AMPLIFIER_PRESENT       :bit1;
  AMPLIFIER_PARAMETER_OVERRIDE   :bit1;
  FORMAT_OVERRIDE                :bit1;
  STRIPE                         :bit1;
  PROCESSING_WIDGET              :bit1;
  UNSOLICITED_RESPONSE_CAPABILITY:bit1;
  CONNECTION_LIST                :bit1;
  DIGITAL                        :bit1;
  POWER_CONTROL                  :bit1;
  LR_SWAP                        :bit1;
  RESERVED0                      :bit4;
  AUDIO_WIDGET_CAPABILITIES_DELAY:bit4;
  _TYPE                          :bit4;
  RESERVED1                      :bit8;
 end;

 TAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record
  AUDIO_CHANNEL_CAPABILITIES     :bit1;
  INPUT_AMPLIFIER_PRESENT        :bit1;
  OUTPUT_AMPLIFIER_PRESENT       :bit1;
  AMPLIFIER_PARAMETER_OVERRIDE   :bit1;
  FORMAT_OVERRIDE                :bit1;
  STRIPE                         :bit1;
  PROCESSING_WIDGET              :bit1;
  UNSOLICITED_RESPONSE_CAPABILITY:bit1;
  CONNECTION_LIST                :bit1;
  DIGITAL                        :bit1;
  POWER_CONTROL                  :bit1;
  LR_SWAP                        :bit1;
  RESERVED0                      :bit4;
  AUDIO_WIDGET_CAPABILITIES_DELAY:bit4;
  _TYPE                          :bit4;
  RESERVED1                      :bit8;
 end;


implementation

end.

