Luke Usher
GitHub
commit
d393637a47
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@ -351,7 +351,7 @@ struct {
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uint32_t enabled_interrupts;
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std::thread puller_thread;
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Cache1State cache1;
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uint32_t regs[NV_PFIFO_SIZE]; // TODO : union
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uint32_t regs[_NV_PFIFO_SIZE]; // TODO : union
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} pfifo;
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struct {
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@ -572,12 +572,14 @@ const char *DebugNV_##DEV##(xbaddr addr) \
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DEBUG_START(PMC)
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DEBUG_CASE(NV_PMC_BOOT_0);
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DEBUG_CASE(NV_PMC_BOOT_1);
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DEBUG_CASE(NV_PMC_INTR_0);
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DEBUG_CASE(NV_PMC_INTR_EN_0);
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DEBUG_CASE(NV_PMC_ENABLE);
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DEBUG_END(PMC)
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DEBUG_START(PBUS)
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DEBUG_CASE(NV_PBUS_FBIO_RAM)
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DEBUG_CASE_EX(NV_PBUS_PCI_NV_0, ":VENDOR_ID");
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DEBUG_CASE(NV_PBUS_PCI_NV_1);
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DEBUG_CASE_EX(NV_PBUS_PCI_NV_2, ":REVISION_ID");
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@ -605,25 +607,45 @@ DEBUG_START(PBUS)
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DEBUG_END(PBUS)
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DEBUG_START(PFIFO)
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DEBUG_CASE(NV_PFIFO_DELAY_0);
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DEBUG_CASE(NV_PFIFO_DMA_TIMESLICE);
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DEBUG_CASE(NV_PFIFO_TIMESLICE);
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DEBUG_CASE(NV_PFIFO_INTR_0);
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DEBUG_CASE(NV_PFIFO_INTR_EN_0);
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DEBUG_CASE(NV_PFIFO_RAMHT);
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DEBUG_CASE(NV_PFIFO_RAMFC);
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DEBUG_CASE(NV_PFIFO_RAMRO);
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DEBUG_CASE(NV_PFIFO_RUNOUT_STATUS);
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DEBUG_CASE(NV_PFIFO_RUNOUT_PUT_ADDRESS);
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DEBUG_CASE(NV_PFIFO_RUNOUT_GET_ADDRESS);
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DEBUG_CASE(NV_PFIFO_CACHES);
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DEBUG_CASE(NV_PFIFO_MODE);
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DEBUG_CASE(NV_PFIFO_DMA);
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DEBUG_CASE(NV_PFIFO_SIZE)
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DEBUG_CASE(NV_PFIFO_CACHE0_PUSH0);
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DEBUG_CASE(NV_PFIFO_CACHE0_PULL0);
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DEBUG_CASE(NV_PFIFO_CACHE0_HASH);
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DEBUG_CASE(NV_PFIFO_CACHE1_PUSH0);
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DEBUG_CASE(NV_PFIFO_CACHE1_PUSH1);
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DEBUG_CASE(NV_PFIFO_CACHE1_PUT);
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DEBUG_CASE(NV_PFIFO_CACHE1_STATUS);
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DEBUG_CASE(NV_PFIFO_CACHE1_DMA_PUSH);
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DEBUG_CASE(NV_PFIFO_CACHE1_DMA_FETCH);
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DEBUG_CASE(NV_PFIFO_CACHE1_DMA_STATE);
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DEBUG_CASE(NV_PFIFO_CACHE1_DMA_INSTANCE);
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DEBUG_CASE(NV_PFIFO_CACHE1_DMA_CTL);
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DEBUG_CASE(NV_PFIFO_CACHE1_DMA_PUT);
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DEBUG_CASE(NV_PFIFO_CACHE1_DMA_GET);
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DEBUG_CASE(NV_PFIFO_CACHE1_REF);
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DEBUG_CASE(NV_PFIFO_CACHE1_DMA_SUBROUTINE);
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DEBUG_CASE(NV_PFIFO_CACHE1_PULL0);
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DEBUG_CASE(NV_PFIFO_CACHE1_PULL1);
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DEBUG_CASE(NV_PFIFO_CACHE1_HASH);
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DEBUG_CASE(NV_PFIFO_CACHE1_ACQUIRE_0);
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DEBUG_CASE(NV_PFIFO_CACHE1_ACQUIRE_1);
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DEBUG_CASE(NV_PFIFO_CACHE1_ACQUIRE_2);
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DEBUG_CASE(NV_PFIFO_CACHE1_SEMAPHORE);
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DEBUG_CASE(NV_PFIFO_CACHE1_GET);
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DEBUG_CASE(NV_PFIFO_CACHE1_ENGINE);
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DEBUG_CASE(NV_PFIFO_CACHE1_DMA_DCOUNT);
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DEBUG_CASE(NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW);
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@ -635,22 +657,36 @@ DEBUG_START(PRMA)
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DEBUG_END(PRMA)
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DEBUG_START(PVIDEO)
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DEBUG_CASE(NV_PVIDEO_DEBUG_2);
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DEBUG_CASE(NV_PVIDEO_DEBUG_3);
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DEBUG_CASE(NV_PVIDEO_INTR);
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DEBUG_CASE(NV_PVIDEO_INTR_EN);
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DEBUG_CASE(NV_PVIDEO_BUFFER);
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DEBUG_CASE(NV_PVIDEO_STOP);
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DEBUG_CASE(NV_PVIDEO_BASE);
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DEBUG_CASE(NV_PVIDEO_LIMIT);
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DEBUG_CASE(NV_PVIDEO_LUMINANCE);
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DEBUG_CASE(NV_PVIDEO_CHROMINANCE);
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DEBUG_CASE(NV_PVIDEO_OFFSET);
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DEBUG_CASE(NV_PVIDEO_SIZE_IN);
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DEBUG_CASE(NV_PVIDEO_POINT_IN);
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DEBUG_CASE(NV_PVIDEO_DS_DX);
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DEBUG_CASE(NV_PVIDEO_DT_DY);
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DEBUG_CASE(NV_PVIDEO_POINT_OUT);
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DEBUG_CASE(NV_PVIDEO_SIZE_OUT);
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DEBUG_CASE(NV_PVIDEO_FORMAT);
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DEBUG_CASE(NV_PVIDEO_BASE(0));
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DEBUG_CASE(NV_PVIDEO_BASE(1));
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DEBUG_CASE(NV_PVIDEO_LIMIT(0));
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DEBUG_CASE(NV_PVIDEO_LIMIT(1));
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DEBUG_CASE(NV_PVIDEO_LUMINANCE(0));
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DEBUG_CASE(NV_PVIDEO_LUMINANCE(1));
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DEBUG_CASE(NV_PVIDEO_CHROMINANCE(0));
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DEBUG_CASE(NV_PVIDEO_CHROMINANCE(1));
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DEBUG_CASE(NV_PVIDEO_OFFSET(0));
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DEBUG_CASE(NV_PVIDEO_OFFSET(1));
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DEBUG_CASE(NV_PVIDEO_SIZE_IN(0));
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DEBUG_CASE(NV_PVIDEO_SIZE_IN(1));
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DEBUG_CASE(NV_PVIDEO_POINT_IN(0));
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DEBUG_CASE(NV_PVIDEO_POINT_IN(1));
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DEBUG_CASE(NV_PVIDEO_DS_DX(0));
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DEBUG_CASE(NV_PVIDEO_DS_DX(1));
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DEBUG_CASE(NV_PVIDEO_DT_DY(0));
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DEBUG_CASE(NV_PVIDEO_DT_DY(1));
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DEBUG_CASE(NV_PVIDEO_POINT_OUT(0));
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DEBUG_CASE(NV_PVIDEO_POINT_OUT(1));
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DEBUG_CASE(NV_PVIDEO_SIZE_OUT(0));
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DEBUG_CASE(NV_PVIDEO_SIZE_OUT(1));
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DEBUG_CASE(NV_PVIDEO_FORMAT(0));
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DEBUG_CASE(NV_PVIDEO_FORMAT(1));
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DEBUG_END(PVIDEO)
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DEBUG_START(PTIMER)
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@ -661,7 +697,6 @@ DEBUG_START(PTIMER)
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DEBUG_CASE(NV_PTIMER_TIME_0);
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DEBUG_CASE(NV_PTIMER_TIME_1);
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DEBUG_CASE(NV_PTIMER_ALARM_0);
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DEBUG_END(PTIMER)
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DEBUG_START(PCOUNTER)
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@ -681,6 +716,7 @@ DEBUG_END(PRMVIO)
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DEBUG_START(PFB)
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DEBUG_CASE(NV_PFB_CFG0)
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DEBUG_CASE(NV_PFB_CFG1)
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DEBUG_CASE(NV_PFB_CSTATUS)
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DEBUG_CASE(NV_PFB_REFCTRL)
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DEBUG_CASE(NV_PFB_NVM) // NV_PFB_NVM_MODE_DISABLE
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@ -689,17 +725,53 @@ DEBUG_START(PFB)
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DEBUG_CASE(NV_PFB_TIMING0)
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DEBUG_CASE(NV_PFB_TIMING1)
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DEBUG_CASE(NV_PFB_TIMING2)
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DEBUG_CASE(NV_PFB_TILE)
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DEBUG_CASE(NV_PFB_TLIMIT)
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DEBUG_CASE(NV_PFB_TSIZE)
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DEBUG_CASE(NV_PFB_TSTATUS)
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DEBUG_CASE(NV_PFB_TILE(0))
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DEBUG_CASE(NV_PFB_TLIMIT(0))
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DEBUG_CASE(NV_PFB_TSIZE(0))
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DEBUG_CASE(NV_PFB_TSTATUS(0))
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DEBUG_CASE(NV_PFB_TILE(1))
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DEBUG_CASE(NV_PFB_TLIMIT(1))
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DEBUG_CASE(NV_PFB_TSIZE(1))
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DEBUG_CASE(NV_PFB_TSTATUS(1))
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DEBUG_CASE(NV_PFB_TILE(2))
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DEBUG_CASE(NV_PFB_TLIMIT(2))
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DEBUG_CASE(NV_PFB_TSIZE(2))
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DEBUG_CASE(NV_PFB_TSTATUS(2))
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DEBUG_CASE(NV_PFB_TILE(3))
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DEBUG_CASE(NV_PFB_TLIMIT(3))
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DEBUG_CASE(NV_PFB_TSIZE(3))
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DEBUG_CASE(NV_PFB_TSTATUS(3))
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DEBUG_CASE(NV_PFB_TILE(4))
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DEBUG_CASE(NV_PFB_TLIMIT(4))
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DEBUG_CASE(NV_PFB_TSIZE(4))
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DEBUG_CASE(NV_PFB_TSTATUS(4))
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DEBUG_CASE(NV_PFB_TILE(5))
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DEBUG_CASE(NV_PFB_TLIMIT(5))
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DEBUG_CASE(NV_PFB_TSIZE(5))
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DEBUG_CASE(NV_PFB_TSTATUS(5))
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DEBUG_CASE(NV_PFB_TILE(6))
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DEBUG_CASE(NV_PFB_TLIMIT(6))
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DEBUG_CASE(NV_PFB_TSIZE(6))
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DEBUG_CASE(NV_PFB_TSTATUS(6))
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DEBUG_CASE(NV_PFB_TILE(7))
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DEBUG_CASE(NV_PFB_TLIMIT(7))
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DEBUG_CASE(NV_PFB_TSIZE(7))
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DEBUG_CASE(NV_PFB_TSTATUS(7))
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DEBUG_CASE(NV_PFB_MRS)
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DEBUG_CASE(NV_PFB_EMRS)
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DEBUG_CASE(NV_PFB_MRS_EXT)
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DEBUG_CASE(NV_PFB_EMRS_EXT)
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DEBUG_CASE(NV_PFB_REF)
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DEBUG_CASE(NV_PFB_PRE)
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DEBUG_CASE(NV_PFB_ZCOMP)
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DEBUG_CASE(NV_PFB_ZCOMP(0))
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DEBUG_CASE(NV_PFB_ZCOMP(1))
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DEBUG_CASE(NV_PFB_ZCOMP(2))
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DEBUG_CASE(NV_PFB_ZCOMP(3))
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DEBUG_CASE(NV_PFB_ZCOMP(4))
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DEBUG_CASE(NV_PFB_ZCOMP(5))
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DEBUG_CASE(NV_PFB_ZCOMP(6))
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DEBUG_CASE(NV_PFB_ZCOMP(7))
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DEBUG_CASE(NV_PFB_ZCOMP_OFFSET)
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DEBUG_CASE(NV_PFB_ARB_PREDIVIDER)
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DEBUG_CASE(NV_PFB_ARB_TIMEOUT)
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DEBUG_CASE(NV_PFB_ARB_XFER_REM)
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@ -723,20 +795,81 @@ DEBUG_START(PSTRAPS)
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DEBUG_END(PSTRAPS)
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DEBUG_START(PGRAPH)
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DEBUG_CASE(NV_PGRAPH_DEBUG_0);
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DEBUG_CASE(NV_PGRAPH_DEBUG_1);
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DEBUG_CASE(NV_PGRAPH_DEBUG_3);
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DEBUG_CASE(NV_PGRAPH_DEBUG_4);
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DEBUG_CASE(NV_PGRAPH_DEBUG_5);
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DEBUG_CASE(NV_PGRAPH_DEBUG_8);
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DEBUG_CASE(NV_PGRAPH_DEBUG_9);
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DEBUG_CASE(NV_PGRAPH_INTR);
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DEBUG_CASE(NV_PGRAPH_NSOURCE);
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DEBUG_CASE(NV_PGRAPH_INTR_EN);
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DEBUG_CASE(NV_PGRAPH_CTX_CONTROL);
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DEBUG_CASE(NV_PGRAPH_CTX_USER);
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DEBUG_CASE(NV_PGRAPH_CTX_SWITCH1);
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DEBUG_CASE(NV_PGRAPH_CTX_SWITCH2);
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DEBUG_CASE(NV_PGRAPH_CTX_SWITCH3);
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DEBUG_CASE(NV_PGRAPH_CTX_SWITCH4);
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DEBUG_CASE(NV_PGRAPH_STATUS);
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DEBUG_CASE(NV_PGRAPH_TRAPPED_ADDR);
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DEBUG_CASE(NV_PGRAPH_TRAPPED_DATA_LOW);
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DEBUG_CASE(NV_PGRAPH_SURFACE);
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DEBUG_CASE(NV_PGRAPH_INCREMENT);
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DEBUG_CASE(NV_PGRAPH_FIFO);
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DEBUG_CASE(NV_PGRAPH_RDI_INDEX);
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DEBUG_CASE(NV_PGRAPH_RDI_DATA);
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DEBUG_CASE(NV_PGRAPH_FFINTFC_ST2);
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DEBUG_CASE(NV_PGRAPH_CHANNEL_CTX_TABLE);
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DEBUG_CASE(NV_PGRAPH_CHANNEL_CTX_POINTER);
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DEBUG_CASE(NV_PGRAPH_CHANNEL_CTX_TRIGGER);
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DEBUG_CASE(NV_PGRAPH_DEBUG_2);
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DEBUG_CASE(NV_PGRAPH_TTILE(0));
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DEBUG_CASE(NV_PGRAPH_TLIMIT(0));
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DEBUG_CASE(NV_PGRAPH_TSIZE(0));
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DEBUG_CASE(NV_PGRAPH_TSTATUS(0));
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DEBUG_CASE(NV_PGRAPH_TTILE(1));
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DEBUG_CASE(NV_PGRAPH_TLIMIT(1));
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DEBUG_CASE(NV_PGRAPH_TSIZE(1));
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DEBUG_CASE(NV_PGRAPH_TSTATUS(1));
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DEBUG_CASE(NV_PGRAPH_TTILE(2));
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DEBUG_CASE(NV_PGRAPH_TLIMIT(2));
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DEBUG_CASE(NV_PGRAPH_TSIZE(2));
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DEBUG_CASE(NV_PGRAPH_TSTATUS(2));
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DEBUG_CASE(NV_PGRAPH_TTILE(3));
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DEBUG_CASE(NV_PGRAPH_TLIMIT(3));
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DEBUG_CASE(NV_PGRAPH_TSIZE(3));
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DEBUG_CASE(NV_PGRAPH_TSTATUS(3));
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DEBUG_CASE(NV_PGRAPH_TTILE(4));
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DEBUG_CASE(NV_PGRAPH_TLIMIT(4));
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DEBUG_CASE(NV_PGRAPH_TSIZE(4));
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DEBUG_CASE(NV_PGRAPH_TSTATUS(4));
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DEBUG_CASE(NV_PGRAPH_TTILE(5));
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DEBUG_CASE(NV_PGRAPH_TLIMIT(5));
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DEBUG_CASE(NV_PGRAPH_TSIZE(5));
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DEBUG_CASE(NV_PGRAPH_TSTATUS(5));
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DEBUG_CASE(NV_PGRAPH_TTILE(6));
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DEBUG_CASE(NV_PGRAPH_TLIMIT(6));
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DEBUG_CASE(NV_PGRAPH_TSIZE(6));
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DEBUG_CASE(NV_PGRAPH_TSTATUS(6));
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DEBUG_CASE(NV_PGRAPH_TTILE(7));
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DEBUG_CASE(NV_PGRAPH_TLIMIT(7));
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DEBUG_CASE(NV_PGRAPH_TSIZE(7));
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DEBUG_CASE(NV_PGRAPH_TSTATUS(7));
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DEBUG_CASE(NV_PGRAPH_ZCOMP(0));
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DEBUG_CASE(NV_PGRAPH_ZCOMP(1));
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DEBUG_CASE(NV_PGRAPH_ZCOMP(2));
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DEBUG_CASE(NV_PGRAPH_ZCOMP(3));
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DEBUG_CASE(NV_PGRAPH_ZCOMP(4));
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DEBUG_CASE(NV_PGRAPH_ZCOMP(5));
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DEBUG_CASE(NV_PGRAPH_ZCOMP(6));
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DEBUG_CASE(NV_PGRAPH_ZCOMP(7));
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DEBUG_CASE(NV_PGRAPH_ZCOMP_OFFSET);
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DEBUG_CASE(NV_PGRAPH_FBCFG0);
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DEBUG_CASE(NV_PGRAPH_FBCFG1);
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DEBUG_CASE(NV_PGRAPH_DEBUG_6);
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DEBUG_CASE(NV_PGRAPH_DEBUG_7);
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DEBUG_CASE(NV_PGRAPH_DEBUG_10);
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DEBUG_CASE(NV_PGRAPH_CSV0_D);
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DEBUG_CASE(NV_PGRAPH_CSV0_C);
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DEBUG_CASE(NV_PGRAPH_CSV1_B);
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@ -775,8 +908,7 @@ DEBUG_START(PGRAPH)
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DEBUG_CASE(NV_PGRAPH_SHADOWZSLOPETHRESHOLD);
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DEBUG_CASE(NV_PGRAPH_SPECFOGFACTOR0);
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DEBUG_CASE(NV_PGRAPH_SPECFOGFACTOR1);
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DEBUG_CASE(NV_PGRAPH_TEXADDRESS0);
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DEBUG_CASE(NV_PGRAPH_TEXADDRESS0_ADDRV);
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DEBUG_CASE_EX(NV_PGRAPH_TEXADDRESS0, ":_ADDRV");
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DEBUG_CASE(NV_PGRAPH_TEXADDRESS1);
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DEBUG_CASE(NV_PGRAPH_TEXADDRESS2);
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DEBUG_CASE(NV_PGRAPH_TEXADDRESS3);
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@ -825,7 +957,6 @@ DEBUG_START(PCRTC)
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DEBUG_CASE(NV_PCRTC_INTR_EN_0);
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DEBUG_CASE(NV_PCRTC_START);
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DEBUG_CASE(NV_PCRTC_CONFIG);
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DEBUG_END(PCRTC)
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DEBUG_START(PRMCIO)
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@ -865,21 +996,19 @@ DEBUG_START(PRAMIN)
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DEBUG_END(PRAMIN)
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DEBUG_START(USER)
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DEBUG_CASE(NV_USER_DMA_PUT);
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DEBUG_CASE(NV_USER_DMA_GET);
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DEBUG_CASE(NV_USER_REF);
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DEBUG_END(USER)
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DEBUG_END(USER)
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#define DEBUG_READ32(DEV) DbgPrintf("X86 : Rd32 NV2A " #DEV "(0x%08X) = 0x%08X [Handled %s]\n", addr, result, DebugNV_##DEV##(addr))
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#define DEBUG_READ32_UNHANDLED(DEV) { DbgPrintf("X86 : Rd32 NV2A " #DEV "(0x%08X) = 0x%08X [Unhandled %s]\n", addr, result, DebugNV_##DEV##(addr)); return result; }
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#define DEBUG_READ32(DEV) DbgPrintf("X86 : Read32 NV2A " #DEV "(0x%08X) = 0x%08X [Handle%s]\n", addr, result, DebugNV_##DEV##(addr))
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#define DEBUG_READ32_UNHANDLED(DEV) { DbgPrintf("X86 : Read32 NV2A " #DEV "(0x%08X) = 0x%08X [Unhandle%s]\n", addr, result, DebugNV_##DEV##(addr)); return result; }
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#define DEBUG_WRITE32(DEV) DbgPrintf("X86 : Wr32 NV2A " #DEV "(0x%08X, 0x%08X) [Handled %s]\n", addr, value, DebugNV_##DEV##(addr))
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#define DEBUG_WRITE32_UNHANDLED(DEV) { DbgPrintf("X86 : Wr32 NV2A " #DEV "(0x%08X, 0x%08X) [Unhandled %s]\n", addr, value, DebugNV_##DEV##(addr)); return; }
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#define DEBUG_WRITE32(DEV) DbgPrintf("X86 : Write32 NV2A " #DEV "(0x%08X, 0x%08X) [Handle%s]\n", addr, value, DebugNV_##DEV##(addr))
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#define DEBUG_WRITE32_UNHANDLED(DEV) { DbgPrintf("X86 : Write32 NV2A " #DEV "(0x%08X, 0x%08X) [Unhandle%s]\n", addr, value, DebugNV_##DEV##(addr)); return; }
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#define DEVICE_READ32(DEV) uint32_t EmuNV2A_##DEV##_Read32(xbaddr addr)
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#define DEVICE_READ32_SWITCH() uint32_t result = 0; switch (addr)
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@ -895,6 +1024,11 @@ static inline uint32_t ldl_le_p(const void *p)
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return *(uint32_t*)p;
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}
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static inline void stl_le_p(uint32_t *p, uint32 v)
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{
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*p = v;
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}
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static DMAObject nv_dma_load(xbaddr dma_obj_address)
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{
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assert(dma_obj_address < NV_PRAMIN_SIZE);
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@ -920,7 +1054,7 @@ static void *nv_dma_map(xbaddr dma_obj_address, xbaddr *len)
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DMAObject dma = nv_dma_load(dma_obj_address);
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/* TODO: Handle targets and classes properly */
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printf("dma_map %x, %x, %x %x" "\n",
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printf("dma_map %x, %x, %x %x\n",
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dma.dma_class, dma.dma_target, dma.address, dma.limit);
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dma.address &= 0x07FFFFFF;
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@ -1074,7 +1208,7 @@ static void pfifo_run_pusher() {
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static uint32_t ramht_hash(uint32_t handle)
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{
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unsigned int ramht_size = 1 << (GET_MASK(pfifo.regs[NV_PFIFO_RAMHT], NV_PFIFO_RAMHT_SIZE) + 12);
|
||||
unsigned int ramht_size = 1 << (GET_MASK(pfifo.regs[NV_PFIFO_RAMHT], NV_PFIFO_RAMHT_SIZE_MASK) + 12);
|
||||
|
||||
/* XXX: Think this is different to what nouveau calculates... */
|
||||
unsigned int bits = ffs(ramht_size) - 2;
|
||||
|
|
@ -1092,14 +1226,14 @@ static uint32_t ramht_hash(uint32_t handle)
|
|||
|
||||
static RAMHTEntry ramht_lookup(uint32_t handle)
|
||||
{
|
||||
unsigned int ramht_size = 1 << (GET_MASK(pfifo.regs[NV_PFIFO_RAMHT], NV_PFIFO_RAMHT_SIZE) + 12);
|
||||
unsigned int ramht_size = 1 << (GET_MASK(pfifo.regs[NV_PFIFO_RAMHT], NV_PFIFO_RAMHT_SIZE_MASK) + 12);
|
||||
|
||||
uint32_t hash = ramht_hash(handle);
|
||||
assert(hash * 8 < ramht_size);
|
||||
|
||||
uint32_t ramht_address =
|
||||
GET_MASK(pfifo.regs[NV_PFIFO_RAMHT],
|
||||
NV_PFIFO_RAMHT_BASE_ADDRESS) << 12;
|
||||
NV_PFIFO_RAMHT_BASE_ADDRESS_MASK) << 12;
|
||||
|
||||
uint8_t *entry_ptr = (uint8_t*)(NV2A_ADDR + NV_PRAMIN_ADDR + ramht_address + hash * 8);
|
||||
|
||||
|
|
@ -1245,6 +1379,12 @@ static bool pgraph_zeta_write_enabled()
|
|||
| NV_PGRAPH_CONTROL_0_STENCIL_WRITE_ENABLE);
|
||||
}
|
||||
|
||||
static void pgraph_update_surface(bool upload,
|
||||
bool color_write, bool zeta_write)
|
||||
{
|
||||
printf("TODO: pgraph_update_surface\n");
|
||||
}
|
||||
|
||||
static unsigned int kelvin_map_stencil_op(uint32_t parameter)
|
||||
{
|
||||
unsigned int op;
|
||||
|
|
@ -1320,7 +1460,7 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
{
|
||||
std::lock_guard<std::mutex> lk(pgraph.mutex);
|
||||
|
||||
int i;
|
||||
// int i;
|
||||
GraphicsSubchannel *subchannel_data;
|
||||
GraphicsObject *object;
|
||||
|
||||
|
|
@ -1397,7 +1537,7 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
/* I guess this kicks it off? */
|
||||
if (image_blit->operation == NV09F_SET_OPERATION_SRCCOPY) {
|
||||
|
||||
printf("NV09F_SET_OPERATION_SRCCOPY");
|
||||
printf("NV09F_SET_OPERATION_SRCCOPY\n");
|
||||
|
||||
GraphicsObject *context_surfaces_obj = lookup_graphics_object(image_blit->context_surfaces);
|
||||
assert(context_surfaces_obj);
|
||||
|
|
@ -1435,7 +1575,7 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
|
||||
printf(" - 0x%tx -> 0x%tx\n", source - MM_SYSTEM_PHYSICAL_MAP,dest - MM_SYSTEM_PHYSICAL_MAP);
|
||||
|
||||
int y;
|
||||
unsigned int y;
|
||||
for (y = 0; y<image_blit->height; y++) {
|
||||
uint8_t *source_row = source
|
||||
+ (image_blit->in_y + y) * context_surfaces->source_pitch
|
||||
|
|
@ -1475,9 +1615,8 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
kelvin->dma_state = parameter;
|
||||
break;
|
||||
case NV097_SET_CONTEXT_DMA_COLOR:
|
||||
printf("TODO: pgraph_update_surface\n");
|
||||
/* try to get any straggling draws in before the surface's changed :/ */
|
||||
//pgraph_update_surface(d, false, true, true);
|
||||
pgraph_update_surface(false, true, true);
|
||||
|
||||
pgraph.dma_color = parameter;
|
||||
break;
|
||||
|
|
@ -1497,8 +1636,7 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
pgraph.dma_report = parameter;
|
||||
break;
|
||||
case NV097_SET_SURFACE_CLIP_HORIZONTAL:
|
||||
printf("TODO: pgraph_update_surface\n");
|
||||
//pgraph_update_surface(d, false, true, true);
|
||||
pgraph_update_surface(false, true, true);
|
||||
|
||||
pgraph.surface_shape.clip_x =
|
||||
GET_MASK(parameter, NV097_SET_SURFACE_CLIP_HORIZONTAL_X);
|
||||
|
|
@ -1506,8 +1644,7 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
GET_MASK(parameter, NV097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH);
|
||||
break;
|
||||
case NV097_SET_SURFACE_CLIP_VERTICAL:
|
||||
printf("TODO: pgraph_update_surface\n");
|
||||
//pgraph_update_surface(d, false, true, true);
|
||||
pgraph_update_surface(false, true, true);
|
||||
|
||||
pgraph.surface_shape.clip_y =
|
||||
GET_MASK(parameter, NV097_SET_SURFACE_CLIP_VERTICAL_Y);
|
||||
|
|
@ -1515,8 +1652,7 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
GET_MASK(parameter, NV097_SET_SURFACE_CLIP_VERTICAL_HEIGHT);
|
||||
break;
|
||||
case NV097_SET_SURFACE_FORMAT:
|
||||
printf("TODO: pgraph_update_surface\n");
|
||||
//pgraph_update_surface(d, false, true, true);
|
||||
pgraph_update_surface(false, true, true);
|
||||
|
||||
pgraph.surface_shape.color_format =
|
||||
GET_MASK(parameter, NV097_SET_SURFACE_FORMAT_COLOR);
|
||||
|
|
@ -1532,8 +1668,7 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
GET_MASK(parameter, NV097_SET_SURFACE_FORMAT_HEIGHT);
|
||||
break;
|
||||
case NV097_SET_SURFACE_PITCH:
|
||||
printf("TODO: pgraph_update_surface\n");
|
||||
//pgraph_update_surface(d, false, true, true);
|
||||
pgraph_update_surface(false, true, true);
|
||||
|
||||
pgraph.surface_color.pitch =
|
||||
GET_MASK(parameter, NV097_SET_SURFACE_PITCH_COLOR);
|
||||
|
|
@ -1541,14 +1676,12 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
GET_MASK(parameter, NV097_SET_SURFACE_PITCH_ZETA);
|
||||
break;
|
||||
case NV097_SET_SURFACE_COLOR_OFFSET:
|
||||
printf("TODO: pgraph_update_surface\n");
|
||||
//pgraph_update_surface(d, false, true, true);
|
||||
pgraph_update_surface(false, true, true);
|
||||
|
||||
pgraph.surface_color.offset = parameter;
|
||||
break;
|
||||
case NV097_SET_SURFACE_ZETA_OFFSET:
|
||||
printf("TODO: pgraph_update_surface\n");
|
||||
//pgraph_update_surface(d, false, true, true);
|
||||
pgraph_update_surface(false, true, true);
|
||||
|
||||
pgraph.surface_zeta.offset = parameter;
|
||||
break;
|
||||
|
|
@ -1563,8 +1696,7 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
pgraph.regs[NV_PGRAPH_TEXADDRESS0 + slot * 4] = parameter;
|
||||
break;
|
||||
case NV097_SET_CONTROL0: {
|
||||
printf("TODO: pgraph_update_surface\n");
|
||||
//pgraph_update_surface(d, false, true, true);
|
||||
pgraph_update_surface(false, true, true);
|
||||
|
||||
bool stencil_write_enable =
|
||||
parameter & NV097_SET_CONTROL0_STENCIL_WRITE_ENABLE;
|
||||
|
|
@ -1990,6 +2122,29 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
|
|||
case NV097_SET_TEXGEN_VIEW_MODEL:
|
||||
SET_MASK(pgraph.regs[NV_PGRAPH_CSV0_D], NV_PGRAPH_CSV0_D_TEXGEN_REF, parameter);
|
||||
break;
|
||||
case NV097_SET_SEMAPHORE_OFFSET:
|
||||
kelvin->semaphore_offset = parameter;
|
||||
break;
|
||||
case NV097_BACK_END_WRITE_SEMAPHORE_RELEASE: {
|
||||
|
||||
pgraph_update_surface(false, true, true);
|
||||
|
||||
//qemu_mutex_unlock(&d->pgraph.lock);
|
||||
//qemu_mutex_lock_iothread();
|
||||
|
||||
xbaddr semaphore_dma_len;
|
||||
uint8_t *semaphore_data = (uint8_t*)nv_dma_map(kelvin->dma_semaphore,
|
||||
&semaphore_dma_len);
|
||||
assert(kelvin->semaphore_offset < semaphore_dma_len);
|
||||
semaphore_data += kelvin->semaphore_offset;
|
||||
|
||||
stl_le_p((uint32_t*)semaphore_data, parameter);
|
||||
|
||||
//qemu_mutex_lock(&d->pgraph.lock);
|
||||
//qemu_mutex_unlock_iothread();
|
||||
|
||||
break;
|
||||
}
|
||||
default:
|
||||
if (method >= NV097_SET_COMBINER_ALPHA_ICW && method <= NV097_SET_COMBINER_ALPHA_ICW + 28) {
|
||||
slot = (method - NV097_SET_COMBINER_ALPHA_ICW) / 4;
|
||||
|
|
@ -2235,10 +2390,13 @@ DEVICE_READ32(PMC)
|
|||
case NV_PMC_BOOT_0: // chipset and stepping: NV2A, A02, Rev 0
|
||||
result = 0x02A000A2;
|
||||
break;
|
||||
case NV_PMC_INTR_0:
|
||||
case NV_PMC_BOOT_1: // Selects big/little endian mode for the card
|
||||
result = 0; // When read, returns 0 if in little-endian mode, 0x01000001 if in big-endian mode.
|
||||
break;
|
||||
case NV_PMC_INTR_0: // Shows which functional units have pending IRQ
|
||||
result = pmc.pending_interrupts;
|
||||
break;
|
||||
case NV_PMC_INTR_EN_0:
|
||||
case NV_PMC_INTR_EN_0: // Selects which functional units can cause IRQs
|
||||
result = pmc.enabled_interrupts;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -2361,7 +2519,7 @@ DEVICE_READ32(PFIFO)
|
|||
pfifo.cache1.error);
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_DMA_INSTANCE:
|
||||
SET_MASK(result, NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS,
|
||||
SET_MASK(result, NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MASK,
|
||||
pfifo.cache1.dma_instance >> 4);
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_DMA_PUT:
|
||||
|
|
@ -2440,7 +2598,7 @@ DEVICE_WRITE32(PFIFO)
|
|||
pfifo.cache1.error = GET_MASK(value, NV_PFIFO_CACHE1_DMA_STATE_ERROR);
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_DMA_INSTANCE:
|
||||
pfifo.cache1.dma_instance = GET_MASK(value, NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS) << 4;
|
||||
pfifo.cache1.dma_instance = GET_MASK(value, NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MASK) << 4;
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_DMA_PUT:
|
||||
user.channel_control[pfifo.cache1.channel_id].dma_put = value;
|
||||
|
|
@ -3259,7 +3417,7 @@ static const NV2ABlockInfo regions[] = {{
|
|||
}, {
|
||||
/* MMIO and DMA FIFO submission to PGRAPH and VPE */
|
||||
NV_PFIFO_ADDR, // = 0x002000
|
||||
NV_PFIFO_SIZE, // = 0x002000
|
||||
_NV_PFIFO_SIZE, // = 0x002000
|
||||
EmuNV2A_PFIFO_Read32,
|
||||
EmuNV2A_PFIFO_Write32,
|
||||
}, {
|
||||
|
|
@ -3307,7 +3465,7 @@ static const NV2ABlockInfo regions[] = {{
|
|||
}, {
|
||||
/* aliases VGA sequencer and graphics controller registers */
|
||||
NV_PRMVIO_ADDR, // = 0x0c0000
|
||||
NV_PRMVIO_SIZE, // = 0x001000
|
||||
NV_PRMVIO_SIZE, // = 0x008000 // Was 0x001000
|
||||
EmuNV2A_PRMVIO_Read32,
|
||||
EmuNV2A_PRMVIO_Write32,
|
||||
},{
|
||||
|
|
@ -3360,10 +3518,16 @@ static const NV2ABlockInfo regions[] = {{
|
|||
EmuNV2A_PRAMIN_Write32,
|
||||
},{
|
||||
/* PFIFO MMIO and DMA submission area */
|
||||
NV_USER_ADDR, // = 0x800000,
|
||||
NV_USER_SIZE, // = 0x800000,
|
||||
NV_USER_ADDR, // = 0x800000
|
||||
NV_USER_SIZE, // = 0x400000 // Was 0x800000
|
||||
EmuNV2A_USER_Read32,
|
||||
EmuNV2A_USER_Write32,
|
||||
}, {
|
||||
/* User area remapped? */
|
||||
NV_UREMAP_ADDR, // = 0xC00000
|
||||
NV_UREMAP_SIZE, // = 0x400000
|
||||
EmuNV2A_USER_Read32, // NOTE : Re-used (*not* EmuNV2A_UREMAP_Read32)
|
||||
EmuNV2A_USER_Write32, // NOTE : Re-used (*not* EmuNV2A_UREMAP_Write32)
|
||||
}, {
|
||||
0xFFFFFFFF,
|
||||
0,
|
||||
|
|
@ -3741,10 +3905,42 @@ static void nv2a_vblank_thread()
|
|||
}
|
||||
}
|
||||
|
||||
void CxbxReserveNV2AMemory()
|
||||
{
|
||||
// Reserve NV2A memory :
|
||||
void *memory = (void *)VirtualAllocEx(
|
||||
GetCurrentProcess(),
|
||||
(void *)NV2A_ADDR,
|
||||
NV2A_SIZE,
|
||||
MEM_RESERVE, // Don't allocate actual physical storage in memory
|
||||
PAGE_NOACCESS); // Any access must result in an access violation exception (handled in EmuException/EmuX86_DecodeException)
|
||||
if (memory == NULL) {
|
||||
EmuWarning("Couldn't reserve NV2A memory, continuing assuming we'll receive (and handle) access violation exceptions anyway...");
|
||||
return;
|
||||
}
|
||||
|
||||
printf("[0x%.4X] INIT: Reserved %d MiB of Xbox NV2A memory at 0x%.8X to 0x%.8X\n",
|
||||
GetCurrentThreadId(), NV2A_SIZE / ONE_MB, NV2A_ADDR, NV2A_ADDR + NV2A_SIZE - 1);
|
||||
|
||||
// Allocate PRAMIN Region
|
||||
memory = VirtualAllocEx(
|
||||
GetCurrentProcess(),
|
||||
(void*)(NV2A_ADDR + NV_PRAMIN_ADDR),
|
||||
NV_PRAMIN_SIZE,
|
||||
MEM_COMMIT, // No MEM_RESERVE |
|
||||
PAGE_READWRITE);
|
||||
if (memory == NULL) {
|
||||
EmuWarning("Couldn't allocate NV2A PRAMIN memory");
|
||||
return;
|
||||
}
|
||||
|
||||
printf("[0x%.4X] INIT: Allocated %d MiB of Xbox NV2A PRAMIN memory at 0x%.8X to 0x%.8X\n",
|
||||
GetCurrentThreadId(), NV_PRAMIN_SIZE / ONE_MB, NV2A_ADDR + NV_PRAMIN_ADDR, NV2A_ADDR + NV_PRAMIN_ADDR + NV_PRAMIN_SIZE - 1);
|
||||
}
|
||||
|
||||
void EmuNV2A_Init()
|
||||
{
|
||||
// Allocate PRAMIN Region
|
||||
VirtualAlloc((void*)(NV2A_ADDR + NV_PRAMIN_ADDR), NV_PRAMIN_SIZE, MEM_RESERVE | MEM_COMMIT, PAGE_READWRITE);
|
||||
CxbxReserveNV2AMemory();
|
||||
|
||||
pcrtc.start = 0;
|
||||
|
||||
|
|
@ -3757,6 +3953,6 @@ void EmuNV2A_Init()
|
|||
|
||||
// Only spawn VBlank thread when LLE is enabled
|
||||
if (bLLE_GPU) {
|
||||
vblank_thread = std::thread(nv2a_vblank_thread);;
|
||||
vblank_thread = std::thread(nv2a_vblank_thread);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
#define NV_PBUS_ADDR 0x00001000
|
||||
#define NV_PBUS_SIZE 0x001000
|
||||
#define NV_PFIFO_ADDR 0x00002000
|
||||
#define NV_PFIFO_SIZE 0x002000
|
||||
#define _NV_PFIFO_SIZE 0x002000 // Underscore prefix to prevent clash with NV_PFIFO_SIZE
|
||||
#define NV_PRMA_ADDR 0x00007000
|
||||
#define NV_PRMA_SIZE 0x001000
|
||||
#define NV_PVIDEO_ADDR 0x00008000
|
||||
|
|
@ -61,7 +61,7 @@
|
|||
#define NV_PRMFB_ADDR 0x000A0000
|
||||
#define NV_PRMFB_SIZE 0x020000
|
||||
#define NV_PRMVIO_ADDR 0x000C0000
|
||||
#define NV_PRMVIO_SIZE 0x001000
|
||||
#define NV_PRMVIO_SIZE 0x008000 // Was 0x001000
|
||||
#define NV_PFB_ADDR 0x00100000
|
||||
#define NV_PFB_SIZE 0x001000
|
||||
#define NV_PSTRAPS_ADDR 0x00101000
|
||||
|
|
@ -79,18 +79,65 @@
|
|||
#define NV_PRAMIN_ADDR 0x00700000
|
||||
#define NV_PRAMIN_SIZE 0x100000
|
||||
#define NV_USER_ADDR 0x00800000
|
||||
#define NV_USER_SIZE 0x800000
|
||||
#define NV_USER_SIZE 0x400000
|
||||
#define NV_UREMAP_ADDR 0x00C00000 // Looks like a mapping of NV_USER_ADDR
|
||||
#define NV_UREMAP_SIZE 0x400000
|
||||
|
||||
typedef volatile DWORD *PPUSH;
|
||||
|
||||
typedef struct {
|
||||
DWORD Ignored[0x10];
|
||||
DWORD* Put; // On Xbox1, this field is only written to by the CPU (the GPU uses this as a trigger to start executing from the given address)
|
||||
DWORD* Get; // On Xbox1, this field is only read from by the CPU (the GPU reflects in here where it is/stopped executing)
|
||||
DWORD Reference; // TODO : xbaddr / void* / DWORD ?
|
||||
PPUSH Put; // On Xbox1, this field is only written to by the CPU (the GPU uses this as a trigger to start executing from the given address)
|
||||
PPUSH Get; // On Xbox1, this field is only read from by the CPU (the GPU reflects in here where it is/stopped executing)
|
||||
PPUSH Reference; // TODO : xbaddr / void* / DWORD ?
|
||||
DWORD Ignored2[0x7ED];
|
||||
} Nv2AControlDma;
|
||||
|
||||
uint32_t EmuNV2A_Read(xbaddr addr, int size);
|
||||
void EmuNV2A_Write(xbaddr addr, uint32_t value, int size);
|
||||
|
||||
#define PUSH_TYPE_MASK 0x00000002 // 2 bits
|
||||
#define PUSH_TYPE_SHIFT 0
|
||||
#define PUSH_TYPE_METHOD 0 // method
|
||||
#define PUSH_TYPE_JMP_FAR 1 // jump far
|
||||
#define PUSH_TYPE_CALL_FAR 2 // call far
|
||||
#define PUSH_TYPE_METHOD_UNUSED 3 // method (unused)
|
||||
#define PUSH_METHOD_MASK 0x00001FFC // 12 bits
|
||||
#define PUSH_METHOD_SHIFT 0 // Dxbx note : Not 2, because methods are actually DWORD offsets (and thus defined with increments of 4)
|
||||
#define PUSH_SUBCH_MASK 0x0000E000 // 3 bits
|
||||
#define PUSH_SUBCH_SHIFT 13
|
||||
#define PUSH_COUNT_MASK 0x1FFC0000 // 11 bits
|
||||
#define PUSH_COUNT_SHIFT 18
|
||||
#define PUSH_INSTR_MASK 0xE0000000 // 3 bits
|
||||
#define PUSH_INSTR_SHIFT 29
|
||||
#define PUSH_INSTR_IMM_INCR 0 // immediate, increment
|
||||
#define PUSH_INSTR_JMP_NEAR 1 // near jump
|
||||
#define PUSH_INSTR_IMM_NOINC 2 // immediate, no-increment
|
||||
#define PUSH_ADDR_FAR_MASK 0xFFFFFFFC // 30 bits
|
||||
#define PUSH_ADDR_FAR_SHIFT 0
|
||||
#define PUSH_ADDR_NEAR_MASK 0x1FFFFFFC // 27 bits
|
||||
#define PUSH_ADDR_NEAR_SHIFT 0 // Cxbx note : Not 2, because methods are actually DWORD offsets (and thus defined with increments of 4)
|
||||
|
||||
#define PUSH_TYPE(dwPushCommand) ((dwPushCommand & PUSH_TYPE_MASK) >> PUSH_TYPE_SHIFT)
|
||||
#define PUSH_METHOD(dwPushCommand) ((dwPushCommand & PUSH_METHOD_MASK) >> PUSH_METHOD_SHIFT)
|
||||
#define PUSH_SUBCH(dwPushCommand) ((dwPushCommand & PUSH_SUBCH_MASK) >> PUSH_SUBCH_SHIFT)
|
||||
#define PUSH_COUNT(dwPushCommand) ((dwPushCommand & PUSH_COUNT_MASK) >> PUSH_COUNT_SHIFT)
|
||||
#define PUSH_INSTR(dwPushCommand) ((dwPushCommand & PUSH_INSTR_MASK) >> PUSH_INSTR_SHIFT)
|
||||
#define PUSH_ADDR_FAR(dwPushCommand) ((dwPushCommand & PUSH_ADDR_FAR_MASK) >> PUSH_ADDR_FAR_SHIFT)
|
||||
#define PUSH_ADDR_NEAR(dwPushCommand) ((dwPushCommand & PUSH_ADDR_NEAR_MASK) >> PUSH_ADDR_NEAR_SHIFT)
|
||||
|
||||
#define PUSH_METHOD_MAX ((PUSH_METHOD_MASK | 3) >> PUSH_METHOD_SHIFT) // = 8191
|
||||
#define PUSH_SUBCH_MAX (PUSH_SUBCH_MASK >> PUSH_SUBCH_SHIFT) // = 7
|
||||
#define PUSH_COUNT_MAX (PUSH_COUNT_MASK >> PUSH_COUNT_SHIFT) // = 2047
|
||||
|
||||
// Decode push buffer conmmand (inverse of D3DPUSH_ENCODE)
|
||||
inline void D3DPUSH_DECODE(const DWORD dwPushCommand, DWORD &dwMethod, DWORD &dwSubCh, DWORD &dwCount)
|
||||
{
|
||||
dwMethod = PUSH_METHOD(dwPushCommand);
|
||||
dwSubCh = PUSH_SUBCH(dwPushCommand);
|
||||
dwCount = PUSH_COUNT(dwPushCommand);
|
||||
}
|
||||
|
||||
void EmuNV2A_Init();
|
||||
|
||||
void InitOpenGLContext();
|
||||
|
|
|
|||
|
|
@ -59,6 +59,14 @@ void NV2ADevice::Init()
|
|||
// Register physical memory on bar 1
|
||||
r.Memory.address = 0;
|
||||
RegisterBAR(1, XBOX_MEMORY_SIZE, r.value); // TODO : Read g_PhysicalMemory->Size
|
||||
/* LukeUsher commented at https://github.com/Cxbx-Reloaded/Cxbx-Reloaded/pull/882#discussion_r162871029
|
||||
|
||||
This is not right: I should have done a better review ;)
|
||||
The starting address here is the physical address in the Xbox memory the VRAM should be placed at,
|
||||
and should point to the TILED memory region ((0xF0000000 >> 4))
|
||||
|
||||
This maps VRAM address 0 to 0xF0000000. (this is what our TILED memory is: VRAM accessed via the GPU device)
|
||||
*/
|
||||
|
||||
m_DeviceId = 0x02A5;
|
||||
m_VendorId = PCI_VENDOR_ID_NVIDIA;
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
// Source : https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a_int.h
|
||||
/*
|
||||
* QEMU Geforce NV2A internal definitions
|
||||
*
|
||||
|
|
@ -18,12 +19,38 @@
|
|||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#define NV_NUM_BLOCKS 21
|
||||
#define NV_PMC 0 /* card master control */
|
||||
#define NV_PBUS 1 /* bus control */
|
||||
#define NV_PFIFO 2 /* MMIO and DMA FIFO submission to PGRAPH and VPE */
|
||||
#define NV_PFIFO_CACHE 3
|
||||
#define NV_PRMA 4 /* access to BAR0/BAR1 from real mode */
|
||||
#define NV_PVIDEO 5 /* video overlay */
|
||||
#define NV_PTIMER 6 /* time measurement and time-based alarms */
|
||||
#define NV_PCOUNTER 7 /* performance monitoring counters */
|
||||
#define NV_PVPE 8 /* MPEG2 decoding engine */
|
||||
#define NV_PTV 9 /* TV encoder */
|
||||
#define NV_PRMFB 10 /* aliases VGA memory window */
|
||||
#define NV_PRMVIO 11 /* aliases VGA sequencer and graphics controller registers */
|
||||
#define NV_PFB 12 /* memory interface */
|
||||
#define NV_PSTRAPS 13 /* straps readout / override */
|
||||
#define NV_PGRAPH 14 /* accelerated 2d/3d drawing engine */
|
||||
#define NV_PCRTC 15 /* more CRTC controls */
|
||||
#define NV_PRMCIO 16 /* aliases VGA CRTC and attribute controller registers */
|
||||
#define NV_PRAMDAC 17 /* RAMDAC, cursor, and PLL control */
|
||||
#define NV_PRMDIO 18 /* aliases VGA palette registers */
|
||||
#define NV_PRAMIN 19 /* RAMIN access */
|
||||
#define NV_USER 20 /* PFIFO MMIO and DMA submission area */
|
||||
|
||||
#define NV_PMC_BOOT_0 0x00000000
|
||||
#define NV_PMC_BOOT_1 0x00000004
|
||||
#define NV_PMC_INTR_0 0x00000100
|
||||
# define NV_PMC_INTR_0_PFIFO (1 << 8)
|
||||
# define NV_PMC_INTR_0_PGRAPH (1 << 12)
|
||||
# define NV_PMC_INTR_0_PVIDEO (1 << 16)
|
||||
# define NV_PMC_INTR_0_PTIMER (1 << 20)
|
||||
# define NV_PMC_INTR_0_PCRTC (1 << 24)
|
||||
# define NV_PMC_INTR_0_PCRTC2 (1 << 25)
|
||||
# define NV_PMC_INTR_0_PBUS (1 << 28)
|
||||
# define NV_PMC_INTR_0_SOFTWARE (1 << 31)
|
||||
#define NV_PMC_INTR_EN_0 0x00000140
|
||||
|
|
@ -32,8 +59,16 @@
|
|||
#define NV_PMC_ENABLE 0x00000200
|
||||
# define NV_PMC_ENABLE_PFIFO (1 << 8)
|
||||
# define NV_PMC_ENABLE_PGRAPH (1 << 12)
|
||||
# define NV_PMC_ENABLE_PFB (1 << 20)
|
||||
# define NV_PMC_ENABLE_PCRTC (1 << 24)
|
||||
# define NV_PMC_ENABLE_PCRTC2 (1 << 25)
|
||||
# define NV_PMC_ENABLE_PVIDEO (1 << 28)
|
||||
|
||||
|
||||
#define NV_PBUS_FBIO_RAM 0x00000218
|
||||
# define NV_PBUS_FBIO_RAM_TYPE 0x00000100
|
||||
# define NV_PBUS_FBIO_RAM_TYPE_DDR (0 << 8)
|
||||
# define NV_PBUS_FBIO_RAM_TYPE_SDR (1 << 8)
|
||||
/* These map approximately to the pci registers */
|
||||
#define NV_PBUS_PCI_NV_0 0x00000800
|
||||
# define NV_PBUS_PCI_NV_0_VENDOR_ID 0x0000FFFF
|
||||
|
|
@ -65,6 +100,9 @@
|
|||
#define NV_PBUS_PCI_NV_26 0x00000868
|
||||
|
||||
|
||||
#define NV_PFIFO_DELAY_0 0x00000040
|
||||
#define NV_PFIFO_DMA_TIMESLICE 0x00000044
|
||||
#define NV_PFIFO_TIMESLICE 0x0000004C
|
||||
#define NV_PFIFO_INTR_0 0x00000100
|
||||
# define NV_PFIFO_INTR_0_CACHE_ERROR (1 << 0)
|
||||
# define NV_PFIFO_INTR_0_RUNOUT (1 << 4)
|
||||
|
|
@ -82,21 +120,37 @@
|
|||
# define NV_PFIFO_INTR_EN_0_SEMAPHORE (1 << 20)
|
||||
# define NV_PFIFO_INTR_EN_0_ACQUIRE_TIMEOUT (1 << 24)
|
||||
#define NV_PFIFO_RAMHT 0x00000210
|
||||
# define NV_PFIFO_RAMHT_BASE_ADDRESS 0x000001F0
|
||||
# define NV_PFIFO_RAMHT_SIZE 0x00030000
|
||||
//# define NV_PFIFO_RAMHT_BASE_ADDRESS 0x000001F0
|
||||
# define NV_PFIFO_RAMHT_BASE_ADDRESS_MASK 0x000001F0
|
||||
# define NV_PFIFO_RAMHT_BASE_ADDRESS_SHIFT 4
|
||||
# define NV_PFIFO_RAMHT_BASE_ADDRESS_MOVE 12
|
||||
//# define NV_PFIFO_RAMHT_SIZE 0x00030000
|
||||
# define NV_PFIFO_RAMHT_SIZE_MASK 0x00030000
|
||||
# define NV_PFIFO_RAMHT_SIZE_SHIFT 16
|
||||
# define NV_PFIFO_RAMHT_SIZE_4K 0
|
||||
# define NV_PFIFO_RAMHT_SIZE_8K 1
|
||||
# define NV_PFIFO_RAMHT_SIZE_16K 2
|
||||
# define NV_PFIFO_RAMHT_SIZE_32K 3
|
||||
# define NV_PFIFO_RAMHT_SEARCH 0x03000000
|
||||
//# define NV_PFIFO_RAMHT_SEARCH 0x03000000
|
||||
# define NV_PFIFO_RAMHT_SEARCH_MASK 0x03000000
|
||||
# define NV_PFIFO_RAMHT_SEARCH_SHIFT 24
|
||||
# define NV_PFIFO_RAMHT_SEARCH_16 0
|
||||
# define NV_PFIFO_RAMHT_SEARCH_32 1
|
||||
# define NV_PFIFO_RAMHT_SEARCH_64 2
|
||||
# define NV_PFIFO_RAMHT_SEARCH_128 3
|
||||
#define NV_PFIFO_RAMFC 0x00000214
|
||||
# define NV_PFIFO_RAMFC_BASE_ADDRESS1 0x000001FC
|
||||
# define NV_PFIFO_RAMFC_SIZE 0x00010000
|
||||
# define NV_PFIFO_RAMFC_BASE_ADDRESS2 0x00FE0000
|
||||
//# define NV_PFIFO_RAMFC_BASE_ADDRESS1 0x000001FC
|
||||
# define NV_PFIFO_RAMFC_BASE_ADDRESS1_MASK 0x000001FC
|
||||
# define NV_PFIFO_RAMFC_BASE_ADDRESS1_SHIFT 2
|
||||
# define NV_PFIFO_RAMFC_BASE_ADDRESS1_MOVE 10
|
||||
//# define NV_PFIFO_RAMFC_SIZE 0x00010000
|
||||
# define NV_PFIFO_RAMFC_SIZE_MASK 0x00010000
|
||||
# define NV_PFIFO_RAMFC_SIZE_1K 0x00000000
|
||||
# define NV_PFIFO_RAMFC_SIZE_2K 0x00010000
|
||||
//# define NV_PFIFO_RAMFC_BASE_ADDRESS2 0x00FE0000
|
||||
# define NV_PFIFO_RAMFC_BASE_ADDRESS2_MASK 0x00FE0000
|
||||
# define NV_PFIFO_RAMFC_BASE_ADDRESS2_SHIFT 17
|
||||
# define NV_PFIFO_RAMFC_BASE_ADDRESS2_MOVE 10
|
||||
#define NV_PFIFO_RAMRO 0x00000218
|
||||
# define NV_PFIFO_RAMRO_BASE_ADDRESS 0x000001FE
|
||||
# define NV_PFIFO_RAMRO_SIZE 0x00010000
|
||||
|
|
@ -104,13 +158,21 @@
|
|||
# define NV_PFIFO_RUNOUT_STATUS_RANOUT (1 << 0)
|
||||
# define NV_PFIFO_RUNOUT_STATUS_LOW_MARK (1 << 4)
|
||||
# define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK (1 << 8)
|
||||
#define NV_PFIFO_RUNOUT_PUT_ADDRESS 0x00000410
|
||||
#define NV_PFIFO_RUNOUT_GET_ADDRESS 0x00000420
|
||||
#define NV_PFIFO_CACHES 0x00000500
|
||||
#define NV_PFIFO_MODE 0x00000504
|
||||
#define NV_PFIFO_DMA 0x00000508
|
||||
#define NV_PFIFO_SIZE 0x0000050C
|
||||
#define NV_PFIFO_CACHE0_PUSH0 0x00001000
|
||||
#define NV_PFIFO_CACHE0_PULL0 0x00001050
|
||||
#define NV_PFIFO_CACHE0_HASH 0x00001058
|
||||
#define NV_PFIFO_CACHE1_PUSH0 0x00001200
|
||||
# define NV_PFIFO_CACHE1_PUSH0_ACCESS (1 << 0)
|
||||
#define NV_PFIFO_CACHE1_PUSH1 0x00001204
|
||||
# define NV_PFIFO_CACHE1_PUSH1_CHID 0x0000001F
|
||||
# define NV_PFIFO_CACHE1_PUSH1_MODE 0x00000100
|
||||
#define NV_PFIFO_CACHE1_PUT 0x00001210
|
||||
#define NV_PFIFO_CACHE1_STATUS 0x00001214
|
||||
# define NV_PFIFO_CACHE1_STATUS_LOW_MARK (1 << 4)
|
||||
# define NV_PFIFO_CACHE1_STATUS_HIGH_MARK (1 << 8)
|
||||
|
|
@ -137,14 +199,26 @@
|
|||
# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 4
|
||||
# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 6
|
||||
#define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000122C
|
||||
# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 0x0000FFFF
|
||||
//# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 0x0000FFFF
|
||||
# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MASK 0x0000FFFF
|
||||
# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_SHIFT 0
|
||||
# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MOVE 4
|
||||
#define NV_PFIFO_CACHE1_DMA_CTL 0x00001230
|
||||
#define NV_PFIFO_CACHE1_DMA_PUT 0x00001240
|
||||
#define NV_PFIFO_CACHE1_DMA_GET 0x00001244
|
||||
#define NV_PFIFO_CACHE1_REF 0x00001248
|
||||
#define NV_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000124C
|
||||
# define NV_PFIFO_CACHE1_DMA_SUBROUTINE_RETURN_OFFSET 0x1FFFFFFC
|
||||
# define NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE (1 << 0)
|
||||
#define NV_PFIFO_CACHE1_PULL0 0x00001250
|
||||
# define NV_PFIFO_CACHE1_PULL0_ACCESS (1 << 0)
|
||||
#define NV_PFIFO_CACHE1_PULL1 0x00001254
|
||||
#define NV_PFIFO_CACHE1_HASH 0x00001258
|
||||
#define NV_PFIFO_CACHE1_ACQUIRE_0 0x00001260
|
||||
#define NV_PFIFO_CACHE1_ACQUIRE_1 0x00001264
|
||||
#define NV_PFIFO_CACHE1_ACQUIRE_2 0x00001268
|
||||
#define NV_PFIFO_CACHE1_SEMAPHORE 0x0000126C
|
||||
#define NV_PFIFO_CACHE1_GET 0x00001270
|
||||
#define NV_PFIFO_CACHE1_ENGINE 0x00001280
|
||||
#define NV_PFIFO_CACHE1_DMA_DCOUNT 0x000012A0
|
||||
# define NV_PFIFO_CACHE1_DMA_DCOUNT_VALUE 0x00001FFC
|
||||
|
|
@ -154,6 +228,13 @@
|
|||
#define NV_PFIFO_CACHE1_DMA_DATA_SHADOW 0x000012AC
|
||||
|
||||
|
||||
#define NV_PGRAPH_DEBUG_0 0x00000080
|
||||
#define NV_PGRAPH_DEBUG_1 0x00000084
|
||||
#define NV_PGRAPH_DEBUG_3 0x0000008C
|
||||
#define NV_PGRAPH_DEBUG_4 0x00000090
|
||||
#define NV_PGRAPH_DEBUG_5 0x00000094
|
||||
#define NV_PGRAPH_DEBUG_8 0x00000098
|
||||
#define NV_PGRAPH_DEBUG_9 0x0000009C
|
||||
#define NV_PGRAPH_INTR 0x00000100
|
||||
# define NV_PGRAPH_INTR_NOTIFY (1 << 0)
|
||||
# define NV_PGRAPH_INTR_MISSING_HW (1 << 4)
|
||||
|
|
@ -212,6 +293,10 @@
|
|||
# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA1 (1 << 29)
|
||||
# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA4 (1 << 30)
|
||||
# define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET (1 << 31)
|
||||
#define NV_PGRAPH_CTX_SWITCH2 0x00000150
|
||||
#define NV_PGRAPH_CTX_SWITCH3 0x00000154
|
||||
#define NV_PGRAPH_CTX_SWITCH4 0x00000158
|
||||
#define NV_PGRAPH_STATUS 0x00000700
|
||||
#define NV_PGRAPH_TRAPPED_ADDR 0x00000704
|
||||
# define NV_PGRAPH_TRAPPED_ADDR_MTHD 0x00001FFF
|
||||
# define NV_PGRAPH_TRAPPED_ADDR_SUBCH 0x00070000
|
||||
|
|
@ -227,6 +312,9 @@
|
|||
# define NV_PGRAPH_INCREMENT_READ_3D (1 << 1)
|
||||
#define NV_PGRAPH_FIFO 0x00000720
|
||||
# define NV_PGRAPH_FIFO_ACCESS (1 << 0)
|
||||
#define NV_PGRAPH_RDI_INDEX 0x00000750
|
||||
#define NV_PGRAPH_RDI_DATA 0x00000754
|
||||
#define NV_PGRAPH_FFINTFC_ST2 0x00000764
|
||||
#define NV_PGRAPH_CHANNEL_CTX_TABLE 0x00000780
|
||||
# define NV_PGRAPH_CHANNEL_CTX_TABLE_INST 0x0000FFFF
|
||||
#define NV_PGRAPH_CHANNEL_CTX_POINTER 0x00000784
|
||||
|
|
@ -234,6 +322,18 @@
|
|||
#define NV_PGRAPH_CHANNEL_CTX_TRIGGER 0x00000788
|
||||
# define NV_PGRAPH_CHANNEL_CTX_TRIGGER_READ_IN (1 << 0)
|
||||
# define NV_PGRAPH_CHANNEL_CTX_TRIGGER_WRITE_OUT (1 << 1)
|
||||
#define NV_PGRAPH_DEBUG_2 0x00000880
|
||||
#define NV_PGRAPH_TTILE(i) 0x00000900 + (i * 0x10)
|
||||
#define NV_PGRAPH_TLIMIT(i) 0x00000904 + (i * 0x10)
|
||||
#define NV_PGRAPH_TSIZE(i) 0x00000908 + (i * 0x10)
|
||||
#define NV_PGRAPH_TSTATUS(i) 0x0000090C + (i * 0x10)
|
||||
#define NV_PGRAPH_ZCOMP(i) 0x00000980 + (i * 4)
|
||||
#define NV_PGRAPH_ZCOMP_OFFSET 0x000009A0
|
||||
#define NV_PGRAPH_FBCFG0 0x000009A4
|
||||
#define NV_PGRAPH_FBCFG1 0x000009A8
|
||||
#define NV_PGRAPH_DEBUG_6 0x00000B80
|
||||
#define NV_PGRAPH_DEBUG_7 0x00000B84
|
||||
#define NV_PGRAPH_DEBUG_10 0x00000B88
|
||||
#define NV_PGRAPH_CSV0_D 0x00000FB4
|
||||
# define NV_PGRAPH_CSV0_D_LIGHTS 0x0000FFFF
|
||||
# define NV_PGRAPH_CSV0_D_LIGHT0 0x00000003
|
||||
|
|
@ -544,6 +644,8 @@
|
|||
#define NV_PCRTC_CONFIG 0x00000804
|
||||
|
||||
|
||||
#define NV_PVIDEO_DEBUG_2 0x00000088
|
||||
#define NV_PVIDEO_DEBUG_3 0x0000008C
|
||||
#define NV_PVIDEO_INTR 0x00000100
|
||||
# define NV_PVIDEO_INTR_BUFFER_0 (1 << 0)
|
||||
# define NV_PVIDEO_INTR_BUFFER_1 (1 << 4)
|
||||
|
|
@ -554,26 +656,26 @@
|
|||
# define NV_PVIDEO_BUFFER_0_USE (1 << 0)
|
||||
# define NV_PVIDEO_BUFFER_1_USE (1 << 4)
|
||||
#define NV_PVIDEO_STOP 0x00000704
|
||||
#define NV_PVIDEO_BASE 0x00000900
|
||||
#define NV_PVIDEO_LIMIT 0x00000908
|
||||
#define NV_PVIDEO_LUMINANCE 0x00000910
|
||||
#define NV_PVIDEO_CHROMINANCE 0x00000918
|
||||
#define NV_PVIDEO_OFFSET 0x00000920
|
||||
#define NV_PVIDEO_SIZE_IN 0x00000928
|
||||
#define NV_PVIDEO_BASE(i) 0x00000900 + (i * 4)
|
||||
#define NV_PVIDEO_LIMIT(i) 0x00000908 + (i * 4)
|
||||
#define NV_PVIDEO_LUMINANCE(i) 0x00000910 + (i * 4)
|
||||
#define NV_PVIDEO_CHROMINANCE(i) 0x00000918 + (i * 4)
|
||||
#define NV_PVIDEO_OFFSET(i) 0x00000920 + (i * 4)
|
||||
#define NV_PVIDEO_SIZE_IN(i) 0x00000928 + (i * 4)
|
||||
# define NV_PVIDEO_SIZE_IN_WIDTH 0x000007FF
|
||||
# define NV_PVIDEO_SIZE_IN_HEIGHT 0x07FF0000
|
||||
#define NV_PVIDEO_POINT_IN 0x00000930
|
||||
#define NV_PVIDEO_POINT_IN(i) 0x00000930 + (i * 4)
|
||||
# define NV_PVIDEO_POINT_IN_S 0x00007FFF
|
||||
# define NV_PVIDEO_POINT_IN_T 0xFFFE0000
|
||||
#define NV_PVIDEO_DS_DX 0x00000938
|
||||
#define NV_PVIDEO_DT_DY 0x00000940
|
||||
#define NV_PVIDEO_POINT_OUT 0x00000948
|
||||
#define NV_PVIDEO_DS_DX(i) 0x00000938 + (i * 4)
|
||||
#define NV_PVIDEO_DT_DY(i) 0x00000940 + (i * 4)
|
||||
#define NV_PVIDEO_POINT_OUT(i) 0x00000948 + (i * 4)
|
||||
# define NV_PVIDEO_POINT_OUT_X 0x00000FFF
|
||||
# define NV_PVIDEO_POINT_OUT_Y 0x0FFF0000
|
||||
#define NV_PVIDEO_SIZE_OUT 0x00000950
|
||||
#define NV_PVIDEO_SIZE_OUT(i) 0x00000950 + (i * 4)
|
||||
# define NV_PVIDEO_SIZE_OUT_WIDTH 0x00000FFF
|
||||
# define NV_PVIDEO_SIZE_OUT_HEIGHT 0x0FFF0000
|
||||
#define NV_PVIDEO_FORMAT 0x00000958
|
||||
#define NV_PVIDEO_FORMAT(i) 0x00000958 + (i * 4)
|
||||
# define NV_PVIDEO_FORMAT_PITCH 0x00001FFF
|
||||
# define NV_PVIDEO_FORMAT_COLOR 0x00030000
|
||||
# define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 1
|
||||
|
|
@ -594,6 +696,7 @@
|
|||
#define NV_PFB_DEBUG_0 0x00000080
|
||||
#define NV_PFB_CFG0 0x00000200
|
||||
# define NV_PFB_CFG0_PART 0x00000003
|
||||
#define NV_PFB_CFG1 0x00000204
|
||||
#define NV_PFB_CSTATUS 0x0000020C
|
||||
#define NV_PFB_REFCTRL 0x00000210
|
||||
#define NV_PFB_NVM 0x00000214 // NV_PFB_NVM_MODE_DISABLE
|
||||
|
|
@ -602,17 +705,18 @@
|
|||
#define NV_PFB_TIMING0 0x00000220
|
||||
#define NV_PFB_TIMING1 0x00000224
|
||||
#define NV_PFB_TIMING2 0x00000228
|
||||
#define NV_PFB_TILE 0x00000240
|
||||
#define NV_PFB_TLIMIT 0x00000244
|
||||
#define NV_PFB_TSIZE 0x00000248
|
||||
#define NV_PFB_TSTATUS 0x0000024C
|
||||
#define NV_PFB_TILE(i) 0x00000240 + (i * 0x10)
|
||||
#define NV_PFB_TLIMIT(i) 0x00000244 + (i * 0x10)
|
||||
#define NV_PFB_TSIZE(i) 0x00000248 + (i * 0x10)
|
||||
#define NV_PFB_TSTATUS(i) 0x0000024C + (i * 0x10)
|
||||
#define NV_PFB_MRS 0x000002C0
|
||||
#define NV_PFB_EMRS 0x000002C4
|
||||
#define NV_PFB_MRS_EXT 0x000002C8
|
||||
#define NV_PFB_EMRS_EXT 0x000002CC
|
||||
#define NV_PFB_REF 0x000002D0
|
||||
#define NV_PFB_PRE 0x000002D4
|
||||
#define NV_PFB_ZCOMP 0x00000300
|
||||
#define NV_PFB_ZCOMP(i) 0x00000300 + (i * 4)
|
||||
#define NV_PFB_ZCOMP_OFFSET 0x00000324
|
||||
#define NV_PFB_ARB_PREDIVIDER 0x00000328
|
||||
#define NV_PFB_ARB_TIMEOUT 0x0000032C
|
||||
#define NV_PFB_ARB_XFER_REM 0x00000334
|
||||
|
|
@ -632,6 +736,10 @@
|
|||
#define NV_PFB_CPU_RRQ 0x00000420
|
||||
#define NV_PFB_BYPASS 0x00000424
|
||||
|
||||
#define NV_PRAMIN_DMA_CLASS(i) 0x00000000 + (i * 0x10)
|
||||
#define NV_PRAMIN_DMA_LIMIT(i) 0x00000004 + (i * 0x10)
|
||||
#define NV_PRAMIN_DMA_START(i) 0x00000008 + (i * 0x10)
|
||||
#define NV_PRAMIN_DMA_ADDRESS(i) 0x0000000C + (i * 0x10)
|
||||
|
||||
#define NV_PRAMDAC_NVPLL_COEFF 0x00000500
|
||||
# define NV_PRAMDAC_NVPLL_COEFF_MDIV 0x000000FF
|
||||
|
|
@ -773,8 +881,84 @@
|
|||
# define NV097_SET_SURFACE_COLOR_OFFSET 0x00000210
|
||||
# define NV097_SET_SURFACE_ZETA_OFFSET 0x00000214
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW 0x00000260
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP 0xE0000000
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_UNSIGNED_IDENTITY 0
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_UNSIGNED_INVERT 1
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_EXPAND_NORMAL 2
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_EXPAND_NEGATE 3
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_HALFBIAS_NORMAL 4
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_HALFBIAS_NEGATE 5
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_SIGNED_IDENTITY 6
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_SIGNED_NEGATE 7
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_ALPHA (1<<28)
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_A_SOURCE 0x0F000000
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP 0x00E00000
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_UNSIGNED_IDENTITY 0
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_UNSIGNED_INVERT 1
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_EXPAND_NORMAL 2
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_EXPAND_NEGATE 3
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_HALFBIAS_NORMAL 4
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_HALFBIAS_NEGATE 5
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_SIGNED_IDENTITY 6
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_SIGNED_NEGATE 7
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_ALPHA (1<<20)
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_B_SOURCE 0x000F0000
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP 0x0000E000
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_UNSIGNED_IDENTITY 0
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_UNSIGNED_INVERT 1
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_EXPAND_NORMAL 2
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_EXPAND_NEGATE 3
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_HALFBIAS_NORMAL 4
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_HALFBIAS_NEGATE 5
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_SIGNED_IDENTITY 6
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_SIGNED_NEGATE 7
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_ALPHA (1<<12)
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_C_SOURCE 0x00000F00
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP 0x000000E0
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_UNSIGNED_IDENTITY 0
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_UNSIGNED_INVERT 1
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_EXPAND_NORMAL 2
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_EXPAND_NEGATE 3
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_HALFBIAS_NORMAL 4
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_HALFBIAS_NEGATE 5
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_SIGNED_IDENTITY 6
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_SIGNED_NEGATE 7
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_ALPHA (1<<4)
|
||||
# define NV097_SET_COMBINER_ALPHA_ICW_D_SOURCE 0x0000000F
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0 0x00000288
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_INVERSE 0xE0000000
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_ALPHA (1<<28)
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE 0x0F000000
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_SPECLIT 0xE
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_EF_PROD 0xF
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_INVERSE 0x00E00000
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_ALPHA (1<<20)
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE 0x000F0000
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_SPECLIT 0xE
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_EF_PROD 0xF
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_INVERSE 0x0000E000
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_ALPHA (1<<12)
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE 0x00000F00
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_SPECLIT 0xE
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_EF_PROD 0xF
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_INVERSE 0x000000E0
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_ALPHA (1<<4)
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE 0x0000000F
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_SPECLIT 0xE
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_EF_PROD 0xF
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1 0x0000028C
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_E_INVERSE 0xE0000000
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_E_ALPHA (1<<28)
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE 0x0F000000
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_F_INVERSE 0x00E00000
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_F_ALPHA (1<<20)
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE 0x000F0000
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_G_INVERSE 0x0000E000
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_G_ALPHA (1<<12)
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE 0x00000F00
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_CLAMP (1<<7)
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R5 (1<<6)
|
||||
# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R12 0x0000003F
|
||||
# define NV097_SET_CONTROL0 0x00000290
|
||||
# define NV097_SET_CONTROL0_STENCIL_WRITE_ENABLE (1 << 0)
|
||||
# define NV097_SET_CONTROL0_Z_FORMAT (1 << 12)
|
||||
|
|
@ -928,13 +1112,37 @@
|
|||
# define NV097_SET_TEXGEN_VIEW_MODEL_LOCAL_VIEWER 0
|
||||
# define NV097_SET_TEXGEN_VIEW_MODEL_INFINITE_VIEWER 1
|
||||
# define NV097_SET_FOG_PLANE 0x000009D0
|
||||
# define NV097_SET_FLAT_SHADE_OP 0x000009FC
|
||||
# define NV097_SET_SCENE_AMBIENT_COLOR 0x00000A10
|
||||
# define NV097_SET_VIEWPORT_OFFSET 0x00000A20
|
||||
# define NV097_SET_EYE_POSITION 0x00000A50
|
||||
# define NV097_SET_COMBINER_FACTOR0 0x00000A60
|
||||
# define NV097_SET_COMBINER_FACTOR1 0x00000A80
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW 0x00000AA0
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_OP 0xFFFF8000
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_OP_NOSHIFT 0
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_OP_NOSHIFT_BIAS 1
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTLEFTBY1 2
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTLEFTBY1_BIAS 3
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTLEFTBY2 4
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTRIGHTBY1 6
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_MUX_ENABLE (1<<14)
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_SUM_DST 0x00000F00
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_AB_DST 0x000000F0
|
||||
# define NV097_SET_COMBINER_ALPHA_OCW_CD_DST 0x0000000F
|
||||
# define NV097_SET_COMBINER_COLOR_ICW 0x00000AC0
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_A_MAP 0xE0000000
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_A_ALPHA (1<<28)
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_A_SOURCE 0x0F000000
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_B_MAP 0x00E00000
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_B_ALPHA (1<<20)
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_B_SOURCE 0x000F0000
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_C_MAP 0x0000E000
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_C_ALPHA (1<<12)
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_C_SOURCE 0x00000F00
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_D_MAP 0x000000E0
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_D_ALPHA (1<<4)
|
||||
# define NV097_SET_COMBINER_COLOR_ICW_D_SOURCE 0x0000000F
|
||||
# define NV097_SET_VIEWPORT_SCALE 0x00000AF0
|
||||
# define NV097_SET_TRANSFORM_PROGRAM 0x00000B00
|
||||
# define NV097_SET_TRANSFORM_CONSTANT 0x00000B80
|
||||
|
|
@ -1081,6 +1289,8 @@
|
|||
# define NV097_SET_TEXTURE_SET_BUMP_ENV_OFFSET 0x00001B3C
|
||||
# define NV097_SET_SEMAPHORE_OFFSET 0x00001D6C
|
||||
# define NV097_BACK_END_WRITE_SEMAPHORE_RELEASE 0x00001D70
|
||||
# define NV097_SET_ZMIN_MAX_CONTROL 0x00001D78
|
||||
# define NV097_SET_COMPRESS_ZBUFFER_EN 0x00001D80
|
||||
# define NV097_SET_ZSTENCIL_CLEAR_VALUE 0x00001D8C
|
||||
# define NV097_SET_COLOR_CLEAR_VALUE 0x00001D90
|
||||
# define NV097_CLEAR_SURFACE 0x00001D94
|
||||
|
|
@ -1095,13 +1305,118 @@
|
|||
# define NV097_SET_CLEAR_RECT_VERTICAL 0x00001D9C
|
||||
# define NV097_SET_SPECULAR_FOG_FACTOR 0x00001E20
|
||||
# define NV097_SET_COMBINER_COLOR_OCW 0x00001E40
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB 0xFFF80000
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB_DISABLE 0
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB_AB_DST_ENABLE 1
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD (1<<18)
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD_DISABLE 0
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD_CD_DST_ENABLE 1
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_OP 0x00038000
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_OP_NOSHIFT 0
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_OP_NOSHIFT_BIAS 1
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY1 2
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY1_BIAS 3
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY2 4
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTRIGHTBY1 6
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_MUX_ENABLE (1 << 14)
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_AB_DOT_ENABLE (1 << 13)
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_CD_DOT_ENABLE (1<<12)
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_SUM_DST 0x00000F00
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_AB_DST 0x000000F0
|
||||
# define NV097_SET_COMBINER_COLOR_OCW_CD_DST 0x0000000F
|
||||
# define NV097_SET_COMBINER_CONTROL 0x00001E60
|
||||
# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT 0x000000FF
|
||||
# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_ONE 1
|
||||
# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_TWO 2
|
||||
# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_THREE 3
|
||||
# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_FOUR 4
|
||||
# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_FIVE 5
|
||||
# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_SIX 6
|
||||
# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_SEVEN 7
|
||||
# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_EIGHT 8
|
||||
# define NV097_SET_COMBINER_CONTROL_MUX_SELECT 0x00000F00
|
||||
# define NV097_SET_COMBINER_CONTROL_MUX_SELECT_LSB 0
|
||||
# define NV097_SET_COMBINER_CONTROL_MUX_SELECT_MSB 1
|
||||
# define NV097_SET_COMBINER_CONTROL_FACTOR0 0x0000F000
|
||||
# define NV097_SET_COMBINER_CONTROL_FACTOR0_SAME_FACTOR_ALL 0
|
||||
# define NV097_SET_COMBINER_CONTROL_FACTOR0_EACH_STAGE 1
|
||||
# define NV097_SET_COMBINER_CONTROL_FACTOR1 0xFFFF0000
|
||||
# define NV097_SET_COMBINER_CONTROL_FACTOR1_SAME_FACTOR_ALL 0
|
||||
# define NV097_SET_COMBINER_CONTROL_FACTOR1_EACH_STAGE 1
|
||||
# define NV097_SET_SHADOW_ZSLOPE_THRESHOLD 0x00001E68
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM 0x00001E70
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0 0x0000001F
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_PROGRAM_NONE 0
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_2D_PROJECTIVE 1
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_3D_PROJECTIVE 2
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_CUBE_MAP 3
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_PASS_THROUGH 4
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_CLIP_PLANE 5
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1 0x000003E0
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_PROGRAM_NONE 0x00
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_2D_PROJECTIVE 0x01
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_3D_PROJECTIVE 0x02
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_CUBE_MAP 0x03
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_PASS_THROUGH 0x04
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_CLIP_PLANE 0x05
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_BUMPENVMAP 0x06
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_BUMPENVMAP_LUMINANCE 0x07
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_DEPENDENT_AR 0x0F
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_DEPENDENT_GB 0x10
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_DOT_PRODUCT 0x11
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2 0x00007C00
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_PROGRAM_NONE 0x00
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_2D_PROJECTIVE 0x01
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_3D_PROJECTIVE 0x02
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_CUBE_MAP 0x03
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_PASS_THROUGH 0x04
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_CLIP_PLANE 0x05
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_BUMPENVMAP 0x06
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_BUMPENVMAP_LUMINANCE 0x07
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_BRDF 0x08
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_ST 0x09
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_ZW 0x0A
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_REFLECT_DIFFUSE 0x0B
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DEPENDENT_AR 0x0F
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DEPENDENT_GB 0x10
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_PRODUCT 0x11
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3 0x000F8000
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_PROGRAM_NONE 0x00
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_2D_PROJECTIVE 0x01
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_3D_PROJECTIVE 0x02
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_CUBE_MAP 0x03
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_PASS_THROUGH 0x04
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_CLIP_PLANE 0x05
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_BUMPENVMAP 0x06
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_BUMPENVMAP_LUMINANCE 0x07
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_BRDF 0x08
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_ST 0x09
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_ZW 0x0A
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_REFLECT_SPECULAR 0x0C
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_STR_3D 0x0D
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_STR_CUBE 0x0E
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DEPENDENT_AR 0x0F
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DEPENDENT_GB 0x10
|
||||
# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_REFLECT_SPECULAR_CONST 0x12
|
||||
# define NV097_SET_SHADER_OTHER_STAGE_INPUT 0x00001E78
|
||||
# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE1 0x0000FFFF
|
||||
# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE1_INSTAGE_0 0
|
||||
# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2 0x000F0000
|
||||
# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2_INSTAGE_0 0
|
||||
# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2_INSTAGE_1 1
|
||||
# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3 0x00F00000
|
||||
# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_0 0
|
||||
# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_1 1
|
||||
# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_2 2
|
||||
# define NV097_SET_TRANSFORM_DATA 0x00001E80
|
||||
# define NV097_LAUNCH_TRANSFORM_PROGRAM 0x00001E90
|
||||
# define NV097_SET_TRANSFORM_EXECUTION_MODE 0x00001E94
|
||||
# define NV097_SET_TRANSFORM_EXECUTION_MODE_MODE 0x00000003
|
||||
# define NV097_SET_TRANSFORM_EXECUTION_MODE_MODE_FIXED 0
|
||||
# define NV097_SET_TRANSFORM_EXECUTION_MODE_MODE_PROGRAM 2
|
||||
# define NV097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE 0xFFFFFFFC
|
||||
# define NV097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE_USER 0
|
||||
# define NV097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE_PRIV 1
|
||||
# define NV097_SET_TRANSFORM_PROGRAM_CXT_WRITE_EN 0x00001E98
|
||||
# define NV097_SET_TRANSFORM_PROGRAM_LOAD 0x00001E9C
|
||||
# define NV097_SET_TRANSFORM_PROGRAM_START 0x00001EA0
|
||||
|
|
|
|||
Loading…
Reference in New Issue