More NV2A porting from XQEMU
Current Status: Official XDK titles deadlock while calling BlockOnTime. NXDK titles are generating render commands and appear to be working, although we do not actually implement pgraph yet, so we get a blank screen.
This commit is contained in:
Luke Usher
PatrickvL
parent
abdaf89602
commit
c9cc6eced0
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@ -339,7 +339,7 @@ typedef struct ChannelControl {
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struct {
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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uint32_t regs[NV_PMC_SIZE / sizeof(uint32_t)]; // TODO : union
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uint32_t regs[NV_PMC_SIZE]; // TODO : union
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} pmc;
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struct {
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@ -347,11 +347,11 @@ struct {
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uint32_t enabled_interrupts;
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std::thread puller_thread;
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Cache1State cache1;
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uint32_t regs[NV_PFIFO_SIZE / sizeof(uint32_t)]; // TODO : union
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uint32_t regs[NV_PFIFO_SIZE]; // TODO : union
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} pfifo;
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struct {
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uint32_t regs[NV_PVIDEO_SIZE / sizeof(uint32_t)]; // TODO : union
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uint32_t regs[NV_PVIDEO_SIZE]; // TODO : union
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} pvideo;
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@ -361,18 +361,18 @@ struct {
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uint32_t numerator;
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uint32_t denominator;
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uint32_t alarm_time;
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uint32_t regs[NV_PTIMER_SIZE / sizeof(uint32_t)]; // TODO : union
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uint32_t regs[NV_PTIMER_SIZE]; // TODO : union
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} ptimer;
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struct {
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uint32_t regs[NV_PFB_SIZE / sizeof(uint32_t)]; // TODO : union
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uint32_t regs[NV_PFB_SIZE]; // TODO : union
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} pfb;
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struct {
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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uint32_t start;
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uint32_t regs[NV_PCRTC_SIZE / sizeof(uint32_t)]; // TODO : union
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uint32_t regs[NV_PCRTC_SIZE]; // TODO : union
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} pcrtc;
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struct {
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@ -380,11 +380,11 @@ struct {
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uint64_t core_clock_freq;
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uint32_t memory_clock_coeff;
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uint32_t video_clock_coeff;
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uint32_t regs[NV_PRAMDAC_SIZE / sizeof(uint32_t)]; // TODO : union
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uint32_t regs[NV_PRAMDAC_SIZE]; // TODO : union
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} pramdac;
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struct {
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uint32_t regs[NV_PRAMIN_SIZE / sizeof(uint32_t)]; // TODO : union
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uint32_t regs[NV_PRAMIN_SIZE]; // TODO : union
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} pramin;
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struct {
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@ -494,7 +494,7 @@ struct {
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GLuint gl_memory_buffer;
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GLuint gl_vertex_array;
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uint32_t regs[NV_PGRAPH_SIZE / sizeof(uint32_t)]; // TODO : union
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uint32_t regs[NV_PGRAPH_SIZE]; // TODO : union
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} pgraph;
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static void update_irq()
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@ -846,11 +846,11 @@ DEBUG_START(USER)
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#define DEBUG_READ32(DEV) DbgPrintf("EmuX86 Read32 NV2A " #DEV "(0x%08X) = 0x%08X [Handled, %s]\n", addr, result, DebugNV_##DEV##(addr))
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#define DEBUG_READ32_UNHANDLED(DEV) { DbgPrintf("EmuX86 Read32 NV2A " #DEV "(0x%08X) = 0x%08X [Unhandled, %s]\n", addr, result, DebugNV_##DEV##(addr)); return result; }
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#define DEBUG_READ32(DEV) DbgPrintf("EmuX86 Read32 NV2A " #DEV "(0x%08X) = 0x%08X [Handle%s]\n", addr, result, DebugNV_##DEV##(addr))
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#define DEBUG_READ32_UNHANDLED(DEV) { DbgPrintf("EmuX86 Read32 NV2A " #DEV "(0x%08X) = 0x%08X [Unhandle%s]\n", addr, result, DebugNV_##DEV##(addr)); return result; }
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#define DEBUG_WRITE32(DEV) DbgPrintf("EmuX86 Write32 NV2A " #DEV "(0x%08X, 0x%08X) [Handled, %s]\n", addr, value, DebugNV_##DEV##(addr))
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#define DEBUG_WRITE32_UNHANDLED(DEV) { DbgPrintf("EmuX86 Write32 NV2A " #DEV "(0x%08X, 0x%08X) [Unhandled, %s]\n", addr, value, DebugNV_##DEV##(addr)); return; }
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#define DEBUG_WRITE32(DEV) DbgPrintf("EmuX86 Write32 NV2A " #DEV "(0x%08X, 0x%08X) [Handle%s]\n", addr, value, DebugNV_##DEV##(addr))
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#define DEBUG_WRITE32_UNHANDLED(DEV) { DbgPrintf("EmuX86 Write32 NV2A " #DEV "(0x%08X, 0x%08X) [Unhandle%s]\n", addr, value, DebugNV_##DEV##(addr)); return; }
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#define DEVICE_READ32(DEV) uint32_t EmuNV2A_##DEV##_Read32(xbaddr addr)
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#define DEVICE_READ32_SWITCH() uint32_t result = 0; switch (addr)
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@ -863,9 +863,7 @@ DEBUG_START(USER)
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static inline uint32_t ldl_le_p(const void *p)
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{
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uint32_t val;
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memcpy(&val, p, 4);
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return val;
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return *(uint32_t*)p;
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}
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static DMAObject nv_dma_load(xbaddr dma_obj_address)
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@ -1128,7 +1126,7 @@ static void pgraph_wait_fifo_access() {
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}
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}
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static void pgraph_method_log(unsigned int subchannel, unsigned int graphics_class,unsigned int method, uint32_t parameter) {
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static void pgraph_method_log(unsigned int subchannel, unsigned int graphics_class, unsigned int method, uint32_t parameter) {
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static unsigned int last = 0;
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static unsigned int count = 0;
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@ -1168,7 +1166,31 @@ static void pgraph_method_log(unsigned int subchannel, unsigned int graphics_cla
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last = method;
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}
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static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t parameter)
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static void load_graphics_object(xbaddr instance_address, GraphicsObject *obj)
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{
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uint8_t *obj_ptr;
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uint32_t switch1, switch2, switch3;
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assert(instance_address < NV_PRAMIN_SIZE);
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obj_ptr = (uint8_t*)(NV2A_ADDR + NV_PRAMIN_ADDR + instance_address);
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switch1 = ldl_le_p((uint32_t*)obj_ptr);
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switch2 = ldl_le_p((uint32_t*)(obj_ptr + 4));
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switch3 = ldl_le_p((uint32_t*)(obj_ptr + 8));
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obj->graphics_class = switch1 & NV_PGRAPH_CTX_SWITCH1_GRCLASS;
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/* init graphics object */
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switch (obj->graphics_class) {
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case NV_KELVIN_PRIMITIVE:
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// kelvin->vertex_attributes[NV2A_VERTEX_ATTR_DIFFUSE].inline_value = 0xFFFFFFF;
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break;
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default:
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break;
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}
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}
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static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t parameter)
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{
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std::lock_guard<std::mutex> lk(pgraph.mutex);
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@ -1182,12 +1204,27 @@ static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t
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subchannel_data = &pgraph.subchannel_data[subchannel];
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object = &subchannel_data->object;
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ContextSurfaces2DState *context_surfaces_2d = &object->data.context_surfaces_2d;
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ContextSurfaces2DState *context_surfaces_2d = &object->data.context_surfaces_2d;
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ImageBlitState *image_blit = &object->data.image_blit;
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KelvinState *kelvin = &object->data.kelvin;
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printf("PGRAPH METHOD!\n");
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pgraph_method_log(subchannel, object->graphics_class, method, parameter);
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if (method == NV_SET_OBJECT) {
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subchannel_data->object_instance = parameter;
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//qemu_mutex_lock_iothread();
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load_graphics_object(parameter, object);
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//qemu_mutex_unlock_iothread();
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return;
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}
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switch (object->graphics_class) {
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default:
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EmuWarning("EmuNV2A: Unknown Graphics Class/Method 0x%08Xm 0x%08X\n", object->graphics_class, method);
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break;
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}
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}
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static void* pfifo_puller_thread()
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@ -1669,14 +1706,11 @@ DEVICE_READ32(PTIMER)
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case NV_PTIMER_INTR_EN_0:
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result = ptimer.enabled_interrupts;
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break;
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case NV_PTIMER_DENOMINATOR:
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result = ptimer.denominator;
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break;
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case NV_PTIMER_NUMERATOR:
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result = ptimer.numerator;
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break;
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case NV_PTIMER_ALARM_0:
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result = ptimer.alarm_time;
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case NV_PTIMER_DENOMINATOR:
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result = ptimer.denominator;
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break;
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case NV_PTIMER_TIME_0:
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result = (ptimer_get_clock() & 0x7ffffff) << 5;
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@ -2083,7 +2117,7 @@ DEVICE_READ32(PRAMDAC)
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break;
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default:
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DEVICE_READ32_REG(pramdac); // Was : DEBUG_READ32_UNHANDLED(PRAMDAC);
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//DEVICE_READ32_REG(pramdac); // Was : DEBUG_READ32_UNHANDLED(PRAMDAC);
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break;
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}
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@ -2119,7 +2153,7 @@ DEVICE_WRITE32(PRAMDAC)
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break;
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default:
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DEVICE_WRITE32_REG(pramdac); // Was : DEBUG_WRITE32_UNHANDLED(PRAMDAC);
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//DEVICE_WRITE32_REG(pramdac); // Was : DEBUG_WRITE32_UNHANDLED(PRAMDAC);
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break;
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}
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@ -704,6 +704,7 @@
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# define NV062_SET_CONTEXT_DMA_IMAGE_DESTIN 0x00000188
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# define NV062_SET_COLOR_FORMAT 0x00000300
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# define NV062_SET_COLOR_FORMAT_LE_Y8 0x01
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# define NV062_SET_COLOR_FORMAT_LE_R5G6B5 0x04
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# define NV062_SET_COLOR_FORMAT_LE_A8R8G8B8 0x0A
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# define NV062_SET_PITCH 0x00000304
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# define NV062_SET_OFFSET_SOURCE 0x00000308
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