NV2A : Construct unique_lock mutex wrappers once (and avoid any other use of the mutex'es)
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@ -540,7 +540,7 @@ void TriggerPendingConnectedInterrupts()
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{
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for (int i = 0; i < MAX_BUS_INTERRUPT_LEVEL; i++) {
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// If the interrupt is pending and connected, process it
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if (HalSystemInterrupts[i].IsPending() && EmuInterruptList[i]->Connected) {
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if (HalSystemInterrupts[i].IsPending() && EmuInterruptList[i] && EmuInterruptList[i]->Connected) {
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HalSystemInterrupts[i].Trigger(EmuInterruptList[i]);
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}
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}
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@ -362,10 +362,8 @@ int pfifo_puller_thread(NV2AState *d)
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while (true) {
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state->cache_lock.lock();
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std::unique_lock<std::mutex> _cache_lock(state->cache_lock); // TODO : Is this correct??
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while (state->cache.empty() || !state->pull_enabled) {
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state->cache_cond.wait(_cache_lock);
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state->cache_cond.wait(state->cache_lock);
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}
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// Copy cache to working_cache
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@ -713,10 +713,8 @@ static void pgraph_method(NV2AState *d,
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pg->lock.lock();
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qemu_mutex_unlock_iothread();
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std::unique_lock<std::mutex> _lock(pg->lock); // TODO : Is this correct??
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while (pg->pending_interrupts & NV_PGRAPH_INTR_ERROR) {
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pg->interrupt_cond.wait(_lock);
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pg->interrupt_cond.wait(pg->lock);
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}
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}
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break;
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@ -786,9 +784,8 @@ static void pgraph_method(NV2AState *d,
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!= GET_MASK(s, NV_PGRAPH_SURFACE_WRITE_3D)) {
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break;
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}
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std::unique_lock<std::mutex> _lock(pg->lock); // TODO : Is this correct??
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pg->flip_3d.wait(_lock);
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pg->flip_3d.wait(pg->lock);
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}
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NV2A_DPRINTF("flip stall done\n");
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break;
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@ -2602,19 +2599,15 @@ static void pgraph_context_switch(NV2AState *d, unsigned int channel_id)
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d->pgraph.lock.lock();
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qemu_mutex_unlock_iothread();
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std::unique_lock<std::mutex> _lock(d->pgraph.lock); // TODO : Is this correct??
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while (d->pgraph.pending_interrupts & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
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d->pgraph.interrupt_cond.wait(_lock);
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d->pgraph.interrupt_cond.wait(d->pgraph.lock);
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}
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}
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}
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static void pgraph_wait_fifo_access(NV2AState *d) {
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std::unique_lock<std::mutex> _lock(d->pgraph.lock); // TODO : Is this correct??
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while (!d->pgraph.fifo_access) {
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d->pgraph.fifo_access_cond.wait(_lock);
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d->pgraph.fifo_access_cond.wait(d->pgraph.lock);
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}
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}
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@ -615,6 +615,12 @@ void CxbxReserveNV2AMemory(NV2AState *d)
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/* NV2ADevice */
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NV2ADevice::NV2ADevice()
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{
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m_nv2a_state.pfifo.cache1.cache_lock = std::unique_lock<std::mutex>(m_nv2a_state.pfifo.cache1._cache_lock, std::defer_lock);
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m_nv2a_state.pgraph.lock = std::unique_lock<std::mutex>(m_nv2a_state.pgraph._lock, std::defer_lock);
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}
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// PCI Device functions
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void NV2ADevice::Init()
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@ -293,7 +293,8 @@ typedef struct GraphicsContext {
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typedef struct PGRAPHState {
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std::mutex lock; // std::unique_lock<std::mutex>(lock, std::defer_lock);
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std::mutex _lock;
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std::unique_lock<std::mutex> lock;
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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@ -436,7 +437,8 @@ typedef struct Cache1State {
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enum FIFOEngine last_engine;
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/* The actual command queue */
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std::mutex cache_lock; // std::unique_lock<std::mutex>(cache_lock, std::defer_lock);
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std::mutex _cache_lock;
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std::unique_lock<std::mutex> cache_lock;
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std::condition_variable cache_cond;
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std::queue<CacheEntry*> cache;
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std::queue<CacheEntry*> working_cache;
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@ -611,6 +613,9 @@ void InitOpenGLContext();
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class NV2ADevice : public PCIDevice {
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public:
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// constructor
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NV2ADevice();
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// PCI Device functions
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void Init();
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void Reset();
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