Added CLI and STI instruction support to EmuX86. Fixes a crash in ohci dpc routine

This commit is contained in:
ergo720 2018-07-23 11:52:20 +02:00
parent f31b57830e
commit a70aab8fa6
3 changed files with 43 additions and 4 deletions

View File

@ -108,6 +108,9 @@ bool g_bIsRetail = false;
DWORD_PTR g_CPUXbox = 0;
DWORD_PTR g_CPUOthers = 0;
// Indicates to enable/disable all interrupts when cli and sti instructions are executed
std::atomic_bool g_bEnableAllInterrupts = true;
// Set by the VMManager during initialization. Exported because it's needed in other parts of the emu
size_t g_SystemMaxMemory = 0;
@ -668,7 +671,7 @@ static unsigned int WINAPI CxbxKrnlInterruptThread(PVOID param)
InitSoftwareInterrupts();
#endif
while (true) {
while (g_bEnableAllInterrupts) {
TriggerPendingConnectedInterrupts();
Sleep(1);
}

View File

@ -52,9 +52,11 @@
#include "HLEIntercept.h" // for bLLE_GPU
#include <assert.h>
#include "devices\Xbox.h" // For g_PCIBus
#include "devices\Xbox.h" // For g_PCIBus
#include <atomic>
extern uint32_t GetAPUTime();
extern uint32_t GetAPUTime();
extern std::atomic_bool g_bEnableAllInterrupts;
//
// Read & write handlers handlers for I/O
@ -1010,6 +1012,16 @@ bool EmuX86_Opcode_TEST(LPEXCEPTION_POINTERS e, _DInst& info)
// result is thrown away
return true;
}
void EmuX86_Opcode_CLI()
{
g_bEnableAllInterrupts = false;
}
void EmuX86_Opcode_STI()
{
g_bEnableAllInterrupts = true;
}
bool EmuX86_DecodeOpcode(const uint8_t *Eip, _DInst &info)
@ -1115,7 +1127,17 @@ bool EmuX86_DecodeException(LPEXCEPTION_POINTERS e)
// This needs fixing eventually, but should be acceptible to ignore for now!
// Chase: Hollywood Stunt Driver hits this
EmuWarning("WRMSR instruction ignored");
break;
break;
case I_CLI: {
// Disable all interrupts
EmuX86_Opcode_CLI();
break;
}
case I_STI: {
// Enable all interrupts
EmuX86_Opcode_STI();
break;
}
default:
EmuWarning("Unhandled instruction : %u", info.opcode);
e->ContextRecord->Eip += info.size;

View File

@ -1090,6 +1090,14 @@ uint32_t OHCI::OHCI_ReadRegister(xbaddr Addr)
case 22: // RhPort 1
ret = m_Registers.RhPort[1].HcRhPortStatus | OHCI_PORT_PPS;
break;
case 23:
ret = 0;
break;
case 24:
ret = 0;
break;
default:
@ -1221,6 +1229,12 @@ void OHCI::OHCI_WriteRegister(xbaddr Addr, uint32_t Value)
case 22: // RhPort 1
OHCI_PortSetStatus(1, Value);
break;
case 23:
break;
case 24:
break;
default: