diff --git a/build/win32/Cxbx.vcxproj b/build/win32/Cxbx.vcxproj
index 1ad605219..d55126b81 100644
--- a/build/win32/Cxbx.vcxproj
+++ b/build/win32/Cxbx.vcxproj
@@ -293,6 +293,7 @@
+
diff --git a/build/win32/Cxbx.vcxproj.filters b/build/win32/Cxbx.vcxproj.filters
index 99e3a8c4a..7cb8b66f3 100644
--- a/build/win32/Cxbx.vcxproj.filters
+++ b/build/win32/Cxbx.vcxproj.filters
@@ -808,4 +808,9 @@
+
+
+ Hardware\Video
+
+
\ No newline at end of file
diff --git a/src/core/HLE/D3D8/Direct3D9/Direct3D9.cpp b/src/core/HLE/D3D8/Direct3D9/Direct3D9.cpp
index 6960aea7c..b1fa981d7 100644
--- a/src/core/HLE/D3D8/Direct3D9/Direct3D9.cpp
+++ b/src/core/HLE/D3D8/Direct3D9/Direct3D9.cpp
@@ -2377,7 +2377,7 @@ static void EmuVerifyResourceIsRegistered(XTL::X_D3DResource *pResource, DWORD D
typedef struct {
DWORD Hash = 0;
- DWORD IndexCount = 0;;
+ DWORD IndexCount = 0;
XTL::IDirect3DIndexBuffer* pHostIndexBuffer = nullptr;
} ConvertedIndexBuffer;
@@ -4870,7 +4870,7 @@ void CreateHostResource(XTL::X_D3DResource *pResource, DWORD D3DUsage, int iText
// If, and ONLY if this is the default backbuffer, make sure the format matches the host backbuffer
if (pResource == g_XboxBackBufferSurface) {
- PCFormat = g_EmuCDPD.HostPresentationParameters.BackBufferFormat;;
+ PCFormat = g_EmuCDPD.HostPresentationParameters.BackBufferFormat;
}
}
else {
@@ -8541,7 +8541,7 @@ HRESULT WINAPI XTL::EMUPATCH(D3DDevice_SetDepthClipPlanes)
break;
default:
- EmuLog(LOG_PREFIX, LOG_LEVEL::WARNING, "Unknown SetDepthClipPlanes Flags provided");;
+ EmuLog(LOG_PREFIX, LOG_LEVEL::WARNING, "Unknown SetDepthClipPlanes Flags provided");
}
// TODO
diff --git a/src/core/HLE/D3D8/XbPushBuffer.cpp b/src/core/HLE/D3D8/XbPushBuffer.cpp
index c5019eb73..15bfa7482 100644
--- a/src/core/HLE/D3D8/XbPushBuffer.cpp
+++ b/src/core/HLE/D3D8/XbPushBuffer.cpp
@@ -449,7 +449,8 @@ extern void XTL::EmuExecutePushBufferRaw
// Retrieve NV2AState via the (LLE) NV2A device :
NV2AState *d = g_NV2A->GetDeviceState();
- d->pgraph.channel_valid = true; // avoid assert
+ d->pgraph.regs[NV_PGRAPH_CTX_CONTROL] |= NV_PGRAPH_CTX_CONTROL_CHID; // avoid assert in pgraph_handle_method()
+
// DMA Pusher state -- see https://envytools.readthedocs.io/en/latest/hw/fifo/dma-pusher.html#pusher-state
#if 0
diff --git a/src/core/HLE/D3D8/XbVertexShader.cpp b/src/core/HLE/D3D8/XbVertexShader.cpp
index 82df11195..dc564ec80 100644
--- a/src/core/HLE/D3D8/XbVertexShader.cpp
+++ b/src/core/HLE/D3D8/XbVertexShader.cpp
@@ -905,7 +905,7 @@ static void VshWriteShader(VSH_XBOX_SHADER *pShader,
}
i++;
- } while (i < RegVUsage.size());;
+ } while (i < RegVUsage.size());
}
for (int i = 0; i < pShader->IntermediateCount && (i < VSH_MAX_INSTRUCTION_COUNT || !Truncate); i++)
diff --git a/src/core/HLE/DSOUND/DirectSound/DirectSound.cpp b/src/core/HLE/DSOUND/DirectSound/DirectSound.cpp
index db356c68d..067243ecf 100644
--- a/src/core/HLE/DSOUND/DirectSound/DirectSound.cpp
+++ b/src/core/HLE/DSOUND/DirectSound/DirectSound.cpp
@@ -1839,7 +1839,7 @@ HRESULT WINAPI XTL::EMUPATCH(IDirectSound_CreateSoundStream)
LOG_FUNC_ARG(pUnknown)
LOG_FUNC_END;
- return EMUPATCH(DirectSoundCreateStream)(pdssd, ppStream);;
+ return EMUPATCH(DirectSoundCreateStream)(pdssd, ppStream);
}
// ******************************************************************
diff --git a/src/core/HLE/XAPI/Xapi.cpp b/src/core/HLE/XAPI/Xapi.cpp
index 6663fcae4..4b95063ed 100644
--- a/src/core/HLE/XAPI/Xapi.cpp
+++ b/src/core/HLE/XAPI/Xapi.cpp
@@ -864,11 +864,11 @@ void EmuSBCGetState(XTL::PX_SBC_GAMEPAD pSBCGamepad, XTL::PX_XINPUT_GAMEPAD pXIG
// Analog Sticks
- pSBCGamepad->sAimingX = pXIGamepad->sThumbRX;;
- pSBCGamepad->sAimingY = pXIGamepad->sThumbRY;;
+ pSBCGamepad->sAimingX = pXIGamepad->sThumbRX;
+ pSBCGamepad->sAimingY = pXIGamepad->sThumbRY;
pSBCGamepad->sRotationLever = 0;//(pXIGamepad->wButtons & XINPUT_GAMEPAD_LEFT_SHOULDER) ? 255 : 0;
- pSBCGamepad->sSightChangeX = pXIGamepad->sThumbLX;;
- pSBCGamepad->sSightChangeY = pXIGamepad->sThumbLY;;
+ pSBCGamepad->sSightChangeX = pXIGamepad->sThumbLX;
+ pSBCGamepad->sSightChangeY = pXIGamepad->sThumbLY;
pSBCGamepad->wLeftPedal = ((SHORT)(pXIGamepad->bAnalogButtons[X_XINPUT_GAMEPAD_LEFT_TRIGGER]))<<8;
pSBCGamepad->wMiddlePedal=0;// = (pXIGamepad->wButtons & XINPUT_GAMEPAD_RIGHT_SHOULDER) ? 255 : 0;
pSBCGamepad->wRightPedal = (SHORT)(pXIGamepad->bAnalogButtons[X_XINPUT_GAMEPAD_RIGHT_TRIGGER])<<8;
diff --git a/src/devices/video/EmuNV2A_DEBUG.cpp b/src/devices/video/EmuNV2A_DEBUG.cpp
index cac08307f..5dac1bc48 100644
--- a/src/devices/video/EmuNV2A_DEBUG.cpp
+++ b/src/devices/video/EmuNV2A_DEBUG.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/tree/master/hw/xbox/nv2a/nv2a_debug.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
@@ -134,6 +137,8 @@ DEBUG_START(PFIFO)
DEBUG_CASE(NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW);
DEBUG_CASE(NV_PFIFO_CACHE1_DMA_RSVD_SHADOW);
DEBUG_CASE(NV_PFIFO_CACHE1_DMA_DATA_SHADOW);
+ DEBUG_CASE(NV_PFIFO_CACHE1_METHOD);
+ DEBUG_CASE(NV_PFIFO_CACHE1_DATA);
DEBUG_END(PFIFO)
// TODO: Remove disabled warning once case are add to PRMA switch.
@@ -322,6 +327,12 @@ DEBUG_START(PGRAPH)
DEBUG_CASE(NV_PGRAPH_CTX_SWITCH2);
DEBUG_CASE(NV_PGRAPH_CTX_SWITCH3);
DEBUG_CASE(NV_PGRAPH_CTX_SWITCH4);
+ DEBUG_CASE(NV_PGRAPH_CTX_SWITCH5);
+ DEBUG_CASE(NV_PGRAPH_CTX_CACHE1);
+ DEBUG_CASE(NV_PGRAPH_CTX_CACHE2);
+ DEBUG_CASE(NV_PGRAPH_CTX_CACHE3);
+ DEBUG_CASE(NV_PGRAPH_CTX_CACHE4);
+ DEBUG_CASE(NV_PGRAPH_CTX_CACHE5);
DEBUG_CASE(NV_PGRAPH_STATUS);
DEBUG_CASE(NV_PGRAPH_TRAPPED_ADDR);
DEBUG_CASE(NV_PGRAPH_TRAPPED_DATA_LOW);
@@ -378,6 +389,7 @@ DEBUG_START(PGRAPH)
DEBUG_CASE(NV_PGRAPH_ZCOMP_OFFSET);
DEBUG_CASE(NV_PGRAPH_FBCFG0);
DEBUG_CASE(NV_PGRAPH_FBCFG1);
+ DEBUG_CASE(NV_PGRAPH_PATT_COLOR0);
DEBUG_CASE(NV_PGRAPH_DEBUG_6);
DEBUG_CASE(NV_PGRAPH_DEBUG_7);
DEBUG_CASE(NV_PGRAPH_DEBUG_10);
@@ -386,6 +398,7 @@ DEBUG_START(PGRAPH)
DEBUG_CASE(NV_PGRAPH_CSV1_B);
DEBUG_CASE(NV_PGRAPH_CSV1_A);
DEBUG_CASE(NV_PGRAPH_CHEOPS_OFFSET);
+ DEBUG_CASE(NV_PGRAPH_DMA_STATE);
DEBUG_CASE(NV_PGRAPH_BLEND);
DEBUG_CASE(NV_PGRAPH_BLENDCOLOR);
DEBUG_CASE(NV_PGRAPH_BORDERCOLOR0);
@@ -407,6 +420,7 @@ DEBUG_START(PGRAPH)
DEBUG_CASE(NV_PGRAPH_COMBINESPECFOG0);
DEBUG_CASE(NV_PGRAPH_COMBINESPECFOG1);
DEBUG_CASE(NV_PGRAPH_CONTROL_0);
+ DEBUG_CASE(NV_PGRAPH_CONTROL_1);
DEBUG_CASE(NV_PGRAPH_CONTROL_2);
DEBUG_CASE(NV_PGRAPH_CONTROL_3);
DEBUG_CASE(NV_PGRAPH_FOGCOLOR);
@@ -416,6 +430,7 @@ DEBUG_START(PGRAPH)
DEBUG_CASE(NV_PGRAPH_SHADERCLIPMODE);
DEBUG_CASE(NV_PGRAPH_SHADERCTL);
DEBUG_CASE(NV_PGRAPH_SHADERPROG);
+ DEBUG_CASE(NV_PGRAPH_SEMAPHOREOFFSET);
DEBUG_CASE(NV_PGRAPH_SHADOWZSLOPETHRESHOLD);
DEBUG_CASE(NV_PGRAPH_SPECFOGFACTOR0);
DEBUG_CASE(NV_PGRAPH_SPECFOGFACTOR1);
@@ -453,6 +468,22 @@ DEBUG_START(PGRAPH)
DEBUG_CASE(NV_PGRAPH_TEXPALETTE1);
DEBUG_CASE(NV_PGRAPH_TEXPALETTE2);
DEBUG_CASE(NV_PGRAPH_TEXPALETTE3);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPX0);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPX1);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPX2);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPX3);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPX4);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPX5);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPX6);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPX7);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPY0);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPY1);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPY2);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPY3);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPY4);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPY5);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPY6);
+ DEBUG_CASE(NV_PGRAPH_WINDOWCLIPY7);
DEBUG_CASE(NV_PGRAPH_ZSTENCILCLEARVALUE);
DEBUG_CASE(NV_PGRAPH_ZCLIPMIN);
DEBUG_CASE(NV_PGRAPH_ZOFFSETBIAS);
diff --git a/src/devices/video/EmuNV2A_PBUS.cpp b/src/devices/video/EmuNV2A_PBUS.cpp
index dac79600f..323be6ec9 100644
--- a/src/devices/video/EmuNV2A_PBUS.cpp
+++ b/src/devices/video/EmuNV2A_PBUS.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/tree/master/hw/xbox/nv2a/nv2a_pbus.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PCOUNTER.cpp b/src/devices/video/EmuNV2A_PCOUNTER.cpp
index 7b0014980..7e493e45d 100644
--- a/src/devices/video/EmuNV2A_PCOUNTER.cpp
+++ b/src/devices/video/EmuNV2A_PCOUNTER.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_stubs.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PCRTC.cpp b/src/devices/video/EmuNV2A_PCRTC.cpp
index eb57ba9f3..cbf9df07f 100644
--- a/src/devices/video/EmuNV2A_PCRTC.cpp
+++ b/src/devices/video/EmuNV2A_PCRTC.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/tree/master/hw/xbox/nv2a/nv2a_pcrtc.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PFB.cpp b/src/devices/video/EmuNV2A_PFB.cpp
index 75dc2ea30..ebb56e3bd 100644
--- a/src/devices/video/EmuNV2A_PFB.cpp
+++ b/src/devices/video/EmuNV2A_PFB.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_pfb.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PFIFO.cpp b/src/devices/video/EmuNV2A_PFIFO.cpp
index ab188b75d..2ce86bb79 100644
--- a/src/devices/video/EmuNV2A_PFIFO.cpp
+++ b/src/devices/video/EmuNV2A_PFIFO.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_pfifo.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
@@ -47,14 +50,13 @@ typedef struct RAMHTEntry {
bool valid;
} RAMHTEntry;
-static void pfifo_run_pusher(NV2AState *d); // forward declaration
-int pfifo_puller_thread(NV2AState *d);
-static uint32_t ramht_hash(NV2AState *d, uint32_t handle);
static RAMHTEntry ramht_lookup(NV2AState *d, uint32_t handle); // forward declaration
/* PFIFO - MMIO and DMA FIFO submission to PGRAPH and VPE */
DEVICE_READ32(PFIFO)
{
+ qemu_mutex_lock(&d->pfifo.pfifo_lock);
+
DEVICE_READ32_SWITCH() {
case NV_PFIFO_RAMHT:
result = 0x03000100; // = NV_PFIFO_RAMHT_SIZE_4K | NV_PFIFO_RAMHT_BASE_ADDRESS(NumberOfPaddingBytes >> 12) | NV_PFIFO_RAMHT_SEARCH_128
@@ -71,94 +73,19 @@ DEVICE_READ32(PFIFO)
case NV_PFIFO_RUNOUT_STATUS:
result = NV_PFIFO_RUNOUT_STATUS_LOW_MARK; /* low mark empty */
break;
- case NV_PFIFO_CACHE1_PUSH0:
- result = d->pfifo.cache1.push_enabled;
- break;
- case NV_PFIFO_CACHE1_PUSH1:
- SET_MASK(result, NV_PFIFO_CACHE1_PUSH1_CHID, d->pfifo.cache1.channel_id);
- SET_MASK(result, NV_PFIFO_CACHE1_PUSH1_MODE, d->pfifo.cache1.mode);
- break;
- case NV_PFIFO_CACHE1_STATUS: {
- qemu_mutex_lock(&d->pfifo.cache1.cache_lock);
-
- if (d->pfifo.cache1.cache.empty()) {
- result |= NV_PFIFO_CACHE1_STATUS_LOW_MARK; /* low mark empty */
- }
-
- qemu_mutex_unlock(&d->pfifo.cache1.cache_lock);
- break;
- }
- case NV_PFIFO_CACHE1_DMA_PUSH:
- SET_MASK(result, NV_PFIFO_CACHE1_DMA_PUSH_ACCESS,
- d->pfifo.cache1.dma_push_enabled);
- SET_MASK(result, NV_PFIFO_CACHE1_DMA_PUSH_STATUS,
- d->pfifo.cache1.dma_push_suspended);
- SET_MASK(result, NV_PFIFO_CACHE1_DMA_PUSH_BUFFER, 1); /* buffer emoty */
- break;
- case NV_PFIFO_CACHE1_DMA_STATE:
- SET_MASK(result, NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE,
- d->pfifo.cache1.method_nonincreasing);
- SET_MASK(result, NV_PFIFO_CACHE1_DMA_STATE_METHOD,
- d->pfifo.cache1.method >> 2);
- SET_MASK(result, NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL,
- d->pfifo.cache1.subchannel);
- SET_MASK(result, NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT,
- d->pfifo.cache1.method_count);
- SET_MASK(result, NV_PFIFO_CACHE1_DMA_STATE_ERROR,
- d->pfifo.cache1.error);
- break;
- case NV_PFIFO_CACHE1_DMA_INSTANCE:
- SET_MASK(result, NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MASK,
- d->pfifo.cache1.dma_instance >> 4);
- break;
- case NV_PFIFO_CACHE1_DMA_PUT:
- result = d->user.channel_control[d->pfifo.cache1.channel_id].dma_put;
- break;
- case NV_PFIFO_CACHE1_DMA_GET:
- result = d->user.channel_control[d->pfifo.cache1.channel_id].dma_get;
- break;
- case NV_PFIFO_CACHE1_DMA_SUBROUTINE:
- result = d->pfifo.cache1.subroutine_return
- | (xbaddr)d->pfifo.cache1.subroutine_active;
- break;
- case NV_PFIFO_CACHE1_PULL0: {
- qemu_mutex_lock(&d->pfifo.cache1.cache_lock);
- result = d->pfifo.cache1.pull_enabled;
- qemu_mutex_unlock(&d->pfifo.cache1.cache_lock);
- break;
- }
- case NV_PFIFO_CACHE1_ENGINE: {
- qemu_mutex_lock(&d->pfifo.cache1.cache_lock);
-
- for (int i = 0; i < NV2A_NUM_SUBCHANNELS; i++) {
- result |= d->pfifo.cache1.bound_engines[i] << (i * 2);
- }
- qemu_mutex_unlock(&d->pfifo.cache1.cache_lock);
- break;
- }
- case NV_PFIFO_CACHE1_DMA_DCOUNT:
- result = d->pfifo.cache1.dcount;
- break;
- case NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW:
- result = d->pfifo.cache1.get_jmp_shadow;
- break;
- case NV_PFIFO_CACHE1_DMA_RSVD_SHADOW:
- result = d->pfifo.cache1.rsvd_shadow;
- break;
- case NV_PFIFO_CACHE1_DMA_DATA_SHADOW:
- result = d->pfifo.cache1.data_shadow;
- break;
default:
DEVICE_READ32_REG(pfifo); // Was : DEBUG_READ32_UNHANDLED(PFIFO);
break;
}
+ qemu_mutex_unlock(&d->pfifo.pfifo_lock);
+
DEVICE_READ32_END(PFIFO);
}
DEVICE_WRITE32(PFIFO)
{
- int i;
+ qemu_mutex_lock(&d->pfifo.pfifo_lock);
switch(addr) {
case NV_PFIFO_INTR_0:
@@ -169,356 +96,383 @@ DEVICE_WRITE32(PFIFO)
d->pfifo.enabled_interrupts = value;
update_irq(d);
break;
- case NV_PFIFO_CACHE1_PUSH0:
- d->pfifo.cache1.push_enabled = value & NV_PFIFO_CACHE1_PUSH0_ACCESS;
- break;
- case NV_PFIFO_CACHE1_PUSH1:
- d->pfifo.cache1.channel_id = GET_MASK(value, NV_PFIFO_CACHE1_PUSH1_CHID);
- d->pfifo.cache1.mode = (FifoMode)GET_MASK(value, NV_PFIFO_CACHE1_PUSH1_MODE);
- assert(d->pfifo.cache1.channel_id < NV2A_NUM_CHANNELS);
- break;
- case NV_PFIFO_CACHE1_DMA_PUSH:
- d->pfifo.cache1.dma_push_enabled =
- GET_MASK(value, NV_PFIFO_CACHE1_DMA_PUSH_ACCESS);
- if (d->pfifo.cache1.dma_push_suspended
- && !GET_MASK(value, NV_PFIFO_CACHE1_DMA_PUSH_STATUS)) {
- d->pfifo.cache1.dma_push_suspended = false;
- pfifo_run_pusher(d);
- }
- d->pfifo.cache1.dma_push_suspended =
- GET_MASK(value, NV_PFIFO_CACHE1_DMA_PUSH_STATUS);
- break;
- case NV_PFIFO_CACHE1_DMA_STATE:
- d->pfifo.cache1.method_nonincreasing =
- GET_MASK(value, NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE);
- d->pfifo.cache1.method =
- GET_MASK(value, NV_PFIFO_CACHE1_DMA_STATE_METHOD) << 2;
- d->pfifo.cache1.subchannel =
- GET_MASK(value, NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL);
- d->pfifo.cache1.method_count =
- GET_MASK(value, NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT);
- d->pfifo.cache1.error =
- GET_MASK(value, NV_PFIFO_CACHE1_DMA_STATE_ERROR);
- break;
- case NV_PFIFO_CACHE1_DMA_INSTANCE:
- d->pfifo.cache1.dma_instance =
- GET_MASK(value, NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MASK) << 4;
- break;
- case NV_PFIFO_CACHE1_DMA_PUT:
- d->user.channel_control[d->pfifo.cache1.channel_id].dma_put = value;
- break;
- case NV_PFIFO_CACHE1_DMA_GET:
- d->user.channel_control[d->pfifo.cache1.channel_id].dma_get = value;
- break;
- case NV_PFIFO_CACHE1_DMA_SUBROUTINE:
- d->pfifo.cache1.subroutine_return =
- (value & NV_PFIFO_CACHE1_DMA_SUBROUTINE_RETURN_OFFSET);
- d->pfifo.cache1.subroutine_active =
- (value & NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE);
- break;
- case NV_PFIFO_CACHE1_PULL0: {
- qemu_mutex_lock(&d->pfifo.cache1.cache_lock);
-
- if ((value & NV_PFIFO_CACHE1_PULL0_ACCESS)
- && !d->pfifo.cache1.pull_enabled) {
- d->pfifo.cache1.pull_enabled = true;
-
- /* the puller thread should wake up */
- qemu_cond_signal(&d->pfifo.cache1.cache_cond);
- }
- else if (!(value & NV_PFIFO_CACHE1_PULL0_ACCESS)
- && d->pfifo.cache1.pull_enabled) {
- d->pfifo.cache1.pull_enabled = false;
- }
-
- qemu_mutex_unlock(&d->pfifo.cache1.cache_lock);
- break;
- }
- case NV_PFIFO_CACHE1_ENGINE: {
- qemu_mutex_lock(&d->pfifo.cache1.cache_lock);
-
- for (i = 0; i < NV2A_NUM_SUBCHANNELS; i++) {
- d->pfifo.cache1.bound_engines[i] = (FIFOEngine)((value >> (i * 2)) & 3);
- }
-
- qemu_mutex_unlock(&d->pfifo.cache1.cache_lock);
- break;
- }
- case NV_PFIFO_CACHE1_DMA_DCOUNT:
- d->pfifo.cache1.dcount =
- (value & NV_PFIFO_CACHE1_DMA_DCOUNT_VALUE);
- break;
- case NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW:
- d->pfifo.cache1.get_jmp_shadow =
- (value & NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW_OFFSET);
- break;
- case NV_PFIFO_CACHE1_DMA_RSVD_SHADOW:
- d->pfifo.cache1.rsvd_shadow = value;
- break;
- case NV_PFIFO_CACHE1_DMA_DATA_SHADOW:
- d->pfifo.cache1.data_shadow = value;
- break;
default:
DEVICE_WRITE32_REG(pfifo); // Was : DEBUG_WRITE32_UNHANDLED(PFIFO);
break;
}
+ qemu_cond_broadcast(&d->pfifo.pusher_cond);
+ qemu_cond_broadcast(&d->pfifo.puller_cond);
+
+ qemu_mutex_unlock(&d->pfifo.pfifo_lock);
+
DEVICE_WRITE32_END(PFIFO);
}
+static void pfifo_run_puller(NV2AState *d)
+{
+ uint32_t *pull0 = &d->pfifo.regs[NV_PFIFO_CACHE1_PULL0];
+ uint32_t *pull1 = &d->pfifo.regs[NV_PFIFO_CACHE1_PULL1];
+ uint32_t *engine_reg = &d->pfifo.regs[NV_PFIFO_CACHE1_ENGINE];
-/* pusher should be fine to run from a mimo handler
-* whenever's it's convenient */
-static void pfifo_run_pusher(NV2AState *d) {
- uint8_t channel_id;
- ChannelControl *control;
- Cache1State *state;
- CacheEntry *command;
- uint8_t *dma;
- xbaddr dma_len;
- uint32_t word;
+ uint32_t *status = &d->pfifo.regs[NV_PFIFO_CACHE1_STATUS];
+ uint32_t *get_reg = &d->pfifo.regs[NV_PFIFO_CACHE1_GET];
+ uint32_t *put_reg = &d->pfifo.regs[NV_PFIFO_CACHE1_PUT];
- /* TODO: How is cache1 selected? */
- state = &d->pfifo.cache1;
- channel_id = state->channel_id;
- control = &d->user.channel_control[channel_id];
+ // TODO
+ // CacheEntry working_cache[NV2A_CACHE1_SIZE];
+ // int working_cache_size = 0;
+ // pull everything into our own queue
- if (!state->push_enabled)
- return;
+ // TODO think more about locking
+
+ while (true) {
+ if (!GET_MASK(*pull0, NV_PFIFO_CACHE1_PULL0_ACCESS)) return;
+
+ /* empty cache1 */
+ if (*status & NV_PFIFO_CACHE1_STATUS_LOW_MARK) break;
+
+ uint32_t get = *get_reg;
+ uint32_t put = *put_reg;
+
+ assert(get < 128*4 && (get % 4) == 0);
+ uint32_t method_entry = d->pfifo.regs[NV_PFIFO_CACHE1_METHOD + get*2];
+ uint32_t parameter = d->pfifo.regs[NV_PFIFO_CACHE1_DATA + get*2];
+
+ uint32_t new_get = (get+4) & 0x1fc;
+ *get_reg = new_get;
+
+ if (new_get == put) {
+ // set low mark
+ *status |= NV_PFIFO_CACHE1_STATUS_LOW_MARK;
+ }
+ if (*status & NV_PFIFO_CACHE1_STATUS_HIGH_MARK) {
+ // unset high mark
+ *status &= ~NV_PFIFO_CACHE1_STATUS_HIGH_MARK;
+ // signal pusher
+ qemu_cond_signal(&d->pfifo.pusher_cond);
+ }
- /* only handling DMA for now... */
+ uint32_t method = method_entry & 0x1FFC;
+ uint32_t subchannel = GET_MASK(method_entry, NV_PFIFO_CACHE1_METHOD_SUBCHANNEL);
- /* Channel running DMA */
- uint32_t channel_modes = d->pfifo.regs[NV_PFIFO_MODE];
- assert(channel_modes & (1 << channel_id));
- assert(state->mode == FIFO_DMA);
+ // NV2A_DPRINTF("pull %d 0x%08X 0x%08X - subch %d\n", get/4, method_entry, parameter, subchannel);
- if (!state->dma_push_enabled)
- return;
- if (state->dma_push_suspended)
- return;
+ if (method == 0) {
+ RAMHTEntry entry = ramht_lookup(d, parameter);
+ assert(entry.valid);
- /* We're running so there should be no pending errors... */
- assert(state->error == NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE);
+ // assert(entry.channel_id == state->channel_id);
- dma = (uint8_t*)nv_dma_map(d, state->dma_instance, &dma_len);
+ assert(entry.engine == ENGINE_GRAPHICS);
- NV2A_DPRINTF("DMA pusher: max 0x%08X, 0x%08X - 0x%08X\n",
- dma_len, control->dma_get, control->dma_put);
- /* based on the convenient pseudocode in envytools */
- while (control->dma_get != control->dma_put) {
- if (control->dma_get >= dma_len) {
+ /* the engine is bound to the subchannel */
+ assert(subchannel < 8);
+ SET_MASK(*engine_reg, 3 << (4*subchannel), entry.engine);
+ SET_MASK(*pull1, NV_PFIFO_CACHE1_PULL1_ENGINE, entry.engine);
+ // NV2A_DPRINTF("engine_reg1 %d 0x%08X\n", subchannel, *engine_reg);
- state->error = NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION;
- break;
- }
- word = ldl_le_p((uint32_t*)(dma + control->dma_get));
- control->dma_get += 4;
+ // TODO: this is fucked
+ qemu_mutex_lock(&d->pgraph.pgraph_lock);
+ //make pgraph busy
+ qemu_mutex_unlock(&d->pfifo.pfifo_lock);
- if (state->method_count) {
- /* data word of methods command */
- state->data_shadow = word;
+ pgraph_switch_context(d, entry.channel_id);
+ pgraph_wait_fifo_access(d);
+ pgraph_handle_method(d, subchannel, 0, entry.instance);
- command = (CacheEntry*)g_malloc0(sizeof(CacheEntry));
- command->method = state->method;
- command->subchannel = state->subchannel;
- command->nonincreasing = state->method_nonincreasing;
- command->parameter = word;
+ // make pgraph not busy
+ qemu_mutex_unlock(&d->pgraph.pgraph_lock);
+ qemu_mutex_lock(&d->pfifo.pfifo_lock);
- qemu_mutex_lock(&state->cache_lock);
- state->cache.push(command);
- qemu_cond_signal(&state->cache_cond);
- qemu_mutex_unlock(&state->cache_lock);
+ } else if (method >= 0x100) {
+ // method passed to engine
- if (!state->method_nonincreasing) {
- state->method += 4;
- }
- state->method_count--;
- state->dcount++;
- } else {
- /* no command active - this is the first word of a new one */
- state->rsvd_shadow = word;
- /* match all forms */
- if ((word & 0xe0000003) == 0x20000000) {
- /* old jump */
- state->get_jmp_shadow = control->dma_get;
- control->dma_get = word & 0x1fffffff;
- NV2A_DPRINTF("pb OLD_JMP 0x%08X\n", control->dma_get);
- } else if ((word & 3) == 1) {
- /* jump */
- state->get_jmp_shadow = control->dma_get;
- control->dma_get = word & 0xfffffffc;
- NV2A_DPRINTF("pb JMP 0x%08X\n", control->dma_get);
- } else if ((word & 3) == 2) {
- /* call */
- if (state->subroutine_active) {
- state->error = NV_PFIFO_CACHE1_DMA_STATE_ERROR_CALL;
- break;
- }
- state->subroutine_return = control->dma_get;
- state->subroutine_active = true;
- control->dma_get = word & 0xfffffffc;
- NV2A_DPRINTF("pb CALL 0x%08X\n", control->dma_get);
- } else if (word == 0x00020000) {
- /* return */
- if (!state->subroutine_active) {
- state->error = NV_PFIFO_CACHE1_DMA_STATE_ERROR_RETURN;
- break;
- }
- control->dma_get = state->subroutine_return;
- state->subroutine_active = false;
- NV2A_DPRINTF("pb RET 0x%08X\n", control->dma_get);
- } else if ((word & 0xe0030003) == 0) {
- /* increasing methods */
- state->method = word & 0x1fff;
- state->subchannel = (word >> 13) & 7;
- state->method_count = (word >> 18) & 0x7ff;
- state->method_nonincreasing = false;
- state->dcount = 0;
- } else if ((word & 0xe0030003) == 0x40000000) {
- /* non-increasing methods */
- state->method = word & 0x1fff;
- state->subchannel = (word >> 13) & 7;
- state->method_count = (word >> 18) & 0x7ff;
- state->method_nonincreasing = true;
- state->dcount = 0;
- } else {
- NV2A_DPRINTF("pb reserved cmd 0x%08X - 0x%08X\n",
- control->dma_get, word);
- state->error = NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD;
- break;
- }
- }
- }
+ /* methods that take objects.
+ * TODO: Check this range is correct for the nv2a */
+ if (method >= 0x180 && method < 0x200) {
+ //qemu_mutex_lock_iothread();
+ RAMHTEntry entry = ramht_lookup(d, parameter);
+ assert(entry.valid);
+ // assert(entry.channel_id == state->channel_id);
+ parameter = entry.instance;
+ //qemu_mutex_unlock_iothread();
+ }
- NV2A_DPRINTF("DMA pusher done: max 0x%08X, 0x%08X - 0x%08X\n",
- dma_len, control->dma_get, control->dma_put);
+ enum FIFOEngine engine = (enum FIFOEngine)GET_MASK(*engine_reg, 3 << (4*subchannel));
+ // NV2A_DPRINTF("engine_reg2 %d 0x%08X\n", subchannel, *engine_reg);
+ assert(engine == ENGINE_GRAPHICS);
+ SET_MASK(*pull1, NV_PFIFO_CACHE1_PULL1_ENGINE, engine);
- if (state->error) {
- NV2A_DPRINTF("pb error: %d\n", state->error);
- assert(false);
+ // TODO: this is fucked
+ qemu_mutex_lock(&d->pgraph.pgraph_lock);
+ //make pgraph busy
+ qemu_mutex_unlock(&d->pfifo.pfifo_lock);
- state->dma_push_suspended = true;
+ pgraph_wait_fifo_access(d);
+ pgraph_handle_method(d, subchannel, method, parameter);
- d->pfifo.pending_interrupts |= NV_PFIFO_INTR_0_DMA_PUSHER;
- update_irq(d);
- }
+ // make pgraph not busy
+ qemu_mutex_unlock(&d->pgraph.pgraph_lock);
+ qemu_mutex_lock(&d->pfifo.pfifo_lock);
+ } else {
+ assert(false);
+ }
+
+ }
}
int pfifo_puller_thread(NV2AState *d)
{
- CxbxSetThreadName("Cxbx NV2A FIFO");
+ CxbxSetThreadName("Cxbx NV2A FIFO puller");
- Cache1State *state = &(d->pfifo.cache1);
+ glo_set_current(d->pgraph.gl_context);
- glo_set_current(d->pgraph.gl_context);
+ qemu_mutex_lock(&d->pfifo.pfifo_lock);
+ while (true) {
+ pfifo_run_puller(d);
+ qemu_cond_wait(&d->pfifo.puller_cond, &d->pfifo.pfifo_lock);
- while (true) {
- qemu_mutex_lock(&state->cache_lock);
+ if (d->exiting) {
+ break;
+ }
+ }
+ qemu_mutex_unlock(&d->pfifo.pfifo_lock);
- while (state->cache.empty() || !state->pull_enabled) {
- qemu_cond_wait(&state->cache_cond, &state->cache_lock);
+ glo_set_current(NULL); // Cxbx addition
- if (d->exiting) {
- qemu_mutex_unlock(&state->cache_lock);
- glo_set_current(NULL);
- return 0;
- }
- }
+ return NULL;
+}
- // Copy cache to working_cache
- while (!state->cache.empty()) {
- state->working_cache.push(state->cache.front());
- state->cache.pop();
- }
+static void pfifo_run_pusher(NV2AState *d)
+{
+ uint32_t *push0 = &d->pfifo.regs[NV_PFIFO_CACHE1_PUSH0];
+ uint32_t *push1 = &d->pfifo.regs[NV_PFIFO_CACHE1_PUSH1];
+ uint32_t *dma_subroutine = &d->pfifo.regs[NV_PFIFO_CACHE1_DMA_SUBROUTINE];
+ uint32_t *dma_state = &d->pfifo.regs[NV_PFIFO_CACHE1_DMA_STATE];
+ uint32_t *dma_push = &d->pfifo.regs[NV_PFIFO_CACHE1_DMA_PUSH];
+ uint32_t *dma_get = &d->pfifo.regs[NV_PFIFO_CACHE1_DMA_GET];
+ uint32_t *dma_put = &d->pfifo.regs[NV_PFIFO_CACHE1_DMA_PUT];
+ uint32_t *dma_dcount = &d->pfifo.regs[NV_PFIFO_CACHE1_DMA_DCOUNT];
- qemu_mutex_unlock(&state->cache_lock);
+ uint32_t *status = &d->pfifo.regs[NV_PFIFO_CACHE1_STATUS];
+ uint32_t *get_reg = &d->pfifo.regs[NV_PFIFO_CACHE1_GET];
+ uint32_t *put_reg = &d->pfifo.regs[NV_PFIFO_CACHE1_PUT];
- qemu_mutex_lock(&d->pgraph.lock);
+ if (!GET_MASK(*push0, NV_PFIFO_CACHE1_PUSH0_ACCESS)) return;
+ if (!GET_MASK(*dma_push, NV_PFIFO_CACHE1_DMA_PUSH_ACCESS)) return;
- while (!state->working_cache.empty()) {
- if (d->exiting) {
- qemu_mutex_lock(&d->pgraph.lock);
- glo_set_current(NULL);
- return 0;
- }
+ /* suspended */
+ if (GET_MASK(*dma_push, NV_PFIFO_CACHE1_DMA_PUSH_STATUS)) return;
- CacheEntry* command = state->working_cache.front();
- state->working_cache.pop();
+ // TODO: should we become busy here??
+ // NV_PFIFO_CACHE1_DMA_PUSH_STATE _BUSY
- if (command->method == 0) {
- // qemu_mutex_lock_iothread();
- RAMHTEntry entry = ramht_lookup(d, command->parameter);
- assert(entry.valid);
+ unsigned int channel_id = GET_MASK(*push1,
+ NV_PFIFO_CACHE1_PUSH1_CHID);
- assert(entry.channel_id == state->channel_id);
- // qemu_mutex_unlock_iothread();
- switch (entry.engine) {
- case ENGINE_GRAPHICS:
- pgraph_switch_context(d, entry.channel_id);
- pgraph_wait_fifo_access(d);
- pgraph_handle_method(d, command->subchannel, 0, entry.instance);
- break;
- default:
- assert(false);
- break;
- }
+ /* Channel running DMA */
+ uint32_t channel_modes = d->pfifo.regs[NV_PFIFO_MODE];
+ assert(channel_modes & (1 << channel_id));
- /* the engine is bound to the subchannel */
- qemu_mutex_lock(&state->cache_lock);
- state->bound_engines[command->subchannel] = entry.engine;
- state->last_engine = entry.engine;
- qemu_mutex_unlock(&state->cache_lock);
- }
- else if (command->method >= 0x100) {
- /* method passed to engine */
+ assert(GET_MASK(*push1, NV_PFIFO_CACHE1_PUSH1_MODE)
+ == NV_PFIFO_CACHE1_PUSH1_MODE_DMA);
- uint32_t parameter = command->parameter;
+ /* We're running so there should be no pending errors... */
+ assert(GET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_ERROR)
+ == NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE);
- /* methods that take objects.
- * TODO: Check this range is correct for the nv2a */
- if (command->method >= 0x180 && command->method < 0x200) {
- //qemu_mutex_lock_iothread();
- RAMHTEntry entry = ramht_lookup(d, parameter);
- assert(entry.valid);
- assert(entry.channel_id == state->channel_id);
- parameter = entry.instance;
- //qemu_mutex_unlock_iothread();
- }
+ hwaddr dma_instance =
+ GET_MASK(d->pfifo.regs[NV_PFIFO_CACHE1_DMA_INSTANCE],
+ NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MASK) << 4; // TODO : Use NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MOVE?
- // state->cache_lock.lock();
- enum FIFOEngine engine = state->bound_engines[command->subchannel];
- // state->cache_lock.unlock();
+ hwaddr dma_len;
+ uint8_t *dma = (uint8_t*)nv_dma_map(d, dma_instance, &dma_len);
- switch (engine) {
- case ENGINE_GRAPHICS:
- pgraph_wait_fifo_access(d);
- pgraph_handle_method(d, command->subchannel,
- command->method, parameter);
- break;
- default:
- // TODO: FIx this
- // assert(false);
- break;
- }
+ /* based on the convenient pseudocode in envytools */
+ while (true) {
+ uint32_t dma_get_v = *dma_get;
+ uint32_t dma_put_v = *dma_put;
+ if (dma_get_v == dma_put_v) break;
+ if (dma_get_v >= dma_len) {
+ assert(false);
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_ERROR,
+ NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION);
+ break;
+ }
- // state->cache_lock.lock();
- state->last_engine = state->bound_engines[command->subchannel];
- // state->cache_lock.unlock();
- }
- else
- NV2A_DPRINTF("FIFO: Unknown Method - 0x%08X\n",
- command->method);
+ uint32_t word = ldl_le_p((uint32_t*)(dma + dma_get_v));
+ dma_get_v += 4;
- g_free(command);
- }
+ uint32_t method_type =
+ GET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE);
+ uint32_t method_subchannel =
+ GET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL);
+ uint32_t method =
+ GET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD) << 2;
+ uint32_t method_count =
+ GET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT);
- qemu_mutex_unlock(&d->pgraph.lock);
- }
+ uint32_t subroutine_state =
+ GET_MASK(*dma_subroutine, NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE);
+
+ if (method_count) {
+ /* full */
+ if (*status & NV_PFIFO_CACHE1_STATUS_HIGH_MARK) return;
+
+
+ /* data word of methods command */
+ d->pfifo.regs[NV_PFIFO_CACHE1_DMA_DATA_SHADOW] = word;
+
+ uint32_t put = *put_reg;
+ uint32_t get = *get_reg;
+
+ assert((method & 3) == 0);
+ uint32_t method_entry = 0;
+ SET_MASK(method_entry, NV_PFIFO_CACHE1_METHOD_ADDRESS, method >> 2);
+ SET_MASK(method_entry, NV_PFIFO_CACHE1_METHOD_TYPE, method_type);
+ SET_MASK(method_entry, NV_PFIFO_CACHE1_METHOD_SUBCHANNEL, method_subchannel);
+
+ // NV2A_DPRINTF("push %d 0x%08X 0x%08X - subch %d\n", put/4, method_entry, word, method_subchannel);
+
+ assert(put < 128*4 && (put%4) == 0);
+ d->pfifo.regs[NV_PFIFO_CACHE1_METHOD + put*2] = method_entry;
+ d->pfifo.regs[NV_PFIFO_CACHE1_DATA + put*2] = word;
+
+ uint32_t new_put = (put+4) & 0x1fc;
+ *put_reg = new_put;
+ if (new_put == get) {
+ // set high mark
+ *status |= NV_PFIFO_CACHE1_STATUS_HIGH_MARK;
+ }
+ if (*status & NV_PFIFO_CACHE1_STATUS_LOW_MARK) {
+ // unset low mark
+ *status &= ~NV_PFIFO_CACHE1_STATUS_LOW_MARK;
+ // signal puller
+ qemu_cond_signal(&d->pfifo.puller_cond);
+ }
+
+ if (method_type == NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_INC) {
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD,
+ (method + 4) >> 2);
+ }
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT,
+ method_count - 1);
+ (*dma_dcount)++;
+ } else {
+ /* no command active - this is the first word of a new one */
+ d->pfifo.regs[NV_PFIFO_CACHE1_DMA_RSVD_SHADOW] = word;
+
+ /* match all forms */
+ if ((word & 0xe0000003) == 0x20000000) {
+ /* old jump */
+ d->pfifo.regs[NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW] =
+ dma_get_v;
+ dma_get_v = word & 0x1fffffff;
+ NV2A_DPRINTF("pb OLD_JMP 0x%08X\n", dma_get_v);
+ } else if ((word & 3) == 1) {
+ /* jump */
+ d->pfifo.regs[NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW] =
+ dma_get_v;
+ dma_get_v = word & 0xfffffffc;
+ NV2A_DPRINTF("pb JMP 0x%08X\n", dma_get_v);
+ } else if ((word & 3) == 2) {
+ /* call */
+ if (subroutine_state) {
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_ERROR,
+ NV_PFIFO_CACHE1_DMA_STATE_ERROR_CALL);
+ break;
+ } else {
+ *dma_subroutine = dma_get_v;
+ SET_MASK(*dma_subroutine,
+ NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE, 1);
+ dma_get_v = word & 0xfffffffc;
+ NV2A_DPRINTF("pb CALL 0x%08X\n", dma_get_v);
+ }
+ } else if (word == 0x00020000) {
+ /* return */
+ if (!subroutine_state) {
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_ERROR,
+ NV_PFIFO_CACHE1_DMA_STATE_ERROR_RETURN);
+ // break;
+ } else {
+ dma_get_v = *dma_subroutine & 0xfffffffc;
+ SET_MASK(*dma_subroutine,
+ NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE, 0);
+ NV2A_DPRINTF("pb RET 0x%08X\n", dma_get_v);
+ }
+ } else if ((word & 0xe0030003) == 0) {
+ /* increasing methods */
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD,
+ (word & 0x1fff) >> 2 );
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL,
+ (word >> 13) & 7);
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT,
+ (word >> 18) & 0x7ff);
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE,
+ NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_INC);
+ *dma_dcount = 0;
+ } else if ((word & 0xe0030003) == 0x40000000) {
+ /* non-increasing methods */
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD,
+ (word & 0x1fff) >> 2 );
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL,
+ (word >> 13) & 7);
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT,
+ (word >> 18) & 0x7ff);
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE,
+ NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_NON_INC);
+ *dma_dcount = 0;
+ } else {
+ NV2A_DPRINTF("pb reserved cmd 0x%08X - 0x%08X\n",
+ dma_get_v, word);
+ SET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_ERROR,
+ NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD);
+ // break;
+ assert(false);
+ }
+ }
+
+ *dma_get = dma_get_v;
+
+ if (GET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_ERROR)) {
+ break;
+ }
+ }
+
+ // NV2A_DPRINTF("DMA pusher done: max 0x%08X, 0x%08X - 0x%08X\n",
+ // dma_len, control->dma_get, control->dma_put);
+
+ uint32_t error = GET_MASK(*dma_state, NV_PFIFO_CACHE1_DMA_STATE_ERROR);
+ if (error) {
+ NV2A_DPRINTF("pb error: %d\n", error);
+ assert(false);
+
+ SET_MASK(*dma_push, NV_PFIFO_CACHE1_DMA_PUSH_STATUS, 1); /* suspended */
+
+ // d->pfifo.pending_interrupts |= NV_PFIFO_INTR_0_DMA_PUSHER;
+ // update_irq(d);
+ }
+}
+
+int pfifo_pusher_thread(NV2AState *d)
+{
+ CxbxSetThreadName("Cxbx NV2A FIFO pusher");
+
+ qemu_mutex_lock(&d->pfifo.pfifo_lock);
+ while (true) {
+ pfifo_run_pusher(d);
+ qemu_cond_wait(&d->pfifo.pusher_cond, &d->pfifo.pfifo_lock);
+
+ if (d->exiting) {
+ break;
+ }
+ }
+ qemu_mutex_unlock(&d->pfifo.pfifo_lock);
return 0;
}
@@ -539,7 +493,10 @@ static uint32_t ramht_hash(NV2AState *d, uint32_t handle)
hash ^= (handle & ((1 << bits) - 1));
handle >>= bits;
}
- hash ^= d->pfifo.cache1.channel_id << (bits - 4);
+
+ unsigned int channel_id = GET_MASK(d->pfifo.regs[NV_PFIFO_CACHE1_PUSH1],
+ NV_PFIFO_CACHE1_PUSH1_CHID);
+ hash ^= channel_id << (bits - 4);
return hash;
}
@@ -549,7 +506,7 @@ static RAMHTEntry ramht_lookup(NV2AState *d, uint32_t handle)
uint32_t hash = ramht_hash(d, handle);
assert(hash * 8 < ramht_size(d));
- uint32_t ramht_address =
+ xbaddr ramht_address =
GET_MASK(d->pfifo.regs[NV_PFIFO_RAMHT],
NV_PFIFO_RAMHT_BASE_ADDRESS_MASK) << 12;
diff --git a/src/devices/video/EmuNV2A_PGRAPH.cpp b/src/devices/video/EmuNV2A_PGRAPH.cpp
index 2520a4f20..aac8ecd52 100644
--- a/src/devices/video/EmuNV2A_PGRAPH.cpp
+++ b/src/devices/video/EmuNV2A_PGRAPH.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_pgraph.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
@@ -408,10 +411,9 @@ void (*pgraph_draw_inline_elements)(NV2AState *d);
void (*pgraph_draw_state_update)(NV2AState *d);
void (*pgraph_draw_clear)(NV2AState *d);
-static void pgraph_switch_context(NV2AState *d, unsigned int channel_id);
-static void pgraph_set_context_user(NV2AState *d, uint32_t value);
-static void pgraph_wait_fifo_access(NV2AState *d);
+//static void pgraph_set_context_user(NV2AState *d, uint32_t value);
void pgraph_handle_method(NV2AState *d, unsigned int subchannel, unsigned int method, uint32_t parameter);
+static void pgraph_log_method(unsigned int subchannel, unsigned int graphics_class, unsigned int method, uint32_t parameter);
static void pgraph_allocate_inline_buffer_vertices(PGRAPHState *pg, unsigned int attr);
static void pgraph_finish_inline_buffer_vertex(PGRAPHState *pg);
static void pgraph_update_shader_constants(PGRAPHState *pg, ShaderBinding *binding, bool binding_changed, bool vertex_program, bool fixed_function);
@@ -429,8 +431,6 @@ static void pgraph_update_memory_buffer(NV2AState *d, hwaddr addr, hwaddr size,
static void pgraph_bind_vertex_attributes(NV2AState *d, unsigned int num_elements, bool inline_data, unsigned int inline_stride);
static unsigned int pgraph_bind_inline_array(NV2AState *d);
-static void load_graphics_object(NV2AState *d, hwaddr instance_address, GraphicsObject *obj);
-static GraphicsObject* lookup_graphics_object(PGRAPHState *s, hwaddr instance_address);
static float convert_f16_to_float(uint16_t f16);
static float convert_f24_to_float(uint32_t f24);
static uint8_t* convert_texture_data(const unsigned int color_format, const uint8_t *data, const uint8_t *palette_data, const unsigned int width, const unsigned int height, const unsigned int depth, const unsigned int row_pitch, const unsigned int slice_pitch);
@@ -446,14 +446,13 @@ static gboolean shader_equal(gconstpointer a, gconstpointer b);
static unsigned int kelvin_map_stencil_op(uint32_t parameter);
static unsigned int kelvin_map_polygon_mode(uint32_t parameter);
static unsigned int kelvin_map_texgen(uint32_t parameter, unsigned int channel);
-static void pgraph_log_method(unsigned int subchannel, unsigned int graphics_class, unsigned int method, uint32_t parameter);
static uint64_t fnv_hash(const uint8_t *data, size_t len);
static uint64_t fast_hash(const uint8_t *data, size_t len, unsigned int samples);
/* PGRAPH - accelerated 2d/3d drawing engine */
DEVICE_READ32(PGRAPH)
{
- qemu_mutex_lock(&d->pgraph.lock);
+ qemu_mutex_lock(&d->pgraph.pgraph_lock);
DEVICE_READ32_SWITCH() {
case NV_PGRAPH_INTR:
@@ -462,60 +461,22 @@ DEVICE_READ32(PGRAPH)
case NV_PGRAPH_INTR_EN:
result = d->pgraph.enabled_interrupts;
break;
- case NV_PGRAPH_NSOURCE:
- result = d->pgraph.notify_source;
- break;
- case NV_PGRAPH_CTX_USER:
- SET_MASK(result, NV_PGRAPH_CTX_USER_CHANNEL_3D,
- d->pgraph.context[d->pgraph.channel_id].channel_3d);
- SET_MASK(result, NV_PGRAPH_CTX_USER_CHANNEL_3D_VALID, 1);
- SET_MASK(result, NV_PGRAPH_CTX_USER_SUBCH,
- d->pgraph.context[d->pgraph.channel_id].subchannel << 13);
- SET_MASK(result, NV_PGRAPH_CTX_USER_CHID, d->pgraph.channel_id);
- break;
- case NV_PGRAPH_TRAPPED_ADDR:
- SET_MASK(result, NV_PGRAPH_TRAPPED_ADDR_CHID, d->pgraph.trapped_channel_id);
- SET_MASK(result, NV_PGRAPH_TRAPPED_ADDR_SUBCH, d->pgraph.trapped_subchannel);
- SET_MASK(result, NV_PGRAPH_TRAPPED_ADDR_MTHD, d->pgraph.trapped_method);
- break;
- case NV_PGRAPH_TRAPPED_DATA_LOW:
- result = d->pgraph.trapped_data[0];
- break;
- case NV_PGRAPH_FIFO:
- SET_MASK(result, NV_PGRAPH_FIFO_ACCESS, d->pgraph.fifo_access);
- break;
- case NV_PGRAPH_CHANNEL_CTX_TABLE:
- result = d->pgraph.context_table >> 4;
- break;
- case NV_PGRAPH_CHANNEL_CTX_POINTER:
- result = d->pgraph.context_address >> 4;
- break;
default:
DEVICE_READ32_REG(pgraph); // Was : DEBUG_READ32_UNHANDLED(PGRAPH);
}
- qemu_mutex_unlock(&d->pgraph.lock);
+ qemu_mutex_unlock(&d->pgraph.pgraph_lock);
// reg_log_read(NV_PGRAPH, addr, r);
DEVICE_READ32_END(PGRAPH);
}
-static void pgraph_set_context_user(NV2AState *d, uint32_t value)
-{
- d->pgraph.channel_id = (value & NV_PGRAPH_CTX_USER_CHID) >> 24;
-
- d->pgraph.context[d->pgraph.channel_id].channel_3d =
- GET_MASK(value, NV_PGRAPH_CTX_USER_CHANNEL_3D);
- d->pgraph.context[d->pgraph.channel_id].subchannel =
- GET_MASK(value, NV_PGRAPH_CTX_USER_SUBCH);
-}
-
DEVICE_WRITE32(PGRAPH)
{
// reg_log_write(NV_PGRAPH, addr, val);
- qemu_mutex_lock(&d->pgraph.lock);
+ qemu_mutex_lock(&d->pgraph.pgraph_lock);
switch (addr) {
case NV_PGRAPH_INTR:
@@ -525,12 +486,6 @@ DEVICE_WRITE32(PGRAPH)
case NV_PGRAPH_INTR_EN:
d->pgraph.enabled_interrupts = value;
break;
- case NV_PGRAPH_CTX_CONTROL:
- d->pgraph.channel_valid = (value & NV_PGRAPH_CTX_CONTROL_CHID);
- break;
- case NV_PGRAPH_CTX_USER:
- pgraph_set_context_user(d, value);
- break;
case NV_PGRAPH_INCREMENT:
if (value & NV_PGRAPH_INCREMENT_READ_3D) {
SET_MASK(d->pgraph.regs[NV_PGRAPH_SURFACE],
@@ -542,43 +497,44 @@ DEVICE_WRITE32(PGRAPH)
qemu_cond_broadcast(&d->pgraph.flip_3d);
}
break;
- case NV_PGRAPH_FIFO:
- d->pgraph.fifo_access = GET_MASK(value, NV_PGRAPH_FIFO_ACCESS);
- qemu_cond_broadcast(&d->pgraph.fifo_access_cond);
- break;
- case NV_PGRAPH_CHANNEL_CTX_TABLE:
- d->pgraph.context_table =
- (value & NV_PGRAPH_CHANNEL_CTX_TABLE_INST) << 4;
- break;
- case NV_PGRAPH_CHANNEL_CTX_POINTER:
- d->pgraph.context_address =
- (value & NV_PGRAPH_CHANNEL_CTX_POINTER_INST) << 4;
- break;
- case NV_PGRAPH_CHANNEL_CTX_TRIGGER:
+ case NV_PGRAPH_CHANNEL_CTX_TRIGGER: {
+ xbaddr context_address =
+ GET_MASK(d->pgraph.regs[NV_PGRAPH_CHANNEL_CTX_POINTER], NV_PGRAPH_CHANNEL_CTX_POINTER_INST) << 4;
if (value & NV_PGRAPH_CHANNEL_CTX_TRIGGER_READ_IN) {
- NV2A_DPRINTF("PGRAPH: read channel %d context from %" HWADDR_PRIx "\n",
- d->pgraph.channel_id, d->pgraph.context_address);
+ unsigned pgraph_channel_id =
+ GET_MASK(d->pgraph.regs[NV_PGRAPH_CTX_USER], NV_PGRAPH_CTX_USER_CHID);
- uint8_t *context_ptr = d->pramin.ramin_ptr + d->pgraph.context_address;
+ NV2A_DPRINTF("PGRAPH: read channel %d context from %" HWADDR_PRIx "\n",
+ pgraph_channel_id, context_address);
+
+ uint8_t *context_ptr = d->pramin.ramin_ptr + context_address;
uint32_t context_user = ldl_le_p((uint32_t*)context_ptr);
- NV2A_DPRINTF(" - CTX_USER = 0x%x\n", context_user);
+ NV2A_DPRINTF(" - CTX_USER = 0x%08X\n", context_user);
-
- pgraph_set_context_user(d, context_user);
+ d->pgraph.regs[NV_PGRAPH_CTX_USER] = context_user;
+ // pgraph_set_context_user(d, context_user);
}
if (value & NV_PGRAPH_CHANNEL_CTX_TRIGGER_WRITE_OUT) {
/* do stuff ... */
}
break;
+ }
default:
DEVICE_WRITE32_REG(pgraph); // Was : DEBUG_WRITE32_UNHANDLED(PGRAPH);
break;
}
- qemu_mutex_unlock(&d->pgraph.lock);
+ // events
+ switch (addr) {
+ case NV_PGRAPH_FIFO:
+ qemu_cond_broadcast(&d->pgraph.fifo_access_cond);
+ break;
+ }
+
+ qemu_mutex_unlock(&d->pgraph.pgraph_lock);
DEVICE_WRITE32_END(PGRAPH);
}
@@ -895,8 +851,6 @@ void OpenGL_draw_clear(NV2AState *d)
assert(pg->opengl_enabled);
- lockGL(pg);
-
NV2A_DPRINTF("---------PRE CLEAR ------\n");
GLbitfield gl_mask = 0;
@@ -1064,6 +1018,8 @@ void OpenGL_draw_clear(NV2AState *d)
/* FIXME: Should this really be inverted instead of ymin? */
glScissor(scissor_x, scissor_y, scissor_width, scissor_height);
+ /* FIXME: Respect window clip?!?! */
+
NV2A_DPRINTF("------------------CLEAR 0x%x %d,%d - %d,%d %x---------------\n",
parameter, xmin, ymin, xmax, ymax, d->pgraph.regs[NV_PGRAPH_COLORCLEARVALUE]);
@@ -1083,8 +1039,6 @@ void OpenGL_draw_clear(NV2AState *d)
}
pgraph_set_surface_dirty(pg, write_color, write_zeta);
-
- unlockGL(pg);
}
void OpenGL_init_pgraph_plugins()
@@ -1103,41 +1057,75 @@ void pgraph_handle_method(NV2AState *d,
uint32_t parameter)
{
unsigned int i;
-
- GraphicsSubchannel *subchannel_data;
- GraphicsObject *object;
-
unsigned int slot;
PGRAPHState *pg = &d->pgraph;
- assert(pg->channel_valid);
- subchannel_data = &pg->subchannel_data[subchannel];
- object = &subchannel_data->object;
+ bool channel_valid =
+ d->pgraph.regs[NV_PGRAPH_CTX_CONTROL] & NV_PGRAPH_CTX_CONTROL_CHID;
+ assert(channel_valid);
- ContextSurfaces2DState *context_surfaces_2d
- = &object->data.context_surfaces_2d;
- ImageBlitState *image_blit = &object->data.image_blit;
- KelvinState *kelvin = &object->data.kelvin;
+ unsigned channel_id = GET_MASK(pg->regs[NV_PGRAPH_CTX_USER], NV_PGRAPH_CTX_USER_CHID);
+ ContextSurfaces2DState *context_surfaces_2d = &pg->context_surfaces_2d;
+ ImageBlitState *image_blit = &pg->image_blit;
+ KelvinState *kelvin = &pg->kelvin;
- // Logging is slow.. disable for now..
- //pgraph_log_method(subchannel, object->graphics_class, method, parameter);
+ assert(subchannel < 8);
if (method == NV_SET_OBJECT) {
- subchannel_data->object_instance = parameter;
+ assert(parameter < d->pramin.ramin_size);
+ uint8_t *obj_ptr = d->pramin.ramin_ptr + parameter;
- //qemu_mutex_lock_iothread();
- load_graphics_object(d, parameter, object);
- //qemu_mutex_unlock_iothread();
- return;
- }
+ uint32_t ctx_1 = ldl_le_p((uint32_t*)obj_ptr);
+ uint32_t ctx_2 = ldl_le_p((uint32_t*)(obj_ptr+4));
+ uint32_t ctx_3 = ldl_le_p((uint32_t*)(obj_ptr+8));
+ uint32_t ctx_4 = ldl_le_p((uint32_t*)(obj_ptr+12));
+ uint32_t ctx_5 = parameter;
+
+ pg->regs[NV_PGRAPH_CTX_CACHE1 + subchannel * 4] = ctx_1;
+ pg->regs[NV_PGRAPH_CTX_CACHE2 + subchannel * 4] = ctx_2;
+ pg->regs[NV_PGRAPH_CTX_CACHE3 + subchannel * 4] = ctx_3;
+ pg->regs[NV_PGRAPH_CTX_CACHE4 + subchannel * 4] = ctx_4;
+ pg->regs[NV_PGRAPH_CTX_CACHE5 + subchannel * 4] = ctx_5;
+ }
+
+ // is this right?
+ pg->regs[NV_PGRAPH_CTX_SWITCH1] = pg->regs[NV_PGRAPH_CTX_CACHE1 + subchannel * 4];
+ pg->regs[NV_PGRAPH_CTX_SWITCH2] = pg->regs[NV_PGRAPH_CTX_CACHE2 + subchannel * 4];
+ pg->regs[NV_PGRAPH_CTX_SWITCH3] = pg->regs[NV_PGRAPH_CTX_CACHE3 + subchannel * 4];
+ pg->regs[NV_PGRAPH_CTX_SWITCH4] = pg->regs[NV_PGRAPH_CTX_CACHE4 + subchannel * 4];
+ pg->regs[NV_PGRAPH_CTX_SWITCH5] = pg->regs[NV_PGRAPH_CTX_CACHE5 + subchannel * 4];
+
+ uint32_t graphics_class = GET_MASK(pg->regs[NV_PGRAPH_CTX_SWITCH1],
+ NV_PGRAPH_CTX_SWITCH1_GRCLASS);
+
+ // Logging is slow.. disable for now..
+ //pgraph_log_method(subchannel, graphics_class, method, parameter);
+
+ if (subchannel != 0) {
+ // catches context switching issues on xbox d3d
+ assert(graphics_class != 0x97);
+ }
/* ugly switch for now */
- switch (object->graphics_class) {
+ switch (graphics_class) {
- case NV_CONTEXT_SURFACES_2D: {
+ case NV_CONTEXT_PATTERN: {
switch (method) {
+ case NV044_SET_MONOCHROME_COLOR0:
+ pg->regs[NV_PGRAPH_PATT_COLOR0] = parameter;
+ break;
+ }
+
+ break;
+ }
+
+ case NV_CONTEXT_SURFACES_2D: {
+ switch (method) {
+ case NV062_SET_OBJECT:
+ context_surfaces_2d->object_instance = parameter;
+ break;
case NV062_SET_CONTEXT_DMA_IMAGE_SOURCE:
context_surfaces_2d->dma_image_source = parameter;
break;
@@ -1158,7 +1146,7 @@ void pgraph_handle_method(NV2AState *d,
context_surfaces_2d->dest_offset = parameter & 0x07FFFFFF;
break;
default:
- EmuLog(LOG_PREFIX, LOG_LEVEL::WARNING, "Unknown NV_CONTEXT_SURFACES_2D Method: 0x%08X\n", method);
+ EmuLog(LOG_PREFIX, LOG_LEVEL::WARNING, "Unknown NV_CONTEXT_SURFACES_2D Method: 0x%08X", method);
}
break;
@@ -1166,6 +1154,9 @@ void pgraph_handle_method(NV2AState *d,
case NV_IMAGE_BLIT: {
switch (method) {
+ case NV09F_SET_OBJECT:
+ image_blit->object_instance = parameter;
+ break;
case NV09F_SET_CONTEXT_SURFACES:
image_blit->context_surfaces = parameter;
break;
@@ -1189,14 +1180,9 @@ void pgraph_handle_method(NV2AState *d,
NV2A_GL_DPRINTF(true, "NV09F_SET_OPERATION_SRCCOPY");
- GraphicsObject *context_surfaces_obj =
- lookup_graphics_object(pg, image_blit->context_surfaces);
- assert(context_surfaces_obj);
- assert(context_surfaces_obj->graphics_class
- == NV_CONTEXT_SURFACES_2D);
-
- ContextSurfaces2DState *context_surfaces =
- &context_surfaces_obj->data.context_surfaces_2d;
+ ContextSurfaces2DState *context_surfaces = context_surfaces_2d;
+ assert(context_surfaces->object_instance
+ == image_blit->context_surfaces);
unsigned int bytes_per_pixel;
switch (context_surfaces->color_format) {
@@ -1251,13 +1237,17 @@ void pgraph_handle_method(NV2AState *d,
break;
default:
- EmuLog(LOG_PREFIX, LOG_LEVEL::WARNING, "Unknown NV_IMAGE_BLIT Method: 0x%08X\n", method);
+ EmuLog(LOG_PREFIX, LOG_LEVEL::WARNING, "Unknown NV_IMAGE_BLIT Method: 0x%08X", method);
}
break;
}
case NV_KELVIN_PRIMITIVE: {
switch (method) {
+ case NV097_SET_OBJECT:
+ kelvin->object_instance = parameter;
+ break;
+
case NV097_NO_OPERATION:
/* The bios uses nop as a software method call -
* it seems to expect a notify interrupt if the parameter isn't 0.
@@ -1268,31 +1258,30 @@ void pgraph_handle_method(NV2AState *d,
if (parameter != 0) {
assert(!(pg->pending_interrupts & NV_PGRAPH_INTR_ERROR));
-
- pg->trapped_channel_id = pg->channel_id;
- pg->trapped_subchannel = subchannel;
- pg->trapped_method = method;
- pg->trapped_data[0] = parameter;
- pg->notify_source = NV_PGRAPH_NSOURCE_NOTIFICATION; /* TODO: check this */
+ SET_MASK(pg->regs[NV_PGRAPH_TRAPPED_ADDR],
+ NV_PGRAPH_TRAPPED_ADDR_CHID, channel_id);
+ SET_MASK(pg->regs[NV_PGRAPH_TRAPPED_ADDR],
+ NV_PGRAPH_TRAPPED_ADDR_SUBCH, subchannel);
+ SET_MASK(pg->regs[NV_PGRAPH_TRAPPED_ADDR],
+ NV_PGRAPH_TRAPPED_ADDR_MTHD, method);
+ pg->regs[NV_PGRAPH_TRAPPED_DATA_LOW] = parameter;
+ pg->regs[NV_PGRAPH_NSOURCE] = NV_PGRAPH_NSOURCE_NOTIFICATION; /* TODO: check this */
pg->pending_interrupts |= NV_PGRAPH_INTR_ERROR;
- qemu_mutex_unlock(&pg->lock);
+ qemu_mutex_unlock(&pg->pgraph_lock);
qemu_mutex_lock_iothread();
update_irq(d);
-
- qemu_mutex_lock(&pg->lock);
+ qemu_mutex_lock(&pg->pgraph_lock);
qemu_mutex_unlock_iothread();
while (pg->pending_interrupts & NV_PGRAPH_INTR_ERROR) {
- qemu_cond_wait(&pg->interrupt_cond, &pg->lock);
+ qemu_cond_wait(&pg->interrupt_cond, &pg->pgraph_lock);
}
}
break;
case NV097_WAIT_FOR_IDLE:
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
break;
@@ -1309,7 +1298,6 @@ void pgraph_handle_method(NV2AState *d,
parameter);
break;
case NV097_FLIP_INCREMENT_WRITE: {
- lockGL(pg);
NV2A_DPRINTF("flip increment write %d -> ",
GET_MASK(pg->regs[NV_PGRAPH_SURFACE],
NV_PGRAPH_SURFACE_WRITE_3D));
@@ -1328,13 +1316,10 @@ void pgraph_handle_method(NV2AState *d,
glFrameTerminatorGREMEDY();
}
#endif // __APPLE__
- unlockGL(pg);
break;
}
case NV097_FLIP_STALL:
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
// TODO: Fix this (why does it hang?)
@@ -1359,7 +1344,7 @@ void pgraph_handle_method(NV2AState *d,
break;
case NV097_SET_CONTEXT_DMA_NOTIFIES:
- kelvin->dma_notifies = parameter;
+ pg->dma_notifies = parameter;
break;
case NV097_SET_CONTEXT_DMA_A:
pg->dma_a = parameter;
@@ -1368,13 +1353,11 @@ void pgraph_handle_method(NV2AState *d,
pg->dma_b = parameter;
break;
case NV097_SET_CONTEXT_DMA_STATE:
- kelvin->dma_state = parameter;
+ pg->dma_state = parameter;
break;
case NV097_SET_CONTEXT_DMA_COLOR:
/* try to get any straggling draws in before the surface's changed :/ */
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
pg->dma_color = parameter;
break;
@@ -1388,16 +1371,14 @@ void pgraph_handle_method(NV2AState *d,
pg->dma_vertex_b = parameter;
break;
case NV097_SET_CONTEXT_DMA_SEMAPHORE:
- kelvin->dma_semaphore = parameter;
+ pg->dma_semaphore = parameter;
break;
case NV097_SET_CONTEXT_DMA_REPORT:
pg->dma_report = parameter;
break;
case NV097_SET_SURFACE_CLIP_HORIZONTAL:
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
pg->surface_shape.clip_x =
GET_MASK(parameter, NV097_SET_SURFACE_CLIP_HORIZONTAL_X);
@@ -1405,9 +1386,7 @@ void pgraph_handle_method(NV2AState *d,
GET_MASK(parameter, NV097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH);
break;
case NV097_SET_SURFACE_CLIP_VERTICAL:
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
pg->surface_shape.clip_y =
GET_MASK(parameter, NV097_SET_SURFACE_CLIP_VERTICAL_Y);
@@ -1415,9 +1394,7 @@ void pgraph_handle_method(NV2AState *d,
GET_MASK(parameter, NV097_SET_SURFACE_CLIP_VERTICAL_HEIGHT);
break;
case NV097_SET_SURFACE_FORMAT:
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
pg->surface_shape.color_format =
GET_MASK(parameter, NV097_SET_SURFACE_FORMAT_COLOR);
@@ -1433,9 +1410,7 @@ void pgraph_handle_method(NV2AState *d,
GET_MASK(parameter, NV097_SET_SURFACE_FORMAT_HEIGHT);
break;
case NV097_SET_SURFACE_PITCH:
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
pg->surface_color.pitch =
GET_MASK(parameter, NV097_SET_SURFACE_PITCH_COLOR);
@@ -1443,16 +1418,12 @@ void pgraph_handle_method(NV2AState *d,
GET_MASK(parameter, NV097_SET_SURFACE_PITCH_ZETA);
break;
case NV097_SET_SURFACE_COLOR_OFFSET:
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
pg->surface_color.offset = parameter;
break;
case NV097_SET_SURFACE_ZETA_OFFSET:
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
pg->surface_zeta.offset = parameter;
break;
@@ -1475,9 +1446,7 @@ void pgraph_handle_method(NV2AState *d,
pg->regs[NV_PGRAPH_TEXADDRESS0 + slot * 4] = parameter;
break;
case NV097_SET_CONTROL0: {
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
bool stencil_write_enable =
parameter & NV097_SET_CONTROL0_STENCIL_WRITE_ENABLE;
@@ -1568,6 +1537,18 @@ void pgraph_handle_method(NV2AState *d,
SET_MASK(pg->regs[NV_PGRAPH_FOGCOLOR], NV_PGRAPH_FOGCOLOR_BLUE, blue);
break;
}
+ case NV097_SET_WINDOW_CLIP_TYPE:
+ SET_MASK(pg->regs[NV_PGRAPH_SETUPRASTER],
+ NV_PGRAPH_SETUPRASTER_WINDOWCLIPTYPE, parameter);
+ break;
+ CASE_8(NV097_SET_WINDOW_CLIP_HORIZONTAL, 4):
+ slot = (method - NV097_SET_WINDOW_CLIP_HORIZONTAL) / 4;
+ pg->regs[NV_PGRAPH_WINDOWCLIPX0 + slot * 4] = parameter;
+ break;
+ CASE_8(NV097_SET_WINDOW_CLIP_VERTICAL, 4):
+ slot = (method - NV097_SET_WINDOW_CLIP_VERTICAL) / 4;
+ pg->regs[NV_PGRAPH_WINDOWCLIPY0 + slot * 4] = parameter;
+ break;
case NV097_SET_ALPHA_TEST_ENABLE:
SET_MASK(pg->regs[NV_PGRAPH_CONTROL_0],
NV_PGRAPH_CONTROL_0_ALPHATESTENABLE, parameter);
@@ -2264,11 +2245,12 @@ void pgraph_handle_method(NV2AState *d,
slot = (method - NV097_SET_VERTEX_DATA_ARRAY_OFFSET) / 4;
- VertexAttribute *vertex_attribute = &pg->vertex_attributes[slot];
+ pg->vertex_attributes[slot].dma_select =
+ parameter & 0x80000000;
+ pg->vertex_attributes[slot].offset =
+ parameter & 0x7fffffff;
- vertex_attribute->dma_select = parameter & 0x80000000;
- vertex_attribute->offset = parameter & 0x7fffffff;
- vertex_attribute->converted_elements = 0;
+ pg->vertex_attributes[slot].converted_elements = 0;
break;
}
@@ -2284,7 +2266,6 @@ void pgraph_handle_method(NV2AState *d,
break;
case NV097_CLEAR_REPORT_VALUE:
- lockGL(pg);
/* FIXME: Does this have a value in parameter? Also does this (also?) modify
* the report memory block?
@@ -2298,7 +2279,6 @@ void pgraph_handle_method(NV2AState *d,
}
pg->zpass_pixel_count_result = 0;
- unlockGL(pg);
break;
case NV097_SET_ZPASS_PIXEL_COUNT_ENABLE:
@@ -2306,8 +2286,6 @@ void pgraph_handle_method(NV2AState *d,
break;
case NV097_GET_REPORT: {
- lockGL(pg);
-
/* FIXME: This was first intended to be watchpoint-based. However,
* qemu / kvm only supports virtual-address watchpoints.
* This'll do for now, but accuracy and performance with other
@@ -2349,7 +2327,6 @@ void pgraph_handle_method(NV2AState *d,
stl_le_p((uint32_t*)&report_data[12], done);
}
- unlockGL(pg);
break;
}
@@ -2360,8 +2337,6 @@ void pgraph_handle_method(NV2AState *d,
break;
case NV097_SET_BEGIN_END: {
- lockGL(pg);
-
uint32_t control_0 = pg->regs[NV_PGRAPH_CONTROL_0];
uint32_t control_1 = pg->regs[NV_PGRAPH_CONTROL_1];
@@ -2428,8 +2403,6 @@ void pgraph_handle_method(NV2AState *d,
}
pgraph_set_surface_dirty(pg, true, depth_test || stencil_test);
-
- unlockGL(pg);
break;
}
CASE_4(NV097_SET_TEXTURE_OFFSET, 64):
@@ -2669,21 +2642,21 @@ void pgraph_handle_method(NV2AState *d,
break;
}
case NV097_SET_SEMAPHORE_OFFSET:
- kelvin->semaphore_offset = parameter;
+ pg->regs[NV_PGRAPH_SEMAPHOREOFFSET] = parameter;
break;
case NV097_BACK_END_WRITE_SEMAPHORE_RELEASE: {
- lockGL(pg);
pgraph_update_surface(d, false, true, true);
- unlockGL(pg);
//qemu_mutex_unlock(&pg->pgraph_lock);
//qemu_mutex_lock_iothread();
+ uint32_t semaphore_offset = pg->regs[NV_PGRAPH_SEMAPHOREOFFSET];
+
xbaddr semaphore_dma_len;
- uint8_t *semaphore_data = (uint8_t*)nv_dma_map(d, kelvin->dma_semaphore,
+ uint8_t *semaphore_data = (uint8_t*)nv_dma_map(d, pg->dma_semaphore,
&semaphore_dma_len);
- assert(kelvin->semaphore_offset < semaphore_dma_len);
- semaphore_data += kelvin->semaphore_offset;
+ assert(semaphore_offset < semaphore_dma_len);
+ semaphore_data += semaphore_offset;
stl_le_p((uint32_t*)semaphore_data, parameter);
@@ -2780,15 +2753,15 @@ void pgraph_handle_method(NV2AState *d,
break;
default:
NV2A_GL_DPRINTF(true, " unhandled (0x%02x 0x%08x)",
- object->graphics_class, method);
+ graphics_class, method);
break;
}
break;
}
default:
- NV2A_GL_DPRINTF(true, "Unknown Graphics Class/Method 0x%08X/0x%08X\n",
- object->graphics_class, method);
+ NV2A_GL_DPRINTF(true, "Unknown Graphics Class/Method 0x%08X/0x%08X",
+ graphics_class, method);
break;
}
@@ -2796,35 +2769,39 @@ void pgraph_handle_method(NV2AState *d,
static void pgraph_switch_context(NV2AState *d, unsigned int channel_id)
{
- bool valid;
-
+ bool channel_valid =
+ d->pgraph.regs[NV_PGRAPH_CTX_CONTROL] & NV_PGRAPH_CTX_CONTROL_CHID;
+ unsigned pgraph_channel_id = GET_MASK(d->pgraph.regs[NV_PGRAPH_CTX_USER], NV_PGRAPH_CTX_USER_CHID);
// Cxbx Note : This isn't present in xqemu / OpenXbox : d->pgraph.pgraph_lock.lock();
- valid = d->pgraph.channel_valid && d->pgraph.channel_id == channel_id;
+ bool valid = channel_valid && pgraph_channel_id == channel_id;
if (!valid) {
- d->pgraph.trapped_channel_id = channel_id;
- }
- // Cxbx Note : This isn't present in xqemu / OpenXbox : d->pgraph.pgraph_lock.unlock();
+ SET_MASK(d->pgraph.regs[NV_PGRAPH_TRAPPED_ADDR],
+ NV_PGRAPH_TRAPPED_ADDR_CHID, channel_id);
- if (!valid) {
- NV2A_DPRINTF("puller needs to switch to ch %d\n", channel_id);
+ NV2A_DPRINTF("pgraph switching to ch %d\n", channel_id);
- qemu_mutex_unlock(&d->pgraph.lock);
+ /* TODO: hardware context switching */
+ assert(!(d->pgraph.regs[NV_PGRAPH_DEBUG_3]
+ & NV_PGRAPH_DEBUG_3_HW_CONTEXT_SWITCH));
+
+ qemu_mutex_unlock(&d->pgraph.pgraph_lock);
qemu_mutex_lock_iothread();
- d->pgraph.pending_interrupts |= NV_PGRAPH_INTR_CONTEXT_SWITCH;
+ d->pgraph.pending_interrupts |= NV_PGRAPH_INTR_CONTEXT_SWITCH; // TODO : Should this be done before unlocking pgraph_lock?
update_irq(d);
- qemu_mutex_lock(&d->pgraph.lock);
+ qemu_mutex_lock(&d->pgraph.pgraph_lock);
qemu_mutex_unlock_iothread();
+ // wait for the interrupt to be serviced
while (d->pgraph.pending_interrupts & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
- qemu_cond_wait(&d->pgraph.interrupt_cond, &d->pgraph.lock);
+ qemu_cond_wait(&d->pgraph.interrupt_cond, &d->pgraph.pgraph_lock);
}
}
}
static void pgraph_wait_fifo_access(NV2AState *d) {
- while (!d->pgraph.fifo_access) {
- qemu_cond_wait(&d->pgraph.fifo_access_cond, &d->pgraph.lock);
+ while (!(d->pgraph.regs[NV_PGRAPH_FIFO] & NV_PGRAPH_FIFO_ACCESS)) {
+ qemu_cond_wait(&d->pgraph.fifo_access_cond, &d->pgraph.pgraph_lock);
}
}
@@ -2842,29 +2819,28 @@ static void pgraph_log_method(unsigned int subchannel,
subchannel, last, method_name, count);
}
if (method != 0x1800) {
- const char* method_name = NV2AMethodToString(method);
- unsigned int nmethod = 0;
- switch (graphics_class) {
- case NV_KELVIN_PRIMITIVE:
- nmethod = method | (0x5c << 16);
- break;
- case NV_CONTEXT_SURFACES_2D:
- nmethod = method | (0x6d << 16);
- break;
- default:
- break;
- }
- /*
- if (nmethod != 0 && nmethod < ARRAY_SIZE(nv2a_method_names)) {
- method_name = nv2a_method_names[nmethod];
- }*/
- if (method_name) {
- NV2A_DPRINTF("d->pgraph method (%d): %s (0x%x)\n",
- subchannel, method_name, parameter);
- } else {
- NV2A_DPRINTF("d->pgraph method (%d): 0x%x -> 0x%04x (0x%x)\n",
+ // const char* method_name = NV2AMethodToString(method);
+ // unsigned int nmethod = 0;
+ // switch (graphics_class) {
+ // case NV_KELVIN_PRIMITIVE:
+ // nmethod = method | (0x5c << 16);
+ // break;
+ // case NV_CONTEXT_SURFACES_2D:
+ // nmethod = method | (0x6d << 16);
+ // break;
+ // case NV_CONTEXT_PATTERN:
+ // nmethod = method | (0x68 << 16);
+ // break;
+ // default:
+ // break;
+ // }
+ // if (method_name) {
+ // NV2A_DPRINTF("d->pgraph method (%d): %s (0x%x)\n",
+ // subchannel, method_name, parameter);
+ // } else {
+ NV2A_DPRINTF("pgraph method (%d): 0x%08X -> 0x%04x (0x%x)\n",
subchannel, graphics_class, method, parameter);
- }
+ // }
}
if (method == last) { count++; }
@@ -2917,8 +2893,7 @@ void pgraph_init(NV2AState *d)
PGRAPHState *pg = &d->pgraph;
- qemu_mutex_init(&pg->lock);
- qemu_mutex_init(&pg->gl_lock);
+ qemu_mutex_init(&pg->pgraph_lock);
qemu_cond_init(&pg->interrupt_cond);
qemu_cond_init(&pg->fifo_access_cond);
qemu_cond_init(&pg->flip_3d);
@@ -2931,8 +2906,6 @@ void pgraph_init(NV2AState *d)
/* fire up opengl */
- lockGL(pg);
-
pg->gl_context = glo_context_create();
assert(pg->gl_context);
@@ -3008,14 +2981,18 @@ void pgraph_init(NV2AState *d)
// assert(glGetError() == GL_NO_ERROR);
- unlockGL(pg);
+ glo_set_current(NULL);
}
void pgraph_destroy(PGRAPHState *pg)
{
- if (pg->opengl_enabled) {
- lockGL(pg);
+ qemu_mutex_destroy(&pg->pgraph_lock);
+ qemu_cond_destroy(&pg->interrupt_cond);
+ qemu_cond_destroy(&pg->fifo_access_cond);
+ qemu_cond_destroy(&pg->flip_3d);
+
+ if (pg->opengl_enabled) {
glo_set_current(pg->gl_context);
if (pg->gl_color_buffer) {
@@ -3032,15 +3009,7 @@ void pgraph_destroy(PGRAPHState *pg)
glo_set_current(NULL);
glo_context_destroy(pg->gl_context);
-
- unlockGL(pg);
}
-
- qemu_mutex_destroy(&pg->lock);
- qemu_mutex_destroy(&pg->gl_lock);
- qemu_cond_destroy(&pg->interrupt_cond);
- qemu_cond_destroy(&pg->fifo_access_cond);
- qemu_cond_destroy(&pg->flip_3d);
}
static void pgraph_update_shader_constants(PGRAPHState *pg,
@@ -3256,6 +3225,8 @@ static void pgraph_bind_shaders(PGRAPHState *pg)
ShaderState state;
/* register combiner stuff */
+ state.psh.window_clip_exclusive = pg->regs[NV_PGRAPH_SETUPRASTER]
+ & NV_PGRAPH_SETUPRASTER_WINDOWCLIPTYPE,
state.psh.combiner_control = pg->regs[NV_PGRAPH_COMBINECTL];
state.psh.shader_stage_program = pg->regs[NV_PGRAPH_SHADERPROG];
state.psh.other_stage_input = pg->regs[NV_PGRAPH_SHADERCTL];
@@ -3351,6 +3322,45 @@ static void pgraph_bind_shaders(PGRAPHState *pg)
}
}
+ /* Window clip
+ *
+ * Optimization note: very quickly check to ignore any repeated or zero-size
+ * clipping regions. Note that if region number 7 is valid, but the rest are
+ * not, we will still add all of them. Clip regions seem to be typically
+ * front-loaded (meaning the first one or two regions are populated, and the
+ * following are zeroed-out), so let's avoid adding any more complicated
+ * masking or copying logic here for now unless we discover a valid case.
+ */
+ assert(!state.psh.window_clip_exclusive); /* FIXME: Untested */
+ state.psh.window_clip_count = 0;
+ uint32_t last_x = 0, last_y = 0;
+
+ for (i = 0; i < 8; i++) {
+ const uint32_t x = pg->regs[NV_PGRAPH_WINDOWCLIPX0 + i * 4];
+ const uint32_t y = pg->regs[NV_PGRAPH_WINDOWCLIPY0 + i * 4];
+ const uint32_t x_min = GET_MASK(x, NV_PGRAPH_WINDOWCLIPX0_XMIN);
+ const uint32_t x_max = GET_MASK(x, NV_PGRAPH_WINDOWCLIPX0_XMAX);
+ const uint32_t y_min = GET_MASK(y, NV_PGRAPH_WINDOWCLIPY0_YMIN);
+ const uint32_t y_max = GET_MASK(y, NV_PGRAPH_WINDOWCLIPY0_YMAX);
+
+ /* Check for zero width or height clipping region */
+ if ((x_min == x_max) || (y_min == y_max)) {
+ continue;
+ }
+
+ /* Check for in-order duplicate regions */
+ if ((x == last_x) && (y == last_y)) {
+ continue;
+ }
+
+ NV2A_DPRINTF("Clipping Region %d: min=(%d, %d) max=(%d, %d)\n",
+ i, x_min, y_min, x_max, y_max);
+
+ state.psh.window_clip_count = i + 1;
+ last_x = x;
+ last_y = y;
+ }
+
for (i = 0; i < 8; i++) {
state.psh.rgb_inputs[i] = pg->regs[NV_PGRAPH_COMBINECOLORI0 + i * 4];
state.psh.rgb_outputs[i] = pg->regs[NV_PGRAPH_COMBINECOLORO0 + i * 4];
@@ -3402,6 +3412,33 @@ static void pgraph_bind_shaders(PGRAPHState *pg)
glUseProgram(pg->shader_binding->gl_program);
+ /* Clipping regions */
+ for (i = 0; i < state.psh.window_clip_count; i++) {
+ if (pg->shader_binding->clip_region_loc[i] == -1) {
+ continue;
+ }
+
+ uint32_t x = pg->regs[NV_PGRAPH_WINDOWCLIPX0 + i * 4];
+ GLuint x_min = GET_MASK(x, NV_PGRAPH_WINDOWCLIPX0_XMIN);
+ GLuint x_max = GET_MASK(x, NV_PGRAPH_WINDOWCLIPX0_XMAX);
+
+ /* Adjust y-coordinates for the OpenGL viewport: translate coordinates
+ * to have the origin at the bottom-left of the surface (as opposed to
+ * top-left), and flip y-min and y-max accordingly.
+ */
+ uint32_t y = pg->regs[NV_PGRAPH_WINDOWCLIPY0 + i * 4];
+ GLuint y_min = (pg->surface_shape.clip_height - 1) -
+ GET_MASK(y, NV_PGRAPH_WINDOWCLIPY0_YMAX);
+ GLuint y_max = (pg->surface_shape.clip_height - 1) -
+ GET_MASK(y, NV_PGRAPH_WINDOWCLIPY0_YMIN);
+
+ pgraph_apply_anti_aliasing_factor(pg, &x_min, &y_min);
+ pgraph_apply_anti_aliasing_factor(pg, &x_max, &y_max);
+
+ glUniform4i(pg->shader_binding->clip_region_loc[i],
+ x_min, y_min, x_max, y_max);
+ }
+
pgraph_update_shader_constants(pg, pg->shader_binding, binding_changed,
vertex_program, fixed_function);
@@ -3630,7 +3667,7 @@ static void pgraph_update_surface_part(NV2AState *d, bool upload, bool color) {
}
surface->buffer_dirty = false;
-
+#ifdef DEBUG_NV2A
uint8_t *out = data + surface->offset + 64;
NV2A_DPRINTF("upload_surface %s 0x%" HWADDR_PRIx " - 0x%" HWADDR_PRIx ", "
"(0x%" HWADDR_PRIx " - 0x%" HWADDR_PRIx ", "
@@ -3644,7 +3681,7 @@ static void pgraph_update_surface_part(NV2AState *d, bool upload, bool color) {
pg->surface_shape.clip_height,
surface->pitch,
out[0], out[1], out[2], out[3]);
-
+#endif
}
if (!upload && surface->draw_dirty) {
@@ -3680,6 +3717,7 @@ static void pgraph_update_surface_part(NV2AState *d, bool upload, bool color) {
surface->draw_dirty = false;
surface->write_enabled_cache = false;
+#ifdef DEBUG_NV2A
uint8_t *out = data + surface->offset + 64;
NV2A_DPRINTF("read_surface %s 0x%" HWADDR_PRIx " - 0x%" HWADDR_PRIx ", "
"(0x%" HWADDR_PRIx " - 0x%" HWADDR_PRIx ", "
@@ -3692,7 +3730,7 @@ static void pgraph_update_surface_part(NV2AState *d, bool upload, bool color) {
pg->surface_shape.clip_width, pg->surface_shape.clip_height,
surface->pitch,
out[0], out[1], out[2], out[3]);
-
+#endif
}
if (swizzle) {
@@ -3810,9 +3848,10 @@ static void pgraph_bind_textures(NV2AState *d)
unsigned int rect_height =
GET_MASK(pg->regs[NV_PGRAPH_TEXIMAGERECT0 + i*4],
NV_PGRAPH_TEXIMAGERECT0_HEIGHT);
-
+#ifdef DEBUG_NV2A
unsigned int lod_bias =
GET_MASK(filter, NV_PGRAPH_TEXFILTER0_MIPMAP_LOD_BIAS);
+#endif
unsigned int min_filter = GET_MASK(filter, NV_PGRAPH_TEXFILTER0_MIN);
unsigned int mag_filter = GET_MASK(filter, NV_PGRAPH_TEXFILTER0_MAG);
@@ -3863,9 +3902,9 @@ static void pgraph_bind_textures(NV2AState *d)
continue;
}
- NV2A_DPRINTF(" texture %d is format 0x%x, (r %d, %d or %d, %d, %d; %d%s),"
+ NV2A_DPRINTF(" texture %d is format 0x%x, off 0x%x (r %d, %d or %d, %d, %d; %d%s),"
" filter %x %x, levels %d-%d %d bias %d\n",
- i, color_format,
+ i, color_format, offset,
rect_width, rect_height,
1 << log_width, 1 << log_height, 1 << log_depth,
pitch,
@@ -4307,44 +4346,6 @@ static unsigned int pgraph_bind_inline_array(NV2AState *d)
return index_count;
}
-static void load_graphics_object(NV2AState *d, hwaddr instance_address,
- GraphicsObject *obj)
-{
- uint8_t *obj_ptr;
- uint32_t switch1, switch2, switch3;
-
- assert(instance_address < d->pramin.ramin_size);
-
- obj_ptr = d->pramin.ramin_ptr + instance_address;
-
- switch1 = ldl_le_p((uint32_t*)obj_ptr);
- switch2 = ldl_le_p((uint32_t*)(obj_ptr + 4));
- switch3 = ldl_le_p((uint32_t*)(obj_ptr + 8));
-
- obj->graphics_class = switch1 & NV_PGRAPH_CTX_SWITCH1_GRCLASS;
-
- /* init graphics object */
- switch (obj->graphics_class) {
- case NV_KELVIN_PRIMITIVE:
- // kelvin->vertex_attributes[NV2A_VERTEX_ATTR_DIFFUSE].inline_value = 0xFFFFFFF;
- break;
- default:
- break;
- }
-}
-
-static GraphicsObject* lookup_graphics_object(PGRAPHState *s,
- hwaddr instance_address)
-{
- int i;
- for (i = 0; isubchannel_data[i].object_instance == instance_address) {
- return &s->subchannel_data[i].object;
- }
- }
- return NULL;
-}
-
/* 16 bit to [0.0, F16_MAX = 511.9375] */
static float convert_f16_to_float(uint16_t f16) {
if (f16 == 0x0000) { return 0.0f; }
@@ -4658,7 +4659,7 @@ static TextureBinding* generate_texture(const TextureShape s,
NV2A_GL_DLABEL(GL_TEXTURE, gl_texture,
"format: 0x%02X%s, %d dimensions%s, width: %d, height: %d, depth: %d",
- s.color_format, {"", " (SZ)", " (DXT)"}[f.encoding],
+ s.color_format, (f.encoding == linear) ? "" : (f.encoding == swizzled) ? " (SZ)" : " (DXT)", // compressed
s.dimensionality, s.cubemap ? " (Cubemap)" : "",
s.width, s.height, s.depth);
diff --git a/src/devices/video/EmuNV2A_PMC.cpp b/src/devices/video/EmuNV2A_PMC.cpp
index e9a11d6b7..7ce9d2078 100644
--- a/src/devices/video/EmuNV2A_PMC.cpp
+++ b/src/devices/video/EmuNV2A_PMC.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_pmc.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PRAMDAC.cpp b/src/devices/video/EmuNV2A_PRAMDAC.cpp
index 217fbcbb4..89f5c382b 100644
--- a/src/devices/video/EmuNV2A_PRAMDAC.cpp
+++ b/src/devices/video/EmuNV2A_PRAMDAC.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_pramdac.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PRAMIN.cpp b/src/devices/video/EmuNV2A_PRAMIN.cpp
index c00766f5f..265b5d6e4 100644
--- a/src/devices/video/EmuNV2A_PRAMIN.cpp
+++ b/src/devices/video/EmuNV2A_PRAMIN.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_stubs.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PRMA.cpp b/src/devices/video/EmuNV2A_PRMA.cpp
index b57701778..58e0a4242 100644
--- a/src/devices/video/EmuNV2A_PRMA.cpp
+++ b/src/devices/video/EmuNV2A_PRMA.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_stubs.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PRMCIO.cpp b/src/devices/video/EmuNV2A_PRMCIO.cpp
index efc6a1f91..69c9ab99d 100644
--- a/src/devices/video/EmuNV2A_PRMCIO.cpp
+++ b/src/devices/video/EmuNV2A_PRMCIO.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_prmcio.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PRMDIO.cpp b/src/devices/video/EmuNV2A_PRMDIO.cpp
index 6432d42b0..13472f719 100644
--- a/src/devices/video/EmuNV2A_PRMDIO.cpp
+++ b/src/devices/video/EmuNV2A_PRMDIO.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_stubs.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PRMFB.cpp b/src/devices/video/EmuNV2A_PRMFB.cpp
index af125829f..65ed63614 100644
--- a/src/devices/video/EmuNV2A_PRMFB.cpp
+++ b/src/devices/video/EmuNV2A_PRMFB.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_stubs.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PRMVIO.cpp b/src/devices/video/EmuNV2A_PRMVIO.cpp
index cd49cce9d..67aa1bc9a 100644
--- a/src/devices/video/EmuNV2A_PRMVIO.cpp
+++ b/src/devices/video/EmuNV2A_PRMVIO.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_prmvio.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PSTRAPS.cpp b/src/devices/video/EmuNV2A_PSTRAPS.cpp
index 802a17a50..ded464e01 100644
--- a/src/devices/video/EmuNV2A_PSTRAPS.cpp
+++ b/src/devices/video/EmuNV2A_PSTRAPS.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_stubs.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PTIMER.cpp b/src/devices/video/EmuNV2A_PTIMER.cpp
index 758cb7e77..508e7efab 100644
--- a/src/devices/video/EmuNV2A_PTIMER.cpp
+++ b/src/devices/video/EmuNV2A_PTIMER.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_ptimer.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
@@ -50,7 +53,7 @@ static uint64_t ptimer_get_clock(NV2AState * d)
uint64_t time = std::chrono::duration_cast(std::chrono::high_resolution_clock::now().time_since_epoch()).count();
return Muldiv64(Muldiv64(time,
- d->pramdac.core_clock_freq,
+ d->pramdac.core_clock_freq, // TODO : Research how this can be updated to accept uint64_t
NANOSECONDS_PER_SECOND), // Was CLOCKS_PER_SEC
d->ptimer.denominator,
d->ptimer.numerator);
diff --git a/src/devices/video/EmuNV2A_PTV.cpp b/src/devices/video/EmuNV2A_PTV.cpp
index 7c7b56a2f..bf3f25bce 100644
--- a/src/devices/video/EmuNV2A_PTV.cpp
+++ b/src/devices/video/EmuNV2A_PTV.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_stubs.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PVIDEO.cpp b/src/devices/video/EmuNV2A_PVIDEO.cpp
index b593d137a..3a6e2cdee 100644
--- a/src/devices/video/EmuNV2A_PVIDEO.cpp
+++ b/src/devices/video/EmuNV2A_PVIDEO.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_pvideo.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_PVPE.cpp b/src/devices/video/EmuNV2A_PVPE.cpp
index 09a1f62e2..9cb762e0b 100644
--- a/src/devices/video/EmuNV2A_PVPE.cpp
+++ b/src/devices/video/EmuNV2A_PVPE.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_stubs.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
diff --git a/src/devices/video/EmuNV2A_USER.cpp b/src/devices/video/EmuNV2A_USER.cpp
index 7a8d4a6bd..8997524b2 100644
--- a/src/devices/video/EmuNV2A_USER.cpp
+++ b/src/devices/video/EmuNV2A_USER.cpp
@@ -28,12 +28,15 @@
// * If not, write to the Free Software Foundation, Inc.,
// * 59 Temple Place - Suite 330, Bostom, MA 02111-1307, USA.
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
-// * (c) 2017-2018 Luke Usher
-// * (c) 2018 Patrick van Logchem
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a_user.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
+// *
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
@@ -45,31 +48,43 @@ DEVICE_READ32(USER)
unsigned int channel_id = addr >> 16;
assert(channel_id < NV2A_NUM_CHANNELS);
- ChannelControl *control = &d->user.channel_control[channel_id];
+ qemu_mutex_lock(&d->pfifo.pfifo_lock);
uint32_t channel_modes = d->pfifo.regs[NV_PFIFO_MODE];
- /* PIO Mode */
- if (!channel_modes & (1 << channel_id)) {
+ uint32_t result = 0;
+ if (channel_modes & (1 << channel_id)) {
+ /* DMA Mode */
+
+ unsigned int cur_channel_id =
+ GET_MASK(d->pfifo.regs[NV_PFIFO_CACHE1_PUSH1],
+ NV_PFIFO_CACHE1_PUSH1_CHID);
+
+ if (channel_id == cur_channel_id) {
+ switch(addr & 0xFFFF) { // Was DEVICE_READ32_SWITCH()
+ case NV_USER_DMA_PUT:
+ result = d->pfifo.regs[NV_PFIFO_CACHE1_DMA_PUT];
+ break;
+ case NV_USER_DMA_GET:
+ result = d->pfifo.regs[NV_PFIFO_CACHE1_DMA_GET];
+ break;
+ case NV_USER_REF:
+ result = d->pfifo.regs[NV_PFIFO_CACHE1_REF];
+ break;
+ default:
+ DEBUG_READ32_UNHANDLED(USER);
+ break;
+ }
+ } else {
+ /* ramfc */
+ assert(false);
+ }
+ } else {
+ /* PIO Mode */
assert(false);
}
- /* DMA Mode */
- addr &= 0xFFFF;
- DEVICE_READ32_SWITCH() {
- case NV_USER_DMA_PUT:
- result = control->dma_put;
- break;
- case NV_USER_DMA_GET:
- result = control->dma_get;
- break;
- case NV_USER_REF:
- result = control->ref;
- break;
- default:
- DEBUG_READ32_UNHANDLED(USER);
- break;
- }
+ qemu_mutex_unlock(&d->pfifo.pfifo_lock);
DEVICE_READ32_END(USER);
}
@@ -79,33 +94,44 @@ DEVICE_WRITE32(USER)
unsigned int channel_id = addr >> 16;
assert(channel_id < NV2A_NUM_CHANNELS);
- ChannelControl *control = &d->user.channel_control[channel_id];
+ qemu_mutex_lock(&d->pfifo.pfifo_lock);
uint32_t channel_modes = d->pfifo.regs[NV_PFIFO_MODE];
if (channel_modes & (1 << channel_id)) {
/* DMA Mode */
- switch (addr & 0xFFFF) {
- case NV_USER_DMA_PUT:
- control->dma_put = value;
+ unsigned int cur_channel_id =
+ GET_MASK(d->pfifo.regs[NV_PFIFO_CACHE1_PUSH1],
+ NV_PFIFO_CACHE1_PUSH1_CHID);
- if (d->pfifo.cache1.push_enabled) {
- pfifo_run_pusher(d);
+ if (channel_id == cur_channel_id) {
+ switch (addr & 0xFFFF) {
+ case NV_USER_DMA_PUT:
+ d->pfifo.regs[NV_PFIFO_CACHE1_DMA_PUT] = value;
+ break;
+ case NV_USER_DMA_GET:
+ d->pfifo.regs[NV_PFIFO_CACHE1_DMA_GET] = value;
+ break;
+ case NV_USER_REF:
+ d->pfifo.regs[NV_PFIFO_CACHE1_REF] = value;
+ break;
+ default:
+ assert(false);
+ break;
}
- break;
- case NV_USER_DMA_GET:
- control->dma_get = value;
- break;
- case NV_USER_REF:
- control->ref = value;
- break;
- default:
- DEBUG_WRITE32_UNHANDLED(USER);
- break;
+
+ // kick pfifo
+ qemu_cond_broadcast(&d->pfifo.pusher_cond);
+ qemu_cond_broadcast(&d->pfifo.puller_cond);
+ } else {
+ /* ramfc */
+ assert(false);
}
} else {
/* PIO Mode */
assert(false);
}
+ qemu_mutex_unlock(&d->pfifo.pfifo_lock);
+
DEVICE_WRITE32_END(USER);
}
diff --git a/src/devices/video/nv2a.cpp b/src/devices/video/nv2a.cpp
index 3e5dd6fc6..67e6a1954 100644
--- a/src/devices/video/nv2a.cpp
+++ b/src/devices/video/nv2a.cpp
@@ -30,13 +30,15 @@
// *
// * (c) 2002-2003 Aaron Robinson
// *
-// * nv2a.cpp is heavily based on code from XQEMU
-// * Copyright(c) 2012 espes
-// * Copyright(c) 2015 Jannik Vogel
-// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
+// * This file is heavily based on code from XQEMU
+// * https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a/nv2a.c
+// * Copyright (c) 2012 espes
+// * Copyright (c) 2015 Jannik Vogel
+// * Copyright (c) 2018 Matt Borgerson
// *
-// * (c) 2016-2018 Luke Usher
-// * (c) 2017-2018 Patrick van Logchem
+// * Contributions for Cxbx-Reloaded
+// * Copyright (c) 2017-2018 Luke Usher
+// * Copyright (c) 2018 Patrick van Logchem
// *
// * All rights reserved
// *
@@ -99,6 +101,9 @@ struct _GError
#include "CxbxKrnl/gloffscreen/glextensions.h" // for glextensions_init
+GLuint create_gl_shader(GLenum gl_shader_type,
+ const char *code,
+ const char *name); // forward to nv2a_shaders.cpp
static void update_irq(NV2AState *d)
{
@@ -1068,10 +1073,10 @@ void NV2ADevice::UpdateHostDisplay(NV2AState *d)
return;
}
- lockGL(pg);
-
NV2A_GL_DGROUP_BEGIN("VGA Frame");
+ glo_set_current(pg->gl_context);
+
cxbx_gl_update_displaymode(d);
for (int v = 0; v < 2; v++) {
@@ -1114,7 +1119,7 @@ void NV2ADevice::UpdateHostDisplay(NV2AState *d)
NV2A_GL_DGROUP_END();
- unlockGL(pg);
+// glo_set_current(NULL);
UpdateFPSCounter();
}
@@ -1224,8 +1229,6 @@ void NV2ADevice::Init()
d->pramdac.video_clock_coeff = 0x0003C20D; /* 25182Khz...? */
// Setup the conditions/mutexes
- qemu_mutex_init(&d->pfifo.cache1.cache_lock);
- qemu_cond_init(&d->pfifo.cache1.cache_cond);
pgraph_init(d);
// Only spawn VBlank thread when LLE is enabled
@@ -1235,7 +1238,16 @@ void NV2ADevice::Init()
vblank_thread = std::thread(nv2a_vblank_thread, d);
}
+ qemu_mutex_init(&d->pfifo.pfifo_lock);
+ qemu_cond_init(&d->pfifo.puller_cond);
+ qemu_cond_init(&d->pfifo.pusher_cond);
+
+ d->pfifo.regs[NV_PFIFO_CACHE1_STATUS] |= NV_PFIFO_CACHE1_STATUS_LOW_MARK;
+
+ /* fire up puller */
d->pfifo.puller_thread = std::thread(pfifo_puller_thread, d);
+ /* fire up pusher */
+ d->pfifo.pusher_thread = std::thread(pfifo_pusher_thread, d);
}
void NV2ADevice::Reset()
@@ -1244,17 +1256,18 @@ void NV2ADevice::Reset()
if (!d) return;
d->exiting = true;
- qemu_cond_signal(&d->pfifo.cache1.cache_cond);
- d->pfifo.puller_thread.join(); // was qemu_thread_join(&d->pfifo.puller_thread);
+ qemu_cond_broadcast(&d->pfifo.puller_cond);
+ qemu_cond_broadcast(&d->pfifo.pusher_cond);
+ d->pfifo.puller_thread.join();
+ d->pfifo.pusher_thread.join();
+ qemu_mutex_destroy(&d->pfifo.pfifo_lock); // Cbxbx addition
if (d->pgraph.opengl_enabled) {
vblank_thread.join();
pvideo_destroy(d);
}
pgraph_destroy(&d->pgraph);
- qemu_mutex_destroy(&d->pfifo.cache1.cache_lock);
- qemu_cond_destroy(&d->pfifo.cache1.cache_cond);
}
uint32_t NV2ADevice::IORead(int barIndex, uint32_t port, unsigned size)
diff --git a/src/devices/video/nv2a.h b/src/devices/video/nv2a.h
index 93002668b..6f2ae71c5 100644
--- a/src/devices/video/nv2a.h
+++ b/src/devices/video/nv2a.h
@@ -34,553 +34,9 @@
// ******************************************************************
#pragma once
-#undef USE_SHADER_CACHE
-
-#ifdef USE_SHADER_CACHE
-#include "glib_compat.h" // For GHashTable, g_hash_table_new, g_hash_table_lookup, g_hash_table_insert
-#endif
-
-#include "Cxbx.h" // For xbaddr
#include "devices\PCIDevice.h" // For PCIDevice
-#include
-#include
-
-#include
-
-#include "swizzle.h"
-#include "nv2a_int.h"
-#include "nv2a_debug.h" // For HWADDR_PRIx, NV2A_DPRINTF, NV2A_GL_DPRINTF, etc.
-#include "CxbxKrnl/gloffscreen/gloffscreen.h"
-#include "qemu-thread.h" // For qemu_mutex, etc
-#include "nv2a_shaders.h" // For ShaderBinding
-
-#define NV_PMC_SIZE 0x001000
-#define _NV_PFIFO_SIZE 0x002000 // Underscore prefix to prevent clash with NV_PFIFO_SIZE
-#define NV_PVIDEO_SIZE 0x001000
-#define NV_PTIMER_SIZE 0x001000
-#define NV_PFB_SIZE 0x001000
-#define NV_PGRAPH_SIZE 0x002000
-#define NV_PCRTC_SIZE 0x001000
-#define NV_PRAMDAC_SIZE 0x001000
-
-typedef xbaddr hwaddr; // Compatibility; Cxbx uses xbaddr, xqemu and OpenXbox use hwaddr
-typedef uint32_t value_t; // Compatibility; Cxbx values are uint32_t (xqemu and OpenXbox use uint64_t)
-
-#ifdef __cplusplus
-template struct ArraySizeHelper { char _[N]; };
-template
-ArraySizeHelper makeArraySizeHelper(T(&)[N]);
-# define ARRAY_SIZE(a) sizeof(makeArraySizeHelper(a))
-#else
-// The expression ARRAY_SIZE(a) is a compile-time constant of type
-// size_t which represents the number of elements of the given
-// array. You should only use ARRAY_SIZE on statically allocated
-// arrays.
-
-#define ARRAY_SIZE(a) \
- ((sizeof(a) / sizeof(*(a))) / \
- static_cast(!(sizeof(a) % sizeof(*(a)))))
-#endif
-
-#define VSH_TOKEN_SIZE 4 // Compatibility; TODO : Move this to nv2a_vsh.h
-#define MAX(a,b) ((a)>(b) ? (a) : (b)) // Compatibility
-#define MIN(a,b) ((a)<(b) ? (a) : (b)) // Compatibility
-
-#define g_free(x) free(x) // Compatibility
-#define g_malloc(x) malloc(x) // Compatibility
-#define g_malloc0(x) calloc(1, x) // Compatibility
-#define g_realloc(x, y) realloc(x, y) // Compatibility
-
-#undef USE_TEXTURE_CACHE
-
-#if __cplusplus >= 201402L
-# define NV2A_CONSTEXPR constexpr
-#else
-# define NV2A_CONSTEXPR static
-#endif
-
-// GCC implementation of FFS
-static int ffs(register int valu)
-{
- register int bit;
-
- if (valu == 0)
- return 0;
-
- for (bit = 1; !(valu & 1); bit++)
- valu >>= 1;
-
- return bit;
-}
-
-#define GET_MASK(v, mask) (((v) & (mask)) >> (ffs(mask)-1))
-
-#define SET_MASK(v, mask, val) \
- do { \
- (v) &= ~(mask); \
- (v) |= ((val) << (ffs(mask)-1)) & (mask); \
- } while (0)
-
-// Power-of-two CASE statements
-#define CASE_1(v, step) case (v)
-#define CASE_2(v, step) CASE_1(v, step) : CASE_1(v + (step) * 1, step)
-#define CASE_4(v, step) CASE_2(v, step) : CASE_2(v + (step) * 2, step)
-#define CASE_8(v, step) CASE_4(v, step) : CASE_4(v + (step) * 4, step)
-#define CASE_16(v, step) CASE_8(v, step) : CASE_8(v + (step) * 8, step)
-#define CASE_32(v, step) CASE_16(v, step) : CASE_16(v + (step) * 16, step)
-#define CASE_64(v, step) CASE_32(v, step) : CASE_32(v + (step) * 32, step)
-#define CASE_128(v, step) CASE_64(v, step) : CASE_64(v + (step) * 64, step)
-#define CASE_256(v, step) CASE_128(v, step) : CASE_128(v + (step) * 128, step)
-
-// Non-power-of-two CASE statements
-#define CASE_3(v, step) CASE_2(v, step) : CASE_1(v + (step) * 2, step)
-
-#define NV2A_DEVICE(obj) \
- OBJECT_CHECK(NV2AState, (obj), "nv2a")
-
-//void reg_log_read(int block, hwaddr addr, uint64_t val);
-//void reg_log_write(int block, hwaddr addr, uint64_t val);
-
-enum FifoMode {
- FIFO_PIO = 0,
- FIFO_DMA = 1,
-};
-
-enum FIFOEngine {
- ENGINE_SOFTWARE = 0,
- ENGINE_GRAPHICS = 1,
- ENGINE_DVD = 2,
-};
-
-typedef struct DMAObject {
- unsigned int dma_class;
- unsigned int dma_target;
- xbaddr address;
- xbaddr limit;
-} DMAObject;
-
-typedef struct VertexAttribute {
- bool dma_select;
- xbaddr offset;
-
- /* inline arrays are packed in order?
- * Need to pass the offset to converted attributes */
- unsigned int inline_array_offset;
-
- float inline_value[4];
-
- unsigned int format;
- unsigned int size; /* size of the data type */
- unsigned int count; /* number of components */
- uint32_t stride;
-
- bool needs_conversion;
- uint8_t *converted_buffer;
- unsigned int converted_elements;
- unsigned int converted_size;
- unsigned int converted_count;
-
- float *inline_buffer;
-
- GLint gl_count;
- GLenum gl_type;
- GLboolean gl_normalize;
-
- GLuint gl_converted_buffer;
- GLuint gl_inline_buffer;
-} VertexAttribute;
-
-typedef struct Surface {
- bool draw_dirty;
- bool buffer_dirty;
- bool write_enabled_cache;
- unsigned int pitch;
-
- xbaddr offset;
-} Surface;
-
-typedef struct SurfaceShape {
- unsigned int z_format;
- unsigned int color_format;
- unsigned int zeta_format;
- unsigned int log_width, log_height;
- unsigned int clip_x, clip_y;
- unsigned int clip_width, clip_height;
- unsigned int anti_aliasing;
-} SurfaceShape;
-
-typedef struct TextureShape {
- bool cubemap;
- unsigned int dimensionality;
- unsigned int color_format;
- unsigned int levels;
- unsigned int width, height, depth;
-
- unsigned int min_mipmap_level, max_mipmap_level;
- unsigned int pitch;
-} TextureShape;
-
-typedef struct TextureKey {
- TextureShape state;
- uint64_t data_hash;
- uint8_t* texture_data;
- uint8_t* palette_data;
-} TextureKey;
-
-typedef struct TextureBinding {
- GLenum gl_target;
- GLuint gl_texture;
- unsigned int refcnt;
-} TextureBinding;
-
-typedef struct KelvinState {
- xbaddr dma_notifies;
- xbaddr dma_state;
- xbaddr dma_semaphore;
- unsigned int semaphore_offset;
-} KelvinState;
-
-typedef struct ContextSurfaces2DState {
- xbaddr dma_image_source;
- xbaddr dma_image_dest;
- unsigned int color_format;
- unsigned int source_pitch, dest_pitch;
- xbaddr source_offset, dest_offset;
-
-} ContextSurfaces2DState;
-
-typedef struct ImageBlitState {
- xbaddr context_surfaces;
- unsigned int operation;
- unsigned int in_x, in_y;
- unsigned int out_x, out_y;
- unsigned int width, height;
-
-} ImageBlitState;
-
-typedef struct GraphicsObject {
- uint8_t graphics_class;
- union {
- ContextSurfaces2DState context_surfaces_2d;
-
- ImageBlitState image_blit;
-
- KelvinState kelvin;
- } data;
-} GraphicsObject;
-
-typedef struct GraphicsSubchannel {
- xbaddr object_instance;
- GraphicsObject object;
- uint32_t object_cache[5];
-} GraphicsSubchannel;
-
-typedef struct GraphicsContext {
- bool channel_3d;
- unsigned int subchannel;
-} GraphicsContext;
-
-
-typedef struct PGRAPHState {
- bool opengl_enabled; // == bLLE_GPU
- QemuMutex lock;
-
- uint32_t pending_interrupts;
- uint32_t enabled_interrupts;
- QemuCond interrupt_cond;
-
- xbaddr context_table;
- xbaddr context_address;
-
-
- unsigned int trapped_method;
- unsigned int trapped_subchannel;
- unsigned int trapped_channel_id;
- uint32_t trapped_data[2];
- uint32_t notify_source;
-
- bool fifo_access;
- QemuCond fifo_access_cond;
-
- QemuCond flip_3d;
-
- unsigned int channel_id;
- bool channel_valid;
- GraphicsContext context[NV2A_NUM_CHANNELS];
-
- xbaddr dma_color, dma_zeta;
- Surface surface_color, surface_zeta;
- unsigned int surface_type;
- SurfaceShape surface_shape;
- SurfaceShape last_surface_shape;
-
- xbaddr dma_a, dma_b;
-#ifdef USE_TEXTURE_CACHE
- GLruCache *texture_cache;
-#endif
- bool texture_dirty[NV2A_MAX_TEXTURES];
- TextureBinding *texture_binding[NV2A_MAX_TEXTURES];
-
-#ifdef USE_SHADER_CACHE
- GHashTable *shader_cache;
-#endif
- ShaderBinding *shader_binding;
-
- bool texture_matrix_enable[NV2A_MAX_TEXTURES];
-
- /* FIXME: Move to NV_PGRAPH_BUMPMAT... */
- float bump_env_matrix[NV2A_MAX_TEXTURES - 1][4]; /* 3 allowed stages with 2x2 matrix each */
-
- GloContext *gl_context;
- QemuMutex gl_lock;
-
- GLuint gl_framebuffer;
- GLuint gl_color_buffer, gl_zeta_buffer;
- GraphicsSubchannel subchannel_data[NV2A_NUM_SUBCHANNELS];
-
- xbaddr dma_report;
- xbaddr report_offset;
- bool zpass_pixel_count_enable;
- unsigned int zpass_pixel_count_result;
- unsigned int gl_zpass_pixel_count_query_count;
- GLuint* gl_zpass_pixel_count_queries;
-
- xbaddr dma_vertex_a, dma_vertex_b;
-
- unsigned int primitive_mode;
-
- unsigned int clear_surface;
-
- bool enable_vertex_program_write;
-
- uint32_t program_data[NV2A_MAX_TRANSFORM_PROGRAM_LENGTH][VSH_TOKEN_SIZE];
-
- uint32_t vsh_constants[NV2A_VERTEXSHADER_CONSTANTS][4];
- bool vsh_constants_dirty[NV2A_VERTEXSHADER_CONSTANTS];
-
- /* lighting constant arrays */
- uint32_t ltctxa[NV2A_LTCTXA_COUNT][4];
- bool ltctxa_dirty[NV2A_LTCTXA_COUNT];
- uint32_t ltctxb[NV2A_LTCTXB_COUNT][4];
- bool ltctxb_dirty[NV2A_LTCTXB_COUNT];
- uint32_t ltc1[NV2A_LTC1_COUNT][4];
- bool ltc1_dirty[NV2A_LTC1_COUNT];
-
- // should figure out where these are in lighting context
- float light_infinite_half_vector[NV2A_MAX_LIGHTS][3];
- float light_infinite_direction[NV2A_MAX_LIGHTS][3];
- float light_local_position[NV2A_MAX_LIGHTS][3];
- float light_local_attenuation[NV2A_MAX_LIGHTS][3];
-
- VertexAttribute vertex_attributes[NV2A_VERTEXSHADER_ATTRIBUTES];
-
- unsigned int inline_array_length;
- uint32_t inline_array[NV2A_MAX_BATCH_LENGTH];
- GLuint gl_inline_array_buffer;
-
- unsigned int inline_elements_length;
- uint16_t inline_elements[NV2A_MAX_BATCH_LENGTH]; // Cxbx-Reloaded TODO : Restore uint32_t once HLE_draw_inline_elements can using that
-
-
- unsigned int inline_buffer_length;
-
- unsigned int draw_arrays_length;
- unsigned int draw_arrays_max_count;
-
- /* FIXME: Unknown size, possibly endless, 1000 will do for now */
- GLint gl_draw_arrays_start[1000];
- GLsizei gl_draw_arrays_count[1000];
-
- GLuint gl_element_buffer;
- GLuint gl_memory_buffer;
- GLuint gl_vertex_array;
-
- uint32_t regs[NV_PGRAPH_SIZE]; // TODO : union
-} PGRAPHState;
-
-#define lockGL(x) lockGL_(x, __LINE__)
-static void lockGL_(PGRAPHState* pg, unsigned int line) {
- //printf("Locking from line %d\n", line);
- qemu_mutex_lock(&pg->gl_lock);
- if (pg->opengl_enabled) {
- glo_set_current(pg->gl_context);
- }
-}
-
-#define unlockGL(x) unlockGL_(x, __LINE__)
-static void unlockGL_(PGRAPHState* pg, unsigned int line) {
- //printf("Unlocking from line %d\n", line);
- if (pg->opengl_enabled) {
- glo_set_current(NULL);
- }
- qemu_mutex_unlock(&pg->gl_lock);
-}
-
-typedef struct CacheEntry {
- //QSIMPLEQ_ENTRY(CacheEntry) entry;
- unsigned int method : 14;
- unsigned int subchannel : 3;
- bool nonincreasing;
- uint32_t parameter;
-} CacheEntry;
-
-typedef struct Cache1State {
- unsigned int channel_id;
- FifoMode mode;
-
- /* Pusher state */
- bool push_enabled;
- bool dma_push_enabled;
- bool dma_push_suspended;
- xbaddr dma_instance;
-
- bool method_nonincreasing;
- unsigned int method : 14;
- unsigned int subchannel : 3;
- unsigned int method_count : 24;
- uint32_t dcount;
-
- bool subroutine_active;
- xbaddr subroutine_return;
- xbaddr get_jmp_shadow;
- uint32_t rsvd_shadow;
- uint32_t data_shadow;
- uint32_t error;
-
- bool pull_enabled;
- enum FIFOEngine bound_engines[NV2A_NUM_SUBCHANNELS];
- enum FIFOEngine last_engine;
-
- /* The actual command queue */
- QemuMutex cache_lock;
- QemuCond cache_cond;
- std::queue cache;
- std::queue working_cache;
-} Cache1State;
-
-typedef struct OverlayState {
- bool video_buffer_use;
- int pitch;
- bool is_transparent;
-#ifdef DEBUG
- hwaddr base;
- hwaddr limit;
-#endif
- hwaddr offset;
- uint32_t in_height;
- uint32_t in_width;
- int out_x;
- int out_y;
- int out_width;
- int out_height;
-
- bool covers_framebuffer;
- int old_in_width;
- int old_in_height;
- int old_pitch;
- GLuint gl_texture;
-} OverlayState;
-
-typedef struct ChannelControl {
- xbaddr dma_put;
- xbaddr dma_get;
- uint32_t ref;
-} ChannelControl;
-
-typedef struct NV2AState {
- // PCIDevice dev;
- // qemu_irq irq;
- bool exiting;
- bool enable_overlay = false;
-
- // VGACommonState vga;
- // GraphicHwOps hw_ops;
- // QEMUTimer *vblank_timer;
-
- // MemoryRegion *vram;
- // MemoryRegion vram_pci;
- uint8_t *vram_ptr;
- size_t vram_size;
- // MemoryRegion ramin;
- struct {
- uint8_t *ramin_ptr;
- size_t ramin_size;
- } pramin;
-
- // MemoryRegion mmio;
- // MemoryRegion block_mmio[NV_NUM_BLOCKS];
-
- struct {
- uint32_t pending_interrupts;
- uint32_t enabled_interrupts;
- uint32_t regs[NV_PMC_SIZE]; // Not in xqemu/openxbox? TODO : union
- } pmc;
-
- struct {
- std::thread puller_thread;
- uint32_t pending_interrupts;
- uint32_t enabled_interrupts;
- Cache1State cache1;
- uint32_t regs[_NV_PFIFO_SIZE]; // TODO : union
- } pfifo;
-
- struct {
- uint32_t pending_interrupts;
- uint32_t enabled_interrupts;
- //QemuCond interrupt_cond; // pvideo.interrupt_cond not used (yet)
- OverlayState overlays[2]; // NV2A supports 2 video overlays
- uint32_t regs[NV_PVIDEO_SIZE]; // TODO : union
- } pvideo;
-
- struct {
- uint32_t pending_interrupts;
- uint32_t enabled_interrupts;
- uint32_t numerator;
- uint32_t denominator;
- uint32_t alarm_time;
- uint32_t regs[NV_PTIMER_SIZE]; // Not in xqemu/openxbox? TODO : union
- } ptimer;
-
- struct {
- uint32_t regs[NV_PFB_SIZE]; // TODO : union
- } pfb;
-
- struct PGRAPHState pgraph;
-
- struct {
- uint32_t pending_interrupts;
- uint32_t enabled_interrupts;
- hwaddr start;
- uint32_t regs[NV_PCRTC_SIZE]; // Not in xqemu/openxbox? TODO : union
- } pcrtc;
-
- struct {
- uint32_t core_clock_coeff;
- uint64_t core_clock_freq;
- uint32_t memory_clock_coeff;
- uint32_t video_clock_coeff;
- uint32_t regs[NV_PRAMDAC_SIZE]; // Not in xqemu/openxbox? TODO : union
- } pramdac;
-
- struct {
- ChannelControl channel_control[NV2A_NUM_CHANNELS];
- } user;
-
- // PRMCIO (Actually the VGA controller)
- struct {
- uint8_t cr_index;
- uint8_t cr[256]; /* CRT registers */
- } prmcio; // Not in xqemu/openxbox?
-} NV2AState;
-
-typedef value_t(*read_func)(NV2AState *d, hwaddr addr); //, unsigned int size);
-typedef void(*write_func)(NV2AState *d, hwaddr addr, value_t val); //, unsigned int size);
-
-typedef struct {
- read_func read;
- write_func write;
-} MemoryRegionOps;
+#include "nv2a_int.h" // For NV2AState
typedef struct NV2ABlockInfo {
const char* name;
@@ -591,69 +47,8 @@ typedef struct NV2ABlockInfo {
const NV2ABlockInfo* EmuNV2A_Block(xbaddr addr);
-#if 0
-// Valid after PCI init :
-#define NV20_REG_BASE_KERNEL 0xFD000000
-
-typedef volatile DWORD *PPUSH;
-
-typedef struct {
- DWORD Ignored[0x10];
- PPUSH Put; // On Xbox1, this field is only written to by the CPU (the GPU uses this as a trigger to start executing from the given address)
- PPUSH Get; // On Xbox1, this field is only read from by the CPU (the GPU reflects in here where it is/stopped executing)
- PPUSH Reference; // TODO : xbaddr / void* / DWORD ?
- DWORD Ignored2[0x7ED];
-} Nv2AControlDma;
-
-#define PUSH_TYPE_MASK 0x00000002 // 2 bits
-#define PUSH_TYPE_SHIFT 0
-#define PUSH_TYPE_METHOD 0 // method
-#define PUSH_TYPE_JMP_FAR 1 // jump far
-#define PUSH_TYPE_CALL_FAR 2 // call far
-#define PUSH_TYPE_METHOD_UNUSED 3 // method (unused)
-#define PUSH_METHOD_MASK 0x00001FFC // 12 bits
-#define PUSH_METHOD_SHIFT 0 // Dxbx note : Not 2, because methods are actually DWORD offsets (and thus defined with increments of 4)
-#define PUSH_SUBCH_MASK 0x0000E000 // 3 bits
-#define PUSH_SUBCH_SHIFT 13
-#define PUSH_COUNT_MASK 0x1FFC0000 // 11 bits
-#define PUSH_COUNT_SHIFT 18
-#define PUSH_INSTR_MASK 0xE0000000 // 3 bits
-#define PUSH_INSTR_SHIFT 29
-#define PUSH_INSTR_IMM_INCR 0 // immediate, increment
-#define PUSH_INSTR_JMP_NEAR 1 // near jump
-#define PUSH_INSTR_IMM_NOINC 2 // immediate, no-increment
-#define PUSH_ADDR_FAR_MASK 0xFFFFFFFC // 30 bits
-#define PUSH_ADDR_FAR_SHIFT 0
-#define PUSH_ADDR_NEAR_MASK 0x1FFFFFFC // 27 bits
-#define PUSH_ADDR_NEAR_SHIFT 0 // Cxbx note : Not 2, because methods are actually DWORD offsets (and thus defined with increments of 4)
-
-#define PUSH_TYPE(dwPushCommand) ((dwPushCommand & PUSH_TYPE_MASK) >> PUSH_TYPE_SHIFT)
-#define PUSH_METHOD(dwPushCommand) ((dwPushCommand & PUSH_METHOD_MASK) >> PUSH_METHOD_SHIFT)
-#define PUSH_SUBCH(dwPushCommand) ((dwPushCommand & PUSH_SUBCH_MASK) >> PUSH_SUBCH_SHIFT)
-#define PUSH_COUNT(dwPushCommand) ((dwPushCommand & PUSH_COUNT_MASK) >> PUSH_COUNT_SHIFT)
-#define PUSH_INSTR(dwPushCommand) ((dwPushCommand & PUSH_INSTR_MASK) >> PUSH_INSTR_SHIFT)
-#define PUSH_ADDR_FAR(dwPushCommand) ((dwPushCommand & PUSH_ADDR_FAR_MASK) >> PUSH_ADDR_FAR_SHIFT)
-#define PUSH_ADDR_NEAR(dwPushCommand) ((dwPushCommand & PUSH_ADDR_NEAR_MASK) >> PUSH_ADDR_NEAR_SHIFT)
-
-#define PUSH_METHOD_MAX ((PUSH_METHOD_MASK | 3) >> PUSH_METHOD_SHIFT) // = 8191
-#define PUSH_SUBCH_MAX (PUSH_SUBCH_MASK >> PUSH_SUBCH_SHIFT) // = 7
-#define PUSH_COUNT_MAX (PUSH_COUNT_MASK >> PUSH_COUNT_SHIFT) // = 2047
-
-// Decode push buffer conmmand (inverse of D3DPUSH_ENCODE)
-inline void D3DPUSH_DECODE(const DWORD dwPushCommand, DWORD &dwMethod, DWORD &dwSubCh, DWORD &dwCount)
-{
- dwMethod = PUSH_METHOD(dwPushCommand);
- dwSubCh = PUSH_SUBCH(dwPushCommand);
- dwCount = PUSH_COUNT(dwPushCommand);
-}
-#endif
-
void CxbxReserveNV2AMemory(NV2AState *d);
-GLuint create_gl_shader(GLenum gl_shader_type,
- const char *code,
- const char *name); // forward to nv2a_shaders.cpp
-
class NV2ADevice : public PCIDevice {
public:
// constructor
diff --git a/src/devices/video/nv2a_debug.cpp b/src/devices/video/nv2a_debug.cpp
index 44d7ceb8b..206c45d9e 100644
--- a/src/devices/video/nv2a_debug.cpp
+++ b/src/devices/video/nv2a_debug.cpp
@@ -23,6 +23,7 @@
#ifdef DEBUG_NV2A_GL
#include
+#include
#include
#include
diff --git a/src/devices/video/nv2a_debug.h b/src/devices/video/nv2a_debug.h
index d0bfcd868..0e4b7dc07 100644
--- a/src/devices/video/nv2a_debug.h
+++ b/src/devices/video/nv2a_debug.h
@@ -25,9 +25,6 @@
// Enable for NV2A Debug logging (Warning: Slow!)
// #define DEBUG_NV2A
-#include "CxbxKrnl/gloffscreen/gloffscreen.h"
-#include "CxbxKrnl/gloffscreen/glextensions.h"
-
#ifdef DEBUG_NV2A
# define NV2A_DPRINTF(format, ...) printf("[0x????] NV2A: " format, ## __VA_ARGS__)
#else
@@ -39,6 +36,9 @@
#ifdef DEBUG_NV2A_GL
#include
+#include "CxbxKrnl/gloffscreen/gloffscreen.h"
+#include "CxbxKrnl/gloffscreen/glextensions.h"
+
void gl_debug_message(bool cc, const char *fmt, ...);
void gl_debug_group_begin(const char *fmt, ...);
void gl_debug_group_end(void);
diff --git a/src/devices/video/nv2a_int.h b/src/devices/video/nv2a_int.h
index 62cf9aa02..c26d1180b 100644
--- a/src/devices/video/nv2a_int.h
+++ b/src/devices/video/nv2a_int.h
@@ -1,9 +1,10 @@
-// Source : https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a_int.h
+// Source : https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a_int.h
/*
* QEMU Geforce NV2A internal definitions
*
* Copyright (c) 2012 espes
* Copyright (c) 2015 Jannik Vogel
+ * Copyright (c) 2018 Matt Borgerson
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,1754 +20,506 @@
* along with this program; if not, see .
*/
-#define NV_NUM_BLOCKS 21
-#define NV_PMC 0 /* card master control */
-#define NV_PBUS 1 /* bus control */
-#define NV_PFIFO 2 /* MMIO and DMA FIFO submission to PGRAPH and VPE */
-#define NV_PFIFO_CACHE 3
-#define NV_PRMA 4 /* access to BAR0/BAR1 from real mode */
-#define NV_PVIDEO 5 /* video overlay */
-#define NV_PTIMER 6 /* time measurement and time-based alarms */
-#define NV_PCOUNTER 7 /* performance monitoring counters */
-#define NV_PVPE 8 /* MPEG2 decoding engine */
-#define NV_PTV 9 /* TV encoder */
-#define NV_PRMFB 10 /* aliases VGA memory window */
-#define NV_PRMVIO 11 /* aliases VGA sequencer and graphics controller registers */
-#define NV_PFB 12 /* memory interface */
-#define NV_PSTRAPS 13 /* straps readout / override */
-#define NV_PGRAPH 14 /* accelerated 2d/3d drawing engine */
-#define NV_PCRTC 15 /* more CRTC controls */
-#define NV_PRMCIO 16 /* aliases VGA CRTC and attribute controller registers */
-#define NV_PRAMDAC 17 /* RAMDAC, cursor, and PLL control */
-#define NV_PRMDIO 18 /* aliases VGA palette registers */
-#define NV_PRAMIN 19 /* RAMIN access */
-#define NV_USER 20 /* PFIFO MMIO and DMA submission area */
+#ifndef HW_NV2A_INT_H
+#define HW_NV2A_INT_H
-#define NV_PMC_BOOT_0 0x00000000
-#define NV_PMC_BOOT_1 0x00000004
-#define NV_PMC_INTR_0 0x00000100
-# define NV_PMC_INTR_0_PFIFO (1 << 8)
-# define NV_PMC_INTR_0_PGRAPH (1 << 12)
-# define NV_PMC_INTR_0_PVIDEO (1 << 16)
-# define NV_PMC_INTR_0_PTIMER (1 << 20)
-# define NV_PMC_INTR_0_PCRTC (1 << 24)
-# define NV_PMC_INTR_0_PCRTC2 (1 << 25)
-# define NV_PMC_INTR_0_PBUS (1 << 28)
-# define NV_PMC_INTR_0_SOFTWARE (1 << 31)
-#define NV_PMC_INTR_EN_0 0x00000140
-# define NV_PMC_INTR_EN_0_HARDWARE 1
-# define NV_PMC_INTR_EN_0_SOFTWARE 2
-#define NV_PMC_ENABLE 0x00000200
-# define NV_PMC_ENABLE_PFIFO (1 << 8)
-# define NV_PMC_ENABLE_PGRAPH (1 << 12)
-# define NV_PMC_ENABLE_PFB (1 << 20)
-# define NV_PMC_ENABLE_PCRTC (1 << 24)
-# define NV_PMC_ENABLE_PCRTC2 (1 << 25)
-# define NV_PMC_ENABLE_PVIDEO (1 << 28)
+#undef USE_SHADER_CACHE
+
+#include
+#include
+#include
+
+#include "Cxbx.h" // For xbaddr
+
+#include "qemu-thread.h" // For qemu_mutex, etc
+
+#ifdef USE_SHADER_CACHE
+#include "glib_compat.h" // For GHashTable, g_hash_table_new, g_hash_table_lookup, g_hash_table_insert
+#endif
+#include "CxbxKrnl/gloffscreen/gloffscreen.h" // For GloContext, etc
+
+#include "swizzle.h"
+
+#include "nv2a_debug.h" // For HWADDR_PRIx, NV2A_DPRINTF, NV2A_GL_DPRINTF, etc.
+#include "nv2a_shaders.h" // For ShaderBinding, etc
+#include "nv2a_regs.h" // For NV2A_MAX_TEXTURES, etc
-#define NV_PBUS_FBIO_RAM 0x00000218
-# define NV_PBUS_FBIO_RAM_TYPE 0x00000100
-# define NV_PBUS_FBIO_RAM_TYPE_DDR (0 << 8)
-# define NV_PBUS_FBIO_RAM_TYPE_SDR (1 << 8)
-/* These map approximately to the pci registers */
-#define NV_PBUS_PCI_NV_0 0x00000800
-# define NV_PBUS_PCI_NV_0_VENDOR_ID 0x0000FFFF
-# define NV_CONFIG_PCI_NV_0_DEVICE_ID 0xFFFF0000
-#define NV_PBUS_PCI_NV_1 0x00000804
-#define NV_PBUS_PCI_NV_2 0x00000808
-# define NV_PBUS_PCI_NV_2_REVISION_ID 0x000000FF
-# define NV_PBUS_PCI_NV_2_CLASS_CODE 0xFFFFFF00
-#define NV_PBUS_PCI_NV_3 0x0000080C
-#define NV_PBUS_PCI_NV_4 0x00000810
-#define NV_PBUS_PCI_NV_5 0x00000814
-#define NV_PBUS_PCI_NV_6 0x00000818
-#define NV_PBUS_PCI_NV_7 0x0000081C
-#define NV_PBUS_PCI_NV_11 0x0000082C
-#define NV_PBUS_PCI_NV_12 0x00000830
-#define NV_PBUS_PCI_NV_13 0x00000834
-#define NV_PBUS_PCI_NV_14 0x00000838
-#define NV_PBUS_PCI_NV_15 0x0000083C
-#define NV_PBUS_PCI_NV_16 0x00000840
-#define NV_PBUS_PCI_NV_17 0x00000844
-#define NV_PBUS_PCI_NV_18 0x00000848
-#define NV_PBUS_PCI_NV_19 0x0000084C
-#define NV_PBUS_PCI_NV_20 0x00000850
-#define NV_PBUS_PCI_NV_21 0x00000854
-#define NV_PBUS_PCI_NV_22 0x00000858
-#define NV_PBUS_PCI_NV_23 0x0000085C
-#define NV_PBUS_PCI_NV_24 0x00000860
-#define NV_PBUS_PCI_NV_25 0x00000864
-#define NV_PBUS_PCI_NV_26 0x00000868
+typedef xbaddr hwaddr; // Compatibility; Cxbx uses xbaddr, xqemu and OpenXbox use hwaddr
+typedef uint32_t value_t; // Compatibility; Cxbx values are uint32_t (xqemu and OpenXbox use uint64_t)
+#ifdef __cplusplus
+template struct ArraySizeHelper { char _[N]; };
+template
+ArraySizeHelper makeArraySizeHelper(T(&)[N]);
+# define ARRAY_SIZE(a) sizeof(makeArraySizeHelper(a))
+#else
+// The expression ARRAY_SIZE(a) is a compile-time constant of type
+// size_t which represents the number of elements of the given
+// array. You should only use ARRAY_SIZE on statically allocated
+// arrays.
-#define NV_PFIFO_DELAY_0 0x00000040
-#define NV_PFIFO_DMA_TIMESLICE 0x00000044
-#define NV_PFIFO_TIMESLICE 0x0000004C
-#define NV_PFIFO_INTR_0 0x00000100
-# define NV_PFIFO_INTR_0_CACHE_ERROR (1 << 0)
-# define NV_PFIFO_INTR_0_RUNOUT (1 << 4)
-# define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW (1 << 8)
-# define NV_PFIFO_INTR_0_DMA_PUSHER (1 << 12)
-# define NV_PFIFO_INTR_0_DMA_PT (1 << 16)
-# define NV_PFIFO_INTR_0_SEMAPHORE (1 << 20)
-# define NV_PFIFO_INTR_0_ACQUIRE_TIMEOUT (1 << 24)
-#define NV_PFIFO_INTR_EN_0 0x00000140
-# define NV_PFIFO_INTR_EN_0_CACHE_ERROR (1 << 0)
-# define NV_PFIFO_INTR_EN_0_RUNOUT (1 << 4)
-# define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW (1 << 8)
-# define NV_PFIFO_INTR_EN_0_DMA_PUSHER (1 << 12)
-# define NV_PFIFO_INTR_EN_0_DMA_PT (1 << 16)
-# define NV_PFIFO_INTR_EN_0_SEMAPHORE (1 << 20)
-# define NV_PFIFO_INTR_EN_0_ACQUIRE_TIMEOUT (1 << 24)
-#define NV_PFIFO_RAMHT 0x00000210
-//# define NV_PFIFO_RAMHT_BASE_ADDRESS 0x000001F0
-# define NV_PFIFO_RAMHT_BASE_ADDRESS_MASK 0x000001F0
-# define NV_PFIFO_RAMHT_BASE_ADDRESS_SHIFT 4
-# define NV_PFIFO_RAMHT_BASE_ADDRESS_MOVE 12
-//# define NV_PFIFO_RAMHT_SIZE 0x00030000
-# define NV_PFIFO_RAMHT_SIZE_MASK 0x00030000
-# define NV_PFIFO_RAMHT_SIZE_SHIFT 16
-# define NV_PFIFO_RAMHT_SIZE_4K 0
-# define NV_PFIFO_RAMHT_SIZE_8K 1
-# define NV_PFIFO_RAMHT_SIZE_16K 2
-# define NV_PFIFO_RAMHT_SIZE_32K 3
-//# define NV_PFIFO_RAMHT_SEARCH 0x03000000
-# define NV_PFIFO_RAMHT_SEARCH_MASK 0x03000000
-# define NV_PFIFO_RAMHT_SEARCH_SHIFT 24
-# define NV_PFIFO_RAMHT_SEARCH_16 0
-# define NV_PFIFO_RAMHT_SEARCH_32 1
-# define NV_PFIFO_RAMHT_SEARCH_64 2
-# define NV_PFIFO_RAMHT_SEARCH_128 3
-#define NV_PFIFO_RAMFC 0x00000214
-//# define NV_PFIFO_RAMFC_BASE_ADDRESS1 0x000001FC
-# define NV_PFIFO_RAMFC_BASE_ADDRESS1_MASK 0x000001FC
-# define NV_PFIFO_RAMFC_BASE_ADDRESS1_SHIFT 2
-# define NV_PFIFO_RAMFC_BASE_ADDRESS1_MOVE 10
-//# define NV_PFIFO_RAMFC_SIZE 0x00010000
-# define NV_PFIFO_RAMFC_SIZE_MASK 0x00010000
-# define NV_PFIFO_RAMFC_SIZE_1K 0x00000000
-# define NV_PFIFO_RAMFC_SIZE_2K 0x00010000
-//# define NV_PFIFO_RAMFC_BASE_ADDRESS2 0x00FE0000
-# define NV_PFIFO_RAMFC_BASE_ADDRESS2_MASK 0x00FE0000
-# define NV_PFIFO_RAMFC_BASE_ADDRESS2_SHIFT 17
-# define NV_PFIFO_RAMFC_BASE_ADDRESS2_MOVE 10
-#define NV_PFIFO_RAMRO 0x00000218
-# define NV_PFIFO_RAMRO_BASE_ADDRESS 0x000001FE
-# define NV_PFIFO_RAMRO_SIZE 0x00010000
-#define NV_PFIFO_RUNOUT_STATUS 0x00000400
-# define NV_PFIFO_RUNOUT_STATUS_RANOUT (1 << 0)
-# define NV_PFIFO_RUNOUT_STATUS_LOW_MARK (1 << 4)
-# define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK (1 << 8)
-#define NV_PFIFO_RUNOUT_PUT_ADDRESS 0x00000410
-#define NV_PFIFO_RUNOUT_GET_ADDRESS 0x00000420
-#define NV_PFIFO_CACHES 0x00000500
-#define NV_PFIFO_MODE 0x00000504
-#define NV_PFIFO_DMA 0x00000508
-#define NV_PFIFO_SIZE 0x0000050C
-#define NV_PFIFO_CACHE0_PUSH0 0x00001000
-#define NV_PFIFO_CACHE0_PULL0 0x00001050
-#define NV_PFIFO_CACHE0_HASH 0x00001058
-#define NV_PFIFO_CACHE1_PUSH0 0x00001200
-# define NV_PFIFO_CACHE1_PUSH0_ACCESS (1 << 0)
-#define NV_PFIFO_CACHE1_PUSH1 0x00001204
-# define NV_PFIFO_CACHE1_PUSH1_CHID 0x0000001F
-# define NV_PFIFO_CACHE1_PUSH1_MODE 0x00000100
-#define NV_PFIFO_CACHE1_PUT 0x00001210
-#define NV_PFIFO_CACHE1_STATUS 0x00001214
-# define NV_PFIFO_CACHE1_STATUS_LOW_MARK (1 << 4)
-# define NV_PFIFO_CACHE1_STATUS_HIGH_MARK (1 << 8)
-#define NV_PFIFO_CACHE1_DMA_PUSH 0x00001220
-# define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS (1 << 0)
-# define NV_PFIFO_CACHE1_DMA_PUSH_STATE (1 << 4)
-# define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER (1 << 8)
-# define NV_PFIFO_CACHE1_DMA_PUSH_STATUS (1 << 12)
-# define NV_PFIFO_CACHE1_DMA_PUSH_ACQUIRE (1 << 16)
-#define NV_PFIFO_CACHE1_DMA_FETCH 0x00001224
-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG 0x000000F8
-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000
-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000
-#define NV_PFIFO_CACHE1_DMA_STATE 0x00001228
-# define NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE (1 << 0)
-# define NV_PFIFO_CACHE1_DMA_STATE_METHOD 0x00001FFC
-# define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 0x0000E000
-# define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 0x1FFC0000
-# define NV_PFIFO_CACHE1_DMA_STATE_ERROR 0xE0000000
-# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0
-# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_CALL 1
-# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 2
-# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RETURN 3
-# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 4
-# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 6
-#define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000122C
-//# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 0x0000FFFF
-# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MASK 0x0000FFFF
-# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_SHIFT 0
-# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MOVE 4
-#define NV_PFIFO_CACHE1_DMA_CTL 0x00001230
-#define NV_PFIFO_CACHE1_DMA_PUT 0x00001240
-#define NV_PFIFO_CACHE1_DMA_GET 0x00001244
-#define NV_PFIFO_CACHE1_REF 0x00001248
-#define NV_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000124C
-# define NV_PFIFO_CACHE1_DMA_SUBROUTINE_RETURN_OFFSET 0x1FFFFFFC
-# define NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE (1 << 0)
-#define NV_PFIFO_CACHE1_PULL0 0x00001250
-# define NV_PFIFO_CACHE1_PULL0_ACCESS (1 << 0)
-#define NV_PFIFO_CACHE1_PULL1 0x00001254
-#define NV_PFIFO_CACHE1_HASH 0x00001258
-#define NV_PFIFO_CACHE1_ACQUIRE_0 0x00001260
-#define NV_PFIFO_CACHE1_ACQUIRE_1 0x00001264
-#define NV_PFIFO_CACHE1_ACQUIRE_2 0x00001268
-#define NV_PFIFO_CACHE1_SEMAPHORE 0x0000126C
-#define NV_PFIFO_CACHE1_GET 0x00001270
-#define NV_PFIFO_CACHE1_ENGINE 0x00001280
-#define NV_PFIFO_CACHE1_DMA_DCOUNT 0x000012A0
-# define NV_PFIFO_CACHE1_DMA_DCOUNT_VALUE 0x00001FFC
-#define NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW 0x000012A4
-# define NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW_OFFSET 0x1FFFFFFC
-#define NV_PFIFO_CACHE1_DMA_RSVD_SHADOW 0x000012A8
-#define NV_PFIFO_CACHE1_DMA_DATA_SHADOW 0x000012AC
+#define ARRAY_SIZE(a) \
+ ((sizeof(a) / sizeof(*(a))) / \
+ static_cast(!(sizeof(a) % sizeof(*(a)))))
+#endif
+#define NV_PMC_SIZE 0x001000
+#define _NV_PFIFO_SIZE 0x002000 // Underscore prefix to prevent clash with NV_PFIFO_SIZE
+#define NV_PVIDEO_SIZE 0x001000
+#define NV_PTIMER_SIZE 0x001000
+#define NV_PFB_SIZE 0x001000
+#define NV_PGRAPH_SIZE 0x002000
+#define NV_PCRTC_SIZE 0x001000
+#define NV_PRAMDAC_SIZE 0x001000
-#define NV_PGRAPH_DEBUG_0 0x00000080
-#define NV_PGRAPH_DEBUG_1 0x00000084
-#define NV_PGRAPH_DEBUG_3 0x0000008C
-#define NV_PGRAPH_DEBUG_4 0x00000090
-#define NV_PGRAPH_DEBUG_5 0x00000094
-#define NV_PGRAPH_DEBUG_8 0x00000098
-#define NV_PGRAPH_DEBUG_9 0x0000009C
-#define NV_PGRAPH_INTR 0x00000100
-# define NV_PGRAPH_INTR_NOTIFY (1 << 0)
-# define NV_PGRAPH_INTR_MISSING_HW (1 << 4)
-# define NV_PGRAPH_INTR_TLB_PRESENT_DMA_R (1 << 6)
-# define NV_PGRAPH_INTR_TLB_PRESENT_DMA_W (1 << 7)
-# define NV_PGRAPH_INTR_TLB_PRESENT_TEX_A (1 << 8)
-# define NV_PGRAPH_INTR_TLB_PRESENT_TEX_B (1 << 9)
-# define NV_PGRAPH_INTR_TLB_PRESENT_VTX (1 << 10)
-# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1 << 12)
-# define NV_PGRAPH_INTR_STATE3D (1 << 13)
-# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1 << 16)
-# define NV_PGRAPH_INTR_ERROR (1 << 20)
-# define NV_PGRAPH_INTR_SINGLE_STEP (1 << 24)
-#define NV_PGRAPH_NSOURCE 0x00000108
-# define NV_PGRAPH_NSOURCE_NOTIFICATION (1 << 0)
-#define NV_PGRAPH_INTR_EN 0x00000140
-# define NV_PGRAPH_INTR_EN_NOTIFY (1 << 0)
-# define NV_PGRAPH_INTR_EN_MISSING_HW (1 << 4)
-# define NV_PGRAPH_INTR_EN_TLB_PRESENT_DMA_R (1 << 6)
-# define NV_PGRAPH_INTR_EN_TLB_PRESENT_DMA_W (1 << 7)
-# define NV_PGRAPH_INTR_EN_TLB_PRESENT_TEX_A (1 << 8)
-# define NV_PGRAPH_INTR_EN_TLB_PRESENT_TEX_B (1 << 9)
-# define NV_PGRAPH_INTR_EN_TLB_PRESENT_VTX (1 << 10)
-# define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH (1 << 12)
-# define NV_PGRAPH_INTR_EN_STATE3D (1 << 13)
-# define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY (1 << 16)
-# define NV_PGRAPH_INTR_EN_ERROR (1 << 20)
-# define NV_PGRAPH_INTR_EN_SINGLE_STEP (1 << 24)
-#define NV_PGRAPH_CTX_CONTROL 0x00000144
-# define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 0x00000003
-# define NV_PGRAPH_CTX_CONTROL_TIME (1 << 8)
-# define NV_PGRAPH_CTX_CONTROL_CHID (1 << 16)
-# define NV_PGRAPH_CTX_CONTROL_CHANGE (1 << 20)
-# define NV_PGRAPH_CTX_CONTROL_SWITCHING (1 << 24)
-# define NV_PGRAPH_CTX_CONTROL_DEVICE (1 << 28)
-#define NV_PGRAPH_CTX_USER 0x00000148
-# define NV_PGRAPH_CTX_USER_CHANNEL_3D (1 << 0)
-# define NV_PGRAPH_CTX_USER_CHANNEL_3D_VALID (1 << 4)
-# define NV_PGRAPH_CTX_USER_SUBCH 0x0000E000
-# define NV_PGRAPH_CTX_USER_CHID 0x1F000000
-# define NV_PGRAPH_CTX_USER_SINGLE_STEP (1 << 31)
-#define NV_PGRAPH_CTX_SWITCH1 0x0000014C
-# define NV_PGRAPH_CTX_SWITCH1_GRCLASS 0x000000FF
-# define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY (1 << 12)
-# define NV_PGRAPH_CTX_SWITCH1_SWIZZLE (1 << 14)
-# define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 0x00038000
-# define NV_PGRAPH_CTX_SWITCH1_SYNCHRONIZE (1 << 18)
-# define NV_PGRAPH_CTX_SWITCH1_ENDIAN_MODE (1 << 19)
-# define NV_PGRAPH_CTX_SWITCH1_CLASS_TYPE (1 << 22)
-# define NV_PGRAPH_CTX_SWITCH1_SINGLE_STEP (1 << 23)
-# define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS (1 << 24)
-# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE0 (1 << 25)
-# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE1 (1 << 26)
-# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_PATTERN (1 << 27)
-# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_ROP (1 << 28)
-# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA1 (1 << 29)
-# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA4 (1 << 30)
-# define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET (1 << 31)
-#define NV_PGRAPH_CTX_SWITCH2 0x00000150
-#define NV_PGRAPH_CTX_SWITCH3 0x00000154
-#define NV_PGRAPH_CTX_SWITCH4 0x00000158
-#define NV_PGRAPH_STATUS 0x00000700
-#define NV_PGRAPH_TRAPPED_ADDR 0x00000704
-# define NV_PGRAPH_TRAPPED_ADDR_MTHD 0x00001FFF
-# define NV_PGRAPH_TRAPPED_ADDR_SUBCH 0x00070000
-# define NV_PGRAPH_TRAPPED_ADDR_CHID 0x01F00000
-# define NV_PGRAPH_TRAPPED_ADDR_DHV 0x10000000
-#define NV_PGRAPH_TRAPPED_DATA_LOW 0x00000708
-#define NV_PGRAPH_SURFACE 0x00000710
-# define NV_PGRAPH_SURFACE_WRITE_3D 0x00700000
-# define NV_PGRAPH_SURFACE_READ_3D 0x07000000
-# define NV_PGRAPH_SURFACE_MODULO_3D 0x70000000
-#define NV_PGRAPH_INCREMENT 0x0000071C
-# define NV_PGRAPH_INCREMENT_READ_BLIT (1 << 0)
-# define NV_PGRAPH_INCREMENT_READ_3D (1 << 1)
-#define NV_PGRAPH_FIFO 0x00000720
-# define NV_PGRAPH_FIFO_ACCESS (1 << 0)
-#define NV_PGRAPH_RDI_INDEX 0x00000750
-#define NV_PGRAPH_RDI_DATA 0x00000754
-#define NV_PGRAPH_FFINTFC_ST2 0x00000764
-#define NV_PGRAPH_CHANNEL_CTX_TABLE 0x00000780
-# define NV_PGRAPH_CHANNEL_CTX_TABLE_INST 0x0000FFFF
-#define NV_PGRAPH_CHANNEL_CTX_POINTER 0x00000784
-# define NV_PGRAPH_CHANNEL_CTX_POINTER_INST 0x0000FFFF
-#define NV_PGRAPH_CHANNEL_CTX_TRIGGER 0x00000788
-# define NV_PGRAPH_CHANNEL_CTX_TRIGGER_READ_IN (1 << 0)
-# define NV_PGRAPH_CHANNEL_CTX_TRIGGER_WRITE_OUT (1 << 1)
-#define NV_PGRAPH_DEBUG_2 0x00000880
-#define NV_PGRAPH_TTILE(i) 0x00000900 + (i * 0x10)
-#define NV_PGRAPH_TLIMIT(i) 0x00000904 + (i * 0x10)
-#define NV_PGRAPH_TSIZE(i) 0x00000908 + (i * 0x10)
-#define NV_PGRAPH_TSTATUS(i) 0x0000090C + (i * 0x10)
-#define NV_PGRAPH_ZCOMP(i) 0x00000980 + (i * 4)
-#define NV_PGRAPH_ZCOMP_OFFSET 0x000009A0
-#define NV_PGRAPH_FBCFG0 0x000009A4
-#define NV_PGRAPH_FBCFG1 0x000009A8
-#define NV_PGRAPH_DEBUG_6 0x00000B80
-#define NV_PGRAPH_DEBUG_7 0x00000B84
-#define NV_PGRAPH_DEBUG_10 0x00000B88
-#define NV_PGRAPH_CSV0_D 0x00000FB4
-# define NV_PGRAPH_CSV0_D_LIGHTS 0x0000FFFF
-# define NV_PGRAPH_CSV0_D_LIGHT0 0x00000003
-# define NV_PGRAPH_CSV0_D_LIGHT0_OFF 0
-# define NV_PGRAPH_CSV0_D_LIGHT0_INFINITE 1
-# define NV_PGRAPH_CSV0_D_LIGHT0_LOCAL 2
-# define NV_PGRAPH_CSV0_D_LIGHT0_SPOT 3
-# define NV_PGRAPH_CSV0_D_RANGE_MODE (1 << 18)
-# define NV_PGRAPH_CSV0_D_FOGENABLE (1 << 19)
-# define NV_PGRAPH_CSV0_D_TEXGEN_REF (1 << 20)
-# define NV_PGRAPH_CSV0_D_TEXGEN_REF_LOCAL_VIEWER 0
-# define NV_PGRAPH_CSV0_D_TEXGEN_REF_INFINITE_VIEWER 1
-# define NV_PGRAPH_CSV0_D_FOG_MODE (1 << 21)
-# define NV_PGRAPH_CSV0_D_FOG_MODE_LINEAR 0
-# define NV_PGRAPH_CSV0_D_FOG_MODE_EXP 1
-# define NV_PGRAPH_CSV0_D_FOGGENMODE 0x01C00000
-# define NV_PGRAPH_CSV0_D_FOGGENMODE_SPEC_ALPHA 0
-# define NV_PGRAPH_CSV0_D_FOGGENMODE_RADIAL 1
-# define NV_PGRAPH_CSV0_D_FOGGENMODE_PLANAR 2
-# define NV_PGRAPH_CSV0_D_FOGGENMODE_ABS_PLANAR 3
-# define NV_PGRAPH_CSV0_D_FOGGENMODE_FOG_X 4
-# define NV_PGRAPH_CSV0_D_MODE 0xC0000000
-# define NV_PGRAPH_CSV0_D_SKIN 0x1C000000
-# define NV_PGRAPH_CSV0_D_SKIN_OFF 0
-# define NV_PGRAPH_CSV0_D_SKIN_2G 1
-# define NV_PGRAPH_CSV0_D_SKIN_2 2
-# define NV_PGRAPH_CSV0_D_SKIN_3G 3
-# define NV_PGRAPH_CSV0_D_SKIN_3 4
-# define NV_PGRAPH_CSV0_D_SKIN_4G 5
-# define NV_PGRAPH_CSV0_D_SKIN_4 6
-#define NV_PGRAPH_CSV0_C 0x00000FB8
-# define NV_PGRAPH_CSV0_C_CHEOPS_PROGRAM_START 0x0000FF00
-# define NV_PGRAPH_CSV0_C_NORMALIZATION_ENABLE (1 << 27)
-# define NV_PGRAPH_CSV0_C_LIGHTING (1 << 31)
-#define NV_PGRAPH_CSV1_B 0x00000FBC
-#define NV_PGRAPH_CSV1_A 0x00000FC0
-# define NV_PGRAPH_CSV1_A_T0_ENABLE (1 << 0)
-# define NV_PGRAPH_CSV1_A_T0_MODE (1 << 1)
-# define NV_PGRAPH_CSV1_A_T0_TEXTURE (1 << 2)
-# define NV_PGRAPH_CSV1_A_T0_TEXTURE_2D 0
-# define NV_PGRAPH_CSV1_A_T0_TEXTURE_3D 1
-# define NV_PGRAPH_CSV1_A_T0_S 0x00000070
-# define NV_PGRAPH_CSV1_A_T0_S_DISABLE 0
-# define NV_PGRAPH_CSV1_A_T0_S_NORMAL_MAP 4
-# define NV_PGRAPH_CSV1_A_T0_S_REFLECTION_MAP 5
-# define NV_PGRAPH_CSV1_A_T0_S_EYE_LINEAR 1
-# define NV_PGRAPH_CSV1_A_T0_S_OBJECT_LINEAR 2
-# define NV_PGRAPH_CSV1_A_T0_S_SPHERE_MAP 3
-# define NV_PGRAPH_CSV1_A_T0_T 0x00000380
-# define NV_PGRAPH_CSV1_A_T0_R 0x00001C00
-# define NV_PGRAPH_CSV1_A_T0_Q 0x0000E000
-# define NV_PGRAPH_CSV1_A_T1_ENABLE (1 << 16)
-# define NV_PGRAPH_CSV1_A_T1_MODE (1 << 17)
-# define NV_PGRAPH_CSV1_A_T1_TEXTURE (1 << 18)
-# define NV_PGRAPH_CSV1_A_T1_S 0x00700000
-# define NV_PGRAPH_CSV1_A_T1_T 0x03800000
-# define NV_PGRAPH_CSV1_A_T1_R 0x1C000000
-# define NV_PGRAPH_CSV1_A_T1_Q 0xE0000000
-#define NV_PGRAPH_CHEOPS_OFFSET 0x00000FC4
-# define NV_PGRAPH_CHEOPS_OFFSET_PROG_LD_PTR 0x000000FF
-# define NV_PGRAPH_CHEOPS_OFFSET_CONST_LD_PTR 0x0000FF00
-#define NV_PGRAPH_BLEND 0x00001804
-# define NV_PGRAPH_BLEND_EQN 0x00000007
-# define NV_PGRAPH_BLEND_EN (1 << 3)
-# define NV_PGRAPH_BLEND_SFACTOR 0x000000F0
-# define NV_PGRAPH_BLEND_SFACTOR_ZERO 0
-# define NV_PGRAPH_BLEND_SFACTOR_ONE 1
-# define NV_PGRAPH_BLEND_SFACTOR_SRC_COLOR 2
-# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_SRC_COLOR 3
-# define NV_PGRAPH_BLEND_SFACTOR_SRC_ALPHA 4
-# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_SRC_ALPHA 5
-# define NV_PGRAPH_BLEND_SFACTOR_DST_ALPHA 6
-# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_DST_ALPHA 7
-# define NV_PGRAPH_BLEND_SFACTOR_DST_COLOR 8
-# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_DST_COLOR 9
-# define NV_PGRAPH_BLEND_SFACTOR_SRC_ALPHA_SATURATE 10
-# define NV_PGRAPH_BLEND_SFACTOR_CONSTANT_COLOR 12
-# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_CONSTANT_COLOR 13
-# define NV_PGRAPH_BLEND_SFACTOR_CONSTANT_ALPHA 14
-# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_CONSTANT_ALPHA 15
-# define NV_PGRAPH_BLEND_DFACTOR 0x00000F00
-# define NV_PGRAPH_BLEND_DFACTOR_ZERO 0
-# define NV_PGRAPH_BLEND_DFACTOR_ONE 1
-# define NV_PGRAPH_BLEND_DFACTOR_SRC_COLOR 2
-# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_SRC_COLOR 3
-# define NV_PGRAPH_BLEND_DFACTOR_SRC_ALPHA 4
-# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_SRC_ALPHA 5
-# define NV_PGRAPH_BLEND_DFACTOR_DST_ALPHA 6
-# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_DST_ALPHA 7
-# define NV_PGRAPH_BLEND_DFACTOR_DST_COLOR 8
-# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_DST_COLOR 9
-# define NV_PGRAPH_BLEND_DFACTOR_SRC_ALPHA_SATURATE 10
-# define NV_PGRAPH_BLEND_DFACTOR_CONSTANT_COLOR 12
-# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_CONSTANT_COLOR 13
-# define NV_PGRAPH_BLEND_DFACTOR_CONSTANT_ALPHA 14
-# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_CONSTANT_ALPHA 15
-# define NV_PGRAPH_BLEND_LOGICOP_ENABLE (1 << 16)
-# define NV_PGRAPH_BLEND_LOGICOP 0x0000F000
-#define NV_PGRAPH_BLENDCOLOR 0x00001808
-#define NV_PGRAPH_BORDERCOLOR0 0x0000180C
-#define NV_PGRAPH_BORDERCOLOR1 0x00001810
-#define NV_PGRAPH_BORDERCOLOR2 0x00001814
-#define NV_PGRAPH_BORDERCOLOR3 0x00001818
-#define NV_PGRAPH_BUMPOFFSET1 0x0000184C
-#define NV_PGRAPH_BUMPSCALE1 0x00001858
-#define NV_PGRAPH_CLEARRECTX 0x00001864
-# define NV_PGRAPH_CLEARRECTX_XMIN 0x00000FFF
-# define NV_PGRAPH_CLEARRECTX_XMAX 0x0FFF0000
-#define NV_PGRAPH_CLEARRECTY 0x00001868
-# define NV_PGRAPH_CLEARRECTY_YMIN 0x00000FFF
-# define NV_PGRAPH_CLEARRECTY_YMAX 0x0FFF0000
-#define NV_PGRAPH_COLORCLEARVALUE 0x0000186C
-#define NV_PGRAPH_COMBINEFACTOR0 0x00001880
-#define NV_PGRAPH_COMBINEFACTOR1 0x000018A0
-#define NV_PGRAPH_COMBINEALPHAI0 0x000018C0
-#define NV_PGRAPH_COMBINEALPHAO0 0x000018E0
-#define NV_PGRAPH_COMBINECOLORI0 0x00001900
-#define NV_PGRAPH_COMBINECOLORO0 0x00001920
-#define NV_PGRAPH_COMBINECTL 0x00001940
-#define NV_PGRAPH_COMBINESPECFOG0 0x00001944
-#define NV_PGRAPH_COMBINESPECFOG1 0x00001948
-#define NV_PGRAPH_CONTROL_0 0x0000194C
-# define NV_PGRAPH_CONTROL_0_ALPHAREF 0x000000FF
-# define NV_PGRAPH_CONTROL_0_ALPHAFUNC 0x00000F00
-# define NV_PGRAPH_CONTROL_0_ALPHATESTENABLE (1 << 12)
-# define NV_PGRAPH_CONTROL_0_ZENABLE (1 << 14)
-# define NV_PGRAPH_CONTROL_0_ZFUNC 0x000F0000
-# define NV_PGRAPH_CONTROL_0_ZFUNC_NEVER 0
-# define NV_PGRAPH_CONTROL_0_ZFUNC_LESS 1
-# define NV_PGRAPH_CONTROL_0_ZFUNC_EQUAL 2
-# define NV_PGRAPH_CONTROL_0_ZFUNC_LEQUAL 3
-# define NV_PGRAPH_CONTROL_0_ZFUNC_GREATER 4
-# define NV_PGRAPH_CONTROL_0_ZFUNC_NOTEQUAL 5
-# define NV_PGRAPH_CONTROL_0_ZFUNC_GEQUAL 6
-# define NV_PGRAPH_CONTROL_0_ZFUNC_ALWAYS 7
-# define NV_PGRAPH_CONTROL_0_DITHERENABLE (1 << 22)
-# define NV_PGRAPH_CONTROL_0_Z_PERSPECTIVE_ENABLE (1 << 23)
-# define NV_PGRAPH_CONTROL_0_ZWRITEENABLE (1 << 24)
-# define NV_PGRAPH_CONTROL_0_STENCIL_WRITE_ENABLE (1 << 25)
-# define NV_PGRAPH_CONTROL_0_ALPHA_WRITE_ENABLE (1 << 26)
-# define NV_PGRAPH_CONTROL_0_RED_WRITE_ENABLE (1 << 27)
-# define NV_PGRAPH_CONTROL_0_GREEN_WRITE_ENABLE (1 << 28)
-# define NV_PGRAPH_CONTROL_0_BLUE_WRITE_ENABLE (1 << 29)
-# define NV_PGRAPH_CONTROL_0_CSCONVERT (3 << 30)
-#define NV_PGRAPH_CONTROL_1 0x00001950
-# define NV_PGRAPH_CONTROL_1_STENCIL_TEST_ENABLE (1 << 0)
-# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC 0x000000F0
-# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_NEVER 0
-# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_LESS 1
-# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_EQUAL 2
-# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_LEQUAL 3
-# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_GREATER 4
-# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_NOTEQUAL 5
-# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_GEQUAL 6
-# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_ALWAYS 7
-# define NV_PGRAPH_CONTROL_1_STENCIL_REF 0x0000FF00
-# define NV_PGRAPH_CONTROL_1_STENCIL_MASK_READ 0x00FF0000
-# define NV_PGRAPH_CONTROL_1_STENCIL_MASK_WRITE 0xFF000000
-#define NV_PGRAPH_CONTROL_2 0x00001954
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL 0x0000000F
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL 0x000000F0
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS 0x00000F00
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_KEEP 1
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_ZERO 2
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_REPLACE 3
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_INCRSAT 4
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_DECRSAT 5
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_INVERT 6
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_INCR 7
-# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_DECR 8
-#define NV_PGRAPH_CONTROL_3 0x00001958
-# define NV_PGRAPH_CONTROL_3_FOGENABLE (1 << 8)
-# define NV_PGRAPH_CONTROL_3_FOG_MODE 0x00070000
-# define NV_PGRAPH_CONTROL_3_FOG_MODE_LINEAR 0
-# define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP 1
-# define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP2 3
-# define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP_ABS 5
-# define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP2_ABS 7
-# define NV_PGRAPH_CONTROL_3_FOG_MODE_LINEAR_ABS 4
-#define NV_PGRAPH_FOGCOLOR 0x00001980
-# define NV_PGRAPH_FOGCOLOR_RED 0x00FF0000
-# define NV_PGRAPH_FOGCOLOR_GREEN 0x0000FF00
-# define NV_PGRAPH_FOGCOLOR_BLUE 0x000000FF
-# define NV_PGRAPH_FOGCOLOR_ALPHA 0xFF000000
-#define NV_PGRAPH_FOGPARAM0 0x00001984
-#define NV_PGRAPH_FOGPARAM1 0x00001988
-#define NV_PGRAPH_SETUPRASTER 0x00001990
-# define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE 0x00000003
-# define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE_FILL 0
-# define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE_POINT 1
-# define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE_LINE 2
-# define NV_PGRAPH_SETUPRASTER_BACKFACEMODE 0x0000000C
-# define NV_PGRAPH_SETUPRASTER_POFFSETPOINTENABLE (1 << 6)
-# define NV_PGRAPH_SETUPRASTER_POFFSETLINEENABLE (1 << 7)
-# define NV_PGRAPH_SETUPRASTER_POFFSETFILLENABLE (1 << 8)
-# define NV_PGRAPH_SETUPRASTER_CULLCTRL 0x00600000
-# define NV_PGRAPH_SETUPRASTER_CULLCTRL_FRONT 1
-# define NV_PGRAPH_SETUPRASTER_CULLCTRL_BACK 2
-# define NV_PGRAPH_SETUPRASTER_CULLCTRL_FRONT_AND_BACK 3
-# define NV_PGRAPH_SETUPRASTER_FRONTFACE (1 << 23)
-# define NV_PGRAPH_SETUPRASTER_CULLENABLE (1 << 28)
-# define NV_PGRAPH_SETUPRASTER_Z_FORMAT (1 << 29)
-#define NV_PGRAPH_SHADERCLIPMODE 0x00001994
-#define NV_PGRAPH_SHADERCTL 0x00001998
-#define NV_PGRAPH_SHADERPROG 0x0000199C
-#define NV_PGRAPH_SHADOWZSLOPETHRESHOLD 0x000019A8
-#define NV_PGRAPH_SPECFOGFACTOR0 0x000019AC
-#define NV_PGRAPH_SPECFOGFACTOR1 0x000019B0
-#define NV_PGRAPH_TEXADDRESS0 0x000019BC
-# define NV_PGRAPH_TEXADDRESS0_ADDRU 0x00000007
-# define NV_PGRAPH_TEXADDRESS0_ADDRU_WRAP 1
-# define NV_PGRAPH_TEXADDRESS0_ADDRU_MIRROR 2
-# define NV_PGRAPH_TEXADDRESS0_ADDRU_CLAMP_TO_EDGE 3
-# define NV_PGRAPH_TEXADDRESS0_ADDRU_BORDER 4
-# define NV_PGRAPH_TEXADDRESS0_ADDRU_CLAMP_OGL 5
-# define NV_PGRAPH_TEXADDRESS0_WRAP_U (1 << 4)
-# define NV_PGRAPH_TEXADDRESS0_ADDRV 0x00000700
-# define NV_PGRAPH_TEXADDRESS0_WRAP_V (1 << 12)
-# define NV_PGRAPH_TEXADDRESS0_ADDRP 0x00070000
-# define NV_PGRAPH_TEXADDRESS0_WRAP_P (1 << 20)
-# define NV_PGRAPH_TEXADDRESS0_WRAP_Q (1 << 24)
-#define NV_PGRAPH_TEXADDRESS1 0x000019C0
-#define NV_PGRAPH_TEXADDRESS2 0x000019C4
-#define NV_PGRAPH_TEXADDRESS3 0x000019C8
-#define NV_PGRAPH_TEXCTL0_0 0x000019CC
-# define NV_PGRAPH_TEXCTL0_0_ALPHAKILLEN (1 << 2)
-# define NV_PGRAPH_TEXCTL0_0_MAX_LOD_CLAMP 0x0003FFC0
-# define NV_PGRAPH_TEXCTL0_0_MIN_LOD_CLAMP 0x3FFC0000
-# define NV_PGRAPH_TEXCTL0_0_ENABLE (1 << 30)
-#define NV_PGRAPH_TEXCTL0_1 0x000019D0
-#define NV_PGRAPH_TEXCTL0_2 0x000019D4
-#define NV_PGRAPH_TEXCTL0_3 0x000019D8
-#define NV_PGRAPH_TEXCTL1_0 0x000019DC
-# define NV_PGRAPH_TEXCTL1_0_IMAGE_PITCH 0xFFFF0000
-#define NV_PGRAPH_TEXCTL1_1 0x000019E0
-#define NV_PGRAPH_TEXCTL1_2 0x000019E4
-#define NV_PGRAPH_TEXCTL1_3 0x000019E8
-#define NV_PGRAPH_TEXCTL2_0 0x000019EC
-#define NV_PGRAPH_TEXCTL2_1 0x000019F0
-#define NV_PGRAPH_TEXFILTER0 0x000019F4
-# define NV_PGRAPH_TEXFILTER0_MIPMAP_LOD_BIAS 0x00001FFF
-# define NV_PGRAPH_TEXFILTER0_MIN 0x003F0000
-# define NV_PGRAPH_TEXFILTER0_MIN_BOX_LOD0 1
-# define NV_PGRAPH_TEXFILTER0_MIN_TENT_LOD0 2
-# define NV_PGRAPH_TEXFILTER0_MIN_BOX_NEARESTLOD 3
-# define NV_PGRAPH_TEXFILTER0_MIN_TENT_NEARESTLOD 4
-# define NV_PGRAPH_TEXFILTER0_MIN_BOX_TENT_LOD 5
-# define NV_PGRAPH_TEXFILTER0_MIN_TENT_TENT_LOD 6
-# define NV_PGRAPH_TEXFILTER0_MIN_CONVOLUTION_2D_LOD0 7
-# define NV_PGRAPH_TEXFILTER0_MAG 0x0F000000
-# define NV_PGRAPH_TEXFILTER0_ASIGNED (1 << 28)
-# define NV_PGRAPH_TEXFILTER0_RSIGNED (1 << 29)
-# define NV_PGRAPH_TEXFILTER0_GSIGNED (1 << 30)
-# define NV_PGRAPH_TEXFILTER0_BSIGNED (1 << 31)
-#define NV_PGRAPH_TEXFILTER1 0x000019F8
-#define NV_PGRAPH_TEXFILTER2 0x000019FC
-#define NV_PGRAPH_TEXFILTER3 0x00001A00
-#define NV_PGRAPH_TEXFMT0 0x00001A04
-# define NV_PGRAPH_TEXFMT0_CONTEXT_DMA (1 << 1)
-# define NV_PGRAPH_TEXFMT0_CUBEMAPENABLE (1 << 2)
-# define NV_PGRAPH_TEXFMT0_BORDER_SOURCE (1 << 3)
-# define NV_PGRAPH_TEXFMT0_BORDER_SOURCE_TEXTURE 0
-# define NV_PGRAPH_TEXFMT0_BORDER_SOURCE_COLOR 1
-# define NV_PGRAPH_TEXFMT0_DIMENSIONALITY 0x000000C0
-# define NV_PGRAPH_TEXFMT0_COLOR 0x00007F00
-# define NV_PGRAPH_TEXFMT0_MIPMAP_LEVELS 0x000F0000
-# define NV_PGRAPH_TEXFMT0_BASE_SIZE_U 0x00F00000
-# define NV_PGRAPH_TEXFMT0_BASE_SIZE_V 0x0F000000
-# define NV_PGRAPH_TEXFMT0_BASE_SIZE_P 0xF0000000
-#define NV_PGRAPH_TEXFMT1 0x00001A08
-#define NV_PGRAPH_TEXFMT2 0x00001A0C
-#define NV_PGRAPH_TEXFMT3 0x00001A10
-#define NV_PGRAPH_TEXIMAGERECT0 0x00001A14
-# define NV_PGRAPH_TEXIMAGERECT0_WIDTH 0x1FFF0000
-# define NV_PGRAPH_TEXIMAGERECT0_HEIGHT 0x00001FFF
-#define NV_PGRAPH_TEXIMAGERECT1 0x00001A18
-#define NV_PGRAPH_TEXIMAGERECT2 0x00001A1C
-#define NV_PGRAPH_TEXIMAGERECT3 0x00001A20
-#define NV_PGRAPH_TEXOFFSET0 0x00001A24
-#define NV_PGRAPH_TEXOFFSET1 0x00001A28
-#define NV_PGRAPH_TEXOFFSET2 0x00001A2C
-#define NV_PGRAPH_TEXOFFSET3 0x00001A30
-#define NV_PGRAPH_TEXPALETTE0 0x00001A34
-# define NV_PGRAPH_TEXPALETTE0_CONTEXT_DMA (1 << 0)
-# define NV_PGRAPH_TEXPALETTE0_LENGTH 0x0000000C
-# define NV_PGRAPH_TEXPALETTE0_LENGTH_256 0
-# define NV_PGRAPH_TEXPALETTE0_LENGTH_128 1
-# define NV_PGRAPH_TEXPALETTE0_LENGTH_64 2
-# define NV_PGRAPH_TEXPALETTE0_LENGTH_32 3
-# define NV_PGRAPH_TEXPALETTE0_OFFSET 0xFFFFFFC0
-#define NV_PGRAPH_TEXPALETTE1 0x00001A38
-#define NV_PGRAPH_TEXPALETTE2 0x00001A3C
-#define NV_PGRAPH_TEXPALETTE3 0x00001A40
-#define NV_PGRAPH_ZSTENCILCLEARVALUE 0x00001A88
-#define NV_PGRAPH_ZCLIPMIN 0x00001A90
-#define NV_PGRAPH_ZOFFSETBIAS 0x00001AA4
-#define NV_PGRAPH_ZOFFSETFACTOR 0x00001AA8
-#define NV_PGRAPH_EYEVEC0 0x00001AAC
-#define NV_PGRAPH_EYEVEC1 0x00001AB0
-#define NV_PGRAPH_EYEVEC2 0x00001AB4
-#define NV_PGRAPH_ZCLIPMAX 0x00001ABC
+#define VSH_TOKEN_SIZE 4 // Compatibility; TODO : Move this to nv2a_vsh.h
+#define MAX(a,b) ((a)>(b) ? (a) : (b)) // Compatibility
+#define MIN(a,b) ((a)<(b) ? (a) : (b)) // Compatibility
+#define g_free(x) free(x) // Compatibility
+#define g_malloc(x) malloc(x) // Compatibility
+#define g_malloc0(x) calloc(1, x) // Compatibility
+#define g_realloc(x, y) realloc(x, y) // Compatibility
-#define NV_PCRTC_INTR_0 0x00000100
-# define NV_PCRTC_INTR_0_VBLANK (1 << 0)
-#define NV_PCRTC_INTR_EN_0 0x00000140
-# define NV_PCRTC_INTR_EN_0_VBLANK (1 << 0)
-#define NV_PCRTC_START 0x00000800
-#define NV_PCRTC_CONFIG 0x00000804
+#undef USE_TEXTURE_CACHE
+#if __cplusplus >= 201402L
+# define NV2A_CONSTEXPR constexpr
+#else
+# define NV2A_CONSTEXPR static
+#endif
-#define NV_PVIDEO_DEBUG_2 0x00000088
-#define NV_PVIDEO_DEBUG_3 0x0000008C
-#define NV_PVIDEO_INTR 0x00000100
-# define NV_PVIDEO_INTR_BUFFER_0 (1 << 0)
-# define NV_PVIDEO_INTR_BUFFER_1 (1 << 4)
-#define NV_PVIDEO_INTR_EN 0x00000140
-# define NV_PVIDEO_INTR_EN_BUFFER_0 (1 << 0)
-# define NV_PVIDEO_INTR_EN_BUFFER_1 (1 << 4)
-#define NV_PVIDEO_BUFFER 0x00000700
-# define NV_PVIDEO_BUFFER_0_USE (1 << 0)
-# define NV_PVIDEO_BUFFER_1_USE (1 << 4)
-#define NV_PVIDEO_STOP 0x00000704
-#define NV_PVIDEO_BASE(i) 0x00000900 + (i * 4)
-#define NV_PVIDEO_LIMIT(i) 0x00000908 + (i * 4)
-#define NV_PVIDEO_LUMINANCE(i) 0x00000910 + (i * 4)
-#define NV_PVIDEO_CHROMINANCE(i) 0x00000918 + (i * 4)
-#define NV_PVIDEO_OFFSET(i) 0x00000920 + (i * 4)
-#define NV_PVIDEO_SIZE_IN(i) 0x00000928 + (i * 4)
-# define NV_PVIDEO_SIZE_IN_WIDTH 0x000007FF
-# define NV_PVIDEO_SIZE_IN_HEIGHT 0x07FF0000
-#define NV_PVIDEO_POINT_IN(i) 0x00000930 + (i * 4)
-# define NV_PVIDEO_POINT_IN_S 0x00007FFF
-# define NV_PVIDEO_POINT_IN_T 0xFFFE0000
-#define NV_PVIDEO_DS_DX(i) 0x00000938 + (i * 4)
-#define NV_PVIDEO_DT_DY(i) 0x00000940 + (i * 4)
-#define NV_PVIDEO_POINT_OUT(i) 0x00000948 + (i * 4)
-# define NV_PVIDEO_POINT_OUT_X 0x00000FFF
-# define NV_PVIDEO_POINT_OUT_Y 0x0FFF0000
-#define NV_PVIDEO_SIZE_OUT(i) 0x00000950 + (i * 4)
-# define NV_PVIDEO_SIZE_OUT_WIDTH 0x00000FFF
-# define NV_PVIDEO_SIZE_OUT_HEIGHT 0x0FFF0000
-#define NV_PVIDEO_FORMAT(i) 0x00000958 + (i * 4)
-# define NV_PVIDEO_FORMAT_PITCH 0x00001FFF
-# define NV_PVIDEO_FORMAT_COLOR 0x00030000
-# define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 1
-# define NV_PVIDEO_FORMAT_DISPLAY (1 << 20)
-#define NV_PVIDEO_COLOR_KEY(i) 0x00000b00 + (i * 4)
+// GCC implementation of FFS
+static int ffs(register int valu)
+{
+ register int bit;
+ if (valu == 0)
+ return 0;
-#define NV_PTIMER_INTR_0 0x00000100
-# define NV_PTIMER_INTR_0_ALARM (1 << 0)
-#define NV_PTIMER_INTR_EN_0 0x00000140
-# define NV_PTIMER_INTR_EN_0_ALARM (1 << 0)
-#define NV_PTIMER_NUMERATOR 0x00000200
-#define NV_PTIMER_DENOMINATOR 0x00000210
-#define NV_PTIMER_TIME_0 0x00000400
-#define NV_PTIMER_TIME_1 0x00000410
-#define NV_PTIMER_ALARM_0 0x00000420
+ for (bit = 1; !(valu & 1); bit++)
+ valu >>= 1;
-#define NV_PRMVIO_MISC__WRITE 0x000c03c2
-#define NV_PRMVIO_SRX 0x000c03c4
-#define NV_PRMVIO_SR 0x000c03c5
-# define NV_VIO_SR_RESET_INDEX 0x00
-# define NV_VIO_SR_CLOCK_INDEX 0x01
-# define NV_VIO_SR_PLANE_MASK_INDEX 0x02
-# define NV_VIO_SR_CHAR_MAP_INDEX 0x03
-# define NV_VIO_SR_MEM_MODE_INDEX 0x04
-#define NV_PRMVIO_MISC__READ 0x000c03cc
-#define NV_PRMVIO_GRX 0x000c03ce
-#define NV_PRMVIO_GX 0x000c03cf
-# define NV_VIO_GX_SR_INDEX 0x00
-# define NV_VIO_GX_SREN_INDEX 0x01
-# define NV_VIO_GX_CCOMP_INDEX 0x02
-# define NV_VIO_GX_ROP_INDEX 0x03
-# define NV_VIO_GX_READ_MAP_INDEX 0x04
-# define NV_VIO_GX_MODE_INDEX 0x05
-# define NV_VIO_GX_MISC_INDEX 0x06
-# define NV_VIO_GX_DONT_CARE_INDEX 0x07
-# define NV_VIO_GX_BIT_MASK_INDEX 0x08
+ return bit;
+}
-#define NV_PFB_DEBUG_0 0x00000080
-#define NV_PFB_CFG0 0x00000200
-# define NV_PFB_CFG0_PART 0x00000003
-#define NV_PFB_CFG1 0x00000204
-#define NV_PFB_CSTATUS 0x0000020C
-#define NV_PFB_REFCTRL 0x00000210
-#define NV_PFB_NVM 0x00000214 // NV_PFB_NVM_MODE_DISABLE
-#define NV_PFB_PIN 0x00000218
-#define NV_PFB_PAD 0x0000021C
-#define NV_PFB_TIMING0 0x00000220
-#define NV_PFB_TIMING1 0x00000224
-#define NV_PFB_TIMING2 0x00000228
-#define NV_PFB_TILE(i) 0x00000240 + (i * 0x10)
-#define NV_PFB_TLIMIT(i) 0x00000244 + (i * 0x10)
-#define NV_PFB_TSIZE(i) 0x00000248 + (i * 0x10)
-#define NV_PFB_TSTATUS(i) 0x0000024C + (i * 0x10)
-#define NV_PFB_MRS 0x000002C0
-#define NV_PFB_EMRS 0x000002C4
-#define NV_PFB_MRS_EXT 0x000002C8
-#define NV_PFB_EMRS_EXT 0x000002CC
-#define NV_PFB_REF 0x000002D0
-#define NV_PFB_PRE 0x000002D4
-#define NV_PFB_ZCOMP(i) 0x00000300 + (i * 4)
-#define NV_PFB_ZCOMP_OFFSET 0x00000324
-#define NV_PFB_ARB_PREDIVIDER 0x00000328
-#define NV_PFB_ARB_TIMEOUT 0x0000032C
-#define NV_PFB_ARB_XFER_REM 0x00000334
-#define NV_PFB_ARB_DIFF_BANK 0x00000338
-#define NV_PFB_CLOSE_PAGE0 0x00000340
-#define NV_PFB_CLOSE_PAGE1 0x00000344
-#define NV_PFB_CLOSE_PAGE2 0x00000348
-#define NV_PFB_BPARB 0x0000034C
-#define NV_PFB_CMDQ0 0x00000350
-#define NV_PFB_CMDQ1 0x00000354
-#define NV_PFB_ILL_INSTR 0x00000360
-#define NV_PFB_RT 0x00000400
-#define NV_PFB_AUTOCLOSE 0x00000404
-#define NV_PFB_WBC 0x00000410
-# define NV_PFB_WBC_FLUSH (1 << 16)
-#define NV_PFB_CMDQ_PRT 0x00000418
-#define NV_PFB_CPU_RRQ 0x00000420
-#define NV_PFB_BYPASS 0x00000424
+#define GET_MASK(v, mask) (((v) & (mask)) >> (ffs(mask)-1))
-#define NV_PRAMIN_DMA_CLASS(i) 0x00000000 + (i * 0x10)
-#define NV_PRAMIN_DMA_LIMIT(i) 0x00000004 + (i * 0x10)
-#define NV_PRAMIN_DMA_START(i) 0x00000008 + (i * 0x10)
-#define NV_PRAMIN_DMA_ADDRESS(i) 0x0000000C + (i * 0x10)
+#define SET_MASK(v, mask, val) \
+ do { \
+ const unsigned int __val = (val); \
+ const unsigned int __mask = (mask); \
+ (v) &= ~(__mask); \
+ (v) |= ((__val) << (ffs(__mask) - 1)) & (__mask); \
+ } while (0)
-#define NV_PRAMDAC_NVPLL_COEFF 0x00000500
-# define NV_PRAMDAC_NVPLL_COEFF_MDIV 0x000000FF
-# define NV_PRAMDAC_NVPLL_COEFF_NDIV 0x0000FF00
-# define NV_PRAMDAC_NVPLL_COEFF_PDIV 0x00070000
-#define NV_PRAMDAC_MPLL_COEFF 0x00000504
-# define NV_PRAMDAC_MPLL_COEFF_MDIV 0x000000FF
-# define NV_PRAMDAC_MPLL_COEFF_NDIV 0x0000FF00
-# define NV_PRAMDAC_MPLL_COEFF_PDIV 0x00070000
-#define NV_PRAMDAC_VPLL_COEFF 0x00000508
-# define NV_PRAMDAC_VPLL_COEFF_MDIV 0x000000FF
-# define NV_PRAMDAC_VPLL_COEFF_NDIV 0x0000FF00
-# define NV_PRAMDAC_VPLL_COEFF_PDIV 0x00070000
-#define NV_PRAMDAC_PLL_TEST_COUNTER 0x00000514
-# define NV_PRAMDAC_PLL_TEST_COUNTER_NOOFIPCLKS 0x000003FF
-# define NV_PRAMDAC_PLL_TEST_COUNTER_VALUE 0x0000FFFF
-# define NV_PRAMDAC_PLL_TEST_COUNTER_ENABLE (1 << 16)
-# define NV_PRAMDAC_PLL_TEST_COUNTER_RESET (1 << 20)
-# define NV_PRAMDAC_PLL_TEST_COUNTER_SOURCE 0x03000000
-# define NV_PRAMDAC_PLL_TEST_COUNTER_VPLL2_LOCK (1 << 27)
-# define NV_PRAMDAC_PLL_TEST_COUNTER_PDIV_RST (1 << 28)
-# define NV_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCK (1 << 29)
-# define NV_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCK (1 << 30)
-# define NV_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCK (1 << 31)
-#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600
-# define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON (3 << 4)
-# define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL (1 << 8)
-# define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL (1 << 12)
-# define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM (2 << 16)
-# define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS (1 << 20)
-# define NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG (2 << 28)
+// Power-of-two CASE statements
+#define CASE_1(v, step) case (v)
+#define CASE_2(v, step) CASE_1(v, step) : CASE_1(v + (step) * 1, step)
+#define CASE_4(v, step) CASE_2(v, step) : CASE_2(v + (step) * 2, step)
+#define CASE_8(v, step) CASE_4(v, step) : CASE_4(v + (step) * 4, step)
+#define CASE_16(v, step) CASE_8(v, step) : CASE_8(v + (step) * 8, step)
+#define CASE_32(v, step) CASE_16(v, step) : CASE_16(v + (step) * 16, step)
+#define CASE_64(v, step) CASE_32(v, step) : CASE_32(v + (step) * 32, step)
+#define CASE_128(v, step) CASE_64(v, step) : CASE_64(v + (step) * 64, step)
+#define CASE_256(v, step) CASE_128(v, step) : CASE_128(v + (step) * 128, step)
-#define NV_PRMCIO_ARX 0x006013c0
-#define NV_PRMCIO_AR__WRITE 0x006013c0
-#define NV_PRMCIO_AR__READ 0x006013c1
-# define NV_CIO_AR_MODE_INDEX 0x10
-# define NV_CIO_AR_OSCAN_INDEX 0x11
-# define NV_CIO_AR_PLANE_INDEX 0x12
-# define NV_CIO_AR_HPP_INDEX 0x13
-# define NV_CIO_AR_CSEL_INDEX 0x14
-#define NV_PRMCIO_INP0 0x006013c2
-#define NV_PRMCIO_CRX__COLOR 0x006013d4
-#define NV_PRMCIO_CR__COLOR 0x006013d5
-/* Standard VGA CRTC registers */
-# define NV_CIO_CR_HDT_INDEX 0x00 /* horizontal display total */
-# define NV_CIO_CR_HDE_INDEX 0x01 /* horizontal display end */
-# define NV_CIO_CR_HBS_INDEX 0x02 /* horizontal blanking start */
-# define NV_CIO_CR_HBE_INDEX 0x03 /* horizontal blanking end */
-# define NV_CIO_CR_HBE_4_0 4:0
-# define NV_CIO_CR_HRS_INDEX 0x04 /* horizontal retrace start */
-# define NV_CIO_CR_HRE_INDEX 0x05 /* horizontal retrace end */
-# define NV_CIO_CR_HRE_4_0 4:0
-# define NV_CIO_CR_HRE_HBE_5 7:7
-# define NV_CIO_CR_VDT_INDEX 0x06 /* vertical display total */
-# define NV_CIO_CR_OVL_INDEX 0x07 /* overflow bits */
-# define NV_CIO_CR_OVL_VDT_8 0:0
-# define NV_CIO_CR_OVL_VDE_8 1:1
-# define NV_CIO_CR_OVL_VRS_8 2:2
-# define NV_CIO_CR_OVL_VBS_8 3:3
-# define NV_CIO_CR_OVL_VDT_9 5:5
-# define NV_CIO_CR_OVL_VDE_9 6:6
-# define NV_CIO_CR_OVL_VRS_9 7:7
-# define NV_CIO_CR_RSAL_INDEX 0x08 /* normally "preset row scan" */
-# define NV_CIO_CR_CELL_HT_INDEX 0x09 /* cell height?! normally "max scan line" */
-# define NV_CIO_CR_CELL_HT_VBS_9 5:5
-# define NV_CIO_CR_CELL_HT_SCANDBL 7:7
-# define NV_CIO_CR_CURS_ST_INDEX 0x0a /* cursor start */
-# define NV_CIO_CR_CURS_END_INDEX 0x0b /* cursor end */
-# define NV_CIO_CR_SA_HI_INDEX 0x0c /* screen start address high */
-# define NV_CIO_CR_SA_LO_INDEX 0x0d /* screen start address low */
-# define NV_CIO_CR_TCOFF_HI_INDEX 0x0e /* cursor offset high */
-# define NV_CIO_CR_TCOFF_LO_INDEX 0x0f /* cursor offset low */
-# define NV_CIO_CR_VRS_INDEX 0x10 /* vertical retrace start */
-# define NV_CIO_CR_VRE_INDEX 0x11 /* vertical retrace end */
-# define NV_CIO_CR_VRE_3_0 3:0
-# define NV_CIO_CR_VDE_INDEX 0x12 /* vertical display end */
-# define NV_CIO_CR_OFFSET_INDEX 0x13 /* sets screen pitch */
-# define NV_CIO_CR_ULINE_INDEX 0x14 /* underline location */
-# define NV_CIO_CR_VBS_INDEX 0x15 /* vertical blank start */
-# define NV_CIO_CR_VBE_INDEX 0x16 /* vertical blank end */
-# define NV_CIO_CR_MODE_INDEX 0x17 /* crtc mode control */
-# define NV_CIO_CR_LCOMP_INDEX 0x18 /* line compare */
-/* Extended VGA CRTC registers */
-# define NV_CIO_CRE_RPC0_INDEX 0x19 /* repaint control 0 */
-# define NV_CIO_CRE_RPC0_OFFSET_10_8 7:5
-# define NV_CIO_CRE_RPC1_INDEX 0x1a /* repaint control 1 */
-# define NV_CIO_CRE_RPC1_LARGE 2:2
-# define NV_CIO_CRE_FF_INDEX 0x1b /* fifo control */
-# define NV_CIO_CRE_ENH_INDEX 0x1c /* enhanced? */
-# define NV_CIO_SR_LOCK_INDEX 0x1f /* crtc lock */
-# define NV_CIO_SR_UNLOCK_RW_VALUE 0x57
-# define NV_CIO_SR_LOCK_VALUE 0x99
-# define NV_CIO_CRE_FFLWM__INDEX 0x20 /* fifo low water mark */
-# define NV_CIO_CRE_21 0x21 /* vga shadow crtc lock */
-# define NV_CIO_CRE_LSR_INDEX 0x25 /* ? */
-# define NV_CIO_CRE_LSR_VDT_10 0:0
-# define NV_CIO_CRE_LSR_VDE_10 1:1
-# define NV_CIO_CRE_LSR_VRS_10 2:2
-# define NV_CIO_CRE_LSR_VBS_10 3:3
-# define NV_CIO_CRE_LSR_HBE_6 4:4
-# define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index -- ro copy of 0x60.3c0 */
-# define NV_CIO_CRE_CHIP_ID_INDEX 0x27 /* chip revision */
-# define NV_CIO_CRE_PIXEL_INDEX 0x28
-# define NV_CIO_CRE_PIXEL_FORMAT 1:0
-# define NV_CIO_CRE_HEB__INDEX 0x2d /* horizontal extra bits? */
-# define NV_CIO_CRE_HEB_HDT_8 0:0
-# define NV_CIO_CRE_HEB_HDE_8 1:1
-# define NV_CIO_CRE_HEB_HBS_8 2:2
-# define NV_CIO_CRE_HEB_HRS_8 3:3
-# define NV_CIO_CRE_HEB_ILC_8 4:4
-# define NV_CIO_CRE_2E 0x2e /* some scratch or dummy reg to force writes to sink in */
-# define NV_CIO_CRE_HCUR_ADDR2_INDEX 0x2f /* cursor */
-# define NV_CIO_CRE_HCUR_ADDR0_INDEX 0x30 /* pixmap */
-# define NV_CIO_CRE_HCUR_ADDR0_ADR 6:0
-# define NV_CIO_CRE_HCUR_ASI 7:7
-# define NV_CIO_CRE_HCUR_ADDR1_INDEX 0x31 /* address */
-# define NV_CIO_CRE_HCUR_ADDR1_ENABLE 0:0
-# define NV_CIO_CRE_HCUR_ADDR1_CUR_DBL 1:1
-# define NV_CIO_CRE_HCUR_ADDR1_ADR 7:2
-# define NV_CIO_CRE_LCD__INDEX 0x33
-# define NV_CIO_CRE_LCD_LCD_SELECT 0:0
-# define NV_CIO_CRE_DDC0_STATUS__INDEX 0x36
-# define NV_CIO_CRE_DDC0_WR__INDEX 0x37
-# define NV_CIO_CRE_ILACE__INDEX 0x39 /* interlace */
-# define NV_CIO_CRE_SCRATCH3__INDEX 0x3b
-# define NV_CIO_CRE_SCRATCH4__INDEX 0x3c
-# define NV_CIO_CRE_DDC_STATUS__INDEX 0x3e
-# define NV_CIO_CRE_DDC_WR__INDEX 0x3f
-# define NV_CIO_CRE_EBR_INDEX 0x41 /* extra bits ? (vertical) */
-# define NV_CIO_CRE_EBR_VDT_11 0:0
-# define NV_CIO_CRE_EBR_VDE_11 2:2
-# define NV_CIO_CRE_EBR_VRS_11 4:4
-# define NV_CIO_CRE_EBR_VBS_11 6:6
-# define NV_CIO_CRE_43 0x43
-# define NV_CIO_CRE_44 0x44 /* head control */
-# define NV_CIO_CRE_CSB 0x45 /* colour saturation boost */
-# define NV_CIO_CRE_RCR 0x46
-# define NV_CIO_CRE_RCR_ENDIAN_BIG 7:7
-# define NV_CIO_CRE_47 0x47 /* extended fifo lwm, used on nv30+ */
-# define NV_CIO_CRE_49 0x49
-# define NV_CIO_CRE_4B 0x4b /* given patterns in 0x[2-3][a-c] regs, probably scratch 6 */
-# define NV_CIO_CRE_TVOUT_LATENCY 0x52
-# define NV_CIO_CRE_53 0x53 /* `fp_htiming' according to Haiku */
-# define NV_CIO_CRE_54 0x54 /* `fp_vtiming' according to Haiku */
-# define NV_CIO_CRE_57 0x57 /* index reg for cr58 */
-# define NV_CIO_CRE_58 0x58 /* data reg for cr57 */
-# define NV_CIO_CRE_59 0x59 /* related to on/off-chip-ness of digital outputs */
-# define NV_CIO_CRE_5B 0x5B /* newer colour saturation reg */
-# define NV_CIO_CRE_85 0x85
-# define NV_CIO_CRE_86 0x86
-#define NV_PRMCIO_INP0__COLOR 0x006013da
+// Non-power-of-two CASE statements
+#define CASE_3(v, step) CASE_2(v, step) : CASE_1(v + (step) * 2, step)
-#define NV_USER_DMA_PUT 0x40
-#define NV_USER_DMA_GET 0x44
-#define NV_USER_REF 0x48
+#define NV2A_DEVICE(obj) \
+ OBJECT_CHECK(NV2AState, (obj), "nv2a")
+//void reg_log_read(int block, hwaddr addr, uint64_t val);
+//void reg_log_write(int block, hwaddr addr, uint64_t val);
+enum FIFOEngine {
+ ENGINE_SOFTWARE = 0,
+ ENGINE_GRAPHICS = 1,
+ ENGINE_DVD = 2,
+};
-/* DMA objects */
-#define NV_DMA_FROM_MEMORY_CLASS 0x02
-#define NV_DMA_TO_MEMORY_CLASS 0x03
-#define NV_DMA_IN_MEMORY_CLASS 0x3d
+typedef struct DMAObject {
+ unsigned int dma_class;
+ unsigned int dma_target;
+ xbaddr address;
+ xbaddr limit;
+} DMAObject;
-#define NV_DMA_CLASS 0x00000FFF
-#define NV_DMA_PAGE_TABLE (1 << 12)
-#define NV_DMA_PAGE_ENTRY (1 << 13)
-#define NV_DMA_FLAGS_ACCESS (1 << 14)
-#define NV_DMA_FLAGS_MAPPING_COHERENCY (1 << 15)
-#define NV_DMA_TARGET 0x00030000
-# define NV_DMA_TARGET_NVM 0x00000000
-# define NV_DMA_TARGET_NVM_TILED 0x00010000
-# define NV_DMA_TARGET_PCI 0x00020000
-# define NV_DMA_TARGET_AGP 0x00030000
-#define NV_DMA_ADJUST 0xFFF00000
+typedef struct VertexAttribute {
+ bool dma_select;
+ xbaddr offset;
-#define NV_DMA_ADDRESS 0xFFFFF000
+ /* inline arrays are packed in order?
+ * Need to pass the offset to converted attributes */
+ unsigned int inline_array_offset;
+ float inline_value[4];
-#define NV_RAMHT_HANDLE 0xFFFFFFFF
-#define NV_RAMHT_INSTANCE 0x0000FFFF
-#define NV_RAMHT_ENGINE 0x00030000
-# define NV_RAMHT_ENGINE_SW 0x00000000
-# define NV_RAMHT_ENGINE_GRAPHICS 0x00010000
-# define NV_RAMHT_ENGINE_DVD 0x00020000
-#define NV_RAMHT_CHID 0x1F000000
-#define NV_RAMHT_STATUS 0x80000000
+ unsigned int format;
+ unsigned int size; /* size of the data type */
+ unsigned int count; /* number of components */
+ uint32_t stride;
+ bool needs_conversion;
+ uint8_t *converted_buffer;
+ unsigned int converted_elements;
+ unsigned int converted_size;
+ unsigned int converted_count;
+ float *inline_buffer;
-/* graphic classes and methods */
-#define NV_SET_OBJECT 0x00000000
+ GLint gl_count;
+ GLenum gl_type;
+ GLboolean gl_normalize;
+ GLuint gl_converted_buffer;
+ GLuint gl_inline_buffer;
+} VertexAttribute;
-#define NV_CONTEXT_SURFACES_2D 0x0062
-# define NV062_SET_CONTEXT_DMA_IMAGE_SOURCE 0x00000184
-# define NV062_SET_CONTEXT_DMA_IMAGE_DESTIN 0x00000188
-# define NV062_SET_COLOR_FORMAT 0x00000300
-# define NV062_SET_COLOR_FORMAT_LE_Y8 0x01
-# define NV062_SET_COLOR_FORMAT_LE_R5G6B5 0x04
-# define NV062_SET_COLOR_FORMAT_LE_A8R8G8B8 0x0A
-# define NV062_SET_PITCH 0x00000304
-# define NV062_SET_OFFSET_SOURCE 0x00000308
-# define NV062_SET_OFFSET_DESTIN 0x0000030C
+typedef struct Surface {
+ bool draw_dirty;
+ bool buffer_dirty;
+ bool write_enabled_cache;
+ unsigned int pitch;
-#define NV_IMAGE_BLIT 0x009F
-# define NV09F_SET_CONTEXT_SURFACES 0x0000019C
-# define NV09F_SET_OPERATION 0x000002FC
-# define NV09F_SET_OPERATION_SRCCOPY 3
-# define NV09F_CONTROL_POINT_IN 0x00000300
-# define NV09F_CONTROL_POINT_OUT 0x00000304
-# define NV09F_SIZE 0x00000308
+ xbaddr offset;
+} Surface;
+typedef struct SurfaceShape {
+ unsigned int z_format;
+ unsigned int color_format;
+ unsigned int zeta_format;
+ unsigned int log_width, log_height;
+ unsigned int clip_x, clip_y;
+ unsigned int clip_width, clip_height;
+ unsigned int anti_aliasing;
+} SurfaceShape;
-#define NV_KELVIN_PRIMITIVE 0x0097
-# define NV097_NO_OPERATION 0x00000100
-# define NV097_WAIT_FOR_IDLE 0x00000110
-# define NV097_SET_FLIP_READ 0x00000120
-# define NV097_SET_FLIP_WRITE 0x00000124
-# define NV097_SET_FLIP_MODULO 0x00000128
-# define NV097_FLIP_INCREMENT_WRITE 0x0000012C
-# define NV097_FLIP_STALL 0x00000130
-# define NV097_SET_CONTEXT_DMA_NOTIFIES 0x00000180
-# define NV097_SET_CONTEXT_DMA_A 0x00000184
-# define NV097_SET_CONTEXT_DMA_B 0x00000188
-# define NV097_SET_CONTEXT_DMA_STATE 0x00000190
-# define NV097_SET_CONTEXT_DMA_COLOR 0x00000194
-# define NV097_SET_CONTEXT_DMA_ZETA 0x00000198
-# define NV097_SET_CONTEXT_DMA_VERTEX_A 0x0000019C
-# define NV097_SET_CONTEXT_DMA_VERTEX_B 0x000001A0
-# define NV097_SET_CONTEXT_DMA_SEMAPHORE 0x000001A4
-# define NV097_SET_CONTEXT_DMA_REPORT 0x000001A8
-# define NV097_SET_SURFACE_CLIP_HORIZONTAL 0x00000200
-# define NV097_SET_SURFACE_CLIP_HORIZONTAL_X 0x0000FFFF
-# define NV097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 0xFFFF0000
-# define NV097_SET_SURFACE_CLIP_VERTICAL 0x00000204
-# define NV097_SET_SURFACE_CLIP_VERTICAL_Y 0x0000FFFF
-# define NV097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 0xFFFF0000
-# define NV097_SET_SURFACE_FORMAT 0x00000208
-# define NV097_SET_SURFACE_FORMAT_COLOR 0x0000000F
-# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X1R5G5B5_Z1R5G5B5 0x01
-# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X1R5G5B5_O1R5G5B5 0x02
-# define NV097_SET_SURFACE_FORMAT_COLOR_LE_R5G6B5 0x03
-# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X8R8G8B8_Z8R8G8B8 0x04
-# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X8R8G8B8_O8R8G8B8 0x05
-# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X1A7R8G8B8_Z1A7R8G8B8 0x06
-# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X1A7R8G8B8_O1A7R8G8B8 0x07
-# define NV097_SET_SURFACE_FORMAT_COLOR_LE_A8R8G8B8 0x08
-# define NV097_SET_SURFACE_FORMAT_COLOR_LE_B8 0x09
-# define NV097_SET_SURFACE_FORMAT_COLOR_LE_G8B8 0x0A
-# define NV097_SET_SURFACE_FORMAT_ZETA 0x000000F0
-# define NV097_SET_SURFACE_FORMAT_ZETA_Z16 1
-# define NV097_SET_SURFACE_FORMAT_ZETA_Z24S8 2
-# define NV097_SET_SURFACE_FORMAT_TYPE 0x00000F00
-# define NV097_SET_SURFACE_FORMAT_TYPE_PITCH 0x1
-# define NV097_SET_SURFACE_FORMAT_TYPE_SWIZZLE 0x2
-# define NV097_SET_SURFACE_FORMAT_ANTI_ALIASING 0x0000F000
-# define NV097_SET_SURFACE_FORMAT_ANTI_ALIASING_CENTER_1 0
-# define NV097_SET_SURFACE_FORMAT_ANTI_ALIASING_CENTER_CORNER_2 1
-# define NV097_SET_SURFACE_FORMAT_ANTI_ALIASING_SQUARE_OFFSET_4 2
-# define NV097_SET_SURFACE_FORMAT_WIDTH 0x00FF0000
-# define NV097_SET_SURFACE_FORMAT_HEIGHT 0xFF000000
-# define NV097_SET_SURFACE_PITCH 0x0000020C
-# define NV097_SET_SURFACE_PITCH_COLOR 0x0000FFFF
-# define NV097_SET_SURFACE_PITCH_ZETA 0xFFFF0000
-# define NV097_SET_SURFACE_COLOR_OFFSET 0x00000210
-# define NV097_SET_SURFACE_ZETA_OFFSET 0x00000214
-# define NV097_SET_COMBINER_ALPHA_ICW 0x00000260
-# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP 0xE0000000
-# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_UNSIGNED_IDENTITY 0
-# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_UNSIGNED_INVERT 1
-# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_EXPAND_NORMAL 2
-# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_EXPAND_NEGATE 3
-# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_HALFBIAS_NORMAL 4
-# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_HALFBIAS_NEGATE 5
-# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_SIGNED_IDENTITY 6
-# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_SIGNED_NEGATE 7
-# define NV097_SET_COMBINER_ALPHA_ICW_A_ALPHA (1<<28)
-# define NV097_SET_COMBINER_ALPHA_ICW_A_SOURCE 0x0F000000
-# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP 0x00E00000
-# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_UNSIGNED_IDENTITY 0
-# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_UNSIGNED_INVERT 1
-# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_EXPAND_NORMAL 2
-# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_EXPAND_NEGATE 3
-# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_HALFBIAS_NORMAL 4
-# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_HALFBIAS_NEGATE 5
-# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_SIGNED_IDENTITY 6
-# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_SIGNED_NEGATE 7
-# define NV097_SET_COMBINER_ALPHA_ICW_B_ALPHA (1<<20)
-# define NV097_SET_COMBINER_ALPHA_ICW_B_SOURCE 0x000F0000
-# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP 0x0000E000
-# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_UNSIGNED_IDENTITY 0
-# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_UNSIGNED_INVERT 1
-# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_EXPAND_NORMAL 2
-# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_EXPAND_NEGATE 3
-# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_HALFBIAS_NORMAL 4
-# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_HALFBIAS_NEGATE 5
-# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_SIGNED_IDENTITY 6
-# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_SIGNED_NEGATE 7
-# define NV097_SET_COMBINER_ALPHA_ICW_C_ALPHA (1<<12)
-# define NV097_SET_COMBINER_ALPHA_ICW_C_SOURCE 0x00000F00
-# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP 0x000000E0
-# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_UNSIGNED_IDENTITY 0
-# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_UNSIGNED_INVERT 1
-# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_EXPAND_NORMAL 2
-# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_EXPAND_NEGATE 3
-# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_HALFBIAS_NORMAL 4
-# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_HALFBIAS_NEGATE 5
-# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_SIGNED_IDENTITY 6
-# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_SIGNED_NEGATE 7
-# define NV097_SET_COMBINER_ALPHA_ICW_D_ALPHA (1<<4)
-# define NV097_SET_COMBINER_ALPHA_ICW_D_SOURCE 0x0000000F
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0 0x00000288
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_INVERSE 0xE0000000
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_ALPHA (1<<28)
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE 0x0F000000
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_SPECLIT 0xE
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_EF_PROD 0xF
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_INVERSE 0x00E00000
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_ALPHA (1<<20)
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE 0x000F0000
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_SPECLIT 0xE
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_EF_PROD 0xF
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_INVERSE 0x0000E000
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_ALPHA (1<<12)
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE 0x00000F00
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_SPECLIT 0xE
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_EF_PROD 0xF
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_INVERSE 0x000000E0
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_ALPHA (1<<4)
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE 0x0000000F
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_SPECLIT 0xE
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_EF_PROD 0xF
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1 0x0000028C
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_E_INVERSE 0xE0000000
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_E_ALPHA (1<<28)
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE 0x0F000000
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_F_INVERSE 0x00E00000
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_F_ALPHA (1<<20)
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE 0x000F0000
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_G_INVERSE 0x0000E000
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_G_ALPHA (1<<12)
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE 0x00000F00
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_CLAMP (1<<7)
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R5 (1<<6)
-# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R12 0x0000003F
-# define NV097_SET_CONTROL0 0x00000290
-# define NV097_SET_CONTROL0_STENCIL_WRITE_ENABLE (1 << 0)
-# define NV097_SET_CONTROL0_Z_FORMAT (1 << 12)
-# define NV097_SET_CONTROL0_Z_PERSPECTIVE_ENABLE (1 << 16)
-# define NV097_SET_CONTROL0_COLOR_SPACE_CONVERT (0xF << 28)
-# define NV097_SET_FOG_MODE 0x0000029C
-# define NV097_SET_FOG_MODE_V_LINEAR 0x2601
-# define NV097_SET_FOG_MODE_V_EXP 0x800
-# define NV097_SET_FOG_MODE_V_EXP2 0x801
-# define NV097_SET_FOG_MODE_V_EXP_ABS 0x802
-# define NV097_SET_FOG_MODE_V_EXP2_ABS 0x803
-# define NV097_SET_FOG_MODE_V_LINEAR_ABS 0x804
-# define NV097_SET_FOG_GEN_MODE 0x000002A0
-# define NV097_SET_FOG_GEN_MODE_V_SPEC_ALPHA 0
-# define NV097_SET_FOG_GEN_MODE_V_RADIAL 1
-# define NV097_SET_FOG_GEN_MODE_V_PLANAR 2
-# define NV097_SET_FOG_GEN_MODE_V_ABS_PLANAR 3
-# define NV097_SET_FOG_GEN_MODE_V_FOG_X 6
-# define NV097_SET_FOG_ENABLE 0x000002A4
-# define NV097_SET_FOG_COLOR 0x000002A8
-# define NV097_SET_FOG_COLOR_RED 0x000000FF
-# define NV097_SET_FOG_COLOR_GREEN 0x0000FF00
-# define NV097_SET_FOG_COLOR_BLUE 0x00FF0000
-# define NV097_SET_FOG_COLOR_ALPHA 0xFF000000
-# define NV097_SET_ALPHA_TEST_ENABLE 0x00000300
-# define NV097_SET_BLEND_ENABLE 0x00000304
-# define NV097_SET_CULL_FACE_ENABLE 0x00000308
-# define NV097_SET_DEPTH_TEST_ENABLE 0x0000030C
-# define NV097_SET_DITHER_ENABLE 0x00000310
-# define NV097_SET_LIGHTING_ENABLE 0x00000314
-# define NV097_SET_SKIN_MODE 0x00000328
-# define NV097_SET_SKIN_MODE_OFF 0
-# define NV097_SET_SKIN_MODE_2G 1
-# define NV097_SET_SKIN_MODE_2 2
-# define NV097_SET_SKIN_MODE_3G 3
-# define NV097_SET_SKIN_MODE_3 4
-# define NV097_SET_SKIN_MODE_4G 5
-# define NV097_SET_SKIN_MODE_4 6
-# define NV097_SET_STENCIL_TEST_ENABLE 0x0000032C
-# define NV097_SET_POLY_OFFSET_POINT_ENABLE 0x00000330
-# define NV097_SET_POLY_OFFSET_LINE_ENABLE 0x00000334
-# define NV097_SET_POLY_OFFSET_FILL_ENABLE 0x00000338
-# define NV097_SET_ALPHA_FUNC 0x0000033C
-# define NV097_SET_ALPHA_REF 0x00000340
-# define NV097_SET_BLEND_FUNC_SFACTOR 0x00000344
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_ZERO 0x0000
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE 0x0001
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_SRC_COLOR 0x0300
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_SRC_COLOR 0x0301
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_SRC_ALPHA 0x0302
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_SRC_ALPHA 0x0303
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_DST_ALPHA 0x0304
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_DST_ALPHA 0x0305
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_DST_COLOR 0x0306
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_DST_COLOR 0x0307
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_SRC_ALPHA_SATURATE 0x0308
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_CONSTANT_COLOR 0x8001
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_CONSTANT_COLOR 0x8002
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_CONSTANT_ALPHA 0x8003
-# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_CONSTANT_ALPHA 0x8004
-# define NV097_SET_BLEND_FUNC_DFACTOR 0x00000348
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_ZERO 0x0000
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE 0x0001
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_SRC_COLOR 0x0300
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_SRC_COLOR 0x0301
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_SRC_ALPHA 0x0302
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_SRC_ALPHA 0x0303
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_DST_ALPHA 0x0304
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_DST_ALPHA 0x0305
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_DST_COLOR 0x0306
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_DST_COLOR 0x0307
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_SRC_ALPHA_SATURATE 0x0308
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_CONSTANT_COLOR 0x8001
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_CONSTANT_COLOR 0x8002
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_CONSTANT_ALPHA 0x8003
-# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_CONSTANT_ALPHA 0x8004
-# define NV097_SET_BLEND_COLOR 0x0000034C
-# define NV097_SET_BLEND_EQUATION 0x00000350
-# define NV097_SET_BLEND_EQUATION_V_FUNC_SUBTRACT 0x800A
-# define NV097_SET_BLEND_EQUATION_V_FUNC_REVERSE_SUBTRACT 0x800B
-# define NV097_SET_BLEND_EQUATION_V_FUNC_ADD 0x8006
-# define NV097_SET_BLEND_EQUATION_V_MIN 0x8007
-# define NV097_SET_BLEND_EQUATION_V_MAX 0x8008
-# define NV097_SET_BLEND_EQUATION_V_FUNC_REVERSE_SUBTRACT_SIGNED 0xF005
-# define NV097_SET_BLEND_EQUATION_V_FUNC_ADD_SIGNED 0xF006
-# define NV097_SET_DEPTH_FUNC 0x00000354
-# define NV097_SET_COLOR_MASK 0x00000358
-# define NV097_SET_COLOR_MASK_BLUE_WRITE_ENABLE (1 << 0)
-# define NV097_SET_COLOR_MASK_GREEN_WRITE_ENABLE (1 << 8)
-# define NV097_SET_COLOR_MASK_RED_WRITE_ENABLE (1 << 16)
-# define NV097_SET_COLOR_MASK_ALPHA_WRITE_ENABLE (1 << 24)
-# define NV097_SET_DEPTH_MASK 0x0000035C
-# define NV097_SET_STENCIL_MASK 0x00000360
-# define NV097_SET_STENCIL_FUNC 0x00000364
-# define NV097_SET_STENCIL_FUNC_REF 0x00000368
-# define NV097_SET_STENCIL_FUNC_MASK 0x0000036C
-# define NV097_SET_STENCIL_OP_FAIL 0x00000370
-# define NV097_SET_STENCIL_OP_ZFAIL 0x00000374
-# define NV097_SET_STENCIL_OP_ZPASS 0x00000378
-# define NV097_SET_STENCIL_OP_V_KEEP 0x1E00
-# define NV097_SET_STENCIL_OP_V_ZERO 0x0000
-# define NV097_SET_STENCIL_OP_V_REPLACE 0x1E01
-# define NV097_SET_STENCIL_OP_V_INCRSAT 0x1E02
-# define NV097_SET_STENCIL_OP_V_DECRSAT 0x1E03
-# define NV097_SET_STENCIL_OP_V_INVERT 0x150A
-# define NV097_SET_STENCIL_OP_V_INCR 0x8507
-# define NV097_SET_STENCIL_OP_V_DECR 0x8508
-# define NV097_SET_POLYGON_OFFSET_SCALE_FACTOR 0x00000384
-# define NV097_SET_POLYGON_OFFSET_BIAS 0x00000388
-# define NV097_SET_FRONT_POLYGON_MODE 0x0000038C
-# define NV097_SET_FRONT_POLYGON_MODE_V_POINT 0x1B00
-# define NV097_SET_FRONT_POLYGON_MODE_V_LINE 0x1B01
-# define NV097_SET_FRONT_POLYGON_MODE_V_FILL 0x1B02
-# define NV097_SET_BACK_POLYGON_MODE 0x00000390
-# define NV097_SET_CLIP_MIN 0x00000394
-# define NV097_SET_CLIP_MAX 0x00000398
-# define NV097_SET_CULL_FACE 0x0000039C
-# define NV097_SET_CULL_FACE_V_FRONT 0x404
-# define NV097_SET_CULL_FACE_V_BACK 0x405
-# define NV097_SET_CULL_FACE_V_FRONT_AND_BACK 0x408
-# define NV097_SET_FRONT_FACE 0x000003A0
-# define NV097_SET_FRONT_FACE_V_CW 0x900
-# define NV097_SET_FRONT_FACE_V_CCW 0x901
-# define NV097_SET_NORMALIZATION_ENABLE 0x000003A4
-# define NV097_SET_LIGHT_ENABLE_MASK 0x000003BC
-# define NV097_SET_LIGHT_ENABLE_MASK_LIGHT0_OFF 0
-# define NV097_SET_LIGHT_ENABLE_MASK_LIGHT0_INFINITE 1
-# define NV097_SET_LIGHT_ENABLE_MASK_LIGHT0_LOCAL 2
-# define NV097_SET_LIGHT_ENABLE_MASK_LIGHT0_SPOT 3
-# define NV097_SET_TEXGEN_S 0x000003C0
-# define NV097_SET_TEXGEN_S_DISABLE 0x0000
-# define NV097_SET_TEXGEN_S_EYE_LINEAR 0x2400
-# define NV097_SET_TEXGEN_S_OBJECT_LINEAR 0x2401
-# define NV097_SET_TEXGEN_S_SPHERE_MAP 0x2402
-# define NV097_SET_TEXGEN_S_REFLECTION_MAP 0x8512
-# define NV097_SET_TEXGEN_S_NORMAL_MAP 0x8511
-# define NV097_SET_TEXGEN_T 0x000003C4
-# define NV097_SET_TEXGEN_R 0x000003C8
-# define NV097_SET_TEXGEN_Q 0x000003CC
-# define NV097_SET_TEXTURE_MATRIX_ENABLE 0x00000420
-# define NV097_SET_PROJECTION_MATRIX 0x00000440
-# define NV097_SET_MODEL_VIEW_MATRIX 0x00000480
-# define NV097_SET_INVERSE_MODEL_VIEW_MATRIX 0x00000580
-# define NV097_SET_COMPOSITE_MATRIX 0x00000680
-# define NV097_SET_TEXTURE_MATRIX 0x000006C0
-# define NV097_SET_TEXGEN_PLANE_S 0x00000840
-# define NV097_SET_TEXGEN_PLANE_T 0x00000850
-# define NV097_SET_TEXGEN_PLANE_R 0x00000860
-# define NV097_SET_TEXGEN_PLANE_Q 0x00000870
-# define NV097_SET_FOG_PARAMS 0x000009C0
-# define NV097_SET_TEXGEN_VIEW_MODEL 0x000009CC
-# define NV097_SET_TEXGEN_VIEW_MODEL_LOCAL_VIEWER 0
-# define NV097_SET_TEXGEN_VIEW_MODEL_INFINITE_VIEWER 1
-# define NV097_SET_FOG_PLANE 0x000009D0
-# define NV097_SET_FLAT_SHADE_OP 0x000009FC
-# define NV097_SET_SCENE_AMBIENT_COLOR 0x00000A10
-# define NV097_SET_VIEWPORT_OFFSET 0x00000A20
-# define NV097_SET_EYE_POSITION 0x00000A50
-# define NV097_SET_COMBINER_FACTOR0 0x00000A60
-# define NV097_SET_COMBINER_FACTOR1 0x00000A80
-# define NV097_SET_COMBINER_ALPHA_OCW 0x00000AA0
-# define NV097_SET_COMBINER_ALPHA_OCW_OP 0xFFFF8000
-# define NV097_SET_COMBINER_ALPHA_OCW_OP_NOSHIFT 0
-# define NV097_SET_COMBINER_ALPHA_OCW_OP_NOSHIFT_BIAS 1
-# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTLEFTBY1 2
-# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTLEFTBY1_BIAS 3
-# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTLEFTBY2 4
-# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTRIGHTBY1 6
-# define NV097_SET_COMBINER_ALPHA_OCW_MUX_ENABLE (1<<14)
-# define NV097_SET_COMBINER_ALPHA_OCW_SUM_DST 0x00000F00
-# define NV097_SET_COMBINER_ALPHA_OCW_AB_DST 0x000000F0
-# define NV097_SET_COMBINER_ALPHA_OCW_CD_DST 0x0000000F
-# define NV097_SET_COMBINER_COLOR_ICW 0x00000AC0
-# define NV097_SET_COMBINER_COLOR_ICW_A_MAP 0xE0000000
-# define NV097_SET_COMBINER_COLOR_ICW_A_ALPHA (1<<28)
-# define NV097_SET_COMBINER_COLOR_ICW_A_SOURCE 0x0F000000
-# define NV097_SET_COMBINER_COLOR_ICW_B_MAP 0x00E00000
-# define NV097_SET_COMBINER_COLOR_ICW_B_ALPHA (1<<20)
-# define NV097_SET_COMBINER_COLOR_ICW_B_SOURCE 0x000F0000
-# define NV097_SET_COMBINER_COLOR_ICW_C_MAP 0x0000E000
-# define NV097_SET_COMBINER_COLOR_ICW_C_ALPHA (1<<12)
-# define NV097_SET_COMBINER_COLOR_ICW_C_SOURCE 0x00000F00
-# define NV097_SET_COMBINER_COLOR_ICW_D_MAP 0x000000E0
-# define NV097_SET_COMBINER_COLOR_ICW_D_ALPHA (1<<4)
-# define NV097_SET_COMBINER_COLOR_ICW_D_SOURCE 0x0000000F
-# define NV097_SET_VIEWPORT_SCALE 0x00000AF0
-# define NV097_SET_TRANSFORM_PROGRAM 0x00000B00
-# define NV097_SET_TRANSFORM_CONSTANT 0x00000B80
-# define NV097_SET_BACK_LIGHT_AMBIENT_COLOR 0x00000C00
-# define NV097_SET_BACK_LIGHT_DIFFUSE_COLOR 0x00000C0C
-# define NV097_SET_BACK_LIGHT_SPECULAR_COLOR 0x00000C18
-# define NV097_SET_LIGHT_AMBIENT_COLOR 0x00001000
-# define NV097_SET_LIGHT_DIFFUSE_COLOR 0x0000100C
-# define NV097_SET_LIGHT_SPECULAR_COLOR 0x00001018
-# define NV097_SET_LIGHT_LOCAL_RANGE 0x00001024
-# define NV097_SET_LIGHT_INFINITE_HALF_VECTOR 0x00001028
-# define NV097_SET_LIGHT_INFINITE_DIRECTION 0x00001034
-# define NV097_SET_LIGHT_SPOT_FALLOFF 0x00001040
-# define NV097_SET_LIGHT_SPOT_DIRECTION 0x0000104C
-# define NV097_SET_LIGHT_LOCAL_POSITION 0x0000105C
-# define NV097_SET_LIGHT_LOCAL_ATTENUATION 0x00001068
-# define NV097_SET_VERTEX3F 0x00001500
-# define NV097_SET_VERTEX4F 0x00001518
-# define NV097_SET_VERTEX_DATA_ARRAY_OFFSET 0x00001720
-# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT 0x00001760
-# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE 0x0000000F
-# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_UB_D3D 0
-# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_S1 1
-# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_F 2
-# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_UB_OGL 4
-# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_S32K 5
-# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_CMP 6
-# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_SIZE 0x000000F0
-# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_STRIDE 0xFFFFFF00
-# define NV097_SET_LOGIC_OP_ENABLE 0x000017BC
-# define NV097_SET_LOGIC_OP 0x000017C0
-# define NV097_CLEAR_REPORT_VALUE 0x000017C8
-# define NV097_CLEAR_REPORT_VALUE_TYPE 0xFFFFFFFF
-# define NV097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 1
-# define NV097_SET_ZPASS_PIXEL_COUNT_ENABLE 0x000017CC
-# define NV097_GET_REPORT 0x000017D0
-# define NV097_GET_REPORT_OFFSET 0x00FFFFFF
-# define NV097_GET_REPORT_TYPE 0xFF000000
-# define NV097_GET_REPORT_TYPE_ZPASS_PIXEL_CNT 1
-# define NV097_SET_EYE_DIRECTION 0x000017E0
-# define NV097_SET_SHADER_CLIP_PLANE_MODE 0x000017F8
-# define NV097_SET_BEGIN_END 0x000017FC
-# define NV097_SET_BEGIN_END_OP_END 0x00
-# define NV097_SET_BEGIN_END_OP_POINTS 0x01
-# define NV097_SET_BEGIN_END_OP_LINES 0x02
-# define NV097_SET_BEGIN_END_OP_LINE_LOOP 0x03
-# define NV097_SET_BEGIN_END_OP_LINE_STRIP 0x04
-# define NV097_SET_BEGIN_END_OP_TRIANGLES 0x05
-# define NV097_SET_BEGIN_END_OP_TRIANGLE_STRIP 0x06
-# define NV097_SET_BEGIN_END_OP_TRIANGLE_FAN 0x07
-# define NV097_SET_BEGIN_END_OP_QUADS 0x08
-# define NV097_SET_BEGIN_END_OP_QUAD_STRIP 0x09
-# define NV097_SET_BEGIN_END_OP_POLYGON 0x0A
-# define NV097_ARRAY_ELEMENT16 0x00001800
-# define NV097_ARRAY_ELEMENT32 0x00001808
-# define NV097_DRAW_ARRAYS 0x00001810
-# define NV097_DRAW_ARRAYS_COUNT 0xFF000000
-# define NV097_DRAW_ARRAYS_START_INDEX 0x00FFFFFF
-# define NV097_INLINE_ARRAY 0x00001818
-# define NV097_SET_EYE_VECTOR 0x0000181C
-# define NV097_SET_VERTEX_DATA2F_M 0x00001880
-# define NV097_SET_VERTEX_DATA2S 0x00001900
-# define NV097_SET_VERTEX_DATA4UB 0x00001940
-# define NV097_SET_VERTEX_DATA4S_M 0x00001980
-# define NV097_SET_VERTEX_DATA4F_M 0x00001A00
-# define NV097_SET_TEXTURE_OFFSET 0x00001B00
-# define NV097_SET_TEXTURE_FORMAT 0x00001B04
-# define NV097_SET_TEXTURE_FORMAT_CONTEXT_DMA 0x00000003
-# define NV097_SET_TEXTURE_FORMAT_CUBEMAP_ENABLE (1 << 2)
-# define NV097_SET_TEXTURE_FORMAT_BORDER_SOURCE (1 << 3)
-# define NV097_SET_TEXTURE_FORMAT_BORDER_SOURCE_TEXTURE 0
-# define NV097_SET_TEXTURE_FORMAT_BORDER_SOURCE_COLOR 1
-# define NV097_SET_TEXTURE_FORMAT_DIMENSIONALITY 0x000000F0
-# define NV097_SET_TEXTURE_FORMAT_COLOR 0x0000FF00
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_Y8 0x00
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_AY8 0x01
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A1R5G5B5 0x02
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_X1R5G5B5 0x03
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A4R4G4B4 0x04
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R5G6B5 0x05
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A8R8G8B8 0x06
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_X8R8G8B8 0x07
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_I8_A8R8G8B8 0x0B
-# define NV097_SET_TEXTURE_FORMAT_COLOR_L_DXT1_A1R5G5B5 0x0C
-# define NV097_SET_TEXTURE_FORMAT_COLOR_L_DXT23_A8R8G8B8 0x0E
-# define NV097_SET_TEXTURE_FORMAT_COLOR_L_DXT45_A8R8G8B8 0x0F
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A1R5G5B5 0x10
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R5G6B5 0x11
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8R8G8B8 0x12
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_Y8 0x13
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_SY8 0x14
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_X7SY9 0x15
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R8B8 0x16
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_G8B8 0x17
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_SG8SB8 0x18
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A8 0x19
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A8Y8 0x1A
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_AY8 0x1B
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_X1R5G5B5 0x1C
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A4R4G4B4 0x1D
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_X8R8G8B8 0x1E
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8 0x1F
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8Y8 0x20
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LC_IMAGE_CR8YB8CB8YA8 0x24
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LC_IMAGE_YB8CR8YA8CB8 0x25
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8CR8CB8Y8 0x26
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R6G5B5 0x27
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_G8B8 0x28
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R8B8 0x29
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_X8_Y24_FIXED 0x2A
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_X8_Y24_FLOAT 0x2B
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_Y16_FIXED 0x2C
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_Y16_FLOAT 0x2D
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_DEPTH_X8_Y24_FIXED 0x2E
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_DEPTH_Y16_FIXED 0x30
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_DEPTH_Y16_FLOAT 0x31
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_Y16 0x32
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_YB16YA16 0x33 // was NV097_SET_TEXTURE_FORMAT_COLOR_SZ_YB_16_YA_16
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LC_IMAGE_A4V6YB6A4U6YA6 0x34
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_Y16 0x35
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_YB16YA16 0x36
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R6G5B5 0x37
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R5G5B5A1 0x38
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R4G4B4A4 0x39
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A8B8G8R8 0x3A
-# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R8G8B8A8 0x3C
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R5G5B5A1 0x3D
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R4G4B4A4 0x3E
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8B8G8R8 0x3F
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_B8G8R8A8 0x40
-# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R8G8B8A8 0x41
-# define NV097_SET_TEXTURE_FORMAT_MIPMAP_LEVELS 0x000F0000
-# define NV097_SET_TEXTURE_FORMAT_BASE_SIZE_U 0x00F00000
-# define NV097_SET_TEXTURE_FORMAT_BASE_SIZE_V 0x0F000000
-# define NV097_SET_TEXTURE_FORMAT_BASE_SIZE_P 0xF0000000
-# define NV097_SET_TEXTURE_ADDRESS 0x00001B08
-# define NV097_SET_TEXTURE_CONTROL0 0x00001B0C
-# define NV097_SET_TEXTURE_CONTROL0_ENABLE (1 << 30)
-# define NV097_SET_TEXTURE_CONTROL0_MIN_LOD_CLAMP 0x3FFC0000
-# define NV097_SET_TEXTURE_CONTROL0_MAX_LOD_CLAMP 0x0003FFC0
-# define NV097_SET_TEXTURE_CONTROL1 0x00001B10
-# define NV097_SET_TEXTURE_CONTROL1_IMAGE_PITCH 0xFFFF0000
-# define NV097_SET_TEXTURE_FILTER 0x00001B14
-# define NV097_SET_TEXTURE_FILTER_MIPMAP_LOD_BIAS 0x00001FFF
-# define NV097_SET_TEXTURE_FILTER_MIN 0x00FF0000
-# define NV097_SET_TEXTURE_FILTER_MAG 0x0F000000
-# define NV097_SET_TEXTURE_FILTER_ASIGNED (1 << 28)
-# define NV097_SET_TEXTURE_FILTER_RSIGNED (1 << 29)
-# define NV097_SET_TEXTURE_FILTER_GSIGNED (1 << 30)
-# define NV097_SET_TEXTURE_FILTER_BSIGNED (1 << 31)
-# define NV097_SET_TEXTURE_IMAGE_RECT 0x00001B1C
-# define NV097_SET_TEXTURE_IMAGE_RECT_WIDTH 0xFFFF0000
-# define NV097_SET_TEXTURE_IMAGE_RECT_HEIGHT 0x0000FFFF
-# define NV097_SET_TEXTURE_PALETTE 0x00001B20
-# define NV097_SET_TEXTURE_PALETTE_CONTEXT_DMA (1 << 0)
-# define NV097_SET_TEXTURE_PALETTE_LENGTH 0x0000000C
-# define NV097_SET_TEXTURE_PALETTE_LENGTH_256 0
-# define NV097_SET_TEXTURE_PALETTE_LENGTH_128 1
-# define NV097_SET_TEXTURE_PALETTE_LENGTH_64 2
-# define NV097_SET_TEXTURE_PALETTE_LENGTH_32 3
-# define NV097_SET_TEXTURE_PALETTE_OFFSET 0xFFFFFFC0
-# define NV097_SET_TEXTURE_BORDER_COLOR 0x00001B24
-# define NV097_SET_TEXTURE_SET_BUMP_ENV_MAT 0x00001B28
-# define NV097_SET_TEXTURE_SET_BUMP_ENV_SCALE 0x00001B38
-# define NV097_SET_TEXTURE_SET_BUMP_ENV_OFFSET 0x00001B3C
-# define NV097_SET_SEMAPHORE_OFFSET 0x00001D6C
-# define NV097_BACK_END_WRITE_SEMAPHORE_RELEASE 0x00001D70
-# define NV097_SET_ZMIN_MAX_CONTROL 0x00001D78
-# define NV097_SET_COMPRESS_ZBUFFER_EN 0x00001D80
-# define NV097_SET_ZSTENCIL_CLEAR_VALUE 0x00001D8C
-# define NV097_SET_COLOR_CLEAR_VALUE 0x00001D90
-# define NV097_CLEAR_SURFACE 0x00001D94
-# define NV097_CLEAR_SURFACE_Z (1 << 0)
-# define NV097_CLEAR_SURFACE_STENCIL (1 << 1)
-# define NV097_CLEAR_SURFACE_COLOR 0x000000F0
-# define NV097_CLEAR_SURFACE_R (1 << 4)
-# define NV097_CLEAR_SURFACE_G (1 << 5)
-# define NV097_CLEAR_SURFACE_B (1 << 6)
-# define NV097_CLEAR_SURFACE_A (1 << 7)
-# define NV097_SET_CLEAR_RECT_HORIZONTAL 0x00001D98
-# define NV097_SET_CLEAR_RECT_VERTICAL 0x00001D9C
-# define NV097_SET_SPECULAR_FOG_FACTOR 0x00001E20
-# define NV097_SET_COMBINER_COLOR_OCW 0x00001E40
-# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB 0xFFF80000
-# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB_DISABLE 0
-# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB_AB_DST_ENABLE 1
-# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD (1<<18)
-# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD_DISABLE 0
-# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD_CD_DST_ENABLE 1
-# define NV097_SET_COMBINER_COLOR_OCW_OP 0x00038000
-# define NV097_SET_COMBINER_COLOR_OCW_OP_NOSHIFT 0
-# define NV097_SET_COMBINER_COLOR_OCW_OP_NOSHIFT_BIAS 1
-# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY1 2
-# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY1_BIAS 3
-# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY2 4
-# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTRIGHTBY1 6
-# define NV097_SET_COMBINER_COLOR_OCW_MUX_ENABLE (1 << 14)
-# define NV097_SET_COMBINER_COLOR_OCW_AB_DOT_ENABLE (1 << 13)
-# define NV097_SET_COMBINER_COLOR_OCW_CD_DOT_ENABLE (1<<12)
-# define NV097_SET_COMBINER_COLOR_OCW_SUM_DST 0x00000F00
-# define NV097_SET_COMBINER_COLOR_OCW_AB_DST 0x000000F0
-# define NV097_SET_COMBINER_COLOR_OCW_CD_DST 0x0000000F
-# define NV097_SET_COMBINER_CONTROL 0x00001E60
-# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT 0x000000FF
-# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_ONE 1
-# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_TWO 2
-# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_THREE 3
-# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_FOUR 4
-# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_FIVE 5
-# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_SIX 6
-# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_SEVEN 7
-# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_EIGHT 8
-# define NV097_SET_COMBINER_CONTROL_MUX_SELECT 0x00000F00
-# define NV097_SET_COMBINER_CONTROL_MUX_SELECT_LSB 0
-# define NV097_SET_COMBINER_CONTROL_MUX_SELECT_MSB 1
-# define NV097_SET_COMBINER_CONTROL_FACTOR0 0x0000F000
-# define NV097_SET_COMBINER_CONTROL_FACTOR0_SAME_FACTOR_ALL 0
-# define NV097_SET_COMBINER_CONTROL_FACTOR0_EACH_STAGE 1
-# define NV097_SET_COMBINER_CONTROL_FACTOR1 0xFFFF0000
-# define NV097_SET_COMBINER_CONTROL_FACTOR1_SAME_FACTOR_ALL 0
-# define NV097_SET_COMBINER_CONTROL_FACTOR1_EACH_STAGE 1
-# define NV097_SET_SHADOW_ZSLOPE_THRESHOLD 0x00001E68
-# define NV097_SET_SHADER_STAGE_PROGRAM 0x00001E70
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0 0x0000001F
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_PROGRAM_NONE 0
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_2D_PROJECTIVE 1
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_3D_PROJECTIVE 2
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_CUBE_MAP 3
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_PASS_THROUGH 4
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_CLIP_PLANE 5
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1 0x000003E0
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_PROGRAM_NONE 0x00
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_2D_PROJECTIVE 0x01
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_3D_PROJECTIVE 0x02
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_CUBE_MAP 0x03
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_PASS_THROUGH 0x04
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_CLIP_PLANE 0x05
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_BUMPENVMAP 0x06
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_BUMPENVMAP_LUMINANCE 0x07
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_DEPENDENT_AR 0x0F
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_DEPENDENT_GB 0x10
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_DOT_PRODUCT 0x11
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2 0x00007C00
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_PROGRAM_NONE 0x00
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_2D_PROJECTIVE 0x01
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_3D_PROJECTIVE 0x02
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_CUBE_MAP 0x03
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_PASS_THROUGH 0x04
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_CLIP_PLANE 0x05
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_BUMPENVMAP 0x06
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_BUMPENVMAP_LUMINANCE 0x07
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_BRDF 0x08
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_ST 0x09
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_ZW 0x0A
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_REFLECT_DIFFUSE 0x0B
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DEPENDENT_AR 0x0F
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DEPENDENT_GB 0x10
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_PRODUCT 0x11
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3 0x000F8000
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_PROGRAM_NONE 0x00
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_2D_PROJECTIVE 0x01
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_3D_PROJECTIVE 0x02
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_CUBE_MAP 0x03
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_PASS_THROUGH 0x04
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_CLIP_PLANE 0x05
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_BUMPENVMAP 0x06
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_BUMPENVMAP_LUMINANCE 0x07
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_BRDF 0x08
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_ST 0x09
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_ZW 0x0A
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_REFLECT_SPECULAR 0x0C
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_STR_3D 0x0D
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_STR_CUBE 0x0E
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DEPENDENT_AR 0x0F
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DEPENDENT_GB 0x10
-# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_REFLECT_SPECULAR_CONST 0x12
-# define NV097_SET_SHADER_OTHER_STAGE_INPUT 0x00001E78
-# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE1 0x0000FFFF
-# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE1_INSTAGE_0 0
-# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2 0x000F0000
-# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2_INSTAGE_0 0
-# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2_INSTAGE_1 1
-# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3 0x00F00000
-# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_0 0
-# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_1 1
-# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_2 2
-# define NV097_SET_TRANSFORM_DATA 0x00001E80
-# define NV097_LAUNCH_TRANSFORM_PROGRAM 0x00001E90
-# define NV097_SET_TRANSFORM_EXECUTION_MODE 0x00001E94
-# define NV097_SET_TRANSFORM_EXECUTION_MODE_MODE 0x00000003
-# define NV097_SET_TRANSFORM_EXECUTION_MODE_MODE_FIXED 0
-# define NV097_SET_TRANSFORM_EXECUTION_MODE_MODE_PROGRAM 2
-# define NV097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE 0xFFFFFFFC
-# define NV097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE_USER 0
-# define NV097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE_PRIV 1
-# define NV097_SET_TRANSFORM_PROGRAM_CXT_WRITE_EN 0x00001E98
-# define NV097_SET_TRANSFORM_PROGRAM_LOAD 0x00001E9C
-# define NV097_SET_TRANSFORM_PROGRAM_START 0x00001EA0
-# define NV097_SET_TRANSFORM_CONSTANT_LOAD 0x00001EA4
+typedef struct TextureShape {
+ bool cubemap;
+ unsigned int dimensionality;
+ unsigned int color_format;
+ unsigned int levels;
+ unsigned int width, height, depth;
-/* vertex processing (cheops) context layout */
-#define NV_IGRAPH_XF_XFCTX_CMAT0 0x00
-#define NV_IGRAPH_XF_XFCTX_PMAT0 0x04
-#define NV_IGRAPH_XF_XFCTX_MMAT0 0x08
-#define NV_IGRAPH_XF_XFCTX_IMMAT0 0x0c
-#define NV_IGRAPH_XF_XFCTX_MMAT1 0x10
-#define NV_IGRAPH_XF_XFCTX_IMMAT1 0x14
-#define NV_IGRAPH_XF_XFCTX_MMAT2 0x18
-#define NV_IGRAPH_XF_XFCTX_IMMAT2 0x1c
-#define NV_IGRAPH_XF_XFCTX_MMAT3 0x20
-#define NV_IGRAPH_XF_XFCTX_IMMAT3 0x24
-#define NV_IGRAPH_XF_XFCTX_LIT0 0x28
-#define NV_IGRAPH_XF_XFCTX_LIT1 0x29
-#define NV_IGRAPH_XF_XFCTX_LIT2 0x2a
-#define NV_IGRAPH_XF_XFCTX_LIT3 0x2b
-#define NV_IGRAPH_XF_XFCTX_LIT4 0x2c
-#define NV_IGRAPH_XF_XFCTX_LIT5 0x2d
-#define NV_IGRAPH_XF_XFCTX_LIT6 0x2e
-#define NV_IGRAPH_XF_XFCTX_LIT7 0x2f
-#define NV_IGRAPH_XF_XFCTX_SPOT0 0x30
-#define NV_IGRAPH_XF_XFCTX_SPOT1 0x31
-#define NV_IGRAPH_XF_XFCTX_SPOT2 0x32
-#define NV_IGRAPH_XF_XFCTX_SPOT3 0x33
-#define NV_IGRAPH_XF_XFCTX_SPOT4 0x34
-#define NV_IGRAPH_XF_XFCTX_SPOT5 0x35
-#define NV_IGRAPH_XF_XFCTX_SPOT6 0x36
-#define NV_IGRAPH_XF_XFCTX_SPOT7 0x37
-#define NV_IGRAPH_XF_XFCTX_EYEP 0x38
-#define NV_IGRAPH_XF_XFCTX_FOG 0x39
-#define NV_IGRAPH_XF_XFCTX_VPSCL 0x3a
-#define NV_IGRAPH_XF_XFCTX_VPOFF 0x3b
-#define NV_IGRAPH_XF_XFCTX_CONS0 0x3c
-#define NV_IGRAPH_XF_XFCTX_CONS1 0x3d
-#define NV_IGRAPH_XF_XFCTX_CONS2 0x3e
-#define NV_IGRAPH_XF_XFCTX_CONS3 0x3f
-#define NV_IGRAPH_XF_XFCTX_TG0MAT 0x40
-#define NV_IGRAPH_XF_XFCTX_T0MAT 0x44
-#define NV_IGRAPH_XF_XFCTX_TG1MAT 0x48
-#define NV_IGRAPH_XF_XFCTX_T1MAT 0x4c
-#define NV_IGRAPH_XF_XFCTX_TG2MAT 0x50
-#define NV_IGRAPH_XF_XFCTX_T2MAT 0x54
-#define NV_IGRAPH_XF_XFCTX_TG3MAT 0x58
-#define NV_IGRAPH_XF_XFCTX_T3MAT 0x5c
-#define NV_IGRAPH_XF_XFCTX_PRSPACE 0x60
+ unsigned int min_mipmap_level, max_mipmap_level;
+ unsigned int pitch;
+} TextureShape;
-/* lighting (zoser) context layout */
-#define NV_IGRAPH_XF_LTCTXA_L0_K 0x00
-#define NV_IGRAPH_XF_LTCTXA_L0_SPT 0x01
-#define NV_IGRAPH_XF_LTCTXA_L1_K 0x02
-#define NV_IGRAPH_XF_LTCTXA_L1_SPT 0x03
-#define NV_IGRAPH_XF_LTCTXA_L2_K 0x04
-#define NV_IGRAPH_XF_LTCTXA_L2_SPT 0x05
-#define NV_IGRAPH_XF_LTCTXA_L3_K 0x06
-#define NV_IGRAPH_XF_LTCTXA_L3_SPT 0x07
-#define NV_IGRAPH_XF_LTCTXA_L4_K 0x08
-#define NV_IGRAPH_XF_LTCTXA_L4_SPT 0x09
-#define NV_IGRAPH_XF_LTCTXA_L5_K 0x0a
-#define NV_IGRAPH_XF_LTCTXA_L5_SPT 0x0b
-#define NV_IGRAPH_XF_LTCTXA_L6_K 0x0c
-#define NV_IGRAPH_XF_LTCTXA_L6_SPT 0x0d
-#define NV_IGRAPH_XF_LTCTXA_L7_K 0x0e
-#define NV_IGRAPH_XF_LTCTXA_L7_SPT 0x0f
-#define NV_IGRAPH_XF_LTCTXA_EYED 0x10
-#define NV_IGRAPH_XF_LTCTXA_FR_AMB 0x11
-#define NV_IGRAPH_XF_LTCTXA_BR_AMB 0x12
-#define NV_IGRAPH_XF_LTCTXA_CM_COL 0x13
-#define NV_IGRAPH_XF_LTCTXA_BCM_COL 0x14
-#define NV_IGRAPH_XF_LTCTXA_FOG_K 0x15
-#define NV_IGRAPH_XF_LTCTXA_ZERO 0x16
-#define NV_IGRAPH_XF_LTCTXA_PT0 0x17
-#define NV_IGRAPH_XF_LTCTXA_FOGLIN 0x18
+typedef struct TextureKey {
+ TextureShape state;
+ uint64_t data_hash;
+ uint8_t* texture_data;
+ uint8_t* palette_data;
+} TextureKey;
-#define NV_IGRAPH_XF_LTCTXB_L0_AMB 0x00
-#define NV_IGRAPH_XF_LTCTXB_L0_DIF 0x01
-#define NV_IGRAPH_XF_LTCTXB_L0_SPC 0x02
-#define NV_IGRAPH_XF_LTCTXB_L0_BAMB 0x03
-#define NV_IGRAPH_XF_LTCTXB_L0_BDIF 0x04
-#define NV_IGRAPH_XF_LTCTXB_L0_BSPC 0x05
-#define NV_IGRAPH_XF_LTCTXB_L1_AMB 0x06
-#define NV_IGRAPH_XF_LTCTXB_L1_DIF 0x07
-#define NV_IGRAPH_XF_LTCTXB_L1_SPC 0x08
-#define NV_IGRAPH_XF_LTCTXB_L1_BAMB 0x09
-#define NV_IGRAPH_XF_LTCTXB_L1_BDIF 0x0a
-#define NV_IGRAPH_XF_LTCTXB_L1_BSPC 0x0b
-#define NV_IGRAPH_XF_LTCTXB_L2_AMB 0x0c
-#define NV_IGRAPH_XF_LTCTXB_L2_DIF 0x0d
-#define NV_IGRAPH_XF_LTCTXB_L2_SPC 0x0e
-#define NV_IGRAPH_XF_LTCTXB_L2_BAMB 0x0f
-#define NV_IGRAPH_XF_LTCTXB_L2_BDIF 0x10
-#define NV_IGRAPH_XF_LTCTXB_L2_BSPC 0x11
-#define NV_IGRAPH_XF_LTCTXB_L3_AMB 0x12
-#define NV_IGRAPH_XF_LTCTXB_L3_DIF 0x13
-#define NV_IGRAPH_XF_LTCTXB_L3_SPC 0x14
-#define NV_IGRAPH_XF_LTCTXB_L3_BAMB 0x15
-#define NV_IGRAPH_XF_LTCTXB_L3_BDIF 0x16
-#define NV_IGRAPH_XF_LTCTXB_L3_BSPC 0x17
-#define NV_IGRAPH_XF_LTCTXB_L4_AMB 0x18
-#define NV_IGRAPH_XF_LTCTXB_L4_DIF 0x19
-#define NV_IGRAPH_XF_LTCTXB_L4_SPC 0x1a
-#define NV_IGRAPH_XF_LTCTXB_L4_BAMB 0x1b
-#define NV_IGRAPH_XF_LTCTXB_L4_BDIF 0x1c
-#define NV_IGRAPH_XF_LTCTXB_L4_BSPC 0x1d
-#define NV_IGRAPH_XF_LTCTXB_L5_AMB 0x1e
-#define NV_IGRAPH_XF_LTCTXB_L5_DIF 0x1f
-#define NV_IGRAPH_XF_LTCTXB_L5_SPC 0x20
-#define NV_IGRAPH_XF_LTCTXB_L5_BAMB 0x21
-#define NV_IGRAPH_XF_LTCTXB_L5_BDIF 0x22
-#define NV_IGRAPH_XF_LTCTXB_L5_BSPC 0x23
-#define NV_IGRAPH_XF_LTCTXB_L6_AMB 0x24
-#define NV_IGRAPH_XF_LTCTXB_L6_DIF 0x25
-#define NV_IGRAPH_XF_LTCTXB_L6_SPC 0x26
-#define NV_IGRAPH_XF_LTCTXB_L6_BAMB 0x27
-#define NV_IGRAPH_XF_LTCTXB_L6_BDIF 0x28
-#define NV_IGRAPH_XF_LTCTXB_L6_BSPC 0x29
-#define NV_IGRAPH_XF_LTCTXB_L7_AMB 0x2a
-#define NV_IGRAPH_XF_LTCTXB_L7_DIF 0x2b
-#define NV_IGRAPH_XF_LTCTXB_L7_SPC 0x2c
-#define NV_IGRAPH_XF_LTCTXB_L7_BAMB 0x2d
-#define NV_IGRAPH_XF_LTCTXB_L7_BDIF 0x2e
-#define NV_IGRAPH_XF_LTCTXB_L7_BSPC 0x2f
-#define NV_IGRAPH_XF_LTCTXB_PT1 0x30
-#define NV_IGRAPH_XF_LTCTXB_ONE 0x31
-#define NV_IGRAPH_XF_LTCTXB_VPOFFSET 0x32
+typedef struct TextureBinding {
+ GLenum gl_target;
+ GLuint gl_texture;
+ unsigned int refcnt;
+} TextureBinding;
-#define NV_IGRAPH_XF_LTC1_ZERO1 0x00
-#define NV_IGRAPH_XF_LTC1_l0 0x01
-#define NV_IGRAPH_XF_LTC1_Bl0 0x02
-#define NV_IGRAPH_XF_LTC1_PP 0x03
-#define NV_IGRAPH_XF_LTC1_r0 0x04
-#define NV_IGRAPH_XF_LTC1_r1 0x05
-#define NV_IGRAPH_XF_LTC1_r2 0x06
-#define NV_IGRAPH_XF_LTC1_r3 0x07
-#define NV_IGRAPH_XF_LTC1_r4 0x08
-#define NV_IGRAPH_XF_LTC1_r5 0x09
-#define NV_IGRAPH_XF_LTC1_r6 0x0a
-#define NV_IGRAPH_XF_LTC1_r7 0x0b
-#define NV_IGRAPH_XF_LTC1_L0 0x0c
-#define NV_IGRAPH_XF_LTC1_L1 0x0d
-#define NV_IGRAPH_XF_LTC1_L2 0x0e
-#define NV_IGRAPH_XF_LTC1_L3 0x0f
-#define NV_IGRAPH_XF_LTC1_L4 0x10
-#define NV_IGRAPH_XF_LTC1_L5 0x11
-#define NV_IGRAPH_XF_LTC1_L6 0x12
-#define NV_IGRAPH_XF_LTC1_L7 0x13
+typedef struct KelvinState {
+ xbaddr object_instance;
+} KelvinState;
+typedef struct ContextSurfaces2DState {
+ xbaddr object_instance;
+ xbaddr dma_image_source;
+ xbaddr dma_image_dest;
+ unsigned int color_format;
+ unsigned int source_pitch, dest_pitch;
+ xbaddr source_offset, dest_offset;
+} ContextSurfaces2DState;
-#define NV2A_VERTEX_ATTR_POSITION 0
-#define NV2A_VERTEX_ATTR_WEIGHT 1
-#define NV2A_VERTEX_ATTR_NORMAL 2
-#define NV2A_VERTEX_ATTR_DIFFUSE 3
-#define NV2A_VERTEX_ATTR_SPECULAR 4
-#define NV2A_VERTEX_ATTR_FOG 5
-#define NV2A_VERTEX_ATTR_POINT_SIZE 6
-#define NV2A_VERTEX_ATTR_BACK_DIFFUSE 7
-#define NV2A_VERTEX_ATTR_BACK_SPECULAR 8
-#define NV2A_VERTEX_ATTR_TEXTURE0 9
-#define NV2A_VERTEX_ATTR_TEXTURE1 10
-#define NV2A_VERTEX_ATTR_TEXTURE2 11
-#define NV2A_VERTEX_ATTR_TEXTURE3 12
-#define NV2A_VERTEX_ATTR_RESERVED1 13
-#define NV2A_VERTEX_ATTR_RESERVED2 14
-#define NV2A_VERTEX_ATTR_RESERVED3 15
+typedef struct ImageBlitState {
+ xbaddr object_instance;
+ xbaddr context_surfaces;
+ unsigned int operation;
+ unsigned int in_x, in_y;
+ unsigned int out_x, out_y;
+ unsigned int width, height;
+} ImageBlitState;
-#define NV2A_CRYSTAL_FREQ 16666666 // Was 13500000
-#define NV2A_NUM_CHANNELS 32
-#define NV2A_NUM_SUBCHANNELS 8
+typedef struct PGRAPHState {
+ bool opengl_enabled; // == bLLE_GPU
+ QemuMutex pgraph_lock;
-#define NV2A_MAX_BATCH_LENGTH 0x1FFFF
-#define NV2A_VERTEXSHADER_ATTRIBUTES 16
-#define NV2A_MAX_TEXTURES 4
+ uint32_t pending_interrupts;
+ uint32_t enabled_interrupts;
+ QemuCond interrupt_cond;
-#define NV2A_MAX_TRANSFORM_PROGRAM_LENGTH 136
-#define NV2A_VERTEXSHADER_CONSTANTS 192
-#define NV2A_MAX_LIGHTS 8
+ /* subchannels state we're not sure the location of... */
+ ContextSurfaces2DState context_surfaces_2d;
+ ImageBlitState image_blit;
+ KelvinState kelvin;
-#define NV2A_LTCTXA_COUNT 26
-#define NV2A_LTCTXB_COUNT 52
-#define NV2A_LTC1_COUNT 20
+ QemuCond fifo_access_cond;
+ QemuCond flip_3d;
+
+ xbaddr dma_color, dma_zeta;
+ Surface surface_color, surface_zeta;
+ unsigned int surface_type;
+ SurfaceShape surface_shape;
+ SurfaceShape last_surface_shape;
+
+ xbaddr dma_a, dma_b;
+#ifdef USE_TEXTURE_CACHE
+ GLruCache *texture_cache;
+#endif
+ bool texture_dirty[NV2A_MAX_TEXTURES];
+ TextureBinding *texture_binding[NV2A_MAX_TEXTURES];
+
+#ifdef USE_SHADER_CACHE
+ GHashTable *shader_cache;
+#endif
+ ShaderBinding *shader_binding;
+
+ bool texture_matrix_enable[NV2A_MAX_TEXTURES];
+
+ /* FIXME: Move to NV_PGRAPH_BUMPMAT... */
+ float bump_env_matrix[NV2A_MAX_TEXTURES - 1][4]; /* 3 allowed stages with 2x2 matrix each */
+
+ GloContext *gl_context;
+ GLuint gl_framebuffer;
+ GLuint gl_color_buffer, gl_zeta_buffer;
+
+ xbaddr dma_state;
+ xbaddr dma_notifies;
+ xbaddr dma_semaphore;
+
+ xbaddr dma_report;
+ xbaddr report_offset;
+ bool zpass_pixel_count_enable;
+ unsigned int zpass_pixel_count_result;
+ unsigned int gl_zpass_pixel_count_query_count;
+ GLuint* gl_zpass_pixel_count_queries;
+
+ xbaddr dma_vertex_a, dma_vertex_b;
+
+ unsigned int primitive_mode;
+
+ unsigned int clear_surface;
+
+ bool enable_vertex_program_write;
+
+ uint32_t program_data[NV2A_MAX_TRANSFORM_PROGRAM_LENGTH][VSH_TOKEN_SIZE];
+
+ uint32_t vsh_constants[NV2A_VERTEXSHADER_CONSTANTS][4];
+ bool vsh_constants_dirty[NV2A_VERTEXSHADER_CONSTANTS];
+
+ /* lighting constant arrays */
+ uint32_t ltctxa[NV2A_LTCTXA_COUNT][4];
+ bool ltctxa_dirty[NV2A_LTCTXA_COUNT];
+ uint32_t ltctxb[NV2A_LTCTXB_COUNT][4];
+ bool ltctxb_dirty[NV2A_LTCTXB_COUNT];
+ uint32_t ltc1[NV2A_LTC1_COUNT][4];
+ bool ltc1_dirty[NV2A_LTC1_COUNT];
+
+ // should figure out where these are in lighting context
+ float light_infinite_half_vector[NV2A_MAX_LIGHTS][3];
+ float light_infinite_direction[NV2A_MAX_LIGHTS][3];
+ float light_local_position[NV2A_MAX_LIGHTS][3];
+ float light_local_attenuation[NV2A_MAX_LIGHTS][3];
+
+ VertexAttribute vertex_attributes[NV2A_VERTEXSHADER_ATTRIBUTES];
+
+ unsigned int inline_array_length;
+ uint32_t inline_array[NV2A_MAX_BATCH_LENGTH];
+ GLuint gl_inline_array_buffer;
+
+ unsigned int inline_elements_length;
+ uint16_t inline_elements[NV2A_MAX_BATCH_LENGTH]; // Cxbx-Reloaded TODO : Restore uint32_t once HLE_draw_inline_elements can using that
+
+ unsigned int inline_buffer_length;
+
+ unsigned int draw_arrays_length;
+ unsigned int draw_arrays_max_count;
+
+ /* FIXME: Unknown size, possibly endless, 1000 will do for now */
+ GLint gl_draw_arrays_start[1000];
+ GLsizei gl_draw_arrays_count[1000];
+
+ GLuint gl_element_buffer;
+ GLuint gl_memory_buffer;
+ GLuint gl_vertex_array;
+
+ uint32_t regs[NV_PGRAPH_SIZE]; // TODO : union
+} PGRAPHState;
+
+typedef struct OverlayState {
+ bool video_buffer_use;
+ int pitch;
+ bool is_transparent;
+#ifdef DEBUG
+ hwaddr base;
+ hwaddr limit;
+#endif
+ hwaddr offset;
+ uint32_t in_height;
+ uint32_t in_width;
+ int out_x;
+ int out_y;
+ int out_width;
+ int out_height;
+
+ bool covers_framebuffer;
+ int old_in_width;
+ int old_in_height;
+ int old_pitch;
+ GLuint gl_texture;
+} OverlayState;
+
+typedef struct NV2AState {
+ // PCIDevice dev;
+ // qemu_irq irq;
+ bool exiting;
+ bool enable_overlay = false;
+
+ // VGACommonState vga;
+ // GraphicHwOps hw_ops;
+ // QEMUTimer *vblank_timer;
+
+ // MemoryRegion *vram;
+ // MemoryRegion vram_pci;
+ uint8_t *vram_ptr;
+ size_t vram_size;
+ // MemoryRegion ramin;
+ struct {
+ uint8_t *ramin_ptr;
+ size_t ramin_size;
+ } pramin;
+
+ // MemoryRegion mmio;
+ // MemoryRegion block_mmio[NV_NUM_BLOCKS];
+
+ struct {
+ uint32_t pending_interrupts;
+ uint32_t enabled_interrupts;
+ uint32_t regs[NV_PMC_SIZE]; // Not in xqemu/openxbox? TODO : union
+ } pmc;
+
+ struct {
+ uint32_t pending_interrupts;
+ uint32_t enabled_interrupts;
+ uint32_t regs[_NV_PFIFO_SIZE]; // TODO : union
+ QemuMutex pfifo_lock;
+ std::thread puller_thread;
+ QemuCond puller_cond;
+ std::thread pusher_thread;
+ QemuCond pusher_cond;
+ } pfifo;
+
+ struct {
+ uint32_t pending_interrupts;
+ uint32_t enabled_interrupts;
+ //QemuCond interrupt_cond; // pvideo.interrupt_cond not used (yet)
+ OverlayState overlays[2]; // NV2A supports 2 video overlays
+ uint32_t regs[NV_PVIDEO_SIZE]; // TODO : union
+ } pvideo;
+
+ struct {
+ uint32_t pending_interrupts;
+ uint32_t enabled_interrupts;
+ uint32_t numerator;
+ uint32_t denominator;
+ uint32_t alarm_time;
+ uint32_t regs[NV_PTIMER_SIZE]; // Not in xqemu/openxbox? TODO : union
+ } ptimer;
+
+ struct {
+ uint32_t regs[NV_PFB_SIZE]; // TODO : union
+ } pfb;
+
+ struct PGRAPHState pgraph;
+
+ struct {
+ uint32_t pending_interrupts;
+ uint32_t enabled_interrupts;
+ hwaddr start;
+ uint32_t regs[NV_PCRTC_SIZE]; // Not in xqemu/openxbox? TODO : union
+ } pcrtc;
+
+ struct {
+ uint32_t core_clock_coeff;
+ uint64_t core_clock_freq;
+ uint32_t memory_clock_coeff;
+ uint32_t video_clock_coeff;
+ uint32_t regs[NV_PRAMDAC_SIZE]; // Not in xqemu/openxbox? TODO : union
+ } pramdac;
+
+ // PRMCIO (Actually the VGA controller)
+ struct {
+ uint8_t cr_index;
+ uint8_t cr[256]; /* CRT registers */
+ } prmcio; // Not in xqemu/openxbox?
+} NV2AState;
+
+typedef value_t(*read_func)(NV2AState *d, hwaddr addr); //, unsigned int size);
+typedef void(*write_func)(NV2AState *d, hwaddr addr, value_t val); //, unsigned int size);
+
+typedef struct {
+ read_func read;
+ write_func write;
+} MemoryRegionOps;
+
+#if 0
+// Valid after PCI init :
+#define NV20_REG_BASE_KERNEL 0xFD000000
+
+typedef volatile DWORD *PPUSH;
+
+typedef struct {
+ DWORD Ignored[0x10];
+ PPUSH Put; // On Xbox1, this field is only written to by the CPU (the GPU uses this as a trigger to start executing from the given address)
+ PPUSH Get; // On Xbox1, this field is only read from by the CPU (the GPU reflects in here where it is/stopped executing)
+ PPUSH Reference; // TODO : xbaddr / void* / DWORD ?
+ DWORD Ignored2[0x7ED];
+} Nv2AControlDma;
+
+#define PUSH_TYPE_MASK 0x00000002 // 2 bits
+#define PUSH_TYPE_SHIFT 0
+#define PUSH_TYPE_METHOD 0 // method
+#define PUSH_TYPE_JMP_FAR 1 // jump far
+#define PUSH_TYPE_CALL_FAR 2 // call far
+#define PUSH_TYPE_METHOD_UNUSED 3 // method (unused)
+#define PUSH_METHOD_MASK 0x00001FFC // 12 bits
+#define PUSH_METHOD_SHIFT 0 // Dxbx note : Not 2, because methods are actually DWORD offsets (and thus defined with increments of 4)
+#define PUSH_SUBCH_MASK 0x0000E000 // 3 bits
+#define PUSH_SUBCH_SHIFT 13
+#define PUSH_COUNT_MASK 0x1FFC0000 // 11 bits
+#define PUSH_COUNT_SHIFT 18
+#define PUSH_INSTR_MASK 0xE0000000 // 3 bits
+#define PUSH_INSTR_SHIFT 29
+#define PUSH_INSTR_IMM_INCR 0 // immediate, increment
+#define PUSH_INSTR_JMP_NEAR 1 // near jump
+#define PUSH_INSTR_IMM_NOINC 2 // immediate, no-increment
+#define PUSH_ADDR_FAR_MASK 0xFFFFFFFC // 30 bits
+#define PUSH_ADDR_FAR_SHIFT 0
+#define PUSH_ADDR_NEAR_MASK 0x1FFFFFFC // 27 bits
+#define PUSH_ADDR_NEAR_SHIFT 0 // Cxbx note : Not 2, because methods are actually DWORD offsets (and thus defined with increments of 4)
+
+#define PUSH_TYPE(dwPushCommand) ((dwPushCommand & PUSH_TYPE_MASK) >> PUSH_TYPE_SHIFT)
+#define PUSH_METHOD(dwPushCommand) ((dwPushCommand & PUSH_METHOD_MASK) >> PUSH_METHOD_SHIFT)
+#define PUSH_SUBCH(dwPushCommand) ((dwPushCommand & PUSH_SUBCH_MASK) >> PUSH_SUBCH_SHIFT)
+#define PUSH_COUNT(dwPushCommand) ((dwPushCommand & PUSH_COUNT_MASK) >> PUSH_COUNT_SHIFT)
+#define PUSH_INSTR(dwPushCommand) ((dwPushCommand & PUSH_INSTR_MASK) >> PUSH_INSTR_SHIFT)
+#define PUSH_ADDR_FAR(dwPushCommand) ((dwPushCommand & PUSH_ADDR_FAR_MASK) >> PUSH_ADDR_FAR_SHIFT)
+#define PUSH_ADDR_NEAR(dwPushCommand) ((dwPushCommand & PUSH_ADDR_NEAR_MASK) >> PUSH_ADDR_NEAR_SHIFT)
+
+#define PUSH_METHOD_MAX ((PUSH_METHOD_MASK | 3) >> PUSH_METHOD_SHIFT) // = 8191
+#define PUSH_SUBCH_MAX (PUSH_SUBCH_MASK >> PUSH_SUBCH_SHIFT) // = 7
+#define PUSH_COUNT_MAX (PUSH_COUNT_MASK >> PUSH_COUNT_SHIFT) // = 2047
+
+// Decode push buffer conmmand (inverse of D3DPUSH_ENCODE)
+inline void D3DPUSH_DECODE(const DWORD dwPushCommand, DWORD &dwMethod, DWORD &dwSubCh, DWORD &dwCount)
+{
+ dwMethod = PUSH_METHOD(dwPushCommand);
+ dwSubCh = PUSH_SUBCH(dwPushCommand);
+ dwCount = PUSH_COUNT(dwPushCommand);
+}
+#endif
+
+#endif
diff --git a/src/devices/video/nv2a_psh.cpp b/src/devices/video/nv2a_psh.cpp
index ef48257ba..c559cf9ed 100644
--- a/src/devices/video/nv2a_psh.cpp
+++ b/src/devices/video/nv2a_psh.cpp
@@ -338,7 +338,7 @@ static QString* get_input_var(struct PixelShader *ps, struct InputInfo in, bool
switch (in.mod) {
case PS_INPUTMAPPING_SIGNED_IDENTITY:
case PS_INPUTMAPPING_UNSIGNED_IDENTITY:
- QINCREF(reg);
+ qobject_ref(reg);
res = reg;
break;
case PS_INPUTMAPPING_UNSIGNED_INVERT:
@@ -364,7 +364,7 @@ static QString* get_input_var(struct PixelShader *ps, struct InputInfo in, bool
break;
}
- QDECREF(reg);
+ qobject_unref(reg);
return res;
}
@@ -374,7 +374,7 @@ static QString* get_output(QString *reg, int mapping)
QString *res;
switch (mapping) {
case PS_COMBINEROUTPUT_IDENTITY:
- QINCREF(reg);
+ qobject_ref(reg);
res = reg;
break;
case PS_COMBINEROUTPUT_BIAS:
@@ -442,8 +442,8 @@ static void add_stage_code(struct PixelShader *ps,
qstring_append_fmt(ps->code, "%s.%s = %s(%s);\n",
qstring_get_str(ab_dest), write_mask, caster, qstring_get_str(ab_mapping));
} else {
- QDECREF(ab_dest);
- QINCREF(ab_mapping);
+ qobject_unref(ab_dest);
+ qobject_ref(ab_mapping);
ab_dest = ab_mapping;
}
@@ -451,8 +451,8 @@ static void add_stage_code(struct PixelShader *ps,
qstring_append_fmt(ps->code, "%s.%s = %s(%s);\n",
qstring_get_str(cd_dest), write_mask, caster, qstring_get_str(cd_mapping));
} else {
- QDECREF(cd_dest);
- QINCREF(cd_mapping);
+ qobject_unref(cd_dest);
+ qobject_ref(cd_mapping);
cd_dest = cd_mapping;
}
@@ -479,19 +479,19 @@ static void add_stage_code(struct PixelShader *ps,
qstring_get_str(sum_dest), write_mask, caster, qstring_get_str(sum_mapping));
}
- QDECREF(a);
- QDECREF(b);
- QDECREF(c);
- QDECREF(d);
- QDECREF(ab);
- QDECREF(cd);
- QDECREF(ab_mapping);
- QDECREF(cd_mapping);
- QDECREF(ab_dest);
- QDECREF(cd_dest);
- QDECREF(sum_dest);
- QDECREF(sum);
- QDECREF(sum_mapping);
+ qobject_unref(a);
+ qobject_unref(b);
+ qobject_unref(c);
+ qobject_unref(d);
+ qobject_unref(ab);
+ qobject_unref(cd);
+ qobject_unref(ab_mapping);
+ qobject_unref(cd_mapping);
+ qobject_unref(ab_dest);
+ qobject_unref(cd_dest);
+ qobject_unref(sum_dest);
+ qobject_unref(sum);
+ qobject_unref(sum_mapping);
}
// Add code for the final combiner stage
@@ -513,14 +513,14 @@ static void add_final_stage_code(struct PixelShader *ps, struct FCInputInfo fina
/* FIXME: Is .x correctly here? */
qstring_append_fmt(ps->code, "r0.a = vec3(%s).x;\n", qstring_get_str(g));
- QDECREF(a);
- QDECREF(b);
- QDECREF(c);
- QDECREF(d);
- QDECREF(g);
+ qobject_unref(a);
+ qobject_unref(b);
+ qobject_unref(c);
+ qobject_unref(d);
+ qobject_unref(g);
- QDECREF(ps->varE);
- QDECREF(ps->varF);
+ qobject_unref(ps->varE);
+ qobject_unref(ps->varF);
ps->varE = ps->varF = NULL;
}
@@ -539,6 +539,42 @@ static QString* psh_convert(struct PixelShader *ps)
qstring_append(preflight, "\n");
qstring_append(preflight, "uniform vec4 fogColor;\n");
+ /* Window Clipping */
+ QString *clip = qstring_new();
+ if (ps->state.window_clip_count != 0) {
+ qstring_append_fmt(preflight, "uniform ivec4 clipRegion[%d];\n",
+ ps->state.window_clip_count);
+ qstring_append_fmt(clip, "/* Window-clip (%s) */\n",
+ ps->state.window_clip_exclusive ?
+ "Exclusive" : "Inclusive");
+ if (!ps->state.window_clip_exclusive) {
+ qstring_append(clip, "bool clipContained = false;\n");
+ }
+ qstring_append_fmt(clip, "for (int i = 0; i < %d; i++) {\n",
+ ps->state.window_clip_count);
+ qstring_append(clip, " bvec4 clipTest = bvec4(lessThan(gl_FragCoord.xy, clipRegion[i].xy),\n"
+ " greaterThan(gl_FragCoord.xy, clipRegion[i].zw));\n"
+ " if (!any(clipTest)) {\n");
+ if (ps->state.window_clip_exclusive) {
+ /* Pixel in clip region = exclude by discarding */
+ qstring_append(clip, " discard;\n");
+ assert(false); /* Untested */
+ } else {
+ /* Pixel in clip region = mark pixel as contained and leave */
+ qstring_append(clip, " clipContained = true;\n"
+ " break;\n");
+ }
+ qstring_append(clip, " }\n"
+ "}\n");
+ /* Check for inclusive window clip */
+ if (!ps->state.window_clip_exclusive) {
+ qstring_append(clip, "if (!clipContained) { discard; }\n");
+ }
+ } else if (ps->state.window_clip_exclusive) {
+ /* Clip everything */
+ qstring_append(clip, "discard;\n");
+ }
+
/* calculate perspective-correct inputs */
QString *vars = qstring_new();
qstring_append(vars, "vec4 pD0 = vtx.D0 / vtx.inv_w;\n");
@@ -746,14 +782,15 @@ static QString* psh_convert(struct PixelShader *ps)
qstring_append(final, "#version 330\n\n");
qstring_append(final, qstring_get_str(preflight));
qstring_append(final, "void main() {\n");
+ qstring_append(final, qstring_get_str(clip));
qstring_append(final, qstring_get_str(vars));
qstring_append(final, qstring_get_str(ps->code));
qstring_append(final, "fragColor = r0;\n");
qstring_append(final, "}\n");
- QDECREF(preflight);
- QDECREF(vars);
- QDECREF(ps->code);
+ qobject_unref(preflight);
+ qobject_unref(vars);
+ qobject_unref(ps->code);
return final;
}
diff --git a/src/devices/video/nv2a_psh.h b/src/devices/video/nv2a_psh.h
index 2be7eaa50..5355c8778 100644
--- a/src/devices/video/nv2a_psh.h
+++ b/src/devices/video/nv2a_psh.h
@@ -52,6 +52,9 @@ typedef struct PshState {
bool alpha_test;
enum PshAlphaFunc alpha_func;
+
+ bool window_clip_exclusive;
+ unsigned int window_clip_count;
} PshState;
QString *psh_translate(const PshState state);
diff --git a/src/devices/video/nv2a_regs.h b/src/devices/video/nv2a_regs.h
new file mode 100644
index 000000000..101e0beb6
--- /dev/null
+++ b/src/devices/video/nv2a_regs.h
@@ -0,0 +1,1833 @@
+// Source : https://github.com/xqemu/xqemu/blob/master/hw/xbox/nv2a_regs.h
+/*
+ * QEMU Geforce NV2A register definitions
+ *
+ * Copyright (c) 2012 espes
+ * Copyright (c) 2015 Jannik Vogel
+ * Copyright (c) 2018 Matt Borgerson
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see .
+ */
+
+#ifndef HW_NV2A_REGS_H
+#define HW_NV2A_REGS_H
+
+#define NV_NUM_BLOCKS 21
+#define NV_PMC 0 /* card master control */
+#define NV_PBUS 1 /* bus control */
+#define NV_PFIFO 2 /* MMIO and DMA FIFO submission to PGRAPH and VPE */
+#define NV_PFIFO_CACHE 3
+#define NV_PRMA 4 /* access to BAR0/BAR1 from real mode */
+#define NV_PVIDEO 5 /* video overlay */
+#define NV_PTIMER 6 /* time measurement and time-based alarms */
+#define NV_PCOUNTER 7 /* performance monitoring counters */
+#define NV_PVPE 8 /* MPEG2 decoding engine */
+#define NV_PTV 9 /* TV encoder */
+#define NV_PRMFB 10 /* aliases VGA memory window */
+#define NV_PRMVIO 11 /* aliases VGA sequencer and graphics controller registers */
+#define NV_PFB 12 /* memory interface */
+#define NV_PSTRAPS 13 /* straps readout / override */
+#define NV_PGRAPH 14 /* accelerated 2d/3d drawing engine */
+#define NV_PCRTC 15 /* more CRTC controls */
+#define NV_PRMCIO 16 /* aliases VGA CRTC and attribute controller registers */
+#define NV_PRAMDAC 17 /* RAMDAC, cursor, and PLL control */
+#define NV_PRMDIO 18 /* aliases VGA palette registers */
+#define NV_PRAMIN 19 /* RAMIN access */
+#define NV_USER 20 /* PFIFO MMIO and DMA submission area */
+
+#define NV_PMC_BOOT_0 0x00000000
+#define NV_PMC_BOOT_1 0x00000004
+#define NV_PMC_INTR_0 0x00000100
+# define NV_PMC_INTR_0_PFIFO (1 << 8)
+# define NV_PMC_INTR_0_PGRAPH (1 << 12)
+# define NV_PMC_INTR_0_PVIDEO (1 << 16)
+# define NV_PMC_INTR_0_PTIMER (1 << 20)
+# define NV_PMC_INTR_0_PCRTC (1 << 24)
+# define NV_PMC_INTR_0_PCRTC2 (1 << 25)
+# define NV_PMC_INTR_0_PBUS (1 << 28)
+# define NV_PMC_INTR_0_SOFTWARE (1 << 31)
+#define NV_PMC_INTR_EN_0 0x00000140
+# define NV_PMC_INTR_EN_0_HARDWARE 1
+# define NV_PMC_INTR_EN_0_SOFTWARE 2
+#define NV_PMC_ENABLE 0x00000200
+# define NV_PMC_ENABLE_PFIFO (1 << 8)
+# define NV_PMC_ENABLE_PGRAPH (1 << 12)
+# define NV_PMC_ENABLE_PFB (1 << 20)
+# define NV_PMC_ENABLE_PCRTC (1 << 24)
+# define NV_PMC_ENABLE_PCRTC2 (1 << 25)
+# define NV_PMC_ENABLE_PVIDEO (1 << 28)
+
+
+#define NV_PBUS_FBIO_RAM 0x00000218
+# define NV_PBUS_FBIO_RAM_TYPE 0x00000100
+# define NV_PBUS_FBIO_RAM_TYPE_DDR (0 << 8)
+# define NV_PBUS_FBIO_RAM_TYPE_SDR (1 << 8)
+/* These map approximately to the pci registers */
+#define NV_PBUS_PCI_NV_0 0x00000800
+# define NV_PBUS_PCI_NV_0_VENDOR_ID 0x0000FFFF
+# define NV_CONFIG_PCI_NV_0_DEVICE_ID 0xFFFF0000
+#define NV_PBUS_PCI_NV_1 0x00000804
+#define NV_PBUS_PCI_NV_2 0x00000808
+# define NV_PBUS_PCI_NV_2_REVISION_ID 0x000000FF
+# define NV_PBUS_PCI_NV_2_CLASS_CODE 0xFFFFFF00
+#define NV_PBUS_PCI_NV_3 0x0000080C
+#define NV_PBUS_PCI_NV_4 0x00000810
+#define NV_PBUS_PCI_NV_5 0x00000814
+#define NV_PBUS_PCI_NV_6 0x00000818
+#define NV_PBUS_PCI_NV_7 0x0000081C
+#define NV_PBUS_PCI_NV_11 0x0000082C
+#define NV_PBUS_PCI_NV_12 0x00000830
+#define NV_PBUS_PCI_NV_13 0x00000834
+#define NV_PBUS_PCI_NV_14 0x00000838
+#define NV_PBUS_PCI_NV_15 0x0000083C
+#define NV_PBUS_PCI_NV_16 0x00000840
+#define NV_PBUS_PCI_NV_17 0x00000844
+#define NV_PBUS_PCI_NV_18 0x00000848
+#define NV_PBUS_PCI_NV_19 0x0000084C
+#define NV_PBUS_PCI_NV_20 0x00000850
+#define NV_PBUS_PCI_NV_21 0x00000854
+#define NV_PBUS_PCI_NV_22 0x00000858
+#define NV_PBUS_PCI_NV_23 0x0000085C
+#define NV_PBUS_PCI_NV_24 0x00000860
+#define NV_PBUS_PCI_NV_25 0x00000864
+#define NV_PBUS_PCI_NV_26 0x00000868
+
+
+#define NV_PFIFO_DELAY_0 0x00000040
+#define NV_PFIFO_DMA_TIMESLICE 0x00000044
+#define NV_PFIFO_TIMESLICE 0x0000004C
+#define NV_PFIFO_INTR_0 0x00000100
+# define NV_PFIFO_INTR_0_CACHE_ERROR (1 << 0)
+# define NV_PFIFO_INTR_0_RUNOUT (1 << 4)
+# define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW (1 << 8)
+# define NV_PFIFO_INTR_0_DMA_PUSHER (1 << 12)
+# define NV_PFIFO_INTR_0_DMA_PT (1 << 16)
+# define NV_PFIFO_INTR_0_SEMAPHORE (1 << 20)
+# define NV_PFIFO_INTR_0_ACQUIRE_TIMEOUT (1 << 24)
+#define NV_PFIFO_INTR_EN_0 0x00000140
+# define NV_PFIFO_INTR_EN_0_CACHE_ERROR (1 << 0)
+# define NV_PFIFO_INTR_EN_0_RUNOUT (1 << 4)
+# define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW (1 << 8)
+# define NV_PFIFO_INTR_EN_0_DMA_PUSHER (1 << 12)
+# define NV_PFIFO_INTR_EN_0_DMA_PT (1 << 16)
+# define NV_PFIFO_INTR_EN_0_SEMAPHORE (1 << 20)
+# define NV_PFIFO_INTR_EN_0_ACQUIRE_TIMEOUT (1 << 24)
+#define NV_PFIFO_RAMHT 0x00000210
+//# define NV_PFIFO_RAMHT_BASE_ADDRESS 0x000001F0
+# define NV_PFIFO_RAMHT_BASE_ADDRESS_MASK 0x000001F0
+# define NV_PFIFO_RAMHT_BASE_ADDRESS_SHIFT 4
+# define NV_PFIFO_RAMHT_BASE_ADDRESS_MOVE 12
+//# define NV_PFIFO_RAMHT_SIZE 0x00030000
+# define NV_PFIFO_RAMHT_SIZE_MASK 0x00030000
+# define NV_PFIFO_RAMHT_SIZE_SHIFT 16
+# define NV_PFIFO_RAMHT_SIZE_4K 0
+# define NV_PFIFO_RAMHT_SIZE_8K 1
+# define NV_PFIFO_RAMHT_SIZE_16K 2
+# define NV_PFIFO_RAMHT_SIZE_32K 3
+//# define NV_PFIFO_RAMHT_SEARCH 0x03000000
+# define NV_PFIFO_RAMHT_SEARCH_MASK 0x03000000
+# define NV_PFIFO_RAMHT_SEARCH_SHIFT 24
+# define NV_PFIFO_RAMHT_SEARCH_16 0
+# define NV_PFIFO_RAMHT_SEARCH_32 1
+# define NV_PFIFO_RAMHT_SEARCH_64 2
+# define NV_PFIFO_RAMHT_SEARCH_128 3
+#define NV_PFIFO_RAMFC 0x00000214
+//# define NV_PFIFO_RAMFC_BASE_ADDRESS1 0x000001FC
+# define NV_PFIFO_RAMFC_BASE_ADDRESS1_MASK 0x000001FC
+# define NV_PFIFO_RAMFC_BASE_ADDRESS1_SHIFT 2
+# define NV_PFIFO_RAMFC_BASE_ADDRESS1_MOVE 10
+//# define NV_PFIFO_RAMFC_SIZE 0x00010000
+# define NV_PFIFO_RAMFC_SIZE_MASK 0x00010000
+# define NV_PFIFO_RAMFC_SIZE_1K 0x00000000
+# define NV_PFIFO_RAMFC_SIZE_2K 0x00010000
+//# define NV_PFIFO_RAMFC_BASE_ADDRESS2 0x00FE0000
+# define NV_PFIFO_RAMFC_BASE_ADDRESS2_MASK 0x00FE0000
+# define NV_PFIFO_RAMFC_BASE_ADDRESS2_SHIFT 17
+# define NV_PFIFO_RAMFC_BASE_ADDRESS2_MOVE 10
+#define NV_PFIFO_RAMRO 0x00000218
+# define NV_PFIFO_RAMRO_BASE_ADDRESS 0x000001FE
+# define NV_PFIFO_RAMRO_SIZE 0x00010000
+#define NV_PFIFO_RUNOUT_STATUS 0x00000400
+# define NV_PFIFO_RUNOUT_STATUS_RANOUT (1 << 0)
+# define NV_PFIFO_RUNOUT_STATUS_LOW_MARK (1 << 4)
+# define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK (1 << 8)
+#define NV_PFIFO_RUNOUT_PUT_ADDRESS 0x00000410
+#define NV_PFIFO_RUNOUT_GET_ADDRESS 0x00000420
+#define NV_PFIFO_CACHES 0x00000500
+#define NV_PFIFO_MODE 0x00000504
+#define NV_PFIFO_DMA 0x00000508
+#define NV_PFIFO_SIZE 0x0000050C
+#define NV_PFIFO_CACHE0_PUSH0 0x00001000
+#define NV_PFIFO_CACHE0_PULL0 0x00001050
+#define NV_PFIFO_CACHE0_HASH 0x00001058
+#define NV_PFIFO_CACHE1_PUSH0 0x00001200
+# define NV_PFIFO_CACHE1_PUSH0_ACCESS (1 << 0)
+#define NV_PFIFO_CACHE1_PUSH1 0x00001204
+# define NV_PFIFO_CACHE1_PUSH1_CHID 0x0000001F
+# define NV_PFIFO_CACHE1_PUSH1_MODE 0x00000100
+# define NV_PFIFO_CACHE1_PUSH1_MODE_PIO 0
+# define NV_PFIFO_CACHE1_PUSH1_MODE_DMA 1
+#define NV_PFIFO_CACHE1_PUT 0x00001210
+#define NV_PFIFO_CACHE1_STATUS 0x00001214
+# define NV_PFIFO_CACHE1_STATUS_LOW_MARK (1 << 4)
+# define NV_PFIFO_CACHE1_STATUS_HIGH_MARK (1 << 8)
+#define NV_PFIFO_CACHE1_DMA_PUSH 0x00001220
+# define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS (1 << 0)
+# define NV_PFIFO_CACHE1_DMA_PUSH_STATE (1 << 4)
+# define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER (1 << 8)
+# define NV_PFIFO_CACHE1_DMA_PUSH_STATUS (1 << 12)
+# define NV_PFIFO_CACHE1_DMA_PUSH_ACQUIRE (1 << 16)
+#define NV_PFIFO_CACHE1_DMA_FETCH 0x00001224
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG 0x000000F8
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000
+#define NV_PFIFO_CACHE1_DMA_STATE 0x00001228
+# define NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE (1 << 0)
+# define NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_INC 0
+# define NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_NON_INC 1
+# define NV_PFIFO_CACHE1_DMA_STATE_METHOD 0x00001FFC
+# define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 0x0000E000
+# define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 0x1FFC0000
+# define NV_PFIFO_CACHE1_DMA_STATE_ERROR 0xE0000000
+# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0
+# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_CALL 1
+# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 2
+# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RETURN 3
+# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 4
+# define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 6
+#define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000122C
+//# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 0x0000FFFF
+# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MASK 0x0000FFFF
+# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_SHIFT 0
+# define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS_MOVE 4
+#define NV_PFIFO_CACHE1_DMA_CTL 0x00001230
+#define NV_PFIFO_CACHE1_DMA_PUT 0x00001240
+#define NV_PFIFO_CACHE1_DMA_GET 0x00001244
+#define NV_PFIFO_CACHE1_REF 0x00001248
+#define NV_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000124C
+# define NV_PFIFO_CACHE1_DMA_SUBROUTINE_RETURN_OFFSET 0x1FFFFFFC
+# define NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE (1 << 0)
+#define NV_PFIFO_CACHE1_PULL0 0x00001250
+# define NV_PFIFO_CACHE1_PULL0_ACCESS (1 << 0)
+#define NV_PFIFO_CACHE1_PULL1 0x00001254
+# define NV_PFIFO_CACHE1_PULL1_ENGINE 0x00000003
+#define NV_PFIFO_CACHE1_HASH 0x00001258
+#define NV_PFIFO_CACHE1_ACQUIRE_0 0x00001260
+#define NV_PFIFO_CACHE1_ACQUIRE_1 0x00001264
+#define NV_PFIFO_CACHE1_ACQUIRE_2 0x00001268
+#define NV_PFIFO_CACHE1_SEMAPHORE 0x0000126C
+#define NV_PFIFO_CACHE1_GET 0x00001270
+#define NV_PFIFO_CACHE1_ENGINE 0x00001280
+#define NV_PFIFO_CACHE1_DMA_DCOUNT 0x000012A0
+# define NV_PFIFO_CACHE1_DMA_DCOUNT_VALUE 0x00001FFC
+#define NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW 0x000012A4
+# define NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW_OFFSET 0x1FFFFFFC
+#define NV_PFIFO_CACHE1_DMA_RSVD_SHADOW 0x000012A8
+#define NV_PFIFO_CACHE1_DMA_DATA_SHADOW 0x000012AC
+#define NV_PFIFO_CACHE1_METHOD 0x00001800
+# define NV_PFIFO_CACHE1_METHOD_TYPE (1 << 0)
+# define NV_PFIFO_CACHE1_METHOD_ADDRESS 0x00001FFC
+# define NV_PFIFO_CACHE1_METHOD_SUBCHANNEL 0x0000E000
+#define NV_PFIFO_CACHE1_DATA 0x00001804
+
+
+#define NV_PGRAPH_DEBUG_0 0x00000080
+#define NV_PGRAPH_DEBUG_1 0x00000084
+#define NV_PGRAPH_DEBUG_3 0x0000008C
+# define NV_PGRAPH_DEBUG_3_HW_CONTEXT_SWITCH (1 << 2)
+#define NV_PGRAPH_DEBUG_4 0x00000090
+#define NV_PGRAPH_DEBUG_5 0x00000094
+#define NV_PGRAPH_DEBUG_8 0x00000098
+#define NV_PGRAPH_DEBUG_9 0x0000009C
+#define NV_PGRAPH_INTR 0x00000100
+# define NV_PGRAPH_INTR_NOTIFY (1 << 0)
+# define NV_PGRAPH_INTR_MISSING_HW (1 << 4)
+# define NV_PGRAPH_INTR_TLB_PRESENT_DMA_R (1 << 6)
+# define NV_PGRAPH_INTR_TLB_PRESENT_DMA_W (1 << 7)
+# define NV_PGRAPH_INTR_TLB_PRESENT_TEX_A (1 << 8)
+# define NV_PGRAPH_INTR_TLB_PRESENT_TEX_B (1 << 9)
+# define NV_PGRAPH_INTR_TLB_PRESENT_VTX (1 << 10)
+# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1 << 12)
+# define NV_PGRAPH_INTR_STATE3D (1 << 13)
+# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1 << 16)
+# define NV_PGRAPH_INTR_ERROR (1 << 20)
+# define NV_PGRAPH_INTR_SINGLE_STEP (1 << 24)
+#define NV_PGRAPH_NSOURCE 0x00000108
+# define NV_PGRAPH_NSOURCE_NOTIFICATION (1 << 0)
+#define NV_PGRAPH_INTR_EN 0x00000140
+# define NV_PGRAPH_INTR_EN_NOTIFY (1 << 0)
+# define NV_PGRAPH_INTR_EN_MISSING_HW (1 << 4)
+# define NV_PGRAPH_INTR_EN_TLB_PRESENT_DMA_R (1 << 6)
+# define NV_PGRAPH_INTR_EN_TLB_PRESENT_DMA_W (1 << 7)
+# define NV_PGRAPH_INTR_EN_TLB_PRESENT_TEX_A (1 << 8)
+# define NV_PGRAPH_INTR_EN_TLB_PRESENT_TEX_B (1 << 9)
+# define NV_PGRAPH_INTR_EN_TLB_PRESENT_VTX (1 << 10)
+# define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH (1 << 12)
+# define NV_PGRAPH_INTR_EN_STATE3D (1 << 13)
+# define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY (1 << 16)
+# define NV_PGRAPH_INTR_EN_ERROR (1 << 20)
+# define NV_PGRAPH_INTR_EN_SINGLE_STEP (1 << 24)
+#define NV_PGRAPH_CTX_CONTROL 0x00000144
+# define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 0x00000003
+# define NV_PGRAPH_CTX_CONTROL_TIME (1 << 8)
+# define NV_PGRAPH_CTX_CONTROL_CHID (1 << 16)
+# define NV_PGRAPH_CTX_CONTROL_CHANGE (1 << 20)
+# define NV_PGRAPH_CTX_CONTROL_SWITCHING (1 << 24)
+# define NV_PGRAPH_CTX_CONTROL_DEVICE (1 << 28)
+#define NV_PGRAPH_CTX_USER 0x00000148
+# define NV_PGRAPH_CTX_USER_CHANNEL_3D (1 << 0)
+# define NV_PGRAPH_CTX_USER_CHANNEL_3D_VALID (1 << 4)
+# define NV_PGRAPH_CTX_USER_SUBCH 0x0000E000
+# define NV_PGRAPH_CTX_USER_CHID 0x1F000000
+# define NV_PGRAPH_CTX_USER_SINGLE_STEP (1 << 31)
+#define NV_PGRAPH_CTX_SWITCH1 0x0000014C
+# define NV_PGRAPH_CTX_SWITCH1_GRCLASS 0x000000FF
+# define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY (1 << 12)
+# define NV_PGRAPH_CTX_SWITCH1_SWIZZLE (1 << 14)
+# define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 0x00038000
+# define NV_PGRAPH_CTX_SWITCH1_SYNCHRONIZE (1 << 18)
+# define NV_PGRAPH_CTX_SWITCH1_ENDIAN_MODE (1 << 19)
+# define NV_PGRAPH_CTX_SWITCH1_CLASS_TYPE (1 << 22)
+# define NV_PGRAPH_CTX_SWITCH1_SINGLE_STEP (1 << 23)
+# define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS (1 << 24)
+# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE0 (1 << 25)
+# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE1 (1 << 26)
+# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_PATTERN (1 << 27)
+# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_ROP (1 << 28)
+# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA1 (1 << 29)
+# define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA4 (1 << 30)
+# define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET (1 << 31)
+#define NV_PGRAPH_CTX_SWITCH2 0x00000150
+#define NV_PGRAPH_CTX_SWITCH3 0x00000154
+#define NV_PGRAPH_CTX_SWITCH4 0x00000158
+# define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE 0x0000FFFF
+#define NV_PGRAPH_CTX_SWITCH5 0x0000015C
+#define NV_PGRAPH_CTX_CACHE1 0x00000160
+#define NV_PGRAPH_CTX_CACHE2 0x00000180
+#define NV_PGRAPH_CTX_CACHE3 0x000001A0
+#define NV_PGRAPH_CTX_CACHE4 0x000001C0
+#define NV_PGRAPH_CTX_CACHE5 0x000001E0
+#define NV_PGRAPH_STATUS 0x00000700
+#define NV_PGRAPH_TRAPPED_ADDR 0x00000704
+# define NV_PGRAPH_TRAPPED_ADDR_MTHD 0x00001FFF
+# define NV_PGRAPH_TRAPPED_ADDR_SUBCH 0x00070000
+# define NV_PGRAPH_TRAPPED_ADDR_CHID 0x01F00000
+# define NV_PGRAPH_TRAPPED_ADDR_DHV 0x10000000
+#define NV_PGRAPH_TRAPPED_DATA_LOW 0x00000708
+#define NV_PGRAPH_SURFACE 0x00000710
+# define NV_PGRAPH_SURFACE_WRITE_3D 0x00700000
+# define NV_PGRAPH_SURFACE_READ_3D 0x07000000
+# define NV_PGRAPH_SURFACE_MODULO_3D 0x70000000
+#define NV_PGRAPH_INCREMENT 0x0000071C
+# define NV_PGRAPH_INCREMENT_READ_BLIT (1 << 0)
+# define NV_PGRAPH_INCREMENT_READ_3D (1 << 1)
+#define NV_PGRAPH_FIFO 0x00000720
+# define NV_PGRAPH_FIFO_ACCESS (1 << 0)
+#define NV_PGRAPH_RDI_INDEX 0x00000750
+#define NV_PGRAPH_RDI_DATA 0x00000754
+#define NV_PGRAPH_FFINTFC_ST2 0x00000764
+#define NV_PGRAPH_CHANNEL_CTX_TABLE 0x00000780
+# define NV_PGRAPH_CHANNEL_CTX_TABLE_INST 0x0000FFFF
+#define NV_PGRAPH_CHANNEL_CTX_POINTER 0x00000784
+# define NV_PGRAPH_CHANNEL_CTX_POINTER_INST 0x0000FFFF
+#define NV_PGRAPH_CHANNEL_CTX_TRIGGER 0x00000788
+# define NV_PGRAPH_CHANNEL_CTX_TRIGGER_READ_IN (1 << 0)
+# define NV_PGRAPH_CHANNEL_CTX_TRIGGER_WRITE_OUT (1 << 1)
+#define NV_PGRAPH_DEBUG_2 0x00000880
+#define NV_PGRAPH_TTILE(i) 0x00000900 + (i * 0x10)
+#define NV_PGRAPH_TLIMIT(i) 0x00000904 + (i * 0x10)
+#define NV_PGRAPH_TSIZE(i) 0x00000908 + (i * 0x10)
+#define NV_PGRAPH_TSTATUS(i) 0x0000090C + (i * 0x10)
+#define NV_PGRAPH_ZCOMP(i) 0x00000980 + (i * 4)
+#define NV_PGRAPH_ZCOMP_OFFSET 0x000009A0
+#define NV_PGRAPH_FBCFG0 0x000009A4
+#define NV_PGRAPH_FBCFG1 0x000009A8
+#define NV_PGRAPH_PATT_COLOR0 0x00000B10
+#define NV_PGRAPH_DEBUG_6 0x00000B80
+#define NV_PGRAPH_DEBUG_7 0x00000B84
+#define NV_PGRAPH_DEBUG_10 0x00000B88
+#define NV_PGRAPH_CSV0_D 0x00000FB4
+# define NV_PGRAPH_CSV0_D_LIGHTS 0x0000FFFF
+# define NV_PGRAPH_CSV0_D_LIGHT0 0x00000003
+# define NV_PGRAPH_CSV0_D_LIGHT0_OFF 0
+# define NV_PGRAPH_CSV0_D_LIGHT0_INFINITE 1
+# define NV_PGRAPH_CSV0_D_LIGHT0_LOCAL 2
+# define NV_PGRAPH_CSV0_D_LIGHT0_SPOT 3
+# define NV_PGRAPH_CSV0_D_RANGE_MODE (1 << 18)
+# define NV_PGRAPH_CSV0_D_FOGENABLE (1 << 19)
+# define NV_PGRAPH_CSV0_D_TEXGEN_REF (1 << 20)
+# define NV_PGRAPH_CSV0_D_TEXGEN_REF_LOCAL_VIEWER 0
+# define NV_PGRAPH_CSV0_D_TEXGEN_REF_INFINITE_VIEWER 1
+# define NV_PGRAPH_CSV0_D_FOG_MODE (1 << 21)
+# define NV_PGRAPH_CSV0_D_FOG_MODE_LINEAR 0
+# define NV_PGRAPH_CSV0_D_FOG_MODE_EXP 1
+# define NV_PGRAPH_CSV0_D_FOGGENMODE 0x01C00000
+# define NV_PGRAPH_CSV0_D_FOGGENMODE_SPEC_ALPHA 0
+# define NV_PGRAPH_CSV0_D_FOGGENMODE_RADIAL 1
+# define NV_PGRAPH_CSV0_D_FOGGENMODE_PLANAR 2
+# define NV_PGRAPH_CSV0_D_FOGGENMODE_ABS_PLANAR 3
+# define NV_PGRAPH_CSV0_D_FOGGENMODE_FOG_X 4
+# define NV_PGRAPH_CSV0_D_MODE 0xC0000000
+# define NV_PGRAPH_CSV0_D_SKIN 0x1C000000
+# define NV_PGRAPH_CSV0_D_SKIN_OFF 0
+# define NV_PGRAPH_CSV0_D_SKIN_2G 1
+# define NV_PGRAPH_CSV0_D_SKIN_2 2
+# define NV_PGRAPH_CSV0_D_SKIN_3G 3
+# define NV_PGRAPH_CSV0_D_SKIN_3 4
+# define NV_PGRAPH_CSV0_D_SKIN_4G 5
+# define NV_PGRAPH_CSV0_D_SKIN_4 6
+#define NV_PGRAPH_CSV0_C 0x00000FB8
+# define NV_PGRAPH_CSV0_C_CHEOPS_PROGRAM_START 0x0000FF00
+# define NV_PGRAPH_CSV0_C_NORMALIZATION_ENABLE (1 << 27)
+# define NV_PGRAPH_CSV0_C_LIGHTING (1 << 31)
+#define NV_PGRAPH_CSV1_B 0x00000FBC
+#define NV_PGRAPH_CSV1_A 0x00000FC0
+# define NV_PGRAPH_CSV1_A_T0_ENABLE (1 << 0)
+# define NV_PGRAPH_CSV1_A_T0_MODE (1 << 1)
+# define NV_PGRAPH_CSV1_A_T0_TEXTURE (1 << 2)
+# define NV_PGRAPH_CSV1_A_T0_TEXTURE_2D 0
+# define NV_PGRAPH_CSV1_A_T0_TEXTURE_3D 1
+# define NV_PGRAPH_CSV1_A_T0_S 0x00000070
+# define NV_PGRAPH_CSV1_A_T0_S_DISABLE 0
+# define NV_PGRAPH_CSV1_A_T0_S_NORMAL_MAP 4
+# define NV_PGRAPH_CSV1_A_T0_S_REFLECTION_MAP 5
+# define NV_PGRAPH_CSV1_A_T0_S_EYE_LINEAR 1
+# define NV_PGRAPH_CSV1_A_T0_S_OBJECT_LINEAR 2
+# define NV_PGRAPH_CSV1_A_T0_S_SPHERE_MAP 3
+# define NV_PGRAPH_CSV1_A_T0_T 0x00000380
+# define NV_PGRAPH_CSV1_A_T0_R 0x00001C00
+# define NV_PGRAPH_CSV1_A_T0_Q 0x0000E000
+# define NV_PGRAPH_CSV1_A_T1_ENABLE (1 << 16)
+# define NV_PGRAPH_CSV1_A_T1_MODE (1 << 17)
+# define NV_PGRAPH_CSV1_A_T1_TEXTURE (1 << 18)
+# define NV_PGRAPH_CSV1_A_T1_S 0x00700000
+# define NV_PGRAPH_CSV1_A_T1_T 0x03800000
+# define NV_PGRAPH_CSV1_A_T1_R 0x1C000000
+# define NV_PGRAPH_CSV1_A_T1_Q 0xE0000000
+#define NV_PGRAPH_CHEOPS_OFFSET 0x00000FC4
+# define NV_PGRAPH_CHEOPS_OFFSET_PROG_LD_PTR 0x000000FF
+# define NV_PGRAPH_CHEOPS_OFFSET_CONST_LD_PTR 0x0000FF00
+#define NV_PGRAPH_DMA_STATE 0x00001034
+#define NV_PGRAPH_BLEND 0x00001804
+# define NV_PGRAPH_BLEND_EQN 0x00000007
+# define NV_PGRAPH_BLEND_EN (1 << 3)
+# define NV_PGRAPH_BLEND_SFACTOR 0x000000F0
+# define NV_PGRAPH_BLEND_SFACTOR_ZERO 0
+# define NV_PGRAPH_BLEND_SFACTOR_ONE 1
+# define NV_PGRAPH_BLEND_SFACTOR_SRC_COLOR 2
+# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_SRC_COLOR 3
+# define NV_PGRAPH_BLEND_SFACTOR_SRC_ALPHA 4
+# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_SRC_ALPHA 5
+# define NV_PGRAPH_BLEND_SFACTOR_DST_ALPHA 6
+# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_DST_ALPHA 7
+# define NV_PGRAPH_BLEND_SFACTOR_DST_COLOR 8
+# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_DST_COLOR 9
+# define NV_PGRAPH_BLEND_SFACTOR_SRC_ALPHA_SATURATE 10
+# define NV_PGRAPH_BLEND_SFACTOR_CONSTANT_COLOR 12
+# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_CONSTANT_COLOR 13
+# define NV_PGRAPH_BLEND_SFACTOR_CONSTANT_ALPHA 14
+# define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_CONSTANT_ALPHA 15
+# define NV_PGRAPH_BLEND_DFACTOR 0x00000F00
+# define NV_PGRAPH_BLEND_DFACTOR_ZERO 0
+# define NV_PGRAPH_BLEND_DFACTOR_ONE 1
+# define NV_PGRAPH_BLEND_DFACTOR_SRC_COLOR 2
+# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_SRC_COLOR 3
+# define NV_PGRAPH_BLEND_DFACTOR_SRC_ALPHA 4
+# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_SRC_ALPHA 5
+# define NV_PGRAPH_BLEND_DFACTOR_DST_ALPHA 6
+# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_DST_ALPHA 7
+# define NV_PGRAPH_BLEND_DFACTOR_DST_COLOR 8
+# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_DST_COLOR 9
+# define NV_PGRAPH_BLEND_DFACTOR_SRC_ALPHA_SATURATE 10
+# define NV_PGRAPH_BLEND_DFACTOR_CONSTANT_COLOR 12
+# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_CONSTANT_COLOR 13
+# define NV_PGRAPH_BLEND_DFACTOR_CONSTANT_ALPHA 14
+# define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_CONSTANT_ALPHA 15
+# define NV_PGRAPH_BLEND_LOGICOP_ENABLE (1 << 16)
+# define NV_PGRAPH_BLEND_LOGICOP 0x0000F000
+#define NV_PGRAPH_BLENDCOLOR 0x00001808
+#define NV_PGRAPH_BORDERCOLOR0 0x0000180C
+#define NV_PGRAPH_BORDERCOLOR1 0x00001810
+#define NV_PGRAPH_BORDERCOLOR2 0x00001814
+#define NV_PGRAPH_BORDERCOLOR3 0x00001818
+#define NV_PGRAPH_BUMPOFFSET1 0x0000184C
+#define NV_PGRAPH_BUMPSCALE1 0x00001858
+#define NV_PGRAPH_CLEARRECTX 0x00001864
+# define NV_PGRAPH_CLEARRECTX_XMIN 0x00000FFF
+# define NV_PGRAPH_CLEARRECTX_XMAX 0x0FFF0000
+#define NV_PGRAPH_CLEARRECTY 0x00001868
+# define NV_PGRAPH_CLEARRECTY_YMIN 0x00000FFF
+# define NV_PGRAPH_CLEARRECTY_YMAX 0x0FFF0000
+#define NV_PGRAPH_COLORCLEARVALUE 0x0000186C
+#define NV_PGRAPH_COMBINEFACTOR0 0x00001880
+#define NV_PGRAPH_COMBINEFACTOR1 0x000018A0
+#define NV_PGRAPH_COMBINEALPHAI0 0x000018C0
+#define NV_PGRAPH_COMBINEALPHAO0 0x000018E0
+#define NV_PGRAPH_COMBINECOLORI0 0x00001900
+#define NV_PGRAPH_COMBINECOLORO0 0x00001920
+#define NV_PGRAPH_COMBINECTL 0x00001940
+#define NV_PGRAPH_COMBINESPECFOG0 0x00001944
+#define NV_PGRAPH_COMBINESPECFOG1 0x00001948
+#define NV_PGRAPH_CONTROL_0 0x0000194C
+# define NV_PGRAPH_CONTROL_0_ALPHAREF 0x000000FF
+# define NV_PGRAPH_CONTROL_0_ALPHAFUNC 0x00000F00
+# define NV_PGRAPH_CONTROL_0_ALPHATESTENABLE (1 << 12)
+# define NV_PGRAPH_CONTROL_0_ZENABLE (1 << 14)
+# define NV_PGRAPH_CONTROL_0_ZFUNC 0x000F0000
+# define NV_PGRAPH_CONTROL_0_ZFUNC_NEVER 0
+# define NV_PGRAPH_CONTROL_0_ZFUNC_LESS 1
+# define NV_PGRAPH_CONTROL_0_ZFUNC_EQUAL 2
+# define NV_PGRAPH_CONTROL_0_ZFUNC_LEQUAL 3
+# define NV_PGRAPH_CONTROL_0_ZFUNC_GREATER 4
+# define NV_PGRAPH_CONTROL_0_ZFUNC_NOTEQUAL 5
+# define NV_PGRAPH_CONTROL_0_ZFUNC_GEQUAL 6
+# define NV_PGRAPH_CONTROL_0_ZFUNC_ALWAYS 7
+# define NV_PGRAPH_CONTROL_0_DITHERENABLE (1 << 22)
+# define NV_PGRAPH_CONTROL_0_Z_PERSPECTIVE_ENABLE (1 << 23)
+# define NV_PGRAPH_CONTROL_0_ZWRITEENABLE (1 << 24)
+# define NV_PGRAPH_CONTROL_0_STENCIL_WRITE_ENABLE (1 << 25)
+# define NV_PGRAPH_CONTROL_0_ALPHA_WRITE_ENABLE (1 << 26)
+# define NV_PGRAPH_CONTROL_0_RED_WRITE_ENABLE (1 << 27)
+# define NV_PGRAPH_CONTROL_0_GREEN_WRITE_ENABLE (1 << 28)
+# define NV_PGRAPH_CONTROL_0_BLUE_WRITE_ENABLE (1 << 29)
+# define NV_PGRAPH_CONTROL_0_CSCONVERT (3 << 30)
+#define NV_PGRAPH_CONTROL_1 0x00001950
+# define NV_PGRAPH_CONTROL_1_STENCIL_TEST_ENABLE (1 << 0)
+# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC 0x000000F0
+# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_NEVER 0
+# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_LESS 1
+# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_EQUAL 2
+# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_LEQUAL 3
+# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_GREATER 4
+# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_NOTEQUAL 5
+# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_GEQUAL 6
+# define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_ALWAYS 7
+# define NV_PGRAPH_CONTROL_1_STENCIL_REF 0x0000FF00
+# define NV_PGRAPH_CONTROL_1_STENCIL_MASK_READ 0x00FF0000
+# define NV_PGRAPH_CONTROL_1_STENCIL_MASK_WRITE 0xFF000000
+#define NV_PGRAPH_CONTROL_2 0x00001954
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL 0x0000000F
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL 0x000000F0
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS 0x00000F00
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_KEEP 1
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_ZERO 2
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_REPLACE 3
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_INCRSAT 4
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_DECRSAT 5
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_INVERT 6
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_INCR 7
+# define NV_PGRAPH_CONTROL_2_STENCIL_OP_V_DECR 8
+#define NV_PGRAPH_CONTROL_3 0x00001958
+# define NV_PGRAPH_CONTROL_3_FOGENABLE (1 << 8)
+# define NV_PGRAPH_CONTROL_3_FOG_MODE 0x00070000
+# define NV_PGRAPH_CONTROL_3_FOG_MODE_LINEAR 0
+# define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP 1
+# define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP2 3
+# define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP_ABS 5
+# define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP2_ABS 7
+# define NV_PGRAPH_CONTROL_3_FOG_MODE_LINEAR_ABS 4
+#define NV_PGRAPH_FOGCOLOR 0x00001980
+# define NV_PGRAPH_FOGCOLOR_RED 0x00FF0000
+# define NV_PGRAPH_FOGCOLOR_GREEN 0x0000FF00
+# define NV_PGRAPH_FOGCOLOR_BLUE 0x000000FF
+# define NV_PGRAPH_FOGCOLOR_ALPHA 0xFF000000
+#define NV_PGRAPH_FOGPARAM0 0x00001984
+#define NV_PGRAPH_FOGPARAM1 0x00001988
+#define NV_PGRAPH_SETUPRASTER 0x00001990
+# define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE 0x00000003
+# define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE_FILL 0
+# define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE_POINT 1
+# define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE_LINE 2
+# define NV_PGRAPH_SETUPRASTER_BACKFACEMODE 0x0000000C
+# define NV_PGRAPH_SETUPRASTER_POFFSETPOINTENABLE (1 << 6)
+# define NV_PGRAPH_SETUPRASTER_POFFSETLINEENABLE (1 << 7)
+# define NV_PGRAPH_SETUPRASTER_POFFSETFILLENABLE (1 << 8)
+# define NV_PGRAPH_SETUPRASTER_CULLCTRL 0x00600000
+# define NV_PGRAPH_SETUPRASTER_CULLCTRL_FRONT 1
+# define NV_PGRAPH_SETUPRASTER_CULLCTRL_BACK 2
+# define NV_PGRAPH_SETUPRASTER_CULLCTRL_FRONT_AND_BACK 3
+# define NV_PGRAPH_SETUPRASTER_FRONTFACE (1 << 23)
+# define NV_PGRAPH_SETUPRASTER_CULLENABLE (1 << 28)
+# define NV_PGRAPH_SETUPRASTER_Z_FORMAT (1 << 29)
+# define NV_PGRAPH_SETUPRASTER_WINDOWCLIPTYPE (1 << 31)
+#define NV_PGRAPH_SHADERCLIPMODE 0x00001994
+#define NV_PGRAPH_SHADERCTL 0x00001998
+#define NV_PGRAPH_SHADERPROG 0x0000199C
+#define NV_PGRAPH_SEMAPHOREOFFSET 0x000019A0
+#define NV_PGRAPH_SHADOWZSLOPETHRESHOLD 0x000019A8
+#define NV_PGRAPH_SPECFOGFACTOR0 0x000019AC
+#define NV_PGRAPH_SPECFOGFACTOR1 0x000019B0
+#define NV_PGRAPH_TEXADDRESS0 0x000019BC
+# define NV_PGRAPH_TEXADDRESS0_ADDRU 0x00000007
+# define NV_PGRAPH_TEXADDRESS0_ADDRU_WRAP 1
+# define NV_PGRAPH_TEXADDRESS0_ADDRU_MIRROR 2
+# define NV_PGRAPH_TEXADDRESS0_ADDRU_CLAMP_TO_EDGE 3
+# define NV_PGRAPH_TEXADDRESS0_ADDRU_BORDER 4
+# define NV_PGRAPH_TEXADDRESS0_ADDRU_CLAMP_OGL 5
+# define NV_PGRAPH_TEXADDRESS0_WRAP_U (1 << 4)
+# define NV_PGRAPH_TEXADDRESS0_ADDRV 0x00000700
+# define NV_PGRAPH_TEXADDRESS0_WRAP_V (1 << 12)
+# define NV_PGRAPH_TEXADDRESS0_ADDRP 0x00070000
+# define NV_PGRAPH_TEXADDRESS0_WRAP_P (1 << 20)
+# define NV_PGRAPH_TEXADDRESS0_WRAP_Q (1 << 24)
+#define NV_PGRAPH_TEXADDRESS1 0x000019C0
+#define NV_PGRAPH_TEXADDRESS2 0x000019C4
+#define NV_PGRAPH_TEXADDRESS3 0x000019C8
+#define NV_PGRAPH_TEXCTL0_0 0x000019CC
+# define NV_PGRAPH_TEXCTL0_0_ALPHAKILLEN (1 << 2)
+# define NV_PGRAPH_TEXCTL0_0_MAX_LOD_CLAMP 0x0003FFC0
+# define NV_PGRAPH_TEXCTL0_0_MIN_LOD_CLAMP 0x3FFC0000
+# define NV_PGRAPH_TEXCTL0_0_ENABLE (1 << 30)
+#define NV_PGRAPH_TEXCTL0_1 0x000019D0
+#define NV_PGRAPH_TEXCTL0_2 0x000019D4
+#define NV_PGRAPH_TEXCTL0_3 0x000019D8
+#define NV_PGRAPH_TEXCTL1_0 0x000019DC
+# define NV_PGRAPH_TEXCTL1_0_IMAGE_PITCH 0xFFFF0000
+#define NV_PGRAPH_TEXCTL1_1 0x000019E0
+#define NV_PGRAPH_TEXCTL1_2 0x000019E4
+#define NV_PGRAPH_TEXCTL1_3 0x000019E8
+#define NV_PGRAPH_TEXCTL2_0 0x000019EC
+#define NV_PGRAPH_TEXCTL2_1 0x000019F0
+#define NV_PGRAPH_TEXFILTER0 0x000019F4
+# define NV_PGRAPH_TEXFILTER0_MIPMAP_LOD_BIAS 0x00001FFF
+# define NV_PGRAPH_TEXFILTER0_MIN 0x003F0000
+# define NV_PGRAPH_TEXFILTER0_MIN_BOX_LOD0 1
+# define NV_PGRAPH_TEXFILTER0_MIN_TENT_LOD0 2
+# define NV_PGRAPH_TEXFILTER0_MIN_BOX_NEARESTLOD 3
+# define NV_PGRAPH_TEXFILTER0_MIN_TENT_NEARESTLOD 4
+# define NV_PGRAPH_TEXFILTER0_MIN_BOX_TENT_LOD 5
+# define NV_PGRAPH_TEXFILTER0_MIN_TENT_TENT_LOD 6
+# define NV_PGRAPH_TEXFILTER0_MIN_CONVOLUTION_2D_LOD0 7
+# define NV_PGRAPH_TEXFILTER0_MAG 0x0F000000
+# define NV_PGRAPH_TEXFILTER0_ASIGNED (1 << 28)
+# define NV_PGRAPH_TEXFILTER0_RSIGNED (1 << 29)
+# define NV_PGRAPH_TEXFILTER0_GSIGNED (1 << 30)
+# define NV_PGRAPH_TEXFILTER0_BSIGNED (1 << 31)
+#define NV_PGRAPH_TEXFILTER1 0x000019F8
+#define NV_PGRAPH_TEXFILTER2 0x000019FC
+#define NV_PGRAPH_TEXFILTER3 0x00001A00
+#define NV_PGRAPH_TEXFMT0 0x00001A04
+# define NV_PGRAPH_TEXFMT0_CONTEXT_DMA (1 << 1)
+# define NV_PGRAPH_TEXFMT0_CUBEMAPENABLE (1 << 2)
+# define NV_PGRAPH_TEXFMT0_BORDER_SOURCE (1 << 3)
+# define NV_PGRAPH_TEXFMT0_BORDER_SOURCE_TEXTURE 0
+# define NV_PGRAPH_TEXFMT0_BORDER_SOURCE_COLOR 1
+# define NV_PGRAPH_TEXFMT0_DIMENSIONALITY 0x000000C0
+# define NV_PGRAPH_TEXFMT0_COLOR 0x00007F00
+# define NV_PGRAPH_TEXFMT0_MIPMAP_LEVELS 0x000F0000
+# define NV_PGRAPH_TEXFMT0_BASE_SIZE_U 0x00F00000
+# define NV_PGRAPH_TEXFMT0_BASE_SIZE_V 0x0F000000
+# define NV_PGRAPH_TEXFMT0_BASE_SIZE_P 0xF0000000
+#define NV_PGRAPH_TEXFMT1 0x00001A08
+#define NV_PGRAPH_TEXFMT2 0x00001A0C
+#define NV_PGRAPH_TEXFMT3 0x00001A10
+#define NV_PGRAPH_TEXIMAGERECT0 0x00001A14
+# define NV_PGRAPH_TEXIMAGERECT0_WIDTH 0x1FFF0000
+# define NV_PGRAPH_TEXIMAGERECT0_HEIGHT 0x00001FFF
+#define NV_PGRAPH_TEXIMAGERECT1 0x00001A18
+#define NV_PGRAPH_TEXIMAGERECT2 0x00001A1C
+#define NV_PGRAPH_TEXIMAGERECT3 0x00001A20
+#define NV_PGRAPH_TEXOFFSET0 0x00001A24
+#define NV_PGRAPH_TEXOFFSET1 0x00001A28
+#define NV_PGRAPH_TEXOFFSET2 0x00001A2C
+#define NV_PGRAPH_TEXOFFSET3 0x00001A30
+#define NV_PGRAPH_TEXPALETTE0 0x00001A34
+# define NV_PGRAPH_TEXPALETTE0_CONTEXT_DMA (1 << 0)
+# define NV_PGRAPH_TEXPALETTE0_LENGTH 0x0000000C
+# define NV_PGRAPH_TEXPALETTE0_LENGTH_256 0
+# define NV_PGRAPH_TEXPALETTE0_LENGTH_128 1
+# define NV_PGRAPH_TEXPALETTE0_LENGTH_64 2
+# define NV_PGRAPH_TEXPALETTE0_LENGTH_32 3
+# define NV_PGRAPH_TEXPALETTE0_OFFSET 0xFFFFFFC0
+#define NV_PGRAPH_TEXPALETTE1 0x00001A38
+#define NV_PGRAPH_TEXPALETTE2 0x00001A3C
+#define NV_PGRAPH_TEXPALETTE3 0x00001A40
+#define NV_PGRAPH_WINDOWCLIPX0 0x00001A44
+# define NV_PGRAPH_WINDOWCLIPX0_XMIN 0x00000FFF
+# define NV_PGRAPH_WINDOWCLIPX0_XMAX 0x0FFF0000
+#define NV_PGRAPH_WINDOWCLIPX1 0x00001A48
+#define NV_PGRAPH_WINDOWCLIPX2 0x00001A4C
+#define NV_PGRAPH_WINDOWCLIPX3 0x00001A50
+#define NV_PGRAPH_WINDOWCLIPX4 0x00001A54
+#define NV_PGRAPH_WINDOWCLIPX5 0x00001A58
+#define NV_PGRAPH_WINDOWCLIPX6 0x00001A5C
+#define NV_PGRAPH_WINDOWCLIPX7 0x00001A60
+#define NV_PGRAPH_WINDOWCLIPY0 0x00001A64
+# define NV_PGRAPH_WINDOWCLIPY0_YMIN 0x00000FFF
+# define NV_PGRAPH_WINDOWCLIPY0_YMAX 0x0FFF0000
+#define NV_PGRAPH_WINDOWCLIPY1 0x00001A68
+#define NV_PGRAPH_WINDOWCLIPY2 0x00001A6C
+#define NV_PGRAPH_WINDOWCLIPY3 0x00001A70
+#define NV_PGRAPH_WINDOWCLIPY4 0x00001A74
+#define NV_PGRAPH_WINDOWCLIPY5 0x00001A78
+#define NV_PGRAPH_WINDOWCLIPY6 0x00001A7C
+#define NV_PGRAPH_WINDOWCLIPY7 0x00001A80
+#define NV_PGRAPH_ZSTENCILCLEARVALUE 0x00001A88
+#define NV_PGRAPH_ZCLIPMIN 0x00001A90
+#define NV_PGRAPH_ZOFFSETBIAS 0x00001AA4
+#define NV_PGRAPH_ZOFFSETFACTOR 0x00001AA8
+#define NV_PGRAPH_EYEVEC0 0x00001AAC
+#define NV_PGRAPH_EYEVEC1 0x00001AB0
+#define NV_PGRAPH_EYEVEC2 0x00001AB4
+#define NV_PGRAPH_ZCLIPMAX 0x00001ABC
+
+
+#define NV_PCRTC_INTR_0 0x00000100
+# define NV_PCRTC_INTR_0_VBLANK (1 << 0)
+#define NV_PCRTC_INTR_EN_0 0x00000140
+# define NV_PCRTC_INTR_EN_0_VBLANK (1 << 0)
+#define NV_PCRTC_START 0x00000800
+#define NV_PCRTC_CONFIG 0x00000804
+
+
+#define NV_PVIDEO_DEBUG_2 0x00000088
+#define NV_PVIDEO_DEBUG_3 0x0000008C
+#define NV_PVIDEO_INTR 0x00000100
+# define NV_PVIDEO_INTR_BUFFER_0 (1 << 0)
+# define NV_PVIDEO_INTR_BUFFER_1 (1 << 4)
+#define NV_PVIDEO_INTR_EN 0x00000140
+# define NV_PVIDEO_INTR_EN_BUFFER_0 (1 << 0)
+# define NV_PVIDEO_INTR_EN_BUFFER_1 (1 << 4)
+#define NV_PVIDEO_BUFFER 0x00000700
+# define NV_PVIDEO_BUFFER_0_USE (1 << 0)
+# define NV_PVIDEO_BUFFER_1_USE (1 << 4)
+#define NV_PVIDEO_STOP 0x00000704
+#define NV_PVIDEO_BASE(i) 0x00000900 + (i * 4)
+#define NV_PVIDEO_LIMIT(i) 0x00000908 + (i * 4)
+#define NV_PVIDEO_LUMINANCE(i) 0x00000910 + (i * 4)
+#define NV_PVIDEO_CHROMINANCE(i) 0x00000918 + (i * 4)
+#define NV_PVIDEO_OFFSET(i) 0x00000920 + (i * 4)
+#define NV_PVIDEO_SIZE_IN(i) 0x00000928 + (i * 4)
+# define NV_PVIDEO_SIZE_IN_WIDTH 0x000007FF
+# define NV_PVIDEO_SIZE_IN_HEIGHT 0x07FF0000
+#define NV_PVIDEO_POINT_IN(i) 0x00000930 + (i * 4)
+# define NV_PVIDEO_POINT_IN_S 0x00007FFF
+# define NV_PVIDEO_POINT_IN_T 0xFFFE0000
+#define NV_PVIDEO_DS_DX(i) 0x00000938 + (i * 4)
+#define NV_PVIDEO_DT_DY(i) 0x00000940 + (i * 4)
+#define NV_PVIDEO_POINT_OUT(i) 0x00000948 + (i * 4)
+# define NV_PVIDEO_POINT_OUT_X 0x00000FFF
+# define NV_PVIDEO_POINT_OUT_Y 0x0FFF0000
+#define NV_PVIDEO_SIZE_OUT(i) 0x00000950 + (i * 4)
+# define NV_PVIDEO_SIZE_OUT_WIDTH 0x00000FFF
+# define NV_PVIDEO_SIZE_OUT_HEIGHT 0x0FFF0000
+#define NV_PVIDEO_FORMAT(i) 0x00000958 + (i * 4)
+# define NV_PVIDEO_FORMAT_PITCH 0x00001FFF
+# define NV_PVIDEO_FORMAT_COLOR 0x00030000
+# define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 1
+# define NV_PVIDEO_FORMAT_DISPLAY (1 << 20)
+#define NV_PVIDEO_COLOR_KEY(i) 0x00000b00 + (i * 4)
+
+
+#define NV_PTIMER_INTR_0 0x00000100
+# define NV_PTIMER_INTR_0_ALARM (1 << 0)
+#define NV_PTIMER_INTR_EN_0 0x00000140
+# define NV_PTIMER_INTR_EN_0_ALARM (1 << 0)
+#define NV_PTIMER_NUMERATOR 0x00000200
+#define NV_PTIMER_DENOMINATOR 0x00000210
+#define NV_PTIMER_TIME_0 0x00000400
+#define NV_PTIMER_TIME_1 0x00000410
+#define NV_PTIMER_ALARM_0 0x00000420
+
+#define NV_PRMVIO_MISC__WRITE 0x000c03c2
+#define NV_PRMVIO_SRX 0x000c03c4
+#define NV_PRMVIO_SR 0x000c03c5
+# define NV_VIO_SR_RESET_INDEX 0x00
+# define NV_VIO_SR_CLOCK_INDEX 0x01
+# define NV_VIO_SR_PLANE_MASK_INDEX 0x02
+# define NV_VIO_SR_CHAR_MAP_INDEX 0x03
+# define NV_VIO_SR_MEM_MODE_INDEX 0x04
+#define NV_PRMVIO_MISC__READ 0x000c03cc
+#define NV_PRMVIO_GRX 0x000c03ce
+#define NV_PRMVIO_GX 0x000c03cf
+# define NV_VIO_GX_SR_INDEX 0x00
+# define NV_VIO_GX_SREN_INDEX 0x01
+# define NV_VIO_GX_CCOMP_INDEX 0x02
+# define NV_VIO_GX_ROP_INDEX 0x03
+# define NV_VIO_GX_READ_MAP_INDEX 0x04
+# define NV_VIO_GX_MODE_INDEX 0x05
+# define NV_VIO_GX_MISC_INDEX 0x06
+# define NV_VIO_GX_DONT_CARE_INDEX 0x07
+# define NV_VIO_GX_BIT_MASK_INDEX 0x08
+
+#define NV_PFB_DEBUG_0 0x00000080
+#define NV_PFB_CFG0 0x00000200
+# define NV_PFB_CFG0_PART 0x00000003
+#define NV_PFB_CFG1 0x00000204
+#define NV_PFB_CSTATUS 0x0000020C
+#define NV_PFB_REFCTRL 0x00000210
+#define NV_PFB_NVM 0x00000214 // NV_PFB_NVM_MODE_DISABLE
+#define NV_PFB_PIN 0x00000218
+#define NV_PFB_PAD 0x0000021C
+#define NV_PFB_TIMING0 0x00000220
+#define NV_PFB_TIMING1 0x00000224
+#define NV_PFB_TIMING2 0x00000228
+#define NV_PFB_TILE(i) 0x00000240 + (i * 0x10)
+#define NV_PFB_TLIMIT(i) 0x00000244 + (i * 0x10)
+#define NV_PFB_TSIZE(i) 0x00000248 + (i * 0x10)
+#define NV_PFB_TSTATUS(i) 0x0000024C + (i * 0x10)
+#define NV_PFB_MRS 0x000002C0
+#define NV_PFB_EMRS 0x000002C4
+#define NV_PFB_MRS_EXT 0x000002C8
+#define NV_PFB_EMRS_EXT 0x000002CC
+#define NV_PFB_REF 0x000002D0
+#define NV_PFB_PRE 0x000002D4
+#define NV_PFB_ZCOMP(i) 0x00000300 + (i * 4)
+#define NV_PFB_ZCOMP_OFFSET 0x00000324
+#define NV_PFB_ARB_PREDIVIDER 0x00000328
+#define NV_PFB_ARB_TIMEOUT 0x0000032C
+#define NV_PFB_ARB_XFER_REM 0x00000334
+#define NV_PFB_ARB_DIFF_BANK 0x00000338
+#define NV_PFB_CLOSE_PAGE0 0x00000340
+#define NV_PFB_CLOSE_PAGE1 0x00000344
+#define NV_PFB_CLOSE_PAGE2 0x00000348
+#define NV_PFB_BPARB 0x0000034C
+#define NV_PFB_CMDQ0 0x00000350
+#define NV_PFB_CMDQ1 0x00000354
+#define NV_PFB_ILL_INSTR 0x00000360
+#define NV_PFB_RT 0x00000400
+#define NV_PFB_AUTOCLOSE 0x00000404
+#define NV_PFB_WBC 0x00000410
+# define NV_PFB_WBC_FLUSH (1 << 16)
+#define NV_PFB_CMDQ_PRT 0x00000418
+#define NV_PFB_CPU_RRQ 0x00000420
+#define NV_PFB_BYPASS 0x00000424
+
+#define NV_PRAMIN_DMA_CLASS(i) 0x00000000 + (i * 0x10)
+#define NV_PRAMIN_DMA_LIMIT(i) 0x00000004 + (i * 0x10)
+#define NV_PRAMIN_DMA_START(i) 0x00000008 + (i * 0x10)
+#define NV_PRAMIN_DMA_ADDRESS(i) 0x0000000C + (i * 0x10)
+
+#define NV_PRAMDAC_NVPLL_COEFF 0x00000500
+# define NV_PRAMDAC_NVPLL_COEFF_MDIV 0x000000FF
+# define NV_PRAMDAC_NVPLL_COEFF_NDIV 0x0000FF00
+# define NV_PRAMDAC_NVPLL_COEFF_PDIV 0x00070000
+#define NV_PRAMDAC_MPLL_COEFF 0x00000504
+# define NV_PRAMDAC_MPLL_COEFF_MDIV 0x000000FF
+# define NV_PRAMDAC_MPLL_COEFF_NDIV 0x0000FF00
+# define NV_PRAMDAC_MPLL_COEFF_PDIV 0x00070000
+#define NV_PRAMDAC_VPLL_COEFF 0x00000508
+# define NV_PRAMDAC_VPLL_COEFF_MDIV 0x000000FF
+# define NV_PRAMDAC_VPLL_COEFF_NDIV 0x0000FF00
+# define NV_PRAMDAC_VPLL_COEFF_PDIV 0x00070000
+#define NV_PRAMDAC_PLL_TEST_COUNTER 0x00000514
+# define NV_PRAMDAC_PLL_TEST_COUNTER_NOOFIPCLKS 0x000003FF
+# define NV_PRAMDAC_PLL_TEST_COUNTER_VALUE 0x0000FFFF
+# define NV_PRAMDAC_PLL_TEST_COUNTER_ENABLE (1 << 16)
+# define NV_PRAMDAC_PLL_TEST_COUNTER_RESET (1 << 20)
+# define NV_PRAMDAC_PLL_TEST_COUNTER_SOURCE 0x03000000
+# define NV_PRAMDAC_PLL_TEST_COUNTER_VPLL2_LOCK (1 << 27)
+# define NV_PRAMDAC_PLL_TEST_COUNTER_PDIV_RST (1 << 28)
+# define NV_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCK (1 << 29)
+# define NV_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCK (1 << 30)
+# define NV_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCK (1 << 31)
+#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600
+# define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON (3 << 4)
+# define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL (1 << 8)
+# define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL (1 << 12)
+# define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM (2 << 16)
+# define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS (1 << 20)
+# define NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG (2 << 28)
+
+#define NV_PRMCIO_ARX 0x006013c0
+#define NV_PRMCIO_AR__WRITE 0x006013c0
+#define NV_PRMCIO_AR__READ 0x006013c1
+# define NV_CIO_AR_MODE_INDEX 0x10
+# define NV_CIO_AR_OSCAN_INDEX 0x11
+# define NV_CIO_AR_PLANE_INDEX 0x12
+# define NV_CIO_AR_HPP_INDEX 0x13
+# define NV_CIO_AR_CSEL_INDEX 0x14
+#define NV_PRMCIO_INP0 0x006013c2
+#define NV_PRMCIO_CRX__COLOR 0x006013d4
+#define NV_PRMCIO_CR__COLOR 0x006013d5
+/* Standard VGA CRTC registers */
+# define NV_CIO_CR_HDT_INDEX 0x00 /* horizontal display total */
+# define NV_CIO_CR_HDE_INDEX 0x01 /* horizontal display end */
+# define NV_CIO_CR_HBS_INDEX 0x02 /* horizontal blanking start */
+# define NV_CIO_CR_HBE_INDEX 0x03 /* horizontal blanking end */
+# define NV_CIO_CR_HBE_4_0 4:0
+# define NV_CIO_CR_HRS_INDEX 0x04 /* horizontal retrace start */
+# define NV_CIO_CR_HRE_INDEX 0x05 /* horizontal retrace end */
+# define NV_CIO_CR_HRE_4_0 4:0
+# define NV_CIO_CR_HRE_HBE_5 7:7
+# define NV_CIO_CR_VDT_INDEX 0x06 /* vertical display total */
+# define NV_CIO_CR_OVL_INDEX 0x07 /* overflow bits */
+# define NV_CIO_CR_OVL_VDT_8 0:0
+# define NV_CIO_CR_OVL_VDE_8 1:1
+# define NV_CIO_CR_OVL_VRS_8 2:2
+# define NV_CIO_CR_OVL_VBS_8 3:3
+# define NV_CIO_CR_OVL_VDT_9 5:5
+# define NV_CIO_CR_OVL_VDE_9 6:6
+# define NV_CIO_CR_OVL_VRS_9 7:7
+# define NV_CIO_CR_RSAL_INDEX 0x08 /* normally "preset row scan" */
+# define NV_CIO_CR_CELL_HT_INDEX 0x09 /* cell height?! normally "max scan line" */
+# define NV_CIO_CR_CELL_HT_VBS_9 5:5
+# define NV_CIO_CR_CELL_HT_SCANDBL 7:7
+# define NV_CIO_CR_CURS_ST_INDEX 0x0a /* cursor start */
+# define NV_CIO_CR_CURS_END_INDEX 0x0b /* cursor end */
+# define NV_CIO_CR_SA_HI_INDEX 0x0c /* screen start address high */
+# define NV_CIO_CR_SA_LO_INDEX 0x0d /* screen start address low */
+# define NV_CIO_CR_TCOFF_HI_INDEX 0x0e /* cursor offset high */
+# define NV_CIO_CR_TCOFF_LO_INDEX 0x0f /* cursor offset low */
+# define NV_CIO_CR_VRS_INDEX 0x10 /* vertical retrace start */
+# define NV_CIO_CR_VRE_INDEX 0x11 /* vertical retrace end */
+# define NV_CIO_CR_VRE_3_0 3:0
+# define NV_CIO_CR_VDE_INDEX 0x12 /* vertical display end */
+# define NV_CIO_CR_OFFSET_INDEX 0x13 /* sets screen pitch */
+# define NV_CIO_CR_ULINE_INDEX 0x14 /* underline location */
+# define NV_CIO_CR_VBS_INDEX 0x15 /* vertical blank start */
+# define NV_CIO_CR_VBE_INDEX 0x16 /* vertical blank end */
+# define NV_CIO_CR_MODE_INDEX 0x17 /* crtc mode control */
+# define NV_CIO_CR_LCOMP_INDEX 0x18 /* line compare */
+/* Extended VGA CRTC registers */
+# define NV_CIO_CRE_RPC0_INDEX 0x19 /* repaint control 0 */
+# define NV_CIO_CRE_RPC0_OFFSET_10_8 7:5
+# define NV_CIO_CRE_RPC1_INDEX 0x1a /* repaint control 1 */
+# define NV_CIO_CRE_RPC1_LARGE 2:2
+# define NV_CIO_CRE_FF_INDEX 0x1b /* fifo control */
+# define NV_CIO_CRE_ENH_INDEX 0x1c /* enhanced? */
+# define NV_CIO_SR_LOCK_INDEX 0x1f /* crtc lock */
+# define NV_CIO_SR_UNLOCK_RW_VALUE 0x57
+# define NV_CIO_SR_LOCK_VALUE 0x99
+# define NV_CIO_CRE_FFLWM__INDEX 0x20 /* fifo low water mark */
+# define NV_CIO_CRE_21 0x21 /* vga shadow crtc lock */
+# define NV_CIO_CRE_LSR_INDEX 0x25 /* ? */
+# define NV_CIO_CRE_LSR_VDT_10 0:0
+# define NV_CIO_CRE_LSR_VDE_10 1:1
+# define NV_CIO_CRE_LSR_VRS_10 2:2
+# define NV_CIO_CRE_LSR_VBS_10 3:3
+# define NV_CIO_CRE_LSR_HBE_6 4:4
+# define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index -- ro copy of 0x60.3c0 */
+# define NV_CIO_CRE_CHIP_ID_INDEX 0x27 /* chip revision */
+# define NV_CIO_CRE_PIXEL_INDEX 0x28
+# define NV_CIO_CRE_PIXEL_FORMAT 1:0
+# define NV_CIO_CRE_HEB__INDEX 0x2d /* horizontal extra bits? */
+# define NV_CIO_CRE_HEB_HDT_8 0:0
+# define NV_CIO_CRE_HEB_HDE_8 1:1
+# define NV_CIO_CRE_HEB_HBS_8 2:2
+# define NV_CIO_CRE_HEB_HRS_8 3:3
+# define NV_CIO_CRE_HEB_ILC_8 4:4
+# define NV_CIO_CRE_2E 0x2e /* some scratch or dummy reg to force writes to sink in */
+# define NV_CIO_CRE_HCUR_ADDR2_INDEX 0x2f /* cursor */
+# define NV_CIO_CRE_HCUR_ADDR0_INDEX 0x30 /* pixmap */
+# define NV_CIO_CRE_HCUR_ADDR0_ADR 6:0
+# define NV_CIO_CRE_HCUR_ASI 7:7
+# define NV_CIO_CRE_HCUR_ADDR1_INDEX 0x31 /* address */
+# define NV_CIO_CRE_HCUR_ADDR1_ENABLE 0:0
+# define NV_CIO_CRE_HCUR_ADDR1_CUR_DBL 1:1
+# define NV_CIO_CRE_HCUR_ADDR1_ADR 7:2
+# define NV_CIO_CRE_LCD__INDEX 0x33
+# define NV_CIO_CRE_LCD_LCD_SELECT 0:0
+# define NV_CIO_CRE_DDC0_STATUS__INDEX 0x36
+# define NV_CIO_CRE_DDC0_WR__INDEX 0x37
+# define NV_CIO_CRE_ILACE__INDEX 0x39 /* interlace */
+# define NV_CIO_CRE_SCRATCH3__INDEX 0x3b
+# define NV_CIO_CRE_SCRATCH4__INDEX 0x3c
+# define NV_CIO_CRE_DDC_STATUS__INDEX 0x3e
+# define NV_CIO_CRE_DDC_WR__INDEX 0x3f
+# define NV_CIO_CRE_EBR_INDEX 0x41 /* extra bits ? (vertical) */
+# define NV_CIO_CRE_EBR_VDT_11 0:0
+# define NV_CIO_CRE_EBR_VDE_11 2:2
+# define NV_CIO_CRE_EBR_VRS_11 4:4
+# define NV_CIO_CRE_EBR_VBS_11 6:6
+# define NV_CIO_CRE_43 0x43
+# define NV_CIO_CRE_44 0x44 /* head control */
+# define NV_CIO_CRE_CSB 0x45 /* colour saturation boost */
+# define NV_CIO_CRE_RCR 0x46
+# define NV_CIO_CRE_RCR_ENDIAN_BIG 7:7
+# define NV_CIO_CRE_47 0x47 /* extended fifo lwm, used on nv30+ */
+# define NV_CIO_CRE_49 0x49
+# define NV_CIO_CRE_4B 0x4b /* given patterns in 0x[2-3][a-c] regs, probably scratch 6 */
+# define NV_CIO_CRE_TVOUT_LATENCY 0x52
+# define NV_CIO_CRE_53 0x53 /* `fp_htiming' according to Haiku */
+# define NV_CIO_CRE_54 0x54 /* `fp_vtiming' according to Haiku */
+# define NV_CIO_CRE_57 0x57 /* index reg for cr58 */
+# define NV_CIO_CRE_58 0x58 /* data reg for cr57 */
+# define NV_CIO_CRE_59 0x59 /* related to on/off-chip-ness of digital outputs */
+# define NV_CIO_CRE_5B 0x5B /* newer colour saturation reg */
+# define NV_CIO_CRE_85 0x85
+# define NV_CIO_CRE_86 0x86
+#define NV_PRMCIO_INP0__COLOR 0x006013da
+
+#define NV_USER_DMA_PUT 0x40
+#define NV_USER_DMA_GET 0x44
+#define NV_USER_REF 0x48
+
+
+
+/* DMA objects */
+#define NV_DMA_FROM_MEMORY_CLASS 0x02
+#define NV_DMA_TO_MEMORY_CLASS 0x03
+#define NV_DMA_IN_MEMORY_CLASS 0x3d
+
+#define NV_DMA_CLASS 0x00000FFF
+#define NV_DMA_PAGE_TABLE (1 << 12)
+#define NV_DMA_PAGE_ENTRY (1 << 13)
+#define NV_DMA_FLAGS_ACCESS (1 << 14)
+#define NV_DMA_FLAGS_MAPPING_COHERENCY (1 << 15)
+#define NV_DMA_TARGET 0x00030000
+# define NV_DMA_TARGET_NVM 0x00000000
+# define NV_DMA_TARGET_NVM_TILED 0x00010000
+# define NV_DMA_TARGET_PCI 0x00020000
+# define NV_DMA_TARGET_AGP 0x00030000
+#define NV_DMA_ADJUST 0xFFF00000
+
+#define NV_DMA_ADDRESS 0xFFFFF000
+
+
+#define NV_RAMHT_HANDLE 0xFFFFFFFF
+#define NV_RAMHT_INSTANCE 0x0000FFFF
+#define NV_RAMHT_ENGINE 0x00030000
+# define NV_RAMHT_ENGINE_SW 0x00000000
+# define NV_RAMHT_ENGINE_GRAPHICS 0x00010000
+# define NV_RAMHT_ENGINE_DVD 0x00020000
+#define NV_RAMHT_CHID 0x1F000000
+#define NV_RAMHT_STATUS 0x80000000
+
+
+
+/* graphic classes and methods */
+#define NV_SET_OBJECT 0x00000000
+
+#define NV_MEMORY_TO_MEMORY_FORMAT 0x0039
+
+#define NV_CONTEXT_PATTERN 0x0044
+# define NV044_SET_MONOCHROME_COLOR0 0x00000310
+
+#define NV_CONTEXT_SURFACES_2D 0x0062
+# define NV062_SET_OBJECT 0x00000000
+# define NV062_SET_CONTEXT_DMA_IMAGE_SOURCE 0x00000184
+# define NV062_SET_CONTEXT_DMA_IMAGE_DESTIN 0x00000188
+# define NV062_SET_COLOR_FORMAT 0x00000300
+# define NV062_SET_COLOR_FORMAT_LE_Y8 0x01
+# define NV062_SET_COLOR_FORMAT_LE_R5G6B5 0x04
+# define NV062_SET_COLOR_FORMAT_LE_A8R8G8B8 0x0A
+# define NV062_SET_PITCH 0x00000304
+# define NV062_SET_OFFSET_SOURCE 0x00000308
+# define NV062_SET_OFFSET_DESTIN 0x0000030C
+
+#define NV_IMAGE_BLIT 0x009F
+# define NV09F_SET_OBJECT 0x00000000
+# define NV09F_SET_CONTEXT_SURFACES 0x0000019C
+# define NV09F_SET_OPERATION 0x000002FC
+# define NV09F_SET_OPERATION_SRCCOPY 3
+# define NV09F_CONTROL_POINT_IN 0x00000300
+# define NV09F_CONTROL_POINT_OUT 0x00000304
+# define NV09F_SIZE 0x00000308
+
+
+#define NV_KELVIN_PRIMITIVE 0x0097
+# define NV097_SET_OBJECT 0x00000000
+# define NV097_NO_OPERATION 0x00000100
+# define NV097_WAIT_FOR_IDLE 0x00000110
+# define NV097_SET_FLIP_READ 0x00000120
+# define NV097_SET_FLIP_WRITE 0x00000124
+# define NV097_SET_FLIP_MODULO 0x00000128
+# define NV097_FLIP_INCREMENT_WRITE 0x0000012C
+# define NV097_FLIP_STALL 0x00000130
+# define NV097_SET_CONTEXT_DMA_NOTIFIES 0x00000180
+# define NV097_SET_CONTEXT_DMA_A 0x00000184
+# define NV097_SET_CONTEXT_DMA_B 0x00000188
+# define NV097_SET_CONTEXT_DMA_STATE 0x00000190
+# define NV097_SET_CONTEXT_DMA_COLOR 0x00000194
+# define NV097_SET_CONTEXT_DMA_ZETA 0x00000198
+# define NV097_SET_CONTEXT_DMA_VERTEX_A 0x0000019C
+# define NV097_SET_CONTEXT_DMA_VERTEX_B 0x000001A0
+# define NV097_SET_CONTEXT_DMA_SEMAPHORE 0x000001A4
+# define NV097_SET_CONTEXT_DMA_REPORT 0x000001A8
+# define NV097_SET_SURFACE_CLIP_HORIZONTAL 0x00000200
+# define NV097_SET_SURFACE_CLIP_HORIZONTAL_X 0x0000FFFF
+# define NV097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 0xFFFF0000
+# define NV097_SET_SURFACE_CLIP_VERTICAL 0x00000204
+# define NV097_SET_SURFACE_CLIP_VERTICAL_Y 0x0000FFFF
+# define NV097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 0xFFFF0000
+# define NV097_SET_SURFACE_FORMAT 0x00000208
+# define NV097_SET_SURFACE_FORMAT_COLOR 0x0000000F
+# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X1R5G5B5_Z1R5G5B5 0x01
+# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X1R5G5B5_O1R5G5B5 0x02
+# define NV097_SET_SURFACE_FORMAT_COLOR_LE_R5G6B5 0x03
+# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X8R8G8B8_Z8R8G8B8 0x04
+# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X8R8G8B8_O8R8G8B8 0x05
+# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X1A7R8G8B8_Z1A7R8G8B8 0x06
+# define NV097_SET_SURFACE_FORMAT_COLOR_LE_X1A7R8G8B8_O1A7R8G8B8 0x07
+# define NV097_SET_SURFACE_FORMAT_COLOR_LE_A8R8G8B8 0x08
+# define NV097_SET_SURFACE_FORMAT_COLOR_LE_B8 0x09
+# define NV097_SET_SURFACE_FORMAT_COLOR_LE_G8B8 0x0A
+# define NV097_SET_SURFACE_FORMAT_ZETA 0x000000F0
+# define NV097_SET_SURFACE_FORMAT_ZETA_Z16 1
+# define NV097_SET_SURFACE_FORMAT_ZETA_Z24S8 2
+# define NV097_SET_SURFACE_FORMAT_TYPE 0x00000F00
+# define NV097_SET_SURFACE_FORMAT_TYPE_PITCH 0x1
+# define NV097_SET_SURFACE_FORMAT_TYPE_SWIZZLE 0x2
+# define NV097_SET_SURFACE_FORMAT_ANTI_ALIASING 0x0000F000
+# define NV097_SET_SURFACE_FORMAT_ANTI_ALIASING_CENTER_1 0
+# define NV097_SET_SURFACE_FORMAT_ANTI_ALIASING_CENTER_CORNER_2 1
+# define NV097_SET_SURFACE_FORMAT_ANTI_ALIASING_SQUARE_OFFSET_4 2
+# define NV097_SET_SURFACE_FORMAT_WIDTH 0x00FF0000
+# define NV097_SET_SURFACE_FORMAT_HEIGHT 0xFF000000
+# define NV097_SET_SURFACE_PITCH 0x0000020C
+# define NV097_SET_SURFACE_PITCH_COLOR 0x0000FFFF
+# define NV097_SET_SURFACE_PITCH_ZETA 0xFFFF0000
+# define NV097_SET_SURFACE_COLOR_OFFSET 0x00000210
+# define NV097_SET_SURFACE_ZETA_OFFSET 0x00000214
+# define NV097_SET_COMBINER_ALPHA_ICW 0x00000260
+# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP 0xE0000000
+# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_UNSIGNED_IDENTITY 0
+# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_UNSIGNED_INVERT 1
+# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_EXPAND_NORMAL 2
+# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_EXPAND_NEGATE 3
+# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_HALFBIAS_NORMAL 4
+# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_HALFBIAS_NEGATE 5
+# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_SIGNED_IDENTITY 6
+# define NV097_SET_COMBINER_ALPHA_ICW_A_MAP_SIGNED_NEGATE 7
+# define NV097_SET_COMBINER_ALPHA_ICW_A_ALPHA (1<<28)
+# define NV097_SET_COMBINER_ALPHA_ICW_A_SOURCE 0x0F000000
+# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP 0x00E00000
+# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_UNSIGNED_IDENTITY 0
+# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_UNSIGNED_INVERT 1
+# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_EXPAND_NORMAL 2
+# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_EXPAND_NEGATE 3
+# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_HALFBIAS_NORMAL 4
+# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_HALFBIAS_NEGATE 5
+# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_SIGNED_IDENTITY 6
+# define NV097_SET_COMBINER_ALPHA_ICW_B_MAP_SIGNED_NEGATE 7
+# define NV097_SET_COMBINER_ALPHA_ICW_B_ALPHA (1<<20)
+# define NV097_SET_COMBINER_ALPHA_ICW_B_SOURCE 0x000F0000
+# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP 0x0000E000
+# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_UNSIGNED_IDENTITY 0
+# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_UNSIGNED_INVERT 1
+# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_EXPAND_NORMAL 2
+# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_EXPAND_NEGATE 3
+# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_HALFBIAS_NORMAL 4
+# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_HALFBIAS_NEGATE 5
+# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_SIGNED_IDENTITY 6
+# define NV097_SET_COMBINER_ALPHA_ICW_C_MAP_SIGNED_NEGATE 7
+# define NV097_SET_COMBINER_ALPHA_ICW_C_ALPHA (1<<12)
+# define NV097_SET_COMBINER_ALPHA_ICW_C_SOURCE 0x00000F00
+# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP 0x000000E0
+# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_UNSIGNED_IDENTITY 0
+# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_UNSIGNED_INVERT 1
+# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_EXPAND_NORMAL 2
+# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_EXPAND_NEGATE 3
+# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_HALFBIAS_NORMAL 4
+# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_HALFBIAS_NEGATE 5
+# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_SIGNED_IDENTITY 6
+# define NV097_SET_COMBINER_ALPHA_ICW_D_MAP_SIGNED_NEGATE 7
+# define NV097_SET_COMBINER_ALPHA_ICW_D_ALPHA (1<<4)
+# define NV097_SET_COMBINER_ALPHA_ICW_D_SOURCE 0x0000000F
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0 0x00000288
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_INVERSE 0xE0000000
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_ALPHA (1<<28)
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE 0x0F000000
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_SPECLIT 0xE
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_EF_PROD 0xF
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_INVERSE 0x00E00000
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_ALPHA (1<<20)
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE 0x000F0000
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_SPECLIT 0xE
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_EF_PROD 0xF
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_INVERSE 0x0000E000
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_ALPHA (1<<12)
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE 0x00000F00
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_SPECLIT 0xE
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_EF_PROD 0xF
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_INVERSE 0x000000E0
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_ALPHA (1<<4)
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE 0x0000000F
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_SPECLIT 0xE
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_EF_PROD 0xF
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1 0x0000028C
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_E_INVERSE 0xE0000000
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_E_ALPHA (1<<28)
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE 0x0F000000
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_F_INVERSE 0x00E00000
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_F_ALPHA (1<<20)
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE 0x000F0000
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_G_INVERSE 0x0000E000
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_G_ALPHA (1<<12)
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE 0x00000F00
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_CLAMP (1<<7)
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R5 (1<<6)
+# define NV097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R12 0x0000003F
+# define NV097_SET_CONTROL0 0x00000290
+# define NV097_SET_CONTROL0_STENCIL_WRITE_ENABLE (1 << 0)
+# define NV097_SET_CONTROL0_Z_FORMAT (1 << 12)
+# define NV097_SET_CONTROL0_Z_PERSPECTIVE_ENABLE (1 << 16)
+# define NV097_SET_CONTROL0_COLOR_SPACE_CONVERT (0xF << 28)
+# define NV097_SET_FOG_MODE 0x0000029C
+# define NV097_SET_FOG_MODE_V_LINEAR 0x2601
+# define NV097_SET_FOG_MODE_V_EXP 0x800
+# define NV097_SET_FOG_MODE_V_EXP2 0x801
+# define NV097_SET_FOG_MODE_V_EXP_ABS 0x802
+# define NV097_SET_FOG_MODE_V_EXP2_ABS 0x803
+# define NV097_SET_FOG_MODE_V_LINEAR_ABS 0x804
+# define NV097_SET_FOG_GEN_MODE 0x000002A0
+# define NV097_SET_FOG_GEN_MODE_V_SPEC_ALPHA 0
+# define NV097_SET_FOG_GEN_MODE_V_RADIAL 1
+# define NV097_SET_FOG_GEN_MODE_V_PLANAR 2
+# define NV097_SET_FOG_GEN_MODE_V_ABS_PLANAR 3
+# define NV097_SET_FOG_GEN_MODE_V_FOG_X 6
+# define NV097_SET_FOG_ENABLE 0x000002A4
+# define NV097_SET_FOG_COLOR 0x000002A8
+# define NV097_SET_FOG_COLOR_RED 0x000000FF
+# define NV097_SET_FOG_COLOR_GREEN 0x0000FF00
+# define NV097_SET_FOG_COLOR_BLUE 0x00FF0000
+# define NV097_SET_FOG_COLOR_ALPHA 0xFF000000
+# define NV097_SET_WINDOW_CLIP_TYPE 0x000002B4
+# define NV097_SET_WINDOW_CLIP_HORIZONTAL 0x000002C0
+# define NV097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 0x00000FFF
+# define NV097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 0x0FFF0000
+# define NV097_SET_WINDOW_CLIP_VERTICAL 0x000002E0
+# define NV097_SET_ALPHA_TEST_ENABLE 0x00000300
+# define NV097_SET_BLEND_ENABLE 0x00000304
+# define NV097_SET_CULL_FACE_ENABLE 0x00000308
+# define NV097_SET_DEPTH_TEST_ENABLE 0x0000030C
+# define NV097_SET_DITHER_ENABLE 0x00000310
+# define NV097_SET_LIGHTING_ENABLE 0x00000314
+# define NV097_SET_SKIN_MODE 0x00000328
+# define NV097_SET_SKIN_MODE_OFF 0
+# define NV097_SET_SKIN_MODE_2G 1
+# define NV097_SET_SKIN_MODE_2 2
+# define NV097_SET_SKIN_MODE_3G 3
+# define NV097_SET_SKIN_MODE_3 4
+# define NV097_SET_SKIN_MODE_4G 5
+# define NV097_SET_SKIN_MODE_4 6
+# define NV097_SET_STENCIL_TEST_ENABLE 0x0000032C
+# define NV097_SET_POLY_OFFSET_POINT_ENABLE 0x00000330
+# define NV097_SET_POLY_OFFSET_LINE_ENABLE 0x00000334
+# define NV097_SET_POLY_OFFSET_FILL_ENABLE 0x00000338
+# define NV097_SET_ALPHA_FUNC 0x0000033C
+# define NV097_SET_ALPHA_REF 0x00000340
+# define NV097_SET_BLEND_FUNC_SFACTOR 0x00000344
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_ZERO 0x0000
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE 0x0001
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_SRC_COLOR 0x0300
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_SRC_COLOR 0x0301
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_SRC_ALPHA 0x0302
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_SRC_ALPHA 0x0303
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_DST_ALPHA 0x0304
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_DST_ALPHA 0x0305
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_DST_COLOR 0x0306
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_DST_COLOR 0x0307
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_SRC_ALPHA_SATURATE 0x0308
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_CONSTANT_COLOR 0x8001
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_CONSTANT_COLOR 0x8002
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_CONSTANT_ALPHA 0x8003
+# define NV097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_CONSTANT_ALPHA 0x8004
+# define NV097_SET_BLEND_FUNC_DFACTOR 0x00000348
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_ZERO 0x0000
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE 0x0001
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_SRC_COLOR 0x0300
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_SRC_COLOR 0x0301
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_SRC_ALPHA 0x0302
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_SRC_ALPHA 0x0303
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_DST_ALPHA 0x0304
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_DST_ALPHA 0x0305
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_DST_COLOR 0x0306
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_DST_COLOR 0x0307
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_SRC_ALPHA_SATURATE 0x0308
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_CONSTANT_COLOR 0x8001
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_CONSTANT_COLOR 0x8002
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_CONSTANT_ALPHA 0x8003
+# define NV097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_CONSTANT_ALPHA 0x8004
+# define NV097_SET_BLEND_COLOR 0x0000034C
+# define NV097_SET_BLEND_EQUATION 0x00000350
+# define NV097_SET_BLEND_EQUATION_V_FUNC_SUBTRACT 0x800A
+# define NV097_SET_BLEND_EQUATION_V_FUNC_REVERSE_SUBTRACT 0x800B
+# define NV097_SET_BLEND_EQUATION_V_FUNC_ADD 0x8006
+# define NV097_SET_BLEND_EQUATION_V_MIN 0x8007
+# define NV097_SET_BLEND_EQUATION_V_MAX 0x8008
+# define NV097_SET_BLEND_EQUATION_V_FUNC_REVERSE_SUBTRACT_SIGNED 0xF005
+# define NV097_SET_BLEND_EQUATION_V_FUNC_ADD_SIGNED 0xF006
+# define NV097_SET_DEPTH_FUNC 0x00000354
+# define NV097_SET_COLOR_MASK 0x00000358
+# define NV097_SET_COLOR_MASK_BLUE_WRITE_ENABLE (1 << 0)
+# define NV097_SET_COLOR_MASK_GREEN_WRITE_ENABLE (1 << 8)
+# define NV097_SET_COLOR_MASK_RED_WRITE_ENABLE (1 << 16)
+# define NV097_SET_COLOR_MASK_ALPHA_WRITE_ENABLE (1 << 24)
+# define NV097_SET_DEPTH_MASK 0x0000035C
+# define NV097_SET_STENCIL_MASK 0x00000360
+# define NV097_SET_STENCIL_FUNC 0x00000364
+# define NV097_SET_STENCIL_FUNC_REF 0x00000368
+# define NV097_SET_STENCIL_FUNC_MASK 0x0000036C
+# define NV097_SET_STENCIL_OP_FAIL 0x00000370
+# define NV097_SET_STENCIL_OP_ZFAIL 0x00000374
+# define NV097_SET_STENCIL_OP_ZPASS 0x00000378
+# define NV097_SET_STENCIL_OP_V_KEEP 0x1E00
+# define NV097_SET_STENCIL_OP_V_ZERO 0x0000
+# define NV097_SET_STENCIL_OP_V_REPLACE 0x1E01
+# define NV097_SET_STENCIL_OP_V_INCRSAT 0x1E02
+# define NV097_SET_STENCIL_OP_V_DECRSAT 0x1E03
+# define NV097_SET_STENCIL_OP_V_INVERT 0x150A
+# define NV097_SET_STENCIL_OP_V_INCR 0x8507
+# define NV097_SET_STENCIL_OP_V_DECR 0x8508
+# define NV097_SET_POLYGON_OFFSET_SCALE_FACTOR 0x00000384
+# define NV097_SET_POLYGON_OFFSET_BIAS 0x00000388
+# define NV097_SET_FRONT_POLYGON_MODE 0x0000038C
+# define NV097_SET_FRONT_POLYGON_MODE_V_POINT 0x1B00
+# define NV097_SET_FRONT_POLYGON_MODE_V_LINE 0x1B01
+# define NV097_SET_FRONT_POLYGON_MODE_V_FILL 0x1B02
+# define NV097_SET_BACK_POLYGON_MODE 0x00000390
+# define NV097_SET_CLIP_MIN 0x00000394
+# define NV097_SET_CLIP_MAX 0x00000398
+# define NV097_SET_CULL_FACE 0x0000039C
+# define NV097_SET_CULL_FACE_V_FRONT 0x404
+# define NV097_SET_CULL_FACE_V_BACK 0x405
+# define NV097_SET_CULL_FACE_V_FRONT_AND_BACK 0x408
+# define NV097_SET_FRONT_FACE 0x000003A0
+# define NV097_SET_FRONT_FACE_V_CW 0x900
+# define NV097_SET_FRONT_FACE_V_CCW 0x901
+# define NV097_SET_NORMALIZATION_ENABLE 0x000003A4
+# define NV097_SET_LIGHT_ENABLE_MASK 0x000003BC
+# define NV097_SET_LIGHT_ENABLE_MASK_LIGHT0_OFF 0
+# define NV097_SET_LIGHT_ENABLE_MASK_LIGHT0_INFINITE 1
+# define NV097_SET_LIGHT_ENABLE_MASK_LIGHT0_LOCAL 2
+# define NV097_SET_LIGHT_ENABLE_MASK_LIGHT0_SPOT 3
+# define NV097_SET_TEXGEN_S 0x000003C0
+# define NV097_SET_TEXGEN_S_DISABLE 0x0000
+# define NV097_SET_TEXGEN_S_EYE_LINEAR 0x2400
+# define NV097_SET_TEXGEN_S_OBJECT_LINEAR 0x2401
+# define NV097_SET_TEXGEN_S_SPHERE_MAP 0x2402
+# define NV097_SET_TEXGEN_S_REFLECTION_MAP 0x8512
+# define NV097_SET_TEXGEN_S_NORMAL_MAP 0x8511
+# define NV097_SET_TEXGEN_T 0x000003C4
+# define NV097_SET_TEXGEN_R 0x000003C8
+# define NV097_SET_TEXGEN_Q 0x000003CC
+# define NV097_SET_TEXTURE_MATRIX_ENABLE 0x00000420
+# define NV097_SET_PROJECTION_MATRIX 0x00000440
+# define NV097_SET_MODEL_VIEW_MATRIX 0x00000480
+# define NV097_SET_INVERSE_MODEL_VIEW_MATRIX 0x00000580
+# define NV097_SET_COMPOSITE_MATRIX 0x00000680
+# define NV097_SET_TEXTURE_MATRIX 0x000006C0
+# define NV097_SET_TEXGEN_PLANE_S 0x00000840
+# define NV097_SET_TEXGEN_PLANE_T 0x00000850
+# define NV097_SET_TEXGEN_PLANE_R 0x00000860
+# define NV097_SET_TEXGEN_PLANE_Q 0x00000870
+# define NV097_SET_FOG_PARAMS 0x000009C0
+# define NV097_SET_TEXGEN_VIEW_MODEL 0x000009CC
+# define NV097_SET_TEXGEN_VIEW_MODEL_LOCAL_VIEWER 0
+# define NV097_SET_TEXGEN_VIEW_MODEL_INFINITE_VIEWER 1
+# define NV097_SET_FOG_PLANE 0x000009D0
+# define NV097_SET_FLAT_SHADE_OP 0x000009FC
+# define NV097_SET_SCENE_AMBIENT_COLOR 0x00000A10
+# define NV097_SET_VIEWPORT_OFFSET 0x00000A20
+# define NV097_SET_EYE_POSITION 0x00000A50
+# define NV097_SET_COMBINER_FACTOR0 0x00000A60
+# define NV097_SET_COMBINER_FACTOR1 0x00000A80
+# define NV097_SET_COMBINER_ALPHA_OCW 0x00000AA0
+# define NV097_SET_COMBINER_ALPHA_OCW_OP 0xFFFF8000
+# define NV097_SET_COMBINER_ALPHA_OCW_OP_NOSHIFT 0
+# define NV097_SET_COMBINER_ALPHA_OCW_OP_NOSHIFT_BIAS 1
+# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTLEFTBY1 2
+# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTLEFTBY1_BIAS 3
+# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTLEFTBY2 4
+# define NV097_SET_COMBINER_ALPHA_OCW_OP_SHIFTRIGHTBY1 6
+# define NV097_SET_COMBINER_ALPHA_OCW_MUX_ENABLE (1<<14)
+# define NV097_SET_COMBINER_ALPHA_OCW_SUM_DST 0x00000F00
+# define NV097_SET_COMBINER_ALPHA_OCW_AB_DST 0x000000F0
+# define NV097_SET_COMBINER_ALPHA_OCW_CD_DST 0x0000000F
+# define NV097_SET_COMBINER_COLOR_ICW 0x00000AC0
+# define NV097_SET_COMBINER_COLOR_ICW_A_MAP 0xE0000000
+# define NV097_SET_COMBINER_COLOR_ICW_A_ALPHA (1<<28)
+# define NV097_SET_COMBINER_COLOR_ICW_A_SOURCE 0x0F000000
+# define NV097_SET_COMBINER_COLOR_ICW_B_MAP 0x00E00000
+# define NV097_SET_COMBINER_COLOR_ICW_B_ALPHA (1<<20)
+# define NV097_SET_COMBINER_COLOR_ICW_B_SOURCE 0x000F0000
+# define NV097_SET_COMBINER_COLOR_ICW_C_MAP 0x0000E000
+# define NV097_SET_COMBINER_COLOR_ICW_C_ALPHA (1<<12)
+# define NV097_SET_COMBINER_COLOR_ICW_C_SOURCE 0x00000F00
+# define NV097_SET_COMBINER_COLOR_ICW_D_MAP 0x000000E0
+# define NV097_SET_COMBINER_COLOR_ICW_D_ALPHA (1<<4)
+# define NV097_SET_COMBINER_COLOR_ICW_D_SOURCE 0x0000000F
+# define NV097_SET_VIEWPORT_SCALE 0x00000AF0
+# define NV097_SET_TRANSFORM_PROGRAM 0x00000B00
+# define NV097_SET_TRANSFORM_CONSTANT 0x00000B80
+# define NV097_SET_BACK_LIGHT_AMBIENT_COLOR 0x00000C00
+# define NV097_SET_BACK_LIGHT_DIFFUSE_COLOR 0x00000C0C
+# define NV097_SET_BACK_LIGHT_SPECULAR_COLOR 0x00000C18
+# define NV097_SET_LIGHT_AMBIENT_COLOR 0x00001000
+# define NV097_SET_LIGHT_DIFFUSE_COLOR 0x0000100C
+# define NV097_SET_LIGHT_SPECULAR_COLOR 0x00001018
+# define NV097_SET_LIGHT_LOCAL_RANGE 0x00001024
+# define NV097_SET_LIGHT_INFINITE_HALF_VECTOR 0x00001028
+# define NV097_SET_LIGHT_INFINITE_DIRECTION 0x00001034
+# define NV097_SET_LIGHT_SPOT_FALLOFF 0x00001040
+# define NV097_SET_LIGHT_SPOT_DIRECTION 0x0000104C
+# define NV097_SET_LIGHT_LOCAL_POSITION 0x0000105C
+# define NV097_SET_LIGHT_LOCAL_ATTENUATION 0x00001068
+# define NV097_SET_VERTEX3F 0x00001500
+# define NV097_SET_VERTEX4F 0x00001518
+# define NV097_SET_VERTEX_DATA_ARRAY_OFFSET 0x00001720
+# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT 0x00001760
+# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE 0x0000000F
+# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_UB_D3D 0
+# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_S1 1
+# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_F 2
+# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_UB_OGL 4
+# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_S32K 5
+# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_CMP 6
+# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_SIZE 0x000000F0
+# define NV097_SET_VERTEX_DATA_ARRAY_FORMAT_STRIDE 0xFFFFFF00
+# define NV097_SET_LOGIC_OP_ENABLE 0x000017BC
+# define NV097_SET_LOGIC_OP 0x000017C0
+# define NV097_CLEAR_REPORT_VALUE 0x000017C8
+# define NV097_CLEAR_REPORT_VALUE_TYPE 0xFFFFFFFF
+# define NV097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 1
+# define NV097_SET_ZPASS_PIXEL_COUNT_ENABLE 0x000017CC
+# define NV097_GET_REPORT 0x000017D0
+# define NV097_GET_REPORT_OFFSET 0x00FFFFFF
+# define NV097_GET_REPORT_TYPE 0xFF000000
+# define NV097_GET_REPORT_TYPE_ZPASS_PIXEL_CNT 1
+# define NV097_SET_EYE_DIRECTION 0x000017E0
+# define NV097_SET_SHADER_CLIP_PLANE_MODE 0x000017F8
+# define NV097_SET_BEGIN_END 0x000017FC
+# define NV097_SET_BEGIN_END_OP_END 0x00
+# define NV097_SET_BEGIN_END_OP_POINTS 0x01
+# define NV097_SET_BEGIN_END_OP_LINES 0x02
+# define NV097_SET_BEGIN_END_OP_LINE_LOOP 0x03
+# define NV097_SET_BEGIN_END_OP_LINE_STRIP 0x04
+# define NV097_SET_BEGIN_END_OP_TRIANGLES 0x05
+# define NV097_SET_BEGIN_END_OP_TRIANGLE_STRIP 0x06
+# define NV097_SET_BEGIN_END_OP_TRIANGLE_FAN 0x07
+# define NV097_SET_BEGIN_END_OP_QUADS 0x08
+# define NV097_SET_BEGIN_END_OP_QUAD_STRIP 0x09
+# define NV097_SET_BEGIN_END_OP_POLYGON 0x0A
+# define NV097_ARRAY_ELEMENT16 0x00001800
+# define NV097_ARRAY_ELEMENT32 0x00001808
+# define NV097_DRAW_ARRAYS 0x00001810
+# define NV097_DRAW_ARRAYS_COUNT 0xFF000000
+# define NV097_DRAW_ARRAYS_START_INDEX 0x00FFFFFF
+# define NV097_INLINE_ARRAY 0x00001818
+# define NV097_SET_EYE_VECTOR 0x0000181C
+# define NV097_SET_VERTEX_DATA2F_M 0x00001880
+# define NV097_SET_VERTEX_DATA2S 0x00001900
+# define NV097_SET_VERTEX_DATA4UB 0x00001940
+# define NV097_SET_VERTEX_DATA4S_M 0x00001980
+# define NV097_SET_VERTEX_DATA4F_M 0x00001A00
+# define NV097_SET_TEXTURE_OFFSET 0x00001B00
+# define NV097_SET_TEXTURE_FORMAT 0x00001B04
+# define NV097_SET_TEXTURE_FORMAT_CONTEXT_DMA 0x00000003
+# define NV097_SET_TEXTURE_FORMAT_CUBEMAP_ENABLE (1 << 2)
+# define NV097_SET_TEXTURE_FORMAT_BORDER_SOURCE (1 << 3)
+# define NV097_SET_TEXTURE_FORMAT_BORDER_SOURCE_TEXTURE 0
+# define NV097_SET_TEXTURE_FORMAT_BORDER_SOURCE_COLOR 1
+# define NV097_SET_TEXTURE_FORMAT_DIMENSIONALITY 0x000000F0
+# define NV097_SET_TEXTURE_FORMAT_COLOR 0x0000FF00
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_Y8 0x00
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_AY8 0x01
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A1R5G5B5 0x02
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_X1R5G5B5 0x03
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A4R4G4B4 0x04
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R5G6B5 0x05
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A8R8G8B8 0x06
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_X8R8G8B8 0x07
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_I8_A8R8G8B8 0x0B
+# define NV097_SET_TEXTURE_FORMAT_COLOR_L_DXT1_A1R5G5B5 0x0C
+# define NV097_SET_TEXTURE_FORMAT_COLOR_L_DXT23_A8R8G8B8 0x0E
+# define NV097_SET_TEXTURE_FORMAT_COLOR_L_DXT45_A8R8G8B8 0x0F
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A1R5G5B5 0x10
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R5G6B5 0x11
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8R8G8B8 0x12
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_Y8 0x13
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_SY8 0x14
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_X7SY9 0x15
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R8B8 0x16
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_G8B8 0x17
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_SG8SB8 0x18
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A8 0x19
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A8Y8 0x1A
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_AY8 0x1B
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_X1R5G5B5 0x1C
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A4R4G4B4 0x1D
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_X8R8G8B8 0x1E
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8 0x1F
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8Y8 0x20
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LC_IMAGE_CR8YB8CB8YA8 0x24
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LC_IMAGE_YB8CR8YA8CB8 0x25
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8CR8CB8Y8 0x26
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R6G5B5 0x27
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_G8B8 0x28
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R8B8 0x29
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_X8_Y24_FIXED 0x2A
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_X8_Y24_FLOAT 0x2B
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_Y16_FIXED 0x2C
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_Y16_FLOAT 0x2D
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_DEPTH_X8_Y24_FIXED 0x2E
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_DEPTH_Y16_FIXED 0x30
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_DEPTH_Y16_FLOAT 0x31
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_Y16 0x32
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_YB16YA16 0x33 // was NV097_SET_TEXTURE_FORMAT_COLOR_SZ_YB_16_YA_16
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LC_IMAGE_A4V6YB6A4U6YA6 0x34
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_Y16 0x35
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_YB16YA16 0x36
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R6G5B5 0x37
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R5G5B5A1 0x38
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R4G4B4A4 0x39
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_A8B8G8R8 0x3A
+# define NV097_SET_TEXTURE_FORMAT_COLOR_SZ_R8G8B8A8 0x3C
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R5G5B5A1 0x3D
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R4G4B4A4 0x3E
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8B8G8R8 0x3F
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_B8G8R8A8 0x40
+# define NV097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R8G8B8A8 0x41
+# define NV097_SET_TEXTURE_FORMAT_MIPMAP_LEVELS 0x000F0000
+# define NV097_SET_TEXTURE_FORMAT_BASE_SIZE_U 0x00F00000
+# define NV097_SET_TEXTURE_FORMAT_BASE_SIZE_V 0x0F000000
+# define NV097_SET_TEXTURE_FORMAT_BASE_SIZE_P 0xF0000000
+# define NV097_SET_TEXTURE_ADDRESS 0x00001B08
+# define NV097_SET_TEXTURE_CONTROL0 0x00001B0C
+# define NV097_SET_TEXTURE_CONTROL0_ENABLE (1 << 30)
+# define NV097_SET_TEXTURE_CONTROL0_MIN_LOD_CLAMP 0x3FFC0000
+# define NV097_SET_TEXTURE_CONTROL0_MAX_LOD_CLAMP 0x0003FFC0
+# define NV097_SET_TEXTURE_CONTROL1 0x00001B10
+# define NV097_SET_TEXTURE_CONTROL1_IMAGE_PITCH 0xFFFF0000
+# define NV097_SET_TEXTURE_FILTER 0x00001B14
+# define NV097_SET_TEXTURE_FILTER_MIPMAP_LOD_BIAS 0x00001FFF
+# define NV097_SET_TEXTURE_FILTER_MIN 0x00FF0000
+# define NV097_SET_TEXTURE_FILTER_MAG 0x0F000000
+# define NV097_SET_TEXTURE_FILTER_ASIGNED (1 << 28)
+# define NV097_SET_TEXTURE_FILTER_RSIGNED (1 << 29)
+# define NV097_SET_TEXTURE_FILTER_GSIGNED (1 << 30)
+# define NV097_SET_TEXTURE_FILTER_BSIGNED (1 << 31)
+# define NV097_SET_TEXTURE_IMAGE_RECT 0x00001B1C
+# define NV097_SET_TEXTURE_IMAGE_RECT_WIDTH 0xFFFF0000
+# define NV097_SET_TEXTURE_IMAGE_RECT_HEIGHT 0x0000FFFF
+# define NV097_SET_TEXTURE_PALETTE 0x00001B20
+# define NV097_SET_TEXTURE_PALETTE_CONTEXT_DMA (1 << 0)
+# define NV097_SET_TEXTURE_PALETTE_LENGTH 0x0000000C
+# define NV097_SET_TEXTURE_PALETTE_LENGTH_256 0
+# define NV097_SET_TEXTURE_PALETTE_LENGTH_128 1
+# define NV097_SET_TEXTURE_PALETTE_LENGTH_64 2
+# define NV097_SET_TEXTURE_PALETTE_LENGTH_32 3
+# define NV097_SET_TEXTURE_PALETTE_OFFSET 0xFFFFFFC0
+# define NV097_SET_TEXTURE_BORDER_COLOR 0x00001B24
+# define NV097_SET_TEXTURE_SET_BUMP_ENV_MAT 0x00001B28
+# define NV097_SET_TEXTURE_SET_BUMP_ENV_SCALE 0x00001B38
+# define NV097_SET_TEXTURE_SET_BUMP_ENV_OFFSET 0x00001B3C
+# define NV097_SET_SEMAPHORE_OFFSET 0x00001D6C
+# define NV097_BACK_END_WRITE_SEMAPHORE_RELEASE 0x00001D70
+# define NV097_SET_ZMIN_MAX_CONTROL 0x00001D78
+# define NV097_SET_COMPRESS_ZBUFFER_EN 0x00001D80
+# define NV097_SET_ZSTENCIL_CLEAR_VALUE 0x00001D8C
+# define NV097_SET_COLOR_CLEAR_VALUE 0x00001D90
+# define NV097_CLEAR_SURFACE 0x00001D94
+# define NV097_CLEAR_SURFACE_Z (1 << 0)
+# define NV097_CLEAR_SURFACE_STENCIL (1 << 1)
+# define NV097_CLEAR_SURFACE_COLOR 0x000000F0
+# define NV097_CLEAR_SURFACE_R (1 << 4)
+# define NV097_CLEAR_SURFACE_G (1 << 5)
+# define NV097_CLEAR_SURFACE_B (1 << 6)
+# define NV097_CLEAR_SURFACE_A (1 << 7)
+# define NV097_SET_CLEAR_RECT_HORIZONTAL 0x00001D98
+# define NV097_SET_CLEAR_RECT_VERTICAL 0x00001D9C
+# define NV097_SET_SPECULAR_FOG_FACTOR 0x00001E20
+# define NV097_SET_COMBINER_COLOR_OCW 0x00001E40
+# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB 0xFFF80000
+# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB_DISABLE 0
+# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB_AB_DST_ENABLE 1
+# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD (1<<18)
+# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD_DISABLE 0
+# define NV097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD_CD_DST_ENABLE 1
+# define NV097_SET_COMBINER_COLOR_OCW_OP 0x00038000
+# define NV097_SET_COMBINER_COLOR_OCW_OP_NOSHIFT 0
+# define NV097_SET_COMBINER_COLOR_OCW_OP_NOSHIFT_BIAS 1
+# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY1 2
+# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY1_BIAS 3
+# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY2 4
+# define NV097_SET_COMBINER_COLOR_OCW_OP_SHIFTRIGHTBY1 6
+# define NV097_SET_COMBINER_COLOR_OCW_MUX_ENABLE (1 << 14)
+# define NV097_SET_COMBINER_COLOR_OCW_AB_DOT_ENABLE (1 << 13)
+# define NV097_SET_COMBINER_COLOR_OCW_CD_DOT_ENABLE (1<<12)
+# define NV097_SET_COMBINER_COLOR_OCW_SUM_DST 0x00000F00
+# define NV097_SET_COMBINER_COLOR_OCW_AB_DST 0x000000F0
+# define NV097_SET_COMBINER_COLOR_OCW_CD_DST 0x0000000F
+# define NV097_SET_COMBINER_CONTROL 0x00001E60
+# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT 0x000000FF
+# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_ONE 1
+# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_TWO 2
+# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_THREE 3
+# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_FOUR 4
+# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_FIVE 5
+# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_SIX 6
+# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_SEVEN 7
+# define NV097_SET_COMBINER_CONTROL_ITERATION_COUNT_EIGHT 8
+# define NV097_SET_COMBINER_CONTROL_MUX_SELECT 0x00000F00
+# define NV097_SET_COMBINER_CONTROL_MUX_SELECT_LSB 0
+# define NV097_SET_COMBINER_CONTROL_MUX_SELECT_MSB 1
+# define NV097_SET_COMBINER_CONTROL_FACTOR0 0x0000F000
+# define NV097_SET_COMBINER_CONTROL_FACTOR0_SAME_FACTOR_ALL 0
+# define NV097_SET_COMBINER_CONTROL_FACTOR0_EACH_STAGE 1
+# define NV097_SET_COMBINER_CONTROL_FACTOR1 0xFFFF0000
+# define NV097_SET_COMBINER_CONTROL_FACTOR1_SAME_FACTOR_ALL 0
+# define NV097_SET_COMBINER_CONTROL_FACTOR1_EACH_STAGE 1
+# define NV097_SET_SHADOW_ZSLOPE_THRESHOLD 0x00001E68
+# define NV097_SET_SHADER_STAGE_PROGRAM 0x00001E70
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0 0x0000001F
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_PROGRAM_NONE 0
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_2D_PROJECTIVE 1
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_3D_PROJECTIVE 2
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_CUBE_MAP 3
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_PASS_THROUGH 4
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE0_CLIP_PLANE 5
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1 0x000003E0
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_PROGRAM_NONE 0x00
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_2D_PROJECTIVE 0x01
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_3D_PROJECTIVE 0x02
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_CUBE_MAP 0x03
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_PASS_THROUGH 0x04
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_CLIP_PLANE 0x05
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_BUMPENVMAP 0x06
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_BUMPENVMAP_LUMINANCE 0x07
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_DEPENDENT_AR 0x0F
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_DEPENDENT_GB 0x10
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE1_DOT_PRODUCT 0x11
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2 0x00007C00
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_PROGRAM_NONE 0x00
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_2D_PROJECTIVE 0x01
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_3D_PROJECTIVE 0x02
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_CUBE_MAP 0x03
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_PASS_THROUGH 0x04
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_CLIP_PLANE 0x05
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_BUMPENVMAP 0x06
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_BUMPENVMAP_LUMINANCE 0x07
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_BRDF 0x08
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_ST 0x09
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_ZW 0x0A
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_REFLECT_DIFFUSE 0x0B
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DEPENDENT_AR 0x0F
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DEPENDENT_GB 0x10
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_PRODUCT 0x11
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3 0x000F8000
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_PROGRAM_NONE 0x00
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_2D_PROJECTIVE 0x01
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_3D_PROJECTIVE 0x02
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_CUBE_MAP 0x03
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_PASS_THROUGH 0x04
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_CLIP_PLANE 0x05
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_BUMPENVMAP 0x06
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_BUMPENVMAP_LUMINANCE 0x07
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_BRDF 0x08
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_ST 0x09
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_ZW 0x0A
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_REFLECT_SPECULAR 0x0C
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_STR_3D 0x0D
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_STR_CUBE 0x0E
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DEPENDENT_AR 0x0F
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DEPENDENT_GB 0x10
+# define NV097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_REFLECT_SPECULAR_CONST 0x12
+# define NV097_SET_SHADER_OTHER_STAGE_INPUT 0x00001E78
+# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE1 0x0000FFFF
+# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE1_INSTAGE_0 0
+# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2 0x000F0000
+# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2_INSTAGE_0 0
+# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2_INSTAGE_1 1
+# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3 0x00F00000
+# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_0 0
+# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_1 1
+# define NV097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_2 2
+# define NV097_SET_TRANSFORM_DATA 0x00001E80
+# define NV097_LAUNCH_TRANSFORM_PROGRAM 0x00001E90
+# define NV097_SET_TRANSFORM_EXECUTION_MODE 0x00001E94
+# define NV097_SET_TRANSFORM_EXECUTION_MODE_MODE 0x00000003
+# define NV097_SET_TRANSFORM_EXECUTION_MODE_MODE_FIXED 0
+# define NV097_SET_TRANSFORM_EXECUTION_MODE_MODE_PROGRAM 2
+# define NV097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE 0xFFFFFFFC
+# define NV097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE_USER 0
+# define NV097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE_PRIV 1
+# define NV097_SET_TRANSFORM_PROGRAM_CXT_WRITE_EN 0x00001E98
+# define NV097_SET_TRANSFORM_PROGRAM_LOAD 0x00001E9C
+# define NV097_SET_TRANSFORM_PROGRAM_START 0x00001EA0
+# define NV097_SET_TRANSFORM_CONSTANT_LOAD 0x00001EA4
+
+/* vertex processing (cheops) context layout */
+#define NV_IGRAPH_XF_XFCTX_CMAT0 0x00
+#define NV_IGRAPH_XF_XFCTX_PMAT0 0x04
+#define NV_IGRAPH_XF_XFCTX_MMAT0 0x08
+#define NV_IGRAPH_XF_XFCTX_IMMAT0 0x0c
+#define NV_IGRAPH_XF_XFCTX_MMAT1 0x10
+#define NV_IGRAPH_XF_XFCTX_IMMAT1 0x14
+#define NV_IGRAPH_XF_XFCTX_MMAT2 0x18
+#define NV_IGRAPH_XF_XFCTX_IMMAT2 0x1c
+#define NV_IGRAPH_XF_XFCTX_MMAT3 0x20
+#define NV_IGRAPH_XF_XFCTX_IMMAT3 0x24
+#define NV_IGRAPH_XF_XFCTX_LIT0 0x28
+#define NV_IGRAPH_XF_XFCTX_LIT1 0x29
+#define NV_IGRAPH_XF_XFCTX_LIT2 0x2a
+#define NV_IGRAPH_XF_XFCTX_LIT3 0x2b
+#define NV_IGRAPH_XF_XFCTX_LIT4 0x2c
+#define NV_IGRAPH_XF_XFCTX_LIT5 0x2d
+#define NV_IGRAPH_XF_XFCTX_LIT6 0x2e
+#define NV_IGRAPH_XF_XFCTX_LIT7 0x2f
+#define NV_IGRAPH_XF_XFCTX_SPOT0 0x30
+#define NV_IGRAPH_XF_XFCTX_SPOT1 0x31
+#define NV_IGRAPH_XF_XFCTX_SPOT2 0x32
+#define NV_IGRAPH_XF_XFCTX_SPOT3 0x33
+#define NV_IGRAPH_XF_XFCTX_SPOT4 0x34
+#define NV_IGRAPH_XF_XFCTX_SPOT5 0x35
+#define NV_IGRAPH_XF_XFCTX_SPOT6 0x36
+#define NV_IGRAPH_XF_XFCTX_SPOT7 0x37
+#define NV_IGRAPH_XF_XFCTX_EYEP 0x38
+#define NV_IGRAPH_XF_XFCTX_FOG 0x39
+#define NV_IGRAPH_XF_XFCTX_VPSCL 0x3a
+#define NV_IGRAPH_XF_XFCTX_VPOFF 0x3b
+#define NV_IGRAPH_XF_XFCTX_CONS0 0x3c
+#define NV_IGRAPH_XF_XFCTX_CONS1 0x3d
+#define NV_IGRAPH_XF_XFCTX_CONS2 0x3e
+#define NV_IGRAPH_XF_XFCTX_CONS3 0x3f
+#define NV_IGRAPH_XF_XFCTX_TG0MAT 0x40
+#define NV_IGRAPH_XF_XFCTX_T0MAT 0x44
+#define NV_IGRAPH_XF_XFCTX_TG1MAT 0x48
+#define NV_IGRAPH_XF_XFCTX_T1MAT 0x4c
+#define NV_IGRAPH_XF_XFCTX_TG2MAT 0x50
+#define NV_IGRAPH_XF_XFCTX_T2MAT 0x54
+#define NV_IGRAPH_XF_XFCTX_TG3MAT 0x58
+#define NV_IGRAPH_XF_XFCTX_T3MAT 0x5c
+#define NV_IGRAPH_XF_XFCTX_PRSPACE 0x60
+
+/* lighting (zoser) context layout */
+#define NV_IGRAPH_XF_LTCTXA_L0_K 0x00
+#define NV_IGRAPH_XF_LTCTXA_L0_SPT 0x01
+#define NV_IGRAPH_XF_LTCTXA_L1_K 0x02
+#define NV_IGRAPH_XF_LTCTXA_L1_SPT 0x03
+#define NV_IGRAPH_XF_LTCTXA_L2_K 0x04
+#define NV_IGRAPH_XF_LTCTXA_L2_SPT 0x05
+#define NV_IGRAPH_XF_LTCTXA_L3_K 0x06
+#define NV_IGRAPH_XF_LTCTXA_L3_SPT 0x07
+#define NV_IGRAPH_XF_LTCTXA_L4_K 0x08
+#define NV_IGRAPH_XF_LTCTXA_L4_SPT 0x09
+#define NV_IGRAPH_XF_LTCTXA_L5_K 0x0a
+#define NV_IGRAPH_XF_LTCTXA_L5_SPT 0x0b
+#define NV_IGRAPH_XF_LTCTXA_L6_K 0x0c
+#define NV_IGRAPH_XF_LTCTXA_L6_SPT 0x0d
+#define NV_IGRAPH_XF_LTCTXA_L7_K 0x0e
+#define NV_IGRAPH_XF_LTCTXA_L7_SPT 0x0f
+#define NV_IGRAPH_XF_LTCTXA_EYED 0x10
+#define NV_IGRAPH_XF_LTCTXA_FR_AMB 0x11
+#define NV_IGRAPH_XF_LTCTXA_BR_AMB 0x12
+#define NV_IGRAPH_XF_LTCTXA_CM_COL 0x13
+#define NV_IGRAPH_XF_LTCTXA_BCM_COL 0x14
+#define NV_IGRAPH_XF_LTCTXA_FOG_K 0x15
+#define NV_IGRAPH_XF_LTCTXA_ZERO 0x16
+#define NV_IGRAPH_XF_LTCTXA_PT0 0x17
+#define NV_IGRAPH_XF_LTCTXA_FOGLIN 0x18
+
+#define NV_IGRAPH_XF_LTCTXB_L0_AMB 0x00
+#define NV_IGRAPH_XF_LTCTXB_L0_DIF 0x01
+#define NV_IGRAPH_XF_LTCTXB_L0_SPC 0x02
+#define NV_IGRAPH_XF_LTCTXB_L0_BAMB 0x03
+#define NV_IGRAPH_XF_LTCTXB_L0_BDIF 0x04
+#define NV_IGRAPH_XF_LTCTXB_L0_BSPC 0x05
+#define NV_IGRAPH_XF_LTCTXB_L1_AMB 0x06
+#define NV_IGRAPH_XF_LTCTXB_L1_DIF 0x07
+#define NV_IGRAPH_XF_LTCTXB_L1_SPC 0x08
+#define NV_IGRAPH_XF_LTCTXB_L1_BAMB 0x09
+#define NV_IGRAPH_XF_LTCTXB_L1_BDIF 0x0a
+#define NV_IGRAPH_XF_LTCTXB_L1_BSPC 0x0b
+#define NV_IGRAPH_XF_LTCTXB_L2_AMB 0x0c
+#define NV_IGRAPH_XF_LTCTXB_L2_DIF 0x0d
+#define NV_IGRAPH_XF_LTCTXB_L2_SPC 0x0e
+#define NV_IGRAPH_XF_LTCTXB_L2_BAMB 0x0f
+#define NV_IGRAPH_XF_LTCTXB_L2_BDIF 0x10
+#define NV_IGRAPH_XF_LTCTXB_L2_BSPC 0x11
+#define NV_IGRAPH_XF_LTCTXB_L3_AMB 0x12
+#define NV_IGRAPH_XF_LTCTXB_L3_DIF 0x13
+#define NV_IGRAPH_XF_LTCTXB_L3_SPC 0x14
+#define NV_IGRAPH_XF_LTCTXB_L3_BAMB 0x15
+#define NV_IGRAPH_XF_LTCTXB_L3_BDIF 0x16
+#define NV_IGRAPH_XF_LTCTXB_L3_BSPC 0x17
+#define NV_IGRAPH_XF_LTCTXB_L4_AMB 0x18
+#define NV_IGRAPH_XF_LTCTXB_L4_DIF 0x19
+#define NV_IGRAPH_XF_LTCTXB_L4_SPC 0x1a
+#define NV_IGRAPH_XF_LTCTXB_L4_BAMB 0x1b
+#define NV_IGRAPH_XF_LTCTXB_L4_BDIF 0x1c
+#define NV_IGRAPH_XF_LTCTXB_L4_BSPC 0x1d
+#define NV_IGRAPH_XF_LTCTXB_L5_AMB 0x1e
+#define NV_IGRAPH_XF_LTCTXB_L5_DIF 0x1f
+#define NV_IGRAPH_XF_LTCTXB_L5_SPC 0x20
+#define NV_IGRAPH_XF_LTCTXB_L5_BAMB 0x21
+#define NV_IGRAPH_XF_LTCTXB_L5_BDIF 0x22
+#define NV_IGRAPH_XF_LTCTXB_L5_BSPC 0x23
+#define NV_IGRAPH_XF_LTCTXB_L6_AMB 0x24
+#define NV_IGRAPH_XF_LTCTXB_L6_DIF 0x25
+#define NV_IGRAPH_XF_LTCTXB_L6_SPC 0x26
+#define NV_IGRAPH_XF_LTCTXB_L6_BAMB 0x27
+#define NV_IGRAPH_XF_LTCTXB_L6_BDIF 0x28
+#define NV_IGRAPH_XF_LTCTXB_L6_BSPC 0x29
+#define NV_IGRAPH_XF_LTCTXB_L7_AMB 0x2a
+#define NV_IGRAPH_XF_LTCTXB_L7_DIF 0x2b
+#define NV_IGRAPH_XF_LTCTXB_L7_SPC 0x2c
+#define NV_IGRAPH_XF_LTCTXB_L7_BAMB 0x2d
+#define NV_IGRAPH_XF_LTCTXB_L7_BDIF 0x2e
+#define NV_IGRAPH_XF_LTCTXB_L7_BSPC 0x2f
+#define NV_IGRAPH_XF_LTCTXB_PT1 0x30
+#define NV_IGRAPH_XF_LTCTXB_ONE 0x31
+#define NV_IGRAPH_XF_LTCTXB_VPOFFSET 0x32
+
+#define NV_IGRAPH_XF_LTC1_ZERO1 0x00
+#define NV_IGRAPH_XF_LTC1_l0 0x01
+#define NV_IGRAPH_XF_LTC1_Bl0 0x02
+#define NV_IGRAPH_XF_LTC1_PP 0x03
+#define NV_IGRAPH_XF_LTC1_r0 0x04
+#define NV_IGRAPH_XF_LTC1_r1 0x05
+#define NV_IGRAPH_XF_LTC1_r2 0x06
+#define NV_IGRAPH_XF_LTC1_r3 0x07
+#define NV_IGRAPH_XF_LTC1_r4 0x08
+#define NV_IGRAPH_XF_LTC1_r5 0x09
+#define NV_IGRAPH_XF_LTC1_r6 0x0a
+#define NV_IGRAPH_XF_LTC1_r7 0x0b
+#define NV_IGRAPH_XF_LTC1_L0 0x0c
+#define NV_IGRAPH_XF_LTC1_L1 0x0d
+#define NV_IGRAPH_XF_LTC1_L2 0x0e
+#define NV_IGRAPH_XF_LTC1_L3 0x0f
+#define NV_IGRAPH_XF_LTC1_L4 0x10
+#define NV_IGRAPH_XF_LTC1_L5 0x11
+#define NV_IGRAPH_XF_LTC1_L6 0x12
+#define NV_IGRAPH_XF_LTC1_L7 0x13
+
+
+#define NV2A_VERTEX_ATTR_POSITION 0
+#define NV2A_VERTEX_ATTR_WEIGHT 1
+#define NV2A_VERTEX_ATTR_NORMAL 2
+#define NV2A_VERTEX_ATTR_DIFFUSE 3
+#define NV2A_VERTEX_ATTR_SPECULAR 4
+#define NV2A_VERTEX_ATTR_FOG 5
+#define NV2A_VERTEX_ATTR_POINT_SIZE 6
+#define NV2A_VERTEX_ATTR_BACK_DIFFUSE 7
+#define NV2A_VERTEX_ATTR_BACK_SPECULAR 8
+#define NV2A_VERTEX_ATTR_TEXTURE0 9
+#define NV2A_VERTEX_ATTR_TEXTURE1 10
+#define NV2A_VERTEX_ATTR_TEXTURE2 11
+#define NV2A_VERTEX_ATTR_TEXTURE3 12
+#define NV2A_VERTEX_ATTR_RESERVED1 13
+#define NV2A_VERTEX_ATTR_RESERVED2 14
+#define NV2A_VERTEX_ATTR_RESERVED3 15
+
+#define NV2A_CRYSTAL_FREQ 16666666 // Was 13500000
+#define NV2A_NUM_CHANNELS 32
+#define NV2A_NUM_SUBCHANNELS 8
+#define NV2A_CACHE1_SIZE 128
+
+#define NV2A_MAX_BATCH_LENGTH 0x1FFFF
+#define NV2A_VERTEXSHADER_ATTRIBUTES 16
+#define NV2A_MAX_TEXTURES 4
+
+#define NV2A_MAX_TRANSFORM_PROGRAM_LENGTH 136
+#define NV2A_VERTEXSHADER_CONSTANTS 192
+#define NV2A_MAX_LIGHTS 8
+
+#define NV2A_LTCTXA_COUNT 26
+#define NV2A_LTCTXB_COUNT 52
+#define NV2A_LTC1_COUNT 20
+
+#endif
diff --git a/src/devices/video/nv2a_shaders.cpp b/src/devices/video/nv2a_shaders.cpp
index bd9865853..4d48772cb 100644
--- a/src/devices/video/nv2a_shaders.cpp
+++ b/src/devices/video/nv2a_shaders.cpp
@@ -759,7 +759,7 @@ STRUCT_VERTEX_DATA);
/* Return combined header + source */
qstring_append(header, qstring_get_str(body));
- QDECREF(body);
+ qobject_unref(body);
return header;
}
@@ -824,7 +824,7 @@ ShaderBinding* generate_shaders(const ShaderState state)
"geometry shader");
glAttachShader(program, geometry_shader);
- QDECREF(geometry_shader_code);
+ qobject_unref(geometry_shader_code);
vtx_prefix = 'v';
} else {
@@ -838,7 +838,7 @@ ShaderBinding* generate_shaders(const ShaderState state)
qstring_get_str(vertex_shader_code),
"vertex shader");
glAttachShader(program, vertex_shader);
- QDECREF(vertex_shader_code);
+ qobject_unref(vertex_shader_code);
/* Bind attributes for vertices */
@@ -859,7 +859,7 @@ ShaderBinding* generate_shaders(const ShaderState state)
"fragment shader");
glAttachShader(program, fragment_shader);
- QDECREF(fragment_shader_code);
+ qobject_unref(fragment_shader_code);
/* link the program */
@@ -952,6 +952,10 @@ ShaderBinding* generate_shaders(const ShaderState state)
snprintf(tmp, sizeof(tmp), "lightLocalAttenuation%d", i);
ret->light_local_attenuation_loc[i] = glGetUniformLocation(program, tmp);
}
+ for (i = 0; i < 8; i++) {
+ snprintf(tmp, sizeof(tmp), "clipRegion[%d]", i);
+ ret->clip_region_loc[i] = glGetUniformLocation(program, tmp);
+ }
return ret;
}
diff --git a/src/devices/video/nv2a_shaders.h b/src/devices/video/nv2a_shaders.h
index 7a6146dc7..f9b261567 100644
--- a/src/devices/video/nv2a_shaders.h
+++ b/src/devices/video/nv2a_shaders.h
@@ -22,12 +22,11 @@
#define HW_NV2A_SHADERS_H
#include "qstring.h"
-#include "CxbxKrnl/gloffscreen/gloffscreen.h"
+#include "CxbxKrnl/gloffscreen/gloffscreen.h" // For GLenum, etc
#include "nv2a_vsh.h"
#include "nv2a_psh.h"
-#include "nv2a_int.h"
-
+#include "nv2a_regs.h"
enum ShaderPrimitiveMode {
PRIM_TYPE_NONE,
@@ -108,6 +107,7 @@ typedef struct ShaderBinding {
GLint light_local_position_loc[NV2A_MAX_LIGHTS];
GLint light_local_attenuation_loc[NV2A_MAX_LIGHTS];
+ GLint clip_region_loc[8];
} ShaderBinding;
ShaderBinding* generate_shaders(const ShaderState state);
diff --git a/src/devices/video/nv2a_vsh.cpp b/src/devices/video/nv2a_vsh.cpp
index 38b9af830..5028dffe0 100644
--- a/src/devices/video/nv2a_vsh.cpp
+++ b/src/devices/video/nv2a_vsh.cpp
@@ -373,7 +373,7 @@ static QString* decode_opcode_input(const uint32_t *shader_token,
/* swizzle bits are next to the neg bit */
QString *swizzle_str = decode_swizzle(shader_token, (VshFieldName)((int)neg_field+1));
qstring_append(ret_str, qstring_get_str(swizzle_str));
- QDECREF(swizzle_str);
+ qobject_unref(swizzle_str);
}
return ret_str;
@@ -463,7 +463,7 @@ static QString* decode_token(const uint32_t *shader_token)
vsh_get_field(shader_token, FLD_A_R));
qstring_append(inputs_mac, ", ");
qstring_append(inputs_mac, qstring_get_str(input_a));
- QDECREF(input_a);
+ qobject_unref(input_a);
}
if (mac_opcode_params[mac].B) {
QString *input_b =
@@ -473,7 +473,7 @@ static QString* decode_token(const uint32_t *shader_token)
vsh_get_field(shader_token, FLD_B_R));
qstring_append(inputs_mac, ", ");
qstring_append(inputs_mac, qstring_get_str(input_b));
- QDECREF(input_b);
+ qobject_unref(input_b);
}
if (mac_opcode_params[mac].C) {
qstring_append(inputs_mac, ", ");
@@ -486,7 +486,7 @@ static QString* decode_token(const uint32_t *shader_token)
vsh_get_field(shader_token, FLD_OUT_MAC_MASK),
mac_opcode[mac],
qstring_get_str(inputs_mac));
- QDECREF(inputs_mac);
+ qobject_unref(inputs_mac);
} else {
ret = qstring_new();
}
@@ -507,11 +507,11 @@ static QString* decode_token(const uint32_t *shader_token)
qstring_append(ret, qstring_get_str(ilu_op));
- QDECREF(inputs_c);
- QDECREF(ilu_op);
+ qobject_unref(inputs_c);
+ qobject_unref(ilu_op);
}
- QDECREF(input_c);
+ qobject_unref(input_c);
return ret;
}
@@ -625,7 +625,16 @@ static const char* vsh_header =
"#define ARL(dest, src) dest = _ARL(_in(src).x)\n"
"int _ARL(float src)\n"
"{\n"
- " return int(floor(src));\n"
+ " /* Xbox GPU does specify rounding, OpenGL doesn't; so we need a bias.\n"
+ " * Example: We probably want to floor 16.99.. to 17, not 16.\n"
+ " * Source of error (why we get 16.99.. instead of 17.0) is typically\n"
+ " * vertex-attributes being normalized from a byte value to float:\n"
+ " * 17 / 255 = 0.06666.. so is this 0.06667 (ceil) or 0.06666 (floor)?\n"
+ " * Which value we get depends on the host GPU.\n"
+ " * If we multiply these rounded values by 255 later, we get:\n"
+ " * 17.00 (ARL result = 17) or 16.99 (ARL result = 16).\n"
+ " * We assume the intend was to get 17, so we add our bias to fix it. */\n"
+ " return int(floor(src + 0.001));\n"
"}\n"
"\n"
"#define SGE(dest, mask, src0, src1) dest.mask = _SGE(_in(src0), _in(src1)).mask\n"
@@ -663,13 +672,25 @@ static const char* vsh_header =
"#define EXP(dest, mask, src) dest.mask = _EXP(_in(src).x).mask\n"
"vec4 _EXP(float src)\n"
"{\n"
- " return vec4(exp2(src));\n"
+ " vec4 result;\n"
+ " result.x = exp2(floor(src));\n"
+ " result.y = src - floor(src);\n"
+ " result.z = exp2(src);\n"
+ " result.w = 1.0;\n"
+ " return result;\n"
"}\n"
"\n"
"#define LOG(dest, mask, src) dest.mask = _LOG(_in(src).x).mask\n"
"vec4 _LOG(float src)\n"
"{\n"
- " return vec4(log2(src));\n"
+ " float tmp = abs(src);\n"
+ " if (tmp == 0.0) { return vec4(-INFINITY, 1.0f, -INFINITY, 1.0f); }\n"
+ " vec4 result;\n"
+ " result.x = floor(log2(tmp));\n"
+ " result.y = tmp / exp2(floor(log2(tmp)));\n"
+ " result.z = log2(tmp);\n"
+ " result.w = 1.0;\n"
+ " return result;\n"
"}\n"
"\n"
"#define LIT(dest, mask, src) dest.mask = _LIT(_in(src)).mask\n"
@@ -711,7 +732,7 @@ void vsh_translate(uint16_t version,
qstring_append(body, "\n");
qstring_append(body, qstring_get_str(token_str));
qstring_append(body, "\n");
- QDECREF(token_str);
+ qobject_unref(token_str);
if (vsh_get_field(cur_token, FLD_FINAL)) {
has_final = true;
diff --git a/src/devices/video/qstring.h b/src/devices/video/qstring.h
index a97c7db39..ccf01bd2d 100644
--- a/src/devices/video/qstring.h
+++ b/src/devices/video/qstring.h
@@ -37,7 +37,7 @@ static QString* qstring_from_fmt(std::string fmt, ...) {
#define qstring_append_fmt(gs, fmt, ...) gs->append(*(std::string*)(qstring_from_fmt(fmt, ##__VA_ARGS__)))
#define qstring_get_length(gs) gs->size()
-#define QDECREF(X) // FIXME: Mostly free, but needs to be reviewed case-by-case
-#define QINCREF(X) // FIXME: Tricky!
+#define qobject_unref(X) // FIXME: Mostly free, but needs to be reviewed case-by-case
+#define qobject_ref(X) // FIXME: Tricky!
#endif