Transfer descriptor stuff
This commit is contained in:
ergo720
parent
d8c42fc79b
commit
756760d76b
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@ -109,19 +109,74 @@
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#define OHCI_ED_EN_SHIFT 7
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#define OHCI_ED_EN_MASK (0xF<<OHCI_ED_EN_SHIFT)
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#define OHCI_ED_D_SHIFT 11
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#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
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#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) // Direction
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#define OHCI_ED_S (1<<13)
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#define OHCI_ED_K (1<<14) // sKip
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#define OHCI_ED_F (1<<15) // Format
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#define OHCI_ED_MPS_SHIFT 16
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#define OHCI_ED_MPS_MASK (0x7FF<<OHCI_ED_MPS_SHIFT)
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#define OHCI_ED_MPS_MASK (0x7FF<<OHCI_ED_MPS_SHIFT) // MaximumPacketSize
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/* Flags in the HeadP field of an ED */
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#define OHCI_ED_H 1 // Halted
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#define OHCI_ED_C 2
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/* Mask for the four least significant bits in an ED address */
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/* Bitfields for the first word of a TD */
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#define OHCI_TD_R (1<<18) // bufferRounding
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#define OHCI_TD_DP_SHIFT 19
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#define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) // Direction-Pid
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#define OHCI_TD_DI_SHIFT 21
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#define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
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#define OHCI_TD_T0 (1<<24)
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#define OHCI_TD_T1 (1<<25)
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#define OHCI_TD_EC_SHIFT 26
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#define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
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#define OHCI_TD_CC_SHIFT 28
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#define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
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/* Mask the four least significant bits in an ED address */
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#define OHCI_DPTR_MASK 0xFFFFFFF0
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#define OHCI_BM(val, field) \
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(((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
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#define OHCI_SET_BM(val, field, newval) do { \
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val &= ~OHCI_##field##_MASK; \
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val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
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} while(0)
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/* Indicates the direction of data flow as specified by the TD */
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#define OHCI_TD_DIR_SETUP 0x0 // to endpoint
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#define OHCI_TD_DIR_OUT 0x1 // to endpoint
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#define OHCI_TD_DIR_IN 0x2 // from endpoint
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#define OHCI_TD_DIR_RESERVED 0x3
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#define OHCI_CC_NOERROR 0x0
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#define OHCI_CC_CRC 0x1
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#define OHCI_CC_BITSTUFFING 0x2
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#define OHCI_CC_DATATOGGLEMISMATCH 0x3
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#define OHCI_CC_STALL 0x4
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#define OHCI_CC_DEVICENOTRESPONDING 0x5
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#define OHCI_CC_PIDCHECKFAILURE 0x6
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#define OHCI_CC_UNDEXPETEDPID 0x7
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#define OHCI_CC_DATAOVERRUN 0x8
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#define OHCI_CC_DATAUNDERRUN 0x9
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#define OHCI_CC_BUFFEROVERRUN 0xC
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#define OHCI_CC_BUFFERUNDERRUN 0xD
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#define USB_TOKEN_SETUP 0x2D
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#define USB_TOKEN_IN 0x69 // device -> host
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#define USB_TOKEN_OUT 0xE1 // host -> device
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#define USB_RET_SUCCESS (0)
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#define USB_RET_NODEV (-1)
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#define USB_RET_NAK (-2)
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#define USB_RET_STALL (-3)
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#define USB_RET_BABBLE (-4)
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#define USB_RET_IOERROR (-5)
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#define USB_RET_ASYNC (-6)
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#define USB_RET_ADD_TO_QUEUE (-7)
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#define USB_RET_REMOVE_FROM_QUEUE (-8)
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#define USB_HZ 12000000
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#define USB_SPEED_LOW 0
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@ -179,7 +234,7 @@ void OHCI::OHCI_FrameBoundaryWorker()
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if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
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if (ohci->async_td) {
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usb_cancel_packet(&ohci->usb_packet);
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ohci->async_td = 0;
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m_AsyncTD = xbnull;
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}
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OHCI_StopEndpoints();
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}
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@ -243,6 +298,7 @@ void OHCI::OHCI_FatalError()
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OHCI_SetInterrupt(OHCI_INTR_UE);
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OHCI_BusStop();
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DbgPrintf("Ohci: an unrecoverable error occoured!\n");
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}
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bool OHCI::OHCI_ReadHCCA(xbaddr Paddr, OHCI_HCCA* Hcca)
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@ -291,6 +347,83 @@ bool OHCI::OHCI_WriteED(xbaddr Paddr, OHCI_ED* Ed)
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return OHCI_WriteDwords(Paddr + OffsetOfHeadP, reinterpret_cast<uint32_t*>(reinterpret_cast<uint8_t*>(Ed) + OffsetOfHeadP), 1);
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}
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bool OHCI::OHCI_ReadTD(xbaddr Paddr, OHCI_TD* Td)
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{
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return OHCI_GetDwords(Paddr, reinterpret_cast<uint32_t*>(Td), sizeof(*Td) >> 2); // TD is 16 bytes large
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}
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bool OHCI::OHCI_WriteTD(xbaddr Paddr, OHCI_TD* Td)
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{
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return OHCI_WriteDwords(Paddr, reinterpret_cast<uint32_t*>(Td), sizeof(*Td) >> 2);
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}
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bool OHCI::OHCI_CopyTD(OHCI_TD* Td, uint8_t* Buffer, int Length, bool bIsWrite)
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{
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uint32_t ptr, n;
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// Figure out if we are crossing a 4K page boundary
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ptr = Td->CurrentBufferPointer;
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n = 0x1000 - (ptr & 0xFFF);
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if (n > Length) {
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n = Length;
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}
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if (OHCI_FindAndCopyTD(ptr, Buffer, n, bIsWrite)) {
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return true; // error
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}
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if (n == Length) {
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return false; // no bytes left to copy
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}
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// From the standard: "If during the data transfer the buffer address contained in the HC<48>fs working copy of
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// CurrentBufferPointer crosses a 4K boundary, the upper 20 bits of BufferEnd are copied to the
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// working value of CurrentBufferPointer causing the next buffer address to be the 0th byte in the
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// same 4K page that contains the last byte of the buffer."
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ptr = Td->BufferEnd & ~0xFFFu;
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Buffer += n;
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if (OHCI_FindAndCopyTD(ptr, Buffer, Length - n, bIsWrite)) {
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return true; // error
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}
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return false;
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}
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bool OHCI::OHCI_FindAndCopyTD(xbaddr Paddr, uint8_t* Buffer, int Length, bool bIsWrite)
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{
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// ergo720: the buffer pointed to by Paddr can be anywhere in memory (it depends on how the xbe has
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// allocated it) so, sadly, we cannot make any assumptions here regarding its location like we did
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// in OHCI_ReadHCCA and the problem with VirtualAlloc can arise this time. Because of the hack in
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// TranslateVAddrToPAddr, VirtualAlloc allocations are identity mapped and addresses below 0x4000000
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// (Xbox) or 0x8000000 (Chihiro, Devkit) cannot be used by the VMManager for anything but to allocate
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// xbe sections. This means that if Paddr is higher than the maximum possible physical address, then
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// we know it's an identity mapped address, otherwise it's a contiguous address
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int offset = 0;
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if (Paddr == xbnull) {
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return true; // error
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}
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if (g_bIsRetail) {
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if (Paddr < XBOX_MEMORY_SIZE) {
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offset = CONTIGUOUS_MEMORY_BASE;
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}
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}
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else {
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if (Paddr < CHIHIRO_MEMORY_SIZE) {
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offset = CONTIGUOUS_MEMORY_BASE;
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}
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}
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if (bIsWrite) {
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std::memcpy(reinterpret_cast<void*>(Paddr + offset), Buffer, Length);
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}
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else {
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std::memcpy(Buffer, reinterpret_cast<void*>(Paddr + offset), Length);
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}
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return false;
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}
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bool OHCI::OHCI_GetDwords(xbaddr Paddr, uint32_t* Buffer, int Number)
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{
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if (Paddr != xbnull) {
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@ -343,9 +476,9 @@ int OHCI::OHCI_ServiceEDlist(xbaddr Head, int Completion)
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if ((ed.HeadP & OHCI_ED_H) || (ed.Flags & OHCI_ED_K)) { // halted or skip
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// Cancel pending packets for ED that have been paused
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xbaddr addr = ed.HeadP & OHCI_DPTR_MASK;
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if (AsyncTD && addr == AsyncTD) {
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if (m_AsyncTD && addr == m_AsyncTD) {
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usb_cancel_packet(&ohci->usb_packet);
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AsyncTD = xbnull;
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m_AsyncTD = xbnull;
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USB_DeviceEPstopped(m_UsbPacket.Endpoint->Dev, m_UsbPacket.Endpoint);
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}
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continue;
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@ -366,12 +499,13 @@ int OHCI::OHCI_ServiceEDlist(xbaddr Head, int Completion)
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if ((ed.Flags & OHCI_ED_F) == 0) {
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// Handle control, interrupt or bulk endpoints
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if (ohci_service_td(ohci, &ed))
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if (OHCI_ServiceTD(&ed)) {
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break;
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}
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}
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else {
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// Handle isochronous endpoints
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if (ohci_service_iso_td(ohci, &ed, completion))
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if (ohci_service_iso_td(ohci, &ed, Completion))
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break;
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}
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}
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@ -386,6 +520,250 @@ int OHCI::OHCI_ServiceEDlist(xbaddr Head, int Completion)
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return active;
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}
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int OHCI::OHCI_ServiceTD(OHCI_ED* Ed)
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{
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int direction;
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size_t length = 0, packetlen = 0;
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#ifdef DEBUG_PACKET
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const char *str = NULL;
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#endif
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int pid;
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int ret;
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int i;
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USBDev* dev;
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USBEndpoint* ep;
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OHCI_TD td;
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xbaddr addr;
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int flag_r;
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int completion;
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addr = Ed->HeadP & OHCI_DPTR_MASK;
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// See if this TD has already been submitted to the device
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completion = (addr == m_AsyncTD);
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if (completion && !m_AsyncComplete) { // ??
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#ifdef DEBUG_PACKET
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DPRINTF("Skipping async TD\n");
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DbgPrintf("Skipping async TD\n");
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#endif
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return 1;
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}
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if (OHCI_ReadTD(addr, &td)) {
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EmuWarning("Ohci: TD read error at physical address 0x%X", addr);
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OHCI_FatalError();
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return 0;
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}
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// From the standard: "This 2-bit field indicates the direction of data flow and the PID
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// to be used for the token. This field is only relevant to the HC if the D field in the ED
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// was set to 00b or 11b indicating that the PID determination is deferred to the TD."
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direction = OHCI_BM(Ed->Flags, ED_D);
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switch (direction) {
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case OHCI_TD_DIR_OUT:
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case OHCI_TD_DIR_IN:
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// Same value
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break;
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default:
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direction = OHCI_BM(td.Flags, TD_DP);
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}
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switch (direction) {
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case OHCI_TD_DIR_IN:
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#ifdef DEBUG_PACKET
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str = "in";
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#endif
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pid = USB_TOKEN_IN;
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break;
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case OHCI_TD_DIR_OUT:
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#ifdef DEBUG_PACKET
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str = "out";
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#endif
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pid = USB_TOKEN_OUT;
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break;
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case OHCI_TD_DIR_SETUP:
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#ifdef DEBUG_PACKET
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str = "setup";
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#endif
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pid = USB_TOKEN_SETUP;
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break;
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default:
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EmuWarning("Ohci: bad direction");
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return 1;
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}
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// Check if this TD has a buffer of user data to transfer
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if (td.CurrentBufferPointer && td.BufferEnd) {
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if ((td.CurrentBufferPointer & 0xFFFFF000) != (td.BufferEnd & 0xFFFFF000)) {
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// the buffer crosses a 4K page boundary
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length = (td.BufferEnd & 0xFFF) + 0x1001 - (td.CurrentBufferPointer & 0xFFF);
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}
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else {
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// the buffer is within a single page
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length = (td.BufferEnd - td.CurrentBufferPointer) + 1;
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}
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packetlen = length;
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if (length && direction != OHCI_TD_DIR_IN) {
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// The endpoint may not allow us to transfer it all now
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packetlen = (Ed->Flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT;
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if (packetlen > length) {
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packetlen = length;
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}
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if (!completion) {
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if (OHCI_CopyTD(&td, m_UsbBuffer, packetlen, false)) {
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OHCI_FatalError();
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}
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}
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}
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}
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flag_r = (td.Flags & OHCI_TD_R) != 0;
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#ifdef DEBUG_PACKET
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DPRINTF(" TD @ 0x%.8x %" PRId64 " of %" PRId64
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" bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
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addr, (int64_t)pktlen, (int64_t)len, str, flag_r, td.cbp, td.be);
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if (pktlen > 0 && dir != OHCI_TD_DIR_IN) {
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DPRINTF(" data:");
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for (i = 0; i < pktlen; i++) {
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printf(" %.2x", ohci->usb_buf[i]);
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}
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DPRINTF("\n");
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}
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#endif
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if (completion) {
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m_AsyncTD = 0;
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m_AsyncComplete = 0;
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}
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else {
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if (m_AsyncTD) {
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// From XQEMU: "??? The hardware should allow one active packet per endpoint.
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// We only allow one active packet per controller. This should be sufficient
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// as long as devices respond in a timely manner."
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#ifdef DEBUG_PACKET
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DPRINTF("Too many pending packets\n");
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#endif
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DbgPrintf("Too many pending packets\n");
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return 1;
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}
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dev = ohci_find_device(ohci, OHCI_BM(Ed->Flags, ED_FA));
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ep = usb_ep_get(dev, pid, OHCI_BM(Ed->Flags, ED_EN));
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usb_packet_setup(&m_UsbPacket, pid, ep, 0, addr, !flag_r, OHCI_BM(td.Flags, TD_DI) == 0);
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usb_packet_addbuf(&m_UsbPacket, ohci->usb_buf, packetlen);
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usb_handle_packet(dev, &m_UsbPacket);
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#ifdef DEBUG_PACKET
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DPRINTF("status=%d\n", ohci->usb_packet.status);
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#endif
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if (m_UsbPacket.status == USB_RET_ASYNC) {
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usb_device_flush_ep_queue(dev, ep);
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m_AsyncTD = addr;
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return 1;
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}
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}
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if (m_UsbPacket.status == USB_RET_SUCCESS) {
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ret = m_UsbPacket.actual_length;
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}
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else {
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ret = m_UsbPacket.status;
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}
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if (ret >= 0) {
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if (direction == OHCI_TD_DIR_IN) {
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if (OHCI_CopyTD(&td, m_UsbBuffer, ret, true)) {
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OHCI_FatalError();
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}
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#ifdef DEBUG_PACKET
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DPRINTF(" data:");
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for (i = 0; i < ret; i++)
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printf(" %.2x", ohci->usb_buf[i]);
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DPRINTF("\n");
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#endif
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}
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else {
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ret = packetlen;
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}
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}
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if (ret >= 0) {
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if ((td.CurrentBufferPointer & 0xFFF) + ret > 0xFFF) {
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td.CurrentBufferPointer = (td.BufferEnd & ~0xFFF) + ((td.CurrentBufferPointer + ret) & 0xFFF);
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}
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else {
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td.CurrentBufferPointer += ret;
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}
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}
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// Writeback
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if (ret == packetlen || (direction == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
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// Transmission succeeded
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if (ret == length) {
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td.CurrentBufferPointer = 0;
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}
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td.Flags |= OHCI_TD_T1;
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td.Flags ^= OHCI_TD_T0;
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OHCI_SET_BM(td.Flags, TD_CC, OHCI_CC_NOERROR);
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OHCI_SET_BM(td.Flags, TD_EC, 0);
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if ((direction != OHCI_TD_DIR_IN) && (ret != length)) {
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// Partial packet transfer: TD not ready to retire yet
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goto exit_no_retire;
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}
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// Setting ED_C is part of the TD retirement process
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Ed->HeadP &= ~OHCI_ED_C;
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if (td.Flags & OHCI_TD_T0)
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Ed->HeadP |= OHCI_ED_C;
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}
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else {
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if (ret >= 0) {
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DbgPrintf("Ohci: Underrun\n");
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OHCI_SET_BM(td.Flags, TD_CC, OHCI_CC_DATAUNDERRUN);
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}
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else {
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switch (ret) {
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case USB_RET_IOERROR:
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case USB_RET_NODEV:
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DbgPrintf("Ohci: Received DEV ERROR\n");
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OHCI_SET_BM(td.Flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
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break;
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case USB_RET_NAK:
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DbgPrintf("Ohci: Received NAK\n");
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return 1;
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case USB_RET_STALL:
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DbgPrintf("Ohci: Received STALL\n");
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OHCI_SET_BM(td.Flags, TD_CC, OHCI_CC_STALL);
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break;
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case USB_RET_BABBLE:
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DbgPrintf("Ohci: Received BABBLE\n");
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OHCI_SET_BM(td.Flags, TD_CC, OHCI_CC_DATAOVERRUN);
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break;
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default:
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DbgPrintf("Ohci: Bad device response %d\n", ret);
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OHCI_SET_BM(td.Flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
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OHCI_SET_BM(td.Flags, TD_EC, 3);
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}
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}
|
||||
Ed->HeadP |= OHCI_ED_H;
|
||||
}
|
||||
|
||||
// Retire this TD
|
||||
Ed->HeadP &= ~OHCI_DPTR_MASK;
|
||||
Ed->HeadP |= td.NextTD & OHCI_DPTR_MASK;
|
||||
td.NextTD = m_Registers.HcDoneHead;
|
||||
m_Registers.HcDoneHead = addr;
|
||||
i = OHCI_BM(td.Flags, TD_DI);
|
||||
if (i < m_DoneCount)
|
||||
m_DoneCount = i;
|
||||
if (OHCI_BM(td.Flags, TD_CC) != OHCI_CC_NOERROR)
|
||||
m_DoneCount = 0;
|
||||
|
||||
exit_no_retire:
|
||||
if (OHCI_WriteTD(addr, &td)) {
|
||||
OHCI_FatalError();
|
||||
return 1;
|
||||
}
|
||||
return OHCI_BM(td.Flags, TD_CC) != OHCI_CC_NOERROR;
|
||||
}
|
||||
|
||||
void OHCI::OHCI_StateReset()
|
||||
{
|
||||
// The usb state can be USB_Suspend if it is a software reset, and USB_Reset if it is a hardware
|
||||
|
|
@ -431,9 +809,9 @@ void OHCI::OHCI_StateReset()
|
|||
USB_PortReset(&Port->UsbPort);
|
||||
}
|
||||
}
|
||||
if (AsyncTD) {
|
||||
if (m_AsyncTD) {
|
||||
usb_cancel_packet(&ohci->usb_packet);
|
||||
AsyncTD = xbnull;
|
||||
m_AsyncTD = xbnull;
|
||||
}
|
||||
|
||||
OHCI_StopEndpoints();
|
||||
|
|
|
|||
|
|
@ -61,6 +61,15 @@ typedef struct _OHCI_ED {
|
|||
}
|
||||
OHCI_ED;
|
||||
|
||||
/* general transfer descriptor */
|
||||
typedef struct _OHCI_TD {
|
||||
uint32_t Flags;
|
||||
uint32_t CurrentBufferPointer;
|
||||
uint32_t NextTD;
|
||||
uint32_t BufferEnd;
|
||||
}
|
||||
OHCI_TD;
|
||||
|
||||
/* enum indicating the current HC state */
|
||||
typedef enum _OHCI_State
|
||||
{
|
||||
|
|
@ -153,6 +162,8 @@ class OHCI
|
|||
uint64_t m_TicksPerUsbTick;
|
||||
// pending usb packet to process
|
||||
USBPacket m_UsbPacket;
|
||||
// temporary buffer that holds the user data to transfer in a packet
|
||||
uint8_t m_UsbBuffer[8192];
|
||||
// ergo720: I believe it's the value of HcControl in the last frame
|
||||
uint32_t old_ctl;
|
||||
// irq number
|
||||
|
|
@ -161,7 +172,9 @@ class OHCI
|
|||
// -> num of frames to wait before generating an interrupt for this TD
|
||||
int m_DoneCount;
|
||||
// the address of the pending TD
|
||||
xbaddr AsyncTD;
|
||||
xbaddr m_AsyncTD;
|
||||
// ergo720: I think it signals that a TD has been processed completely
|
||||
bool m_AsyncComplete;
|
||||
|
||||
// EOF callback wrapper
|
||||
static void OHCI_FrameBoundaryWrapper(void* pVoid);
|
||||
|
|
@ -210,12 +223,22 @@ class OHCI
|
|||
bool OHCI_ReadED(xbaddr Paddr, OHCI_ED* Ed);
|
||||
// write an ED in memory
|
||||
bool OHCI_WriteED(xbaddr Paddr, OHCI_ED* Ed);
|
||||
// read an TD in memory
|
||||
bool OHCI_ReadTD(xbaddr Paddr, OHCI_TD* Td);
|
||||
// write a TD in memory
|
||||
bool OHCI_WriteTD(xbaddr Paddr, OHCI_TD* Td);
|
||||
// read/write the contents of a TD from/to main memory
|
||||
bool OHCI_CopyTD(OHCI_TD* Td, uint8_t* Buffer, int Length, bool bIsWrite);
|
||||
// find a TD buffer in memory and copy it
|
||||
bool OHCI_FindAndCopyTD(xbaddr Paddr, uint8_t* Buffer, int Length, bool bIsWrite);
|
||||
// read an array of DWORDs in memory
|
||||
bool OHCI_GetDwords(xbaddr Paddr, uint32_t* Buffer, int Number);
|
||||
// write an array of DWORDs in memory
|
||||
bool OHCI_WriteDwords(xbaddr Paddr, uint32_t* Buffer, int Number);
|
||||
//
|
||||
// process an ED list
|
||||
int OHCI_ServiceEDlist(xbaddr Head, int Completion);
|
||||
// process a TD. Returns nonzero to terminate processing of this endpoint
|
||||
int OHCI_ServiceTD(OHCI_ED* Ed);
|
||||
|
||||
// register a port with the HC
|
||||
void USB_RegisterPort(USBPort* Port, int Index, int SpeedMask);
|
||||
|
|
|
|||
Loading…
Reference in New Issue