From 6d9d89c5f1368a5869e1b18bfca14a391f167d59 Mon Sep 17 00:00:00 2001 From: patrickvl Date: Sun, 28 Jan 2018 17:51:38 +0100 Subject: [PATCH] Picked some comments from OpenXbox --- src/devices/video/EmuNV2A_PBUS.cpp | 5 ++++- src/devices/video/EmuNV2A_PCRTC.cpp | 4 +++- src/devices/video/EmuNV2A_PFB.cpp | 3 ++- src/devices/video/EmuNV2A_PMC.cpp | 1 + src/devices/video/EmuNV2A_PRAMDAC.cpp | 3 +++ src/devices/video/EmuNV2A_PRMCIO.cpp | 14 ++++++++++++++ src/devices/video/EmuNV2A_PRMVIO.cpp | 2 ++ 7 files changed, 29 insertions(+), 3 deletions(-) diff --git a/src/devices/video/EmuNV2A_PBUS.cpp b/src/devices/video/EmuNV2A_PBUS.cpp index f44e483c4..604731bb2 100644 --- a/src/devices/video/EmuNV2A_PBUS.cpp +++ b/src/devices/video/EmuNV2A_PBUS.cpp @@ -3,13 +3,15 @@ DEVICE_READ32(PBUS) DEVICE_READ32_SWITCH() { case NV_PBUS_PCI_NV_0: result = 0x10de; // PCI_VENDOR_ID_NVIDIA (?where to return PCI_DEVICE_ID_NVIDIA_NV2A = 0x01b7) - + // TODO : result = pci_get_long(d->dev.config + PCI_VENDOR_ID); break; case NV_PBUS_PCI_NV_1: result = 1; // NV_PBUS_PCI_NV_1_IO_SPACE_ENABLED + // TODO : result = pci_get_long(d->dev.config + PCI_COMMAND); break; case NV_PBUS_PCI_NV_2: result = (0x02 << 24) | 161; // PCI_CLASS_DISPLAY_3D (0x02) Rev 161 (0xA1) + // TODO : result = pci_get_long(d->dev.config + PCI_CLASS_REVISION); break; default: @@ -25,6 +27,7 @@ DEVICE_WRITE32(PBUS) switch(addr) { case NV_PBUS_PCI_NV_1: // TODO : Handle write on NV_PBUS_PCI_NV_1 with 1 (NV_PBUS_PCI_NV_1_IO_SPACE_ENABLED) + 4 (NV_PBUS_PCI_NV_1_BUS_MASTER_ENABLED) + // pci_set_long(d->dev.config + PCI_COMMAND, val); break; default: DEBUG_WRITE32_UNHANDLED(PBUS); // TODO : DEVICE_WRITE32_REG(pbus); diff --git a/src/devices/video/EmuNV2A_PCRTC.cpp b/src/devices/video/EmuNV2A_PCRTC.cpp index 46b59e634..fdf01a1c8 100644 --- a/src/devices/video/EmuNV2A_PCRTC.cpp +++ b/src/devices/video/EmuNV2A_PCRTC.cpp @@ -33,7 +33,9 @@ DEVICE_WRITE32(PCRTC) update_irq(); break; case NV_PCRTC_START: - pcrtc.start = value &= 0x07FFFFFF; + value &= 0x07FFFFFF; + // assert(val < memory_region_size(d->vram)); + pcrtc.start = value; break; default: diff --git a/src/devices/video/EmuNV2A_PFB.cpp b/src/devices/video/EmuNV2A_PFB.cpp index 03f6aa213..7e17c92ef 100644 --- a/src/devices/video/EmuNV2A_PFB.cpp +++ b/src/devices/video/EmuNV2A_PFB.cpp @@ -2,6 +2,7 @@ DEVICE_READ32(PFB) { DEVICE_READ32_SWITCH() { case NV_PFB_CFG0: + /* 3-4 memory partitions. The debug bios checks this. */ result = 3; // = NV_PFB_CFG0_PART_4 break; case NV_PFB_CSTATUS: @@ -11,7 +12,7 @@ DEVICE_READ32(PFB) } break; case NV_PFB_WBC: - result = 0; // = !NV_PFB_WBC_FLUSH + result = 0; // = !NV_PFB_WBC_FLUSH /* Flush not pending. */ break; default: DEVICE_READ32_REG(pfb); diff --git a/src/devices/video/EmuNV2A_PMC.cpp b/src/devices/video/EmuNV2A_PMC.cpp index f21260070..95050ba32 100644 --- a/src/devices/video/EmuNV2A_PMC.cpp +++ b/src/devices/video/EmuNV2A_PMC.cpp @@ -26,6 +26,7 @@ DEVICE_WRITE32(PMC) { switch(addr) { case NV_PMC_INTR_0: + /* the bits of the interrupts to clear are wrtten */ pmc.pending_interrupts &= ~value; update_irq(); break; diff --git a/src/devices/video/EmuNV2A_PRAMDAC.cpp b/src/devices/video/EmuNV2A_PRAMDAC.cpp index b9e8f8b12..be91e6242 100644 --- a/src/devices/video/EmuNV2A_PRAMDAC.cpp +++ b/src/devices/video/EmuNV2A_PRAMDAC.cpp @@ -24,6 +24,9 @@ DEVICE_READ32(PRAMDAC) break; } + /* Surprisingly, QEMU doesn't handle unaligned access for you properly */ + // result >>= 32 - 8 * size - 8 * (addr & 3); + DEVICE_READ32_END(PRAMDAC); } diff --git a/src/devices/video/EmuNV2A_PRMCIO.cpp b/src/devices/video/EmuNV2A_PRMCIO.cpp index 381e64132..0505b4359 100644 --- a/src/devices/video/EmuNV2A_PRMCIO.cpp +++ b/src/devices/video/EmuNV2A_PRMCIO.cpp @@ -1,5 +1,6 @@ DEVICE_READ32(PRMCIO) { + // vga_ioport_read : DEVICE_READ32_SWITCH() { case VGA_CRT_IM: case VGA_CRT_IC: @@ -23,6 +24,19 @@ DEVICE_READ32(PRMCIO) DEVICE_WRITE32(PRMCIO) { switch (addr) { +#if 0 // TODO : Enable + case VGA_ATT_W: + /* Cromwell sets attrs without enabling VGA_AR_ENABLE_DISPLAY + * (which should result in a blank screen). + * Either nvidia's hardware is lenient or it is set through + * something else. The former seems more likely. + */ + if (d->vga.ar_flip_flop == 0) { + value |= VGA_AR_ENABLE_DISPLAY; + } + break; +#endif + // vga_ioport_write : case VGA_CRT_IM: case VGA_CRT_IC: prmcio.cr_index = value; diff --git a/src/devices/video/EmuNV2A_PRMVIO.cpp b/src/devices/video/EmuNV2A_PRMVIO.cpp index 7527e00e4..290252cb1 100644 --- a/src/devices/video/EmuNV2A_PRMVIO.cpp +++ b/src/devices/video/EmuNV2A_PRMVIO.cpp @@ -1,5 +1,6 @@ DEVICE_READ32(PRMVIO) { + // vga_ioport_read DEVICE_READ32_SWITCH() { default: DEBUG_READ32_UNHANDLED(PRMVIO); // TODO : DEVICE_READ32_REG(prmvio); @@ -11,6 +12,7 @@ DEVICE_READ32(PRMVIO) DEVICE_WRITE32(PRMVIO) { + // vga_ioport_write switch (addr) { default: DEBUG_WRITE32_UNHANDLED(PRMVIO); // TODO : DEVICE_WRITE32_REG(prmvio);