Began porting NV2A emulation from XQEMU.
This commit is contained in:
Luke Usher
parent
d424f0b004
commit
588aa5745b
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@ -28,6 +28,11 @@
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// *
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// * (c) 2002-2003 Aaron Robinson <caustik@caustik.com>
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// * (c) 2016 Luke Usher <luke.usher@outlook.com>
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// *
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// * EmuNV2A.cpp is heavily based on code from XQEMU
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// * (c) XQEMU Team
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// * https://github.com/espes/xqemu/blob/xbox/hw/xbox/nv2a.c
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// *
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// * All rights reserved
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// *
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// ******************************************************************
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@ -41,9 +46,80 @@
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#include "EmuNV2A.h"
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#include "nv2a_int.h" // from https://github.com/espes/xqemu/tree/xbox/hw/xbox
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struct {
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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} pmc;
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struct {
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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//TODO:
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// QemuThread puller_thread;
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// Cache1State cache1;
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uint32_t regs[0x2000];
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} pfifo;
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struct {
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uint32_t regs[0x1000];
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} pvideo;
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struct {
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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uint32_t numerator;
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uint32_t denominator;
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uint32_t alarm_time;
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} ptimer;
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struct {
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uint32_t regs[0x1000];
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} pfb;
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struct {
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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uint32_t start;
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} pcrtc;
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struct {
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uint32_t core_clock_coeff;
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uint64_t core_clock_freq;
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uint32_t memory_clock_coeff;
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uint32_t video_clock_coeff;
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} pramdac;
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static void update_irq()
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{
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/* PFIFO */
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if (pfifo.pending_interrupts & pfifo.enabled_interrupts) {
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pmc.pending_interrupts |= NV_PMC_INTR_0_PFIFO;
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}
else {
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pmc.pending_interrupts &= ~NV_PMC_INTR_0_PFIFO;
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}
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if (pcrtc.pending_interrupts & pcrtc.enabled_interrupts) {
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pmc.pending_interrupts |= NV_PMC_INTR_0_PCRTC;
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}
else {
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pmc.pending_interrupts &= ~NV_PMC_INTR_0_PCRTC;
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}
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/* TODO PGRAPH */
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/*
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if (pgraph.pending_interrupts & pgraph.enabled_interrupts) {
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pmc.pending_interrupts |= NV_PMC_INTR_0_PGRAPH;
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}
else {
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pmc.pending_interrupts &= ~NV_PMC_INTR_0_PGRAPH;
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} */
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if (pmc.pending_interrupts && pmc.enabled_interrupts) {
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// TODO Raise IRQ
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EmuWarning("EmuNV2A: Raise IRQ Not Implemented");
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}
else {
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// TODO: Cancel IRQ
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EmuWarning("EmuNV2A: Cancel IRQ Not Implemented");
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}
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}
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uint32_t EmuNV2A_PMC_Read32(uint32_t addr)
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{
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switch (addr) {
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case NV_PMC_BOOT_0: // chipset and stepping: NV2A, A02, Rev 0
return 0x02A000A2;
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case NV_PMC_INTR_0:
return pmc.pending_interrupts;
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case NV_PMC_INTR_EN_0:
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return pmc.enabled_interrupts;
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default:
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EmuWarning("EmuNV2A_PMC_Read32: Unknown Read Address %08X", addr);
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}
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@ -57,7 +133,7 @@ uint32_t EmuNV2A_PBUS_Read32(uint32_t addr)
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case NV_PBUS_PCI_NV_0:
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return 0x10de; // PCI_VENDOR_ID_NVIDIA
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case NV_PBUS_PCI_NV_2:
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return 0x0; // NV_PBUS_PCI_NV_2_REVISION_ID ??
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return (0x02 << 24) | 161; // PCI_CLASS_DISPLAY_3D (0x02) Rev 161 (0xA1)
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default:
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EmuWarning("EmuNV2A_PBUS_Read32: Unknown Read Address %08X", addr);
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}
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@ -98,8 +174,10 @@ uint32_t EmuNV2A_PRMA_Read32(uint32_t addr)
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uint32_t EmuNV2A_PVIDEO_Read32(uint32_t addr)
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{
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switch (addr) {
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case NV_PVIDEO_STOP:
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return 0;
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default:
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EmuWarning("EmuNV2A_PVIDEO_Read32: Unknown Read Address %08X", addr);
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return pvideo.regs[addr];
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}
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return 0;
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@ -198,6 +276,12 @@ uint32_t EmuNV2A_PGRAPH_Read32(uint32_t addr)
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uint32_t EmuNV2A_PCRTC_Read32(uint32_t addr)
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{
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switch (addr) {
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case NV_PCRTC_INTR_0:
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return pcrtc.pending_interrupts;
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case NV_PCRTC_INTR_EN_0:
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return pcrtc.enabled_interrupts;
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case NV_PCRTC_START:
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return pcrtc.start;
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default:
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EmuWarning("EmuNV2A_PCRTC_Read32: Unknown Read Address %08X", addr);
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}
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@ -217,11 +301,27 @@ uint32_t EmuNV2A_PRMCIO_Read32(uint32_t addr)
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uint32_t EmuNV2A_PRAMDAC_Read32(uint32_t addr)
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{
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switch (addr) {
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default:
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EmuWarning("EmuNV2A_PRAMDAC_Read32: Unknown Read Address %08X", addr);
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switch (addr & 3) {
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case NV_PRAMDAC_NVPLL_COEFF:
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return pramdac.core_clock_coeff;
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break;
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case NV_PRAMDAC_MPLL_COEFF:
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return pramdac.memory_clock_coeff;
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break;
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case NV_PRAMDAC_VPLL_COEFF:
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return pramdac.video_clock_coeff;
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break;
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case NV_PRAMDAC_PLL_TEST_COUNTER:
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/* emulated PLLs locked instantly? */
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return NV_PRAMDAC_PLL_TEST_COUNTER_VPLL2_LOCK
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| NV_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCK
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| NV_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCK
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| NV_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCK;
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break;
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default:
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EmuWarning("EmuNV2A_PRAMDAC_Read32: Unknown Read Address %08X", addr);
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}
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return 0;
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}
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@ -309,6 +409,13 @@ uint32_t EmuNV2A_Read32(uint32_t addr)
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void EmuNV2A_PMC_Write32(uint32_t addr, uint32_t value)
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{
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switch (addr) {
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case NV_PMC_INTR_0:
pmc.pending_interrupts &= ~value;
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update_irq();
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break;
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case NV_PMC_INTR_EN_0:
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pmc.enabled_interrupts = value;
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update_irq();
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break;
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default:
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EmuWarning("EmuNV2A_PMC_Write32: Unknown Write Address %08X (value %08X)", addr, value);
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}
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@ -366,6 +473,23 @@ void EmuNV2A_PCOUNTER_Write32(uint32_t addr, uint32_t value)
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void EmuNV2A_PTIMER_Write32(uint32_t addr, uint32_t value)
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{
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switch (addr) {
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case NV_PTIMER_INTR_0:
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ptimer.pending_interrupts &= ~value;
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update_irq();
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break;
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case NV_PTIMER_INTR_EN_0:
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ptimer.enabled_interrupts = value;
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update_irq();
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break;
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case NV_PTIMER_DENOMINATOR:
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ptimer.denominator = value;
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break;
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case NV_PTIMER_NUMERATOR:
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ptimer.numerator = value;
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break;
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case NV_PTIMER_ALARM_0:
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ptimer.alarm_time = value;
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break;
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default:
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EmuWarning("EmuNV2A_PTIMER_Write32: Unknown Write Address %08X (value %08X)", addr, value);
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}
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@ -406,8 +530,8 @@ void EmuNV2A_PRMVIO_Write32(uint32_t addr, uint32_t value)
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void EmuNV2A_PFB_Write32(uint32_t addr, uint32_t value)
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{
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switch (addr) {
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default:
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EmuWarning("EmuNV2A_PFB_Write32: Unknown Write Address %08X (value %08X)", addr, value);
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default:
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pfb.regs[addr] = value;
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}
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}
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@ -430,6 +554,16 @@ void EmuNV2A_PGRAPH_Write32(uint32_t addr, uint32_t value)
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void EmuNV2A_PCRTC_Write32(uint32_t addr, uint32_t value)
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{
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switch (addr) {
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case NV_PCRTC_INTR_0:
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pcrtc.pending_interrupts &= ~value;
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update_irq();
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break;
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case NV_PCRTC_INTR_EN_0:
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pcrtc.enabled_interrupts = value;
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update_irq();
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break;
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case NV_PCRTC_START:
pcrtc.start = value &= 0x07FFFFFF;
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break;
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default:
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EmuWarning("EmuNV2A_PCRTC_Write32: Unknown Write Address %08X (value %08X)", addr, value);
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}
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