Fix vertex shader op independence
Ensure the MAC op does not interfere with the input of the ILU op. - Use a temp register to hold the input of the ILU op when necessary - Reorganize vertex shader decoding to better reflect the data. Decode one vsh instruction to one intermediate instruction, rather than to multiple independent instructions. Test case: KOTOR II (menu) GTA III (lighting)
This commit is contained in:
Anthony
parent
b43f6bbcdf
commit
46b1f24153
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@ -323,6 +323,9 @@ VS_OUTPUT main(const VS_INPUT xIn)
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init_v( 8); init_v( 9); init_v(10); init_v(11);
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init_v(12); init_v(13); init_v(14); init_v(15);
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// Temp variable for paired VS instruction
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float4 temp;
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// Xbox shader program)DELIMITER", /* This terminates the header raw string" // */
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R"DELIMITER(
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@ -11,9 +11,7 @@
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extern const char* g_vs_model = vs_model_3_0;
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// HLSL generation
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void OutputHlsl(std::stringstream& hlsl, VSH_IMD_OUTPUT& dest)
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{
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void DestRegisterHlsl(std::stringstream& hlsl, VSH_IMD_DEST& dest) {
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static const char* OReg_Name[/*VSH_OREG_NAME*/] = {
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"oPos",
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"???",
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@ -34,34 +32,37 @@ void OutputHlsl(std::stringstream& hlsl, VSH_IMD_OUTPUT& dest)
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};
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switch (dest.Type) {
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case IMD_OUTPUT_C:
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case IMD_DEST_C:
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// Access the HLSL capital C[] constants array, with the index bias applied :
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// TODO : Avoid out-of-bound writes (perhaps writing to a reserved index?)
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hlsl << "C[" << dest.Address + X_D3DSCM_CORRECTION << "]";
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LOG_TEST_CASE("Vertex shader writes to constant table");
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break;
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case IMD_OUTPUT_R:
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case IMD_DEST_R:
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hlsl << "r" << dest.Address;
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break;
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case IMD_OUTPUT_O:
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case IMD_DEST_O:
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assert(dest.Address < OREG_A0X);
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hlsl << OReg_Name[dest.Address];
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break;
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case IMD_OUTPUT_A0X:
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case IMD_DEST_A0X:
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hlsl << "a0";
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break;
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default:
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assert(false);
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break;
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}
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}
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void DestMaskHlsl(std::stringstream& hlsl, VSH_IMD_DEST& dest)
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{
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// Write the mask as a separate argument to the opcode defines
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// (No space, so that "dest,mask, ..." looks close to "dest.mask, ...")
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hlsl << ",";
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// Detect oFog masks other than x
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// Test case: Lego Star Wars II (menu)
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if (dest.Type == IMD_OUTPUT_O &&
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if (dest.Type == IMD_DEST_O &&
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dest.Address == OREG_OFOG &&
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dest.Mask != MASK_X)
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{
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@ -78,7 +79,7 @@ void OutputHlsl(std::stringstream& hlsl, VSH_IMD_OUTPUT& dest)
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if (dest.Mask & MASK_W) hlsl << "w";
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}
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void ParameterHlsl(std::stringstream& hlsl, VSH_IMD_PARAMETER& param, bool IndexesWithA0_X)
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void ParameterHlsl(std::stringstream& hlsl, VSH_IMD_PARAMETER& param, bool IndexesWithA0_X, bool useTemp)
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{
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static const char* RegisterName[/*VSH_PARAMETER_TYPE*/] = {
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"?", // PARAM_UNKNOWN = 0,
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@ -92,7 +93,10 @@ void ParameterHlsl(std::stringstream& hlsl, VSH_IMD_PARAMETER& param, bool Index
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hlsl << "-";
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}
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if (param.ParameterType == PARAM_C) {
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if (useTemp) {
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hlsl << "temp";
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}
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else if (param.Type == PARAM_C) {
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// Access constant registers through our HLSL c() function,
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// which allows dumping negative indices (like Xbox shaders),
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// and which returns zero when out-of-bounds indices are passed in:
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@ -112,7 +116,7 @@ void ParameterHlsl(std::stringstream& hlsl, VSH_IMD_PARAMETER& param, bool Index
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}
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}
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else {
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hlsl << RegisterName[param.ParameterType] << param.Address;
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hlsl << RegisterName[param.Type] << param.Address;
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}
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// Write the swizzle if we need to
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@ -175,25 +179,107 @@ void BuildShader(IntermediateVertexShader* pShader, std::stringstream& hlsl)
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/*ILU_LIT:*/"x_lit" // = 7 - all values of the 3 bits are used
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};
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for (size_t i = 0; i < pShader->Instructions.size(); i++) {
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VSH_INTERMEDIATE_FORMAT& IntermediateInstruction = pShader->Instructions[i];
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auto WriteOp = [&](
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const std::string& opcode,
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VSH_IMD_DEST dest,
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int paramCount, VSH_IMD_PARAMETER* params,
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bool indexesWithA0_X,
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bool iluUseTempParam
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) {
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// opcode(dest, a, b, c);
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hlsl << "\n " << opcode << "(";
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std::string str;
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if (IntermediateInstruction.MAC > MAC_NOP) {
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str = VSH_MAC_HLSL[IntermediateInstruction.MAC];
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}
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else {
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str = VSH_ILU_HLSL[IntermediateInstruction.ILU];
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}
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DestRegisterHlsl(hlsl, dest);
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DestMaskHlsl(hlsl, dest);
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hlsl << "\n " << str << "("; // opcode
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OutputHlsl(hlsl, IntermediateInstruction.Output);
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for (unsigned i = 0; i < IntermediateInstruction.ParamCount; i++) {
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for (int i = 0; i < paramCount; i++) {
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hlsl << ", ";
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ParameterHlsl(hlsl, IntermediateInstruction.Parameters[i], IntermediateInstruction.IndexesWithA0_X);
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ParameterHlsl(hlsl, params[i], indexesWithA0_X, iluUseTempParam);
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}
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hlsl << ");";
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};
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for (size_t i = 0; i < pShader->Instructions.size(); i++) {
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VSH_IMD_INSTR& in = pShader->Instructions[i];
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// Paired if both MAC and ILU write to a dest register
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bool isPaired =
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in.MAC.Opcode != MAC_NOP &&
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in.ILU.Opcode != ILU_NOP &&
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(in.MAC.Dest.Mask || in.ORegSource == SRC_MAC) &&
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(in.ILU.Dest.Mask || in.ORegSource == SRC_ILU);
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// If there are two "paired" instructions that need to run "simultaneously",
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// we need to prevent the output of the first instruction interfering
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// with the input of the second instruction
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// If the MAC output is the same as the ILU input
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// we will use a temp variable to hold the ILU input
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VSH_IMD_DEST* iluTemp = nullptr;
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if (isPaired) {
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if (in.MAC.Dest.Address == in.ILU.Parameter.Address &&
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(in.MAC.Dest.Type == IMD_DEST_C && in.ILU.Parameter.Type == PARAM_C ||
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in.MAC.Dest.Type == IMD_DEST_R && in.ILU.Parameter.Type == PARAM_R ||
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in.MAC.Dest.Type == IMD_DEST_A0X && in.ILU.Parameter.Type == PARAM_C && in.IndexesWithA0_X)) {
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// Normal MAC output matches ILU input
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iluTemp = &in.MAC.Dest;
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}
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else if (in.ORegSource == SRC_MAC &&
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in.ORegDest.Type == IMD_DEST_O && in.ORegDest.Address == 0 &&
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in.ILU.Parameter.Type == PARAM_R && in.ILU.Parameter.Address == 12) {
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// OReg MAC output matches ILU input
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// Note oPos is the same as r12
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iluTemp = &in.ORegDest;
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}
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if (iluTemp) {
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// MAC and ILU use the same register.
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// This is fine unless the ILU op uses a component written to by the MAC op
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bool conflict = false;
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for (int s = 0; s < 4; s++) {
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auto swizzle = in.ILU.Parameter.Swizzle[s];
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if (iluTemp->Mask & MASK_X && swizzle == SWIZZLE_X ||
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iluTemp->Mask & MASK_Y && swizzle == SWIZZLE_Y ||
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iluTemp->Mask & MASK_Z && swizzle == SWIZZLE_Z ||
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iluTemp->Mask & MASK_W && swizzle == SWIZZLE_W) {
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conflict = true;
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break;
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}
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}
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if (!conflict) {
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iluTemp = nullptr; // We don't need a temp after all
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}
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}
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}
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if (iluTemp) {
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// Write the ILU input to a temp
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hlsl << "\n " << "temp = ";
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DestRegisterHlsl(hlsl, *iluTemp);
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hlsl << ";";
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}
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// Write MAC op
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if (in.MAC.Opcode != MAC_NOP) {
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if (in.MAC.Dest.Mask) {
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WriteOp(VSH_MAC_HLSL[in.MAC.Opcode], in.MAC.Dest, in.MAC.ParamCount, in.MAC.Parameters, in.IndexesWithA0_X, false);
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}
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if (in.ORegSource == SRC_MAC && in.ORegDest.Mask) {
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WriteOp(VSH_MAC_HLSL[in.MAC.Opcode], in.ORegDest, in.MAC.ParamCount, in.MAC.Parameters, in.IndexesWithA0_X, false);
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}
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}
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// Write ILU op
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if (in.ILU.Opcode != ILU_NOP) {
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if (in.ILU.Dest.Mask) {
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WriteOp(VSH_ILU_HLSL[in.ILU.Opcode], in.ILU.Dest, 1, &in.ILU.Parameter, in.IndexesWithA0_X, iluTemp);
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}
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if (in.ORegSource == SRC_ILU && in.ORegDest.Mask) {
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WriteOp(VSH_ILU_HLSL[in.ILU.Opcode], in.ORegDest, 1, &in.ILU.Parameter, in.IndexesWithA0_X, iluTemp);
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}
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}
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hlsl << "\n"; // Group operations by instruction
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}
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}
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@ -528,7 +528,7 @@ namespace XboxVertexShaderDecoder
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return ((((CReg >> 5) & 7) - 3) * 32) + (CReg & 31);
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}
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static void VshConvertIntermediateParam(VSH_IMD_PARAMETER& Param,
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static VSH_IMD_PARAMETER VshGetIntermediateParam(
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uint32_t* pShaderToken,
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VSH_FIELD_NAME FLD_MUX,
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VSH_FIELD_NAME FLD_NEG,
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@ -536,80 +536,30 @@ namespace XboxVertexShaderDecoder
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uint16_t V,
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uint16_t C)
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{
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Param.ParameterType = (VSH_PARAMETER_TYPE)VshGetField(pShaderToken, FLD_MUX);
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switch (Param.ParameterType) {
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VSH_IMD_PARAMETER param{};
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param.Type = (VSH_IMD_PARAMETER_TYPE)VshGetField(pShaderToken, FLD_MUX);
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switch (param.Type) {
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case PARAM_R:
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Param.Address = R;
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param.Address = R;
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break;
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case PARAM_V:
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Param.Address = V;
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param.Address = V;
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break;
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case PARAM_C:
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Param.Address = C;
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param.Address = C;
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break;
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default:
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LOG_TEST_CASE("parameter type unknown");
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}
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int d = FLD_NEG - FLD_A_NEG;
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Param.Neg = VshGetField(pShaderToken, (VSH_FIELD_NAME)(d + FLD_A_NEG)) > 0;
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Param.Swizzle[0] = (VSH_SWIZZLE)VshGetField(pShaderToken, (VSH_FIELD_NAME)(d + FLD_A_SWZ_X));
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Param.Swizzle[1] = (VSH_SWIZZLE)VshGetField(pShaderToken, (VSH_FIELD_NAME)(d + FLD_A_SWZ_Y));
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Param.Swizzle[2] = (VSH_SWIZZLE)VshGetField(pShaderToken, (VSH_FIELD_NAME)(d + FLD_A_SWZ_Z));
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Param.Swizzle[3] = (VSH_SWIZZLE)VshGetField(pShaderToken, (VSH_FIELD_NAME)(d + FLD_A_SWZ_W));
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}
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param.Neg = VshGetField(pShaderToken, (VSH_FIELD_NAME)(d + FLD_A_NEG)) > 0;
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param.Swizzle[0] = (VSH_SWIZZLE)VshGetField(pShaderToken, (VSH_FIELD_NAME)(d + FLD_A_SWZ_X));
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param.Swizzle[1] = (VSH_SWIZZLE)VshGetField(pShaderToken, (VSH_FIELD_NAME)(d + FLD_A_SWZ_Y));
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param.Swizzle[2] = (VSH_SWIZZLE)VshGetField(pShaderToken, (VSH_FIELD_NAME)(d + FLD_A_SWZ_Z));
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param.Swizzle[3] = (VSH_SWIZZLE)VshGetField(pShaderToken, (VSH_FIELD_NAME)(d + FLD_A_SWZ_W));
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static void VshAddIntermediateInstruction(
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uint32_t* pShaderToken,
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IntermediateVertexShader* pShader,
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VSH_MAC MAC,
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VSH_ILU ILU,
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VSH_IMD_OUTPUT_TYPE output_type,
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int16_t output_address,
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int8_t output_mask)
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{
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// Is the output mask set?
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if (output_mask == 0) {
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return;
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}
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if (pShader->Instructions.size() >= VSH_MAX_INTERMEDIATE_COUNT) {
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CxbxrAbort("Shader exceeds conversion buffer!");
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}
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VSH_INTERMEDIATE_FORMAT intermediate;
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intermediate.MAC = MAC;
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intermediate.ILU = ILU;
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intermediate.Output.Type = output_type;
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intermediate.Output.Address = output_address;
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intermediate.Output.Mask = output_mask;
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// Get a0.x indirect constant addressing
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intermediate.IndexesWithA0_X = VshGetField(pShaderToken, FLD_A0X) > 0; // Applies to PARAM_C parameter reads
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int16_t R;
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int16_t V = VshGetField(pShaderToken, FLD_V);
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int16_t C = ConvertCRegister(VshGetField(pShaderToken, FLD_CONST));
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intermediate.ParamCount = 0;
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if (MAC >= MAC_MOV) {
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// Get parameter A
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R = VshGetField(pShaderToken, FLD_A_R);
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VshConvertIntermediateParam(intermediate.Parameters[intermediate.ParamCount++], pShaderToken, FLD_A_MUX, FLD_A_NEG, R, V, C);
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}
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if ((MAC == MAC_MUL) || ((MAC >= MAC_MAD) && (MAC <= MAC_SGE))) {
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// Get parameter B
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R = VshGetField(pShaderToken, FLD_B_R);
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VshConvertIntermediateParam(intermediate.Parameters[intermediate.ParamCount++], pShaderToken, FLD_B_MUX, FLD_B_NEG, R, V, C);
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}
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if ((ILU >= ILU_MOV) || (MAC == MAC_ADD) || (MAC == MAC_MAD)) {
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// Get parameter C
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R = VshGetField(pShaderToken, FLD_C_R_HIGH) << 2 | VshGetField(pShaderToken, FLD_C_R_LOW);
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VshConvertIntermediateParam(intermediate.Parameters[intermediate.ParamCount++], pShaderToken, FLD_C_MUX, FLD_C_NEG, R, V, C);
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}
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// Add the instruction to the shader
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pShader->Instructions.push_back(intermediate);
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return param;
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}
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static bool VshConvertToIntermediate(uint32_t* pShaderToken, IntermediateVertexShader* pShader)
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@ -619,52 +569,86 @@ namespace XboxVertexShaderDecoder
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VSH_MAC MAC = (VSH_MAC)VshGetField(pShaderToken, FLD_MAC);
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if (MAC > MAC_ARL) LOG_TEST_CASE("Unknown MAC");
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// Output register
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VSH_OUTPUT_MUX OutputMux = (VSH_OUTPUT_MUX)VshGetField(pShaderToken, FLD_OUT_MUX);
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int16_t OutputAddress = VshGetField(pShaderToken, FLD_OUT_ADDRESS);
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VSH_IMD_OUTPUT_TYPE OutputType;
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if ((VSH_OUTPUT_TYPE)VshGetField(pShaderToken, FLD_OUT_ORB) == OUTPUT_C) {
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OutputType = IMD_OUTPUT_C;
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OutputAddress = ConvertCRegister(OutputAddress);
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} else { // OUTPUT_O:
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OutputType = IMD_OUTPUT_O;
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OutputAddress = OutputAddress & 0xF;
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}
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// MAC,ILU output R register
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int16_t RAddress = VshGetField(pShaderToken, FLD_OUT_R);
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// Test for paired opcodes
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bool bIsPaired = (MAC != MAC_NOP) && (ILU != ILU_NOP);
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VSH_IMD_MAC_OP MacOp{};
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VSH_IMD_ILU_OP IluOp{};
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// Set up input registers
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int16_t AR = VshGetField(pShaderToken, FLD_A_R);
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int16_t BR = VshGetField(pShaderToken, FLD_B_R);
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int16_t CR = VshGetField(pShaderToken, FLD_C_R_HIGH) << 2 | VshGetField(pShaderToken, FLD_C_R_LOW);
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int16_t V = VshGetField(pShaderToken, FLD_V);
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int16_t C = ConvertCRegister(VshGetField(pShaderToken, FLD_CONST));
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// Check if there's a MAC opcode
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if (MAC > MAC_NOP && MAC <= MAC_ARL) {
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if (MAC != MAC_NOP && MAC <= MAC_ARL) {
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MacOp.Opcode = MAC;
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if (bIsPaired && RAddress == 1) {
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// Ignore paired MAC opcodes that write to R1
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} else {
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if (MAC == MAC_ARL) {
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VshAddIntermediateInstruction(pShaderToken, pShader, MAC, ILU_NOP, IMD_OUTPUT_A0X, 0, MASK_X);
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} else {
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VshAddIntermediateInstruction(pShaderToken, pShader, MAC, ILU_NOP, IMD_OUTPUT_R, RAddress, VshGetField(pShaderToken, FLD_OUT_MAC_MASK));
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}
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}
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else if (MAC == MAC_ARL) {
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MacOp.Dest.Type = IMD_DEST_A0X;
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MacOp.Dest.Mask = MASK_X;
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}
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else {
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MacOp.Dest.Type = IMD_DEST_R;
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MacOp.Dest.Address = RAddress;
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MacOp.Dest.Mask = VshGetField(pShaderToken, FLD_OUT_MAC_MASK);
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}
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// Check if we must add a muxed MAC opcode as well
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if (OutputMux == OMUX_MAC) {
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VshAddIntermediateInstruction(pShaderToken, pShader, MAC, ILU_NOP, OutputType, OutputAddress, VshGetField(pShaderToken, FLD_OUT_O_MASK));
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if (MAC >= MAC_MOV) {
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MacOp.Parameters[MacOp.ParamCount++] = VshGetIntermediateParam(pShaderToken, FLD_A_MUX, FLD_A_NEG, AR, V, C);
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}
|
||||
|
||||
if (MAC == MAC_MUL || (MAC >= MAC_MAD && MAC <= MAC_SGE)) {
|
||||
MacOp.Parameters[MacOp.ParamCount++] = VshGetIntermediateParam(pShaderToken, FLD_B_MUX, FLD_B_NEG, BR, V, C);
|
||||
}
|
||||
|
||||
if (MAC == MAC_ADD || MAC == MAC_MAD) {
|
||||
MacOp.Parameters[MacOp.ParamCount++] = VshGetIntermediateParam(pShaderToken, FLD_C_MUX, FLD_C_NEG, CR, V, C);
|
||||
}
|
||||
}
|
||||
|
||||
// Check if there's an ILU opcode
|
||||
if (ILU != ILU_NOP) {
|
||||
// Paired ILU opcodes will only write to R1
|
||||
VshAddIntermediateInstruction(pShaderToken, pShader, MAC_NOP, ILU, IMD_OUTPUT_R, bIsPaired ? 1 : RAddress, VshGetField(pShaderToken, FLD_OUT_ILU_MASK));
|
||||
// Check if we must add a muxed ILU opcode as well
|
||||
if (OutputMux == OMUX_ILU) {
|
||||
VshAddIntermediateInstruction(pShaderToken, pShader, MAC_NOP, ILU, OutputType, OutputAddress, VshGetField(pShaderToken, FLD_OUT_O_MASK));
|
||||
}
|
||||
IluOp.Opcode = ILU;
|
||||
IluOp.Dest.Type = IMD_DEST_R;
|
||||
IluOp.Dest.Address = bIsPaired ? 1 : RAddress;
|
||||
IluOp.Dest.Mask = VshGetField(pShaderToken, FLD_OUT_ILU_MASK);
|
||||
IluOp.Parameter = VshGetIntermediateParam(pShaderToken, FLD_C_MUX, FLD_C_NEG, CR, V, C);
|
||||
}
|
||||
|
||||
// Output register
|
||||
VSH_OUTPUT_MUX OutputMux = (VSH_OUTPUT_MUX)VshGetField(pShaderToken, FLD_OUT_MUX);
|
||||
int16_t OutputAddress = VshGetField(pShaderToken, FLD_OUT_ADDRESS);
|
||||
VSH_IMD_DEST_TYPE OutputType;
|
||||
if ((VSH_OUTPUT_TYPE)VshGetField(pShaderToken, FLD_OUT_ORB) == OUTPUT_C) {
|
||||
OutputType = IMD_DEST_C;
|
||||
OutputAddress = ConvertCRegister(OutputAddress);
|
||||
}
|
||||
else { // OUTPUT_O:
|
||||
OutputType = IMD_DEST_O;
|
||||
OutputAddress = OutputAddress & 0xF;
|
||||
}
|
||||
|
||||
VSH_IMD_INSTR imd{};
|
||||
imd.MAC = MacOp;
|
||||
imd.ILU = IluOp;
|
||||
imd.IndexesWithA0_X = VshGetField(pShaderToken, FLD_A0X) > 0;
|
||||
imd.ORegSource = OutputMux == OMUX_MAC ? SRC_MAC : SRC_ILU;
|
||||
imd.ORegDest.Type = OutputType;
|
||||
imd.ORegDest.Address = OutputAddress;
|
||||
imd.ORegDest.Mask = VshGetField(pShaderToken, FLD_OUT_O_MASK);
|
||||
|
||||
pShader->Instructions.push_back(imd);
|
||||
|
||||
return VshGetField(pShaderToken, FLD_FINAL) == 0;
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -147,18 +147,18 @@ enum VSH_MAC { // Dxbx note : MAC stands for 'Multiply And Accumulate' opcodes
|
|||
// ??? 15 - 2 values of the 4 bits are undefined
|
||||
};
|
||||
|
||||
enum VSH_IMD_OUTPUT_TYPE {
|
||||
IMD_OUTPUT_C,
|
||||
IMD_OUTPUT_R,
|
||||
IMD_OUTPUT_O,
|
||||
IMD_OUTPUT_A0X
|
||||
enum VSH_IMD_DEST_TYPE {
|
||||
IMD_DEST_C,
|
||||
IMD_DEST_R,
|
||||
IMD_DEST_O,
|
||||
IMD_DEST_A0X
|
||||
};
|
||||
|
||||
typedef struct _VSH_IMD_OUTPUT {
|
||||
VSH_IMD_OUTPUT_TYPE Type;
|
||||
int16_t Address;
|
||||
int8_t Mask;
|
||||
} VSH_IMD_OUTPUT;
|
||||
typedef struct {
|
||||
VSH_IMD_DEST_TYPE Type;
|
||||
int16_t Address;
|
||||
int8_t Mask; // If 0 skip writing to this output
|
||||
} VSH_IMD_DEST;
|
||||
|
||||
enum VSH_SWIZZLE {
|
||||
SWIZZLE_X = 0,
|
||||
|
|
@ -167,7 +167,7 @@ enum VSH_SWIZZLE {
|
|||
SWIZZLE_W
|
||||
};
|
||||
|
||||
enum VSH_PARAMETER_TYPE {
|
||||
enum VSH_IMD_PARAMETER_TYPE {
|
||||
PARAM_UNKNOWN = 0,
|
||||
PARAM_R, // Temporary (scRatch) registers
|
||||
PARAM_V, // Vertex registers
|
||||
|
|
@ -175,28 +175,49 @@ enum VSH_PARAMETER_TYPE {
|
|||
PARAM_O // = 0??
|
||||
};
|
||||
|
||||
typedef struct _VSH_IMD_PARAMETER {
|
||||
VSH_PARAMETER_TYPE ParameterType; // Parameter type, R, V or C
|
||||
typedef struct {
|
||||
VSH_IMD_PARAMETER_TYPE Type; // Parameter type, R, V or C
|
||||
bool Neg; // true if negated, false if not
|
||||
VSH_SWIZZLE Swizzle[4]; // The four swizzles
|
||||
int16_t Address; // Register address
|
||||
} VSH_IMD_PARAMETER;
|
||||
|
||||
typedef struct _VSH_INTERMEDIATE_FORMAT {
|
||||
VSH_MAC MAC;
|
||||
VSH_ILU ILU;
|
||||
VSH_IMD_OUTPUT Output;
|
||||
unsigned ParamCount;
|
||||
VSH_IMD_PARAMETER Parameters[3];
|
||||
// There is only a single address register in Microsoft DirectX 8.0.
|
||||
// The address register, designated as a0.x, may be used as signed
|
||||
// integer offset in relative addressing into the constant register file.
|
||||
// c[a0.x + n]
|
||||
bool IndexesWithA0_X;
|
||||
} VSH_INTERMEDIATE_FORMAT;
|
||||
typedef struct {
|
||||
VSH_ILU Opcode;
|
||||
VSH_IMD_DEST Dest;
|
||||
VSH_IMD_PARAMETER Parameter;
|
||||
} VSH_IMD_ILU_OP;
|
||||
|
||||
typedef struct _IntermediateVertexShader {
|
||||
std::vector<VSH_INTERMEDIATE_FORMAT> Instructions;
|
||||
typedef struct {
|
||||
VSH_MAC Opcode;
|
||||
VSH_IMD_DEST Dest;
|
||||
uint8_t ParamCount;
|
||||
VSH_IMD_PARAMETER Parameters[3];
|
||||
} VSH_IMD_MAC_OP;
|
||||
|
||||
enum VSH_IMD_OREG_SOURCE {
|
||||
SRC_MAC,
|
||||
SRC_ILU,
|
||||
};
|
||||
|
||||
// Intermediate decoded VSH instruction
|
||||
// Up to two operations (MAC and ILU)
|
||||
// Writes to up to 3 destination registers
|
||||
// One dest per op + one output register
|
||||
typedef struct {
|
||||
VSH_IMD_MAC_OP MAC;
|
||||
VSH_IMD_ILU_OP ILU;
|
||||
|
||||
VSH_IMD_OREG_SOURCE ORegSource;
|
||||
VSH_IMD_DEST ORegDest;
|
||||
|
||||
// True if the constant input C should use the index register a0
|
||||
// c[a0.x + n]
|
||||
bool IndexesWithA0_X;
|
||||
} VSH_IMD_INSTR;
|
||||
|
||||
typedef struct {
|
||||
std::vector<VSH_IMD_INSTR> Instructions;
|
||||
} IntermediateVertexShader;
|
||||
|
||||
// parse xbox vertex shader function into an intermediate format
|
||||
|
|
|
|||
Loading…
Reference in New Issue