X86 : Only fail opcode handling if operands can't be decoded.
Operand read or write failues won't bail out anymore. Logging unhandled opcodes separate from opcode handling errors. Log useless (internal) operand writes (these should never occur)
This commit is contained in:
patrickvl
parent
e7f69b0aaa
commit
3c4331ad3f
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@ -92,7 +92,7 @@ uint32_t EmuX86_IORead(xbaddr addr, int size)
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return value;
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}
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EmuWarning("EmuX86_IORead(0x%08X, %d) [Unknown address]", addr, size);
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EmuWarning("EmuX86_IORead(0x%08X, %d) [Unhandled]", addr, size);
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return 0;
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}
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@ -103,7 +103,7 @@ void EmuX86_IOWrite(xbaddr addr, uint32_t value, int size)
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return;
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}
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EmuWarning("EmuX86_IOWrite(0x%08X, 0x%04X, %d) [Unknown address]", addr, value, size);
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EmuWarning("EmuX86_IOWrite(0x%08X, 0x%04X, %d) [Unhandled]", addr, value, size);
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}
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//
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@ -171,7 +171,7 @@ uint32_t EmuX86_Read(xbaddr addr, int size)
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{
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if ((addr & (size - 1)) != 0) {
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EmuWarning("EmuX86_Read(0x%08X, %d) [Unaligned unimplemented]", addr, size);
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// LOG_UNIMPLEMENTD();
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// LOG_UNIMPLEMENTED();
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return 0;
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}
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@ -197,46 +197,45 @@ uint32_t EmuX86_Read(xbaddr addr, int size)
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value = EmuX86_Mem_Read(addr, size);
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}
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DbgPrintf("EmuX86_Read(0x%08X, %d) = 0x%08X\n", addr, size, value);
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DbgPrintf("X86 : Read(0x%08X, %d) = 0x%08X\n", addr, size, value);
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}
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return value;
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}
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bool EmuX86_Write(xbaddr addr, uint32_t value, int size)
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void EmuX86_Write(xbaddr addr, uint32_t value, int size)
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{
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if ((addr & (size - 1)) != 0) {
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EmuWarning("EmuX86_Write(0x%08X, 0x%08X, %d) [Unaligned unimplemented]", addr, value, size);
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// LOG_UNIMPLEMENTD();
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return false;
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// LOG_UNIMPLEMENTED();
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return;
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}
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if (addr >= NV2A_ADDR && addr < NV2A_ADDR + NV2A_SIZE) {
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// Access NV2A regardless weither HLE is disabled or not (ignoring bLLE_GPU)
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EmuNV2A_Write(addr - NV2A_ADDR, value, size);
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// Note : EmuNV2A_Write does it's own logging
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return true; // Assume successfull NV2A write
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return;
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}
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if (addr >= XBOX_FLASH_ROM_BASE) { // 0xFFF00000 - 0xFFFFFFF
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EmuWarning("EmuX86_Write(0x%08X, 0x%08X) [FLASH_ROM]", addr, value);
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return true; // TODO : Fake successfull flash write
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return;
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}
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// Pass the Write to the PCI Bus, this will handle devices with BARs set to MMIO addresses
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if (g_PCIBus->MMIOWrite(addr, value, size)) {
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return true;
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return;
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}
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if (g_bEmuException) {
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EmuWarning("EmuX86_Write(0x%08X, 0x%08X) [Unknown address]", addr, value);
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return false;
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return;
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}
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// Outside EmuException, pass the memory-access through to normal memory :
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DbgPrintf("X86 : Write(0x%.8X, 0x%.8X, %d)\n", addr, value, size);
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EmuX86_Mem_Write(addr, value, size);
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return true;
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}
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int ContextRecordOffsetByRegisterType[/*_RegisterType*/R_DR7 + 1] = { 0 };
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@ -349,6 +348,7 @@ inline void * EmuX86_GetRegisterPointer(LPEXCEPTION_POINTERS e, uint8_t reg)
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if (offset > 0)
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return (void*)((uintptr_t)(e->ContextRecord) + offset);
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assert(false);
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return nullptr;
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}
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@ -364,34 +364,6 @@ inline uint32_t EmuX86_GetRegisterValue32(LPEXCEPTION_POINTERS e, uint8_t reg)
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return 0;
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}
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/* Unused :
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inline uint16_t EmuX86_GetRegisterValue16(LPEXCEPTION_POINTERS e, uint8_t reg)
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{
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if (reg != R_NONE)
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{
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void* regptr = EmuX86_GetRegisterPointer(e, reg);
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if (regptr != nullptr)
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return *(uint16_t *)regptr;
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}
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return 0;
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}
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*/
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/* Unused :
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inline uint8_t EmuX86_GetRegisterValue8(LPEXCEPTION_POINTERS e, uint8_t reg)
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{
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if (reg != R_NONE)
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{
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void* regptr = EmuX86_GetRegisterPointer(e, reg);
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if (regptr != nullptr)
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return *(uint8_t *)regptr;
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}
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return 0;
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}
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*/
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xbaddr EmuX86_Distorm_O_SMEM_Addr(LPEXCEPTION_POINTERS e, _DInst& info, int operand)
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{
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xbaddr base = EmuX86_GetRegisterValue32(e, info.ops[operand].index);
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@ -411,7 +383,11 @@ xbaddr EmuX86_Distorm_O_MEM_Addr(LPEXCEPTION_POINTERS e, _DInst& info, int opera
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return base + index + (uint32_t)info.disp;
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}
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xbaddr EmuX86_Operand_Addr(LPEXCEPTION_POINTERS e, _DInst& info, int operand, bool &is_internal_addr, int &size)
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#define no_internal_addr 0
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#define internal_addr_read_only 1
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#define internal_addr_read_write 3
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xbaddr EmuX86_Operand_Addr(LPEXCEPTION_POINTERS e, _DInst& info, int operand, int &is_internal_addr, int &size)
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{
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size = info.ops[operand].size / 8; // Convert size in bits into bytes
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switch (info.ops[operand].type) {
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@ -421,48 +397,51 @@ xbaddr EmuX86_Operand_Addr(LPEXCEPTION_POINTERS e, _DInst& info, int operand, bo
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return xbnull;
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}
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case O_REG:
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is_internal_addr = true;
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is_internal_addr = internal_addr_read_write;
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return (xbaddr)EmuX86_GetRegisterPointer(e, info.ops[operand].index);
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{
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}
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case O_IMM:
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{
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is_internal_addr = true;
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is_internal_addr = internal_addr_read_only;
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return (xbaddr)(&info.imm);
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}
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case O_IMM1:
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{
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is_internal_addr = true;
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is_internal_addr = internal_addr_read_only;
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return (xbaddr)(&info.imm.ex.i1);
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}
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case O_IMM2:
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{
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is_internal_addr = true;
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is_internal_addr = internal_addr_read_only;
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return (xbaddr)(&info.imm.ex.i2);
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}
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case O_DISP:
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{
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is_internal_addr = false;
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is_internal_addr = no_internal_addr;
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// TODO : Use info.dispSize instead?
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return (xbaddr)info.disp;
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}
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case O_SMEM:
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{
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is_internal_addr = false;
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is_internal_addr = no_internal_addr;
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// TODO : Use info.dispSize instead?
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return EmuX86_Distorm_O_SMEM_Addr(e, info, operand);
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}
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case O_MEM:
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{
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is_internal_addr = false;
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is_internal_addr = no_internal_addr;
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// TODO : Use info.dispSize instead?
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return EmuX86_Distorm_O_MEM_Addr(e, info, operand);
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}
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case O_PC:
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{
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is_internal_addr = false;
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is_internal_addr = no_internal_addr;
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return (xbaddr)INSTRUCTION_GET_TARGET(&info);
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}
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case O_PTR:
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{
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is_internal_addr = false;
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is_internal_addr = no_internal_addr;
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return (xbaddr)info.imm.ptr.off; // TODO : What about info.imm.ptr.seg ?
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}
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default:
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@ -472,7 +451,7 @@ xbaddr EmuX86_Operand_Addr(LPEXCEPTION_POINTERS e, _DInst& info, int operand, bo
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return xbnull;
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}
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bool EmuX86_Addr_Read(xbaddr srcAddr, bool is_internal_addr, int size, OUT uint32_t *value)
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void EmuX86_Addr_Read(xbaddr srcAddr, int is_internal_addr, int size, OUT uint32_t *value)
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{
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assert(size == sizeof(uint8_t) || size == sizeof(uint16_t) || size == sizeof(uint32_t));
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@ -482,41 +461,50 @@ bool EmuX86_Addr_Read(xbaddr srcAddr, bool is_internal_addr, int size, OUT uint3
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else {
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*value = EmuX86_Read(srcAddr, size);
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}
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return true;
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}
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bool EmuX86_Addr_Write(xbaddr destAddr, bool is_internal_addr, int size, uint32_t value)
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void EmuX86_Addr_Write(xbaddr destAddr, int is_internal_addr, int size, uint32_t value)
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{
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assert(size == sizeof(uint8_t) || size == sizeof(uint16_t) || size == sizeof(uint32_t));
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if (is_internal_addr) {
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if (is_internal_addr != internal_addr_read_write) {
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EmuWarning("EmuX86_Addr_Write() : Useless (internal) write detected!");
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assert(false); // This is the only reason to return a bool, but should never happen!
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return;
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// TODO : If it can be proven that writes to read-only internal addresses never happen,
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// is_internal_addr can be made a bool again.
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}
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EmuX86_Mem_Write(destAddr, value, size);
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return true;
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}
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else {
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return EmuX86_Write(destAddr, value, size);
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EmuX86_Write(destAddr, value, size);
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}
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}
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bool EmuX86_Operand_Read(LPEXCEPTION_POINTERS e, _DInst& info, int operand, OUT uint32_t *value)
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{
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bool is_internal_addr;
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int is_internal_addr;
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int size;
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xbaddr srcAddr = EmuX86_Operand_Addr(e, info, operand, OUT is_internal_addr, OUT size);
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if (srcAddr != xbnull)
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return EmuX86_Addr_Read(srcAddr, is_internal_addr, size, value);
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if (srcAddr != xbnull) {
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EmuX86_Addr_Read(srcAddr, is_internal_addr, size, value);
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return true;
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}
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return false;
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}
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bool EmuX86_Operand_Write(LPEXCEPTION_POINTERS e, _DInst& info, int operand, uint32_t value)
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{
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bool is_internal_addr;
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int is_internal_addr;
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int size;
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xbaddr destAddr = EmuX86_Operand_Addr(e, info, operand, OUT is_internal_addr, OUT size);
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if (destAddr != xbnull)
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return EmuX86_Addr_Write(destAddr, is_internal_addr, size, value);
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if (destAddr != xbnull) {
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EmuX86_Addr_Write(destAddr, is_internal_addr, size, value);
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return true;
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}
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return false;
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}
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@ -610,7 +598,7 @@ bool EmuX86_Opcode_ADD(LPEXCEPTION_POINTERS e, _DInst& info)
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return false;
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// ADD reads and writes the same operand :
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bool is_internal_addr;
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int is_internal_addr;
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int size;
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xbaddr addr = EmuX86_Operand_Addr(e, info, 0, OUT is_internal_addr, OUT size);
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if (addr == xbnull)
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@ -624,8 +612,7 @@ bool EmuX86_Opcode_ADD(LPEXCEPTION_POINTERS e, _DInst& info)
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const uint64_t result = (uint64_t)dest + (uint64_t)src;
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// Write back the result
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if (!EmuX86_Write(addr, static_cast<uint32_t>(result), size))
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return false;
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EmuX86_Write(addr, static_cast<uint32_t>(result), size);
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// The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
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EmuX86_SetFlags_OSZAPC(e,
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@ -647,22 +634,20 @@ bool EmuX86_Opcode_AND(LPEXCEPTION_POINTERS e, _DInst& info)
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return false;
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// AND reads and writes the same operand :
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bool is_internal_addr;
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int is_internal_addr;
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int size;
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xbaddr addr = EmuX86_Operand_Addr(e, info, 0, OUT is_internal_addr, OUT size);
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if (addr == xbnull)
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return false;
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uint32_t dest = 0;
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if (!EmuX86_Addr_Read(addr, is_internal_addr, size, &dest))
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return false;
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EmuX86_Addr_Read(addr, is_internal_addr, size, &dest);
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// AND Destination with src
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uint32_t result = dest & src;
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// Write back the result
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if (!EmuX86_Addr_Write(addr, is_internal_addr, size, result))
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return false;
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EmuX86_Addr_Write(addr, is_internal_addr, size, result);
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// The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.
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EmuX86_SetFlags_OSZPC(e,
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@ -788,22 +773,20 @@ void EmuX86_Opcode_CPUID(LPEXCEPTION_POINTERS e, _DInst& info)
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bool EmuX86_Opcode_DEC(LPEXCEPTION_POINTERS e, _DInst& info)
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{
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// DEC reads and writes the same operand :
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bool is_internal_addr;
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int is_internal_addr;
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int size;
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xbaddr addr = EmuX86_Operand_Addr(e, info, 0, OUT is_internal_addr, OUT size);
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if (addr == xbnull)
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return false;
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uint32_t dest = 0;
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if (!EmuX86_Addr_Read(addr, is_internal_addr, size, &dest))
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return false;
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EmuX86_Addr_Read(addr, is_internal_addr, size, &dest);
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// DEC Destination to src
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uint64_t result = (uint64_t)dest - (uint64_t)1;
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// Write result back
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if (!EmuX86_Addr_Write(addr, is_internal_addr, size, static_cast<uint32_t>(result)))
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return false;
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EmuX86_Addr_Write(addr, is_internal_addr, size, static_cast<uint32_t>(result));
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// The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.
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EmuX86_SetFlags_OSZAP(e,
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@ -837,22 +820,20 @@ bool EmuX86_Opcode_IN(LPEXCEPTION_POINTERS e, _DInst& info)
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bool EmuX86_Opcode_INC(LPEXCEPTION_POINTERS e, _DInst& info)
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{
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// INC reads and writes the same operand :
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bool is_internal_addr;
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int is_internal_addr;
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int size;
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xbaddr addr = EmuX86_Operand_Addr(e, info, 0, OUT is_internal_addr, OUT size);
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if (addr == xbnull)
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return false;
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uint32_t dest = 0;
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if (!EmuX86_Addr_Read(addr, is_internal_addr, size, &dest))
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return false;
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EmuX86_Addr_Read(addr, is_internal_addr, size, &dest);
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// INC Destination to src
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uint64_t result = (uint64_t)dest + (uint64_t)1;
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// Write result back
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if (!EmuX86_Addr_Write(addr, is_internal_addr, size, static_cast<uint32_t>(result)))
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return false;
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EmuX86_Addr_Write(addr, is_internal_addr, size, static_cast<uint32_t>(result));
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// The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the re
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EmuX86_SetFlags_OSZAP(e,
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@ -906,16 +887,21 @@ bool EmuX86_Opcode_OR(LPEXCEPTION_POINTERS e, _DInst& info)
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if (!EmuX86_Operand_Read(e, info, 1, &src))
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return false;
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uint32_t dest = 0;
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if (!EmuX86_Operand_Read(e, info, 0, &dest))
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// OR reads and writes the same operand :
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int is_internal_addr;
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int size;
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xbaddr addr = EmuX86_Operand_Addr(e, info, 0, OUT is_internal_addr, OUT size);
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if (addr == xbnull)
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return false;
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uint32_t dest = 0;
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EmuX86_Addr_Read(addr, is_internal_addr, size, &dest);
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// OR Destination with src
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uint32_t result = dest | src;
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// Write back the result
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if (!EmuX86_Operand_Write(e, info, 0, result))
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return false;
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EmuX86_Addr_Write(addr, is_internal_addr, size, result);
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// The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.
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EmuX86_SetFlags_OSZPC(e,
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@ -954,15 +940,21 @@ bool EmuX86_Opcode_SUB(LPEXCEPTION_POINTERS e, _DInst& info)
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if (!EmuX86_Operand_Read(e, info, 1, &src))
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return false;
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uint32_t dest = 0;
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if (!EmuX86_Operand_Read(e, info, 0, &dest))
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// SUB reads and writes the same operand :
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int is_internal_addr;
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int size;
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xbaddr addr = EmuX86_Operand_Addr(e, info, 0, OUT is_internal_addr, OUT size);
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if (addr == xbnull)
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return false;
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uint32_t dest = 0;
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EmuX86_Addr_Read(addr, is_internal_addr, size, &dest);
|
||||
|
||||
// SUB Destination with src
|
||||
uint64_t result = (uint64_t)dest - (uint64_t)src;
|
||||
|
||||
// Write result back
|
||||
EmuX86_Operand_Write(e, info, 0, static_cast<uint32_t>(result));
|
||||
EmuX86_Addr_Write(addr, is_internal_addr, size, static_cast<uint32_t>(result));
|
||||
|
||||
// The OF, SF, ZF, AF, PF, and CF flags are set according to the result.
|
||||
EmuX86_SetFlags_OSZAPC(e,
|
||||
|
|
@ -1042,80 +1034,83 @@ bool EmuX86_DecodeException(LPEXCEPTION_POINTERS e)
|
|||
}
|
||||
|
||||
// Decoded instruction information.
|
||||
// Opcode handler note :
|
||||
// If an opcode or one of it's operand can't be decoded, that's a clear failure.
|
||||
// However, if for any reason, an opcode operand cannot be read from or written to,
|
||||
// that case may be logged, but it shouldn't fail the opcode handler.
|
||||
_DInst info;
|
||||
if (!EmuX86_DecodeOpcode((uint8_t*)e->ContextRecord->Eip, info)) {
|
||||
EmuWarning("Error decoding opcode at 0x%08X", e->ContextRecord->Eip);
|
||||
return false;
|
||||
}
|
||||
else {
|
||||
switch (info.opcode) { // Keep these cases alphabetically ordered and condensed
|
||||
case I_ADD:
|
||||
if (EmuX86_Opcode_ADD(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_AND:
|
||||
if (EmuX86_Opcode_AND(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_CMP:
|
||||
if (EmuX86_Opcode_CMP(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_CMPXCHG:
|
||||
if (EmuX86_Opcode_CMPXCHG(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_CPUID:
|
||||
EmuX86_Opcode_CPUID(e, info);
|
||||
break;
|
||||
case I_DEC:
|
||||
if (EmuX86_Opcode_DEC(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_IN:
|
||||
if (EmuX86_Opcode_IN(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_INC:
|
||||
if (EmuX86_Opcode_INC(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_INVD: // Flush internal caches; initiate flushing of external caches.
|
||||
break; // We can safely ignore this
|
||||
case I_MOV:
|
||||
if (EmuX86_Opcode_MOV(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_MOVZX:
|
||||
if (EmuX86_Opcode_MOVZX(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_OR:
|
||||
if (EmuX86_Opcode_OR(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_OUT:
|
||||
if (EmuX86_Opcode_OUT(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_SUB:
|
||||
if (EmuX86_Opcode_SUB(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_TEST:
|
||||
if (EmuX86_Opcode_TEST(e, info)) break;
|
||||
goto unimplemented_opcode;
|
||||
case I_WBINVD: // Write back and flush internal caches; initiate writing-back and flushing of external caches.
|
||||
break; // We can safely ignore this
|
||||
case I_WRMSR:
|
||||
// We do not emulate processor specific registers just yet
|
||||
// Some titles attempt to manually set the TSC via this instruction
|
||||
// This needs fixing eventually, but should be acceptible to ignore for now!
|
||||
// Chase: Hollywood Stunt Driver hits this
|
||||
EmuWarning("WRMSR instruction ignored");
|
||||
break;
|
||||
default:
|
||||
EmuWarning("Unhandled instruction : %u", info.opcode);
|
||||
goto unimplemented_opcode;
|
||||
}
|
||||
|
||||
// When falling through here, the instruction was handled correctly,
|
||||
// skip over the instruction and continue execution :
|
||||
e->ContextRecord->Eip += info.size;
|
||||
return true;
|
||||
|
||||
unimplemented_opcode:
|
||||
EmuWarning("0x%08X: Not Implemented\n", e->ContextRecord->Eip); // TODO : format decodedInstructions[0]
|
||||
switch (info.opcode) { // Keep these cases alphabetically ordered and condensed
|
||||
case I_ADD:
|
||||
if (EmuX86_Opcode_ADD(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_AND:
|
||||
if (EmuX86_Opcode_AND(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_CMP:
|
||||
if (EmuX86_Opcode_CMP(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_CMPXCHG:
|
||||
if (EmuX86_Opcode_CMPXCHG(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_CPUID:
|
||||
EmuX86_Opcode_CPUID(e, info);
|
||||
break;
|
||||
case I_DEC:
|
||||
if (EmuX86_Opcode_DEC(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_IN:
|
||||
if (EmuX86_Opcode_IN(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_INC:
|
||||
if (EmuX86_Opcode_INC(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_INVD: // Flush internal caches; initiate flushing of external caches.
|
||||
break; // We can safely ignore this
|
||||
case I_MOV:
|
||||
if (EmuX86_Opcode_MOV(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_MOVZX:
|
||||
if (EmuX86_Opcode_MOVZX(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_OR:
|
||||
if (EmuX86_Opcode_OR(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_OUT:
|
||||
if (EmuX86_Opcode_OUT(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_SUB:
|
||||
if (EmuX86_Opcode_SUB(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_TEST:
|
||||
if (EmuX86_Opcode_TEST(e, info)) break;
|
||||
goto opcode_error;
|
||||
case I_WBINVD: // Write back and flush internal caches; initiate writing-back and flushing of external caches.
|
||||
break; // We can safely ignore this
|
||||
case I_WRMSR:
|
||||
// We do not emulate processor specific registers just yet
|
||||
// Some titles attempt to manually set the TSC via this instruction
|
||||
// This needs fixing eventually, but should be acceptible to ignore for now!
|
||||
// Chase: Hollywood Stunt Driver hits this
|
||||
EmuWarning("WRMSR instruction ignored");
|
||||
break;
|
||||
default:
|
||||
EmuWarning("Unhandled instruction : %u", info.opcode);
|
||||
e->ContextRecord->Eip += info.size;
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
// When falling through here, the instruction was handled correctly,
|
||||
// skip over the instruction and continue execution :
|
||||
e->ContextRecord->Eip += info.size;
|
||||
return true;
|
||||
|
||||
opcode_error:
|
||||
EmuWarning("0x%08X: Error while handling instruction %u", e->ContextRecord->Eip, info.opcode); // TODO : format decodedInstructions[0]
|
||||
e->ContextRecord->Eip += info.size;
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue