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X86 : Restored indent (by request of Radwolfie)

This commit is contained in:
PatrickvL 2018-09-20 18:20:30 +02:00
parent 6782c89b62
commit 3216fac4ad
1 changed files with 295 additions and 294 deletions
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589
src/CxbxKrnl/EmuX86.cpp
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@ -1420,323 +1420,324 @@ bool EmuX86_DecodeException(LPEXCEPTION_POINTERS e)
} }
switch (info.opcode) { // Keep these cases alphabetically ordered and condensed switch (info.opcode) { // Keep these cases alphabetically ordered and condensed
case I_ADD: case I_ADD:
if (EmuX86_Opcode_ADD(e, info)) break; if (EmuX86_Opcode_ADD(e, info)) break;
goto opcode_error; goto opcode_error;
case I_AND: case I_AND:
if (EmuX86_Opcode_AND(e, info)) break; if (EmuX86_Opcode_AND(e, info)) break;
goto opcode_error; goto opcode_error;
case I_CALL: case I_CALL:
// RET and CALL always signify the end of a code block // RET and CALL always signify the end of a code block
return true; return true;
case I_CDQ: // = 250 : Convert Doubleword to Quadword case I_CDQ: // = 250 : Convert Doubleword to Quadword
EmuX86_Opcode_CDQ(e, info); EmuX86_Opcode_CDQ(e, info);
break; break;
case I_CLI: { // = 502 : Disable all interrupts case I_CLI: { // = 502 : Disable all interrupts
EmuX86_Opcode_CLI(); EmuX86_Opcode_CLI();
break; break;
} }
case I_CMP: case I_CMP:
if (EmuX86_Opcode_CMP(e, info)) break; if (EmuX86_Opcode_CMP(e, info)) break;
goto opcode_error; goto opcode_error;
case I_CMPXCHG: case I_CMPXCHG:
if (EmuX86_Opcode_CMPXCHG(e, info)) break; if (EmuX86_Opcode_CMPXCHG(e, info)) break;
goto opcode_error; goto opcode_error;
case I_CPUID: case I_CPUID:
EmuX86_Opcode_CPUID(e, info); EmuX86_Opcode_CPUID(e, info);
break; break;
case I_DEC: case I_DEC:
if (EmuX86_Opcode_DEC(e, info)) break; if (EmuX86_Opcode_DEC(e, info)) break;
goto opcode_error; goto opcode_error;
#if 0 // TODO : Implement EmuX86_Opcode_IMUL and enable this : #if 0 // TODO : Implement EmuX86_Opcode_IMUL and enable this :
case I_IMUL: { // = 117 : Signed Multiply case I_IMUL: { // = 117 : Signed Multiply
if (EmuX86_Opcode_IMUL(e, info)) break; if (EmuX86_Opcode_IMUL(e, info)) break;
goto opcode_error; goto opcode_error;
} }
#endif #endif
case I_IN: case I_IN:
if (EmuX86_Opcode_IN(e, info)) break; if (EmuX86_Opcode_IN(e, info)) break;
goto opcode_error; goto opcode_error;
case I_INC: case I_INC:
if (EmuX86_Opcode_INC(e, info)) break; if (EmuX86_Opcode_INC(e, info)) break;
goto opcode_error; goto opcode_error;
case I_INVD: // = 555 : Flush internal caches; initiate flushing of external caches. case I_INVD: // = 555 : Flush internal caches; initiate flushing of external caches.
break; // Privileged Level (Ring 0) Instruction. Causes a priviledge instruction exception - We can safely ignore this break; // Privileged Level (Ring 0) Instruction. Causes a priviledge instruction exception - We can safely ignore this
case I_INVLPG: { // = 1727 case I_INVLPG: { // = 1727
// This instruction invalidates the TLB entry specified with the source operand. Since we don't emulate // This instruction invalidates the TLB entry specified with the source operand. Since we don't emulate
// the TLB yet, we can safely ignore this. Test case: Fable. // the TLB yet, we can safely ignore this. Test case: Fable.
break; break;
}
case I_JA: { // = 166 : Jump if above (CF=0 and ZF=0).
if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_CF(e) && !EmuX86_HasFlag_ZF(e))) {
continue;
} }
break; case I_JA: { // = 166 : Jump if above (CF=0 and ZF=0).
} if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_CF(e) && !EmuX86_HasFlag_ZF(e))) {
case I_JAE: { // = 147 : Jump if above or equal (CF=0). continue;
if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_CF(e))) { }
continue; break;
} }
break; case I_JAE: { // = 147 : Jump if above or equal (CF=0).
} if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_CF(e))) {
case I_JB: { // = 143 : Jump if below (CF=1). continue;
if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_CF(e))) { }
continue; break;
} }
break; case I_JB: { // = 143 : Jump if below (CF=1).
} if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_CF(e))) {
case I_JBE: { // = 161 : Jump if below or equal (CF=1 or ZF=1). continue;
if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_CF(e) || EmuX86_HasFlag_ZF(e))) { }
continue; break;
} }
break; case I_JBE: { // = 161 : Jump if below or equal (CF=1 or ZF=1).
} if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_CF(e) || EmuX86_HasFlag_ZF(e))) {
case I_JCXZ: { // = 427 : Jump if CX register is 0. continue;
if (EmuX86_Opcode_Jcc(e, info, ((e->ContextRecord->Ecx & 0xFF) == 0))) { }
continue; break;
} }
break; case I_JCXZ: { // = 427 : Jump if CX register is 0.
} if (EmuX86_Opcode_Jcc(e, info, ((e->ContextRecord->Ecx & 0xFF) == 0))) {
case I_JECXZ: { // = 433 : Jump if ECX register is 0. continue;
if (EmuX86_Opcode_Jcc(e, info, e->ContextRecord->Ecx == 0)) { }
continue; break;
} }
break; case I_JECXZ: { // = 433 : Jump if ECX register is 0.
} if (EmuX86_Opcode_Jcc(e, info, e->ContextRecord->Ecx == 0)) {
case I_JG: { // = 202 : Jump if greater (ZF=0 and SF=OF). continue;
if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_ZF(e) && (EmuX86_HasFlag_SF(e) == EmuX86_HasFlag_OF(e)))) { }
continue; break;
} }
break; case I_JG: { // = 202 : Jump if greater (ZF=0 and SF=OF).
} if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_ZF(e) && (EmuX86_HasFlag_SF(e) == EmuX86_HasFlag_OF(e)))) {
case I_JGE: { // = 192 : Jump if greater or equal (SF=OF). continue;
if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_SF(e) == EmuX86_HasFlag_OF(e))) { }
continue; break;
} }
break; case I_JGE: { // = 192 : Jump if greater or equal (SF=OF).
} if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_SF(e) == EmuX86_HasFlag_OF(e))) {
case I_JL: { // = 188 : Jump if less (SF<>OF). continue;
if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_SF(e) != EmuX86_HasFlag_OF(e))) { }
continue; break;
} }
break; case I_JL: { // = 188 : Jump if less (SF<>OF).
} if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_SF(e) != EmuX86_HasFlag_OF(e))) {
case I_JLE: { // = 197 : Jump if less or equal (ZF=1 or SF<>OF). continue;
if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_ZF(e) || (EmuX86_HasFlag_SF(e) != EmuX86_HasFlag_OF(e)))) { }
continue; break;
} }
break; case I_JLE: { // = 197 : Jump if less or equal (ZF=1 or SF<>OF).
} if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_ZF(e) || (EmuX86_HasFlag_SF(e) != EmuX86_HasFlag_OF(e)))) {
case I_JMP: // = 462 : Jump continue;
case I_JMP_FAR: { // = 467 : Jump }
if (EmuX86_Opcode_JMP(e, info)) { break;
continue;
} }
break; case I_JMP: // = 462 : Jump
} case I_JMP_FAR: { // = 467 : Jump
case I_JNO: { // = 138 : Jump if not overflow (OF=0). if (EmuX86_Opcode_JMP(e, info)) {
if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_OF(e))) { continue;
continue; }
break;
} }
break; case I_JNO: { // = 138 : Jump if not overflow (OF=0).
} if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_OF(e))) {
case I_JNP: { // = 183 : Jump if not parity (PF=0). continue;
if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_PF(e))) { }
continue; break;
} }
break; case I_JNP: { // = 183 : Jump if not parity (PF=0).
} if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_PF(e))) {
case I_JNS: { // = 174 : Jump if not sign (SF=0). continue;
if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_SF(e))) { }
continue; break;
} }
break; case I_JNS: { // = 174 : Jump if not sign (SF=0).
} if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_SF(e))) {
case I_JNZ: { // = 156 : Jump if not zero (ZF=0). continue;
if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_ZF(e))) { }
continue; break;
} }
break; case I_JNZ: { // = 156 : Jump if not zero (ZF=0).
} if (EmuX86_Opcode_Jcc(e, info, !EmuX86_HasFlag_ZF(e))) {
case I_JO: { // = 134 : Jump if overflow (OF=1). continue;
if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_OF(e))) { }
continue; break;
} }
break; case I_JO: { // = 134 : Jump if overflow (OF=1).
} if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_OF(e))) {
case I_JP: { // = 179 : Jump if parity (PF=1). continue;
if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_PF(e))) { }
continue; break;
} }
break; case I_JP: { // = 179 : Jump if parity (PF=1).
} if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_PF(e))) {
case I_JS: { // = 170 : Jump if sign (SF=1). continue;
if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_SF(e))) { }
continue; break;
} }
break; case I_JS: { // = 170 : Jump if sign (SF=1).
} if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_SF(e))) {
case I_JZ: { // = 152 : Jump if zero (ZF = 1). continue;
if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_ZF(e))) { }
continue; break;
} }
break; case I_JZ: { // = 152 : Jump if zero (ZF = 1).
} if (EmuX86_Opcode_Jcc(e, info, EmuX86_HasFlag_ZF(e))) {
case I_LEA: { // = 223 : Load Effective Address continue;
if (EmuX86_Opcode_LEA(e, info)) break; }
goto opcode_error; break;
} }
case I_LFENCE: { // = 4287 : Serializes load operations. case I_LEA: { // = 223 : Load Effective Address
__asm { lfence }; // emulate as-is (doesn't cause exceptions) if (EmuX86_Opcode_LEA(e, info)) break;
break; goto opcode_error;
} }
case I_MFENCE: { // = 4313 : Serializes load and store operations. case I_LFENCE: { // = 4287 : Serializes load operations.
__asm { mfence }; // emulate as-is (doesn't cause exceptions) __asm { lfence }; // emulate as-is (doesn't cause exceptions)
break; break;
} }
case I_MOV: case I_MFENCE: { // = 4313 : Serializes load and store operations.
if (EmuX86_Opcode_MOV(e, info)) break; __asm { mfence }; // emulate as-is (doesn't cause exceptions)
goto opcode_error; break;
case I_MOVSX: }
if (EmuX86_Opcode_MOVSX(e, info)) break; case I_MOV:
goto opcode_error; if (EmuX86_Opcode_MOV(e, info)) break;
case I_MOVZX: goto opcode_error;
if (EmuX86_Opcode_MOVZX(e, info)) break; case I_MOVSX:
goto opcode_error; if (EmuX86_Opcode_MOVSX(e, info)) break;
case I_NOT: goto opcode_error;
if (EmuX86_Opcode_NOT(e, info)) break; case I_MOVZX:
goto opcode_error; if (EmuX86_Opcode_MOVZX(e, info)) break;
case I_OR: goto opcode_error;
if (EmuX86_Opcode_OR(e, info)) break; case I_NOT:
goto opcode_error; if (EmuX86_Opcode_NOT(e, info)) break;
case I_OUT: goto opcode_error;
if (EmuX86_Opcode_OUT(e, info)) break; case I_OR:
goto opcode_error; if (EmuX86_Opcode_OR(e, info)) break;
case I_POP: { // = 22 : Pop a Value from the Stack goto opcode_error;
if (EmuX86_Opcode_POP(e, info)) break; case I_OUT:
goto opcode_error; if (EmuX86_Opcode_OUT(e, info)) break;
} goto opcode_error;
case I_PUSH: { // = 16 : Push Word or Doubleword Onto the Stack case I_POP: { // = 22 : Pop a Value from the Stack
if (EmuX86_Opcode_PUSH(e, info)) break; if (EmuX86_Opcode_POP(e, info)) break;
goto opcode_error; goto opcode_error;
} }
// TODO : case I_RDPMC: // = 607 : Read Performance-Monitoring Counters; Privileged Level (Ring 0) Instruction. Causes a priviledge instruction exception case I_PUSH: { // = 16 : Push Word or Doubleword Onto the Stack
case I_RDTSC: // = 593 : Read Time-Stamp Counter if (EmuX86_Opcode_PUSH(e, info)) break;
EmuX86_Opcode_RDTSC(e); goto opcode_error;
break; }
case I_RET: // TODO : case I_RDPMC: // = 607 : Read Performance-Monitoring Counters; Privileged Level (Ring 0) Instruction. Causes a priviledge instruction exception
// RET and CALL always signify the end of a code block case I_RDTSC: // = 593 : Read Time-Stamp Counter
return true; EmuX86_Opcode_RDTSC(e);
case I_SAR: // = 1002 : Shift arithmetic right break;
EmuX86_Opcode_SAR(e, info); case I_RET:
break; // RET and CALL always signify the end of a code block
case I_SBB: return true;
if (EmuX86_Opcode_SBB(e, info)) break; case I_SAR: // = 1002 : Shift arithmetic right
goto opcode_error; EmuX86_Opcode_SAR(e, info);
case I_SETA: { // Set byte if above (CF=0 and ZF=0). break;
if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_CF(e) && !EmuX86_HasFlag_ZF(e))) break; case I_SBB:
goto opcode_error; if (EmuX86_Opcode_SBB(e, info)) break;
} goto opcode_error;
case I_SETAE: { // Set byte if above or equal (CF=0). case I_SETA: { // Set byte if above (CF=0 and ZF=0).
if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_CF(e))) break; if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_CF(e) && !EmuX86_HasFlag_ZF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETB: { // Set byte if below (CF=1). case I_SETAE: { // Set byte if above or equal (CF=0).
if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_CF(e))) break; if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_CF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETBE: { // Set byte if below or equal (CF=1 or ZF=1). case I_SETB: { // Set byte if below (CF=1).
if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_CF(e) || EmuX86_HasFlag_ZF(e))) break; if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_CF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETG: { // Set byte if greater (ZF=0 and SF=OF). case I_SETBE: { // Set byte if below or equal (CF=1 or ZF=1).
if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_ZF(e) && (EmuX86_HasFlag_SF(e) == EmuX86_HasFlag_OF(e)))) break; if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_CF(e) || EmuX86_HasFlag_ZF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETGE: { // Set byte if greater or equal (SF=OF). case I_SETG: { // Set byte if greater (ZF=0 and SF=OF).
if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_SF(e) == EmuX86_HasFlag_OF(e))) break; if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_ZF(e) && (EmuX86_HasFlag_SF(e) == EmuX86_HasFlag_OF(e)))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETL: { // Set byte if less (SF<>OF). case I_SETGE: { // Set byte if greater or equal (SF=OF).
if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_SF(e) != EmuX86_HasFlag_OF(e))) break; if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_SF(e) == EmuX86_HasFlag_OF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETLE: { // Set byte if less or equal (ZF=1 or SF<>OF). case I_SETL: { // Set byte if less (SF<>OF).
if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_ZF(e) || (EmuX86_HasFlag_SF(e) != EmuX86_HasFlag_OF(e)))) break; if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_SF(e) != EmuX86_HasFlag_OF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETNO: { // Set byte if not overflow (OF=0). case I_SETLE: { // Set byte if less or equal (ZF=1 or SF<>OF).
if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_OF(e))) break; if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_ZF(e) || (EmuX86_HasFlag_SF(e) != EmuX86_HasFlag_OF(e)))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETNP: { // Set byte if not parity (PF=0). case I_SETNO: { // Set byte if not overflow (OF=0).
if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_PF(e))) break; if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_OF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETNS: { // Set byte if not sign (SF=0). case I_SETNP: { // Set byte if not parity (PF=0).
if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_SF(e))) break; if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_PF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETNZ: { // Set byte if not zero (ZF=0). case I_SETNS: { // Set byte if not sign (SF=0).
if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_ZF(e))) break; if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_SF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETO: { // Set byte if overflow (OF=1). case I_SETNZ: { // Set byte if not zero (ZF=0).
if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_OF(e))) break; if (EmuX86_Opcode_SETcc(e, info, !EmuX86_HasFlag_ZF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETP: { // Set byte if parity (PF=1). case I_SETO: { // Set byte if overflow (OF=1).
if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_PF(e))) break; if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_OF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETS: { // Set byte if sign (SF=1). case I_SETP: { // Set byte if parity (PF=1).
if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_SF(e))) break; if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_PF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SETZ: { // Set byte if zero (ZF=1). case I_SETS: { // Set byte if sign (SF=1).
if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_ZF(e))) break; if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_SF(e))) break;
goto opcode_error; goto opcode_error;
} }
case I_SFENCE: { // = 4343 : Serializes store operations. case I_SETZ: { // Set byte if zero (ZF=1).
__asm { sfence }; // emulate as-is (doesn't cause exceptions) if (EmuX86_Opcode_SETcc(e, info, EmuX86_HasFlag_ZF(e))) break;
break; goto opcode_error;
} }
case I_SHL: case I_SFENCE: { // = 4343 : Serializes store operations.
if (EmuX86_Opcode_SHL(e, info)) break; __asm { sfence }; // emulate as-is (doesn't cause exceptions)
goto opcode_error; break;
case I_SHR: }
if (EmuX86_Opcode_SHR(e, info)) break; case I_SHL:
goto opcode_error; if (EmuX86_Opcode_SHL(e, info)) break;
case I_STI: { goto opcode_error;
// Enable all interrupts case I_SHR:
EmuX86_Opcode_STI(); if (EmuX86_Opcode_SHR(e, info)) break;
break; goto opcode_error;
} case I_STI: {
case I_SUB: // Enable all interrupts
if (EmuX86_Opcode_SUB(e, info)) break; EmuX86_Opcode_STI();
goto opcode_error; break;
case I_TEST: }
if (EmuX86_Opcode_TEST(e, info)) break; case I_SUB:
goto opcode_error; if (EmuX86_Opcode_SUB(e, info)) break;
case I_WBINVD: // Write back and flush internal caches; initiate writing-back and flushing of external caches. goto opcode_error;
break; // Privileged Level (Ring 0) Instruction. Causes a priviledge instruction exception - We can safely ignore this case I_TEST:
case I_WRMSR: if (EmuX86_Opcode_TEST(e, info)) break;
// We do not emulate processor specific registers just yet goto opcode_error;
// Some titles attempt to manually set the TSC via this instruction case I_WBINVD: // Write back and flush internal caches; initiate writing-back and flushing of external caches.
// This needs fixing eventually, but should be acceptible to ignore for now! break; // Privileged Level (Ring 0) Instruction. Causes a priviledge instruction exception - We can safely ignore this
// Chase: Hollywood Stunt Driver hits this case I_WRMSR:
EmuLog(LOG_PREFIX, LOG_LEVEL::WARNING, "WRMSR instruction ignored"); // We do not emulate processor specific registers just yet
break; // Some titles attempt to manually set the TSC via this instruction
case I_XOR: // This needs fixing eventually, but should be acceptible to ignore for now!
if (EmuX86_Opcode_XOR(e, info)) break; // Chase: Hollywood Stunt Driver hits this
goto opcode_error; EmuLog(LOG_PREFIX, LOG_LEVEL::WARNING, "WRMSR instruction ignored");
default: break;
EmuLog(LOG_PREFIX, LOG_LEVEL::WARNING, "Unhandled instruction : %u", info.opcode); case I_XOR:
// Fail if the first hit instruction couldn't be emulated, if (EmuX86_Opcode_XOR(e, info)) break;
// but let host CPU execute following (unhandled) instructions : goto opcode_error;
return (StartingEip != e->ContextRecord->Eip); default:
EmuLog(LOG_PREFIX, LOG_LEVEL::WARNING, "Unhandled instruction : %u", info.opcode);
// Fail if the first hit instruction couldn't be emulated,
// but let host CPU execute following (unhandled) instructions :
return (StartingEip != e->ContextRecord->Eip);
} // switch info.opcode } // switch info.opcode
// EmuLog(LOG_PREFIX, LOG_LEVEL::INFO, "Processed instruction : 0x%08X %u", e->ContextRecord->Eip, info.opcode);
e->ContextRecord->Eip += info.size; e->ContextRecord->Eip += info.size;
} // while true } // while true