NV2A : Make m_nv2a_state a pointer type, so that it can be zeroed during construction of the NV2ADevice (memset on the variable caused damage to the mutex-es and condition_variable's, so this is a work-around). A zeroed-out state prevents a crashes early in the unpatched CreateDevice code sequence.
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b146b0569f
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290f1f6036
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@ -617,8 +617,15 @@ void CxbxReserveNV2AMemory(NV2AState *d)
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NV2ADevice::NV2ADevice()
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{
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m_nv2a_state.pfifo.cache1.cache_lock = std::unique_lock<std::mutex>(m_nv2a_state.pfifo.cache1._cache_lock, std::defer_lock);
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m_nv2a_state.pgraph.lock = std::unique_lock<std::mutex>(m_nv2a_state.pgraph._lock, std::defer_lock);
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m_nv2a_state = new NV2AState();
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m_nv2a_state->pfifo.cache1.cache_lock = std::unique_lock<std::mutex>(m_nv2a_state->pfifo.cache1._cache_lock, std::defer_lock);
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m_nv2a_state->pgraph.lock = std::unique_lock<std::mutex>(m_nv2a_state->pgraph._lock, std::defer_lock);
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}
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NV2ADevice::~NV2ADevice()
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{
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delete m_nv2a_state;
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}
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// PCI Device functions
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@ -647,7 +654,7 @@ void NV2ADevice::Init()
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m_DeviceId = 0x02A5;
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m_VendorId = PCI_VENDOR_ID_NVIDIA;
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NV2AState *d = &m_nv2a_state; // glue
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NV2AState *d = m_nv2a_state; // glue
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CxbxReserveNV2AMemory(d);
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@ -693,15 +700,15 @@ uint32_t NV2ADevice::MMIORead(int barIndex, uint32_t addr, unsigned size)
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if (block != nullptr) {
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switch (size) {
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case sizeof(uint8_t) :
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return block->ops.read(&m_nv2a_state, addr - block->offset) & 0xFF;
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return block->ops.read(m_nv2a_state, addr - block->offset) & 0xFF;
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case sizeof(uint16_t) :
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assert((addr & 1) == 0); // TODO : What if this fails?
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return block->ops.read(&m_nv2a_state, addr - block->offset) & 0xFFFF;
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return block->ops.read(m_nv2a_state, addr - block->offset) & 0xFFFF;
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case sizeof(uint32_t) :
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assert((addr & 3) == 0); // TODO : What if this fails?
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return block->ops.read(&m_nv2a_state, addr - block->offset);
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return block->ops.read(m_nv2a_state, addr - block->offset);
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}
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}
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break;
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@ -732,24 +739,24 @@ void NV2ADevice::MMIOWrite(int barIndex, uint32_t addr, uint32_t value, unsigned
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switch (size) {
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case sizeof(uint8_t) :
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aligned_addr = addr & ~3;
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aligned_value = block->ops.read(&m_nv2a_state, aligned_addr - block->offset);
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aligned_value = block->ops.read(m_nv2a_state, aligned_addr - block->offset);
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shift = (addr & 3) * 8;
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mask = 0xFF << shift;
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block->ops.write(&m_nv2a_state, aligned_addr - block->offset, (aligned_value & ~mask) | (value << shift));
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block->ops.write(m_nv2a_state, aligned_addr - block->offset, (aligned_value & ~mask) | (value << shift));
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return;
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case sizeof(uint16_t) :
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assert((addr & 1) == 0); // TODO : What if this fails?
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aligned_addr = addr & ~3;
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aligned_value = block->ops.read(&m_nv2a_state, aligned_addr - block->offset);
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aligned_value = block->ops.read(m_nv2a_state, aligned_addr - block->offset);
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shift = (addr & 2) * 16;
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mask = 0xFFFF << shift;
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block->ops.write(&m_nv2a_state, aligned_addr - block->offset, (aligned_value & ~mask) | (value << shift));
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block->ops.write(m_nv2a_state, aligned_addr - block->offset, (aligned_value & ~mask) | (value << shift));
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return;
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case sizeof(uint32_t) :
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assert((addr & 3) == 0); // TODO : What if this fails?
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block->ops.write(&m_nv2a_state, addr - block->offset, value);
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block->ops.write(m_nv2a_state, addr - block->offset, value);
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return;
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}
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}
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@ -615,6 +615,8 @@ class NV2ADevice : public PCIDevice {
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public:
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// constructor
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NV2ADevice();
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// destructor
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~NV2ADevice();
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// PCI Device functions
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void Init();
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@ -625,5 +627,5 @@ public:
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uint32_t MMIORead(int barIndex, uint32_t addr, unsigned size);
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void MMIOWrite(int barIndex, uint32_t addr, uint32_t value, unsigned size);
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private:
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NV2AState m_nv2a_state;
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NV2AState *m_nv2a_state;
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};
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