More porting from XQEMU.
LLE execution now gets stuck on D3D_BlockOnTime. Could be lack of interrupts.
This commit is contained in:
Luke Usher
PatrickvL
parent
fb74bb8e9c
commit
03ce1333a4
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@ -124,13 +124,6 @@ inline int SET_MASK(int v, int mask, int val) {
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return (v) |= ((__val) << (ffs(__mask)-1)) & (__mask);
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}
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typedef struct DMAObject {
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unsigned int dma_class;
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unsigned int dma_target;
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xbaddr address;
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xbaddr limit;
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} DMAObject;
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enum FifoMode {
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FIFO_PIO = 0,
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FIFO_DMA = 1,
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@ -142,6 +135,142 @@ enum FIFOEngine {
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ENGINE_DVD = 2,
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};
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typedef struct RAMHTEntry {
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uint32_t handle;
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xbaddr instance;
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enum FIFOEngine engine;
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unsigned int channel_id : 5;
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bool valid;
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} RAMHTEntry;
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typedef struct DMAObject {
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unsigned int dma_class;
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unsigned int dma_target;
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xbaddr address;
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xbaddr limit;
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} DMAObject;
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typedef struct VertexAttribute {
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bool dma_select;
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xbaddr offset;
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/* inline arrays are packed in order?
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* Need to pass the offset to converted attributes */
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unsigned int inline_array_offset;
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float inline_value[4];
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unsigned int format;
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unsigned int size; /* size of the data type */
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unsigned int count; /* number of components */
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uint32_t stride;
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bool needs_conversion;
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uint8_t *converted_buffer;
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unsigned int converted_elements;
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unsigned int converted_size;
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unsigned int converted_count;
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float *inline_buffer;
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GLint gl_count;
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GLenum gl_type;
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GLboolean gl_normalize;
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GLuint gl_converted_buffer;
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GLuint gl_inline_buffer;
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} VertexAttribute;
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typedef struct Surface {
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bool draw_dirty;
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bool buffer_dirty;
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bool write_enabled_cache;
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unsigned int pitch;
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xbaddr offset;
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} Surface;
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typedef struct SurfaceShape {
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unsigned int z_format;
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unsigned int color_format;
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unsigned int zeta_format;
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unsigned int log_width, log_height;
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unsigned int clip_x, clip_y;
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unsigned int clip_width, clip_height;
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unsigned int anti_aliasing;
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} SurfaceShape;
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typedef struct TextureShape {
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bool cubemap;
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unsigned int dimensionality;
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unsigned int color_format;
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unsigned int levels;
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unsigned int width, height, depth;
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unsigned int min_mipmap_level, max_mipmap_level;
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unsigned int pitch;
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} TextureShape;
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typedef struct TextureKey {
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TextureShape state;
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uint64_t data_hash;
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uint8_t* texture_data;
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uint8_t* palette_data;
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} TextureKey;
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typedef struct TextureBinding {
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GLenum gl_target;
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GLuint gl_texture;
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unsigned int refcnt;
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} TextureBinding;
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typedef struct KelvinState {
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xbaddr dma_notifies;
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xbaddr dma_state;
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xbaddr dma_semaphore;
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unsigned int semaphore_offset;
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} KelvinState;
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typedef struct ContextSurfaces2DState {
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xbaddr dma_image_source;
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xbaddr dma_image_dest;
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unsigned int color_format;
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unsigned int source_pitch, dest_pitch;
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xbaddr source_offset, dest_offset;
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} ContextSurfaces2DState;
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typedef struct ImageBlitState {
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xbaddr context_surfaces;
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unsigned int operation;
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unsigned int in_x, in_y;
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unsigned int out_x, out_y;
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unsigned int width, height;
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} ImageBlitState;
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typedef struct GraphicsObject {
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uint8_t graphics_class;
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union {
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ContextSurfaces2DState context_surfaces_2d;
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ImageBlitState image_blit;
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KelvinState kelvin;
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} data;
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} GraphicsObject;
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typedef struct GraphicsSubchannel {
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xbaddr object_instance;
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GraphicsObject object;
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uint32_t object_cache[5];
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} GraphicsSubchannel;
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typedef struct GraphicsContext {
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bool channel_3d;
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unsigned int subchannel;
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} GraphicsContext;
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typedef struct CacheEntry {
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unsigned int method : 14;
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unsigned int subchannel : 3;
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@ -177,10 +306,10 @@ typedef struct Cache1State {
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enum FIFOEngine last_engine;
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/* The actual command queue */
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std::mutex cache_lock;
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std::mutex mutex;
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std::condition_variable cache_cond;
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std::queue<CacheEntry> cache;
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std::queue<CacheEntry> working_cache;
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std::queue<CacheEntry*> cache;
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//std::queue<CacheEntry*> working_cache;
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} Cache1State;
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typedef struct ChannelControl {
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@ -244,18 +373,16 @@ struct {
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ChannelControl channel_control[NV2A_NUM_CHANNELS];
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} user;
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typedef struct GraphicsContext {
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bool channel_3d;
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unsigned int subchannel;
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} GraphicsContext;
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struct {
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std::mutex mutex;
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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std::condition_variable interrupt_cond;
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xbaddr context_table;
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xbaddr context_address;
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uint32_t context_table;
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uint32_t context_address;
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unsigned int trapped_method;
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unsigned int trapped_subchannel;
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@ -264,11 +391,90 @@ struct {
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uint32_t notify_source;
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bool fifo_access;
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std::condition_variable fifo_access_cond;
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std::condition_variable flip_3d;
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unsigned int channel_id;
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bool channel_valid;
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GraphicsContext context[NV2A_NUM_CHANNELS];
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xbaddr dma_color, dma_zeta;
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Surface surface_color, surface_zeta;
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unsigned int surface_type;
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SurfaceShape surface_shape;
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SurfaceShape last_surface_shape;
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xbaddr dma_a, dma_b;
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//GLruCache *texture_cache;
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bool texture_dirty[NV2A_MAX_TEXTURES];
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TextureBinding *texture_binding[NV2A_MAX_TEXTURES];
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//GHashTable *shader_cache;
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//ShaderBinding *shader_binding;
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bool texture_matrix_enable[NV2A_MAX_TEXTURES];
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/* FIXME: Move to NV_PGRAPH_BUMPMAT... */
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float bump_env_matrix[NV2A_MAX_TEXTURES - 1][4]; /* 3 allowed stages with 2x2 matrix each */
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// wglContext *gl_context;
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GLuint gl_framebuffer;
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GLuint gl_color_buffer, gl_zeta_buffer;
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GraphicsSubchannel subchannel_data[NV2A_NUM_SUBCHANNELS];
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xbaddr dma_report;
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xbaddr report_offset;
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bool zpass_pixel_count_enable;
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unsigned int zpass_pixel_count_result;
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unsigned int gl_zpass_pixel_count_query_count;
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GLuint* gl_zpass_pixel_count_queries;
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xbaddr dma_vertex_a, dma_vertex_b;
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unsigned int primitive_mode;
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bool enable_vertex_program_write;
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//uint32_t program_data[NV2A_MAX_TRANSFORM_PROGRAM_LENGTH][VSH_TOKEN_SIZE];
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uint32_t vsh_constants[NV2A_VERTEXSHADER_CONSTANTS][4];
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bool vsh_constants_dirty[NV2A_VERTEXSHADER_CONSTANTS];
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/* lighting constant arrays */
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uint32_t ltctxa[NV2A_LTCTXA_COUNT][4];
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bool ltctxa_dirty[NV2A_LTCTXA_COUNT];
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uint32_t ltctxb[NV2A_LTCTXB_COUNT][4];
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bool ltctxb_dirty[NV2A_LTCTXB_COUNT];
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uint32_t ltc1[NV2A_LTC1_COUNT][4];
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bool ltc1_dirty[NV2A_LTC1_COUNT];
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// should figure out where these are in lighting context
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float light_infinite_half_vector[NV2A_MAX_LIGHTS][3];
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float light_infinite_direction[NV2A_MAX_LIGHTS][3];
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float light_local_position[NV2A_MAX_LIGHTS][3];
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float light_local_attenuation[NV2A_MAX_LIGHTS][3];
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//VertexAttribute vertex_attributes[NV2A_VERTEXSHADER_ATTRIBUTES];
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unsigned int inline_array_length;
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uint32_t inline_array[NV2A_MAX_BATCH_LENGTH];
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GLuint gl_inline_array_buffer;
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unsigned int inline_elements_length;
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uint32_t inline_elements[NV2A_MAX_BATCH_LENGTH];
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unsigned int inline_buffer_length;
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unsigned int draw_arrays_length;
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unsigned int draw_arrays_max_count;
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/* FIXME: Unknown size, possibly endless, 1000 will do for now */
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GLint gl_draw_arrays_start[1000];
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GLsizei gl_draw_arrays_count[1000];
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GLuint gl_element_buffer;
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GLuint gl_memory_buffer;
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GLuint gl_vertex_array;
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uint32_t regs[NV_PGRAPH_SIZE / sizeof(uint32_t)]; // TODO : union
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} pgraph;
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@ -699,6 +905,8 @@ static void pfifo_run_pusher() {
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if (!state->push_enabled) return;
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std::unique_lock<std::mutex> cache_lock(state->mutex, std::defer_lock);
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/* only handling DMA for now... */
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/* Channel running DMA */
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@ -732,16 +940,16 @@ static void pfifo_run_pusher() {
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/* data word of methods command */
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state->data_shadow = word;
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CacheEntry command;
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command.method = state->method;
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command.subchannel = state->subchannel;
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command.nonincreasing = state->method_nonincreasing;
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command.parameter = word;
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CacheEntry* command = new CacheEntry;
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command->method = state->method;
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command->subchannel = state->subchannel;
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command->nonincreasing = state->method_nonincreasing;
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command->parameter = word;
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state->cache_lock.lock();
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cache_lock.lock();
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state->cache.push(command);
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state->cache_cond.notify_all();
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state->cache_lock.unlock();
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cache_lock.unlock();
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if (!state->method_nonincreasing) {
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state->method += 4;
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@ -825,6 +1033,234 @@ static void pfifo_run_pusher() {
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}
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}
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static uint32_t ramht_hash(uint32_t handle)
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{
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unsigned int ramht_size = 1 << (GET_MASK(pfifo.regs[NV_PFIFO_RAMHT], NV_PFIFO_RAMHT_SIZE) + 12);
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/* XXX: Think this is different to what nouveau calculates... */
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unsigned int bits = ffs(ramht_size) - 2;
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uint32_t hash = 0;
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while (handle) {
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hash ^= (handle & ((1 << bits) - 1));
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handle >>= bits;
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}
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hash ^= pfifo.cache1.channel_id << (bits - 4);
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return hash;
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}
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static RAMHTEntry ramht_lookup(uint32_t handle)
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{
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unsigned int ramht_size = 1 << (GET_MASK(pfifo.regs[NV_PFIFO_RAMHT], NV_PFIFO_RAMHT_SIZE) + 12);
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uint32_t hash = ramht_hash(handle);
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assert(hash * 8 < ramht_size);
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uint32_t ramht_address =
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GET_MASK(pfifo.regs[NV_PFIFO_RAMHT],
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NV_PFIFO_RAMHT_BASE_ADDRESS) << 12;
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uint8_t *entry_ptr = (uint8_t*)(NV2A_ADDR + NV_PRAMIN_ADDR + ramht_address + hash * 8);
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uint32_t entry_handle = ldl_le_p((uint32_t*)entry_ptr);
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uint32_t entry_context = ldl_le_p((uint32_t*)(entry_ptr + 4));
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RAMHTEntry entry;
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entry.handle = entry_handle;
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entry.instance = (entry_context & NV_RAMHT_INSTANCE) << 4;
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entry.engine = (FIFOEngine)((entry_context & NV_RAMHT_ENGINE) >> 16);
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entry.channel_id = (entry_context & NV_RAMHT_CHID) >> 24;
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entry.valid = entry_context & NV_RAMHT_STATUS;
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return entry;
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}
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static void pgraph_context_switch(unsigned int channel_id)
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{
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std::unique_lock<std::mutex> pgraph_lock(pgraph.mutex, std::defer_lock);
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bool valid;
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valid = pgraph.channel_valid && pgraph.channel_id == channel_id;
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if (!valid) {
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pgraph.trapped_channel_id = channel_id;
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}
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if (!valid) {
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DbgPrintf("puller needs to switch to ch %d\n", channel_id);
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pgraph_lock.unlock();
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//qemu_mutex_lock_iothread();
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pgraph.pending_interrupts |= NV_PGRAPH_INTR_CONTEXT_SWITCH;
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update_irq();
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pgraph_lock.lock();
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//qemu_mutex_unlock_iothread();
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while (pgraph.pending_interrupts & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
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pgraph.interrupt_cond.wait(pgraph_lock);
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}
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}
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}
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static void pgraph_wait_fifo_access() {
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std::unique_lock<std::mutex> lk(pgraph.mutex, std::defer_lock);
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while (!pgraph.fifo_access) {
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pgraph.fifo_access_cond.wait(lk);
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}
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}
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static void pgraph_method_log(unsigned int subchannel, unsigned int graphics_class,unsigned int method, uint32_t parameter) {
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static unsigned int last = 0;
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static unsigned int count = 0;
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if (last == 0x1800 && method != last) {
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DbgPrintf("pgraph method (%d) 0x%08X * %d", subchannel, last, count);
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}
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if (method != 0x1800) {
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const char* method_name = NULL;
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unsigned int nmethod = 0;
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switch (graphics_class) {
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case NV_KELVIN_PRIMITIVE:
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nmethod = method | (0x5c << 16);
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break;
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case NV_CONTEXT_SURFACES_2D:
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nmethod = method | (0x6d << 16);
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break;
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default:
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break;
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}
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/*
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if (nmethod != 0 && nmethod < ARRAY_SIZE(nv2a_method_names)) {
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method_name = nv2a_method_names[nmethod];
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}
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if (method_name) {
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DbgPrintf("pgraph method (%d): %s (0x%x)\n",
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subchannel, method_name, parameter);
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}
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else {
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*/
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DbgPrintf("pgraph method (%d): 0x%x -> 0x%04x (0x%x)\n",
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subchannel, graphics_class, method, parameter);
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//}
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}
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if (method == last) { count++; }
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else { count = 0; }
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last = method;
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}
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static void pgraph_method(unsigned int subchannel, unsigned int method, uint32_t parameter)
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{
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int i;
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GraphicsSubchannel *subchannel_data;
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GraphicsObject *object;
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unsigned int slot;
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assert(pgraph.channel_valid);
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subchannel_data = &pgraph.subchannel_data[subchannel];
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object = &subchannel_data->object;
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ContextSurfaces2DState *context_surfaces_2d = &object->data.context_surfaces_2d;
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ImageBlitState *image_blit = &object->data.image_blit;
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KelvinState *kelvin = &object->data.kelvin;
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pgraph_method_log(subchannel, object->graphics_class, method, parameter);
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}
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static void* pfifo_puller_thread()
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{
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Cache1State *state = &pfifo.cache1;
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std::unique_lock<std::mutex> cache_lock(state->mutex, std::defer_lock);
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std::unique_lock<std::mutex> pgraph_lock(pgraph.mutex, std::defer_lock);
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while (true) {
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cache_lock.lock();
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while (state->cache.empty() || !state->pull_enabled) {
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state->cache_cond.wait(cache_lock);
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}
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cache_lock.unlock();
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pgraph_lock.lock();
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while (!state->cache.empty()) {
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CacheEntry * command = state->cache.front();
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state->cache.pop();
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if (command->method == 0) {
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// qemu_mutex_lock_iothread();
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RAMHTEntry entry = ramht_lookup(command->parameter);
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assert(entry.valid);
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assert(entry.channel_id == state->channel_id);
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// qemu_mutex_unlock_iothread();
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switch (entry.engine) {
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case ENGINE_GRAPHICS:
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pgraph_context_switch(entry.channel_id);
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pgraph_wait_fifo_access();
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pgraph_method(command->subchannel, 0, entry.instance);
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break;
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default:
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assert(false);
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break;
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}
|
||||
|
||||
/* the engine is bound to the subchannel */
|
||||
cache_lock.lock();
|
||||
state->bound_engines[command->subchannel] = entry.engine;
|
||||
state->last_engine = entry.engine;
|
||||
cache_lock.unlock();
|
||||
}
|
||||
else if (command->method >= 0x100) {
|
||||
/* method passed to engine */
|
||||
|
||||
uint32_t parameter = command->parameter;
|
||||
|
||||
/* methods that take objects.
|
||||
* TODO: Check this range is correct for the nv2a */
|
||||
if (command->method >= 0x180 && command->method < 0x200) {
|
||||
//qemu_mutex_lock_iothread();
|
||||
RAMHTEntry entry = ramht_lookup(parameter);
|
||||
assert(entry.valid);
|
||||
assert(entry.channel_id == state->channel_id);
|
||||
parameter = entry.instance;
|
||||
//qemu_mutex_unlock_iothread();
|
||||
}
|
||||
|
||||
// qemu_mutex_lock(&state->cache_lock);
|
||||
enum FIFOEngine engine = state->bound_engines[command->subchannel];
|
||||
// qemu_mutex_unlock(&state->cache_lock);
|
||||
|
||||
switch (engine) {
|
||||
case ENGINE_GRAPHICS:
|
||||
pgraph_wait_fifo_access();
|
||||
pgraph_method(command->subchannel, command->method, parameter);
|
||||
break;
|
||||
default:
|
||||
assert(false);
|
||||
break;
|
||||
}
|
||||
|
||||
// qemu_mutex_lock(&state->cache_lock);
|
||||
state->last_engine = state->bound_engines[command->subchannel];
|
||||
// qemu_mutex_unlock(&state->cache_lock);
|
||||
}
|
||||
|
||||
free(command);
|
||||
}
|
||||
|
||||
pgraph_lock.unlock();
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
DEVICE_READ32(PMC)
|
||||
{
|
||||
DEVICE_READ32_SWITCH() {
|
||||
|
|
@ -905,6 +1341,8 @@ DEVICE_WRITE32(PBUS)
|
|||
|
||||
DEVICE_READ32(PFIFO)
|
||||
{
|
||||
std::unique_lock<std::mutex> cache_lock(pfifo.cache1.mutex, std::defer_lock);
|
||||
|
||||
DEVICE_READ32_SWITCH() {
|
||||
case NV_PFIFO_RAMHT:
|
||||
result = 0x03000100; // = NV_PFIFO_RAMHT_SIZE_4K | NV_PFIFO_RAMHT_BASE_ADDRESS(NumberOfPaddingBytes >> 12) | NV_PFIFO_RAMHT_SEARCH_128
|
||||
|
|
@ -929,13 +1367,13 @@ DEVICE_READ32(PFIFO)
|
|||
SET_MASK(result, NV_PFIFO_CACHE1_PUSH1_MODE, pfifo.cache1.mode);
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_STATUS:
|
||||
pfifo.cache1.cache_lock.lock();
|
||||
cache_lock.lock();
|
||||
|
||||
if (pfifo.cache1.cache.empty()) {
|
||||
result |= NV_PFIFO_CACHE1_STATUS_LOW_MARK; /* low mark empty */
|
||||
}
|
||||
|
||||
pfifo.cache1.cache_lock.unlock();
|
||||
cache_lock.unlock();
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_DMA_PUSH:
|
||||
SET_MASK(result, NV_PFIFO_CACHE1_DMA_PUSH_ACCESS,
|
||||
|
|
@ -971,16 +1409,16 @@ DEVICE_READ32(PFIFO)
|
|||
| pfifo.cache1.subroutine_active;
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_PULL0:
|
||||
pfifo.cache1.cache_lock.lock();
|
||||
cache_lock.lock();
|
||||
result = pfifo.cache1.pull_enabled;
|
||||
pfifo.cache1.cache_lock.unlock();
|
||||
cache_lock.unlock();
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_ENGINE:
|
||||
pfifo.cache1.cache_lock.lock();
|
||||
cache_lock.lock();
|
||||
for (int i = 0; i<NV2A_NUM_SUBCHANNELS; i++) {
|
||||
result |= pfifo.cache1.bound_engines[i] << (i * 2);
|
||||
}
|
||||
pfifo.cache1.cache_lock.unlock();
|
||||
cache_lock.unlock();
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_DMA_DCOUNT:
|
||||
result = pfifo.cache1.dcount;
|
||||
|
|
@ -1004,6 +1442,8 @@ DEVICE_READ32(PFIFO)
|
|||
|
||||
DEVICE_WRITE32(PFIFO)
|
||||
{
|
||||
std::unique_lock<std::mutex> cache_lock(pfifo.cache1.mutex, std::defer_lock);
|
||||
|
||||
switch(addr) {
|
||||
case NV_PFIFO_INTR_0:
|
||||
pfifo.pending_interrupts &= ~value;
|
||||
|
|
@ -1050,7 +1490,7 @@ DEVICE_WRITE32(PFIFO)
|
|||
pfifo.cache1.subroutine_active = (value & NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE);
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_PULL0:
|
||||
pfifo.cache1.cache_lock.lock();
|
||||
cache_lock.lock();
|
||||
|
||||
if ((value & NV_PFIFO_CACHE1_PULL0_ACCESS)
|
||||
&& !pfifo.cache1.pull_enabled) {
|
||||
|
|
@ -1062,14 +1502,14 @@ DEVICE_WRITE32(PFIFO)
|
|||
&& pfifo.cache1.pull_enabled) {
|
||||
pfifo.cache1.pull_enabled = false;
|
||||
}
|
||||
pfifo.cache1.cache_lock.unlock();
|
||||
cache_lock.unlock();
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_ENGINE:
|
||||
pfifo.cache1.cache_lock.lock();
|
||||
cache_lock.lock();
|
||||
for (int i = 0; i<NV2A_NUM_SUBCHANNELS; i++) {
|
||||
pfifo.cache1.bound_engines[i] = (FIFOEngine)((value >> (i * 2)) & 3);
|
||||
}
|
||||
pfifo.cache1.cache_lock.unlock();
|
||||
cache_lock.unlock();
|
||||
break;
|
||||
case NV_PFIFO_CACHE1_DMA_DCOUNT:
|
||||
pfifo.cache1.dcount = (value & NV_PFIFO_CACHE1_DMA_DCOUNT_VALUE);
|
||||
|
|
@ -2201,4 +2641,7 @@ void EmuNV2A_Init()
|
|||
pramdac.core_clock_freq = 189000000;
|
||||
pramdac.memory_clock_coeff = 0;
|
||||
pramdac.video_clock_coeff = 0x0003C20D; /* 25182Khz...? */
|
||||
|
||||
MessageBoxA(NULL, "TEST", "TEST", 0);
|
||||
pfifo.puller_thread = std::thread(pfifo_puller_thread);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue