724 lines
23 KiB
C#
724 lines
23 KiB
C#
using System;
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namespace BizHawk.Emulation.CPUs.M68000
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{
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partial class MC68000
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{
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bool TestCondition(int condition)
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{
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switch (condition)
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{
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case 0x00: return true; // True
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case 0x01: return false; // False
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case 0x02: return !C && !Z; // High (Unsigned)
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case 0x03: return C || Z; // Less or Same (Unsigned)
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case 0x04: return !C; // Carry Clear (High or Same)
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case 0x05: return C; // Carry Set (Lower)
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case 0x06: return !Z; // Not Equal
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case 0x07: return Z; // Equal
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case 0x08: return !V; // Overflow Clear
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case 0x09: return V; // Overflow Set
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case 0x0A: return !N; // Plus (Positive)
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case 0x0B: return N; // Minus (Negative)
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case 0x0C: return N && V || !N && !V; // Greater or Equal
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case 0x0D: return N && !V || !N && V; // Less Than
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case 0x0E: return N && V && !Z || !N && !V && !Z; // Greater Than
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case 0x0F: return Z || N && !V || !N && V; // Less or Equal
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default:
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throw new Exception("Invalid condition "+condition);
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}
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}
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string DisassembleCondition(int condition)
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{
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switch (condition)
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{
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case 0x00: return "t"; // True
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case 0x01: return "f"; // False
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case 0x02: return "hi"; // High (Unsigned)
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case 0x03: return "ls"; // Less or Same (Unsigned)
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case 0x04: return "cc"; // Carry Clear (High or Same)
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case 0x05: return "cs"; // Carry Set (Lower)
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case 0x06: return "ne"; // Not Equal
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case 0x07: return "eq"; // Equal
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case 0x08: return "vc"; // Overflow Clear
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case 0x09: return "vs"; // Overflow Set
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case 0x0A: return "pl"; // Plus (Positive)
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case 0x0B: return "mi"; // Minus (Negative)
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case 0x0C: return "ge"; // Greater or Equal
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case 0x0D: return "lt"; // Less Than
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case 0x0E: return "gt"; // Greater Than
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case 0x0F: return "le"; // Less or Equal
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default: return "??"; // Invalid condition
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}
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}
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void Bcc() // Branch on condition
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{
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sbyte displacement8 = (sbyte) op;
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int cond = (op >> 8) & 0x0F;
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if (TestCondition(cond) == true)
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{
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if (displacement8 != 0)
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{
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// use opcode-embedded displacement
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PC += displacement8;
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PendingCycles -= 10;
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} else {
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// use extension word displacement
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PC += ReadWord(PC);
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PendingCycles -= 10;
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}
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} else { // false
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if (displacement8 != 0)
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PendingCycles -= 8;
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else {
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PC += 2;
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PendingCycles -= 12;
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}
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}
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}
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void Bcc_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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sbyte displacement8 = (sbyte)op;
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int cond = (op >> 8) & 0x0F;
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info.Mnemonic = "b" + DisassembleCondition(cond);
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if (displacement8 != 0)
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{
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info.Args = string.Format("${0:X}", pc + displacement8);
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} else {
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info.Args = string.Format("${0:X}", pc + ReadWord(pc));
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pc += 2;
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}
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info.Length = pc - info.PC;
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}
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void BRA()
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{
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sbyte displacement8 = (sbyte)op;
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if (displacement8 != 0)
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PC += displacement8;
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else
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PC += ReadWord(PC);
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PendingCycles -= 10;
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}
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void BRA_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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info.Mnemonic = "bra";
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sbyte displacement8 = (sbyte)op;
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if (displacement8 != 0)
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info.Args = String.Format("${0:X}", pc + displacement8);
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else
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{
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info.Args = String.Format("${0:X}", pc + ReadWord(pc));
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pc += 2;
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}
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info.Length = pc - info.PC;
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}
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void BSR()
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{
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sbyte displacement8 = (sbyte)op;
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A[7].s32 -= 4;
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if (displacement8 != 0)
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{
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// use embedded displacement
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WriteLong(A[7].s32, PC);
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PC += displacement8;
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} else {
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// use extension word displacement
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WriteLong(A[7].s32, PC + 2);
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PC += ReadWord(PC);
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}
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PendingCycles -= 18;
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}
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void BSR_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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info.Mnemonic = "bsr";
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sbyte displacement8 = (sbyte)op;
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if (displacement8 != 0)
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info.Args = String.Format("${0:X}", pc + displacement8);
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else {
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info.Args = String.Format("${0:X}", pc + ReadWord(pc));
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pc += 2;
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}
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info.Length = pc - info.PC;
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}
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void DBcc()
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{
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if (TestCondition((op >> 8) & 0x0F) == true)
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{
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PC += 2; // condition met, break out of loop
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PendingCycles -= 12;
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} else {
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int reg = op & 7;
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D[reg].u16--;
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if (D[reg].u16 == 0xFFFF)
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{
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PC += 2; // counter underflowed, break out of loop
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PendingCycles -= 14;
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} else {
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PC += ReadWord(PC); // condition false and counter not exhausted, so branch.
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PendingCycles -= 10;
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}
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}
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}
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void DBcc_Disasm(DisassemblyInfo info)
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{
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int cond = (op >> 8) & 0x0F;
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if (cond == 1)
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info.Mnemonic = "dbra";
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else
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info.Mnemonic = "db" + DisassembleCondition(cond);
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int pc = info.PC + 2;
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info.Args = String.Format("D{0}, ${1:X}", op & 7, pc + ReadWord(pc));
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info.Length = 4;
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}
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void RTS()
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{
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PC = ReadLong(A[7].s32);
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A[7].s32 += 4;
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PendingCycles -= 16;
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}
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void RTS_Disasm(DisassemblyInfo info)
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{
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info.Mnemonic = "rts";
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info.Args = "";
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}
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void RTR()
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{
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ushort sr = (ushort)ReadWord(A[7].s32);
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A[7].s32 += 2;
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C = (sr & 0x0001) != 0;
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V = (sr & 0x0002) != 0;
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Z = (sr & 0x0004) != 0;
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N = (sr & 0x0008) != 0;
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X = (sr & 0x0010) != 0;
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PC = ReadLong(A[7].s32);
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A[7].s32 += 4;
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PendingCycles -= 20;
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}
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void RTR_Disasm(DisassemblyInfo info)
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{
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info.Mnemonic = "rtr";
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info.Args = "";
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}
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void RTE()
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{
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short newSR = ReadWord(A[7].s32);
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A[7].s32 += 2;
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PC = ReadLong(A[7].s32);
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A[7].s32 += 4;
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SR = newSR;
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PendingCycles -= 20;
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}
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void RTE_Disasm(DisassemblyInfo info)
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{
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info.Mnemonic = "rte";
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info.Args = "";
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}
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void TST()
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{
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int size = (op >> 6) & 3;
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int mode = (op >> 3) & 7;
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int reg = (op >> 0) & 7;
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int value;
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switch (size)
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{
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case 0: value = ReadValueB(mode, reg); PendingCycles -= 4 + EACyclesBW[mode, reg]; N = (value & 0x80) !=0; break;
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case 1: value = ReadValueW(mode, reg); PendingCycles -= 4 + EACyclesBW[mode, reg]; N = (value & 0x8000) !=0; break;
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default: value = ReadValueL(mode, reg); PendingCycles -= 4 + EACyclesL[mode, reg]; N = (value & 0x80000000) !=0; break;
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}
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V = false;
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C = false;
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Z = (value == 0);
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}
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void TST_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int size = (op >> 6) & 3;
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int mode = (op >> 3) & 7;
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int reg = (op >> 0) & 7;
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switch (size)
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{
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case 0: info.Mnemonic = "tst.b"; info.Args = DisassembleValue(mode, reg, 1, ref pc); break;
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case 1: info.Mnemonic = "tst.w"; info.Args = DisassembleValue(mode, reg, 2, ref pc); break;
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case 2: info.Mnemonic = "tst.l"; info.Args = DisassembleValue(mode, reg, 4, ref pc); break;
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}
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info.Length = pc - info.PC;
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}
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void BTSTi()
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{
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int bit = ReadWord(PC); PC += 2;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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if (mode == 0)
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{
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bit &= 31;
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int mask = 1 << bit;
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Z = (D[reg].s32 & mask) == 0;
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PendingCycles -= 10;
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} else {
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bit &= 7;
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int mask = 1 << bit;
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Z = (ReadValueB(mode, reg) & mask) == 0;
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PendingCycles -= 8 + EACyclesBW[mode, reg];
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}
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}
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void BTSTi_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int bit = ReadWord(pc); pc += 2;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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info.Mnemonic = "btst";
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info.Args = String.Format("${0:X}, {1}", bit, DisassembleValue(mode, reg, 1, ref pc));
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info.Length = pc - info.PC;
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}
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void BTSTr()
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{
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int dReg = (op >> 9) & 7;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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int bit = D[dReg].s32;
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if (mode == 0)
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{
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bit &= 31;
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int mask = 1 << bit;
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Z = (D[reg].s32 & mask) == 0;
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PendingCycles -= 6;
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}
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else
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{
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bit &= 7;
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int mask = 1 << bit;
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Z = (ReadValueB(mode, reg) & mask) == 0;
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PendingCycles -= 4 + EACyclesBW[mode, reg];
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}
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}
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void BTSTr_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int dReg = (op >> 9) & 7;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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info.Mnemonic = "btst";
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info.Args = String.Format("D{0}, {1}", dReg, DisassembleValue(mode, reg, 1, ref pc));
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info.Length = pc - info.PC;
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}
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void BCHGi()
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{
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int bit = ReadWord(PC); PC += 2;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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if (mode == 0)
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{
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bit &= 31;
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int mask = 1 << bit;
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Z = (D[reg].s32 & mask) == 0;
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D[reg].s32 ^= mask;
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PendingCycles -= 10;
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}
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else
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{
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bit &= 7;
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int mask = 1 << bit;
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sbyte value = PeekValueB(mode, reg);
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Z = (value & mask) == 0;
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value ^= (sbyte) mask;
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WriteValueB(mode, reg, value);
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PendingCycles -= 8 + EACyclesBW[mode, reg];
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}
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}
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void BCHGi_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int bit = ReadWord(pc); pc += 2;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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info.Mnemonic = "bchg";
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info.Args = String.Format("${0:X}, {1}", bit, DisassembleValue(mode, reg, 1, ref pc));
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info.Length = pc - info.PC;
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}
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void BCHGr()
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{
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int dReg = (op >> 9) & 7;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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int bit = D[dReg].s32;
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if (mode == 0)
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{
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bit &= 31;
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int mask = 1 << bit;
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Z = (D[reg].s32 & mask) == 0;
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D[reg].s32 ^= mask;
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PendingCycles -= 6;
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}
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else
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{
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bit &= 7;
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int mask = 1 << bit;
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sbyte value = PeekValueB(mode, reg);
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Z = (value & mask) == 0;
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value ^= (sbyte) mask;
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WriteValueB(mode, reg, value);
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PendingCycles -= 4 + EACyclesBW[mode, reg];
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}
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}
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void BCHGr_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int dReg = (op >> 9) & 7;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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info.Mnemonic = "bchg";
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info.Args = String.Format("D{0}, {1}", dReg, DisassembleValue(mode, reg, 1, ref pc));
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info.Length = pc - info.PC;
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}
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void BCLRi()
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{
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int bit = ReadWord(PC); PC += 2;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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if (mode == 0)
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{
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bit &= 31;
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int mask = 1 << bit;
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Z = (D[reg].s32 & mask) == 0;
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D[reg].s32 &= ~mask;
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PendingCycles -= 10;
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}
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else
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{
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bit &= 7;
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int mask = 1 << bit;
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sbyte value = PeekValueB(mode, reg);
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Z = (value & mask) == 0;
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value &= (sbyte) ~mask;
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WriteValueB(mode, reg, value);
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PendingCycles -= 8 + EACyclesBW[mode, reg];
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}
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}
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void BCLRi_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int bit = ReadWord(pc); pc += 2;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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info.Mnemonic = "bclr";
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info.Args = String.Format("${0:X}, {1}", bit, DisassembleValue(mode, reg, 1, ref pc));
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info.Length = pc - info.PC;
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}
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void BCLRr()
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{
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int dReg = (op >> 9) & 7;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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int bit = D[dReg].s32;
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if (mode == 0)
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{
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bit &= 31;
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int mask = 1 << bit;
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Z = (D[reg].s32 & mask) == 0;
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D[reg].s32 &= ~mask;
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PendingCycles -= 6;
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}
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else
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{
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bit &= 7;
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int mask = 1 << bit;
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sbyte value = PeekValueB(mode, reg);
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Z = (value & mask) == 0;
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value &= (sbyte) ~mask;
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WriteValueB(mode, reg, value);
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PendingCycles -= 4 + EACyclesBW[mode, reg];
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}
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}
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void BCLRr_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int dReg = (op >> 9) & 7;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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info.Mnemonic = "bclr";
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info.Args = String.Format("D{0}, {1}", dReg, DisassembleValue(mode, reg, 1, ref pc));
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info.Length = pc - info.PC;
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}
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void BSETi()
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{
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int bit = ReadWord(PC); PC += 2;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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if (mode == 0)
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{
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bit &= 31;
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int mask = 1 << bit;
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Z = (D[reg].s32 & mask) == 0;
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D[reg].s32 |= mask;
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PendingCycles -= 10;
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}
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else
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{
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bit &= 7;
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int mask = 1 << bit;
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sbyte value = PeekValueB(mode, reg);
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Z = (value & mask) == 0;
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value |= (sbyte) mask;
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WriteValueB(mode, reg, value);
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PendingCycles -= 8 + EACyclesBW[mode, reg];
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}
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}
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void BSETi_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int bit = ReadWord(pc); pc += 2;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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info.Mnemonic = "bset";
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info.Args = String.Format("${0:X}, {1}", bit, DisassembleValue(mode, reg, 1, ref pc));
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info.Length = pc - info.PC;
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}
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void BSETr()
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{
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int dReg = (op >> 9) & 7;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
|
|
int bit = D[dReg].s32;
|
|
|
|
if (mode == 0)
|
|
{
|
|
bit &= 31;
|
|
int mask = 1 << bit;
|
|
Z = (D[reg].s32 & mask) == 0;
|
|
D[reg].s32 |= mask;
|
|
PendingCycles -= 6;
|
|
}
|
|
else
|
|
{
|
|
bit &= 7;
|
|
int mask = 1 << bit;
|
|
sbyte value = PeekValueB(mode, reg);
|
|
Z = (value & mask) == 0;
|
|
value |= (sbyte) mask;
|
|
WriteValueB(mode, reg, value);
|
|
PendingCycles -= 4 + EACyclesBW[mode, reg];
|
|
}
|
|
}
|
|
|
|
void BSETr_Disasm(DisassemblyInfo info)
|
|
{
|
|
int pc = info.PC + 2;
|
|
int dReg = (op >> 9) & 7;
|
|
int mode = (op >> 3) & 7;
|
|
int reg = op & 7;
|
|
|
|
info.Mnemonic = "bset";
|
|
info.Args = String.Format("D{0}, {1}", dReg, DisassembleValue(mode, reg, 1, ref pc));
|
|
info.Length = pc - info.PC;
|
|
}
|
|
|
|
void JMP()
|
|
{
|
|
int mode = (op >> 3) & 7;
|
|
int reg = (op >> 0) & 7;
|
|
PC = ReadAddress(mode, reg);
|
|
|
|
switch (mode)
|
|
{
|
|
case 2: PendingCycles -= 8; break;
|
|
case 5: PendingCycles -= 10; break;
|
|
case 6: PendingCycles -= 14; break;
|
|
case 7:
|
|
switch (reg)
|
|
{
|
|
case 0: PendingCycles -= 10; break;
|
|
case 1: PendingCycles -= 12; break;
|
|
case 2: PendingCycles -= 10; break;
|
|
case 3: PendingCycles -= 14; break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
void JMP_Disasm(DisassemblyInfo info)
|
|
{
|
|
int pc = info.PC + 2;
|
|
int mode = (op >> 3) & 7;
|
|
int reg = (op >> 0) & 7;
|
|
info.Mnemonic = "jmp";
|
|
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
|
info.Length = pc - info.PC;
|
|
}
|
|
|
|
void JSR()
|
|
{
|
|
int mode = (op >> 3) & 7;
|
|
int reg = (op >> 0) & 7;
|
|
int addr = ReadAddress(mode, reg);
|
|
|
|
A[7].s32 -= 4;
|
|
WriteLong(A[7].s32, PC);
|
|
PC = addr;
|
|
|
|
switch (mode)
|
|
{
|
|
case 2: PendingCycles -= 16; break;
|
|
case 5: PendingCycles -= 18; break;
|
|
case 6: PendingCycles -= 22; break;
|
|
case 7:
|
|
switch (reg)
|
|
{
|
|
case 0: PendingCycles -= 18; break;
|
|
case 1: PendingCycles -= 20; break;
|
|
case 2: PendingCycles -= 18; break;
|
|
case 3: PendingCycles -= 22; break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
void JSR_Disasm(DisassemblyInfo info)
|
|
{
|
|
int pc = info.PC + 2;
|
|
int mode = (op >> 3) & 7;
|
|
int reg = (op >> 0) & 7;
|
|
info.Mnemonic = "jsr";
|
|
info.Args = DisassembleAddress(mode, reg, ref pc);
|
|
info.Length = pc - info.PC;
|
|
}
|
|
|
|
void LINK()
|
|
{
|
|
int reg = op & 7;
|
|
A[7].s32 -= 4;
|
|
short offset = ReadWord(PC); PC += 2;
|
|
WriteLong(A[7].s32, A[reg].s32);
|
|
A[reg].s32 = A[7].s32;
|
|
A[7].s32 += offset;
|
|
PendingCycles -= 16;
|
|
}
|
|
|
|
void LINK_Disasm(DisassemblyInfo info)
|
|
{
|
|
int pc = info.PC + 2;
|
|
int reg = op & 7;
|
|
info.Mnemonic = "link";
|
|
info.Args = "A"+reg+", "+DisassembleImmediate(2, ref pc); // TODO need a DisassembleSigned or something
|
|
info.Length = pc - info.PC;
|
|
}
|
|
|
|
void UNLK()
|
|
{
|
|
int reg = op & 7;
|
|
A[7].s32 = A[reg].s32;
|
|
A[reg].s32 = ReadLong(A[7].s32);
|
|
A[7].s32 += 4;
|
|
PendingCycles -= 12;
|
|
}
|
|
|
|
void UNLK_Disasm(DisassemblyInfo info)
|
|
{
|
|
int reg = op & 7;
|
|
info.Mnemonic = "unlk";
|
|
info.Args = "A" + reg;
|
|
info.Length = 2;
|
|
}
|
|
|
|
void NOP()
|
|
{
|
|
PendingCycles -= 4;
|
|
}
|
|
|
|
void NOP_Disasm(DisassemblyInfo info)
|
|
{
|
|
info.Mnemonic = "nop";
|
|
}
|
|
|
|
void Scc() // Set on condition
|
|
{
|
|
int cond = (op >> 8) & 0x0F;
|
|
int mode = (op >> 3) & 7;
|
|
int reg = (op >> 0) & 7;
|
|
|
|
if (TestCondition(cond) == true)
|
|
{
|
|
WriteValueB(mode, reg, -1);
|
|
if (mode == 0) PendingCycles -= 6;
|
|
else PendingCycles -= 8 + EACyclesBW[mode, reg];
|
|
} else {
|
|
WriteValueB(mode, reg, 0);
|
|
if (mode == 0) PendingCycles -= 4;
|
|
else PendingCycles -= 8 + EACyclesBW[mode, reg];
|
|
}
|
|
}
|
|
|
|
void Scc_Disasm(DisassemblyInfo info)
|
|
{
|
|
int pc = info.PC + 2;
|
|
int cond = (op >> 8) & 0x0F;
|
|
int mode = (op >> 3) & 7;
|
|
int reg = (op >> 0) & 7;
|
|
|
|
info.Mnemonic = "s" + DisassembleCondition(cond);
|
|
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
|
info.Length = pc - info.PC;
|
|
}
|
|
}
|
|
}
|