380 lines
11 KiB
C#
380 lines
11 KiB
C#
using System;
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namespace BizHawk.Emulation.Computers.Commodore64.MOS
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{
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// emulates the PLA
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// which handles all bank switching
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public class MOSPLA
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{
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// ------------------------------------
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public Func<int, byte> PeekBasicRom;
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public Func<int, byte> PeekCartridgeLo;
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public Func<int, byte> PeekCartridgeHi;
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public Func<int, byte> PeekCharRom;
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public Func<int, byte> PeekCia0;
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public Func<int, byte> PeekCia1;
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public Func<int, byte> PeekColorRam;
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public Func<int, byte> PeekExpansionLo;
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public Func<int, byte> PeekExpansionHi;
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public Func<int, byte> PeekKernalRom;
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public Func<int, byte> PeekMemory;
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public Func<int, byte> PeekSid;
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public Func<int, byte> PeekVic;
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public Action<int, byte> PokeCartridgeLo;
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public Action<int, byte> PokeCartridgeHi;
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public Action<int, byte> PokeCia0;
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public Action<int, byte> PokeCia1;
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public Action<int, byte> PokeColorRam;
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public Action<int, byte> PokeExpansionLo;
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public Action<int, byte> PokeExpansionHi;
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public Action<int, byte> PokeMemory;
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public Action<int, byte> PokeSid;
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public Action<int, byte> PokeVic;
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public Func<bool> ReadAEC;
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public Func<bool> ReadBA;
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public Func<int, byte> ReadBasicRom;
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public Func<int, byte> ReadCartridgeLo;
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public Func<int, byte> ReadCartridgeHi;
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public Func<bool> ReadCharen;
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public Func<int, byte> ReadCharRom;
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public Func<int, byte> ReadCia0;
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public Func<int, byte> ReadCia1;
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public Func<int, byte> ReadColorRam;
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public Func<int, byte> ReadExpansionLo;
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public Func<int, byte> ReadExpansionHi;
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public Func<bool> ReadExRom;
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public Func<bool> ReadGame;
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public Func<bool> ReadHiRam;
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public Func<int, byte> ReadKernalRom;
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public Func<bool> ReadLoRam;
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public Func<int, byte> ReadMemory;
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public Func<int, byte> ReadSid;
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public Func<int, byte> ReadVic;
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public Action<int, byte> WriteCartridgeLo;
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public Action<int, byte> WriteCartridgeHi;
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public Action<int, byte> WriteCia0;
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public Action<int, byte> WriteCia1;
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public Action<int, byte> WriteColorRam;
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public Action<int, byte> WriteExpansionLo;
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public Action<int, byte> WriteExpansionHi;
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public Action<int, byte> WriteMemory;
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public Action<int, byte> WriteSid;
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public Action<int, byte> WriteVic;
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// ------------------------------------
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private enum PLABank
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{
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None,
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RAM,
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BasicROM,
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KernalROM,
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CharROM,
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IO,
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CartridgeLo,
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CartridgeHi,
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Vic,
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Sid,
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ColorRam,
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Cia0,
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Cia1,
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Expansion0,
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Expansion1
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}
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// ------------------------------------
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bool p0;
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bool p1;
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bool p2;
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bool p3;
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bool p4;
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bool p5;
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bool p6;
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bool p7;
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bool p9;
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bool p10;
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bool p11;
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bool p12;
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bool p13;
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bool p14;
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bool p15;
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bool p16;
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bool p17;
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bool p18;
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bool p19;
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bool p20;
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bool p21;
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bool p22;
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bool p23;
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bool p24;
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bool p25;
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bool p26;
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bool p27;
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bool p28;
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bool p30;
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bool loram;
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bool hiram;
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bool game;
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bool exrom;
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bool charen;
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bool a15;
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bool a14;
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bool a13;
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bool a12;
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bool aec;
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bool cas;
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private PLABank Bank(int addr, bool read)
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{
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loram = ReadLoRam();
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hiram = ReadHiRam();
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game = ReadGame();
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a15 = (addr & 0x08000) != 0;
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a14 = (addr & 0x04000) != 0;
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a13 = (addr & 0x02000) != 0;
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a12 = (addr & 0x01000) != 0;
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aec = !ReadAEC(); //active low
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p0 = loram && hiram && a15 && !a14 && a13 && !aec && read && game;
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if (p0)
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return PLABank.BasicROM;
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exrom = ReadExRom();
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p1 = hiram && a15 && a14 && a13 && !aec && read && game;
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p2 = hiram && a15 && a14 && a13 && !aec && read && !exrom && !game;
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if (p1 || p2)
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return PLABank.KernalROM;
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charen = ReadCharen();
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p3 = hiram && !charen && a15 && a14 && !a13 && a12 && !aec && read && game;
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p4 = loram && !charen && a15 && a14 && !a13 && a12 && !aec && read && game;
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p5 = hiram && !charen && a15 && a14 && !a13 && a12 && !aec && read && !exrom && !game;
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p6 = a14 && !a13 && a12 && aec && game;
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p7 = a14 && !a13 && a12 && aec && !exrom && !game;
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if (p3 || p4 || p5 || p6 || p7)
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return PLABank.CharROM;
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p9 = hiram && charen && a15 && a14 && !a13 && a12 && !aec && read && game;
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p10 = hiram && charen && a15 && a14 && !a13 && a12 && !aec && !read && game;
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p11 = loram && charen && a15 && a14 && !a13 && a12 && !aec && read && game;
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p12 = loram && charen && a15 && a14 && !a13 && a12 && !aec && !read && game;
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p13 = hiram && charen && a15 && a14 && !a13 && a12 && !aec && read && !exrom && !game;
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p14 = hiram && charen && a15 && a14 && !a13 && a12 && !aec && !read && !exrom && !game;
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p15 = loram && charen && a15 && a14 && !a13 && a12 && !aec && read && !exrom && !game;
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p16 = loram && charen && a15 && a14 && !a13 && a12 && !aec && !read && !exrom && !game;
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p17 = a15 && a14 && !a13 && a12 && !aec && read && exrom && !game;
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p18 = a15 && a14 && !a13 && a12 && !aec && !read && exrom && !game;
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if (p9 || p10 || p11 || p12 || p13 || p14 || p15 || p16 || p17 || p18)
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{
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switch (addr & 0x0F00)
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{
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case 0x000:
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case 0x100:
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case 0x200:
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case 0x300:
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return PLABank.Vic;
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case 0x400:
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case 0x500:
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case 0x600:
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case 0x700:
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return PLABank.Sid;
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case 0x800:
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case 0x900:
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case 0xA00:
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case 0xB00:
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return PLABank.ColorRam;
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case 0xC00:
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return PLABank.Cia0;
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case 0xD00:
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return PLABank.Cia1;
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case 0xE00:
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return PLABank.Expansion0;
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case 0xF00:
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return PLABank.Expansion1;
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}
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return PLABank.IO;
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}
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p19 = loram && hiram && a15 && !a14 && !a13 && !aec && read && !exrom;
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p20 = a15 && !a14 && !a13 && !aec && exrom && !game;
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if (p19 || p20)
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return PLABank.CartridgeLo;
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p21 = hiram && a15 && !a14 && a13 && !aec && read && !exrom && !game;
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p22 = a15 && a14 && a13 && !aec && exrom && !game;
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p23 = a13 && a12 && aec && exrom && !game;
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if (p21 || p22 || p23)
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return PLABank.CartridgeHi;
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cas = !true; //active low
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p24 = !a15 && !a14 && a12 && exrom && !game;
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p25 = !a15 && !a14 && a13 && exrom && !game;
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p26 = !a15 && a14 && exrom && !game;
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p27 = a15 && !a14 && a13 && exrom && !game;
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p28 = a15 && a14 && !a13 && !a12 && exrom && !game;
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p30 = cas;
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if (!(p24 || p25 || p26 || p27 || p28 || p30))
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return PLABank.RAM;
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//p31 = !cas && a15 && a14 && !a13 && a12 && !aec && !read;
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//grw = p31;
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return PLABank.None;
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}
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public byte Peek(int addr)
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{
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addr &= 0x0FFFF;
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switch (Bank(addr, true))
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{
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case PLABank.BasicROM:
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return PeekBasicRom(addr);
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case PLABank.CartridgeHi:
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return PeekCartridgeHi(addr);
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case PLABank.CartridgeLo:
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return PeekCartridgeLo(addr);
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case PLABank.CharROM:
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return PeekCharRom(addr);
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case PLABank.Cia0:
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return PeekCia0(addr);
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case PLABank.Cia1:
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return PeekCia1(addr);
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case PLABank.ColorRam:
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return PeekColorRam(addr);
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case PLABank.Expansion0:
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return PeekExpansionLo(addr);
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case PLABank.Expansion1:
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return PeekExpansionHi(addr);
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case PLABank.KernalROM:
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return PeekKernalRom(addr);
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case PLABank.RAM:
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return PeekMemory(addr);
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case PLABank.Sid:
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return PeekSid(addr);
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case PLABank.Vic:
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return PeekVic(addr);
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}
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return 0xFF;
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}
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public void Poke(int addr, byte val)
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{
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addr &= 0x0FFFF;
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switch (Bank(addr, false))
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{
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case PLABank.CartridgeHi:
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PokeCartridgeHi(addr, val);
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break;
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case PLABank.CartridgeLo:
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PokeCartridgeLo(addr, val);
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break;
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case PLABank.Cia0:
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PokeCia0(addr, val);
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break;
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case PLABank.Cia1:
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PokeCia1(addr, val);
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break;
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case PLABank.ColorRam:
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PokeColorRam(addr, val);
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break;
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case PLABank.Expansion0:
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PokeExpansionLo(addr, val);
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break;
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case PLABank.Expansion1:
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PokeExpansionHi(addr, val);
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break;
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case PLABank.RAM:
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PokeMemory(addr, val);
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break;
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case PLABank.Sid:
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PokeSid(addr, val);
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break;
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case PLABank.Vic:
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PokeVic(addr, val);
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break;
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}
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}
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public byte Read(int addr)
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{
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addr &= 0x0FFFF;
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switch (Bank(addr, true))
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{
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case PLABank.BasicROM:
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return ReadBasicRom(addr);
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case PLABank.CartridgeHi:
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return ReadCartridgeHi(addr);
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case PLABank.CartridgeLo:
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return ReadCartridgeLo(addr);
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case PLABank.CharROM:
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return ReadCharRom(addr);
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case PLABank.Cia0:
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return ReadCia0(addr);
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case PLABank.Cia1:
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return ReadCia1(addr);
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case PLABank.ColorRam:
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return ReadColorRam(addr);
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case PLABank.Expansion0:
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return ReadExpansionLo(addr);
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case PLABank.Expansion1:
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return ReadExpansionHi(addr);
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case PLABank.KernalROM:
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return ReadKernalRom(addr);
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case PLABank.RAM:
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return ReadMemory(addr);
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case PLABank.Sid:
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return ReadSid(addr);
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case PLABank.Vic:
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return ReadVic(addr);
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}
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return 0xFF;
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}
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public void Write(int addr, byte val)
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{
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addr &= 0x0FFFF;
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switch (Bank(addr, false))
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{
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case PLABank.BasicROM:
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break;
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case PLABank.CartridgeHi:
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WriteCartridgeHi(addr, val);
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WriteMemory(addr, val);
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break;
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case PLABank.CartridgeLo:
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WriteCartridgeLo(addr, val);
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WriteMemory(addr, val);
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break;
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case PLABank.Cia0:
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WriteCia0(addr, val);
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break;
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case PLABank.Cia1:
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WriteCia1(addr, val);
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break;
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case PLABank.ColorRam:
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WriteColorRam(addr, val);
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break;
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case PLABank.Expansion0:
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WriteExpansionLo(addr, val);
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return;
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case PLABank.Expansion1:
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WriteExpansionHi(addr, val);
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return;
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case PLABank.RAM:
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WriteMemory(addr, val);
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break;
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case PLABank.Sid:
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WriteSid(addr, val);
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break;
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case PLABank.Vic:
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WriteVic(addr, val);
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break;
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}
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}
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}
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}
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