350 lines
19 KiB
C#
350 lines
19 KiB
C#
using System;
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namespace BizHawk.Emulation.Common.Components.MC6809
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{
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public partial class MC6809
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{
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private ulong totalExecutedCycles;
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public ulong TotalExecutedCycles { get { return totalExecutedCycles; } set { totalExecutedCycles = value; } }
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private int EI_pending;
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private bool interrupts_enabled;
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// variables for executing instructions
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public int instr_pntr = 0;
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public ushort[] cur_instr;
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public int opcode;
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public bool halted;
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public bool stopped;
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public bool jammed;
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public int LY;
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public void FetchInstruction(byte opcode)
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{
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switch (opcode)
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{
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case 0x00: DIRECT_MEM(NEG); break; // NEG (Direct)
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case 0x01: ILLEGAL(); break; // ILLEGAL
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case 0x02: ILLEGAL(); break; // ILLEGAL
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case 0x03: DIRECT_MEM(COM); break; // COM (Direct)
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case 0x04: DIRECT_MEM(LSR); break; // LSR (Direct)
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case 0x05: ILLEGAL(); break; // ILLEGAL
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case 0x06: DIRECT_MEM(ROR); break; // ROR (Direct)
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case 0x07: DIRECT_MEM(ASR); break; // ASR (Direct)
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case 0x08: DIRECT_MEM(ASL); break; // ASL , LSL (Direct)
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case 0x09: DIRECT_MEM(ROL); break; // ROL (Direct)
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case 0x0A: DIRECT_MEM(DEC8); break; // DEC (Direct)
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case 0x0B: ILLEGAL(); break; // ILLEGAL
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case 0x0C: DIRECT_MEM(INC8); break; // INC (Direct)
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case 0x0D: DIRECT_MEM(TST); break; // TST (Direct)
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case 0x0E: JMP_DIR_(); break; // JMP (Direct)
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case 0x0F: DIRECT_MEM(CLR); break; // CLR (Direct)
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case 0x10: PAGE_2(); break; // Page 2
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case 0x11: PAGE_3(); break; // Page 3
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case 0x12: NOP_(); break; // NOP (Inherent)
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case 0x13: SYNC_(); break; // SYNC (Inherent)
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case 0x14: ILLEGAL(); break; // ILLEGAL
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case 0x15: ILLEGAL(); break; // ILLEGAL
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case 0x16: LBR_(true); break; // LBRA (Relative)
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case 0x17: LBSR_(); break; // LBSR (Relative)
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case 0x18: ILLEGAL(); break; // ILLEGAL
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case 0x19: REG_OP(DA, A); break; // DAA (Inherent)
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case 0x1A: REG_OP_IMD_CC(OR8); break; // ORCC (Immediate)
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case 0x1B: ILLEGAL(); break; // ILLEGAL
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case 0x1C: REG_OP_IMD_CC(AND8); break; // ANDCC (Immediate)
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case 0x1D: REG_OP(SEX, A); break; // SEX (Inherent)
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case 0x1E: EXG_(); break; // EXG (Immediate)
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case 0x1F: TFR_(); break; // TFR (Immediate)
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case 0x20: BR_(true); break; // BRA (Relative)
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case 0x21: BR_(false); break; // BRN (Relative)
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case 0x22: BR_(!(FlagC | FlagZ)); break; // BHI (Relative)
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case 0x23: BR_(FlagC | FlagZ); break; // BLS (Relative)
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case 0x24: BR_(!FlagC); break; // BHS , BCC (Relative)
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case 0x25: BR_(FlagC); break; // BLO , BCS (Relative)
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case 0x26: BR_(!FlagZ); break; // BNE (Relative)
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case 0x27: BR_(FlagZ); break; // BEQ (Relative)
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case 0x28: BR_(!FlagV); break; // BVC (Relative)
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case 0x29: BR_(FlagV); break; // BVS (Relative)
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case 0x2A: BR_(!FlagN); break; // BPL (Relative)
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case 0x2B: BR_(FlagN); break; // BMI (Relative)
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case 0x2C: BR_(FlagN == FlagV); break; // BGE (Relative)
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case 0x2D: BR_(FlagN ^ FlagV); break; // BLT (Relative)
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case 0x2E: BR_((!FlagZ) & (FlagN == FlagV)); break; // BGT (Relative)
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case 0x2F: BR_(FlagZ | (FlagN ^ FlagV)); break; // BLE (Relative)
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case 0x30: INDEX_OP(LEAX); break; // LEAX (Indexed)
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case 0x31: INDEX_OP(LEAY); break; // LEAY (Indexed)
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case 0x32: INDEX_OP(LEAS); break; // LEAS (Indexed)
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case 0x33: INDEX_OP(LEAU); break; // LEAU (Indexed)
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case 0x34: PSH(SP); break; // PSHS (Immediate)
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case 0x35: PUL(SP); break; // PULS (Immediate)
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case 0x36: PSH(US); break; // PSHU (Immediate)
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case 0x37: PUL(US); break; // PULU (Immediate)
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case 0x38: ILLEGAL(); break; // ILLEGAL
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case 0x39: RTS(); break; // RTS (Inherent)
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case 0x3A: ABX_(); break; // ABX (Inherent)
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case 0x3B: RTI(); break; // RTI (Inherent)
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case 0x3C: CWAI_(); break; // CWAI (Inherent)
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case 0x3D: MUL_(); break; // MUL (Inherent)
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case 0x3E: ILLEGAL(); break; // ILLEGAL
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case 0x3F: SWI1(); break; // SWI (Inherent)
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case 0x40: REG_OP(NEG, A); break; // NEGA (Inherent)
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case 0x41: ILLEGAL(); break; // ILLEGAL
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case 0x42: ILLEGAL(); break; // ILLEGAL
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case 0x43: REG_OP(COM, A); break; // COMA (Inherent)
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case 0x44: REG_OP(LSR, A); break; // LSRA (Inherent)
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case 0x45: ILLEGAL(); break; // ILLEGAL
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case 0x46: REG_OP(ROR, A); break; // RORA (Inherent)
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case 0x47: REG_OP(ASR, A); break; // ASRA (Inherent)
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case 0x48: REG_OP(ASL, A); break; // ASLA , LSLA (Inherent)
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case 0x49: REG_OP(ROL, A); break; // ROLA (Inherent)
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case 0x4A: REG_OP(DEC8, A); break; // DECA (Inherent)
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case 0x4B: ILLEGAL(); break; // ILLEGAL
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case 0x4C: REG_OP(INC8, A); break; // INCA (Inherent)
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case 0x4D: REG_OP(TST, A); break; // TSTA (Inherent)
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case 0x4E: ILLEGAL(); break; // ILLEGAL
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case 0x4F: REG_OP(CLR, A); break; // CLRA (Inherent)
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case 0x50: REG_OP(NEG, B); break; // NEGB (Inherent)
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case 0x51: ILLEGAL(); break; // ILLEGAL
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case 0x52: ILLEGAL(); break; // ILLEGAL
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case 0x53: REG_OP(COM, B); break; // COMB (Inherent)
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case 0x54: REG_OP(LSR, B); break; // LSRB (Inherent)
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case 0x55: ILLEGAL(); break; // ILLEGAL
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case 0x56: REG_OP(ROR, B); break; // RORB (Inherent)
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case 0x57: REG_OP(ASR, B); break; // ASRB (Inherent)
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case 0x58: REG_OP(ASL, B); break; // ASLB , LSLB (Inherent)
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case 0x59: REG_OP(ROL, B); break; // ROLB (Inherent)
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case 0x5A: REG_OP(DEC8, B); break; // DECB (Inherent)
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case 0x5B: ILLEGAL(); break; // ILLEGAL
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case 0x5C: REG_OP(INC8, B); break; // INCB (Inherent)
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case 0x5D: REG_OP(TST, B); break; // TSTB (Inherent)
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case 0x5E: ILLEGAL(); break; // ILLEGAL
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case 0x5F: REG_OP(CLR, B); break; // CLRB (Inherent)
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case 0x60: INDEX_OP(I_NEG); break; // NEG (Indexed)
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case 0x61: ILLEGAL(); break; // ILLEGAL
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case 0x62: ILLEGAL(); break; // ILLEGAL
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case 0x63: INDEX_OP(I_COM); break; // COM (Indexed)
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case 0x64: INDEX_OP(I_LSR); break; // LSR (Indexed)
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case 0x65: ILLEGAL(); break; // ILLEGAL
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case 0x66: INDEX_OP(I_ROR); break; // ROR (Indexed)
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case 0x67: INDEX_OP(I_ASR); break; // ASR (Indexed)
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case 0x68: INDEX_OP(I_ASL); break; // ASL , LSL (Indexed)
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case 0x69: INDEX_OP(I_ROL); break; // ROL (Indexed)
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case 0x6A: INDEX_OP(I_DEC); break; // DEC (Indexed)
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case 0x6B: ILLEGAL(); break; // ILLEGAL
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case 0x6C: INDEX_OP(I_INC); break; // INC (Indexed)
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case 0x6D: INDEX_OP(I_TST); break; // TST (Indexed)
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case 0x6E: INDEX_OP(I_JMP); break; // JMP (Indexed)
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case 0x6F: INDEX_OP(I_CLR); break; // CLR (Indexed)
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case 0x70: EXT_MEM(NEG); break; // NEG (Extended)
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case 0x71: ILLEGAL(); break; // ILLEGAL
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case 0x72: ILLEGAL(); break; // ILLEGAL
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case 0x73: EXT_MEM(COM); break; // COM (Extended)
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case 0x74: EXT_MEM(LSR); break; // LSR (Extended)
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case 0x75: ILLEGAL(); break; // ILLEGAL
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case 0x76: EXT_MEM(ROR); break; // ROR (Extended)
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case 0x77: EXT_MEM(ASR); break; // ASR (Extended)
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case 0x78: EXT_MEM(ASL); break; // ASL , LSL (Extended)
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case 0x79: EXT_MEM(ROL); break; // ROL (Extended)
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case 0x7A: EXT_MEM(DEC8); break; // DEC (Extended)
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case 0x7B: ILLEGAL(); break; // ILLEGAL
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case 0x7C: EXT_MEM(INC8); break; // INC (Extended)
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case 0x7D: EXT_MEM(TST); break; // TST (Extended)
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case 0x7E: JMP_EXT_(); break; // JMP (Extended)
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case 0x7F: EXT_MEM(CLR); break; // CLR (Extended)
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case 0x80: REG_OP(ADD8, A); break; // SUBA (Immediate)
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case 0x81: REG_OP(ADD8, A); break; // CMPA (Immediate)
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case 0x82: REG_OP(ADD8, A); break; // SBCA (Immediate)
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case 0x83: REG_OP(ADD8, A); break; // SUBD (Immediate)
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case 0x84: REG_OP(ADD8, A); break; // ANDA (Immediate)
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case 0x85: REG_OP(ADD8, A); break; // BITA (Immediate)
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case 0x86: REG_OP(ADD8, A); break; // LDA (Immediate)
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case 0x87: ILLEGAL(); break; // ILLEGAL
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case 0x88: REG_OP(ADC8, A); break; // EORA (Immediate)
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case 0x89: REG_OP(ADC8, A); break; // ADCA (Immediate)
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case 0x8A: REG_OP(ADC8, A); break; // ORA (Immediate)
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case 0x8B: REG_OP(ADC8, A); break; // ADDA (Immediate)
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case 0x8C: REG_OP(ADC8, A); break; // CMPX (Immediate)
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case 0x8D: REG_OP(ADC8, A); break; // BSR (Relative)
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case 0x8E: REG_OP(ADC8, A); break; // LDX (Immediate)
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case 0x8F: ILLEGAL(); break; // ILLEGAL
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case 0x90: REG_OP(ADD8, A); break; // SUBA (Direct)
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case 0x91: REG_OP(ADD8, A); break; // CMPA (Direct)
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case 0x92: REG_OP(ADD8, A); break; // SBCA (Direct)
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case 0x93: REG_OP(ADD8, A); break; // SUBD (Direct)
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case 0x94: REG_OP(ADD8, A); break; // ANDA (Direct)
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case 0x95: REG_OP(ADD8, A); break; // BITA (Direct)
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case 0x96: REG_OP(ADD8, A); break; // LDA (Direct)
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case 0x97: REG_OP(ADD8, A); break; // STA (Direct)
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case 0x98: REG_OP(ADC8, A); break; // EORA (Direct)
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case 0x99: REG_OP(ADC8, A); break; // ADCA (Direct)
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case 0x9A: REG_OP(ADC8, A); break; // ORA (Direct)
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case 0x9B: REG_OP(ADC8, A); break; // ADDA (Direct)
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case 0x9C: REG_OP(ADC8, A); break; // CMPX (Direct)
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case 0x9D: REG_OP(ADC8, A); break; // JSR (Direct)
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case 0x9E: REG_OP(ADC8, A); break; // LDX (Direct)
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case 0x9F: REG_OP(ADC8, A); break; // STX (Direct)
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case 0xA0: REG_OP(AND8, A); break; // SUBA (Indexed)
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case 0xA1: REG_OP(AND8, A); break; // CMPA (Indexed)
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case 0xA2: REG_OP(AND8, A); break; // SBCA (Indexed)
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case 0xA3: REG_OP(AND8, A); break; // SUBD (Indexed)
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case 0xA4: REG_OP(AND8, A); break; // ANDA (Indexed)
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case 0xA5: REG_OP(AND8, A); break; // BITA (Indexed)
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case 0xA6: REG_OP(AND8, A); break; // LDA (Indexed)
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case 0xA7: REG_OP(AND8, A); break; // STA (Indexed)
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case 0xA8: REG_OP(XOR8, A); break; // EORA (Indexed)
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case 0xA9: REG_OP(XOR8, A); break; // ADCA (Indexed)
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case 0xAA: REG_OP(XOR8, A); break; // ORA (Indexed)
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case 0xAB: REG_OP(XOR8, A); break; // ADDA (Indexed)
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case 0xAC: REG_OP(XOR8, A); break; // CMPX (Indexed)
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case 0xAD: REG_OP(XOR8, A); break; // JSR (Indexed)
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case 0xAE: REG_OP(XOR8, A); break; // LDX (Indexed)
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case 0xAF: REG_OP(XOR8, A); break; // STX (Indexed)
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case 0xB0: REG_OP(AND8, A); break; // SUBA (Extended)
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case 0xB1: REG_OP(AND8, A); break; // CMPA (Extended)
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case 0xB2: REG_OP(AND8, A); break; // SBCA (Extended)
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case 0xB3: REG_OP(AND8, A); break; // SUBD (Extended)
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case 0xB4: REG_OP(AND8, A); break; // ANDA (Extended)
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case 0xB5: REG_OP(AND8, A); break; // BITA (Extended)
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case 0xB6: REG_OP(AND8, A); break; // LDA (Extended)
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case 0xB7: REG_OP(AND8, A); break; // STA (Extended)
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case 0xB8: REG_OP(XOR8, A); break; // EORA (Extended)
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case 0xB9: REG_OP(XOR8, A); break; // ADCA (Extended)
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case 0xBA: REG_OP(XOR8, A); break; // ORA (Extended)
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case 0xBB: REG_OP(XOR8, A); break; // ADDA (Extended)
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case 0xBC: REG_OP(XOR8, A); break; // CMPX (Extended)
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case 0xBD: REG_OP(XOR8, A); break; // JSR (Extended)
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case 0xBE: REG_OP(XOR8, A); break; // LDX (Extended)
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case 0xBF: REG_OP(XOR8, A); break; // STX (Extended)
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case 0xC0: REG_OP(ADD8, A); break; // SUBB (Immediate)
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case 0xC1: REG_OP(ADD8, A); break; // CMPB (Immediate)
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case 0xC2: REG_OP(ADD8, A); break; // SBCB (Immediate)
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case 0xC3: REG_OP(ADD8, A); break; // ADDD (Immediate)
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case 0xC4: REG_OP(ADD8, A); break; // ANDB (Immediate)
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case 0xC5: REG_OP(ADD8, A); break; // BITB (Immediate)
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case 0xC6: REG_OP(ADD8, A); break; // LDB (Immediate)
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case 0xC7: ILLEGAL(); break; // ILLEGAL
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case 0xC8: REG_OP(ADC8, A); break; // EORB (Immediate)
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case 0xC9: REG_OP(ADC8, A); break; // ADCB (Immediate)
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case 0xCA: REG_OP(ADC8, A); break; // ORB (Immediate)
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case 0xCB: REG_OP(ADC8, A); break; // ADDB (Immediate)
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case 0xCC: REG_OP(ADC8, A); break; // LDD (Immediate)
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case 0xCD: ILLEGAL(); break; // ILLEGAL
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case 0xCE: REG_OP(ADC8, A); break; // LDU (Immediate)
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case 0xCF: ILLEGAL(); break; // ILLEGAL
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case 0xD0: REG_OP(ADD8, B); break; // SUBB (Direct)
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case 0xD1: REG_OP(ADD8, B); break; // CMPB (Direct)
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case 0xD2: REG_OP(ADD8, B); break; // SBCB (Direct)
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case 0xD3: REG_OP(ADD8, B); break; // ADDD (Direct)
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case 0xD4: REG_OP(ADD8, B); break; // ANDB (Direct)
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case 0xD5: REG_OP(ADD8, B); break; // BITB (Direct)
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case 0xD6: REG_OP(ADD8, B); break; // LDB (Direct)
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case 0xD7: REG_OP(ADD8, B); break; // STB (Direct)
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case 0xD8: REG_OP(ADC8, B); break; // EORB (Direct)
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case 0xD9: REG_OP(ADC8, B); break; // ADCB (Direct)
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case 0xDA: REG_OP(ADC8, B); break; // ORB (Direct)
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case 0xDB: REG_OP(ADC8, B); break; // ADDB (Direct)
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case 0xDC: REG_OP(ADC8, B); break; // LDD (Direct)
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case 0xDD: REG_OP(ADC8, B); break; // STD (Direct)
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case 0xDE: REG_OP(ADC8, B); break; // LDU (Direct)
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case 0xDF: REG_OP(ADC8, B); break; // STU (Direct)
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case 0xE0: REG_OP(AND8, B); break; // SUBB (Indexed)
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case 0xE1: REG_OP(AND8, B); break; // CMPB (Indexed)
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case 0xE2: REG_OP(AND8, B); break; // SBCB (Indexed)
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case 0xE3: REG_OP(AND8, B); break; // ADDD (Indexed)
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case 0xE4: REG_OP(AND8, B); break; // ANDB (Indexed)
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case 0xE5: REG_OP(AND8, B); break; // BITB (Indexed)
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case 0xE6: REG_OP(AND8, B); break; // LDB (Indexed)
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case 0xE7: REG_OP(AND8, B); break; // STB (Indexed)
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case 0xE8: REG_OP(XOR8, B); break; // EORB (Indexed)
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case 0xE9: REG_OP(XOR8, B); break; // ADCB (Indexed)
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case 0xEA: REG_OP(XOR8, B); break; // ORB (Indexed)
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case 0xEB: REG_OP(XOR8, B); break; // ADDB (Indexed)
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case 0xEC: REG_OP(XOR8, B); break; // LDD (Indexed)
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case 0xED: REG_OP(XOR8, B); break; // STD (Indexed)
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case 0xEE: REG_OP(XOR8, B); break; // LDU (Indexed)
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case 0xEF: REG_OP(XOR8, B); break; // STU (Indexed)
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case 0xF0: REG_OP(AND8, B); break; // SUBB (Extended)
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case 0xF1: REG_OP(AND8, B); break; // CMPB (Extended)
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case 0xF2: REG_OP(AND8, B); break; // SBCB (Extended)
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case 0xF3: REG_OP(AND8, B); break; // ADDD (Extended)
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case 0xF4: REG_OP(AND8, B); break; // ANDB (Extended)
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case 0xF5: REG_OP(AND8, B); break; // BITB (Extended)
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case 0xF6: REG_OP(AND8, B); break; // LDB (Extended)
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case 0xF7: REG_OP(AND8, B); break; // STB (Extended)
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case 0xF8: REG_OP(XOR8, B); break; // EORB (Extended)
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case 0xF9: REG_OP(XOR8, B); break; // ADCB (Extended)
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case 0xFA: REG_OP(XOR8, B); break; // ORB (Extended)
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case 0xFB: REG_OP(XOR8, B); break; // ADDB (Extended)
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case 0xFC: REG_OP(XOR8, B); break; // LDD (Extended)
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case 0xFD: REG_OP(XOR8, B); break; // STD (Extended)
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case 0xFE: REG_OP(XOR8, B); break; // LDU (Extended)
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case 0xFF: REG_OP(XOR8, B); break; // STU (Extended)
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}
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}
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public void FetchInstruction2(byte opcode)
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{
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switch (opcode)
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{
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case 0x21: REG_OP(XOR8, B); break; // LBRN (Relative)
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case 0x22: REG_OP(XOR8, B); break; // LBHI (Relative)
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case 0x23: REG_OP(XOR8, B); break; // LBLS (Relative)
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case 0x24: REG_OP(XOR8, B); break; // LBHS , LBCC (Relative)
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case 0x25: REG_OP(XOR8, B); break; // LBCS , LBLO (Relative)
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case 0x26: REG_OP(XOR8, B); break; // LBNE (Relative)
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case 0x27: REG_OP(XOR8, B); break; // LBEQ (Relative)
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case 0x28: REG_OP(XOR8, B); break; // LBVC (Relative)
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case 0x29: REG_OP(XOR8, B); break; // LBVS (Relative)
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case 0x2A: REG_OP(XOR8, B); break; // LBPL (Relative)
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case 0x2B: REG_OP(XOR8, B); break; // LBMI (Relative)
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case 0x2C: REG_OP(XOR8, B); break; // LBGE (Relative)
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case 0x2D: REG_OP(XOR8, B); break; // LBLT (Relative)
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case 0x2E: REG_OP(XOR8, B); break; // LBGT (Relative)
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case 0x2F: REG_OP(XOR8, B); break; // LBLE (Relative)
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case 0x3F: REG_OP(XOR8, B); break; // SWI2 (Inherent)
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case 0x83: REG_OP(XOR8, B); break; // CMPD (Immediate)
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case 0x8C: REG_OP(XOR8, B); break; // CMPY (Immediate)
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case 0x8E: REG_OP(XOR8, B); break; // LDY (Immediate)
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case 0x93: REG_OP(XOR8, B); break; // CMPD (Direct)
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case 0x9C: REG_OP(XOR8, B); break; // CMPY (Direct)
|
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case 0x9E: REG_OP(XOR8, B); break; // LDY (Direct)
|
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case 0x9F: REG_OP(XOR8, B); break; // STY (Direct)
|
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case 0xA3: REG_OP(XOR8, B); break; // CMPD (Indexed)
|
|
case 0xAC: REG_OP(XOR8, B); break; // CMPY (Indexed)
|
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case 0xAE: REG_OP(XOR8, B); break; // LDY (Indexed)
|
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case 0xAF: REG_OP(XOR8, B); break; // STY (Indexed)
|
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case 0xB3: REG_OP(XOR8, B); break; // CMPD (Extended)
|
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case 0xBC: REG_OP(XOR8, B); break; // CMPY (Extended)
|
|
case 0xBE: REG_OP(XOR8, B); break; // LDY (Extended)
|
|
case 0xBF: REG_OP(XOR8, B); break; // STY (Extended)
|
|
case 0xCE: REG_OP(XOR8, B); break; // LDS (Immediate)
|
|
case 0xDE: REG_OP(XOR8, B); break; // LDS (Direct)
|
|
case 0xDF: REG_OP(XOR8, B); break; // STS (Direct)
|
|
case 0xEE: REG_OP(XOR8, B); break; // LDS (Indexed)
|
|
case 0xEF: REG_OP(XOR8, B); break; // STS (Indexed)
|
|
case 0xFE: REG_OP(XOR8, B); break; // LDS (Extended)
|
|
case 0xFF: REG_OP(XOR8, B); break; // STS (Extended)
|
|
|
|
default: ILLEGAL(); break;
|
|
}
|
|
}
|
|
|
|
public void FetchInstruction3(byte opcode)
|
|
{
|
|
switch (opcode)
|
|
{
|
|
case 0x3F: REG_OP(XOR8, B); break; // SWI3 (Inherent)
|
|
case 0x83: REG_OP(XOR8, B); break; // CMPU (Immediate)
|
|
case 0x8C: REG_OP(XOR8, B); break; // CMPS (Immediate)
|
|
case 0x93: REG_OP(XOR8, B); break; // CMPU (Direct)
|
|
case 0x9C: REG_OP(XOR8, B); break; // CMPS (Direct)
|
|
case 0xA3: REG_OP(XOR8, B); break; // CMPU (Indexed)
|
|
case 0xAC: REG_OP(XOR8, B); break; // CMPS (Indexed)
|
|
case 0xB3: REG_OP(XOR8, B); break; // CMPU (Extended)
|
|
case 0xBC: REG_OP(XOR8, B); break; // CMPS (Extended)
|
|
|
|
default: ILLEGAL(); break;
|
|
}
|
|
}
|
|
}
|
|
} |