134 lines
4.6 KiB
C++
134 lines
4.6 KiB
C++
#ifdef HITACHIDSP_CPP
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uint8 HitachiDSP::bus_read(unsigned addr) {
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if((addr & 0x408000) == 0x008000) return bus.read(addr);
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return 0x00;
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}
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void HitachiDSP::bus_write(unsigned addr, uint8 data) {
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if((addr & 0x40e000) == 0x006000) return bus.write(addr, data);
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}
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uint8 HitachiDSP::rom_read(unsigned addr) {
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if(co_active() == cpu.thread) {
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if(state == State::Idle) return cartridge.rom.read(addr);
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if((addr & 0x40ffe0) == 0x00ffe0) return regs.vector[addr & 0x1f];
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return cpu.regs.mdr;
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}
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if(co_active() == hitachidsp.thread) {
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return cartridge.rom.read(addr);
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}
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return cpu.regs.mdr;
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}
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void HitachiDSP::rom_write(unsigned addr, uint8 data) {
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}
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uint8 HitachiDSP::dsp_read(unsigned addr) {
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addr &= 0x1fff;
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//Data RAM
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if((addr >= 0x0000 && addr <= 0x0bff) || (addr >= 0x1000 && addr <= 0x1bff)) {
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return dataRAM[addr & 0x0fff];
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}
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//MMIO
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switch(addr) {
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case 0x1f40: return regs.dma_source >> 0;
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case 0x1f41: return regs.dma_source >> 8;
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case 0x1f42: return regs.dma_source >> 16;
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case 0x1f43: return regs.dma_length >> 0;
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case 0x1f44: return regs.dma_length >> 8;
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case 0x1f45: return regs.dma_target >> 0;
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case 0x1f46: return regs.dma_target >> 8;
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case 0x1f47: return regs.dma_target >> 16;
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case 0x1f48: return regs.r1f48;
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case 0x1f49: return regs.program_offset >> 0;
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case 0x1f4a: return regs.program_offset >> 8;
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case 0x1f4b: return regs.program_offset >> 16;
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case 0x1f4c: return regs.r1f4c;
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case 0x1f4d: return regs.page_number >> 0;
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case 0x1f4e: return regs.page_number >> 8;
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case 0x1f4f: return regs.program_counter;
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case 0x1f50: return regs.r1f50;
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case 0x1f51: return regs.r1f51;
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case 0x1f52: return regs.r1f52;
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case 0x1f53: case 0x1f54: case 0x1f55: case 0x1f56:
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case 0x1f57: case 0x1f58: case 0x1f59: case 0x1f5a:
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case 0x1f5b: case 0x1f5c: case 0x1f5d: case 0x1f5e:
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case 0x1f5f: return ((state != State::Idle) << 6) | ((state == State::Idle) << 1);
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}
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//Vector
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if(addr >= 0x1f60 && addr <= 0x1f7f) {
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return regs.vector[addr & 0x1f];
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}
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//GPRs
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if((addr >= 0x1f80 && addr <= 0x1faf) || (addr >= 0x1fc0 && addr <= 0x1fef)) {
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unsigned index = (addr & 0x3f) / 3; //0..15
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unsigned shift = ((addr & 0x3f) % 3) * 8; //0, 8, 16
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return regs.gpr[index] >> shift;
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}
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return 0x00;
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}
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void HitachiDSP::dsp_write(unsigned addr, uint8 data) {
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addr &= 0x1fff;
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//Data RAM
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if((addr >= 0x0000 && addr <= 0x0bff) || (addr >= 0x1000 && addr <= 0x1bff)) {
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dataRAM[addr & 0x0fff] = data;
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return;
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}
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//MMIO
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switch(addr) {
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case 0x1f40: regs.dma_source = (regs.dma_source & 0xffff00) | (data << 0); return;
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case 0x1f41: regs.dma_source = (regs.dma_source & 0xff00ff) | (data << 8); return;
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case 0x1f42: regs.dma_source = (regs.dma_source & 0x00ffff) | (data << 16); return;
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case 0x1f43: regs.dma_length = (regs.dma_length & 0xff00) | (data << 0); return;
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case 0x1f44: regs.dma_length = (regs.dma_length & 0x00ff) | (data << 8); return;
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case 0x1f45: regs.dma_target = (regs.dma_target & 0xffff00) | (data << 0); return;
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case 0x1f46: regs.dma_target = (regs.dma_target & 0xff00ff) | (data << 8); return;
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case 0x1f47: regs.dma_target = (regs.dma_target & 0x00ffff) | (data << 16);
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if(state == State::Idle) state = State::DMA;
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return;
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case 0x1f48: regs.r1f48 = data & 0x01; return;
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case 0x1f49: regs.program_offset = (regs.program_offset & 0xffff00) | (data << 0); return;
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case 0x1f4a: regs.program_offset = (regs.program_offset & 0xff00ff) | (data << 8); return;
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case 0x1f4b: regs.program_offset = (regs.program_offset & 0x00ffff) | (data << 16); return;
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case 0x1f4c: regs.r1f4c = data & 0x03; return;
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case 0x1f4d: regs.page_number = (regs.page_number & 0x7f00) | ((data & 0xff) << 0); return;
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case 0x1f4e: regs.page_number = (regs.page_number & 0x00ff) | ((data & 0x7f) << 8); return;
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case 0x1f4f: regs.program_counter = data;
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if(state == State::Idle) {
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regs.pc = regs.page_number * 256 + regs.program_counter;
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state = State::Execute;
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}
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return;
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case 0x1f50: regs.r1f50 = data & 0x77; return;
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case 0x1f51: regs.r1f51 = data & 0x01; return;
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case 0x1f52: regs.r1f52 = data & 0x01; return;
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}
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//Vector
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if(addr >= 0x1f60 && addr <= 0x1f7f) {
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regs.vector[addr & 0x1f] = data;
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return;
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}
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//GPRs
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if((addr >= 0x1f80 && addr <= 0x1faf) || (addr >= 0x1fc0 && addr <= 0x1fef)) {
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unsigned index = (addr & 0x3f) / 3;
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switch((addr & 0x3f) % 3) {
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case 0: regs.gpr[index] = (regs.gpr[index] & 0xffff00) | (data << 0); return;
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case 1: regs.gpr[index] = (regs.gpr[index] & 0xff00ff) | (data << 8); return;
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case 2: regs.gpr[index] = (regs.gpr[index] & 0x00ffff) | (data << 16); return;
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}
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}
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}
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#endif
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