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BizHawk/BizHawk.Emulation.Cores/CPUs/Z80A
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alyosha-tas c0d6c02b2e Z80: Recast core to cycle accurate memory accesses and wait state timing 2018-05-31 21:05:41 -04:00
..
Execute.cs Z80: Recast core to cycle accurate memory accesses and wait state timing 2018-05-31 21:05:41 -04:00
Interrupts.cs Z80: Recast core to cycle accurate memory accesses and wait state timing 2018-05-31 21:05:41 -04:00
NewDisassembler.cs z80: clean up 2018-03-16 17:50:51 -04:00
Operations.cs Z80: Recast core to cycle accurate memory accesses and wait state timing 2018-05-31 21:05:41 -04:00
ReadMe.txt z80: clean up 2018-03-16 17:50:51 -04:00
Registers.cs Z80A: Add a WAIT state that can puase the CPU on reads / writes 2018-05-15 09:44:39 -04:00
Tables_Direct.cs Z80: Recast core to cycle accurate memory accesses and wait state timing 2018-05-31 21:05:41 -04:00
Tables_Indirect.cs Z80: Recast core to cycle accurate memory accesses and wait state timing 2018-05-31 21:05:41 -04:00
Z80A.cs Z80: Recast core to cycle accurate memory accesses and wait state timing 2018-05-31 21:05:41 -04:00

ReadMe.txt 

TODO: 

Mode 0
Check T-cycle level memory access timing
Check R register 
new tests for WZ Registers
Memory refresh - IR is pushed onto the address bus at instruction start, does anything need this?