1015 lines
31 KiB
C
1015 lines
31 KiB
C
/*
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* PicoDrive - Internal Header File
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* (c) Copyright Dave, 2004
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* (C) notaz, 2006-2010
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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*/
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#ifndef PICO_INTERNAL_INCLUDED
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#define PICO_INTERNAL_INCLUDED
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "pico.h"
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#include "carthw/carthw.h"
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//
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#define USE_POLL_DETECT
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#ifndef PICO_INTERNAL
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#define PICO_INTERNAL
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#endif
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#ifndef PICO_INTERNAL_ASM
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#define PICO_INTERNAL_ASM
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#endif
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// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project
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#ifdef __cplusplus
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extern "C" {
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#endif
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// ----------------------- 68000 CPU -----------------------
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#ifdef EMU_C68K
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#include "../cpu/cyclone/Cyclone.h"
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extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;
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#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run
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#define SekCyclesLeftS68k PicoCpuCS68k.cycles
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#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)
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#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)
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#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])
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#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])
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#define SekSr CycloneGetSr(&PicoCpuCM68k)
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#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)
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#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }
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#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }
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#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)
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#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)
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#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))
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#define SekNotPolling PicoCpuCM68k.not_pol
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#define SekNotPollingS68k PicoCpuCS68k.not_pol
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#define SekInterrupt(i) PicoCpuCM68k.irq=i
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#define SekIrqLevel PicoCpuCM68k.irq
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#endif
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#ifdef EMU_F68K
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#include "../cpu/fame/fame.h"
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extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;
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#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter
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#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter
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#define SekPc fm68k_get_pc(&PicoCpuFM68k)
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#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)
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#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)
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#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)
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#define SekSr PicoCpuFM68k.sr
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#define SekSrS68k PicoCpuFS68k.sr
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#define SekSetStop(x) { \
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PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \
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if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \
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}
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#define SekSetStopS68k(x) { \
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PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \
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if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \
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}
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#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)
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#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)
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#define SekShouldInterrupt() fm68k_would_interrupt()
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#define SekNotPolling PicoCpuFM68k.not_polling
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#define SekNotPollingS68k PicoCpuFS68k.not_polling
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#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq
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#define SekIrqLevel PicoCpuFM68k.interrupts[0]
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#endif
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#ifdef EMU_M68K
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#include "../cpu/musashi/m68kcpu.h"
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extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;
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#ifndef SekCyclesLeft
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#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles
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#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles
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#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)
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#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)
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#define SekDar(x) PicoCpuMM68k.dar[x]
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#define SekDarS68k(x) PicoCpuMS68k.dar[x]
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#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)
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#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)
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#define SekSetStop(x) { \
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if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \
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else PicoCpuMM68k.stopped=0; \
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}
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#define SekSetStopS68k(x) { \
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if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \
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else PicoCpuMS68k.stopped=0; \
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}
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#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)
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#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)
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#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)
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#define SekNotPolling PicoCpuMM68k.not_polling
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#define SekNotPollingS68k PicoCpuMS68k.not_polling
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#define SekInterrupt(irq) { \
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void *oldcontext = m68ki_cpu_p; \
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m68k_set_context(&PicoCpuMM68k); \
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m68k_set_irq(irq); \
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m68k_set_context(oldcontext); \
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}
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#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)
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#endif
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#endif // EMU_M68K
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// while running, cnt represents target of current timeslice
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// while not in SekRun(), it's actual cycles done
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// (but always use SekCyclesDone() if you need current position)
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// cnt may change if timeslice is ended prematurely or extended,
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// so we use SekCycleAim for the actual target
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extern unsigned int SekCycleCnt;
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extern unsigned int SekCycleAim;
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// number of cycles done (can be checked anywhere)
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#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)
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// burn cycles while not in SekRun() and while in
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#define SekCyclesBurn(c) SekCycleCnt += c
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#define SekCyclesBurnRun(c) { \
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SekCyclesLeft -= c; \
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}
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// note: sometimes may extend timeslice to delay an irq
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#define SekEndRun(after) { \
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SekCycleCnt -= SekCyclesLeft - (after); \
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SekCyclesLeft = after; \
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}
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extern unsigned int SekCycleCntS68k;
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extern unsigned int SekCycleAimS68k;
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#define SekEndRunS68k(after) { \
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if (SekCyclesLeftS68k > (after)) { \
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SekCycleCntS68k -= SekCyclesLeftS68k - (after); \
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SekCyclesLeftS68k = after; \
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} \
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}
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#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)
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// compare cycles, handling overflows
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// check if a > b
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#define CYCLES_GT(a, b) \
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((int)((a) - (b)) > 0)
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// check if a >= b
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#define CYCLES_GE(a, b) \
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((int)((a) - (b)) >= 0)
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// ----------------------- Z80 CPU -----------------------
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#if defined(_USE_DRZ80)
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#include "../cpu/DrZ80/drz80.h"
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extern struct DrZ80 drZ80;
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#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))
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#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)
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#define z80_int() drZ80.Z80_IRQ = 1
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#define z80_int() drZ80.Z80_IRQ = 1
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#define z80_nmi() drZ80.Z80IF |= 8
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#define z80_cyclesLeft drZ80.cycles
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#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)
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#elif defined(_USE_CZ80)
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#include "../cpu/cz80/cz80.h"
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#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)
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#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)
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#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)
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#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)
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#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)
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#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)
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#else
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#define z80_run(cycles) (cycles)
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#define z80_run_nr(cycles)
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#define z80_int()
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#define z80_nmi()
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#endif
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#define Z80_STATE_SIZE 0x60
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extern unsigned int last_z80_sync;
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extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */
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extern int z80_cycle_aim;
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extern int z80_scanline;
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extern int z80_scanline_cycles; /* cycles done until z80_scanline */
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#define z80_resetCycles() \
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last_z80_sync = SekCyclesDone(); \
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z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;
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#define z80_cyclesDone() \
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(z80_cycle_aim - z80_cyclesLeft)
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#define cycles_68k_to_z80(x) ((x)*957 >> 11)
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// ----------------------- SH2 CPU -----------------------
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#include "cpu/sh2/sh2.h"
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extern SH2 sh2s[2];
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#define msh2 sh2s[0]
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#define ssh2 sh2s[1]
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#ifndef DRC_SH2
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# define sh2_end_run(sh2, after_) do { \
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if ((sh2)->icount > (after_)) { \
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(sh2)->cycles_timeslice -= (sh2)->icount - (after_); \
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(sh2)->icount = after_; \
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} \
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} while (0)
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# define sh2_cycles_left(sh2) (sh2)->icount
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# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n
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# define sh2_pc(sh2) (sh2)->ppc
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#else
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# define sh2_end_run(sh2, after_) do { \
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int left_ = (signed int)(sh2)->sr >> 12; \
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if (left_ > (after_)) { \
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(sh2)->cycles_timeslice -= left_ - (after_); \
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(sh2)->sr &= 0xfff; \
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(sh2)->sr |= (after_) << 12; \
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} \
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} while (0)
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# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)
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# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)
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# define sh2_pc(sh2) (sh2)->pc
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#endif
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#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))
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#define sh2_cycles_done_t(sh2) \
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((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))
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#define sh2_cycles_done_m68k(sh2) \
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((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))
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#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]
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#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr
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#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr
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#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)
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#define sh2_set_gbr(c, v) \
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{ if (c) ssh2.gbr = v; else msh2.gbr = v; }
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#define sh2_set_vbr(c, v) \
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{ if (c) ssh2.vbr = v; else msh2.vbr = v; }
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#define elprintf_sh2(sh2, w, f, ...) \
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elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)
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// ---------------------------------------------------------
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// main oscillator clock which controls timing
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#define OSC_NTSC 53693100
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#define OSC_PAL 53203424
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struct PicoVideo
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{
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unsigned char reg[0x20];
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unsigned int command; // 32-bit Command
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unsigned char pending; // 1 if waiting for second half of 32-bit command
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unsigned char type; // Command type (v/c/vsram read/write)
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unsigned short addr; // Read/Write address
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int status; // Status bits
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unsigned char pending_ints; // pending interrupts: ??VH????
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signed char lwrite_cnt; // VDP write count during active display line
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unsigned short v_counter; // V-counter
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unsigned char pad[0x10];
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};
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struct PicoMisc
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{
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unsigned char rotate;
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unsigned char z80Run;
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unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches
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unsigned short scanline; // 04 0 to 261||311
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char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)
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unsigned char hardware; // 07 Hardware value for country
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unsigned char pal; // 08 1=PAL 0=NTSC
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unsigned char sram_reg; // 09 SRAM reg. See SRR_* below
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unsigned short z80_bank68k; // 0a
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unsigned short pad0;
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unsigned char ncart_in; // 0e !cart_in
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unsigned char z80_reset; // 0f z80 reset held
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unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay
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unsigned short eeprom_addr; // EEPROM address register
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unsigned char eeprom_cycle; // EEPROM cycle number
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unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs
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unsigned char eeprom_status;
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unsigned char pad2;
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unsigned short dma_xfers; // 18
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unsigned char eeprom_wb[2]; // EEPROM latch/write buffer
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unsigned int frame_count; // 1c for movies and idle det
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};
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struct PicoMS
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{
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unsigned char carthw[0x10];
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unsigned char io_ctl;
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unsigned char nmi_state;
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unsigned char pad[0x4e];
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};
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// some assembly stuff depend on these, do not touch!
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struct Pico
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{
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unsigned char ram[0x10000]; // 0x00000 scratch ram
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union { // vram is byteswapped for easier reads when drawing
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unsigned short vram[0x8000]; // 0x10000
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unsigned char vramb[0x4000]; // VRAM in SMS mode
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};
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unsigned char zram[0x2000]; // 0x20000 Z80 ram
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unsigned char ioports[0x10]; // XXX: fix asm and mv
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unsigned char pad[0xf0]; // unused
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unsigned short cram[0x40]; // 0x22100
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unsigned short vsram[0x40]; // 0x22180
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unsigned char *rom; // 0x22200
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unsigned int romsize; // 0x22204 (on 32bits)
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struct PicoMisc m;
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struct PicoVideo video;
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struct PicoMS ms;
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};
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// sram
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#define SRR_MAPPED (1 << 0)
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#define SRR_READONLY (1 << 1)
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#define SRF_ENABLED (1 << 0)
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#define SRF_EEPROM (1 << 1)
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struct PicoSRAM
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{
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unsigned char *data; // actual data
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unsigned int start; // start address in 68k address space
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unsigned int end;
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unsigned char flags; // 0c: SRF_*
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unsigned char unused2;
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unsigned char changed;
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unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words
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unsigned char unused3;
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unsigned char eeprom_bit_cl; // bit number for cl
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unsigned char eeprom_bit_in; // bit number for in
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unsigned char eeprom_bit_out; // bit number for out
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unsigned int size;
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};
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// MCD
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#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)
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struct mcd_pcm
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{
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unsigned char control; // reg7
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unsigned char enabled; // reg8
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unsigned char cur_ch;
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unsigned char bank;
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unsigned int update_cycles;
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struct pcm_chan // 08, size 0x10
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{
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unsigned char regs[8];
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unsigned int addr; // .08: played sample address
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int pad;
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} ch[8];
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};
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#define PCD_ST_S68K_RST 1
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struct mcd_misc
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{
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unsigned short hint_vector;
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unsigned char busreq; // not s68k_regs[1]
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unsigned char s68k_pend_ints;
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unsigned int state_flags; // 04
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unsigned int stopwatch_base_c;
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unsigned short m68k_poll_a;
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unsigned short m68k_poll_cnt;
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unsigned short s68k_poll_a;
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unsigned short s68k_poll_cnt;
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unsigned int s68k_poll_clk;
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unsigned char bcram_reg; // 18: battery-backed RAM cart register
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unsigned char dmna_ret_2m;
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unsigned char need_sync;
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unsigned char pad3;
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int pad4[9];
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};
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typedef struct
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{
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unsigned char bios[0x20000]; // 000000: 128K
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union { // 020000: 512K
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unsigned char prg_ram[0x80000];
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unsigned char prg_ram_b[4][0x20000];
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};
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union { // 0a0000: 256K
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struct {
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unsigned char word_ram2M[0x40000];
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unsigned char unused0[0x20000];
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};
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struct {
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unsigned char unused1[0x20000];
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unsigned char word_ram1M[2][0x20000];
|
|
};
|
|
};
|
|
union { // 100000: 64K
|
|
unsigned char pcm_ram[0x10000];
|
|
unsigned char pcm_ram_b[0x10][0x1000];
|
|
};
|
|
unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs
|
|
unsigned char bram[0x2000]; // 110200: 8K
|
|
struct mcd_misc m; // 112200: misc
|
|
struct mcd_pcm pcm; // 112240:
|
|
int pcm_mixbuf[PCM_MIXBUF_LEN * 2];
|
|
int pcm_mixpos;
|
|
char pcm_mixbuf_dirty;
|
|
char pcm_regs_dirty;
|
|
} mcd_state;
|
|
|
|
// XXX: this will need to be reworked for cart+cd support.
|
|
#define Pico_mcd ((mcd_state *)Pico.rom)
|
|
|
|
// 32X
|
|
#define P32XS_FM (1<<15)
|
|
#define P32XS_nCART (1<< 8)
|
|
#define P32XS_REN (1<< 7)
|
|
#define P32XS_nRES (1<< 1)
|
|
#define P32XS_ADEN (1<< 0)
|
|
#define P32XS2_ADEN (1<< 9)
|
|
#define P32XS_FULL (1<< 7) // DREQ FIFO full
|
|
#define P32XS_68S (1<< 2)
|
|
#define P32XS_DMA (1<< 1)
|
|
#define P32XS_RV (1<< 0)
|
|
|
|
#define P32XV_nPAL (1<<15) // VDP
|
|
#define P32XV_PRI (1<< 7)
|
|
#define P32XV_Mx (3<< 0) // display mode mask
|
|
|
|
#define P32XV_SFT (1<< 0)
|
|
|
|
#define P32XV_VBLK (1<<15)
|
|
#define P32XV_HBLK (1<<14)
|
|
#define P32XV_PEN (1<<13)
|
|
#define P32XV_nFEN (1<< 1)
|
|
#define P32XV_FS (1<< 0)
|
|
|
|
#define P32XP_RTP (1<<7) // PWM control
|
|
#define P32XP_FULL (1<<15) // PWM pulse
|
|
#define P32XP_EMPTY (1<<14)
|
|
|
|
#define P32XF_68KCPOLL (1 << 0)
|
|
#define P32XF_68KVPOLL (1 << 1)
|
|
#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io
|
|
|
|
#define P32XI_VRES (1 << 14/2) // IRL/2
|
|
#define P32XI_VINT (1 << 12/2)
|
|
#define P32XI_HINT (1 << 10/2)
|
|
#define P32XI_CMD (1 << 8/2)
|
|
#define P32XI_PWM (1 << 6/2)
|
|
|
|
// peripheral reg access
|
|
#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]
|
|
|
|
#define DMAC_FIFO_LEN (4*2)
|
|
#define PWM_BUFF_LEN 1024 // in one channel samples
|
|
|
|
#define SH2_DRCBLK_RAM_SHIFT 1
|
|
#define SH2_DRCBLK_DA_SHIFT 1
|
|
|
|
#define SH2_READ_SHIFT 25
|
|
#define SH2_WRITE_SHIFT 25
|
|
|
|
struct Pico32x
|
|
{
|
|
unsigned short regs[0x20];
|
|
unsigned short vdp_regs[0x10]; // 0x40
|
|
unsigned short sh2_regs[3]; // 0x60
|
|
unsigned char pending_fb;
|
|
unsigned char dirty_pal;
|
|
unsigned int emu_flags;
|
|
unsigned char sh2irq_mask[2];
|
|
unsigned char sh2irqi[2]; // individual
|
|
unsigned int sh2irqs; // common irqs
|
|
unsigned short dmac_fifo[DMAC_FIFO_LEN];
|
|
unsigned int pad[4];
|
|
unsigned int dmac0_fifo_ptr;
|
|
unsigned short vdp_fbcr_fake;
|
|
unsigned short pad2;
|
|
unsigned char comm_dirty_68k;
|
|
unsigned char comm_dirty_sh2;
|
|
unsigned char pwm_irq_cnt;
|
|
unsigned char pad1;
|
|
unsigned short pwm_p[2]; // pwm pos in fifo
|
|
unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)
|
|
unsigned int reserved[6];
|
|
};
|
|
|
|
struct Pico32xMem
|
|
{
|
|
unsigned char sdram[0x40000];
|
|
#ifdef DRC_SH2
|
|
unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];
|
|
#endif
|
|
unsigned short dram[2][0x20000/2]; // AKA fb
|
|
union {
|
|
unsigned char m68k_rom[0x100];
|
|
unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE
|
|
};
|
|
#ifdef DRC_SH2
|
|
unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];
|
|
#endif
|
|
union {
|
|
unsigned char b[0x800];
|
|
unsigned short w[0x800/2];
|
|
} sh2_rom_m;
|
|
union {
|
|
unsigned char b[0x400];
|
|
unsigned short w[0x400/2];
|
|
} sh2_rom_s;
|
|
unsigned short pal[0x100];
|
|
unsigned short pal_native[0x100]; // converted to native (for renderer)
|
|
signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame
|
|
signed short pwm_current[2]; // current converted samples
|
|
unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries
|
|
};
|
|
|
|
// cart.c
|
|
extern int PicoCartResize(int newsize);
|
|
extern void Byteswap(void *dst, const void *src, int len);
|
|
extern void (*PicoCartMemSetup)(void);
|
|
|
|
// debug.c
|
|
int CM_compareRun(int cyc, int is_sub);
|
|
|
|
// draw.c
|
|
PICO_INTERNAL void PicoFrameStart(void);
|
|
void PicoDrawSync(int to, int blank_last_line);
|
|
void BackFill(int reg7, int sh);
|
|
void FinalizeLine555(int sh, int line);
|
|
extern int (*PicoScanBegin)(unsigned int num);
|
|
extern int (*PicoScanEnd)(unsigned int num);
|
|
extern int DrawScanline;
|
|
#define MAX_LINE_SPRITES 29
|
|
extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];
|
|
extern void *DrawLineDestBase;
|
|
extern int DrawLineDestIncrement;
|
|
|
|
// draw2.c
|
|
PICO_INTERNAL void PicoFrameFull();
|
|
|
|
// mode4.c
|
|
void PicoFrameStartMode4(void);
|
|
void PicoLineMode4(int line);
|
|
void PicoDoHighPal555M4(void);
|
|
void PicoDrawSetOutputMode4(pdso_t which);
|
|
|
|
// memory.c
|
|
PICO_INTERNAL void PicoMemSetup(void);
|
|
unsigned int PicoRead8_io(unsigned int a);
|
|
unsigned int PicoRead16_io(unsigned int a);
|
|
void PicoWrite8_io(unsigned int a, unsigned int d);
|
|
void PicoWrite16_io(unsigned int a, unsigned int d);
|
|
|
|
// pico/memory.c
|
|
PICO_INTERNAL void PicoMemSetupPico(void);
|
|
|
|
// cd/cdc.c
|
|
void cdc_init(void);
|
|
void cdc_reset(void);
|
|
void cdc_dma_update(void);
|
|
int cdc_decoder_update(unsigned char header[4]);
|
|
void cdc_reg_w(unsigned char data);
|
|
unsigned char cdc_reg_r(void);
|
|
unsigned short cdc_host_r(void);
|
|
|
|
// cd/cdd.c
|
|
void cdd_reset(void);
|
|
void cdd_read_data(unsigned char *dst);
|
|
void cdd_read_audio(short *buffer, unsigned int samples);
|
|
void cdd_update(void);
|
|
void cdd_process(void);
|
|
|
|
// cd/cd_image.c
|
|
int load_cd_image(const char *cd_img_name, int *type);
|
|
|
|
// cd/gfx.c
|
|
void gfx_init(void);
|
|
void gfx_start(unsigned int base);
|
|
void gfx_update(unsigned int cycles);
|
|
|
|
// cd/gfx_dma.c
|
|
void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);
|
|
|
|
// cd/memory.c
|
|
PICO_INTERNAL void PicoMemSetupCD(void);
|
|
unsigned int PicoRead8_mcd_io(unsigned int a);
|
|
unsigned int PicoRead16_mcd_io(unsigned int a);
|
|
void PicoWrite8_mcd_io(unsigned int a, unsigned int d);
|
|
void PicoWrite16_mcd_io(unsigned int a, unsigned int d);
|
|
void pcd_state_loaded_mem(void);
|
|
|
|
// pico.c
|
|
extern struct Pico Pico;
|
|
extern struct PicoSRAM SRam;
|
|
extern int PicoPadInt[2];
|
|
extern int emustatus;
|
|
extern int scanlines_total;
|
|
extern void (*PicoResetHook)(void);
|
|
extern void (*PicoLineHook)(void);
|
|
PICO_INTERNAL int CheckDMA(void);
|
|
PICO_INTERNAL void PicoDetectRegion(void);
|
|
PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);
|
|
|
|
// cd/mcd.c
|
|
#define PCDS_IEN1 (1<<1)
|
|
#define PCDS_IEN2 (1<<2)
|
|
#define PCDS_IEN3 (1<<3)
|
|
#define PCDS_IEN4 (1<<4)
|
|
#define PCDS_IEN5 (1<<5)
|
|
#define PCDS_IEN6 (1<<6)
|
|
|
|
PICO_INTERNAL void PicoInitMCD(void);
|
|
PICO_INTERNAL void PicoExitMCD(void);
|
|
PICO_INTERNAL void PicoPowerMCD(void);
|
|
PICO_INTERNAL int PicoResetMCD(void);
|
|
PICO_INTERNAL void PicoFrameMCD(void);
|
|
|
|
enum pcd_event {
|
|
PCD_EVENT_CDC,
|
|
PCD_EVENT_TIMER3,
|
|
PCD_EVENT_GFX,
|
|
PCD_EVENT_DMA,
|
|
PCD_EVENT_COUNT,
|
|
};
|
|
extern unsigned int pcd_event_times[PCD_EVENT_COUNT];
|
|
void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);
|
|
void pcd_event_schedule_s68k(enum pcd_event event, int after);
|
|
void pcd_prepare_frame(void);
|
|
unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);
|
|
int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);
|
|
void pcd_run_cpus(int m68k_cycles);
|
|
void pcd_soft_reset(void);
|
|
void pcd_state_loaded(void);
|
|
|
|
// cd/pcm.c
|
|
void pcd_pcm_sync(unsigned int to);
|
|
void pcd_pcm_update(int *buffer, int length, int stereo);
|
|
void pcd_pcm_write(unsigned int a, unsigned int d);
|
|
unsigned int pcd_pcm_read(unsigned int a);
|
|
|
|
// pico/pico.c
|
|
PICO_INTERNAL void PicoInitPico(void);
|
|
PICO_INTERNAL void PicoReratePico(void);
|
|
|
|
// pico/xpcm.c
|
|
PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);
|
|
PICO_INTERNAL void PicoPicoPCMReset(void);
|
|
PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);
|
|
|
|
// sek.c
|
|
PICO_INTERNAL void SekInit(void);
|
|
PICO_INTERNAL int SekReset(void);
|
|
PICO_INTERNAL void SekState(int *data);
|
|
PICO_INTERNAL void SekSetRealTAS(int use_real);
|
|
PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);
|
|
PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);
|
|
void SekStepM68k(void);
|
|
void SekInitIdleDet(void);
|
|
void SekFinishIdleDet(void);
|
|
#if defined(CPU_CMP_R) || defined(CPU_CMP_W)
|
|
void SekTrace(int is_s68k);
|
|
#else
|
|
#define SekTrace(x)
|
|
#endif
|
|
|
|
// cd/sek.c
|
|
PICO_INTERNAL void SekInitS68k(void);
|
|
PICO_INTERNAL int SekResetS68k(void);
|
|
PICO_INTERNAL int SekInterruptS68k(int irq);
|
|
void SekInterruptClearS68k(int irq);
|
|
|
|
// sound/sound.c
|
|
extern int PsndLen_exc_cnt;
|
|
extern int PsndLen_exc_add;
|
|
extern int timer_a_next_oflow, timer_a_step; // in z80 cycles
|
|
extern int timer_b_next_oflow, timer_b_step;
|
|
|
|
void cdda_start_play(int lba_base, int lba_offset, int lb_len);
|
|
|
|
void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);
|
|
void ym2612_pack_state(void);
|
|
void ym2612_unpack_state(void);
|
|
|
|
#define TIMER_NO_OFLOW 0x70000000
|
|
// tA = 72 * (1024 - NA) / M
|
|
#define TIMER_A_TICK_ZCYCLES 17203
|
|
// tB = 1152 * (256 - NA) / M
|
|
#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura
|
|
|
|
#define timers_cycle() \
|
|
if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \
|
|
timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \
|
|
if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \
|
|
timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \
|
|
ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);
|
|
|
|
#define timers_reset() \
|
|
timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \
|
|
timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \
|
|
timer_b_step = TIMER_B_TICK_ZCYCLES * 256;
|
|
|
|
|
|
// videoport.c
|
|
extern int line_base_cycles;
|
|
PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);
|
|
PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);
|
|
PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);
|
|
extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);
|
|
|
|
// misc.c
|
|
PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);
|
|
PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);
|
|
PICO_INTERNAL_ASM void memcpy32(void *dest, const void *src, int count); // 32bit word count
|
|
PICO_INTERNAL_ASM void memset32(void *dest, int c, int count);
|
|
|
|
// eeprom.c
|
|
void EEPROM_write8(unsigned int a, unsigned int d);
|
|
void EEPROM_write16(unsigned int d);
|
|
unsigned int EEPROM_read(void);
|
|
|
|
// z80 functionality wrappers
|
|
PICO_INTERNAL void z80_init(void);
|
|
PICO_INTERNAL void z80_pack(void *data);
|
|
PICO_INTERNAL int z80_unpack(const void *data);
|
|
PICO_INTERNAL void z80_reset(void);
|
|
PICO_INTERNAL void z80_exit(void);
|
|
|
|
// cd/misc.c
|
|
PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);
|
|
PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);
|
|
|
|
// sound/sound.c
|
|
PICO_INTERNAL void PsndReset(void);
|
|
PICO_INTERNAL void PsndDoDAC(int line_to);
|
|
PICO_INTERNAL void PsndClear(void);
|
|
PICO_INTERNAL void PsndGetSamples(int y);
|
|
PICO_INTERNAL void PsndGetSamplesMS(void);
|
|
extern int PsndDacLine;
|
|
|
|
// sms.c
|
|
#ifndef NO_SMS
|
|
void PicoPowerMS(void);
|
|
void PicoResetMS(void);
|
|
void PicoMemSetupMS(void);
|
|
void PicoStateLoadedMS(void);
|
|
void PicoFrameMS(void);
|
|
void PicoFrameDrawOnlyMS(void);
|
|
#else
|
|
#define PicoPowerMS()
|
|
#define PicoResetMS()
|
|
#define PicoMemSetupMS()
|
|
#define PicoStateLoadedMS()
|
|
#define PicoFrameMS()
|
|
#define PicoFrameDrawOnlyMS()
|
|
#endif
|
|
|
|
// 32x/32x.c
|
|
#ifndef NO_32X
|
|
extern struct Pico32x Pico32x;
|
|
enum p32x_event {
|
|
P32X_EVENT_PWM,
|
|
P32X_EVENT_FILLEND,
|
|
P32X_EVENT_HINT,
|
|
P32X_EVENT_COUNT,
|
|
};
|
|
extern unsigned int p32x_event_times[P32X_EVENT_COUNT];
|
|
|
|
void Pico32xInit(void);
|
|
void PicoPower32x(void);
|
|
void PicoReset32x(void);
|
|
void Pico32xStartup(void);
|
|
void PicoFrame32x(void);
|
|
void p32x_sync_sh2s(unsigned int m68k_target);
|
|
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);
|
|
void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);
|
|
void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);
|
|
void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);
|
|
void p32x_reset_sh2s(void);
|
|
void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);
|
|
void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);
|
|
void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);
|
|
|
|
// 32x/memory.c
|
|
struct Pico32xMem *Pico32xMem;
|
|
unsigned int PicoRead8_32x(unsigned int a);
|
|
unsigned int PicoRead16_32x(unsigned int a);
|
|
void PicoWrite8_32x(unsigned int a, unsigned int d);
|
|
void PicoWrite16_32x(unsigned int a, unsigned int d);
|
|
void PicoMemSetup32x(void);
|
|
void Pico32xSwapDRAM(int b);
|
|
void p32x_m68k_poll_event(unsigned int flags);
|
|
void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);
|
|
|
|
// 32x/draw.c
|
|
void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);
|
|
void FinalizeLine32xRGB555(int sh, int line);
|
|
void PicoDraw32xLayer(int offs, int lines, int mdbg);
|
|
void PicoDraw32xLayerMdOnly(int offs, int lines);
|
|
extern int (*PicoScan32xBegin)(unsigned int num);
|
|
extern int (*PicoScan32xEnd)(unsigned int num);
|
|
enum {
|
|
PDM32X_OFF,
|
|
PDM32X_32X_ONLY,
|
|
PDM32X_BOTH,
|
|
};
|
|
extern int Pico32xDrawMode;
|
|
|
|
// 32x/pwm.c
|
|
unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,
|
|
unsigned int m68k_cycles);
|
|
void p32x_pwm_write16(unsigned int a, unsigned int d,
|
|
SH2 *sh2, unsigned int m68k_cycles);
|
|
void p32x_pwm_update(int *buf32, int length, int stereo);
|
|
void p32x_pwm_ctl_changed(void);
|
|
void p32x_pwm_schedule(unsigned int m68k_now);
|
|
void p32x_pwm_schedule_sh2(SH2 *sh2);
|
|
void p32x_pwm_sync_to_sh2(SH2 *sh2);
|
|
void p32x_pwm_irq_event(unsigned int m68k_now);
|
|
void p32x_pwm_state_loaded(void);
|
|
|
|
// 32x/sh2soc.c
|
|
void p32x_dreq0_trigger(void);
|
|
void p32x_dreq1_trigger(void);
|
|
void p32x_timers_recalc(void);
|
|
void p32x_timers_do(unsigned int m68k_slice);
|
|
void sh2_peripheral_reset(SH2 *sh2);
|
|
unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);
|
|
unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);
|
|
unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);
|
|
void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);
|
|
void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);
|
|
void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);
|
|
|
|
#else
|
|
#define Pico32xInit()
|
|
#define PicoPower32x()
|
|
#define PicoReset32x()
|
|
#define PicoFrame32x()
|
|
#define Pico32xStateLoaded()
|
|
#define FinalizeLine32xRGB555 NULL
|
|
#define p32x_pwm_update(...)
|
|
#define p32x_timers_recalc()
|
|
#endif
|
|
|
|
/* avoid dependency on newer glibc */
|
|
static __inline int isspace_(int c)
|
|
{
|
|
return (0x09 <= c && c <= 0x0d) || c == ' ';
|
|
}
|
|
|
|
#ifndef ARRAY_SIZE
|
|
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
|
|
#endif
|
|
|
|
// emulation event logging
|
|
#ifndef EL_LOGMASK
|
|
# ifdef __x86_64__ // HACK
|
|
# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)
|
|
# else
|
|
# define EL_LOGMASK (EL_STATUS)
|
|
# endif
|
|
#endif
|
|
|
|
#define EL_HVCNT 0x00000001 /* hv counter reads */
|
|
#define EL_SR 0x00000002 /* SR reads */
|
|
#define EL_INTS 0x00000004 /* ints and acks */
|
|
#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */
|
|
#define EL_INTSW 0x00000010 /* log irq switching on/off */
|
|
#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */
|
|
#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */
|
|
#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */
|
|
#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */
|
|
#define EL_SRAMIO 0x00000200 /* sram i/o */
|
|
#define EL_EEPROM 0x00000400 /* eeprom debug */
|
|
#define EL_UIO 0x00000800 /* unmapped i/o */
|
|
#define EL_IO 0x00001000 /* all i/o */
|
|
#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */
|
|
#define EL_SVP 0x00004000 /* SVP stuff */
|
|
#define EL_PICOHW 0x00008000 /* Pico stuff */
|
|
#define EL_IDLE 0x00010000 /* idle loop det. */
|
|
#define EL_CDREGS 0x00020000 /* MCD: register access */
|
|
#define EL_CDREG3 0x00040000 /* MCD: register 3 only */
|
|
#define EL_32X 0x00080000
|
|
#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */
|
|
#define EL_32XP 0x00200000 /* 32X peripherals */
|
|
#define EL_CD 0x00400000 /* MCD */
|
|
|
|
#define EL_STATUS 0x40000000 /* status messages */
|
|
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */
|
|
|
|
#if EL_LOGMASK
|
|
#define elprintf(w,f,...) \
|
|
do { \
|
|
if ((w) & EL_LOGMASK) \
|
|
lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \
|
|
} while (0)
|
|
#elif defined(_MSC_VER)
|
|
#define elprintf
|
|
#else
|
|
#define elprintf(w,f,...)
|
|
#endif
|
|
|
|
// profiling
|
|
#ifdef PPROF
|
|
#include <platform/linux/pprof.h>
|
|
#else
|
|
#define pprof_init()
|
|
#define pprof_finish()
|
|
#define pprof_start(x)
|
|
#define pprof_end(...)
|
|
#define pprof_end_sub(...)
|
|
#endif
|
|
|
|
#ifdef EVT_LOG
|
|
enum evt {
|
|
EVT_FRAME_START,
|
|
EVT_NEXT_LINE,
|
|
EVT_RUN_START,
|
|
EVT_RUN_END,
|
|
EVT_POLL_START,
|
|
EVT_POLL_END,
|
|
EVT_CNT
|
|
};
|
|
|
|
enum evt_cpu {
|
|
EVT_M68K,
|
|
EVT_S68K,
|
|
EVT_MSH2,
|
|
EVT_SSH2,
|
|
EVT_CPU_CNT
|
|
};
|
|
|
|
void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);
|
|
void pevt_dump(void);
|
|
|
|
#define pevt_log_m68k(e) \
|
|
pevt_log(SekCyclesDone(), EVT_M68K, e)
|
|
#define pevt_log_m68k_o(e) \
|
|
pevt_log(SekCyclesDone(), EVT_M68K, e)
|
|
#define pevt_log_sh2(sh2, e) \
|
|
pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)
|
|
#define pevt_log_sh2_o(sh2, e) \
|
|
pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)
|
|
#else
|
|
#define pevt_log(c, e)
|
|
#define pevt_log_m68k(e)
|
|
#define pevt_log_m68k_o(e)
|
|
#define pevt_log_sh2(sh2, e)
|
|
#define pevt_log_sh2_o(sh2, e)
|
|
#define pevt_dump()
|
|
#endif
|
|
|
|
// misc
|
|
#ifdef _MSC_VER
|
|
#define cdprintf
|
|
#else
|
|
#define cdprintf(x...)
|
|
#endif
|
|
|
|
#if defined(__GNUC__) && defined(__i386__)
|
|
#define REGPARM(x) __attribute__((regparm(x)))
|
|
#else
|
|
#define REGPARM(x)
|
|
#endif
|
|
|
|
#ifdef __GNUC__
|
|
#define NOINLINE __attribute__((noinline))
|
|
#else
|
|
#define NOINLINE
|
|
#endif
|
|
|
|
#ifdef __cplusplus
|
|
} // End of extern "C"
|
|
#endif
|
|
|
|
#endif // PICO_INTERNAL_INCLUDED
|
|
|