343 lines
11 KiB
C#
343 lines
11 KiB
C#
using BizHawk.Common;
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using BizHawk.Emulation.Common;
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using BizHawk.Emulation.Cores.Components.H6280;
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using System;
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namespace BizHawk.Emulation.Cores.PCEngine
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{
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// HuC6270 Video Display Controller
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public sealed partial class VDC : IVideoProvider
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{
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public ushort[] VRAM = new ushort[0x8000];
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public ushort[] SpriteAttributeTable = new ushort[256];
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public readonly byte[] PatternBuffer = new byte[0x20000];
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public readonly byte[] SpriteBuffer = new byte[0x20000];
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public byte RegisterLatch;
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public ushort[] Registers = new ushort[0x20];
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public ushort ReadBuffer;
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public byte StatusByte;
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internal bool DmaRequested;
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internal bool SatDmaRequested;
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internal bool SatDmaPerformed;
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public ushort IncrementWidth
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{
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get
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{
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switch ((Registers[5] >> 11) & 3)
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{
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case 0: return 1;
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case 1: return 32;
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case 2: return 64;
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case 3: return 128;
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}
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return 1;
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}
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}
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public bool BackgroundEnabled => (Registers[CR] & 0x80) != 0;
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public bool SpritesEnabled => (Registers[CR] & 0x40) != 0;
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public bool VBlankInterruptEnabled => (Registers[CR] & 0x08) != 0;
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public bool RasterCompareInterruptEnabled => (Registers[CR] & 0x04) != 0;
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public bool SpriteOverflowInterruptEnabled => (Registers[CR] & 0x02) != 0;
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public bool SpriteCollisionInterruptEnabled => (Registers[CR] & 0x01) != 0;
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public bool Sprite4ColorModeEnabled => (Registers[MWR] & 0x0C) == 4;
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public int BatWidth { get { switch ((Registers[MWR] >> 4) & 3) { case 0: return 32; case 1: return 64; default: return 128; } } }
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public int BatHeight => (Registers[MWR] & 0x40) == 0 ? 32 : 64;
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public int RequestedFrameWidth => ((Registers[HDR] & 0x3F) + 1) * 8;
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public int RequestedFrameHeight => (Registers[VDW] & 0x1FF) + 1;
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public int DisplayStartLine => (Registers[VPR] >> 8) + (Registers[VPR] & 0x1F);
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public int ViewStartLine => (Registers[VPR] >> 8) + 2;
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private const int MAWR = 0; // Memory Address Write Register
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private const int MARR = 1; // Memory Address Read Register
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private const int VRR = 2; // VRAM Read Register
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private const int VWR = 2; // VRAM Write Register
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private const int CR = 5; // Control Register
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private const int RCR = 6; // Raster Compare Register
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private const int BXR = 7; // Background X-scroll Register
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private const int BYR = 8; // Background Y-scroll Register
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private const int MWR = 9; // Memory-access Width Register
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private const int HSR = 10; // Horizontal Sync Register
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private const int HDR = 11; // Horizontal Display Register
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private const int VPR = 12; // Vertical synchronous register
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private const int VDW = 13; // Vertical display register
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private const int VCR = 14; // Vertical display END position register;
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private const int DCR = 15; // DMA Control Register
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private const int SOUR = 16; // Source address for DMA
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private const int DESR = 17; // Destination address for DMA
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private const int LENR = 18; // Length of DMA transfer. Writing this will initiate DMA.
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private const int SATB = 19; // Sprite Attribute Table base location in VRAM
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private const int RegisterSelect = 0;
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private const int LSB = 2;
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private const int MSB = 3;
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public const byte StatusVerticalBlanking = 0x20;
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public const byte StatusVramVramDmaComplete = 0x10;
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public const byte StatusVramSatDmaComplete = 0x08;
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public const byte StatusRasterCompare = 0x04;
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public const byte StatusSpriteOverflow = 0x02;
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public const byte StatusSprite0Collision = 0x01;
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const int VramSize = 0x8000;
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private readonly PCEngine pce;
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private readonly HuC6280 cpu;
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private readonly VCE vce;
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public int MultiResHack = 0;
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public VDC(PCEngine pce, HuC6280 cpu, VCE vce)
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{
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this.pce = pce;
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this.cpu = cpu;
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this.vce = vce;
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RenderBackgroundScanline = RenderBackgroundScanlineUnsafe;
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Registers[HSR] = 0x00FF;
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Registers[HDR] = 0x001F;
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Registers[VDW] = 0x01FF;
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Registers[VPR] = 0xFFFF;
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Registers[VCR] = 0xFFFF;
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ReadBuffer = 0xFFFF;
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}
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public void WriteVDC(int port, byte value)
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{
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cpu.PendingCycles--;
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port &= 3;
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if (port == RegisterSelect)
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{
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RegisterLatch = (byte)(value & 0x1F);
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}
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else if (port == LSB)
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{
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Registers[RegisterLatch] &= 0xFF00;
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Registers[RegisterLatch] |= value;
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if (RegisterLatch == BYR)
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BackgroundY = Registers[BYR] & 0x1FF;
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RegisterCommit(RegisterLatch, msbComplete: false);
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}
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else if (port == MSB)
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{
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Registers[RegisterLatch] &= 0x00FF;
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Registers[RegisterLatch] |= (ushort)(value << 8);
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RegisterCommit(RegisterLatch, msbComplete: true);
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}
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}
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private void RegisterCommit(int register, bool msbComplete)
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{
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switch (register)
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{
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case MARR: // Memory Address Read Register
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if (!msbComplete) break;
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ReadBuffer = VRAM[Registers[MARR] & 0x7FFF];
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break;
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case VWR: // VRAM Write Register
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if (!msbComplete) break;
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if (Registers[MAWR] < VramSize) // Several games attempt to write past the end of VRAM
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{
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VRAM[Registers[MAWR]] = Registers[VWR];
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UpdatePatternData((ushort)(Registers[MAWR] & 0x7FFF));
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UpdateSpriteData((ushort)(Registers[MAWR] & 0x7FFF));
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}
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Registers[MAWR] += IncrementWidth;
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break;
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case BXR:
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Registers[BXR] &= 0x3FF;
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break;
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case BYR:
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Registers[BYR] &= 0x1FF;
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BackgroundY = Registers[BYR];
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break;
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case HDR: // Horizontal Display Register - update framebuffer size
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FrameWidth = RequestedFrameWidth;
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FramePitch = MultiResHack == 0 ? FrameWidth : MultiResHack;
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//if (FrameBuffer.Length != FramePitch * FrameHeight)
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//FrameBuffer = new int[FramePitch * FrameHeight];
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break;
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case VDW: // Vertical Display Word? - update framebuffer size
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//FrameHeight = RequestedFrameHeight;
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FrameWidth = RequestedFrameWidth;
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//if (FrameHeight > 242)
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//FrameHeight = 242;
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if (MultiResHack != 0)
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FramePitch = MultiResHack;
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//if (FrameBuffer.Length != FramePitch * FrameHeight)
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//FrameBuffer = new int[FramePitch * FrameHeight];
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break;
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case LENR: // Initiate DMA transfer
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if (!msbComplete) break;
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DmaRequested = true;
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break;
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case SATB:
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if (!msbComplete) break;
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SatDmaRequested = true;
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break;
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}
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}
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public byte ReadVDC(int port)
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{
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cpu.PendingCycles--;
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byte retval = 0;
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port &= 3;
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switch (port)
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{
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case 0: // return status byte;
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retval = StatusByte;
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StatusByte = 0; // maybe bit 6 should be preserved. but we dont currently emulate it.
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cpu.IRQ1Assert = false;
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return retval;
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case 1: // unused
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return 0;
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case 2: // LSB
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return (byte)ReadBuffer;
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case 3: // MSB
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retval = (byte)(ReadBuffer >> 8);
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if (RegisterLatch == VRR)
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{
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Registers[MARR] += IncrementWidth;
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ReadBuffer = VRAM[Registers[MARR] & 0x7FFF];
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}
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return retval;
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}
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return 0;
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}
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internal void RunDmaForScanline()
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{
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// TODO: dont do this all in one scanline. I guess it can do about 227 words per scanline.
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// TODO: to be honest, dont do it in a block per scanline. put it in the CPU think function.
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//Console.WriteLine("******************************* Doing some dma ******************************");
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int advanceSource = (Registers[DCR] & 4) == 0 ? +1 : -1;
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int advanceDest = (Registers[DCR] & 8) == 0 ? +1 : -1;
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int wordsDone = 0;
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for (; Registers[LENR] < 0xFFFF; Registers[LENR]--, wordsDone++)
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{
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VRAM[Registers[DESR] & 0x7FFF] = VRAM[Registers[SOUR] & 0x7FFF];
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UpdatePatternData(Registers[DESR]);
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UpdateSpriteData(Registers[DESR]);
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Registers[DESR] = (ushort)(Registers[DESR] + advanceDest);
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Registers[SOUR] = (ushort)(Registers[SOUR] + advanceSource);
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/*if (wordsDone == 227) {
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Console.WriteLine("ended dma for this scanline");
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return;
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}*/
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}
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DmaRequested = false;
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//Console.WriteLine("DMA finished");
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if ((Registers[DCR] & 2) > 0)
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{
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//Log.Note("Vdc","FIRE VRAM-VRAM DMA COMPLETE IRQ");
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StatusByte |= StatusVramVramDmaComplete;
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cpu.IRQ1Assert = true;
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}
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}
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public void UpdateSpriteAttributeTable()
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{
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if ((SatDmaRequested || (Registers[DCR] & 0x10) != 0) && Registers[SATB] <= 0x7F00)
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{
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SatDmaRequested = false;
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SatDmaPerformed = true;
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for (int i = 0; i < 256; i++)
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{
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SpriteAttributeTable[i] = VRAM[Registers[SATB] + i];
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}
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}
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}
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public void UpdatePatternData(ushort addr)
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{
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int tileNo = addr >> 4;
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int tileLineOffset = addr & 0x7;
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int bitplane01 = VRAM[((tileNo * 16) + tileLineOffset) & 0x7FFF];
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int bitplane23 = VRAM[((tileNo * 16) + tileLineOffset + 8) & 0x7FFF];
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int patternBufferBase = (tileNo * 64) + (tileLineOffset * 8);
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for (int x = 0; x < 8; x++)
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{
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byte pixel = (byte)((bitplane01 >> x) & 1);
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pixel |= (byte)(((bitplane01 >> (x + 8)) & 1) << 1);
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pixel |= (byte)(((bitplane23 >> x) & 1) << 2);
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pixel |= (byte)(((bitplane23 >> (x + 8)) & 1) << 3);
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PatternBuffer[patternBufferBase + (7 - x)] = pixel;
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}
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}
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public void UpdateSpriteData(ushort addr)
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{
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int tileNo = addr >> 6;
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int tileOfs = addr & 0x3F;
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int bitplane = tileOfs / 16;
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int line = addr & 0x0F;
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int ofs = (tileNo * 256) + (line * 16) + 15;
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ushort value = VRAM[addr & 0x7FFF];
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byte bitAnd = (byte)(~(1 << bitplane));
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byte bitOr = (byte)(1 << bitplane);
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for (int i = 0; i < 16; i++)
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{
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if ((value & 1) == 1)
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SpriteBuffer[ofs] |= bitOr;
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else
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SpriteBuffer[ofs] &= bitAnd;
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ofs--;
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value >>= 1;
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}
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}
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public void SyncState(Serializer ser, int vdcNo)
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{
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ser.BeginSection("VDC"+vdcNo);
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ser.Sync("VRAM", ref VRAM, false);
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ser.Sync("SAT", ref SpriteAttributeTable, false);
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ser.Sync("Registers", ref Registers, false);
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ser.Sync("RegisterLatch", ref RegisterLatch);
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ser.Sync("ReadBuffer", ref ReadBuffer);
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ser.Sync("StatusByte", ref StatusByte);
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ser.Sync("DmaRequested", ref DmaRequested);
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ser.Sync("SatDmaRequested", ref SatDmaRequested);
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ser.Sync("SatDmaPerformed", ref SatDmaPerformed);
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ser.Sync("ScanLine", ref ScanLine);
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ser.Sync("BackgroundY", ref BackgroundY);
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ser.Sync("RCRCounter", ref RCRCounter);
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ser.Sync("ActiveLine", ref ActiveLine);
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ser.EndSection();
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if (ser.IsReader)
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{
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for (ushort i = 0; i < VRAM.Length; i++)
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{
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UpdatePatternData(i);
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UpdateSpriteData(i);
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}
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RegisterCommit(HDR, true);
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RegisterCommit(VDW, true);
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}
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}
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}
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}
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