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BizHawk/BizHawk.Emulation.Cores/CPUs/Z80A
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alyosha-tas a185f33487 Z80A: Add a WAIT state that can puase the CPU on reads / writes 
NOTE: a wait state is added automatically to IN/OUT reads / writes, but I don't know if this is already accounted for in the cycle timings, TODO.
 		2018-05-15 09:44:39 -04:00
..
Execute.cs Z80A: Add a WAIT state that can puase the CPU on reads / writes 2018-05-15 09:44:39 -04:00
Interrupts.cs z80: clean up 2018-03-16 17:50:51 -04:00
NewDisassembler.cs z80: clean up 2018-03-16 17:50:51 -04:00
Operations.cs Z80: Fix Flags for IN operations 2018-04-18 19:00:59 -04:00
ReadMe.txt z80: clean up 2018-03-16 17:50:51 -04:00
Registers.cs Z80A: Add a WAIT state that can puase the CPU on reads / writes 2018-05-15 09:44:39 -04:00
Tables_Direct.cs z80: fix port access behaviour 2017-12-01 08:20:18 -05:00
Tables_Indirect.cs z80: fix port addressing in some cases 2018-03-15 20:47:47 -04:00
Z80A.cs Z80A: Add a WAIT state that can puase the CPU on reads / writes 2018-05-15 09:44:39 -04:00

ReadMe.txt 

TODO: 

Mode 0
Check T-cycle level memory access timing
Check R register 
new tests for WZ Registers
Memory refresh - IR is pushed onto the address bus at instruction start, does anything need this?