232 lines
6.2 KiB
C++
232 lines
6.2 KiB
C++
//
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// Copyright (c) 2004 K. Wilkins
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//
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// This software is provided 'as-is', without any express or implied warranty.
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// In no event will the authors be held liable for any damages arising from
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// the use of this software.
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//
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// Permission is granted to anyone to use this software for any purpose,
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// including commercial applications, and to alter it and redistribute it
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// freely, subject to the following restrictions:
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//
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// 1. The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software. If you use this software
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// in a product, an acknowledgment in the product documentation would be
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// appreciated but is not required.
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//
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// 2. Altered source versions must be plainly marked as such, and must not
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// be misrepresented as being the original software.
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//
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// 3. This notice may not be removed or altered from any source distribution.
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//
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//////////////////////////////////////////////////////////////////////////////
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// Handy - An Atari Lynx Emulator //
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// Copyright (c) 1996,1997 //
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// K. Wilkins //
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//////////////////////////////////////////////////////////////////////////////
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// 65C02 Emulation class //
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//////////////////////////////////////////////////////////////////////////////
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// //
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// This class emulates a 65C02 processor. It is interfaced to the rest of //
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// the system via the PEEK/POKE macros and a number of global variables //
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// //
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// K. Wilkins //
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// August 1997 //
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// //
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//////////////////////////////////////////////////////////////////////////////
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// Revision History: //
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// ----------------- //
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// //
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// 01Aug1997 KW Document header added & class documented. //
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// //
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//////////////////////////////////////////////////////////////////////////////
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#ifndef C65C02_H
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#define C65C02_H
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//#include <crtdbg.h>
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//#define TRACE_CPU
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#ifdef TRACE_CPU
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#define TRACE_CPU0(msg) _RPT1(_CRT_WARN,"C65C02::"msg" (Time=%012d)\n",gSystemCycleCount)
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#define TRACE_CPU1(msg,arg1) _RPT2(_CRT_WARN,"C65C02::"msg" (Time=%012d)\n",arg1,gSystemCycleCount)
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#define TRACE_CPU2(msg,arg1,arg2) _RPT3(_CRT_WARN,"C65C02::"msg" (Time=%012d)\n",arg1,arg2,gSystemCycleCount)
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#define TRACE_CPU3(msg,arg1,arg2,arg3) _RPT4(_CRT_WARN,"C65C02::"msg" (Time=%012d)\n",arg1,arg2,arg3,gSystemCycleCount)
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#else
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#define TRACE_CPU0(msg)
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#define TRACE_CPU1(msg,arg1)
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#define TRACE_CPU2(msg,arg1,arg2)
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#define TRACE_CPU3(msg,arg1,arg2,arg3)
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#endif
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//
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// Handy definitions
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//
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#define NMI_VECTOR 0xfffa
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#define BOOT_VECTOR 0xfffc
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#define IRQ_VECTOR 0xfffe
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#define MAX_CPU_BREAKPOINTS 8
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//
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// ACCESS MACROS
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//
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//#define CPU_PEEK(m) (mSystem.Peek_CPU(m))
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//#define CPU_PEEKW(m) (mSystem.PeekW_CPU(m))
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//#define CPU_POKE(m1,m2) (mSystem.Poke_CPU(m1,m2))
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#define CPU_PEEK(m) (((m<0xfc00)?mRamPointer[m]:mSystem.Peek_CPU(m)))
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#define CPU_PEEKW(m) (((m<0xfc00)?(mRamPointer[m]+(mRamPointer[m+1]<<8)):mSystem.PeekW_CPU(m)))
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#define CPU_POKE(m1,m2) {if(m1<0xfc00) mRamPointer[m1]=m2; else mSystem.Poke_CPU(m1,m2);}
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enum { illegal=0,
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accu,
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imm,
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absl,
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zp,
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zpx,
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zpy,
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absx,
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absy,
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iabsx,
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impl,
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rel,
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zrel,
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indx,
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indy,
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iabs,
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ind
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};
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typedef struct
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{
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int PS; // Processor status register 8 bits
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int A; // Accumulator 8 bits
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int X; // X index register 8 bits
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int Y; // Y index register 8 bits
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int SP; // Stack Pointer 8 bits
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int Opcode; // Instruction opcode 8 bits
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int Operand;// Intructions operand 16 bits
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int PC; // Program Counter 16 bits
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bool NMI;
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bool IRQ;
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bool WAIT;
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}C6502_REGS;
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//
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// The CPU emulation macros
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//
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#include "c6502mak.h"
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//
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// The CPU emulation macros
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//
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class C65C02
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{
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public:
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C65C02(CSystem& parent)
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:mSystem(parent)
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{
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TRACE_CPU0("C65C02()");
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// Compute the BCD lookup table
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for(uint16 t=0;t<256;++t)
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{
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mBCDTable[0][t]=((t >> 4) * 10) + (t & 0x0f);
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mBCDTable[1][t]=(((t % 100) / 10) << 4) | (t % 10);
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}
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Reset();
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}
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~C65C02()
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{
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TRACE_CPU0("~C65C02()");
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}
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public:
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void Reset();
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void Update();
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void SetRegs(C6502_REGS ®s);
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void GetRegs(C6502_REGS ®s);
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inline int GetPC() { return mPC; }
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template<bool isReader>void SyncState(NewState *ns);
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private:
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CSystem &mSystem;
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// CPU Flags & status
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int mA; // Accumulator 8 bits
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int mX; // X index register 8 bits
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int mY; // Y index register 8 bits
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int mSP; // Stack Pointer 8 bits
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int mOpcode; // Instruction opcode 8 bits
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int mOperand; // Intructions operand 16 bits
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int mPC; // Program Counter 16 bits
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int mN; // N flag for processor status register
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int mV; // V flag for processor status register
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int mB; // B flag for processor status register
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int mD; // D flag for processor status register
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int mI; // I flag for processor status register
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int mZ; // Z flag for processor status register
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int mC; // C flag for processor status register
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int mIRQActive;
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uint8 *mRamPointer;
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// Associated lookup tables
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int mBCDTable[2][256];
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//
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// Opcode prototypes
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//
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private:
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// Answers value of the Processor Status register
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INLINE int PS() const
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{
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uint8 ps = 0x20;
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if(mN) ps|=0x80;
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if(mV) ps|=0x40;
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if(mB) ps|=0x10;
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if(mD) ps|=0x08;
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if(mI) ps|=0x04;
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if(mZ) ps|=0x02;
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if(mC) ps|=0x01;
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return ps;
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}
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// Change the processor flags to correspond to the given value
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INLINE void PS(int ps)
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{
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mN=ps&0x80;
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mV=ps&0x40;
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mB=ps&0x10;
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mD=ps&0x08;
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mI=ps&0x04;
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mZ=ps&0x02;
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mC=ps&0x01;
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}
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};
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#endif
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