520 lines
14 KiB
C
520 lines
14 KiB
C
/*
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* SH2 peripherals/"system on chip"
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* (C) notaz, 2013
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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*
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* rough fffffe00-ffffffff map:
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* e00-e05 SCI serial communication interface
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* e10-e1a FRT free-running timer
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* e60-e68 VCRx irq vectors
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* e71-e72 DRCR dma selection
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* e80-e83 WDT watchdog timer
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* e91 SBYCR standby control
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* e92 CCR cache control
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* ee0 ICR irq control
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* ee2 IPRA irq priorities
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* ee4 VCRWDT WDT irq vectors
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* f00-f17 DIVU
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* f40-f7b UBC user break controller
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* f80-fb3 DMAC
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* fe0-ffb BSC bus state controller
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*/
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#include "../pico_int.h"
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#include "../memory.h"
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// DMAC handling
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struct dma_chan {
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unsigned int sar, dar; // src, dst addr
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unsigned int tcr; // transfer count
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unsigned int chcr; // chan ctl
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// -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de
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// ts - transfer size: 1, 2, 4, 16 bytes
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// ar - auto request if 1, else dreq signal
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// ie - irq enable
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// te - transfer end
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// de - dma enable
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#define DMA_AR (1 << 9)
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#define DMA_IE (1 << 2)
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#define DMA_TE (1 << 1)
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#define DMA_DE (1 << 0)
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};
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struct dmac {
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struct dma_chan chan[2];
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unsigned int vcrdma0;
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unsigned int unknown0;
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unsigned int vcrdma1;
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unsigned int unknown1;
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unsigned int dmaor;
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// -- pr ae nmif dme
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// pr - priority: chan0 > chan1 or round-robin
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// ae - address error
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// nmif - nmi occurred
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// dme - DMA master enable
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#define DMA_DME (1 << 0)
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};
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static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
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{
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char *regs = (void *)sh2->peri_regs;
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struct dmac *dmac = (void *)(regs + 0x180);
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int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
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int vector = (chan == &dmac->chan[0]) ?
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dmac->vcrdma0 : dmac->vcrdma1;
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elprintf(EL_32XP, "dmac irq %d %d", level, vector);
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sh2_internal_irq(sh2, level, vector & 0x7f);
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}
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static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
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{
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chan->chcr |= DMA_TE; // DMA has ended normally
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p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDone());
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if (chan->chcr & DMA_IE)
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dmac_te_irq(sh2, chan);
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}
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static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
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{
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u32 size, d;
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size = (chan->chcr >> 10) & 3;
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switch (size) {
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case 0:
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d = p32x_sh2_read8(chan->sar, sh2);
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p32x_sh2_write8(chan->dar, d, sh2);
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case 1:
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d = p32x_sh2_read16(chan->sar, sh2);
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p32x_sh2_write16(chan->dar, d, sh2);
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break;
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case 2:
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d = p32x_sh2_read32(chan->sar, sh2);
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p32x_sh2_write32(chan->dar, d, sh2);
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break;
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case 3:
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d = p32x_sh2_read32(chan->sar + 0x00, sh2);
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p32x_sh2_write32(chan->dar + 0x00, d, sh2);
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d = p32x_sh2_read32(chan->sar + 0x04, sh2);
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p32x_sh2_write32(chan->dar + 0x04, d, sh2);
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d = p32x_sh2_read32(chan->sar + 0x08, sh2);
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p32x_sh2_write32(chan->dar + 0x08, d, sh2);
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d = p32x_sh2_read32(chan->sar + 0x0c, sh2);
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p32x_sh2_write32(chan->dar + 0x0c, d, sh2);
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chan->sar += 16; // always?
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if (chan->chcr & (1 << 15))
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chan->dar -= 16;
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if (chan->chcr & (1 << 14))
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chan->dar += 16;
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chan->tcr -= 4;
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return;
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}
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chan->tcr--;
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size = 1 << size;
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if (chan->chcr & (1 << 15))
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chan->dar -= size;
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if (chan->chcr & (1 << 14))
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chan->dar += size;
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if (chan->chcr & (1 << 13))
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chan->sar -= size;
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if (chan->chcr & (1 << 12))
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chan->sar += size;
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}
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// DMA trigger by SH2 register write
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static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
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{
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elprintf_sh2(sh2, EL_32XP, "DMA %08x->%08x, cnt %d, chcr %04x @%06x",
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chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
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chan->tcr &= 0xffffff;
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if (chan->chcr & DMA_AR) {
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// auto-request transfer
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while ((int)chan->tcr > 0)
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dmac_transfer_one(sh2, chan);
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dmac_transfer_complete(sh2, chan);
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return;
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}
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// DREQ0 is only sent after first 4 words are written.
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// we do multiple of 4 words to avoid messing up alignment
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if ((chan->sar & ~0x20000000) == 0x00004012) {
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if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
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elprintf(EL_32XP, "68k -> sh2 DMA");
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p32x_dreq0_trigger();
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}
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return;
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}
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// DREQ1
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if ((chan->dar & 0xc7fffff0) == 0x00004030)
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return;
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elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
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"%08x->%08x, cnt %d, chcr %04x @%06x",
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chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
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}
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// timer state - FIXME
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static int timer_cycles[2];
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static int timer_tick_cycles[2];
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// timers
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void p32x_timers_recalc(void)
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{
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int cycles;
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int tmp, i;
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// SH2 timer step
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for (i = 0; i < 2; i++) {
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tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7;
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// Sclk cycles per timer tick
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if (tmp)
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cycles = 0x20 << tmp;
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else
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cycles = 2;
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timer_tick_cycles[i] = cycles;
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timer_cycles[i] = 0;
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elprintf(EL_32XP, "WDT cycles[%d] = %d", i, cycles);
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}
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}
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void p32x_timers_do(unsigned int m68k_slice)
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{
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unsigned int cycles = m68k_slice * 3;
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int cnt, i;
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// WDT timers
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for (i = 0; i < 2; i++) {
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void *pregs = sh2s[i].peri_regs;
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if (PREG8(pregs, 0x80) & 0x20) { // TME
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timer_cycles[i] += cycles;
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cnt = PREG8(pregs, 0x81);
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while (timer_cycles[i] >= timer_tick_cycles[i]) {
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timer_cycles[i] -= timer_tick_cycles[i];
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cnt++;
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}
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if (cnt >= 0x100) {
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int level = PREG8(pregs, 0xe3) >> 4;
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int vector = PREG8(pregs, 0xe4) & 0x7f;
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elprintf(EL_32XP, "%csh2 WDT irq (%d, %d)",
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i ? 's' : 'm', level, vector);
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sh2_internal_irq(&sh2s[i], level, vector);
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cnt &= 0xff;
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}
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PREG8(pregs, 0x81) = cnt;
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}
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}
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}
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void sh2_peripheral_reset(SH2 *sh2)
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{
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memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ?
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PREG8(sh2->peri_regs, 0x001) = 0xff; // SCI BRR
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PREG8(sh2->peri_regs, 0x003) = 0xff; // SCI TDR
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PREG8(sh2->peri_regs, 0x004) = 0x84; // SCI SSR
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PREG8(sh2->peri_regs, 0x011) = 0x01; // TIER
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PREG8(sh2->peri_regs, 0x017) = 0xe0; // TOCR
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}
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// ------------------------------------------------------------------
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// SH2 internal peripheral memhandlers
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// we keep them in little endian format
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u32 sh2_peripheral_read8(u32 a, SH2 *sh2)
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{
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u8 *r = (void *)sh2->peri_regs;
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u32 d;
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a &= 0x1ff;
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d = PREG8(r, a);
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elprintf_sh2(sh2, EL_32XP, "peri r8 [%08x] %02x @%06x",
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a | ~0x1ff, d, sh2_pc(sh2));
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return d;
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}
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u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
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{
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u16 *r = (void *)sh2->peri_regs;
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u32 d;
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a &= 0x1ff;
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d = r[(a / 2) ^ 1];
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elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
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a | ~0x1ff, d, sh2_pc(sh2));
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return d;
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}
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u32 sh2_peripheral_read32(u32 a, SH2 *sh2)
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{
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u32 d;
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a &= 0x1fc;
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d = sh2->peri_regs[a / 4];
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elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x",
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a | ~0x1ff, d, sh2_pc(sh2));
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return d;
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}
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static void sci_trigger(SH2 *sh2, u8 *r)
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{
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u8 *oregs;
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if (!(PREG8(r, 2) & 0x20))
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return; // transmitter not enabled
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if ((PREG8(r, 4) & 0x80)) // TDRE - TransmitDataR Empty
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return;
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oregs = (u8 *)sh2->other_sh2->peri_regs;
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if (!(PREG8(oregs, 2) & 0x10))
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return; // receiver not enabled
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PREG8(oregs, 5) = PREG8(r, 3); // other.RDR = this.TDR
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PREG8(r, 4) |= 0x80; // TDRE - TDR empty
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PREG8(oregs, 4) |= 0x40; // RDRF - RDR Full
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// might need to delay these a bit..
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if (PREG8(r, 2) & 0x80) { // TIE - tx irq enabled
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int level = PREG8(oregs, 0x60) >> 4;
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int vector = PREG8(oregs, 0x64) & 0x7f;
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elprintf_sh2(sh2, EL_32XP, "SCI tx irq (%d, %d)",
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level, vector);
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sh2_internal_irq(sh2, level, vector);
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}
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// TODO: TEIE
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if (PREG8(oregs, 2) & 0x40) { // RIE - rx irq enabled
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int level = PREG8(oregs, 0x60) >> 4;
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int vector = PREG8(oregs, 0x63) & 0x7f;
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elprintf_sh2(sh2->other_sh2, EL_32XP, "SCI rx irq (%d, %d)",
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level, vector);
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sh2_internal_irq(sh2->other_sh2, level, vector);
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}
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}
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void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
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{
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u8 *r = (void *)sh2->peri_regs;
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u8 old;
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elprintf_sh2(sh2, EL_32XP, "peri w8 [%08x] %02x @%06x",
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a, d, sh2_pc(sh2));
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a &= 0x1ff;
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old = PREG8(r, a);
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switch (a) {
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case 0x002: // SCR - serial control
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if (!(PREG8(r, a) & 0x20) && (d & 0x20)) { // TE being set
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PREG8(r, a) = d;
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sci_trigger(sh2, r);
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}
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break;
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case 0x003: // TDR - transmit data
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break;
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case 0x004: // SSR - serial status
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d = (old & (d | 0x06)) | (d & 1);
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PREG8(r, a) = d;
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sci_trigger(sh2, r);
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return;
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case 0x005: // RDR - receive data
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break;
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case 0x010: // TIER
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if (d & 0x8e)
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elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d);
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d = (d & 0x8e) | 1;
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break;
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case 0x017: // TOCR
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d |= 0xe0;
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break;
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}
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PREG8(r, a) = d;
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}
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void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
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{
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u16 *r = (void *)sh2->peri_regs;
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elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x",
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a, d, sh2_pc(sh2));
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a &= 0x1ff;
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// evil WDT
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if (a == 0x80) {
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if ((d & 0xff00) == 0xa500) { // WTCSR
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PREG8(r, 0x80) = d;
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p32x_timers_recalc();
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}
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if ((d & 0xff00) == 0x5a00) // WTCNT
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PREG8(r, 0x81) = d;
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return;
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}
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r[(a / 2) ^ 1] = d;
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}
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void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
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{
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u32 *r = sh2->peri_regs;
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u32 old;
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elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x",
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a, d, sh2_pc(sh2));
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a &= 0x1fc;
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old = r[a / 4];
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r[a / 4] = d;
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switch (a) {
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// division unit (TODO: verify):
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case 0x104: // DVDNT: divident L, starts divide
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elprintf_sh2(sh2, EL_32XP, "divide %08x / %08x",
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d, r[0x100 / 4]);
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if (r[0x100 / 4]) {
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signed int divisor = r[0x100 / 4];
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r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
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r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
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}
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else
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r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
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break;
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case 0x114:
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elprintf_sh2(sh2, EL_32XP, "divide %08x%08x / %08x @%08x",
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r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
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if (r[0x100 / 4]) {
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signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
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signed int divisor = r[0x100 / 4];
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// XXX: undocumented mirroring to 0x118,0x11c?
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r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
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divident /= divisor;
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r[0x11c / 4] = r[0x114 / 4] = divident;
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divident >>= 31;
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if ((unsigned long long)divident + 1 > 1) {
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//elprintf_sh2(sh2, EL_32XP, "divide overflow! @%08x", sh2_pc(sh2));
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r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
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}
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}
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else
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r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
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break;
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}
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// perhaps starting a DMA?
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if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
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struct dmac *dmac = (void *)&sh2->peri_regs[0x180 / 4];
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if (a == 0x1b0 && !((old ^ d) & d & DMA_DME))
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return;
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if (!(dmac->dmaor & DMA_DME))
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return;
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if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
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dmac_trigger(sh2, &dmac->chan[0]);
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if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
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dmac_trigger(sh2, &dmac->chan[1]);
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}
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}
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/* 32X specific */
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static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
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{
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unsigned short dreqlen = Pico32x.regs[0x10 / 2];
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int i;
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// debug/sanity checks
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if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d",
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chan->tcr, dreqlen);
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// note: DACK is not connected, single addr mode should not be used
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if ((chan->chcr & 0x3f08) != 0x0400)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
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if ((chan->sar & ~0x20000000) != 0x00004012)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x", chan->sar);
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// HACK: assume bus is busy and SH2 is halted
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sh2->state |= SH2_STATE_SLEEP;
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for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
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elprintf_sh2(sh2, EL_32XP, "dreq0 [%08x] %04x, dreq_len %d",
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chan->dar, Pico32x.dmac_fifo[i], dreqlen);
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p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
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chan->dar += 2;
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chan->tcr--;
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}
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if (Pico32x.dmac0_fifo_ptr != i)
|
|
memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i],
|
|
(Pico32x.dmac0_fifo_ptr - i) * 2);
|
|
Pico32x.dmac0_fifo_ptr -= i;
|
|
|
|
Pico32x.regs[6 / 2] &= ~P32XS_FULL;
|
|
if (chan->tcr == 0)
|
|
dmac_transfer_complete(sh2, chan);
|
|
else
|
|
sh2_end_run(sh2, 16);
|
|
}
|
|
|
|
static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
|
|
{
|
|
// debug/sanity checks
|
|
if ((chan->chcr & 0xc308) != 0x0000)
|
|
elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr);
|
|
if ((chan->dar & ~0xf) != 0x20004030)
|
|
elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
|
|
|
|
dmac_transfer_one(sh2, chan);
|
|
if (chan->tcr == 0)
|
|
dmac_transfer_complete(sh2, chan);
|
|
}
|
|
|
|
void p32x_dreq0_trigger(void)
|
|
{
|
|
struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
|
|
struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
|
|
|
|
elprintf(EL_32XP, "dreq0_trigger");
|
|
if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
|
|
dreq0_do(&msh2, &mdmac->chan[0]);
|
|
}
|
|
if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) {
|
|
dreq0_do(&ssh2, &sdmac->chan[0]);
|
|
}
|
|
}
|
|
|
|
void p32x_dreq1_trigger(void)
|
|
{
|
|
struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
|
|
struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
|
|
int hit = 0;
|
|
|
|
elprintf(EL_32XP, "dreq1_trigger");
|
|
if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) {
|
|
dreq1_do(&msh2, &mdmac->chan[1]);
|
|
hit = 1;
|
|
}
|
|
if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) {
|
|
dreq1_do(&ssh2, &sdmac->chan[1]);
|
|
hit = 1;
|
|
}
|
|
|
|
// debug
|
|
#if (EL_LOGMASK & (EL_32XP|EL_ANOMALY))
|
|
{
|
|
static int miss_count;
|
|
if (!hit) {
|
|
if (++miss_count == 4)
|
|
elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
|
|
}
|
|
else
|
|
miss_count = 0;
|
|
}
|
|
#endif
|
|
(void)hit;
|
|
}
|
|
|
|
// vim:shiftwidth=2:ts=2:expandtab
|