9 lines
294 B
Plaintext
9 lines
294 B
Plaintext
TODO:
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Mode 0 and 2 interrupts
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Check T-cycle level memory access timing
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Check R register
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new tests for WZ Registers
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Memory refresh - IR is pushed onto the address bus at instruction start, does anything need this?
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Data Bus - For mode zero and 2 interrupts, need a system that uses it to test
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