223 lines
6.6 KiB
C#
223 lines
6.6 KiB
C#
using System;
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namespace BizHawk.Emulation.Cores.Sega.MasterSystem
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{
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public partial class SMS
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{
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// The Sega memory mapper layout looks like so:
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// $0000-$03FF - ROM (unpaged)
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// $0400-$3FFF - ROM mapper slot 0
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// $4000-$7FFF - ROM mapper slot 1
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// $8000-$BFFF - ROM mapper slot 2 - OR - SaveRAM
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// $C000-$DFFF - System RAM
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// $E000-$FFFF - System RAM (mirror)
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// $FFFC - SaveRAM mapper control
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// $FFFD - Mapper slot 0 control
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// $FFFE - Mapper slot 1 control
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// $FFFF - Mapper slot 2 control
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const ushort BankSizeMask = 0x3FFF;
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const ushort RamSizeMask = 0x1FFF;
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bool BiosMapped { get { return (Port3E & 0x40) == 0x40; } }
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byte ReadMemorySega(ushort address)
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{
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byte ret = 0xFF;
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if (address < 0xC000)
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{
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if ((Port3E & 0x48) == 0x48) // cart and bios disabled, return empty bus
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ret = 0xFF;
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else if (BiosMapped && BiosRom != null)
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{
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if (BiosRom.Length == 0x2000)
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{
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ret = BiosRom[address & 0x1FFF];
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}
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else
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{
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// korean BIOS (and a couple of rarer BIOses) use memory slot 2 mechanics as needed
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if (address < 0x8000)
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{
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return BiosRom[address];
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}
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else
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{
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switch (SaveRamBank)
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{
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case 0: ret = BiosRom[(Bios_bank * BankSize) + (address & BankSizeMask)]; break;
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case 1: if (SaveRAM != null) ret = SaveRAM[(address & BankSizeMask) % SaveRAM.Length]; break;
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case 2: if (SaveRAM != null) ret = SaveRAM[(BankSize + (address & BankSizeMask)) % SaveRAM.Length]; break;
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default:
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ret = SystemRam[address & RamSizeMask];
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break;
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}
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}
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}
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}
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else if (address < 1024)
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ret = RomData[address];
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else if (address < 0x4000)
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ret = RomData[(RomBank0 * BankSize) + address];
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else if (address < 0x8000)
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ret = RomData[(RomBank1 * BankSize) + (address & BankSizeMask)];
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else
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{
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switch (SaveRamBank)
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{
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case 0: ret = RomData[(RomBank2 * BankSize) + (address & BankSizeMask)]; break;
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case 1: if (SaveRAM != null) ret = SaveRAM[(address & BankSizeMask) % SaveRAM.Length]; break;
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case 2: if (SaveRAM != null) ret = SaveRAM[(BankSize + (address & BankSizeMask)) % SaveRAM.Length]; break;
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default:
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ret = SystemRam[address & RamSizeMask];
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break;
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}
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}
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}
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else
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{
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ret = SystemRam[address & RamSizeMask];
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}
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return ret;
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}
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CDLog_MapResults MapMemorySega(ushort address, bool write)
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{
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if (address < 0xC000)
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{
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if ((Port3E & 0x48) == 0x48) // cart and bios disabled, return empty bus
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return new CDLog_MapResults();
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else if (BiosMapped && BiosRom != null)
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return new CDLog_MapResults(); //bios tracking of CDL is not supported
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else if (address < 1024)
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
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else if (address < 0x4000)
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank0 * BankSize) + address };
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else if (address < 0x8000)
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * BankSize) + (address & BankSizeMask) };
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else
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{
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switch (SaveRamBank)
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{
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case 0: return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
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case 1:
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if (SaveRAM != null) return new CDLog_MapResults() { Type = CDLog_AddrType.SaveRAM, Address = (address & BankSizeMask) % SaveRAM.Length };
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else return new CDLog_MapResults();
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case 2:
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if (SaveRAM != null) return new CDLog_MapResults() { Type = CDLog_AddrType.SaveRAM, Address = (BankSize + (address & BankSizeMask)) & BankSizeMask };
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else return new CDLog_MapResults();
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default:
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return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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}
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}
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else
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{
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return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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}
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void WriteMemorySega(ushort address, byte value)
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{
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if (address >= 0xC000)
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SystemRam[address & RamSizeMask] = value;
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else if (address >= 0x8000)
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{
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if (SaveRAM != null)
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{
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SaveRamModified = true;
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switch (SaveRamBank)
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{
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case 1: SaveRAM[(address & BankSizeMask) % SaveRAM.Length] = value; return;
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case 2: SaveRAM[(BankSize + (address & BankSizeMask)) % SaveRAM.Length] = value; return;
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}
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}
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else System.Console.WriteLine("Game attempt to use SRAM but SRAM not present");
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}
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if (address >= 0xFFFC)
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{
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if (address == 0xFFFC)
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{
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if ((value & 8) != 0)
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SaveRamBank = (byte)((value & 4) == 0 ? 1 : 2); // SaveRAM selected
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else
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SaveRamBank = 0; // ROM bank selected
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}
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else if (address == 0xFFFD) RomBank0 = (byte)(value % RomBanks);
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else if (address == 0xFFFE) RomBank1 = (byte)(value % RomBanks);
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else if (address == 0xFFFF)
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{
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if (BiosMapped)
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{
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Bios_bank = (byte)value;
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}
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else
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{
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RomBank2 = (byte)(value % RomBanks);
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}
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}
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return;
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}
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}
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void InitSegaMapper()
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{
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ReadMemoryMapper = ReadMemorySega;
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WriteMemoryMapper = WriteMemorySega;
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MapMemory = MapMemorySega;
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WriteMemorySega(0xFFFC, 0);
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WriteMemorySega(0xFFFD, 0);
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WriteMemorySega(0xFFFE, 1);
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WriteMemorySega(0xFFFF, 2);
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Bios_bank = 2;
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}
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// Mapper when loading a BIOS as a ROM (simulating no cart loaded)
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byte ReadMemoryBIOS(ushort address)
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{
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if ((Port3E & 0x08) != 0 && address < 0xC000)
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return 0xFF;
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if (address < 1024)
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return RomData[address];
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if (address < 0x4000)
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return RomData[(RomBank0 * BankSize) + address];
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if (address < 0x8000)
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return RomData[(RomBank1 * BankSize) + (address & BankSizeMask)];
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if (address < 0xC000)
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return RomData[(RomBank2 * BankSize) + (address & BankSizeMask)];
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return SystemRam[address & RamSizeMask];
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}
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void WriteMemoryBIOS(ushort address, byte value)
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{
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if (address >= 0xC000)
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SystemRam[address & RamSizeMask] = value;
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if (address >= 0xFFFC)
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{
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if (address == 0xFFFD) RomBank0 = (byte)(value % RomBanks);
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else if (address == 0xFFFE) RomBank1 = (byte)(value % RomBanks);
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else if (address == 0xFFFF) RomBank2 = (byte)(value % RomBanks);
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return;
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}
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}
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void InitBiosMapper()
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{
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ReadMemoryMapper = ReadMemoryBIOS;
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WriteMemoryMapper = WriteMemoryBIOS;
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WriteMemorySega(0xFFFC, 0);
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WriteMemorySega(0xFFFD, 0);
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WriteMemorySega(0xFFFE, 1);
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WriteMemorySega(0xFFFF, 2);
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}
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}
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} |