292 lines
7.0 KiB
C#
292 lines
7.0 KiB
C#
using System;
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using System.IO;
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using System.Diagnostics;
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namespace BizHawk.Emulation.Consoles.Nintendo
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{
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//AKA mapper 19 + 210
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//210 lacks the sound and nametable control
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//I'm not sure why bootgod turned all of these into mapper 19..
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//some of them (example: family circuit) cannot work on mapper 19 because it clobbers nametable[0]
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//luckily, we work by board
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public class NAMCOT_m19_m210 : NES.NESBoardBase
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{
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//configuration
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int prg_bank_mask_8k;
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int chr_bank_mask_1k;
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//state
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IntBuffer prg_banks_8k = new IntBuffer(4);
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IntBuffer chr_banks_1k = new IntBuffer(8);
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IntBuffer nt_banks_1k = new IntBuffer(4);
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bool[] vram_enable = new bool[2];
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int irq_counter;
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bool irq_enabled;
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int irq_cycles;
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bool irq_pending;
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public override void Dispose()
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{
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base.Dispose();
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prg_banks_8k.Dispose();
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chr_banks_1k.Dispose();
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nt_banks_1k.Dispose();
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}
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public override void SyncState(Serializer ser)
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{
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base.SyncState(ser);
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ser.Sync("prg_banks_8k", ref prg_banks_8k);
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ser.Sync("chr_banks_1k", ref chr_banks_1k);
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ser.Sync("nt_banks_1k", ref nt_banks_1k);
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for(int i=0;i<2;i++) ser.Sync("vram_enable_" + i, ref vram_enable[i]);
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ser.Sync("irq_counter", ref irq_counter);
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ser.Sync("irq_enabled", ref irq_enabled);
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ser.Sync("irq_cycles", ref irq_cycles);
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ser.Sync("irq_pending", ref irq_pending);
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}
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public override bool Configure(NES.EDetectionOrigin origin)
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{
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switch (Cart.board_type)
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{
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case "MAPPER019":
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break;
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case "MAPPER210":
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break;
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//mapper 19:
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case "NAMCOT-163":
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//final lap
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//battle fleet
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//dragon ninja
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//famista '90
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//hydelide 3 *this is a good test of more advanced features
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Cart.vram_size = 8; //not many test cases of this, but hydelide 3 needs it.
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AssertPrg(128,256); AssertChr(128,256); AssertVram(8); AssertWram(0,8);
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break;
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//mapper 210:
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case "NAMCOT-175":
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//wagyan land 2
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//splatter house
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AssertPrg(128,256); AssertChr(128); AssertVram(0); AssertWram(0);
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break;
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case "NAMCOT-340":
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//family circuit '91
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//dream master
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//famista '92
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AssertPrg(128,256,512); AssertChr(128,256); AssertVram(0); AssertWram(0,8);
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break;
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default:
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return false;
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}
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prg_bank_mask_8k = Cart.prg_size / 8 - 1;
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chr_bank_mask_1k = Cart.chr_size / 1 - 1;
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prg_banks_8k[3] = (byte)(0xFF & prg_bank_mask_8k);
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nt_banks_1k[0] = nt_banks_1k[2] = 0xFF;
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nt_banks_1k[1] = nt_banks_1k[3] = 0xFF;
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return true;
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}
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public override byte ReadEXP(int addr)
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{
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addr &= 0xF800;
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switch (addr)
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{
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case 0x1000:
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return (byte)(irq_counter & 0xFF);
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case 0x1800:
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return (byte)((irq_counter >> 8) | (irq_enabled ? 0x8000 : 0));
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}
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return base.ReadEXP(addr);
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}
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public override void WriteEXP(int addr, byte value)
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{
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addr &= 0xF800;
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switch (addr)
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{
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case 0x0800:
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//sound data port. not used.
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break;
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case 0x1000:
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irq_counter = (irq_counter & 0xFF00) | value;
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irq_pending = false;
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SyncIRQ();
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break;
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case 0x1800:
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{
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irq_counter = (irq_counter & 0x00FF) | (((value & 0x7F) << 8));
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bool last_enabled = irq_enabled;
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irq_enabled = value.Bit(7);
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irq_pending = false;
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if (irq_enabled && !last_enabled)
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{
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irq_cycles = 3;
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}
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SyncIRQ();
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break;
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}
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}
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}
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public override void WritePRG(int addr, byte value)
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{
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addr &= 0xF800;
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switch (addr)
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{
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case 0x0000: chr_banks_1k[0] = value & chr_bank_mask_1k; break;
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case 0x0800: chr_banks_1k[1] = value & chr_bank_mask_1k; break;
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case 0x1000: chr_banks_1k[2] = value & chr_bank_mask_1k; break;
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case 0x1800: chr_banks_1k[3] = value & chr_bank_mask_1k; break;
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case 0x2000: chr_banks_1k[4] = value & chr_bank_mask_1k; break;
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case 0x2800: chr_banks_1k[5] = value & chr_bank_mask_1k; break;
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case 0x3000: chr_banks_1k[6] = value & chr_bank_mask_1k; break;
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case 0x3800: chr_banks_1k[7] = value & chr_bank_mask_1k; break;
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case 0x4000: //$C000
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nt_banks_1k[0] = value;
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break;
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case 0x4800: //$C800
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nt_banks_1k[1] = value;
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break;
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case 0x5000: //$D000
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nt_banks_1k[2] = value;
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break;
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case 0x5800: //$D800
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nt_banks_1k[3] = value;
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break;
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case 0x6000: //$E000
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prg_banks_8k[0] = (value & 0x3F) & prg_bank_mask_8k;
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break;
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case 0x6800: //$E800
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prg_banks_8k[1] = (value & 0x3F) & prg_bank_mask_8k;
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vram_enable[0] = !value.Bit(6);
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vram_enable[1] = !value.Bit(7);
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break;
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case 0x7000: //$F000
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prg_banks_8k[2] = (value & 0x3F) & prg_bank_mask_8k;
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break;
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}
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}
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public override byte ReadPRG(int addr)
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{
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int bank_8k = addr >> 13;
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int ofs = addr & ((1 << 13) - 1);
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bank_8k = prg_banks_8k[bank_8k];
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addr = (bank_8k << 13) | ofs;
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return ROM[addr];
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}
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public override void WritePPU(int addr, byte value)
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{
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if (addr < 0x2000)
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{
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//hydelide 3 is the first game i found that tests this
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VRAM[addr] = value;
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}
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else
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{
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addr -= 0x2000;
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int bank_1k = addr >> 10;
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int ofs = addr & ((1 << 10) - 1);
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bank_1k = nt_banks_1k[bank_1k];
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if (bank_1k >= 0xE0)
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{
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int which_nt = bank_1k & 1;
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NES.CIRAM[which_nt * 0x400 + ofs] = value;
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}
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else
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{
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//throw new InvalidOperationException("what? the nametable was mapped to rom..");
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base.WritePPU(addr + 0x2000, value);
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}
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}
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}
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public override byte ReadPPU(int addr)
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{
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if (addr < 0x2000)
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{
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int bank_1k = addr >> 10;
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int ofs = addr & ((1 << 10) - 1);
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bank_1k = chr_banks_1k[bank_1k];
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if (bank_1k >= 0xE0)
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{
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//chr ram handling
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int side = addr >> 12;
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if (vram_enable[side])
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{
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bank_1k -= 0xE0;
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bank_1k &= 7; //??
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return VRAM[bank_1k * 0x400 + ofs];
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}
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}
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addr = (bank_1k << 10) | ofs;
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return VROM[addr];
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}
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else
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{
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addr -= 0x2000;
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int bank_1k = addr >> 10;
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if (bank_1k > 3) return base.ReadPPU(addr); //namco classic 2 tests this at the title screen
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int ofs = addr & ((1 << 10) - 1);
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bank_1k = nt_banks_1k[bank_1k];
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if (bank_1k >= 0xE0)
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{
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int which_nt = bank_1k & 1;
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return NES.CIRAM[which_nt * 0x400 + ofs];
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}
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else
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{
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int chr_bank_1k = bank_1k;
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return VROM[chr_bank_1k * 0x400 + ofs];
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}
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}
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}
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void SyncIRQ()
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{
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NES.irq_cart = (irq_pending && irq_enabled);
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}
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void TriggerIRQ()
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{
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//NES.LogLine("trigger irq");
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irq_pending = true;
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SyncIRQ();
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}
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void ClockIRQ()
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{
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if (irq_counter == 0x7FFF)
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{
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//irq_counter = 0;
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TriggerIRQ();
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}
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else irq_counter++;
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}
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public override void ClockPPU()
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{
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if (!irq_enabled) return;
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irq_cycles--;
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if (irq_cycles == 0)
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{
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irq_cycles += 3;
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ClockIRQ();
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}
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}
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}
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} |