1131 lines
29 KiB
C++
1131 lines
29 KiB
C++
/* V810 Emulator
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*
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* Copyright (C) 2006 David Tucker
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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// Macro test taken from http://gcc.gnu.org/viewcvs/trunk/gcc/testsuite/gcc.dg/20020919-1.c?view=markup&pathrev=142696
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//#if defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) || defined (__POWERPC__) || defined (PPC) || defined (_IBMR2)
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// register v810_timestamp_t timestamp_rl asm("15") = v810_timestamp;
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//#elif defined(__x86_64__)
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// register v810_timestamp_t timestamp_rl asm("r11") = v810_timestamp;
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//#else
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register v810_timestamp_t timestamp_rl = v810_timestamp;
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//#endif
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uint32 opcode;
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uint32 tmp2;
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int val = 0;
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#define ADDCLOCK(__n) { timestamp += __n; }
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#define CHECK_HALTED(); { if(Halted && timestamp < next_event_ts) { timestamp = next_event_ts; } }
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while(Running)
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{
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#ifdef RB_DEBUGMODE
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uint32 old_PC = RB_GETPC();
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#endif
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uint32 tmpop;
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assert(timestamp_rl <= next_event_ts);
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if(!IPendingCache)
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{
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if(Halted)
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{
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timestamp_rl = next_event_ts;
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}
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else if(in_bstr)
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{
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tmpop = in_bstr_to;
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opcode = tmpop >> 9;
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goto op_BSTR;
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}
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}
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while(timestamp_rl < next_event_ts)
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{
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#ifdef RB_DEBUGMODE
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old_PC = RB_GETPC();
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#endif
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P_REG[0] = 0; //Zero the Zero Reg!!!
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RB_CPUHOOK(RB_GETPC());
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{
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//printf("%08x\n", RB_GETPC());
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{
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v810_timestamp_t timestamp = timestamp_rl;
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tmpop = RB_RDOP(0, 0);
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timestamp_rl = timestamp;
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}
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opcode = (tmpop >> 9) | IPendingCache;
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//printf("%02x\n", opcode >> 1);
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#if HAVE_COMPUTED_GOTO
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#define CGBEGIN static const void *const op_goto_table[256] = {
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#define CGE(l) &&l,
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#define CGEND }; goto *op_goto_table[opcode];
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#else
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/* (uint8) cast for cheaper alternative to generated branch+compare bounds check instructions, but still more
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expensive than computed goto which needs no masking nor bounds checking.
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*/
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#define CGBEGIN { enum { CGESB = 1 + __COUNTER__ }; switch((uint8)opcode) {
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#define CGE(l) case __COUNTER__ - CGESB: goto l;
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#define CGEND } }
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#endif
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CGBEGIN
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CGE(op_MOV) CGE(op_MOV) CGE(op_ADD) CGE(op_ADD) CGE(op_SUB) CGE(op_SUB) CGE(op_CMP) CGE(op_CMP)
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CGE(op_SHL) CGE(op_SHL) CGE(op_SHR) CGE(op_SHR) CGE(op_JMP) CGE(op_JMP) CGE(op_SAR) CGE(op_SAR)
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CGE(op_MUL) CGE(op_MUL) CGE(op_DIV) CGE(op_DIV) CGE(op_MULU) CGE(op_MULU) CGE(op_DIVU) CGE(op_DIVU)
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CGE(op_OR) CGE(op_OR) CGE(op_AND) CGE(op_AND) CGE(op_XOR) CGE(op_XOR) CGE(op_NOT) CGE(op_NOT)
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CGE(op_MOV_I) CGE(op_MOV_I) CGE(op_ADD_I) CGE(op_ADD_I) CGE(op_SETF) CGE(op_SETF) CGE(op_CMP_I) CGE(op_CMP_I)
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CGE(op_SHL_I) CGE(op_SHL_I) CGE(op_SHR_I) CGE(op_SHR_I) CGE(op_EI) CGE(op_EI) CGE(op_SAR_I) CGE(op_SAR_I)
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CGE(op_TRAP) CGE(op_TRAP) CGE(op_RETI) CGE(op_RETI) CGE(op_HALT) CGE(op_HALT) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_LDSR) CGE(op_LDSR) CGE(op_STSR) CGE(op_STSR) CGE(op_DI) CGE(op_DI) CGE(op_BSTR) CGE(op_BSTR)
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CGE(op_BV) CGE(op_BL) CGE(op_BE) CGE(op_BNH) CGE(op_BN) CGE(op_BR) CGE(op_BLT) CGE(op_BLE)
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CGE(op_BNV) CGE(op_BNL) CGE(op_BNE) CGE(op_BH) CGE(op_BP) CGE(op_NOP) CGE(op_BGE) CGE(op_BGT)
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CGE(op_MOVEA) CGE(op_MOVEA) CGE(op_ADDI) CGE(op_ADDI) CGE(op_JR) CGE(op_JR) CGE(op_JAL) CGE(op_JAL)
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CGE(op_ORI) CGE(op_ORI) CGE(op_ANDI) CGE(op_ANDI) CGE(op_XORI) CGE(op_XORI) CGE(op_MOVHI) CGE(op_MOVHI)
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CGE(op_LD_B) CGE(op_LD_B) CGE(op_LD_H) CGE(op_LD_H) CGE(op_INVALID) CGE(op_INVALID) CGE(op_LD_W) CGE(op_LD_W)
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CGE(op_ST_B) CGE(op_ST_B) CGE(op_ST_H) CGE(op_ST_H) CGE(op_INVALID) CGE(op_INVALID) CGE(op_ST_W) CGE(op_ST_W)
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CGE(op_IN_B) CGE(op_IN_B) CGE(op_IN_H) CGE(op_IN_H) CGE(op_CAXI) CGE(op_CAXI) CGE(op_IN_W) CGE(op_IN_W)
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CGE(op_OUT_B) CGE(op_OUT_B) CGE(op_OUT_H) CGE(op_OUT_H) CGE(op_FPP) CGE(op_FPP) CGE(op_OUT_W) CGE(op_OUT_W)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID)
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CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INVALID) CGE(op_INT_HANDLER)
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CGEND
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// Bit string subopcodes
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#define DO_AM_BSTR() \
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const uint32 arg1 = (tmpop >> 5) & 0x1F; \
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const uint32 arg2 = (tmpop & 0x1F); \
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RB_INCPCBY2();
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#define DO_AM_FPP() \
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const uint32 arg1 = (tmpop >> 5) & 0x1F; \
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const uint32 arg2 = (tmpop & 0x1F); \
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const uint32 arg3 = ((RB_RDOP(2) >> 10)&0x3F); \
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RB_INCPCBY4();
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#define DO_AM_UDEF() \
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RB_INCPCBY2();
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#define DO_AM_I() \
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const uint32 arg1 = tmpop & 0x1F; \
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const uint32 arg2 = (tmpop >> 5) & 0x1F; \
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RB_INCPCBY2();
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#define DO_AM_II() DO_AM_I();
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#define DO_AM_IV() \
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const uint32 arg1 = ((tmpop & 0x000003FF) << 16) | RB_RDOP(2); \
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#define DO_AM_V() \
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const uint32 arg3 = (tmpop >> 5) & 0x1F; \
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const uint32 arg2 = tmpop & 0x1F; \
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const uint32 arg1 = RB_RDOP(2); \
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RB_INCPCBY4();
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#define DO_AM_VIa() \
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const uint32 arg1 = RB_RDOP(2); \
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const uint32 arg2 = tmpop & 0x1F; \
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const uint32 arg3 = (tmpop >> 5) & 0x1F; \
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RB_INCPCBY4(); \
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#define DO_AM_VIb() \
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const uint32 arg1 = (tmpop >> 5) & 0x1F; \
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const uint32 arg2 = RB_RDOP(2); \
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const uint32 arg3 = (tmpop & 0x1F); \
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RB_INCPCBY4(); \
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#define DO_AM_IX() \
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const uint32 arg1 = (tmpop & 0x1); \
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RB_INCPCBY2(); \
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#define DO_AM_III() \
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const uint32 arg1 = tmpop & 0x1FE;
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#include "v810_do_am.h"
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#define BEGIN_OP(meowtmpop) { op_##meowtmpop: v810_timestamp_t timestamp = timestamp_rl; DO_##meowtmpop ##_AM();
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#define END_OP() timestamp_rl = timestamp; goto OpFinished; }
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#define END_OP_SKIPLO() timestamp_rl = timestamp; goto OpFinishedSkipLO; }
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BEGIN_OP(MOV);
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ADDCLOCK(1);
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SetPREG(arg2, P_REG[arg1]);
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END_OP();
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BEGIN_OP(ADD);
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ADDCLOCK(1);
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uint32 temp = P_REG[arg2] + P_REG[arg1];
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SetFlag(PSW_OV, ((P_REG[arg2]^(~P_REG[arg1]))&(P_REG[arg2]^temp))&0x80000000);
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SetFlag(PSW_CY, temp < P_REG[arg2]);
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SetPREG(arg2, temp);
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SetSZ(P_REG[arg2]);
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END_OP();
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BEGIN_OP(SUB);
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ADDCLOCK(1);
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uint32 temp = P_REG[arg2] - P_REG[arg1];
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SetFlag(PSW_OV, ((P_REG[arg2]^P_REG[arg1])&(P_REG[arg2]^temp))&0x80000000);
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SetFlag(PSW_CY, temp > P_REG[arg2]);
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SetPREG(arg2, temp);
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SetSZ(P_REG[arg2]);
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END_OP();
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BEGIN_OP(CMP);
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ADDCLOCK(1);
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uint32 temp = P_REG[arg2] - P_REG[arg1];
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SetSZ(temp);
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SetFlag(PSW_OV, ((P_REG[arg2]^P_REG[arg1])&(P_REG[arg2]^temp))&0x80000000);
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SetFlag(PSW_CY, temp > P_REG[arg2]);
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END_OP();
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BEGIN_OP(SHL);
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ADDCLOCK(1);
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val = P_REG[arg1] & 0x1F;
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// set CY before we destroy the regisrer info....
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SetFlag(PSW_CY, (val != 0) && ((P_REG[arg2] >> (32 - val))&0x01) );
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SetFlag(PSW_OV, FALSE);
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SetPREG(arg2, P_REG[arg2] << val);
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SetSZ(P_REG[arg2]);
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END_OP();
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BEGIN_OP(SHR);
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ADDCLOCK(1);
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val = P_REG[arg1] & 0x1F;
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// set CY before we destroy the regisrer info....
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SetFlag(PSW_CY, (val) && ((P_REG[arg2] >> (val-1))&0x01));
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SetFlag(PSW_OV, FALSE);
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SetPREG(arg2, P_REG[arg2] >> val);
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SetSZ(P_REG[arg2]);
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END_OP();
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BEGIN_OP(JMP);
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(void)arg2; // arg2 is unused.
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ADDCLOCK(3);
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RB_SETPC((P_REG[arg1] & 0xFFFFFFFE));
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if(RB_AccurateMode)
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{
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BRANCH_ALIGN_CHECK(PC);
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}
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RB_ADDBT(old_PC, RB_GETPC(), 0);
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END_OP();
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BEGIN_OP(SAR);
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ADDCLOCK(1);
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val = P_REG[arg1] & 0x1F;
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SetFlag(PSW_CY, (val) && ((P_REG[arg2]>>(val-1))&0x01) );
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SetFlag(PSW_OV, FALSE);
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SetPREG(arg2, (uint32) ((int32)P_REG[arg2] >> val));
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SetSZ(P_REG[arg2]);
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END_OP();
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BEGIN_OP(OR);
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ADDCLOCK(1);
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SetPREG(arg2, P_REG[arg1] | P_REG[arg2]);
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SetFlag(PSW_OV, FALSE);
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SetSZ(P_REG[arg2]);
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END_OP();
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BEGIN_OP(AND);
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ADDCLOCK(1);
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SetPREG(arg2, P_REG[arg1] & P_REG[arg2]);
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SetFlag(PSW_OV, FALSE);
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SetSZ(P_REG[arg2]);
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END_OP();
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BEGIN_OP(XOR);
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ADDCLOCK(1);
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SetPREG(arg2, P_REG[arg1] ^ P_REG[arg2]);
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SetFlag(PSW_OV, FALSE);
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SetSZ(P_REG[arg2]);
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END_OP();
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BEGIN_OP(NOT);
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ADDCLOCK(1);
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SetPREG(arg2, ~P_REG[arg1]);
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SetFlag(PSW_OV, FALSE);
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SetSZ(P_REG[arg2]);
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END_OP();
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BEGIN_OP(MOV_I);
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ADDCLOCK(1);
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SetPREG(arg2,sign_5(arg1));
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END_OP();
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BEGIN_OP(ADD_I);
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ADDCLOCK(1);
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uint32 temp = P_REG[arg2] + sign_5(arg1);
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SetFlag(PSW_OV, ((P_REG[arg2]^(~sign_5(arg1)))&(P_REG[arg2]^temp))&0x80000000);
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SetFlag(PSW_CY, (uint32)temp < P_REG[arg2]);
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SetPREG(arg2, (uint32)temp);
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SetSZ(P_REG[arg2]);
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END_OP();
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BEGIN_OP(SETF);
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ADDCLOCK(1);
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P_REG[arg2] = 0;
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switch (arg1 & 0x0F)
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{
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case COND_V:
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if (TESTCOND_V) P_REG[arg2] = 1;
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break;
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case COND_C:
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if (TESTCOND_C) P_REG[arg2] = 1;
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break;
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case COND_Z:
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if (TESTCOND_Z) P_REG[arg2] = 1;
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break;
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case COND_NH:
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if (TESTCOND_NH) P_REG[arg2] = 1;
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break;
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case COND_S:
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if (TESTCOND_S) P_REG[arg2] = 1;
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break;
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case COND_T:
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P_REG[arg2] = 1;
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break;
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case COND_LT:
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if (TESTCOND_LT) P_REG[arg2] = 1;
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break;
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case COND_LE:
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if (TESTCOND_LE) P_REG[arg2] = 1;
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break;
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case COND_NV:
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if (TESTCOND_NV) P_REG[arg2] = 1;
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break;
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case COND_NC:
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if (TESTCOND_NC) P_REG[arg2] = 1;
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break;
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case COND_NZ:
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if (TESTCOND_NZ) P_REG[arg2] = 1;
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break;
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case COND_H:
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if (TESTCOND_H) P_REG[arg2] = 1;
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break;
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case COND_NS:
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if (TESTCOND_NS) P_REG[arg2] = 1;
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break;
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case COND_F:
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//always false! do nothing more
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break;
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case COND_GE:
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if (TESTCOND_GE) P_REG[arg2] = 1;
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break;
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case COND_GT:
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if (TESTCOND_GT) P_REG[arg2] = 1;
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break;
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}
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END_OP();
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BEGIN_OP(CMP_I);
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ADDCLOCK(1);
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uint32 temp = P_REG[arg2] - sign_5(arg1);
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SetSZ(temp);
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SetFlag(PSW_OV, ((P_REG[arg2]^(sign_5(arg1)))&(P_REG[arg2]^temp))&0x80000000);
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SetFlag(PSW_CY, temp > P_REG[arg2]);
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END_OP();
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BEGIN_OP(SHR_I);
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ADDCLOCK(1);
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SetFlag(PSW_CY, arg1 && ((P_REG[arg2] >> (arg1-1))&0x01) );
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// set CY before we destroy the regisrer info....
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SetPREG(arg2, P_REG[arg2] >> arg1);
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SetFlag(PSW_OV, FALSE);
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SetSZ(P_REG[arg2]);
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END_OP();
|
|
|
|
BEGIN_OP(SHL_I);
|
|
ADDCLOCK(1);
|
|
SetFlag(PSW_CY, arg1 && ((P_REG[arg2] >> (32 - arg1))&0x01) );
|
|
// set CY before we destroy the regisrer info....
|
|
|
|
SetPREG(arg2, P_REG[arg2] << arg1);
|
|
SetFlag(PSW_OV, FALSE);
|
|
SetSZ(P_REG[arg2]);
|
|
END_OP();
|
|
|
|
BEGIN_OP(SAR_I);
|
|
ADDCLOCK(1);
|
|
SetFlag(PSW_CY, arg1 && ((P_REG[arg2]>>(arg1-1))&0x01) );
|
|
|
|
SetPREG(arg2, (uint32) ((int32)P_REG[arg2] >> arg1));
|
|
|
|
SetFlag(PSW_OV, FALSE);
|
|
SetSZ(P_REG[arg2]);
|
|
END_OP();
|
|
|
|
BEGIN_OP(LDSR); // Loads a Sys Reg with the value in specified PR
|
|
ADDCLOCK(1); // ?
|
|
|
|
SetSREG(timestamp, arg1 & 0x1F, P_REG[arg2 & 0x1F]);
|
|
END_OP();
|
|
|
|
BEGIN_OP(STSR); // Loads a PR with the value in specified Sys Reg
|
|
ADDCLOCK(1); // ?
|
|
P_REG[arg2 & 0x1F] = GetSREG(arg1 & 0x1F);
|
|
END_OP();
|
|
|
|
BEGIN_OP(EI);
|
|
(void)arg1; // arg1 is unused.
|
|
(void)arg2; // arg2 is unused.
|
|
|
|
if(VBMode)
|
|
{
|
|
ADDCLOCK(1);
|
|
S_REG[PSW] = S_REG[PSW] &~ PSW_ID;
|
|
RecalcIPendingCache();
|
|
}
|
|
else
|
|
{
|
|
ADDCLOCK(1);
|
|
RB_DECPCBY2();
|
|
Exception(INVALID_OP_HANDLER_ADDR, ECODE_INVALID_OP);
|
|
CHECK_HALTED();
|
|
}
|
|
END_OP();
|
|
|
|
BEGIN_OP(DI);
|
|
(void)arg1; // arg1 is unused.
|
|
(void)arg2; // arg2 is unused.
|
|
|
|
if(VBMode)
|
|
{
|
|
ADDCLOCK(1);
|
|
S_REG[PSW] |= PSW_ID;
|
|
IPendingCache = 0;
|
|
}
|
|
else
|
|
{
|
|
ADDCLOCK(1);
|
|
RB_DECPCBY2();
|
|
Exception(INVALID_OP_HANDLER_ADDR, ECODE_INVALID_OP);
|
|
CHECK_HALTED();
|
|
}
|
|
END_OP();
|
|
|
|
|
|
#define COND_BRANCH(cond) \
|
|
if(cond) \
|
|
{ \
|
|
ADDCLOCK(3); \
|
|
RB_PCRELCHANGE(sign_9(arg1) & 0xFFFFFFFE); \
|
|
if(RB_AccurateMode) \
|
|
{ \
|
|
BRANCH_ALIGN_CHECK(PC); \
|
|
} \
|
|
RB_ADDBT(old_PC, RB_GETPC(), 0); \
|
|
} \
|
|
else \
|
|
{ \
|
|
ADDCLOCK(1); \
|
|
RB_INCPCBY2(); \
|
|
}
|
|
|
|
BEGIN_OP(BV);
|
|
COND_BRANCH(TESTCOND_V);
|
|
END_OP();
|
|
|
|
|
|
BEGIN_OP(BL);
|
|
COND_BRANCH(TESTCOND_L);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BE);
|
|
COND_BRANCH(TESTCOND_E);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BNH);
|
|
COND_BRANCH(TESTCOND_NH);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BN);
|
|
COND_BRANCH(TESTCOND_N);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BR);
|
|
COND_BRANCH(TRUE);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BLT);
|
|
COND_BRANCH(TESTCOND_LT);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BLE);
|
|
COND_BRANCH(TESTCOND_LE);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BNV);
|
|
COND_BRANCH(TESTCOND_NV);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BNL);
|
|
COND_BRANCH(TESTCOND_NL);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BNE);
|
|
COND_BRANCH(TESTCOND_NE);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BH);
|
|
COND_BRANCH(TESTCOND_H);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BP);
|
|
COND_BRANCH(TESTCOND_P);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BGE);
|
|
COND_BRANCH(TESTCOND_GE);
|
|
END_OP();
|
|
|
|
BEGIN_OP(BGT);
|
|
COND_BRANCH(TESTCOND_GT);
|
|
END_OP();
|
|
|
|
BEGIN_OP(JR);
|
|
ADDCLOCK(3);
|
|
RB_PCRELCHANGE(sign_26(arg1) & 0xFFFFFFFE);
|
|
if(RB_AccurateMode)
|
|
{
|
|
BRANCH_ALIGN_CHECK(PC);
|
|
}
|
|
RB_ADDBT(old_PC, RB_GETPC(), 0);
|
|
END_OP();
|
|
|
|
BEGIN_OP(JAL);
|
|
ADDCLOCK(3);
|
|
P_REG[31] = RB_GETPC() + 4;
|
|
RB_PCRELCHANGE(sign_26(arg1) & 0xFFFFFFFE);
|
|
if(RB_AccurateMode)
|
|
{
|
|
BRANCH_ALIGN_CHECK(PC);
|
|
}
|
|
RB_ADDBT(old_PC, RB_GETPC(), 0);
|
|
END_OP();
|
|
|
|
BEGIN_OP(MOVEA);
|
|
ADDCLOCK(1);
|
|
SetPREG(arg3, P_REG[arg2] + sign_16(arg1));
|
|
END_OP();
|
|
|
|
BEGIN_OP(ADDI);
|
|
ADDCLOCK(1);
|
|
uint32 temp = P_REG[arg2] + sign_16(arg1);
|
|
|
|
SetFlag(PSW_OV, ((P_REG[arg2]^(~sign_16(arg1)))&(P_REG[arg2]^temp))&0x80000000);
|
|
SetFlag(PSW_CY, (uint32)temp < P_REG[arg2]);
|
|
|
|
SetPREG(arg3, (uint32)temp);
|
|
SetSZ(P_REG[arg3]);
|
|
END_OP();
|
|
|
|
BEGIN_OP(ORI);
|
|
ADDCLOCK(1);
|
|
SetPREG(arg3, arg1 | P_REG[arg2]);
|
|
SetFlag(PSW_OV, FALSE);
|
|
SetSZ(P_REG[arg3]);
|
|
END_OP();
|
|
|
|
BEGIN_OP(ANDI);
|
|
ADDCLOCK(1);
|
|
SetPREG(arg3, (arg1 & P_REG[arg2]));
|
|
SetFlag(PSW_OV, FALSE);
|
|
SetSZ(P_REG[arg3]);
|
|
END_OP();
|
|
|
|
BEGIN_OP(XORI);
|
|
ADDCLOCK(1);
|
|
SetPREG(arg3, arg1 ^ P_REG[arg2]);
|
|
SetFlag(PSW_OV, FALSE);
|
|
SetSZ(P_REG[arg3]);
|
|
END_OP();
|
|
|
|
BEGIN_OP(MOVHI);
|
|
ADDCLOCK(1);
|
|
SetPREG(arg3, (arg1 << 16) + P_REG[arg2]);
|
|
END_OP();
|
|
|
|
// LD.B
|
|
BEGIN_OP(LD_B);
|
|
ADDCLOCK(1);
|
|
tmp2 = (sign_16(arg1)+P_REG[arg2])&0xFFFFFFFF;
|
|
|
|
SetPREG(arg3, sign_8(MemRead8(timestamp, tmp2)));
|
|
|
|
//should be 3 clocks when executed alone, 2 when precedes another LD, or 1
|
|
//when precedes an instruction with many clocks (I'm guessing FP, MUL, DIV, etc)
|
|
if(lastop >= 0)
|
|
{
|
|
if(lastop == LASTOP_LD)
|
|
{
|
|
ADDCLOCK(1);
|
|
}
|
|
else
|
|
{
|
|
ADDCLOCK(2);
|
|
}
|
|
}
|
|
lastop = LASTOP_LD;
|
|
END_OP_SKIPLO();
|
|
|
|
// LD.H
|
|
BEGIN_OP(LD_H);
|
|
ADDCLOCK(1);
|
|
tmp2 = (sign_16(arg1)+P_REG[arg2]) & 0xFFFFFFFE;
|
|
SetPREG(arg3, sign_16(MemRead16(timestamp, tmp2)));
|
|
|
|
if(lastop >= 0)
|
|
{
|
|
if(lastop == LASTOP_LD)
|
|
{
|
|
ADDCLOCK(1);
|
|
}
|
|
else
|
|
{
|
|
ADDCLOCK(2);
|
|
}
|
|
}
|
|
lastop = LASTOP_LD;
|
|
END_OP_SKIPLO();
|
|
|
|
|
|
// LD.W
|
|
BEGIN_OP(LD_W);
|
|
ADDCLOCK(1);
|
|
|
|
tmp2 = (sign_16(arg1)+P_REG[arg2]) & 0xFFFFFFFC;
|
|
|
|
if(MemReadBus32[tmp2 >> 24])
|
|
{
|
|
SetPREG(arg3, MemRead32(timestamp, tmp2));
|
|
|
|
if(lastop >= 0)
|
|
{
|
|
if(lastop == LASTOP_LD)
|
|
{
|
|
ADDCLOCK(1);
|
|
}
|
|
else
|
|
{
|
|
ADDCLOCK(2);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
uint32 rv;
|
|
|
|
rv = MemRead16(timestamp, tmp2);
|
|
rv |= MemRead16(timestamp, tmp2 | 2) << 16;
|
|
|
|
SetPREG(arg3, rv);
|
|
|
|
if(lastop >= 0)
|
|
{
|
|
if(lastop == LASTOP_LD)
|
|
{
|
|
ADDCLOCK(3);
|
|
}
|
|
else
|
|
{
|
|
ADDCLOCK(4);
|
|
}
|
|
}
|
|
}
|
|
lastop = LASTOP_LD;
|
|
END_OP_SKIPLO();
|
|
|
|
// ST.B
|
|
BEGIN_OP(ST_B);
|
|
ADDCLOCK(1);
|
|
MemWrite8(timestamp, sign_16(arg2)+P_REG[arg3], P_REG[arg1] & 0xFF);
|
|
|
|
if(lastop == LASTOP_ST)
|
|
{
|
|
ADDCLOCK(1);
|
|
}
|
|
lastop = LASTOP_ST;
|
|
END_OP_SKIPLO();
|
|
|
|
// ST.H
|
|
BEGIN_OP(ST_H);
|
|
ADDCLOCK(1);
|
|
|
|
MemWrite16(timestamp, (sign_16(arg2)+P_REG[arg3])&0xFFFFFFFE, P_REG[arg1] & 0xFFFF);
|
|
|
|
if(lastop == LASTOP_ST)
|
|
{
|
|
ADDCLOCK(1);
|
|
}
|
|
lastop = LASTOP_ST;
|
|
END_OP_SKIPLO();
|
|
|
|
// ST.W
|
|
BEGIN_OP(ST_W);
|
|
ADDCLOCK(1);
|
|
tmp2 = (sign_16(arg2)+P_REG[arg3]) & 0xFFFFFFFC;
|
|
|
|
if(MemWriteBus32[tmp2 >> 24])
|
|
{
|
|
MemWrite32(timestamp, tmp2, P_REG[arg1]);
|
|
|
|
if(lastop == LASTOP_ST)
|
|
{
|
|
ADDCLOCK(1);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
MemWrite16(timestamp, tmp2, P_REG[arg1] & 0xFFFF);
|
|
MemWrite16(timestamp, tmp2 | 2, P_REG[arg1] >> 16);
|
|
|
|
if(lastop == LASTOP_ST)
|
|
{
|
|
ADDCLOCK(3);
|
|
}
|
|
}
|
|
lastop = LASTOP_ST;
|
|
END_OP_SKIPLO();
|
|
|
|
// IN.B
|
|
BEGIN_OP(IN_B);
|
|
{
|
|
ADDCLOCK(3);
|
|
SetPREG(arg3, IORead8(timestamp, sign_16(arg1)+P_REG[arg2]));
|
|
}
|
|
lastop = LASTOP_IN;
|
|
END_OP_SKIPLO();
|
|
|
|
|
|
// IN.H
|
|
BEGIN_OP(IN_H);
|
|
{
|
|
ADDCLOCK(3);
|
|
SetPREG(arg3, IORead16(timestamp, (sign_16(arg1)+P_REG[arg2]) & 0xFFFFFFFE));
|
|
}
|
|
lastop = LASTOP_IN;
|
|
END_OP_SKIPLO();
|
|
|
|
|
|
// IN.W
|
|
BEGIN_OP(IN_W);
|
|
if(IORead32)
|
|
{
|
|
ADDCLOCK(3);
|
|
SetPREG(arg3, IORead32(timestamp, (sign_16(arg1)+P_REG[arg2]) & 0xFFFFFFFC));
|
|
}
|
|
else
|
|
{
|
|
uint32 eff_addr = (sign_16(arg1) + P_REG[arg2]) & 0xFFFFFFFC;
|
|
uint32 rv;
|
|
|
|
ADDCLOCK(5);
|
|
|
|
rv = IORead16(timestamp, eff_addr);
|
|
rv |= IORead16(timestamp, eff_addr | 2) << 16;
|
|
|
|
SetPREG(arg3, rv);
|
|
}
|
|
lastop = LASTOP_IN;
|
|
END_OP_SKIPLO();
|
|
|
|
|
|
// OUT.B
|
|
BEGIN_OP(OUT_B);
|
|
ADDCLOCK(1);
|
|
IOWrite8(timestamp, sign_16(arg2)+P_REG[arg3],P_REG[arg1]&0xFF);
|
|
|
|
if(lastop == LASTOP_OUT)
|
|
{
|
|
ADDCLOCK(1);
|
|
}
|
|
lastop = LASTOP_OUT;
|
|
END_OP_SKIPLO();
|
|
|
|
|
|
// OUT.H
|
|
BEGIN_OP(OUT_H);
|
|
ADDCLOCK(1);
|
|
IOWrite16(timestamp, (sign_16(arg2)+P_REG[arg3])&0xFFFFFFFE,P_REG[arg1]&0xFFFF);
|
|
|
|
if(lastop == LASTOP_OUT)
|
|
{
|
|
ADDCLOCK(1);
|
|
}
|
|
lastop = LASTOP_OUT;
|
|
END_OP_SKIPLO();
|
|
|
|
|
|
// OUT.W
|
|
BEGIN_OP(OUT_W);
|
|
ADDCLOCK(1);
|
|
|
|
if(IOWrite32)
|
|
IOWrite32(timestamp, (sign_16(arg2)+P_REG[arg3])&0xFFFFFFFC,P_REG[arg1]);
|
|
else
|
|
{
|
|
uint32 eff_addr = (sign_16(arg2)+P_REG[arg3])&0xFFFFFFFC;
|
|
IOWrite16(timestamp, eff_addr, P_REG[arg1] & 0xFFFF);
|
|
IOWrite16(timestamp, eff_addr | 2, P_REG[arg1] >> 16);
|
|
}
|
|
|
|
if(lastop == LASTOP_OUT)
|
|
{
|
|
if(IOWrite32)
|
|
{
|
|
ADDCLOCK(1);
|
|
}
|
|
else
|
|
{
|
|
ADDCLOCK(3);
|
|
}
|
|
}
|
|
lastop = LASTOP_OUT;
|
|
END_OP_SKIPLO();
|
|
|
|
BEGIN_OP(NOP);
|
|
(void)arg1; // arg1 is unused.
|
|
|
|
ADDCLOCK(1);
|
|
RB_INCPCBY2();
|
|
END_OP();
|
|
|
|
BEGIN_OP(RETI);
|
|
(void)arg1; // arg1 is unused.
|
|
|
|
ADDCLOCK(10);
|
|
|
|
//Return from Trap/Interupt
|
|
if(S_REG[PSW] & PSW_NP) { // Read the FE Reg
|
|
RB_SETPC(S_REG[FEPC] & 0xFFFFFFFE);
|
|
S_REG[PSW] = S_REG[FEPSW];
|
|
} else { //Read the EI Reg Interupt
|
|
RB_SETPC(S_REG[EIPC] & 0xFFFFFFFE);
|
|
S_REG[PSW] = S_REG[EIPSW];
|
|
}
|
|
RecalcIPendingCache();
|
|
|
|
RB_ADDBT(old_PC, RB_GETPC(), 0);
|
|
END_OP();
|
|
|
|
BEGIN_OP(MUL);
|
|
ADDCLOCK(13);
|
|
|
|
uint64 temp = (int64)(int32)P_REG[arg1] * (int32)P_REG[arg2];
|
|
|
|
SetPREG(30, (uint32)(temp >> 32));
|
|
SetPREG(arg2, temp);
|
|
SetSZ(P_REG[arg2]);
|
|
SetFlag(PSW_OV, temp != (uint64)(int64)(int32)(uint32)temp);
|
|
lastop = -1;
|
|
END_OP_SKIPLO();
|
|
|
|
BEGIN_OP(MULU);
|
|
ADDCLOCK(13);
|
|
uint64 temp = (uint64)P_REG[arg1] * (uint64)P_REG[arg2];
|
|
|
|
SetPREG(30, (uint32)(temp >> 32));
|
|
SetPREG(arg2, (uint32)temp);
|
|
|
|
SetSZ(P_REG[arg2]);
|
|
SetFlag(PSW_OV, temp != (uint32)temp);
|
|
lastop = -1;
|
|
END_OP_SKIPLO();
|
|
|
|
BEGIN_OP(DIVU);
|
|
ADDCLOCK(36);
|
|
if(P_REG[arg1] == 0) // Divide by zero!
|
|
{
|
|
RB_DECPCBY2();
|
|
Exception(ZERO_DIV_HANDLER_ADDR, ECODE_ZERO_DIV);
|
|
CHECK_HALTED();
|
|
}
|
|
else
|
|
{
|
|
// Careful here, since arg2 can be == 30
|
|
uint32 quotient = (uint32)P_REG[arg2] / (uint32)P_REG[arg1];
|
|
uint32 remainder = (uint32)P_REG[arg2] % (uint32)P_REG[arg1];
|
|
|
|
SetPREG(30, remainder);
|
|
SetPREG(arg2, quotient);
|
|
|
|
SetFlag(PSW_OV, FALSE);
|
|
SetSZ(quotient);
|
|
}
|
|
lastop = -1;
|
|
END_OP_SKIPLO();
|
|
|
|
BEGIN_OP(DIV);
|
|
//if(P_REG[arg1] & P_REG[arg2] & 0x80000000)
|
|
//{
|
|
// printf("Div: %08x %08x\n", P_REG[arg1], P_REG[arg2]);
|
|
//}
|
|
|
|
ADDCLOCK(38);
|
|
if((uint32)P_REG[arg1] == 0) // Divide by zero!
|
|
{
|
|
RB_DECPCBY2();
|
|
Exception(ZERO_DIV_HANDLER_ADDR, ECODE_ZERO_DIV);
|
|
CHECK_HALTED();
|
|
}
|
|
else
|
|
{
|
|
if((P_REG[arg2]==0x80000000)&&(P_REG[arg1]==0xFFFFFFFF))
|
|
{
|
|
SetFlag(PSW_OV, TRUE);
|
|
P_REG[30]=0;
|
|
SetPREG(arg2, 0x80000000);
|
|
SetSZ(P_REG[arg2]);
|
|
}
|
|
else
|
|
{
|
|
// Careful here, since arg2 can be == 30
|
|
uint32 quotient = (int32)P_REG[arg2] / (int32)P_REG[arg1];
|
|
uint32 remainder = (int32)P_REG[arg2] % (int32)P_REG[arg1];
|
|
|
|
SetPREG(30, remainder);
|
|
SetPREG(arg2, quotient);
|
|
|
|
SetFlag(PSW_OV, FALSE);
|
|
SetSZ(quotient);
|
|
}
|
|
}
|
|
lastop = -1;
|
|
END_OP_SKIPLO();
|
|
|
|
BEGIN_OP(FPP);
|
|
ADDCLOCK(1);
|
|
fpu_subop(timestamp, arg3, arg1, arg2);
|
|
lastop = -1;
|
|
CHECK_HALTED();
|
|
END_OP_SKIPLO();
|
|
|
|
BEGIN_OP(BSTR);
|
|
if(!in_bstr)
|
|
{
|
|
ADDCLOCK(1);
|
|
}
|
|
|
|
if(bstr_subop(timestamp, arg2, arg1))
|
|
{
|
|
RB_DECPCBY2();
|
|
in_bstr = TRUE;
|
|
in_bstr_to = tmpop;
|
|
}
|
|
else
|
|
{
|
|
in_bstr = FALSE;
|
|
have_src_cache = have_dst_cache = FALSE;
|
|
}
|
|
END_OP();
|
|
|
|
BEGIN_OP(HALT);
|
|
(void)arg1; // arg1 is unused.
|
|
|
|
ADDCLOCK(1);
|
|
Halted = HALT_HALT;
|
|
//printf("Untested opcode: HALT\n");
|
|
END_OP();
|
|
|
|
BEGIN_OP(TRAP);
|
|
(void)arg2; // arg2 is unused.
|
|
|
|
ADDCLOCK(15);
|
|
|
|
Exception(TRAP_HANDLER_BASE + (arg1 & 0x10), ECODE_TRAP_BASE + (arg1 & 0x1F));
|
|
CHECK_HALTED();
|
|
END_OP();
|
|
|
|
BEGIN_OP(CAXI);
|
|
//printf("Untested opcode: caxi\n");
|
|
|
|
// Lock bus(N/A)
|
|
|
|
ADDCLOCK(26);
|
|
|
|
{
|
|
uint32 addr, tmp, compare_temp;
|
|
uint32 to_write;
|
|
|
|
addr = sign_16(arg1) + P_REG[arg2];
|
|
addr &= ~3;
|
|
|
|
if(MemReadBus32[addr >> 24])
|
|
tmp = MemRead32(timestamp, addr);
|
|
else
|
|
{
|
|
tmp = MemRead16(timestamp, addr);
|
|
tmp |= MemRead16(timestamp, addr | 2) << 16;
|
|
}
|
|
|
|
compare_temp = P_REG[arg3] - tmp;
|
|
|
|
SetSZ(compare_temp);
|
|
SetFlag(PSW_OV, ((P_REG[arg3]^tmp)&(P_REG[arg3]^compare_temp))&0x80000000);
|
|
SetFlag(PSW_CY, compare_temp > P_REG[arg3]);
|
|
|
|
if(!compare_temp) // If they're equal...
|
|
to_write = P_REG[30];
|
|
else
|
|
to_write = tmp;
|
|
|
|
if(MemWriteBus32[addr >> 24])
|
|
MemWrite32(timestamp, addr, to_write);
|
|
else
|
|
{
|
|
MemWrite16(timestamp, addr, to_write & 0xFFFF);
|
|
MemWrite16(timestamp, addr | 2, to_write >> 16);
|
|
}
|
|
P_REG[arg3] = tmp;
|
|
}
|
|
|
|
// Unlock bus(N/A)
|
|
|
|
END_OP();
|
|
|
|
|
|
|
|
op_INT_HANDLER:
|
|
{
|
|
int iNum = ilevel;
|
|
|
|
S_REG[EIPC] = GetPC();
|
|
S_REG[EIPSW] = S_REG[PSW];
|
|
|
|
SetPC(0xFFFFFE00 | (iNum << 4));
|
|
|
|
RB_ADDBT(old_PC, RB_GETPC(), 0xFE00 | (iNum << 4));
|
|
|
|
S_REG[ECR] = 0xFE00 | (iNum << 4);
|
|
|
|
S_REG[PSW] |= PSW_EP;
|
|
S_REG[PSW] |= PSW_ID;
|
|
S_REG[PSW] &= ~PSW_AE;
|
|
|
|
// Now, set need to set the interrupt enable level to he level that is being processed + 1,
|
|
// saturating at 15.
|
|
iNum++;
|
|
|
|
if(iNum > 0x0F)
|
|
iNum = 0x0F;
|
|
|
|
S_REG[PSW] &= ~PSW_IA;
|
|
S_REG[PSW] |= iNum << 16;
|
|
|
|
// Accepting an interrupt takes us out of normal HALT status, of course!
|
|
Halted = HALT_NONE;
|
|
|
|
// Invalidate our bitstring state(forces the instruction to be re-read, and the r/w buffers reloaded).
|
|
in_bstr = FALSE;
|
|
have_src_cache = FALSE;
|
|
have_dst_cache = FALSE;
|
|
|
|
IPendingCache = 0;
|
|
|
|
goto OpFinished;
|
|
}
|
|
|
|
|
|
BEGIN_OP(INVALID);
|
|
RB_DECPCBY2();
|
|
if(!RB_AccurateMode)
|
|
{
|
|
RB_SETPC(RB_GETPC());
|
|
if((uint32)(RB_RDOP(0, 0) >> 9) != opcode)
|
|
{
|
|
//printf("Trampoline: %08x %02x\n", RB_GETPC(), opcode >> 1);
|
|
}
|
|
else
|
|
{
|
|
ADDCLOCK(1);
|
|
Exception(INVALID_OP_HANDLER_ADDR, ECODE_INVALID_OP);
|
|
CHECK_HALTED();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
ADDCLOCK(1);
|
|
Exception(INVALID_OP_HANDLER_ADDR, ECODE_INVALID_OP);
|
|
CHECK_HALTED();
|
|
}
|
|
END_OP();
|
|
|
|
}
|
|
|
|
OpFinished: ;
|
|
lastop = opcode;
|
|
OpFinishedSkipLO: ;
|
|
} // end while(timestamp_rl < next_event_ts)
|
|
next_event_ts = event_handler(timestamp_rl);
|
|
//printf("Next: %d, Cur: %d\n", next_event_ts, timestamp);
|
|
}
|
|
|
|
v810_timestamp = timestamp_rl;
|