666 lines
16 KiB
C#
666 lines
16 KiB
C#
using System;
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using BizHawk.Common;
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using BizHawk.Common.NumberExtensions;
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namespace BizHawk.Emulation.Cores.Nintendo.NES
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{
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public sealed class Mapper090 : NES.NESBoardBase
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{
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ByteBuffer prg_regs = new ByteBuffer(4);
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IntBuffer chr_regs = new IntBuffer(8);
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IntBuffer nt_regs = new IntBuffer(4);
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IntBuffer prg_banks = new IntBuffer(4);
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IntBuffer chr_banks = new IntBuffer(8);
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ByteBuffer ram_bytes = new ByteBuffer(5);
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[MapperProp]
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public bool dipswitch_0;
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[MapperProp]
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public bool dipswitch_1;
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int prg_bank_mask_8k;
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int chr_bank_mask_1k;
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byte prg_mode_select = 0;
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byte chr_mode_select = 0;
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bool sram_prg = false;
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int ram_bank;
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bool mapper_090 = false;
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bool mapper_209 = false;
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bool mapper_211 = false;
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bool nt_advanced_control = false;
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bool nt_ram_disable = false;
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bool nt_ram_select = false;
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bool mirror_chr = false;
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bool chr_block_mode = true;
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int chr_block = 0;
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int prg_block = 0;
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int multiplicator = 0;
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int multiplicand = 0;
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int multiplication_result = 0;
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bool irq_enable = false;
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bool irq_pending = false;
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bool irq_count_down = false;
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bool irq_count_up = false;
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int irq_prescaler_size;
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byte irq_source = 0;
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byte prescaler;
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byte irq_counter;
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byte xor_reg;
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int a12_old;
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public override bool Configure(NES.EDetectionOrigin origin)
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{
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switch (Cart.board_type)
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{
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case "MAPPER090":
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case "UNIF_UNL-TEK90":
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mapper_090 = true;
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nt_advanced_control = false;
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break;
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case "MAPPER209":
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mapper_209 = true;
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break;
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case "MAPPER211":
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nt_advanced_control = true;
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mapper_211 = true;
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break;
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default:
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return false;
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}
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prg_bank_mask_8k = Cart.prg_size / 8 - 1;
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chr_bank_mask_1k = Cart.chr_size - 1;
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InitValues();
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return true;
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}
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public override void NESSoftReset()
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{
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InitValues();
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base.NESSoftReset();
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}
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private void InitValues()
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{
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for (int i = 0; i < 4; i++)
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{
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prg_regs[i] = 0xFF;
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nt_regs[i] = 0;
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}
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for (int i = 0; i < 8; i++)
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{
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chr_regs[i] = 0xFFFF;
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}
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AutoMapperProps.Apply(this);
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Sync();
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}
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public override void SyncState(Serializer ser)
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{
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base.SyncState(ser);
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ser.Sync("prg_regs", ref prg_regs);
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ser.Sync("chr_regs", ref chr_regs);
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ser.Sync("nt_regs", ref nt_regs);
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ser.Sync("prg_banks", ref prg_banks);
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ser.Sync("chr_banks", ref chr_banks);
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ser.Sync("ram_bytes", ref ram_bytes);
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ser.Sync("dipswitch_0", ref dipswitch_0);
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ser.Sync("dipswitch_1", ref dipswitch_1);
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ser.Sync("prg_bank_mask_8k", ref prg_bank_mask_8k);
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ser.Sync("chr_bank_mask_1k", ref chr_bank_mask_1k);
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ser.Sync("prg_mode_select", ref prg_mode_select);
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ser.Sync("chr_mode_select", ref chr_mode_select);
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ser.Sync("sram_prg", ref sram_prg);
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ser.Sync("ram_bank", ref ram_bank);
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ser.Sync("mapper_090", ref mapper_090);
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ser.Sync("mapper_209", ref mapper_209);
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ser.Sync("mapper_211", ref mapper_211);
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ser.Sync("nt_advanced_control", ref nt_advanced_control);
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ser.Sync("nt_ram_disable", ref nt_ram_disable);
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ser.Sync("nt_ram_select", ref nt_ram_select);
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ser.Sync("mirror_chr", ref mirror_chr);
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ser.Sync("chr_block_mode", ref chr_block_mode);
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ser.Sync("chr_block", ref chr_block);
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ser.Sync("prg_block", ref prg_block);
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ser.Sync("multiplicator", ref multiplicator);
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ser.Sync("multiplicand", ref multiplicand);
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ser.Sync("multiplication_result", ref multiplication_result);
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ser.Sync("irq_enable", ref irq_enable);
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ser.Sync("irq_pending", ref irq_pending);
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ser.Sync("irq_count_down", ref irq_count_down);
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ser.Sync("irq_count_up", ref irq_count_up);
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ser.Sync("irq_prescaler_size", ref irq_prescaler_size);
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ser.Sync("irq_source", ref irq_source);
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ser.Sync("prescaler", ref prescaler);
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ser.Sync("irq_counter", ref irq_counter);
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ser.Sync("xor_reg", ref xor_reg);
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ser.Sync("a12_old", ref a12_old);
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Sync();
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}
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public override void Dispose()
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{
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prg_regs.Dispose();
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chr_regs.Dispose();
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nt_regs.Dispose();
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prg_banks.Dispose();
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chr_banks.Dispose();
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ram_bytes.Dispose();
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base.Dispose();
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}
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private void Sync()
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{
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SyncIRQ();
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SyncPRGBanks();
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SyncCHRBanks();
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SyncNametables();
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}
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private void SetBank(IntBuffer target, byte offset, byte size, int value)
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{
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value &= ~(size - 1);
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for (int i = 0; i < size; i++)
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{
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int index = i + offset;
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target[index] = value;
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value++;
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}
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}
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private byte BitRev6(int value)
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{
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int newvalue = 0;
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newvalue |= (value & 0x20) >> 5;
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newvalue |= (value & 0x10) >> 3;
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newvalue |= (value & 0x08) >> 1;
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newvalue |= (value & 0x04) << 1;
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newvalue |= (value & 0x02) << 3;
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newvalue |= (value & 0x01) << 5;
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return (byte)newvalue;
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}
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private void SyncPRGBanks()
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{
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int bankmode = prg_block << 6;
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switch(prg_mode_select)
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{
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case 0:
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SetBank(prg_banks, 0, 4, ( bankmode | (prg_bank_mask_8k & 0x3F) ));
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ram_bank = bankmode | (((prg_regs[3] << 2) + 3) & 0x3F);
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break;
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case 1:
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SetBank(prg_banks, 0, 2, ( bankmode | (prg_regs[1] & 0x1F) ));
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SetBank(prg_banks, 2, 2, ( bankmode | (prg_bank_mask_8k & 0x3F) ));
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ram_bank = bankmode | (((prg_regs[3] << 1) + 1) & 0x3F);
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break;
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case 2:
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SetBank(prg_banks, 0, 1, ( bankmode | prg_regs[0] ));
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SetBank(prg_banks, 1, 1, ( bankmode | prg_regs[1] ));
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SetBank(prg_banks, 2, 1, ( bankmode | prg_regs[2] ));
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SetBank(prg_banks, 3, 1, ( bankmode | (prg_bank_mask_8k & 0x3F) ));
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ram_bank = bankmode | prg_regs[3];
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break;
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case 3:
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SetBank(prg_banks, 0, 1, ( bankmode | BitRev6(prg_regs[0]) ));
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SetBank(prg_banks, 1, 1, ( bankmode | BitRev6(prg_regs[1]) ));
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SetBank(prg_banks, 2, 1, ( bankmode | BitRev6(prg_regs[2]) ));
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SetBank(prg_banks, 3, 1, ( bankmode | (prg_bank_mask_8k & 0x3F) ));
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ram_bank = bankmode | BitRev6(prg_regs[3]);
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break;
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case 4:
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SetBank(prg_banks, 0, 4, ( bankmode | (prg_regs[3] & 0x3F) ));
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ram_bank = bankmode | (((prg_regs[3] << 2) + 3) & 0x3F);
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break;
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case 5:
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SetBank(prg_banks, 0, 2, ( bankmode | (prg_regs[1] & 0x1F) ));
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SetBank(prg_banks, 2, 2, ( bankmode | (prg_regs[3] & 0x1F) ));
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ram_bank = bankmode | (((prg_regs[3] << 1) + 1) & 0x3F);
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break;
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case 6:
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SetBank(prg_banks, 0, 1, ( bankmode | prg_regs[0] ));
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SetBank(prg_banks, 1, 1, ( bankmode | prg_regs[1] ));
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SetBank(prg_banks, 2, 1, ( bankmode | prg_regs[2] ));
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SetBank(prg_banks, 3, 1, ( bankmode | prg_regs[3] ));
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ram_bank = bankmode | prg_regs[3];
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break;
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case 7:
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SetBank(prg_banks, 0, 1, ( bankmode | BitRev6(prg_regs[0]) ));
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SetBank(prg_banks, 1, 1, ( bankmode | BitRev6(prg_regs[1]) ));
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SetBank(prg_banks, 2, 1, ( bankmode | BitRev6(prg_regs[2]) ));
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SetBank(prg_banks, 3, 1, ( bankmode | BitRev6(prg_regs[3]) ));
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ram_bank = bankmode | BitRev6(prg_regs[3]);
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break;
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}
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}
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private void SyncCHRBanks()
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{
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int mask = 0xFFFF;
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int block = 0;
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if (chr_block_mode)
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{
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mask = 0xFF >> (chr_mode_select ^ 3);
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block = chr_block << (chr_mode_select + 5);
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}
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int mirror_chr_9002 = mirror_chr ? 0 : 2;
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int mirror_chr_9003 = mirror_chr ? 1 : 3;
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switch (chr_mode_select)
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{
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case 0:
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SetBank(chr_banks, 0, 8, ((chr_regs[0] & mask) | block) << 3);
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break;
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case 1:
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SetBank(chr_banks, 0, 4, ((chr_regs[0] & mask) | block) << 2);
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SetBank(chr_banks, 4, 4, ((chr_regs[4] & mask) | block) << 2);
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break;
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case 2:
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SetBank(chr_banks, 0, 2, ((chr_regs[0] & mask) | block) << 1);
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SetBank(chr_banks, 2, 2, ((chr_regs[mirror_chr_9002] & mask) | block) << 1);
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SetBank(chr_banks, 4, 2, ((chr_regs[4] & mask) | block) << 1);
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SetBank(chr_banks, 6, 2, ((chr_regs[6] & mask) | block) << 1);
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break;
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case 3:
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SetBank(chr_banks, 0, 1, (chr_regs[0] & mask) | block);
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SetBank(chr_banks, 1, 1, (chr_regs[1] & mask) | block);
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SetBank(chr_banks, 2, 1, (chr_regs[mirror_chr_9002] & mask) | block);
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SetBank(chr_banks, 3, 1, (chr_regs[mirror_chr_9003] & mask) | block);
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SetBank(chr_banks, 4, 1, (chr_regs[4] & mask) | block);
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SetBank(chr_banks, 5, 1, (chr_regs[5] & mask) | block);
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SetBank(chr_banks, 6, 1, (chr_regs[6] & mask) | block);
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SetBank(chr_banks, 7, 1, (chr_regs[7] & mask) | block);
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break;
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}
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}
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private void SyncNametables()
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{
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if (nt_advanced_control)
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{
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int[] m = new int[4];
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for (var i = 0; i < 4; i++)
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{
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m[i] = nt_regs[i] & 0x01;
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}
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SetMirroring(m[0], m[1], m[2], m[3]);
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}
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}
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public override void WritePRG(int addr, byte value)
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{
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switch (addr & 0x7007)
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{
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case 0x0000: //0x8000: PRG ROM select
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case 0x0001:
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case 0x0002:
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case 0x0003:
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case 0x0004:
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case 0x0005:
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case 0x0006:
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case 0x0007:
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prg_regs[addr & 3] = (byte)(value & 0x3F);
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SyncPRGBanks();
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break;
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case 0x1000: //0x9000: CHR ROM lower 8 bits select
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case 0x1001:
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case 0x1002:
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case 0x1003:
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case 0x1004:
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case 0x1005:
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case 0x1006:
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case 0x1007:
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chr_regs[addr & 7] &= 0xff00;
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chr_regs[addr & 7] |= value;
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SyncCHRBanks();
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break;
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case 0x2000: //0xA000: CHR ROM upper 8 bits select
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case 0x2001:
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case 0x2002:
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case 0x2003:
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case 0x2004:
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case 0x2005:
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case 0x2006:
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case 0x2007:
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chr_regs[addr & 7] &= 0x00ff;
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chr_regs[addr & 7] |= (value << 8);
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SyncCHRBanks();
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break;
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case 0x3000: //0xB000 Nametable Regs
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case 0x3001:
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case 0x3002:
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case 0x3003:
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nt_regs[addr & 3] &= 0xff00;
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nt_regs[addr & 3] |= value;
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SyncNametables();
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break;
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case 0x3004:
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case 0x3005:
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case 0x3006:
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case 0x3007:
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nt_regs[addr & 3] &= 0x00ff;
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nt_regs[addr & 3] |= (value << 8);
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SyncNametables();
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break;
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case 0x4000: //0xC000 IRQ operation
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if (value.Bit(0))
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{
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goto case 0x4003;
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}
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else
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{
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goto case 0x4002;
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}
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case 0x4001: //IRQ control
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irq_count_down = value.Bit(7);
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irq_count_up = value.Bit(6);
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//Bit 3 enables IRQ prescaler adjusting at 0xC007.
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irq_prescaler_size = value.Bit(2) ? 8 : 256;
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//TODO: Mode 4 (CPU reads) not implemented. No game actually seems to use it, however.
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irq_source = (byte)(value & 0x03);
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break;
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case 0x4002: //IRQ acknowledge and disable
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irq_pending = false;
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irq_enable = false;
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SyncIRQ();
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break;
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case 0x4003: //IRQ enable
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irq_enable = true;
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SyncIRQ();
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break;
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case 0x4004: //Prescaler
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prescaler = (byte)(value ^ xor_reg);
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break;
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case 0x4005: //IRQ_Counter
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irq_counter = (byte)(value ^ xor_reg);
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break;
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case 0x4006: //XOR Reg
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xor_reg = value;
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break;
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case 0x4007: //IRQ prescaler adjust
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//Poorly understood, and no games actually appear to use it.
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//We therefore forego emulating it.
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break;
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case 0x5000: //0xD000 Mapper Banking Control and Mirroring
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case 0x5004:
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//Only Mapper 209 can set this. It is always clear for Mapper 90 and always set for Mapper 211
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if (mapper_209)
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{
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nt_advanced_control = value.Bit(5);
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}
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nt_ram_disable = value.Bit(6);
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prg_mode_select = (byte)(value & 0x07);
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chr_mode_select = (byte)((value >> 3) & 0x03);
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sram_prg = value.Bit(7);
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SyncPRGBanks();
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SyncCHRBanks();
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SyncNametables();
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break;
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case 0x5001: //0xD001: Mirroring
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case 0x5005:
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switch (value & 0x3)
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{
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case 0:
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SetMirrorType(EMirrorType.Vertical);
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break;
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case 1:
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SetMirrorType(EMirrorType.Horizontal);
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break;
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case 2:
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SetMirrorType(EMirrorType.OneScreenA);
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break;
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case 3:
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SetMirrorType(EMirrorType.OneScreenB);
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break;
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}
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break;
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case 0x5002:
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case 0x5006:
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nt_ram_select = value.Bit(7);
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SyncNametables();
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break;
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case 0x5003:
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case 0x5007:
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mirror_chr = value.Bit(7);
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chr_block_mode = !value.Bit(5);
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chr_block = ((value & 0x18) >> 2) | (value & 0x1);
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prg_block = (value & 0x06) >> 1;
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SyncPRGBanks();
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SyncCHRBanks();
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break;
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}
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}
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public override byte ReadPRG(int addr)
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{
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int offset = addr & 0x1FFF;
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int bank = prg_banks[addr >> 13];
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bank &= prg_bank_mask_8k;
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return ROM[bank << 13 | offset];
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}
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public override byte ReadWRAM(int addr)
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{
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return sram_prg ? ROM[ram_bank << 13 | addr & 0x1FFF] : base.ReadWRAM(addr);
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}
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public override byte ReadEXP(int addr)
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{
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switch (addr & 0x1807)
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{
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case 0x1000:
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int value = dipswitch_0 ? 0x80 : 0x00;
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value = dipswitch_1 ? value | 0x40 : value;
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return (byte)(value | (NES.DB & 0x3F));
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case 0x1800:
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return (byte)multiplication_result;
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case 0x1801:
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return (byte)(multiplication_result >> 8);
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case 0x1803:
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case 0x1804:
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case 0x1805:
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case 0x1806:
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case 0x1807:
|
|
return ram_bytes[addr - 0x1803];
|
|
default:
|
|
return base.ReadEXP(addr);
|
|
}
|
|
}
|
|
|
|
public override void WriteEXP(int addr, byte value)
|
|
{
|
|
switch (addr)
|
|
{
|
|
case 0x1800:
|
|
multiplicator = value;
|
|
multiplication_result = multiplicator * multiplicand;
|
|
break;
|
|
case 0x1801:
|
|
multiplicand = value;
|
|
multiplication_result = multiplicator * multiplicand;
|
|
break;
|
|
case 0x1803: //It's not known if 0x1804 - 0x1807 are actually RAM. For safety, we'll assume it is.
|
|
case 0x1804:
|
|
case 0x1805:
|
|
case 0x1806:
|
|
case 0x1807:
|
|
ram_bytes[addr - 0x1803] = value;
|
|
break;
|
|
}
|
|
}
|
|
|
|
public override void ClockCPU()
|
|
{
|
|
if (irq_source == 0)
|
|
{
|
|
ClockIRQ();
|
|
}
|
|
}
|
|
|
|
public void ClockIRQ()
|
|
{
|
|
int mask = irq_prescaler_size - 1;
|
|
|
|
if (irq_count_up && !irq_count_down)
|
|
{
|
|
prescaler++;
|
|
if((prescaler & mask) == 0)
|
|
{
|
|
irq_counter++;
|
|
if(irq_counter == 0)
|
|
{
|
|
irq_pending = irq_enable;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (irq_count_down && !irq_count_up)
|
|
{
|
|
prescaler--;
|
|
if((prescaler & mask) == mask)
|
|
{
|
|
irq_counter--;
|
|
if(irq_counter == 0xFF)
|
|
{
|
|
irq_pending = irq_enable;
|
|
}
|
|
}
|
|
}
|
|
|
|
SyncIRQ();
|
|
}
|
|
|
|
public void SyncIRQ()
|
|
{
|
|
SyncIRQ(irq_pending);
|
|
}
|
|
|
|
public override void AddressPPU(int addr)
|
|
{
|
|
int a12 = (addr >> 12) & 1;
|
|
bool rising_edge = (a12 == 1 && a12_old == 0);
|
|
|
|
if (rising_edge && irq_source == 1)
|
|
{
|
|
ClockIRQ();
|
|
}
|
|
|
|
a12_old = a12;
|
|
}
|
|
|
|
public override byte PeekPPU(int addr)
|
|
{
|
|
if (addr < 0x2000) //Read CHR
|
|
{
|
|
int bank = chr_banks[addr >> 10];
|
|
bank &= chr_bank_mask_1k;
|
|
int offset = addr & 0x3FF;
|
|
|
|
return VROM[bank << 10 | offset];
|
|
}
|
|
|
|
if (nt_advanced_control) //Read from Nametables
|
|
{
|
|
addr -= 0x2000;
|
|
int nt = nt_regs[addr >> 10];
|
|
int offset = addr & 0x3FF;
|
|
|
|
if (!nt_ram_disable)
|
|
{
|
|
if(nt.Bit(7) == nt_ram_select)
|
|
{
|
|
return nt.Bit(0) ? NES.CIRAM[0x400 | offset] : NES.CIRAM[offset];
|
|
}
|
|
}
|
|
|
|
return VROM[nt << 10 | offset];
|
|
}
|
|
else
|
|
{
|
|
return base.PeekPPU(addr);
|
|
}
|
|
}
|
|
|
|
public override byte ReadPPU(int addr)
|
|
{
|
|
if (irq_source == 2)
|
|
{
|
|
ClockIRQ(); //No game ever should use this.
|
|
}
|
|
|
|
if (addr < 0x2000) //Read CHR
|
|
{
|
|
int bank = chr_banks[addr >> 10];
|
|
bank &= chr_bank_mask_1k;
|
|
int offset = addr & 0x3FF;
|
|
|
|
return VROM[bank << 10 | offset];
|
|
}
|
|
|
|
if (nt_advanced_control) //Read from Nametables
|
|
{
|
|
addr -= 0x2000;
|
|
int nt = nt_regs[addr >> 10];
|
|
int offset = addr & 0x3FF;
|
|
|
|
if (!nt_ram_disable)
|
|
{
|
|
if(nt.Bit(7) == nt_ram_select)
|
|
{
|
|
return nt.Bit(0) ? NES.CIRAM[0x400 | offset] : NES.CIRAM[offset];
|
|
}
|
|
}
|
|
|
|
return VROM[nt << 10 | offset];
|
|
}
|
|
else
|
|
{
|
|
return base.ReadPPU(addr);
|
|
}
|
|
}
|
|
}
|
|
}
|