173 lines
4.4 KiB
C#
173 lines
4.4 KiB
C#
using System;
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using BizHawk.Common;
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namespace BizHawk.Emulation.Cores.Nintendo.NES
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{
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//generally mapper2
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//Mega Man
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//Castlevania
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//Contra
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//Duck Tales
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//Metal Gear
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//TODO - look for a mirror=H UNROM--maybe there are none? this may be fixed to the board type.
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// why are there no bus conflicts in here???????
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[NES.INESBoardImplPriority]
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public sealed class UxROM : NES.NESBoardBase
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{
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//configuration
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int prg_mask;
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int vram_byte_mask;
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Func<int, int> adjust_prg;
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//state
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int prg;
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//the VS actually does have 2 KB of nametable address space
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//let's make the extra space here, instead of in the main NES to avoid confusion
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byte[] CIRAM_VS = new byte[0x800];
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public override bool Configure(NES.EDetectionOrigin origin)
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{
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adjust_prg = (x) => x;
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//configure
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switch (Cart.board_type)
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{
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case "MAPPER0002-00":
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//probably a mistake.
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//but (for chrram): "Use of $00 with no CHR ROM implies that the game is wired to map nametable memory in CHR space. The value $00 MUST NOT be used if a mapper isn't defined to allow this. "
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//well, i'm not going to do that now. we'll save it for when it's needed
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//"it's only mapper 218 and no other mappers"
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//so, dont assume this
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//Cart.vram_size = 8;
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break;
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case "MAPPER002":
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AssertChr(0); Cart.vram_size = 8;
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break;
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case "NES-UNROM": //mega man
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case "HVC-UNROM":
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case "KONAMI-UNROM":
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case "NES-UNEPROM": // proto
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case "IREM-UNROM":
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case "TAITO-UNROM":
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AssertPrg(128); AssertChr(0); AssertVram(8);
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//AssertWram(0); //JJ - Tobidase Daisakusen Part 2 (J) includes WRAM
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break;
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case "HVC-UN1ROM":
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AssertPrg(128); AssertChr(0); AssertWram(0); AssertVram(8);
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adjust_prg = (x) => ((x >> 2) & 7);
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break;
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case "NES-UOROM": //paperboy 2
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case "HVC-UOROM":
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case "JALECO-JF-15":
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case "JALECO-JF-18":
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AssertPrg(256); AssertChr(0); AssertVram(8); AssertWram(0);
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break;
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case "NES-UNROM_VS":
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//update the state of the dip switches
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//this is only done at power on
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NES.VS_dips[0] = (byte)(NES.SyncSettings.VSDipswitches.Dip_Switch_1 ? 1 : 0);
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NES.VS_dips[1] = (byte)(NES.SyncSettings.VSDipswitches.Dip_Switch_2 ? 1 : 0);
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NES.VS_dips[2] = (byte)(NES.SyncSettings.VSDipswitches.Dip_Switch_3 ? 1 : 0);
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NES.VS_dips[3] = (byte)(NES.SyncSettings.VSDipswitches.Dip_Switch_4 ? 1 : 0);
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NES.VS_dips[4] = (byte)(NES.SyncSettings.VSDipswitches.Dip_Switch_5 ? 1 : 0);
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NES.VS_dips[5] = (byte)(NES.SyncSettings.VSDipswitches.Dip_Switch_6 ? 1 : 0);
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NES.VS_dips[6] = (byte)(NES.SyncSettings.VSDipswitches.Dip_Switch_7 ? 1 : 0);
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NES.VS_dips[7] = (byte)(NES.SyncSettings.VSDipswitches.Dip_Switch_8 ? 1 : 0);
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NES._isVS = true;
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break;
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default:
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return false;
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}
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//these boards always have 8KB of VRAM
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vram_byte_mask = (Cart.vram_size*1024) - 1;
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prg_mask = (Cart.prg_size / 16) - 1;
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SetMirrorType(Cart.pad_h, Cart.pad_v);
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return true;
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}
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public override byte ReadPRG(int addr)
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{
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int block = addr >> 14;
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int page = block == 1 ? prg_mask : prg;
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int ofs = addr & 0x3FFF;
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return ROM[(page << 14) | ofs];
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}
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public override void WritePRG(int addr, byte value)
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{
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prg = adjust_prg(value) & prg_mask;
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}
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public override byte ReadPPU(int addr)
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{
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if (addr < 0x2000)
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{
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return VRAM[addr & vram_byte_mask];
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}
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else
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{
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if (NES._isVS)
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{
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addr = addr - 0x2000;
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if (addr < 0x800)
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{
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return NES.CIRAM[addr];
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}
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else
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{
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return CIRAM_VS[addr - 0x800];
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}
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}
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else
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return base.ReadPPU(addr);
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}
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}
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public override void WritePPU(int addr, byte value)
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{
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if (addr < 0x2000)
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{
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VRAM[addr & vram_byte_mask] = value;
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}
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else if (NES._isVS)
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{
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// The game VS Castlevania apparently scans for more CIRAM then actually exists, so we have to mask out nonsensical values
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addr &= 0x2FFF;
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addr = addr - 0x2000;
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if (addr < 0x800)
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{
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NES.CIRAM[addr] = value;
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}
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else
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{
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CIRAM_VS[addr - 0x800] = value;
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}
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}
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else
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base.WritePPU(addr,value);
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}
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public override void SyncState(Serializer ser)
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{
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base.SyncState(ser);
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ser.Sync("prg", ref prg);
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if (NES.IsVS)
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{
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ser.Sync("VS_CIRAM", ref CIRAM_VS, false);
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}
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}
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}
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}
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