625 lines
16 KiB
C#
625 lines
16 KiB
C#
using System;
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using System.Globalization;
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using System.IO;
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using BizHawk.Common;
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using BizHawk.Emulation.Common;
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using BizHawk.Common.NumberExtensions;
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// GameBoy CPU (Sharp LR35902)
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namespace BizHawk.Emulation.Cores.Components.LR35902
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{
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public sealed partial class LR35902
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{
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// operations that can take place in an instruction
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public const ushort IDLE = 0;
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public const ushort OP = 1;
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public const ushort RD = 2;
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public const ushort WR = 3;
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public const ushort TR = 4;
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public const ushort ADD16 = 5;
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public const ushort ADD8 = 6;
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public const ushort SUB8 = 7;
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public const ushort ADC8 = 8;
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public const ushort SBC8 = 9;
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public const ushort INC16 = 10;
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public const ushort INC8 = 11;
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public const ushort DEC16 = 12;
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public const ushort DEC8 = 13;
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public const ushort RLC = 14;
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public const ushort RL = 15;
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public const ushort RRC = 16;
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public const ushort RR = 17;
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public const ushort CPL = 18;
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public const ushort DA = 19;
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public const ushort SCF = 20;
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public const ushort CCF = 21;
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public const ushort AND8 = 22;
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public const ushort XOR8 = 23;
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public const ushort OR8 = 24;
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public const ushort CP8 = 25;
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public const ushort SLA = 26;
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public const ushort SRA = 27;
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public const ushort SRL = 28;
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public const ushort SWAP = 29;
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public const ushort BIT = 30;
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public const ushort RES = 31;
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public const ushort SET = 32;
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public const ushort EI = 33;
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public const ushort DI = 34;
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public const ushort HALT = 35;
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public const ushort STOP = 36;
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public const ushort PREFIX = 37;
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public const ushort ASGN = 38;
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public const ushort ADDS = 39; // signed 16 bit operation used in 2 instructions
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public const ushort OP_G = 40; // glitchy opcode read performed by halt when interrupts disabled
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public const ushort JAM = 41; // all undocumented opcodes jam the machine
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public const ushort RD_F = 42; // special read case to pop value into F
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public const ushort EI_RETI = 43; // reti has no delay in interrupt enable
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public const ushort INT_GET = 44;
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public const ushort HALT_CHK = 45; // when in halt mode, actually check I Flag here
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public const ushort IRQ_CLEAR = 46;
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public LR35902()
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{
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Reset();
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}
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public void Reset()
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{
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ResetRegisters();
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ResetInterrupts();
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TotalExecutedCycles = 8;
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stop_check = false;
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cur_instr = new ushort[] { IDLE, IDLE, HALT_CHK, OP };
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}
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// Memory Access
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public Func<ushort, byte> ReadMemory;
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public Action<ushort, byte> WriteMemory;
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public Func<ushort, byte> PeekMemory;
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public Func<ushort, byte> DummyReadMemory;
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// Special Function for Speed switching executed on a STOP
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public Func<int, int> SpeedFunc;
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//this only calls when the first byte of an instruction is fetched.
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public Action<ushort> OnExecFetch;
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public void UnregisterMemoryMapper()
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{
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ReadMemory = null;
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ReadMemory = null;
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PeekMemory = null;
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DummyReadMemory = null;
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}
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public void SetCallbacks
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(
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Func<ushort, byte> ReadMemory,
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Func<ushort, byte> DummyReadMemory,
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Func<ushort, byte> PeekMemory,
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Action<ushort, byte> WriteMemory
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)
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{
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this.ReadMemory = ReadMemory;
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this.DummyReadMemory = DummyReadMemory;
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this.PeekMemory = PeekMemory;
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this.WriteMemory = WriteMemory;
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}
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//a little CDL related stuff
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public delegate void DoCDLCallbackType(ushort addr, LR35902.eCDLogMemFlags flags);
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public DoCDLCallbackType CDLCallback;
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public enum eCDLogMemFlags
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{
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FetchFirst = 1,
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FetchOperand = 2,
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Data = 4,
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Write = 8
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};
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// Execute instructions
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public void ExecuteOne(ref byte interrupt_src, byte interrupt_enable)
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{
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switch (cur_instr[instr_pntr++])
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{
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case IDLE:
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// do nothing
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break;
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case OP:
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// Read the opcode of the next instruction
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if (EI_pending > 0 && !CB_prefix)
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{
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EI_pending--;
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if (EI_pending == 0)
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{
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interrupts_enabled = true;
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}
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}
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if (I_use && interrupts_enabled && !CB_prefix && !jammed)
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{
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interrupts_enabled = false;
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo
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{
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Disassembly = "====IRQ====",
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RegisterInfo = ""
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});
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}
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// call interrupt processor
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// lowest bit set is highest priority
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INTERRUPT_();
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}
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else
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{
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if (OnExecFetch != null) OnExecFetch(RegPC);
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if (TraceCallback != null && !CB_prefix) TraceCallback(State());
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if (CDLCallback != null) CDLCallback(RegPC, eCDLogMemFlags.FetchFirst);
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FetchInstruction(ReadMemory(RegPC++));
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}
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instr_pntr = 0;
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I_use = false;
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break;
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case RD:
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Read_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case WR:
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Write_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case TR:
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TR_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case ADD16:
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ADD16_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case ADD8:
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ADD8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case SUB8:
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SUB8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case ADC8:
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ADC8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case SBC8:
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SBC8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case INC16:
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INC16_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case INC8:
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INC8_Func(cur_instr[instr_pntr++]);
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break;
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case DEC16:
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DEC16_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case DEC8:
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DEC8_Func(cur_instr[instr_pntr++]);
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break;
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case RLC:
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RLC_Func(cur_instr[instr_pntr++]);
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break;
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case RL:
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RL_Func(cur_instr[instr_pntr++]);
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break;
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case RRC:
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RRC_Func(cur_instr[instr_pntr++]);
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break;
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case RR:
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RR_Func(cur_instr[instr_pntr++]);
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break;
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case CPL:
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CPL_Func(cur_instr[instr_pntr++]);
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break;
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case DA:
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DA_Func(cur_instr[instr_pntr++]);
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break;
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case SCF:
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SCF_Func(cur_instr[instr_pntr++]);
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break;
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case CCF:
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CCF_Func(cur_instr[instr_pntr++]);
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break;
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case AND8:
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AND8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case XOR8:
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XOR8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case OR8:
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OR8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case CP8:
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CP8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case SLA:
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SLA_Func(cur_instr[instr_pntr++]);
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break;
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case SRA:
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SRA_Func(cur_instr[instr_pntr++]);
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break;
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case SRL:
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SRL_Func(cur_instr[instr_pntr++]);
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break;
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case SWAP:
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SWAP_Func(cur_instr[instr_pntr++]);
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break;
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case BIT:
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BIT_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case RES:
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RES_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case SET:
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SET_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case EI:
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if (EI_pending == 0) { EI_pending = 2; }
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break;
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case DI:
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interrupts_enabled = false;
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EI_pending = 0;
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break;
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case HALT:
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halted = true;
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bool temp = false;
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if (cur_instr[instr_pntr++] == 1)
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{
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temp = FlagI;
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}
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else
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{
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temp = I_use;
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}
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if (EI_pending > 0 && !CB_prefix)
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{
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EI_pending--;
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if (EI_pending == 0)
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{
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interrupts_enabled = true;
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}
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}
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// if the I flag is asserted at the time of halt, don't halt
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if (temp && interrupts_enabled && !CB_prefix && !jammed)
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{
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interrupts_enabled = false;
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo
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{
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Disassembly = "====IRQ====",
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RegisterInfo = ""
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});
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}
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halted = false;
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if (is_GBC)
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{
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// call the interrupt processor after 4 extra cycles
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if (!Halt_bug_3)
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{
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INTERRUPT_GBC_NOP();
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}
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else
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{
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INTERRUPT_();
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Halt_bug_3 = false;
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//Console.WriteLine("Hit INT");
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}
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}
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else
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{
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// call interrupt processor
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INTERRUPT_();
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Halt_bug_3 = false;
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}
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}
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else if (temp)
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{
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// even if interrupt servicing is disabled, any interrupt flag raised still resumes execution
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo
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{
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Disassembly = "====un-halted====",
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RegisterInfo = ""
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});
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}
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halted = false;
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if (is_GBC)
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{
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// extra 4 cycles for GBC
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if (Halt_bug_3)
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{
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if (OnExecFetch != null) OnExecFetch(RegPC);
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if (TraceCallback != null && !CB_prefix) TraceCallback(State());
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if (CDLCallback != null) CDLCallback(RegPC, eCDLogMemFlags.FetchFirst);
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RegPC++;
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FetchInstruction(ReadMemory(RegPC));
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Halt_bug_3 = false;
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//Console.WriteLine("Hit un");
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}
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else
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{
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cur_instr = new ushort[]
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{IDLE,
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IDLE,
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IDLE,
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OP };
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}
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}
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else
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{
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if (OnExecFetch != null) OnExecFetch(RegPC);
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if (TraceCallback != null && !CB_prefix) TraceCallback(State());
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if (CDLCallback != null) CDLCallback(RegPC, eCDLogMemFlags.FetchFirst);
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if (Halt_bug_3)
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{
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//special variant of halt bug where RegPC also isn't incremented post fetch
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RegPC++;
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FetchInstruction(ReadMemory(RegPC));
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Halt_bug_3 = false;
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}
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else
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{
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FetchInstruction(ReadMemory(RegPC++));
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}
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}
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}
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else
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{
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if (skip_once)
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{
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cur_instr = new ushort[]
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{IDLE,
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IDLE,
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IDLE,
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HALT, 0 };
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skip_once = false;
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}
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else
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{
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if (is_GBC)
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{
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cur_instr = new ushort[]
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{IDLE,
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IDLE,
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HALT_CHK,
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HALT, 0 };
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}
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else
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{
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cur_instr = new ushort[]
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{HALT_CHK,
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IDLE,
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IDLE,
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HALT, 0 };
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}
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}
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}
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I_use = false;
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instr_pntr = 0;
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break;
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case STOP:
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stopped = true;
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if (!stop_check)
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{
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stop_time = SpeedFunc(0);
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stop_check = true;
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}
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if (stop_time > 0)
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{
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stop_time--;
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if (stop_time == 0)
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{
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo
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{
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Disassembly = "====un-stop====",
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RegisterInfo = ""
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});
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}
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stopped = false;
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if (OnExecFetch != null) OnExecFetch(RegPC);
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if (TraceCallback != null && !CB_prefix) TraceCallback(State());
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if (CDLCallback != null) CDLCallback(RegPC, eCDLogMemFlags.FetchFirst);
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FetchInstruction(ReadMemory(RegPC++));
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instr_pntr = 0;
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stop_check = false;
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}
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else
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{
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instr_pntr = 0;
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cur_instr = new ushort[]
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{IDLE,
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IDLE,
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IDLE,
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STOP };
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}
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}
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else if (interrupt_src.Bit(4)) // button pressed, not actually an interrupt though
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{
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo
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{
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Disassembly = "====un-stop====",
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RegisterInfo = ""
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});
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}
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stopped = false;
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if (OnExecFetch != null) OnExecFetch(RegPC);
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if (TraceCallback != null && !CB_prefix) TraceCallback(State());
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if (CDLCallback != null) CDLCallback(RegPC, eCDLogMemFlags.FetchFirst);
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FetchInstruction(ReadMemory(RegPC++));
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instr_pntr = 0;
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stop_check = false;
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}
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else
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{
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instr_pntr = 0;
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cur_instr = new ushort[]
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{IDLE,
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IDLE,
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IDLE,
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STOP };
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}
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break;
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case PREFIX:
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CB_prefix = true;
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break;
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case ASGN:
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ASGN_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case ADDS:
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ADDS_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case OP_G:
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if (OnExecFetch != null) OnExecFetch(RegPC);
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if (TraceCallback != null) TraceCallback(State());
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if (CDLCallback != null) CDLCallback(RegPC, eCDLogMemFlags.FetchFirst);
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FetchInstruction(ReadMemory(RegPC)); // note no increment
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instr_pntr = 0;
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break;
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case JAM:
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jammed = true;
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instr_pntr--;
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break;
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case RD_F:
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Read_Func_F(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case EI_RETI:
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EI_pending = 1;
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break;
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case INT_GET:
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// check if any interrupts got cancelled along the way
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// interrupt src = 5 sets the PC to zero as observed
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// also the triggering interrupt seems like it is held low (i.e. annot trigger I flag) until the interrupt is serviced
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if (interrupt_src.Bit(0) && interrupt_enable.Bit(0)) { int_src = 0; int_clear = 1; }
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else if (interrupt_src.Bit(1) && interrupt_enable.Bit(1)) { int_src = 1; int_clear = 2; }
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else if (interrupt_src.Bit(2) && interrupt_enable.Bit(2)) { int_src = 2; int_clear = 4; }
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else if (interrupt_src.Bit(3) && interrupt_enable.Bit(3)) { int_src = 3; int_clear = 8; }
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else if (interrupt_src.Bit(4) && interrupt_enable.Bit(4)) { int_src = 4; int_clear = 16; }
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else { int_src = 5; int_clear = 0; }
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Regs[cur_instr[instr_pntr++]] = INT_vectors[int_src];
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break;
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case HALT_CHK:
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I_use = FlagI;
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if (Halt_bug_2 && I_use)
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{
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RegPC--;
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Halt_bug_3 = true;
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//Console.WriteLine("Halt_bug_3");
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//Console.WriteLine(TotalExecutedCycles);
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}
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Halt_bug_2 = false;
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break;
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case IRQ_CLEAR:
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if (interrupt_src.Bit(int_src)) { interrupt_src -= int_clear; }
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if ((interrupt_src & interrupt_enable) == 0) { FlagI = false; }
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break;
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}
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TotalExecutedCycles++;
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|
}
|
|
|
|
// tracer stuff
|
|
|
|
public Action<TraceInfo> TraceCallback;
|
|
|
|
public string TraceHeader
|
|
{
|
|
get { return "LR35902: PC, machine code, mnemonic, operands, registers (A, F, B, C, D, E, H, L, SP), Cy, flags (ZNHCI)"; }
|
|
}
|
|
|
|
public TraceInfo State(bool disassemble = true)
|
|
{
|
|
ushort notused;
|
|
|
|
return new TraceInfo
|
|
{
|
|
Disassembly = $"{(disassemble ? Disassemble(RegPC, ReadMemory, out notused) : "---")} ".PadRight(40),
|
|
RegisterInfo = string.Join(" ",
|
|
$"A:{Regs[A]:X2}",
|
|
$"F:{Regs[F]:X2}",
|
|
$"B:{Regs[B]:X2}",
|
|
$"C:{Regs[C]:X2}",
|
|
$"D:{Regs[D]:X2}",
|
|
$"E:{Regs[E]:X2}",
|
|
$"H:{Regs[H]:X2}",
|
|
$"L:{Regs[L]:X2}",
|
|
$"SP:{Regs[SPl] | (Regs[SPh] << 8):X2}",
|
|
$"Cy:{TotalExecutedCycles}",
|
|
$"LY:{LY}",
|
|
string.Concat(
|
|
FlagZ ? "Z" : "z",
|
|
FlagN ? "N" : "n",
|
|
FlagH ? "H" : "h",
|
|
FlagC ? "C" : "c",
|
|
FlagI ? "I" : "i",
|
|
interrupts_enabled ? "E" : "e"))
|
|
};
|
|
}
|
|
// State Save/Load
|
|
|
|
public void SyncState(Serializer ser)
|
|
{
|
|
ser.BeginSection(nameof(LR35902));
|
|
ser.Sync(nameof(Regs), ref Regs, false);
|
|
ser.Sync(nameof(interrupts_enabled), ref interrupts_enabled);
|
|
ser.Sync(nameof(I_use), ref I_use);
|
|
ser.Sync(nameof(skip_once), ref skip_once);
|
|
ser.Sync(nameof(Halt_bug_2), ref Halt_bug_2);
|
|
ser.Sync(nameof(Halt_bug_3), ref Halt_bug_3);
|
|
ser.Sync(nameof(halted), ref halted);
|
|
ser.Sync(nameof(TotalExecutedCycles), ref TotalExecutedCycles);
|
|
ser.Sync(nameof(EI_pending), ref EI_pending);
|
|
ser.Sync(nameof(int_src), ref int_src);
|
|
ser.Sync(nameof(int_clear), ref int_clear);
|
|
ser.Sync(nameof(stop_time), ref stop_time);
|
|
ser.Sync(nameof(stop_check), ref stop_check);
|
|
ser.Sync(nameof(is_GBC), ref is_GBC);
|
|
|
|
ser.Sync(nameof(instr_pntr), ref instr_pntr);
|
|
ser.Sync(nameof(cur_instr), ref cur_instr, false);
|
|
ser.Sync(nameof(CB_prefix), ref CB_prefix);
|
|
ser.Sync(nameof(stopped), ref stopped);
|
|
ser.Sync(nameof(opcode), ref opcode);
|
|
ser.Sync(nameof(jammed), ref jammed);
|
|
ser.Sync(nameof(LY), ref LY);
|
|
ser.Sync(nameof(FlagI), ref FlagI);
|
|
|
|
ser.EndSection();
|
|
}
|
|
}
|
|
} |