455 lines
12 KiB
C#
455 lines
12 KiB
C#
using System;
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namespace BizHawk.Emulation.Common.Components.MC6809
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{
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public partial class MC6809
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{
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public const ushort LEAX = 0;
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public const ushort LEAY = 1;
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public const ushort LEAS = 2;
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public const ushort LEAU = 3;
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public const ushort I_NEG = 4;
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public const ushort I_COM = 5;
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public const ushort I_LSR = 6;
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public const ushort I_ROR = 7;
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public const ushort I_ASR = 8;
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public const ushort I_ASL = 9;
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public const ushort I_ROL = 10;
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public const ushort I_DEC = 11;
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public const ushort I_INC = 12;
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public const ushort I_TST = 13;
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public const ushort I_JMP = 14;
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public const ushort I_CLR = 15;
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public const ushort I_SUB = 16;
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public const ushort I_CMP = 17;
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public const ushort I_SBC = 18;
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public const ushort I_AND = 19;
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public const ushort I_BIT = 20;
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public const ushort I_LD = 21;
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public const ushort I_ST = 22;
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public const ushort I_XOR = 23;
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public const ushort I_ADC = 24;
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public const ushort I_OR = 25;
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public const ushort I_ADD = 26;
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public const ushort I_SUBD = 27;
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public const ushort I_ADDD = 28;
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public const ushort I_CMP16 = 29;
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public const ushort I_JSR = 30;
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public const ushort I_LD16 = 31;
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public const ushort I_ST16 = 32;
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public const ushort I_LD16D = 33;
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public const ushort I_ST16D = 34;
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public const ushort I_CMP16D = 35;
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public ushort indexed_op;
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public ushort indexed_reg;
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public ushort indexed_op_reg;
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public ushort temp;
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private void INDEX_OP(ushort oper)
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{
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indexed_op = oper;
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PopulateCURINSTR(RD_INC_OP, ALU, PC, IDX_DCDE);
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IRQS = -1;
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}
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private void INDEX_OP_REG(ushort oper, ushort src)
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{
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indexed_op = oper;
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indexed_op_reg = src;
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PopulateCURINSTR(RD_INC_OP, ALU, PC, IDX_DCDE);
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IRQS = -1;
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}
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private void INDEX_OP_JMP()
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{
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PopulateCURINSTR(TR, PC, IDX_EA);
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IRQS = 1;
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}
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private void INDEX_OP_JSR()
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{
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PopulateCURINSTR(TR, ADDR, PC,
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DEC16, SP,
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TR, PC, IDX_EA,
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WR_DEC_LO, SP, ADDR,
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WR_HI, SP, ADDR);
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IRQS = 5;
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}
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private void INDEX_OP_LEA(ushort dest)
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{
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PopulateCURINSTR(LEA, dest, IDX_EA,
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IDLE);
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IRQS = 2;
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}
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private void INDEX_OP_LD()
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{
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PopulateCURINSTR(IDLE,
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RD_INC, ALU, IDX_EA,
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RD_INC_OP, ALU2, IDX_EA, LD_16, indexed_op_reg, ALU, ALU2);
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IRQS = 3;
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}
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private void INDEX_OP_ST()
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{
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PopulateCURINSTR(ST_16, indexed_op_reg,
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WR_HI_INC, IDX_EA, indexed_op_reg,
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WR_DEC_LO, IDX_EA, indexed_op_reg);
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IRQS = 3;
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}
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private void INDEX_OP_LDD()
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{
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PopulateCURINSTR(IDLE,
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RD_INC, A, IDX_EA,
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RD_INC_OP, B, IDX_EA, LD_16, ADDR, A, B);
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IRQS = 3;
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}
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private void INDEX_OP_STD()
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{
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PopulateCURINSTR(ST_16, Dr,
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WR_LO_INC, IDX_EA, A,
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WR_DEC_LO, IDX_EA, B);
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IRQS = 3;
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}
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private void INDEX_OP_EX4(ushort oper)
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{
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PopulateCURINSTR(IDLE,
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RD_INC_OP, ALU, IDX_EA, oper, indexed_op_reg, ALU);
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IRQS = 2;
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}
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private void INDEX_OP_EX4_ST()
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{
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PopulateCURINSTR(ST_8, indexed_op_reg,
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WR, IDX_EA, indexed_op_reg);
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IRQS = 2;
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}
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private void INDEX_OP_EX6(ushort oper)
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{
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PopulateCURINSTR(IDLE,
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RD, ALU, IDX_EA,
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oper, ALU,
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WR, IDX_EA, ALU);
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IRQS = 4;
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}
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private void INDEX_OP_EX6D(ushort oper)
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{
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PopulateCURINSTR(IDLE,
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RD_INC, ALU, IDX_EA,
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RD_INC_OP, ALU2, IDX_EA, SET_ADDR, ADDR, ALU, ALU2,
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oper, ADDR);
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IRQS = 4;
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}
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private void INDEX_CMP_EX6(ushort oper)
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{
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PopulateCURINSTR(IDLE,
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RD_INC, ALU, IDX_EA,
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RD_INC_OP, ALU2, IDX_EA, SET_ADDR, ADDR, ALU, ALU2,
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oper, indexed_op_reg, ADDR);
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IRQS = 4;
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}
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// ALU holds the post byte
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public void Index_decode()
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{
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switch ((Regs[ALU] >> 5) & 3)
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{
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case 0: indexed_reg = X; break;
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case 1: indexed_reg = Y; break;
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case 2: indexed_reg = US; break;
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case 3: indexed_reg = SP; break;
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}
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if ((Regs[ALU] & 0x80) == 0)
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{
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temp = (ushort)(Regs[ALU] & 0x1F);
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if ((Regs[ALU] & 0x10) == 0x10)
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{
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temp |= 0xFFE0;
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}
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Regs[IDX_EA] = (ushort)(Regs[indexed_reg] + temp);
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PopulateCURINSTR(IDX_OP_BLD);
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}
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else
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{
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if ((Regs[ALU] & 0x10) == 0x10)
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{
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switch (Regs[ALU] & 0xF)
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{
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case 0x0:
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// Illegal
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break;
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case 0x1:
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Regs[ADDR] = Regs[indexed_reg];
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PopulateCURINSTR(INC16, indexed_reg,
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INC16, indexed_reg,
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RD_INC, ALU, ADDR,
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RD_INC, ALU2, ADDR,
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SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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break;
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case 0x2:
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// Illegal
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break;
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case 0x3:
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Regs[ADDR] = (ushort)(Regs[indexed_reg] - 2);
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PopulateCURINSTR(DEC16, indexed_reg,
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DEC16, indexed_reg,
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RD_INC, ALU, ADDR,
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RD_INC, ALU2, ADDR,
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SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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break;
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case 0x4:
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Regs[ADDR] = Regs[indexed_reg];
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PopulateCURINSTR(RD_INC, ALU, ADDR,
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RD_INC_OP, ALU2, ADDR, SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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break;
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case 0x5:
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Regs[ADDR] = (ushort)(Regs[indexed_reg] + (((Regs[B] & 0x80) == 0x80) ? (Regs[B] | 0xFF00) : Regs[B]));
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PopulateCURINSTR(RD_INC, ALU, ADDR,
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RD_INC, ALU2, ADDR,
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SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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break;
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case 0x6:
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Regs[ADDR] = (ushort)(Regs[indexed_reg] + (((Regs[A] & 0x80) == 0x80) ? (Regs[A] | 0xFF00) : Regs[A]));
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PopulateCURINSTR(RD_INC, ALU, ADDR,
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RD_INC, ALU2, ADDR,
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SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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break;
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case 0x7:
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// Illegal
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break;
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case 0x8:
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Regs[ADDR] = Regs[indexed_reg];
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PopulateCURINSTR(RD_INC_OP, ALU2, PC, ADD8BR, ADDR, ALU2,
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RD_INC, ALU, ADDR,
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RD_INC_OP, ALU2, ADDR, SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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break;
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case 0x9:
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Regs[ADDR] = Regs[indexed_reg];
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PopulateCURINSTR(RD_INC, ALU, PC,
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RD_INC, ALU2, PC,
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SET_ADDR, IDX_EA, ALU, ALU2,
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ADD16BR, ADDR, IDX_EA,
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RD_INC, ALU, ADDR,
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RD_INC_OP, ALU2, ADDR, SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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break;
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case 0xA:
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// Illegal
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break;
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case 0xB:
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Regs[ADDR] = Regs[indexed_reg];
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PopulateCURINSTR(IDLE,
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IDLE,
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SET_ADDR, IDX_EA, A, B,
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ADD16BR, ADDR, IDX_EA,
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RD_INC, ALU, ADDR,
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RD_INC_OP, ALU2, ADDR, SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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break;
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case 0xC:
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indexed_reg = PC;
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Regs[ADDR] = Regs[indexed_reg];
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PopulateCURINSTR(RD_INC_OP, ALU2, PC, ADD8BR, ADDR, ALU2,
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RD_INC, ALU, ADDR,
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RD_INC_OP, ALU2, ADDR, SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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break;
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case 0xD:
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indexed_reg = PC;
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Regs[ADDR] = Regs[indexed_reg];
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PopulateCURINSTR(IDLE,
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RD_INC, ALU, PC,
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RD_INC, ALU2, PC,
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SET_ADDR, IDX_EA, ALU, ALU2,
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ADD16BR, ADDR, IDX_EA,
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RD_INC, ALU, ADDR,
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RD_INC_OP, ALU2, ADDR, SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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break;
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case 0xE:
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// Illegal
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break;
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case 0xF:
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if (((Regs[ALU] >> 5) & 3) == 0)
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{
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PopulateCURINSTR(RD_INC, ALU, PC,
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RD_INC_OP, ALU2, PC, SET_ADDR, ADDR, ALU, ALU2,
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RD_INC, ALU, ADDR,
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RD_INC_OP, ALU2, ADDR, SET_ADDR, IDX_EA, ALU, ALU2,
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IDX_OP_BLD);
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}
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else
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{
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// illegal
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}
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break;
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}
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}
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else
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{
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switch (Regs[ALU] & 0xF)
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{
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case 0x0:
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Regs[IDX_EA] = Regs[indexed_reg];
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PopulateCURINSTR(INC16, indexed_reg,
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IDX_OP_BLD);
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break;
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case 0x1:
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Regs[IDX_EA] = Regs[indexed_reg];
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PopulateCURINSTR(INC16, indexed_reg,
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INC16, indexed_reg,
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IDX_OP_BLD);
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break;
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case 0x2:
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Regs[IDX_EA] = (ushort)(Regs[indexed_reg] - 1);
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PopulateCURINSTR(DEC16, indexed_reg,
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IDX_OP_BLD);
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break;
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case 0x3:
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Regs[IDX_EA] = (ushort)(Regs[indexed_reg] - 2);
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PopulateCURINSTR(DEC16, indexed_reg,
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DEC16, indexed_reg,
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IDX_OP_BLD);
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break;
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case 0x4:
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Regs[IDX_EA] = Regs[indexed_reg];
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Index_Op_Builder();
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return; // need to return here or else we run into the code below invalidating irq_pntr
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break;
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case 0x5:
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Regs[IDX_EA] = (ushort)(Regs[indexed_reg] + (((Regs[B] & 0x80) == 0x80) ? (Regs[B] | 0xFF00) : Regs[B]));
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PopulateCURINSTR(IDX_OP_BLD);
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break;
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case 0x6:
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Regs[IDX_EA] = (ushort)(Regs[indexed_reg] + (((Regs[A] & 0x80) == 0x80) ? (Regs[A] | 0xFF00) : Regs[A]));
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PopulateCURINSTR(IDX_OP_BLD);
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break;
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case 0x7:
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// Illegal
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break;
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case 0x8:
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PopulateCURINSTR(RD_INC_OP, ALU2, PC, EA_8);
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break;
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case 0x9:
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PopulateCURINSTR(RD_INC, ALU, PC,
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RD_INC, ALU2, PC,
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SET_ADDR, ADDR, ALU, ALU2,
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EA_16);
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break;
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case 0xA:
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// Illegal
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break;
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case 0xB:
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PopulateCURINSTR(IDLE,
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IDLE,
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SET_ADDR, ADDR, A, B,
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EA_16);
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break;
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case 0xC:
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indexed_reg = PC;
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PopulateCURINSTR(RD_INC_OP, ALU2, PC, EA_8);
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break;
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case 0xD:
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indexed_reg = PC;
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PopulateCURINSTR(IDLE,
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RD_INC, ALU, PC,
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RD_INC, ALU2, PC,
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SET_ADDR, ADDR, ALU, ALU2,
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EA_16);
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break;
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case 0xE:
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// Illegal
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break;
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case 0xF:
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// Illegal
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break;
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}
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}
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}
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instr_pntr = 0;
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irq_pntr = 100;
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}
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public void Index_Op_Builder()
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{
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switch(indexed_op)
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{
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case LEAX: INDEX_OP_LEA(X); break; // LEAX
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case LEAY: INDEX_OP_LEA(Y); break; // LEAY
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case LEAS: INDEX_OP_LEA(SP); break; // LEAS
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case LEAU: INDEX_OP_LEA(US); break; // LEAU
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case I_NEG: INDEX_OP_EX6(NEG); break; // NEG
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case I_COM: INDEX_OP_EX6(COM); break; // COM
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case I_LSR: INDEX_OP_EX6(LSR); break; // LSR
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case I_ROR: INDEX_OP_EX6(ROR); break; // ROR
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case I_ASR: INDEX_OP_EX6(ASR); break; // ASR
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case I_ASL: INDEX_OP_EX6(ASL); break; // ASL
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case I_ROL: INDEX_OP_EX6(ROL); break; // ROL
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case I_DEC: INDEX_OP_EX6(DEC8); break; // DEC
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case I_INC: INDEX_OP_EX6(INC8); break; // INC
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case I_TST: INDEX_OP_EX6(TST); break; // TST
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case I_JMP: INDEX_OP_JMP(); break; // JMP
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case I_CLR: INDEX_OP_EX6(CLR); break; // CLR
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case I_SUB: INDEX_OP_EX4(SUB8); break; // SUB A,B
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case I_CMP: INDEX_OP_EX4(CMP8); break; // CMP A,B
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case I_SBC: INDEX_OP_EX4(SBC8); break; // SBC A,B
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case I_AND: INDEX_OP_EX4(AND8); break; // AND A,B
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case I_BIT: INDEX_OP_EX4(BIT); break; // BIT A,B
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case I_LD: INDEX_OP_EX4(LD_8); break; // LD A,B
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case I_ST: INDEX_OP_EX4_ST(); break; // ST A,B
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case I_XOR: INDEX_OP_EX4(XOR8); break; // XOR A,B
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case I_ADC: INDEX_OP_EX4(ADC8); break; // ADC A,B
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case I_OR: INDEX_OP_EX4(OR8); break; // OR A,B
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case I_ADD: INDEX_OP_EX4(ADD8); break; // ADD A,B
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case I_SUBD: INDEX_OP_EX6D(SUB16); break; // SUB D
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case I_ADDD: INDEX_OP_EX6D(ADD16); break; // ADD D
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case I_CMP16: INDEX_CMP_EX6(CMP16); break; // CMP X, Y, SP, US
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case I_JSR: INDEX_OP_JSR(); break; // JSR
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case I_LD16: INDEX_OP_LD(); break; // LD X, Y, SP, US
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case I_ST16: INDEX_OP_ST(); break; // ST X, Y, SP, US
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case I_LD16D: INDEX_OP_LDD(); break; // LD D
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case I_ST16D: INDEX_OP_STD(); break; // ST D
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case I_CMP16D: INDEX_OP_EX6D(CMP16D); break; // CMP D
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}
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instr_pntr = 0;
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irq_pntr = -1;
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}
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}
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}
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