378 lines
9.4 KiB
C#
378 lines
9.4 KiB
C#
using BizHawk.Common;
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using BizHawk.Common.NumberExtensions;
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namespace BizHawk.Emulation.Cores.Nintendo.NES
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{
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/*
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I'm breaking FCG boards into 7 main types:
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[1] FCG-1, FCG-2: regs at 6000:7fff.
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FCG-3: regs at 8000:ffff. one of the following at 6000:7fff:
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[2] nothing
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[3] seeprom (1kbit)
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[4] seeprom (2kbit)
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[5] sram (8kbyte) (SEE SIZE NOTES BELOW)
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[6] Datach Joint ROM System: daughterboard setup (DON'T KNOW MUCH ABOUT THIS)
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[7] Non-existant zombie board: regs are at 6000:ffff and 2kbit seeprom is present
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iNES #16 refers to [7], which ends up working correctly for most [1], [2], or [4] games.
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iNES #153 refers to [5], theoretically.
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iNES #157 refers to [6], theoretically.
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iNES #159 refers to [3], theoretically.
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We try to emulate everything but [6] here.
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Size notes:
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chr regs are 8 bit wide and swap 1K at a time, for a max size of 256K chr, always rom.
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prg reg is 4 bit wide and swaps 16K at a time, for a max size of 256K prg.
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[5] is a special case; it has 8K of vram and uses some of the chr banking lines to handle 512K of prgrom.
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I have no idea what [6] does.
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Every real instance of [1], [2], [3], [4] had 128K or 256K of each of chr and prg.
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*/
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public sealed class BANDAI_FCG_1 : NES.NESBoardBase
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{
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//configuration
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int prg_bank_mask_16k, chr_bank_mask_1k;
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bool regs_prg_enable; // can the mapper regs be written to in 8000:ffff?
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bool regs_wram_enable; // can the mapper regs be written to in 6000:7fff?
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bool jump2 = false; // are we in special mode for the JUMP2 board?
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bool vram = false; // is this a VRAM board? (also set to true for JUMP2)
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//regenerable state
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IntBuffer prg_banks_16k = new IntBuffer(2);
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//state
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int prg_reg_16k;
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ByteBuffer regs = new ByteBuffer(8);
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bool irq_enabled;
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ushort irq_counter;
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SEEPROM eprom;
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public DatachBarcode reader;
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public override void SyncState(Serializer ser)
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{
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base.SyncState(ser);
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ser.Sync("prg_reg_16k", ref prg_reg_16k);
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ser.Sync("regs", ref regs);
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ser.Sync("irq_counter", ref irq_counter);
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ser.Sync("irq_enabled", ref irq_enabled);
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if (eprom != null)
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eprom.SyncState(ser);
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if (reader != null)
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reader.SyncState(ser);
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SyncPRG();
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}
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public override void Dispose()
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{
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base.Dispose();
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regs.Dispose();
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prg_banks_16k.Dispose();
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}
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public override bool Configure(NES.EDetectionOrigin origin)
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{
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switch (Cart.board_type)
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{
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// see notes above that explain some of this in more detail
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case "BANDAI-FCG-1": // [1]
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case "BANDAI-FCG-2": // [1]
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case "IREM-FCG-1": // [1] (the extra glue logic is to connect the two chr roms, and doesn't affect emulation)
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AssertPrg(128, 256); AssertChr(128, 256); AssertWram(0); AssertVram(0);
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regs_prg_enable = false;
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regs_wram_enable = true;
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break;
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case "BANDAI-LZ93D50": // [2]
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AssertPrg(128, 256); AssertChr(128, 256); AssertWram(0); AssertVram(0);
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regs_prg_enable = true;
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regs_wram_enable = false;
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break;
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case "BANDAI-LZ93D50+24C01": // [3]
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AssertPrg(128, 256); AssertChr(128, 256); AssertWram(0); AssertVram(0);
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eprom = new SEEPROM(false);
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regs_prg_enable = true;
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regs_wram_enable = false;
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break;
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case "MAPPER159": // [3]
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AssertPrg(128, 256); AssertChr(128, 256);
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Cart.wram_size = 0;
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regs_prg_enable = true;
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regs_wram_enable = false;
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eprom = new SEEPROM(false);
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break;
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case "BANDAI-LZ93D50+24C02": // [4]
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AssertPrg(128, 256); AssertChr(128, 256); AssertWram(0); AssertVram(0);
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eprom = new SEEPROM(true);
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regs_prg_enable = true;
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regs_wram_enable = false;
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break;
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case "MAPPER016": // [7]
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if (Cart.prg_size > 256)
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{
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// you have two options:
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// 1) assume prg > 256 => jump2 (aka mapper 153, type [5])
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// this will break hypothetical prg oversize hacks
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// 2) assume prg > 256 => oversize regular FCG
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// this will break famicom 2 dumps without hash match,
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// which are marked mapper016 usually
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goto case "MAPPER153";
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}
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AssertPrg(128, 256); AssertChr(128, 256);
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Cart.wram_size = 0;
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regs_prg_enable = true;
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regs_wram_enable = true;
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eprom = new SEEPROM(true);
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break;
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case "MAPPER153": // [5]
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AssertPrg(512);
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AssertChr(0);
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Cart.vram_size = 8;
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Cart.wram_size = 8;
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regs_prg_enable = true;
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regs_wram_enable = false;
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jump2 = true;
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vram = true;
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break;
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case "BANDAI-JUMP2": // [5]
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AssertPrg(512);
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AssertChr(0);
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AssertVram(8);
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AssertWram(8);
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regs_prg_enable = true;
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regs_wram_enable = false;
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jump2 = true;
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vram = true;
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break;
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case "MAPPER157": // [6]
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// incomplete
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// bootgod doesn't have any of these recorded
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AssertPrg(128, 256);
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AssertChr(0);
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Cart.vram_size = 8;
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Cart.wram_size = 0;
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regs_prg_enable = true;
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regs_wram_enable = false;
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// 24C02 is present on all boards
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// some also have a 24C01 with SCK connected to reg ($8000-$8003).3
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// (does that second seeprom use the same SDA and OE connections as the first? 99% yes, but not implemented)
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eprom = new SEEPROM(true);
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vram = true;
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reader = new DatachBarcode();
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break;
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default:
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return false;
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}
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prg_bank_mask_16k = (Cart.prg_size / 16) - 1;
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chr_bank_mask_1k = Cart.chr_size - 1;
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SetMirrorType(EMirrorType.Vertical);
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prg_reg_16k = 0;
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SyncPRG();
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return true;
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}
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void SyncPRG()
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{
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prg_banks_16k[0] = prg_reg_16k & prg_bank_mask_16k;
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prg_banks_16k[1] = 0xFF & prg_bank_mask_16k;
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if (jump2)
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{
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if (regs[0].Bit(0))
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{
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prg_banks_16k[0] |= 0x10;
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prg_banks_16k[1] |= 0x10;
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}
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else // wouldn't need this, except we aren't &=15 on the prg bank addresses
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{
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prg_banks_16k[0] &= 0x0f;
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prg_banks_16k[1] &= 0x0f;
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}
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}
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}
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void WriteReg(int reg, byte value)
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{
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//Console.WriteLine("reg {0:X2} = {1:X2}", reg, value);
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switch (reg)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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regs[reg] = value;
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if (jump2) // in jump2, chr regs are rewired to swap prg
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SyncPRG();
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break;
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case 8:
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//NES.LogLine("mapping PRG {0}", value);
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prg_reg_16k = value;
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SyncPRG();
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break;
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case 9:
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switch (value & 3)
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{
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case 0: SetMirrorType(NES.NESBoardBase.EMirrorType.Vertical); break;
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case 1: SetMirrorType(NES.NESBoardBase.EMirrorType.Horizontal); break;
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case 2: SetMirrorType(NES.NESBoardBase.EMirrorType.OneScreenA); break;
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case 3: SetMirrorType(NES.NESBoardBase.EMirrorType.OneScreenB); break;
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}
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break;
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case 0xA:
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irq_enabled = value.Bit(0);
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// all write acknolwedge
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IRQSignal = false;
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break;
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case 0xB:
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irq_counter &= 0xFF00;
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irq_counter |= value;
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break;
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case 0xC:
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irq_counter &= 0x00FF;
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irq_counter |= (ushort)(value << 8);
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break;
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case 0xD:
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if (eprom != null)
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eprom.WriteByte(value);
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break;
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}
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}
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public override void WriteWRAM(int addr, byte value)
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{
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//NES.LogLine("writewram {0:X4} = {1:X2}", addr, value);
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if (regs_wram_enable)
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{
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addr &= 0xF;
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WriteReg(addr, value);
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}
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else if (jump2)
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{
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WRAM[addr] = value;
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}
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}
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public override void WritePRG(int addr, byte value)
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{
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//NES.LogLine("writeprg {0:X4} = {1:X2}", addr, value);
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if (regs_prg_enable)
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{
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addr &= 0xF;
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WriteReg(addr, value);
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}
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}
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public override byte ReadWRAM(int addr)
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{
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// reading any addr in 6000:7fff returns a single bit from the eeprom
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// in bit 4.
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if (!jump2)
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{
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byte ret = (byte)(NES.DB & 0xef);
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if (eprom != null && eprom.ReadBit(NES.DB.Bit(4)))
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ret |= 0x10;
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if (reader != null)
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{
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if (reader.GetOutput())
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ret |= 0x08;
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else
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ret &= 0xf7;
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}
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return ret;
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}
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else
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{
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return WRAM[addr];
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}
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}
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public override void ClockCPU()
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{
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if (irq_enabled)
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{
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irq_counter--;
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if (irq_counter == 0x0000)
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{
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IRQSignal = true;
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}
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}
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if (reader != null)
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{
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reader.Clock();
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}
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}
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public override byte ReadPRG(int addr)
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{
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int bank_16k = addr >> 14;
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int ofs = addr & ((1 << 14) - 1);
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bank_16k = prg_banks_16k[bank_16k];
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addr = (bank_16k << 14) | ofs;
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return ROM[addr];
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}
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int CalcPPUAddress(int addr)
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{
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int bank_1k = addr >> 10;
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int ofs = addr & ((1 << 10) - 1);
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bank_1k = regs[bank_1k];
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bank_1k &= chr_bank_mask_1k;
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return (bank_1k << 10) | ofs;
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}
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public override byte ReadPPU(int addr)
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{
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if (addr < 0x2000)
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{
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if (vram)
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return VRAM[addr];
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else
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return VROM[CalcPPUAddress(addr)];
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}
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else
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{
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return base.ReadPPU(addr);
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}
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}
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public override void WritePPU(int addr, byte value)
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{
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if (addr < 0x2000)
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{
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if (vram)
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VRAM[addr] = value;
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}
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else
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{
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base.WritePPU(addr, value);
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}
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}
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public override byte[] SaveRam
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{
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get
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{
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if (eprom != null)
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return eprom.GetSaveRAM();
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else if (jump2)
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{
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return WRAM;
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}
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else
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{
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return null;
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}
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}
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}
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}
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}
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