64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
/* x86_features.c - x86 feature check
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*
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* Copyright (C) 2013 Intel Corporation. All rights reserved.
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* Author:
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* Jim Kukunas
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*
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* For conditions of distribution and use, see copyright notice in README.md
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*/
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#include <cpuid.h>
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#include <string.h>
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int x86_cpu_has_avx2;
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int x86_cpu_has_avx512;
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int x86_cpu_has_avx512vnni;
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int x86_cpu_has_sse2;
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int x86_cpu_has_ssse3;
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int x86_cpu_has_sse41;
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int x86_cpu_has_sse42;
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int x86_cpu_has_pclmulqdq;
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int x86_cpu_has_vpclmulqdq;
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int x86_cpu_has_tzcnt;
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int x86_cpu_has_sha;
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void x86_check_features(void) {
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static int features_checked = 0;
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if (features_checked)
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return;
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unsigned eax, ebx, ecx, edx;
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unsigned maxbasic;
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__cpuid(0, maxbasic, ebx, ecx, edx);
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__cpuid(1 /*CPU_PROCINFO_AND_FEATUREBITS*/, eax, ebx, ecx, edx);
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x86_cpu_has_sse2 = edx & 0x4000000;
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x86_cpu_has_ssse3 = ecx & 0x200;
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x86_cpu_has_sse41 = ecx & 0x80000;
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x86_cpu_has_sse42 = ecx & 0x100000;
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x86_cpu_has_pclmulqdq = ecx & 0x2;
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if (maxbasic >= 7) {
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__cpuid_count(7, 0, eax, ebx, ecx, edx);
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// check BMI1 bit
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// Reference: https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf
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x86_cpu_has_tzcnt = ebx & 0x8;
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// check AVX2 bit
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x86_cpu_has_avx2 = ebx & 0x20;
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x86_cpu_has_avx512 = ebx & 0x00010000;
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x86_cpu_has_avx512vnni = ecx & 0x800;
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x86_cpu_has_vpclmulqdq = ecx & 0x400;
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// check SHA bit
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x86_cpu_has_sha = ebx & 0x20000000;
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} else {
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x86_cpu_has_tzcnt = 0;
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x86_cpu_has_avx2 = 0;
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x86_cpu_has_avx512 = 0;
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x86_cpu_has_avx512vnni = 0;
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x86_cpu_has_vpclmulqdq = 0;
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x86_cpu_has_sha = 0;
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}
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}
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