99 lines
4.0 KiB
C
99 lines
4.0 KiB
C
/* crc32_fold_vpclmulqdq.c -- VPCMULQDQ-based CRC32 folding implementation.
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* Copyright Wangyang Guo (wangyang.guo@intel.com)
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* For conditions of distribution and use, see copyright notice in README.md
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*/
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#include <immintrin.h>
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#include <stdint.h>
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#define ONCE(op) if (first) { first = 0; op; }
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#define XOR_INITIAL(where) ONCE(where = _mm512_xor_si512(where, zmm_initial))
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__attribute__((target("sse4.1,pclmul,avx512f,vpclmulqdq")))
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uint64_t fold_16_vpclmulqdq(__m128i *xmm_crc0, __m128i *xmm_crc1,
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__m128i *xmm_crc2, __m128i *xmm_crc3, const uint8_t *src, uint64_t len,
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__m128i init_crc, int32_t first) {
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__m512i zmm_initial = _mm512_zextsi128_si512(init_crc);
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__m512i zmm_t0, zmm_t1, zmm_t2, zmm_t3;
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__m512i zmm_crc0, zmm_crc1, zmm_crc2, zmm_crc3;
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__m512i z0, z1, z2, z3;
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uint64_t len_tmp = len;
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const __m512i zmm_fold4 = _mm512_set4_epi32(0x00000001, 0x54442bd4, 0x00000001, 0xc6e41596);
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const __m512i zmm_fold16 = _mm512_set4_epi32(0x00000001, 0x1542778a, 0x00000001, 0x322d1430);
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// zmm register init
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zmm_crc0 = _mm512_setzero_si512();
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zmm_t0 = _mm512_loadu_si512((__m512i *)src);
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XOR_INITIAL(zmm_t0);
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zmm_crc1 = _mm512_loadu_si512((__m512i *)src + 1);
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zmm_crc2 = _mm512_loadu_si512((__m512i *)src + 2);
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zmm_crc3 = _mm512_loadu_si512((__m512i *)src + 3);
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// already have intermediate CRC in xmm registers
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// fold4 with 4 xmm_crc to get zmm_crc0
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zmm_crc0 = _mm512_inserti32x4(zmm_crc0, *xmm_crc0, 0);
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zmm_crc0 = _mm512_inserti32x4(zmm_crc0, *xmm_crc1, 1);
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zmm_crc0 = _mm512_inserti32x4(zmm_crc0, *xmm_crc2, 2);
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zmm_crc0 = _mm512_inserti32x4(zmm_crc0, *xmm_crc3, 3);
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z0 = _mm512_clmulepi64_epi128(zmm_crc0, zmm_fold4, 0x01);
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zmm_crc0 = _mm512_clmulepi64_epi128(zmm_crc0, zmm_fold4, 0x10);
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zmm_crc0 = _mm512_xor_si512(z0, zmm_crc0);
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zmm_crc0 = _mm512_xor_si512(zmm_crc0, zmm_t0);
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len -= 256;
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src += 256;
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// fold-16 loops
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while (len >= 256) {
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zmm_t0 = _mm512_loadu_si512((__m512i *)src);
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zmm_t1 = _mm512_loadu_si512((__m512i *)src + 1);
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zmm_t2 = _mm512_loadu_si512((__m512i *)src + 2);
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zmm_t3 = _mm512_loadu_si512((__m512i *)src + 3);
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z0 = _mm512_clmulepi64_epi128(zmm_crc0, zmm_fold16, 0x01);
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z1 = _mm512_clmulepi64_epi128(zmm_crc1, zmm_fold16, 0x01);
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z2 = _mm512_clmulepi64_epi128(zmm_crc2, zmm_fold16, 0x01);
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z3 = _mm512_clmulepi64_epi128(zmm_crc3, zmm_fold16, 0x01);
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zmm_crc0 = _mm512_clmulepi64_epi128(zmm_crc0, zmm_fold16, 0x10);
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zmm_crc1 = _mm512_clmulepi64_epi128(zmm_crc1, zmm_fold16, 0x10);
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zmm_crc2 = _mm512_clmulepi64_epi128(zmm_crc2, zmm_fold16, 0x10);
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zmm_crc3 = _mm512_clmulepi64_epi128(zmm_crc3, zmm_fold16, 0x10);
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zmm_crc0 = _mm512_xor_si512(z0, zmm_crc0);
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zmm_crc1 = _mm512_xor_si512(z1, zmm_crc1);
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zmm_crc2 = _mm512_xor_si512(z2, zmm_crc2);
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zmm_crc3 = _mm512_xor_si512(z3, zmm_crc3);
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zmm_crc0 = _mm512_xor_si512(zmm_crc0, zmm_t0);
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zmm_crc1 = _mm512_xor_si512(zmm_crc1, zmm_t1);
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zmm_crc2 = _mm512_xor_si512(zmm_crc2, zmm_t2);
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zmm_crc3 = _mm512_xor_si512(zmm_crc3, zmm_t3);
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len -= 256;
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src += 256;
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}
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// zmm_crc[0,1,2,3] -> zmm_crc0
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z0 = _mm512_clmulepi64_epi128(zmm_crc0, zmm_fold4, 0x01);
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zmm_crc0 = _mm512_clmulepi64_epi128(zmm_crc0, zmm_fold4, 0x10);
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zmm_crc0 = _mm512_xor_si512(z0, zmm_crc0);
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zmm_crc0 = _mm512_xor_si512(zmm_crc0, zmm_crc1);
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z0 = _mm512_clmulepi64_epi128(zmm_crc0, zmm_fold4, 0x01);
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zmm_crc0 = _mm512_clmulepi64_epi128(zmm_crc0, zmm_fold4, 0x10);
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zmm_crc0 = _mm512_xor_si512(z0, zmm_crc0);
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zmm_crc0 = _mm512_xor_si512(zmm_crc0, zmm_crc2);
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z0 = _mm512_clmulepi64_epi128(zmm_crc0, zmm_fold4, 0x01);
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zmm_crc0 = _mm512_clmulepi64_epi128(zmm_crc0, zmm_fold4, 0x10);
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zmm_crc0 = _mm512_xor_si512(z0, zmm_crc0);
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zmm_crc0 = _mm512_xor_si512(zmm_crc0, zmm_crc3);
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// zmm_crc0 -> xmm_crc[0, 1, 2, 3]
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*xmm_crc0 = _mm512_extracti32x4_epi32(zmm_crc0, 0);
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*xmm_crc1 = _mm512_extracti32x4_epi32(zmm_crc0, 1);
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*xmm_crc2 = _mm512_extracti32x4_epi32(zmm_crc0, 2);
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*xmm_crc3 = _mm512_extracti32x4_epi32(zmm_crc0, 3);
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return (len_tmp - len); // return n bytes processed
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} |