305 lines
8.2 KiB
C++
305 lines
8.2 KiB
C++
auto CPU::readRAM(uint addr, uint8 data) -> uint8 {
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return wram[addr];
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}
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auto CPU::readAPU(uint addr, uint8 data) -> uint8 {
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synchronizeSMP();
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return smp.portRead(addr & 3);
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}
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auto CPU::readCPU(uint addr, uint8 data) -> uint8 {
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switch(addr & 0xffff) {
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case 0x2180: //WMDATA
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return bus.read(0x7e0000 | io.wramAddress++, data);
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//todo: it is not known what happens when reading from this register during auto-joypad polling
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case 0x4016: //JOYSER0
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data &= 0xfc;
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data |= controllerPort1.device->data();
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platform->notify("NO_LAG");
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return data;
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//todo: it is not known what happens when reading from this register during auto-joypad polling
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case 0x4017: //JOYSER1
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data &= 0xe0;
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data |= 0x1c; //pins are connected to GND
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data |= controllerPort2.device->data();
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platform->notify("NO_LAG");
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return data;
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case 0x4210: //RDNMI
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data &= 0x70;
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data |= rdnmi() << 7;
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data |= (uint4)version;
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return data;
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case 0x4211: //TIMEUP
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data &= 0x7f;
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data |= timeup() << 7;
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return data;
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case 0x4212: //HVBJOY
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data &= 0x3e;
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data |= io.autoJoypadPoll && status.autoJoypadCounter < 33;
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data |= (hcounter() <= 2 || hcounter() >= 1096) << 6; //hblank
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data |= (vcounter() >= ppu.vdisp()) << 7; //vblank
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return data;
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case 0x4213: return io.pio; //RDIO
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case 0x4214: return io.rddiv >> 0; //RDDIVL
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case 0x4215: return io.rddiv >> 8; //RDDIVH
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case 0x4216: return io.rdmpy >> 0; //RDMPYL
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case 0x4217: return io.rdmpy >> 8; //RDMPYH
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//todo: it is not known what happens when reading from these registers during auto-joypad polling
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case 0x4218: platform->notify("NO_LAG"); return io.joy1 >> 0; //JOY1L
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case 0x4219: platform->notify("NO_LAG"); return io.joy1 >> 8; //JOY1H
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case 0x421a: platform->notify("NO_LAG"); return io.joy2 >> 0; //JOY2L
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case 0x421b: platform->notify("NO_LAG"); return io.joy2 >> 8; //JOY2H
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case 0x421c: platform->notify("NO_LAG"); return io.joy3 >> 0; //JOY3L
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case 0x421d: platform->notify("NO_LAG"); return io.joy3 >> 8; //JOY3H
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case 0x421e: platform->notify("NO_LAG"); return io.joy4 >> 0; //JOY4L
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case 0x421f: platform->notify("NO_LAG"); return io.joy4 >> 8; //JOY4H
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}
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return data;
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}
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auto CPU::readDMA(uint addr, uint8 data) -> uint8 {
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auto& channel = this->channels[addr >> 4 & 7];
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switch(addr & 0xff8f) {
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case 0x4300: //DMAPx
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return (
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channel.transferMode << 0
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| channel.fixedTransfer << 3
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| channel.reverseTransfer << 4
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| channel.unused << 5
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| channel.indirect << 6
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| channel.direction << 7
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);
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case 0x4301: return channel.targetAddress; //BBADx
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case 0x4302: return channel.sourceAddress >> 0; //A1TxL
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case 0x4303: return channel.sourceAddress >> 8; //A1TxH
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case 0x4304: return channel.sourceBank; //A1Bx
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case 0x4305: return channel.transferSize >> 0; //DASxL
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case 0x4306: return channel.transferSize >> 8; //DASxH
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case 0x4307: return channel.indirectBank; //DASBx
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case 0x4308: return channel.hdmaAddress >> 0; //A2AxL
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case 0x4309: return channel.hdmaAddress >> 8; //A2AxH
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case 0x430a: return channel.lineCounter; //NTRLx
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case 0x430b: return channel.unknown; //???x
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case 0x430f: return channel.unknown; //???x ($43xb mirror)
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}
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return data;
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}
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auto CPU::writeRAM(uint addr, uint8 data) -> void {
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wram[addr] = data;
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}
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auto CPU::writeAPU(uint addr, uint8 data) -> void {
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synchronizeSMP();
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return smp.portWrite(addr & 3, data);
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}
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auto CPU::writeCPU(uint addr, uint8 data) -> void {
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switch(addr & 0xffff) {
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case 0x2180: //WMDATA
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return bus.write(0x7e0000 | io.wramAddress++, data);
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case 0x2181: //WMADDL
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io.wramAddress = io.wramAddress & 0x1ff00 | data << 0;
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return;
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case 0x2182: //WMADDM
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io.wramAddress = io.wramAddress & 0x100ff | data << 8;
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return;
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case 0x2183: //WMADDH
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io.wramAddress = io.wramAddress & 0x0ffff | (data & 1) << 16;
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return;
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//todo: it is not known what happens when writing to this register during auto-joypad polling
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case 0x4016: //JOYSER0
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//bit 0 is shared between JOYSER0 and JOYSER1:
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//strobing $4016.d0 affects both controller port latches.
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//$4017 bit 0 writes are ignored.
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controllerPort1.device->latch(data & 1);
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controllerPort2.device->latch(data & 1);
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return;
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case 0x4200: //NMITIMEN
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io.autoJoypadPoll = data & 1;
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if(!io.autoJoypadPoll) status.autoJoypadCounter = 33; // Disable auto-joypad read
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nmitimenUpdate(data);
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return;
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case 0x4201: //WRIO
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if((io.pio & 0x80) && !(data & 0x80)) ppu.latchCounters();
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io.pio = data;
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return;
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case 0x4202: //WRMPYA
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io.wrmpya = data;
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return;
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case 0x4203: //WRMPYB
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io.rdmpy = 0;
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if(alu.mpyctr || alu.divctr) return;
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io.wrmpyb = data;
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io.rddiv = io.wrmpyb << 8 | io.wrmpya;
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if(!configuration.hacks.cpu.fastMath) {
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if (!alu.mpylast) {
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alu.mpyctr = 8; //perform multiplication over the next eight cycles
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alu.shift = io.wrmpyb;
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}
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} else {
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io.rdmpy = io.wrmpya * io.wrmpyb;
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}
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return;
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case 0x4204: //WRDIVL
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io.wrdiva = io.wrdiva & 0xff00 | data << 0;
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return;
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case 0x4205: //WRDIVH
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io.wrdiva = io.wrdiva & 0x00ff | data << 8;
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return;
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case 0x4206: //WRDIVB
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io.rdmpy = io.wrdiva;
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if(alu.mpyctr || alu.divctr) return;
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if(!configuration.hacks.cpu.fastMath) {
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if (!alu.divlast) {
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io.wrdivb = data;
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alu.divctr = 16; //perform division over the next sixteen cycles
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alu.shift = io.wrdivb << 16;
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}
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} else {
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io.wrdivb = data;
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if(io.wrdivb) {
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io.rddiv = io.wrdiva / io.wrdivb;
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io.rdmpy = io.wrdiva % io.wrdivb;
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} else {
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io.rddiv = 0xffff;
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io.rdmpy = io.wrdiva;
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}
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}
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return;
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case 0x4207: //HTIMEL
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io.htime = (io.htime >> 2) - 1;
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io.htime = io.htime & 0x100 | data << 0;
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io.htime = (io.htime + 1) << 2;
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irqPoll(); //unverified
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return;
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case 0x4208: //HTIMEH
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io.htime = (io.htime >> 2) - 1;
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io.htime = io.htime & 0x0ff | (data & 1) << 8;
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io.htime = (io.htime + 1) << 2;
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irqPoll(); //unverified
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return;
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case 0x4209: //VTIMEL
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io.vtime = io.vtime & 0x100 | data << 0;
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irqPoll(); //unverified
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return;
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case 0x420a: //VTIMEH
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io.vtime = io.vtime & 0x0ff | (data & 1) << 8;
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irqPoll(); //unverified
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return;
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case 0x420b: //DMAEN
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for(auto n : range(8)) channels[n].dmaEnable = bool(data & 1 << n);
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if(data) status.dmaPending = true;
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return;
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case 0x420c: //HDMAEN
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for(auto n : range(8)) channels[n].hdmaEnable = bool(data & 1 << n);
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return;
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case 0x420d: //MEMSEL
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io.fastROM = data & 1;
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return;
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}
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}
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auto CPU::writeDMA(uint addr, uint8 data) -> void {
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auto& channel = this->channels[addr >> 4 & 7];
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switch(addr & 0xff8f) {
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case 0x4300: //DMAPx
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channel.transferMode = data >> 0 & 7;
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channel.fixedTransfer = data >> 3 & 1;
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channel.reverseTransfer = data >> 4 & 1;
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channel.unused = data >> 5 & 1;
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channel.indirect = data >> 6 & 1;
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channel.direction = data >> 7 & 1;
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return;
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case 0x4301: //BBADx
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channel.targetAddress = data;
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return;
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case 0x4302: //A1TxL
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channel.sourceAddress = channel.sourceAddress & 0xff00 | data << 0;
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return;
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case 0x4303: //A1TxH
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channel.sourceAddress = channel.sourceAddress & 0x00ff | data << 8;
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return;
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case 0x4304: //A1Bx
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channel.sourceBank = data;
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return;
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case 0x4305: //DASxL
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channel.transferSize = channel.transferSize & 0xff00 | data << 0;
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return;
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case 0x4306: //DASxH
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channel.transferSize = channel.transferSize & 0x00ff | data << 8;
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return;
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case 0x4307: //DASBx
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channel.indirectBank = data;
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return;
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case 0x4308: //A2AxL
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channel.hdmaAddress = channel.hdmaAddress & 0xff00 | data << 0;
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return;
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case 0x4309: //A2AxH
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channel.hdmaAddress = channel.hdmaAddress & 0x00ff | data << 8;
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return;
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case 0x430a: //NTRLx
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channel.lineCounter = data;
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return;
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case 0x430b: //???x
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channel.unknown = data;
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return;
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case 0x430f: //???x ($43xb mirror)
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channel.unknown = data;
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return;
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}
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}
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