/* src/psp/rtl.h: Declarations for register transfer language used in dynamic translation Copyright 2009 Andrew Church This file is part of Yabause. Yabause is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. Yabause is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with Yabause; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef RTL_H #define RTL_H /*************************************************************************/ /** * RTLBlock: State information used in translating a block of code. * Opaque to callers. */ typedef struct RTLBlock_ RTLBlock; /*-----------------------------------------------------------------------*/ /** * RTLOpcode: Enumeration of operations, used as the value of the * RTLInsn.op field. */ typedef enum RTLOpcode_ { /* Zero is invalid */ /* No operation */ RTLOP_NOP = 1, // [No operation -- note that a value can be given // in src1 for debugging purposes] /* Register-register operations */ RTLOP_MOVE, // dest = src1 RTLOP_SELECT, // dest = other ? src1 : src2 RTLOP_ADD, // dest = src1 + src2 RTLOP_SUB, // dest = src1 - src2 RTLOP_MULU, // (uint64_t){other,dest} = // (unsigned)src1 * (unsigned)src2 // [upper 32 bits of result stored in "other", // lower 32 bits of result stored in "dest"; // either dest or other may be zero = omitted] RTLOP_MULS, // (int64_t){other,dest} = (signed)src1 * (signed)src2 // [either dest or other may be zero = omitted] RTLOP_MADDU, // (uint64_t){other,dest} += // (unsigned)src1 * (unsigned)src2 // [other/dest are both inputs and outputs; for // optimal performance, they should be the same // registers used as outputs of a MULU/MULS or // previous MADDU/MADDS insn] RTLOP_MADDS, // (int64_t){other,dest} += (signed)src1 * (signed)src2 RTLOP_DIVMODU, // dest = (unsigned)src1 / (unsigned)src2; // other = (unsigned)src1 % (unsigned)src2 // [both undefined if src2 == 0] // [either dest or other may be zero = omitted] RTLOP_DIVMODS, // dest = (signed)src1 / (signed)src2; // other = (signed)src1 % (signed)src2 // [both undefined if src2 == 0] // [either dest or other may be zero = omitted] RTLOP_AND, // dest = src1 & src2 RTLOP_OR, // dest = src1 | src2 RTLOP_XOR, // dest = src1 ^ src2 RTLOP_NOT, // dest = ~src1 RTLOP_SLL, // dest = src1 << src2 [undefined when src2 >= 32] RTLOP_SRL, // dest = (unsigned)src1 >> src2 // [undefined when src2 >= 32] RTLOP_SRA, // dest = (signed)src1 >> src2 // [undefined when src2 >= 32] RTLOP_ROR, // dest = src1 ROR (src2 % 32) [in 32 bits] RTLOP_CLZ, // dest = [number of leading zeros in src1] RTLOP_CLO, // dest = [number of leading ones in src1] RTLOP_SLTU, // dest = (unsigned)src1 < (unsigned)src2 ? 1 : 0 RTLOP_SLTS, // dest = (signed)src1 < (signed)src2 ? 1 : 0 RTLOP_BSWAPH, // dest = [swap adjacent pairs of bytes in src1] RTLOP_BSWAPW, // dest = [reverse order of sets of 4 bytes in src1] RTLOP_HSWAPW, // dest = [swap adjacent pairs of halfword in src1] /* Register-immediate operations */ RTLOP_ADDI, // dest = src1 + IMMEDIATE(src2) RTLOP_ANDI, // dest = src1 & IMMEDIATE(src2) RTLOP_ORI, // dest = src1 | IMMEDIATE(src2) RTLOP_XORI, // dest = src1 ^ IMMEDIATE(src2) RTLOP_SLLI, // dest = src1 << IMMEDIATE(src2) RTLOP_SRLI, // dest = (unsigned)src1 >> IMMEDIATE(src2) RTLOP_SRAI, // dest = (signed)src1 << IMMEDIATE(src2) RTLOP_RORI, // dest = src1 ROR IMMEDIATE(src2) [in 32 bits] RTLOP_SLTUI, // dest = (unsigned)src1 < (unsigned)IMMEDIATE(src2) // ? 1 : 0 RTLOP_SLTSI, // dest = (signed)src1 < (signed)IMMEDIATE(src2) // ? 1 : 0 /* Bitfield operations ("start" and "count" are encoded in the "other" * parameter as: other = start | count<<8) */ RTLOP_BFEXT, // dest = (src1 >> start) & ((1<