3bbfb98fc2
C64: Split out VIC IRQ delays
2019-07-13 19:28:44 -05:00
7df8ed1f27
A2600: Add HMCLR delay
2019-07-13 18:33:54 -04:00
154eefd2ad
C64: Give BA/IRQ counting another go, seems to resolve many issues
2019-07-13 16:51:30 -05:00
db38d5e65b
C64: Try counting IRQ and BA correctly
2019-07-13 15:28:57 -05:00
f22c9b7abd
C64: CPU reads open bus when !AEC is asserted
2019-07-13 15:25:40 -05:00
894adbb610
C64: Remove an unused variable
2019-07-13 15:02:18 -05:00
76679bc8bc
C64: Use the correct background color in bitmapped modes for 0
2019-07-13 15:01:11 -05:00
bd20b355f0
C64: Writing to CPU port writes open bus data to 00/01
2019-07-13 14:06:23 -05:00
f18e7c8833
C64: Make the system debuggable for once
2019-07-13 13:15:50 -05:00
cae3340946
C64: No need to expose these with the CPU link in place
2019-07-13 12:53:34 -05:00
3369dbf43f
C64: IRQ is implemented as a delay line; no delay added (yet)
2019-07-13 12:51:39 -05:00
d39f3e2e61
6502X: pending IRQs are not delayed when !RDY is asserted
2019-07-13 12:31:09 -05:00
bf2cba0e23
6502X: remove a comment (this is indeed a dummy fetch)
2019-07-13 11:38:03 -05:00
d62f2ac3fe
C64: 0F7 is a badline eligible raster (fixes 26-line text demo in Frodo test suite)
2019-07-13 01:41:58 -05:00
e6871b2cc3
C64: Move VIC raster IRQ to phase 1
2019-07-13 00:27:08 -05:00
dbf6b39e7f
C64: Split out VIC phase1/phase2
2019-07-12 23:51:55 -05:00
85bc92b688
Merge remote-tracking branch 'origin/c64-refactor' into c64-refactor
...
# Conflicts:
# BizHawk.Emulation.Cores/Computers/Commodore64/MOS/Chip6510.cs
2019-07-12 22:10:08 -05:00
68a58c1dd5
CurrentBotAttmpt.Log will not go over amount of frames.
...
Restricting the Update function from adding additional _currentBotAttempt inputs. Checks if Emulator.Frame advanced from last Update. Works fine if you are not flipping through multiple branches in TasStudio. Doing that results in some other Ram Watches being off sometimes.
2019-07-12 21:08:12 -04:00
66cf00a917
Vectrex: Add frame buffer to state an set to released
2019-07-12 18:15:25 -04:00
90436811b9
GG: Fix World Derby
2019-07-12 15:07:58 -04:00
5e2b097902
MC6809: fix DAA
2019-07-10 19:30:17 -04:00
fd51934ea4
Vectrex: Fix some bugs
2019-07-10 15:42:01 -04:00
9fe277a3ff
Vectrex: a bit more controller and frame cleanup
2019-07-10 06:58:41 -04:00
0a7dc52aa0
C64: BA and raster IRQ cleanup
2019-07-09 22:41:12 -05:00
3a135c7c26
C64: Raster interrupt bit can be set even if not enabled, just won't actually assert IRQ
2019-07-09 21:40:03 -05:00
e63d10b608
C64: Interrupts generated in phase 2 by the VIC won't trigger for the CPU until next cycle, also buffer BA
2019-07-09 20:55:14 -05:00
b471fdc692
C64: The CPU can trigger VIC badlines on its own (needed for VSP)
2019-07-09 20:53:54 -05:00
2abe832289
C64: AEC does not prohibit the CPU from functioning, only BA (RDY) does
2019-07-09 20:52:51 -05:00
9758efe604
6502X: CPU does a read or write regardless if the result is trashed, even during reset and dummy pushes
2019-07-09 19:46:33 -05:00
84b0917f65
Vectrex: Add schema and do some miscellanous clean up
2019-07-09 20:01:45 -04:00
a8fd85157c
VIC: Use correct color mapping for non-multicolor bitmap mode
2019-07-09 08:02:55 -05:00
83b6553749
VIC: Respect idle state background color registers, plus black in undocumented gfx mode
2019-07-09 06:58:13 -05:00
89fa153477
VIC: Resolve background color registers separately to color matrix memory
2019-07-09 06:55:55 -05:00
9f733d3e7a
VIC: More accurate pixel pipeline
2019-07-09 05:26:26 -05:00
3efea15038
6502X: When !RDY is asserted, still do other operations. Plus, do dummy reads on stack ops
2019-07-09 05:24:47 -05:00
f544c044bf
NES MMC3: Mapper test indicates IRQ was happening one ppu tick too late.
2019-07-08 08:16:43 -04:00
5b2ed7e4ff
MC6800: disassembler and cleanup
2019-07-07 17:32:14 -04:00
53dd500875
MC6800: More cleanup
2019-07-07 09:08:26 -04:00
e2014ba3f5
MC6800 work and MC6809 bug fix
2019-07-07 08:22:01 -04:00
a4b38aa7a5
MC6800: Initial commit
2019-07-06 20:16:48 -04:00
d36e02045b
C64: Optimize the RNG for 1541 flux transitions. (same output)
2019-07-06 16:32:21 -05:00
3bf37f1c17
C64: No need for LagCycles anymore.
2019-07-06 16:29:14 -05:00
475702c1e8
Vectrex: code cleanup
2019-07-06 16:44:46 -04:00
432abb27f6
Vectrex: expose menues
2019-07-06 08:56:25 -04:00
6ed11de85b
C64: Soft/Hard reset: it's about time
2019-07-06 01:19:58 -05:00
d48964b642
6502X: According to the datasheet, RDY must be high in order for interrupts to trigger
...
- this has implications for C64, as it may cause VIC interrupts to fire quite later than they currently do
2019-07-06 00:00:51 -05:00
400b04b690
C64: CIA was sometimes delaying too long to fire interrupts by 1 cycle.
...
- This could have implications for existing TASes (!)
2019-07-05 23:59:01 -05:00
69f8b143a3
C64: Foreground pixels are black when VIC is in idle state.
2019-07-05 21:05:38 -05:00
8698aa41be
Merge branch 'master' into c64-refactor
2019-07-05 20:14:28 -05:00
9cbc78778f
Vectrex: interrupt fixes
2019-07-05 20:25:03 -04:00
SaxxonPike