SaxxonPike
|
a119420c79
|
C64: VC count enable seems to need to be delayed by 1 cycle after badline
- which doesn't affect normal operation
- which DOES affect VSP
|
2019-07-14 20:22:07 -05:00 |
|
SaxxonPike
|
4d6ed8d6c8
|
C64: Savestate should include the new variables
|
2019-07-14 16:32:53 -05:00 |
|
SaxxonPike
|
8e8d3a6a1b
|
C64: Writes to some registers on the VIC in phase 2 by the CPU should only take effect on the following cycle
|
2019-07-14 10:44:56 -05:00 |
|
SaxxonPike
|
3369dbf43f
|
C64: IRQ is implemented as a delay line; no delay added (yet)
|
2019-07-13 12:51:39 -05:00 |
|
SaxxonPike
|
3a135c7c26
|
C64: Raster interrupt bit can be set even if not enabled, just won't actually assert IRQ
|
2019-07-09 21:40:03 -05:00 |
|
SaxxonPike
|
e63d10b608
|
C64: Interrupts generated in phase 2 by the VIC won't trigger for the CPU until next cycle, also buffer BA
|
2019-07-09 20:55:14 -05:00 |
|
SaxxonPike
|
89fa153477
|
VIC: Resolve background color registers separately to color matrix memory
|
2019-07-09 06:55:55 -05:00 |
|
SaxxonPike
|
9f733d3e7a
|
VIC: More accurate pixel pipeline
|
2019-07-09 05:26:26 -05:00 |
|
SaxxonPike
|
6ed11de85b
|
C64: Soft/Hard reset: it's about time
|
2019-07-06 01:19:58 -05:00 |
|
James Groom
|
4e91f88af3
|
Use nameof in cores
|
2019-03-28 14:18:58 +11:00 |
|
adelikat
|
1877cce021
|
C64 - misc cleanups
|
2017-05-30 13:10:01 -04:00 |
|
adelikat
|
caf9802412
|
C64 - remove the SaveState.DoNotSave attribute
|
2017-05-13 13:04:02 -05:00 |
|
adelikat
|
762a35773c
|
C64 - convert VIC and sublasses to not use SyncObject
|
2017-05-13 09:37:11 -05:00 |
|
adelikat
|
3dd5478efd
|
spaces to tabs in C64 files
|
2017-04-24 10:09:31 -05:00 |
|
Anthony Konzel
|
ac9a4ef777
|
Apply C64 core update patch.
|
2016-02-22 17:50:11 -06:00 |
|
saxxonpike
|
2fb95adb1a
|
Commodore 64: Remove useless 'experimental' folder, make namespaces match folders
|
2014-10-03 21:04:37 +00:00 |
|
adelikat
|
7e45f13282
|
Change project name BizHawk.Emulation to BizHawk.Emulation.Cores
|
2013-11-15 14:05:47 +00:00 |