GBHawk: Bug Fixes
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@ -33,22 +33,27 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
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if (ppu.DMA_start)
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if (ppu.DMA_start)
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{
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{
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if ((addr >= 0xFE00) && (addr < 0xFEA0) && ppu.DMA_OAM_access)
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if (addr < 0x4000)
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{
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{
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return OAM[addr - 0xFE00];
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return mapper.ReadMemory(addr); // some of gekkio's tests require this to be accessible during DMA
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}
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else if ((addr >= 0xFF80))
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{
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return ZP_RAM[addr - 0xFF80];
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}
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}
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else if ((addr >= 0xE000) && (addr < 0xFE00))
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else if ((addr >= 0xE000) && (addr < 0xFE00))
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{
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{
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return RAM[addr - 0xE000]; // some of gekkio's tests require this to be accessible during DMA
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return RAM[addr - 0xE000]; // some of gekkio's tests require this to be accessible during DMA
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}
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}
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else if (addr < 0x4000)
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else if ((addr >= 0xFE00) && (addr < 0xFEA0) && ppu.DMA_OAM_access)
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{
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{
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return mapper.ReadMemory(addr); // some of gekkio's tests require this to be accessible during DMA
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return OAM[addr - 0xFE00];
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}
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}
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else if ((addr >= 0xFF00) && (addr < 0xFF80)) // The game GOAL! Requires Hardware Regs to be accessible
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{
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return Read_Registers(addr);
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}
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else if ((addr >= 0xFF80))
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{
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return ZP_RAM[addr - 0xFF80];
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}
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return 0xFF;
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return 0xFF;
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}
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}
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@ -126,22 +131,22 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
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if (ppu.DMA_start)
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if (ppu.DMA_start)
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{
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{
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if ((addr >= 0xFE00) && (addr < 0xFEA0) && ppu.DMA_OAM_access)
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if ((addr >= 0xE000) && (addr < 0xFE00))
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{
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RAM[addr - 0xE000] = value; // some of gekkio's tests require this to be accessible during DMA
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}
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else if ((addr >= 0xFE00) && (addr < 0xFEA0) && ppu.DMA_OAM_access)
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{
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{
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OAM[addr - 0xFE00] = value;
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OAM[addr - 0xFE00] = value;
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}
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}
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else if ((addr >= 0xFF00) && (addr < 0xFF80)) // The game GOAL! Requires Hardware Regs to be accessible
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{
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Write_Registers(addr, value);
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}
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else if ((addr >= 0xFF80))
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else if ((addr >= 0xFF80))
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{
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{
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ZP_RAM[addr - 0xFF80] = value;
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ZP_RAM[addr - 0xFF80] = value;
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}
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}
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else if (addr == 0xFF46)
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{
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Write_Registers(addr, value); // a second DMA can start, but what about other registers?
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}
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else if ((addr >= 0xE000) && (addr < 0xFE00))
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{
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RAM[addr - 0xE000] = value; // some of gekkio's tests require this to be accessible during DMA
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}
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return;
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return;
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}
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}
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@ -211,22 +216,27 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
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{
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{
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if (ppu.DMA_start)
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if (ppu.DMA_start)
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{
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{
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if ((addr >= 0xFE00) && (addr < 0xFEA0) && ppu.DMA_OAM_access)
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if (addr < 0x4000)
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{
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{
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return OAM[addr - 0xFE00];
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return mapper.ReadMemory(addr); // some of gekkio's tests require this to be accessible during DMA
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}
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else if ((addr >= 0xFF80))
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{
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return ZP_RAM[addr - 0xFF80];
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}
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}
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else if ((addr >= 0xE000) && (addr < 0xFE00))
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else if ((addr >= 0xE000) && (addr < 0xFE00))
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{
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{
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return RAM[addr - 0xE000]; // some of gekkio's tests require this to be accessible during DMA
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return RAM[addr - 0xE000]; // some of gekkio's tests require this to be accessible during DMA
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}
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}
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else if (addr < 0x4000)
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else if ((addr >= 0xFE00) && (addr < 0xFEA0) && ppu.DMA_OAM_access)
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{
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{
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return mapper.PeekMemory(addr); // some of gekkio's tests require this to be accessible during DMA
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return OAM[addr - 0xFE00];
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}
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}
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else if ((addr >= 0xFF00) && (addr < 0xFF80)) // The game GOAL! Requires Hardware Regs to be accessible
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{
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return Read_Registers(addr);
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}
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else if ((addr >= 0xFF80))
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{
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return ZP_RAM[addr - 0xFF80];
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}
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return 0xFF;
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return 0xFF;
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}
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}
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@ -117,6 +117,14 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
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switch (addr)
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switch (addr)
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{
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{
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case 0xFF40: // LCDC
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case 0xFF40: // LCDC
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if (LCDC.Bit(7) && !value.Bit(7))
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{
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VRAM_access_read = true;
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VRAM_access_write = true;
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OAM_access_read = true;
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OAM_access_write = true;
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}
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LCDC = value;
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LCDC = value;
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break;
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break;
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case 0xFF41: // STAT
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case 0xFF41: // STAT
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@ -1047,8 +1055,8 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
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BGP = 0xFF;
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BGP = 0xFF;
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obj_pal_0 = 0xFF;
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obj_pal_0 = 0xFF;
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obj_pal_1 = 0xFF;
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obj_pal_1 = 0xFF;
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window_y = 0;
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window_y = 0x0;
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window_x = 0;
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window_x = 0x0;
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LY_inc = 1;
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LY_inc = 1;
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no_scan = false;
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no_scan = false;
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OAM_access_read = true;
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OAM_access_read = true;
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