(partial) update to Mednafen 0.9.39-unstable
This commit is contained in:
parent
75beb338b9
commit
f5f63349f6
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@ -952,14 +952,12 @@ void PS_CDC::HandlePlayRead(void)
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{
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{
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uint8 tr[8];
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uint8 tr[8];
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//zero 14-jun-2016 - useful after all for fixing bugs in "Fantastic Pinball Kyutenkai"
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//zero 14-jun-2016 - useful after all for fixing bugs in "Fantastic Pinball Kyutenkai"
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#if 1
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uint16 abs_lev_max = 0;
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uint16 abs_lev_max = 0;
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bool abs_lev_chselect = SubQBuf_Safe[0x8] & 0x01;
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bool abs_lev_chselect = SubQBuf_Safe[0x8] & 0x01;
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for(int i = 0; i < 588; i++)
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for(int i = 0; i < 588; i++)
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abs_lev_max = std::max<uint16>(abs_lev_max, std::min<int>(abs((int16)MDFN_de16lsb(&read_buf[i * 4 + (abs_lev_chselect * 2)])), 32767));
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abs_lev_max = std::max<uint16>(abs_lev_max, std::min<int>(abs((int16)MDFN_de16lsb(&read_buf[i * 4 + (abs_lev_chselect * 2)])), 32767));
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abs_lev_max |= abs_lev_chselect << 15;
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abs_lev_max |= abs_lev_chselect << 15;
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#endif
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ReportLastF = SubQBuf_Safe[0x9] >> 4;
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ReportLastF = SubQBuf_Safe[0x9] >> 4;
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@ -980,9 +978,6 @@ void PS_CDC::HandlePlayRead(void)
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tr[5] = SubQBuf_Safe[0x9]; // A F
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tr[5] = SubQBuf_Safe[0x9]; // A F
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}
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}
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//zero 14-jun-2016 - useful after all for fixing bugs in "Fantastic Pinball Kyutenkai"
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//tr[6] = 0; //abs_lev_max >> 0;
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//tr[7] = 0; //abs_lev_max >> 8;
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tr[6] = abs_lev_max >> 0;
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tr[6] = abs_lev_max >> 0;
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tr[7] = abs_lev_max >> 8;
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tr[7] = abs_lev_max >> 8;
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@ -22,8 +22,8 @@ class PS_CDC
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{
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{
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public:
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public:
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PS_CDC();
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PS_CDC() MDFN_COLD;
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~PS_CDC();
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~PS_CDC() MDFN_COLD;
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template<bool isReader>void SyncState(EW::NewState *ns);
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template<bool isReader>void SyncState(EW::NewState *ns);
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@ -31,7 +31,7 @@ class PS_CDC
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void SetDisc(ShockDiscRef *disc, const char disc_id[4], bool poke);
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void SetDisc(ShockDiscRef *disc, const char disc_id[4], bool poke);
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void CloseTray(bool poke);
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void CloseTray(bool poke);
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void Power(void);
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void Power(void) MDFN_COLD;
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void ResetTS(void);
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void ResetTS(void);
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int32 CalcNextEvent(void); // Returns in master cycles to next event.
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int32 CalcNextEvent(void); // Returns in master cycles to next event.
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File diff suppressed because it is too large
Load Diff
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@ -1,41 +1,62 @@
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/******************************************************************************/
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/* Mednafen Sony PS1 Emulation Module */
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/******************************************************************************/
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/* cpu.h:
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** Copyright (C) 2011-2016 Mednafen Team
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**
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** This program is free software; you can redistribute it and/or
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** modify it under the terms of the GNU General Public License
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** as published by the Free Software Foundation; either version 2
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** of the License, or (at your option) any later version.
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**
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** This program is distributed in the hope that it will be useful,
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** but WITHOUT ANY WARRANTY; without even the implied warranty of
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** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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** GNU General Public License for more details.
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**
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** You should have received a copy of the GNU General Public License
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** along with this program; if not, write to the Free Software Foundation, Inc.,
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** 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __MDFN_PSX_CPU_H
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#ifndef __MDFN_PSX_CPU_H
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#define __MDFN_PSX_CPU_H
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#define __MDFN_PSX_CPU_H
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/*
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/*
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Load delay notes:
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Load delay notes:
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// Takes 1 less
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// Takes 1 less
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".set noreorder\n\t"
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".set noreorder\n\t"
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".set nomacro\n\t"
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".set nomacro\n\t"
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"lw %0, 0(%2)\n\t"
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"lw %0, 0(%2)\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"or %0, %1, %1\n\t"
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"or %0, %1, %1\n\t"
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// cycle than this:
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// cycle than this:
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".set noreorder\n\t"
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".set noreorder\n\t"
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".set nomacro\n\t"
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".set nomacro\n\t"
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"lw %0, 0(%2)\n\t"
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"lw %0, 0(%2)\n\t"
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"nop\n\t"
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"nop\n\t"
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"or %0, %1, %1\n\t"
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"or %0, %1, %1\n\t"
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"nop\n\t"
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"nop\n\t"
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// Both of these
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// Both of these
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".set noreorder\n\t"
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".set noreorder\n\t"
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".set nomacro\n\t"
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".set nomacro\n\t"
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"lw %0, 0(%2)\n\t"
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"lw %0, 0(%2)\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"or %1, %0, %0\n\t"
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"or %1, %0, %0\n\t"
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// take same...(which is kind of odd).
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// take same...(which is kind of odd).
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".set noreorder\n\t"
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".set noreorder\n\t"
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".set nomacro\n\t"
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".set nomacro\n\t"
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"lw %0, 0(%2)\n\t"
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"lw %0, 0(%2)\n\t"
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"nop\n\t"
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"nop\n\t"
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"or %1, %0, %0\n\t"
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"or %1, %0, %0\n\t"
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"nop\n\t"
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"nop\n\t"
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*/
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*/
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#include "gte.h"
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#include "gte.h"
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@ -45,217 +66,220 @@ namespace MDFN_IEN_PSX
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#define PS_CPU_EMULATE_ICACHE 1
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#define PS_CPU_EMULATE_ICACHE 1
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class PS_CPU
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class PS_CPU
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{
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{
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public:
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public:
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PS_CPU() MDFN_COLD;
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PS_CPU() MDFN_COLD;
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~PS_CPU() MDFN_COLD;
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~PS_CPU() MDFN_COLD;
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template<bool isReader>void SyncState(EW::NewState *ns);
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template<bool isReader>void SyncState(EW::NewState *ns);
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// FAST_MAP_* enums are in BYTES(8-bit), not in 32-bit units("words" in MIPS context), but the sizes
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// will always be multiples of 4.
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enum { FAST_MAP_SHIFT = 16 };
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enum { FAST_MAP_PSIZE = 1 << FAST_MAP_SHIFT };
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// FAST_MAP_* enums are in BYTES(8-bit), not in 32-bit units("words" in MIPS context), but the sizes
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void SetFastMap(void *region_mem, uint32 region_address, uint32 region_size);
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// will always be multiples of 4.
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enum { FAST_MAP_SHIFT = 16 };
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enum { FAST_MAP_PSIZE = 1 << FAST_MAP_SHIFT };
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void SetFastMap(void *region_mem, uint32 region_address, uint32 region_size);
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INLINE void SetEventNT(const pscpu_timestamp_t next_event_ts_arg)
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{
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next_event_ts = next_event_ts_arg;
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}
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INLINE void SetEventNT(const pscpu_timestamp_t next_event_ts_arg)
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pscpu_timestamp_t Run(pscpu_timestamp_t timestamp_in, bool BIOSPrintMode, bool ILHMode);
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{
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next_event_ts = next_event_ts_arg;
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}
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pscpu_timestamp_t Run(pscpu_timestamp_t timestamp_in, bool BIOSPrintMode, bool ILHMode);
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void Power(void) MDFN_COLD;
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void Power(void) MDFN_COLD;
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// which ranges 0-5, inclusive
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void AssertIRQ(unsigned which, bool asserted);
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// which ranges 0-5, inclusive
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void SetHalt(bool status);
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void AssertIRQ(unsigned which, bool asserted);
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void SetHalt(bool status);
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// TODO eventually: factor BIU address decoding directly in the CPU core somehow without hurting speed.
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void SetBIU(uint32 val);
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uint32 GetBIU(void);
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// TODO eventually: factor BIU address decoding directly in the CPU core somehow without hurting speed.
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void SetBIU(uint32 val);
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uint32 GetBIU(void);
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private:
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private:
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uint32 GPR[32 + 1]; // GPR[32] Used as dummy in load delay simulation(indexing past the end of real GPR)
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uint32 GPR[32 + 1]; // GPR[32] Used as dummy in load delay simulation(indexing past the end of real GPR)
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uint32 LO;
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uint32 LO;
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uint32 HI;
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uint32 HI;
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uint32 BACKED_PC;
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uint32 BACKED_PC;
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uint32 BACKED_new_PC;
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uint32 BACKED_new_PC;
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uint32 BACKED_new_PC_mask;
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uint32 IPCache;
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uint32 IPCache;
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void RecalcIPCache(void);
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uint8 BDBT;
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bool Halted;
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uint32 BACKED_LDWhich;
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uint8 ReadAbsorb[0x20 + 1];
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uint32 BACKED_LDValue;
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uint8 ReadAbsorbWhich;
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uint32 LDAbsorb;
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uint8 ReadFudge;
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pscpu_timestamp_t next_event_ts;
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void RecalcIPCache(void);
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pscpu_timestamp_t gte_ts_done;
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bool Halted;
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pscpu_timestamp_t muldiv_ts_done;
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uint32 BIU;
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uint32 BACKED_LDWhich;
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uint32 BACKED_LDValue;
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uint32 LDAbsorb;
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struct __ICache
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pscpu_timestamp_t next_event_ts;
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{
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pscpu_timestamp_t gte_ts_done;
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uint32 TV;
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pscpu_timestamp_t muldiv_ts_done;
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uint32 Data;
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};
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union
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uint32 BIU;
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{
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__ICache ICache[1024];
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uint32 ICache_Bulk[2048];
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};
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enum
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const uint32 addr_mask[8] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, 0x1FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
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{
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CP0REG_BPC = 3, // PC breakpoint address.
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CP0REG_BDA = 5, // Data load/store breakpoint address.
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CP0REG_TAR = 6, // Target address(???)
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CP0REG_DCIC = 7, // Cache control
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CP0REG_BADVA = 8,
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CP0REG_BDAM = 9, // Data load/store address mask.
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CP0REG_BPCM = 11, // PC breakpoint address mask.
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CP0REG_SR = 12,
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CP0REG_CAUSE = 13,
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CP0REG_EPC = 14,
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CP0REG_PRID = 15 // Product ID
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};
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struct
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enum
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{
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{
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union
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CP0REG_BPC = 3, // PC breakpoint address.
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{
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CP0REG_BDA = 5, // Data load/store breakpoint address.
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uint32 Regs[32];
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CP0REG_TAR = 6, // Target address(???)
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struct
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CP0REG_DCIC = 7, // Cache control
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{
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CP0REG_BADA = 8,
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uint32 Unused00;
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CP0REG_BDAM = 9, // Data load/store address mask.
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uint32 Unused01;
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CP0REG_BPCM = 11, // PC breakpoint address mask.
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uint32 Unused02;
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CP0REG_SR = 12,
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uint32 BPC; // RW
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CP0REG_CAUSE = 13,
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uint32 Unused04;
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CP0REG_EPC = 14,
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uint32 BDA; // RW
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CP0REG_PRID = 15 // Product ID
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uint32 TAR; // R
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};
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uint32 DCIC; // RW
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uint32 BADVA; // R
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uint32 BDAM; // R/W
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uint32 Unused0A;
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uint32 BPCM; // R/W
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uint32 SR; // R/W
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uint32 CAUSE; // R/W(partial)
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uint32 EPC; // R
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uint32 PRID; // R
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};
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};
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} CP0;
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#if 1
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struct
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//uint32 WrAbsorb;
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{
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//uint8 WrAbsorbShift;
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union
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{
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uint32 Regs[32];
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struct
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{
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uint32 Unused00;
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uint32 Unused01;
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uint32 Unused02;
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uint32 BPC; // RW
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uint32 Unused04;
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uint32 BDA; // RW
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uint32 TAR; // R
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uint32 DCIC; // RW
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uint32 BADA; // R
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uint32 BDAM; // R/W
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uint32 Unused0A;
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uint32 BPCM; // R/W
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uint32 SR; // R/W
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uint32 CAUSE; // R/W(partial)
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uint32 EPC; // R
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uint32 PRID; // R
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};
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};
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} CP0;
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// On read:
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uint8 MULT_Tab24[24];
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//WrAbsorb = 0;
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//WrAbsorbShift = 0;
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// On write:
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struct __ICache
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//WrAbsorb >>= (WrAbsorbShift >> 2) & 8;
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{
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//WrAbsorbShift -= (WrAbsorbShift >> 2) & 8;
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/*
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TV:
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Mask 0x00000001: 0x0 = icache enabled((BIU & 0x800) == 0x800), 0x1 = icache disabled(changed in bulk on BIU value changes; preserve everywhere else!)
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Mask 0x00000002: 0x0 = valid, 0x2 = invalid
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Mask 0x00000FFC: Always 0
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Mask 0xFFFFF000: Tag.
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*/
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uint32 TV;
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uint32 Data;
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};
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//WrAbsorb |= (timestamp - pre_write_timestamp) << WrAbsorbShift;
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union
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//WrAbsorbShift += 8;
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{
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#endif
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__ICache ICache[1024];
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uint32 ICache_Bulk[2048];
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};
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uint8 ReadAbsorb[0x20 + 1];
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MultiAccessSizeMem<1024, false> ScratchRAM;
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uint8 ReadAbsorbWhich;
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uint8 ReadFudge;
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//uint32 WriteAbsorb;
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//PS_GTE GTE;
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//uint8 WriteAbsorbCount;
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//uint8 WriteAbsorbMonkey;
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uint8 MULT_Tab24[24];
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MultiAccessSizeMem<1024, false> ScratchRAM;
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uint8 *FastMap[1 << (32 - FAST_MAP_SHIFT)];
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uint8 DummyPage[FAST_MAP_PSIZE];
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//PS_GTE GTE;
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enum
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{
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EXCEPTION_INT = 0,
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EXCEPTION_MOD = 1,
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EXCEPTION_TLBL = 2,
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EXCEPTION_TLBS = 3,
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EXCEPTION_ADEL = 4, // Address error on load
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EXCEPTION_ADES = 5, // Address error on store
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EXCEPTION_IBE = 6, // Instruction bus error
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EXCEPTION_DBE = 7, // Data bus error
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EXCEPTION_SYSCALL = 8, // System call
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EXCEPTION_BP = 9, // Breakpoint
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EXCEPTION_RI = 10, // Reserved instruction
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EXCEPTION_COPU = 11, // Coprocessor unusable
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EXCEPTION_OV = 12 // Arithmetic overflow
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};
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uint8 *FastMap[1 << (32 - FAST_MAP_SHIFT)];
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uint32 Exception(uint32 code, uint32 PC, const uint32 NP, const uint32 instr) MDFN_WARN_UNUSED_RESULT;
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uint8 DummyPage[FAST_MAP_PSIZE];
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enum
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template<bool DebugMode, bool BIOSPrintMode, bool ILHMode> pscpu_timestamp_t RunReal(pscpu_timestamp_t timestamp_in) NO_INLINE;
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{
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EXCEPTION_INT = 0,
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|
||||||
EXCEPTION_MOD = 1,
|
|
||||||
EXCEPTION_TLBL = 2,
|
|
||||||
EXCEPTION_TLBS = 3,
|
|
||||||
EXCEPTION_ADEL = 4, // Address error on load
|
|
||||||
EXCEPTION_ADES = 5, // Address error on store
|
|
||||||
EXCEPTION_IBE = 6, // Instruction bus error
|
|
||||||
EXCEPTION_DBE = 7, // Data bus error
|
|
||||||
EXCEPTION_SYSCALL = 8, // System call
|
|
||||||
EXCEPTION_BP = 9, // Breakpoint
|
|
||||||
EXCEPTION_RI = 10, // Reserved instruction
|
|
||||||
EXCEPTION_COPU = 11, // Coprocessor unusable
|
|
||||||
EXCEPTION_OV = 12 // Arithmetic overflow
|
|
||||||
};
|
|
||||||
|
|
||||||
uint32 Exception(uint32 code, uint32 PC, const uint32 NP, const uint32 NPM, const uint32 instr) MDFN_WARN_UNUSED_RESULT;
|
template<typename T> T PeekMemory(uint32 address) MDFN_COLD;
|
||||||
|
template<typename T> void PokeMemory(uint32 address, T value) MDFN_COLD;
|
||||||
|
template<typename T> T ReadMemory(pscpu_timestamp_t ×tamp, uint32 address, bool DS24 = false, bool LWC_timing = false);
|
||||||
|
template<typename T> void WriteMemory(pscpu_timestamp_t ×tamp, uint32 address, uint32 value, bool DS24 = false);
|
||||||
|
|
||||||
template<bool DebugMode, bool BIOSPrintMode, bool ILHMode> pscpu_timestamp_t RunReal(pscpu_timestamp_t timestamp_in) NO_INLINE;
|
uint32 ReadInstruction(pscpu_timestamp_t ×tamp, uint32 address);
|
||||||
|
|
||||||
template<typename T> T PeekMemory(uint32 address) MDFN_COLD;
|
//
|
||||||
template<typename T> void PokeMemory(uint32 address, T value) MDFN_COLD;
|
// Mednafen debugger stuff follows:
|
||||||
template<typename T> T ReadMemory(pscpu_timestamp_t ×tamp, uint32 address, bool DS24 = false, bool LWC_timing = false);
|
//
|
||||||
template<typename T> void WriteMemory(pscpu_timestamp_t ×tamp, uint32 address, uint32 value, bool DS24 = false);
|
public:
|
||||||
|
void SetCPUHook(void (*cpuh)(const pscpu_timestamp_t timestamp, uint32 pc), void (*addbt)(uint32 from, uint32 to, bool exception));
|
||||||
|
void CheckBreakpoints(void (*callback)(bool write, uint32 address, unsigned int len), uint32 instr);
|
||||||
|
void* debug_GetScratchRAMPtr() { return ScratchRAM.data8; }
|
||||||
|
void* debug_GetGPRPtr() { return GPR; }
|
||||||
|
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
GSREG_GPR = 0,
|
||||||
|
GSREG_PC = 32,
|
||||||
|
GSREG_PC_NEXT,
|
||||||
|
GSREG_IN_BD_SLOT,
|
||||||
|
GSREG_LO,
|
||||||
|
GSREG_HI,
|
||||||
|
//
|
||||||
|
//
|
||||||
|
GSREG_BPC,
|
||||||
|
GSREG_BDA,
|
||||||
|
GSREG_TAR,
|
||||||
|
GSREG_DCIC,
|
||||||
|
GSREG_BADA,
|
||||||
|
GSREG_BDAM,
|
||||||
|
GSREG_BPCM,
|
||||||
|
GSREG_SR,
|
||||||
|
GSREG_CAUSE,
|
||||||
|
GSREG_EPC
|
||||||
|
};
|
||||||
|
|
||||||
|
uint32 GetRegister(unsigned int which, char *special, const uint32 special_len);
|
||||||
|
void SetRegister(unsigned int which, uint32 value);
|
||||||
|
bool PeekCheckICache(uint32 PC, uint32 *iw);
|
||||||
|
|
||||||
|
|
||||||
//
|
uint8 PeekMem8(uint32 A);
|
||||||
// Mednafen debugger stuff follows:
|
uint16 PeekMem16(uint32 A);
|
||||||
//
|
uint32 PeekMem32(uint32 A);
|
||||||
public:
|
|
||||||
void SetCPUHook(void(*cpuh)(const pscpu_timestamp_t timestamp, uint32 pc), void(*addbt)(uint32 from, uint32 to, bool exception));
|
|
||||||
void CheckBreakpoints(void(*callback)(bool write, uint32 address, unsigned int len), uint32 instr);
|
|
||||||
void* debug_GetScratchRAMPtr() { return ScratchRAM.data8; }
|
|
||||||
void* debug_GetGPRPtr() { return GPR; }
|
|
||||||
|
|
||||||
enum
|
void PokeMem8(uint32 A, uint8 V);
|
||||||
{
|
void PokeMem16(uint32 A, uint16 V);
|
||||||
GSREG_GPR = 0,
|
void PokeMem32(uint32 A, uint32 V);
|
||||||
GSREG_PC = 32,
|
|
||||||
GSREG_PC_NEXT,
|
|
||||||
GSREG_IN_BD_SLOT,
|
|
||||||
GSREG_LO,
|
|
||||||
GSREG_HI,
|
|
||||||
GSREG_SR,
|
|
||||||
GSREG_CAUSE,
|
|
||||||
GSREG_EPC,
|
|
||||||
};
|
|
||||||
|
|
||||||
uint32 GetRegister(unsigned int which, char *special, const uint32 special_len);
|
private:
|
||||||
void SetRegister(unsigned int which, uint32 value);
|
void (*CPUHook)(const pscpu_timestamp_t timestamp, uint32 pc);
|
||||||
bool PeekCheckICache(uint32 PC, uint32 *iw);
|
void (*ADDBT)(uint32 from, uint32 to, bool exception);
|
||||||
|
};
|
||||||
uint8 PeekMem8(uint32 A);
|
|
||||||
uint16 PeekMem16(uint32 A);
|
|
||||||
uint32 PeekMem32(uint32 A);
|
|
||||||
|
|
||||||
void PokeMem8(uint32 A, uint8 V);
|
|
||||||
void PokeMem16(uint32 A, uint16 V);
|
|
||||||
void PokeMem32(uint32 A, uint32 V);
|
|
||||||
|
|
||||||
private:
|
|
||||||
void(*CPUHook)(const pscpu_timestamp_t timestamp, uint32 pc);
|
|
||||||
void(*ADDBT)(uint32 from, uint32 to, bool exception);
|
|
||||||
};
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue