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revert some of baa3bdf948, as it caused regressions elsewhere, make GPU interrupts not stupid (makes Myst stop crashing with NTSC)

This commit is contained in:
CasualPokePlayer 2022-09-30 02:28:27 -07:00
parent baa3bdf948
commit f1a3e02e89
4 changed files with 41 additions and 45 deletions
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Assets/dll/virtualjaguar.wbx.zst
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12
waterbox/virtualjaguar/src/dsp.cpp
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@ -23,8 +23,6 @@
#include "jerry.h" #include "jerry.h"
#include "m68000/m68kinterface.h" #include "m68000/m68kinterface.h"
bool IMASKCleared = false;
// DSP flags (old--have to get rid of this crap) // DSP flags (old--have to get rid of this crap)
#define CINT0FLAG 0x00200 #define CINT0FLAG 0x00200
@ -187,6 +185,9 @@ uint32_t dsp_reg_bank_0[32], dsp_reg_bank_1[32];
static uint32_t dsp_opcode_first_parameter; static uint32_t dsp_opcode_first_parameter;
static uint32_t dsp_opcode_second_parameter; static uint32_t dsp_opcode_second_parameter;
static bool IMASKCleared;
static uint32_t dsp_inhibit_interrupt;
#define DSP_RUNNING (dsp_control & 0x01) #define DSP_RUNNING (dsp_control & 0x01)
static uint8_t branch_condition_table[32 * 8]; static uint8_t branch_condition_table[32 * 8];
@ -392,7 +393,7 @@ void DSPWriteLong(uint32_t offset, uint32_t data, uint32_t who)
{ {
case 0x00: case 0x00:
{ {
IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK); IMASKCleared |= (dsp_flags & IMASK) && !(data & IMASK);
dsp_flags = data & (~IMASK); dsp_flags = data & (~IMASK);
dsp_flag_z = dsp_flags & 0x01; dsp_flag_z = dsp_flags & 0x01;
@ -582,18 +583,21 @@ void DSPExec(int32_t cycles)
{ {
MAYBE_CALLBACK(DSPTraceCallback, dsp_pc, dsp_reg); MAYBE_CALLBACK(DSPTraceCallback, dsp_pc, dsp_reg);
if (IMASKCleared) if (IMASKCleared && !dsp_inhibit_interrupt)
{ {
DSPHandleIRQsNP(); DSPHandleIRQsNP();
IMASKCleared = false; IMASKCleared = false;
} }
dsp_inhibit_interrupt = 0;
uint16_t opcode = DSPReadWord(dsp_pc, DSP); uint16_t opcode = DSPReadWord(dsp_pc, DSP);
uint32_t index = opcode >> 10; uint32_t index = opcode >> 10;
dsp_opcode_first_parameter = (opcode >> 5) & 0x1F; dsp_opcode_first_parameter = (opcode >> 5) & 0x1F;
dsp_opcode_second_parameter = opcode & 0x1F; dsp_opcode_second_parameter = opcode & 0x1F;
dsp_pc += 2; dsp_pc += 2;
dsp_opcode[index](); dsp_opcode[index]();
cycles -= dsp_opcode_cycles[index]; cycles -= dsp_opcode_cycles[index];
} }
} }

22
waterbox/virtualjaguar/src/gpu.cpp
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@ -182,6 +182,9 @@ static uint32_t * gpu_alternate_reg;
static uint32_t gpu_opcode_first_parameter; static uint32_t gpu_opcode_first_parameter;
static uint32_t gpu_opcode_second_parameter; static uint32_t gpu_opcode_second_parameter;
static bool IMASKCleared;
static uint32_t gpu_inhibit_interrupt;
#define GPU_RUNNING (gpu_control & 0x01) #define GPU_RUNNING (gpu_control & 0x01)
static uint8_t branch_condition_table[32 * 8]; static uint8_t branch_condition_table[32 * 8];
@ -414,15 +417,14 @@ void GPUWriteLong(uint32_t offset, uint32_t data, uint32_t who)
{ {
case 0x00: case 0x00:
{ {
bool IMASKCleared = (gpu_flags & IMASK) && !(data & IMASK); IMASKCleared |= (gpu_flags & IMASK) && !(data & IMASK);
gpu_flags = data & (~IMASK); gpu_flags = data & (~IMASK);
gpu_flag_z = gpu_flags & ZERO_FLAG; gpu_flag_z = gpu_flags & ZERO_FLAG;
gpu_flag_c = (gpu_flags & CARRY_FLAG) >> 1; gpu_flag_c = (gpu_flags & CARRY_FLAG) >> 1;
gpu_flag_n = (gpu_flags & NEGA_FLAG) >> 2; gpu_flag_n = (gpu_flags & NEGA_FLAG) >> 2;
GPUUpdateRegisterBanks(); GPUUpdateRegisterBanks();
gpu_control &= ~((gpu_flags & CINT04FLAGS) >> 3); gpu_control &= ~((gpu_flags & CINT04FLAGS) >> 3);
if (IMASKCleared)
GPUHandleIRQs();
break; break;
} }
case 0x04: case 0x04:
@ -566,6 +568,7 @@ void GPUReset(void)
gpu_reg[i] = gpu_alternate_reg[i] = 0x00000000; gpu_reg[i] = gpu_alternate_reg[i] = 0x00000000;
gpu_flag_z = gpu_flag_n = gpu_flag_c = 0; gpu_flag_z = gpu_flag_n = gpu_flag_c = 0;
IMASKCleared = false;
memset(gpu_ram_8, 0xFF, 0x1000); memset(gpu_ram_8, 0xFF, 0x1000);
for(uint32_t i=0; i<4096; i+=4) for(uint32_t i=0; i<4096; i+=4)
@ -579,18 +582,19 @@ void GPUDone(void)
// //
// Main GPU execution core // Main GPU execution core
// //
void GPUExec(int32_t cycles) void GPUExec(int32_t cycles)
{ {
if (!GPU_RUNNING)
return;
GPUHandleIRQs();
while (cycles > 0 && GPU_RUNNING) while (cycles > 0 && GPU_RUNNING)
{ {
MAYBE_CALLBACK(GPUTraceCallback, gpu_pc, gpu_reg); MAYBE_CALLBACK(GPUTraceCallback, gpu_pc, gpu_reg);
if (IMASKCleared && !gpu_inhibit_interrupt)
{
GPUHandleIRQs();
IMASKCleared = false;
}
gpu_inhibit_interrupt = 0;
uint16_t opcode = GPUReadWord(gpu_pc, GPU); uint16_t opcode = GPUReadWord(gpu_pc, GPU);
uint32_t index = opcode >> 10; uint32_t index = opcode >> 10;
gpu_opcode_first_parameter = (opcode >> 5) & 0x1F; gpu_opcode_first_parameter = (opcode >> 5) & 0x1F;

52
waterbox/virtualjaguar/src/risc_opcodes.h
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@ -2,7 +2,7 @@
#if RISC == 3 #if RISC == 3
#define RISC_OPCODE(op) static void gpu_opcode_##op(void) #define RISC_OPCODE(op) static void gpu_opcode_##op(void)
#define risc_opcode gpu_opcode #define risc_inhibit_interrupt gpu_inhibit_interrupt
#define IMM_1 gpu_opcode_first_parameter #define IMM_1 gpu_opcode_first_parameter
#define IMM_2 gpu_opcode_second_parameter #define IMM_2 gpu_opcode_second_parameter
#define risc_flag_n gpu_flag_n #define risc_flag_n gpu_flag_n
@ -17,12 +17,13 @@
#define risc_div_control gpu_div_control #define risc_div_control gpu_div_control
#define risc_remain gpu_remain #define risc_remain gpu_remain
#define IS_RISC_RAM(x) x >= GPU_WORK_RAM_BASE && x <= (GPU_WORK_RAM_BASE + 0xFFF) #define IS_RISC_RAM(x) x >= GPU_WORK_RAM_BASE && x <= (GPU_WORK_RAM_BASE + 0xFFF)
#define RISCExec(x) GPUExec(x)
#define RISCReadWord(x, y) GPUReadWord(x, y) #define RISCReadWord(x, y) GPUReadWord(x, y)
#define RISCReadLong(x, y) GPUReadLong(x, y) #define RISCReadLong(x, y) GPUReadLong(x, y)
#define RISCWriteLong(x, y, z) GPUWriteLong(x, y, z) #define RISCWriteLong(x, y, z) GPUWriteLong(x, y, z)
#elif RISC == 2 #elif RISC == 2
#define RISC_OPCODE(op) static void dsp_opcode_##op(void) #define RISC_OPCODE(op) static void dsp_opcode_##op(void)
#define risc_opcode dsp_opcode #define risc_inhibit_interrupt dsp_inhibit_interrupt
#define IMM_1 dsp_opcode_first_parameter #define IMM_1 dsp_opcode_first_parameter
#define IMM_2 dsp_opcode_second_parameter #define IMM_2 dsp_opcode_second_parameter
#define risc_flag_n dsp_flag_n #define risc_flag_n dsp_flag_n
@ -37,6 +38,7 @@
#define risc_div_control dsp_div_control #define risc_div_control dsp_div_control
#define risc_remain dsp_remain #define risc_remain dsp_remain
#define IS_RISC_RAM(x) x >= DSP_WORK_RAM_BASE && x <= (DSP_WORK_RAM_BASE + 0x1FFF) #define IS_RISC_RAM(x) x >= DSP_WORK_RAM_BASE && x <= (DSP_WORK_RAM_BASE + 0x1FFF)
#define RISCExec(x) DSPExec(x)
#define RISCReadWord(x, y) DSPReadWord(x, y) #define RISCReadWord(x, y) DSPReadWord(x, y)
#define RISCReadLong(x, y) DSPReadLong(x, y) #define RISCReadLong(x, y) DSPReadLong(x, y)
#define RISCWriteLong(x, y, z) DSPWriteLong(x, y, z) #define RISCWriteLong(x, y, z) DSPWriteLong(x, y, z)
@ -83,10 +85,8 @@ RISC_OPCODE(jump)
if (BRANCH_CONDITION(IMM_2)) if (BRANCH_CONDITION(IMM_2))
{ {
uint32_t delayed_pc = RM; uint32_t delayed_pc = RM;
uint16_t opcode = RISCReadWord(risc_pc, RISC); risc_inhibit_interrupt = 1;
IMM_1 = (opcode >> 5) & 0x1F; RISCExec(1);
IMM_2 = opcode & 0x1F;
risc_opcode[opcode >> 10]();
risc_pc = delayed_pc; risc_pc = delayed_pc;
} }
} }
@ -99,10 +99,8 @@ RISC_OPCODE(jr)
{ {
int32_t offset = (IMM_1 > 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1); int32_t offset = (IMM_1 > 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1);
int32_t delayed_pc = risc_pc + (offset * 2); int32_t delayed_pc = risc_pc + (offset * 2);
uint16_t opcode = RISCReadWord(risc_pc, RISC); risc_inhibit_interrupt = 1;
IMM_1 = (opcode >> 5) & 0x1F; RISCExec(1);
IMM_2 = opcode & 0x1F;
risc_opcode[opcode >> 10]();
risc_pc = delayed_pc; risc_pc = delayed_pc;
} }
} }
@ -334,7 +332,9 @@ RISC_OPCODE(moveq)
RISC_OPCODE(resmac) RISC_OPCODE(resmac)
{ {
RN = risc_acc; RN = (uint32_t)risc_acc;
//this makes Club Drive sound ok, but it has missing sounds and other games/bios suffer
//risc_inhibit_interrupt = 1;
} }
RISC_OPCODE(imult) RISC_OPCODE(imult)
@ -381,7 +381,8 @@ RISC_OPCODE(addqt)
RISC_OPCODE(imacn) RISC_OPCODE(imacn)
{ {
int32_t res = (int16_t)RM * (int16_t)RN; int32_t res = (int16_t)RM * (int16_t)RN;
risc_acc += res; risc_acc += (int64_t)res;
risc_inhibit_interrupt = 1;
} }
RISC_OPCODE(mtoi) RISC_OPCODE(mtoi)
@ -421,6 +422,7 @@ RISC_OPCODE(mmult)
int64_t accum = 0; int64_t accum = 0;
uint32_t res; uint32_t res;
// remove the + 2 and change the 4s to 2 for Baldies to sound ok, screws up bios however
if (!(risc_matrix_control & 0x10)) if (!(risc_matrix_control & 0x10))
{ {
for (int i = 0; i < count; i++) for (int i = 0; i < count; i++)
@ -431,9 +433,9 @@ RISC_OPCODE(mmult)
else else
a = (int16_t)(risc_alternate_reg[IMM_1 + (i >> 1)] & 0xffff); a = (int16_t)(risc_alternate_reg[IMM_1 + (i >> 1)] & 0xffff);
int16_t b = (int16_t)RISCReadWord(addr, RISC); int16_t b = (int16_t)RISCReadWord(addr + 2, RISC);
accum += a * b; accum += a * b;
addr += 2; addr += 4;
} }
} }
else else
@ -448,7 +450,7 @@ RISC_OPCODE(mmult)
int16_t b = (int16_t)RISCReadWord(addr, RISC); int16_t b = (int16_t)RISCReadWord(addr, RISC);
accum += a * b; accum += a * b;
addr += 2 * count; addr += 4 * count;
} }
} }
@ -488,24 +490,10 @@ RISC_OPCODE(div)
RISC_OPCODE(imultn) RISC_OPCODE(imultn)
{ {
uint32_t res = (int16_t)RN * (int16_t)RM; uint32_t res = (int32_t)((int16_t)RN * (int16_t)RM);
risc_acc = (int32_t)res; risc_acc = (int64_t)res;
SET_ZN(res); SET_ZN(res);
risc_inhibit_interrupt = 1;
uint16_t opcode = RISCReadWord(risc_pc, RISC);
while ((opcode >> 10) == 20)
{
IMM_1 = (opcode >> 5) & 0x1F;
IMM_2 = opcode & 0x1F;
risc_acc += (int32_t)((int16_t)RN * (int16_t)RM);
risc_pc += 2;
opcode = RISCReadWord(risc_pc, RISC);
}
if ((opcode >> 10) == 19)
{
RN = risc_acc;
risc_pc += 2;
}
} }
RISC_OPCODE(neg) RISC_OPCODE(neg)