revert some of baa3bdf948, as it caused regressions elsewhere, make GPU interrupts not stupid (makes Myst stop crashing with NTSC)
This commit is contained in:
CasualPokePlayer
parent
baa3bdf948
commit
f1a3e02e89
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@ -23,8 +23,6 @@
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#include "jerry.h"
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#include "m68000/m68kinterface.h"
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bool IMASKCleared = false;
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// DSP flags (old--have to get rid of this crap)
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#define CINT0FLAG 0x00200
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@ -187,6 +185,9 @@ uint32_t dsp_reg_bank_0[32], dsp_reg_bank_1[32];
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static uint32_t dsp_opcode_first_parameter;
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static uint32_t dsp_opcode_second_parameter;
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static bool IMASKCleared;
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static uint32_t dsp_inhibit_interrupt;
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#define DSP_RUNNING (dsp_control & 0x01)
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static uint8_t branch_condition_table[32 * 8];
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@ -392,7 +393,7 @@ void DSPWriteLong(uint32_t offset, uint32_t data, uint32_t who)
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{
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case 0x00:
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{
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IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK);
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IMASKCleared |= (dsp_flags & IMASK) && !(data & IMASK);
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dsp_flags = data & (~IMASK);
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dsp_flag_z = dsp_flags & 0x01;
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@ -582,18 +583,21 @@ void DSPExec(int32_t cycles)
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{
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MAYBE_CALLBACK(DSPTraceCallback, dsp_pc, dsp_reg);
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if (IMASKCleared)
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if (IMASKCleared && !dsp_inhibit_interrupt)
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{
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DSPHandleIRQsNP();
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IMASKCleared = false;
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}
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dsp_inhibit_interrupt = 0;
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uint16_t opcode = DSPReadWord(dsp_pc, DSP);
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uint32_t index = opcode >> 10;
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dsp_opcode_first_parameter = (opcode >> 5) & 0x1F;
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dsp_opcode_second_parameter = opcode & 0x1F;
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dsp_pc += 2;
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dsp_opcode[index]();
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cycles -= dsp_opcode_cycles[index];
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}
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}
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@ -182,6 +182,9 @@ static uint32_t * gpu_alternate_reg;
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static uint32_t gpu_opcode_first_parameter;
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static uint32_t gpu_opcode_second_parameter;
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static bool IMASKCleared;
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static uint32_t gpu_inhibit_interrupt;
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#define GPU_RUNNING (gpu_control & 0x01)
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static uint8_t branch_condition_table[32 * 8];
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@ -414,15 +417,14 @@ void GPUWriteLong(uint32_t offset, uint32_t data, uint32_t who)
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{
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case 0x00:
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{
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bool IMASKCleared = (gpu_flags & IMASK) && !(data & IMASK);
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IMASKCleared |= (gpu_flags & IMASK) && !(data & IMASK);
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gpu_flags = data & (~IMASK);
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gpu_flag_z = gpu_flags & ZERO_FLAG;
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gpu_flag_c = (gpu_flags & CARRY_FLAG) >> 1;
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gpu_flag_n = (gpu_flags & NEGA_FLAG) >> 2;
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GPUUpdateRegisterBanks();
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gpu_control &= ~((gpu_flags & CINT04FLAGS) >> 3);
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if (IMASKCleared)
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GPUHandleIRQs();
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break;
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}
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case 0x04:
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@ -566,6 +568,7 @@ void GPUReset(void)
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gpu_reg[i] = gpu_alternate_reg[i] = 0x00000000;
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gpu_flag_z = gpu_flag_n = gpu_flag_c = 0;
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IMASKCleared = false;
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memset(gpu_ram_8, 0xFF, 0x1000);
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for(uint32_t i=0; i<4096; i+=4)
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@ -579,18 +582,19 @@ void GPUDone(void)
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//
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// Main GPU execution core
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//
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void GPUExec(int32_t cycles)
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{
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if (!GPU_RUNNING)
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return;
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GPUHandleIRQs();
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while (cycles > 0 && GPU_RUNNING)
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{
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MAYBE_CALLBACK(GPUTraceCallback, gpu_pc, gpu_reg);
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if (IMASKCleared && !gpu_inhibit_interrupt)
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{
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GPUHandleIRQs();
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IMASKCleared = false;
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}
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gpu_inhibit_interrupt = 0;
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uint16_t opcode = GPUReadWord(gpu_pc, GPU);
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uint32_t index = opcode >> 10;
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gpu_opcode_first_parameter = (opcode >> 5) & 0x1F;
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@ -2,7 +2,7 @@
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#if RISC == 3
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#define RISC_OPCODE(op) static void gpu_opcode_##op(void)
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#define risc_opcode gpu_opcode
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#define risc_inhibit_interrupt gpu_inhibit_interrupt
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#define IMM_1 gpu_opcode_first_parameter
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#define IMM_2 gpu_opcode_second_parameter
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#define risc_flag_n gpu_flag_n
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@ -17,12 +17,13 @@
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#define risc_div_control gpu_div_control
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#define risc_remain gpu_remain
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#define IS_RISC_RAM(x) x >= GPU_WORK_RAM_BASE && x <= (GPU_WORK_RAM_BASE + 0xFFF)
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#define RISCExec(x) GPUExec(x)
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#define RISCReadWord(x, y) GPUReadWord(x, y)
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#define RISCReadLong(x, y) GPUReadLong(x, y)
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#define RISCWriteLong(x, y, z) GPUWriteLong(x, y, z)
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#elif RISC == 2
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#define RISC_OPCODE(op) static void dsp_opcode_##op(void)
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#define risc_opcode dsp_opcode
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#define risc_inhibit_interrupt dsp_inhibit_interrupt
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#define IMM_1 dsp_opcode_first_parameter
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#define IMM_2 dsp_opcode_second_parameter
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#define risc_flag_n dsp_flag_n
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@ -37,6 +38,7 @@
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#define risc_div_control dsp_div_control
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#define risc_remain dsp_remain
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#define IS_RISC_RAM(x) x >= DSP_WORK_RAM_BASE && x <= (DSP_WORK_RAM_BASE + 0x1FFF)
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#define RISCExec(x) DSPExec(x)
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#define RISCReadWord(x, y) DSPReadWord(x, y)
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#define RISCReadLong(x, y) DSPReadLong(x, y)
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#define RISCWriteLong(x, y, z) DSPWriteLong(x, y, z)
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@ -83,10 +85,8 @@ RISC_OPCODE(jump)
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if (BRANCH_CONDITION(IMM_2))
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{
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uint32_t delayed_pc = RM;
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uint16_t opcode = RISCReadWord(risc_pc, RISC);
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IMM_1 = (opcode >> 5) & 0x1F;
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IMM_2 = opcode & 0x1F;
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risc_opcode[opcode >> 10]();
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risc_inhibit_interrupt = 1;
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RISCExec(1);
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risc_pc = delayed_pc;
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}
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}
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@ -99,10 +99,8 @@ RISC_OPCODE(jr)
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{
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int32_t offset = (IMM_1 > 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1);
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int32_t delayed_pc = risc_pc + (offset * 2);
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uint16_t opcode = RISCReadWord(risc_pc, RISC);
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IMM_1 = (opcode >> 5) & 0x1F;
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IMM_2 = opcode & 0x1F;
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risc_opcode[opcode >> 10]();
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risc_inhibit_interrupt = 1;
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RISCExec(1);
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risc_pc = delayed_pc;
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}
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}
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@ -334,7 +332,9 @@ RISC_OPCODE(moveq)
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RISC_OPCODE(resmac)
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{
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RN = risc_acc;
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RN = (uint32_t)risc_acc;
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//this makes Club Drive sound ok, but it has missing sounds and other games/bios suffer
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//risc_inhibit_interrupt = 1;
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}
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RISC_OPCODE(imult)
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@ -381,7 +381,8 @@ RISC_OPCODE(addqt)
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RISC_OPCODE(imacn)
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{
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int32_t res = (int16_t)RM * (int16_t)RN;
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risc_acc += res;
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risc_acc += (int64_t)res;
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risc_inhibit_interrupt = 1;
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}
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RISC_OPCODE(mtoi)
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@ -421,6 +422,7 @@ RISC_OPCODE(mmult)
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int64_t accum = 0;
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uint32_t res;
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// remove the + 2 and change the 4s to 2 for Baldies to sound ok, screws up bios however
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if (!(risc_matrix_control & 0x10))
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{
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for (int i = 0; i < count; i++)
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@ -431,9 +433,9 @@ RISC_OPCODE(mmult)
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else
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a = (int16_t)(risc_alternate_reg[IMM_1 + (i >> 1)] & 0xffff);
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int16_t b = (int16_t)RISCReadWord(addr, RISC);
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int16_t b = (int16_t)RISCReadWord(addr + 2, RISC);
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accum += a * b;
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addr += 2;
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addr += 4;
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}
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}
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else
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@ -448,7 +450,7 @@ RISC_OPCODE(mmult)
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int16_t b = (int16_t)RISCReadWord(addr, RISC);
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accum += a * b;
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addr += 2 * count;
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addr += 4 * count;
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}
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}
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@ -488,24 +490,10 @@ RISC_OPCODE(div)
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RISC_OPCODE(imultn)
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{
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uint32_t res = (int16_t)RN * (int16_t)RM;
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risc_acc = (int32_t)res;
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uint32_t res = (int32_t)((int16_t)RN * (int16_t)RM);
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risc_acc = (int64_t)res;
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SET_ZN(res);
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uint16_t opcode = RISCReadWord(risc_pc, RISC);
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while ((opcode >> 10) == 20)
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{
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IMM_1 = (opcode >> 5) & 0x1F;
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IMM_2 = opcode & 0x1F;
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risc_acc += (int32_t)((int16_t)RN * (int16_t)RM);
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risc_pc += 2;
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opcode = RISCReadWord(risc_pc, RISC);
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}
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if ((opcode >> 10) == 19)
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{
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RN = risc_acc;
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risc_pc += 2;
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}
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risc_inhibit_interrupt = 1;
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}
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RISC_OPCODE(neg)
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