From e96912dab0f92165218e85fb3a33476853fb7769 Mon Sep 17 00:00:00 2001 From: beirich Date: Thu, 27 Oct 2011 03:06:33 +0000 Subject: [PATCH] 68000: fix dumb MULS/MULU/DIVS/DIVU bug --- .../CPUs/68000/Instructions/IntegerMath.cs | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/BizHawk.Emulation/CPUs/68000/Instructions/IntegerMath.cs b/BizHawk.Emulation/CPUs/68000/Instructions/IntegerMath.cs index 7190c3871f..259d99642b 100644 --- a/BizHawk.Emulation/CPUs/68000/Instructions/IntegerMath.cs +++ b/BizHawk.Emulation/CPUs/68000/Instructions/IntegerMath.cs @@ -969,7 +969,7 @@ namespace BizHawk.Emulation.CPUs.M68000 void MULU() { - int dreg = (op >> 9) & 3; + int dreg = (op >> 9) & 7; int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; @@ -986,11 +986,11 @@ namespace BizHawk.Emulation.CPUs.M68000 void MULU_Disasm(DisassemblyInfo info) { - int dreg = (op >> 9) & 3; + int dreg = (op >> 9) & 7; int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; - int pc = info.PC; + int pc = info.PC + 2; info.Mnemonic = "mulu"; info.Args = String.Format("{0}, D{1}", DisassembleValue(mode, reg, 2, ref pc), dreg); info.Length = pc - info.PC; @@ -998,7 +998,7 @@ namespace BizHawk.Emulation.CPUs.M68000 void MULS() { - int dreg = (op >> 9) & 3; + int dreg = (op >> 9) & 7; int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; @@ -1015,11 +1015,11 @@ namespace BizHawk.Emulation.CPUs.M68000 void MULS_Disasm(DisassemblyInfo info) { - int dreg = (op >> 9) & 3; + int dreg = (op >> 9) & 7; int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; - int pc = info.PC; + int pc = info.PC + 2; info.Mnemonic = "muls"; info.Args = String.Format("{0}, D{1}", DisassembleValue(mode, reg, 2, ref pc), dreg); info.Length = pc - info.PC; @@ -1027,7 +1027,7 @@ namespace BizHawk.Emulation.CPUs.M68000 void DIVU() { - int dreg = (op >> 9) & 3; + int dreg = (op >> 9) & 7; int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; @@ -1051,11 +1051,11 @@ namespace BizHawk.Emulation.CPUs.M68000 void DIVU_Disasm(DisassemblyInfo info) { - int dreg = (op >> 9) & 3; + int dreg = (op >> 9) & 7; int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; - int pc = info.PC; + int pc = info.PC + 2; info.Mnemonic = "divu"; info.Args = String.Format("{0}, D{1}", DisassembleValue(mode, reg, 2, ref pc), dreg); info.Length = pc - info.PC; @@ -1063,7 +1063,7 @@ namespace BizHawk.Emulation.CPUs.M68000 void DIVS() { - int dreg = (op >> 9) & 3; + int dreg = (op >> 9) & 7; int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; @@ -1087,11 +1087,11 @@ namespace BizHawk.Emulation.CPUs.M68000 void DIVS_Disasm(DisassemblyInfo info) { - int dreg = (op >> 9) & 3; + int dreg = (op >> 9) & 7; int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; - int pc = info.PC; + int pc = info.PC + 2; info.Mnemonic = "divs"; info.Args = String.Format("{0}, D{1}", DisassembleValue(mode, reg, 2, ref pc), dreg); info.Length = pc - info.PC;