diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Interrupts.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Interrupts.cs
index 88e0a264c2..2c4f5c5204 100644
--- a/BizHawk.Emulation.Cores/CPUs/Z80A/Interrupts.cs
+++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Interrupts.cs
@@ -83,8 +83,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 		}
 
 		// Interrupt mode 2 uses the I vector combined with a byte on the data bus
-		// Again for now we assume only a 0 on the data bus and jump to (0xI00)
-		private void INTERRUPT_2(ushort src)
+		private void INTERRUPT_2()
 		{
 			cur_instr = new ushort[]
 						{IDLE,
diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/NewDisassembler.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/NewDisassembler.cs
index effe7400df..8bc3938c7d 100644
--- a/BizHawk.Emulation.Cores/CPUs/Z80A/NewDisassembler.cs
+++ b/BizHawk.Emulation.Cores/CPUs/Z80A/NewDisassembler.cs
@@ -438,7 +438,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 			// handle case of addr wrapping around at 16 bit boundary
 			if (addr < start_addr)
 			{
-				size = addr + 1;
+				size = (0x10000 + addr) - start_addr;
 			}
 
 			return temp;
diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/ReadMe.txt b/BizHawk.Emulation.Cores/CPUs/Z80A/ReadMe.txt
index d11f79b637..10804fde94 100644
--- a/BizHawk.Emulation.Cores/CPUs/Z80A/ReadMe.txt
+++ b/BizHawk.Emulation.Cores/CPUs/Z80A/ReadMe.txt
@@ -1,8 +1,7 @@
 TODO: 
 
-Mode 0 and 2 interrupts
+Mode 0
 Check T-cycle level memory access timing
 Check R register 
 new tests for WZ Registers
 Memory refresh - IR is pushed onto the address bus at instruction start, does anything need this?
-Data Bus - For mode zero and 2 interrupts, need a system that uses it to test
diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs
index 182056f026..25992d5b81 100644
--- a/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs
+++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs
@@ -107,7 +107,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 		public Func<ushort, byte> ReadHardware;
 		public Action<ushort, byte> WriteHardware;
 
-		// Data BUs
+		// Data Bus
 		// Interrupting Devices are responsible for putting a value onto the data bus
 		// for as long as the interrupt is valid
 		public Func<byte> FetchDB;
@@ -196,9 +196,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 								INTERRUPT_1();
 								break;
 							case 2:
-								// Low byte of interrupt vector comes from data bus
-								// We'll assume it's zero for now
-								INTERRUPT_2(0);
+								INTERRUPT_2();
 								break;
 						}
 						IRQCallback();
@@ -321,9 +319,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 									INTERRUPT_1();
 									break;
 								case 2:
-									// Low byte of interrupt vector comes from data bus
-									// We'll assume it's zero for now
-									INTERRUPT_2(0);
+									INTERRUPT_2();
 									break;
 							}
 							IRQCallback();
@@ -391,9 +387,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 								INTERRUPT_1();
 								break;
 							case 2:
-								// Low byte of interrupt vector comes from data bus
-								// We'll assume it's zero for now
-								INTERRUPT_2(0);
+								INTERRUPT_2();
 								break;
 						}
 						IRQCallback();
@@ -663,8 +657,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 					FlagI ? "E" : "e")
 			};
 		}
-		// State Save/Load
 
+		// State Save/Load
 		public void SyncState(Serializer ser)
 		{
 			ser.BeginSection("Z80A");