same for mdec, nothing to see here
This commit is contained in:
zeromus
parent
e2389e25d7
commit
d8fad23324
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@ -1,25 +1,25 @@
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/******************************************************************************/
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/* Mednafen Sony PS1 Emulation Module */
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/******************************************************************************/
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/* mdec.cpp:
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** Copyright (C) 2011-2016 Mednafen Team
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**
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** This program is free software; you can redistribute it and/or
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** modify it under the terms of the GNU General Public License
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** as published by the Free Software Foundation; either version 2
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** of the License, or (at your option) any later version.
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**
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** This program is distributed in the hope that it will be useful,
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** but WITHOUT ANY WARRANTY; without even the implied warranty of
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** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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** GNU General Public License for more details.
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**
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** You should have received a copy of the GNU General Public License
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** along with this program; if not, write to the Free Software Foundation, Inc.,
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** 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#pragma GCC optimize ("unroll-loops")
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/******************************************************************************/
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/* Mednafen Sony PS1 Emulation Module */
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/******************************************************************************/
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/* mdec.cpp:
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** Copyright (C) 2011-2016 Mednafen Team
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**
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** This program is free software; you can redistribute it and/or
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** modify it under the terms of the GNU General Public License
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** as published by the Free Software Foundation; either version 2
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** of the License, or (at your option) any later version.
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**
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** This program is distributed in the hope that it will be useful,
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** but WITHOUT ANY WARRANTY; without even the implied warranty of
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** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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** GNU General Public License for more details.
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**
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** You should have received a copy of the GNU General Public License
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** along with this program; if not, write to the Free Software Foundation, Inc.,
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** 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#pragma GCC optimize ("unroll-loops")
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/*
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MDEC_READ_FIFO(tfr) vs InCounter vs MDEC_DMACanRead() is a bit fragile right now. Actually, the entire horrible state machine monstrosity is fragile.
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@ -73,8 +73,8 @@
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#include <emmintrin.h>
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#endif
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#if 0 //defined(HAVE_NEON_INTRINSICS)
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#include <arm_neon.h>
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#if 0 //defined(HAVE_NEON_INTRINSICS)
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#include <arm_neon.h>
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#endif
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#if defined(HAVE_ALTIVEC_INTRINSICS) && defined(HAVE_ALTIVEC_H)
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@ -90,7 +90,7 @@ namespace MDFN_IEN_PSX
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static int32 ClockCounter;
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static unsigned MDRPhase;
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static FastFIFO<uint32, 0x20> InFIFO;
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static FastFIFO<uint32, 0x20> InFIFO;
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static FastFIFO<uint32, 0x20> OutFIFO;
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static int8 block_y[8][8];
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@ -242,125 +242,125 @@ static INLINE int8 Mask9ClampS8(int32 v)
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return v;
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}
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////////////////////////
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//
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//
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#pragma GCC push_options
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#if defined(__SSE2__) || (defined(ARCH_X86) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)))
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//
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//
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//
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#pragma GCC target("sse2")
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template<typename T>
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static INLINE void IDCT_1D_Multi(int16 *in_coeff, T *out_coeff)
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{
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for(unsigned col = 0; col < 8; col++)
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{
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__m128i c = _mm_load_si128((__m128i *)&in_coeff[(col * 8)]);
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for(unsigned x = 0; x < 8; x++)
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{
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__m128i sum;
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__m128i m;
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alignas(16) int32 tmp[4];
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m = _mm_load_si128((__m128i *)&IDCTMatrix[(x * 8)]);
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sum = _mm_madd_epi16(m, c);
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sum = _mm_add_epi32(sum, _mm_shuffle_epi32(sum, (3 << 0) | (2 << 2) | (1 << 4) | (0 << 6)));
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sum = _mm_add_epi32(sum, _mm_shuffle_epi32(sum, (1 << 0) | (0 << 2)));
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//_mm_store_ss((float *)&tmp[0], (__m128)sum);
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_mm_store_si128((__m128i*)tmp, sum);
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if(sizeof(T) == 1)
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out_coeff[(col * 8) + x] = Mask9ClampS8((tmp[0] + 0x4000) >> 15);
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else
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out_coeff[(x * 8) + col] = (tmp[0] + 0x4000) >> 15;
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}
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}
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}
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//
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//
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//
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#elif 0 //defined(HAVE_NEON_INTRINSICS)
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//
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//
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//
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template<typename T>
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static INLINE void IDCT_1D_Multi(int16 *in_coeff, T *out_coeff)
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{
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for(unsigned col = 0; col < 8; col++)
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{
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register int16x4_t c0 = vld1_s16(MDFN_ASSUME_ALIGNED(in_coeff + col * 8 + 0, sizeof(int16x4_t)));
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register int16x4_t c1 = vld1_s16(MDFN_ASSUME_ALIGNED(in_coeff + col * 8 + 4, sizeof(int16x4_t)));
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int32 buf[8];
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for(unsigned x = 0; x < 8; x++)
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{
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register int32x4_t accum;
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register int32x2_t sum2;
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accum = vdupq_n_s32(0);
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accum = vmlal_s16(accum, c0, vld1_s16(MDFN_ASSUME_ALIGNED(IDCTMatrix + x * 8 + 0, sizeof(int16x4_t))));
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accum = vmlal_s16(accum, c1, vld1_s16(MDFN_ASSUME_ALIGNED(IDCTMatrix + x * 8 + 4, sizeof(int16x4_t))));
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sum2 = vadd_s32(vget_high_s32(accum), vget_low_s32(accum));
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sum2 = vpadd_s32(sum2, sum2);
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vst1_lane_s32(buf + x, sum2, 0);
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}
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for(unsigned x = 0; x < 8; x++)
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{
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if(sizeof(T) == 1)
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out_coeff[(col * 8) + x] = Mask9ClampS8((buf[x] + 0x4000) >> 15);
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else
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out_coeff[(x * 8) + col] = (buf[x] + 0x4000) >> 15;
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}
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}
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}
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//
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//
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//
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#else
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//
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//
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//
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template<typename T>
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static INLINE void IDCT_1D_Multi(int16 *in_coeff, T *out_coeff)
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{
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for(unsigned col = 0; col < 8; col++)
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{
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for(unsigned x = 0; x < 8; x++)
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{
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int32 sum = 0;
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for(unsigned u = 0; u < 8; u++)
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{
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sum += (in_coeff[(col * 8) + u] * IDCTMatrix[(x * 8) + u]);
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}
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if(sizeof(T) == 1)
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out_coeff[(col * 8) + x] = Mask9ClampS8((sum + 0x4000) >> 15);
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else
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out_coeff[(x * 8) + col] = (sum + 0x4000) >> 15;
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}
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}
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}
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//
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//
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//
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#endif
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static NO_INLINE void IDCT(int16 *in_coeff, int8 *out_coeff)
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{
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alignas(16) int16 tmpbuf[64];
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IDCT_1D_Multi<int16>(in_coeff, tmpbuf);
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IDCT_1D_Multi<int8>(tmpbuf, out_coeff);
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}
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#pragma GCC pop_options
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//
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//
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////////////////////////
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//
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//
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#pragma GCC push_options
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#if defined(__SSE2__) || (defined(ARCH_X86) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)))
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//
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//
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//
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#pragma GCC target("sse2")
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template<typename T>
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static INLINE void IDCT_1D_Multi(int16 *in_coeff, T *out_coeff)
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{
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for(unsigned col = 0; col < 8; col++)
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{
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__m128i c = _mm_load_si128((__m128i *)&in_coeff[(col * 8)]);
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for(unsigned x = 0; x < 8; x++)
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{
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__m128i sum;
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__m128i m;
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alignas(16) int32 tmp[4];
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m = _mm_load_si128((__m128i *)&IDCTMatrix[(x * 8)]);
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sum = _mm_madd_epi16(m, c);
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sum = _mm_add_epi32(sum, _mm_shuffle_epi32(sum, (3 << 0) | (2 << 2) | (1 << 4) | (0 << 6)));
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sum = _mm_add_epi32(sum, _mm_shuffle_epi32(sum, (1 << 0) | (0 << 2)));
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//_mm_store_ss((float *)&tmp[0], (__m128)sum);
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_mm_store_si128((__m128i*)tmp, sum);
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if(sizeof(T) == 1)
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out_coeff[(col * 8) + x] = Mask9ClampS8((tmp[0] + 0x4000) >> 15);
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else
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out_coeff[(x * 8) + col] = (tmp[0] + 0x4000) >> 15;
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}
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}
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}
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//
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//
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//
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#elif 0 //defined(HAVE_NEON_INTRINSICS)
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//
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//
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//
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template<typename T>
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static INLINE void IDCT_1D_Multi(int16 *in_coeff, T *out_coeff)
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{
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for(unsigned col = 0; col < 8; col++)
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{
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register int16x4_t c0 = vld1_s16(MDFN_ASSUME_ALIGNED(in_coeff + col * 8 + 0, sizeof(int16x4_t)));
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register int16x4_t c1 = vld1_s16(MDFN_ASSUME_ALIGNED(in_coeff + col * 8 + 4, sizeof(int16x4_t)));
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int32 buf[8];
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for(unsigned x = 0; x < 8; x++)
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{
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register int32x4_t accum;
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register int32x2_t sum2;
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accum = vdupq_n_s32(0);
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accum = vmlal_s16(accum, c0, vld1_s16(MDFN_ASSUME_ALIGNED(IDCTMatrix + x * 8 + 0, sizeof(int16x4_t))));
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accum = vmlal_s16(accum, c1, vld1_s16(MDFN_ASSUME_ALIGNED(IDCTMatrix + x * 8 + 4, sizeof(int16x4_t))));
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sum2 = vadd_s32(vget_high_s32(accum), vget_low_s32(accum));
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sum2 = vpadd_s32(sum2, sum2);
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vst1_lane_s32(buf + x, sum2, 0);
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}
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for(unsigned x = 0; x < 8; x++)
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{
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if(sizeof(T) == 1)
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out_coeff[(col * 8) + x] = Mask9ClampS8((buf[x] + 0x4000) >> 15);
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else
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out_coeff[(x * 8) + col] = (buf[x] + 0x4000) >> 15;
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}
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}
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}
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//
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//
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//
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#else
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//
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//
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//
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template<typename T>
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static INLINE void IDCT_1D_Multi(int16 *in_coeff, T *out_coeff)
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{
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for(unsigned col = 0; col < 8; col++)
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{
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for(unsigned x = 0; x < 8; x++)
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{
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int32 sum = 0;
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for(unsigned u = 0; u < 8; u++)
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{
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sum += (in_coeff[(col * 8) + u] * IDCTMatrix[(x * 8) + u]);
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}
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if(sizeof(T) == 1)
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out_coeff[(col * 8) + x] = Mask9ClampS8((sum + 0x4000) >> 15);
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else
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out_coeff[(x * 8) + col] = (sum + 0x4000) >> 15;
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}
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}
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}
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//
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//
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//
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#endif
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static NO_INLINE void IDCT(int16 *in_coeff, int8 *out_coeff)
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{
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alignas(16) int16 tmpbuf[64];
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IDCT_1D_Multi<int16>(in_coeff, tmpbuf);
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IDCT_1D_Multi<int8>(tmpbuf, out_coeff);
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}
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#pragma GCC pop_options
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//
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//
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///////////////////////
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static INLINE void YCbCr_to_RGB(const int8 y, const int8 cb, const int8 cr, int &r, int &g, int &b)
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@ -519,9 +519,9 @@ static INLINE void WriteImageData(uint16 V, int32* eat_cycles)
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int ci = sign_10_to_s16(V & 0x3FF);
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int tmp;
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if(q != 0)
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tmp = (int32)((uint32)(ci * q) << 4) + (ci ? ((ci < 0) ? 8 : -8) : 0);
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else
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if(q != 0)
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tmp = (int32)((uint32)(ci * q) << 4) + (ci ? ((ci < 0) ? 8 : -8) : 0);
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else
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tmp = (uint32)(ci * 2) << 4;
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// Not sure if it should be 0x3FFF or 0x3FF0 or maybe 0x3FF8?
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@ -552,9 +552,9 @@ static INLINE void WriteImageData(uint16 V, int32* eat_cycles)
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int ci = sign_10_to_s16(V & 0x3FF);
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int tmp;
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if(q != 0)
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tmp = (int32)((uint32)((ci * q) >> 3) << 4) + (ci ? ((ci < 0) ? 8 : -8) : 0);
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else
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if(q != 0)
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tmp = (int32)((uint32)((ci * q) >> 3) << 4) + (ci ? ((ci < 0) ? 8 : -8) : 0);
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else
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tmp = (uint32)(ci * 2) << 4;
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// Not sure if it should be 0x3FFF or 0x3FF0 or maybe 0x3FF8?
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@ -572,16 +572,16 @@ static INLINE void WriteImageData(uint16 V, int32* eat_cycles)
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switch(DecodeWB)
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{
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case 0: IDCT(Coeff, MDAP(block_cr)); break;
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case 1: IDCT(Coeff, MDAP(block_cb)); break;
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case 2: IDCT(Coeff, MDAP(block_y)); break;
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case 3: IDCT(Coeff, MDAP(block_y)); break;
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case 4: IDCT(Coeff, MDAP(block_y)); break;
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case 0: IDCT(Coeff, MDAP(block_cr)); break;
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case 1: IDCT(Coeff, MDAP(block_cb)); break;
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case 2: IDCT(Coeff, MDAP(block_y)); break;
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case 3: IDCT(Coeff, MDAP(block_y)); break;
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case 4: IDCT(Coeff, MDAP(block_y)); break;
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case 5: IDCT(Coeff, MDAP(block_y)); break;
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}
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// Timing in the PS1 MDEC is complex due to (apparent) pipelining, but the average when decoding a large number of blocks is
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// about 512.
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// Timing in the PS1 MDEC is complex due to (apparent) pipelining, but the average when decoding a large number of blocks is
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// about 512.
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*eat_cycles += 512;
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if(DecodeWB >= 2)
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@ -604,7 +604,7 @@ static INLINE void WriteImageData(uint16 V, int32* eat_cycles)
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//
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#define MDEC_WAIT_COND(n) { case __COUNTER__: if(!(n)) { MDRPhase = __COUNTER__ - MDRPhaseBias - 1; return; } }
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#define MDEC_WRITE_FIFO(n) { MDEC_WAIT_COND(OutFIFO.CanWrite()); OutFIFO.Write(n); }
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#define MDEC_WRITE_FIFO(n) { MDEC_WAIT_COND(OutFIFO.CanWrite()); OutFIFO.Write(n); }
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#define MDEC_READ_FIFO(n) { MDEC_WAIT_COND(InFIFO.CanRead()); n = InFIFO.Read(); }
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#define MDEC_EAT_CLOCKS(n) { ClockCounter -= (n); MDEC_WAIT_COND(ClockCounter > 0); }
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@ -682,7 +682,7 @@ MDFN_FASTCALL void MDEC_Run(int32 clocks)
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PixelBufferReadOffset = 0;
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while(PixelBufferReadOffset < PixelBufferCount32)
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{
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MDEC_WRITE_FIFO(MDFN_de32lsb<true>(&PixelBuffer.pix32[PixelBufferReadOffset++]));
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MDEC_WRITE_FIFO((MDFN_de32lsb<true>(&PixelBuffer.pix32[PixelBufferReadOffset++])));
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}
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} while(InCounter != 0xFFFF);
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}
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@ -746,52 +746,51 @@ MDFN_FASTCALL void MDEC_Run(int32 clocks)
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}
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#endif
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MDFN_FASTCALL void MDEC_DMAWrite(uint32 V)
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{
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if(InFIFO.CanWrite())
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{
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InFIFO.Write(V);
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MDEC_Run(0);
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}
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else
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{
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PSX_DBG(PSX_DBG_WARNING, "[MDEC] DMA write when input FIFO is full!!\n");
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}
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}
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MDFN_FASTCALL uint32 MDEC_DMARead(uint32* offs)
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{
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uint32 V = 0;
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*offs = 0;
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if(MDFN_LIKELY(OutFIFO.CanRead()))
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{
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V = OutFIFO.Read();
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*offs = (RAMOffsetY & 0x7) * RAMOffsetWWS;
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if(RAMOffsetY & 0x08)
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{
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*offs = (*offs - RAMOffsetWWS*7);
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}
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|
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RAMOffsetCounter--;
|
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if(!RAMOffsetCounter)
|
||||
{
|
||||
RAMOffsetCounter = RAMOffsetWWS;
|
||||
RAMOffsetY++;
|
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}
|
||||
|
||||
MDEC_Run(0);
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||||
}
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||||
else
|
||||
{
|
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PSX_DBG(PSX_DBG_WARNING, "[MDEC] DMA read when output FIFO is empty!\n");
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||||
}
|
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|
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return(V);
|
||||
MDFN_FASTCALL void MDEC_DMAWrite(uint32 V)
|
||||
{
|
||||
if(InFIFO.CanWrite())
|
||||
{
|
||||
InFIFO.Write(V);
|
||||
MDEC_Run(0);
|
||||
}
|
||||
else
|
||||
{
|
||||
PSX_DBG(PSX_DBG_WARNING, "[MDEC] DMA write when input FIFO is full!!\n");
|
||||
}
|
||||
}
|
||||
|
||||
MDFN_FASTCALL uint32 MDEC_DMARead(uint32* offs)
|
||||
{
|
||||
uint32 V = 0;
|
||||
|
||||
*offs = 0;
|
||||
|
||||
if(MDFN_LIKELY(OutFIFO.CanRead()))
|
||||
{
|
||||
V = OutFIFO.Read();
|
||||
|
||||
*offs = (RAMOffsetY & 0x7) * RAMOffsetWWS;
|
||||
|
||||
if(RAMOffsetY & 0x08)
|
||||
{
|
||||
*offs = (*offs - RAMOffsetWWS*7);
|
||||
}
|
||||
|
||||
RAMOffsetCounter--;
|
||||
if(!RAMOffsetCounter)
|
||||
{
|
||||
RAMOffsetCounter = RAMOffsetWWS;
|
||||
RAMOffsetY++;
|
||||
}
|
||||
|
||||
MDEC_Run(0);
|
||||
}
|
||||
else
|
||||
{
|
||||
PSX_DBG(PSX_DBG_WARNING, "[MDEC] DMA read when output FIFO is empty!\n");
|
||||
}
|
||||
|
||||
return(V);
|
||||
}
|
||||
|
||||
bool MDEC_DMACanWrite(void)
|
||||
|
|
|
|||
Loading…
Reference in New Issue