simplify atari 7800 mapper code

This commit is contained in:
adelikat 2020-02-18 07:22:56 -06:00
parent 48c9ada3e7
commit d3c048c13c
7 changed files with 238 additions and 278 deletions

View File

@ -15,46 +15,42 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
{
return Core._hsram[addr - 0x1000];
}
return 0xFF;
}
else if (addr < 0x4000)
if (addr < 0x4000)
{
// could be either RAM mirror or ROM
if (addr >= 0x3000 && Core._hsbios != null)
{
return Core._hsbios[addr - 0x3000];
}
else
{
return Core.RAM[0x800 + addr & 0x7FF];
}
return Core.RAM[0x800 + addr & 0x7FF];
}
else if (addr < 0x8000 && Core.is_pokey)
if (addr < 0x8000 && Core.is_pokey)
{
return Core.pokey.ReadReg(addr & 0xF);
}
else
// cartridge and other OPSYS
if (Core._rom.Length >= 0x10000 - addr
&& Core.A7800_control_register.Bit(2))
{
// cartridge and other OPSYS
if ((Core._rom.Length >= 0x10000 - addr) && Core.A7800_control_register.Bit(2))
{
return Core._rom[Core._rom.Length - (0x10000 - addr)];
}
else if (addr >= (0x10000-Core._bios.Length) && !Core.A7800_control_register.Bit(2))
{
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
else
{
return 0x00;
}
return Core._rom[Core._rom.Length - (0x10000 - addr)];
}
if (addr >= (0x10000-Core._bios.Length) && !Core.A7800_control_register.Bit(2))
{
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
return 0x00;
}
public override byte PeekMemory(ushort addr)
{
return ReadMemory(addr);
}
public override byte PeekMemory(ushort addr) => ReadMemory(addr);
public override void WriteMemory(ushort addr, byte value)
{

View File

@ -6,7 +6,7 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
// Mapper only used by F-18 Hornet
public class MapperF18 : MapperBase
{
public byte bank = 0;
private byte _bank;
public override byte ReadMemory(ushort addr)
{
@ -17,49 +17,40 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
{
return Core._hsram[addr - 0x1000];
}
return 0xFF;
}
else if (addr < 0x4000)
if (addr < 0x4000)
{
// could be either RAM mirror or ROM
if (addr >= 0x3000 && Core._hsbios != null)
{
return Core._hsbios[addr - 0x3000];
}
else
{
return Core.RAM[0x800 + addr & 0x7FF];
}
return Core.RAM[0x800 + addr & 0x7FF];
}
else
// cartridge and other OPSYS
if (addr >= (0x10000 - Core._bios.Length) && !Core.A7800_control_register.Bit(2))
{
// cartridge and other OPSYS
if (addr >= (0x10000 - Core._bios.Length) && !Core.A7800_control_register.Bit(2))
{
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
else
{
if (addr >= 0x8000)
{
// top 32k is fixed
return Core._rom[Core._rom.Length - (0x10000 - addr)];
}
else
{
// return whichever extra 16k bank is swapped in
int temp_addr = addr - 0x4000;
return Core._rom[temp_addr + bank * 0x4000];
}
}
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
if (addr >= 0x8000)
{
// top 32k is fixed
return Core._rom[Core._rom.Length - (0x10000 - addr)];
}
// return whichever extra 16k bank is swapped in
int tempAddr = addr - 0x4000;
return Core._rom[tempAddr + _bank * 0x4000];
}
public override byte PeekMemory(ushort addr)
{
return ReadMemory(addr);
}
public override byte PeekMemory(ushort addr) => ReadMemory(addr);
public override void WriteMemory(ushort addr, byte value)
{
@ -87,8 +78,8 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
// cartridge and other OPSYS
if (addr == 0x8000) // might be other addresses, but only 0x8000 is used
{
bank = (byte)(value & 3);
bank -= 1;
_bank = (byte)(value & 3);
_bank -= 1;
}
}
}
@ -100,7 +91,7 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
public override void SyncState(Serializer ser)
{
ser.Sync("Bank", ref bank);
ser.Sync("Bank", ref _bank);
}
}
}

View File

@ -3,57 +3,56 @@ using BizHawk.Common.NumberExtensions;
namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
{
// Rescue on Fractulus has unique RAM mapping
// Rescue on Fractalus has unique RAM mapping
public class MapperFractalus : MapperBase
{
public byte[] RAM = new byte[0x800];
private byte[] RAM = new byte[0x800];
public override byte ReadMemory(ushort addr)
{
if (addr >=0x1000 && addr < 0x1800)
if (addr >= 0x1000 && addr < 0x1800)
{
//could be hsbios RAM here
if (Core._hsbios != null)
{
return Core._hsram[addr - 0x1000];
}
return 0xFF;
}
else if (addr < 0x4000)
if (addr < 0x4000)
{
// could be either RAM mirror or ROM
if (addr >= 0x3000 && Core._hsbios != null)
{
return Core._hsbios[addr - 0x3000];
}
else
{
return Core.RAM[0x800 + addr & 0x7FF];
}
}
else
{
// cartridge and other OPSYS
if ((Core._rom.Length >= 0x10000 - addr) && Core.A7800_control_register.Bit(2))
{
return Core._rom[Core._rom.Length - (0x10000 - addr)];
}
else if (addr >= (0x10000-Core._bios.Length) && !Core.A7800_control_register.Bit(2))
{
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
else if (addr >= 0x4000 && addr <0x5000)
{
int temp_ret_1 = ((addr >> 8) & 0xE) >> 1;
int temp_ret_2 = addr & 0xFF;
return RAM[(temp_ret_1 << 8) + temp_ret_2];
}
else
{
return 0x00;
}
return Core.RAM[0x800 + addr & 0x7FF];
}
// cartridge and other OPSYS
if (Core._rom.Length >= 0x10000 - addr
&& Core.A7800_control_register.Bit(2))
{
return Core._rom[Core._rom.Length - (0x10000 - addr)];
}
if (addr >= 0x10000-Core._bios.Length && !Core.A7800_control_register.Bit(2))
{
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
if (addr >= 0x4000 && addr <0x5000)
{
int tempRet1 = ((addr >> 8) & 0xE) >> 1;
int tempRet2 = addr & 0xFF;
return RAM[(tempRet1 << 8) + tempRet2];
}
return 0x00;
}
public override byte PeekMemory(ushort addr)
@ -86,10 +85,10 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
{
if (addr >= 0x4000 && addr < 0x5000)
{
int temp_ret_1 = ((addr >> 8) & 0xE) >> 1;
int temp_ret_2 = addr & 0xFF;
int tempRet1 = ((addr >> 8) & 0xE) >> 1;
int tempRet2 = addr & 0xFF;
RAM[(temp_ret_1 << 8) + temp_ret_2] = value;
RAM[(tempRet1 << 8) + tempRet2] = value;
}
}
}

View File

@ -6,81 +6,73 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
// Mapper only used by Rampage and Double Dragon
public class MapperRampage : MapperBase
{
public byte bank = 0;
private byte _bank;
public override byte ReadMemory(ushort addr)
{
if (addr >= 0x1000 && addr < 0x1800)
{
//could be hsbios RAM here
// could be hsbios RAM here
if (Core._hsbios != null)
{
return Core._hsram[addr - 0x1000];
}
return 0xFF;
}
else if (addr < 0x4000)
if (addr < 0x4000)
{
// could be either RAM mirror or ROM
if (addr >= 0x3000 && Core._hsbios != null)
{
return Core._hsbios[addr - 0x3000];
}
else
{
return Core.RAM[0x800 + addr & 0x7FF];
}
return Core.RAM[0x800 + addr & 0x7FF];
}
else
// cartridge and other OPSYS
if (addr >= (0x10000 - Core._bios.Length) && !Core.A7800_control_register.Bit(2))
{
// cartridge and other OPSYS
if (addr >= (0x10000 - Core._bios.Length) && !Core.A7800_control_register.Bit(2))
{
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
else
{
/*
$4000 -$5fff second 8kb of bank 6
$6000 -$7fff first 8kb of bank 6
$8000 -$9fff second 8kb of bank 7
$e000 -$ffff first 8kb of bank 7
$a000-$dfff Banked
*/
if (addr >= 0x4000 && addr < 0x6000)
{
int temp_addr = addr - 0x4000;
return Core._rom[6 * 0x4000 + 0x2000 + temp_addr];
}
else if (addr >= 0x6000 && addr < 0x8000)
{
int temp_addr = addr - 0x6000;
return Core._rom[6 * 0x4000 + temp_addr];
}
else if (addr >= 0x8000 && addr < 0xA000)
{
int temp_addr = addr - 0x8000;
return Core._rom[7 * 0x4000 + 0x2000 + temp_addr];
}
else if (addr >= 0xA000 && addr < 0xE000)
{
int temp_addr = addr - 0xA000;
return Core._rom[bank * 0x4000 + temp_addr];
}
else
{
int temp_addr = addr - 0xE000;
return Core._rom[7 * 0x4000 + temp_addr];
}
}
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
/*
$4000 -$5fff second 8kb of bank 6
$6000 -$7fff first 8kb of bank 6
$8000 -$9fff second 8kb of bank 7
$e000 -$ffff first 8kb of bank 7
$a000-$dfff Banked
*/
int tempAddr;
if (addr >= 0x4000 && addr < 0x6000)
{
tempAddr = addr - 0x4000;
return Core._rom[6 * 0x4000 + 0x2000 + tempAddr];
}
if (addr >= 0x6000 && addr < 0x8000)
{
tempAddr = addr - 0x6000;
return Core._rom[6 * 0x4000 + tempAddr];
}
if (addr >= 0x8000 && addr < 0xA000)
{
tempAddr = addr - 0x8000;
return Core._rom[7 * 0x4000 + 0x2000 + tempAddr];
}
if (addr >= 0xA000 && addr < 0xE000)
{
tempAddr = addr - 0xA000;
return Core._rom[_bank * 0x4000 + tempAddr];
}
tempAddr = addr - 0xE000;
return Core._rom[7 * 0x4000 + tempAddr];
}
public override byte PeekMemory(ushort addr)
@ -114,7 +106,7 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
// cartridge and other OPSYS
if (addr >= 0xFF80 && addr < 0xFF88) // might be other addresses, but only these are used
{
bank = (byte)(addr & 7);
_bank = (byte)(addr & 7);
}
}
}
@ -126,7 +118,7 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
public override void SyncState(Serializer ser)
{
ser.Sync("Bank", ref bank);
ser.Sync("Bank", ref _bank);
}
}
}

View File

@ -6,8 +6,8 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
// Default Bank Switching Mapper used by most games
public class MapperSG : MapperBase
{
public byte bank = 0;
public byte[] RAM = new byte[0x4000];
private byte _bank;
private byte[] RAM = new byte[0x4000];
public override byte ReadMemory(ushort addr)
{
@ -20,97 +20,83 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
}
return 0xFF;
}
else if (addr < 0x4000)
if (addr < 0x4000)
{
// could be either RAM mirror or ROM
if (addr >= 0x3000 && Core._hsbios != null)
{
return Core._hsbios[addr - 0x3000];
}
else
{
return Core.RAM[0x800 + addr & 0x7FF];
}
return Core.RAM[0x800 + addr & 0x7FF];
}
else
// cartridge and other OPSYS
if (addr >= (0x10000 - Core._bios.Length) && !Core.A7800_control_register.Bit(2))
{
// cartridge and other OPSYS
if (addr >= (0x10000 - Core._bios.Length) && !Core.A7800_control_register.Bit(2))
{
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
else
{
if (addr >= 0xC000)
{
// bank 7 is fixed
return Core._rom[Core._rom.Length - (0x10000 - addr)];
}
else if (addr >= 0x8000)
{
// return whatever bank is there
int temp_addr = addr - 0x8000;
return Core._rom[temp_addr + bank * 0x4000];
}
else
{
if (Core.cart_RAM == 0 && !Core.is_pokey)
{
// return bank 6
int temp_addr = addr - 0x4000;
if (!Core.small_flag)
{
return Core._rom[temp_addr + 6 * 0x4000];
}
else
{
if (Core.PAL_Kara)
{
return Core._rom[temp_addr + 2 * 0x4000];
}
else
{
// Should never get here, but in case we do just return FF
return 0xFF;
}
}
}
else if (Core.cart_RAM > 0)
{
// return RAM
if (Core.cart_RAM == 8 && addr >= 0x6000)
{
return RAM[addr - 0x6000];
}
else if (Core.cart_RAM == 16)
{
return RAM[addr - 0x4000];
}
else
{
// this would coorespond to reading from 0x4000-0x5FFF with only 8k of RAM
// Let's just return FF for now
return 0xFF;
}
}
else if (Core.is_pokey)
{
return Core.pokey.ReadReg(addr & 0xF);
}
else
{
return 0xFF;
}
}
}
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
if (addr >= 0xC000)
{
// bank 7 is fixed
return Core._rom[Core._rom.Length - (0x10000 - addr)];
}
if (addr >= 0x8000)
{
// return whatever bank is there
int tempAddr = addr - 0x8000;
return Core._rom[tempAddr + _bank * 0x4000];
}
if (Core.cart_RAM == 0 && !Core.is_pokey)
{
// return bank 6
int tempAddr = addr - 0x4000;
if (!Core.small_flag)
{
return Core._rom[tempAddr + 6 * 0x4000];
}
if (Core.PAL_Kara)
{
return Core._rom[tempAddr + 2 * 0x4000];
}
// Should never get here, but in case we do just return FF
return 0xFF;
}
if (Core.cart_RAM > 0)
{
// return RAM
if (Core.cart_RAM == 8 && addr >= 0x6000)
{
return RAM[addr - 0x6000];
}
if (Core.cart_RAM == 16)
{
return RAM[addr - 0x4000];
}
// this would correspond to reading from 0x4000-0x5FFF with only 8k of RAM
// Let's just return FF for now
return 0xFF;
}
if (Core.is_pokey)
{
return Core.pokey.ReadReg(addr & 0xF);
}
return 0xFF;
}
public override byte PeekMemory(ushort addr)
{
return ReadMemory(addr);
}
public override byte PeekMemory(ushort addr) => ReadMemory(addr);
public override void WriteMemory(ushort addr, byte value)
{
@ -138,7 +124,7 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
// cartridge and other OPSYS
if (addr>=0x8000)
{
bank = (byte)(value & (Core.small_flag ? 0x3 : mask));
_bank = (byte)(value & (Core.small_flag ? 0x3 : mask));
}
else if (Core.is_pokey)
{
@ -165,7 +151,7 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
public override void SyncState(Serializer ser)
{
ser.Sync("Bank", ref bank);
ser.Sync("Bank", ref _bank);
ser.Sync(nameof(RAM), ref RAM, false);
}
}

View File

@ -7,7 +7,7 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
// Have to add 1 to bank number to get correct bank value
public class MapperSGE : MapperBase
{
public byte bank = 0;
private byte _bank;
public override byte ReadMemory(ushort addr)
{
@ -18,65 +18,59 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
{
return Core._hsram[addr - 0x1000];
}
return 0xFF;
}
else if (addr < 0x4000)
if (addr < 0x4000)
{
// could be either RAM mirror or ROM
if (addr >= 0x3000 && Core._hsbios != null)
{
return Core._hsbios[addr - 0x3000];
}
else if (Core.is_pokey)
if (Core.is_pokey)
{
return Core.pokey.ReadReg(addr & 0xF);
}
else
{
return Core.RAM[0x800 + addr & 0x7FF];
}
return Core.RAM[0x800 + addr & 0x7FF];
}
else
// cartridge and other OPSYS
if (addr >= 0x10000 - Core._bios.Length && !Core.A7800_control_register.Bit(2))
{
// cartridge and other OPSYS
if (addr >= (0x10000 - Core._bios.Length) && !Core.A7800_control_register.Bit(2))
{
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
else
{
if (addr >=0xC000)
{
// bank 7 is fixed
return Core._rom[Core._rom.Length - (0x10000 - addr)];
}
else if (addr >= 0x8000)
{
// return whatever bank is there
// but remember we need to add 1 to adjust for the extra bank at the beginning
int temp_addr = addr - 0x8000;
return Core._rom[temp_addr + (bank + 1) * 0x4000];
}
/*
else if (Core.is_pokey)
{
return Core.pokey.ReadReg(addr & 0xF);
}
*/
else
{
// return the 16k extra ROM (located at beginning of file)
int temp_addr = addr - 0x4000;
return Core._rom[temp_addr];
}
}
return Core._bios[addr - (0x10000 - Core._bios.Length)];
}
if (addr >=0xC000)
{
// bank 7 is fixed
return Core._rom[Core._rom.Length - (0x10000 - addr)];
}
int tempAddr;
if (addr >= 0x8000)
{
// return whatever bank is there
// but remember we need to add 1 to adjust for the extra bank at the beginning
tempAddr = addr - 0x8000;
return Core._rom[tempAddr + (_bank + 1) * 0x4000];
}
/*
if (Core.is_pokey)
{
return Core.pokey.ReadReg(addr & 0xF);
}
*/
// return the 16k extra ROM (located at beginning of file)
tempAddr = addr - 0x4000;
return Core._rom[tempAddr];
}
public override byte PeekMemory(ushort addr)
{
return ReadMemory(addr);
}
public override byte PeekMemory(ushort addr) => ReadMemory(addr);
public override void WriteMemory(ushort addr, byte value)
{
@ -108,7 +102,7 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
// cartridge and other OPSYS
if (addr>=0x8000)
{
bank = (byte)(value & 0x7);
_bank = (byte)(value & 0x7);
}
else if (Core.is_pokey)
{
@ -124,7 +118,7 @@ namespace BizHawk.Emulation.Cores.Atari.A7800Hawk
public override void SyncState(Serializer ser)
{
ser.Sync("Bank", ref bank);
ser.Sync("Bank", ref _bank);
}
}
}

View File

@ -264,6 +264,7 @@
<s:Boolean x:Key="/Default/UserDictionary/Words/=Finetuned/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=Fmpeg/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=fname/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=Fractalus/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=frameadvance/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=FCEUX/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=feos/@EntryIndexedValue">True</s:Boolean>
@ -288,6 +289,7 @@
<s:Boolean x:Key="/Default/UserDictionary/Words/=Homebrew/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=Hotkey/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=Hotkeys/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=hsbios/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=hwnd/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=Intelli/@EntryIndexedValue">True</s:Boolean>
<s:Boolean x:Key="/Default/UserDictionary/Words/=Intellivision/@EntryIndexedValue">True</s:Boolean>