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F8 CPU: Code tidy

This commit is contained in:
ASNiVOR 2021-11-20 22:14:29 +00:00
parent 1c90bbc273
commit cee3d411b9
2 changed files with 56 additions and 84 deletions
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93
src/BizHawk.Emulation.Cores/CPUs/FairchildF8/F3850.Tables.cs
View File

@ -50,7 +50,6 @@
END);
}
/// <summary>
/// LR - LOAD REGISTER
/// The LR group of instructions move one or two bytes of data between a source and destination register.
@ -565,6 +564,11 @@
END);
}
/// <summary>
/// LR - LOAD REGISTER
/// The LR group of instructions move one or two bytes of data between a source and destination register.
/// No status bits are modified.
/// </summary>
private void LR_W_J()
{
PopulateCURINSTR(
@ -580,6 +584,11 @@
END);
}
/// <summary>
/// LR - LOAD REGISTER
/// The LR group of instructions move one or two bytes of data between a source and destination register.
/// No status bits are modified.
/// </summary>
private void LR_J_W()
{
PopulateCURINSTR(
@ -751,7 +760,9 @@
END);
}
/// <summary>
/// Illegal Opcode
/// </summary>
private void ILLEGAL()
{
PopulateCURINSTR(
@ -1064,6 +1075,11 @@
END);
}
/// <summary>
/// LR - LOAD REGISTER
/// The LR group of instructions move one or two bytes of data between a source and destination register.
/// No status bits are modified.
/// </summary>
private void LR_A_ISAR()
{
PopulateCURINSTR(
@ -1074,6 +1090,12 @@
END);
}
/// <summary>
/// LR - LOAD REGISTER
/// The LR group of instructions move one or two bytes of data between a source and destination register.
/// ISAR incremented
/// No status bits are modified.
/// </summary>
private void LR_A_ISAR_INC()
{
PopulateCURINSTR(
@ -1084,6 +1106,12 @@
END);
}
/// <summary>
/// LR - LOAD REGISTER
/// The LR group of instructions move one or two bytes of data between a source and destination register.
/// ISAR deccremented
/// No status bits are modified.
/// </summary>
private void LR_A_ISAR_DEC()
{
PopulateCURINSTR(
@ -1094,6 +1122,11 @@
END);
}
/// <summary>
/// LR - LOAD REGISTER
/// The LR group of instructions move one or two bytes of data between a source and destination register.
/// No status bits are modified.
/// </summary>
private void LR_R_A(byte rIndex)
{
// only scratch registers 0-16
@ -1107,6 +1140,11 @@
END);
}
/// <summary>
/// LR - LOAD REGISTER
/// The LR group of instructions move one or two bytes of data between a source and destination register.
/// No status bits are modified.
/// </summary>
private void LR_ISAR_A()
{
PopulateCURINSTR(
@ -1117,6 +1155,12 @@
END);
}
/// <summary>
/// LR - LOAD REGISTER
/// The LR group of instructions move one or two bytes of data between a source and destination register.
/// ISAR incremented
/// No status bits are modified.
/// </summary>
private void LR_ISAR_A_INC()
{
PopulateCURINSTR(
@ -1127,6 +1171,12 @@
END);
}
/// <summary>
/// LR - LOAD REGISTER
/// The LR group of instructions move one or two bytes of data between a source and destination register.
/// ISAR decremented
/// No status bits are modified.
/// </summary>
private void LR_ISAR_A_DEC()
{
PopulateCURINSTR(
@ -1187,7 +1237,7 @@
}
/// <summary>
/// Branch on True - Do not branch
/// Branch on True - DO NOT BRANCH
/// </summary>
private void BTN()
{
@ -1290,19 +1340,6 @@
OP_BT_ZCS);
}
/*
private void BT(byte index)
{
PopulateCURINSTR(
// S
ROMC_1C_S, // Idle
IDLE,
IDLE,
OP_BT, index); // no END as there is branching logic within OP_BT
}
*/
/// <summary>
/// AM - ADD (BINARY) MEMORY TO ACCUMULATOR
/// The content of the memory iocation addressed by the DC0 registers is added to the accumulator. The sum is returned in the accumulator.
@ -1473,14 +1510,6 @@
END);
}
/*
private void BR7()
{
PopulateCURINSTR(
OP_BR7); // no END as there is branching logic within OP_BR7
}
*/
/// <summary>
/// Branch if any of the 3 low bits of ISAR are reset
/// Testing of ISAR is immediate so we will have to lose a CPU tick in the next phase
@ -1488,7 +1517,7 @@
private void BR7()
{
PopulateCURINSTR(
OP_BR7); // no END as there is branching logic within OP_BR7
OP_BR7);
}
/// <summary>
@ -1698,19 +1727,7 @@
IDLE,
OP_BF_OZCS);
}
/*
private void BF(byte index)
{
PopulateCURINSTR(
// S
ROMC_1C_S, // Idle
IDLE,
IDLE,
OP_BF, index); // no END as there is branching logic within OP_BF
}
*/
/// <summary>
/// INS - INPUT SHORT ADDRESS
/// Data input to the I/O port specified by the operand of the INS instruction is loaded into the accumulator.

47
src/BizHawk.Emulation.Cores/CPUs/FairchildF8/F3850.cs
View File

@ -118,27 +118,14 @@ namespace BizHawk.Emulation.Cores.Components.FairchildF8
public const byte OP_BT_ZS = 141;
public const byte OP_BT_ZC = 142;
public const byte OP_BT_ZCS = 143;
public const byte OP_BF = 141;
//public const byte OP_BF = 141;
public const byte OP_IN = 151;
public const byte OP_OUT = 152;
//public const byte OP_AS_IS = 123;
//public const byte OP_XS_IS = 124;
//public const byte OP_NS_IS = 125;
public const byte OP_LR_A_DB_IO = 156;
public const byte OP_DS = 157;
//public const byte OP_CLEAR_FLAGS = 126;
//public const byte OP_SET_FLAGS_SZ = 127;
public const byte OP_LIS = 158;
public F3850()
{
Reset();
@ -290,7 +277,6 @@ namespace BizHawk.Emulation.Cores.Components.FairchildF8
//Regs[A] = (byte)(Regs[A] ^ 0xFF);
break;
// x <- (x) + 1
case OP_INC8:
ADD_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
@ -564,21 +550,6 @@ namespace BizHawk.Emulation.Cores.Components.FairchildF8
case ROMC_01:
Read_Func(DB, PC0l, PC0h);
RegPC0 = Regs[DB].Bit(7) ? (ushort)(RegPC0 - (byte)((Regs[DB] ^ 0xFF) + 1)) : (ushort)(RegPC0 + Regs[DB]);
/*
if (Regs[DB].Bit(7))
{
// sign bit set
var cN = (byte)((Regs[DB] ^ 0xFF) + 1);
// subtract
RegPC0 -= cN;
}
else
{
// positive signed number
RegPC0 += Regs[DB];
}
//RegPC0 += (ushort)((sbyte) Regs[DB]);
*/
break;
// The device whose DC0 address addresses a memory word within the address space of that device must place on the data bus the contents
@ -651,22 +622,6 @@ namespace BizHawk.Emulation.Cores.Components.FairchildF8
case ROMC_0A:
// The contents of the accumulator are treated as a signed binary number, and are added to the contents of every DCO register.
RegDC0 = Regs[DB].Bit(7) ? (ushort)(RegDC0 - (byte)((Regs[DB] ^ 0xFF) + 1)) : (ushort)(RegDC0 + Regs[DB]);
/*
if (Regs[DB].Bit(7))
{
// sign bit set
var cN = (byte)((Regs[DB] ^ 0xFF) + 1);
// subtract
RegDC0 -= cN;
}
else
{
// positive signed number
RegDC0 += Regs[DB];
}
*/
//RegDC0 += (ushort) ((sbyte) Regs[DB]);
break;
// The device whose address space includes the value in PC1 must place the low order byte of PC1 on the data bus