Add files via upload

This commit is contained in:
alyosha-tas 2017-10-13 17:50:54 -04:00 committed by GitHub
parent 3be21c583e
commit ce6dcab323
6 changed files with 111 additions and 95 deletions

View File

@ -38,7 +38,7 @@ namespace BizHawk.Emulation.Cores.ColecoVision
public byte Read(IController c, bool left_mode, int wheel)
{
return 0; // needs checking
return 0x7F; // needs checking
}
public ControllerDefinition Definition { get; }

View File

@ -12,36 +12,36 @@ namespace BizHawk.Emulation.Cores.ColecoVision
{
return new Dictionary<string, RegisterValue>
{
["A"] = _cpu.RegisterA,
["AF"] = _cpu.RegisterAF,
["B"] = _cpu.RegisterB,
["BC"] = _cpu.RegisterBC,
["C"] = _cpu.RegisterC,
["D"] = _cpu.RegisterD,
["DE"] = _cpu.RegisterDE,
["E"] = _cpu.RegisterE,
["F"] = _cpu.RegisterF,
["H"] = _cpu.RegisterH,
["HL"] = _cpu.RegisterHL,
["I"] = _cpu.RegisterI,
["IX"] = _cpu.RegisterIX,
["IY"] = _cpu.RegisterIY,
["L"] = _cpu.RegisterL,
["PC"] = _cpu.RegisterPC,
["R"] = _cpu.RegisterR,
["Shadow AF"] = _cpu.RegisterShadowAF,
["Shadow BC"] = _cpu.RegisterShadowBC,
["Shadow DE"] = _cpu.RegisterShadowDE,
["Shadow HL"] = _cpu.RegisterShadowHL,
["SP"] = _cpu.RegisterSP,
["Flag C"] = _cpu.RegisterF.Bit(0),
["Flag N"] = _cpu.RegisterF.Bit(1),
["Flag P/V"] = _cpu.RegisterF.Bit(2),
["Flag 3rd"] = _cpu.RegisterF.Bit(3),
["Flag H"] = _cpu.RegisterF.Bit(4),
["Flag 5th"] = _cpu.RegisterF.Bit(5),
["Flag Z"] = _cpu.RegisterF.Bit(6),
["Flag S"] = _cpu.RegisterF.Bit(7)
["A"] = _cpu.Regs[_cpu.A],
["AF"] = _cpu.Regs[_cpu.F] + (_cpu.Regs[_cpu.A] << 8),
["B"] = _cpu.Regs[_cpu.B],
["BC"] = _cpu.Regs[_cpu.C] + (_cpu.Regs[_cpu.B] << 8),
["C"] = _cpu.Regs[_cpu.C],
["D"] = _cpu.Regs[_cpu.D],
["DE"] = _cpu.Regs[_cpu.E] + (_cpu.Regs[_cpu.D] << 8),
["E"] = _cpu.Regs[_cpu.E],
["F"] = _cpu.Regs[_cpu.F],
["H"] = _cpu.Regs[_cpu.H],
["HL"] = _cpu.Regs[_cpu.L] + (_cpu.Regs[_cpu.H] << 8),
["I"] = _cpu.Regs[_cpu.I],
["IX"] = _cpu.Regs[_cpu.Ixl] + (_cpu.Regs[_cpu.Ixh] << 8),
["IY"] = _cpu.Regs[_cpu.Iyl] + (_cpu.Regs[_cpu.Iyh] << 8),
["L"] = _cpu.Regs[_cpu.L],
["PC"] = _cpu.Regs[_cpu.PCl] + (_cpu.Regs[_cpu.PCh] << 8),
["R"] = _cpu.Regs[_cpu.R],
["Shadow AF"] = _cpu.Regs[_cpu.F_s] + (_cpu.Regs[_cpu.A_s] << 8),
["Shadow BC"] = _cpu.Regs[_cpu.C_s] + (_cpu.Regs[_cpu.B_s] << 8),
["Shadow DE"] = _cpu.Regs[_cpu.E_s] + (_cpu.Regs[_cpu.D_s] << 8),
["Shadow HL"] = _cpu.Regs[_cpu.L_s] + (_cpu.Regs[_cpu.H_s] << 8),
["SP"] = _cpu.Regs[_cpu.Iyl] + (_cpu.Regs[_cpu.Iyh] << 8),
["Flag C"] = _cpu.FlagC,
["Flag N"] = _cpu.FlagN,
["Flag P/V"] = _cpu.FlagP,
["Flag 3rd"] = _cpu.Flag3,
["Flag H"] = _cpu.FlagH,
["Flag 5th"] = _cpu.Flag5,
["Flag Z"] = _cpu.FlagZ,
["Flag S"] = _cpu.FlagS
};
}
@ -52,70 +52,82 @@ namespace BizHawk.Emulation.Cores.ColecoVision
default:
throw new InvalidOperationException();
case "A":
_cpu.RegisterA = (byte)value;
_cpu.Regs[_cpu.A] = (ushort)value;
break;
case "AF":
_cpu.RegisterAF = (byte)value;
_cpu.Regs[_cpu.F] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.A] = (ushort)(value & 0xFF00);
break;
case "B":
_cpu.RegisterB = (byte)value;
_cpu.Regs[_cpu.B] = (ushort)value;
break;
case "BC":
_cpu.RegisterBC = (byte)value;
_cpu.Regs[_cpu.C] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.B] = (ushort)(value & 0xFF00);
break;
case "C":
_cpu.RegisterC = (byte)value;
_cpu.Regs[_cpu.C] = (ushort)value;
break;
case "D":
_cpu.RegisterD = (byte)value;
_cpu.Regs[_cpu.D] = (ushort)value;
break;
case "DE":
_cpu.RegisterDE = (byte)value;
_cpu.Regs[_cpu.E] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.D] = (ushort)(value & 0xFF00);
break;
case "E":
_cpu.RegisterE = (byte)value;
_cpu.Regs[_cpu.E] = (ushort)value;
break;
case "F":
_cpu.RegisterF = (byte)value;
_cpu.Regs[_cpu.F] = (ushort)value;
break;
case "H":
_cpu.RegisterH = (byte)value;
_cpu.Regs[_cpu.H] = (ushort)value;
break;
case "HL":
_cpu.RegisterHL = (byte)value;
_cpu.Regs[_cpu.L] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.H] = (ushort)(value & 0xFF00);
break;
case "I":
_cpu.RegisterI = (byte)value;
_cpu.Regs[_cpu.I] = (ushort)value;
break;
case "IX":
_cpu.RegisterIX = (byte)value;
_cpu.Regs[_cpu.Ixl] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.Ixh] = (ushort)(value & 0xFF00);
break;
case "IY":
_cpu.RegisterIY = (byte)value;
_cpu.Regs[_cpu.Iyl] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.Iyh] = (ushort)(value & 0xFF00);
break;
case "L":
_cpu.RegisterL = (byte)value;
_cpu.Regs[_cpu.L] = (ushort)value;
break;
case "PC":
_cpu.RegisterPC = (ushort)value;
_cpu.Regs[_cpu.PCl] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.PCh] = (ushort)(value & 0xFF00);
break;
case "R":
_cpu.RegisterR = (byte)value;
_cpu.Regs[_cpu.R] = (ushort)value;
break;
case "Shadow AF":
_cpu.RegisterShadowAF = (byte)value;
_cpu.Regs[_cpu.F_s] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.A_s] = (ushort)(value & 0xFF00);
break;
case "Shadow BC":
_cpu.RegisterShadowBC = (byte)value;
_cpu.Regs[_cpu.C_s] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.B_s] = (ushort)(value & 0xFF00);
break;
case "Shadow DE":
_cpu.RegisterShadowDE = (byte)value;
_cpu.Regs[_cpu.E_s] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.D_s] = (ushort)(value & 0xFF00);
break;
case "Shadow HL":
_cpu.RegisterShadowHL = (byte)value;
_cpu.Regs[_cpu.L_s] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.H_s] = (ushort)(value & 0xFF00);
break;
case "SP":
_cpu.RegisterSP = (byte)value;
_cpu.Regs[_cpu.SPl] = (ushort)(value & 0xFF);
_cpu.Regs[_cpu.SPh] = (ushort)(value & 0xFF00);
break;
}
}

View File

@ -24,16 +24,18 @@ namespace BizHawk.Emulation.Cores.ColecoVision
SoftReset();
}
_cpu.Debug = _tracer.Enabled;
_frame++;
_isLag = true;
PSG.BeginFrame(_cpu.TotalExecutedCycles);
if (_cpu.Debug && _cpu.Logger == null) // TODO, lets not do this on each frame. But lets refactor CoreComm/CoreComm first
if (_tracer.Enabled)
{
_cpu.Logger = (s) => _tracer.Put(s);
_cpu.TraceCallback = s => _tracer.Put(s);
}
else
{
_cpu.TraceCallback = null;
}
byte tempRet1 = ControllerDeck.ReadPort1(controller, true, true);
byte tempRet2 = ControllerDeck.ReadPort2(controller, true, true);

View File

@ -7,53 +7,52 @@ namespace BizHawk.Emulation.Cores.ColecoVision
{
public partial class ColecoVision : IStatable
{
public bool BinarySaveStatesPreferred => false;
public bool BinarySaveStatesPreferred
{
get { return true; }
}
public void SaveStateText(TextWriter writer)
{
SyncState(new Serializer(writer));
}
public void LoadStateText(TextReader reader)
{
SyncState(new Serializer(reader));
}
public void SaveStateBinary(BinaryWriter bw)
{
SyncState(Serializer.CreateBinaryWriter(bw));
SyncState(new Serializer(bw));
}
public void LoadStateBinary(BinaryReader br)
{
SyncState(Serializer.CreateBinaryReader(br));
}
public void SaveStateText(TextWriter tw)
{
SyncState(Serializer.CreateTextWriter(tw));
}
public void LoadStateText(TextReader tr)
{
SyncState(Serializer.CreateTextReader(tr));
SyncState(new Serializer(br));
}
public byte[] SaveStateBinary()
{
if (_stateBuffer == null)
{
var stream = new MemoryStream();
var writer = new BinaryWriter(stream);
SaveStateBinary(writer);
_stateBuffer = stream.ToArray();
writer.Close();
return _stateBuffer;
}
else
{
var stream = new MemoryStream(_stateBuffer);
var writer = new BinaryWriter(stream);
SaveStateBinary(writer);
writer.Close();
return _stateBuffer;
}
MemoryStream ms = new MemoryStream();
BinaryWriter bw = new BinaryWriter(ms);
SaveStateBinary(bw);
bw.Flush();
return ms.ToArray();
}
private void SyncState(Serializer ser)
{
ser.BeginSection("Coleco");
byte[] core = null;
if (ser.IsWriter)
{
var ms = new MemoryStream();
ms.Close();
core = ms.ToArray();
}
_cpu.SyncState(ser);
ser.BeginSection("Coleco");
_vdp.SyncState(ser);
PSG.SyncState(ser);
ser.Sync("RAM", ref _ram, false);

View File

@ -1,6 +1,6 @@
using BizHawk.Emulation.Common;
using BizHawk.Emulation.Cores.Components;
using BizHawk.Emulation.Cores.Components.Z80;
using BizHawk.Emulation.Common.Components.Z80A;
namespace BizHawk.Emulation.Cores.ColecoVision
{
@ -53,7 +53,7 @@ namespace BizHawk.Emulation.Cores.ColecoVision
SetupMemoryDomains();
_tracer.Header = _cpu.TraceHeader;
ser.Register<IDisassemblable>(new Disassembler());
ser.Register<IDisassemblable>(_cpu);
ser.Register<ITraceable>(_tracer);
}

View File

@ -2,7 +2,7 @@
using BizHawk.Common;
using BizHawk.Emulation.Common;
using BizHawk.Emulation.Cores.Components.Z80;
using BizHawk.Emulation.Common.Components.Z80A;
namespace BizHawk.Emulation.Cores.ColecoVision
{
@ -54,14 +54,17 @@ namespace BizHawk.Emulation.Cores.ColecoVision
Cpu.NonMaskableInterrupt = true;
}
Cpu.ExecuteCycles(228);
Cpu.Interrupt = false;
for (int i = 0; i < 228; i++)
{
Cpu.ExecuteOne();
}
Cpu.FlagI = false;
if (Int_pending && scanLine==50)
{
if (EnableInterrupts)
{
Cpu.Interrupt = true;
Cpu.FlagI = true;
Int_pending = false;
}
}